diff --git a/chili-chips-ba_openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/4.dac/3.build/luttable_lut_module/3.sw/systemverilog/sinewave_code_generator.py b/chili-chips-ba_openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/4.dac/3.build/luttable_lut_module/3.sw/systemverilog/sinewave_code_generator.py new file mode 100644 index 0000000000000000000000000000000000000000..18ba49ed1388e902c1755273bcb595ec6a392650 --- /dev/null +++ b/chili-chips-ba_openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/4.dac/3.build/luttable_lut_module/3.sw/systemverilog/sinewave_code_generator.py @@ -0,0 +1,120 @@ +import argparse +import numpy as np +import math + +def generate_unsigned_table(lut_depth, data_width): + table_entries = 1 << lut_depth + max_value = (1 << data_width) - 1 + + sine_data = np.zeros(table_entries, dtype=np.int64) + + for k in range(table_entries): + phase = 2.0 * math.pi * k / table_entries + # Offset sine wave to start from mid-range (unsigned) + sine_data[k] = int((max_value / 2) * (1 + math.sin(phase))) + + return sine_data + +def generate_verilog_lut_module(lut_depth, data_width, filename): + sine_data = generate_unsigned_table(lut_depth, data_width) + table_entries = len(sine_data) + + verilog_code = f""" +module sinewave_table #( + parameter LUT_DEPTH = {lut_depth}, + parameter DATA_WIDTH = {data_width} +)( + input logic [LUT_DEPTH-1 :0] address, // {lut_depth}-bit address signal for {table_entries} values + output logic [DATA_WIDTH-1:0] value // {data_width}-bit output signal +); + + always @(*) begin + unique case (address) +""" + for i, value in enumerate(sine_data): + verilog_code += f" {lut_depth}'d{i}: value = {data_width}'h{value:X};\n" + + verilog_code += f""" default: value = {data_width}'h0; + endcase + end + +endmodule +""" + with open(filename, "w") as f: + f.write(verilog_code) + + return verilog_code + +def generate_verilog_sinewave_generator(lut_depth, data_width, phase_width, filename): + verilog_code = f""" +module sinewave_generator #( + parameter DATA_WIDTH = {data_width}, + LUT_DEPTH = {lut_depth}, + PHASE_WIDTH = {phase_width} +) ( + input logic clk, + input logic arst, + input logic sample_clk_ce, + input logic signed [PHASE_WIDTH-1:0] phase_increment, + output logic [DATA_WIDTH -1:0] sinewave, + output logic [DATA_WIDTH -1:0] cosinewave +); + + logic [PHASE_WIDTH-1:0] phase_accumulator; + + sinewave_table #( + .DATA_WIDTH(DATA_WIDTH), + .LUT_DEPTH(LUT_DEPTH) + ) sinewave_inst ( + .address(phase_accumulator[PHASE_WIDTH-1:PHASE_WIDTH-LUT_DEPTH]), + .value(sinewave) + ); + + sinewave_table #( + .DATA_WIDTH(DATA_WIDTH), + .LUT_DEPTH(LUT_DEPTH) + ) cosinewave_inst ( + .address((phase_accumulator[PHASE_WIDTH-1:PHASE_WIDTH-LUT_DEPTH] + (1<<(LUT_DEPTH-2))) % (1< WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN' + +This is a triple exciting port of @gtaylormb [project](https://github.com/gtaylormb/opl3_fpga) to _Yosys_ and _GateMate_ FPGA. + - **Excitment#1**: Original design is super cool on its own, as it is about the heart of the uber-popular _SoundblasterPro_ audio card from the turbulent '90s. + - **Excitment#2**: RTL is written in, for opensource, unusally rich complement of _SystemVerilog_. The original project had vetted this RTL only with Xilinx-proprietary Vivado. These two circumstances make this codebase a formidable [challenge](https://github.com/chili-chips-ba/openCologne/issues/3) for opensource [Yosys](https://github.com/YosysHQ/yosys) synthesis. And yes, with every challenge comes an opportunity :blush:. + - **Excitment#3**: As of yet, there are no GateMate designs of this complexity. We are therefore buckled up for a fun, bumpy rollercoaster ride. + +Regarding excitment/challenge#2, having tried [Synlig plugin](https://github.com/chipsalliance/synlig) and [Yosys-Slang](https://github.com/povik/yosys-slang), we ended up converging on @zachjs's [SV2V](https://github.com/zachjs/sv2v). This can also be viewed as an independant validation and confirmation of @pu-cc's advice on the opensource flow that works best for _SystemVerilog_. + +To get started, first install SV2V and other tools, as explained in [0.doc](https://github.com/chili-chips-ba/openCologne/blob/main/0.doc/1.README.Tool-Installs.txt). Then: +``` +% cd 3.build +% make synth +``` + +This OPL3 design produces 100% digital audio in I2S format. To hear anything, it needs to be complemented with an external compatible audio CODEC, such as: +> - https://github.com/goran-mahovlic/ulx3s-extensions +> - https://www.waveshare.com/wm8960-audio-board.htm + +For fun, also see OPL3 software emulators. Beware, they are not as good and not as precise as this pure hardware, re-engineered Yamaha chip. +> - https://github.com/Wohlstand/libADLMIDI +> - https://github.com/nukeykt/Nuked-OPL3 + + +#### End of Document diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/debounce.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/debounce.v new file mode 100644 index 0000000000000000000000000000000000000000..3706c9562f51713859016ecfca001b64164b3ff1 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/debounce.v @@ -0,0 +1,53 @@ +//fpga4student.com: FPGA projects, Verilog projects, VHDL projects +// Verilog code for button debouncing on FPGA +// debouncing module without creating another clock domain +// by using clock enable signal +module debounce( + input clk, + input in, + output out +); + + wire slow_clk_en; + wire Q1,Q2,Q2_bar,Q0; + + clock_enable u1(clk,slow_clk_en); + my_dff_en d0(clk,slow_clk_en,in,Q0); + my_dff_en d1(clk,slow_clk_en,Q0,Q1); + my_dff_en d2(clk,slow_clk_en,Q1,Q2); + + assign Q2_bar = ~Q2; + assign out = Q1 & Q2_bar; +endmodule + +// Slow clock enable for debouncing button +module clock_enable( + input Clk_100M, + output slow_clk_en +); + reg [26:0]counter=0; + + always @(posedge Clk_100M) + begin + counter <= (counter>=24999) ? 0 : counter + 1; + end + + assign slow_clk_en = (counter == 24999) ? 1'b1 : 1'b0; +endmodule + +// D-flip-flop with clock enable signal for debouncing module +module my_dff_en( + input DFF_CLOCK, + input clock_enable, + input D, + output reg Q=0 +); + + always @ (posedge DFF_CLOCK) + begin + if(clock_enable==1) + Q <= D; + end + +endmodule + diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/gatemate_25MHz_pll.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/gatemate_25MHz_pll.v new file mode 100644 index 0000000000000000000000000000000000000000..f0ac0d4ee055f5ce78e0d7b30b439e0f15b257a5 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/gatemate_25MHz_pll.v @@ -0,0 +1,47 @@ +/* + * gatemate_25MHz_pll.v + * + * Copyright (C) 2022-2024 Gwenhael Goavec-Merou + * SPDX-License-Identifier: MIT + */ +module pll ( + input wire clock_in, + input wire rst_in, + output wire clock_out, + output reg locked +); + +wire clk270, clk180, clk90, clk0, usr_ref_out; +wire usr_pll_lock; + +wire pll_clk_nobuf; +CC_PLL #( + .REF_CLK("10.0"), // reference input in MHz + .OUT_CLK("25.0"), // pll output frequency in MHz + .LOCK_REQ(0), // 1: Lock status required before PLL output enable + // 0: PLL output before lock + .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED + .LOW_JITTER(1), // 0: disable, 1: enable low jitter mode + .CI_FILTER_CONST(2), // optional CI filter constant + .CP_FILTER_CONST(4) // optional CP filter constant +) pll25 ( + .CLK_REF(clock_in), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0), + /* USR_LOCKED_STDY_RST and USR_PLL_LOCKED_STDY are more or less + * for debug purpose. USR_PLL_LOCKED_STDY is high after first lock + * goes low if PLL unlock and stay low until USR_LOCKED_STDY_RST is + * set during 2 clock cycles + */ + .USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(), + .USR_PLL_LOCKED(usr_pll_lock), + .CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(pll_clk_nobuf), .CLK_REF_OUT(usr_ref_out) +); +CC_BUFG pll_bufg (.I(pll_clk_nobuf), .O(clock_out)); + +// reset is synced the clock +reg locked_s1; +always @(posedge clock_out) begin + locked_s1 <= usr_pll_lock & ~rst_in; + locked <= locked_s1; +end + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picorv32.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picorv32.v new file mode 100644 index 0000000000000000000000000000000000000000..c08e7253fc2b0d189bfd7b28be3aab288d51b97e --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picorv32.v @@ -0,0 +1,2977 @@ +/* + * PicoRV32 -- A Small RISC-V (RV32I) Processor Core + * + * Copyright (C) 2015 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`timescale 1 ns / 1 ps +// `default_nettype none +// `define DEBUGNETS +// `define DEBUGREGS +// `define DEBUGASM +// `define DEBUG + +`ifdef DEBUG + `define debug(debug_command) debug_command +`else + `define debug(debug_command) +`endif + +`ifdef FORMAL + `define FORMAL_KEEP (* keep *) + `define assert(assert_expr) assert(assert_expr) +`else + `ifdef DEBUGNETS + `define FORMAL_KEEP (* keep *) + `else + `define FORMAL_KEEP + `endif + `define assert(assert_expr) empty_statement +`endif + +// uncomment this for register file in extra module +// `define PICORV32_REGS picorv32_regs + +// this macro can be used to check if the verilog files in your +// design are read in the correct order. +`define PICORV32_V + + +/*************************************************************** + * picorv32 + ***************************************************************/ + +module picorv32 #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] LATCHED_MEM_RDATA = 0, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0010_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output reg trap, + + output reg mem_valid, + output reg mem_instr, + input mem_ready, + + output reg [31:0] mem_addr, + output reg [31:0] mem_wdata, + output reg [ 3:0] mem_wstrb, + input [31:0] mem_rdata, + + // Look-Ahead Interface + output mem_la_read, + output mem_la_write, + output [31:0] mem_la_addr, + output reg [31:0] mem_la_wdata, + output reg [ 3:0] mem_la_wstrb, + + // Pico Co-Processor Interface (PCPI) + output reg pcpi_valid, + output reg [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ Interface + input [31:0] irq, + output reg [31:0] eoi, + +`ifdef RISCV_FORMAL + output reg rvfi_valid, + output reg [63:0] rvfi_order, + output reg [31:0] rvfi_insn, + output reg rvfi_trap, + output reg rvfi_halt, + output reg rvfi_intr, + output reg [ 4:0] rvfi_rs1_addr, + output reg [ 4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [ 4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [ 3:0] rvfi_mem_rmask, + output reg [ 3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output reg trace_valid, + output reg [35:0] trace_data +); + localparam integer irq_timer = 0; + localparam integer irq_ebreak = 1; + localparam integer irq_buserror = 2; + + localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; + localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS; + localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS; + + localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV; + + localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; + localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0}; + localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0}; + + reg [63:0] count_cycle, count_instr; + reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out; + reg [4:0] reg_sh; + + reg [31:0] next_insn_opcode; + reg [31:0] dbg_insn_opcode; + reg [31:0] dbg_insn_addr; + + wire dbg_mem_valid = mem_valid; + wire dbg_mem_instr = mem_instr; + wire dbg_mem_ready = mem_ready; + wire [31:0] dbg_mem_addr = mem_addr; + wire [31:0] dbg_mem_wdata = mem_wdata; + wire [ 3:0] dbg_mem_wstrb = mem_wstrb; + wire [31:0] dbg_mem_rdata = mem_rdata; + + assign pcpi_rs1 = reg_op1; + assign pcpi_rs2 = reg_op2; + + wire [31:0] next_pc; + + reg irq_delay; + reg irq_active; + reg [31:0] irq_mask; + reg [31:0] irq_pending; + reg [31:0] timer; + +`ifndef PICORV32_REGS + reg [31:0] cpuregs [0:regfile_size-1]; + + integer i; + initial begin + if (REGS_INIT_ZERO) begin + for (i = 0; i < regfile_size; i = i+1) + cpuregs[i] = 0; + end + end +`endif + + task empty_statement; + // This task is used by the `assert directive in non-formal mode to + // avoid empty statement (which are unsupported by plain Verilog syntax). + begin end + endtask + +`ifdef DEBUGREGS + wire [31:0] dbg_reg_x0 = 0; + wire [31:0] dbg_reg_x1 = cpuregs[1]; + wire [31:0] dbg_reg_x2 = cpuregs[2]; + wire [31:0] dbg_reg_x3 = cpuregs[3]; + wire [31:0] dbg_reg_x4 = cpuregs[4]; + wire [31:0] dbg_reg_x5 = cpuregs[5]; + wire [31:0] dbg_reg_x6 = cpuregs[6]; + wire [31:0] dbg_reg_x7 = cpuregs[7]; + wire [31:0] dbg_reg_x8 = cpuregs[8]; + wire [31:0] dbg_reg_x9 = cpuregs[9]; + wire [31:0] dbg_reg_x10 = cpuregs[10]; + wire [31:0] dbg_reg_x11 = cpuregs[11]; + wire [31:0] dbg_reg_x12 = cpuregs[12]; + wire [31:0] dbg_reg_x13 = cpuregs[13]; + wire [31:0] dbg_reg_x14 = cpuregs[14]; + wire [31:0] dbg_reg_x15 = cpuregs[15]; + wire [31:0] dbg_reg_x16 = cpuregs[16]; + wire [31:0] dbg_reg_x17 = cpuregs[17]; + wire [31:0] dbg_reg_x18 = cpuregs[18]; + wire [31:0] dbg_reg_x19 = cpuregs[19]; + wire [31:0] dbg_reg_x20 = cpuregs[20]; + wire [31:0] dbg_reg_x21 = cpuregs[21]; + wire [31:0] dbg_reg_x22 = cpuregs[22]; + wire [31:0] dbg_reg_x23 = cpuregs[23]; + wire [31:0] dbg_reg_x24 = cpuregs[24]; + wire [31:0] dbg_reg_x25 = cpuregs[25]; + wire [31:0] dbg_reg_x26 = cpuregs[26]; + wire [31:0] dbg_reg_x27 = cpuregs[27]; + wire [31:0] dbg_reg_x28 = cpuregs[28]; + wire [31:0] dbg_reg_x29 = cpuregs[29]; + wire [31:0] dbg_reg_x30 = cpuregs[30]; + wire [31:0] dbg_reg_x31 = cpuregs[31]; +`endif + + // Internal PCPI Cores + + wire pcpi_mul_wr; + wire [31:0] pcpi_mul_rd; + wire pcpi_mul_wait; + wire pcpi_mul_ready; + + wire pcpi_div_wr; + wire [31:0] pcpi_div_rd; + wire pcpi_div_wait; + wire pcpi_div_ready; + + reg pcpi_int_wr; + reg [31:0] pcpi_int_rd; + reg pcpi_int_wait; + reg pcpi_int_ready; + + generate if (ENABLE_FAST_MUL) begin + picorv32_pcpi_fast_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else if (ENABLE_MUL) begin + picorv32_pcpi_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else begin + assign pcpi_mul_wr = 0; + assign pcpi_mul_rd = 32'bx; + assign pcpi_mul_wait = 0; + assign pcpi_mul_ready = 0; + end endgenerate + + generate if (ENABLE_DIV) begin + picorv32_pcpi_div pcpi_div ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_div_wr ), + .pcpi_rd (pcpi_div_rd ), + .pcpi_wait (pcpi_div_wait ), + .pcpi_ready(pcpi_div_ready ) + ); + end else begin + assign pcpi_div_wr = 0; + assign pcpi_div_rd = 32'bx; + assign pcpi_div_wait = 0; + assign pcpi_div_ready = 0; + end endgenerate + + always @* begin + pcpi_int_wr = 0; + pcpi_int_rd = 32'bx; + pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait}; + pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready}; + + (* parallel_case *) + case (1'b1) + ENABLE_PCPI && pcpi_ready: begin + pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0; + pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0; + end + (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin + pcpi_int_wr = pcpi_mul_wr; + pcpi_int_rd = pcpi_mul_rd; + end + ENABLE_DIV && pcpi_div_ready: begin + pcpi_int_wr = pcpi_div_wr; + pcpi_int_rd = pcpi_div_rd; + end + endcase + end + + + // Memory Interface + + reg [1:0] mem_state; + reg [1:0] mem_wordsize; + reg [31:0] mem_rdata_word; + reg [31:0] mem_rdata_q; + reg mem_do_prefetch; + reg mem_do_rinst; + reg mem_do_rdata; + reg mem_do_wdata; + + wire mem_xfer; + reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid; + wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword; + wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg); + + reg prefetched_high_word; + reg clear_prefetched_high_word; + reg [15:0] mem_16bit_buffer; + + wire [31:0] mem_rdata_latched_noshuffle; + wire [31:0] mem_rdata_latched; + + wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word; + assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst); + + wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata}; + wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) && + (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer)); + + assign mem_la_write = resetn && !mem_state && mem_do_wdata; + assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) || + (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0])); + assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00}; + + assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q; + + assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle; + + always @(posedge clk) begin + if (!resetn) begin + mem_la_firstword_reg <= 0; + last_mem_valid <= 0; + end else begin + if (!last_mem_valid) + mem_la_firstword_reg <= mem_la_firstword; + last_mem_valid <= mem_valid && !mem_ready; + end + end + + always @* begin + (* full_case *) + case (mem_wordsize) + 0: begin + mem_la_wdata = reg_op2; + mem_la_wstrb = 4'b1111; + mem_rdata_word = mem_rdata; + end + 1: begin + mem_la_wdata = {2{reg_op2[15:0]}}; + mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011; + case (reg_op1[1]) + 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]}; + 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]}; + endcase + end + 2: begin + mem_la_wdata = {4{reg_op2[7:0]}}; + mem_la_wstrb = 4'b0001 << reg_op1[1:0]; + case (reg_op1[1:0]) + 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]}; + 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]}; + 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]}; + 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]}; + endcase + end + endcase + end + + always @(posedge clk) begin + if (mem_xfer) begin + mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + end + + if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00}; + end + 3'b010: begin // C.LW + mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b 110: begin // C.SW + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b 000: begin // C.ADDI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 010: begin // C.LI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 011: begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3], + mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000}); + end else begin // C.LUI + mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + end + 3'b100: begin + if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI + mem_rdata_q[31:25] <= 7'b0100000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000; + if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100; + if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110; + if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000; + end + end + 3'b 110: begin // C.BEQZ + mem_rdata_q[14:12] <= 3'b000; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + 3'b 111: begin // C.BNEZ + mem_rdata_q[14:12] <= 3'b001; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 001; + end + 3'b010: begin // C.LWSP + mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + end + 3'b110: begin // C.SWSP + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + endcase + end + end + + always @(posedge clk) begin + if (resetn && !trap) begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) + `assert(!mem_do_wdata); + + if (mem_do_prefetch || mem_do_rinst) + `assert(!mem_do_rdata); + + if (mem_do_rdata) + `assert(!mem_do_prefetch && !mem_do_rinst); + + if (mem_do_wdata) + `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata)); + + if (mem_state == 2 || mem_state == 3) + `assert(mem_valid || mem_do_prefetch); + end + end + + always @(posedge clk) begin + if (!resetn || trap) begin + if (!resetn) + mem_state <= 0; + if (!resetn || mem_ready) + mem_valid <= 0; + mem_la_secondword <= 0; + prefetched_high_word <= 0; + end else begin + if (mem_la_read || mem_la_write) begin + mem_addr <= mem_la_addr; + mem_wstrb <= mem_la_wstrb & {4{mem_la_write}}; + end + if (mem_la_write) begin + mem_wdata <= mem_la_wdata; + end + case (mem_state) + 0: begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin + mem_valid <= !mem_la_use_prefetched_high_word; + mem_instr <= mem_do_prefetch || mem_do_rinst; + mem_wstrb <= 0; + mem_state <= 1; + end + if (mem_do_wdata) begin + mem_valid <= 1; + mem_instr <= 0; + mem_state <= 2; + end + end + 1: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata); + `assert(mem_valid == !mem_la_use_prefetched_high_word); + `assert(mem_instr == (mem_do_prefetch || mem_do_rinst)); + if (mem_xfer) begin + if (COMPRESSED_ISA && mem_la_read) begin + mem_valid <= 1; + mem_la_secondword <= 1; + if (!mem_la_use_prefetched_high_word) + mem_16bit_buffer <= mem_rdata[31:16]; + end else begin + mem_valid <= 0; + mem_la_secondword <= 0; + if (COMPRESSED_ISA && !mem_do_rdata) begin + if (~&mem_rdata[1:0] || mem_la_secondword) begin + mem_16bit_buffer <= mem_rdata[31:16]; + prefetched_high_word <= 1; + end else begin + prefetched_high_word <= 0; + end + end + mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3; + end + end + end + 2: begin + `assert(mem_wstrb != 0); + `assert(mem_do_wdata); + if (mem_xfer) begin + mem_valid <= 0; + mem_state <= 0; + end + end + 3: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch); + if (mem_do_rinst) begin + mem_state <= 0; + end + end + endcase + end + + if (clear_prefetched_high_word) + prefetched_high_word <= 0; + end + + + // Instruction Decoder + + reg instr_lui, instr_auipc, instr_jal, instr_jalr; + reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu; + reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; + reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; + reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; + reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak; + reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; + wire instr_trap; + + reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2; + reg [31:0] decoded_imm, decoded_imm_uj; + reg decoder_trigger; + reg decoder_trigger_q; + reg decoder_pseudo_trigger; + reg decoder_pseudo_trigger_q; + reg compressed_instr; + + reg is_lui_auipc_jal; + reg is_lb_lh_lw_lbu_lhu; + reg is_slli_srli_srai; + reg is_jalr_addi_slti_sltiu_xori_ori_andi; + reg is_sb_sh_sw; + reg is_sll_srl_sra; + reg is_lui_auipc_jal_jalr_addi_add_sub; + reg is_slti_blt_slt; + reg is_sltiu_bltu_sltu; + reg is_beq_bne_blt_bge_bltu_bgeu; + reg is_lbu_lhu_lw; + reg is_alu_reg_imm; + reg is_alu_reg_reg; + reg is_compare; + + assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr, + instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu, + instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw, + instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai, + instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and, + instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, + instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer}; + + wire is_rdcycle_rdcycleh_rdinstr_rdinstrh; + assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}; + + reg [63:0] new_ascii_instr; + `FORMAL_KEEP reg [63:0] dbg_ascii_instr; + `FORMAL_KEEP reg [31:0] dbg_insn_imm; + `FORMAL_KEEP reg [4:0] dbg_insn_rs1; + `FORMAL_KEEP reg [4:0] dbg_insn_rs2; + `FORMAL_KEEP reg [4:0] dbg_insn_rd; + `FORMAL_KEEP reg [31:0] dbg_rs1val; + `FORMAL_KEEP reg [31:0] dbg_rs2val; + `FORMAL_KEEP reg dbg_rs1val_valid; + `FORMAL_KEEP reg dbg_rs2val_valid; + + always @* begin + new_ascii_instr = ""; + + if (instr_lui) new_ascii_instr = "lui"; + if (instr_auipc) new_ascii_instr = "auipc"; + if (instr_jal) new_ascii_instr = "jal"; + if (instr_jalr) new_ascii_instr = "jalr"; + + if (instr_beq) new_ascii_instr = "beq"; + if (instr_bne) new_ascii_instr = "bne"; + if (instr_blt) new_ascii_instr = "blt"; + if (instr_bge) new_ascii_instr = "bge"; + if (instr_bltu) new_ascii_instr = "bltu"; + if (instr_bgeu) new_ascii_instr = "bgeu"; + + if (instr_lb) new_ascii_instr = "lb"; + if (instr_lh) new_ascii_instr = "lh"; + if (instr_lw) new_ascii_instr = "lw"; + if (instr_lbu) new_ascii_instr = "lbu"; + if (instr_lhu) new_ascii_instr = "lhu"; + if (instr_sb) new_ascii_instr = "sb"; + if (instr_sh) new_ascii_instr = "sh"; + if (instr_sw) new_ascii_instr = "sw"; + + if (instr_addi) new_ascii_instr = "addi"; + if (instr_slti) new_ascii_instr = "slti"; + if (instr_sltiu) new_ascii_instr = "sltiu"; + if (instr_xori) new_ascii_instr = "xori"; + if (instr_ori) new_ascii_instr = "ori"; + if (instr_andi) new_ascii_instr = "andi"; + if (instr_slli) new_ascii_instr = "slli"; + if (instr_srli) new_ascii_instr = "srli"; + if (instr_srai) new_ascii_instr = "srai"; + + if (instr_add) new_ascii_instr = "add"; + if (instr_sub) new_ascii_instr = "sub"; + if (instr_sll) new_ascii_instr = "sll"; + if (instr_slt) new_ascii_instr = "slt"; + if (instr_sltu) new_ascii_instr = "sltu"; + if (instr_xor) new_ascii_instr = "xor"; + if (instr_srl) new_ascii_instr = "srl"; + if (instr_sra) new_ascii_instr = "sra"; + if (instr_or) new_ascii_instr = "or"; + if (instr_and) new_ascii_instr = "and"; + + if (instr_rdcycle) new_ascii_instr = "rdcycle"; + if (instr_rdcycleh) new_ascii_instr = "rdcycleh"; + if (instr_rdinstr) new_ascii_instr = "rdinstr"; + if (instr_rdinstrh) new_ascii_instr = "rdinstrh"; + + if (instr_getq) new_ascii_instr = "getq"; + if (instr_setq) new_ascii_instr = "setq"; + if (instr_retirq) new_ascii_instr = "retirq"; + if (instr_maskirq) new_ascii_instr = "maskirq"; + if (instr_waitirq) new_ascii_instr = "waitirq"; + if (instr_timer) new_ascii_instr = "timer"; + end + + reg [63:0] q_ascii_instr; + reg [31:0] q_insn_imm; + reg [31:0] q_insn_opcode; + reg [4:0] q_insn_rs1; + reg [4:0] q_insn_rs2; + reg [4:0] q_insn_rd; + reg dbg_next; + + wire launch_next_insn; + reg dbg_valid_insn; + + reg [63:0] cached_ascii_instr; + reg [31:0] cached_insn_imm; + reg [31:0] cached_insn_opcode; + reg [4:0] cached_insn_rs1; + reg [4:0] cached_insn_rs2; + reg [4:0] cached_insn_rd; + + always @(posedge clk) begin + q_ascii_instr <= dbg_ascii_instr; + q_insn_imm <= dbg_insn_imm; + q_insn_opcode <= dbg_insn_opcode; + q_insn_rs1 <= dbg_insn_rs1; + q_insn_rs2 <= dbg_insn_rs2; + q_insn_rd <= dbg_insn_rd; + dbg_next <= launch_next_insn; + + if (!resetn || trap) + dbg_valid_insn <= 0; + else if (launch_next_insn) + dbg_valid_insn <= 1; + + if (decoder_trigger_q) begin + cached_ascii_instr <= new_ascii_instr; + cached_insn_imm <= decoded_imm; + if (&next_insn_opcode[1:0]) + cached_insn_opcode <= next_insn_opcode; + else + cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]}; + cached_insn_rs1 <= decoded_rs1; + cached_insn_rs2 <= decoded_rs2; + cached_insn_rd <= decoded_rd; + end + + if (launch_next_insn) begin + dbg_insn_addr <= next_pc; + end + end + + always @* begin + dbg_ascii_instr = q_ascii_instr; + dbg_insn_imm = q_insn_imm; + dbg_insn_opcode = q_insn_opcode; + dbg_insn_rs1 = q_insn_rs1; + dbg_insn_rs2 = q_insn_rs2; + dbg_insn_rd = q_insn_rd; + + if (dbg_next) begin + if (decoder_pseudo_trigger_q) begin + dbg_ascii_instr = cached_ascii_instr; + dbg_insn_imm = cached_insn_imm; + dbg_insn_opcode = cached_insn_opcode; + dbg_insn_rs1 = cached_insn_rs1; + dbg_insn_rs2 = cached_insn_rs2; + dbg_insn_rd = cached_insn_rd; + end else begin + dbg_ascii_instr = new_ascii_instr; + if (&next_insn_opcode[1:0]) + dbg_insn_opcode = next_insn_opcode; + else + dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]}; + dbg_insn_imm = decoded_imm; + dbg_insn_rs1 = decoded_rs1; + dbg_insn_rs2 = decoded_rs2; + dbg_insn_rd = decoded_rd; + end + end + end + +`ifdef DEBUGASM + always @(posedge clk) begin + if (dbg_next) begin + $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*"); + end + end +`endif + +`ifdef DEBUG + always @(posedge clk) begin + if (dbg_next) begin + if (&dbg_insn_opcode[1:0]) + $display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + else + $display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + end + end +`endif + + always @(posedge clk) begin + is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal}; + is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub}; + is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt}; + is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu}; + is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw}; + is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu}; + + if (mem_do_rinst && mem_done) begin + instr_lui <= mem_rdata_latched[6:0] == 7'b0110111; + instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111; + instr_jal <= mem_rdata_latched[6:0] == 7'b1101111; + instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000; + instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ; + instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ; + + is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011; + is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011; + is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011; + is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011; + is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011; + + { decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0}); + + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[19:15]; + decoded_rs2 <= mem_rdata_latched[24:20]; + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS) + decoded_rs1[regindex_bits-1] <= 1; // instr_getq + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ) + decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq + + compressed_instr <= 0; + if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin + compressed_instr <= 1; + decoded_rd <= 0; + decoded_rs1 <= 0; + decoded_rs2 <= 0; + + { decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6], + decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0}); + + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + is_alu_reg_imm <= |mem_rdata_latched[12:5]; + decoded_rs1 <= 2; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b010: begin // C.LW + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b110: begin // C.SW + is_sb_sh_sw <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.NOP / C.ADDI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + 3'b001: begin // C.JAL + instr_jal <= 1; + decoded_rd <= 1; + end + 3'b 010: begin // C.LI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + 3'b 011: begin + if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end else begin // C.LUI + instr_lui <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + end + end + 3'b100: begin + if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + is_alu_reg_reg <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + end + 3'b101: begin // C.J + instr_jal <= 1; + end + 3'b110: begin // C.BEQZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + 3'b111: begin // C.BNEZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + if (!mem_rdata_latched[12]) begin + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + end + 3'b010: begin // C.LWSP + if (mem_rdata_latched[11:7]) begin + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 2; + end + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + instr_jalr <= 1; + decoded_rd <= 0; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + instr_jalr <= 1; + decoded_rd <= 1; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + end + 3'b110: begin // C.SWSP + is_sb_sh_sw <= 1; + decoded_rs1 <= 2; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + endcase + end + endcase + end + end + + if (decoder_trigger && !decoder_pseudo_trigger) begin + pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx; + + instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000; + instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001; + instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100; + instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101; + instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110; + instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111; + + instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000; + instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001; + instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010; + instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100; + instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101; + + instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000; + instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001; + instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010; + + instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000; + instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010; + instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011; + instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100; + instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110; + instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111; + + instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + + instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000; + instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000; + instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000; + instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000; + instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000; + instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000; + instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000; + + instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS; + instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; + instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + + instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || + (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002)); + + instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ; + instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER; + + is_slli_srli_srai <= is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b000, + mem_rdata_q[14:12] == 3'b010, + mem_rdata_q[14:12] == 3'b011, + mem_rdata_q[14:12] == 3'b100, + mem_rdata_q[14:12] == 3'b110, + mem_rdata_q[14:12] == 3'b111 + }; + + is_sll_srl_sra <= is_alu_reg_reg && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_lui_auipc_jal_jalr_addi_add_sub <= 0; + is_compare <= 0; + + (* parallel_case *) + case (1'b1) + instr_jal: + decoded_imm <= decoded_imm_uj; + |{instr_lui, instr_auipc}: + decoded_imm <= mem_rdata_q[31:12] << 12; + |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}: + decoded_imm <= $signed(mem_rdata_q[31:20]); + is_beq_bne_blt_bge_bltu_bgeu: + decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}); + is_sb_sh_sw: + decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]}); + default: + decoded_imm <= 1'bx; + endcase + end + + if (!resetn) begin + is_beq_bne_blt_bge_bltu_bgeu <= 0; + is_compare <= 0; + + instr_beq <= 0; + instr_bne <= 0; + instr_blt <= 0; + instr_bge <= 0; + instr_bltu <= 0; + instr_bgeu <= 0; + + instr_addi <= 0; + instr_slti <= 0; + instr_sltiu <= 0; + instr_xori <= 0; + instr_ori <= 0; + instr_andi <= 0; + + instr_add <= 0; + instr_sub <= 0; + instr_sll <= 0; + instr_slt <= 0; + instr_sltu <= 0; + instr_xor <= 0; + instr_srl <= 0; + instr_sra <= 0; + instr_or <= 0; + instr_and <= 0; + end + end + + + // Main State Machine + + localparam cpu_state_trap = 8'b10000000; + localparam cpu_state_fetch = 8'b01000000; + localparam cpu_state_ld_rs1 = 8'b00100000; + localparam cpu_state_ld_rs2 = 8'b00010000; + localparam cpu_state_exec = 8'b00001000; + localparam cpu_state_shift = 8'b00000100; + localparam cpu_state_stmem = 8'b00000010; + localparam cpu_state_ldmem = 8'b00000001; + + reg [7:0] cpu_state; + reg [1:0] irq_state; + + `FORMAL_KEEP reg [127:0] dbg_ascii_state; + + always @* begin + dbg_ascii_state = ""; + if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap"; + if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch"; + if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1"; + if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2"; + if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec"; + if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift"; + if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem"; + if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem"; + end + + reg set_mem_do_rinst; + reg set_mem_do_rdata; + reg set_mem_do_wdata; + + reg latched_store; + reg latched_stalu; + reg latched_branch; + reg latched_compr; + reg latched_trace; + reg latched_is_lu; + reg latched_is_lh; + reg latched_is_lb; + reg [regindex_bits-1:0] latched_rd; + + reg [31:0] current_pc; + assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc; + + reg [3:0] pcpi_timeout_counter; + reg pcpi_timeout; + + reg [31:0] next_irq_pending; + reg do_waitirq; + + reg [31:0] alu_out, alu_out_q; + reg alu_out_0, alu_out_0_q; + reg alu_wait, alu_wait_2; + + reg [31:0] alu_add_sub; + reg [31:0] alu_shl, alu_shr; + reg alu_eq, alu_ltu, alu_lts; + + generate if (TWO_CYCLE_ALU) begin + always @(posedge clk) begin + alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq <= reg_op1 == reg_op2; + alu_lts <= $signed(reg_op1) < $signed(reg_op2); + alu_ltu <= reg_op1 < reg_op2; + alu_shl <= reg_op1 << reg_op2[4:0]; + alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end else begin + always @* begin + alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq = reg_op1 == reg_op2; + alu_lts = $signed(reg_op1) < $signed(reg_op2); + alu_ltu = reg_op1 < reg_op2; + alu_shl = reg_op1 << reg_op2[4:0]; + alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end endgenerate + + always @* begin + alu_out_0 = 'bx; + (* parallel_case, full_case *) + case (1'b1) + instr_beq: + alu_out_0 = alu_eq; + instr_bne: + alu_out_0 = !alu_eq; + instr_bge: + alu_out_0 = !alu_lts; + instr_bgeu: + alu_out_0 = !alu_ltu; + is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_lts; + is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_ltu; + endcase + + alu_out = 'bx; + (* parallel_case, full_case *) + case (1'b1) + is_lui_auipc_jal_jalr_addi_add_sub: + alu_out = alu_add_sub; + is_compare: + alu_out = alu_out_0; + instr_xori || instr_xor: + alu_out = reg_op1 ^ reg_op2; + instr_ori || instr_or: + alu_out = reg_op1 | reg_op2; + instr_andi || instr_and: + alu_out = reg_op1 & reg_op2; + BARREL_SHIFTER && (instr_sll || instr_slli): + alu_out = alu_shl; + BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai): + alu_out = alu_shr; + endcase + +`ifdef RISCV_FORMAL_BLACKBOX_ALU + alu_out_0 = $anyseq; + alu_out = $anyseq; +`endif + end + + reg clear_prefetched_high_word_q; + always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word; + + always @* begin + clear_prefetched_high_word = clear_prefetched_high_word_q; + if (!prefetched_high_word) + clear_prefetched_high_word = 0; + if (latched_branch || irq_state || !resetn) + clear_prefetched_high_word = COMPRESSED_ISA; + end + + reg cpuregs_write; + reg [31:0] cpuregs_wrdata; + reg [31:0] cpuregs_rs1; + reg [31:0] cpuregs_rs2; + reg [regindex_bits-1:0] decoded_rs; + + always @* begin + cpuregs_write = 0; + cpuregs_wrdata = 'bx; + + if (cpu_state == cpu_state_fetch) begin + (* parallel_case *) + case (1'b1) + latched_branch: begin + cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4); + cpuregs_write = 1; + end + latched_store && !latched_branch: begin + cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[0]: begin + cpuregs_wrdata = reg_next_pc | latched_compr; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[1]: begin + cpuregs_wrdata = irq_pending & ~irq_mask; + cpuregs_write = 1; + end + endcase + end + end + +`ifndef PICORV32_REGS + always @(posedge clk) begin + if (resetn && cpuregs_write && latched_rd) + cpuregs[latched_rd] <= cpuregs_wrdata; + end + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; +`else + cpuregs_rs1 = decoded_rs1 ? $anyseq : 0; + cpuregs_rs2 = decoded_rs2 ? $anyseq : 0; +`endif + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0; +`else + cpuregs_rs1 = decoded_rs ? $anyseq : 0; +`endif + cpuregs_rs2 = cpuregs_rs1; + end + end +`else + wire[31:0] cpuregs_rdata1; + wire[31:0] cpuregs_rdata2; + + wire [5:0] cpuregs_waddr = latched_rd; + wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs; + wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0; + + `PICORV32_REGS cpuregs ( + .clk(clk), + .wen(resetn && cpuregs_write && latched_rd), + .waddr(cpuregs_waddr), + .raddr1(cpuregs_raddr1), + .raddr2(cpuregs_raddr2), + .wdata(cpuregs_wrdata), + .rdata1(cpuregs_rdata1), + .rdata2(cpuregs_rdata2) + ); + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin + cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0; + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; + cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0; + cpuregs_rs2 = cpuregs_rs1; + end + end +`endif + + assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask)); + + always @(posedge clk) begin + trap <= 0; + reg_sh <= 'bx; + reg_out <= 'bx; + set_mem_do_rinst = 0; + set_mem_do_rdata = 0; + set_mem_do_wdata = 0; + + alu_out_0_q <= alu_out_0; + alu_out_q <= alu_out; + + alu_wait <= 0; + alu_wait_2 <= 0; + + if (launch_next_insn) begin + dbg_rs1val <= 'bx; + dbg_rs2val <= 'bx; + dbg_rs1val_valid <= 0; + dbg_rs2val_valid <= 0; + end + + if (WITH_PCPI && CATCH_ILLINSN) begin + if (resetn && pcpi_valid && !pcpi_int_wait) begin + if (pcpi_timeout_counter) + pcpi_timeout_counter <= pcpi_timeout_counter - 1; + end else + pcpi_timeout_counter <= ~0; + pcpi_timeout <= !pcpi_timeout_counter; + end + + if (ENABLE_COUNTERS) begin + count_cycle <= resetn ? count_cycle + 1 : 0; + if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0; + end else begin + count_cycle <= 'bx; + count_instr <= 'bx; + end + + next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx; + + if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin + if (timer - 1 == 0) + next_irq_pending[irq_timer] = 1; + timer <= timer - 1; + end + + if (ENABLE_IRQ) begin + next_irq_pending = next_irq_pending | irq; + end + + decoder_trigger <= mem_do_rinst && mem_done; + decoder_trigger_q <= decoder_trigger; + decoder_pseudo_trigger <= 0; + decoder_pseudo_trigger_q <= decoder_pseudo_trigger; + do_waitirq <= 0; + + trace_valid <= 0; + + if (!ENABLE_TRACE) + trace_data <= 'bx; + + if (!resetn) begin + reg_pc <= PROGADDR_RESET; + reg_next_pc <= PROGADDR_RESET; + if (ENABLE_COUNTERS) + count_instr <= 0; + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_trace <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + pcpi_valid <= 0; + pcpi_timeout <= 0; + irq_active <= 0; + irq_delay <= 0; + irq_mask <= ~0; + next_irq_pending = 0; + irq_state <= 0; + eoi <= 0; + timer <= 0; + if (~STACKADDR) begin + latched_store <= 1; + latched_rd <= 2; + reg_out <= STACKADDR; + end + cpu_state <= cpu_state_fetch; + end else + (* parallel_case, full_case *) + case (cpu_state) + cpu_state_trap: begin + trap <= 1; + end + + cpu_state_fetch: begin + mem_do_rinst <= !decoder_trigger && !do_waitirq; + mem_wordsize <= 0; + + current_pc = reg_next_pc; + + (* parallel_case *) + case (1'b1) + latched_branch: begin + current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc; + `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);) + end + latched_store && !latched_branch: begin + `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);) + end + ENABLE_IRQ && irq_state[0]: begin + current_pc = PROGADDR_IRQ; + irq_active <= 1; + mem_do_rinst <= 1; + end + ENABLE_IRQ && irq_state[1]: begin + eoi <= irq_pending & ~irq_mask; + next_irq_pending = next_irq_pending & irq_mask; + end + endcase + + if (ENABLE_TRACE && latched_trace) begin + latched_trace <= 0; + trace_valid <= 1; + if (latched_branch) + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe); + else + trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out); + end + + reg_pc <= current_pc; + reg_next_pc <= current_pc; + + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + latched_rd <= decoded_rd; + latched_compr <= compressed_instr; + + if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin + irq_state <= + irq_state == 2'b00 ? 2'b01 : + irq_state == 2'b01 ? 2'b10 : 2'b00; + latched_compr <= latched_compr; + if (ENABLE_IRQ_QREGS) + latched_rd <= irqregs_offset | irq_state[0]; + else + latched_rd <= irq_state[0] ? 4 : 3; + end else + if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin + if (irq_pending) begin + latched_store <= 1; + reg_out <= irq_pending; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + mem_do_rinst <= 1; + end else + do_waitirq <= 1; + end else + if (decoder_trigger) begin + `debug($display("-- %-0t", $time);) + irq_delay <= irq_active; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + if (ENABLE_TRACE) + latched_trace <= 1; + if (ENABLE_COUNTERS) begin + count_instr <= count_instr + 1; + if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0; + end + if (instr_jal) begin + mem_do_rinst <= 1; + reg_next_pc <= current_pc + decoded_imm_uj; + latched_branch <= 1; + end else begin + mem_do_rinst <= 0; + mem_do_prefetch <= !instr_jalr && !instr_retirq; + cpu_state <= cpu_state_ld_rs1; + end + end + end + + cpu_state_ld_rs1: begin + reg_op1 <= 'bx; + reg_op2 <= 'bx; + + (* parallel_case *) + case (1'b1) + (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin + if (WITH_PCPI) begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + pcpi_valid <= 1; + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end else begin + cpu_state <= cpu_state_ld_rs2; + end + end else begin + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin + (* parallel_case, full_case *) + case (1'b1) + instr_rdcycle: + reg_out <= count_cycle[31:0]; + instr_rdcycleh && ENABLE_COUNTERS64: + reg_out <= count_cycle[63:32]; + instr_rdinstr: + reg_out <= count_instr[31:0]; + instr_rdinstrh && ENABLE_COUNTERS64: + reg_out <= count_instr[63:32]; + endcase + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + is_lui_auipc_jal: begin + reg_op1 <= instr_lui ? 0 : reg_pc; + reg_op2 <= decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_rd <= latched_rd | irqregs_offset; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_retirq: begin + eoi <= 0; + irq_active <= 0; + latched_branch <= 1; + latched_store <= 1; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_maskirq: begin + latched_store <= 1; + reg_out <= irq_mask; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + irq_mask <= cpuregs_rs1 | MASKED_IRQ; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin + latched_store <= 1; + reg_out <= timer; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + timer <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + is_lb_lh_lw_lbu_lhu && !instr_trap: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_ldmem; + mem_do_rinst <= 1; + end + is_slli_srli_srai && !BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_sh <= decoded_rs2; + cpu_state <= cpu_state_shift; + end + is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + default: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + (* parallel_case *) + case (1'b1) + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end else + cpu_state <= cpu_state_ld_rs2; + end + endcase + end + + cpu_state_ld_rs2: begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + + (* parallel_case *) + case (1'b1) + WITH_PCPI && instr_trap: begin + pcpi_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end + + cpu_state_exec: begin + reg_out <= reg_pc + decoded_imm; + if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin + mem_do_rinst <= mem_do_prefetch && !alu_wait_2; + alu_wait <= alu_wait_2; + end else + if (is_beq_bne_blt_bge_bltu_bgeu) begin + latched_rd <= 0; + latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + if (mem_done) + cpu_state <= cpu_state_fetch; + if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin + decoder_trigger <= 0; + set_mem_do_rinst = 1; + end + end else begin + latched_branch <= instr_jalr; + latched_store <= 1; + latched_stalu <= 1; + cpu_state <= cpu_state_fetch; + end + end + + cpu_state_shift: begin + latched_store <= 1; + if (reg_sh == 0) begin + reg_out <= reg_op1; + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_fetch; + end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 4; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4; + endcase + reg_sh <= reg_sh - 4; + end else begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 1; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1; + endcase + reg_sh <= reg_sh - 1; + end + end + + cpu_state_stmem: begin + if (ENABLE_TRACE) + reg_out <= reg_op2; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_wdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_sb: mem_wordsize <= 2; + instr_sh: mem_wordsize <= 1; + instr_sw: mem_wordsize <= 0; + endcase + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_wdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + cpu_state <= cpu_state_fetch; + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + end + end + end + + cpu_state_ldmem: begin + latched_store <= 1; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_rdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_lb || instr_lbu: mem_wordsize <= 2; + instr_lh || instr_lhu: mem_wordsize <= 1; + instr_lw: mem_wordsize <= 0; + endcase + latched_is_lu <= is_lbu_lhu_lw; + latched_is_lh <= instr_lh; + latched_is_lb <= instr_lb; + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_rdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + (* parallel_case, full_case *) + case (1'b1) + latched_is_lu: reg_out <= mem_rdata_word; + latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]); + latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]); + endcase + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + cpu_state <= cpu_state_fetch; + end + end + end + endcase + + if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin + if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin + `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (mem_wordsize == 1 && reg_op1[0] != 0) begin + `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + end + if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin + `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin + cpu_state <= cpu_state_trap; + end + + if (!resetn || mem_done) begin + mem_do_prefetch <= 0; + mem_do_rinst <= 0; + mem_do_rdata <= 0; + mem_do_wdata <= 0; + end + + if (set_mem_do_rinst) + mem_do_rinst <= 1; + if (set_mem_do_rdata) + mem_do_rdata <= 1; + if (set_mem_do_wdata) + mem_do_wdata <= 1; + + irq_pending <= next_irq_pending & ~MASKED_IRQ; + + if (!CATCH_MISALIGN) begin + if (COMPRESSED_ISA) begin + reg_pc[0] <= 0; + reg_next_pc[0] <= 0; + end else begin + reg_pc[1:0] <= 0; + reg_next_pc[1:0] <= 0; + end + end + current_pc = 'bx; + end + +`ifdef RISCV_FORMAL + reg dbg_irq_call; + reg dbg_irq_enter; + reg [31:0] dbg_irq_ret; + always @(posedge clk) begin + rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn; + rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0; + + rvfi_insn <= dbg_insn_opcode; + rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0; + rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0; + rvfi_pc_rdata <= dbg_insn_addr; + rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0; + rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0; + rvfi_trap <= trap; + rvfi_halt <= trap; + rvfi_intr <= dbg_irq_enter; + + if (!resetn) begin + dbg_irq_call <= 0; + dbg_irq_enter <= 0; + end else + if (rvfi_valid) begin + dbg_irq_call <= 0; + dbg_irq_enter <= dbg_irq_call; + end else + if (irq_state == 1) begin + dbg_irq_call <= 1; + dbg_irq_ret <= next_pc; + end + + if (!resetn) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end else + if (cpuregs_write && !irq_state) begin + rvfi_rd_addr <= latched_rd; + rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0; + end else + if (rvfi_valid) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + + casez (dbg_insn_opcode) + 32'b 0000000_?????_000??_???_?????_0001011: begin // getq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + 32'b 0000001_?????_?????_???_000??_0001011: begin // setq + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + 32'b 0000010_?????_00000_???_00000_0001011: begin // retirq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + endcase + + if (!dbg_irq_call) begin + if (dbg_mem_instr) begin + rvfi_mem_addr <= 0; + rvfi_mem_rmask <= 0; + rvfi_mem_wmask <= 0; + rvfi_mem_rdata <= 0; + rvfi_mem_wdata <= 0; + end else + if (dbg_mem_valid && dbg_mem_ready) begin + rvfi_mem_addr <= dbg_mem_addr; + rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0; + rvfi_mem_wmask <= dbg_mem_wstrb; + rvfi_mem_rdata <= dbg_mem_rdata; + rvfi_mem_wdata <= dbg_mem_wdata; + end + end + end + + always @* begin + rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr; + end +`endif + + // Formal Verification +`ifdef FORMAL + reg [3:0] last_mem_nowait; + always @(posedge clk) + last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid}; + + // stall the memory interface for max 4 cycles + restrict property (|last_mem_nowait || mem_ready || !mem_valid); + + // resetn low in first cycle, after that resetn high + restrict property (resetn != $initstate); + + // this just makes it much easier to read traces. uncomment as needed. + // assume property (mem_valid || !mem_ready); + + reg ok; + always @* begin + if (resetn) begin + // instruction fetches are read-only + if (mem_valid && mem_instr) + assert (mem_wstrb == 0); + + // cpu_state must be valid + ok = 0; + if (cpu_state == cpu_state_trap) ok = 1; + if (cpu_state == cpu_state_fetch) ok = 1; + if (cpu_state == cpu_state_ld_rs1) ok = 1; + if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT; + if (cpu_state == cpu_state_exec) ok = 1; + if (cpu_state == cpu_state_shift) ok = 1; + if (cpu_state == cpu_state_stmem) ok = 1; + if (cpu_state == cpu_state_ldmem) ok = 1; + assert (ok); + end + end + + reg last_mem_la_read = 0; + reg last_mem_la_write = 0; + reg [31:0] last_mem_la_addr; + reg [31:0] last_mem_la_wdata; + reg [3:0] last_mem_la_wstrb = 0; + + always @(posedge clk) begin + last_mem_la_read <= mem_la_read; + last_mem_la_write <= mem_la_write; + last_mem_la_addr <= mem_la_addr; + last_mem_la_wdata <= mem_la_wdata; + last_mem_la_wstrb <= mem_la_wstrb; + + if (last_mem_la_read) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wstrb == 0); + end + if (last_mem_la_write) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wdata == last_mem_la_wdata); + assert(mem_wstrb == last_mem_la_wstrb); + end + if (mem_la_read || mem_la_write) begin + assert(!mem_valid || mem_ready); + end + end +`endif +endmodule + +// This is a simple example implementation of PICORV32_REGS. +// Use the PICORV32_REGS mechanism if you want to use custom +// memory resources to implement the processor register file. +// Note that your implementation must match the requirements of +// the PicoRV32 configuration. (e.g. QREGS, etc) +module picorv32_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:30]; + + always @(posedge clk) + if (wen) regs[~waddr[4:0]] <= wdata; + + assign rdata1 = regs[~raddr1[4:0]]; + assign rdata2 = regs[~raddr2[4:0]]; +endmodule + + +/*************************************************************** + * picorv32_pcpi_mul + ***************************************************************/ + +module picorv32_pcpi_mul #( + parameter STEPS_AT_ONCE = 1, + parameter CARRY_CHAIN = 4 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg pcpi_wait_q; + wire mul_start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_mul <= 0; + instr_mulh <= 0; + instr_mulhsu <= 0; + instr_mulhu <= 0; + + if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul <= 1; + 3'b001: instr_mulh <= 1; + 3'b010: instr_mulhsu <= 1; + 3'b011: instr_mulhu <= 1; + endcase + end + + pcpi_wait <= instr_any_mul; + pcpi_wait_q <= pcpi_wait; + end + + reg [63:0] rs1, rs2, rd, rdx; + reg [63:0] next_rs1, next_rs2, this_rs2; + reg [63:0] next_rd, next_rdx, next_rdt; + reg [6:0] mul_counter; + reg mul_waiting; + reg mul_finish; + integer i, j; + + // carry save accumulator + always @* begin + next_rd = rd; + next_rdx = rdx; + next_rs1 = rs1; + next_rs2 = rs2; + + for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin + this_rs2 = next_rs1[0] ? next_rs2 : 0; + if (CARRY_CHAIN == 0) begin + next_rdt = next_rd ^ next_rdx ^ this_rs2; + next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1; + next_rd = next_rdt; + end else begin + next_rdt = 0; + for (j = 0; j < 64; j = j + CARRY_CHAIN) + {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} = + next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN]; + next_rdx = next_rdt << 1; + end + next_rs1 = next_rs1 >> 1; + next_rs2 = next_rs2 << 1; + end + end + + always @(posedge clk) begin + mul_finish <= 0; + if (!resetn) begin + mul_waiting <= 1; + end else + if (mul_waiting) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + + rd <= 0; + rdx <= 0; + mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE); + mul_waiting <= !mul_start; + end else begin + rd <= next_rd; + rdx <= next_rdx; + rs1 <= next_rs1; + rs2 <= next_rs2; + + mul_counter <= mul_counter - STEPS_AT_ONCE; + if (mul_counter[6]) begin + mul_finish <= 1; + mul_waiting <= 1; + end + end + end + + always @(posedge clk) begin + pcpi_wr <= 0; + pcpi_ready <= 0; + if (mul_finish && resetn) begin + pcpi_wr <= 1; + pcpi_ready <= 1; + pcpi_rd <= instr_any_mulh ? rd >> 32 : rd; + end + end +endmodule + +module picorv32_pcpi_fast_mul #( + parameter EXTRA_MUL_FFS = 0, + parameter EXTRA_INSN_FFS = 0, + parameter MUL_CLKGATE = 0 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output pcpi_wr, + output [31:0] pcpi_rd, + output pcpi_wait, + output pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg shift_out; + reg [3:0] active; + reg [32:0] rs1, rs2, rs1_q, rs2_q; + reg [63:0] rd, rd_q; + + wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001; + reg pcpi_insn_valid_q; + + always @* begin + instr_mul = 0; + instr_mulh = 0; + instr_mulhsu = 0; + instr_mulhu = 0; + + if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul = 1; + 3'b001: instr_mulh = 1; + 3'b010: instr_mulhsu = 1; + 3'b011: instr_mulhu = 1; + endcase + end + end + + always @(posedge clk) begin + pcpi_insn_valid_q <= pcpi_insn_valid; + if (!MUL_CLKGATE || active[0]) begin + rs1_q <= rs1; + rs2_q <= rs2; + end + if (!MUL_CLKGATE || active[1]) begin + rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2); + end + if (!MUL_CLKGATE || active[2]) begin + rd_q <= rd; + end + end + + always @(posedge clk) begin + if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + active[0] <= 1; + end else begin + active[0] <= 0; + end + + active[3:1] <= active; + shift_out <= instr_any_mulh; + + if (!resetn) + active <= 0; + end + + assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1]; + assign pcpi_wait = 0; + assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1]; +`ifdef RISCV_FORMAL_ALTOPS + assign pcpi_rd = + instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e : + instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 : + instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 : + instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx; +`else + assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd); +`endif +endmodule + + +/*************************************************************** + * picorv32_pcpi_div + ***************************************************************/ + +module picorv32_pcpi_div ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_div, instr_divu, instr_rem, instr_remu; + wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu}; + + reg pcpi_wait_q; + wire start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_div <= 0; + instr_divu <= 0; + instr_rem <= 0; + instr_remu <= 0; + + if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b100: instr_div <= 1; + 3'b101: instr_divu <= 1; + 3'b110: instr_rem <= 1; + 3'b111: instr_remu <= 1; + endcase + end + + pcpi_wait <= instr_any_div_rem && resetn; + pcpi_wait_q <= pcpi_wait && resetn; + end + + reg [31:0] dividend; + reg [62:0] divisor; + reg [31:0] quotient; + reg [31:0] quotient_msk; + reg running; + reg outsign; + + always @(posedge clk) begin + pcpi_ready <= 0; + pcpi_wr <= 0; + pcpi_rd <= 'bx; + + if (!resetn) begin + running <= 0; + end else + if (start) begin + running <= 1; + dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1; + divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31; + outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]); + quotient <= 0; + quotient_msk <= 1 << 31; + end else + if (!quotient_msk && running) begin + running <= 0; + pcpi_ready <= 1; + pcpi_wr <= 1; +`ifdef RISCV_FORMAL_ALTOPS + case (1) + instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec; + instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70; + instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5; + instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1; + endcase +`else + if (instr_div || instr_divu) + pcpi_rd <= outsign ? -quotient : quotient; + else + pcpi_rd <= outsign ? -dividend : dividend; +`endif + end else begin + if (divisor <= dividend) begin + dividend <= dividend - divisor; + quotient <= quotient | quotient_msk; + end + divisor <= divisor >> 1; +`ifdef RISCV_FORMAL_ALTOPS + quotient_msk <= quotient_msk >> 5; +`else + quotient_msk <= quotient_msk >> 1; +`endif + end + end +endmodule + + +/*************************************************************** + * picorv32_axi + ***************************************************************/ + +module picorv32_axi #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output trap, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_rdata; + + picorv32_axi_adapter axi_adapter ( + .clk (clk ), + .resetn (resetn ), + .mem_axi_awvalid(mem_axi_awvalid), + .mem_axi_awready(mem_axi_awready), + .mem_axi_awaddr (mem_axi_awaddr ), + .mem_axi_awprot (mem_axi_awprot ), + .mem_axi_wvalid (mem_axi_wvalid ), + .mem_axi_wready (mem_axi_wready ), + .mem_axi_wdata (mem_axi_wdata ), + .mem_axi_wstrb (mem_axi_wstrb ), + .mem_axi_bvalid (mem_axi_bvalid ), + .mem_axi_bready (mem_axi_bready ), + .mem_axi_arvalid(mem_axi_arvalid), + .mem_axi_arready(mem_axi_arready), + .mem_axi_araddr (mem_axi_araddr ), + .mem_axi_arprot (mem_axi_arprot ), + .mem_axi_rvalid (mem_axi_rvalid ), + .mem_axi_rready (mem_axi_rready ), + .mem_axi_rdata (mem_axi_rdata ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); +endmodule + + +/*************************************************************** + * picorv32_axi_adapter + ***************************************************************/ + +module picorv32_axi_adapter ( + input clk, resetn, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Native PicoRV32 memory interface + + input mem_valid, + input mem_instr, + output mem_ready, + input [31:0] mem_addr, + input [31:0] mem_wdata, + input [ 3:0] mem_wstrb, + output [31:0] mem_rdata +); + reg ack_awvalid; + reg ack_arvalid; + reg ack_wvalid; + reg xfer_done; + + assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid; + assign mem_axi_awaddr = mem_addr; + assign mem_axi_awprot = 0; + + assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid; + assign mem_axi_araddr = mem_addr; + assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000; + + assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid; + assign mem_axi_wdata = mem_wdata; + assign mem_axi_wstrb = mem_wstrb; + + assign mem_ready = mem_axi_bvalid || mem_axi_rvalid; + assign mem_axi_bready = mem_valid && |mem_wstrb; + assign mem_axi_rready = mem_valid && !mem_wstrb; + assign mem_rdata = mem_axi_rdata; + + always @(posedge clk) begin + if (!resetn) begin + ack_awvalid <= 0; + end else begin + xfer_done <= mem_valid && mem_ready; + if (mem_axi_awready && mem_axi_awvalid) + ack_awvalid <= 1; + if (mem_axi_arready && mem_axi_arvalid) + ack_arvalid <= 1; + if (mem_axi_wready && mem_axi_wvalid) + ack_wvalid <= 1; + if (xfer_done || !mem_valid) begin + ack_awvalid <= 0; + ack_arvalid <= 0; + ack_wvalid <= 0; + end + end + end +endmodule + + +/*************************************************************** + * picorv32_wb + ***************************************************************/ + +module picorv32_wb #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + output trap, + + // Wishbone interfaces + input wb_rst_i, + input wb_clk_i, + + output reg [31:0] wbm_adr_o, + output reg [31:0] wbm_dat_o, + input [31:0] wbm_dat_i, + output reg wbm_we_o, + output reg [3:0] wbm_sel_o, + output reg wbm_stb_o, + input wbm_ack_i, + output reg wbm_cyc_o, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data, + + output mem_instr +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + reg mem_ready; + reg [31:0] mem_rdata; + + wire clk; + wire resetn; + + assign clk = wb_clk_i; + assign resetn = ~wb_rst_i; + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); + + localparam IDLE = 2'b00; + localparam WBSTART = 2'b01; + localparam WBEND = 2'b10; + + reg [1:0] state; + + wire we; + assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]); + + always @(posedge wb_clk_i) begin + if (wb_rst_i) begin + wbm_adr_o <= 0; + wbm_dat_o <= 0; + wbm_we_o <= 0; + wbm_sel_o <= 0; + wbm_stb_o <= 0; + wbm_cyc_o <= 0; + state <= IDLE; + end else begin + case (state) + IDLE: begin + if (mem_valid) begin + wbm_adr_o <= mem_addr; + wbm_dat_o <= mem_wdata; + wbm_we_o <= we; + wbm_sel_o <= mem_wstrb; + + wbm_stb_o <= 1'b1; + wbm_cyc_o <= 1'b1; + state <= WBSTART; + end else begin + mem_ready <= 1'b0; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBSTART:begin + if (wbm_ack_i) begin + mem_rdata <= wbm_dat_i; + mem_ready <= 1'b1; + + state <= WBEND; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBEND: begin + mem_ready <= 1'b0; + + state <= IDLE; + end + default: + state <= IDLE; + endcase + end + end +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc.sdc b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc.sdc new file mode 100644 index 0000000000000000000000000000000000000000..11ebd3592e21027e8d0c923c76e3e0dd1b5436db --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc.sdc @@ -0,0 +1 @@ +create_clock -period 10 clk_bufg diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc_noflash.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc_noflash.v new file mode 100644 index 0000000000000000000000000000000000000000..c0cc21c5740dc58d01f700a9dfbabb2ce16535bc --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/picosoc_noflash.v @@ -0,0 +1,266 @@ +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * This is a modified PicoSoC example which has removed the requirement + * for an external SPI flash. The PicoRV32 program is stored in ROM implemented + * as a number of case statements. The ROM file is generated using an external + * script. + * + * + * Copyright (C) 2017 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`ifndef PICORV32_REGS +`ifdef PICORV32_V +//`error "picosoc.v must be read before picorv32.v!" +`endif + +`define PICORV32_REGS picosoc_regs +`endif + +module picosoc_noflash ( + input clk, + input resetn, + + output iomem_valid, + input iomem_ready, + output [ 3:0] iomem_wstrb, + output [31:0] iomem_addr, + output [31:0] iomem_wdata, + input [31:0] iomem_rdata, + + // Rewrite firmware + input progmem_wen, + input [31:0] progmem_waddr, + input [31:0] progmem_wdata, + + input irq_5, + input irq_6, + input irq_7, + + output ser_tx, + input ser_rx +); + parameter integer MEM_WORDS = 8192; + parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory + parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash + + reg [31:0] irq; + wire irq_stall = 0; + wire irq_uart = 0; + + always @* begin + irq = 0; + irq[3] = irq_stall; + irq[4] = irq_uart; + irq[5] = irq_5; + irq[6] = irq_6; + irq[7] = irq_7; + end + + wire mem_valid; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [3:0] mem_wstrb; + wire [31:0] mem_rdata; + + wire progmem_ready; + wire [31:0] progmem_rdata; + + reg ram_ready; + wire [31:0] ram_rdata; + + assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); + assign iomem_wstrb = mem_wstrb; + assign iomem_addr = mem_addr; + assign iomem_wdata = mem_wdata; + + wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000); + + wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004); + wire [31:0] simpleuart_reg_div_do; + + wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008); + wire [31:0] simpleuart_reg_dat_do; + wire simpleuart_reg_dat_wait; + + assign mem_ready = + (iomem_valid && iomem_ready) || progmem_ready || ram_ready || spimemio_cfgreg_sel || + simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait); + + assign mem_rdata = + (iomem_valid && iomem_ready) ? iomem_rdata : + progmem_ready ? progmem_rdata : + ram_ready ? ram_rdata : + spimemio_cfgreg_sel ? 32'h0000_0000 : // Mockup, will always read 0 + simpleuart_reg_div_sel ? simpleuart_reg_div_do : + simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000; + +`ifdef SIMULATION + wire trace_valid; + wire [35:0] trace_data; + integer trace_file; +`endif + + picorv32 #( + .STACKADDR(STACKADDR), + .PROGADDR_RESET(PROGADDR_RESET), + .PROGADDR_IRQ(32'h 0000_0000), + .BARREL_SHIFTER(1), + .COMPRESSED_ISA(1), + .ENABLE_MUL(1), + .ENABLE_DIV(1), + .ENABLE_IRQ(1), +`ifdef SIMULATION + .ENABLE_IRQ_QREGS(0), + .ENABLE_TRACE(1) +`else + .ENABLE_IRQ_QREGS(0) +`endif + ) cpu ( + .clk (clk ), + .resetn (resetn ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ), +`ifdef SIMULATION + .irq (irq ), + .trace_valid (trace_valid), + .trace_data (trace_data ) +`else + .irq (irq ) +`endif + ); + + // This it the program ROM memory for the PicoRV32 + progmem progmem ( + .clk (clk), + .rstn (resetn), + + .valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000), + .ready (progmem_ready), + .addr (mem_addr), + .rdata (progmem_rdata), + .wen (progmem_wen), + .waddr (progmem_waddr), + .wdata (progmem_wdata) + ); + + simpleuart simpleuart ( + .clk (clk ), + .resetn (resetn ), + + .ser_tx (ser_tx ), + .ser_rx (ser_rx ), + + .reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000), + .reg_div_di (mem_wdata), + .reg_div_do (simpleuart_reg_div_do), + + .reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0), + .reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb), + .reg_dat_di (mem_wdata), + .reg_dat_do (simpleuart_reg_dat_do), + .reg_dat_wait(simpleuart_reg_dat_wait) + ); + + always @(posedge clk) + ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS; + + picosoc_mem #(.WORDS(MEM_WORDS)) memory ( + .clk(clk), + .wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0), + .addr(mem_addr[23:2]), + .wdata(mem_wdata), + .rdata(ram_rdata) + ); + + // Simulation debug +`ifdef SIMULATION + always @(posedge clk) + if (resetn) begin + if ( mem_instr && mem_valid && mem_ready) + $display("Inst rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata); + if (!mem_instr && mem_valid && mem_ready) + $display("Data rd: [0x%08X] = 0x%08X", mem_addr, mem_rdata); + end + + // Trace + initial begin + + trace_file = $fopen("testbench.trace", "w"); + repeat (10) @(posedge clk); + + while(1) begin + @(posedge clk) + if (resetn && trace_valid) + $fwrite(trace_file, "%x\n", trace_data); + $fflush(trace_file); + //$display("Trace : %09X", trace_data); + end + end + +`endif // SIMULATION + +endmodule + +// Implementation note: +// Replace the following two modules with wrappers for your SRAM cells. + +module picosoc_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + (* ram_style = "block" *) reg [31:0] regs [0:31]; // distribuirani bio + + always @(posedge clk) + if (wen) regs[waddr[4:0]] <= wdata; + + assign rdata1 = regs[raddr1[4:0]]; + assign rdata2 = regs[raddr2[4:0]]; +endmodule + +module picosoc_mem #( + parameter integer WORDS = 32 +) ( + input clk, + input [3:0] wen, + input [21:0] addr, + input [31:0] wdata, + output reg [31:0] rdata +); + (* ram_style = "block" *) reg [31:0] mem [0:WORDS-1]; + + //initial $readmemh("firmware.hex", mem); + always @(posedge clk) begin + rdata <= mem[addr]; + if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0]; + if (wen[1]) mem[addr][15: 8] <= wdata[15: 8]; + if (wen[2]) mem[addr][23:16] <= wdata[23:16]; + if (wen[3]) mem[addr][31:24] <= wdata[31:24]; + end +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/progmem.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/progmem.v new file mode 100644 index 0000000000000000000000000000000000000000..16febeb1c747b04f9d85822c88f41427a15f183a --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/progmem.v @@ -0,0 +1,5937 @@ + +module progmem ( + // Clock & reset + input wire clk, + input wire rstn, + + // PicoRV32 bus interface + input wire valid, + output wire ready, + input wire [31:0] addr, + output wire [31:0] rdata, + // Rewrite firmware + input wire wen, + input wire [31:0] waddr, + input wire [31:0] wdata +); + + // ============================================================================ + + localparam MEM_SIZE_BITS = 13; // In 32-bit words + localparam MEM_SIZE = 1 << MEM_SIZE_BITS; + localparam MEM_ADDR_MASK = 32'h0010_0000; + + // ============================================================================ + + wire [MEM_SIZE_BITS-1:0] mem_addr; + reg [ 31:0] mem_data; + reg [ 31:0] mem [0:MEM_SIZE]; + + initial begin + mem['h0000] <= 32'h00000093; + mem['h0001] <= 32'h00000193; + mem['h0002] <= 32'h00000213; + mem['h0003] <= 32'h00000293; + mem['h0004] <= 32'h00000313; + mem['h0005] <= 32'h00000393; + mem['h0006] <= 32'h00000413; + mem['h0007] <= 32'h00000493; + mem['h0008] <= 32'h00000513; + mem['h0009] <= 32'h00000593; + mem['h000A] <= 32'h00000613; + mem['h000B] <= 32'h00000693; + mem['h000C] <= 32'h00000713; + mem['h000D] <= 32'h00000793; + mem['h000E] <= 32'h00000813; + mem['h000F] <= 32'h00000893; + mem['h0010] <= 32'h00000913; + mem['h0011] <= 32'h00000993; + mem['h0012] <= 32'h00000A13; + mem['h0013] <= 32'h00000A93; + mem['h0014] <= 32'h00000B13; + mem['h0015] <= 32'h00000B93; + mem['h0016] <= 32'h00000C13; + mem['h0017] <= 32'h00000C93; + mem['h0018] <= 32'h00000D13; + mem['h0019] <= 32'h00000D93; + mem['h001A] <= 32'h00000E13; + mem['h001B] <= 32'h00000E93; + mem['h001C] <= 32'h00000F13; + mem['h001D] <= 32'h00000F93; + mem['h001E] <= 32'h00000513; + mem['h001F] <= 32'h00000593; + mem['h0020] <= 32'h00B52023; + mem['h0021] <= 32'h00450513; + mem['h0022] <= 32'hFE254CE3; + mem['h0023] <= 32'h00006517; + mem['h0024] <= 32'hAE850513; + mem['h0025] <= 32'h00000593; + mem['h0026] <= 32'h07C00613; + mem['h0027] <= 32'h00C5DC63; + mem['h0028] <= 32'h00052683; + mem['h0029] <= 32'h00D5A023; + mem['h002A] <= 32'h00450513; + mem['h002B] <= 32'h00458593; + mem['h002C] <= 32'hFEC5C8E3; + mem['h002D] <= 32'h07C00513; + mem['h002E] <= 32'h53000593; + mem['h002F] <= 32'h00B55863; + mem['h0030] <= 32'h00052023; + mem['h0031] <= 32'h00450513; + mem['h0032] <= 32'hFEB54CE3; + mem['h0033] <= 32'h3A5040EF; + mem['h0034] <= 32'h0000006F; + mem['h0035] <= 32'hFF010113; + mem['h0036] <= 32'h00812623; + mem['h0037] <= 32'h01010413; + mem['h0038] <= 32'h030007B7; + mem['h0039] <= 32'h0007A783; + mem['h003A] <= 32'h0107D793; + mem['h003B] <= 32'h0FF7F713; + mem['h003C] <= 32'h52E00623; + mem['h003D] <= 32'h00000013; + mem['h003E] <= 32'h00C12403; + mem['h003F] <= 32'h01010113; + mem['h0040] <= 32'h00008067; + mem['h0041] <= 32'hFE010113; + mem['h0042] <= 32'h00812E23; + mem['h0043] <= 32'h02010413; + mem['h0044] <= 32'h00300793; + mem['h0045] <= 32'hFEF406A3; + mem['h0046] <= 32'hFE0407A3; + mem['h0047] <= 32'h5940006F; + mem['h0048] <= 32'hFE040723; + mem['h0049] <= 32'h5740006F; + mem['h004A] <= 32'hFEF44703; + mem['h004B] <= 32'h00070793; + mem['h004C] <= 32'h00279793; + mem['h004D] <= 32'h00E787B3; + mem['h004E] <= 32'h00379793; + mem['h004F] <= 32'h00078713; + mem['h0050] <= 32'hFEE44783; + mem['h0051] <= 32'h00F707B3; + mem['h0052] <= 32'h00279713; + mem['h0053] <= 32'h052007B7; + mem['h0054] <= 32'h00F707B3; + mem['h0055] <= 32'h00C00713; + mem['h0056] <= 32'h00E7A023; + mem['h0057] <= 32'hFEF44703; + mem['h0058] <= 32'hFED44783; + mem['h0059] <= 32'h00F71E63; + mem['h005A] <= 32'hFEE44703; + mem['h005B] <= 32'h00200793; + mem['h005C] <= 32'h00E7F863; + mem['h005D] <= 32'hFEE44703; + mem['h005E] <= 32'h00500793; + mem['h005F] <= 32'h08E7F063; + mem['h0060] <= 32'hFEF44703; + mem['h0061] <= 32'hFED44783; + mem['h0062] <= 32'h00478793; + mem['h0063] <= 32'h00F71E63; + mem['h0064] <= 32'hFEE44703; + mem['h0065] <= 32'h00200793; + mem['h0066] <= 32'h00E7F863; + mem['h0067] <= 32'hFEE44703; + mem['h0068] <= 32'h00500793; + mem['h0069] <= 32'h04E7FC63; + mem['h006A] <= 32'hFEE44703; + mem['h006B] <= 32'h00300793; + mem['h006C] <= 32'h02F71063; + mem['h006D] <= 32'hFEF44703; + mem['h006E] <= 32'hFED44783; + mem['h006F] <= 32'h00F76A63; + mem['h0070] <= 32'hFEF44703; + mem['h0071] <= 32'hFED44783; + mem['h0072] <= 32'h00478793; + mem['h0073] <= 32'h02E7D863; + mem['h0074] <= 32'hFEE44703; + mem['h0075] <= 32'h00500793; + mem['h0076] <= 32'h04F71A63; + mem['h0077] <= 32'hFED44783; + mem['h0078] <= 32'h00178713; + mem['h0079] <= 32'hFEF44783; + mem['h007A] <= 32'h04F75263; + mem['h007B] <= 32'hFEF44703; + mem['h007C] <= 32'hFED44783; + mem['h007D] <= 32'h00478793; + mem['h007E] <= 32'h02E7CA63; + mem['h007F] <= 32'hFEF44703; + mem['h0080] <= 32'h00070793; + mem['h0081] <= 32'h00279793; + mem['h0082] <= 32'h00E787B3; + mem['h0083] <= 32'h00379793; + mem['h0084] <= 32'h00078713; + mem['h0085] <= 32'hFEE44783; + mem['h0086] <= 32'h00F707B3; + mem['h0087] <= 32'h00279713; + mem['h0088] <= 32'h052007B7; + mem['h0089] <= 32'h00F707B3; + mem['h008A] <= 32'h0007A023; + mem['h008B] <= 32'hFEE44703; + mem['h008C] <= 32'h00700793; + mem['h008D] <= 32'h00F70863; + mem['h008E] <= 32'hFEE44703; + mem['h008F] <= 32'h00900793; + mem['h0090] <= 32'h02F71063; + mem['h0091] <= 32'hFED44703; + mem['h0092] <= 32'hFEF44783; + mem['h0093] <= 32'h00F77A63; + mem['h0094] <= 32'hFEF44703; + mem['h0095] <= 32'hFED44783; + mem['h0096] <= 32'h00478793; + mem['h0097] <= 32'h02E7DC63; + mem['h0098] <= 32'hFEE44703; + mem['h0099] <= 32'h00800793; + mem['h009A] <= 32'h00F71A63; + mem['h009B] <= 32'hFEF44703; + mem['h009C] <= 32'hFED44783; + mem['h009D] <= 32'h00278793; + mem['h009E] <= 32'h00F70E63; + mem['h009F] <= 32'hFEE44703; + mem['h00A0] <= 32'h00800793; + mem['h00A1] <= 32'h04F71063; + mem['h00A2] <= 32'hFEF44703; + mem['h00A3] <= 32'hFED44783; + mem['h00A4] <= 32'h02F71A63; + mem['h00A5] <= 32'hFEF44703; + mem['h00A6] <= 32'h00070793; + mem['h00A7] <= 32'h00279793; + mem['h00A8] <= 32'h00E787B3; + mem['h00A9] <= 32'h00379793; + mem['h00AA] <= 32'h00078713; + mem['h00AB] <= 32'hFEE44783; + mem['h00AC] <= 32'h00F707B3; + mem['h00AD] <= 32'h00279713; + mem['h00AE] <= 32'h052007B7; + mem['h00AF] <= 32'h00F707B3; + mem['h00B0] <= 32'h0007A023; + mem['h00B1] <= 32'hFEF44703; + mem['h00B2] <= 32'hFED44783; + mem['h00B3] <= 32'h00F71E63; + mem['h00B4] <= 32'hFEE44703; + mem['h00B5] <= 32'h00A00793; + mem['h00B6] <= 32'h00E7F863; + mem['h00B7] <= 32'hFEE44703; + mem['h00B8] <= 32'h00D00793; + mem['h00B9] <= 32'h02E7F663; + mem['h00BA] <= 32'hFEE44703; + mem['h00BB] <= 32'h00C00793; + mem['h00BC] <= 32'h04F71863; + mem['h00BD] <= 32'hFEF44703; + mem['h00BE] <= 32'hFED44783; + mem['h00BF] <= 32'h04F76263; + mem['h00C0] <= 32'hFEF44703; + mem['h00C1] <= 32'hFED44783; + mem['h00C2] <= 32'h00478793; + mem['h00C3] <= 32'h02E7CA63; + mem['h00C4] <= 32'hFEF44703; + mem['h00C5] <= 32'h00070793; + mem['h00C6] <= 32'h00279793; + mem['h00C7] <= 32'h00E787B3; + mem['h00C8] <= 32'h00379793; + mem['h00C9] <= 32'h00078713; + mem['h00CA] <= 32'hFEE44783; + mem['h00CB] <= 32'h00F707B3; + mem['h00CC] <= 32'h00279713; + mem['h00CD] <= 32'h052007B7; + mem['h00CE] <= 32'h00F707B3; + mem['h00CF] <= 32'h0007A023; + mem['h00D0] <= 32'hFEF44703; + mem['h00D1] <= 32'hFED44783; + mem['h00D2] <= 32'h00F70A63; + mem['h00D3] <= 32'hFEF44703; + mem['h00D4] <= 32'hFED44783; + mem['h00D5] <= 32'h00478793; + mem['h00D6] <= 32'h00F71E63; + mem['h00D7] <= 32'hFEE44703; + mem['h00D8] <= 32'h00E00793; + mem['h00D9] <= 32'h00E7F863; + mem['h00DA] <= 32'hFEE44703; + mem['h00DB] <= 32'h01100793; + mem['h00DC] <= 32'h04E7F463; + mem['h00DD] <= 32'hFEF44703; + mem['h00DE] <= 32'hFED44783; + mem['h00DF] <= 32'h00278793; + mem['h00E0] <= 32'h00F71863; + mem['h00E1] <= 32'hFEE44703; + mem['h00E2] <= 32'h01000793; + mem['h00E3] <= 32'h02F70663; + mem['h00E4] <= 32'hFEE44703; + mem['h00E5] <= 32'h00F00793; + mem['h00E6] <= 32'h04F71863; + mem['h00E7] <= 32'hFEF44703; + mem['h00E8] <= 32'hFED44783; + mem['h00E9] <= 32'h04F76263; + mem['h00EA] <= 32'hFEF44703; + mem['h00EB] <= 32'hFED44783; + mem['h00EC] <= 32'h00478793; + mem['h00ED] <= 32'h02E7CA63; + mem['h00EE] <= 32'hFEF44703; + mem['h00EF] <= 32'h00070793; + mem['h00F0] <= 32'h00279793; + mem['h00F1] <= 32'h00E787B3; + mem['h00F2] <= 32'h00379793; + mem['h00F3] <= 32'h00078713; + mem['h00F4] <= 32'hFEE44783; + mem['h00F5] <= 32'h00F707B3; + mem['h00F6] <= 32'h00279713; + mem['h00F7] <= 32'h052007B7; + mem['h00F8] <= 32'h00F707B3; + mem['h00F9] <= 32'h0007A023; + mem['h00FA] <= 32'hFEF44703; + mem['h00FB] <= 32'hFED44783; + mem['h00FC] <= 32'h02F71A63; + mem['h00FD] <= 32'hFEE44703; + mem['h00FE] <= 32'h01400793; + mem['h00FF] <= 32'h08F70A63; + mem['h0100] <= 32'hFEE44703; + mem['h0101] <= 32'h01500793; + mem['h0102] <= 32'h08F70463; + mem['h0103] <= 32'hFEE44703; + mem['h0104] <= 32'h01700793; + mem['h0105] <= 32'h06F70E63; + mem['h0106] <= 32'hFEE44703; + mem['h0107] <= 32'h01800793; + mem['h0108] <= 32'h06F70863; + mem['h0109] <= 32'hFEE44703; + mem['h010A] <= 32'h01400793; + mem['h010B] <= 32'h02F71063; + mem['h010C] <= 32'hFEF44703; + mem['h010D] <= 32'hFED44783; + mem['h010E] <= 32'h00F76A63; + mem['h010F] <= 32'hFEF44703; + mem['h0110] <= 32'hFED44783; + mem['h0111] <= 32'h00478793; + mem['h0112] <= 32'h04E7D463; + mem['h0113] <= 32'hFEE44703; + mem['h0114] <= 32'h01800793; + mem['h0115] <= 32'h02F71063; + mem['h0116] <= 32'hFEF44703; + mem['h0117] <= 32'hFED44783; + mem['h0118] <= 32'h00F76A63; + mem['h0119] <= 32'hFEF44703; + mem['h011A] <= 32'hFED44783; + mem['h011B] <= 32'h00478793; + mem['h011C] <= 32'h02E7D063; + mem['h011D] <= 32'hFEE44703; + mem['h011E] <= 32'h01600793; + mem['h011F] <= 32'h04F71463; + mem['h0120] <= 32'hFEF44703; + mem['h0121] <= 32'hFED44783; + mem['h0122] <= 32'h00178793; + mem['h0123] <= 32'h02F71C63; + mem['h0124] <= 32'hFEF44703; + mem['h0125] <= 32'h00070793; + mem['h0126] <= 32'h00279793; + mem['h0127] <= 32'h00E787B3; + mem['h0128] <= 32'h00379793; + mem['h0129] <= 32'h00078713; + mem['h012A] <= 32'hFEE44783; + mem['h012B] <= 32'h00F707B3; + mem['h012C] <= 32'h00279713; + mem['h012D] <= 32'h052007B7; + mem['h012E] <= 32'h00F707B3; + mem['h012F] <= 32'h00B00713; + mem['h0130] <= 32'h00E7A023; + mem['h0131] <= 32'hFEE44703; + mem['h0132] <= 32'h01A00793; + mem['h0133] <= 32'h00F70863; + mem['h0134] <= 32'hFEE44703; + mem['h0135] <= 32'h01C00793; + mem['h0136] <= 32'h02F71063; + mem['h0137] <= 32'hFED44703; + mem['h0138] <= 32'hFEF44783; + mem['h0139] <= 32'h00F77A63; + mem['h013A] <= 32'hFEF44703; + mem['h013B] <= 32'hFED44783; + mem['h013C] <= 32'h00478793; + mem['h013D] <= 32'h02E7DC63; + mem['h013E] <= 32'hFEE44703; + mem['h013F] <= 32'h01B00793; + mem['h0140] <= 32'h00F71A63; + mem['h0141] <= 32'hFEF44703; + mem['h0142] <= 32'hFED44783; + mem['h0143] <= 32'h00278793; + mem['h0144] <= 32'h00F70E63; + mem['h0145] <= 32'hFEE44703; + mem['h0146] <= 32'h01B00793; + mem['h0147] <= 32'h04F71263; + mem['h0148] <= 32'hFEF44703; + mem['h0149] <= 32'hFED44783; + mem['h014A] <= 32'h02F71C63; + mem['h014B] <= 32'hFEF44703; + mem['h014C] <= 32'h00070793; + mem['h014D] <= 32'h00279793; + mem['h014E] <= 32'h00E787B3; + mem['h014F] <= 32'h00379793; + mem['h0150] <= 32'h00078713; + mem['h0151] <= 32'hFEE44783; + mem['h0152] <= 32'h00F707B3; + mem['h0153] <= 32'h00279713; + mem['h0154] <= 32'h052007B7; + mem['h0155] <= 32'h00F707B3; + mem['h0156] <= 32'h00B00713; + mem['h0157] <= 32'h00E7A023; + mem['h0158] <= 32'hFEF44703; + mem['h0159] <= 32'hFED44783; + mem['h015A] <= 32'h00F71E63; + mem['h015B] <= 32'hFEE44703; + mem['h015C] <= 32'h01D00793; + mem['h015D] <= 32'h00E7F863; + mem['h015E] <= 32'hFEE44703; + mem['h015F] <= 32'h02000793; + mem['h0160] <= 32'h02E7F663; + mem['h0161] <= 32'hFEE44703; + mem['h0162] <= 32'h01F00793; + mem['h0163] <= 32'h04F71A63; + mem['h0164] <= 32'hFEF44703; + mem['h0165] <= 32'hFED44783; + mem['h0166] <= 32'h04F76463; + mem['h0167] <= 32'hFEF44703; + mem['h0168] <= 32'hFED44783; + mem['h0169] <= 32'h00478793; + mem['h016A] <= 32'h02E7CC63; + mem['h016B] <= 32'hFEF44703; + mem['h016C] <= 32'h00070793; + mem['h016D] <= 32'h00279793; + mem['h016E] <= 32'h00E787B3; + mem['h016F] <= 32'h00379793; + mem['h0170] <= 32'h00078713; + mem['h0171] <= 32'hFEE44783; + mem['h0172] <= 32'h00F707B3; + mem['h0173] <= 32'h00279713; + mem['h0174] <= 32'h052007B7; + mem['h0175] <= 32'h00F707B3; + mem['h0176] <= 32'h00B00713; + mem['h0177] <= 32'h00E7A023; + mem['h0178] <= 32'hFEF44703; + mem['h0179] <= 32'hFED44783; + mem['h017A] <= 32'h00F70A63; + mem['h017B] <= 32'hFEF44703; + mem['h017C] <= 32'hFED44783; + mem['h017D] <= 32'h00478793; + mem['h017E] <= 32'h00F71E63; + mem['h017F] <= 32'hFEE44703; + mem['h0180] <= 32'h02100793; + mem['h0181] <= 32'h00E7F863; + mem['h0182] <= 32'hFEE44703; + mem['h0183] <= 32'h02400793; + mem['h0184] <= 32'h04E7F463; + mem['h0185] <= 32'hFEF44703; + mem['h0186] <= 32'hFED44783; + mem['h0187] <= 32'h00278793; + mem['h0188] <= 32'h00F71863; + mem['h0189] <= 32'hFEE44703; + mem['h018A] <= 32'h02300793; + mem['h018B] <= 32'h02F70663; + mem['h018C] <= 32'hFEE44703; + mem['h018D] <= 32'h02200793; + mem['h018E] <= 32'h04F71A63; + mem['h018F] <= 32'hFEF44703; + mem['h0190] <= 32'hFED44783; + mem['h0191] <= 32'h04F76463; + mem['h0192] <= 32'hFEF44703; + mem['h0193] <= 32'hFED44783; + mem['h0194] <= 32'h00478793; + mem['h0195] <= 32'h02E7CC63; + mem['h0196] <= 32'hFEF44703; + mem['h0197] <= 32'h00070793; + mem['h0198] <= 32'h00279793; + mem['h0199] <= 32'h00E787B3; + mem['h019A] <= 32'h00379793; + mem['h019B] <= 32'h00078713; + mem['h019C] <= 32'hFEE44783; + mem['h019D] <= 32'h00F707B3; + mem['h019E] <= 32'h00279713; + mem['h019F] <= 32'h052007B7; + mem['h01A0] <= 32'h00F707B3; + mem['h01A1] <= 32'h00B00713; + mem['h01A2] <= 32'h00E7A023; + mem['h01A3] <= 32'hFEE44783; + mem['h01A4] <= 32'h00178793; + mem['h01A5] <= 32'hFEF40723; + mem['h01A6] <= 32'hFEE44703; + mem['h01A7] <= 32'h02700793; + mem['h01A8] <= 32'hA8E7F4E3; + mem['h01A9] <= 32'hFEF44783; + mem['h01AA] <= 32'h00178793; + mem['h01AB] <= 32'hFEF407A3; + mem['h01AC] <= 32'hFEF44703; + mem['h01AD] <= 32'h01D00793; + mem['h01AE] <= 32'hA6E7F4E3; + mem['h01AF] <= 32'h00000013; + mem['h01B0] <= 32'h00000013; + mem['h01B1] <= 32'h01C12403; + mem['h01B2] <= 32'h02010113; + mem['h01B3] <= 32'h00008067; + mem['h01B4] <= 32'hFE010113; + mem['h01B5] <= 32'h00812E23; + mem['h01B6] <= 32'h02010413; + mem['h01B7] <= 32'h00B00793; + mem['h01B8] <= 32'hFEF406A3; + mem['h01B9] <= 32'h00300793; + mem['h01BA] <= 32'hFEF40623; + mem['h01BB] <= 32'h02400793; + mem['h01BC] <= 32'hFEF405A3; + mem['h01BD] <= 32'h00E00793; + mem['h01BE] <= 32'hFEF40523; + mem['h01BF] <= 32'hFE0407A3; + mem['h01C0] <= 32'h2010006F; + mem['h01C1] <= 32'hFE040723; + mem['h01C2] <= 32'h1E10006F; + mem['h01C3] <= 32'hFEF44703; + mem['h01C4] <= 32'hFED44783; + mem['h01C5] <= 32'h04F71863; + mem['h01C6] <= 32'hFEE44703; + mem['h01C7] <= 32'hFEC44783; + mem['h01C8] <= 32'h04F76263; + mem['h01C9] <= 32'hFEE44703; + mem['h01CA] <= 32'hFEB44783; + mem['h01CB] <= 32'h02E7EC63; + mem['h01CC] <= 32'hFEF44703; + mem['h01CD] <= 32'h00070793; + mem['h01CE] <= 32'h00279793; + mem['h01CF] <= 32'h00E787B3; + mem['h01D0] <= 32'h00379793; + mem['h01D1] <= 32'h00078713; + mem['h01D2] <= 32'hFEE44783; + mem['h01D3] <= 32'h00F707B3; + mem['h01D4] <= 32'h00279713; + mem['h01D5] <= 32'h052007B7; + mem['h01D6] <= 32'h00F707B3; + mem['h01D7] <= 32'h00A00713; + mem['h01D8] <= 32'h00E7A023; + mem['h01D9] <= 32'hFEE44703; + mem['h01DA] <= 32'h00400793; + mem['h01DB] <= 32'h04F71A63; + mem['h01DC] <= 32'hFEF44703; + mem['h01DD] <= 32'hFEA44783; + mem['h01DE] <= 32'h04F76463; + mem['h01DF] <= 32'hFEF44703; + mem['h01E0] <= 32'hFEA44783; + mem['h01E1] <= 32'h00478793; + mem['h01E2] <= 32'h02E7CC63; + mem['h01E3] <= 32'hFEF44703; + mem['h01E4] <= 32'h00070793; + mem['h01E5] <= 32'h00279793; + mem['h01E6] <= 32'h00E787B3; + mem['h01E7] <= 32'h00379793; + mem['h01E8] <= 32'h00078713; + mem['h01E9] <= 32'hFEE44783; + mem['h01EA] <= 32'h00F707B3; + mem['h01EB] <= 32'h00279713; + mem['h01EC] <= 32'h052007B7; + mem['h01ED] <= 32'h00F707B3; + mem['h01EE] <= 32'h00700713; + mem['h01EF] <= 32'h00E7A023; + mem['h01F0] <= 32'hFEF44703; + mem['h01F1] <= 32'hFEA44783; + mem['h01F2] <= 32'h04F71863; + mem['h01F3] <= 32'hFEE44703; + mem['h01F4] <= 32'h00500793; + mem['h01F5] <= 32'h00F70863; + mem['h01F6] <= 32'hFEE44703; + mem['h01F7] <= 32'h00600793; + mem['h01F8] <= 32'h02F71C63; + mem['h01F9] <= 32'hFEF44703; + mem['h01FA] <= 32'h00070793; + mem['h01FB] <= 32'h00279793; + mem['h01FC] <= 32'h00E787B3; + mem['h01FD] <= 32'h00379793; + mem['h01FE] <= 32'h00078713; + mem['h01FF] <= 32'hFEE44783; + mem['h0200] <= 32'h00F707B3; + mem['h0201] <= 32'h00279713; + mem['h0202] <= 32'h052007B7; + mem['h0203] <= 32'h00F707B3; + mem['h0204] <= 32'h00700713; + mem['h0205] <= 32'h00E7A023; + mem['h0206] <= 32'hFEF44703; + mem['h0207] <= 32'hFEA44783; + mem['h0208] <= 32'h00478793; + mem['h0209] <= 32'h04F71863; + mem['h020A] <= 32'hFEE44703; + mem['h020B] <= 32'h00500793; + mem['h020C] <= 32'h00F70863; + mem['h020D] <= 32'hFEE44703; + mem['h020E] <= 32'h00600793; + mem['h020F] <= 32'h02F71C63; + mem['h0210] <= 32'hFEF44703; + mem['h0211] <= 32'h00070793; + mem['h0212] <= 32'h00279793; + mem['h0213] <= 32'h00E787B3; + mem['h0214] <= 32'h00379793; + mem['h0215] <= 32'h00078713; + mem['h0216] <= 32'hFEE44783; + mem['h0217] <= 32'h00F707B3; + mem['h0218] <= 32'h00279713; + mem['h0219] <= 32'h052007B7; + mem['h021A] <= 32'h00F707B3; + mem['h021B] <= 32'h00700713; + mem['h021C] <= 32'h00E7A023; + mem['h021D] <= 32'hFEE44703; + mem['h021E] <= 32'h00800793; + mem['h021F] <= 32'h04F71A63; + mem['h0220] <= 32'hFEF44703; + mem['h0221] <= 32'hFEA44783; + mem['h0222] <= 32'h04F76463; + mem['h0223] <= 32'hFEF44703; + mem['h0224] <= 32'hFEA44783; + mem['h0225] <= 32'h00478793; + mem['h0226] <= 32'h02E7CC63; + mem['h0227] <= 32'hFEF44703; + mem['h0228] <= 32'h00070793; + mem['h0229] <= 32'h00279793; + mem['h022A] <= 32'h00E787B3; + mem['h022B] <= 32'h00379793; + mem['h022C] <= 32'h00078713; + mem['h022D] <= 32'hFEE44783; + mem['h022E] <= 32'h00F707B3; + mem['h022F] <= 32'h00279713; + mem['h0230] <= 32'h052007B7; + mem['h0231] <= 32'h00F707B3; + mem['h0232] <= 32'h00700713; + mem['h0233] <= 32'h00E7A023; + mem['h0234] <= 32'hFEF44703; + mem['h0235] <= 32'hFEA44783; + mem['h0236] <= 32'h00278793; + mem['h0237] <= 32'h04F71863; + mem['h0238] <= 32'hFEE44703; + mem['h0239] <= 32'h00900793; + mem['h023A] <= 32'h00F70863; + mem['h023B] <= 32'hFEE44703; + mem['h023C] <= 32'h00A00793; + mem['h023D] <= 32'h02F71C63; + mem['h023E] <= 32'hFEF44703; + mem['h023F] <= 32'h00070793; + mem['h0240] <= 32'h00279793; + mem['h0241] <= 32'h00E787B3; + mem['h0242] <= 32'h00379793; + mem['h0243] <= 32'h00078713; + mem['h0244] <= 32'hFEE44783; + mem['h0245] <= 32'h00F707B3; + mem['h0246] <= 32'h00279713; + mem['h0247] <= 32'h052007B7; + mem['h0248] <= 32'h00F707B3; + mem['h0249] <= 32'h00700713; + mem['h024A] <= 32'h00E7A023; + mem['h024B] <= 32'hFEE44703; + mem['h024C] <= 32'h00A00793; + mem['h024D] <= 32'h04F71C63; + mem['h024E] <= 32'hFEA44783; + mem['h024F] <= 32'h00178713; + mem['h0250] <= 32'hFEF44783; + mem['h0251] <= 32'h04F75463; + mem['h0252] <= 32'hFEF44703; + mem['h0253] <= 32'hFEA44783; + mem['h0254] <= 32'h00478793; + mem['h0255] <= 32'h02E7CC63; + mem['h0256] <= 32'hFEF44703; + mem['h0257] <= 32'h00070793; + mem['h0258] <= 32'h00279793; + mem['h0259] <= 32'h00E787B3; + mem['h025A] <= 32'h00379793; + mem['h025B] <= 32'h00078713; + mem['h025C] <= 32'hFEE44783; + mem['h025D] <= 32'h00F707B3; + mem['h025E] <= 32'h00279713; + mem['h025F] <= 32'h052007B7; + mem['h0260] <= 32'h00F707B3; + mem['h0261] <= 32'h00700713; + mem['h0262] <= 32'h00E7A023; + mem['h0263] <= 32'hFEE44703; + mem['h0264] <= 32'h00C00793; + mem['h0265] <= 32'h04F71C63; + mem['h0266] <= 32'hFEA44783; + mem['h0267] <= 32'h00178713; + mem['h0268] <= 32'hFEF44783; + mem['h0269] <= 32'h04F75463; + mem['h026A] <= 32'hFEF44703; + mem['h026B] <= 32'hFEA44783; + mem['h026C] <= 32'h00478793; + mem['h026D] <= 32'h02E7CC63; + mem['h026E] <= 32'hFEF44703; + mem['h026F] <= 32'h00070793; + mem['h0270] <= 32'h00279793; + mem['h0271] <= 32'h00E787B3; + mem['h0272] <= 32'h00379793; + mem['h0273] <= 32'h00078713; + mem['h0274] <= 32'hFEE44783; + mem['h0275] <= 32'h00F707B3; + mem['h0276] <= 32'h00279713; + mem['h0277] <= 32'h052007B7; + mem['h0278] <= 32'h00F707B3; + mem['h0279] <= 32'h00700713; + mem['h027A] <= 32'h00E7A023; + mem['h027B] <= 32'hFEE44703; + mem['h027C] <= 32'h00C00793; + mem['h027D] <= 32'h04F71263; + mem['h027E] <= 32'hFEF44703; + mem['h027F] <= 32'hFEA44783; + mem['h0280] <= 32'h02F71C63; + mem['h0281] <= 32'hFEF44703; + mem['h0282] <= 32'h00070793; + mem['h0283] <= 32'h00279793; + mem['h0284] <= 32'h00E787B3; + mem['h0285] <= 32'h00379793; + mem['h0286] <= 32'h00078713; + mem['h0287] <= 32'hFEE44783; + mem['h0288] <= 32'h00F707B3; + mem['h0289] <= 32'h00279713; + mem['h028A] <= 32'h052007B7; + mem['h028B] <= 32'h00F707B3; + mem['h028C] <= 32'h00700713; + mem['h028D] <= 32'h00E7A023; + mem['h028E] <= 32'hFEE44703; + mem['h028F] <= 32'h00E00793; + mem['h0290] <= 32'h04F71A63; + mem['h0291] <= 32'hFEF44703; + mem['h0292] <= 32'hFEA44783; + mem['h0293] <= 32'h04F76463; + mem['h0294] <= 32'hFEF44703; + mem['h0295] <= 32'hFEA44783; + mem['h0296] <= 32'h00478793; + mem['h0297] <= 32'h02E7CC63; + mem['h0298] <= 32'hFEF44703; + mem['h0299] <= 32'h00070793; + mem['h029A] <= 32'h00279793; + mem['h029B] <= 32'h00E787B3; + mem['h029C] <= 32'h00379793; + mem['h029D] <= 32'h00078713; + mem['h029E] <= 32'hFEE44783; + mem['h029F] <= 32'h00F707B3; + mem['h02A0] <= 32'h00279713; + mem['h02A1] <= 32'h052007B7; + mem['h02A2] <= 32'h00F707B3; + mem['h02A3] <= 32'h00700713; + mem['h02A4] <= 32'h00E7A023; + mem['h02A5] <= 32'hFEE44703; + mem['h02A6] <= 32'h01000793; + mem['h02A7] <= 32'h04F71C63; + mem['h02A8] <= 32'hFEA44783; + mem['h02A9] <= 32'h00178713; + mem['h02AA] <= 32'hFEF44783; + mem['h02AB] <= 32'h04F75463; + mem['h02AC] <= 32'hFEF44703; + mem['h02AD] <= 32'hFEA44783; + mem['h02AE] <= 32'h00478793; + mem['h02AF] <= 32'h02E7CC63; + mem['h02B0] <= 32'hFEF44703; + mem['h02B1] <= 32'h00070793; + mem['h02B2] <= 32'h00279793; + mem['h02B3] <= 32'h00E787B3; + mem['h02B4] <= 32'h00379793; + mem['h02B5] <= 32'h00078713; + mem['h02B6] <= 32'hFEE44783; + mem['h02B7] <= 32'h00F707B3; + mem['h02B8] <= 32'h00279713; + mem['h02B9] <= 32'h052007B7; + mem['h02BA] <= 32'h00F707B3; + mem['h02BB] <= 32'h00700713; + mem['h02BC] <= 32'h00E7A023; + mem['h02BD] <= 32'hFEE44703; + mem['h02BE] <= 32'h01000793; + mem['h02BF] <= 32'h04F71263; + mem['h02C0] <= 32'hFEF44703; + mem['h02C1] <= 32'hFEA44783; + mem['h02C2] <= 32'h02F71C63; + mem['h02C3] <= 32'hFEF44703; + mem['h02C4] <= 32'h00070793; + mem['h02C5] <= 32'h00279793; + mem['h02C6] <= 32'h00E787B3; + mem['h02C7] <= 32'h00379793; + mem['h02C8] <= 32'h00078713; + mem['h02C9] <= 32'hFEE44783; + mem['h02CA] <= 32'h00F707B3; + mem['h02CB] <= 32'h00279713; + mem['h02CC] <= 32'h052007B7; + mem['h02CD] <= 32'h00F707B3; + mem['h02CE] <= 32'h00700713; + mem['h02CF] <= 32'h00E7A023; + mem['h02D0] <= 32'hFEE44703; + mem['h02D1] <= 32'h01300793; + mem['h02D2] <= 32'h04F71A63; + mem['h02D3] <= 32'hFEF44703; + mem['h02D4] <= 32'hFEA44783; + mem['h02D5] <= 32'h04F76463; + mem['h02D6] <= 32'hFEF44703; + mem['h02D7] <= 32'hFEA44783; + mem['h02D8] <= 32'h00478793; + mem['h02D9] <= 32'h02E7CC63; + mem['h02DA] <= 32'hFEF44703; + mem['h02DB] <= 32'h00070793; + mem['h02DC] <= 32'h00279793; + mem['h02DD] <= 32'h00E787B3; + mem['h02DE] <= 32'h00379793; + mem['h02DF] <= 32'h00078713; + mem['h02E0] <= 32'hFEE44783; + mem['h02E1] <= 32'h00F707B3; + mem['h02E2] <= 32'h00279713; + mem['h02E3] <= 32'h052007B7; + mem['h02E4] <= 32'h00F707B3; + mem['h02E5] <= 32'h00200713; + mem['h02E6] <= 32'h00E7A023; + mem['h02E7] <= 32'hFEF44703; + mem['h02E8] <= 32'hFEA44783; + mem['h02E9] <= 32'h04F71863; + mem['h02EA] <= 32'hFEE44703; + mem['h02EB] <= 32'h01400793; + mem['h02EC] <= 32'h00F70863; + mem['h02ED] <= 32'hFEE44703; + mem['h02EE] <= 32'h01500793; + mem['h02EF] <= 32'h02F71C63; + mem['h02F0] <= 32'hFEF44703; + mem['h02F1] <= 32'h00070793; + mem['h02F2] <= 32'h00279793; + mem['h02F3] <= 32'h00E787B3; + mem['h02F4] <= 32'h00379793; + mem['h02F5] <= 32'h00078713; + mem['h02F6] <= 32'hFEE44783; + mem['h02F7] <= 32'h00F707B3; + mem['h02F8] <= 32'h00279713; + mem['h02F9] <= 32'h052007B7; + mem['h02FA] <= 32'h00F707B3; + mem['h02FB] <= 32'h00200713; + mem['h02FC] <= 32'h00E7A023; + mem['h02FD] <= 32'hFEF44703; + mem['h02FE] <= 32'hFEA44783; + mem['h02FF] <= 32'h00478793; + mem['h0300] <= 32'h04F71863; + mem['h0301] <= 32'hFEE44703; + mem['h0302] <= 32'h01400793; + mem['h0303] <= 32'h00F70863; + mem['h0304] <= 32'hFEE44703; + mem['h0305] <= 32'h01500793; + mem['h0306] <= 32'h02F71C63; + mem['h0307] <= 32'hFEF44703; + mem['h0308] <= 32'h00070793; + mem['h0309] <= 32'h00279793; + mem['h030A] <= 32'h00E787B3; + mem['h030B] <= 32'h00379793; + mem['h030C] <= 32'h00078713; + mem['h030D] <= 32'hFEE44783; + mem['h030E] <= 32'h00F707B3; + mem['h030F] <= 32'h00279713; + mem['h0310] <= 32'h052007B7; + mem['h0311] <= 32'h00F707B3; + mem['h0312] <= 32'h00200713; + mem['h0313] <= 32'h00E7A023; + mem['h0314] <= 32'hFEE44703; + mem['h0315] <= 32'h01700793; + mem['h0316] <= 32'h04F71A63; + mem['h0317] <= 32'hFEF44703; + mem['h0318] <= 32'hFEA44783; + mem['h0319] <= 32'h04F76463; + mem['h031A] <= 32'hFEF44703; + mem['h031B] <= 32'hFEA44783; + mem['h031C] <= 32'h00478793; + mem['h031D] <= 32'h02E7CC63; + mem['h031E] <= 32'hFEF44703; + mem['h031F] <= 32'h00070793; + mem['h0320] <= 32'h00279793; + mem['h0321] <= 32'h00E787B3; + mem['h0322] <= 32'h00379793; + mem['h0323] <= 32'h00078713; + mem['h0324] <= 32'hFEE44783; + mem['h0325] <= 32'h00F707B3; + mem['h0326] <= 32'h00279713; + mem['h0327] <= 32'h052007B7; + mem['h0328] <= 32'h00F707B3; + mem['h0329] <= 32'h00200713; + mem['h032A] <= 32'h00E7A023; + mem['h032B] <= 32'hFEF44703; + mem['h032C] <= 32'hFEA44783; + mem['h032D] <= 32'h00278793; + mem['h032E] <= 32'h04F71863; + mem['h032F] <= 32'hFEE44703; + mem['h0330] <= 32'h01800793; + mem['h0331] <= 32'h00F70863; + mem['h0332] <= 32'hFEE44703; + mem['h0333] <= 32'h01900793; + mem['h0334] <= 32'h02F71C63; + mem['h0335] <= 32'hFEF44703; + mem['h0336] <= 32'h00070793; + mem['h0337] <= 32'h00279793; + mem['h0338] <= 32'h00E787B3; + mem['h0339] <= 32'h00379793; + mem['h033A] <= 32'h00078713; + mem['h033B] <= 32'hFEE44783; + mem['h033C] <= 32'h00F707B3; + mem['h033D] <= 32'h00279713; + mem['h033E] <= 32'h052007B7; + mem['h033F] <= 32'h00F707B3; + mem['h0340] <= 32'h00200713; + mem['h0341] <= 32'h00E7A023; + mem['h0342] <= 32'hFEE44703; + mem['h0343] <= 32'h01900793; + mem['h0344] <= 32'h04F71A63; + mem['h0345] <= 32'hFEF44703; + mem['h0346] <= 32'hFEA44783; + mem['h0347] <= 32'h04F76463; + mem['h0348] <= 32'hFEF44703; + mem['h0349] <= 32'hFEA44783; + mem['h034A] <= 32'h00478793; + mem['h034B] <= 32'h02E7CC63; + mem['h034C] <= 32'hFEF44703; + mem['h034D] <= 32'h00070793; + mem['h034E] <= 32'h00279793; + mem['h034F] <= 32'h00E787B3; + mem['h0350] <= 32'h00379793; + mem['h0351] <= 32'h00078713; + mem['h0352] <= 32'hFEE44783; + mem['h0353] <= 32'h00F707B3; + mem['h0354] <= 32'h00279713; + mem['h0355] <= 32'h052007B7; + mem['h0356] <= 32'h00F707B3; + mem['h0357] <= 32'h00200713; + mem['h0358] <= 32'h00E7A023; + mem['h0359] <= 32'hFEE44703; + mem['h035A] <= 32'h01B00793; + mem['h035B] <= 32'h04F71A63; + mem['h035C] <= 32'hFEF44703; + mem['h035D] <= 32'hFEA44783; + mem['h035E] <= 32'h04F76463; + mem['h035F] <= 32'hFEF44703; + mem['h0360] <= 32'hFEA44783; + mem['h0361] <= 32'h00478793; + mem['h0362] <= 32'h02E7CC63; + mem['h0363] <= 32'hFEF44703; + mem['h0364] <= 32'h00070793; + mem['h0365] <= 32'h00279793; + mem['h0366] <= 32'h00E787B3; + mem['h0367] <= 32'h00379793; + mem['h0368] <= 32'h00078713; + mem['h0369] <= 32'hFEE44783; + mem['h036A] <= 32'h00F707B3; + mem['h036B] <= 32'h00279713; + mem['h036C] <= 32'h052007B7; + mem['h036D] <= 32'h00F707B3; + mem['h036E] <= 32'h00200713; + mem['h036F] <= 32'h00E7A023; + mem['h0370] <= 32'hFEE44703; + mem['h0371] <= 32'h01D00793; + mem['h0372] <= 32'h04F71A63; + mem['h0373] <= 32'hFEF44703; + mem['h0374] <= 32'hFEA44783; + mem['h0375] <= 32'h04F76463; + mem['h0376] <= 32'hFEF44703; + mem['h0377] <= 32'hFEA44783; + mem['h0378] <= 32'h00478793; + mem['h0379] <= 32'h02E7CC63; + mem['h037A] <= 32'hFEF44703; + mem['h037B] <= 32'h00070793; + mem['h037C] <= 32'h00279793; + mem['h037D] <= 32'h00E787B3; + mem['h037E] <= 32'h00379793; + mem['h037F] <= 32'h00078713; + mem['h0380] <= 32'hFEE44783; + mem['h0381] <= 32'h00F707B3; + mem['h0382] <= 32'h00279713; + mem['h0383] <= 32'h052007B7; + mem['h0384] <= 32'h00F707B3; + mem['h0385] <= 32'h00200713; + mem['h0386] <= 32'h00E7A023; + mem['h0387] <= 32'hFEF44703; + mem['h0388] <= 32'hFEA44783; + mem['h0389] <= 32'h04F71863; + mem['h038A] <= 32'hFEE44703; + mem['h038B] <= 32'h01E00793; + mem['h038C] <= 32'h00F70863; + mem['h038D] <= 32'hFEE44703; + mem['h038E] <= 32'h01F00793; + mem['h038F] <= 32'h02F71C63; + mem['h0390] <= 32'hFEF44703; + mem['h0391] <= 32'h00070793; + mem['h0392] <= 32'h00279793; + mem['h0393] <= 32'h00E787B3; + mem['h0394] <= 32'h00379793; + mem['h0395] <= 32'h00078713; + mem['h0396] <= 32'hFEE44783; + mem['h0397] <= 32'h00F707B3; + mem['h0398] <= 32'h00279713; + mem['h0399] <= 32'h052007B7; + mem['h039A] <= 32'h00F707B3; + mem['h039B] <= 32'h00200713; + mem['h039C] <= 32'h00E7A023; + mem['h039D] <= 32'hFEF44703; + mem['h039E] <= 32'hFEA44783; + mem['h039F] <= 32'h00278793; + mem['h03A0] <= 32'h04F71863; + mem['h03A1] <= 32'hFEE44703; + mem['h03A2] <= 32'h01E00793; + mem['h03A3] <= 32'h00F70863; + mem['h03A4] <= 32'hFEE44703; + mem['h03A5] <= 32'h01F00793; + mem['h03A6] <= 32'h02F71C63; + mem['h03A7] <= 32'hFEF44703; + mem['h03A8] <= 32'h00070793; + mem['h03A9] <= 32'h00279793; + mem['h03AA] <= 32'h00E787B3; + mem['h03AB] <= 32'h00379793; + mem['h03AC] <= 32'h00078713; + mem['h03AD] <= 32'hFEE44783; + mem['h03AE] <= 32'h00F707B3; + mem['h03AF] <= 32'h00279713; + mem['h03B0] <= 32'h052007B7; + mem['h03B1] <= 32'h00F707B3; + mem['h03B2] <= 32'h00200713; + mem['h03B3] <= 32'h00E7A023; + mem['h03B4] <= 32'hFEE44703; + mem['h03B5] <= 32'h01F00793; + mem['h03B6] <= 32'h04F71A63; + mem['h03B7] <= 32'hFEF44703; + mem['h03B8] <= 32'hFEA44783; + mem['h03B9] <= 32'h04F76463; + mem['h03BA] <= 32'hFEF44703; + mem['h03BB] <= 32'hFEA44783; + mem['h03BC] <= 32'h00278793; + mem['h03BD] <= 32'h02E7CC63; + mem['h03BE] <= 32'hFEF44703; + mem['h03BF] <= 32'h00070793; + mem['h03C0] <= 32'h00279793; + mem['h03C1] <= 32'h00E787B3; + mem['h03C2] <= 32'h00379793; + mem['h03C3] <= 32'h00078713; + mem['h03C4] <= 32'hFEE44783; + mem['h03C5] <= 32'h00F707B3; + mem['h03C6] <= 32'h00279713; + mem['h03C7] <= 32'h052007B7; + mem['h03C8] <= 32'h00F707B3; + mem['h03C9] <= 32'h00200713; + mem['h03CA] <= 32'h00E7A023; + mem['h03CB] <= 32'hFEF44703; + mem['h03CC] <= 32'hFEA44783; + mem['h03CD] <= 32'h04F71863; + mem['h03CE] <= 32'hFEE44703; + mem['h03CF] <= 32'h02000793; + mem['h03D0] <= 32'h04E7F263; + mem['h03D1] <= 32'hFEE44703; + mem['h03D2] <= 32'h02300793; + mem['h03D3] <= 32'h02E7EC63; + mem['h03D4] <= 32'hFEF44703; + mem['h03D5] <= 32'h00070793; + mem['h03D6] <= 32'h00279793; + mem['h03D7] <= 32'h00E787B3; + mem['h03D8] <= 32'h00379793; + mem['h03D9] <= 32'h00078713; + mem['h03DA] <= 32'hFEE44783; + mem['h03DB] <= 32'h00F707B3; + mem['h03DC] <= 32'h00279713; + mem['h03DD] <= 32'h052007B7; + mem['h03DE] <= 32'h00F707B3; + mem['h03DF] <= 32'h00200713; + mem['h03E0] <= 32'h00E7A023; + mem['h03E1] <= 32'hFEF44703; + mem['h03E2] <= 32'hFEA44783; + mem['h03E3] <= 32'h00278793; + mem['h03E4] <= 32'h04F71863; + mem['h03E5] <= 32'hFEE44703; + mem['h03E6] <= 32'h02000793; + mem['h03E7] <= 32'h04E7F263; + mem['h03E8] <= 32'hFEE44703; + mem['h03E9] <= 32'h02300793; + mem['h03EA] <= 32'h02E7EC63; + mem['h03EB] <= 32'hFEF44703; + mem['h03EC] <= 32'h00070793; + mem['h03ED] <= 32'h00279793; + mem['h03EE] <= 32'h00E787B3; + mem['h03EF] <= 32'h00379793; + mem['h03F0] <= 32'h00078713; + mem['h03F1] <= 32'hFEE44783; + mem['h03F2] <= 32'h00F707B3; + mem['h03F3] <= 32'h00279713; + mem['h03F4] <= 32'h052007B7; + mem['h03F5] <= 32'h00F707B3; + mem['h03F6] <= 32'h00200713; + mem['h03F7] <= 32'h00E7A023; + mem['h03F8] <= 32'hFEF44703; + mem['h03F9] <= 32'hFEA44783; + mem['h03FA] <= 32'h00478793; + mem['h03FB] <= 32'h04F71863; + mem['h03FC] <= 32'hFEE44703; + mem['h03FD] <= 32'h02000793; + mem['h03FE] <= 32'h04E7F263; + mem['h03FF] <= 32'hFEE44703; + mem['h0400] <= 32'h02300793; + mem['h0401] <= 32'h02E7EC63; + mem['h0402] <= 32'hFEF44703; + mem['h0403] <= 32'h00070793; + mem['h0404] <= 32'h00279793; + mem['h0405] <= 32'h00E787B3; + mem['h0406] <= 32'h00379793; + mem['h0407] <= 32'h00078713; + mem['h0408] <= 32'hFEE44783; + mem['h0409] <= 32'h00F707B3; + mem['h040A] <= 32'h00279713; + mem['h040B] <= 32'h052007B7; + mem['h040C] <= 32'h00F707B3; + mem['h040D] <= 32'h00200713; + mem['h040E] <= 32'h00E7A023; + mem['h040F] <= 32'hFEE44703; + mem['h0410] <= 32'h02100793; + mem['h0411] <= 32'h04F71463; + mem['h0412] <= 32'hFEF44703; + mem['h0413] <= 32'hFEA44783; + mem['h0414] <= 32'h00178793; + mem['h0415] <= 32'h02F71C63; + mem['h0416] <= 32'hFEF44703; + mem['h0417] <= 32'h00070793; + mem['h0418] <= 32'h00279793; + mem['h0419] <= 32'h00E787B3; + mem['h041A] <= 32'h00379793; + mem['h041B] <= 32'h00078713; + mem['h041C] <= 32'hFEE44783; + mem['h041D] <= 32'h00F707B3; + mem['h041E] <= 32'h00279713; + mem['h041F] <= 32'h052007B7; + mem['h0420] <= 32'h00F707B3; + mem['h0421] <= 32'h00200713; + mem['h0422] <= 32'h00E7A023; + mem['h0423] <= 32'hFEE44703; + mem['h0424] <= 32'h02300793; + mem['h0425] <= 32'h04F71463; + mem['h0426] <= 32'hFEF44703; + mem['h0427] <= 32'hFEA44783; + mem['h0428] <= 32'h00378793; + mem['h0429] <= 32'h02F71C63; + mem['h042A] <= 32'hFEF44703; + mem['h042B] <= 32'h00070793; + mem['h042C] <= 32'h00279793; + mem['h042D] <= 32'h00E787B3; + mem['h042E] <= 32'h00379793; + mem['h042F] <= 32'h00078713; + mem['h0430] <= 32'hFEE44783; + mem['h0431] <= 32'h00F707B3; + mem['h0432] <= 32'h00279713; + mem['h0433] <= 32'h052007B7; + mem['h0434] <= 32'h00F707B3; + mem['h0435] <= 32'h00200713; + mem['h0436] <= 32'h00E7A023; + mem['h0437] <= 32'hFEE44783; + mem['h0438] <= 32'h00178793; + mem['h0439] <= 32'hFEF40723; + mem['h043A] <= 32'hFEE44703; + mem['h043B] <= 32'h02700793; + mem['h043C] <= 32'hE0E7FE63; + mem['h043D] <= 32'hFEF44783; + mem['h043E] <= 32'h00178793; + mem['h043F] <= 32'hFEF407A3; + mem['h0440] <= 32'hFEF44703; + mem['h0441] <= 32'h01D00793; + mem['h0442] <= 32'hDEE7FE63; + mem['h0443] <= 32'h00000013; + mem['h0444] <= 32'h00000013; + mem['h0445] <= 32'h01C12403; + mem['h0446] <= 32'h02010113; + mem['h0447] <= 32'h00008067; + mem['h0448] <= 32'hFE010113; + mem['h0449] <= 32'h00812E23; + mem['h044A] <= 32'h02010413; + mem['h044B] <= 32'h01600793; + mem['h044C] <= 32'hFEF406A3; + mem['h044D] <= 32'hFE0407A3; + mem['h044E] <= 32'h1F50006F; + mem['h044F] <= 32'hFE040723; + mem['h0450] <= 32'h1D50006F; + mem['h0451] <= 32'hFEF44703; + mem['h0452] <= 32'hFED44783; + mem['h0453] <= 32'h00F71E63; + mem['h0454] <= 32'hFEE44703; + mem['h0455] <= 32'h00100793; + mem['h0456] <= 32'h00E7F863; + mem['h0457] <= 32'hFEE44703; + mem['h0458] <= 32'h00400793; + mem['h0459] <= 32'h02E7F663; + mem['h045A] <= 32'hFEE44703; + mem['h045B] <= 32'h00300793; + mem['h045C] <= 32'h04F71A63; + mem['h045D] <= 32'hFEF44703; + mem['h045E] <= 32'hFED44783; + mem['h045F] <= 32'h04F76463; + mem['h0460] <= 32'hFEF44703; + mem['h0461] <= 32'hFED44783; + mem['h0462] <= 32'h00478793; + mem['h0463] <= 32'h02E7CC63; + mem['h0464] <= 32'hFEF44703; + mem['h0465] <= 32'h00070793; + mem['h0466] <= 32'h00279793; + mem['h0467] <= 32'h00E787B3; + mem['h0468] <= 32'h00379793; + mem['h0469] <= 32'h00078713; + mem['h046A] <= 32'hFEE44783; + mem['h046B] <= 32'h00F707B3; + mem['h046C] <= 32'h00279713; + mem['h046D] <= 32'h052007B7; + mem['h046E] <= 32'h00F707B3; + mem['h046F] <= 32'h00200713; + mem['h0470] <= 32'h00E7A023; + mem['h0471] <= 32'hFEF44703; + mem['h0472] <= 32'hFED44783; + mem['h0473] <= 32'h00F70A63; + mem['h0474] <= 32'hFEF44703; + mem['h0475] <= 32'hFED44783; + mem['h0476] <= 32'h00478793; + mem['h0477] <= 32'h00F71E63; + mem['h0478] <= 32'hFEE44703; + mem['h0479] <= 32'h00500793; + mem['h047A] <= 32'h00E7F863; + mem['h047B] <= 32'hFEE44703; + mem['h047C] <= 32'h00800793; + mem['h047D] <= 32'h04E7F463; + mem['h047E] <= 32'hFEF44703; + mem['h047F] <= 32'hFED44783; + mem['h0480] <= 32'h00278793; + mem['h0481] <= 32'h00F71863; + mem['h0482] <= 32'hFEE44703; + mem['h0483] <= 32'h00700793; + mem['h0484] <= 32'h02F70663; + mem['h0485] <= 32'hFEE44703; + mem['h0486] <= 32'h00600793; + mem['h0487] <= 32'h04F71A63; + mem['h0488] <= 32'hFEF44703; + mem['h0489] <= 32'hFED44783; + mem['h048A] <= 32'h04F76463; + mem['h048B] <= 32'hFEF44703; + mem['h048C] <= 32'hFED44783; + mem['h048D] <= 32'h00478793; + mem['h048E] <= 32'h02E7CC63; + mem['h048F] <= 32'hFEF44703; + mem['h0490] <= 32'h00070793; + mem['h0491] <= 32'h00279793; + mem['h0492] <= 32'h00E787B3; + mem['h0493] <= 32'h00379793; + mem['h0494] <= 32'h00078713; + mem['h0495] <= 32'hFEE44783; + mem['h0496] <= 32'h00F707B3; + mem['h0497] <= 32'h00279713; + mem['h0498] <= 32'h052007B7; + mem['h0499] <= 32'h00F707B3; + mem['h049A] <= 32'h00200713; + mem['h049B] <= 32'h00E7A023; + mem['h049C] <= 32'hFEF44703; + mem['h049D] <= 32'hFED44783; + mem['h049E] <= 32'h04F71863; + mem['h049F] <= 32'hFEE44703; + mem['h04A0] <= 32'h00900793; + mem['h04A1] <= 32'h04E7F263; + mem['h04A2] <= 32'hFEE44703; + mem['h04A3] <= 32'h00C00793; + mem['h04A4] <= 32'h02E7EC63; + mem['h04A5] <= 32'hFEF44703; + mem['h04A6] <= 32'h00070793; + mem['h04A7] <= 32'h00279793; + mem['h04A8] <= 32'h00E787B3; + mem['h04A9] <= 32'h00379793; + mem['h04AA] <= 32'h00078713; + mem['h04AB] <= 32'hFEE44783; + mem['h04AC] <= 32'h00F707B3; + mem['h04AD] <= 32'h00279713; + mem['h04AE] <= 32'h052007B7; + mem['h04AF] <= 32'h00F707B3; + mem['h04B0] <= 32'h00200713; + mem['h04B1] <= 32'h00E7A023; + mem['h04B2] <= 32'hFEE44703; + mem['h04B3] <= 32'h00B00793; + mem['h04B4] <= 32'h04F71A63; + mem['h04B5] <= 32'hFEF44703; + mem['h04B6] <= 32'hFED44783; + mem['h04B7] <= 32'h04F76463; + mem['h04B8] <= 32'hFEF44703; + mem['h04B9] <= 32'hFED44783; + mem['h04BA] <= 32'h00478793; + mem['h04BB] <= 32'h02E7CC63; + mem['h04BC] <= 32'hFEF44703; + mem['h04BD] <= 32'h00070793; + mem['h04BE] <= 32'h00279793; + mem['h04BF] <= 32'h00E787B3; + mem['h04C0] <= 32'h00379793; + mem['h04C1] <= 32'h00078713; + mem['h04C2] <= 32'hFEE44783; + mem['h04C3] <= 32'h00F707B3; + mem['h04C4] <= 32'h00279713; + mem['h04C5] <= 32'h052007B7; + mem['h04C6] <= 32'h00F707B3; + mem['h04C7] <= 32'h00200713; + mem['h04C8] <= 32'h00E7A023; + mem['h04C9] <= 32'hFEE44703; + mem['h04CA] <= 32'h00E00793; + mem['h04CB] <= 32'h04F71A63; + mem['h04CC] <= 32'hFEF44703; + mem['h04CD] <= 32'hFED44783; + mem['h04CE] <= 32'h04F76463; + mem['h04CF] <= 32'hFEF44703; + mem['h04D0] <= 32'hFED44783; + mem['h04D1] <= 32'h00478793; + mem['h04D2] <= 32'h02E7CC63; + mem['h04D3] <= 32'hFEF44703; + mem['h04D4] <= 32'h00070793; + mem['h04D5] <= 32'h00279793; + mem['h04D6] <= 32'h00E787B3; + mem['h04D7] <= 32'h00379793; + mem['h04D8] <= 32'h00078713; + mem['h04D9] <= 32'hFEE44783; + mem['h04DA] <= 32'h00F707B3; + mem['h04DB] <= 32'h00279713; + mem['h04DC] <= 32'h052007B7; + mem['h04DD] <= 32'h00F707B3; + mem['h04DE] <= 32'h00200713; + mem['h04DF] <= 32'h00E7A023; + mem['h04E0] <= 32'hFEE44703; + mem['h04E1] <= 32'h00F00793; + mem['h04E2] <= 32'h04F71263; + mem['h04E3] <= 32'hFEF44703; + mem['h04E4] <= 32'hFED44783; + mem['h04E5] <= 32'h02F71C63; + mem['h04E6] <= 32'hFEF44703; + mem['h04E7] <= 32'h00070793; + mem['h04E8] <= 32'h00279793; + mem['h04E9] <= 32'h00E787B3; + mem['h04EA] <= 32'h00379793; + mem['h04EB] <= 32'h00078713; + mem['h04EC] <= 32'hFEE44783; + mem['h04ED] <= 32'h00F707B3; + mem['h04EE] <= 32'h00279713; + mem['h04EF] <= 32'h052007B7; + mem['h04F0] <= 32'h00F707B3; + mem['h04F1] <= 32'h00200713; + mem['h04F2] <= 32'h00E7A023; + mem['h04F3] <= 32'hFEE44703; + mem['h04F4] <= 32'h01000793; + mem['h04F5] <= 32'h04F71463; + mem['h04F6] <= 32'hFEF44703; + mem['h04F7] <= 32'hFED44783; + mem['h04F8] <= 32'h00178793; + mem['h04F9] <= 32'h02F71C63; + mem['h04FA] <= 32'hFEF44703; + mem['h04FB] <= 32'h00070793; + mem['h04FC] <= 32'h00279793; + mem['h04FD] <= 32'h00E787B3; + mem['h04FE] <= 32'h00379793; + mem['h04FF] <= 32'h00078713; + mem['h0500] <= 32'hFEE44783; + mem['h0501] <= 32'h00F707B3; + mem['h0502] <= 32'h00279713; + mem['h0503] <= 32'h052007B7; + mem['h0504] <= 32'h00F707B3; + mem['h0505] <= 32'h00200713; + mem['h0506] <= 32'h00E7A023; + mem['h0507] <= 32'hFEE44703; + mem['h0508] <= 32'h00F00793; + mem['h0509] <= 32'h04F71463; + mem['h050A] <= 32'hFEF44703; + mem['h050B] <= 32'hFED44783; + mem['h050C] <= 32'h00278793; + mem['h050D] <= 32'h02F71C63; + mem['h050E] <= 32'hFEF44703; + mem['h050F] <= 32'h00070793; + mem['h0510] <= 32'h00279793; + mem['h0511] <= 32'h00E787B3; + mem['h0512] <= 32'h00379793; + mem['h0513] <= 32'h00078713; + mem['h0514] <= 32'hFEE44783; + mem['h0515] <= 32'h00F707B3; + mem['h0516] <= 32'h00279713; + mem['h0517] <= 32'h052007B7; + mem['h0518] <= 32'h00F707B3; + mem['h0519] <= 32'h00200713; + mem['h051A] <= 32'h00E7A023; + mem['h051B] <= 32'hFEE44703; + mem['h051C] <= 32'h01000793; + mem['h051D] <= 32'h04F71C63; + mem['h051E] <= 32'hFEF44703; + mem['h051F] <= 32'hFED44783; + mem['h0520] <= 32'h00378793; + mem['h0521] <= 32'h00F70A63; + mem['h0522] <= 32'hFEF44703; + mem['h0523] <= 32'hFED44783; + mem['h0524] <= 32'h00478793; + mem['h0525] <= 32'h02F71C63; + mem['h0526] <= 32'hFEF44703; + mem['h0527] <= 32'h00070793; + mem['h0528] <= 32'h00279793; + mem['h0529] <= 32'h00E787B3; + mem['h052A] <= 32'h00379793; + mem['h052B] <= 32'h00078713; + mem['h052C] <= 32'hFEE44783; + mem['h052D] <= 32'h00F707B3; + mem['h052E] <= 32'h00279713; + mem['h052F] <= 32'h052007B7; + mem['h0530] <= 32'h00F707B3; + mem['h0531] <= 32'h00200713; + mem['h0532] <= 32'h00E7A023; + mem['h0533] <= 32'hFEE44703; + mem['h0534] <= 32'h01200793; + mem['h0535] <= 32'h04F71A63; + mem['h0536] <= 32'hFEF44703; + mem['h0537] <= 32'hFED44783; + mem['h0538] <= 32'h04F76463; + mem['h0539] <= 32'hFEF44703; + mem['h053A] <= 32'hFED44783; + mem['h053B] <= 32'h00478793; + mem['h053C] <= 32'h02E7CC63; + mem['h053D] <= 32'hFEF44703; + mem['h053E] <= 32'h00070793; + mem['h053F] <= 32'h00279793; + mem['h0540] <= 32'h00E787B3; + mem['h0541] <= 32'h00379793; + mem['h0542] <= 32'h00078713; + mem['h0543] <= 32'hFEE44783; + mem['h0544] <= 32'h00F707B3; + mem['h0545] <= 32'h00279713; + mem['h0546] <= 32'h052007B7; + mem['h0547] <= 32'h00F707B3; + mem['h0548] <= 32'h00200713; + mem['h0549] <= 32'h00E7A023; + mem['h054A] <= 32'hFEF44703; + mem['h054B] <= 32'hFED44783; + mem['h054C] <= 32'h04F71863; + mem['h054D] <= 32'hFEE44703; + mem['h054E] <= 32'h01400793; + mem['h054F] <= 32'h00F70863; + mem['h0550] <= 32'hFEE44703; + mem['h0551] <= 32'h01500793; + mem['h0552] <= 32'h02F71C63; + mem['h0553] <= 32'hFEF44703; + mem['h0554] <= 32'h00070793; + mem['h0555] <= 32'h00279793; + mem['h0556] <= 32'h00E787B3; + mem['h0557] <= 32'h00379793; + mem['h0558] <= 32'h00078713; + mem['h0559] <= 32'hFEE44783; + mem['h055A] <= 32'h00F707B3; + mem['h055B] <= 32'h00279713; + mem['h055C] <= 32'h052007B7; + mem['h055D] <= 32'h00F707B3; + mem['h055E] <= 32'h00700713; + mem['h055F] <= 32'h00E7A023; + mem['h0560] <= 32'hFEE44703; + mem['h0561] <= 32'h01400793; + mem['h0562] <= 32'h06F71463; + mem['h0563] <= 32'hFEF44703; + mem['h0564] <= 32'hFED44783; + mem['h0565] <= 32'h00178793; + mem['h0566] <= 32'h02F70263; + mem['h0567] <= 32'hFEF44703; + mem['h0568] <= 32'hFED44783; + mem['h0569] <= 32'h00278793; + mem['h056A] <= 32'h00F70A63; + mem['h056B] <= 32'hFEF44703; + mem['h056C] <= 32'hFED44783; + mem['h056D] <= 32'h00478793; + mem['h056E] <= 32'h02F71C63; + mem['h056F] <= 32'hFEF44703; + mem['h0570] <= 32'h00070793; + mem['h0571] <= 32'h00279793; + mem['h0572] <= 32'h00E787B3; + mem['h0573] <= 32'h00379793; + mem['h0574] <= 32'h00078713; + mem['h0575] <= 32'hFEE44783; + mem['h0576] <= 32'h00F707B3; + mem['h0577] <= 32'h00279713; + mem['h0578] <= 32'h052007B7; + mem['h0579] <= 32'h00F707B3; + mem['h057A] <= 32'h00700713; + mem['h057B] <= 32'h00E7A023; + mem['h057C] <= 32'hFEE44703; + mem['h057D] <= 32'h01500793; + mem['h057E] <= 32'h04F71C63; + mem['h057F] <= 32'hFED44783; + mem['h0580] <= 32'h00178713; + mem['h0581] <= 32'hFEF44783; + mem['h0582] <= 32'h04F75463; + mem['h0583] <= 32'hFEF44703; + mem['h0584] <= 32'hFED44783; + mem['h0585] <= 32'h00478793; + mem['h0586] <= 32'h02E7CC63; + mem['h0587] <= 32'hFEF44703; + mem['h0588] <= 32'h00070793; + mem['h0589] <= 32'h00279793; + mem['h058A] <= 32'h00E787B3; + mem['h058B] <= 32'h00379793; + mem['h058C] <= 32'h00078713; + mem['h058D] <= 32'hFEE44783; + mem['h058E] <= 32'h00F707B3; + mem['h058F] <= 32'h00279713; + mem['h0590] <= 32'h052007B7; + mem['h0591] <= 32'h00F707B3; + mem['h0592] <= 32'h00700713; + mem['h0593] <= 32'h00E7A023; + mem['h0594] <= 32'hFEE44703; + mem['h0595] <= 32'h01700793; + mem['h0596] <= 32'h00F70863; + mem['h0597] <= 32'hFEE44703; + mem['h0598] <= 32'h01900793; + mem['h0599] <= 32'h04F71A63; + mem['h059A] <= 32'hFED44703; + mem['h059B] <= 32'hFEF44783; + mem['h059C] <= 32'h04F77463; + mem['h059D] <= 32'hFEF44703; + mem['h059E] <= 32'hFED44783; + mem['h059F] <= 32'h00478793; + mem['h05A0] <= 32'h02E7CC63; + mem['h05A1] <= 32'hFEF44703; + mem['h05A2] <= 32'h00070793; + mem['h05A3] <= 32'h00279793; + mem['h05A4] <= 32'h00E787B3; + mem['h05A5] <= 32'h00379793; + mem['h05A6] <= 32'h00078713; + mem['h05A7] <= 32'hFEE44783; + mem['h05A8] <= 32'h00F707B3; + mem['h05A9] <= 32'h00279713; + mem['h05AA] <= 32'h052007B7; + mem['h05AB] <= 32'h00F707B3; + mem['h05AC] <= 32'h00700713; + mem['h05AD] <= 32'h00E7A023; + mem['h05AE] <= 32'hFEE44703; + mem['h05AF] <= 32'h01800793; + mem['h05B0] <= 32'h04F71463; + mem['h05B1] <= 32'hFEF44703; + mem['h05B2] <= 32'hFED44783; + mem['h05B3] <= 32'h00278793; + mem['h05B4] <= 32'h02F71C63; + mem['h05B5] <= 32'hFEF44703; + mem['h05B6] <= 32'h00070793; + mem['h05B7] <= 32'h00279793; + mem['h05B8] <= 32'h00E787B3; + mem['h05B9] <= 32'h00379793; + mem['h05BA] <= 32'h00078713; + mem['h05BB] <= 32'hFEE44783; + mem['h05BC] <= 32'h00F707B3; + mem['h05BD] <= 32'h00279713; + mem['h05BE] <= 32'h052007B7; + mem['h05BF] <= 32'h00F707B3; + mem['h05C0] <= 32'h00700713; + mem['h05C1] <= 32'h00E7A023; + mem['h05C2] <= 32'hFEE44703; + mem['h05C3] <= 32'h01800793; + mem['h05C4] <= 32'h04F71263; + mem['h05C5] <= 32'hFEF44703; + mem['h05C6] <= 32'hFED44783; + mem['h05C7] <= 32'h02F71C63; + mem['h05C8] <= 32'hFEF44703; + mem['h05C9] <= 32'h00070793; + mem['h05CA] <= 32'h00279793; + mem['h05CB] <= 32'h00E787B3; + mem['h05CC] <= 32'h00379793; + mem['h05CD] <= 32'h00078713; + mem['h05CE] <= 32'hFEE44783; + mem['h05CF] <= 32'h00F707B3; + mem['h05D0] <= 32'h00279713; + mem['h05D1] <= 32'h052007B7; + mem['h05D2] <= 32'h00F707B3; + mem['h05D3] <= 32'h00700713; + mem['h05D4] <= 32'h00E7A023; + mem['h05D5] <= 32'hFEE44703; + mem['h05D6] <= 32'h01B00793; + mem['h05D7] <= 32'h04F71A63; + mem['h05D8] <= 32'hFEF44703; + mem['h05D9] <= 32'hFED44783; + mem['h05DA] <= 32'h04F76463; + mem['h05DB] <= 32'hFEF44703; + mem['h05DC] <= 32'hFED44783; + mem['h05DD] <= 32'h00478793; + mem['h05DE] <= 32'h02E7CC63; + mem['h05DF] <= 32'hFEF44703; + mem['h05E0] <= 32'h00070793; + mem['h05E1] <= 32'h00279793; + mem['h05E2] <= 32'h00E787B3; + mem['h05E3] <= 32'h00379793; + mem['h05E4] <= 32'h00078713; + mem['h05E5] <= 32'hFEE44783; + mem['h05E6] <= 32'h00F707B3; + mem['h05E7] <= 32'h00279713; + mem['h05E8] <= 32'h052007B7; + mem['h05E9] <= 32'h00F707B3; + mem['h05EA] <= 32'h00700713; + mem['h05EB] <= 32'h00E7A023; + mem['h05EC] <= 32'hFEE44703; + mem['h05ED] <= 32'h01C00793; + mem['h05EE] <= 32'h04F71263; + mem['h05EF] <= 32'hFEF44703; + mem['h05F0] <= 32'hFED44783; + mem['h05F1] <= 32'h02F71C63; + mem['h05F2] <= 32'hFEF44703; + mem['h05F3] <= 32'h00070793; + mem['h05F4] <= 32'h00279793; + mem['h05F5] <= 32'h00E787B3; + mem['h05F6] <= 32'h00379793; + mem['h05F7] <= 32'h00078713; + mem['h05F8] <= 32'hFEE44783; + mem['h05F9] <= 32'h00F707B3; + mem['h05FA] <= 32'h00279713; + mem['h05FB] <= 32'h052007B7; + mem['h05FC] <= 32'h00F707B3; + mem['h05FD] <= 32'h00700713; + mem['h05FE] <= 32'h00E7A023; + mem['h05FF] <= 32'hFEE44703; + mem['h0600] <= 32'h01D00793; + mem['h0601] <= 32'h04F71463; + mem['h0602] <= 32'hFEF44703; + mem['h0603] <= 32'hFED44783; + mem['h0604] <= 32'h00178793; + mem['h0605] <= 32'h02F71C63; + mem['h0606] <= 32'hFEF44703; + mem['h0607] <= 32'h00070793; + mem['h0608] <= 32'h00279793; + mem['h0609] <= 32'h00E787B3; + mem['h060A] <= 32'h00379793; + mem['h060B] <= 32'h00078713; + mem['h060C] <= 32'hFEE44783; + mem['h060D] <= 32'h00F707B3; + mem['h060E] <= 32'h00279713; + mem['h060F] <= 32'h052007B7; + mem['h0610] <= 32'h00F707B3; + mem['h0611] <= 32'h00700713; + mem['h0612] <= 32'h00E7A023; + mem['h0613] <= 32'hFEE44703; + mem['h0614] <= 32'h01C00793; + mem['h0615] <= 32'h04F71463; + mem['h0616] <= 32'hFEF44703; + mem['h0617] <= 32'hFED44783; + mem['h0618] <= 32'h00278793; + mem['h0619] <= 32'h02F71C63; + mem['h061A] <= 32'hFEF44703; + mem['h061B] <= 32'h00070793; + mem['h061C] <= 32'h00279793; + mem['h061D] <= 32'h00E787B3; + mem['h061E] <= 32'h00379793; + mem['h061F] <= 32'h00078713; + mem['h0620] <= 32'hFEE44783; + mem['h0621] <= 32'h00F707B3; + mem['h0622] <= 32'h00279713; + mem['h0623] <= 32'h052007B7; + mem['h0624] <= 32'h00F707B3; + mem['h0625] <= 32'h00700713; + mem['h0626] <= 32'h00E7A023; + mem['h0627] <= 32'hFEE44703; + mem['h0628] <= 32'h01D00793; + mem['h0629] <= 32'h04F71C63; + mem['h062A] <= 32'hFEF44703; + mem['h062B] <= 32'hFED44783; + mem['h062C] <= 32'h00378793; + mem['h062D] <= 32'h00F70A63; + mem['h062E] <= 32'hFEF44703; + mem['h062F] <= 32'hFED44783; + mem['h0630] <= 32'h00478793; + mem['h0631] <= 32'h02F71C63; + mem['h0632] <= 32'hFEF44703; + mem['h0633] <= 32'h00070793; + mem['h0634] <= 32'h00279793; + mem['h0635] <= 32'h00E787B3; + mem['h0636] <= 32'h00379793; + mem['h0637] <= 32'h00078713; + mem['h0638] <= 32'hFEE44783; + mem['h0639] <= 32'h00F707B3; + mem['h063A] <= 32'h00279713; + mem['h063B] <= 32'h052007B7; + mem['h063C] <= 32'h00F707B3; + mem['h063D] <= 32'h00700713; + mem['h063E] <= 32'h00E7A023; + mem['h063F] <= 32'hFEE44703; + mem['h0640] <= 32'h01F00793; + mem['h0641] <= 32'h00F70863; + mem['h0642] <= 32'hFEE44703; + mem['h0643] <= 32'h02100793; + mem['h0644] <= 32'h04F71A63; + mem['h0645] <= 32'hFED44703; + mem['h0646] <= 32'hFEF44783; + mem['h0647] <= 32'h04F77463; + mem['h0648] <= 32'hFEF44703; + mem['h0649] <= 32'hFED44783; + mem['h064A] <= 32'h00478793; + mem['h064B] <= 32'h02E7CC63; + mem['h064C] <= 32'hFEF44703; + mem['h064D] <= 32'h00070793; + mem['h064E] <= 32'h00279793; + mem['h064F] <= 32'h00E787B3; + mem['h0650] <= 32'h00379793; + mem['h0651] <= 32'h00078713; + mem['h0652] <= 32'hFEE44783; + mem['h0653] <= 32'h00F707B3; + mem['h0654] <= 32'h00279713; + mem['h0655] <= 32'h052007B7; + mem['h0656] <= 32'h00F707B3; + mem['h0657] <= 32'h00700713; + mem['h0658] <= 32'h00E7A023; + mem['h0659] <= 32'hFEE44703; + mem['h065A] <= 32'h02000793; + mem['h065B] <= 32'h04F71463; + mem['h065C] <= 32'hFEF44703; + mem['h065D] <= 32'hFED44783; + mem['h065E] <= 32'h00278793; + mem['h065F] <= 32'h02F71C63; + mem['h0660] <= 32'hFEF44703; + mem['h0661] <= 32'h00070793; + mem['h0662] <= 32'h00279793; + mem['h0663] <= 32'h00E787B3; + mem['h0664] <= 32'h00379793; + mem['h0665] <= 32'h00078713; + mem['h0666] <= 32'hFEE44783; + mem['h0667] <= 32'h00F707B3; + mem['h0668] <= 32'h00279713; + mem['h0669] <= 32'h052007B7; + mem['h066A] <= 32'h00F707B3; + mem['h066B] <= 32'h00700713; + mem['h066C] <= 32'h00E7A023; + mem['h066D] <= 32'hFEE44703; + mem['h066E] <= 32'h02000793; + mem['h066F] <= 32'h04F71263; + mem['h0670] <= 32'hFEF44703; + mem['h0671] <= 32'hFED44783; + mem['h0672] <= 32'h02F71C63; + mem['h0673] <= 32'hFEF44703; + mem['h0674] <= 32'h00070793; + mem['h0675] <= 32'h00279793; + mem['h0676] <= 32'h00E787B3; + mem['h0677] <= 32'h00379793; + mem['h0678] <= 32'h00078713; + mem['h0679] <= 32'hFEE44783; + mem['h067A] <= 32'h00F707B3; + mem['h067B] <= 32'h00279713; + mem['h067C] <= 32'h052007B7; + mem['h067D] <= 32'h00F707B3; + mem['h067E] <= 32'h00700713; + mem['h067F] <= 32'h00E7A023; + mem['h0680] <= 32'hFEE44703; + mem['h0681] <= 32'h02500793; + mem['h0682] <= 32'h04F71A63; + mem['h0683] <= 32'hFEF44703; + mem['h0684] <= 32'hFED44783; + mem['h0685] <= 32'h04F76463; + mem['h0686] <= 32'hFEF44703; + mem['h0687] <= 32'hFED44783; + mem['h0688] <= 32'h00478793; + mem['h0689] <= 32'h02E7CC63; + mem['h068A] <= 32'hFEF44703; + mem['h068B] <= 32'h00070793; + mem['h068C] <= 32'h00279793; + mem['h068D] <= 32'h00E787B3; + mem['h068E] <= 32'h00379793; + mem['h068F] <= 32'h00078713; + mem['h0690] <= 32'hFEE44783; + mem['h0691] <= 32'h00F707B3; + mem['h0692] <= 32'h00279713; + mem['h0693] <= 32'h052007B7; + mem['h0694] <= 32'h00F707B3; + mem['h0695] <= 32'h00700713; + mem['h0696] <= 32'h00E7A023; + mem['h0697] <= 32'hFEE44703; + mem['h0698] <= 32'h02300793; + mem['h0699] <= 32'h00F70863; + mem['h069A] <= 32'hFEE44703; + mem['h069B] <= 32'h02400793; + mem['h069C] <= 32'h04F71463; + mem['h069D] <= 32'hFEF44703; + mem['h069E] <= 32'hFED44783; + mem['h069F] <= 32'h00478793; + mem['h06A0] <= 32'h02F71C63; + mem['h06A1] <= 32'hFEF44703; + mem['h06A2] <= 32'h00070793; + mem['h06A3] <= 32'h00279793; + mem['h06A4] <= 32'h00E787B3; + mem['h06A5] <= 32'h00379793; + mem['h06A6] <= 32'h00078713; + mem['h06A7] <= 32'hFEE44783; + mem['h06A8] <= 32'h00F707B3; + mem['h06A9] <= 32'h00279713; + mem['h06AA] <= 32'h052007B7; + mem['h06AB] <= 32'h00F707B3; + mem['h06AC] <= 32'h00700713; + mem['h06AD] <= 32'h00E7A023; + mem['h06AE] <= 32'hFEE44703; + mem['h06AF] <= 32'h02300793; + mem['h06B0] <= 32'h04F71463; + mem['h06B1] <= 32'hFEF44703; + mem['h06B2] <= 32'hFED44783; + mem['h06B3] <= 32'h00378793; + mem['h06B4] <= 32'h02F71C63; + mem['h06B5] <= 32'hFEF44703; + mem['h06B6] <= 32'h00070793; + mem['h06B7] <= 32'h00279793; + mem['h06B8] <= 32'h00E787B3; + mem['h06B9] <= 32'h00379793; + mem['h06BA] <= 32'h00078713; + mem['h06BB] <= 32'hFEE44783; + mem['h06BC] <= 32'h00F707B3; + mem['h06BD] <= 32'h00279713; + mem['h06BE] <= 32'h052007B7; + mem['h06BF] <= 32'h00F707B3; + mem['h06C0] <= 32'h00700713; + mem['h06C1] <= 32'h00E7A023; + mem['h06C2] <= 32'hFEE44783; + mem['h06C3] <= 32'h00178793; + mem['h06C4] <= 32'hFEF40723; + mem['h06C5] <= 32'hFEE44703; + mem['h06C6] <= 32'h02700793; + mem['h06C7] <= 32'hE2E7F463; + mem['h06C8] <= 32'hFEF44783; + mem['h06C9] <= 32'h00178793; + mem['h06CA] <= 32'hFEF407A3; + mem['h06CB] <= 32'hFEF44703; + mem['h06CC] <= 32'h01D00793; + mem['h06CD] <= 32'hE0E7F463; + mem['h06CE] <= 32'h00000013; + mem['h06CF] <= 32'h00000013; + mem['h06D0] <= 32'h01C12403; + mem['h06D1] <= 32'h02010113; + mem['h06D2] <= 32'h00008067; + mem['h06D3] <= 32'hFD010113; + mem['h06D4] <= 32'h02812623; + mem['h06D5] <= 32'h03010413; + mem['h06D6] <= 32'hFCA42E23; + mem['h06D7] <= 32'hFCB42C23; + mem['h06D8] <= 32'hFCC42A23; + mem['h06D9] <= 32'hFE042623; + mem['h06DA] <= 32'h6A80006F; + mem['h06DB] <= 32'hFE042423; + mem['h06DC] <= 32'h6880006F; + mem['h06DD] <= 32'hFDC42783; + mem['h06DE] <= 32'h00278793; + mem['h06DF] <= 32'hFE842703; + mem['h06E0] <= 32'h02F70A63; + mem['h06E1] <= 32'hFDC42783; + mem['h06E2] <= 32'h00378793; + mem['h06E3] <= 32'hFE842703; + mem['h06E4] <= 32'h02F70263; + mem['h06E5] <= 32'hFDC42783; + mem['h06E6] <= 32'h00778793; + mem['h06E7] <= 32'hFE842703; + mem['h06E8] <= 32'h00F70A63; + mem['h06E9] <= 32'hFDC42783; + mem['h06EA] <= 32'h00878793; + mem['h06EB] <= 32'hFE842703; + mem['h06EC] <= 32'h04F71063; + mem['h06ED] <= 32'hFEC42703; + mem['h06EE] <= 32'hFD842783; + mem['h06EF] <= 32'h02F71A63; + mem['h06F0] <= 32'hFEC42703; + mem['h06F1] <= 32'h00070793; + mem['h06F2] <= 32'h00279793; + mem['h06F3] <= 32'h00E787B3; + mem['h06F4] <= 32'h00379793; + mem['h06F5] <= 32'h00078713; + mem['h06F6] <= 32'hFE842783; + mem['h06F7] <= 32'h00F707B3; + mem['h06F8] <= 32'h00279713; + mem['h06F9] <= 32'h052007B7; + mem['h06FA] <= 32'h00F707B3; + mem['h06FB] <= 32'h0007A023; + mem['h06FC] <= 32'hFDC42783; + mem['h06FD] <= 32'h00178793; + mem['h06FE] <= 32'hFE842703; + mem['h06FF] <= 32'h02F70A63; + mem['h0700] <= 32'hFDC42783; + mem['h0701] <= 32'h00478793; + mem['h0702] <= 32'hFE842703; + mem['h0703] <= 32'h02F70263; + mem['h0704] <= 32'hFDC42783; + mem['h0705] <= 32'h00678793; + mem['h0706] <= 32'hFE842703; + mem['h0707] <= 32'h00F70A63; + mem['h0708] <= 32'hFDC42783; + mem['h0709] <= 32'h00978793; + mem['h070A] <= 32'hFE842703; + mem['h070B] <= 32'h04F71263; + mem['h070C] <= 32'hFD842783; + mem['h070D] <= 32'h00178793; + mem['h070E] <= 32'hFEC42703; + mem['h070F] <= 32'h02F71A63; + mem['h0710] <= 32'hFEC42703; + mem['h0711] <= 32'h00070793; + mem['h0712] <= 32'h00279793; + mem['h0713] <= 32'h00E787B3; + mem['h0714] <= 32'h00379793; + mem['h0715] <= 32'h00078713; + mem['h0716] <= 32'hFE842783; + mem['h0717] <= 32'h00F707B3; + mem['h0718] <= 32'h00279713; + mem['h0719] <= 32'h052007B7; + mem['h071A] <= 32'h00F707B3; + mem['h071B] <= 32'h0007A023; + mem['h071C] <= 32'hFE842703; + mem['h071D] <= 32'hFDC42783; + mem['h071E] <= 32'h02F70263; + mem['h071F] <= 32'hFDC42783; + mem['h0720] <= 32'h00578793; + mem['h0721] <= 32'hFE842703; + mem['h0722] <= 32'h00F70A63; + mem['h0723] <= 32'hFDC42783; + mem['h0724] <= 32'h00A78793; + mem['h0725] <= 32'hFE842703; + mem['h0726] <= 32'h04F71263; + mem['h0727] <= 32'hFD842783; + mem['h0728] <= 32'h00278793; + mem['h0729] <= 32'hFEC42703; + mem['h072A] <= 32'h02F71A63; + mem['h072B] <= 32'hFEC42703; + mem['h072C] <= 32'h00070793; + mem['h072D] <= 32'h00279793; + mem['h072E] <= 32'h00E787B3; + mem['h072F] <= 32'h00379793; + mem['h0730] <= 32'h00078713; + mem['h0731] <= 32'hFE842783; + mem['h0732] <= 32'h00F707B3; + mem['h0733] <= 32'h00279713; + mem['h0734] <= 32'h052007B7; + mem['h0735] <= 32'h00F707B3; + mem['h0736] <= 32'h0007A023; + mem['h0737] <= 32'hFE842703; + mem['h0738] <= 32'hFDC42783; + mem['h0739] <= 32'h00F70A63; + mem['h073A] <= 32'hFDC42783; + mem['h073B] <= 32'h00A78793; + mem['h073C] <= 32'hFE842703; + mem['h073D] <= 32'h04F71263; + mem['h073E] <= 32'hFD842783; + mem['h073F] <= 32'h00378793; + mem['h0740] <= 32'hFEC42703; + mem['h0741] <= 32'h02F71A63; + mem['h0742] <= 32'hFEC42703; + mem['h0743] <= 32'h00070793; + mem['h0744] <= 32'h00279793; + mem['h0745] <= 32'h00E787B3; + mem['h0746] <= 32'h00379793; + mem['h0747] <= 32'h00078713; + mem['h0748] <= 32'hFE842783; + mem['h0749] <= 32'h00F707B3; + mem['h074A] <= 32'h00279713; + mem['h074B] <= 32'h052007B7; + mem['h074C] <= 32'h00F707B3; + mem['h074D] <= 32'h0007A023; + mem['h074E] <= 32'hFDC42783; + mem['h074F] <= 32'h00178793; + mem['h0750] <= 32'hFE842703; + mem['h0751] <= 32'h00F70A63; + mem['h0752] <= 32'hFDC42783; + mem['h0753] <= 32'h00978793; + mem['h0754] <= 32'hFE842703; + mem['h0755] <= 32'h04F71263; + mem['h0756] <= 32'hFD842783; + mem['h0757] <= 32'h00478793; + mem['h0758] <= 32'hFEC42703; + mem['h0759] <= 32'h02F71A63; + mem['h075A] <= 32'hFEC42703; + mem['h075B] <= 32'h00070793; + mem['h075C] <= 32'h00279793; + mem['h075D] <= 32'h00E787B3; + mem['h075E] <= 32'h00379793; + mem['h075F] <= 32'h00078713; + mem['h0760] <= 32'hFE842783; + mem['h0761] <= 32'h00F707B3; + mem['h0762] <= 32'h00279713; + mem['h0763] <= 32'h052007B7; + mem['h0764] <= 32'h00F707B3; + mem['h0765] <= 32'h0007A023; + mem['h0766] <= 32'hFDC42783; + mem['h0767] <= 32'h00278793; + mem['h0768] <= 32'hFE842703; + mem['h0769] <= 32'h00F70A63; + mem['h076A] <= 32'hFDC42783; + mem['h076B] <= 32'h00878793; + mem['h076C] <= 32'hFE842703; + mem['h076D] <= 32'h04F71263; + mem['h076E] <= 32'hFD842783; + mem['h076F] <= 32'h00578793; + mem['h0770] <= 32'hFEC42703; + mem['h0771] <= 32'h02F71A63; + mem['h0772] <= 32'hFEC42703; + mem['h0773] <= 32'h00070793; + mem['h0774] <= 32'h00279793; + mem['h0775] <= 32'h00E787B3; + mem['h0776] <= 32'h00379793; + mem['h0777] <= 32'h00078713; + mem['h0778] <= 32'hFE842783; + mem['h0779] <= 32'h00F707B3; + mem['h077A] <= 32'h00279713; + mem['h077B] <= 32'h052007B7; + mem['h077C] <= 32'h00F707B3; + mem['h077D] <= 32'h0007A023; + mem['h077E] <= 32'hFDC42783; + mem['h077F] <= 32'h00378793; + mem['h0780] <= 32'hFE842703; + mem['h0781] <= 32'h00F70A63; + mem['h0782] <= 32'hFDC42783; + mem['h0783] <= 32'h00778793; + mem['h0784] <= 32'hFE842703; + mem['h0785] <= 32'h04F71263; + mem['h0786] <= 32'hFD842783; + mem['h0787] <= 32'h00678793; + mem['h0788] <= 32'hFEC42703; + mem['h0789] <= 32'h02F71A63; + mem['h078A] <= 32'hFEC42703; + mem['h078B] <= 32'h00070793; + mem['h078C] <= 32'h00279793; + mem['h078D] <= 32'h00E787B3; + mem['h078E] <= 32'h00379793; + mem['h078F] <= 32'h00078713; + mem['h0790] <= 32'hFE842783; + mem['h0791] <= 32'h00F707B3; + mem['h0792] <= 32'h00279713; + mem['h0793] <= 32'h052007B7; + mem['h0794] <= 32'h00F707B3; + mem['h0795] <= 32'h0007A023; + mem['h0796] <= 32'hFDC42783; + mem['h0797] <= 32'h00478793; + mem['h0798] <= 32'hFE842703; + mem['h0799] <= 32'h00F70A63; + mem['h079A] <= 32'hFDC42783; + mem['h079B] <= 32'h00678793; + mem['h079C] <= 32'hFE842703; + mem['h079D] <= 32'h04F71263; + mem['h079E] <= 32'hFD842783; + mem['h079F] <= 32'h00778793; + mem['h07A0] <= 32'hFEC42703; + mem['h07A1] <= 32'h02F71A63; + mem['h07A2] <= 32'hFEC42703; + mem['h07A3] <= 32'h00070793; + mem['h07A4] <= 32'h00279793; + mem['h07A5] <= 32'h00E787B3; + mem['h07A6] <= 32'h00379793; + mem['h07A7] <= 32'h00078713; + mem['h07A8] <= 32'hFE842783; + mem['h07A9] <= 32'h00F707B3; + mem['h07AA] <= 32'h00279713; + mem['h07AB] <= 32'h052007B7; + mem['h07AC] <= 32'h00F707B3; + mem['h07AD] <= 32'h0007A023; + mem['h07AE] <= 32'hFDC42783; + mem['h07AF] <= 32'h00578793; + mem['h07B0] <= 32'hFE842703; + mem['h07B1] <= 32'h04F71263; + mem['h07B2] <= 32'hFD842783; + mem['h07B3] <= 32'h00878793; + mem['h07B4] <= 32'hFEC42703; + mem['h07B5] <= 32'h02F71A63; + mem['h07B6] <= 32'hFEC42703; + mem['h07B7] <= 32'h00070793; + mem['h07B8] <= 32'h00279793; + mem['h07B9] <= 32'h00E787B3; + mem['h07BA] <= 32'h00379793; + mem['h07BB] <= 32'h00078713; + mem['h07BC] <= 32'hFE842783; + mem['h07BD] <= 32'h00F707B3; + mem['h07BE] <= 32'h00279713; + mem['h07BF] <= 32'h052007B7; + mem['h07C0] <= 32'h00F707B3; + mem['h07C1] <= 32'h0007A023; + mem['h07C2] <= 32'hFDC42783; + mem['h07C3] <= 32'h00278793; + mem['h07C4] <= 32'hFE842703; + mem['h07C5] <= 32'h02F70A63; + mem['h07C6] <= 32'hFDC42783; + mem['h07C7] <= 32'h00378793; + mem['h07C8] <= 32'hFE842703; + mem['h07C9] <= 32'h02F70263; + mem['h07CA] <= 32'hFDC42783; + mem['h07CB] <= 32'h00778793; + mem['h07CC] <= 32'hFE842703; + mem['h07CD] <= 32'h00F70A63; + mem['h07CE] <= 32'hFDC42783; + mem['h07CF] <= 32'h00878793; + mem['h07D0] <= 32'hFE842703; + mem['h07D1] <= 32'h04F71463; + mem['h07D2] <= 32'hFD842783; + mem['h07D3] <= 32'h00178793; + mem['h07D4] <= 32'hFEC42703; + mem['h07D5] <= 32'h02F71C63; + mem['h07D6] <= 32'hFEC42703; + mem['h07D7] <= 32'h00070793; + mem['h07D8] <= 32'h00279793; + mem['h07D9] <= 32'h00E787B3; + mem['h07DA] <= 32'h00379793; + mem['h07DB] <= 32'h00078713; + mem['h07DC] <= 32'hFE842783; + mem['h07DD] <= 32'h00F707B3; + mem['h07DE] <= 32'h00279713; + mem['h07DF] <= 32'h052007B7; + mem['h07E0] <= 32'h00F707B3; + mem['h07E1] <= 32'hFD442703; + mem['h07E2] <= 32'h00E7A023; + mem['h07E3] <= 32'hFDC42703; + mem['h07E4] <= 32'hFE842783; + mem['h07E5] <= 32'h00F75A63; + mem['h07E6] <= 32'hFDC42783; + mem['h07E7] <= 32'h00478793; + mem['h07E8] <= 32'hFE842703; + mem['h07E9] <= 32'h02E7D263; + mem['h07EA] <= 32'hFDC42783; + mem['h07EB] <= 32'h00578793; + mem['h07EC] <= 32'hFE842703; + mem['h07ED] <= 32'h04E7DC63; + mem['h07EE] <= 32'hFDC42783; + mem['h07EF] <= 32'h00978793; + mem['h07F0] <= 32'hFE842703; + mem['h07F1] <= 32'h04E7C463; + mem['h07F2] <= 32'hFD842783; + mem['h07F3] <= 32'h00278793; + mem['h07F4] <= 32'hFEC42703; + mem['h07F5] <= 32'h02F71C63; + mem['h07F6] <= 32'hFEC42703; + mem['h07F7] <= 32'h00070793; + mem['h07F8] <= 32'h00279793; + mem['h07F9] <= 32'h00E787B3; + mem['h07FA] <= 32'h00379793; + mem['h07FB] <= 32'h00078713; + mem['h07FC] <= 32'hFE842783; + mem['h07FD] <= 32'h00F707B3; + mem['h07FE] <= 32'h00279713; + mem['h07FF] <= 32'h052007B7; + mem['h0800] <= 32'h00F707B3; + mem['h0801] <= 32'hFD442703; + mem['h0802] <= 32'h00E7A023; + mem['h0803] <= 32'hFDC42703; + mem['h0804] <= 32'hFE842783; + mem['h0805] <= 32'h04F75C63; + mem['h0806] <= 32'hFDC42783; + mem['h0807] <= 32'h00978793; + mem['h0808] <= 32'hFE842703; + mem['h0809] <= 32'h04E7C463; + mem['h080A] <= 32'hFD842783; + mem['h080B] <= 32'h00378793; + mem['h080C] <= 32'hFEC42703; + mem['h080D] <= 32'h02F71C63; + mem['h080E] <= 32'hFEC42703; + mem['h080F] <= 32'h00070793; + mem['h0810] <= 32'h00279793; + mem['h0811] <= 32'h00E787B3; + mem['h0812] <= 32'h00379793; + mem['h0813] <= 32'h00078713; + mem['h0814] <= 32'hFE842783; + mem['h0815] <= 32'h00F707B3; + mem['h0816] <= 32'h00279713; + mem['h0817] <= 32'h052007B7; + mem['h0818] <= 32'h00F707B3; + mem['h0819] <= 32'hFD442703; + mem['h081A] <= 32'h00E7A023; + mem['h081B] <= 32'hFDC42783; + mem['h081C] <= 32'h00178793; + mem['h081D] <= 32'hFE842703; + mem['h081E] <= 32'h04E7DC63; + mem['h081F] <= 32'hFDC42783; + mem['h0820] <= 32'h00878793; + mem['h0821] <= 32'hFE842703; + mem['h0822] <= 32'h04E7C463; + mem['h0823] <= 32'hFD842783; + mem['h0824] <= 32'h00478793; + mem['h0825] <= 32'hFEC42703; + mem['h0826] <= 32'h02F71C63; + mem['h0827] <= 32'hFEC42703; + mem['h0828] <= 32'h00070793; + mem['h0829] <= 32'h00279793; + mem['h082A] <= 32'h00E787B3; + mem['h082B] <= 32'h00379793; + mem['h082C] <= 32'h00078713; + mem['h082D] <= 32'hFE842783; + mem['h082E] <= 32'h00F707B3; + mem['h082F] <= 32'h00279713; + mem['h0830] <= 32'h052007B7; + mem['h0831] <= 32'h00F707B3; + mem['h0832] <= 32'hFD442703; + mem['h0833] <= 32'h00E7A023; + mem['h0834] <= 32'hFDC42783; + mem['h0835] <= 32'h00278793; + mem['h0836] <= 32'hFE842703; + mem['h0837] <= 32'h04E7DC63; + mem['h0838] <= 32'hFDC42783; + mem['h0839] <= 32'h00778793; + mem['h083A] <= 32'hFE842703; + mem['h083B] <= 32'h04E7C463; + mem['h083C] <= 32'hFD842783; + mem['h083D] <= 32'h00578793; + mem['h083E] <= 32'hFEC42703; + mem['h083F] <= 32'h02F71C63; + mem['h0840] <= 32'hFEC42703; + mem['h0841] <= 32'h00070793; + mem['h0842] <= 32'h00279793; + mem['h0843] <= 32'h00E787B3; + mem['h0844] <= 32'h00379793; + mem['h0845] <= 32'h00078713; + mem['h0846] <= 32'hFE842783; + mem['h0847] <= 32'h00F707B3; + mem['h0848] <= 32'h00279713; + mem['h0849] <= 32'h052007B7; + mem['h084A] <= 32'h00F707B3; + mem['h084B] <= 32'hFD442703; + mem['h084C] <= 32'h00E7A023; + mem['h084D] <= 32'hFDC42783; + mem['h084E] <= 32'h00378793; + mem['h084F] <= 32'hFE842703; + mem['h0850] <= 32'h04E7DC63; + mem['h0851] <= 32'hFDC42783; + mem['h0852] <= 32'h00678793; + mem['h0853] <= 32'hFE842703; + mem['h0854] <= 32'h04E7C463; + mem['h0855] <= 32'hFD842783; + mem['h0856] <= 32'h00678793; + mem['h0857] <= 32'hFEC42703; + mem['h0858] <= 32'h02F71C63; + mem['h0859] <= 32'hFEC42703; + mem['h085A] <= 32'h00070793; + mem['h085B] <= 32'h00279793; + mem['h085C] <= 32'h00E787B3; + mem['h085D] <= 32'h00379793; + mem['h085E] <= 32'h00078713; + mem['h085F] <= 32'hFE842783; + mem['h0860] <= 32'h00F707B3; + mem['h0861] <= 32'h00279713; + mem['h0862] <= 32'h052007B7; + mem['h0863] <= 32'h00F707B3; + mem['h0864] <= 32'hFD442703; + mem['h0865] <= 32'h00E7A023; + mem['h0866] <= 32'hFDC42783; + mem['h0867] <= 32'h00578793; + mem['h0868] <= 32'hFE842703; + mem['h0869] <= 32'h04F71463; + mem['h086A] <= 32'hFD842783; + mem['h086B] <= 32'h00778793; + mem['h086C] <= 32'hFEC42703; + mem['h086D] <= 32'h02F71C63; + mem['h086E] <= 32'hFEC42703; + mem['h086F] <= 32'h00070793; + mem['h0870] <= 32'h00279793; + mem['h0871] <= 32'h00E787B3; + mem['h0872] <= 32'h00379793; + mem['h0873] <= 32'h00078713; + mem['h0874] <= 32'hFE842783; + mem['h0875] <= 32'h00F707B3; + mem['h0876] <= 32'h00279713; + mem['h0877] <= 32'h052007B7; + mem['h0878] <= 32'h00F707B3; + mem['h0879] <= 32'hFD442703; + mem['h087A] <= 32'h00E7A023; + mem['h087B] <= 32'hFE842783; + mem['h087C] <= 32'h00178793; + mem['h087D] <= 32'hFEF42423; + mem['h087E] <= 32'hFE842703; + mem['h087F] <= 32'h02700793; + mem['h0880] <= 32'h96E7DAE3; + mem['h0881] <= 32'hFEC42783; + mem['h0882] <= 32'h00178793; + mem['h0883] <= 32'hFEF42623; + mem['h0884] <= 32'hFEC42703; + mem['h0885] <= 32'h01D00793; + mem['h0886] <= 32'h94E7DAE3; + mem['h0887] <= 32'h00000013; + mem['h0888] <= 32'h00000013; + mem['h0889] <= 32'h02C12403; + mem['h088A] <= 32'h03010113; + mem['h088B] <= 32'h00008067; + mem['h088C] <= 32'hFD010113; + mem['h088D] <= 32'h02812623; + mem['h088E] <= 32'h03010413; + mem['h088F] <= 32'hFCA42E23; + mem['h0890] <= 32'hFE0407A3; + mem['h0891] <= 32'h0640006F; + mem['h0892] <= 32'hFE040723; + mem['h0893] <= 32'h0440006F; + mem['h0894] <= 32'hFEF44703; + mem['h0895] <= 32'h00070793; + mem['h0896] <= 32'h00279793; + mem['h0897] <= 32'h00E787B3; + mem['h0898] <= 32'h00379793; + mem['h0899] <= 32'h00078713; + mem['h089A] <= 32'hFEE44783; + mem['h089B] <= 32'h00F707B3; + mem['h089C] <= 32'h00279713; + mem['h089D] <= 32'h052007B7; + mem['h089E] <= 32'h00F707B3; + mem['h089F] <= 32'hFDC42703; + mem['h08A0] <= 32'h00E7A023; + mem['h08A1] <= 32'hFEE44783; + mem['h08A2] <= 32'h00178793; + mem['h08A3] <= 32'hFEF40723; + mem['h08A4] <= 32'hFEE44703; + mem['h08A5] <= 32'h02700793; + mem['h08A6] <= 32'hFAE7FCE3; + mem['h08A7] <= 32'hFEF44783; + mem['h08A8] <= 32'h00178793; + mem['h08A9] <= 32'hFEF407A3; + mem['h08AA] <= 32'hFEF44703; + mem['h08AB] <= 32'h01D00793; + mem['h08AC] <= 32'hF8E7FCE3; + mem['h08AD] <= 32'h00000013; + mem['h08AE] <= 32'h00000013; + mem['h08AF] <= 32'h02C12403; + mem['h08B0] <= 32'h03010113; + mem['h08B1] <= 32'h00008067; + mem['h08B2] <= 32'hFD010113; + mem['h08B3] <= 32'h02112623; + mem['h08B4] <= 32'h02812423; + mem['h08B5] <= 32'h03010413; + mem['h08B6] <= 32'hFCA42E23; + mem['h08B7] <= 32'h00100793; + mem['h08B8] <= 32'hFEF406A3; + mem['h08B9] <= 32'hFE0407A3; + mem['h08BA] <= 32'h7980006F; + mem['h08BB] <= 32'hFE040723; + mem['h08BC] <= 32'h7780006F; + mem['h08BD] <= 32'hFEF44703; + mem['h08BE] <= 32'h00070793; + mem['h08BF] <= 32'h00279793; + mem['h08C0] <= 32'h00E787B3; + mem['h08C1] <= 32'h00379793; + mem['h08C2] <= 32'h00078713; + mem['h08C3] <= 32'hFEE44783; + mem['h08C4] <= 32'h00F707B3; + mem['h08C5] <= 32'h00279713; + mem['h08C6] <= 32'h052007B7; + mem['h08C7] <= 32'h00F707B3; + mem['h08C8] <= 32'h00900713; + mem['h08C9] <= 32'h00E7A023; + mem['h08CA] <= 32'hFEE44703; + mem['h08CB] <= 32'h00500793; + mem['h08CC] <= 32'h02F71263; + mem['h08CD] <= 32'hFED44783; + mem['h08CE] <= 32'h00178713; + mem['h08CF] <= 32'hFEF44783; + mem['h08D0] <= 32'h00F75A63; + mem['h08D1] <= 32'hFEF44703; + mem['h08D2] <= 32'hFED44783; + mem['h08D3] <= 32'h00578793; + mem['h08D4] <= 32'h0AE7DC63; + mem['h08D5] <= 32'hFEE44703; + mem['h08D6] <= 32'h00600793; + mem['h08D7] <= 32'h02F71263; + mem['h08D8] <= 32'hFEF44703; + mem['h08D9] <= 32'hFED44783; + mem['h08DA] <= 32'h00178793; + mem['h08DB] <= 32'h08F70E63; + mem['h08DC] <= 32'hFEF44703; + mem['h08DD] <= 32'hFED44783; + mem['h08DE] <= 32'h00678793; + mem['h08DF] <= 32'h08F70663; + mem['h08E0] <= 32'hFEE44703; + mem['h08E1] <= 32'h00600793; + mem['h08E2] <= 32'h02E7F663; + mem['h08E3] <= 32'hFEE44703; + mem['h08E4] <= 32'h00B00793; + mem['h08E5] <= 32'h02E7E063; + mem['h08E6] <= 32'hFEF44703; + mem['h08E7] <= 32'hFED44783; + mem['h08E8] <= 32'h06F70463; + mem['h08E9] <= 32'hFEF44703; + mem['h08EA] <= 32'hFED44783; + mem['h08EB] <= 32'h00778793; + mem['h08EC] <= 32'h04F70C63; + mem['h08ED] <= 32'hFEE44703; + mem['h08EE] <= 32'h00B00793; + mem['h08EF] <= 32'h02F71263; + mem['h08F0] <= 32'hFED44783; + mem['h08F1] <= 32'h00378713; + mem['h08F2] <= 32'hFEF44783; + mem['h08F3] <= 32'h00F75A63; + mem['h08F4] <= 32'hFEF44703; + mem['h08F5] <= 32'hFED44783; + mem['h08F6] <= 32'h00778793; + mem['h08F7] <= 32'h02E7D663; + mem['h08F8] <= 32'hFEE44703; + mem['h08F9] <= 32'h00700793; + mem['h08FA] <= 32'h04E7FA63; + mem['h08FB] <= 32'hFEE44703; + mem['h08FC] <= 32'h00B00793; + mem['h08FD] <= 32'h04E7E463; + mem['h08FE] <= 32'hFEF44703; + mem['h08FF] <= 32'hFED44783; + mem['h0900] <= 32'h00478793; + mem['h0901] <= 32'h02F71C63; + mem['h0902] <= 32'hFEF44703; + mem['h0903] <= 32'h00070793; + mem['h0904] <= 32'h00279793; + mem['h0905] <= 32'h00E787B3; + mem['h0906] <= 32'h00379793; + mem['h0907] <= 32'h00078713; + mem['h0908] <= 32'hFEE44783; + mem['h0909] <= 32'h00F707B3; + mem['h090A] <= 32'h00279713; + mem['h090B] <= 32'h052007B7; + mem['h090C] <= 32'h00F707B3; + mem['h090D] <= 32'h00300713; + mem['h090E] <= 32'h00E7A023; + mem['h090F] <= 32'hFEE44703; + mem['h0910] <= 32'h01000793; + mem['h0911] <= 32'h00F71863; + mem['h0912] <= 32'hFEF44703; + mem['h0913] <= 32'hFED44783; + mem['h0914] <= 32'h0CF70263; + mem['h0915] <= 32'hFEE44703; + mem['h0916] <= 32'h00F00793; + mem['h0917] <= 32'h00F70863; + mem['h0918] <= 32'hFEE44703; + mem['h0919] <= 32'h01100793; + mem['h091A] <= 32'h00F71A63; + mem['h091B] <= 32'hFEF44703; + mem['h091C] <= 32'hFED44783; + mem['h091D] <= 32'h00178793; + mem['h091E] <= 32'h08F70E63; + mem['h091F] <= 32'hFEE44703; + mem['h0920] <= 32'h00E00793; + mem['h0921] <= 32'h00F70863; + mem['h0922] <= 32'hFEE44703; + mem['h0923] <= 32'h01200793; + mem['h0924] <= 32'h02F71263; + mem['h0925] <= 32'hFED44783; + mem['h0926] <= 32'h00178713; + mem['h0927] <= 32'hFEF44783; + mem['h0928] <= 32'h00F75A63; + mem['h0929] <= 32'hFEF44703; + mem['h092A] <= 32'hFED44783; + mem['h092B] <= 32'h00378793; + mem['h092C] <= 32'h06E7D263; + mem['h092D] <= 32'hFEE44703; + mem['h092E] <= 32'h00C00793; + mem['h092F] <= 32'h02E7F063; + mem['h0930] <= 32'hFEE44703; + mem['h0931] <= 32'h01300793; + mem['h0932] <= 32'h00E7EA63; + mem['h0933] <= 32'hFEF44703; + mem['h0934] <= 32'hFED44783; + mem['h0935] <= 32'h00478793; + mem['h0936] <= 32'h02F70E63; + mem['h0937] <= 32'hFEE44703; + mem['h0938] <= 32'h00D00793; + mem['h0939] <= 32'h00F70863; + mem['h093A] <= 32'hFEE44703; + mem['h093B] <= 32'h01300793; + mem['h093C] <= 32'h04F71C63; + mem['h093D] <= 32'hFED44783; + mem['h093E] <= 32'h00478713; + mem['h093F] <= 32'hFEF44783; + mem['h0940] <= 32'h04F75463; + mem['h0941] <= 32'hFEF44703; + mem['h0942] <= 32'hFED44783; + mem['h0943] <= 32'h00778793; + mem['h0944] <= 32'h02E7CC63; + mem['h0945] <= 32'hFEF44703; + mem['h0946] <= 32'h00070793; + mem['h0947] <= 32'h00279793; + mem['h0948] <= 32'h00E787B3; + mem['h0949] <= 32'h00379793; + mem['h094A] <= 32'h00078713; + mem['h094B] <= 32'hFEE44783; + mem['h094C] <= 32'h00F707B3; + mem['h094D] <= 32'h00279713; + mem['h094E] <= 32'h052007B7; + mem['h094F] <= 32'h00F707B3; + mem['h0950] <= 32'h00100713; + mem['h0951] <= 32'h00E7A023; + mem['h0952] <= 32'hFEE44703; + mem['h0953] <= 32'h01500793; + mem['h0954] <= 32'h00F70863; + mem['h0955] <= 32'hFEE44703; + mem['h0956] <= 32'h01C00793; + mem['h0957] <= 32'h02F71063; + mem['h0958] <= 32'hFEF44703; + mem['h0959] <= 32'hFED44783; + mem['h095A] <= 32'h00F76A63; + mem['h095B] <= 32'hFEF44703; + mem['h095C] <= 32'hFED44783; + mem['h095D] <= 32'h00778793; + mem['h095E] <= 32'h08E7D263; + mem['h095F] <= 32'hFEE44703; + mem['h0960] <= 32'h01600793; + mem['h0961] <= 32'h00F70863; + mem['h0962] <= 32'hFEE44703; + mem['h0963] <= 32'h01B00793; + mem['h0964] <= 32'h00F71863; + mem['h0965] <= 32'hFEF44703; + mem['h0966] <= 32'hFED44783; + mem['h0967] <= 32'h06F70063; + mem['h0968] <= 32'hFEE44703; + mem['h0969] <= 32'h01700793; + mem['h096A] <= 32'h00F70863; + mem['h096B] <= 32'hFEE44703; + mem['h096C] <= 32'h01A00793; + mem['h096D] <= 32'h02F71063; + mem['h096E] <= 32'hFED44703; + mem['h096F] <= 32'hFEF44783; + mem['h0970] <= 32'h00F77A63; + mem['h0971] <= 32'hFEF44703; + mem['h0972] <= 32'hFED44783; + mem['h0973] <= 32'h00278793; + mem['h0974] <= 32'h02E7D663; + mem['h0975] <= 32'hFEE44703; + mem['h0976] <= 32'h01800793; + mem['h0977] <= 32'h00F70863; + mem['h0978] <= 32'hFEE44703; + mem['h0979] <= 32'h01900793; + mem['h097A] <= 32'h04F71463; + mem['h097B] <= 32'hFEF44703; + mem['h097C] <= 32'hFED44783; + mem['h097D] <= 32'h00378793; + mem['h097E] <= 32'h02F71C63; + mem['h097F] <= 32'hFEF44703; + mem['h0980] <= 32'h00070793; + mem['h0981] <= 32'h00279793; + mem['h0982] <= 32'h00E787B3; + mem['h0983] <= 32'h00379793; + mem['h0984] <= 32'h00078713; + mem['h0985] <= 32'hFEE44783; + mem['h0986] <= 32'h00F707B3; + mem['h0987] <= 32'h00279713; + mem['h0988] <= 32'h052007B7; + mem['h0989] <= 32'h00F707B3; + mem['h098A] <= 32'h00200713; + mem['h098B] <= 32'h00E7A023; + mem['h098C] <= 32'hFEE44703; + mem['h098D] <= 32'h01D00793; + mem['h098E] <= 32'h02E7F663; + mem['h098F] <= 32'hFEE44703; + mem['h0990] <= 32'h02200793; + mem['h0991] <= 32'h02E7E063; + mem['h0992] <= 32'hFEF44703; + mem['h0993] <= 32'hFED44783; + mem['h0994] <= 32'h06F70263; + mem['h0995] <= 32'hFEF44703; + mem['h0996] <= 32'hFED44783; + mem['h0997] <= 32'h00778793; + mem['h0998] <= 32'h04F70A63; + mem['h0999] <= 32'hFEE44703; + mem['h099A] <= 32'h01E00793; + mem['h099B] <= 32'h02F71063; + mem['h099C] <= 32'hFED44703; + mem['h099D] <= 32'hFEF44783; + mem['h099E] <= 32'h00F77A63; + mem['h099F] <= 32'hFEF44703; + mem['h09A0] <= 32'hFED44783; + mem['h09A1] <= 32'h00678793; + mem['h09A2] <= 32'h02E7D663; + mem['h09A3] <= 32'hFEE44703; + mem['h09A4] <= 32'h01E00793; + mem['h09A5] <= 32'h04E7FA63; + mem['h09A6] <= 32'hFEE44703; + mem['h09A7] <= 32'h02100793; + mem['h09A8] <= 32'h04E7E463; + mem['h09A9] <= 32'hFEF44703; + mem['h09AA] <= 32'hFED44783; + mem['h09AB] <= 32'h00478793; + mem['h09AC] <= 32'h02F71C63; + mem['h09AD] <= 32'hFEF44703; + mem['h09AE] <= 32'h00070793; + mem['h09AF] <= 32'h00279793; + mem['h09B0] <= 32'h00E787B3; + mem['h09B1] <= 32'h00379793; + mem['h09B2] <= 32'h00078713; + mem['h09B3] <= 32'hFEE44783; + mem['h09B4] <= 32'h00F707B3; + mem['h09B5] <= 32'h00279713; + mem['h09B6] <= 32'h052007B7; + mem['h09B7] <= 32'h00F707B3; + mem['h09B8] <= 32'h00400713; + mem['h09B9] <= 32'h00E7A023; + mem['h09BA] <= 32'hFEE44703; + mem['h09BB] <= 32'h00700793; + mem['h09BC] <= 32'h00F70863; + mem['h09BD] <= 32'hFEE44703; + mem['h09BE] <= 32'h00C00793; + mem['h09BF] <= 32'h02F71263; + mem['h09C0] <= 32'hFED44783; + mem['h09C1] <= 32'h00A78713; + mem['h09C2] <= 32'hFEF44783; + mem['h09C3] <= 32'h00F75A63; + mem['h09C4] <= 32'hFEF44703; + mem['h09C5] <= 32'hFED44783; + mem['h09C6] <= 32'h01078793; + mem['h09C7] <= 32'h02E7DE63; + mem['h09C8] <= 32'hFEF44703; + mem['h09C9] <= 32'hFED44783; + mem['h09CA] <= 32'h00A78793; + mem['h09CB] <= 32'h00F70A63; + mem['h09CC] <= 32'hFEF44703; + mem['h09CD] <= 32'hFED44783; + mem['h09CE] <= 32'h01178793; + mem['h09CF] <= 32'h04F71863; + mem['h09D0] <= 32'hFEE44703; + mem['h09D1] <= 32'h00700793; + mem['h09D2] <= 32'h04E7F263; + mem['h09D3] <= 32'hFEE44703; + mem['h09D4] <= 32'h00B00793; + mem['h09D5] <= 32'h02E7EC63; + mem['h09D6] <= 32'hFEF44703; + mem['h09D7] <= 32'h00070793; + mem['h09D8] <= 32'h00279793; + mem['h09D9] <= 32'h00E787B3; + mem['h09DA] <= 32'h00379793; + mem['h09DB] <= 32'h00078713; + mem['h09DC] <= 32'hFEE44783; + mem['h09DD] <= 32'h00F707B3; + mem['h09DE] <= 32'h00279713; + mem['h09DF] <= 32'h052007B7; + mem['h09E0] <= 32'h00F707B3; + mem['h09E1] <= 32'h00300713; + mem['h09E2] <= 32'h00E7A023; + mem['h09E3] <= 32'hFEE44703; + mem['h09E4] <= 32'h00E00793; + mem['h09E5] <= 32'h00F70863; + mem['h09E6] <= 32'hFEE44703; + mem['h09E7] <= 32'h01400793; + mem['h09E8] <= 32'h02F71263; + mem['h09E9] <= 32'hFED44783; + mem['h09EA] <= 32'h00978713; + mem['h09EB] <= 32'hFEF44783; + mem['h09EC] <= 32'h00F75A63; + mem['h09ED] <= 32'hFEF44703; + mem['h09EE] <= 32'hFED44783; + mem['h09EF] <= 32'h00C78793; + mem['h09F0] <= 32'h08E7D863; + mem['h09F1] <= 32'hFEE44703; + mem['h09F2] <= 32'h00F00793; + mem['h09F3] <= 32'h00F70863; + mem['h09F4] <= 32'hFEE44703; + mem['h09F5] <= 32'h01300793; + mem['h09F6] <= 32'h02F71263; + mem['h09F7] <= 32'hFED44783; + mem['h09F8] <= 32'h00C78713; + mem['h09F9] <= 32'hFEF44783; + mem['h09FA] <= 32'h00F75A63; + mem['h09FB] <= 32'hFEF44703; + mem['h09FC] <= 32'hFED44783; + mem['h09FD] <= 32'h00E78793; + mem['h09FE] <= 32'h04E7DC63; + mem['h09FF] <= 32'hFEE44703; + mem['h0A00] <= 32'h01000793; + mem['h0A01] <= 32'h00F70863; + mem['h0A02] <= 32'hFEE44703; + mem['h0A03] <= 32'h01200793; + mem['h0A04] <= 32'h00F71A63; + mem['h0A05] <= 32'hFEF44703; + mem['h0A06] <= 32'hFED44783; + mem['h0A07] <= 32'h00F78793; + mem['h0A08] <= 32'h02F70863; + mem['h0A09] <= 32'hFEE44703; + mem['h0A0A] <= 32'h01100793; + mem['h0A0B] <= 32'h04F71C63; + mem['h0A0C] <= 32'hFED44783; + mem['h0A0D] <= 32'h00F78713; + mem['h0A0E] <= 32'hFEF44783; + mem['h0A0F] <= 32'h04F75463; + mem['h0A10] <= 32'hFEF44703; + mem['h0A11] <= 32'hFED44783; + mem['h0A12] <= 32'h01178793; + mem['h0A13] <= 32'h02E7CC63; + mem['h0A14] <= 32'hFEF44703; + mem['h0A15] <= 32'h00070793; + mem['h0A16] <= 32'h00279793; + mem['h0A17] <= 32'h00E787B3; + mem['h0A18] <= 32'h00379793; + mem['h0A19] <= 32'h00078713; + mem['h0A1A] <= 32'hFEE44783; + mem['h0A1B] <= 32'h00F707B3; + mem['h0A1C] <= 32'h00279713; + mem['h0A1D] <= 32'h052007B7; + mem['h0A1E] <= 32'h00F707B3; + mem['h0A1F] <= 32'h00100713; + mem['h0A20] <= 32'h00E7A023; + mem['h0A21] <= 32'hFEE44703; + mem['h0A22] <= 32'h01500793; + mem['h0A23] <= 32'h02E7F863; + mem['h0A24] <= 32'hFEE44703; + mem['h0A25] <= 32'h01A00793; + mem['h0A26] <= 32'h02E7E263; + mem['h0A27] <= 32'hFEF44703; + mem['h0A28] <= 32'hFED44783; + mem['h0A29] <= 32'h00A78793; + mem['h0A2A] <= 32'h06F70463; + mem['h0A2B] <= 32'hFEF44703; + mem['h0A2C] <= 32'hFED44783; + mem['h0A2D] <= 32'h01178793; + mem['h0A2E] <= 32'h04F70C63; + mem['h0A2F] <= 32'hFEE44703; + mem['h0A30] <= 32'h01600793; + mem['h0A31] <= 32'h02F71263; + mem['h0A32] <= 32'hFED44783; + mem['h0A33] <= 32'h00A78713; + mem['h0A34] <= 32'hFEF44783; + mem['h0A35] <= 32'h00F75A63; + mem['h0A36] <= 32'hFEF44703; + mem['h0A37] <= 32'hFED44783; + mem['h0A38] <= 32'h01078793; + mem['h0A39] <= 32'h02E7D663; + mem['h0A3A] <= 32'hFEE44703; + mem['h0A3B] <= 32'h01600793; + mem['h0A3C] <= 32'h04E7FA63; + mem['h0A3D] <= 32'hFEE44703; + mem['h0A3E] <= 32'h01900793; + mem['h0A3F] <= 32'h04E7E463; + mem['h0A40] <= 32'hFEF44703; + mem['h0A41] <= 32'hFED44783; + mem['h0A42] <= 32'h00E78793; + mem['h0A43] <= 32'h02F71C63; + mem['h0A44] <= 32'hFEF44703; + mem['h0A45] <= 32'h00070793; + mem['h0A46] <= 32'h00279793; + mem['h0A47] <= 32'h00E787B3; + mem['h0A48] <= 32'h00379793; + mem['h0A49] <= 32'h00078713; + mem['h0A4A] <= 32'hFEE44783; + mem['h0A4B] <= 32'h00F707B3; + mem['h0A4C] <= 32'h00279713; + mem['h0A4D] <= 32'h052007B7; + mem['h0A4E] <= 32'h00F707B3; + mem['h0A4F] <= 32'h00200713; + mem['h0A50] <= 32'h00E7A023; + mem['h0A51] <= 32'hFEE44703; + mem['h0A52] <= 32'h01C00793; + mem['h0A53] <= 32'h02F71263; + mem['h0A54] <= 32'hFED44783; + mem['h0A55] <= 32'h00978713; + mem['h0A56] <= 32'hFEF44783; + mem['h0A57] <= 32'h00F75A63; + mem['h0A58] <= 32'hFEF44703; + mem['h0A59] <= 32'hFED44783; + mem['h0A5A] <= 32'h01178793; + mem['h0A5B] <= 32'h0AE7DE63; + mem['h0A5C] <= 32'hFEE44703; + mem['h0A5D] <= 32'h01C00793; + mem['h0A5E] <= 32'h02E7F863; + mem['h0A5F] <= 32'hFEE44703; + mem['h0A60] <= 32'h01F00793; + mem['h0A61] <= 32'h02E7E263; + mem['h0A62] <= 32'hFEF44703; + mem['h0A63] <= 32'hFED44783; + mem['h0A64] <= 32'h00E78793; + mem['h0A65] <= 32'h08F70A63; + mem['h0A66] <= 32'hFEF44703; + mem['h0A67] <= 32'hFED44783; + mem['h0A68] <= 32'h00A78793; + mem['h0A69] <= 32'h08F70263; + mem['h0A6A] <= 32'hFEE44703; + mem['h0A6B] <= 32'h02000793; + mem['h0A6C] <= 32'h02F71263; + mem['h0A6D] <= 32'hFED44783; + mem['h0A6E] <= 32'h00A78713; + mem['h0A6F] <= 32'hFEF44783; + mem['h0A70] <= 32'h00F75A63; + mem['h0A71] <= 32'hFEF44703; + mem['h0A72] <= 32'hFED44783; + mem['h0A73] <= 32'h00D78793; + mem['h0A74] <= 32'h04E7DC63; + mem['h0A75] <= 32'hFEE44703; + mem['h0A76] <= 32'h01E00793; + mem['h0A77] <= 32'h00F71A63; + mem['h0A78] <= 32'hFEF44703; + mem['h0A79] <= 32'hFED44783; + mem['h0A7A] <= 32'h00F78793; + mem['h0A7B] <= 32'h02F70E63; + mem['h0A7C] <= 32'hFEE44703; + mem['h0A7D] <= 32'h01F00793; + mem['h0A7E] <= 32'h00F71A63; + mem['h0A7F] <= 32'hFEF44703; + mem['h0A80] <= 32'hFED44783; + mem['h0A81] <= 32'h01078793; + mem['h0A82] <= 32'h02F70063; + mem['h0A83] <= 32'hFEE44703; + mem['h0A84] <= 32'h02000793; + mem['h0A85] <= 32'h04F71463; + mem['h0A86] <= 32'hFEF44703; + mem['h0A87] <= 32'hFED44783; + mem['h0A88] <= 32'h01178793; + mem['h0A89] <= 32'h02F71C63; + mem['h0A8A] <= 32'hFEF44703; + mem['h0A8B] <= 32'h00070793; + mem['h0A8C] <= 32'h00279793; + mem['h0A8D] <= 32'h00E787B3; + mem['h0A8E] <= 32'h00379793; + mem['h0A8F] <= 32'h00078713; + mem['h0A90] <= 32'hFEE44783; + mem['h0A91] <= 32'h00F707B3; + mem['h0A92] <= 32'h00279713; + mem['h0A93] <= 32'h052007B7; + mem['h0A94] <= 32'h00F707B3; + mem['h0A95] <= 32'h00400713; + mem['h0A96] <= 32'h00E7A023; + mem['h0A97] <= 32'hFEE44783; + mem['h0A98] <= 32'h00178793; + mem['h0A99] <= 32'hFEF40723; + mem['h0A9A] <= 32'hFEE44703; + mem['h0A9B] <= 32'h02700793; + mem['h0A9C] <= 32'h88E7F2E3; + mem['h0A9D] <= 32'hFEF44783; + mem['h0A9E] <= 32'h00178793; + mem['h0A9F] <= 32'hFEF407A3; + mem['h0AA0] <= 32'hFEF44703; + mem['h0AA1] <= 32'h01D00793; + mem['h0AA2] <= 32'h86E7F2E3; + mem['h0AA3] <= 32'hFDC42703; + mem['h0AA4] <= 32'h00300793; + mem['h0AA5] <= 32'h02F71A63; + mem['h0AA6] <= 32'h00300613; + mem['h0AA7] <= 32'h01500593; + mem['h0AA8] <= 32'h00500513; + mem['h0AA9] <= 32'h8A8FF0EF; + mem['h0AAA] <= 32'h00300613; + mem['h0AAB] <= 32'h01500593; + mem['h0AAC] <= 32'h00F00513; + mem['h0AAD] <= 32'h898FF0EF; + mem['h0AAE] <= 32'h00300613; + mem['h0AAF] <= 32'h01500593; + mem['h0AB0] <= 32'h01900513; + mem['h0AB1] <= 32'h888FF0EF; + mem['h0AB2] <= 32'hFDC42703; + mem['h0AB3] <= 32'h00200793; + mem['h0AB4] <= 32'h02F71A63; + mem['h0AB5] <= 32'h00300613; + mem['h0AB6] <= 32'h01500593; + mem['h0AB7] <= 32'h00500513; + mem['h0AB8] <= 32'h86CFF0EF; + mem['h0AB9] <= 32'h00300613; + mem['h0ABA] <= 32'h01500593; + mem['h0ABB] <= 32'h00F00513; + mem['h0ABC] <= 32'h85CFF0EF; + mem['h0ABD] <= 32'h00900613; + mem['h0ABE] <= 32'h01500593; + mem['h0ABF] <= 32'h01900513; + mem['h0AC0] <= 32'h84CFF0EF; + mem['h0AC1] <= 32'hFDC42703; + mem['h0AC2] <= 32'h00100793; + mem['h0AC3] <= 32'h02F71A63; + mem['h0AC4] <= 32'h00300613; + mem['h0AC5] <= 32'h01500593; + mem['h0AC6] <= 32'h00500513; + mem['h0AC7] <= 32'h830FF0EF; + mem['h0AC8] <= 32'h00900613; + mem['h0AC9] <= 32'h01500593; + mem['h0ACA] <= 32'h00F00513; + mem['h0ACB] <= 32'h820FF0EF; + mem['h0ACC] <= 32'h00900613; + mem['h0ACD] <= 32'h01500593; + mem['h0ACE] <= 32'h01900513; + mem['h0ACF] <= 32'h810FF0EF; + mem['h0AD0] <= 32'h00000013; + mem['h0AD1] <= 32'h02C12083; + mem['h0AD2] <= 32'h02812403; + mem['h0AD3] <= 32'h03010113; + mem['h0AD4] <= 32'h00008067; + mem['h0AD5] <= 32'hFE010113; + mem['h0AD6] <= 32'h00812E23; + mem['h0AD7] <= 32'h02010413; + mem['h0AD8] <= 32'h00800793; + mem['h0AD9] <= 32'hFEF406A3; + mem['h0ADA] <= 32'hFE0407A3; + mem['h0ADB] <= 32'h4B00006F; + mem['h0ADC] <= 32'hFE040723; + mem['h0ADD] <= 32'h4900006F; + mem['h0ADE] <= 32'hFEF44703; + mem['h0ADF] <= 32'h00070793; + mem['h0AE0] <= 32'h00279793; + mem['h0AE1] <= 32'h00E787B3; + mem['h0AE2] <= 32'h00379793; + mem['h0AE3] <= 32'h00078713; + mem['h0AE4] <= 32'hFEE44783; + mem['h0AE5] <= 32'h00F707B3; + mem['h0AE6] <= 32'h00279713; + mem['h0AE7] <= 32'h052007B7; + mem['h0AE8] <= 32'h00F707B3; + mem['h0AE9] <= 32'h0007A023; + mem['h0AEA] <= 32'hFEF44703; + mem['h0AEB] <= 32'hFED44783; + mem['h0AEC] <= 32'h00F71E63; + mem['h0AED] <= 32'hFEE44703; + mem['h0AEE] <= 32'h00400793; + mem['h0AEF] <= 32'h00E7F863; + mem['h0AF0] <= 32'hFEE44703; + mem['h0AF1] <= 32'h00700793; + mem['h0AF2] <= 32'h02E7F663; + mem['h0AF3] <= 32'hFEE44703; + mem['h0AF4] <= 32'h00600793; + mem['h0AF5] <= 32'h04F71A63; + mem['h0AF6] <= 32'hFEF44703; + mem['h0AF7] <= 32'hFED44783; + mem['h0AF8] <= 32'h04F76463; + mem['h0AF9] <= 32'hFEF44703; + mem['h0AFA] <= 32'hFED44783; + mem['h0AFB] <= 32'h00478793; + mem['h0AFC] <= 32'h02E7CC63; + mem['h0AFD] <= 32'hFEF44703; + mem['h0AFE] <= 32'h00070793; + mem['h0AFF] <= 32'h00279793; + mem['h0B00] <= 32'h00E787B3; + mem['h0B01] <= 32'h00379793; + mem['h0B02] <= 32'h00078713; + mem['h0B03] <= 32'hFEE44783; + mem['h0B04] <= 32'h00F707B3; + mem['h0B05] <= 32'h00279713; + mem['h0B06] <= 32'h052007B7; + mem['h0B07] <= 32'h00F707B3; + mem['h0B08] <= 32'h00300713; + mem['h0B09] <= 32'h00E7A023; + mem['h0B0A] <= 32'hFEF44703; + mem['h0B0B] <= 32'hFED44783; + mem['h0B0C] <= 32'h00278793; + mem['h0B0D] <= 32'h00F71E63; + mem['h0B0E] <= 32'hFEE44703; + mem['h0B0F] <= 32'h00800793; + mem['h0B10] <= 32'h00E7F863; + mem['h0B11] <= 32'hFEE44703; + mem['h0B12] <= 32'h00B00793; + mem['h0B13] <= 32'h02E7FC63; + mem['h0B14] <= 32'hFEE44703; + mem['h0B15] <= 32'h00900793; + mem['h0B16] <= 32'h00F70863; + mem['h0B17] <= 32'hFEE44703; + mem['h0B18] <= 32'h00B00793; + mem['h0B19] <= 32'h04F71A63; + mem['h0B1A] <= 32'hFEF44703; + mem['h0B1B] <= 32'hFED44783; + mem['h0B1C] <= 32'h04F76463; + mem['h0B1D] <= 32'hFEF44703; + mem['h0B1E] <= 32'hFED44783; + mem['h0B1F] <= 32'h00478793; + mem['h0B20] <= 32'h02E7CC63; + mem['h0B21] <= 32'hFEF44703; + mem['h0B22] <= 32'h00070793; + mem['h0B23] <= 32'h00279793; + mem['h0B24] <= 32'h00E787B3; + mem['h0B25] <= 32'h00379793; + mem['h0B26] <= 32'h00078713; + mem['h0B27] <= 32'hFEE44783; + mem['h0B28] <= 32'h00F707B3; + mem['h0B29] <= 32'h00279713; + mem['h0B2A] <= 32'h052007B7; + mem['h0B2B] <= 32'h00F707B3; + mem['h0B2C] <= 32'h00300713; + mem['h0B2D] <= 32'h00E7A023; + mem['h0B2E] <= 32'hFEF44703; + mem['h0B2F] <= 32'hFED44783; + mem['h0B30] <= 32'h00F70A63; + mem['h0B31] <= 32'hFEF44703; + mem['h0B32] <= 32'hFED44783; + mem['h0B33] <= 32'h00478793; + mem['h0B34] <= 32'h00F71E63; + mem['h0B35] <= 32'hFEE44703; + mem['h0B36] <= 32'h00C00793; + mem['h0B37] <= 32'h00E7F863; + mem['h0B38] <= 32'hFEE44703; + mem['h0B39] <= 32'h00F00793; + mem['h0B3A] <= 32'h04E7FA63; + mem['h0B3B] <= 32'hFEE44703; + mem['h0B3C] <= 32'h00D00793; + mem['h0B3D] <= 32'h02F71063; + mem['h0B3E] <= 32'hFEF44703; + mem['h0B3F] <= 32'hFED44783; + mem['h0B40] <= 32'h00F76A63; + mem['h0B41] <= 32'hFEF44703; + mem['h0B42] <= 32'hFED44783; + mem['h0B43] <= 32'h00478793; + mem['h0B44] <= 32'h02E7D663; + mem['h0B45] <= 32'hFEF44703; + mem['h0B46] <= 32'hFED44783; + mem['h0B47] <= 32'h00278793; + mem['h0B48] <= 32'h04F71863; + mem['h0B49] <= 32'hFEE44703; + mem['h0B4A] <= 32'h00C00793; + mem['h0B4B] <= 32'h04E7F263; + mem['h0B4C] <= 32'hFEE44703; + mem['h0B4D] <= 32'h00E00793; + mem['h0B4E] <= 32'h02E7EC63; + mem['h0B4F] <= 32'hFEF44703; + mem['h0B50] <= 32'h00070793; + mem['h0B51] <= 32'h00279793; + mem['h0B52] <= 32'h00E787B3; + mem['h0B53] <= 32'h00379793; + mem['h0B54] <= 32'h00078713; + mem['h0B55] <= 32'hFEE44783; + mem['h0B56] <= 32'h00F707B3; + mem['h0B57] <= 32'h00279713; + mem['h0B58] <= 32'h052007B7; + mem['h0B59] <= 32'h00F707B3; + mem['h0B5A] <= 32'h00300713; + mem['h0B5B] <= 32'h00E7A023; + mem['h0B5C] <= 32'hFEF44703; + mem['h0B5D] <= 32'hFED44783; + mem['h0B5E] <= 32'h00F70A63; + mem['h0B5F] <= 32'hFEF44703; + mem['h0B60] <= 32'hFED44783; + mem['h0B61] <= 32'h00478793; + mem['h0B62] <= 32'h00F71E63; + mem['h0B63] <= 32'hFEE44703; + mem['h0B64] <= 32'h01300793; + mem['h0B65] <= 32'h00E7F863; + mem['h0B66] <= 32'hFEE44703; + mem['h0B67] <= 32'h01600793; + mem['h0B68] <= 32'h04E7FA63; + mem['h0B69] <= 32'hFEE44703; + mem['h0B6A] <= 32'h01400793; + mem['h0B6B] <= 32'h02F71063; + mem['h0B6C] <= 32'hFEF44703; + mem['h0B6D] <= 32'hFED44783; + mem['h0B6E] <= 32'h00F76A63; + mem['h0B6F] <= 32'hFEF44703; + mem['h0B70] <= 32'hFED44783; + mem['h0B71] <= 32'h00478793; + mem['h0B72] <= 32'h02E7D663; + mem['h0B73] <= 32'hFEF44703; + mem['h0B74] <= 32'hFED44783; + mem['h0B75] <= 32'h00278793; + mem['h0B76] <= 32'h04F71863; + mem['h0B77] <= 32'hFEE44703; + mem['h0B78] <= 32'h01300793; + mem['h0B79] <= 32'h04E7F263; + mem['h0B7A] <= 32'hFEE44703; + mem['h0B7B] <= 32'h01500793; + mem['h0B7C] <= 32'h02E7EC63; + mem['h0B7D] <= 32'hFEF44703; + mem['h0B7E] <= 32'h00070793; + mem['h0B7F] <= 32'h00279793; + mem['h0B80] <= 32'h00E787B3; + mem['h0B81] <= 32'h00379793; + mem['h0B82] <= 32'h00078713; + mem['h0B83] <= 32'hFEE44783; + mem['h0B84] <= 32'h00F707B3; + mem['h0B85] <= 32'h00279713; + mem['h0B86] <= 32'h052007B7; + mem['h0B87] <= 32'h00F707B3; + mem['h0B88] <= 32'h00300713; + mem['h0B89] <= 32'h00E7A023; + mem['h0B8A] <= 32'hFEF44703; + mem['h0B8B] <= 32'hFED44783; + mem['h0B8C] <= 32'h00278793; + mem['h0B8D] <= 32'h00F71863; + mem['h0B8E] <= 32'hFEE44703; + mem['h0B8F] <= 32'h01900793; + mem['h0B90] <= 32'h04F70A63; + mem['h0B91] <= 32'hFEF44703; + mem['h0B92] <= 32'hFED44783; + mem['h0B93] <= 32'h00378793; + mem['h0B94] <= 32'h00F71863; + mem['h0B95] <= 32'hFEE44703; + mem['h0B96] <= 32'h01A00793; + mem['h0B97] <= 32'h02F70C63; + mem['h0B98] <= 32'hFEE44703; + mem['h0B99] <= 32'h01800793; + mem['h0B9A] <= 32'h00F70863; + mem['h0B9B] <= 32'hFEE44703; + mem['h0B9C] <= 32'h01B00793; + mem['h0B9D] <= 32'h04F71A63; + mem['h0B9E] <= 32'hFEF44703; + mem['h0B9F] <= 32'hFED44783; + mem['h0BA0] <= 32'h04F76463; + mem['h0BA1] <= 32'hFEF44703; + mem['h0BA2] <= 32'hFED44783; + mem['h0BA3] <= 32'h00478793; + mem['h0BA4] <= 32'h02E7CC63; + mem['h0BA5] <= 32'hFEF44703; + mem['h0BA6] <= 32'h00070793; + mem['h0BA7] <= 32'h00279793; + mem['h0BA8] <= 32'h00E787B3; + mem['h0BA9] <= 32'h00379793; + mem['h0BAA] <= 32'h00078713; + mem['h0BAB] <= 32'hFEE44783; + mem['h0BAC] <= 32'h00F707B3; + mem['h0BAD] <= 32'h00279713; + mem['h0BAE] <= 32'h052007B7; + mem['h0BAF] <= 32'h00F707B3; + mem['h0BB0] <= 32'h00300713; + mem['h0BB1] <= 32'h00E7A023; + mem['h0BB2] <= 32'hFEE44703; + mem['h0BB3] <= 32'h01F00793; + mem['h0BB4] <= 32'h02F71063; + mem['h0BB5] <= 32'hFED44703; + mem['h0BB6] <= 32'hFEF44783; + mem['h0BB7] <= 32'h00F77A63; + mem['h0BB8] <= 32'hFEF44703; + mem['h0BB9] <= 32'hFED44783; + mem['h0BBA] <= 32'h00378793; + mem['h0BBB] <= 32'h06E7D063; + mem['h0BBC] <= 32'hFEF44703; + mem['h0BBD] <= 32'hFED44783; + mem['h0BBE] <= 32'h00F70A63; + mem['h0BBF] <= 32'hFEF44703; + mem['h0BC0] <= 32'hFED44783; + mem['h0BC1] <= 32'h00478793; + mem['h0BC2] <= 32'h00F71E63; + mem['h0BC3] <= 32'hFEE44703; + mem['h0BC4] <= 32'h01C00793; + mem['h0BC5] <= 32'h00E7F863; + mem['h0BC6] <= 32'hFEE44703; + mem['h0BC7] <= 32'h01E00793; + mem['h0BC8] <= 32'h02E7F663; + mem['h0BC9] <= 32'hFEE44703; + mem['h0BCA] <= 32'h01D00793; + mem['h0BCB] <= 32'h04F71A63; + mem['h0BCC] <= 32'hFEF44703; + mem['h0BCD] <= 32'hFED44783; + mem['h0BCE] <= 32'h04F76463; + mem['h0BCF] <= 32'hFEF44703; + mem['h0BD0] <= 32'hFED44783; + mem['h0BD1] <= 32'h00478793; + mem['h0BD2] <= 32'h02E7CC63; + mem['h0BD3] <= 32'hFEF44703; + mem['h0BD4] <= 32'h00070793; + mem['h0BD5] <= 32'h00279793; + mem['h0BD6] <= 32'h00E787B3; + mem['h0BD7] <= 32'h00379793; + mem['h0BD8] <= 32'h00078713; + mem['h0BD9] <= 32'hFEE44783; + mem['h0BDA] <= 32'h00F707B3; + mem['h0BDB] <= 32'h00279713; + mem['h0BDC] <= 32'h052007B7; + mem['h0BDD] <= 32'h00F707B3; + mem['h0BDE] <= 32'h00300713; + mem['h0BDF] <= 32'h00E7A023; + mem['h0BE0] <= 32'hFEE44703; + mem['h0BE1] <= 32'h02100793; + mem['h0BE2] <= 32'h02F71063; + mem['h0BE3] <= 32'hFEF44703; + mem['h0BE4] <= 32'hFED44783; + mem['h0BE5] <= 32'h00F76A63; + mem['h0BE6] <= 32'hFEF44703; + mem['h0BE7] <= 32'hFED44783; + mem['h0BE8] <= 32'h00278793; + mem['h0BE9] <= 32'h02E7D063; + mem['h0BEA] <= 32'hFEE44703; + mem['h0BEB] <= 32'h02100793; + mem['h0BEC] <= 32'h04F71463; + mem['h0BED] <= 32'hFEF44703; + mem['h0BEE] <= 32'hFED44783; + mem['h0BEF] <= 32'h00478793; + mem['h0BF0] <= 32'h02F71C63; + mem['h0BF1] <= 32'hFEF44703; + mem['h0BF2] <= 32'h00070793; + mem['h0BF3] <= 32'h00279793; + mem['h0BF4] <= 32'h00E787B3; + mem['h0BF5] <= 32'h00379793; + mem['h0BF6] <= 32'h00078713; + mem['h0BF7] <= 32'hFEE44783; + mem['h0BF8] <= 32'h00F707B3; + mem['h0BF9] <= 32'h00279713; + mem['h0BFA] <= 32'h052007B7; + mem['h0BFB] <= 32'h00F707B3; + mem['h0BFC] <= 32'h00300713; + mem['h0BFD] <= 32'h00E7A023; + mem['h0BFE] <= 32'hFEE44783; + mem['h0BFF] <= 32'h00178793; + mem['h0C00] <= 32'hFEF40723; + mem['h0C01] <= 32'hFEE44703; + mem['h0C02] <= 32'h02700793; + mem['h0C03] <= 32'hB6E7F6E3; + mem['h0C04] <= 32'hFEF44783; + mem['h0C05] <= 32'h00178793; + mem['h0C06] <= 32'hFEF407A3; + mem['h0C07] <= 32'hFEF44703; + mem['h0C08] <= 32'h01600793; + mem['h0C09] <= 32'hB4E7F6E3; + mem['h0C0A] <= 32'h00000013; + mem['h0C0B] <= 32'h00000013; + mem['h0C0C] <= 32'h01C12403; + mem['h0C0D] <= 32'h02010113; + mem['h0C0E] <= 32'h00008067; + mem['h0C0F] <= 32'hFE010113; + mem['h0C10] <= 32'h00812E23; + mem['h0C11] <= 32'h02010413; + mem['h0C12] <= 32'h000017B7; + mem['h0C13] <= 32'hFFF78793; + mem['h0C14] <= 32'hFEF42623; + mem['h0C15] <= 32'hFE0405A3; + mem['h0C16] <= 32'h2A90006F; + mem['h0C17] <= 32'hFE040523; + mem['h0C18] <= 32'h2890006F; + mem['h0C19] <= 32'hFE0404A3; + mem['h0C1A] <= 32'h2690006F; + mem['h0C1B] <= 32'hFEB44783; + mem['h0C1C] <= 32'h04079863; + mem['h0C1D] <= 32'hFEA44783; + mem['h0C1E] <= 32'h00078863; + mem['h0C1F] <= 32'hFEA44703; + mem['h0C20] <= 32'h00100793; + mem['h0C21] <= 32'h00F71863; + mem['h0C22] <= 32'h22200793; + mem['h0C23] <= 32'hFEF42623; + mem['h0C24] <= 32'h2050006F; + mem['h0C25] <= 32'hFE944703; + mem['h0C26] <= 32'h00E00793; + mem['h0C27] <= 32'h00F70863; + mem['h0C28] <= 32'hFE944703; + mem['h0C29] <= 32'h00F00793; + mem['h0C2A] <= 32'h00F71863; + mem['h0C2B] <= 32'h11100793; + mem['h0C2C] <= 32'hFEF42623; + mem['h0C2D] <= 32'h1E10006F; + mem['h0C2E] <= 32'hFE042623; + mem['h0C2F] <= 32'h1D90006F; + mem['h0C30] <= 32'hFEB44703; + mem['h0C31] <= 32'h00100793; + mem['h0C32] <= 32'h04F71C63; + mem['h0C33] <= 32'hFEA44783; + mem['h0C34] <= 32'h00078863; + mem['h0C35] <= 32'hFEA44703; + mem['h0C36] <= 32'h00100793; + mem['h0C37] <= 32'h00F71863; + mem['h0C38] <= 32'h08000793; + mem['h0C39] <= 32'hFEF42623; + mem['h0C3A] <= 32'h1AD0006F; + mem['h0C3B] <= 32'hFE944703; + mem['h0C3C] <= 32'h00E00793; + mem['h0C3D] <= 32'h00F70863; + mem['h0C3E] <= 32'hFE944703; + mem['h0C3F] <= 32'h00F00793; + mem['h0C40] <= 32'h00F71863; + mem['h0C41] <= 32'h08000793; + mem['h0C42] <= 32'hFEF42623; + mem['h0C43] <= 32'h1890006F; + mem['h0C44] <= 32'h000017B7; + mem['h0C45] <= 32'h8B478793; + mem['h0C46] <= 32'hFEF42623; + mem['h0C47] <= 32'h1790006F; + mem['h0C48] <= 32'hFEB44703; + mem['h0C49] <= 32'h00200793; + mem['h0C4A] <= 32'h04F71A63; + mem['h0C4B] <= 32'hFEA44783; + mem['h0C4C] <= 32'h00078863; + mem['h0C4D] <= 32'hFEA44703; + mem['h0C4E] <= 32'h00100793; + mem['h0C4F] <= 32'h00F71863; + mem['h0C50] <= 32'h00B00793; + mem['h0C51] <= 32'hFEF42623; + mem['h0C52] <= 32'h14D0006F; + mem['h0C53] <= 32'hFE944703; + mem['h0C54] <= 32'h00E00793; + mem['h0C55] <= 32'h00F70863; + mem['h0C56] <= 32'hFE944703; + mem['h0C57] <= 32'h00F00793; + mem['h0C58] <= 32'h00F71863; + mem['h0C59] <= 32'h00B00793; + mem['h0C5A] <= 32'hFEF42623; + mem['h0C5B] <= 32'h1290006F; + mem['h0C5C] <= 32'h09F00793; + mem['h0C5D] <= 32'hFEF42623; + mem['h0C5E] <= 32'h11D0006F; + mem['h0C5F] <= 32'hFEB44703; + mem['h0C60] <= 32'h00300793; + mem['h0C61] <= 32'h06F71063; + mem['h0C62] <= 32'hFEA44783; + mem['h0C63] <= 32'h00078863; + mem['h0C64] <= 32'hFEA44703; + mem['h0C65] <= 32'h00100793; + mem['h0C66] <= 32'h00F71A63; + mem['h0C67] <= 32'h000017B7; + mem['h0C68] <= 32'hA0078793; + mem['h0C69] <= 32'hFEF42623; + mem['h0C6A] <= 32'h0ED0006F; + mem['h0C6B] <= 32'hFE944703; + mem['h0C6C] <= 32'h00E00793; + mem['h0C6D] <= 32'h00F70863; + mem['h0C6E] <= 32'hFE944703; + mem['h0C6F] <= 32'h00F00793; + mem['h0C70] <= 32'h00F71A63; + mem['h0C71] <= 32'h000017B7; + mem['h0C72] <= 32'hB0078793; + mem['h0C73] <= 32'hFEF42623; + mem['h0C74] <= 32'h0C50006F; + mem['h0C75] <= 32'h000017B7; + mem['h0C76] <= 32'hF0078793; + mem['h0C77] <= 32'hFEF42623; + mem['h0C78] <= 32'h0B50006F; + mem['h0C79] <= 32'hFEB44703; + mem['h0C7A] <= 32'h00400793; + mem['h0C7B] <= 32'h06F71063; + mem['h0C7C] <= 32'hFEA44783; + mem['h0C7D] <= 32'h00078863; + mem['h0C7E] <= 32'hFEA44703; + mem['h0C7F] <= 32'h00100793; + mem['h0C80] <= 32'h00F71A63; + mem['h0C81] <= 32'h000017B7; + mem['h0C82] <= 32'hFD878793; + mem['h0C83] <= 32'hFEF42623; + mem['h0C84] <= 32'h0850006F; + mem['h0C85] <= 32'hFE944703; + mem['h0C86] <= 32'h00E00793; + mem['h0C87] <= 32'h00F70863; + mem['h0C88] <= 32'hFE944703; + mem['h0C89] <= 32'h00F00793; + mem['h0C8A] <= 32'h00F71A63; + mem['h0C8B] <= 32'h000017B7; + mem['h0C8C] <= 32'hFD478793; + mem['h0C8D] <= 32'hFEF42623; + mem['h0C8E] <= 32'h05D0006F; + mem['h0C8F] <= 32'h000017B7; + mem['h0C90] <= 32'hFD278793; + mem['h0C91] <= 32'hFEF42623; + mem['h0C92] <= 32'h04D0006F; + mem['h0C93] <= 32'hFEB44703; + mem['h0C94] <= 32'h00500793; + mem['h0C95] <= 32'h04F71A63; + mem['h0C96] <= 32'hFEA44783; + mem['h0C97] <= 32'h00078863; + mem['h0C98] <= 32'hFEA44703; + mem['h0C99] <= 32'h00100793; + mem['h0C9A] <= 32'h00F71863; + mem['h0C9B] <= 32'h75D00793; + mem['h0C9C] <= 32'hFEF42623; + mem['h0C9D] <= 32'h0210006F; + mem['h0C9E] <= 32'hFE944703; + mem['h0C9F] <= 32'h00E00793; + mem['h0CA0] <= 32'h00F70863; + mem['h0CA1] <= 32'hFE944703; + mem['h0CA2] <= 32'h00F00793; + mem['h0CA3] <= 32'h00F71863; + mem['h0CA4] <= 32'h74D00793; + mem['h0CA5] <= 32'hFEF42623; + mem['h0CA6] <= 32'h7FC0006F; + mem['h0CA7] <= 32'h70D00793; + mem['h0CA8] <= 32'hFEF42623; + mem['h0CA9] <= 32'h7F00006F; + mem['h0CAA] <= 32'hFEB44703; + mem['h0CAB] <= 32'h00600793; + mem['h0CAC] <= 32'h06F71063; + mem['h0CAD] <= 32'hFEA44783; + mem['h0CAE] <= 32'h00078863; + mem['h0CAF] <= 32'hFEA44703; + mem['h0CB0] <= 32'h00100793; + mem['h0CB1] <= 32'h00F71A63; + mem['h0CB2] <= 32'h000017B7; + mem['h0CB3] <= 32'hFAF78793; + mem['h0CB4] <= 32'hFEF42623; + mem['h0CB5] <= 32'h7C00006F; + mem['h0CB6] <= 32'hFE944703; + mem['h0CB7] <= 32'h00E00793; + mem['h0CB8] <= 32'h00F70863; + mem['h0CB9] <= 32'hFE944703; + mem['h0CBA] <= 32'h00F00793; + mem['h0CBB] <= 32'h00F71A63; + mem['h0CBC] <= 32'h000017B7; + mem['h0CBD] <= 32'hF6F78793; + mem['h0CBE] <= 32'hFEF42623; + mem['h0CBF] <= 32'h7980006F; + mem['h0CC0] <= 32'h000017B7; + mem['h0CC1] <= 32'hF0F78793; + mem['h0CC2] <= 32'hFEF42623; + mem['h0CC3] <= 32'h7880006F; + mem['h0CC4] <= 32'hFEB44703; + mem['h0CC5] <= 32'h00700793; + mem['h0CC6] <= 32'h06F71063; + mem['h0CC7] <= 32'hFEA44783; + mem['h0CC8] <= 32'h00078863; + mem['h0CC9] <= 32'hFEA44703; + mem['h0CCA] <= 32'h00100793; + mem['h0CCB] <= 32'h00F71A63; + mem['h0CCC] <= 32'h000017B7; + mem['h0CCD] <= 32'hFB078793; + mem['h0CCE] <= 32'hFEF42623; + mem['h0CCF] <= 32'h7580006F; + mem['h0CD0] <= 32'hFE944703; + mem['h0CD1] <= 32'h00E00793; + mem['h0CD2] <= 32'h00F70863; + mem['h0CD3] <= 32'hFE944703; + mem['h0CD4] <= 32'h00F00793; + mem['h0CD5] <= 32'h00F71A63; + mem['h0CD6] <= 32'h000017B7; + mem['h0CD7] <= 32'hF9078793; + mem['h0CD8] <= 32'hFEF42623; + mem['h0CD9] <= 32'h7300006F; + mem['h0CDA] <= 32'h000017B7; + mem['h0CDB] <= 32'hF6378793; + mem['h0CDC] <= 32'hFEF42623; + mem['h0CDD] <= 32'h7200006F; + mem['h0CDE] <= 32'hFEB44703; + mem['h0CDF] <= 32'h00800793; + mem['h0CE0] <= 32'h00F71863; + mem['h0CE1] <= 32'h0A000793; + mem['h0CE2] <= 32'hFEF42623; + mem['h0CE3] <= 32'h7080006F; + mem['h0CE4] <= 32'hFEB44703; + mem['h0CE5] <= 32'h00900793; + mem['h0CE6] <= 32'h04F71E63; + mem['h0CE7] <= 32'hFE944703; + mem['h0CE8] <= 32'h00E00793; + mem['h0CE9] <= 32'h00F70863; + mem['h0CEA] <= 32'hFE944703; + mem['h0CEB] <= 32'h00F00793; + mem['h0CEC] <= 32'h00F71A63; + mem['h0CED] <= 32'h000017B7; + mem['h0CEE] <= 32'hCCC78793; + mem['h0CEF] <= 32'hFEF42623; + mem['h0CF0] <= 32'h6D40006F; + mem['h0CF1] <= 32'hFEA44783; + mem['h0CF2] <= 32'h00078863; + mem['h0CF3] <= 32'hFEA44703; + mem['h0CF4] <= 32'h00100793; + mem['h0CF5] <= 32'h00F71863; + mem['h0CF6] <= 32'h11100793; + mem['h0CF7] <= 32'hFEF42623; + mem['h0CF8] <= 32'h6B40006F; + mem['h0CF9] <= 32'h000017B7; + mem['h0CFA] <= 32'hAAA78793; + mem['h0CFB] <= 32'hFEF42623; + mem['h0CFC] <= 32'h6A40006F; + mem['h0CFD] <= 32'hFEB44703; + mem['h0CFE] <= 32'h00A00793; + mem['h0CFF] <= 32'h04F71A63; + mem['h0D00] <= 32'hFEA44783; + mem['h0D01] <= 32'h00078863; + mem['h0D02] <= 32'hFEA44703; + mem['h0D03] <= 32'h00100793; + mem['h0D04] <= 32'h00F71863; + mem['h0D05] <= 32'h00B00793; + mem['h0D06] <= 32'hFEF42623; + mem['h0D07] <= 32'h6780006F; + mem['h0D08] <= 32'hFE944703; + mem['h0D09] <= 32'h00E00793; + mem['h0D0A] <= 32'h00F70863; + mem['h0D0B] <= 32'hFE944703; + mem['h0D0C] <= 32'h00F00793; + mem['h0D0D] <= 32'h00F71863; + mem['h0D0E] <= 32'h00B00793; + mem['h0D0F] <= 32'hFEF42623; + mem['h0D10] <= 32'h6540006F; + mem['h0D11] <= 32'h00700793; + mem['h0D12] <= 32'hFEF42623; + mem['h0D13] <= 32'h6480006F; + mem['h0D14] <= 32'hFEB44703; + mem['h0D15] <= 32'h00B00793; + mem['h0D16] <= 32'h04F71A63; + mem['h0D17] <= 32'hFEA44783; + mem['h0D18] <= 32'h00078863; + mem['h0D19] <= 32'hFEA44703; + mem['h0D1A] <= 32'h00100793; + mem['h0D1B] <= 32'h00F71863; + mem['h0D1C] <= 32'h00B00793; + mem['h0D1D] <= 32'hFEF42623; + mem['h0D1E] <= 32'h61C0006F; + mem['h0D1F] <= 32'hFE944703; + mem['h0D20] <= 32'h00E00793; + mem['h0D21] <= 32'h00F70863; + mem['h0D22] <= 32'hFE944703; + mem['h0D23] <= 32'h00F00793; + mem['h0D24] <= 32'h00F71863; + mem['h0D25] <= 32'h00B00793; + mem['h0D26] <= 32'hFEF42623; + mem['h0D27] <= 32'h5F80006F; + mem['h0D28] <= 32'h06C00793; + mem['h0D29] <= 32'hFEF42623; + mem['h0D2A] <= 32'h5EC0006F; + mem['h0D2B] <= 32'hFEB44703; + mem['h0D2C] <= 32'h00C00793; + mem['h0D2D] <= 32'h5AF71263; + mem['h0D2E] <= 32'hFE944703; + mem['h0D2F] <= 32'h00200793; + mem['h0D30] <= 32'h00F71663; + mem['h0D31] <= 32'hFEA44783; + mem['h0D32] <= 32'h56078A63; + mem['h0D33] <= 32'hFE944703; + mem['h0D34] <= 32'h00700793; + mem['h0D35] <= 32'h00F71663; + mem['h0D36] <= 32'hFEA44783; + mem['h0D37] <= 32'h56078063; + mem['h0D38] <= 32'hFE944703; + mem['h0D39] <= 32'h00800793; + mem['h0D3A] <= 32'h00F71663; + mem['h0D3B] <= 32'hFEA44783; + mem['h0D3C] <= 32'h54078663; + mem['h0D3D] <= 32'hFE944703; + mem['h0D3E] <= 32'h00D00793; + mem['h0D3F] <= 32'h00F71663; + mem['h0D40] <= 32'hFEA44783; + mem['h0D41] <= 32'h52078C63; + mem['h0D42] <= 32'hFE944703; + mem['h0D43] <= 32'h00100793; + mem['h0D44] <= 32'h00F71863; + mem['h0D45] <= 32'hFEA44703; + mem['h0D46] <= 32'h00100793; + mem['h0D47] <= 32'h52F70063; + mem['h0D48] <= 32'hFE944703; + mem['h0D49] <= 32'h00600793; + mem['h0D4A] <= 32'h00F71863; + mem['h0D4B] <= 32'hFEA44703; + mem['h0D4C] <= 32'h00100793; + mem['h0D4D] <= 32'h50F70463; + mem['h0D4E] <= 32'hFE944703; + mem['h0D4F] <= 32'h00900793; + mem['h0D50] <= 32'h00F71863; + mem['h0D51] <= 32'hFEA44703; + mem['h0D52] <= 32'h00100793; + mem['h0D53] <= 32'h4EF70863; + mem['h0D54] <= 32'hFE944703; + mem['h0D55] <= 32'h00E00793; + mem['h0D56] <= 32'h00F71863; + mem['h0D57] <= 32'hFEA44703; + mem['h0D58] <= 32'h00100793; + mem['h0D59] <= 32'h4CF70C63; + mem['h0D5A] <= 32'hFE944783; + mem['h0D5B] <= 32'h00079863; + mem['h0D5C] <= 32'hFEA44703; + mem['h0D5D] <= 32'h00200793; + mem['h0D5E] <= 32'h4CF70263; + mem['h0D5F] <= 32'hFE944703; + mem['h0D60] <= 32'h00500793; + mem['h0D61] <= 32'h00F71863; + mem['h0D62] <= 32'hFEA44703; + mem['h0D63] <= 32'h00200793; + mem['h0D64] <= 32'h4AF70663; + mem['h0D65] <= 32'hFE944703; + mem['h0D66] <= 32'h00A00793; + mem['h0D67] <= 32'h00F71863; + mem['h0D68] <= 32'hFEA44703; + mem['h0D69] <= 32'h00200793; + mem['h0D6A] <= 32'h48F70A63; + mem['h0D6B] <= 32'hFE944703; + mem['h0D6C] <= 32'h00F00793; + mem['h0D6D] <= 32'h00F71863; + mem['h0D6E] <= 32'hFEA44703; + mem['h0D6F] <= 32'h00200793; + mem['h0D70] <= 32'h46F70E63; + mem['h0D71] <= 32'hFE944703; + mem['h0D72] <= 32'h00200793; + mem['h0D73] <= 32'h00F71863; + mem['h0D74] <= 32'hFEA44703; + mem['h0D75] <= 32'h00300793; + mem['h0D76] <= 32'h46F70263; + mem['h0D77] <= 32'hFE944703; + mem['h0D78] <= 32'h00300793; + mem['h0D79] <= 32'h00F71863; + mem['h0D7A] <= 32'hFEA44703; + mem['h0D7B] <= 32'h00300793; + mem['h0D7C] <= 32'h44F70663; + mem['h0D7D] <= 32'hFE944703; + mem['h0D7E] <= 32'h00400793; + mem['h0D7F] <= 32'h00F71863; + mem['h0D80] <= 32'hFEA44703; + mem['h0D81] <= 32'h00300793; + mem['h0D82] <= 32'h42F70A63; + mem['h0D83] <= 32'hFE944703; + mem['h0D84] <= 32'h00B00793; + mem['h0D85] <= 32'h00F71863; + mem['h0D86] <= 32'hFEA44703; + mem['h0D87] <= 32'h00300793; + mem['h0D88] <= 32'h40F70E63; + mem['h0D89] <= 32'hFE944703; + mem['h0D8A] <= 32'h00C00793; + mem['h0D8B] <= 32'h00F71863; + mem['h0D8C] <= 32'hFEA44703; + mem['h0D8D] <= 32'h00300793; + mem['h0D8E] <= 32'h40F70263; + mem['h0D8F] <= 32'hFE944703; + mem['h0D90] <= 32'h00D00793; + mem['h0D91] <= 32'h00F71863; + mem['h0D92] <= 32'hFEA44703; + mem['h0D93] <= 32'h00300793; + mem['h0D94] <= 32'h3EF70663; + mem['h0D95] <= 32'hFE944703; + mem['h0D96] <= 32'h00200793; + mem['h0D97] <= 32'h00F71863; + mem['h0D98] <= 32'hFEA44703; + mem['h0D99] <= 32'h00400793; + mem['h0D9A] <= 32'h3CF70A63; + mem['h0D9B] <= 32'hFE944703; + mem['h0D9C] <= 32'h00D00793; + mem['h0D9D] <= 32'h00F71863; + mem['h0D9E] <= 32'hFEA44703; + mem['h0D9F] <= 32'h00400793; + mem['h0DA0] <= 32'h3AF70E63; + mem['h0DA1] <= 32'hFE944703; + mem['h0DA2] <= 32'h00200793; + mem['h0DA3] <= 32'h00F71863; + mem['h0DA4] <= 32'hFEA44703; + mem['h0DA5] <= 32'h00500793; + mem['h0DA6] <= 32'h3AF70263; + mem['h0DA7] <= 32'hFE944703; + mem['h0DA8] <= 32'h00D00793; + mem['h0DA9] <= 32'h00F71863; + mem['h0DAA] <= 32'hFEA44703; + mem['h0DAB] <= 32'h00500793; + mem['h0DAC] <= 32'h38F70663; + mem['h0DAD] <= 32'hFE944703; + mem['h0DAE] <= 32'h00100793; + mem['h0DAF] <= 32'h00F71863; + mem['h0DB0] <= 32'hFEA44703; + mem['h0DB1] <= 32'h00600793; + mem['h0DB2] <= 32'h36F70A63; + mem['h0DB3] <= 32'hFE944703; + mem['h0DB4] <= 32'h00E00793; + mem['h0DB5] <= 32'h00F71863; + mem['h0DB6] <= 32'hFEA44703; + mem['h0DB7] <= 32'h00600793; + mem['h0DB8] <= 32'h34F70E63; + mem['h0DB9] <= 32'hFE944783; + mem['h0DBA] <= 32'h00079863; + mem['h0DBB] <= 32'hFEA44703; + mem['h0DBC] <= 32'h00700793; + mem['h0DBD] <= 32'h34F70463; + mem['h0DBE] <= 32'hFE944703; + mem['h0DBF] <= 32'h00F00793; + mem['h0DC0] <= 32'h00F71863; + mem['h0DC1] <= 32'hFEA44703; + mem['h0DC2] <= 32'h00700793; + mem['h0DC3] <= 32'h32F70863; + mem['h0DC4] <= 32'hFE944703; + mem['h0DC5] <= 32'h00100793; + mem['h0DC6] <= 32'h00F71863; + mem['h0DC7] <= 32'hFEA44703; + mem['h0DC8] <= 32'h00800793; + mem['h0DC9] <= 32'h30F70C63; + mem['h0DCA] <= 32'hFE944703; + mem['h0DCB] <= 32'h00E00793; + mem['h0DCC] <= 32'h00F71863; + mem['h0DCD] <= 32'hFEA44703; + mem['h0DCE] <= 32'h00800793; + mem['h0DCF] <= 32'h30F70063; + mem['h0DD0] <= 32'hFE944703; + mem['h0DD1] <= 32'h00200793; + mem['h0DD2] <= 32'h00F71863; + mem['h0DD3] <= 32'hFEA44703; + mem['h0DD4] <= 32'h00900793; + mem['h0DD5] <= 32'h2EF70463; + mem['h0DD6] <= 32'hFE944703; + mem['h0DD7] <= 32'h00D00793; + mem['h0DD8] <= 32'h00F71863; + mem['h0DD9] <= 32'hFEA44703; + mem['h0DDA] <= 32'h00900793; + mem['h0DDB] <= 32'h2CF70863; + mem['h0DDC] <= 32'hFE944703; + mem['h0DDD] <= 32'h00200793; + mem['h0DDE] <= 32'h00F71863; + mem['h0DDF] <= 32'hFEA44703; + mem['h0DE0] <= 32'h00A00793; + mem['h0DE1] <= 32'h2AF70C63; + mem['h0DE2] <= 32'hFE944703; + mem['h0DE3] <= 32'h00D00793; + mem['h0DE4] <= 32'h00F71863; + mem['h0DE5] <= 32'hFEA44703; + mem['h0DE6] <= 32'h00A00793; + mem['h0DE7] <= 32'h2AF70063; + mem['h0DE8] <= 32'hFE944703; + mem['h0DE9] <= 32'h00200793; + mem['h0DEA] <= 32'h00F71863; + mem['h0DEB] <= 32'hFEA44703; + mem['h0DEC] <= 32'h00B00793; + mem['h0DED] <= 32'h28F70463; + mem['h0DEE] <= 32'hFE944703; + mem['h0DEF] <= 32'h00300793; + mem['h0DF0] <= 32'h00F71863; + mem['h0DF1] <= 32'hFEA44703; + mem['h0DF2] <= 32'h00B00793; + mem['h0DF3] <= 32'h26F70863; + mem['h0DF4] <= 32'hFE944703; + mem['h0DF5] <= 32'h00400793; + mem['h0DF6] <= 32'h00F71863; + mem['h0DF7] <= 32'hFEA44703; + mem['h0DF8] <= 32'h00B00793; + mem['h0DF9] <= 32'h24F70C63; + mem['h0DFA] <= 32'hFE944703; + mem['h0DFB] <= 32'h00B00793; + mem['h0DFC] <= 32'h00F71863; + mem['h0DFD] <= 32'hFEA44703; + mem['h0DFE] <= 32'h00B00793; + mem['h0DFF] <= 32'h24F70063; + mem['h0E00] <= 32'hFE944703; + mem['h0E01] <= 32'h00C00793; + mem['h0E02] <= 32'h00F71863; + mem['h0E03] <= 32'hFEA44703; + mem['h0E04] <= 32'h00B00793; + mem['h0E05] <= 32'h22F70463; + mem['h0E06] <= 32'hFE944703; + mem['h0E07] <= 32'h00D00793; + mem['h0E08] <= 32'h00F71863; + mem['h0E09] <= 32'hFEA44703; + mem['h0E0A] <= 32'h00B00793; + mem['h0E0B] <= 32'h20F70863; + mem['h0E0C] <= 32'hFE944703; + mem['h0E0D] <= 32'h00500793; + mem['h0E0E] <= 32'h00F71863; + mem['h0E0F] <= 32'hFEA44703; + mem['h0E10] <= 32'h00C00793; + mem['h0E11] <= 32'h1EF70C63; + mem['h0E12] <= 32'hFE944703; + mem['h0E13] <= 32'h00A00793; + mem['h0E14] <= 32'h00F71863; + mem['h0E15] <= 32'hFEA44703; + mem['h0E16] <= 32'h00C00793; + mem['h0E17] <= 32'h1EF70063; + mem['h0E18] <= 32'hFE944783; + mem['h0E19] <= 32'h00079863; + mem['h0E1A] <= 32'hFEA44703; + mem['h0E1B] <= 32'h00D00793; + mem['h0E1C] <= 32'h1CF70663; + mem['h0E1D] <= 32'hFE944703; + mem['h0E1E] <= 32'h00600793; + mem['h0E1F] <= 32'h00F71863; + mem['h0E20] <= 32'hFEA44703; + mem['h0E21] <= 32'h00D00793; + mem['h0E22] <= 32'h1AF70A63; + mem['h0E23] <= 32'hFE944703; + mem['h0E24] <= 32'h00900793; + mem['h0E25] <= 32'h00F71863; + mem['h0E26] <= 32'hFEA44703; + mem['h0E27] <= 32'h00D00793; + mem['h0E28] <= 32'h18F70E63; + mem['h0E29] <= 32'hFE944703; + mem['h0E2A] <= 32'h00F00793; + mem['h0E2B] <= 32'h00F71863; + mem['h0E2C] <= 32'hFEA44703; + mem['h0E2D] <= 32'h00D00793; + mem['h0E2E] <= 32'h18F70263; + mem['h0E2F] <= 32'hFE944703; + mem['h0E30] <= 32'h00100793; + mem['h0E31] <= 32'h00F71863; + mem['h0E32] <= 32'hFEA44703; + mem['h0E33] <= 32'h00E00793; + mem['h0E34] <= 32'h16F70663; + mem['h0E35] <= 32'hFE944703; + mem['h0E36] <= 32'h00700793; + mem['h0E37] <= 32'h00F71863; + mem['h0E38] <= 32'hFEA44703; + mem['h0E39] <= 32'h00E00793; + mem['h0E3A] <= 32'h14F70A63; + mem['h0E3B] <= 32'hFE944703; + mem['h0E3C] <= 32'h00800793; + mem['h0E3D] <= 32'h00F71863; + mem['h0E3E] <= 32'hFEA44703; + mem['h0E3F] <= 32'h00E00793; + mem['h0E40] <= 32'h12F70E63; + mem['h0E41] <= 32'hFE944703; + mem['h0E42] <= 32'h00E00793; + mem['h0E43] <= 32'h00F71863; + mem['h0E44] <= 32'hFEA44703; + mem['h0E45] <= 32'h00E00793; + mem['h0E46] <= 32'h12F70263; + mem['h0E47] <= 32'hFE944703; + mem['h0E48] <= 32'h00200793; + mem['h0E49] <= 32'h00F71863; + mem['h0E4A] <= 32'hFEA44703; + mem['h0E4B] <= 32'h00F00793; + mem['h0E4C] <= 32'h10F70663; + mem['h0E4D] <= 32'hFE944703; + mem['h0E4E] <= 32'h00300793; + mem['h0E4F] <= 32'h00F71863; + mem['h0E50] <= 32'hFEA44703; + mem['h0E51] <= 32'h00F00793; + mem['h0E52] <= 32'h0EF70A63; + mem['h0E53] <= 32'hFE944703; + mem['h0E54] <= 32'h00400793; + mem['h0E55] <= 32'h00F71863; + mem['h0E56] <= 32'hFEA44703; + mem['h0E57] <= 32'h00F00793; + mem['h0E58] <= 32'h0CF70E63; + mem['h0E59] <= 32'hFE944703; + mem['h0E5A] <= 32'h00500793; + mem['h0E5B] <= 32'h00F71863; + mem['h0E5C] <= 32'hFEA44703; + mem['h0E5D] <= 32'h00F00793; + mem['h0E5E] <= 32'h0CF70263; + mem['h0E5F] <= 32'hFE944703; + mem['h0E60] <= 32'h00600793; + mem['h0E61] <= 32'h00F71863; + mem['h0E62] <= 32'hFEA44703; + mem['h0E63] <= 32'h00F00793; + mem['h0E64] <= 32'h0AF70663; + mem['h0E65] <= 32'hFE944703; + mem['h0E66] <= 32'h00700793; + mem['h0E67] <= 32'h00F71863; + mem['h0E68] <= 32'hFEA44703; + mem['h0E69] <= 32'h00F00793; + mem['h0E6A] <= 32'h08F70A63; + mem['h0E6B] <= 32'hFE944703; + mem['h0E6C] <= 32'h00800793; + mem['h0E6D] <= 32'h00F71863; + mem['h0E6E] <= 32'hFEA44703; + mem['h0E6F] <= 32'h00F00793; + mem['h0E70] <= 32'h06F70E63; + mem['h0E71] <= 32'hFE944703; + mem['h0E72] <= 32'h00900793; + mem['h0E73] <= 32'h00F71863; + mem['h0E74] <= 32'hFEA44703; + mem['h0E75] <= 32'h00F00793; + mem['h0E76] <= 32'h06F70263; + mem['h0E77] <= 32'hFE944703; + mem['h0E78] <= 32'h00A00793; + mem['h0E79] <= 32'h00F71863; + mem['h0E7A] <= 32'hFEA44703; + mem['h0E7B] <= 32'h00F00793; + mem['h0E7C] <= 32'h04F70663; + mem['h0E7D] <= 32'hFE944703; + mem['h0E7E] <= 32'h00B00793; + mem['h0E7F] <= 32'h00F71863; + mem['h0E80] <= 32'hFEA44703; + mem['h0E81] <= 32'h00F00793; + mem['h0E82] <= 32'h02F70A63; + mem['h0E83] <= 32'hFE944703; + mem['h0E84] <= 32'h00C00793; + mem['h0E85] <= 32'h00F71863; + mem['h0E86] <= 32'hFEA44703; + mem['h0E87] <= 32'h00F00793; + mem['h0E88] <= 32'h00F70E63; + mem['h0E89] <= 32'hFE944703; + mem['h0E8A] <= 32'h00D00793; + mem['h0E8B] <= 32'h02F71063; + mem['h0E8C] <= 32'hFEA44703; + mem['h0E8D] <= 32'h00F00793; + mem['h0E8E] <= 32'h00F71A63; + mem['h0E8F] <= 32'h000017B7; + mem['h0E90] <= 32'hFD278793; + mem['h0E91] <= 32'hFEF42623; + mem['h0E92] <= 32'h04C0006F; + mem['h0E93] <= 32'hFFF00793; + mem['h0E94] <= 32'hFEF42623; + mem['h0E95] <= 32'h0400006F; + mem['h0E96] <= 32'hFEB44703; + mem['h0E97] <= 32'h00D00793; + mem['h0E98] <= 32'h00F71A63; + mem['h0E99] <= 32'h000017B7; + mem['h0E9A] <= 32'hA0A78793; + mem['h0E9B] <= 32'hFEF42623; + mem['h0E9C] <= 32'h0240006F; + mem['h0E9D] <= 32'hFEB44703; + mem['h0E9E] <= 32'h00E00793; + mem['h0E9F] <= 32'h00F71A63; + mem['h0EA0] <= 32'h000017B7; + mem['h0EA1] <= 32'hFFF78793; + mem['h0EA2] <= 32'hFEF42623; + mem['h0EA3] <= 32'h0080006F; + mem['h0EA4] <= 32'hFE042623; + mem['h0EA5] <= 32'hFEB44783; + mem['h0EA6] <= 32'h00479713; + mem['h0EA7] <= 32'hFEA44783; + mem['h0EA8] <= 32'h00F707B3; + mem['h0EA9] <= 32'h00479713; + mem['h0EAA] <= 32'hFE944783; + mem['h0EAB] <= 32'h00F707B3; + mem['h0EAC] <= 32'h00279713; + mem['h0EAD] <= 32'h051007B7; + mem['h0EAE] <= 32'h00F707B3; + mem['h0EAF] <= 32'hFEC42703; + mem['h0EB0] <= 32'h00E7A023; + mem['h0EB1] <= 32'hFE944783; + mem['h0EB2] <= 32'h00178793; + mem['h0EB3] <= 32'hFEF404A3; + mem['h0EB4] <= 32'hFE944703; + mem['h0EB5] <= 32'h00F00793; + mem['h0EB6] <= 32'hD8E7FA63; + mem['h0EB7] <= 32'hFEA44783; + mem['h0EB8] <= 32'h00178793; + mem['h0EB9] <= 32'hFEF40523; + mem['h0EBA] <= 32'hFEA44703; + mem['h0EBB] <= 32'h00F00793; + mem['h0EBC] <= 32'hD6E7FA63; + mem['h0EBD] <= 32'hFEB44783; + mem['h0EBE] <= 32'h00178793; + mem['h0EBF] <= 32'hFEF405A3; + mem['h0EC0] <= 32'hFEB44703; + mem['h0EC1] <= 32'h00F00793; + mem['h0EC2] <= 32'hD4E7FA63; + mem['h0EC3] <= 32'h00000013; + mem['h0EC4] <= 32'h00000013; + mem['h0EC5] <= 32'h01C12403; + mem['h0EC6] <= 32'h02010113; + mem['h0EC7] <= 32'h00008067; + mem['h0EC8] <= 32'hFD010113; + mem['h0EC9] <= 32'h02812623; + mem['h0ECA] <= 32'h03010413; + mem['h0ECB] <= 32'hFCA42E23; + mem['h0ECC] <= 32'hFCB42C23; + mem['h0ECD] <= 32'hFCC42A23; + mem['h0ECE] <= 32'hFE042623; + mem['h0ECF] <= 32'hFD442703; + mem['h0ED0] <= 32'h41F75793; + mem['h0ED1] <= 32'h01E7D793; + mem['h0ED2] <= 32'h00F70733; + mem['h0ED3] <= 32'h00377713; + mem['h0ED4] <= 32'h40F707B3; + mem['h0ED5] <= 32'h00300713; + mem['h0ED6] <= 32'h08E78063; + mem['h0ED7] <= 32'h00300713; + mem['h0ED8] <= 32'h08F74C63; + mem['h0ED9] <= 32'h00200713; + mem['h0EDA] <= 32'h04E78863; + mem['h0EDB] <= 32'h00200713; + mem['h0EDC] <= 32'h08F74463; + mem['h0EDD] <= 32'h00078863; + mem['h0EDE] <= 32'h00100713; + mem['h0EDF] <= 32'h02E78063; + mem['h0EE0] <= 32'h0780006F; + mem['h0EE1] <= 32'hFD842783; + mem['h0EE2] <= 32'h00279793; + mem['h0EE3] <= 32'hFDC42703; + mem['h0EE4] <= 32'h00F707B3; + mem['h0EE5] <= 32'hFEF42623; + mem['h0EE6] <= 32'h0600006F; + mem['h0EE7] <= 32'hFD842783; + mem['h0EE8] <= 32'h00C78713; + mem['h0EE9] <= 32'hFDC42783; + mem['h0EEA] <= 32'h00279793; + mem['h0EEB] <= 32'h40F707B3; + mem['h0EEC] <= 32'hFEF42623; + mem['h0EED] <= 32'h0440006F; + mem['h0EEE] <= 32'hFD842783; + mem['h0EEF] <= 32'h00279793; + mem['h0EF0] <= 32'h00F00713; + mem['h0EF1] <= 32'h40F70733; + mem['h0EF2] <= 32'hFDC42783; + mem['h0EF3] <= 32'h40F707B3; + mem['h0EF4] <= 32'hFEF42623; + mem['h0EF5] <= 32'h0240006F; + mem['h0EF6] <= 32'h00300713; + mem['h0EF7] <= 32'hFD842783; + mem['h0EF8] <= 32'h40F70733; + mem['h0EF9] <= 32'hFDC42783; + mem['h0EFA] <= 32'h00279793; + mem['h0EFB] <= 32'h00F707B3; + mem['h0EFC] <= 32'hFEF42623; + mem['h0EFD] <= 32'h00000013; + mem['h0EFE] <= 32'hFEC42783; + mem['h0EFF] <= 32'h00078513; + mem['h0F00] <= 32'h02C12403; + mem['h0F01] <= 32'h03010113; + mem['h0F02] <= 32'h00008067; + mem['h0F03] <= 32'hFD010113; + mem['h0F04] <= 32'h02112623; + mem['h0F05] <= 32'h02812423; + mem['h0F06] <= 32'h03010413; + mem['h0F07] <= 32'hFCA42E23; + mem['h0F08] <= 32'hFCB42C23; + mem['h0F09] <= 32'hFCC42A23; + mem['h0F0A] <= 32'hFCD42823; + mem['h0F0B] <= 32'hFE042623; + mem['h0F0C] <= 32'h0FC0006F; + mem['h0F0D] <= 32'hFE042423; + mem['h0F0E] <= 32'h0DC0006F; + mem['h0F0F] <= 32'hFD842603; + mem['h0F10] <= 32'hFE842583; + mem['h0F11] <= 32'hFEC42503; + mem['h0F12] <= 32'hED9FF0EF; + mem['h0F13] <= 32'hFEA42223; + mem['h0F14] <= 32'hFD042703; + mem['h0F15] <= 32'hFE842783; + mem['h0F16] <= 32'h00F70733; + mem['h0F17] <= 32'h00070793; + mem['h0F18] <= 32'h00279793; + mem['h0F19] <= 32'h00E787B3; + mem['h0F1A] <= 32'h00379793; + mem['h0F1B] <= 32'h00078693; + mem['h0F1C] <= 32'hFD442703; + mem['h0F1D] <= 32'hFEC42783; + mem['h0F1E] <= 32'h00F707B3; + mem['h0F1F] <= 32'h00F687B3; + mem['h0F20] <= 32'hFEF42023; + mem['h0F21] <= 32'hFD442703; + mem['h0F22] <= 32'hFEC42783; + mem['h0F23] <= 32'h00F707B3; + mem['h0F24] <= 32'h0607CC63; + mem['h0F25] <= 32'hFD442703; + mem['h0F26] <= 32'hFEC42783; + mem['h0F27] <= 32'h00F70733; + mem['h0F28] <= 32'h02700793; + mem['h0F29] <= 32'h06E7C263; + mem['h0F2A] <= 32'hFD042703; + mem['h0F2B] <= 32'hFE842783; + mem['h0F2C] <= 32'h00F707B3; + mem['h0F2D] <= 32'h0407CA63; + mem['h0F2E] <= 32'hFD042703; + mem['h0F2F] <= 32'hFE842783; + mem['h0F30] <= 32'h00F70733; + mem['h0F31] <= 32'h01D00793; + mem['h0F32] <= 32'h04E7C063; + mem['h0F33] <= 32'h00000713; + mem['h0F34] <= 32'hFDC42783; + mem['h0F35] <= 32'h00479793; + mem['h0F36] <= 32'h00F70733; + mem['h0F37] <= 32'hFE442783; + mem['h0F38] <= 32'h00F707B3; + mem['h0F39] <= 32'h0007C783; + mem['h0F3A] <= 32'h02078063; + mem['h0F3B] <= 32'h07C00713; + mem['h0F3C] <= 32'hFE042783; + mem['h0F3D] <= 32'h00F707B3; + mem['h0F3E] <= 32'h0007C783; + mem['h0F3F] <= 32'h00078663; + mem['h0F40] <= 32'h00000793; + mem['h0F41] <= 32'h0380006F; + mem['h0F42] <= 32'hFE842783; + mem['h0F43] <= 32'h00178793; + mem['h0F44] <= 32'hFEF42423; + mem['h0F45] <= 32'hFE842703; + mem['h0F46] <= 32'h00300793; + mem['h0F47] <= 32'hF2E7D0E3; + mem['h0F48] <= 32'hFEC42783; + mem['h0F49] <= 32'h00178793; + mem['h0F4A] <= 32'hFEF42623; + mem['h0F4B] <= 32'hFEC42703; + mem['h0F4C] <= 32'h00300793; + mem['h0F4D] <= 32'hF0E7D0E3; + mem['h0F4E] <= 32'h00100793; + mem['h0F4F] <= 32'h00078513; + mem['h0F50] <= 32'h02C12083; + mem['h0F51] <= 32'h02812403; + mem['h0F52] <= 32'h03010113; + mem['h0F53] <= 32'h00008067; + mem['h0F54] <= 32'hFD010113; + mem['h0F55] <= 32'h02812623; + mem['h0F56] <= 32'h03010413; + mem['h0F57] <= 32'hFCA42E23; + mem['h0F58] <= 32'hFCB42C23; + mem['h0F59] <= 32'hFCC42A23; + mem['h0F5A] <= 32'hFD442783; + mem['h0F5B] <= 32'hFEF407A3; + mem['h0F5C] <= 32'h7000006F; + mem['h0F5D] <= 32'hFD842783; + mem['h0F5E] <= 32'hFEF40723; + mem['h0F5F] <= 32'h6D80006F; + mem['h0F60] <= 32'hFDC42703; + mem['h0F61] <= 32'h00900793; + mem['h0F62] <= 32'h6AE7EE63; + mem['h0F63] <= 32'hFDC42783; + mem['h0F64] <= 32'h00279713; + mem['h0F65] <= 32'h001067B7; + mem['h0F66] <= 32'hACC78793; + mem['h0F67] <= 32'h00F707B3; + mem['h0F68] <= 32'h0007A783; + mem['h0F69] <= 32'h00078067; + mem['h0F6A] <= 32'hFEE44783; + mem['h0F6B] <= 32'hFD842703; + mem['h0F6C] <= 32'h02F70863; + mem['h0F6D] <= 32'hFEE44703; + mem['h0F6E] <= 32'hFD842783; + mem['h0F6F] <= 32'h00278793; + mem['h0F70] <= 32'h02F70063; + mem['h0F71] <= 32'hFEF44783; + mem['h0F72] <= 32'hFD442703; + mem['h0F73] <= 32'h00F70A63; + mem['h0F74] <= 32'hFEF44703; + mem['h0F75] <= 32'hFD442783; + mem['h0F76] <= 32'h00478793; + mem['h0F77] <= 32'h02F71A63; + mem['h0F78] <= 32'hFEF44703; + mem['h0F79] <= 32'h00070793; + mem['h0F7A] <= 32'h00279793; + mem['h0F7B] <= 32'h00E787B3; + mem['h0F7C] <= 32'h00379793; + mem['h0F7D] <= 32'h00078713; + mem['h0F7E] <= 32'hFEE44783; + mem['h0F7F] <= 32'h00F707B3; + mem['h0F80] <= 32'h07C00713; + mem['h0F81] <= 32'h00F707B3; + mem['h0F82] <= 32'h00078023; + mem['h0F83] <= 32'h63C0006F; + mem['h0F84] <= 32'hFEF44703; + mem['h0F85] <= 32'h00070793; + mem['h0F86] <= 32'h00279793; + mem['h0F87] <= 32'h00E787B3; + mem['h0F88] <= 32'h00379793; + mem['h0F89] <= 32'h00078713; + mem['h0F8A] <= 32'hFEE44783; + mem['h0F8B] <= 32'h00F707B3; + mem['h0F8C] <= 32'h07C00713; + mem['h0F8D] <= 32'h00F707B3; + mem['h0F8E] <= 32'h00900713; + mem['h0F8F] <= 32'h00E78023; + mem['h0F90] <= 32'h6080006F; + mem['h0F91] <= 32'hFEE44703; + mem['h0F92] <= 32'hFD842783; + mem['h0F93] <= 32'h00278793; + mem['h0F94] <= 32'h00F70A63; + mem['h0F95] <= 32'hFEF44703; + mem['h0F96] <= 32'hFD442783; + mem['h0F97] <= 32'h00178793; + mem['h0F98] <= 32'h02F71A63; + mem['h0F99] <= 32'hFEF44703; + mem['h0F9A] <= 32'h00070793; + mem['h0F9B] <= 32'h00279793; + mem['h0F9C] <= 32'h00E787B3; + mem['h0F9D] <= 32'h00379793; + mem['h0F9E] <= 32'h00078713; + mem['h0F9F] <= 32'hFEE44783; + mem['h0FA0] <= 32'h00F707B3; + mem['h0FA1] <= 32'h07C00713; + mem['h0FA2] <= 32'h00F707B3; + mem['h0FA3] <= 32'h00078023; + mem['h0FA4] <= 32'h5B80006F; + mem['h0FA5] <= 32'hFEF44703; + mem['h0FA6] <= 32'h00070793; + mem['h0FA7] <= 32'h00279793; + mem['h0FA8] <= 32'h00E787B3; + mem['h0FA9] <= 32'h00379793; + mem['h0FAA] <= 32'h00078713; + mem['h0FAB] <= 32'hFEE44783; + mem['h0FAC] <= 32'h00F707B3; + mem['h0FAD] <= 32'h07C00713; + mem['h0FAE] <= 32'h00F707B3; + mem['h0FAF] <= 32'h00900713; + mem['h0FB0] <= 32'h00E78023; + mem['h0FB1] <= 32'h5840006F; + mem['h0FB2] <= 32'hFEF44783; + mem['h0FB3] <= 32'hFD442703; + mem['h0FB4] <= 32'h06F70063; + mem['h0FB5] <= 32'hFEF44703; + mem['h0FB6] <= 32'hFD442783; + mem['h0FB7] <= 32'h00278793; + mem['h0FB8] <= 32'h04F70863; + mem['h0FB9] <= 32'hFEF44703; + mem['h0FBA] <= 32'hFD442783; + mem['h0FBB] <= 32'h00478793; + mem['h0FBC] <= 32'h04F70063; + mem['h0FBD] <= 32'hFEF44703; + mem['h0FBE] <= 32'hFD442783; + mem['h0FBF] <= 32'h00178793; + mem['h0FC0] <= 32'h00F71A63; + mem['h0FC1] <= 32'hFEE44703; + mem['h0FC2] <= 32'hFD842783; + mem['h0FC3] <= 32'h00278793; + mem['h0FC4] <= 32'h02F70063; + mem['h0FC5] <= 32'hFEF44703; + mem['h0FC6] <= 32'hFD442783; + mem['h0FC7] <= 32'h00378793; + mem['h0FC8] <= 32'h04F71063; + mem['h0FC9] <= 32'hFEE44783; + mem['h0FCA] <= 32'hFD842703; + mem['h0FCB] <= 32'h02F71A63; + mem['h0FCC] <= 32'hFEF44703; + mem['h0FCD] <= 32'h00070793; + mem['h0FCE] <= 32'h00279793; + mem['h0FCF] <= 32'h00E787B3; + mem['h0FD0] <= 32'h00379793; + mem['h0FD1] <= 32'h00078713; + mem['h0FD2] <= 32'hFEE44783; + mem['h0FD3] <= 32'h00F707B3; + mem['h0FD4] <= 32'h07C00713; + mem['h0FD5] <= 32'h00F707B3; + mem['h0FD6] <= 32'h00078023; + mem['h0FD7] <= 32'h4EC0006F; + mem['h0FD8] <= 32'hFEF44703; + mem['h0FD9] <= 32'h00070793; + mem['h0FDA] <= 32'h00279793; + mem['h0FDB] <= 32'h00E787B3; + mem['h0FDC] <= 32'h00379793; + mem['h0FDD] <= 32'h00078713; + mem['h0FDE] <= 32'hFEE44783; + mem['h0FDF] <= 32'h00F707B3; + mem['h0FE0] <= 32'h07C00713; + mem['h0FE1] <= 32'h00F707B3; + mem['h0FE2] <= 32'h00900713; + mem['h0FE3] <= 32'h00E78023; + mem['h0FE4] <= 32'h4B80006F; + mem['h0FE5] <= 32'hFEE44703; + mem['h0FE6] <= 32'hFD842783; + mem['h0FE7] <= 32'h00278793; + mem['h0FE8] <= 32'h02F70863; + mem['h0FE9] <= 32'hFEF44783; + mem['h0FEA] <= 32'hFD442703; + mem['h0FEB] <= 32'h02F70263; + mem['h0FEC] <= 32'hFEF44703; + mem['h0FED] <= 32'hFD442783; + mem['h0FEE] <= 32'h00278793; + mem['h0FEF] <= 32'h00F70A63; + mem['h0FF0] <= 32'hFEF44703; + mem['h0FF1] <= 32'hFD442783; + mem['h0FF2] <= 32'h00478793; + mem['h0FF3] <= 32'h02F71A63; + mem['h0FF4] <= 32'hFEF44703; + mem['h0FF5] <= 32'h00070793; + mem['h0FF6] <= 32'h00279793; + mem['h0FF7] <= 32'h00E787B3; + mem['h0FF8] <= 32'h00379793; + mem['h0FF9] <= 32'h00078713; + mem['h0FFA] <= 32'hFEE44783; + mem['h0FFB] <= 32'h00F707B3; + mem['h0FFC] <= 32'h07C00713; + mem['h0FFD] <= 32'h00F707B3; + mem['h0FFE] <= 32'h00078023; + mem['h0FFF] <= 32'h44C0006F; + mem['h1000] <= 32'hFEF44703; + mem['h1001] <= 32'h00070793; + mem['h1002] <= 32'h00279793; + mem['h1003] <= 32'h00E787B3; + mem['h1004] <= 32'h00379793; + mem['h1005] <= 32'h00078713; + mem['h1006] <= 32'hFEE44783; + mem['h1007] <= 32'h00F707B3; + mem['h1008] <= 32'h07C00713; + mem['h1009] <= 32'h00F707B3; + mem['h100A] <= 32'h00900713; + mem['h100B] <= 32'h00E78023; + mem['h100C] <= 32'h4180006F; + mem['h100D] <= 32'hFEE44703; + mem['h100E] <= 32'hFD842783; + mem['h100F] <= 32'h00278793; + mem['h1010] <= 32'h02F70863; + mem['h1011] <= 32'hFEF44703; + mem['h1012] <= 32'hFD442783; + mem['h1013] <= 32'h00278793; + mem['h1014] <= 32'h02F70063; + mem['h1015] <= 32'hFEF44703; + mem['h1016] <= 32'hFD442783; + mem['h1017] <= 32'h00278793; + mem['h1018] <= 32'h04E7C063; + mem['h1019] <= 32'hFEE44783; + mem['h101A] <= 32'hFD842703; + mem['h101B] <= 32'h02F71A63; + mem['h101C] <= 32'hFEF44703; + mem['h101D] <= 32'h00070793; + mem['h101E] <= 32'h00279793; + mem['h101F] <= 32'h00E787B3; + mem['h1020] <= 32'h00379793; + mem['h1021] <= 32'h00078713; + mem['h1022] <= 32'hFEE44783; + mem['h1023] <= 32'h00F707B3; + mem['h1024] <= 32'h07C00713; + mem['h1025] <= 32'h00F707B3; + mem['h1026] <= 32'h00078023; + mem['h1027] <= 32'h3AC0006F; + mem['h1028] <= 32'hFEF44703; + mem['h1029] <= 32'h00070793; + mem['h102A] <= 32'h00279793; + mem['h102B] <= 32'h00E787B3; + mem['h102C] <= 32'h00379793; + mem['h102D] <= 32'h00078713; + mem['h102E] <= 32'hFEE44783; + mem['h102F] <= 32'h00F707B3; + mem['h1030] <= 32'h07C00713; + mem['h1031] <= 32'h00F707B3; + mem['h1032] <= 32'h00900713; + mem['h1033] <= 32'h00E78023; + mem['h1034] <= 32'h3780006F; + mem['h1035] <= 32'hFEF44783; + mem['h1036] <= 32'hFD442703; + mem['h1037] <= 32'h06F70063; + mem['h1038] <= 32'hFEF44703; + mem['h1039] <= 32'hFD442783; + mem['h103A] <= 32'h00278793; + mem['h103B] <= 32'h04F70863; + mem['h103C] <= 32'hFEF44703; + mem['h103D] <= 32'hFD442783; + mem['h103E] <= 32'h00478793; + mem['h103F] <= 32'h04F70063; + mem['h1040] <= 32'hFEF44703; + mem['h1041] <= 32'hFD442783; + mem['h1042] <= 32'h00178793; + mem['h1043] <= 32'h00F71863; + mem['h1044] <= 32'hFEE44783; + mem['h1045] <= 32'hFD842703; + mem['h1046] <= 32'h02F70263; + mem['h1047] <= 32'hFEF44703; + mem['h1048] <= 32'hFD442783; + mem['h1049] <= 32'h00378793; + mem['h104A] <= 32'h04F71263; + mem['h104B] <= 32'hFEE44703; + mem['h104C] <= 32'hFD842783; + mem['h104D] <= 32'h00278793; + mem['h104E] <= 32'h02F71A63; + mem['h104F] <= 32'hFEF44703; + mem['h1050] <= 32'h00070793; + mem['h1051] <= 32'h00279793; + mem['h1052] <= 32'h00E787B3; + mem['h1053] <= 32'h00379793; + mem['h1054] <= 32'h00078713; + mem['h1055] <= 32'hFEE44783; + mem['h1056] <= 32'h00F707B3; + mem['h1057] <= 32'h07C00713; + mem['h1058] <= 32'h00F707B3; + mem['h1059] <= 32'h00078023; + mem['h105A] <= 32'h2E00006F; + mem['h105B] <= 32'hFEF44703; + mem['h105C] <= 32'h00070793; + mem['h105D] <= 32'h00279793; + mem['h105E] <= 32'h00E787B3; + mem['h105F] <= 32'h00379793; + mem['h1060] <= 32'h00078713; + mem['h1061] <= 32'hFEE44783; + mem['h1062] <= 32'h00F707B3; + mem['h1063] <= 32'h07C00713; + mem['h1064] <= 32'h00F707B3; + mem['h1065] <= 32'h00900713; + mem['h1066] <= 32'h00E78023; + mem['h1067] <= 32'h2AC0006F; + mem['h1068] <= 32'hFEE44783; + mem['h1069] <= 32'hFD842703; + mem['h106A] <= 32'h04F70863; + mem['h106B] <= 32'hFEF44783; + mem['h106C] <= 32'hFD442703; + mem['h106D] <= 32'h04F70263; + mem['h106E] <= 32'hFEF44703; + mem['h106F] <= 32'hFD442783; + mem['h1070] <= 32'h00278793; + mem['h1071] <= 32'h02F70A63; + mem['h1072] <= 32'hFEF44703; + mem['h1073] <= 32'hFD442783; + mem['h1074] <= 32'h00478793; + mem['h1075] <= 32'h02F70263; + mem['h1076] <= 32'hFEF44703; + mem['h1077] <= 32'hFD442783; + mem['h1078] <= 32'h00378793; + mem['h1079] <= 32'h04F71263; + mem['h107A] <= 32'hFEE44703; + mem['h107B] <= 32'hFD842783; + mem['h107C] <= 32'h00278793; + mem['h107D] <= 32'h02F71A63; + mem['h107E] <= 32'hFEF44703; + mem['h107F] <= 32'h00070793; + mem['h1080] <= 32'h00279793; + mem['h1081] <= 32'h00E787B3; + mem['h1082] <= 32'h00379793; + mem['h1083] <= 32'h00078713; + mem['h1084] <= 32'hFEE44783; + mem['h1085] <= 32'h00F707B3; + mem['h1086] <= 32'h07C00713; + mem['h1087] <= 32'h00F707B3; + mem['h1088] <= 32'h00078023; + mem['h1089] <= 32'h2240006F; + mem['h108A] <= 32'hFEF44703; + mem['h108B] <= 32'h00070793; + mem['h108C] <= 32'h00279793; + mem['h108D] <= 32'h00E787B3; + mem['h108E] <= 32'h00379793; + mem['h108F] <= 32'h00078713; + mem['h1090] <= 32'hFEE44783; + mem['h1091] <= 32'h00F707B3; + mem['h1092] <= 32'h07C00713; + mem['h1093] <= 32'h00F707B3; + mem['h1094] <= 32'h00900713; + mem['h1095] <= 32'h00E78023; + mem['h1096] <= 32'h1F00006F; + mem['h1097] <= 32'hFEE44703; + mem['h1098] <= 32'hFD842783; + mem['h1099] <= 32'h00278793; + mem['h109A] <= 32'h00F70863; + mem['h109B] <= 32'hFEF44783; + mem['h109C] <= 32'hFD442703; + mem['h109D] <= 32'h02F71A63; + mem['h109E] <= 32'hFEF44703; + mem['h109F] <= 32'h00070793; + mem['h10A0] <= 32'h00279793; + mem['h10A1] <= 32'h00E787B3; + mem['h10A2] <= 32'h00379793; + mem['h10A3] <= 32'h00078713; + mem['h10A4] <= 32'hFEE44783; + mem['h10A5] <= 32'h00F707B3; + mem['h10A6] <= 32'h07C00713; + mem['h10A7] <= 32'h00F707B3; + mem['h10A8] <= 32'h00078023; + mem['h10A9] <= 32'h1A40006F; + mem['h10AA] <= 32'hFEF44703; + mem['h10AB] <= 32'h00070793; + mem['h10AC] <= 32'h00279793; + mem['h10AD] <= 32'h00E787B3; + mem['h10AE] <= 32'h00379793; + mem['h10AF] <= 32'h00078713; + mem['h10B0] <= 32'hFEE44783; + mem['h10B1] <= 32'h00F707B3; + mem['h10B2] <= 32'h07C00713; + mem['h10B3] <= 32'h00F707B3; + mem['h10B4] <= 32'h00900713; + mem['h10B5] <= 32'h00E78023; + mem['h10B6] <= 32'h1700006F; + mem['h10B7] <= 32'hFEE44783; + mem['h10B8] <= 32'hFD842703; + mem['h10B9] <= 32'h04F70063; + mem['h10BA] <= 32'hFEE44703; + mem['h10BB] <= 32'hFD842783; + mem['h10BC] <= 32'h00278793; + mem['h10BD] <= 32'h02F70863; + mem['h10BE] <= 32'hFEF44783; + mem['h10BF] <= 32'hFD442703; + mem['h10C0] <= 32'h02F70263; + mem['h10C1] <= 32'hFEF44703; + mem['h10C2] <= 32'hFD442783; + mem['h10C3] <= 32'h00278793; + mem['h10C4] <= 32'h00F70A63; + mem['h10C5] <= 32'hFEF44703; + mem['h10C6] <= 32'hFD442783; + mem['h10C7] <= 32'h00478793; + mem['h10C8] <= 32'h02F71A63; + mem['h10C9] <= 32'hFEF44703; + mem['h10CA] <= 32'h00070793; + mem['h10CB] <= 32'h00279793; + mem['h10CC] <= 32'h00E787B3; + mem['h10CD] <= 32'h00379793; + mem['h10CE] <= 32'h00078713; + mem['h10CF] <= 32'hFEE44783; + mem['h10D0] <= 32'h00F707B3; + mem['h10D1] <= 32'h07C00713; + mem['h10D2] <= 32'h00F707B3; + mem['h10D3] <= 32'h00078023; + mem['h10D4] <= 32'h0F80006F; + mem['h10D5] <= 32'hFEF44703; + mem['h10D6] <= 32'h00070793; + mem['h10D7] <= 32'h00279793; + mem['h10D8] <= 32'h00E787B3; + mem['h10D9] <= 32'h00379793; + mem['h10DA] <= 32'h00078713; + mem['h10DB] <= 32'hFEE44783; + mem['h10DC] <= 32'h00F707B3; + mem['h10DD] <= 32'h07C00713; + mem['h10DE] <= 32'h00F707B3; + mem['h10DF] <= 32'h00900713; + mem['h10E0] <= 32'h00E78023; + mem['h10E1] <= 32'h0C40006F; + mem['h10E2] <= 32'hFEE44703; + mem['h10E3] <= 32'hFD842783; + mem['h10E4] <= 32'h00278793; + mem['h10E5] <= 32'h04F70663; + mem['h10E6] <= 32'hFEF44783; + mem['h10E7] <= 32'hFD442703; + mem['h10E8] <= 32'h04F70063; + mem['h10E9] <= 32'hFEF44703; + mem['h10EA] <= 32'hFD442783; + mem['h10EB] <= 32'h00278793; + mem['h10EC] <= 32'h02F70863; + mem['h10ED] <= 32'hFEF44703; + mem['h10EE] <= 32'hFD442783; + mem['h10EF] <= 32'h00478793; + mem['h10F0] <= 32'h02F70063; + mem['h10F1] <= 32'hFEF44703; + mem['h10F2] <= 32'hFD442783; + mem['h10F3] <= 32'h00178793; + mem['h10F4] <= 32'h04F71063; + mem['h10F5] <= 32'hFEE44783; + mem['h10F6] <= 32'hFD842703; + mem['h10F7] <= 32'h02F71A63; + mem['h10F8] <= 32'hFEF44703; + mem['h10F9] <= 32'h00070793; + mem['h10FA] <= 32'h00279793; + mem['h10FB] <= 32'h00E787B3; + mem['h10FC] <= 32'h00379793; + mem['h10FD] <= 32'h00078713; + mem['h10FE] <= 32'hFEE44783; + mem['h10FF] <= 32'h00F707B3; + mem['h1100] <= 32'h07C00713; + mem['h1101] <= 32'h00F707B3; + mem['h1102] <= 32'h00078023; + mem['h1103] <= 32'h03C0006F; + mem['h1104] <= 32'hFEF44703; + mem['h1105] <= 32'h00070793; + mem['h1106] <= 32'h00279793; + mem['h1107] <= 32'h00E787B3; + mem['h1108] <= 32'h00379793; + mem['h1109] <= 32'h00078713; + mem['h110A] <= 32'hFEE44783; + mem['h110B] <= 32'h00F707B3; + mem['h110C] <= 32'h07C00713; + mem['h110D] <= 32'h00F707B3; + mem['h110E] <= 32'h00900713; + mem['h110F] <= 32'h00E78023; + mem['h1110] <= 32'h0080006F; + mem['h1111] <= 32'h00000013; + mem['h1112] <= 32'hFEE44783; + mem['h1113] <= 32'h00178793; + mem['h1114] <= 32'hFEF40723; + mem['h1115] <= 32'hFD842783; + mem['h1116] <= 32'h00278713; + mem['h1117] <= 32'hFEE44783; + mem['h1118] <= 32'h92F750E3; + mem['h1119] <= 32'hFEF44783; + mem['h111A] <= 32'h00178793; + mem['h111B] <= 32'hFEF407A3; + mem['h111C] <= 32'hFD442783; + mem['h111D] <= 32'h00478713; + mem['h111E] <= 32'hFEF44783; + mem['h111F] <= 32'h8EF75CE3; + mem['h1120] <= 32'h00000013; + mem['h1121] <= 32'h00000013; + mem['h1122] <= 32'h02C12403; + mem['h1123] <= 32'h03010113; + mem['h1124] <= 32'h00008067; + mem['h1125] <= 32'hFC010113; + mem['h1126] <= 32'h02112E23; + mem['h1127] <= 32'h02812C23; + mem['h1128] <= 32'h04010413; + mem['h1129] <= 32'hFCA42623; + mem['h112A] <= 32'hFCB42423; + mem['h112B] <= 32'hFCC42223; + mem['h112C] <= 32'hFC042E23; + mem['h112D] <= 32'hFE042023; + mem['h112E] <= 32'hFE042223; + mem['h112F] <= 32'hFE042423; + mem['h1130] <= 32'hFE042623; + mem['h1131] <= 32'h03C0006F; + mem['h1132] <= 32'hFEC42783; + mem['h1133] <= 32'h00178713; + mem['h1134] <= 32'hFEE42623; + mem['h1135] <= 32'hFCC42683; + mem['h1136] <= 32'h00A00713; + mem['h1137] <= 32'h02E6E733; + mem['h1138] <= 32'h00279793; + mem['h1139] <= 32'hFF040693; + mem['h113A] <= 32'h00F687B3; + mem['h113B] <= 32'hFEE7A623; + mem['h113C] <= 32'hFCC42703; + mem['h113D] <= 32'h00A00793; + mem['h113E] <= 32'h02F747B3; + mem['h113F] <= 32'hFCF42623; + mem['h1140] <= 32'hFCC42783; + mem['h1141] <= 32'hFC0792E3; + mem['h1142] <= 32'h00300793; + mem['h1143] <= 32'hFEF42623; + mem['h1144] <= 32'h04C0006F; + mem['h1145] <= 32'hFEC42783; + mem['h1146] <= 32'h00279793; + mem['h1147] <= 32'hFF040713; + mem['h1148] <= 32'h00F707B3; + mem['h1149] <= 32'hFEC7A683; + mem['h114A] <= 32'h00300713; + mem['h114B] <= 32'hFEC42783; + mem['h114C] <= 32'h40F707B3; + mem['h114D] <= 32'h00279713; + mem['h114E] <= 32'hFC842783; + mem['h114F] <= 32'h00F707B3; + mem['h1150] <= 32'hFC442603; + mem['h1151] <= 32'h00078593; + mem['h1152] <= 32'h00068513; + mem['h1153] <= 32'h805FF0EF; + mem['h1154] <= 32'hFEC42783; + mem['h1155] <= 32'hFFF78793; + mem['h1156] <= 32'hFEF42623; + mem['h1157] <= 32'hFEC42783; + mem['h1158] <= 32'hFA07DAE3; + mem['h1159] <= 32'h00000013; + mem['h115A] <= 32'h00000013; + mem['h115B] <= 32'h03C12083; + mem['h115C] <= 32'h03812403; + mem['h115D] <= 32'h04010113; + mem['h115E] <= 32'h00008067; + mem['h115F] <= 32'hFD010113; + mem['h1160] <= 32'h02112623; + mem['h1161] <= 32'h02812423; + mem['h1162] <= 32'h03010413; + mem['h1163] <= 32'hFCA42E23; + mem['h1164] <= 32'h01800793; + mem['h1165] <= 32'hFEF407A3; + mem['h1166] <= 32'h4600006F; + mem['h1167] <= 32'h00300793; + mem['h1168] <= 32'hFEF40723; + mem['h1169] <= 32'h43C0006F; + mem['h116A] <= 32'hFEE44703; + mem['h116B] <= 32'h00300793; + mem['h116C] <= 32'h00F70863; + mem['h116D] <= 32'hFEE44703; + mem['h116E] <= 32'h00400793; + mem['h116F] <= 32'h0AF71E63; + mem['h1170] <= 32'hFEF44703; + mem['h1171] <= 32'h01800793; + mem['h1172] <= 32'h04F70663; + mem['h1173] <= 32'hFEF44703; + mem['h1174] <= 32'h01A00793; + mem['h1175] <= 32'h04F70063; + mem['h1176] <= 32'hFEF44703; + mem['h1177] <= 32'h01C00793; + mem['h1178] <= 32'h02F70A63; + mem['h1179] <= 32'hFEE44703; + mem['h117A] <= 32'h00300793; + mem['h117B] <= 32'h00F71863; + mem['h117C] <= 32'hFEF44703; + mem['h117D] <= 32'h01900793; + mem['h117E] <= 32'h00F70E63; + mem['h117F] <= 32'hFEE44703; + mem['h1180] <= 32'h00400793; + mem['h1181] <= 32'h04F71063; + mem['h1182] <= 32'hFEF44703; + mem['h1183] <= 32'h01B00793; + mem['h1184] <= 32'h02F71A63; + mem['h1185] <= 32'hFEF44703; + mem['h1186] <= 32'h00070793; + mem['h1187] <= 32'h00279793; + mem['h1188] <= 32'h00E787B3; + mem['h1189] <= 32'h00379793; + mem['h118A] <= 32'h00078713; + mem['h118B] <= 32'hFEE44783; + mem['h118C] <= 32'h00F707B3; + mem['h118D] <= 32'h07C00713; + mem['h118E] <= 32'h00F707B3; + mem['h118F] <= 32'h00078023; + mem['h1190] <= 32'h3940006F; + mem['h1191] <= 32'hFEF44703; + mem['h1192] <= 32'h00070793; + mem['h1193] <= 32'h00279793; + mem['h1194] <= 32'h00E787B3; + mem['h1195] <= 32'h00379793; + mem['h1196] <= 32'h00078713; + mem['h1197] <= 32'hFEE44783; + mem['h1198] <= 32'h00F707B3; + mem['h1199] <= 32'h07C00713; + mem['h119A] <= 32'h00F707B3; + mem['h119B] <= 32'h00900713; + mem['h119C] <= 32'h00E78023; + mem['h119D] <= 32'h3600006F; + mem['h119E] <= 32'hFEE44703; + mem['h119F] <= 32'h00600793; + mem['h11A0] <= 32'h00F70863; + mem['h11A1] <= 32'hFEE44703; + mem['h11A2] <= 32'h00700793; + mem['h11A3] <= 32'h08F71663; + mem['h11A4] <= 32'hFEE44703; + mem['h11A5] <= 32'h00600793; + mem['h11A6] <= 32'h00F70E63; + mem['h11A7] <= 32'hFEF44703; + mem['h11A8] <= 32'h01800793; + mem['h11A9] <= 32'h00F70863; + mem['h11AA] <= 32'hFEF44703; + mem['h11AB] <= 32'h01C00793; + mem['h11AC] <= 32'h02F71A63; + mem['h11AD] <= 32'hFEF44703; + mem['h11AE] <= 32'h00070793; + mem['h11AF] <= 32'h00279793; + mem['h11B0] <= 32'h00E787B3; + mem['h11B1] <= 32'h00379793; + mem['h11B2] <= 32'h00078713; + mem['h11B3] <= 32'hFEE44783; + mem['h11B4] <= 32'h00F707B3; + mem['h11B5] <= 32'h07C00713; + mem['h11B6] <= 32'h00F707B3; + mem['h11B7] <= 32'h00078023; + mem['h11B8] <= 32'h2F40006F; + mem['h11B9] <= 32'hFEF44703; + mem['h11BA] <= 32'h00070793; + mem['h11BB] <= 32'h00279793; + mem['h11BC] <= 32'h00E787B3; + mem['h11BD] <= 32'h00379793; + mem['h11BE] <= 32'h00078713; + mem['h11BF] <= 32'hFEE44783; + mem['h11C0] <= 32'h00F707B3; + mem['h11C1] <= 32'h07C00713; + mem['h11C2] <= 32'h00F707B3; + mem['h11C3] <= 32'h00900713; + mem['h11C4] <= 32'h00E78023; + mem['h11C5] <= 32'h2C00006F; + mem['h11C6] <= 32'hFEE44703; + mem['h11C7] <= 32'h00900793; + mem['h11C8] <= 32'h00F70E63; + mem['h11C9] <= 32'hFEE44703; + mem['h11CA] <= 32'h00A00793; + mem['h11CB] <= 32'h00F70863; + mem['h11CC] <= 32'hFEE44703; + mem['h11CD] <= 32'h00B00793; + mem['h11CE] <= 32'h08F71C63; + mem['h11CF] <= 32'hFEE44703; + mem['h11D0] <= 32'h00900793; + mem['h11D1] <= 32'h02F70463; + mem['h11D2] <= 32'hFEE44703; + mem['h11D3] <= 32'h00B00793; + mem['h11D4] <= 32'h00F70E63; + mem['h11D5] <= 32'hFEF44703; + mem['h11D6] <= 32'h01800793; + mem['h11D7] <= 32'h00F70863; + mem['h11D8] <= 32'hFEF44703; + mem['h11D9] <= 32'h01C00793; + mem['h11DA] <= 32'h02F71A63; + mem['h11DB] <= 32'hFEF44703; + mem['h11DC] <= 32'h00070793; + mem['h11DD] <= 32'h00279793; + mem['h11DE] <= 32'h00E787B3; + mem['h11DF] <= 32'h00379793; + mem['h11E0] <= 32'h00078713; + mem['h11E1] <= 32'hFEE44783; + mem['h11E2] <= 32'h00F707B3; + mem['h11E3] <= 32'h07C00713; + mem['h11E4] <= 32'h00F707B3; + mem['h11E5] <= 32'h00078023; + mem['h11E6] <= 32'h23C0006F; + mem['h11E7] <= 32'hFEF44703; + mem['h11E8] <= 32'h00070793; + mem['h11E9] <= 32'h00279793; + mem['h11EA] <= 32'h00E787B3; + mem['h11EB] <= 32'h00379793; + mem['h11EC] <= 32'h00078713; + mem['h11ED] <= 32'hFEE44783; + mem['h11EE] <= 32'h00F707B3; + mem['h11EF] <= 32'h07C00713; + mem['h11F0] <= 32'h00F707B3; + mem['h11F1] <= 32'h00900713; + mem['h11F2] <= 32'h00E78023; + mem['h11F3] <= 32'h2080006F; + mem['h11F4] <= 32'hFEE44703; + mem['h11F5] <= 32'h00D00793; + mem['h11F6] <= 32'h00F70E63; + mem['h11F7] <= 32'hFEE44703; + mem['h11F8] <= 32'h00E00793; + mem['h11F9] <= 32'h00F70863; + mem['h11FA] <= 32'hFEE44703; + mem['h11FB] <= 32'h00F00793; + mem['h11FC] <= 32'h0AF71E63; + mem['h11FD] <= 32'hFEE44703; + mem['h11FE] <= 32'h00D00793; + mem['h11FF] <= 32'h04F70663; + mem['h1200] <= 32'hFEE44703; + mem['h1201] <= 32'h00E00793; + mem['h1202] <= 32'h00F71E63; + mem['h1203] <= 32'hFEF44703; + mem['h1204] <= 32'h01800793; + mem['h1205] <= 32'h02F70A63; + mem['h1206] <= 32'hFEF44703; + mem['h1207] <= 32'h01A00793; + mem['h1208] <= 32'h02F70463; + mem['h1209] <= 32'hFEE44703; + mem['h120A] <= 32'h00F00793; + mem['h120B] <= 32'h04F71663; + mem['h120C] <= 32'hFEF44703; + mem['h120D] <= 32'h01900793; + mem['h120E] <= 32'h00F70863; + mem['h120F] <= 32'hFEF44703; + mem['h1210] <= 32'h01A00793; + mem['h1211] <= 32'h02E7FA63; + mem['h1212] <= 32'hFEF44703; + mem['h1213] <= 32'h00070793; + mem['h1214] <= 32'h00279793; + mem['h1215] <= 32'h00E787B3; + mem['h1216] <= 32'h00379793; + mem['h1217] <= 32'h00078713; + mem['h1218] <= 32'hFEE44783; + mem['h1219] <= 32'h00F707B3; + mem['h121A] <= 32'h07C00713; + mem['h121B] <= 32'h00F707B3; + mem['h121C] <= 32'h00078023; + mem['h121D] <= 32'h1600006F; + mem['h121E] <= 32'hFEF44703; + mem['h121F] <= 32'h00070793; + mem['h1220] <= 32'h00279793; + mem['h1221] <= 32'h00E787B3; + mem['h1222] <= 32'h00379793; + mem['h1223] <= 32'h00078713; + mem['h1224] <= 32'hFEE44783; + mem['h1225] <= 32'h00F707B3; + mem['h1226] <= 32'h07C00713; + mem['h1227] <= 32'h00F707B3; + mem['h1228] <= 32'h00900713; + mem['h1229] <= 32'h00E78023; + mem['h122A] <= 32'h12C0006F; + mem['h122B] <= 32'hFEE44703; + mem['h122C] <= 32'h01100793; + mem['h122D] <= 32'h00F70863; + mem['h122E] <= 32'hFEE44703; + mem['h122F] <= 32'h01200793; + mem['h1230] <= 32'h08F71863; + mem['h1231] <= 32'hFEE44703; + mem['h1232] <= 32'h01100793; + mem['h1233] <= 32'h02F70063; + mem['h1234] <= 32'hFEE44703; + mem['h1235] <= 32'h01200793; + mem['h1236] <= 32'h04F71263; + mem['h1237] <= 32'hFEF44783; + mem['h1238] <= 32'h0017F793; + mem['h1239] <= 32'h0FF7F793; + mem['h123A] <= 32'h02079A63; + mem['h123B] <= 32'hFEF44703; + mem['h123C] <= 32'h00070793; + mem['h123D] <= 32'h00279793; + mem['h123E] <= 32'h00E787B3; + mem['h123F] <= 32'h00379793; + mem['h1240] <= 32'h00078713; + mem['h1241] <= 32'hFEE44783; + mem['h1242] <= 32'h00F707B3; + mem['h1243] <= 32'h07C00713; + mem['h1244] <= 32'h00F707B3; + mem['h1245] <= 32'h00078023; + mem['h1246] <= 32'h0BC0006F; + mem['h1247] <= 32'hFEF44703; + mem['h1248] <= 32'h00070793; + mem['h1249] <= 32'h00279793; + mem['h124A] <= 32'h00E787B3; + mem['h124B] <= 32'h00379793; + mem['h124C] <= 32'h00078713; + mem['h124D] <= 32'hFEE44783; + mem['h124E] <= 32'h00F707B3; + mem['h124F] <= 32'h07C00713; + mem['h1250] <= 32'h00F707B3; + mem['h1251] <= 32'h00900713; + mem['h1252] <= 32'h00E78023; + mem['h1253] <= 32'h0880006F; + mem['h1254] <= 32'hFEE44703; + mem['h1255] <= 32'h01400793; + mem['h1256] <= 32'h06F71E63; + mem['h1257] <= 32'hFEF44703; + mem['h1258] <= 32'h01900793; + mem['h1259] <= 32'h00F70863; + mem['h125A] <= 32'hFEF44703; + mem['h125B] <= 32'h01B00793; + mem['h125C] <= 32'h02F71A63; + mem['h125D] <= 32'hFEF44703; + mem['h125E] <= 32'h00070793; + mem['h125F] <= 32'h00279793; + mem['h1260] <= 32'h00E787B3; + mem['h1261] <= 32'h00379793; + mem['h1262] <= 32'h00078713; + mem['h1263] <= 32'hFEE44783; + mem['h1264] <= 32'h00F707B3; + mem['h1265] <= 32'h07C00713; + mem['h1266] <= 32'h00F707B3; + mem['h1267] <= 32'h00078023; + mem['h1268] <= 32'h0340006F; + mem['h1269] <= 32'hFEF44703; + mem['h126A] <= 32'h00070793; + mem['h126B] <= 32'h00279793; + mem['h126C] <= 32'h00E787B3; + mem['h126D] <= 32'h00379793; + mem['h126E] <= 32'h00078713; + mem['h126F] <= 32'hFEE44783; + mem['h1270] <= 32'h00F707B3; + mem['h1271] <= 32'h07C00713; + mem['h1272] <= 32'h00F707B3; + mem['h1273] <= 32'h00900713; + mem['h1274] <= 32'h00E78023; + mem['h1275] <= 32'hFEE44783; + mem['h1276] <= 32'h00178793; + mem['h1277] <= 32'hFEF40723; + mem['h1278] <= 32'hFEE44703; + mem['h1279] <= 32'h01400793; + mem['h127A] <= 32'hBCE7F0E3; + mem['h127B] <= 32'hFEF44783; + mem['h127C] <= 32'h00178793; + mem['h127D] <= 32'hFEF407A3; + mem['h127E] <= 32'hFEF44703; + mem['h127F] <= 32'h01C00793; + mem['h1280] <= 32'hB8E7FEE3; + mem['h1281] <= 32'h01800613; + mem['h1282] <= 32'h01600593; + mem['h1283] <= 32'hFDC42503; + mem['h1284] <= 32'hA85FF0EF; + mem['h1285] <= 32'h00000013; + mem['h1286] <= 32'h02C12083; + mem['h1287] <= 32'h02812403; + mem['h1288] <= 32'h03010113; + mem['h1289] <= 32'h00008067; + mem['h128A] <= 32'hFE010113; + mem['h128B] <= 32'h00812E23; + mem['h128C] <= 32'h02010413; + mem['h128D] <= 32'hFE0407A3; + mem['h128E] <= 32'h0940006F; + mem['h128F] <= 32'hFE040723; + mem['h1290] <= 32'h0740006F; + mem['h1291] <= 32'hFEF44783; + mem['h1292] <= 32'h02078463; + mem['h1293] <= 32'hFEF44703; + mem['h1294] <= 32'h01600793; + mem['h1295] <= 32'h00E7EE63; + mem['h1296] <= 32'hFEE44703; + mem['h1297] <= 32'h01300793; + mem['h1298] <= 32'h00F70863; + mem['h1299] <= 32'hFEE44703; + mem['h129A] <= 32'h01400793; + mem['h129B] <= 32'h00F71663; + mem['h129C] <= 32'h00900713; + mem['h129D] <= 32'h0080006F; + mem['h129E] <= 32'h00000713; + mem['h129F] <= 32'hFEF44683; + mem['h12A0] <= 32'h00068793; + mem['h12A1] <= 32'h00279793; + mem['h12A2] <= 32'h00D787B3; + mem['h12A3] <= 32'h00379793; + mem['h12A4] <= 32'h00078693; + mem['h12A5] <= 32'hFEE44783; + mem['h12A6] <= 32'h00F687B3; + mem['h12A7] <= 32'h07C00693; + mem['h12A8] <= 32'h00F687B3; + mem['h12A9] <= 32'h00E78023; + mem['h12AA] <= 32'hFEE44783; + mem['h12AB] <= 32'h00178793; + mem['h12AC] <= 32'hFEF40723; + mem['h12AD] <= 32'hFEE44703; + mem['h12AE] <= 32'h02700793; + mem['h12AF] <= 32'hF8E7F4E3; + mem['h12B0] <= 32'hFEF44783; + mem['h12B1] <= 32'h00178793; + mem['h12B2] <= 32'hFEF407A3; + mem['h12B3] <= 32'hFEF44703; + mem['h12B4] <= 32'h01D00793; + mem['h12B5] <= 32'hF6E7F4E3; + mem['h12B6] <= 32'h00000013; + mem['h12B7] <= 32'h00000013; + mem['h12B8] <= 32'h01C12403; + mem['h12B9] <= 32'h02010113; + mem['h12BA] <= 32'h00008067; + mem['h12BB] <= 32'hFD010113; + mem['h12BC] <= 32'h02112623; + mem['h12BD] <= 32'h02812423; + mem['h12BE] <= 32'h03010413; + mem['h12BF] <= 32'hFCA42E23; + mem['h12C0] <= 32'hFE041723; + mem['h12C1] <= 32'hFE042423; + mem['h12C2] <= 32'h0340006F; + mem['h12C3] <= 32'h001067B7; + mem['h12C4] <= 32'hAF478513; + mem['h12C5] <= 32'h6E9000EF; + mem['h12C6] <= 32'hFE842783; + mem['h12C7] <= 32'h0017F793; + mem['h12C8] <= 32'h00079863; + mem['h12C9] <= 32'hFEE45783; + mem['h12CA] <= 32'h00178793; + mem['h12CB] <= 32'hFEF41723; + mem['h12CC] <= 32'hFE842783; + mem['h12CD] <= 32'h00178793; + mem['h12CE] <= 32'hFEF42423; + mem['h12CF] <= 32'hFE842703; + mem['h12D0] <= 32'hFDC42783; + mem['h12D1] <= 32'hFCF764E3; + mem['h12D2] <= 32'h00000013; + mem['h12D3] <= 32'h00000013; + mem['h12D4] <= 32'h02C12083; + mem['h12D5] <= 32'h02812403; + mem['h12D6] <= 32'h03010113; + mem['h12D7] <= 32'h00008067; + mem['h12D8] <= 32'hFD010113; + mem['h12D9] <= 32'h02812623; + mem['h12DA] <= 32'h03010413; + mem['h12DB] <= 32'hFCA42E23; + mem['h12DC] <= 32'hFDC42783; + mem['h12DD] <= 32'h0007A783; + mem['h12DE] <= 32'hFEF42623; + mem['h12DF] <= 32'hFEC42783; + mem['h12E0] <= 32'h00D79793; + mem['h12E1] <= 32'hFEC42703; + mem['h12E2] <= 32'h00F747B3; + mem['h12E3] <= 32'hFEF42623; + mem['h12E4] <= 32'hFEC42783; + mem['h12E5] <= 32'h0117D793; + mem['h12E6] <= 32'hFEC42703; + mem['h12E7] <= 32'h00F747B3; + mem['h12E8] <= 32'hFEF42623; + mem['h12E9] <= 32'hFEC42783; + mem['h12EA] <= 32'h00579793; + mem['h12EB] <= 32'hFEC42703; + mem['h12EC] <= 32'h00F747B3; + mem['h12ED] <= 32'hFEF42623; + mem['h12EE] <= 32'hFDC42783; + mem['h12EF] <= 32'hFEC42703; + mem['h12F0] <= 32'h00E7A023; + mem['h12F1] <= 32'hFEC42783; + mem['h12F2] <= 32'h00078513; + mem['h12F3] <= 32'h02C12403; + mem['h12F4] <= 32'h03010113; + mem['h12F5] <= 32'h00008067; + mem['h12F6] <= 32'hFF010113; + mem['h12F7] <= 32'h00112623; + mem['h12F8] <= 32'h00812423; + mem['h12F9] <= 32'h01010413; + mem['h12FA] <= 32'h07400513; + mem['h12FB] <= 32'hF75FF0EF; + mem['h12FC] <= 32'h00050793; + mem['h12FD] <= 32'h0017F793; + mem['h12FE] <= 32'h00078513; + mem['h12FF] <= 32'h00C12083; + mem['h1300] <= 32'h00812403; + mem['h1301] <= 32'h01010113; + mem['h1302] <= 32'h00008067; + mem['h1303] <= 32'hFD010113; + mem['h1304] <= 32'h02112623; + mem['h1305] <= 32'h02812423; + mem['h1306] <= 32'h03010413; + mem['h1307] <= 32'hFCA42E23; + mem['h1308] <= 32'hFCB42C23; + mem['h1309] <= 32'hFD842703; + mem['h130A] <= 32'hFDC42783; + mem['h130B] <= 32'h40F707B3; + mem['h130C] <= 32'h00178793; + mem['h130D] <= 32'hFEF42623; + mem['h130E] <= 32'h07800513; + mem['h130F] <= 32'hF25FF0EF; + mem['h1310] <= 32'h00050713; + mem['h1311] <= 32'hFEC42783; + mem['h1312] <= 32'h02F77733; + mem['h1313] <= 32'hFDC42783; + mem['h1314] <= 32'h00F707B3; + mem['h1315] <= 32'hFEF42423; + mem['h1316] <= 32'hFE842783; + mem['h1317] <= 32'h00078513; + mem['h1318] <= 32'h02C12083; + mem['h1319] <= 32'h02812403; + mem['h131A] <= 32'h03010113; + mem['h131B] <= 32'h00008067; + mem['h131C] <= 32'hF9010113; + mem['h131D] <= 32'h06112623; + mem['h131E] <= 32'h06812423; + mem['h131F] <= 32'h06912223; + mem['h1320] <= 32'h07010413; + mem['h1321] <= 32'h020007B7; + mem['h1322] <= 32'h00478793; + mem['h1323] <= 32'h0D900713; + mem['h1324] <= 32'h00E7A023; + mem['h1325] <= 32'h001067B7; + mem['h1326] <= 32'hB0478513; + mem['h1327] <= 32'h561000EF; + mem['h1328] <= 32'hFE0407A3; + mem['h1329] <= 32'hFE040723; + mem['h132A] <= 32'hFE0406A3; + mem['h132B] <= 32'hFE040623; + mem['h132C] <= 32'hFE0405A3; + mem['h132D] <= 32'h030007B7; + mem['h132E] <= 32'h0007A023; + mem['h132F] <= 32'hB80FE0EF; + mem['h1330] <= 32'hC44FB0EF; + mem['h1331] <= 32'h000017B7; + mem['h1332] <= 32'hBB878513; + mem['h1333] <= 32'hE21FF0EF; + mem['h1334] <= 32'hA01FB0EF; + mem['h1335] <= 32'h000017B7; + mem['h1336] <= 32'hBB878513; + mem['h1337] <= 32'hE11FF0EF; + mem['h1338] <= 32'hC40FC0EF; + mem['h1339] <= 32'h000017B7; + mem['h133A] <= 32'hBB878513; + mem['h133B] <= 32'hE01FF0EF; + mem['h133C] <= 32'hD39FF0EF; + mem['h133D] <= 32'h00C00513; + mem['h133E] <= 32'hD38FD0EF; + mem['h133F] <= 32'h00300613; + mem['h1340] <= 32'h00900593; + mem['h1341] <= 32'h00500513; + mem['h1342] <= 32'hE45FC0EF; + mem['h1343] <= 32'h00300613; + mem['h1344] <= 32'h00900593; + mem['h1345] <= 32'h00F00513; + mem['h1346] <= 32'hE35FC0EF; + mem['h1347] <= 32'h00300613; + mem['h1348] <= 32'h00900593; + mem['h1349] <= 32'h01900513; + mem['h134A] <= 32'hE25FC0EF; + mem['h134B] <= 32'h000017B7; + mem['h134C] <= 32'hFA078513; + mem['h134D] <= 32'hDB9FF0EF; + mem['h134E] <= 32'hFE041423; + mem['h134F] <= 32'h00300793; + mem['h1350] <= 32'hFEF403A3; + mem['h1351] <= 32'hFE040323; + mem['h1352] <= 32'h00F00793; + mem['h1353] <= 32'hFEF402A3; + mem['h1354] <= 32'h00F00793; + mem['h1355] <= 32'hFEF40223; + mem['h1356] <= 32'hFE0401A3; + mem['h1357] <= 32'h00300793; + mem['h1358] <= 32'hFEF40123; + mem['h1359] <= 32'hFA0400A3; + mem['h135A] <= 32'h00100793; + mem['h135B] <= 32'hFEF400A3; + mem['h135C] <= 32'hFC041F23; + mem['h135D] <= 32'hFC041E23; + mem['h135E] <= 32'hF8042E23; + mem['h135F] <= 32'hFC040DA3; + mem['h1360] <= 32'hFC040D23; + mem['h1361] <= 32'hFC040CA3; + mem['h1362] <= 32'hFC040C23; + mem['h1363] <= 32'hFC040BA3; + mem['h1364] <= 32'hFC040B23; + mem['h1365] <= 32'hFDC45783; + mem['h1366] <= 32'h00078513; + mem['h1367] <= 32'hFE0FF0EF; + mem['h1368] <= 32'hFDA44783; + mem['h1369] <= 32'h00078E63; + mem['h136A] <= 32'hFE244703; + mem['h136B] <= 32'h00100793; + mem['h136C] <= 32'h00F71863; + mem['h136D] <= 32'h00100793; + mem['h136E] <= 32'hFCF40CA3; + mem['h136F] <= 32'hFC040D23; + mem['h1370] <= 32'hFDA44783; + mem['h1371] <= 32'h0C078E63; + mem['h1372] <= 32'hFE244783; + mem['h1373] <= 32'hFFF78793; + mem['h1374] <= 32'hFEF40123; + mem['h1375] <= 32'hFE244783; + mem['h1376] <= 32'h00078513; + mem['h1377] <= 32'hCECFD0EF; + mem['h1378] <= 32'h000017B7; + mem['h1379] <= 32'hFA078513; + mem['h137A] <= 32'hD05FF0EF; + mem['h137B] <= 32'hFC040AA3; + mem['h137C] <= 32'h0940006F; + mem['h137D] <= 32'hFC040A23; + mem['h137E] <= 32'h0740006F; + mem['h137F] <= 32'hFD544783; + mem['h1380] <= 32'h02078463; + mem['h1381] <= 32'hFD544703; + mem['h1382] <= 32'h01600793; + mem['h1383] <= 32'h00E7EE63; + mem['h1384] <= 32'hFD444703; + mem['h1385] <= 32'h01300793; + mem['h1386] <= 32'h00F70863; + mem['h1387] <= 32'hFD444703; + mem['h1388] <= 32'h01400793; + mem['h1389] <= 32'h00F71663; + mem['h138A] <= 32'h00900713; + mem['h138B] <= 32'h0080006F; + mem['h138C] <= 32'h00000713; + mem['h138D] <= 32'hFD544683; + mem['h138E] <= 32'h00068793; + mem['h138F] <= 32'h00279793; + mem['h1390] <= 32'h00D787B3; + mem['h1391] <= 32'h00379793; + mem['h1392] <= 32'h00078693; + mem['h1393] <= 32'hFD444783; + mem['h1394] <= 32'h00F687B3; + mem['h1395] <= 32'h07C00693; + mem['h1396] <= 32'h00F687B3; + mem['h1397] <= 32'h00E78023; + mem['h1398] <= 32'hFD444783; + mem['h1399] <= 32'h00178793; + mem['h139A] <= 32'hFCF40A23; + mem['h139B] <= 32'hFD444703; + mem['h139C] <= 32'h02700793; + mem['h139D] <= 32'hF8E7F4E3; + mem['h139E] <= 32'hFD544783; + mem['h139F] <= 32'h00178793; + mem['h13A0] <= 32'hFCF40AA3; + mem['h13A1] <= 32'hFD544703; + mem['h13A2] <= 32'h01D00793; + mem['h13A3] <= 32'hF6E7F4E3; + mem['h13A4] <= 32'hFC040D23; + mem['h13A5] <= 32'hFDC45783; + mem['h13A6] <= 32'h00078513; + mem['h13A7] <= 32'hEE0FF0EF; + mem['h13A8] <= 32'hFD944783; + mem['h13A9] <= 32'h0C078E63; + mem['h13AA] <= 32'hCADFD0EF; + mem['h13AB] <= 32'h0080006F; + mem['h13AC] <= 32'hA24FB0EF; + mem['h13AD] <= 32'h52C04783; + mem['h13AE] <= 32'h0107F793; + mem['h13AF] <= 32'hFE078AE3; + mem['h13B0] <= 32'hFC0409A3; + mem['h13B1] <= 32'h0940006F; + mem['h13B2] <= 32'hFC040923; + mem['h13B3] <= 32'h0740006F; + mem['h13B4] <= 32'hFD344783; + mem['h13B5] <= 32'h02078463; + mem['h13B6] <= 32'hFD344703; + mem['h13B7] <= 32'h01600793; + mem['h13B8] <= 32'h00E7EE63; + mem['h13B9] <= 32'hFD244703; + mem['h13BA] <= 32'h01300793; + mem['h13BB] <= 32'h00F70863; + mem['h13BC] <= 32'hFD244703; + mem['h13BD] <= 32'h01400793; + mem['h13BE] <= 32'h00F71663; + mem['h13BF] <= 32'h00900713; + mem['h13C0] <= 32'h0080006F; + mem['h13C1] <= 32'h00000713; + mem['h13C2] <= 32'hFD344683; + mem['h13C3] <= 32'h00068793; + mem['h13C4] <= 32'h00279793; + mem['h13C5] <= 32'h00D787B3; + mem['h13C6] <= 32'h00379793; + mem['h13C7] <= 32'h00078693; + mem['h13C8] <= 32'hFD244783; + mem['h13C9] <= 32'h00F687B3; + mem['h13CA] <= 32'h07C00693; + mem['h13CB] <= 32'h00F687B3; + mem['h13CC] <= 32'h00E78023; + mem['h13CD] <= 32'hFD244783; + mem['h13CE] <= 32'h00178793; + mem['h13CF] <= 32'hFCF40923; + mem['h13D0] <= 32'hFD244703; + mem['h13D1] <= 32'h02700793; + mem['h13D2] <= 32'hF8E7F4E3; + mem['h13D3] <= 32'hFD344783; + mem['h13D4] <= 32'h00178793; + mem['h13D5] <= 32'hFCF409A3; + mem['h13D6] <= 32'hFD344703; + mem['h13D7] <= 32'h01D00793; + mem['h13D8] <= 32'hF6E7F4E3; + mem['h13D9] <= 32'hFC040CA3; + mem['h13DA] <= 32'hFC041E23; + mem['h13DB] <= 32'h00F00793; + mem['h13DC] <= 32'hFEF40223; + mem['h13DD] <= 32'hFDC45783; + mem['h13DE] <= 32'h00078513; + mem['h13DF] <= 32'hE00FF0EF; + mem['h13E0] <= 32'h07002783; + mem['h13E1] <= 32'hFFF78713; + mem['h13E2] <= 32'h06E02823; + mem['h13E3] <= 32'h948FB0EF; + mem['h13E4] <= 32'h52C04783; + mem['h13E5] <= 32'h0017F793; + mem['h13E6] <= 32'h00078C63; + mem['h13E7] <= 32'h00100793; + mem['h13E8] <= 32'hFEF40623; + mem['h13E9] <= 32'h001067B7; + mem['h13EA] <= 32'hB1478513; + mem['h13EB] <= 32'h251000EF; + mem['h13EC] <= 32'h52C04783; + mem['h13ED] <= 32'h0087F793; + mem['h13EE] <= 32'h00078C63; + mem['h13EF] <= 32'h00100793; + mem['h13F0] <= 32'hFEF40723; + mem['h13F1] <= 32'h001067B7; + mem['h13F2] <= 32'hB2078513; + mem['h13F3] <= 32'h231000EF; + mem['h13F4] <= 32'h52C04783; + mem['h13F5] <= 32'h0027F793; + mem['h13F6] <= 32'h00078C63; + mem['h13F7] <= 32'h00100793; + mem['h13F8] <= 32'hFEF407A3; + mem['h13F9] <= 32'h001067B7; + mem['h13FA] <= 32'hB3078513; + mem['h13FB] <= 32'h211000EF; + mem['h13FC] <= 32'h52C04783; + mem['h13FD] <= 32'h0047F793; + mem['h13FE] <= 32'h00078C63; + mem['h13FF] <= 32'h00100793; + mem['h1400] <= 32'hFEF405A3; + mem['h1401] <= 32'h001067B7; + mem['h1402] <= 32'hB4078513; + mem['h1403] <= 32'h1F1000EF; + mem['h1404] <= 32'h52C04783; + mem['h1405] <= 32'h0107F793; + mem['h1406] <= 32'h00078C63; + mem['h1407] <= 32'h00100793; + mem['h1408] <= 32'hFEF406A3; + mem['h1409] <= 32'h001067B7; + mem['h140A] <= 32'hB5078513; + mem['h140B] <= 32'h1D1000EF; + mem['h140C] <= 32'h52C04783; + mem['h140D] <= 32'h1007E713; + mem['h140E] <= 32'h030007B7; + mem['h140F] <= 32'h00E7A023; + mem['h1410] <= 32'h07002783; + mem['h1411] <= 32'hD4079EE3; + mem['h1412] <= 32'h00001737; + mem['h1413] <= 32'h9C470713; + mem['h1414] <= 32'h06E02823; + mem['h1415] <= 32'hFE344783; + mem['h1416] <= 32'h00178793; + mem['h1417] <= 32'hFEF401A3; + mem['h1418] <= 32'hFE344703; + mem['h1419] <= 32'hFE444783; + mem['h141A] <= 32'h40F707B3; + mem['h141B] <= 32'h0017B793; + mem['h141C] <= 32'hFAF400A3; + mem['h141D] <= 32'hFD644783; + mem['h141E] <= 32'h0E079663; + mem['h141F] <= 32'hFEE44783; + mem['h1420] <= 32'h02078A63; + mem['h1421] <= 32'hFE845703; + mem['h1422] <= 32'hFE744583; + mem['h1423] <= 32'hFE644603; + mem['h1424] <= 32'hFE544783; + mem['h1425] <= 32'h00178793; + mem['h1426] <= 32'h00078693; + mem['h1427] <= 32'h00070513; + mem['h1428] <= 32'hB6DFE0EF; + mem['h1429] <= 32'h00050793; + mem['h142A] <= 32'h00078663; + mem['h142B] <= 32'h00100793; + mem['h142C] <= 32'h0080006F; + mem['h142D] <= 32'h00000793; + mem['h142E] <= 32'h0FF7F713; + mem['h142F] <= 32'hFE544783; + mem['h1430] <= 32'h00F707B3; + mem['h1431] <= 32'hFEF402A3; + mem['h1432] <= 32'hFEC44783; + mem['h1433] <= 32'h02078A63; + mem['h1434] <= 32'hFE845703; + mem['h1435] <= 32'hFE744583; + mem['h1436] <= 32'hFE644603; + mem['h1437] <= 32'hFE544783; + mem['h1438] <= 32'hFFF78793; + mem['h1439] <= 32'h00078693; + mem['h143A] <= 32'h00070513; + mem['h143B] <= 32'hB21FE0EF; + mem['h143C] <= 32'h00050793; + mem['h143D] <= 32'h00078663; + mem['h143E] <= 32'h00100793; + mem['h143F] <= 32'h0080006F; + mem['h1440] <= 32'h00000793; + mem['h1441] <= 32'h0FF7F793; + mem['h1442] <= 32'hFE544703; + mem['h1443] <= 32'h40F707B3; + mem['h1444] <= 32'hFEF402A3; + mem['h1445] <= 32'hFEF44783; + mem['h1446] <= 32'h02078A63; + mem['h1447] <= 32'hFE845703; + mem['h1448] <= 32'hFE744583; + mem['h1449] <= 32'hFE644783; + mem['h144A] <= 32'h00178793; + mem['h144B] <= 32'hFE544683; + mem['h144C] <= 32'h00078613; + mem['h144D] <= 32'h00070513; + mem['h144E] <= 32'hAD5FE0EF; + mem['h144F] <= 32'h00050793; + mem['h1450] <= 32'h00078663; + mem['h1451] <= 32'h00100793; + mem['h1452] <= 32'h0080006F; + mem['h1453] <= 32'h00000793; + mem['h1454] <= 32'h0FF7F713; + mem['h1455] <= 32'hFE644783; + mem['h1456] <= 32'h00F707B3; + mem['h1457] <= 32'hFEF40323; + mem['h1458] <= 32'h0E80006F; + mem['h1459] <= 32'hFEC44783; + mem['h145A] <= 32'h02078A63; + mem['h145B] <= 32'hFE845703; + mem['h145C] <= 32'hFE744583; + mem['h145D] <= 32'hFE644603; + mem['h145E] <= 32'hFE544783; + mem['h145F] <= 32'hFFF78793; + mem['h1460] <= 32'h00078693; + mem['h1461] <= 32'h00070513; + mem['h1462] <= 32'hA85FE0EF; + mem['h1463] <= 32'h00050793; + mem['h1464] <= 32'h00078663; + mem['h1465] <= 32'h00100793; + mem['h1466] <= 32'h0080006F; + mem['h1467] <= 32'h00000793; + mem['h1468] <= 32'h0FF7F793; + mem['h1469] <= 32'hFE544703; + mem['h146A] <= 32'h40F707B3; + mem['h146B] <= 32'hFEF402A3; + mem['h146C] <= 32'hFEE44783; + mem['h146D] <= 32'h02078A63; + mem['h146E] <= 32'hFE845703; + mem['h146F] <= 32'hFE744583; + mem['h1470] <= 32'hFE644603; + mem['h1471] <= 32'hFE544783; + mem['h1472] <= 32'h00178793; + mem['h1473] <= 32'h00078693; + mem['h1474] <= 32'h00070513; + mem['h1475] <= 32'hA39FE0EF; + mem['h1476] <= 32'h00050793; + mem['h1477] <= 32'h00078663; + mem['h1478] <= 32'h00100793; + mem['h1479] <= 32'h0080006F; + mem['h147A] <= 32'h00000793; + mem['h147B] <= 32'h0FF7F713; + mem['h147C] <= 32'hFE544783; + mem['h147D] <= 32'h00F707B3; + mem['h147E] <= 32'hFEF402A3; + mem['h147F] <= 32'hFEB44783; + mem['h1480] <= 32'h02078A63; + mem['h1481] <= 32'hFE845703; + mem['h1482] <= 32'hFE744583; + mem['h1483] <= 32'hFE644783; + mem['h1484] <= 32'hFFF78793; + mem['h1485] <= 32'hFE544683; + mem['h1486] <= 32'h00078613; + mem['h1487] <= 32'h00070513; + mem['h1488] <= 32'h9EDFE0EF; + mem['h1489] <= 32'h00050793; + mem['h148A] <= 32'h00078663; + mem['h148B] <= 32'h00100793; + mem['h148C] <= 32'h0080006F; + mem['h148D] <= 32'h00000793; + mem['h148E] <= 32'h0FF7F793; + mem['h148F] <= 32'hFE644703; + mem['h1490] <= 32'h40F707B3; + mem['h1491] <= 32'hFEF40323; + mem['h1492] <= 32'hFED44783; + mem['h1493] <= 32'h04078C63; + mem['h1494] <= 32'hFE144783; + mem['h1495] <= 32'h02078A63; + mem['h1496] <= 32'hFE845703; + mem['h1497] <= 32'hFE744783; + mem['h1498] <= 32'h00178793; + mem['h1499] <= 32'hFE644603; + mem['h149A] <= 32'hFE544683; + mem['h149B] <= 32'h00078593; + mem['h149C] <= 32'h00070513; + mem['h149D] <= 32'h999FE0EF; + mem['h149E] <= 32'h00050793; + mem['h149F] <= 32'h00078663; + mem['h14A0] <= 32'h00100793; + mem['h14A1] <= 32'h0080006F; + mem['h14A2] <= 32'h00000793; + mem['h14A3] <= 32'h0FF7F713; + mem['h14A4] <= 32'hFE744783; + mem['h14A5] <= 32'h00F707B3; + mem['h14A6] <= 32'hFEF403A3; + mem['h14A7] <= 32'hFE0400A3; + mem['h14A8] <= 32'h00C0006F; + mem['h14A9] <= 32'h00100793; + mem['h14AA] <= 32'hFEF400A3; + mem['h14AB] <= 32'hFA144783; + mem['h14AC] <= 32'h3A078663; + mem['h14AD] <= 32'hFE0401A3; + mem['h14AE] <= 32'hFDE45783; + mem['h14AF] <= 32'h00178793; + mem['h14B0] <= 32'hFCF41F23; + mem['h14B1] <= 32'hFDE45703; + mem['h14B2] <= 32'h03200793; + mem['h14B3] <= 32'h02F777B3; + mem['h14B4] <= 32'h01079793; + mem['h14B5] <= 32'h0107D793; + mem['h14B6] <= 32'h00079E63; + mem['h14B7] <= 32'hFE444703; + mem['h14B8] <= 32'h00900793; + mem['h14B9] <= 32'h00E7F863; + mem['h14BA] <= 32'hFE444783; + mem['h14BB] <= 32'hFFF78793; + mem['h14BC] <= 32'hFEF40223; + mem['h14BD] <= 32'hFE845703; + mem['h14BE] <= 32'hFE744583; + mem['h14BF] <= 32'hFE644783; + mem['h14C0] <= 32'h00178793; + mem['h14C1] <= 32'hFE544683; + mem['h14C2] <= 32'h00078613; + mem['h14C3] <= 32'h00070513; + mem['h14C4] <= 32'h8FDFE0EF; + mem['h14C5] <= 32'h00050793; + mem['h14C6] <= 32'h00078E63; + mem['h14C7] <= 32'hFD644783; + mem['h14C8] <= 32'h00079A63; + mem['h14C9] <= 32'hFE644783; + mem['h14CA] <= 32'h00178793; + mem['h14CB] <= 32'hFEF40323; + mem['h14CC] <= 32'h32C0006F; + mem['h14CD] <= 32'hFE845703; + mem['h14CE] <= 32'hFE744583; + mem['h14CF] <= 32'hFE644783; + mem['h14D0] <= 32'hFFF78793; + mem['h14D1] <= 32'hFE544683; + mem['h14D2] <= 32'h00078613; + mem['h14D3] <= 32'h00070513; + mem['h14D4] <= 32'h8BDFE0EF; + mem['h14D5] <= 32'h00050793; + mem['h14D6] <= 32'h00078E63; + mem['h14D7] <= 32'hFD644783; + mem['h14D8] <= 32'h00078A63; + mem['h14D9] <= 32'hFE644783; + mem['h14DA] <= 32'hFFF78793; + mem['h14DB] <= 32'hFEF40323; + mem['h14DC] <= 32'h2EC0006F; + mem['h14DD] <= 32'hFC042623; + mem['h14DE] <= 32'h0B00006F; + mem['h14DF] <= 32'hFC042423; + mem['h14E0] <= 32'h0900006F; + mem['h14E1] <= 32'hFE845483; + mem['h14E2] <= 32'hFE744783; + mem['h14E3] <= 32'h00078613; + mem['h14E4] <= 32'hFC842583; + mem['h14E5] <= 32'hFCC42503; + mem['h14E6] <= 32'hF88FE0EF; + mem['h14E7] <= 32'h00050693; + mem['h14E8] <= 32'h00000713; + mem['h14E9] <= 32'h00449793; + mem['h14EA] <= 32'h00F707B3; + mem['h14EB] <= 32'h00D787B3; + mem['h14EC] <= 32'h0007C783; + mem['h14ED] <= 32'h04078863; + mem['h14EE] <= 32'hFE845783; + mem['h14EF] <= 32'h0FF7F693; + mem['h14F0] <= 32'hFE544703; + mem['h14F1] <= 32'hFC842783; + mem['h14F2] <= 32'h00F70733; + mem['h14F3] <= 32'h00070793; + mem['h14F4] <= 32'h00279793; + mem['h14F5] <= 32'h00E787B3; + mem['h14F6] <= 32'h00379793; + mem['h14F7] <= 32'h00078613; + mem['h14F8] <= 32'hFE644703; + mem['h14F9] <= 32'hFCC42783; + mem['h14FA] <= 32'h00F707B3; + mem['h14FB] <= 32'h00F607B3; + mem['h14FC] <= 32'h00168713; + mem['h14FD] <= 32'h0FF77713; + mem['h14FE] <= 32'h07C00693; + mem['h14FF] <= 32'h00F687B3; + mem['h1500] <= 32'h00E78023; + mem['h1501] <= 32'hFC842783; + mem['h1502] <= 32'h00178793; + mem['h1503] <= 32'hFCF42423; + mem['h1504] <= 32'hFC842703; + mem['h1505] <= 32'h00300793; + mem['h1506] <= 32'hF6E7D6E3; + mem['h1507] <= 32'hFCC42783; + mem['h1508] <= 32'h00178793; + mem['h1509] <= 32'hFCF42623; + mem['h150A] <= 32'hFCC42703; + mem['h150B] <= 32'h00300793; + mem['h150C] <= 32'hF4E7D6E3; + mem['h150D] <= 32'hFC042223; + mem['h150E] <= 32'h13C0006F; + mem['h150F] <= 32'h00100793; + mem['h1510] <= 32'hFCF401A3; + mem['h1511] <= 32'h00100793; + mem['h1512] <= 32'hFAF42E23; + mem['h1513] <= 32'h0840006F; + mem['h1514] <= 32'hFE644703; + mem['h1515] <= 32'hFC442783; + mem['h1516] <= 32'h00F706B3; + mem['h1517] <= 32'hFBC42703; + mem['h1518] <= 32'h00070793; + mem['h1519] <= 32'h00279793; + mem['h151A] <= 32'h00E787B3; + mem['h151B] <= 32'h00379793; + mem['h151C] <= 32'h00F687B3; + mem['h151D] <= 32'h07C00713; + mem['h151E] <= 32'h00F707B3; + mem['h151F] <= 32'h0007C783; + mem['h1520] <= 32'h02078E63; + mem['h1521] <= 32'hFE644703; + mem['h1522] <= 32'hFC442783; + mem['h1523] <= 32'h00F706B3; + mem['h1524] <= 32'hFBC42703; + mem['h1525] <= 32'h00070793; + mem['h1526] <= 32'h00279793; + mem['h1527] <= 32'h00E787B3; + mem['h1528] <= 32'h00379793; + mem['h1529] <= 32'h00F687B3; + mem['h152A] <= 32'h07C00713; + mem['h152B] <= 32'h00F707B3; + mem['h152C] <= 32'h0007C703; + mem['h152D] <= 32'h00900793; + mem['h152E] <= 32'h00F71663; + mem['h152F] <= 32'hFC0401A3; + mem['h1530] <= 32'h01C0006F; + mem['h1531] <= 32'hFBC42783; + mem['h1532] <= 32'h00178793; + mem['h1533] <= 32'hFAF42E23; + mem['h1534] <= 32'hFBC42703; + mem['h1535] <= 32'h01600793; + mem['h1536] <= 32'hF6E7DCE3; + mem['h1537] <= 32'hFC344783; + mem['h1538] <= 32'h08078463; + mem['h1539] <= 32'h00100793; + mem['h153A] <= 32'hFAF42C23; + mem['h153B] <= 32'h0400006F; + mem['h153C] <= 32'hFE644703; + mem['h153D] <= 32'hFC442783; + mem['h153E] <= 32'h00F706B3; + mem['h153F] <= 32'hFB842703; + mem['h1540] <= 32'h00070793; + mem['h1541] <= 32'h00279793; + mem['h1542] <= 32'h00E787B3; + mem['h1543] <= 32'h00379793; + mem['h1544] <= 32'h00F687B3; + mem['h1545] <= 32'h07C00713; + mem['h1546] <= 32'h00F707B3; + mem['h1547] <= 32'h00078023; + mem['h1548] <= 32'hFB842783; + mem['h1549] <= 32'h00178793; + mem['h154A] <= 32'hFAF42C23; + mem['h154B] <= 32'hFB842703; + mem['h154C] <= 32'h01600793; + mem['h154D] <= 32'hFAE7DEE3; + mem['h154E] <= 32'hFC442783; + mem['h154F] <= 32'h0FF7F693; + mem['h1550] <= 32'hFDB44783; + mem['h1551] <= 32'hFE644703; + mem['h1552] <= 32'h00E68733; + mem['h1553] <= 32'h0FF77713; + mem['h1554] <= 32'hFF040693; + mem['h1555] <= 32'h00F687B3; + mem['h1556] <= 32'hFAE78623; + mem['h1557] <= 32'hFDB44783; + mem['h1558] <= 32'h00178793; + mem['h1559] <= 32'hFCF40DA3; + mem['h155A] <= 32'hFC442783; + mem['h155B] <= 32'h00178793; + mem['h155C] <= 32'hFCF42223; + mem['h155D] <= 32'hFC442703; + mem['h155E] <= 32'h00300793; + mem['h155F] <= 32'hECE7D0E3; + mem['h1560] <= 32'hFD644783; + mem['h1561] <= 32'hFCF40C23; + mem['h1562] <= 32'hFDC45783; + mem['h1563] <= 32'h00178793; + mem['h1564] <= 32'hFCF41E23; + mem['h1565] <= 32'hFDB44783; + mem['h1566] <= 32'h02078263; + mem['h1567] <= 32'hFDB44783; + mem['h1568] <= 32'h01400713; + mem['h1569] <= 32'h00F717B3; + mem['h156A] <= 32'h01079713; + mem['h156B] <= 32'h01075713; + mem['h156C] <= 32'hFDC45783; + mem['h156D] <= 32'h00F707B3; + mem['h156E] <= 32'hFCF41E23; + mem['h156F] <= 32'h00100793; + mem['h1570] <= 32'hFCF40BA3; + mem['h1571] <= 32'h01300593; + mem['h1572] <= 32'h00200513; + mem['h1573] <= 32'hE40FF0EF; + mem['h1574] <= 32'h00050793; + mem['h1575] <= 32'hFEF402A3; + mem['h1576] <= 32'hE00FF0EF; + mem['h1577] <= 32'h00050793; + mem['h1578] <= 32'hFCF40B23; + mem['h1579] <= 32'hFD644783; + mem['h157A] <= 32'h00079A63; + mem['h157B] <= 32'h00300793; + mem['h157C] <= 32'hFEF403A3; + mem['h157D] <= 32'hFE040323; + mem['h157E] <= 32'h0140006F; + mem['h157F] <= 32'h00300793; + mem['h1580] <= 32'hFEF403A3; + mem['h1581] <= 32'h02400793; + mem['h1582] <= 32'hFEF40323; + mem['h1583] <= 32'hFDE45703; + mem['h1584] <= 32'h00700793; + mem['h1585] <= 32'h02F777B3; + mem['h1586] <= 32'hFEF41423; + mem['h1587] <= 32'hFE845783; + mem['h1588] <= 32'hFE744703; + mem['h1589] <= 32'hFE644603; + mem['h158A] <= 32'hFE544683; + mem['h158B] <= 32'h00070593; + mem['h158C] <= 32'h00078513; + mem['h158D] <= 32'hDD8FE0EF; + mem['h158E] <= 32'h00050793; + mem['h158F] <= 32'h00F037B3; + mem['h1590] <= 32'h0FF7F793; + mem['h1591] <= 32'h0017C793; + mem['h1592] <= 32'h0FF7F793; + mem['h1593] <= 32'hFCF40D23; + mem['h1594] <= 32'hFDA44783; + mem['h1595] <= 32'h0017F793; + mem['h1596] <= 32'hFCF40D23; + mem['h1597] <= 32'hFD744783; + mem['h1598] <= 32'h00078E63; + mem['h1599] <= 32'hFC040BA3; + mem['h159A] <= 32'hFDC45783; + mem['h159B] <= 32'h01800613; + mem['h159C] <= 32'h01600593; + mem['h159D] <= 32'h00078513; + mem['h159E] <= 32'hE1DFE0EF; + mem['h159F] <= 32'hFA042A23; + mem['h15A0] <= 32'h0900006F; + mem['h15A1] <= 32'hFA042823; + mem['h15A2] <= 32'h0700006F; + mem['h15A3] <= 32'hFB442703; + mem['h15A4] <= 32'h00070793; + mem['h15A5] <= 32'h00279793; + mem['h15A6] <= 32'h00E787B3; + mem['h15A7] <= 32'h00379793; + mem['h15A8] <= 32'h00078713; + mem['h15A9] <= 32'hFB042783; + mem['h15AA] <= 32'h00F707B3; + mem['h15AB] <= 32'h07C00713; + mem['h15AC] <= 32'h00F707B3; + mem['h15AD] <= 32'h0007C683; + mem['h15AE] <= 32'hFB442703; + mem['h15AF] <= 32'h00070793; + mem['h15B0] <= 32'h00279793; + mem['h15B1] <= 32'h00E787B3; + mem['h15B2] <= 32'h00379793; + mem['h15B3] <= 32'h00078713; + mem['h15B4] <= 32'hFB042783; + mem['h15B5] <= 32'h00F707B3; + mem['h15B6] <= 32'h00279713; + mem['h15B7] <= 32'h052007B7; + mem['h15B8] <= 32'h00F707B3; + mem['h15B9] <= 32'h00068713; + mem['h15BA] <= 32'h00E7A023; + mem['h15BB] <= 32'hFB042783; + mem['h15BC] <= 32'h00178793; + mem['h15BD] <= 32'hFAF42823; + mem['h15BE] <= 32'hFB042703; + mem['h15BF] <= 32'h02700793; + mem['h15C0] <= 32'hF8E7D6E3; + mem['h15C1] <= 32'hFB442783; + mem['h15C2] <= 32'h00178793; + mem['h15C3] <= 32'hFAF42A23; + mem['h15C4] <= 32'hFB442703; + mem['h15C5] <= 32'h01D00793; + mem['h15C6] <= 32'hF6E7D6E3; + mem['h15C7] <= 32'hFA042623; + mem['h15C8] <= 32'h0B00006F; + mem['h15C9] <= 32'hFA042423; + mem['h15CA] <= 32'h0900006F; + mem['h15CB] <= 32'hFE845483; + mem['h15CC] <= 32'hFE744783; + mem['h15CD] <= 32'h00078613; + mem['h15CE] <= 32'hFA842583; + mem['h15CF] <= 32'hFAC42503; + mem['h15D0] <= 32'hBE0FE0EF; + mem['h15D1] <= 32'h00050693; + mem['h15D2] <= 32'h00000713; + mem['h15D3] <= 32'h00449793; + mem['h15D4] <= 32'h00F707B3; + mem['h15D5] <= 32'h00D787B3; + mem['h15D6] <= 32'h0007C783; + mem['h15D7] <= 32'h04078863; + mem['h15D8] <= 32'hFE845783; + mem['h15D9] <= 32'h00178693; + mem['h15DA] <= 32'hFE544703; + mem['h15DB] <= 32'hFA842783; + mem['h15DC] <= 32'h00F70733; + mem['h15DD] <= 32'h00070793; + mem['h15DE] <= 32'h00279793; + mem['h15DF] <= 32'h00E787B3; + mem['h15E0] <= 32'h00379793; + mem['h15E1] <= 32'h00078613; + mem['h15E2] <= 32'hFE644703; + mem['h15E3] <= 32'hFAC42783; + mem['h15E4] <= 32'h00F707B3; + mem['h15E5] <= 32'h00F607B3; + mem['h15E6] <= 32'h00279713; + mem['h15E7] <= 32'h052007B7; + mem['h15E8] <= 32'h00F707B3; + mem['h15E9] <= 32'h00068713; + mem['h15EA] <= 32'h00E7A023; + mem['h15EB] <= 32'hFA842783; + mem['h15EC] <= 32'h00178793; + mem['h15ED] <= 32'hFAF42423; + mem['h15EE] <= 32'hFA842703; + mem['h15EF] <= 32'h00300793; + mem['h15F0] <= 32'hF6E7D6E3; + mem['h15F1] <= 32'hFAC42783; + mem['h15F2] <= 32'h00178793; + mem['h15F3] <= 32'hFAF42623; + mem['h15F4] <= 32'hFAC42703; + mem['h15F5] <= 32'h00300793; + mem['h15F6] <= 32'hF4E7D6E3; + mem['h15F7] <= 32'hFDB44783; + mem['h15F8] <= 32'h1A078A63; + mem['h15F9] <= 32'hFD844783; + mem['h15FA] <= 32'h0C079663; + mem['h15FB] <= 32'hFA0403A3; + mem['h15FC] <= 32'h0B40006F; + mem['h15FD] <= 32'hFA744783; + mem['h15FE] <= 32'hFF040713; + mem['h15FF] <= 32'h00F707B3; + mem['h1600] <= 32'hFAC7C783; + mem['h1601] <= 32'hFAF40323; + mem['h1602] <= 32'h0880006F; + mem['h1603] <= 32'h00100793; + mem['h1604] <= 32'hFAF402A3; + mem['h1605] <= 32'h0640006F; + mem['h1606] <= 32'hFA644783; + mem['h1607] <= 32'hFFF78693; + mem['h1608] <= 32'hFA544703; + mem['h1609] <= 32'h00070793; + mem['h160A] <= 32'h00279793; + mem['h160B] <= 32'h00E787B3; + mem['h160C] <= 32'h00379793; + mem['h160D] <= 32'h00F686B3; + mem['h160E] <= 32'hFA644603; + mem['h160F] <= 32'hFA544703; + mem['h1610] <= 32'h00070793; + mem['h1611] <= 32'h00279793; + mem['h1612] <= 32'h00E787B3; + mem['h1613] <= 32'h00379793; + mem['h1614] <= 32'h00F607B3; + mem['h1615] <= 32'h07C00713; + mem['h1616] <= 32'h00D70733; + mem['h1617] <= 32'h00074703; + mem['h1618] <= 32'h07C00693; + mem['h1619] <= 32'h00F687B3; + mem['h161A] <= 32'h00E78023; + mem['h161B] <= 32'hFA544783; + mem['h161C] <= 32'h00178793; + mem['h161D] <= 32'hFAF402A3; + mem['h161E] <= 32'hFA544703; + mem['h161F] <= 32'h01600793; + mem['h1620] <= 32'hF8E7FCE3; + mem['h1621] <= 32'hFA644783; + mem['h1622] <= 32'hFFF78793; + mem['h1623] <= 32'hFAF40323; + mem['h1624] <= 32'hFA644783; + mem['h1625] <= 32'hF6079CE3; + mem['h1626] <= 32'hFA744783; + mem['h1627] <= 32'h00178793; + mem['h1628] <= 32'hFAF403A3; + mem['h1629] <= 32'hFA744703; + mem['h162A] <= 32'hFDB44783; + mem['h162B] <= 32'hF4F764E3; + mem['h162C] <= 32'h0D00006F; + mem['h162D] <= 32'hFDB44783; + mem['h162E] <= 32'hFAF40223; + mem['h162F] <= 32'h0BC0006F; + mem['h1630] <= 32'hFA444783; + mem['h1631] <= 32'hFFF78793; + mem['h1632] <= 32'hFF040713; + mem['h1633] <= 32'h00F707B3; + mem['h1634] <= 32'hFAC7C783; + mem['h1635] <= 32'hFAF401A3; + mem['h1636] <= 32'h0880006F; + mem['h1637] <= 32'h00100793; + mem['h1638] <= 32'hFAF40123; + mem['h1639] <= 32'h0640006F; + mem['h163A] <= 32'hFA344783; + mem['h163B] <= 32'h00178693; + mem['h163C] <= 32'hFA244703; + mem['h163D] <= 32'h00070793; + mem['h163E] <= 32'h00279793; + mem['h163F] <= 32'h00E787B3; + mem['h1640] <= 32'h00379793; + mem['h1641] <= 32'h00F686B3; + mem['h1642] <= 32'hFA344603; + mem['h1643] <= 32'hFA244703; + mem['h1644] <= 32'h00070793; + mem['h1645] <= 32'h00279793; + mem['h1646] <= 32'h00E787B3; + mem['h1647] <= 32'h00379793; + mem['h1648] <= 32'h00F607B3; + mem['h1649] <= 32'h07C00713; + mem['h164A] <= 32'h00D70733; + mem['h164B] <= 32'h00074703; + mem['h164C] <= 32'h07C00693; + mem['h164D] <= 32'h00F687B3; + mem['h164E] <= 32'h00E78023; + mem['h164F] <= 32'hFA244783; + mem['h1650] <= 32'h00178793; + mem['h1651] <= 32'hFAF40123; + mem['h1652] <= 32'hFA244703; + mem['h1653] <= 32'h01600793; + mem['h1654] <= 32'hF8E7FCE3; + mem['h1655] <= 32'hFA344783; + mem['h1656] <= 32'h00178793; + mem['h1657] <= 32'hFAF401A3; + mem['h1658] <= 32'hFA344703; + mem['h1659] <= 32'h02600793; + mem['h165A] <= 32'hF6E7FAE3; + mem['h165B] <= 32'hFA444783; + mem['h165C] <= 32'hFFF78793; + mem['h165D] <= 32'hFAF40223; + mem['h165E] <= 32'hFA444783; + mem['h165F] <= 32'hF40792E3; + mem['h1660] <= 32'hF8040E23; + mem['h1661] <= 32'hF8040EA3; + mem['h1662] <= 32'hF8040F23; + mem['h1663] <= 32'hF8040FA3; + mem['h1664] <= 32'hFC040DA3; + mem['h1665] <= 32'hFE0407A3; + mem['h1666] <= 32'hFE040723; + mem['h1667] <= 32'hFE0406A3; + mem['h1668] <= 32'hFE040623; + mem['h1669] <= 32'hFE0405A3; + mem['h166A] <= 32'hBF8FF06F; + mem['h166B] <= 32'hFE010113; + mem['h166C] <= 32'h00112E23; + mem['h166D] <= 32'h00812C23; + mem['h166E] <= 32'h02010413; + mem['h166F] <= 32'h00050793; + mem['h1670] <= 32'hFEF407A3; + mem['h1671] <= 32'hFEF44703; + mem['h1672] <= 32'h00A00793; + mem['h1673] <= 32'h00F71663; + mem['h1674] <= 32'h00D00513; + mem['h1675] <= 32'hFD9FF0EF; + mem['h1676] <= 32'h020007B7; + mem['h1677] <= 32'h00878793; + mem['h1678] <= 32'hFEF44703; + mem['h1679] <= 32'h00E7A023; + mem['h167A] <= 32'h00000013; + mem['h167B] <= 32'h01C12083; + mem['h167C] <= 32'h01812403; + mem['h167D] <= 32'h02010113; + mem['h167E] <= 32'h00008067; + mem['h167F] <= 32'hFE010113; + mem['h1680] <= 32'h00112E23; + mem['h1681] <= 32'h00812C23; + mem['h1682] <= 32'h02010413; + mem['h1683] <= 32'hFEA42623; + mem['h1684] <= 32'h01C0006F; + mem['h1685] <= 32'hFEC42783; + mem['h1686] <= 32'h00178713; + mem['h1687] <= 32'hFEE42623; + mem['h1688] <= 32'h0007C783; + mem['h1689] <= 32'h00078513; + mem['h168A] <= 32'hF85FF0EF; + mem['h168B] <= 32'hFEC42783; + mem['h168C] <= 32'h0007C783; + mem['h168D] <= 32'hFE0790E3; + mem['h168E] <= 32'h00000013; + mem['h168F] <= 32'h00000013; + mem['h1690] <= 32'h01C12083; + mem['h1691] <= 32'h01812403; + mem['h1692] <= 32'h02010113; + mem['h1693] <= 32'h00008067; + mem['h1694] <= 32'hFD010113; + mem['h1695] <= 32'h02812623; + mem['h1696] <= 32'h03010413; + mem['h1697] <= 32'hFCA42E23; + mem['h1698] <= 32'hFCB42C23; + mem['h1699] <= 32'hFD842783; + mem['h169A] <= 32'hFFF78793; + mem['h169B] <= 32'h00279793; + mem['h169C] <= 32'hFEF42623; + mem['h169D] <= 32'h03C0006F; + mem['h169E] <= 32'hFEC42783; + mem['h169F] <= 32'hFDC42703; + mem['h16A0] <= 32'h00F757B3; + mem['h16A1] <= 32'h00F7F793; + mem['h16A2] <= 32'h00106737; + mem['h16A3] <= 32'hB6070713; + mem['h16A4] <= 32'h00F707B3; + mem['h16A5] <= 32'h0007C703; + mem['h16A6] <= 32'h020007B7; + mem['h16A7] <= 32'h00878793; + mem['h16A8] <= 32'h00E7A023; + mem['h16A9] <= 32'hFEC42783; + mem['h16AA] <= 32'hFFC78793; + mem['h16AB] <= 32'hFEF42623; + mem['h16AC] <= 32'hFEC42783; + mem['h16AD] <= 32'hFC07D2E3; + mem['h16AE] <= 32'h00000013; + mem['h16AF] <= 32'h00000013; + mem['h16B0] <= 32'h02C12403; + mem['h16B1] <= 32'h03010113; + mem['h16B2] <= 32'h00008067; + mem['h16B3] <= 32'h00103DA8; + mem['h16B4] <= 32'h00103E44; + mem['h16B5] <= 32'h00103EC8; + mem['h16B6] <= 32'h00103F94; + mem['h16B7] <= 32'h00104034; + mem['h16B8] <= 32'h001040D4; + mem['h16B9] <= 32'h001041A0; + mem['h16BA] <= 32'h0010425C; + mem['h16BB] <= 32'h001042DC; + mem['h16BC] <= 32'h00104388; + mem['h16BD] <= 32'h6C65645F; + mem['h16BE] <= 32'h63207961; + mem['h16BF] <= 32'h656C6C61; + mem['h16C0] <= 32'h00000064; + mem['h16C1] <= 32'h72746554; + mem['h16C2] <= 32'h72615369; + mem['h16C3] <= 32'h0A216A61; + mem['h16C4] <= 32'h00000000; + mem['h16C5] <= 32'h54545542; + mem['h16C6] <= 32'h555F4E4F; + mem['h16C7] <= 32'h00000A50; + mem['h16C8] <= 32'h54545542; + mem['h16C9] <= 32'h445F4E4F; + mem['h16CA] <= 32'h0A4E574F; + mem['h16CB] <= 32'h00000000; + mem['h16CC] <= 32'h54545542; + mem['h16CD] <= 32'h525F4E4F; + mem['h16CE] <= 32'h54484749; + mem['h16CF] <= 32'h0000000A; + mem['h16D0] <= 32'h54545542; + mem['h16D1] <= 32'h4C5F4E4F; + mem['h16D2] <= 32'h0A544645; + mem['h16D3] <= 32'h00000000; + mem['h16D4] <= 32'h54545542; + mem['h16D5] <= 32'h435F4E4F; + mem['h16D6] <= 32'h45544E45; + mem['h16D7] <= 32'h00000A52; + mem['h16D8] <= 32'h33323130; + mem['h16D9] <= 32'h37363534; + mem['h16DA] <= 32'h42413938; + mem['h16DB] <= 32'h46454443; + mem['h16DC] <= 32'h00000000; + mem['h16DD] <= 32'h01010101; + mem['h16DE] <= 32'h00000000; + mem['h16DF] <= 32'h00000000; + mem['h16E0] <= 32'h00000000; + mem['h16E1] <= 32'h00010000; + mem['h16E2] <= 32'h00010100; + mem['h16E3] <= 32'h00010000; + mem['h16E4] <= 32'h00000000; + mem['h16E5] <= 32'h00000000; + mem['h16E6] <= 32'h00010100; + mem['h16E7] <= 32'h00010100; + mem['h16E8] <= 32'h00000000; + mem['h16E9] <= 32'h00010000; + mem['h16EA] <= 32'h00010100; + mem['h16EB] <= 32'h00000100; + mem['h16EC] <= 32'h00000000; + mem['h16ED] <= 32'h00000100; + mem['h16EE] <= 32'h00010100; + mem['h16EF] <= 32'h00010000; + mem['h16F0] <= 32'h00000000; + mem['h16F1] <= 32'h00000100; + mem['h16F2] <= 32'h00000100; + mem['h16F3] <= 32'h00010100; + mem['h16F4] <= 32'h00000000; + mem['h16F5] <= 32'h00010000; + mem['h16F6] <= 32'h00010000; + mem['h16F7] <= 32'h00010100; + mem['h16F8] <= 32'h00000000; + mem['h16F9] <= 32'h000009C4; + mem['h16FA] <= 32'h075BCD15; + mem['h16FB] <= 32'h075BCD15; + + end + + always @(posedge clk) mem_data <= mem[mem_addr]; + + // ============================================================================ + + reg o_ready; + + always @(posedge clk or negedge rstn) + if (!rstn) o_ready <= 1'd0; + else o_ready <= valid && ((addr & MEM_ADDR_MASK) != 0); + + // Output connectins + assign ready = o_ready; + assign rdata = mem_data; + assign mem_addr = addr[MEM_SIZE_BITS+1:2]; + + always @(posedge clk) begin + if (wen) mem[waddr] <= wdata; + end + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/simpleuart.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/simpleuart.v new file mode 100644 index 0000000000000000000000000000000000000000..09b3179a27881ea5aa7990d8e95ce25ac9474ace --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/simpleuart.v @@ -0,0 +1,132 @@ +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * Copyright (C) 2017 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module simpleuart ( + input clk, + input resetn, + + output ser_tx, + input ser_rx, + + input [ 3:0] reg_div_we, + input [31:0] reg_div_di, + output [31:0] reg_div_do, + + input reg_dat_we, + input reg_dat_re, + input [31:0] reg_dat_di, + output [31:0] reg_dat_do, + output reg_dat_wait +); + reg [31:0] cfg_divider; + + reg [3:0] recv_state; + reg [31:0] recv_divcnt; + reg [7:0] recv_pattern; + reg [7:0] recv_buf_data; + reg recv_buf_valid; + + reg [9:0] send_pattern; + reg [3:0] send_bitcnt; + reg [31:0] send_divcnt; + reg send_dummy; + + assign reg_div_do = cfg_divider; + + assign reg_dat_wait = reg_dat_we && (send_bitcnt || send_dummy); + assign reg_dat_do = recv_buf_valid ? recv_buf_data : ~0; + + always @(posedge clk) begin + if (!resetn) begin + cfg_divider <= 1; + end else begin + if (reg_div_we[0]) cfg_divider[7:0] <= reg_div_di[7:0]; + if (reg_div_we[1]) cfg_divider[15:8] <= reg_div_di[15:8]; + if (reg_div_we[2]) cfg_divider[23:16] <= reg_div_di[23:16]; + if (reg_div_we[3]) cfg_divider[31:24] <= reg_div_di[31:24]; + end + end + + always @(posedge clk) begin + if (!resetn) begin + recv_state <= 0; + recv_divcnt <= 0; + recv_pattern <= 0; + recv_buf_data <= 0; + recv_buf_valid <= 0; + end else begin + recv_divcnt <= recv_divcnt + 1; + if (reg_dat_re) recv_buf_valid <= 0; + case (recv_state) + 0: begin + if (!ser_rx) recv_state <= 1; + recv_divcnt <= 0; + end + 1: begin + if (2 * recv_divcnt > cfg_divider) begin + recv_state <= 2; + recv_divcnt <= 0; + end + end + 10: begin + if (recv_divcnt > cfg_divider) begin + recv_buf_data <= recv_pattern; + recv_buf_valid <= 1; + recv_state <= 0; + end + end + default: begin + if (recv_divcnt > cfg_divider) begin + recv_pattern <= {ser_rx, recv_pattern[7:1]}; + recv_state <= recv_state + 1; + recv_divcnt <= 0; + end + end + endcase + end + end + + assign ser_tx = send_pattern[0]; + + always @(posedge clk) begin + if (reg_div_we) send_dummy <= 1; + send_divcnt <= send_divcnt + 1; + if (!resetn) begin + send_pattern <= ~0; + send_bitcnt <= 0; + send_divcnt <= 0; + send_dummy <= 1; + end else begin + if (send_dummy && !send_bitcnt) begin + send_pattern <= ~0; + send_bitcnt <= 15; + send_divcnt <= 0; + send_dummy <= 0; + end else if (reg_dat_we && !send_bitcnt) begin + send_pattern <= {1'b1, reg_dat_di[7:0], 1'b0}; + send_bitcnt <= 10; + send_divcnt <= 0; + end else if (send_divcnt > cfg_divider && send_bitcnt) begin + send_pattern <= {1'b1, send_pattern[9:1]}; + send_bitcnt <= send_bitcnt - 1; + send_divcnt <= 0; + end + end + end +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/top.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/top.v new file mode 100644 index 0000000000000000000000000000000000000000..eec836380ca73166fff192ec190f4937a45de3ab --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/top.v @@ -0,0 +1,315 @@ +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * Copyright (C) 2017 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`timescale 1ns / 1ps + +module top ( + input wire clk_10mhz, // 10MHz clock + + //output wire led_olimex, // LED output + + output tx, + input rx, + + input btnC, + input btnU, + input btnD, + input btnL, + input btnR, + + input [15:0] sw, + output [15:0] led, + output [7:0] cathodes, + output [3:0] anodes, + + output hsync, // to VGA connector + output vsync, // to VGA connector + output [11:0] rgb, // to DAC, to VGA connector + + output [7:0] jb +); + + // command protocol constants: + parameter [7:0] C_SOP = 8'h23; + parameter [7:0] C_EOP = 8'h0d; + + // commands: + parameter [7:0] C_REGISTER_RD = 8'h08; + parameter [7:0] C_REGISTER_WR = 8'h07; + + wire rx_busy, tx_busy, converted, data_valid; + reg [15:0] data_length, data_cnt; + reg [7:0] command; + + // Local control logic variables + // FSM state + reg [3:0] state; + + // This variable is super critical in preventing wrong FSM state changes + reg allow_next; // Local signal to prevent race conditions + + // IO related variables + reg flush_ctrl; // Flush the RX data after reading + reg tx_enable_ctrl; // Allow tranmission of output, after data is settled + + wire [7:0] uart_data; // The actual RX UART data + reg [7:0] out_data; // The data that will be sent over TX + + reg ram_wen; + reg [31:0] ram_data, ram_addr; + reg [15:0] display_data; + reg [7:0] checksum; + reg [8:0] leds; + + // UART clock related variables + reg [4:0] counter; + + // VGA signals + wire [9:0] w_x, w_y; + wire w_video_on, w_p_tick; + reg [11:0] rgb_reg; + wire [11:0] rgb_next; + + /////////////////////////////////// + // Power-on Reset + /////////////////////////////////// + reg [7:0] reset_cnt = 0; + wire resetn = &reset_cnt; + + wire clk, lock; + + pll pll_inst ( + .clock_in(clk_10mhz), // 10 MHz + .rst_in(), + .clock_out(clk),// 25 MHz, 0 deg + .locked(lock) + ); + + reg sw_dl1, sw_dl2; + always @(posedge clk) + begin + sw_dl1 <= sw[15]; + sw_dl2 <= sw_dl1; + if(sw_dl2 && !sw[15]) begin + reset_cnt <= 0; + end else begin + reset_cnt <= reset_cnt + !resetn; + end + end + + wire btnC_out; + debounce debBtnC ( + .clk (clk), + .in (btnC), + .out (btnC_out) + ); + wire btnL_out; + debounce debBtnL ( + .clk (clk), + .in (btnL), + .out (btnL_out) + ); + wire btnR_out; + debounce debBtnR ( + .clk (clk), + .in (btnR), + .out (btnR_out) + ); + wire btnD_out; + debounce debBtnD ( + .clk (clk), + .in (btnD), + .out (btnD_out) + ); + wire btnU_out; + debounce debBtnU ( + .clk (clk), + .in (btnU), + .out (btnU_out) + ); + /////////////////////////////////// + // Peripheral Bus + /////////////////////////////////// + wire iomem_valid; + wire iomem_ready; + wire [ 3:0] iomem_wstrb; + wire [31:0] iomem_addr; + wire [31:0] iomem_wdata; + wire [31:0] iomem_rdata; + + reg [31:0] gpio; + wire [4:0] debug_pins_char_gen; + reg [31:0] gpio_iomem_rdata; + reg gpio_iomem_ready; + wire vga_iomem_ready; + + + wire[4:0] buttons; + assign buttons = { btnC_out, btnD_out, btnL_out, btnR_out, btnU_out}; + + + // enable signals for each of the peripherals + wire gpio_en = (iomem_addr[31:24] == 8'h03); /* GPIO mapped to 0x03xx_xxxx */ + wire video_en = (iomem_addr[31:24] == 8'h05); /* Video device mapped to 0x05xx_xxxx */ + + assign led[5:0] = leds[5:0]; + //assign led[10:6] = buttons; + assign led[11] = w_video_on; + assign led[12] = allow_next; + assign led[13] = ram_wen; + assign led[14] = r_CLK_1HZ; + assign led[15] = sw[15]; + + assign iomem_ready = gpio_en ? gpio_iomem_ready : ( video_en ? vga_iomem_ready : 1'b0); + assign iomem_rdata = gpio_en ? gpio_iomem_rdata : 32'h00000000; + + + always @(posedge clk) + begin + if (!resetn) begin + gpio <= 0; + end else begin + gpio_iomem_ready <= 0; + if (iomem_valid && !iomem_ready && gpio_en) begin + gpio_iomem_ready <= 1; + gpio_iomem_rdata <= {8'h00, 1'b0, 1'b0, 1'b0, buttons[4:0], gpio[15:0]}; + if (iomem_wstrb[0]) gpio[7:0] <= iomem_wdata[7:0]; + if (iomem_wstrb[1]) gpio[15:8] <= iomem_wdata[15:8]; + if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16]; + if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24]; + end + end + end + + wire tx_uc, rx_uc, tx_prog, rx_prog; + + assign tx = sw[15] ? tx_prog : tx_uc; + assign rx_uc = sw[15] ? 1'bz : rx; + assign rx_prog = sw[15] ? rx : 1'bz; + + // uC Circuit + picosoc_noflash soc ( + .clk (clk), + .resetn (resetn), + + .ser_tx (tx_uc), + .ser_rx (rx_uc), + + .irq_5 (1'b0), + .irq_6 (1'b0), + .irq_7 (1'b0), + + .iomem_valid(iomem_valid), + .iomem_ready(iomem_ready), + .iomem_wstrb(iomem_wstrb), + .iomem_addr (iomem_addr), + .iomem_wdata(iomem_wdata), + .iomem_rdata(iomem_rdata), + + .progmem_wen (progmem_wen), + .progmem_waddr (ram_addr), + .progmem_wdata (ram_data) + ); + + // VGA Controller + vga_controller vga( + .clk(clk), + .reset(!resetn), + .hsync(hsync), + .vsync(vsync), + .video_on(w_video_on), + .p_tick(w_p_tick), + .x(w_x), + .y(w_y) + ); + + // VGA Wrapper + vga_wrapper at( + .clk(clk), + .reset(!resetn), + .vga_iomem_ready(vga_iomem_ready), + + .iomem_valid(iomem_valid && video_en), + .iomem_ready(iomem_ready), + .iomem_wstrb(iomem_wstrb), + .iomem_addr(iomem_addr), + .iomem_wdata(iomem_wdata), + + .video_on(w_video_on), + .x(w_x), + .y(w_y), + .rgb(rgb_next), + + .o_debug_pins(debug_pins_char_gen) + ); + + // RGB buffer + always @(posedge clk) + begin + //if(w_p_tick) + rgb_reg <= rgb_next; + end + + // output + assign rgb = rgb_reg; + + + wire I_write = (command==C_REGISTER_WR); + wire I_read = (command==C_REGISTER_RD); + + initial begin + counter = 0; + + flush_ctrl = 0; + tx_enable_ctrl = 0; + allow_next = 0; + out_data = 0; + checksum = 0; + display_data = 0; + command = 0; + data_length = 0; + data_cnt = 0; + progmem_wen = 0; + ram_wen = 0; + ram_addr = 32'hFFFFFFFF; + ram_data = 32'd0; + end + + reg progmem_wen; + + // Constants (parameters) to create the frequencies needed: + // Input clock is 100.0 MHz, system clock. + // Formula is: (100000 KHz / 1 Hz) * 50% duty cycle + // So for 1/2 Hz: (100000000 / 1) * 0.5 = 50000000, Input clock is generated 100MHz + parameter c_CNT_CLK_HZ = 50000000; + // These signals will be the counters: + reg [31:0] r_CNT_CLK_HZ = 0; + // These signals will toggle at the frequencies needed: + reg r_CLK_1HZ = 1'b0; + always @(posedge clk) + begin + if (r_CNT_CLK_HZ == c_CNT_CLK_HZ-1) begin// -1, since counter starts at 0 + r_CLK_1HZ <= !r_CLK_1HZ; + r_CNT_CLK_HZ <= 0; + end else + r_CNT_CLK_HZ <= r_CNT_CLK_HZ + 1; + end + //------------------------------------------------------------------------------ + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_rx.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_rx.v new file mode 100644 index 0000000000000000000000000000000000000000..4744dedebbc0f760afc39b230f331485659504f6 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_rx.v @@ -0,0 +1,238 @@ +`timescale 10ns/1ns + +/* + * Custom UART RX design, with all requisite customization options + * Written by Shubhayu Das, November 2021 + * Version: 1.2.0 + * Last updated: 27th November, 2021 + * + * The clock frequency and the baud rate have to be calculated and set manually. + * As it stands now, this module will automatically calculate the prescalar needed. + * This division will be done in software, which is inefficient, and wastes power + * + *************************** + * + * THEORY OF WORKING of this module: + * + * CLOCKS: + * - An input clock of 25MHz is expected. + * - Internally, a "slow_clk_en" pulse is generated, depending on baud rate. + * + * UART: + * An active low signal starts receiving. + * I am implementing oversampling. Each RX bit is sampled 15 times, + * then the "obtained_bit" function is used to calculate the detected bit + * + * An FSM is used to handle the operation of the module. + * FSM states: + * - IDLE : Waiting for start bit(0) + * - DETECT_START : Possible start bit detected. Oversample and decide + * - STARTED : Receiving started, oversample and decide individual bits + * - CONVERSION : RX complete, run parity check, retain data until flushed + * + * Oversampling: + * The incoming RX signal is oversampled, and the oversampled bits are stored in + * the "oversampled_bit" buffer. Once the buffer is full, the "obtained_bit" + * function is used to find the accurate bit. This bit is stored in "sampled_rx_data", + * at the correct location + * + * RX: + * Oversampling is continued until all bits are received. The "sampled_rx_data" + * contains the final data. This data must be read only AFTER the converted flag goes high. + * + *************************** + * Parameters in the module: + * + * FRAME_BITS - The number of bits in the data frame. Allowed values: 5-9 bits/frame + * PARITY_BIT - Set to "2" to disable parity check. Set to "0/1" for odd/even parity resp. + * STOP_BITS - The number of stop bits, Allowed values: 1-2 bits + * + *************************** + * Inputs to the module: + * + * rx - The input rx signal + * i_clk - The clock of the local system, used for sampling the bits and FSM sync + * flush - Clear the converted data from the register + * + *************************** + * Outputs of the module + * + * data - The final converted data, of appropriate bit-width + * converted - Active high signal indicating successfully received frame + * data_valid - Active high signal indicating if received data is valid(if parity is enabled) + * busy - Indicates if data reception has started and system is busy + * + *************************** + * In this version, the oversampling factor is 15. + * + * Note that due to small mismatches, between the input clock frequency and the target baud rate, + * there will a drift over time. This needs to be taken care of in the parent module. + * + *************************** + * + * Sample input clock setup for Basys 3: + * Set the clock to 100MHz in the constraints file. + * Then divide the clock to get a time period of 540ns + * + *************************** + * TODO: handling lost bits, using timeout + * Actually looking at the stop bit(s) +*/ + +//`define DEBUG + +module uart_rx #( + parameter FRAME_BITS = 8, // Number of data bits, can be 7/8 + PARITY_BIT = 2, // Parity disabled by default + STOP_BITS = 1 // Using only 1 stop bit +) ( + input rx, + input i_clk, + input flush, + output reg [FRAME_BITS-1:0] data, + output reg converted, + output reg data_valid, + output reg busy +); + +// FSM states +localparam IDLE = 0; +localparam DETECT_START = 1; +localparam STARTED = 2; +localparam CONVERSION = 3; + +// Calculating the total number of bits that need to be stored +localparam TOTAL_RX_BITS = (PARITY_BIT < 2 ) ? FRAME_BITS + STOP_BITS + 1 : FRAME_BITS + STOP_BITS; + +// Hardcoding the number of samples per bit. +// Change this according to the input clock frequency +localparam OVERSAMPLE_FACTOR = 15; + +// Three parameters used by the "obtained_bit" function +localparam integer SAMPLE_LOC_1 = (OVERSAMPLE_FACTOR / 2) - 1; +localparam integer SAMPLE_LOC_2 = (OVERSAMPLE_FACTOR / 2); +localparam integer SAMPLE_LOC_3 = (OVERSAMPLE_FACTOR / 2) + 1; + +reg [1:0] state; // FSM state + +reg [3:0] bit_location; // Indexing variable for the received data +reg [3:0] insert_location; // current index of data in oversampling buffer + +reg [OVERSAMPLE_FACTOR-1:0] oversampled_bit; // oversampling buffer +reg [TOTAL_RX_BITS-1:0] sampled_rx_data; // RX buffer + +initial begin + + `ifdef DEBUG + $display("Oversampling factor: %2d", OVERSAMPLE_FACTOR); + `endif + + state = IDLE; + + busy = 0; + bit_location = 0; + insert_location = 0; + sampled_rx_data = {(TOTAL_RX_BITS-1){1'b0}}; +end + +// Managing the states of the conversion FSM +always @(posedge i_clk) begin + case (state) + + // Unless "0" is detected on RX line, wait + IDLE : + state <= rx ? IDLE : DETECT_START; + + // Once "0" is seen on RX line, sample certain times, decide if RX started + // If RX started, go to next state + DETECT_START: begin + if(insert_location == (OVERSAMPLE_FACTOR-4)) + if(busy) + state <= STARTED; + else begin + state <= IDLE; + end + end + + // Receive all bits of the RX data, with oversampling + STARTED: + state <= (bit_location == TOTAL_RX_BITS) ? CONVERSION : STARTED; + + // Check parity, then retain data until data is flushed + CONVERSION: + state <= (flush) ? IDLE : CONVERSION; + endcase +end + +// Actual logic in each state +always @(posedge i_clk) begin + case (state) + + // Simply reset all the vectors + IDLE: begin + converted <= 0; + data_valid <= 0; + busy <= 0; + bit_location <= 0; + insert_location <= 0; // Not really needed + oversampled_bit <= 15'b0; + sampled_rx_data = {(TOTAL_RX_BITS-1){1'b0}}; + data <= {FRAME_BITS{1'b0}}; + end + + // Try to detect if a zero bit is detected, marking start of transmission + DETECT_START: begin + if (insert_location == (OVERSAMPLE_FACTOR - 5)) begin + busy <= ~obtained_bit(oversampled_bit); // Decide what bit was received + oversampled_bit <= 15'b0; // Reset the oversampling buffer + end + else + oversampled_bit[insert_location] <= rx; // Fill the oversample buffer + + if(busy) + insert_location <= 0; // Increment insertion location + else + insert_location <= insert_location + 1; + end + + // Once transmission start is confirmed, start receiving the data, with oversampling + STARTED: begin + oversampled_bit[insert_location] <= rx; + insert_location <= insert_location + 1; + + // Once oversampling buffer is full, decide what bit was received + if (insert_location == OVERSAMPLE_FACTOR - 1) begin + sampled_rx_data[bit_location] <= obtained_bit(oversampled_bit); + oversampled_bit <= 15'b0; // Reset the oversampling buffer + + bit_location <= bit_location + 1; + end + end + + // Transmission complete, check parity, put out data and other flag bits + CONVERSION: begin + if(~converted) begin + converted <= 1; + data <= sampled_rx_data[FRAME_BITS-1:0]; + + if(PARITY_BIT < 2) begin + if (^data == PARITY_BIT) + data_valid <= 1; + else + data_valid <= 0; + end + else + data_valid <= 1; + end + end + endcase +end + +// Function to decide the received bit, depending on the oversampled data bits +function obtained_bit (input [OVERSAMPLE_FACTOR-1:0] oversampled_vector); + obtained_bit = (oversampled_vector[SAMPLE_LOC_1] & oversampled_vector[SAMPLE_LOC_2]) | + (oversampled_vector[SAMPLE_LOC_2] & oversampled_vector[SAMPLE_LOC_3]) | + (oversampled_vector[SAMPLE_LOC_1] & oversampled_vector[SAMPLE_LOC_3]); +endfunction + +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_tx.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_tx.v new file mode 100644 index 0000000000000000000000000000000000000000..265204bab59a6e116f3032d925bb8c518cefbcd3 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/uart_tx.v @@ -0,0 +1,183 @@ +`timescale 10ns / 1ns + +/* + * Custom TX design, to match the RX module + * Author: Shubhayu Das + * Date: 27th November, 2021 + * Version: 1.2 + * Last update: 28th Nov, 2021: Changed order of bytes to big-endian + * + ******************** + * Inputs: + * clk: UART clk, which MUST match the clock on the RX module + * tx_enable: start transmitting data ASAP + * data: the actual data to be transmitted + ******************** + * Parameters: + * FRAME_BITS: Number of data bits per transaction + * PARITY_BITS: 0/1 indicate odd or even parity, 2 disables parity + * STOP_BITS: Number of stop bits to send + * RETENTION_DURATION: Compensate for oversampling UART clock + * + ******************** + * Outputs: + * tx: The TX data line + * tx_busy: signal to indicate TX line is busy, don't start anything else + * + ******************** + * Features of this module: + * + * This module automatically compensates for the faster UART clock being used + * for oversampling in the RX module. This is controlled by the + * RETENTION_DURATION" parameter. + * + * The input data is sampled as soon as "tx_enable" is set(on the next clock posedge) + * The input data is stored locally, the source register's value can change + * freely, without corrupting the TX activity. + * + * The data being sent is automatically flipped. So data[7:0] is sent as data[0:7] +*/ + + +module uart_tx #( + parameter FRAME_BITS = 8, // Number of data bits, can be 7/8 + PARITY_BIT = 2, // Parity disabled by default + STOP_BITS = 1, // Using only 1 stop bit + RETENTION_DURATION = 15 // Compensate for oversampling in RX +)( + input clk, + input tx_enable, + input [FRAME_BITS-1:0] data, + output reg tx, + output reg tx_busy +); + +function integer clog2; + input integer value; + integer temp; + begin + temp = value - 1; + for (clog2 = 0; temp > 0; clog2 = clog2 + 1) begin + temp = temp >> 1; + end + end +endfunction + +// Knowing how bits need to be sent +localparam N_TX_BITS = (PARITY_BIT < 2) ? + (1+FRAME_BITS+1+STOP_BITS) : (1+FRAME_BITS+STOP_BITS); +localparam INDEX_SIZE = clog2(N_TX_BITS); + +// FSM states +localparam IDLE = 0; // Wait for tx_enable to be set +localparam CAPTURE = 1; // Copy data into local_data, with parity, stop bits +localparam TRANSMITTING = 2;// Data being put on TX line + +reg [2:0] state; +reg data_framed; // Indicates data has been copied to local_data + +reg [INDEX_SIZE:0] bit_index; + +reg [0:N_TX_BITS-1] local_data; // local data register + +// Keeps TX high for requisite number of cycles +reg [clog2(RETENTION_DURATION):0] retention_counter; + + +initial begin + tx = 1; + tx_busy = 0; + + state = IDLE; + bit_index = 0; + data_framed = 0; + local_data = 0; + + // This is NOT a mistake + // This compensates for the immediate addition that happens + // in "TRANSMITTING" state + retention_counter = RETENTION_DURATION; +end + +// Handle the state changes +always @(posedge clk) begin + case(state) + IDLE: + state <= (tx_enable) ? CAPTURE : IDLE; + + CAPTURE: + state <= (data_framed) ? TRANSMITTING : CAPTURE; + + TRANSMITTING: + state <= (bit_index == N_TX_BITS) ? IDLE : TRANSMITTING; + endcase +end + +always @(posedge clk) begin + case(state) + IDLE: begin + tx <= 1; + tx_busy <= 0; + bit_index <= 0; + local_data <= 0; + data_framed <= 0; + retention_counter <= RETENTION_DURATION; + end + + CAPTURE: begin + tx_busy <= 1; + + // The data needs to be reversed + if(PARITY_BIT < 2) begin + local_data <= { + 1'b0, // Start bit + data[0], // Reversed data + data[1], + data[2], + data[3], + data[4], + data[5], + data[6], + data[7], + ^data, // Parity + {(STOP_BITS){1'b1}} // Stop bit(s) + }; + data_framed <= 1; + end + else begin + // Same as above, but without parity + local_data <= { + 1'b0, + data[0], + data[1], + data[2], + data[3], + data[4], + data[5], + data[6], + data[7], + {(STOP_BITS){1'b1}} + }; + data_framed <= 1; + end + end + + TRANSMITTING: begin + if(retention_counter == 0) begin + tx <= local_data[bit_index]; + bit_index <= bit_index + 1; + + if(bit_index == N_TX_BITS) + tx_busy <= 0; + + end + + if(retention_counter < RETENTION_DURATION) + retention_counter <= retention_counter + 1; + else + retention_counter <= 0; + end + endcase +end + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_controller.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_controller.v new file mode 100644 index 0000000000000000000000000000000000000000..de3ad21c3e462147052b332bd13c4ce4aa261bd1 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_controller.v @@ -0,0 +1,141 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Reference Book: +// Chu, Pong P. +// Wiley, 2008 +// "FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version" +// +// Adapted for the Basys 3 by David J. Marion +// Comments by David J. Marion +// +// FOR USE WITH AN FPGA THAT HAS A 100MHz CLOCK SIGNAL ONLY. +// VGA Mode +// 640x480 pixels VGA screen with 25MHz pixel rate based on 60 Hz refresh rate +// 800 pixels/line * 525 lines/screen * 60 screens/second = ~25.2M pixels/second +// +// A 25MHz signal will suffice. The Basys 3 has a 100MHz signal available, so a +// 25MHz tick is created for syncing the pixel counts, pixel tick, horiz sync, +// vert sync, and video on signals. +////////////////////////////////////////////////////////////////////////////////// + +module vga_controller( + input wire clk, // from Basys 3 + input reset, // system reset + output video_on, // ON while pixel counts for x and y and within display area + output hsync, // horizontal sync + output vsync, // vertical sync + output p_tick, // the 25MHz pixel/second rate signal, pixel tick + output [9:0] x, // pixel count/position of pixel x, max 0-799 + output [9:0] y // pixel count/position of pixel y, max 0-524 + ); + + // Based on VGA standards found at vesa.org for 640x480 resolution + // Total horizontal width of screen = 800 pixels, partitioned into sections + parameter HD = 640; // horizontal display area width in pixels + parameter HF = 48; // horizontal front porch width in pixels + parameter HB = 16; // horizontal back porch width in pixels + parameter HR = 96; // horizontal retrace width in pixels + parameter HMAX = HD+HF+HB+HR-1; // max value of horizontal counter = 799 + // Total vertical length of screen = 525 pixels, partitioned into sections + parameter VD = 480; // vertical display area length in pixels + parameter VF = 10; // vertical front porch length in pixels + parameter VB = 33; // vertical back porch length in pixels + parameter VR = 2; // vertical retrace length in pixels + parameter VMAX = VD+VF+VB+VR-1; // max value of vertical counter = 524 + + // Counter Registers, two each for buffering to avoid glitches + reg [9:0] h_count_reg, h_count_next; + reg [9:0] v_count_reg, v_count_next; + + // Output Buffers + reg v_sync_reg, h_sync_reg; + wire v_sync_next, h_sync_next; + + always @(posedge clk or posedge reset) + if (reset) begin + v_count_reg <= 0; + h_count_reg <= 0; + v_sync_reg <= 1'b0; + h_sync_reg <= 1'b0; + end else begin + // Logika za horizontalni brojač + if (h_count_reg == HMAX) begin + h_count_reg <= 0; + // Logika za vertikalni brojač + if (v_count_reg == VMAX) + v_count_reg <= 0; + else + v_count_reg <= v_count_reg + 1; + end else begin + h_count_reg <= h_count_reg + 1; + end + + // Ažuriranje sinhronizacije + v_sync_reg <= v_sync_next; + h_sync_reg <= h_sync_next; + end + + // reg r_25MHz; + // wire w_25MHz; + + // always @(posedge clk or posedge reset) + // if(reset) + // r_25MHz <= 0; + // else + // r_25MHz <= r_25MHz + 1; + + // assign w_25MHz = (r_25MHz == 0) ? 1 : 0; // assert tick 1/2 of the time + + // // Register Control + // always @(posedge clk or posedge reset) + // if(reset) begin + // v_count_reg <= 0; + // h_count_reg <= 0; + // v_sync_reg <= 1'b0; + // h_sync_reg <= 1'b0; + // end + // else begin + // v_count_reg <= v_count_next; + // h_count_reg <= h_count_next; + // v_sync_reg <= v_sync_next; + // h_sync_reg <= h_sync_next; + // end + + // //Logic for horizontal counter + // always @(posedge w_25MHz or posedge reset) // pixel tick + // if(reset) + // h_count_next = 0; + // else + // if(h_count_reg == HMAX) // end of horizontal scan + // h_count_next = 0; + // else + // h_count_next = h_count_reg + 1; + + // // Logic for vertical counter + // always @(posedge w_25MHz or posedge reset) + // if(reset) + // v_count_next = 0; + // else + // if(h_count_reg == HMAX) // end of horizontal scan + // if((v_count_reg == VMAX)) // end of vertical scan + // v_count_next = 0; + // else + // v_count_next = v_count_reg + 1; + + // h_sync_next asserted within the horizontal retrace area + assign h_sync_next = (h_count_reg >= (HD+HB) && h_count_reg <= (HD+HB+HR-1)); + + // v_sync_next asserted within the vertical retrace area + assign v_sync_next = (v_count_reg >= (VD+VB) && v_count_reg <= (VD+VB+VR-1)); + + // Video ON/OFF - only ON while pixel counts are within the display area + assign video_on = (h_count_reg < HD) && (v_count_reg < VD); // 0-639 and 0-479 respectively + + // Outputs + assign hsync = h_sync_reg; + assign vsync = v_sync_reg; + assign x = h_count_reg; + assign y = v_count_reg; + assign p_tick = clk; + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_map_ram.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_map_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..558f03fde33a24bc348b4da83ba0e1fa4d258b08 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_map_ram.v @@ -0,0 +1,30 @@ + +module vga_map_ram ( + input clk, + input wen, + input [11:0] waddr, + input [3:0] wdata, + input ren, + input [11:0] raddr, + output reg [3:0] rdata +); + //parameter MEM_INIT_FILE = "vid_ram.mem"; + (* ram_style = "block" *) reg [3:0] map_ram [0:1199]; // memory for 40 x 30 position mega character with value between 0-15 for character id + + //initial + //if (MEM_INIT_FILE != "") + // $readmemh(MEM_INIT_FILE, map_ram); + + always @(posedge clk) + begin + if (ren) + rdata <= map_ram[raddr]; + end + + always @(posedge clk) + begin + if (wen) + map_ram[waddr] <= wdata; + end + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_ram.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..61def7876bf6354f82c68a60bc73aa49aeb57e72 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_ram.v @@ -0,0 +1,30 @@ + +module vga_ram ( + input clk, + input wen, + input [11:0] waddr, + input [11:0] wdata, + input ren, + input [11:0] raddr, + output reg [11:0] rdata +); + //parameter MEM_INIT_FILE = "vid_ram.mem"; + (* ram_style = "block" *) reg [11:0] ram [0:4095]; // memory for 16 character with dimension 16x16 pixels @ 12bpp // bio distribuirani + + //initial + //if (MEM_INIT_FILE != "") + // $readmemh(MEM_INIT_FILE, ram); + + always @(posedge clk) + begin + if (ren) + rdata <= ram[raddr]; + end + + always @(posedge clk) + begin + if (wen) + ram[waddr] <= wdata; + end + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_wrapper.v b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_wrapper.v new file mode 100644 index 0000000000000000000000000000000000000000..92bbdaeb5e7e0afcc8835a22bc21118ea7686c04 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/1.hw/vga_wrapper.v @@ -0,0 +1,89 @@ +`timescale 1ns / 1ps + +module vga_wrapper ( + input clk, + input reset, // system reset + + output reg vga_iomem_ready, + input iomem_valid, + input iomem_ready, + input [3:0] iomem_wstrb, + input [31:0] iomem_addr, + input [31:0] iomem_wdata, + + input video_on, + input [9:0] x, y, + output reg [11:0] rgb, + + output[4:0] o_debug_pins +); + + // signal declarations + wire charset_on, charset_on1, charset_on2; + reg char_mem_write, map_mem_write; + wire [11:0] write_address; + wire [11:0] read_address, map_read_address; + wire [11:0] rgb_rdata; + wire [3:0] map_rdata; + + always @(posedge clk) + begin + if (reset) begin + char_mem_write <= 0; + map_mem_write <= 0; + end else begin + vga_iomem_ready <= 0; + char_mem_write <= 0; + map_mem_write <= 0; + if (iomem_valid && !iomem_ready) begin + vga_iomem_ready <= 1; + if(iomem_addr[23:20]==4'h1) begin + if(iomem_wstrb[0]) begin + char_mem_write <= 1; + end + end else if(iomem_addr[23:20]==4'h2) begin + if(iomem_wstrb[0]) begin + map_mem_write <= 1; + end + end + end + end + end + + assign write_address = (iomem_addr[15:0]/4); + assign read_address = {map_rdata, y[3:0], x[3:0]}; + assign map_read_address = ( y >> 4 ) * 6'd40 + ( x >> 4 ); + + vga_map_ram map( + .clk(clk), + .wen(map_mem_write), + .waddr(write_address), + .wdata(iomem_wdata[3:0]), + .ren(video_on), + .raddr(map_read_address), + .rdata(map_rdata) + ); + + vga_ram ram( + .clk(clk), + .wen(char_mem_write), + .waddr(write_address), + .wdata(iomem_wdata[11:0]), + .ren(video_on), + .raddr(read_address), + .rdata(rgb_rdata) + ); + + + // rgb multiplexing circuit + always @(*) + begin + if(~video_on) + rgb = 12'h000; // blank + else + rgb = rgb_rdata; + end + + assign o_debug_pins = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0}; + +endmodule diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/2.sim/README.md b/chili-chips-ba_openCologne/5.TetriSaraj/2.sim/README.md new file mode 100644 index 0000000000000000000000000000000000000000..ea51d7b90c4eb07fc327b1fec5dd7972f3b4dee8 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/2.sim/README.md @@ -0,0 +1,44 @@ +# HW/SW co-sim with VProc VIP +by Simon Southwell +

+ +

+ + +## First things first +- [Vproc Intro](https://drive.google.com/file/d/1V81Q9Ue9HjQIpum2KXUp8eKwzed-kwfm) +- [VProc Manual](https://github.com/wyvernSemi/vproc/blob/master/doc/VProc.pdf) + + +## Native Mode + + + +## ISS Mode + + + +## Testbench structure + + +## How to build and run it + +## Misc Tidbits: VProc Node +Node is simply memory mapped in _display.v_ for cross referencing. When using the C API or when creating a new C++ API object, the node number must be used to connect to a given VProc instantiation which might, accidently, be the wrong one. This simply gives a means, if desired, to check that the API object is connected to the expected node for safety and avoiding unexpected behaviour. It does not have to be there for VProc to work. + +## Misc Tidbits: VProc Delta-Cycle Processing +The "delta-cycle" process can't be a clock in order to access more than 32 bits to read and/or update in a single cycle. Conceivably if one needed to access, say, ten 32-bit ports, then VProc could be run 10 times faster to update by the end of the external clock, but this is an arbitrary number and might not work for all possible cases. + +It would likely run slower than using the delta-cycle updates. It's only needed, in any case, if using VProc to memory map ports---and the jury is out for _display.v_ and I need to measure its impact on performance. + +The whole delta cycle logic can be disabled by setting VProc's **DISABLE_DELTA** generic to non-zero, and the **Update** and **UpdateResponse** signals are then unconnected. In a test bench that only has VProcs used as a 32-bit memory mapped virtual CPUs, then this feature can be ignored and configured out. + +Delta cycle accesses are used for pcievhost, but it might conceivably be configured out for a single lane 8b10b bit in and out port (20 bits) and a electrical idle in and out, but two lanes or more is not possible as this will require multiple accesses per cycle. + +## References +- [LI-2024-01](https://www.linkedin.com/pulse/vproc-virtual-processor-vip-simon-southwell-pjmpe) +- [LI-2024-10](https://www.linkedin.com/posts/simon-southwell-7684482_riscv-iss-embeddedsoftware-activity-7256311551178027008-1nlZ?utm_source=share&utm_medium=member_desktop) +- [VGASIM](https://github.com/wyvernSemi/vgasim) + + +#### End of Document diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/2.sw/main.c b/chili-chips-ba_openCologne/5.TetriSaraj/2.sw/main.c new file mode 100644 index 0000000000000000000000000000000000000000..349d7f3e1dc279e07d801cace001243ed8362e41 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/2.sw/main.c @@ -0,0 +1,1212 @@ +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * Coyright (C) 2017 Clifford Wolf + * + * Permission to use, coy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * coyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// INCLUDES AND DEFINES-------------------------------------------------- + +#include +#include +#include "uart.h" + +#define RAM_TOTAL 0x2000 // 8 KB + +#define reg_uart_clkdiv (*(volatile uint32_t*)0x02000004) +#define reg_uart_data (*(volatile uint32_t*)0x02000008) + +#define reg_gpio (*(volatile uint32_t*) 0x03000000) +#define reg_video_char ((volatile uint32_t*)0x05100000) +#define reg_video_map ((volatile uint32_t*)0x05200000) + +#define BUTTON_UP 0x01 // 0000 0001 +#define BUTTON_RIGHT 0x02 // 0000 0010 +#define BUTTON_LEFT 0x04 // 0000 0100 +#define BUTTON_DOWN 0x08 // 0000 1000 +#define BUTTON_CENTER 0x10 // 0001 0000 + +#define DELAY 2500 + +#define fieldWidth 40 +#define fieldHeight 30 + +// GLOBAL VARIABLES-------------------------------------------------------- + +uint8_t buttons; +static uint32_t delay = DELAY; +static uint8_t field[1200]; + +static uint8_t tetrominoes[7][16]={{1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0}, + {0,0,1,0,0,1,1,0,0,0,1,0,0,0,0,0}, + {0,0,0,0,0,1,1,0,0,1,1,0,0,0,0,0}, + {0,0,1,0,0,1,1,0,0,1,0,0,0,0,0,0}, + {0,1,0,0,0,1,1,0,0,0,1,0,0,0,0,0}, + {0,1,0,0,0,1,0,0,0,1,1,0,0,0,0,0}, + {0,0,1,0,0,0,1,0,0,1,1,0,0,0,0,0}}; + +// PRIVATE FUNCTIONS DECLARATIONS-------------------------------------------- + +static void CharactersInit(void); +static void DisplayProjectName(void); +static void DisplayCompanyName(void); +static void DisplayGameName(void); +static void DisplayHeart(int x_start, int y_start, int color); +static void setScreenColor(int color); +static void DisplayGameOverScreen(int numLives ); +static void DisplayTheEndScreen(void); +static void GetButtonStates(void); +static int Rotate(int x, int y, int r); +static bool DoesPieceFit(int ntetrominoes, int nRotation, int nPosX, int nPosY); +static void DisplayDigit(uint8_t number, uint8_t startX, uint8_t startY); +static void WriteScore(int score); + +// PRIVATE FUNCTIONS IMPLEMENTATION------------------------------------------- + +/* + * brief reads the gpio register and changes the state of buttons variable + * return void + */ +void GetButtonStates() { + buttons = (uint8_t)(reg_gpio >> 16)&0xFF; +} + +/* + * brief displays GATEMATE Demo on the screen + * return void + */ +void DisplayProjectName() +{ + uint8_t nameY = 3; + for (uint8_t y = 0; y < 30; y++) + { + for (uint8_t x = 0; x < 40; x++) // Board Boundary + { + reg_video_map[y * 40 + x] = 12; // Background color + //G + if ((y == nameY && (x >= 3 && x <= 5)) || (y == nameY + 4 && (x >= 3 && x <= 5)) || (x == 3 && (y >= nameY && y <= nameY + 4)) || (x == 5 && (y >= nameY + 2 && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 0; + //a + if((x == 7 || x == 9) && (y >= nameY + 1 && y <= nameY + 4) || (x == 8 && y == nameY + 2) || (x == 8 && y == nameY)) + reg_video_map[y * 40 + x] = 0; + //t + if ((y == nameY && (x >= 11 && x <= 13)) || (x == 12 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 0; + //e + if (((y == nameY || y == nameY + 4) && (x >= 15 && x <= 17)) || (y == nameY + 2 && x == 16) || (x == 15 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 0; + //M + if ((y == nameY && (x == 20 || x == 21 || x == 23 || x == 24)) || (x == 20 && (y >= nameY && y <= nameY + 4)) || (x == 24 && (y >= nameY && y <= nameY + 4)) || (x == 22 && y == nameY + 1)) + reg_video_map[y * 40 + x] = 11; + //a + if((x == 26 || x == 28) && (y >= nameY + 1 && y <= nameY + 4) || (x == 27 && y == nameY + 2) || (x == 27 && y == nameY)) + reg_video_map[y * 40 + x] = 11; + //t + if ((y == nameY && (x >= 30 && x <= 32)) || (x == 31 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 11; + //e + if (((y == nameY || y == nameY + 4) && (x >= 34 && x <= 36)) || (y == nameY + 2 && x == 35) || (x == 34 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 11; + } + } +} + + +/* + * brief displays CHILI CHIPS on the screen + * return void + */ +void DisplayCompanyName() +{ + uint8_t lineY = 11; + uint8_t lineXStart = 3, lineXEnd = 36; + uint8_t nameY = 14; + for (uint8_t y = 0; y < 30; y++) + { + for (uint8_t x = 0; x < 40; x++) // Board Boundary + { + // blue line + if (y == lineY && (x >= lineXStart && x <= lineXEnd)) + reg_video_map[y * 40 + x] = 10; + + //C + if (x == 4 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if (y == nameY && (x == 5 || x == 6)) + reg_video_map[y * 40 + x] = 7; + if (y == nameY + 4 && (x == 5 || x == 6)) + reg_video_map[y * 40 + x] = 7; + //h + if (x == 8 && (y >= nameY && y <= nameY + 4) ) + reg_video_map[y*40+x]=7; + if (y == nameY + 2 && (x == 9 || x == 10)) + reg_video_map[y * 40 + x] = 7; + if (x == 10 && (y >= nameY + 2 && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + // i + if (x == 12 && (y >= nameY + 2 && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if (x == 12 && y == nameY) + reg_video_map[y * 40 + x] = 7; + // l + if (x == 14 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x]=7; + // i + if (x == 16 && (y >= nameY + 2 && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if (x == 16 && y == nameY) + reg_video_map[y * 40 + x] = 7; + // C + if (x == 19 && (y >= nameY && y <= nameY + 4) ) + reg_video_map[y * 40 + x] = 2; + if (y == nameY && (x == 20 || x == 21)) + reg_video_map[y * 40 + x] = 2; + if (y == nameY + 4 && (x == 20 || x == 21)) + reg_video_map[y * 40 + x] = 2; + //H + if (x == 23 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 2; + if (y == nameY + 2 && (x == 24 || x == 25)) + reg_video_map[y * 40 + x] = 2; + if (x == 25 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 2; + // I + if (x == 27 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 2; + // P + if (x == 29 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 2; + if (y == nameY && (x == 30 || x == 31)) + reg_video_map[y * 40 + x] = 2; + if (y == nameY + 2 && (x == 30 || x == 31)) + reg_video_map[y * 40 + x] = 2; + if (x == 31 && (y >= nameY && y <= nameY + 2)) + reg_video_map[y * 40 + x] = 2; + // S + if (y == nameY && (x >= 33 && x <= 35 )) + reg_video_map[y * 40 + x] = 2; + if (y == nameY + 2 && (x >= 33 && x <= 35)) + reg_video_map[y * 40 + x] = 2; + if (y == nameY + 4 && (x >= 33 && x <= 35)) + reg_video_map[y * 40 + x] = 2; + if (x == 33 && y == nameY + 1) + reg_video_map[y * 40 + x] = 2; + if (x == 35 && y == nameY + 3) + reg_video_map[y * 40 + x] = 2; + } + } +} + +/* + * brief displays TETRISARAJ on the screen + * return void + */ +void DisplayGameName() +{ + uint8_t nameY = 22; + for (uint8_t y = 0; y < 30; y++) + { + for (uint8_t x = 0; x < 40; x++) // Board Boundary + { + //T + if(y == nameY && (x>=2 && x<=4) || (x == 3 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 2; + //E + if (((y == nameY || y == nameY + 4) && (x >= 6 && x <= 8)) || (y == nameY + 2 && x == 7) || (x == 6 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 2; + //T + if(y == nameY && (x >= 10 && x <= 12)) + reg_video_map[y * 40 + x] = 2; + if(x == 11 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 2; + //R + if(x == 14 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 2; + if(x == 15 && y== nameY) + reg_video_map[y * 40 + x] = 2; + if(x == 16 && y == nameY + 1) + reg_video_map[y * 40 + x] = 2; + if(x == 15 && y == nameY + 2) + reg_video_map[y * 40 + x] = 2; + if(x == 16 && (y == nameY + 3 || y == nameY + 4)) + reg_video_map[y * 40 + x] = 2; + //I + if(x == 18 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 2; + //S + if(y == nameY && (x == 20 || x == 21)) + reg_video_map[y * 40 + x] = 7; + if(x == 20 && (y == nameY + 1 || y == nameY + 2 || y == nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if(x == 21 && (y >= nameY + 2 && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + //A + if((x == 23 || x == 25) && (y >= nameY + 1 && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if(x == 24 && y == nameY + 2) + reg_video_map[y * 40 + x] = 7; + if(x == 24 && y == nameY) + reg_video_map[y * 40 + x] = 7; + //R + if(x == 27 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if(x == 28 && y == nameY) + reg_video_map[y * 40 + x] = 7; + if(x == 29 && y == nameY + 1) + reg_video_map[y * 40 + x] = 7; + if(x == 28 && y == nameY + 2) + reg_video_map[y * 40 + x] = 7; + if(x == 29 && (y == nameY + 3 || y == nameY + 4)) + reg_video_map[y * 40 + x] = 7; + //A + if((x == 31 || x == 33) && (y >= nameY + 1 && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if(x == 32 && y == nameY + 2) + reg_video_map[y * 40 + x] = 7; + if(x == 32 && y == nameY) + reg_video_map[y * 40 + x] = 7; + //J + if(x == 37 && (y >= nameY && y <= nameY + 4)) + reg_video_map[y * 40 + x] = 7; + if((x == 35 || x == 36) && y == nameY + 4) + reg_video_map[y * 40 + x] = 7; + if(x == 35 && y == nameY + 3) + reg_video_map[y * 40 + x] = 7; + } + } +} +/* + * brief displays heart on screen + * return void + */ +void DisplayHeart(int x_start, int y_start, int color){ + for (int y = 0; y < 30; y++) + { + for (int x = 0; x < 40; x++) // Board Boundary + { + if((x==2+x_start || x==3+x_start || x==7+x_start || x==8+x_start) && y==y_start) + reg_video_map[y * 40 + x] = 0; + if((x==1+x_start || x==4+x_start || x==6+x_start || x==9+x_start) && y==y_start+1) + reg_video_map[y * 40 + x] = 0; + if((x==x_start || x==5+x_start || x==10+x_start) && y==y_start+2) + reg_video_map[y * 40 + x] = 0; + if((x==x_start || x==10+x_start) && y==y_start+3) + reg_video_map[y * 40 + x] = 0; + if((x==1+x_start || x==9+x_start) && y==y_start+4) + reg_video_map[y * 40 + x] = 0; + if((x==2+x_start || x==8+x_start) && y==y_start+5) + reg_video_map[y * 40 + x] = 0; + if((x==3+x_start || x==7+x_start) && y==y_start+6) + reg_video_map[y * 40 + x] = 0; + if((x==4+x_start || x==6+x_start) && y==y_start+7) + reg_video_map[y * 40 + x] = 0; + if((x==5+x_start) && y==y_start+8) + reg_video_map[y * 40 + x] = 0; + + if((x==2+x_start || x==3+x_start || x==7+x_start || x==8+x_start) && y==y_start+1) + reg_video_map[y * 40 + x] = color; + if(((x>=1+x_start && x<=4+x_start) || (x>=6+x_start && x<=9+x_start)) && y==y_start+2) + reg_video_map[y * 40 + x] = color; + if((x>=1+x_start && x<=9+x_start) && y==y_start+3) + reg_video_map[y * 40 + x] = color; + if((x>=2+x_start && x<=8+x_start) && y==y_start+4) + reg_video_map[y * 40 + x] = color; + if((x>=3+x_start && x<=7+x_start) && y==y_start+5) + reg_video_map[y * 40 + x] = color; + if((x>=4+x_start && x<=6+x_start) && y==y_start+6) + reg_video_map[y * 40 + x] = color; + if(x==5+x_start && y==y_start+7) + reg_video_map[y * 40 + x] = color; + + } + } + +} +/* + * brief set screen color + * return void + */ + void setScreenColor(int color){ + for (uint8_t y = 0; y < 30; y++) + { + for (uint8_t x = 0; x < 40; x++) // Board Boundary + { + reg_video_map[y * 40 + x] = color; + } + } + } +/* + * brief displays game over screen + * return void + */ +void DisplayGameOverScreen(int numLives ) +{ + uint8_t nameY = 1; + for (uint8_t y = 0; y < 30; y++) + { + for (uint8_t x = 0; x < 40; x++) // Board Boundary + { + reg_video_map[y * 40 + x] = 9; + + //G + if((x == 5 && (y >= nameY+2 && y <= nameY+5)) || (x == 6 && (y == nameY+1 || y == nameY+6)) || ((x >= 7 && x<= 11) && (y == nameY || y==nameY+7)) || (x==11 && (y>=nameY+4 && y<=nameY+7)) || (x >= 8 && x<= 11) && (y == nameY+4) ) + reg_video_map[y * 40 + x] = 3; + + //A + if((x==16 && y==nameY) || ((x==15 || x==17) && y==nameY+1) || ((x==14 || x==18) && (y>=nameY+2 && y<=nameY+3)) || ((x>=13 && x<=19) && y==nameY+4) || ((x==13 || x==19) && (y>=nameY+5 && y<=nameY+7))) + reg_video_map[y * 40 + x] = 1; + + //M + if(((x==21 || x==28) && (y>=nameY && y<=nameY+7)) || ((x==22 || x==27) && y==nameY) || ((x==23 || x==26) && (y>=nameY+1 && y<=nameY+2)) || ((x==24 || x==25) && y==nameY+3)) + reg_video_map[y * 40 + x] = 2; + + //E + if(((x>=30 && x<=34) && (y==nameY || y==nameY+7)) || (x==30 && (y>=nameY+1 && y<=nameY+6)) || ((x>=31 && x<=33) && y==nameY+4)) + reg_video_map[y * 40 + x] = 4; + + + //O + if(((x==7 || x==12) && (y>=nameY+11 && y<=nameY+16)) || ((y==nameY+10 || y==nameY+17) && (x>=8 && x<=11))) + reg_video_map[y * 40 + x] = 3; + + //V + if(((x==14 || x==20) && (y>=nameY+10 && y<=nameY+12)) || ((x==15 || x==19) && (y>=nameY+13 && y<=nameY+14)) || ((x==16 || x==18) && (y==nameY+15)) || ((x==17) && (y>=nameY+16 && y<=nameY+17))) + reg_video_map[y * 40 + x] = 1; + + //E + if(((x>=22 && x<=26) && (y==nameY+10 || y==nameY+17)) || (x==22 && (y>=nameY+11 && y<=nameY+16)) || ((x>=23 && x<=25) && y==nameY+14)) + reg_video_map[y * 40 + x] = 2; + + //R + if((x==28 && (y>=nameY+10 && y<=nameY+17)) || ((x>=29 && x<=31) && (y==nameY+14 || y==nameY+10)) || ((x==32) && (y>=nameY+11 && y<=nameY+13)) || (x==30 && y==nameY+15) || (x==31 && y==nameY+16) || (x==32 && y==nameY+17)) + reg_video_map[y * 40 + x] = 4; + } + } + // Lives + if(numLives==3){ + DisplayHeart(5,21,3); + DisplayHeart(15,21,3); + DisplayHeart(25,21,3); + } + + if(numLives==2){ + DisplayHeart(5,21,3); + DisplayHeart(15,21,3); + DisplayHeart(25,21,9); + } + + if(numLives==1){ + DisplayHeart(5,21,3); + DisplayHeart(15,21,9); + DisplayHeart(25,21,9); + } +} +/* + * brief displays THE END screen + * return void + */ +void DisplayTheEndScreen(void) +{ + uint8_t nameY = 8; + for (uint8_t y = 0; y < 23; y++) + { + for (uint8_t x = 0; x < 40; x++) // Board Boundary + { + reg_video_map[y * 40 + x] = 0; + + // T + if ((y == nameY && (x >= 5 && x <= 7)) || (x == 6 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 3; + + // H + if ((y == nameY + 2 && (x >= 9 && x <= 11)) || ((x == 9 || x == 11) && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 3; + + // E + if (((y == nameY || y == nameY + 4) && (x >= 13 && x <= 15)) || (x == 13 && (y >= nameY && y <= nameY + 4)) || (y == nameY + 2 && (x >= 13 && x <= 14))) + reg_video_map[y * 40 + x] = 3; + + // E + if (((y == nameY || y == nameY + 4) && (x >= 20 && x <= 22)) || (x == 20 && (y >= nameY && y <= nameY + 4)) || (y == nameY + 2 && (x >= 20 && x <= 21))) + reg_video_map[y * 40 + x] = 3; + + // N + if ((y == nameY + 2 && x == 25) || (y == nameY + 3 && x == 26) || ((x == 24 || x == 27) && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 3; + + // D + if ((x == 31 && (y >= nameY + 1 && y <= nameY + 3)) || ((y == nameY || y == nameY + 4) && (x >= 29 && x <= 30)) || (x == 29 && (y >= nameY && y <= nameY + 4))) + reg_video_map[y * 40 + x] = 3; + + // ! + if ((x == 33 && (y >= nameY && y <= nameY + 2)) || (x == 33 && y == nameY + 4)) + reg_video_map[y * 40 + x] = 3; + } + } +} + +/* + * brief defines all characters that can be used + * return void + */ +void CharactersInit() { + uint32_t pixel = 0x00000FFF; + for(uint8_t z = 0; z < 16; z++) + { + for(uint8_t y = 0; y < 16; y++) + { + for(uint8_t x = 0; x < 16; x++) + { + if(z == 0) // color black + { + if(y == 0 || y == 1) pixel = 0x00000222; + else if (x == 14 || x == 15) pixel = 0x00000111; + else pixel = 0x00000000; + } + else if(z == 1) // color green + { + if(y == 0 || y == 1) pixel = 0x00000080; + else if (x == 14 || x == 15) pixel = 0x00000080; + else pixel = 0x000008B4; + } + else if(z == 2) // color blue + { + if(y == 0 || y == 1) pixel = 0x0000000B; + else if (x == 14 || x == 15) pixel = 0x0000000B; + else pixel = 0x0000009F; + } + else if(z == 3) // color red + { + if(y == 0 || y == 1) pixel = 0x00000A00; + else if (x == 14 || x == 15) pixel = 0x00000B00; + else pixel = 0x00000F00; + } + else if(z == 4) // color yellow + { + if(y == 0 || y == 1) pixel = 0x00000FD8; + else if (x == 14 || x == 15) pixel = 0x00000FD4; + else pixel = 0x00000FD2; + } + else if(z == 5) // color purple + { + if(y == 0 || y == 1) pixel = 0x00000075D; + else if (x == 14 || x == 15) pixel = 0x00000074D; + else pixel = 0x00000070D; + } + else if(z == 6) // color pink + { + if(y == 0 || y == 1) pixel = 0x00000FAF; + else if (x == 14 || x == 15) pixel = 0x00000F6F; + else pixel = 0x00000F0F; + } + else if(z == 7) // color orange + { + if(y == 0 || y == 1) pixel = 0x00000FB0; + else if (x == 14 || x == 15) pixel = 0x00000F90; + else pixel = 0x00000F63; + } + else if(z == 8) // not used + { + pixel = 0x000000A0; + } + else if(z == 9) // color gray + { + if (x == 14 || x == 15) pixel = 0x00000CCC; + else if(y == 0 || y == 1) pixel = 0x00000111; + else pixel = 0x00000AAA; + } + else if(z == 10) // color light blue + { + if(y == 0 || y == 1) pixel = 0x0000000B; + else if (x == 14 || x == 15) pixel = 0x0000000B; + else pixel = 0x00000007; + } + else if(z == 11) // GateMate blue + { + if(y == 0 || y == 1) pixel = 0x0000000B; + else if (x == 14 || x == 15) pixel = 0x0000000B; + else pixel = 0x0000006C; + } + else if(z == 12) // not used + { + // Yellow pixels (color FD2) + if ((x == 2 && y == 0) || (x == 7 && y == 0) || (x == 8 && y == 0) || + (x == 13 && y == 0) || (x == 1 && y == 1) || (x == 6 && y == 1) || + (x == 9 && y == 1) || (x == 14 && y == 1) || (x == 0 && y == 2) || + (x == 5 && y == 2) || (x == 10 && y == 2) || (x == 15 && y == 2) || + (x == 2 && y == 3) || (x == 3 && y == 3) || (x == 4 && y == 3) || + (x == 11 && y == 3) || (x == 12 && y == 3) || (x == 13 && y == 3) || + (x == 2 && y == 4) || (x == 13 && y == 4) || (x == 2 && y == 5) || + (x == 13 && y == 5) || (x == 1 && y == 6) || (x == 14 && y == 6) || + (x == 0 && y == 7) || (x == 15 && y == 7) || (x == 1 && y == 8) || + (x == 14 && y == 8) || (x == 2 && y == 9) || (x == 13 && y == 9) || + (x == 2 && y == 10) || (x == 13 && y == 10) || (x == 2 && y == 11) || + (x == 3 && y == 11) || (x == 4 && y == 11) || (x == 11 && y == 11) || + (x == 12 && y == 11) || (x == 13 && y == 11) || (x == 5 && y == 12) || + (x == 10 && y == 12) || (x == 0 && y == 13) || (x == 6 && y == 13) || + (x == 9 && y == 13) || (x == 15 && y == 13) || (x == 1 && y == 14) || + (x == 7 && y == 14) || (x == 8 && y == 14) || (x == 14 && y == 14) || + (x == 2 && y == 15) || (x == 3 && y == 15) || (x == 4 && y == 15) || + (x == 5 && y == 15) || (x == 6 && y == 15) || (x == 7 && y == 15) || + (x == 8 && y == 15) || (x == 9 && y == 15) || (x == 10 && y == 15) || + (x == 11 && y == 15) || (x == 12 && y == 15) || (x == 13 && y == 15)) + { + pixel = 0x00000FD2; // Yellow color (FD2) + } + // White pixels + else + { + pixel = 0xFFFFFFFF; // White color + } + } + else if(z == 13) // not used + { + pixel = 0x00000A0A; + } + else if(z == 14) // not used + { + pixel = 0x00000FFF; + } + else + { + pixel = 0x00000000; + } + reg_video_char[z * 256 + y * 16 + x] = pixel; + } + } + } +} + +/* + * brief handles the rotation of the piece + * return index of the rotated piece + */ +int Rotate(int x, int y, int r) +{ + int pi = 0; + switch (r % 4) + { + case 0: // 0 degrees // 0 1 2 3 + pi = y * 4 + x; // 4 5 6 7 + break; // 8 9 10 11 + //12 13 14 15 + + case 1: // 90 degrees //12 8 4 0 + pi = 12 + y - (x * 4); //13 9 5 1 + break; //14 10 6 2 + //15 11 7 3 + + case 2: // 180 degrees //15 14 13 12 + pi = 15 - (y * 4) - x; //11 10 9 8 + break; // 7 6 5 4 + // 3 2 1 0 + + case 3: // 270 degrees // 3 7 11 15 + pi = 3 - y + (x * 4); // 2 6 10 14 + break; // 1 5 9 13 + } // 0 4 8 12 + + return pi; +} + +/* + * brief checks if the piece can be moved to a specified position + * return true if the piece can fit and false otherwise + */ +bool DoesPieceFit(int tetrominosIndex, int nRotation, int nPosX, int nPosY) +{ + // All Field cells >0 are occupied + for (int x = 0; x < 4; x++) + for (int y = 0; y < 4; y++) + { + // Get index into piece + int pi = Rotate(x, y, nRotation); + + // Get index into field + int fi = (nPosY + y) * fieldWidth + (nPosX + x); + + // Check that test is in bounds. Note out of bounds does + // not necessarily mean a fail, as the long vertical piece + // can have cells that lie outside the boundary, so we'll + // just ignore them + if (nPosX + x >= 0 && nPosX + x < fieldWidth) + { + if (nPosY + y >= 0 && nPosY + y < fieldHeight) + { + // In Bounds so do collision check + if ((tetrominoes[tetrominosIndex][pi] != 0 && field[fi] != 0) /* || (tetrominoes[ntetrominoes][pi] != 0 && (nPosY+y)==0) */) // dodali smo || .... + return false; // fail on first hit + } + } + } + + return true; +} + +/* + * brief displays a digit on specified location + * return void + */ +void DrawDigit(int number, int startX, int startY) +{ + for (uint8_t y = startY; y < startY + 5; y++) + { + for (uint8_t x = startX; x < startX + 3; x++) + { + switch (number) + { + case 0: + if (x == startX || x == startX + 2 || y == startY || y == startY + 4) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 1: + if (x == startX + 2 || y == startY + 1) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 2: + if (y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 1 && x == startX + 2) || (y == startY + 3 && x == startX)) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 3: + if (x == startX + 2 || y == startY || y == startY + 2 ||y == startY + 4) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 4: + if (x == startX + 2 || y == startY + 2 || (y <= startY + 2 && x == startX)) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 5: + if (y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 1 && x == startX) || (y == startY + 3 && x == startX + 2)) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 6: + if (x == startX || y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 3 && x == startX + 2)) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 7: + if (x == startX + 2 || y == startY) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 8: + if (x == startX || x == startX + 2 || y == startY || y == startY + 2 || y == startY + 4) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + case 9: + if (x == startX + 2 || y == startY || y == startY + 2 || y == startY + 4 || (y == startY + 1 && x == startX)) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + break; + default: + break; + } + } + } +} + +/* + * brief displays the current player score + * return void + */ +void DisplayScore(int score, int startX, int startY) +{ + int digits[4] = {0,0,0,0}; + int i = 0; + while (score != 0) + { + digits[i++] = score % 10; + score /= 10; + } + + for (i = 3; i >= 0; i--) + { + DrawDigit(digits[i], startX + (3 - i)*4, startY); + } +} + +/* + * brief displays the word score on the screen + * return void + */ +void WriteScore(int score) +{ + for (uint8_t y = 24; y < 29; y++) { + for (uint8_t x = 3; x < 21; x++) { + if (x == 3 || x == 4) // letter S + { + if (y == 24 || y == 26 || y == 28 || (x == 3 && y == 25) || (x == 4 && y == 27)) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + } + else if (x == 6 || x == 7) // letter C + { + if (x == 6 || y == 24 || y == 28) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + } + else if (x == 9 || x == 10 || x == 11) // letter O + { + if (x == 9 || x == 11 || y == 24 || y == 28) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + } + else if (x == 13 || x == 14 || x == 15) // letter R + { + if (x == 13 || (x == 14 && (y == 24 || y == 26)) || (x == 15 && (y == 25 || y > 26))) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + } + else if (x == 17 || x == 18) // letter E + { + if (x == 17 || (x == 18 && y % 2 == 0)) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + } + else if (x == 20) // colon + { + if (y == 25 || y == 27) + field[y * fieldWidth + x] = 0; + else + field[y * fieldWidth + x] = 9; + } + } + } + + DisplayScore(score, 22, 24); +} +/* + * brief creating the initial field + * return void + */ +void FieldInitialization(){ + + for (uint8_t y = 0; y < fieldHeight; y++) + { + for (uint8_t x = 0; x < fieldWidth; x++) + { + field[y * fieldWidth + x] = (y == 0 || + y >= fieldHeight - 7 || + x + 1 == fieldWidth / 2 || + x == fieldWidth / 2 ) ? 9u : 0u; + } + } +} + +/* + * brief delay function, u32_delay = 40000 -> approx. 5 seconds + * return void + */ +static inline void _delay(uint32_t u32_delay) +{ + uint16_t local = 0; + for (uint32_t i = 0u; i> 17; + x ^= x << 5; + *state = x; + return x; +} +/* + * brief generates a random binary number (0 or 1) + * return int: The generated random binary number (0 or 1) + */ +int generateRandomBinary() { + static unsigned int state = 123456789; + return xorshift32(&state) % 2; +} +/* + * brief generates a random number within the specified range [min, max] + * param min: The minimum value of the range + * param max: The maximum value of the range + * return int: The generated random number within the range [min, max] + */ +int generateRandomNumber(int min, int max) { + static unsigned int state = 123456789; + unsigned int range = max - min + 1; + unsigned int randomValue = xorshift32(&state) % range + min; + return randomValue; +} + + +void main() +{ + reg_uart_clkdiv = 217; + print("TetriSaraj!\n"); + + bool rightButton = false, downButton = false, centerButton = false, upButton = false, leftButton = false; + + reg_gpio = 0x0; + + CharactersInit(); + DisplayProjectName(); + _delay(3000); // 15000 + + DisplayCompanyName(); + _delay(3000); + + DisplayGameName(); + _delay(3000); + + FieldInitialization(); + + setScreenColor(12); + + DisplayHeart(5,9,3); + DisplayHeart(15,9,3); + DisplayHeart(25,9,3); + _delay(4000); // 20000 + + // Game Logic + uint16_t pieceIndex = 0; + uint8_t pieceRotation = 3; + uint8_t pieceXCoordinate = 0; + uint8_t pieceYCoordinate = fieldHeight / 2; + + uint8_t speed = 15; + uint8_t gameTicksCount = 0; + uint8_t numLives=3; + bool movePiece = false; + bool rotationFlag = true; + + uint16_t pieceCount = 0; + uint16_t score = 0; + + uint8_t linesXCoordinates[4] = {0, 0, 0, 0}; + uint8_t linesCount = 0; + bool isGameOver = false; + bool isTheEnd = false; + uint8_t previousSide = 0; + bool hasScoreChanged = false; + + uint8_t randomSideGenerator = 0; // left - 0, right - 1 + + WriteScore(score); + + while (1) { + + if(isGameOver && numLives==1){ + isTheEnd=true; + isGameOver=false; + } + + if (isGameOver) + { + numLives=numLives-1; + DisplayGameOverScreen(numLives); + + _delay(4000); // 18000 + + for (uint8_t y = 0; y < fieldHeight; y++) + { + for (uint8_t x = 0; x < fieldWidth; x++) + { + field[y * fieldWidth + x] = (y == 0 || + y >= fieldHeight - 7 || + x + 1 == fieldWidth / 2 || + x == fieldWidth / 2 ) ? 9u : 0u; + } + } + isGameOver=false; + WriteScore(score); + } + + if (isTheEnd) + { + DisplayTheEndScreen(); + + while (!(buttons & BUTTON_CENTER)) + { + // Press center button to restart the game + GetButtonStates(); + } + + for (uint8_t y = 0; y < fieldHeight; y++) + { + for (uint8_t x = 0; x < fieldWidth; x++) + { + field[y * fieldWidth + x] = (y == 0 || + y >= fieldHeight - 7 || + x + 1 == fieldWidth / 2 || + x == fieldWidth / 2 ) ? 9u : 0u; + } + } + isTheEnd=false; + + score=0; + speed=15; + + WriteScore(score); + } + delay--; + + GetButtonStates(); + + if (buttons & BUTTON_UP) + { + upButton = true; + print("BUTTON_UP\n"); + } + if (buttons & BUTTON_DOWN) + { + downButton = true; + print("BUTTON_DOWN\n"); + } + if (buttons & BUTTON_RIGHT) + { + rightButton = true; + print("BUTTON_RIGHT\n"); + } + if (buttons & BUTTON_LEFT) + { + leftButton = true; + print("BUTTON_LEFT\n"); + } + if (buttons & BUTTON_CENTER) + { + centerButton = true; + print("BUTTON_CENTER\n"); + } + reg_gpio = 0x00000100 | buttons; // first 9 leds + + + // Game Logic + if (delay == 0) + { + delay = DELAY; + gameTicksCount++; + movePiece = (gameTicksCount == speed); + + + // Player input handling + if (!randomSideGenerator) // left part of the screen + { + pieceYCoordinate += (downButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate + 1)) ? 1 : 0; + pieceYCoordinate -= (upButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate - 1)) ? 1 : 0; + pieceXCoordinate += (rightButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate + 1, pieceYCoordinate)) ? 1 : 0; + } + else // right part of the screen + { + pieceYCoordinate -= (upButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate - 1)) ? 1 : 0; + pieceYCoordinate += (downButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate + 1)) ? 1 : 0; + pieceXCoordinate -= (leftButton && DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate - 1, pieceYCoordinate)) ? 1 : 0; + } + + if (centerButton) + { + pieceRotation += (rotationFlag && DoesPieceFit(pieceIndex, pieceRotation + 1, pieceXCoordinate, pieceYCoordinate)) ? 1 : 0; + rotationFlag = false; + } + else + rotationFlag = true; + + // Move the piece "down" the playfield if it's time + if (movePiece) + { + // Update difficulty every 50 pieces + gameTicksCount = 0; + pieceCount++; + if (pieceCount % 50 == 0) + if (speed >= 10) speed--; + + // Test if piece can be moved down + if (DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate + 1, pieceYCoordinate) && !randomSideGenerator) + { + pieceXCoordinate++; + } + else if (DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate - 1, pieceYCoordinate) && randomSideGenerator) + { + pieceXCoordinate--; + } + else + { + // Lock the piece in place + for (int x = 0; x < 4; x++) + { + for (int y = 0; y < 4; y++) + { + if (tetrominoes[pieceIndex][Rotate(x, y, pieceRotation)] != 0) + { + field[(pieceYCoordinate + y) * fieldWidth + (pieceXCoordinate + x)] = pieceIndex + 1; + } + } + } + + // Check if any lines formed + for (int x = 0; x < 4; x++) + { + bool bLine = true; + for (int y = 1; y < fieldHeight - 7; y++) + { + if (field[(pieceXCoordinate + x) + fieldWidth * y] == 0 || field[(pieceXCoordinate + x) + fieldWidth * y] == 9u) + { + bLine = false; + break; + } + } + + if (bLine) + { + // Remove the line + for (int y = 1; y < fieldHeight - 7; y++) + { + field[(pieceXCoordinate + x) + fieldWidth * y] = 0; + } + + // Remember the coordinates of the removed line + linesXCoordinates[linesCount] = pieceXCoordinate + x; + linesCount++; + } + } + previousSide = randomSideGenerator; + + // Score handling + score += 1; + if (linesCount != 0) score += (1 << linesCount) * 20; + hasScoreChanged = true; + + // Generate new piece + pieceYCoordinate = generateRandomNumber(2,19); + // Generate new side + randomSideGenerator= generateRandomBinary(); + + if (!randomSideGenerator) + { + pieceRotation = 3; + pieceXCoordinate = 0; + } + else + { + pieceRotation = 3; + pieceXCoordinate = fieldWidth - 4; + } + + pieceIndex = pieceCount % 7; + + // Game is over if the piece doesn't fit at the beginning + isGameOver = !DoesPieceFit(pieceIndex, pieceRotation, pieceXCoordinate, pieceYCoordinate); + } + } + + // Rendering part + if (hasScoreChanged) + { + hasScoreChanged = false; + DisplayScore(score, 22, 24); + } + + // Display the current field state + for (int y = 0; y < fieldHeight; y++) + { + for (int x = 0; x < fieldWidth; x++) + { + reg_video_map[y * fieldWidth + x] = field[y * fieldWidth + x]; + } + } + + // Display the current piece on the field + for (int x = 0; x < 4; x++) + { + for (int y = 0; y < 4; y++) + { + if (tetrominoes[pieceIndex][Rotate(x, y, pieceRotation)] != 0) + { + reg_video_map[(pieceYCoordinate + y) * fieldWidth + (pieceXCoordinate + x)] = pieceIndex + 1; + } + } + } + + // Handle the lines removal + if (linesCount != 0) + { + if (previousSide == 0) + { + for (uint8_t v = 0; v < linesCount; v++) + { + for (uint8_t x = linesXCoordinates[v]; x > 0; x--) + { + for (uint8_t y = 1; y < fieldHeight - 7; y++) + { + field[x + fieldWidth * y] = field[x - 1 + fieldWidth * y]; + } + } + } + } + else + { + for (uint8_t v = linesCount; v > 0; v--) + { + for (uint8_t x = linesXCoordinates[v - 1]; x < fieldWidth - 1; x++) + { + for (uint8_t y = 1; y < fieldHeight - 7; y++) + { + field[x + fieldWidth * y] = field[x + 1 + fieldWidth * y]; + } + } + } + + } + + // clear the coordinates array + linesXCoordinates[0] = 0; + linesXCoordinates[1] = 0; + linesXCoordinates[2] = 0; + linesXCoordinates[3] = 0; + linesCount = 0; + } + + rightButton = false; + downButton = false; + centerButton = false; + upButton = false; + leftButton = false; + } + } +} + diff --git a/chili-chips-ba_openCologne/5.TetriSaraj/README.md b/chili-chips-ba_openCologne/5.TetriSaraj/README.md new file mode 100644 index 0000000000000000000000000000000000000000..39a0ae4a9cb9d805e0fd43f943fd4fc3b2ebf517 --- /dev/null +++ b/chili-chips-ba_openCologne/5.TetriSaraj/README.md @@ -0,0 +1,94 @@ +# TetriSaraj on GateMate + +## Introduction + +This project is a demonstration of a complex digital hardware/software system. + +The hardware consists of a custom SoC with RISC-V CPU and our special _Video Controller_ that operates with _Mega Characters (MC)_, which are a close kin to the infamous _"Sprites"_. + +The software is bare-metal, w/o an OS, and implements a well-known, classic game, now rotated by 90 degrees and mirror-duplicated. + +The whole thing is called _TetriSaraj_, and essentially a port: +- from Digilent _Basys3_ (Artix7-35T) with openXC7 tools +- to Olimex _GateMate1-EVB_ board with CologneChip tools. + +For the complete design detail (game logic, system block diagram, memory mapping etc.), please visit the original project repo: +- https://github.com/chili-chips-ba/openXC7-TetriSaraj + +## Surprise, surprise... + +Other than the expected changes related to constraints, pinouts, makefile etc., the operating clock frequency emerged as the main (and indeed unexpected) difference between these two designs. + +The original TetriSaraj ran on Artix-7 at `100MHz` w/o problems, even when built with openXC7 PNR, as opposed to Xilinx-proprietary Vivado. That was however far from possible on GateMate FPGA, where the `Fmax for the original design was 16MHz`, and for a reduced/optimized version barely reached 31 MHz, even at the highest VDD_CORE setting. + +With VGA sub-system needing at least 25MHz, we decided to scale down the clock of the entire (already reduced) system to the `25MHz`. This then caused multiple timing issues in the video generation section (such as within _vga_controller.v_ and _top.v_), calling for significant timing-driven adaptations, in some instances even an overhaul. + +## Hardware setup + +Since Olimex comes with only 1 user button, we had to plug-in _SimpleIO Extension Board_ that brings additional buttons. + +The game needs 5 buttons: +- 4 arrows for the direction of movement +- plus 1 for the rotation. + +The complete setup is shown below: + + + +In addition to the _GateMateA1-EVB_, you will also need: +- monitor with VGA port connected to it. +- _SimpleIO Extension Board_ or, yet better, the new _**joyIO**_ card + + + +## The Gameplay + +Our progam starts with a small, but full-custom Splash 😄: + + + +But, you start with three lives, that is three hearts: + + + +As you're playin', you can earn more hearts, or lose them. +The more you earn, the harder we make it for you to play and win. + + + +Sorry, it's _"Game Over"_ when you lose your last heart. + + + +Time to try again... + + + +## Demo stream + +https://github.com/user-attachments/assets/12611cf4-5f7c-42ba-97fa-0026c773a5dd + +## How to build TetriSaraj for GateMate?! + +To synthesize and run the design locally, one must install the _CologneChip toolchain_ and adapt the _Makefile_. The whole process is explained in `3.build/Makefile`. + +## Our next play shall be audible + +Stay tuned for the arrival of stereo soundtrack to TetriSaraj play... + +## References +1) Also available on [Xilinx Artix7](https://github.com/chili-chips-ba/openXC7-TetriSaraj) and [Gowin LittleBee](https://github.com/chili-chips-ba/openXC7-TetriSaraj/tree/main/99.more-boards/0.tang-nano-9k), thanks to [SymbioticEDA](https://www.symbioticeda.com) support + +2) Postings and mentions: +> - [Dec.15, 2024](https://www.linkedin.com/feed/update/urn:li:activity:7273353028055769089?commentUrn=urn%3Ali%3Acomment%3A%28activity%3A7273353028055769089%2C7274166171325607936%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287274166171325607936%2Curn%3Ali%3Aactivity%3A7273353028055769089%29) +> - [Oct.15, 2024](https://www.linkedin.com/posts/chili-chips_tetrisaraj-gatemate-opensource-activity-7252167674741301249-gOgI?utm_source=share&utm_medium=member_desktop) +> - [Oct.11, 2024](https://www.linkedin.com/feed/update/urn:li:activity:7250565052359921665?commentUrn=urn%3Ali%3Acomment%3A%28activity%3A7250565052359921665%2C7250724417754836992%29&replyUrn=urn%3Ali%3Acomment%3A%28activity%3A7250565052359921665%2C7251814253668544513%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287250724417754836992%2Curn%3Ali%3Aactivity%3A7250565052359921665%29&dashReplyUrn=urn%3Ali%3Afsd_comment%3A%287251814253668544513%2Curn%3Ali%3Aactivity%3A7250565052359921665%29) +> - [Oct.1, 2024](https://www.linkedin.com/feed/update/urn:li:ugcPost:7246625338787602434?commentUrn=urn%3Ali%3Acomment%3A%28ugcPost%3A7246625338787602434%2C7247337428045209600%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287247337428045209600%2Curn%3Ali%3AugcPost%3A7246625338787602434%29) +> - [SarajevoMakerFaire 2024](https://sarajevo.makerfaire.com/maker/entry/143) +> - [May 2023](https://www.linkedin.com/posts/chili-chips_fpga-education-riscv-activity-7076630631165689858-wgK_?utm_source=share&utm_medium=member_desktop) +> - [April 2023](https://www.linkedin.com/posts/chili-chips_fpga-foss-yosys-activity-7069758169639505920-LRyG?utm_source=share&utm_medium=member_desktop) +> - and more... + + + +#### End of Document diff --git a/chili-chips-ba_openCologne/6.PCB.advanced/README.md b/chili-chips-ba_openCologne/6.PCB.advanced/README.md new file mode 100644 index 0000000000000000000000000000000000000000..33d3b8cff268de233cde8453de719459e766322d --- /dev/null +++ b/chili-chips-ba_openCologne/6.PCB.advanced/README.md @@ -0,0 +1,59 @@ +# PCB2 - Advanced (ULX5M-GS) + +For more, please see: +- [Extension_Boards_for_Olimex_GateMate repo](https://github.com/intergalaktik/ulx5m-gs) +- [PCB Request Issues](https://github.com/chili-chips-ba/openCologne/issues?q=label%3A%22PCB+request%22+) + +### ---Conceptual Design--- +

+ + +

+ +### ---Version1 Design--- + +#### V01 layout +

+ +

+ +#### V01 manufactured PCB +

+ +

+ +#### V01 bringup/debug +

+ +

+ +### ---Version2 Design--- + +##### V02 draft for team review +

+ + +

+ +##### V02 assembled prototype +

+ +

+ +#### V02 bringup/debug +[![ULX5M blinks LEDs on its own](0.doc/ulx5m-gs.v02.4.debug.jpg)](https://www.youtube.com/watch?v=LA20pfW7X00 "ULX5M is counting!") + + +#### V02 mounted on the CM4-BB3 carrier card +

+ + +

+ +#### V02 mounted on the CM4 "Piunora" carrier card +

+ + +

+ +#### End of Document diff --git a/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/README.md b/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/README.md new file mode 100644 index 0000000000000000000000000000000000000000..1c7e0f5ad4b044e953fd93c373cc9e939c4157df --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/README.md @@ -0,0 +1,145 @@ +# SerDes App for GateMate + +## References +- Measuring Eye Diagrams on [Rigol MSO5000](https://www.youtube.com/watch?si=vo3GYcDNML9LsX7S&v=JcJbcKl5llo&feature=youtu.be) + +## Verifying board setup + +Using the provided serdestool we can verify that our board setup is functioning correctrly. We can run a loopback test ( `./sedestool --tcloopback `) : + +``` + INFO: Found 1 device in JTAG chain. + INFO: Starting SerDes loopback testcases + + INFO: Enabling TX PMA Loopback (Mode 0) + INFO: Configuring SerDes ADPLL + INFO: SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s + INFO: Disabling SerDes ADPLL + INFO: Writing SerDes ADPLL divider settings + INFO: Stopping SerDes ADPLL self-calibration + INFO: Starting SerDes ADPLL + INFO: Starting SerDes ADPLL self-calibration + INFO: SerDes ADPLL locked + INFO: PFDAC result: max reached: 0, ac_result: 98320, CP: 3 + INFO: ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT: 708 SY: 0 ST: 2 + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 32-Bit comma alignment + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 16-Bit comma alignment + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 8-Bit comma alignment + + INFO: Enabling TX PMA Loopback (Mode 1) + INFO: Configuring SerDes ADPLL + INFO: SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s + INFO: Disabling SerDes ADPLL + INFO: Writing SerDes ADPLL divider settings + INFO: Stopping SerDes ADPLL self-calibration + INFO: Starting SerDes ADPLL + INFO: Starting SerDes ADPLL self-calibration + INFO: SerDes ADPLL locked + INFO: PFDAC result: max reached: 0, ac_result: 16, CP: 6 + INFO: ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT: 706 SY: 0 ST: 2 + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 32-Bit comma alignment + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 16-Bit comma alignment + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 8-Bit comma alignment + + INFO: Enabling TX PCS Loopback + INFO: Configuring SerDes ADPLL + INFO: SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s + INFO: Disabling SerDes ADPLL + INFO: Writing SerDes ADPLL divider settings + INFO: Stopping SerDes ADPLL self-calibration + INFO: Starting SerDes ADPLL + INFO: Starting SerDes ADPLL self-calibration + INFO: SerDes ADPLL locked + INFO: PFDAC result: max reached: 0, ac_result: 98330, CP: 25 + INFO: ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT: 707 SY: 0 ST: 2 + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 32-Bit comma alignment + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 16-Bit comma alignment + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Sending data (this might take a while) ... + INFO: Checking 8-Bit comma alignment + +``` +as well as a PRBS test (`./serdestool --tcprbs`): + + +``` + INFO: Found 1 device in JTAG chain. + INFO: Starting SerDes PRBS testcases + INFO: Configuring SerDes ADPLL + INFO: SerDes ADPLL frequency / data rate is 625.0 MHz / 1250.0 Mbit/s + INFO: Disabling SerDes ADPLL + INFO: Writing SerDes ADPLL divider settings + INFO: Stopping SerDes ADPLL self-calibration + INFO: Starting SerDes ADPLL + INFO: Starting SerDes ADPLL self-calibration + INFO: SerDes ADPLL locked + INFO: PFDAC result: max reached: 0, ac_result: 19, CP: 28 + INFO: ADPLL status: LCK: 1 FTO: 0 FTU: 0 FT: 708 SY: 0 ST: 2 + INFO: Resetting SerDes TX + INFO: Resetting SerDes RX + INFO: Setting up PRBS-7 + INFO: Sending data (this might take a while) ... + INFO: 0/10 + INFO: 1/10 + INFO: 2/10 + INFO: 3/10 + INFO: 4/10 + INFO: 5/10 + INFO: 6/10 + INFO: 7/10 + INFO: 8/10 + INFO: 9/10 + INFO: RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 0 + INFO: Starting error injection + INFO: RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 6 + INFO: Setting up PRBS-15 + INFO: Sending data (this might take a while) ... + INFO: 0/10 + INFO: 1/10 + INFO: 2/10 + INFO: 3/10 + INFO: 4/10 + INFO: 5/10 + INFO: 6/10 + INFO: 7/10 + INFO: 8/10 + INFO: 9/10 + INFO: RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 0 + INFO: Starting error injection + INFO: RX_PRBS_LOCKED: 1, RX_PRBS_ERR_CNT: 7 +``` + +P and N signals of the TX and RX channel are connected as in the following image: + +

+ +

+ + + +### End of Document diff --git a/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdes_lb.v b/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdes_lb.v new file mode 100644 index 0000000000000000000000000000000000000000..57956a22ddac30b29cd09172f90628b1f7db6181 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdes_lb.v @@ -0,0 +1,473 @@ +`timescale 1ns / 1ps + + +// # serdestool -- GateMate FPGA SerDes Toolkit +// # +// # Permission to use, copy, modify, and/or distribute this software for any +// # purpose with or without fee is hereby granted, provided that the above +// # copyright notice and this permission notice appear in all copies. +// # +// # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +// # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +// # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +// # ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +// # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +// # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +// # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +// # +// # Visit https://colognechip.com for more information. +// # +// # Copyright (C) 2022 - 2025 Cologne Chip AG +// # Authors: Patrick Urban + +module serdes_lb ( + input pll_rstn_i, + input trx_rstn_i, + input ref_clk, + + input RX_PRBS_CNT_RESET_I, + input TX_PRBS_FORCE_ERR_I, + + output [63:0] RX_DATA_O, + output PLL_CLK_O, + output RX_CLK_O, + + output RX_RESET_DONE_O_N, TX_RESET_DONE_O_N, + output TX_DETECT_RX_PRESENT_O_N, TX_DETECT_RX_DONE_O_N, + output TX_BUF_ERR_O_N, RX_BUF_ERR_O_N, + output RX_PRBS_ERR_O_N +); + + wire RX_COMMA_DETECT_EN_I = 1'b1; + + // reset + reg [8:0] rst_cnt = 0; + wire rstn = &rst_cnt; + wire rst = !rstn; + + always @(posedge ref_clk) begin + rst_cnt <= rst_cnt + !rstn; + end + + wire trx_rst_i = ~trx_rstn_i | rst; + wire pll_rst_i = ~pll_rstn_i | rst; + + wire CLK_CORE_PLL_O_N; + + wire TX_RESET_DONE_O; + wire RX_RESET_DONE_O; + assign TX_RESET_DONE_O_N = ~TX_RESET_DONE_O; + assign RX_RESET_DONE_O_N = ~RX_RESET_DONE_O; + + wire TX_DETECT_RX_PRESENT_O; + wire TX_DETECT_RX_DONE_O; + assign TX_DETECT_RX_PRESENT_O_N = ~TX_DETECT_RX_PRESENT_O; + assign TX_DETECT_RX_DONE_O_N = ~TX_DETECT_RX_DONE_O; + + wire RX_PRBS_ERR_O; + assign RX_PRBS_ERR_O_N = ~RX_PRBS_ERR_O; + + wire TX_BUF_ERR_O; + wire RX_BUF_ERR_O; + assign TX_BUF_ERR_O_N = ~TX_BUF_ERR_O; + assign RX_BUF_ERR_O_N = ~RX_BUF_ERR_O; + + wire [63:0] RX_DATA_O; + + wire RX_EI_EN_O, REGFILE_RDY_O, CLK_CORE_RX_O; + wire [7:0] RX_CHAR_IS_K_O, RX_CHAR_IS_COMMA_O, RX_NOT_IN_TABLE_O; + wire [15:0] REGFILE_DO_O; + + // 8b/10b control bytes + parameter [27:0] kChar = + //{8'hxx, 10'h000, 10'h000}; // K28_5 + //{8'h1C, 10'h303, 10'h0FC}; // K28_0 + //{8'h3C, 10'h343, 10'h1FC}; // K28_1 + //{8'h5C, 10'h383, 10'h27C}; // K28_2 + //{8'h7C, 10'h3C3, 10'h2FC}; // K28_3 + //{8'h9C, 10'h443, 10'h37C}; // K28_4 + {8'hBC, 10'h283, 10'h17C}; // K28_5 + //{8'hDC, 10'h4C3, 10'h3FC}; // K28_6 + //{8'hFC, 10'h503, 10'h47C}; // K28_7 + //{8'hFB, 10'h11C, 10'h38C}; // K27_7 + //{8'hFD, 10'h11C, 10'h38C}; // K29_7 + //{8'hFE, 10'h11C, 10'h38C}; // K30_7 + + // ADPLL clock settings + parameter N1 = 1; // 1/2 + parameter N2 = 2; // 2/3/4/5 + parameter N3 = 3; // 3/4/5 + parameter OUTDIV = 4; // 1/2/4 + + parameter DATAPATH = 80; // 80, 40, 20 + + parameter ENABLE_8B10B = 1'b1; + parameter ENABLE_COMMADETECT = 1'b1; + + parameter [2:0] PRBS_SEL = + 3'b000; // PRBS checker disabled + //3'b001; // PRBS-7 + //3'b010; // PRBS-15 + //3'b011; // PRBS-23 + //3'b100; // PRBS-31 + //3'b101; // RESERVED + //3'b110; // 2 UI square wave (TX ONLY) + //3'b111; // 20/40/80 UI square wave, depending on data path width (TX ONLY) + + parameter [2:0] LOOPBACK_SEL = + 3'b000; // normal operation + //3'b001; // near-end PCS Loopback + //3'b010; // near-end PMA Loopback + //3'b011; // reserved + //3'b100; // far-end PMA Loopback + //3'b101; // reserved + //3'b110; // far-end PCS Loopback + //3'b111; // reserved + + parameter [1:0] TX_PMA_LOOPBACK = + 2'b00; // disabled + //2'b01; // loopback from TX driver + //2'b10; // loopback from TX pads + + parameter [1:0] DATAPATH_SEL = { + (DATAPATH == 80) ? 2'b11 : (DATAPATH == 40) ? 2'b01 : (DATAPATH == 20) ? 2'b00 : 2'bx + }; // default: 2'h3 + + parameter [5:0] PLL_FCNTRL = { + DATAPATH == 80 ? 6'h3A : (DATAPATH == 40 ? 6'h3A : (DATAPATH == 20 ? 6'd26 : 6'bx)) + }; // default: 6'h3A = 58 ^= 20; + + parameter [5:0] PLL_MAIN_DIVSEL = { + 1'b0, // PLL_MAINDIV[5]: not used + N3 == 3 ? 2'b00 : (N3 == 4 ? 2'b10 : (N3 == 5 ? 2'b11 : 2'bx)), + N1 == 1 ? 1'b0 : (N1 == 2 ? 1'b1 : 1'bx), + N2 == 3 ? 2'b00 : (N2 == 2 ? 2'b01 : (N2 == 4 ? 2'b10 : (N2 == 5 ? 2'b11 : 2'bx))) + }; // default: 6'h1B; + + parameter [1:0] PLL_OUT_DIVSEL = { + OUTDIV == 1 ? 2'b00 : OUTDIV == 2 ? 2'b01 : OUTDIV == 4 ? 2'b11 : 2'bx + }; // default: 2'h0; + + parameter [14:0] RX_EYE_MEAS_CFG = {11'b0, 3'b0}; + + parameter K_POS = 0; + + function [63:0] calcTxData(input integer pos, input comma); + begin + if (comma == 1'b1) begin + calcTxData = + (pos == 0) ? 64'h4A4A4A4A_4A4A4ABC : + (pos == 1) ? 64'h4A4A4A4A_4A4ABC4A : + (pos == 2) ? 64'h4A4A4A4A_4ABC4A4A : + (pos == 3) ? 64'h4A4A4A4A_BC4A4A4A : + (pos == 4) ? 64'h4A4A4ABC_4A4A4A4A : + (pos == 5) ? 64'h4A4ABC4A_4A4A4A4A : + (pos == 6) ? 64'h4ABC4A4A_4A4A4A4A : 64'hBC4A4A4A_4A4A4A4A; + end + else begin + calcTxData = + (pos == 0) ? 64'h08070605_04030201 : + (pos == 1) ? 64'h07060504_03020108 : + (pos == 2) ? 64'h06050403_02010807 : + (pos == 3) ? 64'h05040302_01080706 : + (pos == 4) ? 64'h04030201_08070605 : + (pos == 5) ? 64'h03020108_07060504 : + (pos == 6) ? 64'h02010807_06050403 : 64'h01080706_05040302; + end + end + endfunction + + function [7:0] calcTxK(input integer pos, input comma); + begin + if (comma == 1'b1) begin + calcTxK = + (comma_pos == 0) ? 8'b0000_0001 : + (comma_pos == 1) ? 8'b0000_0010 : + (comma_pos == 2) ? 8'b0000_0100 : + (comma_pos == 3) ? 8'b0000_1000 : + (comma_pos == 4) ? 8'b0001_0000 : + (comma_pos == 5) ? 8'b0010_0000 : + (comma_pos == 6) ? 8'b0100_0000 : 8'b1000_0000; + end + else begin + calcTxK = 8'b0000_0000; + end + end + endfunction + + +// CC_SERDES instance generator +// generated: 2024-01-31 13:57:01 + +CC_SERDES #( + .RX_BUF_RESET_TIME(5'h3), + .RX_PCS_RESET_TIME(5'h3), + .RX_RESET_TIMER_PRESC(5'h0), + .RX_RESET_DONE_GATE(1'h0), + .RX_CDR_RESET_TIME(5'h3), + .RX_EQA_RESET_TIME(5'h3), + .RX_PMA_RESET_TIME(5'h3), + .RX_WAIT_CDR_LOCK(1'b0), // turn off if loopback enabled + .RX_CALIB_EN(1'h1), + .RX_CALIB_OVR(1'h0), + .RX_CALIB_VAL(4'h0), + .RX_RTERM_VCMSEL(3'h4), + .RX_RTERM_PD(1'h0), + .RX_EQA_CKP_LF(8'hA3), + .RX_EQA_CKP_HF(8'hA3), + .RX_EQA_CKP_OFFSET(8'h01), + .RX_EN_EQA(1'h0), + .RX_EQA_LOCK_CFG(4'h0), + .RX_TH_MON1(5'h8), + .RX_EN_EQA_EXT_VALUE(4'h0), + .RX_TH_MON2(5'h8), + .RX_TAPW(5'h8), + .RX_AFE_OFFSET(5'h8), + .RX_EQA_CONFIG(16'h1C0), + .RX_AFE_PEAK(5'hF), + .RX_AFE_GAIN(4'h8), + .RX_AFE_VCMSEL(3'h4), + .RX_CDR_CKP(8'hF8), + .RX_CDR_CKI(8'h00), + .RX_CDR_TRANS_TH(9'h80), // h15? + .RX_CDR_LOCK_CFG(6'hB), + .RX_CDR_FREQ_ACC(15'h0), + .RX_CDR_PHASE_ACC(16'h0000), + .RX_CDR_SET_ACC_CONFIG(2'h0), + .RX_CDR_FORCE_LOCK(1'h0), + .RX_ALIGN_MCOMMA_VALUE(kChar[19:10]), + .RX_MCOMMA_ALIGN_OVR(1'h0), + .RX_MCOMMA_ALIGN(1'h0), + .RX_ALIGN_PCOMMA_VALUE(kChar[9:0]), + .RX_PCOMMA_ALIGN_OVR(1'h0), + .RX_PCOMMA_ALIGN(1'h0), + .RX_ALIGN_COMMA_WORD(2'h3), // 11: 32 bit, 01: 16 bit, 00: 8 bit + .RX_ALIGN_COMMA_ENABLE(10'h3FF), + .RX_SLIDE_MODE(2'b00), // !!! + .RX_COMMA_DETECT_EN_OVR(1'h0), + .RX_COMMA_DETECT_EN(1'h0), + .RX_SLIDE(2'h0), + .RX_EYE_MEAS_EN(1'h0), + .RX_EYE_MEAS_CFG(RX_EYE_MEAS_CFG), + .RX_MON_PH_OFFSET(6'h0), + .RX_EI_BIAS(4'h4), + .RX_EI_BW_SEL(4'h4), + .RX_EN_EI_DETECTOR_OVR(1'h0), + .RX_EN_EI_DETECTOR(1'h0), + .RX_DATA_SEL(1'h0), + .RX_BUF_BYPASS(1'h0), + .RX_CLKCOR_USE(1'h0), + .RX_CLKCOR_MIN_LAT(6'h20), + .RX_CLKCOR_MAX_LAT(6'h27), + .RX_CLKCOR_SEQ_1_0(10'h1F7), + .RX_CLKCOR_SEQ_1_1(10'h1F7), + .RX_CLKCOR_SEQ_1_2(10'h1F7), + .RX_CLKCOR_SEQ_1_3(10'h1F7), + .RX_PMA_LOOPBACK(1'h0), + .RX_PCS_LOOPBACK(1'h0), + .RX_DATAPATH_SEL(DATAPATH_SEL), + .RX_PRBS_OVR(1'b0), + .RX_PRBS_SEL(PRBS_SEL), + .RX_LOOPBACK_OVR(1'h0), + .RX_PRBS_CNT_RESET(1'h0), + .RX_POWER_DOWN_OVR(1'h0), + .RX_POWER_DOWN_N(1'h1), + .RX_RESET_OVR(1'h0), + .RX_RESET(1'h0), + .RX_PMA_RESET_OVR(1'h0), + .RX_PMA_RESET(1'h0), + .RX_EQA_RESET_OVR(1'h0), + .RX_EQA_RESET(1'h0), + .RX_CDR_RESET_OVR(1'h0), + .RX_CDR_RESET(1'h0), + .RX_PCS_RESET_OVR(1'h0), + .RX_PCS_RESET(1'h0), + .RX_BUF_RESET_OVR(1'h0), + .RX_BUF_RESET(1'h0), + .RX_POLARITY_OVR(1'h0), + .RX_POLARITY(1'h0), + .RX_8B10B_EN_OVR(1'h0), + .RX_8B10B_EN(1'h0), + .RX_8B10B_BYPASS(8'h0), + .RX_BYTE_REALIGN(1'h0), + .TX_SEL_PRE(5'h0), + .TX_SEL_POST(5'h0), + .TX_AMP(5'hF), + .TX_BRANCH_EN_PRE(5'h0), + .TX_BRANCH_EN_MAIN(6'h3F), + .TX_BRANCH_EN_POST(5'h0), + .TX_TAIL_CASCODE(3'h4), + .TX_DC_ENABLE(7'h3F), + .TX_DC_OFFSET(5'h8), // ? note: set to 8 + .TX_CM_RAISE(5'h0), + .TX_CM_THRESHOLD_0(5'hE), + .TX_CM_THRESHOLD_1(5'h10), + .TX_SEL_PRE_EI(5'h0), + .TX_SEL_POST_EI(5'h0), + .TX_AMP_EI(5'hF), + .TX_BRANCH_EN_PRE_EI(5'h0), + .TX_BRANCH_EN_MAIN_EI(6'h3F), + .TX_BRANCH_EN_POST_EI(5'h0), + .TX_TAIL_CASCODE_EI(3'h4), + .TX_DC_ENABLE_EI(7'h3F), + .TX_DC_OFFSET_EI(5'h0), + .TX_CM_RAISE_EI(5'h0), + .TX_CM_THRESHOLD_0_EI(5'hE), + .TX_CM_THRESHOLD_1_EI(5'h10), + .TX_SEL_PRE_RXDET(5'h0), + .TX_SEL_POST_RXDET(5'h0), + .TX_AMP_RXDET(5'hF), + .TX_BRANCH_EN_PRE_RXDET(5'h0), + .TX_BRANCH_EN_MAIN_RXDET(6'h3F), + .TX_BRANCH_EN_POST_RXDET(5'h0), + .TX_TAIL_CASCODE_RXDET(3'h4), + .TX_DC_ENABLE_RXDET(7'h3F), + .TX_DC_OFFSET_RXDET(5'h0), + .TX_CM_RAISE_RXDET(5'h0), + .TX_CM_THRESHOLD_0_RXDET(5'hE), + .TX_CM_THRESHOLD_1_RXDET(5'h10), + .TX_CALIB_EN(1'h0), + .TX_CALIB_OVR(1'h0), + .TX_CALIB_VAL(4'h0), + .TX_CM_REG_KI(8'h80), + .TX_CM_SAR_EN(1'h0), + .TX_CM_REG_EN(1'h1), + .TX_PMA_RESET_TIME(5'h3), + .TX_PCS_RESET_TIME(5'h3), + .TX_PCS_RESET_OVR(1'h0), + .TX_PCS_RESET(1'h0), + .TX_PMA_RESET_OVR(1'h0), + .TX_PMA_RESET(1'h0), + .TX_RESET_OVR(1'h0), + .TX_RESET(1'h0), + .TX_PMA_LOOPBACK(TX_PMA_LOOPBACK), + .TX_PCS_LOOPBACK(1'h0), + .TX_DATAPATH_SEL(DATAPATH_SEL), + .TX_PRBS_OVR(1'b0), + .TX_PRBS_SEL(PRBS_SEL), + .TX_PRBS_FORCE_ERR(1'h0), + .TX_LOOPBACK_OVR(1'h0), + .TX_POWER_DOWN_OVR(1'h0), + .TX_POWER_DOWN_N(1'h1), + .TX_ELEC_IDLE_OVR(1'h0), + .TX_ELEC_IDLE(1'h0), + .TX_DETECT_RX_OVR(1'h0), + .TX_DETECT_RX(1'h0), + .TX_POLARITY_OVR(1'h0), + .TX_POLARITY(1'h0), + .TX_8B10B_EN_OVR(1'h0), + .TX_8B10B_EN(1'h0), + .TX_DATA_OVR(1'h0), + .TX_DATA_CNT(3'h0), + .TX_DATA_VALID(1'h0), + .PLL_EN_ADPLL_CTRL(1'h1), + .PLL_CONFIG_SEL(1'h1), // 0: internal, 1: regfile + .PLL_SET_OP_LOCK(1'h0), + .PLL_ENFORCE_LOCK(1'h0), + .PLL_DISABLE_LOCK(1'h0), + .PLL_LOCK_WINDOW(1'h1), // 0: long, 1: short + .PLL_FAST_LOCK(1'h1), + .PLL_SYNC_BYPASS(1'h0), + .PLL_PFD_SELECT(1'h0), + .PLL_REF_BYPASS(1'h0), + .PLL_REF_SEL(1'h1), // 0: single-ended, 1: lvds + .PLL_REF_RTERM(1'h1), + .PLL_FCNTRL(PLL_FCNTRL), + .PLL_MAIN_DIVSEL(PLL_MAIN_DIVSEL), + .PLL_OUT_DIVSEL(PLL_OUT_DIVSEL), + .PLL_CI(5'h3), + .PLL_CP(10'h50), + .PLL_AO(4'h0), + .PLL_SCAP(3'h0), + .PLL_FILTER_SHIFT(2'h2), + .PLL_SAR_LIMIT(3'h2), + .PLL_FT(11'h200), + .PLL_OPEN_LOOP(1'h0), + .PLL_SCAP_AUTO_CAL(1'h1), + .PLL_BISC_MODE(3'h5), // MODE B, enable + .PLL_BISC_TIMER_MAX(4'hC), + .PLL_BISC_OPT_DET_IND(1'h0), + .PLL_BISC_PFD_SEL(1'h0), + .PLL_BISC_DLY_DIR(1'h0), + .PLL_BISC_COR_DLY(3'h1), + .PLL_BISC_CAL_SIGN(1'h1), + .PLL_BISC_CAL_AUTO(1'h1), + .PLL_BISC_CP_MIN(5'h6), + .PLL_BISC_CP_MAX(5'h1E), + .PLL_BISC_CP_START(5'h6), + .PLL_BISC_DLY_PFD_MON_REF(5'h0), + .PLL_BISC_DLY_PFD_MON_DIV(5'h2), + .SERDES_ENABLE(1'h1), + .SERDES_AUTO_INIT(1'h0), + .SERDES_TESTMODE(1'h1) +) i_cc_serdes ( + // ADPLL + .RX_CLK_O(RX_CLK_O), // CDR CLK + .PLL_CLK_O(PLL_CLK_O), + // LOPPBACK + .LOOPBACK_I(LOOPBACK_SEL), + // RESET + .TX_RESET_I(trx_rst_i), + .RX_RESET_I(trx_rst_i), + .RX_PMA_RESET_I(1'b0), + .RX_EQA_RESET_I(1'b0), + .RX_CDR_RESET_I(1'b0), + .RX_PCS_RESET_I(1'b0), + .RX_BUF_RESET_I(1'b0), + .TX_PCS_RESET_I(1'b0), + .TX_PMA_RESET_I(1'b0), + .PLL_RESET_I(pll_rst_i), + .TX_RESET_DONE_O(TX_RESET_DONE_O), + .RX_RESET_DONE_O(RX_RESET_DONE_O), + // TX + .TX_CLK_I(PLL_CLK_O), + .TX_DATA_I(calcTxData(K_POS, 1'b1)), + .TX_POWER_DOWN_N_I(1'h1), + .TX_POLARITY_I(1'h0), + .TX_PRBS_SEL_I(PRBS_SEL), + .TX_PRBS_FORCE_ERR_I(TX_PRBS_FORCE_ERR_I), + .TX_8B10B_EN_I(ENABLE_8B10B), + .TX_8B10B_BYPASS_I(8'h0), + .TX_CHAR_IS_K_I(calcTxK(K_POS, RX_COMMA_DETECT_EN_I)), + .TX_CHAR_DISPMODE_I(8'h0), + .TX_CHAR_DISPVAL_I(8'h0), + .TX_ELEC_IDLE_I(1'h0), + .TX_DETECT_RX_I(1'b1), + .TX_BUF_ERR_O(TX_BUF_ERR_O), + // RX + .RX_CLK_I(RX_CLK_O), + .RX_POWER_DOWN_N_I(1'h1), + .RX_POLARITY_I(1'h0), + .RX_PRBS_SEL_I(PRBS_SEL), + .RX_PRBS_CNT_RESET_I(RX_PRBS_CNT_RESET_I), + .RX_PRBS_ERR_O(RX_PRBS_ERR_O), + .RX_8B10B_EN_I(ENABLE_8B10B), + .RX_8B10B_BYPASS_I(8'h0), + .RX_EN_EI_DETECTOR_I(1'h0), + .RX_COMMA_DETECT_EN_I(RX_COMMA_DETECT_EN_I), + .RX_SLIDE_I(1'h0), + .RX_MCOMMA_ALIGN_I(RX_COMMA_DETECT_EN_I), + .RX_PCOMMA_ALIGN_I(RX_COMMA_DETECT_EN_I), + .RX_DATA_O(RX_DATA_O), + .RX_NOT_IN_TABLE_O(), + .RX_CHAR_IS_COMMA_O(), + .RX_CHAR_IS_K_O(), + .RX_DISP_ERR_O(), + .TX_DETECT_RX_DONE_O(TX_DETECT_RX_DONE_O), + .TX_DETECT_RX_PRESENT_O(TX_DETECT_RX_PRESENT_O), + .RX_BUF_ERR_O(RX_BUF_ERR_O), + .RX_BYTE_IS_ALIGNED_O(), + .RX_BYTE_REALIGN_O(), + .RX_EI_EN_O(), + // REGFILE + .REGFILE_CLK_I(1'h0), + .REGFILE_WE_I(1'h0), + .REGFILE_EN_I(1'h0), + .REGFILE_ADDR_I(8'h0), + .REGFILE_DI_I(16'h0), + .REGFILE_MASK_I(16'h0), + .REGFILE_DO_O(REGFILE_DO_O), + .REGFILE_RDY_O(REGFILE_RDY_O) +); + +endmodule diff --git a/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdestool.py b/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdestool.py new file mode 100644 index 0000000000000000000000000000000000000000..601163ca183667156c80ab78bf117e9ab1bef4cb --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/1.serdestool_by_gm/serdestool.py @@ -0,0 +1,1584 @@ +#!/usr/bin/env python3 +# +# serdestool -- GateMate FPGA SerDes Toolkit +# +# Permission to use, copy, modify, and/or distribute this software for any +# purpose with or without fee is hereby granted, provided that the above +# copyright notice and this permission notice appear in all copies. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +# +# Visit https://colognechip.com for more information. +# +# Copyright (C) 2022 - 2025 Cologne Chip AG +# Authors: Patrick Urban +# + +import re +import sys +import math +import curses +import random +import signal +import argparse +import datetime +import threading + +from time import sleep +from itertools import chain + +from pyftdi.ftdi import Ftdi +from pyftdi.jtag import JtagEngine +from pyftdi.usbtools import UsbTools +from pyftdi.bits import BitSequence + +Boards_e = ['auto', 'pgm', 'evb'] +ArgEpilog = 'example usage: python3 serdestool.py' + +SER_CLK_PERIOD_NS = 10.0 + +class bcolors: + OK = '\033[92m' # GREEN + WARN = '\033[93m' # YELLOW + FAIL = '\033[91m' # RED + OVR = '\033[94m' # BLUE + RESET = '\033[0m' # RESET COLOR + +def ArgHzRegex(value, pat=re.compile(r"^[0-9]+[kM]")): + if not pat.match(value): + raise argparse.ArgumentTypeError + return value + +def ArgHzParse(value) -> int: + freq = 0 + if value.endswith('k'): + freq = int(value[:-1]) * 1e3 + elif value.endswith('M'): + freq = int(value[:-1]) * 1e6 + else: + freq = int(value) + return freq + +def FindAndFormatFtdiAddr(idx=0) -> str: + ftdiname = { + 0x6010: '2232h', + 0x6014: '232h' + } + usb = UsbTools() + vps_lst = list() + vps_lst.append((0x0403, 0x6010)) # evb: FT2232H + vps_lst.append((0x0403, 0x6014)) # pgm: FT232H + d = usb.find_all(vps=vps_lst) + if not d: + raise Exception('Error: No FTDI device found.') + d = d[idx][0] + return f'ftdi://ftdi:{ftdiname[d[1]]}/1' + +class ColorFormatter: + pos_cond = ["DONE", "PRESENT", "LOCKED", "IS_ALIGNED", "EN_ADPLL_CTRL", "CONFIG_SEL", "SERDES_ENABLE"] + neg_cond = ["ERR", "DOWN", "TESTMODE"] + ovr_cond = ["OVR"] + + @staticmethod + def get_color_pair(key, value): + """Returns the curses color pair based on the value conditions.""" + try: + value = int(value) # Convert safely to integer + except ValueError: + return 0 # Default color if conversion fails + + if any(cond in key for cond in ColorFormatter.pos_cond): + return 1 if value != 0 else 2 # Green for positive, Yellow for zero + elif any(cond in key for cond in ColorFormatter.neg_cond) and not any(cond in key for cond in ColorFormatter.ovr_cond): + return 3 if (value < 1 if key.endswith('_N') else value > 0) else 0 # Red for errors + elif any(cond in key for cond in ColorFormatter.ovr_cond) and value > 0: + return 4 # Blue for "OVR" values + return 0 # Default + +class JtagTool: + CMD_JTAG_ID = '000000' # 0x00 + CMD_JTAG_BYPASS = '111111' # 0x3F + CMD_JTAG_CONFIGURE = '000110' # 0x06 + CMD_JTAG_WR_SERDES_REGFILE = '100101' # 0x25 + CMD_JTAG_RD_SERDES_REGFILE = '100110' # 0x26 + + CMD_JTAG_STATUS_PLL0 = '011100' # 0x1C + CMD_JTAG_STATUS_PLL1 = '011101' # 0x1D + CMD_JTAG_STATUS_PLL2 = '011110' # 0x1E + CMD_JTAG_STATUS_PLL3 = '011111' # 0x1F + + _chain_idx = 0 + _taps_before = 0 + + def __init__(self, engine): + self._engine = engine + self._chain_idx = args.idx + self.idcode() + + def write_ir(self, instruction) -> None: + byp_before = BitSequence('1'*6*self._taps_before, msb=True) + byp_after = BitSequence('1'*6*self._chain_idx, msb=True) + self._engine.write_ir(byp_before+instruction+byp_after) + + def write_dr(self, data) -> None: + byp_before = BitSequence('0'*self._taps_before, msb=True) + byp_after = BitSequence('0'*self._chain_idx, msb=True) + self._engine.write_dr(byp_after+data+byp_before) + + def read_dr(self, length: int) -> BitSequence: + word = self._engine.read_dr(length+self._taps_before) + if self._chain_idx > 0: + return word[self._taps_before:-self._chain_idx] + else: + return word[self._taps_before:] + + def get_chunk(self, data, start, length): + return (data >> start) & ((1 << length) - 1) + + # Read the IDCODE right after JTAG reset + def idcode(self) -> int: + idcodes = self._engine.read_dr(128) + self._engine.go_idle() + chain_len = 0 + for i in range(0, 128, 32): + chunk_data = self.get_chunk(int(idcodes), i, 32) + if chunk_data != 0: + chain_len += 1 + print(f'INFO: Found {chain_len} device{"s" if chain_len > 1 else ""} in JTAG chain.') + self._taps_before = chain_len - self._chain_idx - 1 + return chain_len + + # Read the IDCODE using CMD_JTAG_ID + def idcode_seq(self) -> int: + self.write_ir(BitSequence(self.CMD_JTAG_ID, msb=True)) + status = self.read_dr(32) + self._engine.go_idle() + return int(status) + + # Configure FPGA using CMD_JTAG_CONFIGURE + def wr_cfg(self, cfg_data): + a = [] + b = bytearray(cfg_data) + + for i in range(len(b)): + a.append(int(b[i])) + + seq = BitSequence(bytes_=a[:-1], length=len(b)*8, msb=False, msby=True) + + self.write_ir(BitSequence(self.CMD_JTAG_CONFIGURE, msb=True)) + self.write_dr(seq) + self._engine.go_idle() + + def wr_serdes_regfile(self, addr, data, mask, wren): + self.write_ir(BitSequence(self.CMD_JTAG_WR_SERDES_REGFILE, msb=True)) + cmd = BitSequence(value=addr, length=8, msb=False, msby=True) + cmd += BitSequence(value=data, length=16, msb=False, msby=True) + cmd += BitSequence(value=mask, length=16, msb=False, msby=True) + cmd += BitSequence(value=wren, length=1, msb=False, msby=True) + self.write_dr(cmd) + self._engine.go_idle() + + def rd_serdes_regfile(self): + self.write_ir(BitSequence(self.CMD_JTAG_RD_SERDES_REGFILE, msb=True)) + word = self.read_dr(16) + self._engine.go_idle() + return word + + def rd_status_pll(self, device=1, pll=0, verbose=0): + bs = BitSequence() + if pll == 0: + bs += BitSequence(self.CMD_JTAG_STATUS_PLL0, msb=True) + elif pll == 1: + bs += BitSequence(self.CMD_JTAG_STATUS_PLL1, msb=True) + elif pll == 2: + bs += BitSequence(self.CMD_JTAG_STATUS_PLL2, msb=True) + elif pll == 3: + bs += BitSequence(self.CMD_JTAG_STATUS_PLL3, msb=True) + else: + raise JtagError("Invalid PLL number: %s" % pll) + return 0 + self._engine.write_ir(bs) + status = self._engine.read_dr(17) + self._engine.go_idle() + + pll_status_bin = '{:017b}'.format(int(status)) + if verbose: + print('pll{}: 0x{:05X}'.format(pll, int(status))) + print('pll%d: 0b%s' %(pll, pll_status_bin)) + + # 0: fine tune overflow flag + # 1: fine tune underflow flag + # 11: 2: fine tune value + # 13:12: state + # 16:14: coarse tune value + print('pll%d: fine tune overflow flag : %s ' %(pll, pll_status_bin[-1])) + print('pll%d: fine tune underflow flag : %s ' %(pll, pll_status_bin[-2])) + print('pll%d: fine tune value : %s ' %(pll, pll_status_bin[-12:-2])) + + #S_IDLE = ‘d0; S_LOCK_IN = ‘d1; S_LOCKED = ‘d2; S_FAST_LOCK = ‘d3; + if pll_status_bin[-14:-12] == '00': + print('pll%d: state : %s -> S_IDLE' %(pll, pll_status_bin[-14:-12])) + elif pll_status_bin[-14:-12] == '01': + print('pll%d: state : %s -> S_LOCK_IN' %(pll, pll_status_bin[-14:-12])) + elif pll_status_bin[-14:-12] == '10': + print('pll%d: state : %s -> S_LOCKED' %(pll, pll_status_bin[-14:-12])) + elif pll_status_bin[-14:-12] == '11': + print('pll%d: state : %s -> S_FAST_LOCK' %(pll, pll_status_bin[-14:-12])) + print('pll%d: coarse tune value : %s ' %(pll, pll_status_bin[-17:-14])) + return (pll_status_bin[-14:-12] == '10') # locked + +class SerdesRegfile: + def __init__(self, initial_fields): + self.fields = initial_fields + +class SerdesTool: + regfile = SerdesRegfile({ + 'RX_BUF_RESET_TIME': {'addr': 0x00, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 3}, + 'RX_PCS_RESET_TIME': {'addr': 0x00, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 3}, + 'RX_RESET_TIMER_PRESC': {'addr': 0x00, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 0}, + 'RX_RESET_DONE_GATE': {'addr': 0x00, 'mode': 'R/W', 'hbit': 15, 'lbit': 15, 'val': 0}, + 'RX_CDR_RESET_TIME': {'addr': 0x01, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 3}, + 'RX_EQA_RESET_TIME': {'addr': 0x01, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 3}, + 'RX_PMA_RESET_TIME': {'addr': 0x01, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 3}, + 'RX_WAIT_CDR_LOCK': {'addr': 0x01, 'mode': 'R/W', 'hbit': 15, 'lbit': 15, 'val': 0}, + 'RX_CALIB_EN': {'addr': 0x02, 'mode': 'W/C', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'RX_CALIB_DONE': {'addr': 0x02, 'mode': 'R', 'hbit': 1, 'lbit': 1, 'val': 1}, + 'RX_CALIB_OVR': {'addr': 0x02, 'mode': 'R/W', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'RX_CALIB_VAL': {'addr': 0x02, 'mode': 'R/W', 'hbit': 6, 'lbit': 3, 'val': 0}, + 'RX_CALIB_CAL': {'addr': 0x02, 'mode': 'R', 'hbit': 10, 'lbit': 7, 'val': 0}, + 'RX_RTERM_VCMSEL': {'addr': 0x02, 'mode': 'R/W', 'hbit': 13, 'lbit': 11, 'val': 4}, + 'RX_RTERM_PD': {'addr': 0x02, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0}, + 'RX_EQA_CKP_LF': {'addr': 0x03, 'mode': 'R/W', 'hbit': 7, 'lbit': 0, 'val': 0xA3}, + 'RX_EQA_CKP_HF': {'addr': 0x03, 'mode': 'R/W', 'hbit': 15, 'lbit': 8, 'val': 0xA3}, + 'RX_EQA_CKP_OFFSET': {'addr': 0x04, 'mode': 'R/W', 'hbit': 7, 'lbit': 0, 'val': 1}, + 'RX_EN_EQA': {'addr': 0x04, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'RX_EQA_LOCK_CFG': {'addr': 0x04, 'mode': 'R/W', 'hbit': 12, 'lbit': 9, 'val': 0}, + 'RX_EQA_LOCKED': {'addr': 0x04, 'mode': 'R', 'hbit': 13, 'lbit': 13, 'val': 0}, + 'RX_TH_MON1': {'addr': 0x05, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 8}, + 'RX_EN_EQA_EXT_VALUE[0]': {'addr': 0x05, 'mode': 'R/W', 'hbit': 5, 'lbit': 5, 'val': 0}, + 'RX_TH_MON2': {'addr': 0x05, 'mode': 'R/W', 'hbit': 10, 'lbit': 6, 'val': 8}, + 'RX_EN_EQA_EXT_VALUE[1]': {'addr': 0x05, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'RX_TAPW': {'addr': 0x06, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 8}, + 'RX_EN_EQA_EXT_VALUE[2]': {'addr': 0x06, 'mode': 'R/W', 'hbit': 5, 'lbit': 5, 'val': 0}, + 'RX_AFE_OFFSET': {'addr': 0x06, 'mode': 'R/W', 'hbit': 10, 'lbit': 6, 'val': 8}, + 'RX_EN_EQA_EXT_VALUE[3]': {'addr': 0x06, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'RX_EQA_TAPW': {'addr': 0x07, 'mode': 'R', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'RX_TH_MON': {'addr': 0x07, 'mode': 'R', 'hbit': 9, 'lbit': 5, 'val': 0}, + 'RX_OFFSET': {'addr': 0x07, 'mode': 'R', 'hbit': 13, 'lbit': 10, 'val': 0}, + 'RX_EQA_CONFIG': {'addr': 0x08, 'mode': 'R/W', 'hbit': 15, 'lbit': 0, 'val': 0x01C0}, + 'RX_AFE_PEAK': {'addr': 0x09, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 15}, + 'RX_AFE_GAIN': {'addr': 0x09, 'mode': 'R/W', 'hbit': 8, 'lbit': 5, 'val': 8}, + 'RX_AFE_VCMSEL': {'addr': 0x09, 'mode': 'R/W', 'hbit': 11, 'lbit': 9, 'val': 4}, + 'RX_CDR_CKP': {'addr': 0x0A, 'mode': 'R/W', 'hbit': 7, 'lbit': 0, 'val': 0xF8}, + 'RX_CDR_CKI': {'addr': 0x0A, 'mode': 'R/W', 'hbit': 15, 'lbit': 8, 'val': 0}, + 'RX_CDR_TRANS_TH': {'addr': 0x0B, 'mode': 'R/W', 'hbit': 8, 'lbit': 0, 'val': 128}, + 'RX_CDR_LOCK_CFG': {'addr': 0x0B, 'mode': 'R/W', 'hbit': 14, 'lbit': 9, 'val': 0x0B}, + 'RX_CDR_LOCKED': {'addr': 0x0B, 'mode': 'R', 'hbit': 15, 'lbit': 15, 'val': 0}, + 'RX_CDR_FREQ_ACC_VAL': {'addr': 0x0C, 'mode': 'R', 'hbit': 14, 'lbit': 0, 'val': 0}, + 'RX_CDR_PHASE_ACC_VAL': {'addr': 0x0D, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_CDR_FREQ_ACC': {'addr': 0x0E, 'mode': 'R/W', 'hbit': 14, 'lbit': 0, 'val': 0}, + 'RX_CDR_PHASE_ACC': {'addr': 0x0F, 'mode': 'R/W', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_CDR_SET_ACC_CONFIG': {'addr': 0x10, 'mode': 'R/W', 'hbit': 1, 'lbit': 0, 'val': 0}, + 'RX_CDR_FORCE_LOCK': {'addr': 0x10, 'mode': 'R/W', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'RX_ALIGN_MCOMMA_VALUE': {'addr': 0x11, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0x283}, + 'RX_MCOMMA_ALIGN_OVR': {'addr': 0x11, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0}, + 'RX_MCOMMA_ALIGN': {'addr': 0x11, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'RX_ALIGN_PCOMMA_VALUE': {'addr': 0x12, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0x17C}, + 'RX_PCOMMA_ALIGN_OVR': {'addr': 0x12, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0}, + 'RX_PCOMMA_ALIGN': {'addr': 0x12, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'RX_ALIGN_COMMA_WORD': {'addr': 0x12, 'mode': 'R/W', 'hbit': 13, 'lbit': 12, 'val': 0}, + 'RX_ALIGN_COMMA_ENABLE': {'addr': 0x13, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0x3FF}, + 'RX_SLIDE_MODE': {'addr': 0x13, 'mode': 'R/W', 'hbit': 11, 'lbit': 10, 'val': 0}, + 'RX_COMMA_DETECT_EN_OVR': {'addr': 0x13, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0}, + 'RX_COMMA_DETECT_EN': {'addr': 0x13, 'mode': 'R/W', 'hbit': 13, 'lbit': 13, 'val': 0}, + 'RX_SLIDE[0]': {'addr': 0x13, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0}, + 'RX_SLIDE[1]': {'addr': 0x13, 'mode': 'W/C', 'hbit': 15, 'lbit': 15, 'val': 0}, + 'RX_EYE_MEAS_EN': {'addr': 0x14, 'mode': 'W/C', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_CFG': {'addr': 0x14, 'mode': 'R/W', 'hbit': 15, 'lbit': 1, 'val': 0}, + 'RX_MON_PH_OFFSET': {'addr': 0x15, 'mode': 'R/W', 'hbit': 5, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_CORRECT_11S': {'addr': 0x16, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_WRONG_11S': {'addr': 0x17, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_CORRECT_00S': {'addr': 0x18, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_WRONG_00S': {'addr': 0x19, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_CORRECT_001S': {'addr': 0x1A, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_WRONG_001S': {'addr': 0x1B, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_CORRECT_110S': {'addr': 0x1C, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EYE_MEAS_WRONG_110S': {'addr': 0x1D, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_EI_BIAS': {'addr': 0x1E, 'mode': 'R/W', 'hbit': 3, 'lbit': 0, 'val': 4}, + 'RX_EI_BW_SEL': {'addr': 0x1E, 'mode': 'R/W', 'hbit': 7, 'lbit': 4, 'val': 4}, + 'RX_EN_EI_DETECTOR_OVR': {'addr': 0x1E, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'RX_EN_EI_DETECTOR': {'addr': 0x1E, 'mode': 'R/W', 'hbit': 9, 'lbit': 9, 'val': 0}, + 'RX_EI_EN': {'addr': 0x1E, 'mode': 'R', 'hbit': 10, 'lbit': 10, 'val': 0}, + 'RX_PRBS_ERR_CNT': {'addr': 0x1F, 'mode': 'R', 'hbit': 14, 'lbit': 0, 'val': 0}, + 'RX_PRBS_LOCKED': {'addr': 0x1F, 'mode': 'R', 'hbit': 15, 'lbit': 15, 'val': 0}, + 'RX_DATA_SEL': {'addr': 0x20, 'mode': 'R/W', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'RX_DATA[15:0]': {'addr': 0x20, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_DATA[31:16]': {'addr': 0x21, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_DATA[47:32]': {'addr': 0x22, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_DATA[63:48]': {'addr': 0x23, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_DATA[79:64]': {'addr': 0x24, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'RX_BUF_BYPASS': {'addr': 0x25, 'mode': 'R/W', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'RX_CLKCOR_USE': {'addr': 0x25, 'mode': 'R/W', 'hbit': 1, 'lbit': 1, 'val': 0}, + 'RX_CLKCOR_MIN_LAT': {'addr': 0x25, 'mode': 'R/W', 'hbit': 7, 'lbit': 2, 'val': 32}, + 'RX_CLKCOR_MAX_LAT': {'addr': 0x25, 'mode': 'R/W', 'hbit': 13, 'lbit': 8, 'val': 39}, + 'RX_CLKCOR_SEQ_1_0': {'addr': 0x26, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0x1F7}, + 'RX_CLKCOR_SEQ_1_1': {'addr': 0x27, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0x1F7}, + 'RX_CLKCOR_SEQ_1_2': {'addr': 0x28, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0x1F7}, + 'RX_CLKCOR_SEQ_1_3': {'addr': 0x29, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0x1F7}, + 'RX_PMA_LOOPBACK': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'RX_PCS_LOOPBACK': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 1, 'lbit': 1, 'val': 0}, + 'RX_DATAPATH_SEL': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 3, 'lbit': 2, 'val': 3}, + 'RX_PRBS_OVR': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 4, 'lbit': 4, 'val': 0}, + 'RX_PRBS_SEL': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 7, 'lbit': 5, 'val': 0}, + 'RX_LOOPBACK_OVR': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'RX_PRBS_CNT_RESET': {'addr': 0x2A, 'mode': 'W/C', 'hbit': 9, 'lbit': 9, 'val': 0}, + 'RX_POWER_DOWN_OVR': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0}, + 'RX_POWER_DOWN_N': {'addr': 0x2A, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'RX_PRESENT': {'addr': 0x2A, 'mode': 'R', 'hbit': 12, 'lbit': 12, 'val': 0}, + 'RX_DETECT_DONE': {'addr': 0x2A, 'mode': 'R', 'hbit': 13, 'lbit': 13, 'val': 0}, + 'RX_BUF_ERR': {'addr': 0x2A, 'mode': 'R', 'hbit': 14, 'lbit': 14, 'val': 0}, + 'RX_RESET_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'RX_RESET': {'addr': 0x2B, 'mode': 'W/C', 'hbit': 1, 'lbit': 1, 'val': 0}, + 'RX_PMA_RESET_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'RX_PMA_RESET': {'addr': 0x2B, 'mode': 'W/C', 'hbit': 3, 'lbit': 3, 'val': 0}, + 'RX_EQA_RESET_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 4, 'lbit': 4, 'val': 0}, + 'RX_EQA_RESET': {'addr': 0x2B, 'mode': 'W/C', 'hbit': 5, 'lbit': 5, 'val': 0}, + 'RX_CDR_RESET_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 6, 'lbit': 6, 'val': 0}, + 'RX_CDR_RESET': {'addr': 0x2B, 'mode': 'W/C', 'hbit': 7, 'lbit': 7, 'val': 0}, + 'RX_PCS_RESET_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'RX_PCS_RESET': {'addr': 0x2B, 'mode': 'W/C', 'hbit': 9, 'lbit': 9, 'val': 0}, + 'RX_BUF_RESET_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0}, + 'RX_BUF_RESET': {'addr': 0x2B, 'mode': 'W/C', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'RX_POLARITY_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0}, + 'RX_POLARITY': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 13, 'lbit': 13, 'val': 0}, + 'RX_8B10B_EN_OVR': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0}, + 'RX_8B10B_EN': {'addr': 0x2B, 'mode': 'R/W', 'hbit': 15, 'lbit': 15, 'val': 0}, + 'RX_8B10B_BYPASS': {'addr': 0x2C, 'mode': 'R/W', 'hbit': 7, 'lbit': 0, 'val': 0}, + 'RX_BYTE_IS_ALIGNED': {'addr': 0x2C, 'mode': 'R', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'RX_BYTE_REALIGN': {'addr': 0x2C, 'mode': 'R/C', 'hbit': 9, 'lbit': 9, 'val': 0}, + 'RX_RESET_DONE': {'addr': 0x2C, 'mode': 'R', 'hbit': 10, 'lbit': 10, 'val': 0}, + #'RX_DBG_EN': {'addr': 0x2D, 'mode': 'W/C', 'hbit': 0, 'lbit': 0, 'val': 0}, + #'RX_DBG_SEL': {'addr': 0x2D, 'mode': 'R/W', 'hbit': 4, 'lbit': 1, 'val': 0}, + #'RX_DBG_MODE': {'addr': 0x2D, 'mode': 'R/W', 'hbit': 5, 'lbit': 5, 'val': 0}, + #'RX_DBG_SRAM_DELAY': {'addr': 0x2D, 'mode': 'R/W', 'hbit': 11, 'lbit': 6, 'val': 5}, + #'RX_DBG_ADDR': {'addr': 0x2E, 'mode': 'R/W', 'hbit': 9, 'lbit': 0, 'val': 0}, + #'RX_DBG_RE': {'addr': 0x2E, 'mode': 'W/C', 'hbit': 10, 'lbit': 10, 'val': 0}, + #'RX_DBG_WE': {'addr': 0x2E, 'mode': 'W/C', 'hbit': 11, 'lbit': 11, 'val': 0}, + #'RX_DBG_DATA[3:0]': {'addr': 0x2E, 'mode': 'R/W', 'hbit': 15, 'lbit': 12, 'val': 0}, + #'RX_DBG_DATA[19:4]': {'addr': 0x2F, 'mode': 'R/W', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'TX_SEL_PRE': {'addr': 0x30, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_SEL_POST': {'addr': 0x30, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 0}, + 'TX_AMP': {'addr': 0x30, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 15}, + 'TX_BRANCH_EN_PRE': {'addr': 0x31, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_BRANCH_EN_MAIN': {'addr': 0x31, 'mode': 'R/W', 'hbit': 10, 'lbit': 5, 'val': 0x3F}, + 'TX_BRANCH_EN_POST': {'addr': 0x31, 'mode': 'R/W', 'hbit': 15, 'lbit': 11, 'val': 0}, + 'TX_TAIL_CASCODE': {'addr': 0x32, 'mode': 'R/W', 'hbit': 2, 'lbit': 0, 'val': 4}, + 'TX_DC_ENABLE': {'addr': 0x32, 'mode': 'R/W', 'hbit': 9, 'lbit': 3, 'val': 63}, + 'TX_DC_OFFSET': {'addr': 0x32, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 8}, + 'TX_CM_RAISE': {'addr': 0x33, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_CM_THRESHOLD_0': {'addr': 0x33, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 14}, + 'TX_CM_THRESHOLD_1': {'addr': 0x33, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 16}, + 'TX_SEL_PRE_EI': {'addr': 0x34, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_SEL_POST_EI': {'addr': 0x34, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 0}, + 'TX_AMP_EI': {'addr': 0x34, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 15}, + 'TX_BRANCH_EN_PRE_EI': {'addr': 0x35, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_BRANCH_EN_MAIN_EI': {'addr': 0x35, 'mode': 'R/W', 'hbit': 10, 'lbit': 5, 'val': 0x3F}, + 'TX_BRANCH_EN_POST_EI': {'addr': 0x35, 'mode': 'R/W', 'hbit': 15, 'lbit': 11, 'val': 0}, + 'TX_TAIL_CASCODE_EI': {'addr': 0x36, 'mode': 'R/W', 'hbit': 2, 'lbit': 0, 'val': 4}, + 'TX_DC_ENABLE_EI': {'addr': 0x36, 'mode': 'R/W', 'hbit': 9, 'lbit': 3, 'val': 63}, + 'TX_DC_OFFSET_EI': {'addr': 0x36, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 0}, + 'TX_CM_RAISE_EI': {'addr': 0x37, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_CM_THRESHOLD_0_EI': {'addr': 0x37, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 14}, + 'TX_CM_THRESHOLD_1_EI': {'addr': 0x37, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 16}, + 'TX_SEL_PRE_RXDET': {'addr': 0x38, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_SEL_POST_RXDET': {'addr': 0x38, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 0}, + 'TX_AMP_RXDET': {'addr': 0x38, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 15}, + 'TX_BRANCH_EN_PRE_RXDET': {'addr': 0x39, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_BRANCH_EN_MAIN_RXDET': {'addr': 0x39, 'mode': 'R/W', 'hbit': 10, 'lbit': 5, 'val': 0x3F}, + 'TX_BRANCH_EN_POST_RXDET': {'addr': 0x39, 'mode': 'R/W', 'hbit': 15, 'lbit': 11, 'val': 0}, + 'TX_TAIL_CASCODE_RXDET': {'addr': 0x3A, 'mode': 'R/W', 'hbit': 2, 'lbit': 0, 'val': 4}, + 'TX_DC_ENABLE_RXDET': {'addr': 0x3A, 'mode': 'R/W', 'hbit': 9, 'lbit': 3, 'val': 63}, + 'TX_DC_OFFSET_RXDET': {'addr': 0x3A, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 0}, + 'TX_CM_RAISE_RXDET': {'addr': 0x3B, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_CM_THRESHOLD_0_RXDET': {'addr': 0x3B, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 14}, + 'TX_CM_THRESHOLD_1_RXDET': {'addr': 0x3B, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 16}, + 'TX_CALIB_EN': {'addr': 0x3C, 'mode': 'W/C', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'TX_CALIB_DONE': {'addr': 0x3C, 'mode': 'R', 'hbit': 1, 'lbit': 1, 'val': 1}, + 'TX_CALIB_OVR': {'addr': 0x3C, 'mode': 'R/W', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'TX_CALIB_VAL': {'addr': 0x3C, 'mode': 'R/W', 'hbit': 6, 'lbit': 3, 'val': 0}, + 'TX_CALIB_CAL': {'addr': 0x3C, 'mode': 'R', 'hbit': 10, 'lbit': 7, 'val': 0}, + 'TX_CM_REG_KI': {'addr': 0x3D, 'mode': 'R/W', 'hbit': 7, 'lbit': 0, 'val': 0x80}, + 'TX_CM_SAR_EN': {'addr': 0x3D, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'TX_CM_REG_EN': {'addr': 0x3D, 'mode': 'R/W', 'hbit': 9, 'lbit': 9, 'val': 1}, + 'TX_CM_SAR_RESULT_0': {'addr': 0x3E, 'mode': 'R', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'TX_CM_SAR_RESULT_1': {'addr': 0x3E, 'mode': 'R', 'hbit': 9, 'lbit': 5, 'val': 0}, + 'TX_PMA_RESET_TIME': {'addr': 0x3F, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 3}, + 'TX_PCS_RESET_TIME': {'addr': 0x3F, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 3}, + 'TX_PCS_RESET_OVR': {'addr': 0x3F, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0}, + 'TX_PCS_RESET': {'addr': 0x3F, 'mode': 'W/C', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'TX_PMA_RESET_OVR': {'addr': 0x3F, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0}, + 'TX_PMA_RESET': {'addr': 0x3F, 'mode': 'W/C', 'hbit': 13, 'lbit': 13, 'val': 0}, + 'TX_RESET_OVR': {'addr': 0x3F, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 0}, + 'TX_RESET': {'addr': 0x3F, 'mode': 'W/C', 'hbit': 15, 'lbit': 15, 'val': 0}, + 'TX_PMA_LOOPBACK': {'addr': 0x40, 'mode': 'R/W', 'hbit': 1, 'lbit': 0, 'val': 0}, + 'TX_PCS_LOOPBACK': {'addr': 0x40, 'mode': 'R/W', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'TX_DATAPATH_SEL': {'addr': 0x40, 'mode': 'R/W', 'hbit': 4, 'lbit': 3, 'val': 3}, + 'TX_PRBS_OVR': {'addr': 0x40, 'mode': 'R/W', 'hbit': 5, 'lbit': 5, 'val': 0}, + 'TX_PRBS_SEL': {'addr': 0x40, 'mode': 'R/W', 'hbit': 8, 'lbit': 6, 'val': 0}, + 'TX_PRBS_FORCE_ERR': {'addr': 0x40, 'mode': 'W/C', 'hbit': 9, 'lbit': 9, 'val': 0}, + 'TX_LOOPBACK_OVR': {'addr': 0x40, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 0}, + 'TX_POWER_DOWN_OVR': {'addr': 0x40, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'TX_POWER_DOWN_N': {'addr': 0x40, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 0}, + 'TX_ELEC_IDLE_OVR': {'addr': 0x41, 'mode': 'R/W', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'TX_ELEC_IDLE': {'addr': 0x41, 'mode': 'R/W', 'hbit': 1, 'lbit': 1, 'val': 0}, + 'TX_DETECT_RX_OVR': {'addr': 0x41, 'mode': 'R/W', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'TX_DETECT_RX': {'addr': 0x41, 'mode': 'R/W', 'hbit': 3, 'lbit': 3, 'val': 0}, + 'TX_POLARITY_OVR': {'addr': 0x41, 'mode': 'R/W', 'hbit': 4, 'lbit': 4, 'val': 0}, + 'TX_POLARITY': {'addr': 0x41, 'mode': 'R/W', 'hbit': 5, 'lbit': 5, 'val': 0}, + 'TX_8B10B_EN_OVR': {'addr': 0x41, 'mode': 'R/W', 'hbit': 6, 'lbit': 6, 'val': 0}, + 'TX_8B10B_EN': {'addr': 0x41, 'mode': 'R/W', 'hbit': 7, 'lbit': 7, 'val': 0}, + 'TX_DATA_OVR': {'addr': 0x41, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'TX_DATA_CNT': {'addr': 0x41, 'mode': 'R/W', 'hbit': 11, 'lbit': 9, 'val': 0}, + 'TX_DATA_VALID': {'addr': 0x41, 'mode': 'W/C', 'hbit': 12, 'lbit': 12, 'val': 0}, + 'TX_BUF_ERR': {'addr': 0x41, 'mode': 'R', 'hbit': 13, 'lbit': 13, 'val': 0}, + 'TX_RESET_DONE': {'addr': 0x41, 'mode': 'R', 'hbit': 14, 'lbit': 14, 'val': 0}, + 'TX_DATA': {'addr': 0x42, 'mode': 'R/W', 'hbit': 15, 'lbit': 0, 'val': 0}, + # 0x43..0x4F unused + 'PLL_EN_ADPLL_CTRL': {'addr': 0x50, 'mode': 'R/W', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'PLL_CONFIG_SEL': {'addr': 0x50, 'mode': 'R/W', 'hbit': 1, 'lbit': 1, 'val': 1}, + 'PLL_SET_OP_LOCK': {'addr': 0x50, 'mode': 'R/W', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'PLL_ENFORCE_LOCK': {'addr': 0x50, 'mode': 'R/W', 'hbit': 3, 'lbit': 3, 'val': 0}, + 'PLL_DISABLE_LOCK': {'addr': 0x50, 'mode': 'R/W', 'hbit': 4, 'lbit': 4, 'val': 0}, + 'PLL_LOCK_WINDOW': {'addr': 0x50, 'mode': 'R/W', 'hbit': 5, 'lbit': 5, 'val': 1}, + 'PLL_FAST_LOCK': {'addr': 0x50, 'mode': 'R/W', 'hbit': 6, 'lbit': 6, 'val': 1}, + 'PLL_SYNC_BYPASS': {'addr': 0x50, 'mode': 'R/W', 'hbit': 7, 'lbit': 7, 'val': 0}, + 'PLL_PFD_SELECT': {'addr': 0x50, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'PLL_REF_BYPASS': {'addr': 0x50, 'mode': 'R/W', 'hbit': 9, 'lbit': 9, 'val': 0}, + 'PLL_REF_SEL': {'addr': 0x50, 'mode': 'R/W', 'hbit': 10, 'lbit': 10, 'val': 1}, + 'PLL_REF_RTERM': {'addr': 0x50, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 1}, + 'PLL_FCNTRL': {'addr': 0x51, 'mode': 'R/W', 'hbit': 5, 'lbit': 0, 'val': 58}, + 'PLL_MAIN_DIVSEL': {'addr': 0x51, 'mode': 'R/W', 'hbit': 11, 'lbit': 6, 'val': 27}, + 'PLL_OUT_DIVSEL': {'addr': 0x51, 'mode': 'R/W', 'hbit': 13, 'lbit': 12, 'val': 0}, + 'PLL_CI': {'addr': 0x52, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 3}, + 'PLL_CP': {'addr': 0x52, 'mode': 'R/W', 'hbit': 14, 'lbit': 5, 'val': 80}, + 'PLL_AO': {'addr': 0x53, 'mode': 'R/W', 'hbit': 3, 'lbit': 0, 'val': 0}, + 'PLL_SCAP': {'addr': 0x53, 'mode': 'R/W', 'hbit': 6, 'lbit': 4, 'val': 0}, + 'PLL_FILTER_SHIFT': {'addr': 0x53, 'mode': 'R/W', 'hbit': 8, 'lbit': 7, 'val': 2}, + 'PLL_SAR_LIMIT': {'addr': 0x53, 'mode': 'R/W', 'hbit': 11, 'lbit': 9, 'val': 2}, + 'PLL_FT': {'addr': 0x54, 'mode': 'R/W', 'hbit': 10, 'lbit': 0, 'val': 512}, + 'PLL_OPEN_LOOP': {'addr': 0x54, 'mode': 'R/W', 'hbit': 11, 'lbit': 11, 'val': 0}, + 'PLL_SCAP_AUTO_CAL': {'addr': 0x54, 'mode': 'R/W', 'hbit': 12, 'lbit': 12, 'val': 1}, + 'PLL_LOCKED': {'addr': 0x55, 'mode': 'R', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'PLL_CAP_FT_OF': {'addr': 0x55, 'mode': 'R', 'hbit': 1, 'lbit': 1, 'val': 0}, + 'PLL_CAP_FT_UF': {'addr': 0x55, 'mode': 'R', 'hbit': 2, 'lbit': 2, 'val': 0}, + 'PLL_CAP_FT': {'addr': 0x55, 'mode': 'R', 'hbit': 12, 'lbit': 3, 'val': 0}, + 'PLL_CAP_STATE': {'addr': 0x55, 'mode': 'R', 'hbit': 14, 'lbit': 13, 'val': 0}, + 'PLL_SYNC_VALUE': {'addr': 0x56, 'mode': 'R', 'hbit': 7, 'lbit': 0, 'val': 0}, + 'PLL_BISC_MODE': {'addr': 0x57, 'mode': 'R/W', 'hbit': 2, 'lbit': 0, 'val': 4}, + 'PLL_BISC_TIMER_MAX': {'addr': 0x57, 'mode': 'R/W', 'hbit': 6, 'lbit': 3, 'val': 15}, + 'PLL_BISC_OPT_DET_IND': {'addr': 0x57, 'mode': 'R/W', 'hbit': 7, 'lbit': 7, 'val': 0}, + 'PLL_BISC_PFD_SEL': {'addr': 0x57, 'mode': 'R/W', 'hbit': 8, 'lbit': 8, 'val': 0}, + 'PLL_BISC_DLY_DIR': {'addr': 0x57, 'mode': 'R/W', 'hbit': 9, 'lbit': 9, 'val': 0}, + 'PLL_BISC_COR_DLY': {'addr': 0x57, 'mode': 'R/W', 'hbit': 12, 'lbit': 10, 'val': 1}, + 'PLL_BISC_CAL_SIGN': {'addr': 0x57, 'mode': 'R/W', 'hbit': 13, 'lbit': 13, 'val': 0}, + 'PLL_BISC_CAL_AUTO': {'addr': 0x57, 'mode': 'R/W', 'hbit': 14, 'lbit': 14, 'val': 1}, + 'PLL_BISC_CP_MIN': {'addr': 0x58, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 4}, + 'PLL_BISC_CP_MAX': {'addr': 0x58, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 18}, + 'PLL_BISC_CP_START': {'addr': 0x58, 'mode': 'R/W', 'hbit': 14, 'lbit': 10, 'val': 12}, + 'PLL_BISC_DLY_PFD_MON_REF': {'addr': 0x59, 'mode': 'R/W', 'hbit': 4, 'lbit': 0, 'val': 0}, + 'PLL_BISC_DLY_PFD_MON_DIV': {'addr': 0x59, 'mode': 'R/W', 'hbit': 9, 'lbit': 5, 'val': 2}, + 'PLL_BISC_TIMER_DONE': {'addr': 0x5A, 'mode': 'R', 'hbit': 0, 'lbit': 0, 'val': 0}, + 'PLL_BISC_CP': {'addr': 0x5A, 'mode': 'R', 'hbit': 7, 'lbit': 1, 'val': 0}, # BISC_RESULT[15:1] + 'PLL_BISC_CO': {'addr': 0x5B, 'mode': 'R', 'hbit': 15, 'lbit': 0, 'val': 0}, + 'SERDES_ENABLE': {'addr': 0x5C, 'mode': 'R/C', 'hbit': 0, 'lbit': 0, 'val': 1}, + 'SERDES_AUTO_INIT': {'addr': 0x5C, 'mode': 'R/C', 'hbit': 1, 'lbit': 1, 'val': 0}, + 'SERDES_TESTMODE': {'addr': 0x5C, 'mode': 'R/C', 'hbit': 2, 'lbit': 2, 'val': 0}, + }) + + ports = { + # name: width + 'TX_DATA_I': 64, + 'TX_RESET_I': 1, + 'TX_PCS_RESET_I': 1, + 'TX_PMA_RESET_I': 1, + 'PLL_RESET_I': 1, + 'TX_POWER_DOWN_N_I': 1, + 'TX_POLARITY_I': 1, + 'TX_PRBS_SEL_I': 3, + 'TX_PRBS_FORCE_ERR_I': 1, + 'TX_8B10B_EN_I': 1, + 'TX_8B10B_BYPASS_I': 8, + 'TX_CHAR_IS_K_I': 8, + 'TX_CHAR_DISPMODE_I': 8, + 'TX_CHAR_DISPVAL_I': 8, + 'TX_ELEC_IDLE_I': 1, + 'TX_DETECT_RX_I': 1, + 'LOOPBACK_I': 3, + 'TX_CLK_I': 1, + 'RX_CLK_I': 1, + 'RX_RESET_I': 1, + 'RX_PMA_RESET_I': 1, + 'RX_EQA_RESET_I': 1, + 'RX_CDR_RESET_I': 1, + 'RX_PCS_RESET_I': 1, + 'RX_BUF_RESET_I': 1, + 'RX_POWER_DOWN_N_I': 1, + 'RX_POLARITY_I': 1, + 'RX_PRBS_SEL_I': 3, + 'RX_PRBS_CNT_RESET_I': 1, + 'RX_8B10B_EN_I': 1, + 'RX_8B10B_BYPASS_I': 8, + 'RX_EN_EI_DETECTOR_I': 1, + 'RX_COMMA_DETECT_EN_I': 1, + 'RX_SLIDE_I': 1, + 'RX_MCOMMA_ALIGN_I': 1, + 'RX_PCOMMA_ALIGN_I': 1, + 'REGFILE_CLK_I': 1, + 'REGFILE_WE_I': 1, + 'REGFILE_EN_I': 1, + 'REGFILE_ADDR_I': 8, + 'REGFILE_DI_I': 16, + 'REGFILE_MASK_I': 16, + 'RX_DATA_O': 64, + 'RX_NOT_IN_TABLE_O': 8, + 'RX_CHAR_IS_COMMA_O': 8, + 'RX_CHAR_IS_K_O': 8, + 'RX_DISP_ERR_O': 8, + 'TX_DETECT_RX_DONE_O': 1, + 'TX_DETECT_RX_PRESENT_O': 1, + 'TX_BUF_ERR_O': 1, + 'TX_RESET_DONE_O': 1, + 'RX_PRBS_ERR_O': 1, + 'RX_BUF_ERR_O': 1, + 'RX_BYTE_IS_ALIGNED_O': 1, + 'RX_BYTE_REALIGN_O': 1, + 'RX_RESET_DONE_O': 1, + 'RX_EI_EN_O': 1, + 'RX_CLK_O': 1, + 'PLL_CLK_O': 1, + 'REGFILE_DO_O': 16, + 'REGFILE_RDY_O': 1 + } + + olclkg = { # open loop clock generator + # fcntrl : N + 0: 1, 1: 2, 2: 3, 3: 3.5, + 4: 3.5, 5: 3.75, 6: 4, 7: 4, + 8: 4.5, 9: 5.25, 10: 5, 11: 5.5, + 12: 5.5, 13: 5.75, 14: 6, 15: 6, + 16: 6, 17: 7, 18: 6, 19: 7, + 20: 7, 21: 7.5, 22: 8, 23: 8, + 24: 9, 25: 10.5, 26: 10, 27: 11, + 28: 11, 29: 11.5, 30: 12, 31: 12, + 32: 9, 33: 10.5, 34: 9, 35: 10.5, + 36: 10.5, 37: 11.25, 38: 12, 39: 12, + 40: 13.5, 41: 15.75, 42: 15, 43: 16.5, + 44: 16.5, 45: 17.25, 46: 18, 47: 18, + 48: 12, 49: 14, 50: 12, 51: 14, + 52: 14, 53: 15.75, 54: 16.5, 55: 16.5, + 56: 18, 57: 21, 58: 20, 59: 22, + 60: 22, 61: 23, 62: 24, 63: 24, + } + + # keywords for conditional coloring + pos_cond = ["DONE", "PRESENT", "LOCKED", "IS_ALIGNED", "EN_ADPLL_CTRL", "CONFIG_SEL", "SERDES_ENABLE"] + neg_cond = ["ERR", "DOWN", "TESTMODE"] + ovr_cond = ["OVR"] + + # PFDAC settings + ADPLL_PFDAC_TIMER = 12 + ADPLL_PFDAC_COR_DLY = 1 + ADPLL_PFDAC_CP_MIN = 6 + ADPLL_PFDAC_CP_MAX = 30 + ADPLL_PFDAC_CP_START = 6 + ADPLL_PFDAC_CAL_SIGN = 1 + ADPLL_PFDAC_AUTO_CAL = 1 + + # Thread-safe lock for updating values + param_lock = threading.Lock() + + def __init__(self, args, jtag, hwinit): + if hwinit: + self._jtag = jtag + self._board = args.board + if self._jtag is not None: + self.configure() + + def configure(self): + if self._board == Boards_e[0]: # auto + self._jtag.configure(FindAndFormatFtdiAddr(0)) + elif self._board == Boards_e[1]: # pgm + self._jtag.configure('ftdi://ftdi:232h/1') + elif self._board == Boards_e[2]: # evb + self._jtag.configure('ftdi://ftdi:2232h/1') + + self._jtag.reset() + self._tool = JtagTool(self._jtag) + + def rd_id(self): + self._tool.idcode() + + def wr_cfg(self, bitfile): + self._tool.wr_cfg(bitfile) + + def gen_module_vlog(self, filename): + print(f'Generate verilog template: {filename}') + with open(filename, 'w') as file: + file.write('// CC_SERDES instance generator\n') + file.write(f'// generated: {datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")}\n') + file.write('\n') + file.write('CC_SERDES #(\n') + for idx, (param, data) in enumerate(self.regfile.fields.items()): + end = '' if idx == len(self.regfile.fields.items())-1 else ',' + if data['mode'] != 'R': + width = data['hbit']-data['lbit']+1 + file.write(f' .{param}({width}\'h{data['val']:X}){end}\n') + file.write(') i_cc_serdes (\n') + for idx, (port, width) in enumerate(self.ports.items()): + end = '' if idx == len(self.ports.items())-1 else ',' + if port.endswith('_I'): + file.write(f' .{port}({width}\'h{0:X}){end}\n') + else: # port.endswith('_O'): + file.write(f' .{port}(){end}\n') + file.write(');\n') + + def gen_module_vhdl(self, filename): + print(f'Generate VHDL template: {filename}') + with open(filename, 'w') as file: + file.write('-- CC_SERDES instance generator\n') + file.write(f'-- generated: {datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")}\n') + # component + file.write('\n') + file.write('component CC_SERDES is\n') + file.write('generic (\n') + for idx, (param, data) in enumerate(self.regfile.fields.items()): + end = '' if (idx == len(self.regfile.fields.items())-1) else ';' + if data['mode'] != 'R': + hbit = data['hbit']-data['lbit'] + file.write(f' {param} : bit_vector({hbit} downto 0){end}\n') + file.write(');\n') + file.write('port (\n') + for idx, (port, width) in enumerate(self.ports.items()): + end = '' if idx == len(self.ports.items())-1 else ';' + if port.endswith('_I'): + if width > 1: + file.write(f' {port} : in std_logic_vector({width-1} downto 0){end}\n') + else: + file.write(f' {port} : in std_logic{end}\n') + else: # port.endswith('_O'): + if width > 1: + file.write(f' {port} : out std_logic_vector({width-1} downto 0){end}\n') + else: + file.write(f' {port} : out std_logic{end}\n') + file.write(');\n') + file.write('end component;\n') + # instance + file.write('\n') + file.write('i_cc_serdes: CC_SERDES\n') + file.write('generic map (\n') + for idx, (param, data) in enumerate(self.regfile.fields.items()): + end = '' if (idx == len(self.regfile.fields.items())-1) else ',' + if data['mode'] != 'R': + width = data['hbit']-data['lbit']+1 + file.write(f' {param} => {width}X"{data['val']:X}"{end}\n') + file.write(')\n') + file.write('port map (\n') + for idx, (port, width) in enumerate(self.ports.items()): + end = '' if idx == len(self.ports.items())-1 else ',' + if port.endswith('_I'): + if width > 1: + file.write(f' {port} => (others => \'0\'){end}\n') + else: + file.write(f' {port} => \'{0}\'{end}\n') + else: # port.endswith('_O'): + file.write(f' {port} => open{end}\n') + file.write(');\n') + + def fprint(self, key, value, line): + if any(cond in key for cond in self.pos_cond) and int(value) != 0: + print(bcolors.OK + line + bcolors.RESET) + elif any(cond in key for cond in self.pos_cond) and int(value) == 0: + print(bcolors.WARN + line + bcolors.RESET) + elif any(cond in key for cond in self.neg_cond) and (int(value) < 1 if key.endswith('_N') else int(value) > 0): + print(bcolors.FAIL + line + bcolors.RESET) + elif any(cond in key for cond in self.ovr_cond) and int(value) > 0: + print(bcolors.OVR + line + bcolors.RESET) + else: + print(line) + + def rd_regfile(self, addr) -> int: + self._tool.wr_serdes_regfile(addr=addr, data=0, mask=0, wren=0) + return self._tool.rd_serdes_regfile() + + def wr_regfile(self, addr, data, mask): + self._tool.wr_serdes_regfile(addr=addr, data=data, mask=mask, wren=1) + self._tool.rd_serdes_regfile() + + def rd_regfile_rx(self, verbose=0): + for addr in range(0x00, 0x30): + word = self.rd_regfile(addr) + if verbose == 1: + print(f'{addr:02X}: 0x{int(word):04X}') + elif verbose == 2: + filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr} + for (key, value) in filtered_entries.items(): + v = word[value['lbit']:value['hbit']+1] + line = f'{key:24} {int(v):4X}\'h {int(v):6}\'d' + self.fprint(key, v, line) + + def rd_regfile_rx_data(self): + rxd_80bit = BitSequence() + for addr in range(0x20, 0x25): + rxd_80bit += self.rd_regfile(addr) + rxd_64bit = rxd_80bit[0:7+1] + rxd_80bit[10:17+1] + rxd_80bit[20:27+1] + rxd_80bit[30:37+1] + rxd_80bit[40:47+1] + rxd_80bit[50:57+1] + rxd_80bit[60:67+1] + rxd_80bit[70:77+1] + return rxd_64bit, rxd_80bit + + def print_regfile_rx_data(self, verbose=0): + rx_data_80bit = 0 + word_idx = 0 + for addr in range(0x20, 0x25): + word = self.rd_regfile(addr) + if verbose == 1: + print(f'{addr:02X}: 0x{int(word):04X}') + rx_fields = { + key: field for key, field in self.regfile.fields.items() + if field['addr'] == addr and key.startswith('RX_DATA[') + } + for field_name, field_info in rx_fields.items(): + # Extract the relevant bits from the word + bit_slice = word[field_info['lbit']:field_info['hbit'] + 1] + rx_data_80bit |= int(bit_slice) << (16 * word_idx) + word_idx += 1 + + if verbose == 2: + print(f'{"RX_DATA[79:0]":24} {rx_data_80bit:020X}\'h') + + # Convert to 64-bit format by packing every 10 bits into bytes + rx_data_64bit = 0 + byte_position = 0 + for bit_offset in range(0, 80, 10): + byte_value = (rx_data_80bit >> bit_offset) & 0xFF + rx_data_64bit |= byte_value << (byte_position * 8) + byte_position += 1 + + if verbose == 2: + print(f'{"RX_DATA[63:0]":24} {rx_data_64bit:016X}\'h') + + return rx_data_64bit, rx_data_80bit + + def wr_regfile_tx_data(self, data): + self.wr_regfile(addr=0x41, data=0x1000, mask=0x1F00) # TX_DATA_OVR=1, TX_DATA_CNT=0, TX_DATA_VALID=0 + for i in range(5): + self.wr_regfile(addr=0x42, data=(data >> 16*i) & 0xFFFF, mask=0xFFFF) # auto inc + self.wr_regfile(addr=0x41, data=0x1B00, mask=0x1F00) # TX_DATA_OVR=1, TX_DATA_CNT=5, TX_DATA_VALID=1 + + def rd_regfile_tx(self, verbose=0): + for addr in range(0x30, 0x43): # 0x43..0x4F unused + word = self.rd_regfile(addr) + if verbose == 1: + print(f'{addr:02X}: 0x{int(word):04X}') + elif verbose == 2: + filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr} + for (key, value) in filtered_entries.items(): + v = word[value['lbit']:value['hbit']+1] + line = f'{key:24} {int(v):4X}\'h {int(v):6}\'d' + self.fprint(key, v, line) + + def rd_regfile_pll(self, verbose=0): + for addr in range(0x50, 0x5D): + word = self.rd_regfile(addr) + if verbose == 1: + print(f'{addr:02X}: 0x{int(word):04X}') + elif verbose == 2: + filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr} + for (key, value) in filtered_entries.items(): + v = word[value['lbit']:value['hbit']+1] + line = f'{key:24} {int(v):4X}\'h {int(v):6}\'d' + self.fprint(key, v, line) + + def rd_regfile_pll_div_settings(self): + word = self.rd_regfile(addr=0x51) + FCNTRL = word[0:5+1] + MAIN_DIVSEL = word[6:11+1] + OUT_DIVSEL = word[12:13+1] + n1 = MAIN_DIVSEL[2] + n2 = MAIN_DIVSEL[0:1+1] + n3 = MAIN_DIVSEL[3:4+1] + return n1, n2, n3, OUT_DIVSEL + + def rd_regfile_pll_status(self): + return self.rd_regfile(addr=0x55) + self.rd_regfile(addr=0x56) + + def rd_regfile_pll_bisc_status(self): + return self.rd_regfile(addr=0x5A) + self.rd_regfile(addr=0x5B) + + def reset_serdes_tx(self): + print('INFO: Resetting SerDes TX') + + word = self.rd_regfile(addr=0x5C) + if (word[0] != 1 or word[2] != 1): + print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}') + return + + # TX reset + self.wr_regfile(addr=0x3F, data=0xC000, mask=0xC000) # TX_RESET_OVR=1, TX_RESET=1 + self.wr_regfile(addr=0x3F, data=0x0000, mask=0xC000) # TX_RESET_OVR=0, TX_RESET=0 + word = self.rd_regfile(addr=0x41) + timeout = 5 + while timeout > 0: + if (int(word[14]) != 1): # TX_RESET_DONE + timeout = timeout - 1 + if timeout == 0: + print(f'ERROR: TX_RESET_DONE timeout') + else: + break + + def set_serdes_datapath(self, mode=80): + if mode == 0 or mode == 20: + self.wr_regfile(addr=0x2A, data=0x0000, mask=0x000C) # RX_DATAPATH_SEL=0 + self.wr_regfile(addr=0x40, data=0x0000, mask=0x0018) # TX_DATAPATH_SEL=0 (16/20) + elif mode == 1 or mode == 40: + datapath_sel = 1 + self.wr_regfile(addr=0x2A, data=0x0001, mask=0x000C) # RX_DATAPATH_SEL=1 + self.wr_regfile(addr=0x40, data=0x0008, mask=0x0018) # TX_DATAPATH_SEL=1 (32/40) + elif mode == 2 or mode == 3 or mode == 80: + datapath_sel = 3 + self.wr_regfile(addr=0x2A, data=0x000C, mask=0x000C) # RX_DATAPATH_SEL=3 + self.wr_regfile(addr=0x40, data=0x0018, mask=0x0018) # TX_DATAPATH_SEL=3 (64/80) + else: + print(f'ERROR: Invalid datapath configruation {mode}') + + def check_serdes_datapath(self, mode): + check = 3 if mode == 80 else 1 if mode == 40 else 0 if mode == 20 else mode + word = self.rd_regfile(addr=0x2A) + if (int(word[2:3+1]) != check): + print(f'ERROR: RX_DATAPATH_SEL != {check} ({int(word[2:3+1]):2X})') + word = self.rd_regfile(addr=0x40) + if (int(word[3:4+1]) != check): + print(f'ERROR: TX_DATAPATH_SEL != {check} ({int(word[3:4+1]):2X})') + + def reset_serdes_rx(self): + print('INFO: Resetting SerDes RX') + + word = self.rd_regfile(addr=0x5C) + if (word[0] != 1 or word[2] != 1): + print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}') + return + + # RX reset + self.wr_regfile(addr=0x2B, data=0x0003, mask=0x0003) # RX_RESET_OVR=1, RX_RESET=1 + self.wr_regfile(addr=0x3F, data=0x0000, mask=0x0003) # RX_RESET_OVR=0, RX_RESET=0 + word = self.rd_regfile(addr=0x2C) + timeout = 5 + while timeout > 0: + if (int(word[10]) != 1): # RX_RESET_DONE + timeout = timeout - 1 + if timeout == 0: + print(f'ERROR: RX_RESET_DONE timeout') + else: + break + + def reset_serdes_trx(self): + self.reset_serdes_tx() + self.reset_serdes_rx() + + def start_serdes_pll(self, n1=1, n2=2, n3=3, outdiv=4, calib=False): + print('INFO: Configuring SerDes ADPLL') + + if (n1 < 1 or n1 > 2): + print(f'ERROR: Main divider N1 is out of range 1..2') + return + if (n2 < 2 or n2 > 5): + print(f'ERROR: Main divider N2 is out of range 2..5') + return + if (n3 < 3 or n3 > 5): + print(f'ERROR: Main divider N3 is out of range 3..5') + return + if (outdiv != 1 and outdiv != 2 and outdiv != 4): + print(f'ERROR: Output divider N3 is limited to 1, 2 or 4') + return + + dco = 1000.0 / SER_CLK_PERIOD_NS * n1 * n2 * n3 + freq = dco / outdiv + print(f'INFO: SerDes ADPLL frequency / data rate is {freq} MHz / {freq*2} Mbit/s') + + status = self.rd_regfile_pll_status() + if (status[0] == 1): + print('INFO: Disabling SerDes ADPLL') + self.wr_regfile(addr=0x50, data=0x0000, mask=0x0001) + + if outdiv == 1: + pll_div = 0x0000 + elif outdiv == 2: + pll_div = 0x1000 + else: + pll_div = 0x3000 + if n2 == 5: + pll_div = (pll_div & ~(0b11 << 6)) | (0b11 << 6) + elif n2 == 4: + pll_div = (pll_div & ~(0b11 << 6)) | (0b10 << 6) + elif n2 == 2: + pll_div = (pll_div & ~(0b11 << 6)) | (0b01 << 6) + if n1 == 2: + pll_div |= (1 << 8) + if n3 == 5: + pll_div = (pll_div & ~(0b11 << 9)) | (0b11 << 9) + elif n3 == 4: + pll_div = (pll_div & ~(0b11 << 9)) | (0b10 << 9) + + print('INFO: Writing SerDes ADPLL divider settings') + self.wr_regfile(addr=0x51, data=pll_div, mask=0x3FC0) + + if (calib): + print('INFO: Stopping SerDes ADPLL self-calibration') + self.wr_regfile(addr=0x57, data=0x0004, mask=0x0007) + self.wr_regfile(addr=0x57, data= + ((self.ADPLL_PFDAC_TIMER & 0x000F) << 3) | + ((self.ADPLL_PFDAC_COR_DLY & 0x0007) << 10) | + ((self.ADPLL_PFDAC_CAL_SIGN & 0x0001) << 13) | + ((self.ADPLL_PFDAC_AUTO_CAL & 0x0001) << 14), + mask=0xFFF8) + self.wr_regfile(addr=0x58, data= + ((self.ADPLL_PFDAC_COR_DLY & 0x001F) << 0) | + ((self.ADPLL_PFDAC_CAL_SIGN & 0x001F) << 5) | + ((self.ADPLL_PFDAC_AUTO_CAL & 0x001F) << 10), + mask=0xFFFF) + + print('INFO: Starting SerDes ADPLL') + self.wr_regfile(addr=0x50, data=0x0002, mask=0x0007) + self.wr_regfile(addr=0x50, data=0x0003, mask=0x0003) + + if (calib): + print('INFO: Starting SerDes ADPLL self-calibration') + self.wr_regfile(addr=0x57, data=0x0004, mask=0x0007) + self.wr_regfile(addr=0x57, data=0x0005, mask=0x0007) # BISC mode B, enable + + timeout = 5 + while timeout > 0: + sleep(0.5) + status = self.rd_regfile_pll_status() + if (status[0] == 0): + timeout = timeout - 1 + print(f'INFO: LCK: {int(status[0]):1d} FTO: {int(status[1]):1d} FTU: {int(status[2]):1d} FT: {int(status[3:12+1]):4d} SY: {int(status[16:23+1]):3d} ST: {int(status[13:14+1]):1d}') + if timeout == 0: + print(f'ERROR: SerDes ADPLL lock timeout') + else: + print(f'INFO: SerDes ADPLL locked') + break + + if (calib): + result = self.rd_regfile_pll_bisc_status() + print(f'INFO: PFDAC result: max reached: {int(result[0]):1d}, ac_result: {int(result[1:17+1]):6d}, CP: {int(result[18:22+1]):2d}') + + print(f'INFO: ADPLL status: LCK: {int(status[0]):1d} FTO: {int(status[1]):1d} FTU: {int(status[2]):1d} FT: {int(status[3:12+1]):4d} SY: {int(status[16:23+1]):3d} ST: {int(status[13:14+1]):1d}') + + def tc_prbs(self, force_err=False): + print(f'INFO: Starting SerDes PRBS testcases') + + word = self.rd_regfile(addr=0x5C) + if (word[0] != 1 or word[2] != 1): + print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}') + return + + # set 80-bit datapath + self.set_serdes_datapath(80) + + self.start_serdes_pll(n1=1, n2=5, n3=5, outdiv=4, calib=True) # 1250 Mbit/s, PFDAC=on + self.reset_serdes_trx() + + # check datapath + self.check_serdes_datapath(80) + + # disable testmode? + self.wr_regfile(addr=0x2A, data=0x0210, mask=0x02F0) # RX_PRBS_OVR=1, RX_PRBS_SEL=0, RX_PRBS_CNT_RESET=1 + + for i in range(0, 2): + prbs = 7 if i == 0 else 15 if i == 1 else 23 if i == 2 else 31 if i == 3 else 0 + print(f'INFO: Setting up PRBS-{prbs}') + + self.wr_regfile(addr=0x40, data=((i+1) << 6) | (1 << 5), mask=0x01E0) # TX_PRBS_OVR=1, TX_PRBS_SEL=i + word = self.rd_regfile(addr=0x40) + #if (word[5] == 1): + # print(f'ERROR: TX PRBS overwrite is not disabled') + if (int(word[6:8+1]) != i+1): + print(f'ERROR: TX PRBS mode is invalid') + + self.wr_regfile(addr=0x2A, data=((i+1) << 5) | (1 << 4), mask=0x00F0) # RX_PRBS_OVR=1, RX_PRBS_SEL=i + word = self.rd_regfile(addr=0x2A) + #if (word[4] == 1): + # print(f'ERROR: RX PRBS overwrite is not disabled') + if (word[9] == 1): + print(f'ERROR: RX_PRBS_CNT_RESET is active') + if (int(word[5:7+1]) != i+1): + print(f'ERROR: RX PRBS mode is invalid') + + # send data + print(f'INFO: Sending data (this might take a while) ...') + n = 10 + for i in range(n): + print(f'INFO: {i}/{n}') + sleep(1) + + word = self.rd_regfile(addr=0x1F) + print(f'INFO: RX_PRBS_LOCKED: {int(word[15]):1d}, RX_PRBS_ERR_CNT: {int(word[0:14+1]):X}') + if (word[15] == 0): + print(f'ERROR: RX PRBS did not lock') + if (int(word[0:14+1]) > 0): + print(f'ERROR: RX PRBS errors detected ({int(word[0:14+1])})') + + if (force_err): + print(f'INFO: Starting error injection') + self.wr_regfile(addr=0x40, data=0x0200, mask=0x0200) # TX_PRBS_FORCE_ERR=1 + word = self.rd_regfile(addr=0x1F) + print(f'INFO: RX_PRBS_LOCKED: {int(word[15]):1d}, RX_PRBS_ERR_CNT: {int(word[0:14+1]):X}') + if (int(word[0:14+1]) == 0): + print(f'ERROR: RX PRBS error detection failed') + + self.wr_regfile(addr=0x2A, data=0x0210, mask=0x02F0) # RX_PRBS_CNT_RESET=1, RX_PRBS_OVR=1, RX_PRBS_SEL=0 + self.wr_regfile(addr=0x40, data=0x0020, mask=0x01E0) # TX_PRBS_OVR=1, TX_PRBS_SEL=0 + return + + def tc_uipattern(self, mode=0): + print(f'INFO: Starting SerDes UI pattern testcase') + + if not mode in [0,2,20,40,80]: + print(f'ERROR: Invalid UI pattern mode ({mode}), must be in [0,2,20,40,80]') + return + + word = self.rd_regfile(addr=0x5C) + if (word[0] != 1 or word[2] != 1): + print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}') + return + + # set datapath if mode in [20,40,80] + self.set_serdes_datapath(mode) + + self.start_serdes_pll(n1=1, n2=2, n3=3, outdiv=4, calib=True) # 300 Mbit/s, PFDAC=on + self.reset_serdes_trx() + + # check datapath + self.check_serdes_datapath(mode) + + # disable testmode? + self.wr_regfile(addr=0x2A, data=0x0210, mask=0x02F0) # RX_PRBS_OVR=1, RX_PRBS_SEL=0, RX_PRBS_CNT_RESET=1 + + print(f'INFO: Setting up {mode} UI square wave') + + i = 5 if mode == 2 else 6 if mode in [20,40,80] else 0 + self.wr_regfile(addr=0x40, data=((i+1) << 6) | (1 << 5), mask=0x01E0) # TX_PRBS_OVR=1, TX_PRBS_SEL=i + word = self.rd_regfile(addr=0x40) + if (int(word[6:8+1]) != i+1): + print(f'ERROR: TX PRBS mode is invalid') + + def tc_eyemeas(self): + print(f'INFO: Starting SerDes eye measurement') + + word = self.rd_regfile(addr=0x5C) + if (word[0] != 1 or word[2] != 1): + print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}') + return + + def tc_loopback(self): + print(f'INFO: Starting SerDes loopback testcases') + + word = self.rd_regfile(addr=0x5C) + if (word[0] != 1 or word[2] != 1): + print(f'ERROR: SerDes not enabled or in testmode. 0x5C=0x{int(word):04X}') + return + + # testcases: + # + # 0: TX PMA (near-end, mode 1: pre-driver), TX_PMA_LOOPBACK=01 or TX_PMA_LOOPBACK=11 + # 1: TX PMA (near-end, mode 2: pad), TX_PMA_LOOPBACK=10, NOTE: requires termination! + # 3: TX PCS (near-end) + for j in [0, 1, 3]: + if (j < 3): + print(f'\nINFO: Enabling TX PMA Loopback (Mode {j:1d})') + else: + print(f'\nINFO: Enabling TX PCS Loopback') + + # TX_LOOPBACK_OVR=1 | TX_PMA_LOOPBACK=(001=pma-drv, 011=pma-drv, 010=pma-pad, 100=pcs) + self.wr_regfile(addr=0x40, data=(0x0400 | (j+1) & 0x7), mask=0x0407) + word = self.rd_regfile(addr=0x40) + if (word[10] == 0): + print(f'ERROR: TX loopback overwrite is not enabled') + if (int(word[0:1+1]) != j+1 and j < 3): + print(f'ERROR: TX PMA loopback is not enabled') + if (word[2] == 0 and j == 3): + print(f'ERROR: TX PCS loopback is not enabled') + + # turn tx driver off + if (j == 1 or j == 3): + self.wr_regfile(addr=0x30, data=0x0000, mask=0x001F) # TODO TX_SEL_PRE=0, TX_SEL_POST=x, TX_AMP=x + self.wr_regfile(addr=0x31, data=0x07E0, mask=0x07E0) # TX_BRANCH_EN_MAIN=63 + word = self.rd_regfile(addr=0x30) + if (int(word[0:4+1]) != 0): + print(f'ERROR: Invalid TX_SEL_PRE driver setting') + word = self.rd_regfile(addr=0x31) + if (int(word[5:10+1]) != 63): + print(f'ERROR: Invalid TX_BRANCH_EN_MAIN setting') + else: + self.wr_regfile(addr=0x30, data=0x0001, mask=0x001F) # TODO TX_SEL_PRE=1, TX_SEL_POST=x, TX_AMP=x + self.wr_regfile(addr=0x31, data=0x0000, mask=0x07E0) # TX_BRANCH_EN_MAIN=0 + word = self.rd_regfile(addr=0x30) + if (int(word[0:4+1]) != 1): + print(f'ERROR: Invalid TX_SEL_PRE driver setting') + word = self.rd_regfile(addr=0x31) + if (int(word[5:10+1]) != 0): + print(f'ERROR: Invalid TX_BRANCH_EN_MAIN setting') + + self.start_serdes_pll(n1=1, n2=5, n3=5, outdiv=4, calib=True) # 1250 Mbit/s, PFDAC=on + self.reset_serdes_trx() + + self.wr_regfile(addr=0x41, data=0x00C0, mask=0x00C0) # TX_8B10B_EN_OVR=1, TX_8B10B_EN=1 + self.wr_regfile(addr=0x2B, data=0xC000, mask=0xC000) # RX_8B10B_EN_OVR=1, RX_8B10B_EN=1 + + # 32-Bit comma alignment test + self.wr_regfile(addr=0x12, data=0x3000, mask=0x3000) # RX_ALIGN_COMMA_WORD=3 (32 bit) + + # NOTE: Please define position of the k-word using the `TX_CHAR_IS_K_I` input: set to 8'h0000_0001 + self.wr_regfile_tx_data(data=0x1284A1284A1284A128BC) # 64'h4A4A4A4A_4A4A4ABC + + self.wr_regfile(addr=0x11, data=0x0C00, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=1 + self.wr_regfile(addr=0x12, data=0x0C00, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=1 + self.wr_regfile(addr=0x13, data=0x3000, mask=0x3000) # RX_COMMA_DETECT_EN_OVR=1, RX_COMMA_DETECT_EN=1 + + print(f'INFO: Sending data (this might take a while) ...') + sleep(2) + + self.wr_regfile(addr=0x11, data=0x0000, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=0 + self.wr_regfile(addr=0x12, data=0x0000, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=0 + + print(f'INFO: Checking 32-Bit comma alignment') + rx_data, _ = self.rd_regfile_rx_data() + align_pos = 0 if int(rx_data[0:7+1]) == 0xBC else 1 + rx_recv = 0x4A4A4A4A4A4A4ABC if align_pos == 0 else 0x4A4A4ABC4A4A4A4A + + if (int(rx_data[0:7+1]) != 0xBC and int(rx_data[32:39+1]) != 0xBC): + print(f'ERROR: Comma is not aligned to 32-Bit boundary') + if (int(rx_data) != rx_recv): + print(f'ERROR: Invalid idle sequence received: RX_DATA[63:0]: {int(rx_data):016X}') + + # 16-Bit comma alignment test + self.reset_serdes_trx() + self.wr_regfile(addr=0x12, data=0x1000, mask=0x3000) # RX_ALIGN_COMMA_WORD=1 (16 bit) + + # NOTE: Please define position of the k-word using the `TX_CHAR_IS_K_I` input: set to 8'h0000_0001 + self.wr_regfile_tx_data(data=0x1284A1284A1284A128BC) # 64'h4A4A4A4A_4A4A4ABC + + self.wr_regfile(addr=0x11, data=0x0C00, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=1 + self.wr_regfile(addr=0x12, data=0x0C00, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=1 + self.wr_regfile(addr=0x13, data=0x3000, mask=0x3000) # RX_COMMA_DETECT_EN_OVR=1, RX_COMMA_DETECT_EN=1 + + print(f'INFO: Sending data (this might take a while) ...') + sleep(2) + + self.wr_regfile(addr=0x11, data=0x0000, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=0 + self.wr_regfile(addr=0x12, data=0x0000, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=0 + + print(f'INFO: Checking 16-Bit comma alignment') + rx_data, _ = self.rd_regfile_rx_data() + align_pos = 0 if int(rx_data[ 0:7+1]) == 0xBC else \ + 1 if int(rx_data[16:23+1]) == 0xBC else \ + 2 if int(rx_data[32:39+1]) == 0xBC else 3 + rx_recv = 0x4A4A4A4A4A4A4ABC if align_pos == 0 else \ + 0x4A4A4A4A4ABC4A4A if align_pos == 1 else \ + 0x4A4A4ABC4A4A4A4A if align_pos == 2 else 0x4ABC4A4A4A4A4A4A + + if (int(rx_data[0:7+1]) != 0xBC and int(rx_data[16:23+1]) != 0xBC and int(rx_data[32:39+1]) != 0xBC and int(rx_data[48:55+1]) != 0xBC): + print(f'ERROR: Comma is not aligned to 16-Bit boundary') + if (int(rx_data) != rx_recv): + print(f'ERROR: Invalid idle sequence received: RX_DATA[63:0]: {int(rx_data):016X}') + + # 8-Bit comma alignment test + self.reset_serdes_trx() + self.wr_regfile(addr=0x12, data=0x0000, mask=0x3000) # RX_ALIGN_COMMA_WORD=0 (8 bit) + + # NOTE: Please define position of the k-word using the `TX_CHAR_IS_K_I` input: set to 8'h0000_0001 + self.wr_regfile_tx_data(data=0x1284A1284A1284A128BC) # 64'h4A4A4A4A_4A4A4ABC + + self.wr_regfile(addr=0x11, data=0x0C00, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=1 + self.wr_regfile(addr=0x12, data=0x0C00, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=1 + self.wr_regfile(addr=0x13, data=0x3000, mask=0x3000) # RX_COMMA_DETECT_EN_OVR=1, RX_COMMA_DETECT_EN=1 + + print(f'INFO: Sending data (this might take a while) ...') + sleep(2) + + self.wr_regfile(addr=0x11, data=0x0000, mask=0x0C00) # RX_MCOMMA_ALIGN_OVR=1, RX_MCOMMA_ALIGN=0 + self.wr_regfile(addr=0x12, data=0x0000, mask=0x0C00) # RX_PCOMMA_ALIGN_OVR=1, RX_PCOMMA_ALIGN=0 + + print(f'INFO: Checking 8-Bit comma alignment') + rx_data, _ = self.rd_regfile_rx_data() + align_pos = 0 if int(rx_data[ 0:7+1]) == 0xBC else \ + 1 if int(rx_data[ 8:15+1]) == 0xBC else \ + 2 if int(rx_data[16:23+1]) == 0xBC else \ + 3 if int(rx_data[24:31+1]) == 0xBC else \ + 4 if int(rx_data[32:39+1]) == 0xBC else \ + 5 if int(rx_data[40:47+1]) == 0xBC else \ + 6 if int(rx_data[48:55+1]) == 0xBC else 7 + rx_recv = 0x4A4A4A4A4A4A4ABC if align_pos == 0 else \ + 0x4A4A4A4A4A4ABC4A if align_pos == 1 else \ + 0x4A4A4A4A4ABC4A4A if align_pos == 2 else \ + 0x4A4A4A4ABC4A4A4A if align_pos == 3 else \ + 0x4A4A4ABC4A4A4A4A if align_pos == 4 else \ + 0x4A4ABC4A4A4A4A4A if align_pos == 5 else \ + 0x4ABC4A4A4A4A4A4A if align_pos == 6 else 0xBC4A4A4A4A4A4A4A + + if (int(rx_data[0:7+1]) != 0xBC and int(rx_data[ 8:15+1]) != 0xBC and int(rx_data[16:23+1]) != 0xBC and int(rx_data[24:31+1]) != 0xBC and int(rx_data[32:39+1]) != 0xBC and int(rx_data[40:47+1]) != 0xBC and int(rx_data[48:55+1]) != 0xBC and int(rx_data[56:63+1]) != 0xBC): + print(f'ERROR: Comma is not aligned to 8-Bit boundary') + if (int(rx_data) != rx_recv): + print(f'ERROR: Invalid idle sequence received: RX_DATA[63:0]: {int(rx_data):016X}') + + def calc_rxterm_vcm(self, vddio=1.0, vcmsel=None) -> float: + if vcmsel is None: + vcmsel = self.rd_regfile(addr=0x02) + vcmsel = int(vcmsel[11:13+1]) + return (vcmsel/29) * vddio + + def update_values(self): + while True: + sleep(0.5) # 500ms update interval + with self.param_lock: + #for param in self.regfile.fields: + # self.regfile.fields[param]['val'] = random.randint(0, 16) + for addr in chain(range(0x00, 0x30), range(0x30, 0x43), range(0x50, 0x5D)): + word = self.rd_regfile(addr) + filtered_entries = {key: value for key, value in self.regfile.fields.items() if value['addr'] == addr} + for (key, value) in filtered_entries.items(): + val = word[value['lbit']:value['hbit']+1] + self.regfile.fields[key]['val'] = int(val) + + def draw_parameters(self, stdscr): + curses.curs_set(0) + stdscr.keypad(True) + stdscr.timeout(10) #stdscr.nodelay(True) # Non-blocking input + + # Initialize colors + curses.start_color() + curses.init_pair(1, curses.COLOR_GREEN, curses.COLOR_BLACK) # OK (Green) + curses.init_pair(2, curses.COLOR_YELLOW, curses.COLOR_BLACK) # WARN (Yellow) + curses.init_pair(3, curses.COLOR_RED, curses.COLOR_BLACK) # FAIL (Red) + curses.init_pair(4, curses.COLOR_BLUE, curses.COLOR_BLACK) # OVR (Blue) + curses.init_pair(5, curses.COLOR_WHITE, curses.COLOR_BLACK) # Normal text + + def handle_resize(signum, frame): + curses.endwin() + stdscr.refresh() + + signal.signal(signal.SIGWINCH, handle_resize) + + selected_index = 0 + show_hex = False + search_results = [] + search_index = 0 + + while True: + max_y, max_x = stdscr.getmaxyx() + max_name_length = max(len(name) for name in self.regfile.fields.keys()) + col_width = max_name_length + 8 + num_columns = max(1, max_x // col_width) + num_rows = math.ceil(len(self.regfile.fields) / num_columns) + param_list = list(self.regfile.fields.items()) + + # Extract values for bit rate calculation + PLL_MAIN_DIVSEL = self.regfile.fields.get("PLL_MAIN_DIVSEL", {}).get("val", 0x1B) + PLL_OUT_DIVSEL = self.regfile.fields.get("PLL_OUT_DIVSEL", {}).get("val", 0x0) + TX_DATAPATH_SEL = self.regfile.fields.get("TX_DATAPATH_SEL", {}).get("val", 0x0) + + # Decode PLL values + N3 = {0b00: 3, 0b10: 4, 0b11: 5}.get((PLL_MAIN_DIVSEL >> 3) & 0b11, None) + N1 = {0b0: 1, 0b1: 2}.get((PLL_MAIN_DIVSEL >> 2) & 0b1, None) + N2 = {0b00: 3, 0b01: 2, 0b10: 4, 0b11: 5}.get(PLL_MAIN_DIVSEL & 0b11, None) + OUTDIV = {0b00: 1, 0b01: 2, 0b11: 4}.get(PLL_OUT_DIVSEL, None) + + bit_rate_clock = 2 * 100e6 * N1 * N2 * N3 / OUTDIV if None not in (N1, N2, N3, OUTDIV) else None + + # Decode TX_DATAPATH_SEL + datapath_mode = (TX_DATAPATH_SEL & 0b10) >> 1 # Extract MSB + is_64_bit = datapath_mode == 1 # If `1x`, it is 64-bit + + # Determine AddDiv based on OUTDIV + if is_64_bit: + AddDiv = {0b00: 2, 0b01: 4, 0b11: 8}.get(PLL_OUT_DIVSEL, None) + else: + AddDiv = {0b00: 1, 0b01: 2, 0b11: 4}.get(PLL_OUT_DIVSEL, None) + + PLL_FCNTRL = self.regfile.fields.get("PLL_FCNTRL", {}).get("val", 0x0) + data_path_clock = (100e6 * N1 * N2 * N3) / (self.olclkg[PLL_FCNTRL] * AddDiv) if None not in (N1, N2, N3, OUTDIV, AddDiv) else None + + bit_rate_str = f"Bit Rate Clock: {bit_rate_clock / 1e6:.2f} MHz" if bit_rate_clock else "Invalid PLL Config" + data_path_str = f"TX Data Path Clock: {data_path_clock / 1e6:.2f} MHz" if data_path_clock else "Invalid Data Path Config" + + stdscr.clear() + stdscr.addstr(0, 2, " FPGA SerDes Parameters (Auto-Update Enabled) ", curses.A_BOLD | curses.A_REVERSE) + + with self.param_lock: + for row in range(num_rows): + for col in range(num_columns): + index = row + col * num_rows + if index >= len(param_list): + continue + + name, data = param_list[index] + value = data['val'] + mode = data['mode'] # Get mode (R/W, W/C, R/C, R) + color_pair = ColorFormatter.get_color_pair(name, value) + + formatted_value = f"0x{value:X}" if show_hex else f"{value}" + + # Read-only and Write/Clear (dimmed text) + text_attr = curses.color_pair(color_pair) | curses.A_DIM if mode in ["R", "R/C"] else curses.color_pair(color_pair) + + x_pos = col * col_width + 2 + y_pos = row + 2 + + # Highlight selected row + if index == selected_index: + stdscr.addstr(y_pos, x_pos, f"{name:<{max_name_length}} {formatted_value:<8}", curses.A_REVERSE) + else: + # Print parameter name (dimmed for R & W/C) + stdscr.addstr(y_pos, x_pos, f"{name:<{max_name_length}}", text_attr) + + # Print value in color + stdscr.addstr(y_pos, x_pos + max_name_length + 1, f"{formatted_value:<8}", curses.color_pair(color_pair)) + + + stdscr.addstr(max_y - 5, 2, bit_rate_str) + stdscr.addstr(max_y - 4, 2, data_path_str) + + search_hint = "[n] Next match | " if search_results else "" + stdscr.addstr(max_y - 2, 2, f"{search_hint}[Arrow Keys] Navigate | [Enter] Edit | [/] Find | [h] Toggle HEX/DEC | [q] Quit", curses.A_BOLD) + + stdscr.refresh() + + try: + key = stdscr.getch() + except curses.error: + key = -1 # No input + + if key == ord("h"): + show_hex = not show_hex + elif key == curses.KEY_UP and selected_index - 1 >= 0: + selected_index -= 1 + elif key == curses.KEY_DOWN and selected_index + 1 < len(param_list): + selected_index += 1 + elif key == curses.KEY_LEFT and selected_index - num_rows >= 0: + selected_index -= num_rows + elif key == curses.KEY_RIGHT and selected_index + num_rows < len(param_list): + selected_index += num_rows + elif key == ord("\n"): + if param_list[selected_index][1]['mode'] in ["R", "R/C"]: + self.error_message(stdscr, "Cannot edit read-only parameter!") + else: + self.edit_value_popup(stdscr, param_list[selected_index]) + elif key == ord("/"): + search_results, search_index = self.find_parameter(stdscr, param_list) + if search_results: + selected_index = search_results[search_index] + elif key == ord("n") and search_results: + search_index = (search_index + 1) % len(search_results) + selected_index = search_results[search_index] + elif key == ord("q"): + break + + def edit_value_popup(self, stdscr, param): + name, data = param + max_y, max_x = stdscr.getmaxyx() + + # Calculate the valid range from `hbit` and `lbit` + hbit, lbit = data['hbit'], data['lbit'] + mask = ((1 << (hbit - lbit + 1)) - 1) << lbit + addr = data['addr'] + min_value = 0 + max_value = (1 << (hbit - lbit + 1)) - 1 # Compute max based on bit range + + win_height, win_width = 9, 50 + start_y = (max_y - win_height) // 2 + start_x = (max_x - win_width) // 2 + + win = curses.newwin(win_height, win_width, start_y, start_x) + win.box() + win.addstr(1, 2, f"Editing: {name}", curses.A_BOLD) + win.addstr(2, 2, f"Position: addr=0x{addr:02X} mask=0x{mask:04X}") + win.addstr(3, 2, f"Current: {data['val']} (Range: {min_value} - {max_value})") # Show valid range + win.addstr(5, 2, "New value: ") + win.addstr(7, 2, "[Enter] Save | [ESC/q] Cancel", curses.A_DIM) + + win.refresh() + curses.curs_set(1) + win.keypad(True) + + curses.echo() + new_val = "" + + while True: + key = win.getch() + + if key in (27, ord("q")): + break + elif key == ord("\n"): + try: + entered_value = int(new_val, 0) # Convert input to integer + if min_value <= entered_value <= max_value: + with self.param_lock: + #data['val'] = entered_value # Apply change if within range + self._tool.wr_serdes_regfile(addr=addr, data=entered_value << lbit, mask=mask, wren=1) + self._tool.rd_serdes_regfile() + break + else: + win.addstr(6, 2, "Out of range! Try again.", curses.A_BOLD | curses.color_pair(3)) + win.refresh() + time.sleep(1) + win.addstr(6, 2, " " * 30) # Clear error message + except ValueError: + win.addstr(6, 2, "Invalid input!", curses.A_BOLD | curses.color_pair(3)) + win.refresh() + time.sleep(1) + win.addstr(6, 2, " " * 30) # Clear error message + elif key in (curses.KEY_BACKSPACE, 127): + new_val = new_val[:-1] + win.addstr(5, 13, " " * 10) # Clear previous input + elif key in range(32, 127): + new_val += chr(key) + + win.addstr(5, 13, new_val) + win.refresh() + + curses.noecho() + curses.curs_set(0) + + def find_parameter(self, stdscr, param_list): + max_y, max_x = stdscr.getmaxyx() + win_height, win_width = 4, 50 + start_y = (max_y - win_height) // 2 + start_x = (max_x - win_width) // 2 + + win = curses.newwin(win_height, win_width, start_y, start_x) + win.box() + win.addstr(1, 2, "Find: ") + win.addstr(2, 2, "[ESC/q] Cancel", curses.A_DIM) + + win.refresh() + curses.curs_set(1) + curses.echo() + + search_term = "" + + while True: + key = win.getch() + + if key in (27, ord("q")): + return [], 0 + elif key == ord("\n"): + break + elif key in (curses.KEY_BACKSPACE, 127): + search_term = search_term[:-1] + win.addstr(1, 8, " " * 40) + elif key in range(32, 127): + search_term += chr(key) + + win.addstr(1, 8, search_term) + win.refresh() + + curses.noecho() + curses.curs_set(0) + + search_term = search_term.strip().lower() + + if not search_term: + return [], 0 + + matches = [i for i, (name, _) in enumerate(param_list) if search_term in name.lower()] + + if not matches: + self.error_message(stdscr, "No matches found!") + return [], 0 + + return matches, 0 + + def error_message(self, stdscr, message): + max_y, max_x = stdscr.getmaxyx() + win_height, win_width = 3, len(message) + 10 + start_y = (max_y - win_height) // 2 + start_x = (max_x - win_width) // 2 + + win = curses.newwin(win_height, win_width, start_y, start_x) + win.box() + win.addstr(1, 2, message, curses.A_BOLD) + + win.refresh() + curses.napms(1500) + del win + + +if __name__ == '__main__': + try: + p = argparse.ArgumentParser(prog='serdestool', description='', epilog=ArgEpilog) + + p.add_argument('-l', '--list', dest='listdev', action='store_true', help='list available boards/programmers and exit') + p.add_argument('-b', dest='board', type=str, metavar=Boards_e, default=Boards_e[0], required=False, help='select board (default: %(default)s)') + p.add_argument('--index-chain', dest='idx', default=0, required=False, help='device index in JTAG chain (default: %(default)s)') + p.add_argument('--freq', type=ArgHzRegex, default='20M', metavar="[0 - 30M]", required=False, help='frequency setting; append "k" to the argument for kilohertz or "M" for megahertz (default: %(default)s)') + p.add_argument('-m', dest='genmod', type=str, required=False, help='generate verilog or vhdl module and exit; specify the file format with extension .v or .vhd') + p.add_argument('--rdregrx', dest='rdregrx', action='store_true', help='read rx regfile') + p.add_argument('--rdregrxdata', dest='rdregrxdata', action='store_true', help='read rx data') + p.add_argument('--rdregtx', dest='rdregtx', action='store_true', help='read tx regfile') + p.add_argument('--rdregpll', dest='rdregpll', action='store_true', help='read pll regfile') + p.add_argument('--rdstatuspll', dest='rdstatuspll', action='store_true', help='read pll status registers') + p.add_argument('--gui', dest='gui', action='store_true', help='start curses gui') + p.add_argument('--tcprbs', dest='tcprbs', action='store_true', help='testcase: prbs') + p.add_argument('--tcloopback', dest='tcloopback', action='store_true', help='testcase: loopback') + p.add_argument('--tcuipattern', dest='tcuipattern', choices=['0','2','20','40','80'], default=None, required=False, help='testcase: 2,20,40,80 UI square wave pattern') + + args = p.parse_args() + usb = UsbTools() + jtag = JtagEngine(frequency=ArgHzParse(args.freq)) + + if args.listdev: + vps_lst = list() + vps_lst.append((0x0403, 0x6010)) # evb: FT2232H + vps_lst.append((0x0403, 0x6014)) # pgm: FT232H + for line in usb.find_all(vps=vps_lst): + print(*line) + sys.exit() + + s = SerdesTool(args, jtag, hwinit=not args.genmod) + + if args.genmod is not None: + filename = args.genmod.lower() + if filename.endswith('.v') or filename.endswith('.sv'): + s.gen_module_vlog(filename) + elif filename.endswith('.vhd') or filename.endswith('.vhdl'): + s.gen_module_vhdl(filename) + sys.exit() + + if args.gui: + update_thread = threading.Thread(target=s.update_values, daemon=True) + update_thread.start() + curses.wrapper(s.draw_parameters) + else: + if args.tcprbs: + s.tc_prbs(force_err=True) + if args.tcloopback: + s.tc_loopback() + if args.tcuipattern is not None: + s.tc_uipattern(int(args.tcuipattern)) + if args.rdregrx: + s.rd_regfile_rx(verbose=2) + if args.rdregrxdata: + s.print_regfile_rx_data(verbose=2) + if args.rdregtx: + s.rd_regfile_tx(verbose=2) + if args.rdregpll: + s.rd_regfile_pll(verbose=2) + if args.rdstatuspll: + [s._tool.rd_status_pll(pll=i, verbose=1) for i in range(4)] + + except Exception as e: + print(e) \ No newline at end of file diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/README.md b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/README.md new file mode 100644 index 0000000000000000000000000000000000000000..4a183231788cb52a6ab8245096431b20b8e6b758 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/README.md @@ -0,0 +1,102 @@ +[> Bare Metal Demo App +---------------------- + +This directory provides a minimal bare metal demo app that demonstrates how to easily create a bare metal C application and load it/run it on the CPU of a SoC. + +[> Build and Load over LiteX-Term +--------------------------------- + +To build a LiteX SoC for the Arty board (available in LiteX-Boards) and build the demo app for it, execute the following commands: +``` +python3 -m litex_boards.targets.digilent_arty --build --load +litex_bare_metal_demo --build-path=build/digilent_arty +``` +Where `--build-path` is the build path to the Arty build directory. The Arty board is used here but almost any another board supported in LiteX-Boards could be used. When no external RAM is provided directly by the board, `--integrated-main-ram-size` argument could be used to add some integrated RAM in the SoC and be able to execute the demo from it. (ex `--integrated-main-ram-size=0x8000` will add 32KB of integrated RAM). + +Loading the compiled demo app can be done in different ways as explain in LiteX's wiki: +https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU + +Since our app is small and for simplicity we'll just load it over serial here: + `$ litex_term /dev/ttyUSBX --kernel=demo.bin` + +You should see the minimal demo app running and should be able to interact with it: + + --============== Boot ==================-- + Booting from serial... + Press Q or ESC to abort boot completely. + sL5DdSMmkekro + [LITEX-TERM] Received firmware download request from the device. + [LITEX-TERM] Uploading demo.bin to 0x40000000 (9264 bytes)... + [LITEX-TERM] Upload complete (9.8KB/s). + [LITEX-TERM] Booting the device. + [LITEX-TERM] Done. + Executing booted program at 0x40000000 + + --============= Liftoff! ===============-- + + LiteX minimal demo app built Dec 10 2020 17:13:02 + + Available commands: + help - Show this command + reboot - Reboot CPU + led - Led demo + donut - Spinning Donut demo + litex-demo-app> led + Led demo... + Counter mode... + Shift mode... + Dance mode... + litex-demo-app> donut + Donut demo... + + $$$$$@@@@@ + $##########$$$$$$$$ + ###*!!!!!!!!!***##$$$$$$ + ***!!====;;;;===!!**###$$$$# + **!===;;;:::::;:===!!**####$## + !*!!==;;:~-,,.,-~::;;=!!**#######! + !!!!=;:~-,.......-~::==!!***#####* + !!!!==;~~-.........,-:;==!!***###**! + !**!!=;:~-... ..-:;=!!!********! + ;!*#####*!!;. ~:;==!!!******!!= + :!*###$$$$#*! :;==!!!!!****!!!=; + ~=!*#$$$@@@$$##!!!!!!!!!!!!****!!!!=; + ;=!*#$$$@@@@$$#*******!*!!*!!!!!==;~ + -;!*###$$$$$$$###******!!!!!!!===;~ + -;!!*####$#####******!!!!!!==;;:- + ,:=!!!!**#**#***!!!!!!!====;:~, + -:==!!!*!!*!!!!!!!===;;;:~- + .~:;;========;=;;:::~-, + .--~~::::~:~~--,. + litex-demo-app> + +[> Replace the LiteX BIOS with the Demo App +------------------------------------------- +In some cases, we'll just want to replace the LiteX BIOS with our custom app. This demo can be used as a basis to create a such custom app. + +The demo will be recompiled to target the ROM of the SoC: +``` +litex_bare_metal_demo --build-path=build/arty/ --mem=rom +``` + +The SoC can then be re-compiled to integrate the demo app in the ROM with: +``` +python3 -m litex_boards.targets.digilent_arty --integrated-rom-init=demo.bin --build --load +``` + +When loading the bitstream, you should then directly see the demo app executed: +``` + LiteX minimal demo app built Dec 10 2020 17:13:02 + + Available commands: + help - Show this command + reboot - Reboot CPU + led - Led demo + donut - Spinning Donut demo + litex-demo-app> +``` + + +[> Going further +---------------- +To create more complex apps, feel free to explore the source code of the BIOS or other open source projects build with LiteX at https://github.com/enjoy-digital/litex/wiki/Projects. diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/__init__.py b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo.py b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo.py new file mode 100644 index 0000000000000000000000000000000000000000..bb773b3b993a65421110ce923d6fafd35ba0ed75 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX. +# +# Copyright (c) 2020-2022 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +import os +import sys +import argparse + +from litex.build.tools import replace_in_file + +def main(): + parser = argparse.ArgumentParser(description="LiteX Bare Metal Demo App.") + parser.add_argument("--build-path", help="Target's build path (ex build/board_name).", required=True) + parser.add_argument("--with-cxx", action="store_true", help="Enable CXX support.") + parser.add_argument("--mem", default="main_ram", help="Memory Region where code will be loaded/executed.") + args = parser.parse_args() + + # Create demo directory + os.makedirs("demo", exist_ok=True) + + # Copy contents to demo directory + os.system(f"cp {os.path.abspath(os.path.dirname(__file__))}/* demo") + os.system("chmod -R u+w demo") # Nix specific: Allow linker script to be modified. + + # Update memory region. + replace_in_file("demo/linker.ld", "main_ram", args.mem) + + # Compile demo + build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path) + os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make") + + # Copy demo.bin + os.system("cp demo/demo.bin ./") + + # Prepare flash boot image. + python3 = sys.executable or "python3" # Nix specific: Reuse current Python executable if available. + os.system(f"{python3} -m litex.soc.software.crcfbigen demo.bin -o demo.fbi --fbi --little") # FIXME: Endianness. + +if __name__ == "__main__": + main() + diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/README.md b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/README.md new file mode 100644 index 0000000000000000000000000000000000000000..4a183231788cb52a6ab8245096431b20b8e6b758 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/README.md @@ -0,0 +1,102 @@ +[> Bare Metal Demo App +---------------------- + +This directory provides a minimal bare metal demo app that demonstrates how to easily create a bare metal C application and load it/run it on the CPU of a SoC. + +[> Build and Load over LiteX-Term +--------------------------------- + +To build a LiteX SoC for the Arty board (available in LiteX-Boards) and build the demo app for it, execute the following commands: +``` +python3 -m litex_boards.targets.digilent_arty --build --load +litex_bare_metal_demo --build-path=build/digilent_arty +``` +Where `--build-path` is the build path to the Arty build directory. The Arty board is used here but almost any another board supported in LiteX-Boards could be used. When no external RAM is provided directly by the board, `--integrated-main-ram-size` argument could be used to add some integrated RAM in the SoC and be able to execute the demo from it. (ex `--integrated-main-ram-size=0x8000` will add 32KB of integrated RAM). + +Loading the compiled demo app can be done in different ways as explain in LiteX's wiki: +https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU + +Since our app is small and for simplicity we'll just load it over serial here: + `$ litex_term /dev/ttyUSBX --kernel=demo.bin` + +You should see the minimal demo app running and should be able to interact with it: + + --============== Boot ==================-- + Booting from serial... + Press Q or ESC to abort boot completely. + sL5DdSMmkekro + [LITEX-TERM] Received firmware download request from the device. + [LITEX-TERM] Uploading demo.bin to 0x40000000 (9264 bytes)... + [LITEX-TERM] Upload complete (9.8KB/s). + [LITEX-TERM] Booting the device. + [LITEX-TERM] Done. + Executing booted program at 0x40000000 + + --============= Liftoff! ===============-- + + LiteX minimal demo app built Dec 10 2020 17:13:02 + + Available commands: + help - Show this command + reboot - Reboot CPU + led - Led demo + donut - Spinning Donut demo + litex-demo-app> led + Led demo... + Counter mode... + Shift mode... + Dance mode... + litex-demo-app> donut + Donut demo... + + $$$$$@@@@@ + $##########$$$$$$$$ + ###*!!!!!!!!!***##$$$$$$ + ***!!====;;;;===!!**###$$$$# + **!===;;;:::::;:===!!**####$## + !*!!==;;:~-,,.,-~::;;=!!**#######! + !!!!=;:~-,.......-~::==!!***#####* + !!!!==;~~-.........,-:;==!!***###**! + !**!!=;:~-... ..-:;=!!!********! + ;!*#####*!!;. ~:;==!!!******!!= + :!*###$$$$#*! :;==!!!!!****!!!=; + ~=!*#$$$@@@$$##!!!!!!!!!!!!****!!!!=; + ;=!*#$$$@@@@$$#*******!*!!*!!!!!==;~ + -;!*###$$$$$$$###******!!!!!!!===;~ + -;!!*####$#####******!!!!!!==;;:- + ,:=!!!!**#**#***!!!!!!!====;:~, + -:==!!!*!!*!!!!!!!===;;;:~- + .~:;;========;=;;:::~-, + .--~~::::~:~~--,. + litex-demo-app> + +[> Replace the LiteX BIOS with the Demo App +------------------------------------------- +In some cases, we'll just want to replace the LiteX BIOS with our custom app. This demo can be used as a basis to create a such custom app. + +The demo will be recompiled to target the ROM of the SoC: +``` +litex_bare_metal_demo --build-path=build/arty/ --mem=rom +``` + +The SoC can then be re-compiled to integrate the demo app in the ROM with: +``` +python3 -m litex_boards.targets.digilent_arty --integrated-rom-init=demo.bin --build --load +``` + +When loading the bitstream, you should then directly see the demo app executed: +``` + LiteX minimal demo app built Dec 10 2020 17:13:02 + + Available commands: + help - Show this command + reboot - Reboot CPU + led - Led demo + donut - Spinning Donut demo + litex-demo-app> +``` + + +[> Going further +---------------- +To create more complex apps, feel free to explore the source code of the BIOS or other open source projects build with LiteX at https://github.com/enjoy-digital/litex/wiki/Projects. diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/__init__.py b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/__init__.py new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/demo.py b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/demo.py new file mode 100644 index 0000000000000000000000000000000000000000..bb773b3b993a65421110ce923d6fafd35ba0ed75 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/demo.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX. +# +# Copyright (c) 2020-2022 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +import os +import sys +import argparse + +from litex.build.tools import replace_in_file + +def main(): + parser = argparse.ArgumentParser(description="LiteX Bare Metal Demo App.") + parser.add_argument("--build-path", help="Target's build path (ex build/board_name).", required=True) + parser.add_argument("--with-cxx", action="store_true", help="Enable CXX support.") + parser.add_argument("--mem", default="main_ram", help="Memory Region where code will be loaded/executed.") + args = parser.parse_args() + + # Create demo directory + os.makedirs("demo", exist_ok=True) + + # Copy contents to demo directory + os.system(f"cp {os.path.abspath(os.path.dirname(__file__))}/* demo") + os.system("chmod -R u+w demo") # Nix specific: Allow linker script to be modified. + + # Update memory region. + replace_in_file("demo/linker.ld", "main_ram", args.mem) + + # Compile demo + build_path = args.build_path if os.path.isabs(args.build_path) else os.path.join("..", args.build_path) + os.system(f"export BUILD_DIR={build_path} && {'export WITH_CXX=1 &&' if args.with_cxx else ''} cd demo && make") + + # Copy demo.bin + os.system("cp demo/demo.bin ./") + + # Prepare flash boot image. + python3 = sys.executable or "python3" # Nix specific: Reuse current Python executable if available. + os.system(f"{python3} -m litex.soc.software.crcfbigen demo.bin -o demo.fbi --fbi --little") # FIXME: Endianness. + +if __name__ == "__main__": + main() + diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/donut.c b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/donut.c new file mode 100644 index 0000000000000000000000000000000000000000..eab0905dc665c472d554b0438cc78fabf8636d43 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/donut.c @@ -0,0 +1,68 @@ +// The donut code with fixed-point arithmetic; no sines, cosines, square roots, or anything. +// a1k0n 2020 +// Code from: https://gist.github.com/a1k0n/80f48aa8911fffd805316b8ba8f48e83 +// For more info: +// - https://www.a1k0n.net/2011/07/20/donut-math.html +// - https://www.youtube.com/watch?v=DEqXNfs_HhY + +#include +#include +#include + +#include + +#define R(mul,shift,x,y) \ + _=x; \ + x -= mul*y>>shift; \ + y += mul*_>>shift; \ + _ = 3145728-x*x-y*y>>11; \ + x = x*_>>10; \ + y = y*_>>10; + +signed char b[1760], z[1760]; + +void donut(void); +void donut(void) { + int sA=1024,cA=0,sB=1024,cB=0,_; + for (;;) { + memset(b, 32, 1760); // text buffer + memset(z, 127, 1760); // z buffer + int sj=0, cj=1024; + for (int j = 0; j < 90; j++) { + int si = 0, ci = 1024; // sine and cosine of angle i + for (int i = 0; i < 324; i++) { + int R1 = 1, R2 = 2048, K2 = 5120*1024; + + int x0 = R1*cj + R2, + x1 = ci*x0 >> 10, + x2 = cA*sj >> 10, + x3 = si*x0 >> 10, + x4 = R1*x2 - (sA*x3 >> 10), + x5 = sA*sj >> 10, + x6 = K2 + R1*1024*x5 + cA*x3, + x7 = cj*si >> 10, + x = 40 + 30*(cB*x1 - sB*x4)/x6, + y = 12 + 15*(cB*x4 + sB*x1)/x6, + N = (-cA*x7 - cB*((-sA*x7>>10) + x2) - ci*(cj*sB >> 10) >> 10) - x5 >> 7; + + int o = x + 80 * y; + signed char zz = (x6-K2)>>15; + if (22 > y && y > 0 && x > 0 && 80 > x && zz < z[o]) { + z[o] = zz; + b[o] = ".,-~:;=!*#$@"[N > 0 ? N : 0]; + } + R(5, 8, ci, si) // rotate i + } + R(9, 7, cj, sj) // rotate j + } + for (int k = 0; 1761 > k; k++) + putchar(k % 80 ? b[k] : 10); + R(5, 7, cA, sA); + R(5, 8, cB, sB); + if (readchar_nonblock()) { + getchar(); + break; + } + fputs("\x1b[23A", stdout); + } +} diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/helloc.c b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/helloc.c new file mode 100644 index 0000000000000000000000000000000000000000..e8750cc8353350a06700d91b2a1c8eb3d9a85b2b --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/helloc.c @@ -0,0 +1,6 @@ +#include + +void helloc(void); +void helloc(void) { + printf("C: Hello, world!\n"); +} \ No newline at end of file diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/hellocpp.cpp b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/hellocpp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fb9e3fe747d8d0ac3b5112a6869c92817321946b --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/hellocpp.cpp @@ -0,0 +1,7 @@ +#include + +extern "C" void hellocpp(void); +void hellocpp(void) +{ + printf("C++: Hello, world!\n"); +} \ No newline at end of file diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/main.c b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/main.c new file mode 100644 index 0000000000000000000000000000000000000000..38c451fa665b2143abe864c1c0b0b14179d1a783 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/demo/main.c @@ -0,0 +1,210 @@ +// This file is Copyright (c) 2020 Florent Kermarrec +// License: BSD + +#include +#include +#include + +#include +#include +#include +#include + +/*-----------------------------------------------------------------------*/ +/* Uart */ +/*-----------------------------------------------------------------------*/ + +static char *readstr(void) +{ + char c[2]; + static char s[64]; + static int ptr = 0; + + if(readchar_nonblock()) { + c[0] = getchar(); + c[1] = 0; + switch(c[0]) { + case 0x7f: + case 0x08: + if(ptr > 0) { + ptr--; + fputs("\x08 \x08", stdout); + } + break; + case 0x07: + break; + case '\r': + case '\n': + s[ptr] = 0x00; + fputs("\n", stdout); + ptr = 0; + return s; + default: + if(ptr >= (sizeof(s) - 1)) + break; + fputs(c, stdout); + s[ptr] = c[0]; + ptr++; + break; + } + } + + return NULL; +} + +static char *get_token(char **str) +{ + char *c, *d; + + c = (char *)strchr(*str, ' '); + if(c == NULL) { + d = *str; + *str = *str+strlen(*str); + return d; + } + *c = 0; + d = *str; + *str = c+1; + return d; +} + +static void prompt(void) +{ + printf("\e[92;1mlitex-demo-app\e[0m> "); +} + +/*-----------------------------------------------------------------------*/ +/* Help */ +/*-----------------------------------------------------------------------*/ + +static void help(void) +{ + puts("\nLiteX minimal demo app built "__DATE__" "__TIME__"\n"); + puts("Available commands:"); + puts("help - Show this command"); + puts("reboot - Reboot CPU"); +#ifdef CSR_LEDS_BASE + puts("led - Led demo"); +#endif + puts("donut - Spinning Donut demo"); + puts("helloc - Hello C"); +#ifdef WITH_CXX + puts("hellocpp - Hello C++"); +#endif +} + +/*-----------------------------------------------------------------------*/ +/* Commands */ +/*-----------------------------------------------------------------------*/ + +static void reboot_cmd(void) +{ + ctrl_reset_write(1); +} + +#ifdef CSR_LEDS_BASE +static void led_cmd(void) +{ + int i; + printf("Led demo...\n"); + + printf("Counter mode...\n"); + for(i=0; i<32; i++) { + leds_out_write(i); + busy_wait(100); + } + + printf("Shift mode...\n"); + for(i=0; i<4; i++) { + leds_out_write(1< +#include +#include + +#include + +#define R(mul,shift,x,y) \ + _=x; \ + x -= mul*y>>shift; \ + y += mul*_>>shift; \ + _ = 3145728-x*x-y*y>>11; \ + x = x*_>>10; \ + y = y*_>>10; + +signed char b[1760], z[1760]; + +void donut(void); +void donut(void) { + int sA=1024,cA=0,sB=1024,cB=0,_; + for (;;) { + memset(b, 32, 1760); // text buffer + memset(z, 127, 1760); // z buffer + int sj=0, cj=1024; + for (int j = 0; j < 90; j++) { + int si = 0, ci = 1024; // sine and cosine of angle i + for (int i = 0; i < 324; i++) { + int R1 = 1, R2 = 2048, K2 = 5120*1024; + + int x0 = R1*cj + R2, + x1 = ci*x0 >> 10, + x2 = cA*sj >> 10, + x3 = si*x0 >> 10, + x4 = R1*x2 - (sA*x3 >> 10), + x5 = sA*sj >> 10, + x6 = K2 + R1*1024*x5 + cA*x3, + x7 = cj*si >> 10, + x = 40 + 30*(cB*x1 - sB*x4)/x6, + y = 12 + 15*(cB*x4 + sB*x1)/x6, + N = (-cA*x7 - cB*((-sA*x7>>10) + x2) - ci*(cj*sB >> 10) >> 10) - x5 >> 7; + + int o = x + 80 * y; + signed char zz = (x6-K2)>>15; + if (22 > y && y > 0 && x > 0 && 80 > x && zz < z[o]) { + z[o] = zz; + b[o] = ".,-~:;=!*#$@"[N > 0 ? N : 0]; + } + R(5, 8, ci, si) // rotate i + } + R(9, 7, cj, sj) // rotate j + } + for (int k = 0; 1761 > k; k++) + putchar(k % 80 ? b[k] : 10); + R(5, 7, cA, sA); + R(5, 8, cB, sB); + if (readchar_nonblock()) { + getchar(); + break; + } + fputs("\x1b[23A", stdout); + } +} diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/helloc.c b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/helloc.c new file mode 100644 index 0000000000000000000000000000000000000000..e8750cc8353350a06700d91b2a1c8eb3d9a85b2b --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/helloc.c @@ -0,0 +1,6 @@ +#include + +void helloc(void); +void helloc(void) { + printf("C: Hello, world!\n"); +} \ No newline at end of file diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/hellocpp.cpp b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/hellocpp.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fb9e3fe747d8d0ac3b5112a6869c92817321946b --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/hellocpp.cpp @@ -0,0 +1,7 @@ +#include + +extern "C" void hellocpp(void); +void hellocpp(void) +{ + printf("C++: Hello, world!\n"); +} \ No newline at end of file diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/main.c b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/main.c new file mode 100644 index 0000000000000000000000000000000000000000..38c451fa665b2143abe864c1c0b0b14179d1a783 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/2.sw/main.c @@ -0,0 +1,210 @@ +// This file is Copyright (c) 2020 Florent Kermarrec +// License: BSD + +#include +#include +#include + +#include +#include +#include +#include + +/*-----------------------------------------------------------------------*/ +/* Uart */ +/*-----------------------------------------------------------------------*/ + +static char *readstr(void) +{ + char c[2]; + static char s[64]; + static int ptr = 0; + + if(readchar_nonblock()) { + c[0] = getchar(); + c[1] = 0; + switch(c[0]) { + case 0x7f: + case 0x08: + if(ptr > 0) { + ptr--; + fputs("\x08 \x08", stdout); + } + break; + case 0x07: + break; + case '\r': + case '\n': + s[ptr] = 0x00; + fputs("\n", stdout); + ptr = 0; + return s; + default: + if(ptr >= (sizeof(s) - 1)) + break; + fputs(c, stdout); + s[ptr] = c[0]; + ptr++; + break; + } + } + + return NULL; +} + +static char *get_token(char **str) +{ + char *c, *d; + + c = (char *)strchr(*str, ' '); + if(c == NULL) { + d = *str; + *str = *str+strlen(*str); + return d; + } + *c = 0; + d = *str; + *str = c+1; + return d; +} + +static void prompt(void) +{ + printf("\e[92;1mlitex-demo-app\e[0m> "); +} + +/*-----------------------------------------------------------------------*/ +/* Help */ +/*-----------------------------------------------------------------------*/ + +static void help(void) +{ + puts("\nLiteX minimal demo app built "__DATE__" "__TIME__"\n"); + puts("Available commands:"); + puts("help - Show this command"); + puts("reboot - Reboot CPU"); +#ifdef CSR_LEDS_BASE + puts("led - Led demo"); +#endif + puts("donut - Spinning Donut demo"); + puts("helloc - Hello C"); +#ifdef WITH_CXX + puts("hellocpp - Hello C++"); +#endif +} + +/*-----------------------------------------------------------------------*/ +/* Commands */ +/*-----------------------------------------------------------------------*/ + +static void reboot_cmd(void) +{ + ctrl_reset_write(1); +} + +#ifdef CSR_LEDS_BASE +static void led_cmd(void) +{ + int i; + printf("Led demo...\n"); + + printf("Counter mode...\n"); + for(i=0; i<32; i++) { + leds_out_write(i); + busy_wait(100); + } + + printf("Shift mode...\n"); + for(i=0; i<4; i++) { + leds_out_write(1< TX_DATA bits 0-7, tx_data[8] -> dispval, tx_data[9] -> dispmode + # Upper 10-bit word: data[10:18] -> TX_DATA bits 8-15, tx_data[18] -> dispval, tx_data[19] -> dispmode + self.comb += [ + tx_bus[0:8].eq(tx_data[0:8]), # lower byte of data + tx_bus[8].eq(0), tx_bus[9].eq(0), # we set all K/disp bits to 0 by default (assuming data already disparity-corrected) + tx_bus[10:18].eq(tx_data[10:18]), # upper byte of data + tx_bus[18:24].eq(0) # upper word K/disp bits also 0 + ] + # ** RX Data Path ** + # Map SERDES RX bus back to 20-bit data (inverse of TX mapping) + self.comb += [ + rx_data[0:8].eq(rx_bus[0:8]), # lower 8 data bits + rx_data[8].eq(rx_bus[8]), # (not used in fabric, would indicate K or disparity error) + rx_data[9].eq(rx_bus[9]), # (not used in fabric) + rx_data[10:18].eq(rx_bus[10:18]), # upper 8 data bits + rx_data[18].eq(rx_bus[18]), + rx_data[19].eq(rx_bus[19]) + ] + # Feed RX data into PRBS checker + self.comb += self.rx_prbs.i.eq(rx_data) + # Feed RX data into 8b/10b decoders (each decoder handles one 10-bit word) + for i in range(self.nwords): + self.sync.rx += self.decoders[i].input.eq(rx_data[10*i:10*(i+1)]) + # ** Reset and Initialization Sequencing ** + pll_reset_cycles = int((30000 * sys_clk_freq) // 1e9) # ~30 µs at sys_clk_freq + if pll_reset_cycles < 1: pll_reset_cycles = 1 + reset_counter = Signal(max=pll_reset_cycles+1, reset=0) + cdr_lock_time = int((sys_clk_freq * 50e3) // linerate) # ~50,000 UI (bit periods) at sys_clk + if cdr_lock_time < 1: cdr_lock_time = 1 + cdr_lock_counter = Signal(max=int(cdr_lock_time)+1, reset=0) + cdr_locked = Signal(reset=0) + # System clock domain FSM for resets + self.sync += [ + # ADPLL reset release after `pll_reset_cycles` ticks + If(reset_counter < pll_reset_cycles, + reset_counter.eq(reset_counter + 1), + adpll_reset.eq(1) + ).Else( + adpll_reset.eq(0) + ), + # CDR lock timer (starts when RX reset is not asserted and PLL is running) + If(rx_reset | adpll_reset, + cdr_locked.eq(0), + cdr_lock_counter.eq(0) + ).Elif(cdr_lock_counter < cdr_lock_time, + cdr_lock_counter.eq(cdr_lock_counter + 1) + ).Else( + cdr_locked.eq(1) + ) + ] + self.comb += [ + self.rx_ready.eq(cdr_locked), + self.tx_ready.eq(tx_reset_done & cdr_locked) + ] + self.specials += AsyncResetSynchronizer(self.cd_rx, ~cdr_locked) + self.specials += AsyncResetSynchronizer(self.cd_tx, ~tx_reset_done) + + # Select ADPLL parameters for the given reference clock frequency + adpll_config = { + 100e6: {'fcntrl': 0x0A, 'main_divsel': 0x1B, 'out_divsel': 3}, # for 100 MHz ref + 125e6: {'fcntrl': 0x1A, 'main_divsel': 0x1A, 'out_divsel': 3} # for 125 MHz ref + } + assert refclk_freq in adpll_config, "Unsupported refclk_freq (use 100e6 or 125e6)." + cfg = adpll_config[refclk_freq] + + serdes_params = dict( + # Global SERDES configuration + p_SERDES_ENABLE = 1, + p_SERDES_AUTO_INIT = 0, + p_SERDES_TESTMODE = 1, + # ADPLL (PLL) configuration + p_PLL_EN_ADPLL_CTRL = 1, + p_PLL_CONFIG_SEL = 1, #0 :internal, 1: regfile + p_PLL_REF_SEL = 1, # 1 = LVDS reference (expects diff ref clock, or internal calibration if none) + p_PLL_REF_BYPASS = 0, + p_PLL_REF_RTERM = 1, + p_PLL_FCNTRL = cfg['fcntrl'], + p_PLL_MAIN_DIVSEL = cfg['main_divsel'], + p_PLL_OUT_DIVSEL = cfg['out_divsel'], + p_PLL_CI = 3, + p_PLL_CP = 80, + p_PLL_AO = 0, + p_PLL_SCAP = 0, + p_PLL_FILTER_SHIFT = 2, + p_PLL_SAR_LIMIT = 2, + p_PLL_FT = 512, + p_PLL_OPEN_LOOP = 0, + p_PLL_SCAP_AUTO_CAL = 1, + p_PLL_SET_OP_LOCK = 0, + p_PLL_ENFORCE_LOCK = 0, + p_PLL_DISABLE_LOCK = 0, + p_PLL_LOCK_WINDOW = 1, + p_PLL_FAST_LOCK = 1, + p_PLL_SYNC_BYPASS = 0, + p_PLL_PFD_SELECT = 0, + p_PLL_REF_RTERM = 1, + #TX + p_TX_SEL_PRE = 0, + p_TX_SEL_POST = 0, + p_TX_AMP = 0XF, + + p_TX_BRANCH_EN_PRE = 0, + p_TX_BRANCH_EN_MAIN = 0x3F, + p_TX_BRANCH_EN_POST = 0, + p_TX_TAIL_CASCODE = 0x4, + p_TX_DC_ENABLE = 0x3F, + p_TX_DC_OFFSET = 0x8, # note: set to 8 + p_TX_CM_RAISE = 0x0, + p_TX_CM_THRESHOLD_0 = 0xE, + p_TX_CM_THRESHOLD_1 = 0x10, + p_TX_SEL_PRE_EI = 0x0, + p_TX_SEL_POST_EI = 0x0, + p_TX_AMP_EI = 0xF, + p_TX_BRANCH_EN_PRE_EI = 0x0, + p_TX_BRANCH_EN_MAIN_EI = 0x3F, + p_TX_BRANCH_EN_POST_EI = 0x0, + p_TX_TAIL_CASCODE_EI = 0x4, + p_TX_DC_ENABLE_EI = 0x3F, + p_TX_DC_OFFSET_EI = 0x0, + p_TX_CM_RAISE_EI = 0x0, + p_TX_CM_THRESHOLD_0_EI = 0xE, + p_TX_CM_THRESHOLD_1_EI = 0x10, + p_TX_SEL_PRE_RXDET = 0x0, + p_TX_SEL_POST_RXDET = 0x0, + p_TX_AMP_RXDET = 0xF, + p_TX_BRANCH_EN_PRE_RXDET = 0x0, + p_TX_BRANCH_EN_MAIN_RXDET = 0x3F, + p_TX_BRANCH_EN_POST_RXDET = 0x0, + p_TX_TAIL_CASCODE_RXDET = 0x4, + p_TX_DC_ENABLE_RXDET =0x3F, + p_TX_DC_OFFSET_RXDET = 0x0, + p_TX_CM_RAISE_RXDET = 0x0, + p_TX_CM_THRESHOLD_0_RXDET = 0xE, + p_TX_CM_THRESHOLD_1_RXDET = 0x10, + p_TX_CALIB_EN = 0x0, + p_TX_CALIB_OVR = 0x0, + p_TX_CALIB_VAL = 0x0, + p_TX_CM_REG_KI = 0x80, + p_TX_CM_SAR_EN = 0x0, + p_TX_CM_REG_EN = 0x1, + + p_TX_PCS_RESET_OVR=0x0, + p_TX_PCS_RESET=0x0, + p_TX_PMA_RESET_OVR=0x0, + p_TX_PMA_RESET=0x0, + p_TX_RESET_OVR=0x0, + p_TX_RESET=0x0, + p_TX_LOOPBACK_OVR=0x0, + p_TX_DETECT_RX_OVR=0x0, + p_TX_DETECT_RX=0x0, + p_TX_DATA_OVR=0x0, + p_TX_DATA_CNT=0x0, + p_TX_DATA_VALID=0x0, + # ADPLL BISC (Background calibration for PLL) + p_PLL_BISC_MODE = 5, + p_PLL_BISC_TIMER_MAX = 15, + p_PLL_BISC_OPT_DET_IND = 0, + p_PLL_BISC_PFD_SEL = 0, + p_PLL_BISC_DLY_DIR = 0, + p_PLL_BISC_COR_DLY = 1, + p_PLL_BISC_CAL_SIGN = 0, + p_PLL_BISC_CAL_AUTO = 1, + p_PLL_BISC_CP_MIN = 6, + p_PLL_BISC_CP_MAX = 30, + p_PLL_BISC_CP_START = 6, + p_PLL_BISC_DLY_PFD_MON_REF = 0, + p_PLL_BISC_DLY_PFD_MON_DIV = 2, + # 8b/10b settings (bypass internal encoder/decoder) + p_TX_8B10B_EN_OVR = 0, p_TX_8B10B_EN = 0, + p_RX_8B10B_EN_OVR = 0, p_RX_8B10B_EN = 0, + p_RX_8B10B_BYPASS = 0x00, + # Data path width selection: 0 = 20-bit (1:2 gearbox) + p_TX_DATAPATH_SEL = 0, + p_RX_DATAPATH_SEL = 0, + # Reset timings + p_TX_PMA_RESET_TIME = 3, p_TX_PCS_RESET_TIME = 3, + p_RX_PMA_RESET_TIME = 3, p_RX_PCS_RESET_TIME = 3, + p_RX_RESET_TIMER_PRESC = 0, p_RX_RESET_DONE_GATE = 0, + # Electrical idle / power-down (TX/RX always on in this test) + p_TX_POWER_DOWN_OVR = 0, p_TX_POWER_DOWN_N = 1, + p_RX_POWER_DOWN_OVR = 0, p_RX_POWER_DOWN_N = 1, + p_TX_ELEC_IDLE_OVR = 0, p_TX_ELEC_IDLE = 0, + # Polarity control + p_TX_POLARITY_OVR = 0, p_TX_POLARITY = 0, + p_RX_POLARITY_OVR = 0, p_RX_POLARITY = 0, + # Comma alignment + p_RX_COMMA_DETECT_EN_OVR = 0, + p_RX_COMMA_DETECT_EN = 0, + p_RX_ALIGN_COMMA_WORD = 3, + p_RX_ALIGN_COMMA_ENABLE = 0x3FF, + p_RX_ALIGN_MCOMMA_VALUE = 0x283, + p_RX_ALIGN_PCOMMA_VALUE = 0x17C, + p_RX_MCOMMA_ALIGN_OVR = 0, p_RX_MCOMMA_ALIGN = 0, + p_RX_PCOMMA_ALIGN_OVR = 0, p_RX_PCOMMA_ALIGN = 0, + p_RX_SLIDE_MODE = 0, p_RX_SLIDE = 0, + p_RX_BYTE_REALIGN = 1, + # Clock correction + p_RX_CLKCOR_USE = 0, + p_RX_CLKCOR_MIN_LAT= 32, p_RX_CLKCOR_MAX_LAT = 39, + p_RX_CLKCOR_SEQ_1_0= 0x1F7, p_RX_CLKCOR_SEQ_1_1=0x1F7, + p_RX_CLKCOR_SEQ_1_2= 0x1F7, p_RX_CLKCOR_SEQ_1_3=0x1F7, + # CDR configuration + p_RX_WAIT_CDR_LOCK = 0, + p_RX_CDR_FORCE_LOCK= 1, + p_RX_CDR_RESET_TIME= 3, + p_RX_CDR_CKP = 0xF8, + p_RX_CDR_CKI = 0x00, + p_RX_CDR_TRANS_TH = 128, + p_RX_CDR_LOCK_CFG = 0x0B, + p_RX_CDR_FREQ_ACC = 0, + p_RX_CDR_PHASE_ACC = 0, + p_RX_CDR_SET_ACC_CONFIG = 0, + p_RX_CDR_RESET_OVR = 0, p_RX_CDR_RESET = 0, + # RX Equalizer + p_RX_EN_EI_DETECTOR_OVR = 0, p_RX_EN_EI_DETECTOR = 0, + p_RX_EI_BIAS = 4, p_RX_EI_BW_SEL = 4, + p_RX_AFE_PEAK = 0xF, p_RX_AFE_GAIN = 0x8, p_RX_AFE_VCMSEL = 0x4, + p_RX_CALIB_EN = 1, p_RX_CALIB_OVR = 0, p_RX_CALIB_VAL = 0, + p_RX_RTERM_VCMSEL = 4, p_RX_RTERM_PD = 0, + p_RX_EQA_RESET_TIME = 3, p_RX_EQA_RESET_OVR = 0, p_RX_EQA_RESET = 0, + p_RX_EQA_CKP_LF = 0xA3, p_RX_EQA_CKP_HF = 0xA3, + p_RX_EQA_CKP_OFFSET = 0x01, + p_RX_EN_EQA = 0, p_RX_EQA_LOCK_CFG = 0, + p_RX_TH_MON1 = 8, p_RX_TH_MON2 = 8, + p_RX_TAPW = 8, p_RX_AFE_OFFSET = 8, + p_RX_EQA_CONFIG = 0x01C0, p_RX_MON_PH_OFFSET = 0, + # PRBS + p_TX_PRBS_OVR = 0, p_TX_PRBS_SEL = 0, p_TX_PRBS_FORCE_ERR = 0, + p_RX_PRBS_OVR = 0, p_RX_PRBS_SEL = 0, p_RX_PRBS_CNT_RESET = 0, + # Loopback configuration + p_TX_PMA_LOOPBACK = 0, p_TX_PCS_LOOPBACK = 0, + p_RX_PMA_LOOPBACK = 0, p_RX_PCS_LOOPBACK = 0, + p_RX_BUF_RESET_TIME = 0x3, + p_RX_EN_EQA_EXT_VALUE = 0x0, + p_RX_EYE_MEAS_EN =0x0, + p_RX_EYE_MEAS_CFG = 0, + p_RX_DATA_SEL = 0x0, + p_RX_BUF_BYPASS = 0x0, + p_RX_LOOPBACK_OVR= 0x0, + p_RX_RESET_OVR= 0x0, + p_RX_RESET= 0x0, + p_RX_PMA_RESET_OVR= 0x0, + p_RX_PMA_RESET= 0x0, + p_RX_PCS_RESET_OVR=0x0, + p_RX_PCS_RESET= 0x0, + p_RX_BUF_RESET_OVR= 0x0, + p_RX_BUF_RESET= 0x0, + ) + # SERDES I/O port connections + serdes_params.update( + # Clocks & loopback + i_TX_CLK_I = ClockSignal("tx_half"), + i_RX_CLK_I = ClockSignal("rx"), + o_PLL_CLK_O = self.txoutclk, + o_RX_CLK_O = self.rxoutclk, + i_LOOPBACK_I = 0b010 if internal_loopback else 0b000, + + # Resets + i_TX_RESET_I = tx_reset, + i_RX_RESET_I = rx_reset, + i_RX_PMA_RESET_I = 0, + i_RX_EQA_RESET_I = 0, + i_RX_CDR_RESET_I = 0, + i_RX_PCS_RESET_I = 0, + i_RX_BUF_RESET_I = 0, + i_TX_PCS_RESET_I = 0, + i_TX_PMA_RESET_I = 0, + i_PLL_RESET_I = pll_reset, + + # TX data & controls + i_TX_DATA_I = Cat(tx_bus[0:8], tx_bus[10:18]), + i_TX_CHAR_IS_K_I = 0, + i_TX_CHAR_DISPMODE_I = Cat(tx_bus[9], tx_bus[23]), + i_TX_CHAR_DISPVAL_I = Cat(tx_bus[8], tx_bus[22]), + i_TX_POWER_DOWN_N_I = 1, + i_TX_POLARITY_I = tx_polarity, + i_TX_ELEC_IDLE_I = 0, + i_TX_DETECT_RX_I = 1, + i_TX_PRBS_SEL_I = _tx_prbs_config, + i_TX_PRBS_FORCE_ERR_I = _tx_prbs_force_err, + + o_TX_RESET_DONE_O = tx_reset_done, + o_TX_BUF_ERR_O = tx_buf_err, + o_TX_DETECT_RX_DONE_O = tx_detect_rx_done, + o_TX_DETECT_RX_PRESENT_O = tx_detect_rx_present, + + # RX data & controls + i_RX_POWER_DOWN_N_I = 1, + i_RX_POLARITY_I = rx_polarity, + i_RX_EN_EI_DETECTOR_I = 0, + i_RX_COMMA_DETECT_EN_I = rx_comma_detect_en, + i_RX_SLIDE_I = 0, + i_RX_MCOMMA_ALIGN_I = rx_comma_detect_en, + i_RX_PCOMMA_ALIGN_I = rx_comma_detect_en, + i_RX_PRBS_SEL_I = _rx_prbs_config, + i_RX_PRBS_CNT_RESET_I = _rx_prbs_pause, + + o_RX_DATA_O = Cat(rx_bus[0:8], rx_bus[10:18]), + o_RX_PRBS_ERR_O = rx_prbs_err, + o_RX_BUF_ERR_O = rx_buf_err, + o_RX_RESET_DONE_O = rx_reset_done, + + # register file + i_REGFILE_CLK_I = 0, + i_REGFILE_WE_I = 0, + i_REGFILE_EN_I = 0, + i_REGFILE_ADDR_I = 0, + i_REGFILE_DI_I = 0, + i_REGFILE_MASK_I = 0, + o_REGFILE_DO_O = regfile_do, + o_REGFILE_RDY_O = regfile_rdy, + ) + + # Connect SERDES to physical I/O pads if provided + if tx_pads is not None and hasattr(tx_pads, "p"): + serdes_params.update({o_TXP: tx_pads.p, o_TXN: tx_pads.n}) + if rx_pads is not None and hasattr(rx_pads, "p"): + serdes_params.update({i_RXP: rx_pads.p, i_RXN: rx_pads.n}) + # Instantiate the CC_SERDES primitive with all parameters + self.specials += Instance("CC_SERDES", **serdes_params) + def add_stream_endpoints(self): + + # Create stream endpoints for data (each with nwords*8 data bits and nwords control bits for K) + self.sink = stream.Endpoint([("data", 8*self.nwords), ("ctrl", self.nwords)]) + self.source = stream.Endpoint([("data", 8*self.nwords), ("ctrl", self.nwords)]) + + self.comb += self.sink.ready.eq(1) + self.comb += self.source.valid.eq(1) + for i in range(self.nwords): + self.comb += [ + self.encoder.d[i].eq(self.sink.data[8*i:8*(i+1)]), + self.encoder.k[i].eq(self.sink.ctrl[i]) + ] + self.sync.rx += [ + self.source.data[8*i:8*(i+1)].eq(self.decoders[i].d), + self.source.ctrl[i].eq(self.decoders[i].k) + ] + def add_controls(self, auto_enable=True): + self._tx_enable = CSRStorage(fields=[CSRField("enable", size=1, reset=int(auto_enable), description="TX Enable")]) + self._rx_enable = CSRStorage(fields=[CSRField("enable", size=1, reset=int(auto_enable), description="RX Enable")]) + self._tx_ready = CSRStatus(fields=[CSRField("ready", size=1, description="TX Ready (PLL/SerDes locked)")]) + self._rx_ready = CSRStatus(fields=[CSRField("ready", size=1, description="RX Ready (CDR locked)")]) + self._tx_prbs_config = CSRStorage(size=2, description="TX PRBS Configuration (0: PRBS off)") + self._rx_prbs_config = CSRStorage(size=2, description="RX PRBS Configuration (must match TX)") + self._rx_prbs_pause = CSRStorage(size=1, description="Pause RX PRBS Checker") + self._rx_prbs_errors = CSRStatus(32, description="RX PRBS Error Count") + self.comb += [ + self.tx_enable.eq(self._tx_enable.fields.enable), + self.rx_enable.eq(self._rx_enable.fields.enable), + self._tx_ready.fields.ready.eq(self.tx_ready), + self._rx_ready.fields.ready.eq(self.rx_ready), + self.tx_prbs_config.eq(self._tx_prbs_config.storage), + self.rx_prbs_config.eq(self._rx_prbs_config.storage), + self.rx_prbs_pause.eq(self._rx_prbs_pause.storage), + self._rx_prbs_errors.status.eq(self.rx_prbs_errors) + ] diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/platforms/colognechip_gatemate_evb.py b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/platforms/colognechip_gatemate_evb.py new file mode 100644 index 0000000000000000000000000000000000000000..d0a066d0467ed0c8c83423df884e1fe8c40f0804 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/platforms/colognechip_gatemate_evb.py @@ -0,0 +1,141 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2023 Gwenhael Goavec-merou +# SPDX-License-Identifier: BSD-2-Clause + +# Board documentation/schematics: +# https://colognechip.com/docs/ds1003-gatemate1-evalboard-3v1-latest.pdf + +from litex.build.generic_platform import * +from litex.build.colognechip.platform import CologneChipPlatform +from litex.build.openfpgaloader import OpenFPGALoader + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("clk10", 0, Pins("IO_SB_A8"), Misc("SCHMITT_TRIGGER=true")), + + # Leds + ("user_led_n", 0, Pins("IO_EB_B1")), + ("user_led_n", 1, Pins("IO_EB_B2")), + ("user_led_n", 2, Pins("IO_EB_B3")), + ("user_led_n", 3, Pins("IO_EB_B4")), + ("user_led_n", 4, Pins("IO_EB_B5")), + ("user_led_n", 5, Pins("IO_EB_B6")), + ("user_led_n", 6, Pins("IO_EB_B7")), + ("user_led_n", 7, Pins("IO_EB_B8")), + + # Button + ("user_btn_n", 0, Pins("IO_EB_B0")), + + # SPIFlash + ("spiflash", 0, + Subsignal("cs_n", Pins("IO_WA_A8")), + Subsignal("clk", Pins("IO_WA_B8")), + Subsignal("miso", Pins("IO_WA_B7")), + Subsignal("mosi", Pins("IO_WA_A7")), + Subsignal("wp", Pins("IO_WA_B6")), + Subsignal("hold", Pins("IO_WA_B6")), + ), + ("spiflash4x", 0, + Subsignal("cs_n", Pins("IO_WA_A8")), + Subsignal("clk", Pins("IO_WA_B8")), + Subsignal("dq", Pins("IO_WA_B7 IO_WA_A7 IO_WA_B6 IO_WA_B6")), + ), + + # HyperRAM + ("hyperram", 0, + Subsignal("dq", Pins("IO_WB_A5 IO_WB_B5 IO_WB_A6 IO_WB_B6 IO_WB_A7 IO_WB_B7 IO_WB_A8 IO_WB_B8")), + Subsignal("rwds", Pins("IO_WB_B4")), + Subsignal("cs_n", Pins("IO_WB_B0")), + Subsignal("rst_n", Pins("IO_WB_A2")), + Subsignal("clk_p", Pins("IO_WB_A3")), + Subsignal("clk_n", Pins("IO_WB_B3")), + ), +] + +# Connectors --------------------------------------------------------------------------------------- + +_connectors = [ + ("PMODA", "IO_NB_A0 IO_NB_A1 IO_NB_A2 IO_NB_A3 IO_NB_B0 IO_NB_B1 IO_NB_B2 IO_NB_B3"), + ("PMODB", "IO_NB_A4 IO_NB_A5 IO_NB_A6 IO_NB_A7 IO_NB_B4 IO_NB_B5 IO_NB_B6 IO_NB_B7"), + ("io_na", "IO_NA_A0 IO_NA_B0", + "IO_NA_A1 IO_NA_B1", + "IO_NA_A2 IO_NA_B2", + "IO_NA_A3 IO_NA_B3", + "IO_NA_A4 IO_NA_B4", + "IO_NA_A5 IO_NA_B5", + "IO_NA_A6 IO_NA_B6", + "IO_NA_A7 IO_NA_B7", + "IO_NA_A8 IO_NA_B8"), + ("io_nb", "IO_NB_A4 IO_NB_A5", + "IO_NB_A6 IO_NB_A7", + "IO_NB_B4 IO_NB_B5", + "IO_NB_B6 IO_NB_B7"), + ("io_ea", "IO_EA_A0 IO_EA_B0", + "IO_EA_A1 IO_EA_B1", + "IO_EA_A2 IO_EA_B2", + "IO_EA_A3 IO_EA_B3", + "IO_EA_A4 IO_EA_B4", + "IO_EA_A5 IO_EA_B5", + "IO_EA_A6 IO_EA_B6", + "IO_EA_A7 IO_EA_B7", + "IO_EA_A8 IO_EA_B8"), + ("io_sa", "IO_SA_A0 IO_SA_B0", + "IO_SA_A1 IO_SA_B1", + "IO_SA_A2 IO_SA_B2", + "IO_SA_A3 IO_SA_B3", + "IO_SA_A4 IO_SA_B4", + "IO_SA_A5 IO_SA_B5", + "IO_SA_A6 IO_SA_B6", + "IO_SA_A7 IO_SA_B7", + "IO_SA_A8 IO_SA_B8"), + ("io_sb", "IO_SB_A0 IO_SB_B0", + "IO_SB_A1 IO_SB_B1", + "IO_SB_A2 IO_SB_B2", + "IO_SB_A3 IO_SB_B3", + "IO_SB_A4 IO_SB_B4", + "IO_SB_A5 IO_SB_B5", + "IO_SB_A6 IO_SB_B6", + "IO_SB_A7 IO_SB_B7", + "IO_SB_A8 IO_SB_B8"), + + ("io_wc", "IO_WC_A0 IO_WC_B0", + "IO_WC_A1 IO_WC_B1", + "IO_WC_A2 IO_WC_B2", + "IO_WC_A3 IO_WC_B3", + "IO_WC_A4 IO_WC_B4", + "IO_WC_A5 IO_WC_B5", + "IO_WC_A6 IO_WC_B6", + "IO_WC_A7 IO_WC_B7", + "IO_WC_A8 IO_WC_B8"), +] + +# PMODS -------------------------------------------------------------------------------------------- + +def usb_pmod_io(pmod): + return [ + # USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/ + ("usb_uart", 0, + Subsignal("tx", Pins(f"{pmod}:1")), + Subsignal("rx", Pins(f"{pmod}:2")), + ), + ] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(CologneChipPlatform): + default_clk_name = "clk10" + default_clk_period = 1e9/10e6 + + def __init__(self, toolchain="colognechip"): + CologneChipPlatform.__init__(self, "CCGM1A1", _io, _connectors, toolchain=toolchain) + + def create_programmer(self): + return OpenFPGALoader("gatemate_evb_jtag") + + def do_finalize(self, fragment): + CologneChipPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk10", loose=True), 1e9/10e6) diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/targets/colognechip_gatemate_evb.py b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/targets/colognechip_gatemate_evb.py new file mode 100644 index 0000000000000000000000000000000000000000..a6928708fd636075ec8ab87e242c017c3394d842 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/targets/colognechip_gatemate_evb.py @@ -0,0 +1,123 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2023 Gwenhael Goavec-merou +# SPDX-License-Identifier: BSD-2-Clause + +from migen import * + +from litex.gen import * + +from litex_boards.platforms import colognechip_gatemate_evb + +from litex.build.io import CRG + +from litex.soc.cores.clock.colognechip import GateMatePLL +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from litex.build.generic_platform import Pins + +from litex.soc.cores.led import LedChaser + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(LiteXModule): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + rst_n = Signal() + self.cd_sys = ClockDomain() + + # # # + + # Clk / Rst + clk10 = platform.request("clk10") + self.rst = ~platform.request("user_btn_n", 0) + + self.specials += Instance("CC_USR_RSTN", o_USR_RSTN = rst_n) + + # PLL + self.pll = pll = GateMatePLL(perf_mode="economy") + self.comb += pll.reset.eq(~rst_n | self.rst) + pll.register_clkin(clk10, 10e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=48e6, + # with_led_chaser = False, + with_serdes=False, + **kwargs): + platform = colognechip_gatemate_evb.Platform() + + # USBUART PMOD as Serial-------------------------------------------------------------------- + platform.add_extension(colognechip_gatemate_evb.usb_pmod_io("PMODB")) + kwargs["uart_name"] = "usb_uart" + + # CRG -------------------------------------------------------------------------------------- + self.crg = _CRG(platform, sys_clk_freq) + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on GateMate EVB", **kwargs) + + # Leds ------------------------------------------------------------------------------------- + # if with_led_chaser: + # self.leds = LedChaser( + # pads = platform.request_all("user_led_n"), + # sys_clk_freq = sys_clk_freq) + + if with_serdes: + from liteiclink.serdes.serdes_gm import SerDesGM + serdes = SerDesGM(sys_clk_freq=sys_clk_freq, + refclk_freq=125e6, + linerate=1.25e9, + internal_loopback=False) + self.submodules += serdes + serdes.add_stream_endpoints() + serdes.add_controls() + leds = platform.request_all("user_led_n") + self.comb += [ + leds[0].eq(serdes.rx_reset_done_n), # LED0 ← RX_RESET_DONE_O_N + leds[1].eq(serdes.tx_reset_done_n), # LED1 ← TX_RESET_DONE_O_N + leds[2].eq(serdes.tx_detect_rx_done_n), # LED2 ← TX_DETECT_RX_DONE_O_N + leds[3].eq(serdes.tx_detect_rx_present_n), # LED3 ← TX_DETECT_RX_PRESENT_O_N + leds[4].eq(serdes.rx_prbs_err_n), # LED4 ← RX_PRBS_ERR_O_N + leds[5].eq(serdes.rx_buf_err_n), # LED5 ← RX_BUF_ERR_O_N + leds[6].eq(serdes.tx_buf_err_n), # LED6 ← TX_BUF_ERR_O_N + leds[7].eq(~serdes.tx_ready) # LED7 ← “ADPLL locked” indicator + ] + + +# Build -------------------------------------------------------------------------------------------- + +def main(): + from litex.build.parser import LiteXArgumentParser + parser = LiteXArgumentParser(platform=colognechip_gatemate_evb.Platform, description="LiteX SoC on Gatemate EVB") + parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.") + parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") + parser.add_target_argument("--with-serdes", action="store_true", help="Enable SERDES (1.25 Gbps transceiver loopback test).") + args = parser.parse_args() + + + soc = BaseSoC( + sys_clk_freq = args.sys_clk_freq, + with_serdes = args.with_serdes, + **parser.soc_argdict) + builder = Builder(soc, **parser.builder_argdict) + if args.build: + builder.build(**parser.toolchain_argdict) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(builder.get_bitstream_filename(mode="sram")) + + if args.flash: + from litex.build.openfpgaloader import OpenFPGALoader + prog = OpenFPGALoader("gatemate_evb_spi") + prog.flash(0, builder.get_bitstream_filename(mode="flash")) + +if __name__ == "__main__": + main() diff --git a/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/README.md b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/README.md new file mode 100644 index 0000000000000000000000000000000000000000..c3be99bed4ac2eec259fdef2e19f15f5c207b5f4 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/2.liteiclink/README.md @@ -0,0 +1,148 @@ +# Lite IC Link +## Block Diagram + +``` + ┌────────────────────────────────────────────────────────────────────────────┐ + │ sys_clk Domain │ + │────────────────────────────────────────────────────────────────────────────│ + │ • Inputs: │ + │ – sys_clk │ + │ – CSR writes: _tx_enable(1), _rx_enable(1), │ + │ _tx_prbs_config(2), _rx_prbs_config(2), _rx_prbs_pause(1) │ + │ • CSRStatus reads: _tx_ready(1), _rx_ready(1), _rx_prbs_errors(32) │ + │ • MultiReg synchronizers → “tx” and “rx” clock domains │ + │ • Reset & Lock FSM: │ + │ - reset_cnt → adpll_reset │ + │ - lock_cnt → cdr_locked │ + │ - drives tx_reset_done → tx_ready, rx_reset_done → rx_ready │ + └──────────────────────────────────┬─────────────────────────────────────────┘ + | + ┌───────────────────────────┐ | ┌───────────────────────────┐ + │ Clock Buffering | | │ Clock Buffering | + │───────────────────────────| | │───────────────────────────| + │ • Instance CC_BUFG: |◀────────┘───────────────▶│ • Instance CC_BUFG: | + | - txoutclk → cd_tx.clk │ | - rxoutclk → cd_rx.clk │ + └────────────┬──────────────┘ └─────────────┬─────────────┘ + | | +┌───────────────────────────────────▼──────────────────────┐ ┌────────────────────────────▼─────────────────────────────┐ +│ cd_tx Domain | │ cd_rx Domain | +│──────────────────────────────────────────────────────────| │──────────────────────────────────────────────────────────| +│ 1) 8b/10b Encoder (ClockDomainsRenamer “tx”) | │ 1) Bus Unpacking │ +│ – Inputs: sink.data[8·nbytes], sink.ctrl[nbytes] │ │ – rx_data[8*i:8*(i+1)] ← rx_bus[8*i:8*(i+1)] | +│ – Outputs: encoder.output (10-bit symbols + K flags) │ │ – disp_flags (K bits) | +│ │ │ │ +│ 2) PRBSTX │ │ 2) PRBSRX │ +│ – i ← encoder.output │ │ – i ← rx_data │ +│ – config ← synced tx_prbs_config │ │ – config ← synced rx_prbs_config │ +│ – o → PRBS bit-stream │ │ – errors → MultiReg → sys_clk (rx_prbs_errors) │ +│ │ │ │ +│ 3) Datapath MUX │ │ 3) 8b/10b Decoders │ +│ – If prbs_config ≠ 0: tx_data ← PRBS.o │ │ – d,i ← rx_data, disp_flags │ +│ Else: tx_data ← encoder.output | │ – outputs: decoder.d → source.data, | +| | | decoder.k → source.ctrl │ +| │ │ 4) source.valid = 1 │ +│ 4) Bus Packin │ └─────────────────────────┬────────────────────────────────┘ +│ – tx_bus[8*i:8*(i+1)] ← tx_data[8*i:8*(i+1) │ | +│ │ | +│ 5) sink.ready = 1 | | +└─────────────────────────┬────────────────────────────────┘ | + | | + | | + | | + | | + ┌───────────▼────────────────────────────────────────────────────────────────▼───────────────┐ + │ CC_SERDES Primitive │ + │────────────────────────────────────────────────────────────────────────────────────────────│ + │ • Params p_PLL_…, p_TX_…, p_RX_…, loopback, 8b/10b enable, comma align… │ + │ │ + │ • Clocks & resets: │ + │ – i_TX_CLK_I = cd_tx.clk │ + │ – i_TX_RESET_I = tx_reset (from FSM) │ + │ – o_TX_RESET_DONE_O → tx_reset_done │ + │ – o_PLL_CLK_O → txoutclk │ + │ – i_RX_CLK_I = cd_rx.clk │ + │ – i_RX_RESET_I = rx_reset │ + │ – o_RX_RESET_DONE_O → rx_reset_done │ + │ – o_RX_CLK_O → rxoutclk │ + │ │ + │ • Data I/O: │ + │ – i_TX_DATA_I = tx_bus │ + │ – o_RX_DATA_O = rx_bus │ + │ – i_LOOPBACK_I = internal_loopback ? 0b010 : 0b000 │ + │ │ + │ • Physical pads (optional): │ + │ – o_TXP/o_TXN │ + │ – i_RXP/i_RXN │ + └────────────────────────────────────────────────────────────────────────────────────────────┘ + + + ┌─────────────────────────────────────────────────────────────────────────────────────────────────────────┐ + │ Stream Interface │ + │─────────────────────────────────────────────────────────────────────────────────────────────────────────│ + │ • sink Endpoint (sys_clk): │ + │ – data[8·nbytes] → cd_tx.encoder.d │ + │ – ctrl[nbytes] → cd_tx.encoder.k │ + │ – ready = 1 │ + │ • source Endpoint (cd_rx): │ + │ – data[8·nbytes] ← cd_rx.decoder.d │ + │ – ctrl[nbytes] ← cd_rx.decoder.k │ + │ – valid = 1 │ + └─────────────────────────────────────────────────────────────────────────────────────────────────────────┘ + +``` + + +## Workflow Overview +First, let’s dive into the 2.liteiclink folder and walk through its structure so you can see how each component fits together and how the overall build process comes together + +### 2.sw + +In the [2.sw](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/2.sw) is a modified version of the [LiteX Demo Application](https://github.com/enjoy-digital/litex/tree/master/litex/soc/software/demo) that will include generated CSR from the migen target file in the `main.c` function. There lie the control function for the datapath in the bare-metal C. +The UART console is built upon the official demo application. + +### 3.build + +Here in the [3.build](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/3.build) folder we have the [Makefile](https://github.com/chili-chips-ba/openCologne/blob/main/7.SerDes/2.liteiclink/3.build/Makefile) that divides the LiteX workflow into different parts. Running `make help` gives self-exmplanatory commands: + +``` +$ make help +Usage: + make open-target file= + make open-example file= + make build-board [FREQ=..] [OPTIONS='..'] + make load [FREQ=..] [OPTIONS='..'] + make term [PORT=..] + make build-sw [DEMO_FLAGS='..'] + make sim + make view-sim + make clean-sim + make setup-ethernet [ETH_IFACE=..] [STATIC_IP=..] + make start-server + make stop-server + make litescope + make clean + make copy-migen +``` + +The most important ones are: + +* `make build-board` which runs the build process using Vivado (openXC7 might also be used later on). The command has parameters `FREQ` and `OPTIONS` which can be overloaded. + +* `make build-sw` which compiles the bare-metal C application. The imporant note to add is to run the command after the build finishes because the compiler depends of the generated files in the `3.build/build` folder. + +* `make load` simply loads the bitstream onto the FPGA via the JTAG programmer + +* `make term` opens up the serial console in the terminal to control the datapth signals. The default port is `/dev/ttyUSB0` while that can be simply changed with `PORT`. + +**NOTE**: Run `make term` in a seperate terminal before running `make load` + +### 4.migen +The [4.migen](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen) folder contains two subfolders: + +* [liteiclink](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/liteiclink/serdes) which has the file that should be copied in the liteiclink litex folder + +* [litex_boards](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards) which has: + [platforms](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/platforms) which has the specific platform file that specifies the pins of the board + [targets](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/2.liteiclink/4.migen/litex/litex-boards/litex_boards/targets) has the target file that specifies all of the important parts of the CPU design and instantiates the SoC. + +**NOTE**: Right now you need to copy these subfolders with the files manually in your LiteX installation folder in `litex/litex_board/litex-boards`. diff --git a/chili-chips-ba_openCologne/7.SerDes/README.md b/chili-chips-ba_openCologne/7.SerDes/README.md new file mode 100644 index 0000000000000000000000000000000000000000..c52ba3d539e5448e7c5cc4b3fbbf17521a217ef7 --- /dev/null +++ b/chili-chips-ba_openCologne/7.SerDes/README.md @@ -0,0 +1,57 @@ +# SerDes App for GateMate + +Design a high-speed serial, **memory-mapped Chip-to-Chip (C2C) Interconnect**. The goal of such IP is to set the stage for creating compute clusters and Hyper Cubes made of GateMate FPGAs, all physically interconnected with SerDes, with this C2C on top of it, serving as logical and transport layer. + +## References: +- CologneChip [SerDes example design](https://github.com/pu-cc/gm_serdes_lb) and latest [datasheet](https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf) +- Xilinx PG046 - [Aurora 8B/10B](https://docs.amd.com/r/en-US/pg046-aurora-8b10b/Introduction?tocId=Tqe8wtK9r1zAUq13hUnVEw) + - Xilinx SP002 - [Aurora 8B/10B Protocol Spec](https://docs.amd.com/v/u/en-US/aurora_8b10b_protocol_spec_sp002) +- BerkeleyLab [ChitChat](https://berkeleylab.github.io/Bedrock/_gen_md/serial_io/chitchat/README_md.html) protocol +- LiteX [IC Link](https://github.com/enjoy-digital/liteiclink) +- [MesaBusProtocol](https://github.com/blackmesalabs/MesaBusProtocol) +- [Transputer](http://www.bitsavers.org/components/inmos/transputer/C011_Link_Adaptor.pdf) +- [LiteX 1000basex](https://github.com/pu-cc/liteeth/tree/gatemate1000basex) +- [Seding Data Structures from chip to chip](https://www.reddit.com/r/FPGA/comments/1m8gl5o/how_to_send_a_struct_from_one_dev_board_to_another) + +- Timing-aware/better PNR for this high-speed design: + - [Project Peppercorn](https://github.com/YosysHQ/prjpeppercorn) + - [nextpnr for GateMate](https://github.com/YosysHQ/nextpnr/tree/gatemate) + +- Primer on [Eye Diagrams](https://incompliancemag.com/eye-diagram-part1) and [Equivalent Time Sampling](https://www.tek.com/en/documents/application-note/real-time-versus-equivalent-time-sampling) (vs. real-time) + +

+ +

+ +- Gowin primer on SerDes Signal Integrity ([SI](https://www.gowinsemi.com/en/market/market_detail/48)) measurements + +- Altera [Serial Link Analyzer](https://www.altera.com/products/development-tools/quartus-prime/advanced-link-analyzer) + +- Xilinx UG908 - In-System [IBERT](https://docs.amd.com/r/en-US/ug908-vivado-programming-debugging/Using-Vivado-Serial-I/O-Analyzer-to-Debug-the-Design) + + +## Plan of Record +Having thoroughly studied all options, the developers presented them in a project meeting on _July 11, 2025_, where team unanimously decided for the GateMate Chip2Chip SerDes: +- not to mimic the semi-proprietary _Xilinx/AMD Aurora_ +- not to be based on _BerkeleyLab ChitChat_ +- not to be based on _MesaBusProtocol_ +- not to invent _our own scheme_ (which was the original plan of Chili.CHIPS*ba developers) +- but rather to port `LiteX IC Link`, thus honoring CologneChip guidance and strong preference **<== WINNER!** + +The _IC Link_ comes with a worked out interface to the CPU. Its interface to SerDes will leverage from Patrick's _1000basex Ethernet MAC_ project. The best part of the _IC Link_ is that it opens the full power of LiteX integration, making it available for CologneChip customers almosts instantly, and so with minimal coding burden. As such, the _IC Link_ is the Chip2Chip interconnect that CologneChip would benefit the most from for their SerDes. + +Given that GateMate proprietary (aka "legacy") PnR is rather unreliable and insensitive to timing constraints, while the new opensource PnR (Project Peppercorn) has already saved the day for our WP9-[BetrustedSOC](https://github.com/chili-chips-ba/openCologne/tree/main/9.BetrustedSOC), the _Chip2Chip SerDes_ will be delivered solely and exclusively for the _nextpnr_. + + +For details on the work completed so far and the planned next steps, please refer to the [4.liteiclink](https://github.com/chili-chips-ba/openCologne/tree/main/7.SerDes/4.liteiclink) section of the repository. + +## Implementation +We strongly recommend to start with standalone [SerDes loopback test](1.serdestool_by_gm/README.md) to get used to the hardware platform, SerDes settings, cabling and work with RF-class signaling in general. + +Then move onto our [Lite IC Link](2.liteiclink/README.md) port for GateMate SerDes. You will find more detail in the respective project folders. + +### Public Announcements +- [2025-08-10](https://www.linkedin.com/feed/update/urn:li:activity:7359764905572376577?commentUrn=urn%3Ali%3Acomment%3A%28activity%3A7359764905572376577%2C7360217016948985856%29&dashCommentUrn=urn%3Ali%3Afsd_comment%3A%287360217016948985856%2Curn%3Ali%3Aactivity%3A7359764905572376577%29) +- [2025-02-21](https://www.linkedin.com/posts/patrick-urban-086177251_gatemate-fpga-colognechip-activity-7298662301677551616-4sw0?utm_source=share&utm_medium=member_desktop&rcm=ACoAAAJv-TcBSi_5ff0VNMrInrT-xg44YF3jnyU) + +### End of Document diff --git a/chili-chips-ba_openCologne/8.StressTest/0.doc/Gowin-Arora/README.md b/chili-chips-ba_openCologne/8.StressTest/0.doc/Gowin-Arora/README.md new file mode 100644 index 0000000000000000000000000000000000000000..8c8483a39224ddd2f9ff553bcbe3495beeb32a12 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/0.doc/Gowin-Arora/README.md @@ -0,0 +1,4 @@ +## Gowin Documentation + +This directory contains documentation for the Gowin-Arora family of FPGAs. They are direct competitors of the GateMate FPGAs. +First you may want to read this [Introductory User Guide by Mouser](https://device.report/manual/4181959). diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/README.md b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/README.md new file mode 100644 index 0000000000000000000000000000000000000000..59fbcc9e9d355a8070ce12f34cf57eb2bf7dc523 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/README.md @@ -0,0 +1,98 @@ +# CORESCORE - how many Servs can a FPGA serv? +## * WORK IN PROGRESS * UNDER CONSTRUCTION * +> WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN' + +This is a popular metric, determining FPGA's logic capacity, routing algortihm and architectural ability to use all of the FPGA. We were able to achieve **54** cores with Fmax of **22.93 MHz**, when using `-tm 3` PnR "worst" timing setting. For comparison GW2AR-18C C8/I7 (20K LUT4) implemented **50** cores at **58 MHz** for worst timing PnR settings, bare in mind that this is a higher speed grade chip **C8/I7**. + +## Results and analysis +### Tools disclosure +Obviously, comparing results obtained pushing the test sources through open-source yosys and propriatary synth isn't an apples to apples comparison. In an attempt to address this difference, and find the real potential of the GateMate's architecture, we conducted a reference yosys benchmark. Results of yosys synthesis are then compared to the "golden standard" propriatary syntehsis tool (Gowin). Later, all results can potentially be adjusted to account for the defficiencies in yosys. We didn't test the PnR tools since usually there are no alternatives. +Through testing, we obtained utilization figures for `1 <= core_count <= 50` for the **Gowin GW2AR-18C FPGA (20k LUT4)**. + +Graphs are indicating a melting lead of propriatary tools, especially percentage-wise, but they still remain superior. The number of DFFs though, is steadily favoring the propriatary synthesis. Coming to an understanding of these results is possible only when we consider also the number of LUTRAM elements used in both implementations. Proprietary synthesis tools optimize resource usage by leveraging LUTRAM, reducing DFF consumption at the cost of additional LUTs. In contrast, Yosys relies on a basic approach using DFFs and LUTs exclusively. This results in higher LUT and DFF utilization in Yosys, as it emulates LUTRAM behavior with standard logic elements. The number of block RAMs remains unchanged and is therefore not shown. In relative perspective, yosys is far worse off for small designs, but the playing field evens out at higher utilization numbers. + +### Takeaway - not so obvious +Propriatary Gowin PnR topped out at 50 cores, utilizing only 11930 / 15750 of avaliable DFFs before reporting "fail to place 64 REGs". Taking this into account, yosys-based design would fail at 41 cores, or even earlier since the LUT usage is also increased. + +Here we face a tough decision, **how to take yosys into account?** On one hand it's just 5% more LUTs and 18% more DFFs, but on the other hand it's prone to failing PnR with 20% less total logic instatiated. Since we're dealing with GateMate in our analysis, whose PnR isn't directly yosys netlist [compatible](https://github.com/chili-chips-ba/openCologne/issues/28#issuecomment-2353907213), from now on we use a 25% correction when assessing results. That would bring 41 yosys cores to 50 propriatary in Gowin. + +![figure1](absutil.png) +![figure1](relutil.png) +### Test results +These tests have been verified on the real system. +``` +Utilization Report + + CPEs 20037 / 20480 ( 97.8 %) + ----------------------------------------------- + CPE Registers 13921 / 40960 ( 34.0 %) + Flip-flops 13921 + Latches 0 + + GPIOs 3 / 144 ( 2.1 %) + ----------------------------------------------- + Single-ended 3 / 144 ( 2.1 %) + IBF 2 + OBF 1 + TOBF 0 + IOBF 0 + + + Block RAMs 26.0 / 32 ( 81.3 %) + ----------------------------------------------- + BRAM_20K 1 / 64 ( 1.6 %) + BRAM_40K 25 / 32 ( 78.1 %) + FIFO_40K 0 / 32 ( 0.0 %) + + PLLs 1 / 4 ( 25.0 %) + GLBs 1 / 4 ( 25.0 %) + SerDes 0 / 1 ( 0.0 %) +``` + +Considering that only 34% of sequential logic is utilized, but all Cologne Programmable Elements (CPEs) are fully utilized, it can be concluded that nearly all combinatorial elements are consumed. This positions the 20.5k CPE CologneChip GateMate FPGA alongside other FPGAs with similar capacities. + + +Notably, the GateMate's architecture, with 20.5k CPEs, effectively provides 41k LUT4 equivalents, as each CPE comprises an 8-input LUT-tree, which can be configured as two 4-input L2T4 primitives. Due to the reduced number of configuration bits required by this architecture, we can compute the normalized metric of **configuration bits per core** (the lower, the better). Throughput is computed by this formula: `core_count/technology` + +| FPGA Model | Core Count | Configuration Bits per Core | LUT4 Count | Technology | Throughput | +|--------------------|-----------|-----------------------------|------------|------------|-------------| +| 10CL025YU256C8G | 60 | 6666 | 25k | LP 20nm | 3 | +| CCGM1A1-BGA324 | 54 | 9102 | 41k | LP 28nm | 1.964 | +| LFE5U-25F-6BG256C | 61 | 7069 | 24.3k | LP 40nm | 1.525 | +| EP4CE10F17I7N | 54 | 5770 | 22k | 60nm | 0.9 | +| GW2AR-18C C8/I7 | 50 | 6635 | 20.7k | 55nm HS | 0.9 | + + +This indicates that the CCGM1A1 has a lower effective logic density per area unit, as measured by configuration bits per core. Conversely, CCGM1A1 shines in throughput per dollar, holding strong against the competition. + +## Build steps +Put Yosys and GateMate p_r in PATH, and make sure you have FuseSoC installed: +``` +pip install fusesoc +``` +Navigate to 1.corescore_cc +``` +cd 8.StressTest/1.corescore_cc/ +``` +Build FuseSoC target cc_gatemate +``` +fusesoc run --target=cc_gatemate corescore +``` + +At this point your design should've successfully generated a bitstream. Uploading the bitstream to your board: +``` +cd 8.StressTest/1.corescore_cc/ +make program +``` +Listen to serial port at **57600 baud rate 8b no parity, 1 stop bit**, your output should be something like this, with xx ranging from `00` to `number_of_cores-1`: +``` +core xx says hello +``` + +If for any reason you want to change the number of cores instantated, simply go to `fusesoc_libraries/corescore/corescore.core`, under targets find `cc_gatemate`, and change the count in the following line to a desired number of cores +``` +generate: [corescorecore: {count: 55}] +``` +**RTL functional simulation**: +If for any reason you need debugging, there's a `sim` target provided, requiring Verilator. Waveform visualisation is left to the user. + diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0.eda.yml b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0.eda.yml new file mode 100644 index 0000000000000000000000000000000000000000..fb8c3661a91c71e88bd9fd75cc0b6a7ad919e869 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0.eda.yml @@ -0,0 +1,138 @@ +version: 0.2.1 +name: corescore_0 +toplevel: corescore_gatemate +dependencies: + ::serv:1.0.2: [] + ::verilog-axis:0-r3: [] + ::serving:1.0.2: + - ::serv:1.0.2 + ::corescore:0: + - ::serv:1.0.2 + - ::serving:1.0.2 + - ::verilog-axis:0-r3 + - ::corescore-corescorecore:0 + ::corescore-corescorecore:0: [] +parameters: + RISCV_FORMAL: + datatype: bool + paramtype: vlogdefine + SERV_CLEAR_RAM: + datatype: bool + paramtype: vlogdefine +tool_options: + gatemate: + device: CCGM1A1 + yosys_synth_options: + - -nomx8 + p_r_options: + - -cCP + - --verbose + - -tm 1 +filters: [] +flow_options: {} +hooks: {} +files: +- file_type: verilogSource + is_include_file: true + name: src/serv_1.0.2/rtl/serv_params.vh + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_shift.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_bufreg.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_alu.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_csr.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_ctrl.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_decode.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_mem_if.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_rf_if.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_rf_ram_if.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_rf_ram.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_state.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_top.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/rtl/serv_rf_top.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/arbiter.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/priority_encoder.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/axis_arb_mux.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/axis_async_fifo.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving_arbiter.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving_mux.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving_ram.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/corescore_0/rtl/wb2axis.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/base.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/emitter_uart.v + core: ::corescore:0 +- file_type: CCF + name: src/corescore_0/data/cc_gatemate.ccf + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/cc_gatemate_clock_gen.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/corescore_gatemate.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore-corescorecore_0/corescorecore.v + core: ::corescore-corescorecore:0 +- file_type: user + name: core_0.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_1.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_2.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_3.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_4.hex + core: ::corescore-corescorecore:0 +vpi: [] diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0_00.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0_00.v new file mode 100644 index 0000000000000000000000000000000000000000..5666d2e3fd52d4894f95379ca5bac1a242cc57a0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0_00.v @@ -0,0 +1,22414 @@ +// (c) Cologne Chip AG +// FPGA Verilog netlist writer Version: Version 4.2 (1 January 2025) +// Compile Time: 2025-03-05 10:25:39 +// Program Run: 2025-03-05 13:06:38 +// Program Call: /home/tarik/Downloads/cc-toolchain-linux/bin/p_r/p_r -A 1 -i corescore_0_synth.v -o corescore_0 -lib ccag -cCP --verbose -tm 1 -ccf src/corescore_0/data/cc_gatemate.ccf +// File Type: Verilog + +// Gatecount: 2880 +module corescore_0 (i_clk , i_rstn , + o_uart_tx + ) ; + +input i_clk; +input i_rstn; + +output o_uart_tx; + + + +wire i_clk; +wire na2_1; +wire na2_2; +wire na3_1; +wire na4_1; +wire na7_2; +wire na8_1; +wire na9_1; +wire na9_2; +wire i_rstn; +wire na11_1; +wire na12_1; +wire na15_2; +wire na16_1; +wire na17_1; +wire na17_2; +wire na19_1; +wire na21_1; +wire na22_1; +wire na22_2; +wire na24_1; +wire na25_2; +wire na26_1; +wire na27_1; +wire na27_2; +wire na28_1; +wire na30_1; +wire na30_1_i; +wire na31_2; +wire na32_1; +wire na32_1_i; +wire na33_1; +wire na34_1; +wire na34_1_i; +wire na35_1; +wire na35_1_i; +wire na36_1; +wire na36_1_i; +wire na37_1; +wire na37_1_i; +wire na38_1; +wire na38_1_i; +wire na38_2; +wire na38_2_i; +wire na39_1; +wire na39_1_i; +wire na40_1; +wire na40_1_i; +wire na41_1; +wire na41_1_i; +wire na42_1; +wire na42_1_i; +wire na43_1; +wire na43_1_i; +wire na44_1; +wire na44_1_i; +wire na45_1; +wire na45_1_i; +wire na46_1; +wire na46_1_i; +wire na47_1; +wire na47_1_i; +wire na48_1; +wire na48_1_i; +wire na49_1; +wire na49_1_i; +wire na50_1; +wire na50_1_i; +wire na51_1; +wire na51_1_i; +wire na52_1; +wire na52_1_i; +wire na53_1; +wire na53_1_i; +wire na54_2; +wire na55_1; +wire na55_2; +wire na56_1; +wire na56_1_i; +wire na57_1; +wire na57_1_i; +wire na58_1; +wire na58_1_i; +wire na59_1; +wire na59_1_i; +wire na60_1; +wire na60_1_i; +wire na61_1; +wire na61_1_i; +wire na62_1; +wire na62_1_i; +wire na63_1; +wire na63_1_i; +wire na64_1; +wire na64_1_i; +wire na65_1; +wire na65_1_i; +wire na66_1; +wire na66_1_i; +wire na67_1; +wire na67_1_i; +wire na68_1; +wire na68_1_i; +wire na69_1; +wire na69_1_i; +wire na70_1; +wire na70_1_i; +wire na71_1; +wire na71_1_i; +wire na72_1; +wire na72_1_i; +wire na73_1; +wire na73_1_i; +wire na75_1; +wire na75_1_i; +wire na76_1; +wire na76_1_i; +wire na76_2; +wire na76_2_i; +wire na78_1; +wire na78_1_i; +wire na78_2; +wire na78_2_i; +wire na79_1; +wire na79_1_i; +wire na79_2; +wire na79_2_i; +wire na80_1; +wire na80_1_i; +wire na81_1; +wire na83_2; +wire na84_2; +wire na84_2_i; +wire na85_1; +wire na85_1_i; +wire na85_2; +wire na85_2_i; +wire na87_1; +wire na87_1_i; +wire na88_1; +wire na88_1_i; +wire na88_2; +wire na88_2_i; +wire na89_1; +wire na89_1_i; +wire na89_2; +wire na89_2_i; +wire na90_1; +wire na90_2; +wire na91_1; +wire na92_1; +wire na93_1; +wire na94_1; +wire na94_2; +wire na95_1; +wire na95_2; +wire na98_1; +wire na103_1; +wire na103_1_i; +wire na104_1; +wire na104_1_i; +wire na105_1; +wire na105_1_i; +wire na107_1; +wire na107_1_i; +wire na108_1; +wire na108_1_i; +wire na109_1; +wire na109_1_i; +wire na110_1; +wire na110_1_i; +wire na111_1; +wire na111_1_i; +wire na112_1; +wire na112_1_i; +wire na113_1; +wire na113_1_i; +wire na114_1; +wire na114_1_i; +wire na115_1; +wire na115_1_i; +wire na117_1; +wire na117_2; +wire na118_1; +wire na118_1_i; +wire na119_1; +wire na119_1_i; +wire na120_2; +wire na121_2; +wire na122_1; +wire na122_2; +wire na123_1; +wire na123_1_i; +wire na124_1; +wire na124_1_i; +wire na125_1; +wire na125_1_i; +wire na126_1; +wire na126_1_i; +wire na127_1; +wire na127_1_i; +wire na128_1; +wire na128_1_i; +wire na129_1; +wire na129_1_i; +wire na130_1; +wire na130_1_i; +wire na131_1; +wire na131_1_i; +wire na132_1; +wire na132_1_i; +wire na133_1; +wire na133_1_i; +wire na134_1; +wire na134_1_i; +wire na135_1; +wire na135_1_i; +wire na136_1; +wire na136_1_i; +wire na137_2; +wire na138_1; +wire na139_1; +wire na143_1; +wire na145_1; +wire na146_1; +wire na153_1; +wire na153_1_i; +wire na154_1; +wire na154_1_i; +wire na155_2; +wire na156_1; +wire na157_1; +wire na157_1_i; +wire na158_1; +wire na158_1_i; +wire na159_1; +wire na159_1_i; +wire na160_1; +wire na160_1_i; +wire na161_1; +wire na161_1_i; +wire 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na204_1_i; +wire na204_2; +wire na204_2_i; +wire na205_2; +wire na205_2_i; +wire na207_1; +wire na207_1_i; +wire na207_2; +wire na207_2_i; +wire na208_1; +wire na208_1_i; +wire na209_1; +wire na209_1_i; +wire na210_1; +wire na210_1_i; +wire na211_1; +wire na211_1_i; +wire na212_1; +wire na212_1_i; +wire na214_1; +wire na214_1_i; +wire na214_2; +wire na214_2_i; +wire na216_1; +wire na216_1_i; +wire na216_2; +wire na216_2_i; +wire na217_1; +wire na217_1_i; +wire na217_2; +wire na217_2_i; +wire na218_1; +wire na219_2; +wire na220_1; +wire na221_1; +wire na221_1_i; +wire na222_1; +wire na222_2; +wire na223_2; +wire na224_1; +wire na225_2; +wire na226_1; +wire na226_2; +wire na229_1; +wire na232_1; +wire na232_1_i; +wire na232_2; +wire na232_2_i; +wire na233_1; +wire na233_2; +wire na234_1; +wire na235_2; +wire na236_1; +wire na237_1; +wire na237_1_i; +wire na238_1; +wire na238_1_i; +wire na239_1; +wire na239_1_i; +wire na240_1; +wire na240_1_i; +wire na241_1; +wire na241_1_i; +wire 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na4046_1; +wire na4050_1; +wire na4050_2; +wire na4053_1; +wire na4053_2; +wire na4054_2; +wire na4058_1; +wire na4058_2; +wire na4059_2; +wire na4063_1; +wire na4063_2; +wire na4064_1; +wire na4065_2; +wire na4066_2; +wire na4067_2; +wire na4068_2; +wire na4069_2; +wire na4070_2; +wire na4071_2; +wire na4072_2; +wire na4073_2; +wire na4074_2; +wire na4075_2; +wire na4076_2; +wire na4077_2; +wire na4078_2; +wire na4079_2; +wire na4080_2; +wire na4081_2; +wire na4082_2; +wire na4083_2; +wire na4084_2; +wire na4085_2; +wire na4086_2; +wire na4087_2; +wire na4088_2; +wire na4089_2; +wire na4090_2; +wire na4091_2; +wire na4092_2; +wire na4093_2; +wire na4094_2; +wire na4095_2; +wire na4096_2; +wire na4097_2; +wire na4098_2; +wire na4099_2; +wire na4100_2; +wire na4101_2; +wire na4102_2; +wire na4103_2; +wire na4104_2; +wire na4105_2; +wire na4106_2; +wire na4107_2; +wire na4108_2; +wire na4109_2; +wire na4110_2; +wire na4111_2; +wire na4112_2; +wire na4113_2; +wire na4114_2; +wire na4115_2; +wire na4116_2; +wire na4117_2; +wire na4118_2; +wire na4119_2; +wire na4120_2; +wire na4121_2; +wire na4122_2; +wire na4123_2; +wire na4124_2; +wire na4125_2; +wire na4126_2; +wire na4127_2; +wire na4128_2; +wire na4129_2; +wire na4130_2; +wire na4131_2; +wire na4132_2; +wire na4133_2; +wire na4134_2; +wire na4135_2; +wire na4136_2; +wire na4137_2; +wire na4138_2; +wire na4139_2; +wire na4140_2; +wire na4141_2; +wire na4142_2; +wire na4143_2; +wire na4144_2; +wire na4145_2; +wire na4146_2; +wire na4147_2; +wire na4148_2; +wire na4149_2; +wire na4150_2; +wire na4151_2; +wire na4152_2; +wire na4153_2; +wire na4154_2; +wire na4155_2; +wire na4156_2; +wire na4157_2; +wire na4158_2; +wire na4159_2; +wire na4160_2; +wire na4161_2; +wire na4162_2; +wire na4163_2; +wire na4164_2; +wire na4165_2; +wire na4166_2; +wire na4167_2; +wire na4168_2; +wire na4169_2; +wire na4170_2; +wire na4171_2; +wire na4172_2; +wire na4173_2; +wire na4174_2; +wire na4175_2; +wire na4176_2; +wire na4177_2; +wire na4178_2; +wire na4179_2; +wire na4180_2; +wire na4181_2; +wire na4182_2; +wire na4183_2; +wire na4184_2; +wire na4185_2; +wire na4186_2; +wire na4187_2; +wire na4188_2; +wire na4189_2; +wire na4190_2; +wire na4191_2; +wire na4192_2; +wire na4193_2; +wire na4194_2; +wire na4195_2; +wire na4196_2; +wire na4197_2; +wire na4198_2; +wire na4199_2; +wire na4200_2; +wire na4201_2; +wire na4202_2; +wire na4203_2; +wire na4204_2; +wire na4205_2; +wire na4206_2; +wire na4207_2; +wire na4208_2; +wire na4209_2; +wire na4210_2; +wire na4211_2; +wire na4212_2; +wire na4213_2; +wire na4214_2; +wire na4215_2; +wire na4216_2; +wire na4217_2; +wire na4218_2; +wire na4219_2; +wire na4220_2; +wire na4221_2; +wire na4222_2; +wire na4223_2; +wire na4224_2; +wire na4225_2; +wire na4226_2; +wire na4227_2; +wire na4228_2; +wire na4229_2; +wire na4230_2; +wire na4231_2; +wire na4232_2; +wire na4233_2; +wire na4234_2; +wire na4235_2; +wire na4236_2; +wire na4237_2; +wire na4238_2; +wire na4239_2; +wire na4240_2; +wire na4241_2; +wire na4242_2; +wire na4243_2; +wire na4244_2; +wire na4245_2; +wire na4246_2; +wire na4247_2; +wire na4248_2; +wire na4249_2; +wire na4250_2; +wire na4251_2; +wire na4252_2; +wire na4253_2; +wire na4254_2; +wire na4255_2; +wire na4256_2; +wire na4257_2; +wire na4258_2; +wire na4259_2; +wire na4260_2; +wire na4261_2; +wire na4262_2; +wire na4263_2; +wire na4264_2; +wire na4265_2; +wire na4266_2; +wire na4267_2; +wire na4268_2; +wire na4269_2; +wire na4270_2; +wire na4271_2; +wire na4272_2; +wire na4273_2; +wire na4274_2; +wire na4275_2; +wire na4276_2; +wire na4277_2; +wire na4278_2; +wire na4279_2; +wire na4280_2; +wire na4281_2; +wire na4282_2; +wire na4283_2; +wire na4284_2; +wire na4285_2; +wire na4286_2; +wire na4287_2; +wire na4288_2; +wire na4289_2; +wire na4290_2; +wire na4291_2; +wire na4292_2; +wire na4293_2; +wire na4294_2; +wire na4295_2; +wire na4296_2; +wire na4297_2; +wire na4298_2; +wire na4299_2; +wire na4300_2; +wire na4301_2; +wire na4302_2; +wire na4303_2; +wire na4304_2; +wire na4305_2; +wire na4306_2; +wire na4307_2; +wire na4308_2; +wire na4309_2; +wire na4310_2; +wire na4311_2; +wire na4312_2; +wire na4313_2; +wire na4314_2; +wire na4315_2; +wire na4316_2; +wire na4317_2; +wire na4318_2; +wire na4319_2; +wire na4320_2; +wire na4321_2; +wire na4322_2; +wire na4323_2; +wire na4324_2; +wire na4325_2; +wire na4326_2; +wire na4327_2; +wire na4328_2; +wire na4329_2; +wire na4330_2; +wire na4331_2; +wire na4332_2; +wire na4333_2; +wire na4334_2; +wire na4335_2; +wire na4336_2; +wire na4337_2; +wire na4338_2; +wire na4339_2; +wire na4340_2; +wire na4341_2; +wire na4342_2; +wire na4343_2; +wire na4344_2; +wire na4345_2; +wire na4346_2; +wire na4347_2; +wire na4348_2; +wire na4349_2; +wire na4350_2; +wire na4351_2; +wire na4352_2; +wire na4353_2; +wire na4354_2; +wire na4355_2; +wire na4356_2; +wire na4357_2; +wire na4358_2; +wire na4359_2; +wire na4360_2; +wire na4361_2; +wire na4362_2; +wire na4363_2; +wire na4364_2; +wire na4365_2; +wire na4366_2; +wire na4367_2; +wire na4368_2; +wire na4369_2; +wire na4370_2; +wire na4371_2; +wire na4372_2; +wire na4373_2; +wire na4374_2; +wire na4375_2; +wire na4376_2; +wire na4377_2; +wire na4378_2; +wire na4379_2; +wire na4380_2; +wire na4381_2; +wire na4382_2; +wire na4383_2; +wire na4384_2; +wire na4385_2; +wire na4386_2; +wire na4387_2; +wire na4388_2; +wire na4389_2; +wire na4390_2; +wire na4391_2; +wire na4392_2; +wire na4393_2; +wire na4394_2; +wire na4395_2; +wire na4396_2; +wire na4397_2; +wire na4398_2; +wire na4399_2; +wire na4400_2; +wire na4401_2; +wire na4402_2; +wire na4403_2; +wire na4404_2; +wire na4405_2; +wire na4406_2; +wire na4407_2; +wire na4408_2; +wire na4409_2; +wire na4410_2; +wire na4411_2; +wire na4412_2; +wire na4413_2; +wire na4414_2; +wire na4415_2; +wire na4416_2; +wire na4417_2; +wire na4418_2; +wire na4419_2; +wire na4420_2; +wire na4421_2; +wire na4422_2; +wire na4423_2; +wire na4424_2; +wire na4425_2; +wire na4426_2; +wire na4427_2; +wire na4428_2; +wire na4429_2; +wire na4430_2; +wire na4431_2; +wire na4432_2; +wire na4433_2; +wire na4434_2; +wire na4435_2; +wire na4436_2; +wire na4437_2; +wire na4438_2; +wire na4439_2; +wire na4440_2; +wire na4441_2; +wire na4442_2; +wire na4443_2; +wire na4444_2; +wire na4445_2; +wire na4446_2; +wire na4447_2; +wire na4448_2; +wire na4449_2; +wire na4450_2; +wire na4451_2; +wire na4452_2; +wire na4453_2; +wire na4454_2; +wire na4455_2; +wire na4456_2; +wire na4457_2; +wire na4458_2; +wire na4459_2; +wire na4460_2; +wire na4461_2; +wire na4462_2; +wire na4463_2; +wire na4464_2; +wire na4465_2; +wire na4466_2; +wire na4467_2; +wire na4468_2; +wire na4469_2; +wire na4470_2; +wire na4471_2; +wire na4472_2; +wire na4473_2; +wire na4474_2; +wire na4475_2; +wire na4476_2; +wire na4477_2; +wire na4478_2; +wire na4479_2; +wire na4480_2; +wire na4481_2; +wire na4482_2; +wire na4483_2; +wire na4484_2; +wire na4485_2; +wire na4486_2; +wire na4487_2; +wire na4488_2; +wire na4489_2; +wire na4490_2; +wire na4491_2; +wire na4492_2; +wire na4493_2; +wire na4494_2; +wire na4495_2; +wire na4496_2; +wire na4497_2; +wire na4498_2; +wire na4499_2; +wire na4500_2; +wire na4501_2; +wire na4502_2; +wire na4503_2; +wire na4504_2; +wire na4505_2; +wire na4506_2; +wire na4507_2; +wire na4508_2; +wire na4509_2; +wire na4510_2; +wire na4511_2; +wire na4512_2; +wire na4513_2; +wire na4514_2; +wire na4515_2; +wire na4516_2; +wire na4517_2; +wire na4518_2; +wire na4519_2; +wire na4520_2; +wire na4521_2; +wire na4522_2; +wire na4523_2; +wire na4524_2; +wire na4525_2; +wire na4526_2; +wire na4527_2; +wire na4528_2; +wire na4529_2; +wire na4530_2; +wire na4531_2; +wire na4532_2; +wire na4533_2; +wire na4534_2; +wire na4535_2; +wire na4536_2; +wire na4537_2; +wire na4538_2; +wire na4539_2; +wire na4540_2; +wire na4541_2; +wire na4542_2; +wire na4543_2; +wire na4544_2; +wire na4545_2; +wire na4546_2; +wire na4547_2; +wire na4548_2; +wire na4549_2; +wire na4550_2; +wire na4551_2; +wire na4552_2; +wire na4553_2; +wire na4554_2; +wire na4555_2; +wire na4556_2; +wire na4557_2; +wire na4558_2; +wire na4559_2; +wire na4560_2; +wire na4561_2; +wire na4562_2; +wire na4563_2; +wire na4564_2; +wire na4565_2; +wire na4566_2; +wire na4567_2; +wire na4568_2; +wire na4569_2; +wire na4570_2; +wire na4571_2; +wire na4572_2; +wire na4573_2; +wire na4574_2; +wire na4575_2; +wire na4576_2; +wire na4577_2; +wire na4578_2; +wire na4579_2; +wire na4580_2; +wire na4581_2; +wire na4582_2; +wire na4583_2; +wire na4584_2; +wire na4585_2; +wire na4586_2; +wire na4587_2; +wire na4588_2; +wire na4589_2; +wire na4590_2; +wire na4591_2; +wire na4592_2; +wire na4593_2; +wire na4594_2; +wire na4595_2; +wire na4596_2; +wire na4597_2; +wire na4598_2; +wire na4599_2; +wire na4600_2; +wire na4601_2; +wire na4602_2; +wire na4603_2; +wire na4604_2; +wire na4605_2; +wire na4606_2; +wire na4607_2; +wire na4608_2; +wire na4609_2; +wire na4610_2; +wire na4611_2; +wire na4612_2; +wire na4613_2; +wire na4614_2; +wire na4615_2; +wire na4616_2; +wire na4617_2; +wire na4618_2; +wire na4619_2; +wire na4620_2; +wire na4621_2; +wire na4622_2; +wire na4623_2; +wire na4624_2; +wire na4625_2; +wire na4626_2; +wire na4627_2; +wire na4628_2; +wire na4629_2; +wire na4630_2; +wire na4631_2; +wire na4632_2; +wire na3223_93; +wire na3223_94; +wire na3223_95; +wire na3223_96; +wire na3223_97; +wire na3223_98; +wire na3223_99; +wire na3224_10; +wire na3225_93; +wire na3225_94; +wire na3225_95; +wire na3225_96; +wire na3225_97; +wire na3225_98; +wire na3225_99; +wire na3226_93; +wire na3226_94; +wire na3226_95; +wire na3226_96; +wire na3226_97; +wire na3226_98; +wire na3226_99; +wire na3227_10; +wire na3232_10; +wire na3236_10; +wire na3238_10; +wire na3240_10; +wire na3244_10; +wire na3250_10; +wire na3253_10; +wire na3261_10; +wire na3265_10; +wire na3269_10; +wire na3273_10; +wire na3280_10; +wire na3286_10; +wire na3291_10; +wire na3294_10; +wire na3297_10; +wire na3300_10; +wire na3306_10; +wire na3309_10; +wire na3314_10; +wire na3318_10; +wire na3320_10; +wire na3323_10; +wire na3326_10; +wire na3332_10; +wire na3337_10; +wire na3340_10; +wire na3345_10; +wire na3349_10; +wire na3351_10; +wire na3353_10; +wire na3355_10; +wire na3357_10; +wire na3359_10; +wire na3361_10; +wire na3363_10; +wire na3365_10; +wire na3367_10; +wire na3369_10; +wire na3371_10; +wire na3373_10; +wire na3375_10; +wire na3377_10; +wire na3379_10; +wire na3381_10; +wire na3383_10; +wire na3385_10; +wire na3387_10; +wire na3389_10; +wire na3391_10; +wire na3393_10; +wire na3395_10; +wire na3397_10; +wire na3399_10; +wire na3401_10; +wire na3403_10; +wire na3405_10; +wire na3407_10; +wire na3409_10; +wire na3411_10; +wire na3446_10; +wire na3449_10; +wire na3454_10; +wire na3456_10; +wire na3468_10; +wire na3473_10; +wire na3475_10; +wire na3477_10; +wire na3479_10; +wire na3481_10; +wire na3483_10; +wire na3485_10; +wire na3487_10; +wire na3489_10; +wire na3491_10; +wire na3493_10; +wire na3495_10; +wire na3497_10; +wire na3499_10; +wire na3501_10; +wire na3503_10; +wire na3505_10; +wire na3507_10; +wire na3509_10; +wire na3511_10; +wire na3513_10; +wire na3515_10; +wire na3517_10; +wire na3519_10; +wire na3521_10; +wire na3523_10; +wire na3533_10; +wire na3534_10; +wire na3535_10; +wire na3537_10; +wire na3540_10; +wire na3544_10; +wire na3547_10; +wire na3550_10; +wire na3553_10; +wire na3563_10; +wire na3567_10; +wire na3569_10; +wire na3573_10; +wire na3577_10; +wire na3581_10; +wire na3584_10; +wire na3587_10; +wire na3592_10; +wire na3594_10; +wire na3596_10; +wire na3598_10; +wire na3600_10; +wire na3602_10; +wire na3604_10; +wire na3606_10; +wire na3608_10; +wire na3610_10; +wire na3612_10; +wire na3614_10; +wire na3616_10; +wire na3618_10; +wire na3620_10; +wire na3622_10; +wire na3624_10; +wire na3626_10; +wire na3628_10; +wire na3630_10; +wire na3632_10; +wire na3634_10; +wire na3636_10; +wire na3638_10; +wire na3640_10; +wire na3642_10; +wire na3644_10; +wire na3646_10; +wire na3648_10; +wire na3650_10; +wire na3652_10; +wire na3654_10; +wire na3656_10; +wire na3659_10; +wire na3663_10; +wire na3666_10; +wire na3669_10; +wire na3672_10; +wire na3684_10; +wire na3686_10; +wire na3690_10; +wire na3692_10; +wire na3699_10; +wire na3704_10; +wire na3709_10; +wire na4065_10; +wire o_uart_tx; +wire na3223_100; +wire na3223_113; +wire na3223_114; +wire na3223_115; +wire na3223_116; +wire na3223_117; +wire na3223_118; +wire na3223_119; +wire na3223_120; +wire na3225_100; +wire na3226_100; +wire na3226_113; +wire na3226_114; +wire na3226_115; +wire na3226_116; +wire na3226_117; +wire na3226_118; +wire na3226_119; +wire na3226_120; + +// C_AND///AND/ x17y72 80'h00_0078_00_0000_0C88_111F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2_1 ( .OUT(na2_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na7_2), .IN6(~na3_1), .IN7(~na11_1), .IN8(~na15_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2_4 ( .OUT(na2_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na233_2), .IN4(~na420_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x29y68 80'h00_0018_00_0000_0C88_38FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3_1 ( .OUT(na3_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na136_1), .IN6(na4_1), .IN7(1'b1), .IN8(~na645_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x49y64 80'h00_0018_00_0000_0888_2114 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a4_1 ( .OUT(na4_1), .IN1(~na2229_1), .IN2(na2228_1), .IN3(~na80_1), .IN4(~na4432_2), .IN5(~na3228_1), .IN6(~na2228_2), + .IN7(na332_1), .IN8(~na4511_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x33y69 80'h00_0060_00_0000_0C08_FFA4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a7_4 ( .OUT(na7_2), .IN1(~na1290_1), .IN2(na237_1), .IN3(na8_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x50y79 80'h00_0018_00_0000_0888_1AA5 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a8_1 ( .OUT(na8_1), .IN1(~na456_1), .IN2(1'b1), .IN3(na9_1), .IN4(1'b1), .IN5(na2963_2), .IN6(1'b1), .IN7(~na9_2), .IN8(~na392_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x50y83 80'h00_0078_00_0000_0C88_411F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a9_1 ( .OUT(na9_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2962_1), .IN6(~na2965_2), .IN7(~na4570_2), + .IN8(na518_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a9_4 ( .OUT(na9_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na1198_1), .IN4(~na3014_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x24y71 80'h00_0018_00_0000_0C88_A4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a11_1 ( .OUT(na11_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na984_1), .IN6(na12_1), .IN7(na328_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x39y80 80'h00_0018_00_0000_0888_2141 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a12_1 ( .OUT(na12_1), .IN1(~na1354_1), .IN2(~na232_1), .IN3(~na2713_1), .IN4(na4549_2), .IN5(~na2712_2), .IN6(~na4553_2), + .IN7(na1340_1), .IN8(~na3230_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x30y70 80'h00_0060_00_0000_0C08_FFC2 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a15_4 ( .OUT(na15_2), .IN1(na157_1), .IN2(~na690_1), .IN3(1'b1), .IN4(na16_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x32y64 80'h00_0018_00_0000_0888_5A25 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a16_1 ( .OUT(na16_1), .IN1(~na266_1), .IN2(1'b1), .IN3(na17_1), .IN4(~na4442_2), .IN5(na2479_2), .IN6(1'b1), .IN7(~na17_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x28y61 80'h00_0078_00_0000_0C88_4155 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a17_1 ( .OUT(na17_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4528_2), .IN6(~na2478_1), .IN7(~na2481_2), + .IN8(na124_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a17_4 ( .OUT(na17_2), .IN1(~na886_1), .IN2(1'b1), .IN3(~na2529_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y71 80'h00_0018_00_0000_0C88_C2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a19_1 ( .OUT(na19_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na21_1), .IN6(~na508_2), .IN7(1'b1), .IN8(na396_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x57y69 80'h00_0018_00_0000_0888_F423 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a21_1 ( .OUT(na21_1), .IN1(1'b1), .IN2(~na22_2), .IN3(na1991_1), .IN4(~na1443_2), .IN5(~na987_1), .IN6(na22_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x61y72 80'h00_0078_00_0000_0C88_4155 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a22_1 ( .OUT(na22_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4489_2), .IN6(~na1993_2), .IN7(~na4488_2), + .IN8(na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a22_4 ( .OUT(na22_2), .IN1(~na525_1), .IN2(1'b1), .IN3(~na2041_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x15y68 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a24_1 ( .OUT(na24_1), .IN1(1'b1), .IN2(na4143_2), .IN3(1'b0), .IN4(1'b0), .IN5(na4473_2), .IN6(na1617_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x25y72 80'h00_0060_00_0000_0C08_FFEC +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a25_4 ( .OUT(na25_2), .IN1(1'b0), .IN2(na2_1), .IN3(na19_1), .IN4(na26_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x20y70 80'h00_0018_00_0000_0C88_C1FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a26_1 ( .OUT(na26_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na28_1), .IN6(~na4071_2), .IN7(1'b1), .IN8(na27_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x26y68 80'h00_0078_00_0000_0C88_3C55 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a27_1 ( .OUT(na27_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4_1), .IN7(1'b1), .IN8(~na645_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a27_4 ( .OUT(na27_2), .IN1(~na408_1), .IN2(1'b1), .IN3(~na407_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x25y65 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a28_1 ( .OUT(na28_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na690_1), .IN7(1'b1), .IN8(na16_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x37y80 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a30_1 ( .OUT(na30_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4074_2), .IN6(na59_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a30_2 ( .OUT(na30_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na30_1_i) ); +// C_///AND/ x49y83 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a31_4 ( .OUT(na31_2), .IN1(1'b1), .IN2(na4424_2), .IN3(~na115_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x23y74 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a32_1 ( .OUT(na32_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na242_1), .IN6(na32_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a32_2 ( .OUT(na32_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na32_1_i) ); +// C_AND//// x33y70 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a33_1 ( .OUT(na33_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na333_1), .IN6(1'b1), .IN7(1'b1), .IN8(na4432_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x39y74 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a34_1 ( .OUT(na34_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na39_1), .IN6(na34_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a34_2 ( .OUT(na34_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na34_1_i) ); +// C_MX4b/D/// x25y76 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a35_1 ( .OUT(na35_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na53_1), .IN6(na35_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a35_2 ( .OUT(na35_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na35_1_i) ); +// C_MX4b/D/// x29y67 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a36_1 ( .OUT(na36_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na36_1), .IN6(na37_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a36_2 ( .OUT(na36_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na36_1_i) ); +// C_MX4b/D/// x29y72 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a37_1 ( .OUT(na37_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na51_1), .IN6(na37_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a37_2 ( .OUT(na37_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na37_1_i) ); +// C_AND/D//AND/D x66y77 80'h00_FE00_80_0000_0C88_4F88 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a38_1 ( .OUT(na38_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), .IN8(na1645_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a38_2 ( .OUT(na38_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na38_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a38_4 ( .OUT(na38_2_i), .IN1(na360_1), .IN2(na58_1), .IN3(na38_1), .IN4(na4180_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a38_5 ( .OUT(na38_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na38_2_i) ); +// C_MX4b/D/// x37y73 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a39_1 ( .OUT(na39_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na39_1), .IN6(na40_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a39_2 ( .OUT(na39_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na39_1_i) ); +// C_MX4b/D/// x35y76 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a40_1 ( .OUT(na40_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4079_2), .IN6(na41_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a40_2 ( .OUT(na40_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na40_1_i) ); +// C_MX4b/D/// x35y74 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a41_1 ( .OUT(na41_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na42_1), .IN6(na41_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a41_2 ( .OUT(na41_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na41_1_i) ); +// C_MX4b/D/// x37y75 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a42_1 ( .OUT(na42_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na42_1), .IN6(na43_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a42_2 ( .OUT(na42_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na42_1_i) ); +// C_MX4b/D/// x33y78 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a43_1 ( .OUT(na43_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1187_1), .IN6(na43_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a43_2 ( .OUT(na43_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na43_1_i) ); +// C_MX4b/D/// x45y78 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a44_1 ( .OUT(na44_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na45_1), .IN6(na44_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a44_2 ( .OUT(na44_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na44_1_i) ); +// C_MX4b/D/// x43y75 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a45_1 ( .OUT(na45_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na45_1), .IN6(na34_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a45_2 ( .OUT(na45_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na45_1_i) ); +// C_MX4b/D/// x56y86 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a46_1 ( .OUT(na46_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4081_2), + .IN8(na46_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a46_2 ( .OUT(na46_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na46_1_i) ); +// C_MX4b/D/// x45y86 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a47_1 ( .OUT(na47_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na48_1), .IN6(na47_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a47_2 ( .OUT(na47_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na47_1_i) ); +// C_MX4b/D/// x47y79 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a48_1 ( .OUT(na48_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na48_1), .IN6(na49_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a48_2 ( .OUT(na48_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na48_1_i) ); +// C_MX4b/D/// x47y78 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a49_1 ( .OUT(na49_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1339_1), .IN6(na49_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a49_2 ( .OUT(na49_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na49_1_i) ); +// C_MX4b/D/// x64y78 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a50_1 ( .OUT(na50_1_i), .IN1(1'b1), .IN2(~na4424_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na115_1), + .IN8(na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a50_2 ( .OUT(na50_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na50_1_i) ); +// C_MX4b/D/// x23y75 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a51_1 ( .OUT(na51_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4082_2), .IN8(na52_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a51_2 ( .OUT(na51_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na51_1_i) ); +// C_MX4b/D/// x26y78 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a52_1 ( .OUT(na52_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na311_1), .IN8(na52_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a52_2 ( .OUT(na52_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na52_1_i) ); +// C_MX4b/D/// x21y75 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a53_1 ( .OUT(na53_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4083_2), .IN8(na112_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a53_2 ( .OUT(na53_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na53_1_i) ); +// C_///AND/ x62y54 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a54_4 ( .OUT(na54_2), .IN1(1'b1), .IN2(na1451_1), .IN3(1'b1), .IN4(na55_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x56y64 80'h00_0078_00_0000_0C88_C51F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a55_1 ( .OUT(na55_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na31_2), .IN6(1'b1), .IN7(1'b1), .IN8(na56_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a55_4 ( .OUT(na55_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na528_1), .IN4(~na55_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND*/D/// x58y74 80'h00_FE00_00_0000_0788_5FB5 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a56_1 ( .OUT(na56_1_i), .IN1(~na31_2), .IN2(1'b0), .IN3(na4428_2), .IN4(~na56_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a56_2 ( .OUT(na56_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na56_1_i) ); +// C_MX4b/D/// x59y80 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a57_1 ( .OUT(na57_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4085_2), .IN6(na103_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a57_2 ( .OUT(na57_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na57_1_i) ); +// C_MX4b/D/// x59y82 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a58_1 ( .OUT(na58_1_i), .IN1(1'b1), .IN2(~na4424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4085_2), .IN6(na58_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a58_2 ( .OUT(na58_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na58_1_i) ); +// C_MX4b/D/// x35y80 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a59_1 ( .OUT(na59_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na60_1), .IN6(na59_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a59_2 ( .OUT(na59_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na59_1_i) ); +// C_MX4b/D/// x31y77 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a60_1 ( .OUT(na60_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na60_1), .IN6(na61_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a60_2 ( .OUT(na60_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na60_1_i) ); +// C_MX4b/D/// x31y78 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a61_1 ( .OUT(na61_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na62_1), .IN6(na61_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a61_2 ( .OUT(na61_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na61_1_i) ); +// C_MX4b/D/// x33y79 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a62_1 ( .OUT(na62_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na62_1), .IN6(na63_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a62_2 ( .OUT(na62_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na62_1_i) ); +// C_MX4b/D/// x33y80 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a63_1 ( .OUT(na63_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na64_1), .IN6(na63_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a63_2 ( .OUT(na63_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na63_1_i) ); +// C_MX4b/D/// x35y79 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a64_1 ( .OUT(na64_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na64_1), .IN6(na65_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a64_2 ( .OUT(na64_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na64_1_i) ); +// C_MX4b/D/// x35y78 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a65_1 ( .OUT(na65_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1036_1), .IN6(na65_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a65_2 ( .OUT(na65_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na65_1_i) ); +// C_MX4b/D/// x31y76 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a66_1 ( .OUT(na66_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4087_2), .IN6(na66_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a66_2 ( .OUT(na66_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na66_1_i) ); +// C_MX4b/D/// x31y74 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a67_1 ( .OUT(na67_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na68_1), .IN6(na67_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a67_2 ( .OUT(na67_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na67_1_i) ); +// C_MX4b/D/// x33y73 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a68_1 ( .OUT(na68_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na68_1), .IN6(na69_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a68_2 ( .OUT(na68_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na68_1_i) ); +// C_MX4b/D/// x33y74 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a69_1 ( .OUT(na69_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4088_2), .IN6(na69_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a69_2 ( .OUT(na69_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na69_1_i) ); +// C_MX4b/D/// x36y77 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a70_1 ( .OUT(na70_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na70_1), .IN8(na71_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a70_2 ( .OUT(na70_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na70_1_i) ); +// C_MX4b/D/// x36y80 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a71_1 ( .OUT(na71_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na72_1), .IN8(na71_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a71_2 ( .OUT(na71_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na71_1_i) ); +// C_MX4b/D/// x38y79 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a72_1 ( .OUT(na72_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na72_1), .IN8(na73_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a72_2 ( .OUT(na72_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na72_1_i) ); +// C_MX4b/D/// x40y82 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a73_1 ( .OUT(na73_1_i), .IN1(~na31_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na811_1), .IN8(na73_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a73_2 ( .OUT(na73_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na73_1_i) ); +// C_AND/D/// x69y88 80'h00_FE00_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a75_1 ( .OUT(na75_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1694_1), .IN6(1'b1), .IN7(~na115_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a75_2 ( .OUT(na75_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na75_1_i) ); +// C_AND/D//AND/D x68y88 80'h00_FE00_80_0000_0C88_5A1F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a76_1 ( .OUT(na76_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1694_2), .IN6(1'b1), .IN7(~na115_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a76_2 ( .OUT(na76_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na76_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a76_4 ( .OUT(na76_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na115_1), .IN4(~na76_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a76_5 ( .OUT(na76_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na76_2_i) ); +// C_AND/D//AND/D x68y84 80'h00_FE00_80_0000_0C88_5C5C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a78_1 ( .OUT(na78_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1696_2), .IN7(~na115_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a78_2 ( .OUT(na78_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na78_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a78_4 ( .OUT(na78_2_i), .IN1(1'b1), .IN2(na1696_1), .IN3(~na115_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a78_5 ( .OUT(na78_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na78_2_i) ); +// C_AND/D//ORAND*/D x68y82 80'h00_FE00_80_0000_0C87_5A3D +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a79_1 ( .OUT(na79_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1698_1), .IN6(1'b1), .IN7(~na115_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a79_2 ( .OUT(na79_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na79_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a79_4 ( .OUT(na79_2_i), .IN1(~na1445_2), .IN2(na1986_2), .IN3(1'b0), .IN4(~na79_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a79_5 ( .OUT(na79_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na79_2_i) ); +// C_AND/D/// x58y65 80'h00_FE00_00_0000_0888_241C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a80_1 ( .OUT(na80_1_i), .IN1(1'b1), .IN2(na81_1), .IN3(~na80_1), .IN4(~na4366_2), .IN5(~na3228_1), .IN6(na285_2), .IN7(na83_2), + .IN8(~na4153_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a80_2 ( .OUT(na80_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na80_1_i) ); +// C_AND//// x53y62 80'h00_0018_00_0000_0888_F521 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a81_1 ( .OUT(na81_1), .IN1(~na2229_1), .IN2(~na2228_2), .IN3(na332_1), .IN4(~na4432_2), .IN5(~na2229_2), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x52y75 80'h00_0060_00_0000_0C08_FF8A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a83_4 ( .OUT(na83_2), .IN1(na1314_2), .IN2(1'b1), .IN3(na506_2), .IN4(na1296_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x47y44 80'h00_FE00_80_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a84_4 ( .OUT(na84_2_i), .IN1(1'b1), .IN2(na536_2), .IN3(1'b1), .IN4(na3711_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a84_5 ( .OUT(na84_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na84_2_i) ); +// C_AND/D//AND/D x54y71 80'h00_FE00_80_0000_0C88_4F4F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a85_1 ( .OUT(na85_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), .IN8(na4089_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a85_2 ( .OUT(na85_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na85_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a85_4 ( .OUT(na85_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na54_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a85_5 ( .OUT(na85_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na85_2_i) ); +// C_AND/D/// x68y47 80'h00_FE00_00_0000_0C88_3CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a87_1 ( .OUT(na87_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1639_1), .IN7(1'b1), .IN8(~na54_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a87_2 ( .OUT(na87_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na87_1_i) ); +// C_AND/D//AND/D x65y50 80'h00_FE00_80_0000_0C88_3C33 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a88_1 ( .OUT(na88_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1639_2), .IN7(1'b1), .IN8(~na54_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a88_2 ( .OUT(na88_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na88_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a88_4 ( .OUT(na88_2_i), .IN1(1'b1), .IN2(~na88_2), .IN3(1'b1), .IN4(~na54_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a88_5 ( .OUT(na88_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na88_2_i) ); +// C_AND/D//AND/D x67y52 80'h00_FE00_80_0000_0C88_3A3A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a89_1 ( .OUT(na89_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1641_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na54_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a89_2 ( .OUT(na89_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na89_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a89_4 ( .OUT(na89_2_i), .IN1(na1641_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na54_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a89_5 ( .OUT(na89_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na89_2_i) ); +// C_ORAND*////D x61y73 80'h00_FE18_00_0000_0788_DA5D +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a90_1 ( .OUT(na90_1), .IN1(~na4253_2), .IN2(na91_1), .IN3(~na85_1), .IN4(1'b0), .IN5(na4043_1), .IN6(1'b0), .IN7(~na4365_2), + .IN8(na98_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a90_5 ( .OUT(na90_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na90_1) ); +// C_ORAND//// x69y52 80'h00_0018_00_0000_0C88_3DFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a91_1 ( .OUT(na91_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na987_1), .IN6(na4092_2), .IN7(1'b0), .IN8(~na92_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x70y50 80'h00_0018_00_0000_0C88_2CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a92_1 ( .OUT(na92_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1451_1), .IN7(na93_1), .IN8(~na55_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x68y61 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a93_1 ( .OUT(na93_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na525_1), .IN6(1'b1), .IN7(~na2041_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x65y76 80'h00_0078_00_0000_0C88_AA3A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a94_1 ( .OUT(na94_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na95_1), .IN6(1'b1), .IN7(na598_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a94_4 ( .OUT(na94_2), .IN1(na534_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na78_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x67y73 80'h00_0078_00_0000_0C88_C1C8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a95_1 ( .OUT(na95_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4489_2), .IN6(~na1993_2), .IN7(1'b1), .IN8(na1990_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a95_4 ( .OUT(na95_2), .IN1(na4489_2), .IN2(na1993_2), .IN3(1'b1), .IN4(na612_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x66y74 80'h00_0018_00_0040_0A2B_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a98_1 ( .OUT(na98_1), .IN1(1'b1), .IN2(~na1993_2), .IN3(1'b1), .IN4(~na1990_1), .IN5(1'b1), .IN6(~na3241_2), .IN7(1'b0), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x61y78 80'h00_FE00_00_0040_0A3C_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a103_1 ( .OUT(na103_1_i), .IN1(1'b1), .IN2(~na4424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4148_2), .IN6(na103_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a103_2 ( .OUT(na103_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na103_1_i) ); +// C_MX4b/D/// x62y74 80'h00_FE00_00_0040_0AC8_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a104_1 ( .OUT(na104_1_i), .IN1(na105_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4094_2), + .IN8(~na104_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a104_2 ( .OUT(na104_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na104_1_i) ); +// C_ORAND/D/// x63y75 80'h00_FE00_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a105_1 ( .OUT(na105_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na105_1), .IN6(na4090_2), .IN7(1'b0), .IN8(na3243_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a105_2 ( .OUT(na105_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na105_1_i) ); +// C_MX4b/D/// x58y75 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a107_1 ( .OUT(na107_1_i), .IN1(na105_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na107_1), + .IN8(na1628_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a107_2 ( .OUT(na107_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na107_1_i) ); +// C_MX4b/D/// x62y76 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a108_1 ( .OUT(na108_1_i), .IN1(~na105_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1630_2), + .IN8(na108_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a108_2 ( .OUT(na108_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na108_1_i) ); +// C_MX4b/D/// x59y75 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a109_1 ( .OUT(na109_1_i), .IN1(na105_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4097_2), + .IN8(na1628_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a109_2 ( .OUT(na109_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na109_1_i) ); +// C_MX4b/D/// x20y64 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a110_1 ( .OUT(na110_1_i), .IN1(1'b1), .IN2(~na1487_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1369_1), + .IN8(na110_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a110_2 ( .OUT(na110_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na110_1_i) ); +// C_MX4b/D/// x23y76 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a111_1 ( .OUT(na111_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na118_1), .IN6(na111_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a111_2 ( .OUT(na111_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na111_1_i) ); +// C_MX4b/D/// x28y74 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a112_1 ( .OUT(na112_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4099_2), .IN6(na111_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a112_2 ( .OUT(na112_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na112_1_i) ); +// C_MX4b/D/// x15y66 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a113_1 ( .OUT(na113_1_i), .IN1(1'b1), .IN2(~na1487_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4098_2), .IN6(na113_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a113_2 ( .OUT(na113_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na113_1_i) ); +// C_MX4b/D/// x21y63 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a114_1 ( .OUT(na114_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na114_1), .IN6(na113_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a114_2 ( .OUT(na114_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na114_1_i) ); +// C_MX4b/D/// x68y79 80'h00_FE00_00_0040_0A51_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a115_1 ( .OUT(na115_1_i), .IN1(na4078_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na4103_2), .IN5(~na117_1), .IN6(1'b0), .IN7(na115_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a115_2 ( .OUT(na115_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na115_1_i) ); +// C_AND///AND/ x69y75 80'h00_0078_00_0000_0C88_433A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a117_1 ( .OUT(na117_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na94_1), .IN7(~na603_2), .IN8(na98_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a117_4 ( .OUT(na117_2), .IN1(na90_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na50_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x25y75 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a118_1 ( .OUT(na118_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na118_1), .IN6(na127_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a118_2 ( .OUT(na118_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na118_1_i) ); +// C_MX4b/D/// x15y76 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a119_1 ( .OUT(na119_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na125_1), .IN6(na119_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a119_2 ( .OUT(na119_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na119_1_i) ); +// C_///AND/ x15y74 80'h00_0060_00_0000_0C08_FFC3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a120_4 ( .OUT(na120_2), .IN1(1'b1), .IN2(~na299_1), .IN3(1'b1), .IN4(na4442_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x25y53 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a121_4 ( .OUT(na121_2), .IN1(1'b1), .IN2(na122_1), .IN3(1'b1), .IN4(na1495_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x19y48 80'h00_0078_00_0000_0C88_A3F1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a122_1 ( .OUT(na122_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na120_2), .IN7(na123_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a122_4 ( .OUT(na122_2), .IN1(~na196_2), .IN2(~na122_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND*/D/// x18y63 80'h00_FE00_00_0000_0788_5FD3 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a123_1 ( .OUT(na123_1_i), .IN1(1'b0), .IN2(~na120_2), .IN3(~na123_1), .IN4(na1495_2), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a123_2 ( .OUT(na123_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na123_1_i) ); +// C_MX4b/D/// x20y60 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a124_1 ( .OUT(na124_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4105_2), .IN6(na299_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a124_2 ( .OUT(na124_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na124_1_i) ); +// C_MX4b/D/// x13y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a125_1 ( .OUT(na125_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na125_1), .IN6(na126_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a125_2 ( .OUT(na125_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na125_1_i) ); +// C_MX4b/D/// x17y70 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a126_1 ( .OUT(na126_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1367_1), .IN6(na126_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a126_2 ( .OUT(na126_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na126_1_i) ); +// C_MX4b/D/// x25y74 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a127_1 ( .OUT(na127_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na128_1), .IN6(na127_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a127_2 ( .OUT(na127_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na127_1_i) ); +// C_MX4b/D/// x25y73 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a128_1 ( .OUT(na128_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na128_1), .IN6(na4106_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a128_2 ( .OUT(na128_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na128_1_i) ); +// C_MX4b/D/// x27y71 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a129_1 ( .OUT(na129_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na129_1), .IN6(na32_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a129_2 ( .OUT(na129_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na129_1_i) ); +// C_MX4b/D/// x17y66 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a130_1 ( .OUT(na130_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na131_1), .IN6(na130_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a130_2 ( .OUT(na130_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na130_1_i) ); +// C_MX4b/D/// x17y67 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a131_1 ( .OUT(na131_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na131_1), .IN6(na132_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a131_2 ( .OUT(na131_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na131_1_i) ); +// C_MX4b/D/// x19y70 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a132_1 ( .OUT(na132_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na133_1), .IN6(na132_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a132_2 ( .OUT(na132_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na132_1_i) ); +// C_MX4b/D/// x17y75 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a133_1 ( .OUT(na133_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4107_2), + .IN8(na1365_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a133_2 ( .OUT(na133_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na133_1_i) ); +// C_MX4b/D/// x18y83 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a134_1 ( .OUT(na134_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na134_1), + .IN8(na135_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a134_2 ( .OUT(na134_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na134_1_i) ); +// C_MX4b/D/// x18y84 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a135_1 ( .OUT(na135_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na153_1), .IN6(na4108_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a135_2 ( .OUT(na135_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na135_1_i) ); +// C_MX4b/D/// x21y69 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a136_1 ( .OUT(na136_1_i), .IN1(1'b1), .IN2(na137_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na136_1), .IN6(na3147_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a136_2 ( .OUT(na136_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na136_1_i) ); +// C_///AND/ x33y70 80'h00_0060_00_0000_0C08_FF53 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a137_4 ( .OUT(na137_2), .IN1(1'b1), .IN2(~na138_1), .IN3(~na139_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x27y68 80'h00_0018_00_0000_0888_CD35 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a138_1 ( .OUT(na138_1), .IN1(~na28_1), .IN2(1'b0), .IN3(1'b0), .IN4(~na27_1), .IN5(~na21_1), .IN6(na508_2), .IN7(1'b0), .IN8(na27_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x50y75 80'h00_0018_00_0000_0888_3582 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a139_1 ( .OUT(na139_1), .IN1(na3246_1), .IN2(~na146_1), .IN3(na506_2), .IN4(na3248_1), .IN5(~na143_1), .IN6(1'b1), .IN7(1'b1), + .IN8(~na3249_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x41y69 80'h00_0018_00_0000_0888_4CC8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a143_1 ( .OUT(na143_1), .IN1(na145_1), .IN2(na690_1), .IN3(1'b1), .IN4(na4154_2), .IN5(1'b1), .IN6(na900_1), .IN7(~na4152_2), + .IN8(na16_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x47y75 80'h00_0018_00_0000_0C88_85FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a145_1 ( .OUT(na145_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1314_2), .IN6(1'b1), .IN7(na506_2), .IN8(na1296_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x53y70 80'h00_0018_00_0000_0888_28F8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a146_1 ( .OUT(na146_1), .IN1(na145_1), .IN2(na508_2), .IN3(1'b1), .IN4(1'b1), .IN5(na21_1), .IN6(na285_1), .IN7(na551_1), + .IN8(~na4154_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x19y83 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a153_1 ( .OUT(na153_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na153_1), .IN6(na154_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a153_2 ( .OUT(na153_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na153_1_i) ); +// C_MX4b/D/// x19y84 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a154_1 ( .OUT(na154_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1364_1), .IN6(na154_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a154_2 ( .OUT(na154_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na154_1_i) ); +// C_///ORAND/ x13y64 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a155_4 ( .OUT(na155_2), .IN1(~na1614_1), .IN2(~na405_2), .IN3(~na4474_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x14y68 80'h00_0018_00_0000_0C88_37FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a156_1 ( .OUT(na156_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4470_2), .IN6(~na2_2), .IN7(1'b0), .IN8(~na1610_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x19y73 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a157_1 ( .OUT(na157_1_i), .IN1(1'b1), .IN2(na137_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na157_1), .IN6(na3148_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a157_2 ( .OUT(na157_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na157_1_i) ); +// C_MX4b/D/// x19y86 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a158_1 ( .OUT(na158_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4112_2), + .IN8(na159_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a158_2 ( .OUT(na158_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na158_1_i) ); +// C_MX4b/D/// x20y84 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a159_1 ( .OUT(na159_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4113_2), + .IN8(na159_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a159_2 ( .OUT(na159_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na159_1_i) ); +// C_MX4b/D/// x17y83 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a160_1 ( .OUT(na160_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na160_1), .IN6(na161_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a160_2 ( .OUT(na160_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na160_1_i) ); +// C_MX4b/D/// x19y82 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a161_1 ( .OUT(na161_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1357_1), .IN6(na161_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a161_2 ( .OUT(na161_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na161_1_i) ); +// C_MX4b/D/// x38y68 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a162_1 ( .OUT(na162_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4170_2), + .IN8(na162_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a162_2 ( .OUT(na162_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na162_1_i) ); +// C_MX4b/D/// x13y83 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a163_1 ( .OUT(na163_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na164_1), .IN6(na4114_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a163_2 ( .OUT(na163_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na163_1_i) ); +// C_MX4b/D/// x17y81 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a164_1 ( .OUT(na164_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na164_1), .IN6(na4115_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a164_2 ( .OUT(na164_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na164_1_i) ); +// C_MX4b/D/// x17y82 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a165_1 ( .OUT(na165_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na167_1), .IN6(na165_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a165_2 ( .OUT(na165_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na165_1_i) ); +// C_MX4b/D/// x17y79 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a166_1 ( .OUT(na166_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na166_1), .IN6(na165_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a166_2 ( .OUT(na166_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na166_1_i) ); +// C_MX4b/D/// x15y77 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a167_1 ( .OUT(na167_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1355_1), .IN6(na4116_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a167_2 ( .OUT(na167_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na167_1_i) ); +// C_MX4b/D/// x15y80 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a168_1 ( .OUT(na168_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4118_2), .IN6(na168_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a168_2 ( .OUT(na168_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na168_1_i) ); +// C_MX4b/D/// x17y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a169_1 ( .OUT(na169_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na169_1), .IN6(na168_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a169_2 ( .OUT(na169_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na169_1_i) ); +// C_MX4b/D/// x16y80 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a170_1 ( .OUT(na170_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na171_1), + .IN8(na170_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a170_2 ( .OUT(na170_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na170_1_i) ); +// C_MX4b/D/// x16y77 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a171_1 ( .OUT(na171_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na171_1), + .IN8(na174_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a171_2 ( .OUT(na171_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na171_1_i) ); +// C_AND/D/// x13y47 80'h00_FE00_00_0000_0C88_A3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a173_1 ( .OUT(na173_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na299_1), .IN7(na1688_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a173_2 ( .OUT(na173_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na173_1_i) ); +// C_MX4b/D/// x16y76 80'h00_FE00_00_0040_0AC4_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a174_1 ( .OUT(na174_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na175_1), + .IN8(na174_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a174_2 ( .OUT(na174_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na174_1_i) ); +// C_MX2a//// x16y71 80'h00_0018_00_0040_0CCC_F500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a175_1 ( .OUT(na175_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na176_2), .IN4(~na187_2), .IN5(~na1370_2), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x20y69 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a176_4 ( .OUT(na176_2), .IN1(1'b1), .IN2(1'b1), .IN3(na123_1), .IN4(na3252_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x14y64 80'h00_0018_00_0000_0C88_DCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a178_1 ( .OUT(na178_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na119_1), .IN7(~na179_1), .IN8(na3254_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x18y59 80'h00_0018_00_0040_0C92_C300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a179_1 ( .OUT(na179_1), .IN1(1'b1), .IN2(na2478_1), .IN3(1'b0), .IN4(1'b1), .IN5(1'b1), .IN6(~na2478_2), .IN7(1'b1), .IN8(na4525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x15y64 80'h00_0018_00_0000_0C88_B5FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a180_1 ( .OUT(na180_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3255_1), .IN6(1'b0), .IN7(na4582_2), .IN8(~na2499_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x17y57 80'h00_0018_00_0040_0A30_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a181_1 ( .OUT(na181_1), .IN1(na182_1), .IN2(1'b1), .IN3(1'b1), .IN4(na214_2), .IN5(na832_1), .IN6(na827_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x21y55 80'h00_0018_00_0000_0C88_12FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a182_1 ( .OUT(na182_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2479_2), .IN6(~na2477_1), .IN7(~na4529_2), + .IN8(~na4527_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x20y72 80'h00_0060_00_0000_0C06_FFC6 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a187_4 ( .OUT(na187_2), .IN1(na1484_2), .IN2(na119_1), .IN3(1'b0), .IN4(na188_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x16y66 80'h00_0018_00_0000_0C88_2CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a188_1 ( .OUT(na188_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na113_1), .IN7(na189_2), .IN8(~na214_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x16y63 80'h00_0060_00_0000_0C08_FF55 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a189_4 ( .OUT(na189_2), .IN1(~na216_1), .IN2(1'b1), .IN3(~na4134_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D//AND/D x16y50 80'h00_FE00_80_0000_0C88_A333 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a190_1 ( .OUT(na190_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na299_1), .IN7(na1688_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a190_2 ( .OUT(na190_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na190_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a190_4 ( .OUT(na190_2_i), .IN1(1'b1), .IN2(~na299_1), .IN3(1'b1), .IN4(~na190_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a190_5 ( .OUT(na190_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na190_2_i) ); +// C_AND/D//AND/D x15y51 80'h00_FE00_80_0000_0C88_C3C3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a192_1 ( .OUT(na192_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na299_1), .IN7(1'b1), .IN8(na1690_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a192_2 ( .OUT(na192_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na192_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a192_4 ( .OUT(na192_2_i), .IN1(1'b1), .IN2(~na299_1), .IN3(1'b1), .IN4(na1690_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a192_5 ( .OUT(na192_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na192_2_i) ); +// C_AND/D//ORAND*/D x15y50 80'h00_FE00_80_0000_0C87_A33D +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a193_1 ( .OUT(na193_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na299_1), .IN7(na1692_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a193_2 ( .OUT(na193_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na193_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a193_4 ( .OUT(na193_2_i), .IN1(~na4444_2), .IN2(na2474_2), .IN3(1'b0), .IN4(~na4121_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a193_5 ( .OUT(na193_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na193_2_i) ); +// C_ORAND//// x25y44 80'h00_0018_00_0000_0888_FE3A +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a194_1 ( .OUT(na194_1), .IN1(na3259_1), .IN2(1'b0), .IN3(1'b0), .IN4(~na1495_2), .IN5(na196_2), .IN6(na122_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x21y59 80'h00_0060_00_0000_0C08_FF21 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a196_4 ( .OUT(na196_2), .IN1(~na886_1), .IN2(~na4542_2), .IN3(na17_1), .IN4(~na4442_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x24y50 80'h00_FE00_00_0000_0C88_38FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a197_1 ( .OUT(na197_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na210_1), .IN6(na209_1), .IN7(1'b1), .IN8(~na208_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a197_2 ( .OUT(na197_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na197_1_i) ); +// C_OR////D x25y39 80'h00_FE18_00_0000_0EEE_0C03 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a198_1 ( .OUT(na198_1), .IN1(1'b0), .IN2(~na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na3262_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a198_5 ( .OUT(na198_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na198_1) ); +// C_AND/D//AND/D x24y66 80'h00_FE00_80_0000_0C88_4F5A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a200_1 ( .OUT(na200_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), .IN8(na200_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a200_2 ( .OUT(na200_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na200_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a200_4 ( .OUT(na200_2_i), .IN1(na121_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a200_5 ( .OUT(na200_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na200_2_i) ); +// C_///AND/D x40y47 80'h00_FE00_80_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a201_4 ( .OUT(na201_2_i), .IN1(~na121_2), .IN2(1'b1), .IN3(na1709_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a201_5 ( .OUT(na201_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na201_2_i) ); +// C_AND/D/// x25y38 80'h00_FE00_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a202_1 ( .OUT(na202_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4124_2), .IN7(1'b1), .IN8(na3525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a202_2 ( .OUT(na202_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na202_1_i) ); +// C_AND////D x30y42 80'h00_FE18_00_0000_0888_53FC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a203_1 ( .OUT(na203_1), .IN1(1'b1), .IN2(na204_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na204_1), .IN7(~na201_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a203_5 ( .OUT(na203_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na203_1) ); +// C_AND/D//AND/D x39y48 80'h00_FE00_80_0000_0C88_A5F1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a204_1 ( .OUT(na204_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na121_2), .IN6(1'b1), .IN7(na1709_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a204_2 ( .OUT(na204_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na204_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a204_4 ( .OUT(na204_2_i), .IN1(~na121_2), .IN2(~na204_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a204_5 ( .OUT(na204_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na204_2_i) ); +// C_///AND/D x27y46 80'h00_FE00_80_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a205_4 ( .OUT(na205_2_i), .IN1(na4125_2), .IN2(1'b1), .IN3(1'b1), .IN4(na3525_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a205_5 ( .OUT(na205_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na205_2_i) ); +// C_AND/D//AND/D x41y44 80'h00_FE00_80_0000_0C88_C5C5 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a207_1 ( .OUT(na207_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na121_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1711_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a207_2 ( .OUT(na207_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na207_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a207_4 ( .OUT(na207_2_i), .IN1(~na121_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1711_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a207_5 ( .OUT(na207_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na207_2_i) ); +// C_MX4b/D/// x18y60 80'h00_FE00_00_0040_0AC8_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a208_1 ( .OUT(na208_1_i), .IN1(na212_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4128_2), + .IN8(~na208_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a208_2 ( .OUT(na208_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na208_1_i) ); +// C_MX4b/D/// x13y62 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a209_1 ( .OUT(na209_1_i), .IN1(na212_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4129_2), .IN6(na1714_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a209_2 ( .OUT(na209_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na209_1_i) ); +// C_MX4b/D/// x15y57 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a210_1 ( .OUT(na210_1_i), .IN1(na212_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na210_1), .IN6(na1714_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a210_2 ( .OUT(na210_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na210_1_i) ); +// C_MX4b/D/// x18y55 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a211_1 ( .OUT(na211_1_i), .IN1(~na212_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1716_1), .IN6(na4130_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a211_2 ( .OUT(na211_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na211_1_i) ); +// C_ORAND/D/// x13y55 80'h00_FE00_00_0000_0C88_AEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a212_1 ( .OUT(na212_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na212_1), .IN6(na4469_2), .IN7(na3263_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a212_2 ( .OUT(na212_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na212_1_i) ); +// C_AND/D//AND/D x20y62 80'h00_FE00_80_0000_0C88_4F88 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a214_1 ( .OUT(na214_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), .IN8(na1705_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a214_2 ( .OUT(na214_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na214_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a214_4 ( .OUT(na214_2_i), .IN1(na216_1), .IN2(na113_1), .IN3(na4134_2), .IN4(na214_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a214_5 ( .OUT(na214_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na214_2_i) ); +// C_AND/D//AND/D x27y63 80'h00_FE00_80_0000_0C88_2F4F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a216_1 ( .OUT(na216_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1707_1), .IN8(~na4366_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a216_2 ( .OUT(na216_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na216_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a216_4 ( .OUT(na216_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na1705_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a216_5 ( .OUT(na216_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na216_2_i) ); +// C_AND/D//AND/D x36y82 80'h00_FE00_80_0000_0C88_5A4F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a217_1 ( .OUT(na217_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na218_1), .IN6(1'b1), .IN7(~na1149_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a217_2 ( .OUT(na217_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na217_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a217_4 ( .OUT(na217_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na217_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a217_5 ( .OUT(na217_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na217_2_i) ); +// C_AND//// x45y79 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a218_1 ( .OUT(na218_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na219_2), .IN7(na1517_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x39y72 80'h00_0060_00_0000_0C08_FFC5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a219_4 ( .OUT(na219_2), .IN1(~na220_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1337_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x25y89 80'h00_0018_00_0000_0C88_3CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a220_1 ( .OUT(na220_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na232_1), .IN7(1'b1), .IN8(~na1347_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x57y65 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a221_1 ( .OUT(na221_1_i), .IN1(na1465_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na221_1), .IN6(na330_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a221_2 ( .OUT(na221_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na221_1_i) ); +// C_ORAND*////D x37y89 80'h00_FE18_00_0000_0788_DA3D +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a222_1 ( .OUT(na222_1), .IN1(~na1118_2), .IN2(na223_2), .IN3(1'b0), .IN4(~na217_2), .IN5(na1564_1), .IN6(1'b0), .IN7(~na1346_1), + .IN8(na229_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a222_5 ( .OUT(na222_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na222_1) ); +// C_///ORAND/ x61y76 80'h00_0060_00_0000_0C08_FF5D +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a223_4 ( .OUT(na223_2), .IN1(~na1354_1), .IN2(na4581_2), .IN3(~na224_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x58y81 80'h00_0018_00_0000_0C88_21FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a224_1 ( .OUT(na224_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2769_1), .IN6(~na219_2), .IN7(na1517_2), + .IN8(~na1050_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x35y92 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a225_4 ( .OUT(na225_2), .IN1(1'b1), .IN2(1'b1), .IN3(na226_1), .IN4(na1113_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x40y89 80'h00_0078_00_0000_0C88_528C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a226_1 ( .OUT(na226_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2712_2), .IN6(~na4553_2), .IN7(~na2713_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a226_4 ( .OUT(na226_2), .IN1(1'b1), .IN2(na4553_2), .IN3(na2713_1), .IN4(na1127_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x34y86 80'h00_0018_00_0040_0A8E_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a229_1 ( .OUT(na229_1), .IN1(na2712_2), .IN2(1'b1), .IN3(~na2713_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(~na3270_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D//AND/D x41y80 80'h00_FE00_80_0000_0C88_5E88 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a232_1 ( .OUT(na232_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(na232_1), .IN7(~na4141_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a232_2 ( .OUT(na232_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na232_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a232_4 ( .OUT(na232_2_i), .IN1(na434_1), .IN2(na4144_2), .IN3(na432_2), .IN4(na4200_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a232_5 ( .OUT(na232_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na232_2_i) ); +// C_AND///AND/ x18y69 80'h00_0078_00_0000_0C88_515C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a233_1 ( .OUT(na233_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1614_1), .IN6(~na405_2), .IN7(~na4474_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a233_4 ( .OUT(na233_2), .IN1(1'b1), .IN2(na2_1), .IN3(~na19_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x13y63 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a234_1 ( .OUT(na234_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1614_1), .IN6(1'b1), .IN7(~na4474_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x15y65 80'h00_0060_00_0000_0C08_FF31 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a235_4 ( .OUT(na235_2), .IN1(~na4471_2), .IN2(~na2_2), .IN3(1'b1), .IN4(~na1610_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x14y65 80'h00_0018_00_0000_0C88_1FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a236_1 ( .OUT(na236_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na4472_2), .IN8(~na1610_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x21y72 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a237_1 ( .OUT(na237_1_i), .IN1(1'b1), .IN2(~na137_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na3149_1), .IN6(na237_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a237_2 ( .OUT(na237_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na237_1_i) ); +// C_MX4b/D/// x32y85 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a238_1 ( .OUT(na238_1_i), .IN1(1'b1), .IN2(na232_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na238_1), + .IN8(na239_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a238_2 ( .OUT(na238_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na238_1_i) ); +// C_MX4b/D/// x32y86 80'h00_FE00_00_0040_0AC3_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a239_1 ( .OUT(na239_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na241_1), + .IN8(na239_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a239_2 ( .OUT(na239_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na239_1_i) ); +// C_MX4b/D/// x32y84 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a240_1 ( .OUT(na240_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na238_1), + .IN8(na240_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a240_2 ( .OUT(na240_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na240_1_i) ); +// C_MX4b/D/// x32y83 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a241_1 ( .OUT(na241_1_i), .IN1(1'b1), .IN2(na232_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na241_1), + .IN8(na240_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a241_2 ( .OUT(na241_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na241_1_i) ); +// C_MX4b/D/// x23y73 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a242_1 ( .OUT(na242_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na242_1), .IN6(na4146_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a242_2 ( .OUT(na242_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na242_1_i) ); +// C_MX4b/D/// x27y75 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a243_1 ( .OUT(na243_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na243_1), .IN6(na244_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a243_2 ( .OUT(na243_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na243_1_i) ); +// C_MX4b/D/// x29y74 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a244_1 ( .OUT(na244_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4147_2), .IN6(na244_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a244_2 ( .OUT(na244_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na244_1_i) ); +// C_MX4b/D/// x30y74 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a245_1 ( .OUT(na245_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na247_1), + .IN8(na245_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a245_2 ( .OUT(na245_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na245_1_i) ); +// C_MX4b/D/// x60y79 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a246_1 ( .OUT(na246_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4148_2), .IN6(na58_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a246_2 ( .OUT(na246_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na246_1_i) ); +// C_MX4b/D/// x40y73 80'h00_FE00_00_0040_0AC8_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a247_1 ( .OUT(na247_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na247_1), .IN8(~na248_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a247_2 ( .OUT(na247_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na247_1_i) ); +// C_MX2b//// x58y72 80'h00_0018_00_0040_0ACC_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a248_1 ( .OUT(na248_1), .IN1(na349_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na260_2), .IN8(~na249_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x62y68 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a249_1 ( .OUT(na249_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na326_1), .IN8(na3272_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x60y67 80'h00_0060_00_0000_0C08_FFCD +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a251_4 ( .OUT(na251_2), .IN1(~na252_1), .IN2(na3274_2), .IN3(1'b0), .IN4(na327_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x61y63 80'h00_0018_00_0040_0C92_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a252_1 ( .OUT(na252_1), .IN1(1'b1), .IN2(na2228_2), .IN3(1'b0), .IN4(1'b1), .IN5(~na2229_2), .IN6(1'b1), .IN7(na2226_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x61y67 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a253_1 ( .OUT(na253_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3278_2), .IN6(~na2248_1), .IN7(1'b0), .IN8(~na3275_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x58y59 80'h00_0018_00_0040_0AC0_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a254_1 ( .OUT(na254_1), .IN1(1'b1), .IN2(na255_2), .IN3(1'b1), .IN4(~na4160_2), .IN5(1'b0), .IN6(1'b0), .IN7(na653_1), .IN8(na648_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y60 80'h00_0060_00_0000_0C08_FF14 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a255_4 ( .OUT(na255_2), .IN1(~na2229_2), .IN2(na2228_1), .IN3(~na2226_2), .IN4(~na4508_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x60y71 80'h00_0060_00_0000_0C06_FF6C +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a260_4 ( .OUT(na260_2), .IN1(1'b0), .IN2(na261_2), .IN3(na1462_2), .IN4(na327_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y70 80'h00_0060_00_0000_0C08_FFA2 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a261_4 ( .OUT(na261_2), .IN1(na221_1), .IN2(~na295_1), .IN3(na262_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x54y63 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a262_1 ( .OUT(na262_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4161_2), .IN6(1'b1), .IN7(~na297_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x32y57 80'h00_FE00_00_0000_0C88_A5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a264_1 ( .OUT(na264_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na333_1), .IN6(1'b1), .IN7(na1722_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a264_2 ( .OUT(na264_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na264_1_i) ); +// C_AND/D//AND/D x31y60 80'h00_FE00_80_0000_0C88_A5F1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a265_1 ( .OUT(na265_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na333_1), .IN6(1'b1), .IN7(na1722_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a265_2 ( .OUT(na265_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na265_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a265_4 ( .OUT(na265_2_i), .IN1(~na333_1), .IN2(~na265_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a265_5 ( .OUT(na265_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na265_2_i) ); +// C_AND/D/// x39y63 80'h00_FE00_00_0000_0888_4412 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a266_1 ( .OUT(na266_1_i), .IN1(na145_1), .IN2(~na285_1), .IN3(~na1149_2), .IN4(~na4442_2), .IN5(~na266_1), .IN6(na285_2), + .IN7(~na17_2), .IN8(na4068_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a266_2 ( .OUT(na266_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na266_1_i) ); +// C_AND/D//ORAND*/D x45y58 80'h00_FE00_80_0000_0C87_A5B3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a268_1 ( .OUT(na268_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na333_1), .IN6(1'b1), .IN7(na1726_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a268_2 ( .OUT(na268_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na268_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a268_4 ( .OUT(na268_2_i), .IN1(1'b0), .IN2(~na268_1), .IN3(na2223_2), .IN4(~na4434_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a268_5 ( .OUT(na268_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na268_2_i) ); +// C_///AND/D x48y39 80'h00_FE00_80_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a269_4 ( .OUT(na269_2_i), .IN1(1'b1), .IN2(na273_2), .IN3(1'b1), .IN4(na3719_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a269_5 ( .OUT(na269_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na269_2_i) ); +// C_AND/D//AND/D x32y60 80'h00_FE00_80_0000_0C88_C5C5 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a270_1 ( .OUT(na270_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na333_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1724_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a270_2 ( .OUT(na270_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na270_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a270_4 ( .OUT(na270_2_i), .IN1(~na333_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1724_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a270_5 ( .OUT(na270_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na270_2_i) ); +// C_AND/D/// x48y39 80'h00_FE00_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a272_1 ( .OUT(na272_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na273_1), .IN7(1'b1), .IN8(na3719_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a272_2 ( .OUT(na272_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na272_1_i) ); +// C_AND////D x53y38 80'h00_FE18_00_0000_0888_3CF3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a273_1 ( .OUT(na273_1), .IN1(1'b1), .IN2(~na274_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na274_2), .IN7(1'b1), .IN8(~na277_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a273_5 ( .OUT(na273_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na273_1) ); +// C_AND/D//AND/D x65y38 80'h00_FE00_80_0000_0C88_A5F1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a274_1 ( .OUT(na274_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na275_2), .IN6(1'b1), .IN7(na1733_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a274_2 ( .OUT(na274_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na274_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a274_4 ( .OUT(na274_2_i), .IN1(~na275_2), .IN2(~na274_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a274_5 ( .OUT(na274_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na274_2_i) ); +// C_///AND/ x57y45 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a275_4 ( .OUT(na275_2), .IN1(na1473_2), .IN2(1'b1), .IN3(na276_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x50y55 80'h00_0018_00_0000_0C88_A3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a276_1 ( .OUT(na276_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na33_1), .IN7(na326_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x62y40 80'h00_FE00_00_0000_0C88_A5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a277_1 ( .OUT(na277_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na275_2), .IN6(1'b1), .IN7(na1733_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a277_2 ( .OUT(na277_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na277_1_i) ); +// C_AND/D//AND/D x68y35 80'h00_FE00_80_0000_0C88_C5C5 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a280_1 ( .OUT(na280_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na275_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1735_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a280_2 ( .OUT(na280_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na280_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a280_4 ( .OUT(na280_2_i), .IN1(~na275_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1735_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a280_5 ( .OUT(na280_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na280_2_i) ); +// C_AND/D//AND/D x49y66 80'h00_FE00_80_0000_0C88_5C5A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a281_1 ( .OUT(na281_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na281_2), .IN7(~na1149_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a281_2 ( .OUT(na281_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na281_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a281_4 ( .OUT(na281_2_i), .IN1(na275_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a281_5 ( .OUT(na281_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na281_2_i) ); +// C_MX4b/D/// x46y62 80'h00_FE00_00_0040_0AC8_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a282_1 ( .OUT(na282_1_i), .IN1(1'b1), .IN2(na1383_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4151_2), + .IN8(~na282_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a282_2 ( .OUT(na282_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na282_1_i) ); +// C_MX4b/D/// x46y63 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a283_1 ( .OUT(na283_1_i), .IN1(1'b1), .IN2(na1383_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na283_1), + .IN8(na1728_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a283_2 ( .OUT(na283_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na283_1_i) ); +// C_MX4b/D/// x48y62 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a284_1 ( .OUT(na284_1_i), .IN1(1'b1), .IN2(~na1383_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1730_2), + .IN8(na284_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a284_2 ( .OUT(na284_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na284_1_i) ); +// C_ORAND/D//ORAND/D x51y70 80'h00_FE00_80_0000_0C88_5B5E +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a285_1 ( .OUT(na285_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3290_2), .IN6(~na3279_1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a285_2 ( .OUT(na285_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na285_1_i) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a285_4 ( .OUT(na285_2_i), .IN1(na3290_1), .IN2(na321_1), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a285_5 ( .OUT(na285_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na285_2_i) ); +// C_AND/D//ORAND*/D x20y87 80'h00_FE00_80_0000_0C87_1CD5 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a287_1 ( .OUT(na287_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1620_1), .IN7(~na287_2), .IN8(~na4156_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a287_2 ( .OUT(na287_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na287_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a287_4 ( .OUT(na287_2_i), .IN1(~na3700_1), .IN2(1'b0), .IN3(~na287_2), .IN4(na1296_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a287_5 ( .OUT(na287_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na287_2_i) ); +// C_AND/D//AND/D x17y86 80'h00_FE00_80_0000_0C88_5252 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a288_1 ( .OUT(na288_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1618_1), .IN6(~na288_2), .IN7(~na287_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a288_2 ( .OUT(na288_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na288_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a288_4 ( .OUT(na288_2_i), .IN1(na1626_1), .IN2(~na288_2), .IN3(~na287_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a288_5 ( .OUT(na288_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na288_2_i) ); +// C_OR/D/// x14y84 80'h00_FE00_00_0000_0CEE_EC00 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a289_1 ( .OUT(na289_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1620_2), .IN7(na287_2), .IN8(na4158_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a289_2 ( .OUT(na289_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na289_1_i) ); +// C_AND/D//AND/D x16y88 80'h00_FE00_80_0000_0C88_5252 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a292_1 ( .OUT(na292_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1622_2), .IN6(~na288_2), .IN7(~na287_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a292_2 ( .OUT(na292_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na292_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a292_4 ( .OUT(na292_2_i), .IN1(na1622_1), .IN2(~na288_2), .IN3(~na287_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a292_5 ( .OUT(na292_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na292_2_i) ); +// C_///AND/D x17y76 80'h00_FE00_80_0000_0C08_FF1C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a293_4 ( .OUT(na293_2_i), .IN1(1'b1), .IN2(na1624_1), .IN3(~na287_2), .IN4(~na4156_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a293_5 ( .OUT(na293_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na293_2_i) ); +// C_///OR/D x16y81 80'h00_FE00_80_0000_0C0E_FFEC +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a294_4 ( .OUT(na294_2_i), .IN1(1'b0), .IN2(na1624_2), .IN3(na287_2), .IN4(na4158_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a294_5 ( .OUT(na294_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na294_2_i) ); +// C_AND/D//AND/D x53y64 80'h00_FE00_80_0000_0C88_4F88 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a295_1 ( .OUT(na295_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), .IN8(na1718_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a295_2 ( .OUT(na295_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na295_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a295_4 ( .OUT(na295_2_i), .IN1(na221_1), .IN2(na295_1), .IN3(na297_2), .IN4(na4162_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a295_5 ( .OUT(na295_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na295_2_i) ); +// C_AND/D//AND/D x58y63 80'h00_FE00_80_0000_0C88_2F4F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a297_1 ( .OUT(na297_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1720_1), .IN8(~na4366_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a297_2 ( .OUT(na297_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na297_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a297_4 ( .OUT(na297_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na1718_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a297_5 ( .OUT(na297_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na297_2_i) ); +// C_MX4b/D/// x17y60 80'h00_FE00_00_0040_0A31_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a299_1 ( .OUT(na299_1_i), .IN1(~na310_2), .IN2(1'b1), .IN3(1'b1), .IN4(na214_2), .IN5(~na310_1), .IN6(na299_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a299_2 ( .OUT(na299_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na299_1_i) ); +// C_ORAND//// x47y47 80'h00_0018_00_0000_0C88_3DFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a301_1 ( .OUT(na301_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na266_1), .IN6(na4069_2), .IN7(1'b0), .IN8(~na302_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x44y48 80'h00_0018_00_0000_0C88_41FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a302_1 ( .OUT(na302_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na886_1), .IN6(~na122_1), .IN7(~na2529_2), + .IN8(na1495_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x18y54 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a303_4 ( .OUT(na303_2), .IN1(1'b1), .IN2(1'b1), .IN3(na952_2), .IN4(na4166_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x20y57 80'h00_0078_00_0000_0C88_548C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a304_1 ( .OUT(na304_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4528_2), .IN6(na2478_1), .IN7(~na2481_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a304_4 ( .OUT(na304_2), .IN1(1'b1), .IN2(na2478_2), .IN3(na2481_2), .IN4(na187_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x17y53 80'h00_0018_00_0040_0A17_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a307_1 ( .OUT(na307_1), .IN1(1'b1), .IN2(na4535_2), .IN3(~na4526_2), .IN4(1'b1), .IN5(~na3287_1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x17y59 80'h00_0078_00_0000_0C88_322F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a310_1 ( .OUT(na310_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na307_1), .IN6(~na957_2), .IN7(1'b1), .IN8(~na303_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a310_4 ( .OUT(na310_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1567_1), .IN4(~na124_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x28y77 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a311_1 ( .OUT(na311_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na312_1), .IN6(na4167_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a311_2 ( .OUT(na311_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na311_1_i) ); +// C_MX4b/D/// x27y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a312_1 ( .OUT(na312_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na312_1), .IN6(na313_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a312_2 ( .OUT(na312_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na312_1_i) ); +// C_MX4b/D/// x29y78 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a313_1 ( .OUT(na313_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na314_1), .IN6(na313_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a313_2 ( .OUT(na313_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na313_1_i) ); +// C_MX4b/D/// x29y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a314_1 ( .OUT(na314_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na314_1), .IN6(na1396_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a314_2 ( .OUT(na314_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na314_1_i) ); +// C_MX4b/D/// x35y68 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a315_1 ( .OUT(na315_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na36_1), .IN6(na315_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a315_2 ( .OUT(na315_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na315_1_i) ); +// C_MX4b/D/// x23y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a316_1 ( .OUT(na316_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na316_1), .IN6(na35_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a316_2 ( .OUT(na316_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na316_1_i) ); +// C_///OR/ x22y67 80'h00_0060_00_0000_0C0E_FFCC +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a317_4 ( .OUT(na317_2), .IN1(1'b0), .IN2(na138_1), .IN3(1'b0), .IN4(na688_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x18y71 80'h00_0018_00_0000_0C88_1FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a318_1 ( .OUT(na318_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na319_2), .IN8(~na4142_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y71 80'h00_0060_00_0000_0C08_FF51 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a319_4 ( .OUT(na319_2), .IN1(~na7_2), .IN2(~na2_1), .IN3(~na11_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x25y68 80'h00_0018_00_0000_0C88_ECFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a321_1 ( .OUT(na321_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na137_2), .IN7(na319_2), .IN8(na3292_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x36y72 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a322_1 ( .OUT(na322_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na323_1), + .IN8(na322_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a322_2 ( .OUT(na322_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na322_1_i) ); +// C_MX4b/D/// x38y69 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a323_1 ( .OUT(na323_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na323_1), .IN8(na162_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a323_2 ( .OUT(na323_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na323_1_i) ); +// C_MX4b/D/// x33y68 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a324_1 ( .OUT(na324_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na325_1), .IN6(na324_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a324_2 ( .OUT(na324_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na324_1_i) ); +// C_MX4b/D/// x35y65 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a325_1 ( .OUT(na325_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na325_1), .IN6(na315_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a325_2 ( .OUT(na325_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na325_1_i) ); +// C_ORAND*/D/// x50y63 80'h00_FE00_00_0000_0788_5FD3 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a326_1 ( .OUT(na326_1_i), .IN1(1'b0), .IN2(~na33_1), .IN3(~na326_1), .IN4(na4437_2), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a326_2 ( .OUT(na326_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na326_1_i) ); +// C_MX4b/D/// x52y78 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a327_1 ( .OUT(na327_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4169_2), + .IN8(na327_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a327_2 ( .OUT(na327_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na327_1_i) ); +// C_MX4b/D/// x20y75 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a328_1 ( .OUT(na328_1_i), .IN1(1'b1), .IN2(na137_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na328_1), + .IN8(na3150_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a328_2 ( .OUT(na328_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na328_1_i) ); +// C_MX4b/D/// x51y65 80'h00_FE00_00_0040_0A3C_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a329_1 ( .OUT(na329_1_i), .IN1(na1465_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na329_1), .IN6(na331_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a329_2 ( .OUT(na329_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na329_1_i) ); +// C_MX4b/D/// x51y66 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a330_1 ( .OUT(na330_1_i), .IN1(~na1465_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na329_1), .IN6(na330_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a330_2 ( .OUT(na330_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na330_1_i) ); +// C_MX4b/D/// x57y68 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a331_1 ( .OUT(na331_1_i), .IN1(~na1465_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na221_1), .IN6(na331_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a331_2 ( .OUT(na331_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na331_1_i) ); +// C_MX4b/D/// x50y61 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a332_1 ( .OUT(na332_1_i), .IN1(~na1465_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na333_1), .IN6(na4172_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a332_2 ( .OUT(na332_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na332_1_i) ); +// C_MX4b/D/// x45y59 80'h00_FE00_00_0040_0A32_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a333_1 ( .OUT(na333_1_i), .IN1(1'b1), .IN2(na346_2), .IN3(1'b1), .IN4(na4160_2), .IN5(na333_1), .IN6(~na346_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a333_2 ( .OUT(na333_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na333_1_i) ); +// C_ORAND*////D x51y61 80'h00_FE18_00_0000_0788_ADD3 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a335_1 ( .OUT(na335_1), .IN1(1'b0), .IN2(~na281_1), .IN3(~na790_2), .IN4(na336_2), .IN5(~na358_2), .IN6(na343_1), .IN7(na1570_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a335_5 ( .OUT(na335_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na335_1) ); +// C_///ORAND/ x66y42 80'h00_0060_00_0000_0C08_FFD5 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a336_4 ( .OUT(na336_2), .IN1(~na337_2), .IN2(1'b0), .IN3(~na80_1), .IN4(na338_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y39 80'h00_0060_00_0000_0C08_FF4A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a337_4 ( .OUT(na337_2), .IN1(na1473_2), .IN2(1'b1), .IN3(~na276_1), .IN4(na338_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y56 80'h00_0060_00_0000_0C08_FF55 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a338_4 ( .OUT(na338_2), .IN1(~na709_1), .IN2(1'b1), .IN3(~na2278_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x52y64 80'h00_0060_00_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a340_4 ( .OUT(na340_2), .IN1(na785_2), .IN2(na341_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x59y60 80'h00_0078_00_0000_0C88_348A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a341_1 ( .OUT(na341_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2229_1), .IN6(na2228_2), .IN7(1'b1), .IN8(~na4511_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a341_4 ( .OUT(na341_2), .IN1(na2229_1), .IN2(1'b1), .IN3(na260_2), .IN4(na4511_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x55y62 80'h00_0018_00_0040_0A17_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a343_1 ( .OUT(na343_1), .IN1(1'b1), .IN2(~na2228_2), .IN3(1'b1), .IN4(na4510_2), .IN5(~na3298_1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x51y64 80'h00_0078_00_0000_0C88_1C5A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a346_1 ( .OUT(na346_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na343_1), .IN7(~na790_2), .IN8(~na340_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a346_4 ( .OUT(na346_2), .IN1(na335_1), .IN2(1'b1), .IN3(~na332_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/D x59y71 80'h00_FE00_80_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a349_4 ( .OUT(na349_2_i), .IN1(na350_1), .IN2(na3301_1), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a349_5 ( .OUT(na349_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na349_2_i) ); +// C_MX4a//// x59y63 80'h00_0018_00_0040_0C14_3300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a350_1 ( .OUT(na350_1), .IN1(1'b1), .IN2(1'b0), .IN3(na3302_2), .IN4(1'b0), .IN5(1'b1), .IN6(~na357_1), .IN7(1'b1), .IN8(~na4511_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x71y55 80'h00_0018_00_0040_0CAA_1F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a351_1 ( .OUT(na351_1), .IN1(1'b0), .IN2(~na352_1), .IN3(1'b0), .IN4(~na4178_2), .IN5(1'b1), .IN6(1'b1), .IN7(~na2223_1), + .IN8(~na4504_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b////D x67y54 80'h00_FA18_00_0040_0AF1_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a352_1 ( .OUT(na352_1), .IN1(1'b1), .IN2(na4175_2), .IN3(1'b1), .IN4(na720_1), .IN5(~na355_1), .IN6(na1466_1), .IN7(na4433_2), + .IN8(na4177_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a352_5 ( .OUT(na352_2), .CLK(na1739_1), .EN(na1465_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na352_1) ); +// C_MX2b//// x64y53 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a353_1 ( .OUT(na353_1), .IN1(1'b1), .IN2(~na2228_1), .IN3(1'b0), .IN4(1'b0), .IN5(na4176_2), .IN6(na3276_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x54y35 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a354_1 ( .OUT(na354_1), .IN1(1'b1), .IN2(~na273_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na3726_1), .IN8(~na714_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x63y57 80'h00_0018_00_0000_0C88_DCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a355_1 ( .OUT(na355_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na295_2), .IN7(~na2223_1), .IN8(na3305_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x62y53 80'h00_0018_00_0000_0C88_6AFF +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a356_1 ( .OUT(na356_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1465_1), .IN6(1'b0), .IN7(~na353_1), .IN8(na720_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x59y64 80'h00_0018_00_0000_0C88_48FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a357_1 ( .OUT(na357_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na333_1), .IN6(na295_2), .IN7(~na4507_2), .IN8(na4510_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x51y53 80'h00_FE00_80_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a358_4 ( .OUT(na358_2_i), .IN1(na333_1), .IN2(na295_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a358_5 ( .OUT(na358_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na358_2_i) ); +// C_AND/D//AND/D x65y79 80'h00_FE00_80_0000_0C88_2F2F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a360_1 ( .OUT(na360_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1643_2), .IN8(~na4366_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a360_2 ( .OUT(na360_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na360_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a360_4 ( .OUT(na360_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1643_1), .IN4(~na4366_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a360_5 ( .OUT(na360_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na360_2_i) ); +// C_MX4b/D/// x23y88 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a361_1 ( .OUT(na361_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na370_1), .IN6(na361_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a361_2 ( .OUT(na361_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na361_1_i) ); +// C_MX2b////D x58y67 80'h00_FA18_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a362_1 ( .OUT(na362_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4153_2), .IN5(na543_1), .IN6(1'b0), .IN7(na3151_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a362_5 ( .OUT(na362_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na362_1) ); +// C_MX2b////D x54y65 80'h00_FA18_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a363_1 ( .OUT(na363_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4153_2), .IN5(na543_2), .IN6(1'b0), .IN7(na3152_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a363_5 ( .OUT(na363_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na363_1) ); +// C_MX2b////D x50y68 80'h00_FA18_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a364_1 ( .OUT(na364_1), .IN1(1'b1), .IN2(~na285_1), .IN3(1'b0), .IN4(1'b0), .IN5(na545_1), .IN6(na3153_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a364_5 ( .OUT(na364_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na364_1) ); +// C_MX2b////D x54y69 80'h00_FA18_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a365_1 ( .OUT(na365_1), .IN1(1'b1), .IN2(~na285_1), .IN3(1'b0), .IN4(1'b0), .IN5(na545_2), .IN6(na3154_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a365_5 ( .OUT(na365_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na365_1) ); +// C_MX2b////D x56y68 80'h00_FA18_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a366_1 ( .OUT(na366_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4153_2), .IN5(na3155_1), .IN6(1'b0), .IN7(na547_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a366_5 ( .OUT(na366_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na366_1) ); +// C_MX2b////D x52y63 80'h00_FA18_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a367_1 ( .OUT(na367_1), .IN1(1'b1), .IN2(~na285_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na547_2), .IN8(na3156_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a367_5 ( .OUT(na367_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na367_1) ); +// C_MX2b////D x54y67 80'h00_FA18_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a368_1 ( .OUT(na368_1), .IN1(1'b1), .IN2(~na285_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na549_1), .IN8(na3157_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a368_5 ( .OUT(na368_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na368_1) ); +// C_MX2b////D x56y70 80'h00_FA18_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a369_1 ( .OUT(na369_1), .IN1(1'b1), .IN2(~na285_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na549_2), .IN8(na3158_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a369_5 ( .OUT(na369_2), .CLK(na1739_1), .EN(na372_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na369_1) ); +// C_MX4b/D/// x23y89 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a370_1 ( .OUT(na370_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4189_2), + .IN8(na371_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a370_2 ( .OUT(na370_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na370_1_i) ); +// C_MX4b/D/// x26y88 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a371_1 ( .OUT(na371_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4190_2), .IN6(na373_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a371_2 ( .OUT(na371_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na371_1_i) ); +// C_AND//// x49y75 80'h00_0018_00_0000_0C88_4AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a372_1 ( .OUT(na372_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4400_2), .IN6(1'b1), .IN7(~na287_2), .IN8(na1296_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x23y90 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a373_1 ( .OUT(na373_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na374_1), .IN6(na373_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a373_2 ( .OUT(na373_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na373_1_i) ); +// C_MX4b/D/// x21y89 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a374_1 ( .OUT(na374_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na384_1), + .IN8(na4191_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a374_2 ( .OUT(na374_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na374_1_i) ); +// C_MX2b/D/// x43y77 80'h00_F600_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a375_1 ( .OUT(na375_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na376_1), .IN5(na4181_2), .IN6(1'b0), .IN7(na362_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a375_2 ( .OUT(na375_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na375_1_i) ); +// C_ORAND//// x38y76 80'h00_0018_00_0000_0C88_BAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a376_1 ( .OUT(na376_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4400_2), .IN6(1'b0), .IN7(na287_2), .IN8(~na1296_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x42y75 80'h00_F600_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a377_1 ( .OUT(na377_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na376_1), .IN5(na4182_2), .IN6(1'b0), .IN7(na363_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a377_2 ( .OUT(na377_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na377_1_i) ); +// C_MX2b/D/// x37y72 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a378_1 ( .OUT(na378_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na376_1), .IN5(1'b0), .IN6(na4183_2), .IN7(1'b0), .IN8(na364_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a378_2 ( .OUT(na378_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na378_1_i) ); +// C_MX2b/D/// x41y73 80'h00_F600_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a379_1 ( .OUT(na379_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na376_1), .IN5(na4184_2), .IN6(1'b0), .IN7(na365_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a379_2 ( .OUT(na379_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na379_1_i) ); +// C_MX2b/D/// x44y74 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a380_1 ( .OUT(na380_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na376_1), .IN5(1'b0), .IN6(na4185_2), .IN7(1'b0), .IN8(na366_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a380_2 ( .OUT(na380_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na380_1_i) ); +// C_MX2b/D/// x42y73 80'h00_F600_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a381_1 ( .OUT(na381_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na376_1), .IN5(na4186_2), .IN6(1'b0), .IN7(na367_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a381_2 ( .OUT(na381_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na381_1_i) ); +// C_MX2b/D/// x43y76 80'h00_F600_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a382_1 ( .OUT(na382_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na376_1), .IN5(na4187_2), .IN6(1'b0), .IN7(na368_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a382_2 ( .OUT(na382_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na382_1_i) ); +// C_MX2b/D/// x42y78 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a383_1 ( .OUT(na383_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na376_1), .IN5(1'b0), .IN6(na4188_2), .IN7(1'b0), .IN8(na369_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a383_2 ( .OUT(na383_1), .CLK(na1739_1), .EN(~na1398_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na383_1_i) ); +// C_MX4b/D/// x24y91 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a384_1 ( .OUT(na384_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na384_1), + .IN8(na1332_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a384_2 ( .OUT(na384_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na384_1_i) ); +// C_///AND/D x13y84 80'h00_FE00_80_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a387_4 ( .OUT(na387_2_i), .IN1(na1666_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1347_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a387_5 ( .OUT(na387_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na387_2_i) ); +// C_AND/D//AND/D x18y89 80'h00_FE00_80_0000_0C88_3A1F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a388_1 ( .OUT(na388_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1666_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na1347_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a388_2 ( .OUT(na388_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na388_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a388_4 ( .OUT(na388_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na388_2), .IN4(~na1347_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a388_5 ( .OUT(na388_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na388_2_i) ); +// C_AND/D//AND/D x19y89 80'h00_FE00_80_0000_0C88_3C3C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a390_1 ( .OUT(na390_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1668_2), .IN7(1'b1), .IN8(~na1347_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a390_2 ( .OUT(na390_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na390_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a390_4 ( .OUT(na390_2_i), .IN1(1'b1), .IN2(na1668_1), .IN3(1'b1), .IN4(~na1347_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a390_5 ( .OUT(na390_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na390_2_i) ); +// C_AND/D//ORAND*/D x25y92 80'h00_FE00_80_0000_0C87_3AD3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a391_1 ( .OUT(na391_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1670_1), .IN6(1'b1), .IN7(1'b1), .IN8(~na1347_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a391_2 ( .OUT(na391_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na391_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a391_4 ( .OUT(na391_2_i), .IN1(1'b0), .IN2(~na391_1), .IN3(~na1511_2), .IN4(na2707_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a391_5 ( .OUT(na391_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na391_2_i) ); +// C_AND/D/// x50y78 80'h00_FE00_00_0000_0888_1221 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a392_1 ( .OUT(na392_1_i), .IN1(~na456_1), .IN2(~na4367_2), .IN3(na9_1), .IN4(~na392_1), .IN5(na145_1), .IN6(~na285_1), .IN7(~na9_2), + .IN8(~na4154_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a392_2 ( .OUT(na392_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na392_1_i) ); +// C_ORAND//// x15y65 80'h00_0018_00_0000_0C88_AEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a394_1 ( .OUT(na394_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1614_1), .IN6(na405_2), .IN7(na4474_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x14y65 80'h00_0060_00_0000_0C08_FFCE +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a395_4 ( .OUT(na395_2), .IN1(na4470_2), .IN2(na2_2), .IN3(1'b0), .IN4(na1610_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x22y72 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a396_1 ( .OUT(na396_1_i), .IN1(1'b1), .IN2(~na137_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3160_1), + .IN8(na396_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a396_2 ( .OUT(na396_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na396_1_i) ); +// C_AND/D/// x40y55 80'h00_FE00_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a397_1 ( .OUT(na397_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na399_2), .IN6(1'b1), .IN7(1'b1), .IN8(na3413_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a397_2 ( .OUT(na397_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na397_1_i) ); +// C_AND/D/// x42y55 80'h00_FE00_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a398_1 ( .OUT(na398_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na399_1), .IN6(1'b1), .IN7(1'b1), .IN8(na3413_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a398_2 ( .OUT(na398_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na398_1_i) ); +// C_AND////D x41y61 80'h00_FE18_00_0000_0888_F35C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a399_1 ( .OUT(na399_1), .IN1(1'b1), .IN2(na403_2), .IN3(~na402_2), .IN4(1'b1), .IN5(1'b1), .IN6(~na403_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a399_5 ( .OUT(na399_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na399_1) ); +// C_///AND/D x52y83 80'h00_FE00_80_0000_0C08_FFC5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a402_4 ( .OUT(na402_2_i), .IN1(~na218_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1678_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a402_5 ( .OUT(na402_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na402_2_i) ); +// C_AND/D//AND/D x45y82 80'h00_FE00_80_0000_0C88_C5F1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a403_1 ( .OUT(na403_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na218_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1678_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a403_2 ( .OUT(na403_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na403_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a403_4 ( .OUT(na403_2_i), .IN1(~na218_1), .IN2(~na403_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a403_5 ( .OUT(na403_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na403_2_i) ); +// C_///ORAND/ x25y68 80'h00_0060_00_0000_0C08_FFE3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a405_4 ( .OUT(na405_2), .IN1(1'b0), .IN2(~na138_1), .IN3(na407_2), .IN4(na3310_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x34y63 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a407_4 ( .OUT(na407_2), .IN1(~na1290_1), .IN2(1'b1), .IN3(na8_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x29y71 80'h00_0018_00_0000_0C88_F4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a408_1 ( .OUT(na408_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na984_1), .IN6(na12_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x50y90 80'h00_FE00_00_0040_0AC8_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a409_1 ( .OUT(na409_1_i), .IN1(na430_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4192_2), + .IN8(~na409_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a409_2 ( .OUT(na409_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na409_1_i) ); +// C_MX4b/D/// x41y87 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a410_1 ( .OUT(na410_1_i), .IN1(~na430_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1685_1), + .IN8(na4193_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a410_2 ( .OUT(na410_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na410_1_i) ); +// C_MX2b/D/// x17y85 80'h00_F600_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a411_1 ( .OUT(na411_1_i), .IN1(1'b1), .IN2(na288_2), .IN3(1'b0), .IN4(1'b0), .IN5(na375_1), .IN6(na412_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a411_2 ( .OUT(na411_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na411_1_i) ); +// C_MX2b/D/// x21y82 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a412_1 ( .OUT(na412_1_i), .IN1(1'b1), .IN2(na288_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na377_1), .IN8(na413_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a412_2 ( .OUT(na412_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na412_1_i) ); +// C_MX2b/D/// x22y80 80'h00_F600_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a413_1 ( .OUT(na413_1_i), .IN1(1'b1), .IN2(~na288_2), .IN3(1'b0), .IN4(1'b0), .IN5(na414_1), .IN6(na378_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a413_2 ( .OUT(na413_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na413_1_i) ); +// C_MX2b/D/// x25y79 80'h00_F600_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a414_1 ( .OUT(na414_1_i), .IN1(1'b1), .IN2(na288_2), .IN3(1'b0), .IN4(1'b0), .IN5(na379_1), .IN6(na415_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a414_2 ( .OUT(na414_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na414_1_i) ); +// C_MX2b/D/// x25y78 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a415_1 ( .OUT(na415_1_i), .IN1(1'b1), .IN2(~na288_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na416_1), .IN8(na380_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a415_2 ( .OUT(na415_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na415_1_i) ); +// C_MX2b/D/// x26y79 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a416_1 ( .OUT(na416_1_i), .IN1(1'b1), .IN2(na288_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na381_1), .IN8(na417_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a416_2 ( .OUT(na416_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na416_1_i) ); +// C_MX2b/D/// x26y82 80'h00_F600_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a417_1 ( .OUT(na417_1_i), .IN1(1'b1), .IN2(~na288_2), .IN3(1'b0), .IN4(1'b0), .IN5(na418_1), .IN6(na382_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a417_2 ( .OUT(na417_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na417_1_i) ); +// C_MX2b/D/// x21y83 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a418_1 ( .OUT(na418_1_i), .IN1(1'b1), .IN2(~na288_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1351_2), .IN8(na383_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a418_2 ( .OUT(na418_1), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na418_1_i) ); +// C_///AND/ x28y70 80'h00_0060_00_0000_0C08_FF51 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a420_4 ( .OUT(na420_2), .IN1(~na7_2), .IN2(~na2_1), .IN3(~na3312_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x23y64 80'h00_0018_00_0000_0888_FE3C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a421_1 ( .OUT(na421_1), .IN1(1'b0), .IN2(na3313_1), .IN3(1'b0), .IN4(~na1539_1), .IN5(na425_2), .IN6(na423_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x25y66 80'h00_0078_00_0000_0C88_A3F1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a423_1 ( .OUT(na423_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na424_2), .IN7(na531_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a423_4 ( .OUT(na423_2), .IN1(~na425_2), .IN2(~na423_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x33y82 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a424_4 ( .OUT(na424_2), .IN1(na456_1), .IN2(1'b1), .IN3(~na443_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x51y81 80'h00_0060_00_0000_0C08_FF21 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a425_4 ( .OUT(na425_2), .IN1(~na456_1), .IN2(~na4372_2), .IN3(na9_1), .IN4(~na3014_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x32y67 80'h00_FE00_00_0000_0C88_2CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a426_1 ( .OUT(na426_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na929_1), .IN7(na928_1), .IN8(~na926_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a426_2 ( .OUT(na426_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na426_1_i) ); +// C_OR////D x25y56 80'h00_FE18_00_0000_0EEE_03C0 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a427_1 ( .OUT(na427_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3316_1), .IN5(1'b0), .IN6(~na421_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a427_5 ( .OUT(na427_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na427_1) ); +// C_MX4b/D/// x57y74 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a428_1 ( .OUT(na428_1_i), .IN1(~na105_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1630_1), + .IN8(na4196_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a428_2 ( .OUT(na428_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na428_1_i) ); +// C_MX4b/D/// x44y88 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a429_1 ( .OUT(na429_1_i), .IN1(~na430_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1685_2), + .IN8(na429_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a429_2 ( .OUT(na429_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na429_1_i) ); +// C_///ORAND/D x47y89 80'h00_FE00_80_0000_0C08_FFAE +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a430_4 ( .OUT(na430_2_i), .IN1(na430_2), .IN2(na4138_2), .IN3(na3317_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a430_5 ( .OUT(na430_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na430_2_i) ); +// C_///AND/D x36y87 80'h00_FE00_80_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a432_4 ( .OUT(na432_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na1674_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a432_5 ( .OUT(na432_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na432_2_i) ); +// C_AND/D//AND/D x35y91 80'h00_FE00_80_0000_0C88_2F4F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a434_1 ( .OUT(na434_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1676_1), .IN8(~na4366_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a434_2 ( .OUT(na434_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na434_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a434_4 ( .OUT(na434_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na1674_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a434_5 ( .OUT(na434_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na434_2_i) ); +// C_AND/D//AND/D x35y73 80'h00_FE00_80_0000_0C88_5A5A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a435_1 ( .OUT(na435_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na436_1), .IN6(1'b1), .IN7(~na1149_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a435_2 ( .OUT(na435_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na435_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a435_4 ( .OUT(na435_2_i), .IN1(na435_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a435_5 ( .OUT(na435_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na435_2_i) ); +// C_AND//// x33y65 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a436_1 ( .OUT(na436_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na423_1), .IN7(1'b1), .IN8(na1539_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x48y42 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a437_1 ( .OUT(na437_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4228_2), .IN5(na438_1), .IN6(1'b0), .IN7(na3717_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a437_2 ( .OUT(na437_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na437_1_i) ); +// C_MX2b/D/// x49y39 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a438_1 ( .OUT(na438_1_i), .IN1(1'b1), .IN2(na536_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na439_1), .IN8(na3716_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a438_2 ( .OUT(na438_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na438_1_i) ); +// C_MX2b/D/// x50y39 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a439_1 ( .OUT(na439_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4228_2), .IN5(1'b0), .IN6(na440_1), .IN7(1'b0), .IN8(na3715_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a439_2 ( .OUT(na439_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na439_1_i) ); +// C_MX2b/D/// x47y40 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a440_1 ( .OUT(na440_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4228_2), .IN5(na441_1), .IN6(1'b0), .IN7(na3714_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a440_2 ( .OUT(na440_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na440_1_i) ); +// C_MX2b/D/// x47y37 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a441_1 ( .OUT(na441_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4228_2), .IN5(na442_1), .IN6(1'b0), .IN7(na3713_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a441_2 ( .OUT(na441_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na441_1_i) ); +// C_MX2b/D/// x45y39 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a442_1 ( .OUT(na442_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4228_2), .IN5(1'b0), .IN6(na84_2), .IN7(1'b0), .IN8(na3712_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a442_2 ( .OUT(na442_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na442_1_i) ); +// C_MX4b/D/// x62y89 80'h00_FE00_00_0040_0A51_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a443_1 ( .OUT(na443_1_i), .IN1(na456_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na4204_2), .IN5(~na455_1), .IN6(1'b0), .IN7(na443_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a443_2 ( .OUT(na443_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na443_1_i) ); +// C_ORAND*////D x51y83 80'h00_FE18_00_0000_0788_ABB5 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a445_1 ( .OUT(na445_1), .IN1(~na435_2), .IN2(1'b0), .IN3(na446_2), .IN4(~na4398_2), .IN5(na452_1), .IN6(~na469_2), .IN7(na1574_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a445_5 ( .OUT(na445_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na445_1) ); +// C_///ORAND/ x40y63 80'h00_0060_00_0000_0C08_FFB5 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a446_4 ( .OUT(na446_2), .IN1(~na447_2), .IN2(1'b0), .IN3(na9_2), .IN4(~na392_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y61 80'h00_0060_00_0000_0C08_FF12 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a447_4 ( .OUT(na447_2), .IN1(na4460_2), .IN2(~na423_1), .IN3(~na1198_1), .IN4(~na3014_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y83 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a449_4 ( .OUT(na449_2), .IN1(na1255_2), .IN2(1'b1), .IN3(1'b1), .IN4(na450_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x56y88 80'h00_0078_00_0000_0C88_32A8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a450_1 ( .OUT(na450_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2962_1), .IN6(~na2965_2), .IN7(1'b1), .IN8(~na4571_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a450_4 ( .OUT(na450_2), .IN1(na2962_2), .IN2(na2965_2), .IN3(na1269_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x57y87 80'h00_0018_00_0040_0A4D_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a452_1 ( .OUT(na452_1), .IN1(1'b1), .IN2(na2965_2), .IN3(1'b1), .IN4(na4568_2), .IN5(1'b1), .IN6(1'b0), .IN7(~na3324_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x57y89 80'h00_0078_00_0000_0C88_523C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a455_1 ( .OUT(na455_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na452_1), .IN6(~na1260_2), .IN7(~na449_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a455_4 ( .OUT(na455_2), .IN1(1'b1), .IN2(na4203_2), .IN3(1'b1), .IN4(~na518_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D//AND/D x53y77 80'h00_FE00_80_0000_0C88_5E88 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a456_1 ( .OUT(na456_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na456_1), .IN6(na4202_2), .IN7(~na4206_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a456_2 ( .OUT(na456_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na456_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a456_4 ( .OUT(na456_2_i), .IN1(na507_1), .IN2(na4333_2), .IN3(na980_2), .IN4(na986_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a456_5 ( .OUT(na456_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na456_2_i) ); +// C_ORAND/D/// x49y87 80'h00_FE00_00_0000_0C88_5EFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a457_1 ( .OUT(na457_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na458_1), .IN6(na3327_1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a457_2 ( .OUT(na457_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na457_1_i) ); +// C_MX4a//// x59y89 80'h00_0018_00_0040_0C28_3C00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a458_1 ( .OUT(na458_1), .IN1(1'b0), .IN2(1'b1), .IN3(1'b0), .IN4(na3328_2), .IN5(1'b1), .IN6(na468_2), .IN7(1'b1), .IN8(~na4571_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x66y85 80'h00_0018_00_0040_0C55_1000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a459_1 ( .OUT(na459_1), .IN1(~na460_1), .IN2(1'b0), .IN3(~na467_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na2958_2), + .IN8(~na4565_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b////D x65y85 80'h00_FA18_00_0040_0AF4_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a460_1 ( .OUT(na460_1), .IN1(1'b1), .IN2(na4209_2), .IN3(1'b1), .IN4(~na1388_1), .IN5(na1532_1), .IN6(na466_1), .IN7(~na4211_2), + .IN8(na4456_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a460_5 ( .OUT(na460_2), .CLK(na1739_1), .EN(na456_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na460_1) ); +// C_MX2b//// x66y83 80'h00_0018_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a461_1 ( .OUT(na461_1), .IN1(~na2963_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na465_1), .IN8(na3329_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x56y83 80'h00_0018_00_0040_0A30_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a462_1 ( .OUT(na462_1), .IN1(na463_1), .IN2(1'b1), .IN3(1'b1), .IN4(na4207_2), .IN5(na1156_1), .IN6(na1151_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x59y85 80'h00_0018_00_0000_0C88_12FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a463_1 ( .OUT(na463_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2963_2), .IN6(~na4569_2), .IN7(~na2961_1), + .IN8(~na4568_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x38y55 80'h00_0018_00_0040_0ACC_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a465_1 ( .OUT(na465_1), .IN1(~na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na3444_1), .IN8(~na1358_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x63y84 80'h00_0018_00_0000_0C88_DAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a466_1 ( .OUT(na466_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na456_2), .IN6(1'b0), .IN7(~na2958_1), .IN8(na3331_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x68y83 80'h00_0018_00_0000_0C88_6AFF +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a467_1 ( .OUT(na467_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1531_2), .IN6(1'b0), .IN7(~na461_1), .IN8(na1388_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y84 80'h00_0060_00_0000_0C08_FF28 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a468_4 ( .OUT(na468_2), .IN1(na456_2), .IN2(na2965_2), .IN3(na443_1), .IN4(~na4568_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x51y86 80'h00_FE00_80_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a469_4 ( .OUT(na469_2_i), .IN1(na456_2), .IN2(1'b1), .IN3(na443_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a469_5 ( .OUT(na469_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na469_2_i) ); +// C_MX2b/D/// x63y64 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a470_1 ( .OUT(na470_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na2124_1), .IN8(na471_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a470_2 ( .OUT(na470_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na470_1_i) ); +// C_MX2b/D/// x60y62 80'h00_F600_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a471_1 ( .OUT(na471_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1887_2), .IN6(na472_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a471_2 ( .OUT(na471_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na471_1_i) ); +// C_MX2b/D/// x61y58 80'h00_F600_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a472_1 ( .OUT(na472_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1443_2), .IN5(na1887_1), .IN6(1'b0), .IN7(na473_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a472_2 ( .OUT(na472_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na472_1_i) ); +// C_MX2b/D/// x60y57 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a473_1 ( .OUT(na473_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na474_1), .IN6(1'b0), .IN7(na1889_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a473_2 ( .OUT(na473_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na473_1_i) ); +// C_MX2b/D/// x55y57 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a474_1 ( .OUT(na474_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1889_1), .IN8(na480_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a474_2 ( .OUT(na474_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na474_1_i) ); +// C_MX2b/D/// x67y63 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a475_1 ( .OUT(na475_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1866_2), .IN8(na476_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a475_2 ( .OUT(na475_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na475_1_i) ); +// C_MX2b/D/// x62y64 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a476_1 ( .OUT(na476_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na477_1), .IN6(1'b0), .IN7(na1866_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a476_2 ( .OUT(na476_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na476_1_i) ); +// C_MX2b/D/// x59y57 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a477_1 ( .OUT(na477_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1868_2), .IN8(na478_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a477_2 ( .OUT(na477_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na477_1_i) ); +// C_MX2b/D/// x56y58 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a478_1 ( .OUT(na478_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1868_1), .IN8(na479_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a478_2 ( .OUT(na478_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na478_1_i) ); +// C_MX2b/D/// x48y50 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a479_1 ( .OUT(na479_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3718_1), .IN8(na480_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a479_2 ( .OUT(na479_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na479_1_i) ); +// C_MX2b/D/// x50y50 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a480_1 ( .OUT(na480_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na481_1), .IN6(1'b0), .IN7(na3717_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a480_2 ( .OUT(na480_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na480_1_i) ); +// C_MX2b/D/// x51y47 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a481_1 ( .OUT(na481_1_i), .IN1(1'b1), .IN2(~na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na482_1), .IN8(na3716_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a481_2 ( .OUT(na481_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na481_1_i) ); +// C_MX2b/D/// x50y47 80'h00_F600_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a482_1 ( .OUT(na482_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1443_2), .IN5(1'b0), .IN6(na483_1), .IN7(1'b0), .IN8(na3715_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a482_2 ( .OUT(na482_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na482_1_i) ); +// C_MX2b/D/// x49y48 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a483_1 ( .OUT(na483_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3714_1), .IN8(na484_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a483_2 ( .OUT(na483_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na483_1_i) ); +// C_MX2b/D/// x50y48 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a484_1 ( .OUT(na484_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na1579_1), .IN6(1'b0), .IN7(na3713_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a484_2 ( .OUT(na484_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na484_1_i) ); +// C_MX2b/D/// x64y64 80'h00_F600_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a485_1 ( .OUT(na485_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b0), .IN4(1'b0), .IN5(na4502_2), .IN6(na1993_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a485_2 ( .OUT(na485_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na485_1_i) ); +// C_MX2b/D/// x69y63 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a486_1 ( .OUT(na486_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1866_2), .IN8(na487_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a486_2 ( .OUT(na486_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na486_1_i) ); +// C_MX2b/D/// x68y62 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a487_1 ( .OUT(na487_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1891_2), .IN8(na488_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a487_2 ( .OUT(na487_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na487_1_i) ); +// C_MX2b/D/// x66y62 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a488_1 ( .OUT(na488_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na489_1), .IN6(1'b0), .IN7(na1891_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a488_2 ( .OUT(na488_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na488_1_i) ); +// C_MX2b/D/// x65y61 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a489_1 ( .OUT(na489_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na490_1), .IN6(1'b0), .IN7(na1893_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a489_2 ( .OUT(na489_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na489_1_i) ); +// C_MX2b/D/// x65y59 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a490_1 ( .OUT(na490_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na491_1), .IN6(1'b0), .IN7(na1893_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a490_2 ( .OUT(na490_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na490_1_i) ); +// C_MX2b/D/// x67y59 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a491_1 ( .OUT(na491_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na492_1), .IN6(1'b0), .IN7(na1862_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a491_2 ( .OUT(na491_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na491_1_i) ); +// C_MX2b/D/// x63y59 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a492_1 ( .OUT(na492_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(na493_1), .IN6(1'b0), .IN7(na1862_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a492_2 ( .OUT(na492_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na492_1_i) ); +// C_MX2b/D/// x61y61 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a493_1 ( .OUT(na493_1_i), .IN1(1'b1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1864_2), .IN8(na494_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a493_2 ( .OUT(na493_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na493_1_i) ); +// C_MX2b/D/// x66y60 80'h00_F600_00_0040_0A51_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a494_1 ( .OUT(na494_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1443_2), .IN5(~na495_1), .IN6(1'b0), .IN7(na1864_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a494_2 ( .OUT(na494_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na494_1_i) ); +// C_MX2b//// x63y67 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a495_1 ( .OUT(na495_1), .IN1(1'b1), .IN2(na1993_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na475_1), .IN6(~na1993_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x67y61 80'h00_FE00_00_0040_0A54_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a496_1 ( .OUT(na496_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na498_1), .IN5(na499_1), .IN6(1'b0), .IN7(~na497_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a496_2 ( .OUT(na496_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na496_1_i) ); +// C_MX2b//// x70y57 80'h00_0018_00_0040_0A55_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a497_1 ( .OUT(na497_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na54_2), .IN5(~na496_1), .IN6(1'b0), .IN7(~na1893_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x68y64 80'h00_0018_00_0000_0C88_88FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a498_1 ( .OUT(na498_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4423_2), .IN6(na1986_2), .IN7(na4493_2), .IN8(na1990_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x69y57 80'h00_FE00_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a499_1 ( .OUT(na499_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na498_1), .IN5(na501_1), .IN6(1'b0), .IN7(na500_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a499_2 ( .OUT(na499_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na499_1_i) ); +// C_MX2b//// x66y55 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a500_1 ( .OUT(na500_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na54_2), .IN5(na499_1), .IN6(1'b0), .IN7(na1862_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x69y59 80'h00_FE00_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a501_1 ( .OUT(na501_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na498_1), .IN5(na503_1), .IN6(1'b0), .IN7(na502_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a501_2 ( .OUT(na501_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na501_1_i) ); +// C_MX2b//// x64y55 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a502_1 ( .OUT(na502_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na54_2), .IN5(na501_1), .IN6(1'b0), .IN7(na1862_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x63y61 80'h00_FE00_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a503_1 ( .OUT(na503_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na498_1), .IN5(na505_1), .IN6(1'b0), .IN7(na504_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a503_2 ( .OUT(na503_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na503_1_i) ); +// C_MX2a//// x64y57 80'h00_0018_00_0040_0C05_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a504_1 ( .OUT(na504_1), .IN1(na503_1), .IN2(1'b0), .IN3(na1864_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na54_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x65y57 80'h00_FE00_00_0040_0A30_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a505_1 ( .OUT(na505_1_i), .IN1(na4084_2), .IN2(1'b1), .IN3(1'b1), .IN4(na498_1), .IN5(na505_1), .IN6(na4480_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a505_2 ( .OUT(na505_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na505_1_i) ); +// C_///ORAND/D x46y79 80'h00_FE00_80_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a506_4 ( .OUT(na506_2_i), .IN1(na4110_2), .IN2(~na138_1), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a506_5 ( .OUT(na506_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na506_2_i) ); +// C_MX4b/D/// x53y85 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a507_1 ( .OUT(na507_1_i), .IN1(na456_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na507_1), .IN6(na1321_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a507_2 ( .OUT(na507_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na507_1_i) ); +// C_///ORAND/D x37y70 80'h00_FE00_80_0000_0C08_FF5D +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a508_4 ( .OUT(na508_2_i), .IN1(~na3334_1), .IN2(na3335_1), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a508_5 ( .OUT(na508_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na508_2_i) ); +// C_MX4b/D/// x53y90 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a510_1 ( .OUT(na510_1_i), .IN1(~na456_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na507_1), .IN6(na510_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a510_2 ( .OUT(na510_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na510_1_i) ); +// C_MX4b////D x68y69 80'h00_FA18_00_0040_0AF1_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a511_1 ( .OUT(na511_1), .IN1(1'b1), .IN2(na512_1), .IN3(na4226_2), .IN4(1'b1), .IN5(~na4218_2), .IN6(na4425_2), .IN7(na1444_1), + .IN8(na517_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a511_5 ( .OUT(na511_2), .CLK(na1739_1), .EN(na1443_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na511_1) ); +// C_MX2b//// x67y72 80'h00_0018_00_0040_0AA0_00AF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a512_1 ( .OUT(na512_1), .IN1(1'b1), .IN2(1'b1), .IN3(na1991_1), .IN4(1'b1), .IN5(1'b0), .IN6(na3336_1), .IN7(1'b0), .IN8(na4217_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x61y69 80'h00_0018_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a513_1 ( .OUT(na513_1), .IN1(na514_2), .IN2(1'b1), .IN3(na38_2), .IN4(1'b1), .IN5(na475_1), .IN6(na470_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y69 80'h00_0060_00_0000_0C08_FF21 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a514_4 ( .OUT(na514_2), .IN1(~na4489_2), .IN2(~na1989_2), .IN3(na1991_1), .IN4(~na1990_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x53y45 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a516_1 ( .OUT(na516_1), .IN1(1'b1), .IN2(~na536_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na3718_1), .IN8(~na437_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x68y78 80'h00_0060_00_0000_0C08_FFAB +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a517_4 ( .OUT(na517_2), .IN1(na3338_2), .IN2(~na1986_1), .IN3(na38_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x58y88 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a518_1 ( .OUT(na518_1_i), .IN1(~na456_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na443_1), + .IN8(na518_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a518_2 ( .OUT(na518_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na518_1_i) ); +// C_ANDXOR////D x70y68 80'h00_FA18_00_0000_0666_F35D +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a519_1 ( .OUT(na519_1), .IN1(na535_1), .IN2(~na3341_1), .IN3(na520_2), .IN4(1'b1), .IN5(1'b1), .IN6(na1438_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a519_5 ( .OUT(na519_2), .CLK(na1739_1), .EN(na1436_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na519_1) ); +// C_///AND/ x70y75 80'h00_0060_00_0000_0C08_FF13 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a520_4 ( .OUT(na520_2), .IN1(1'b1), .IN2(~na3336_1), .IN3(~na521_1), .IN4(~na1990_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x70y73 80'h00_0018_00_0000_0888_9FAC +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a521_1 ( .OUT(na521_1), .IN1(1'b0), .IN2(~na1993_2), .IN3(~na4221_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na4487_2), + .IN8(na1990_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x71y77 80'h00_0060_00_0000_0C08_FFC4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a522_4 ( .OUT(na522_2), .IN1(~na360_2), .IN2(na103_1), .IN3(1'b1), .IN4(na4222_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x65y80 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a523_1 ( .OUT(na523_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na360_1), .IN6(1'b1), .IN7(~na38_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x65y69 80'h00_0018_00_0000_0C88_ABFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a524_1 ( .OUT(na524_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3342_2), .IN6(~na1993_2), .IN7(na4226_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x63y71 80'h00_F600_00_0040_0C0C_F200 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a525_1 ( .OUT(na525_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na4219_2), .IN4(na2011_1), .IN5(na95_1), .IN6(~na4102_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a525_2 ( .OUT(na525_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na525_1_i) ); +// C_ORAND//// x54y54 80'h00_0018_00_0000_0888_EFA3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a526_1 ( .OUT(na526_1), .IN1(1'b0), .IN2(~na1451_1), .IN3(na3343_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(na528_1), .IN8(na55_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y61 80'h00_0018_00_0000_0C88_2CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a528_1 ( .OUT(na528_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na22_1), .IN7(na93_1), .IN8(~na1443_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x68y57 80'h00_FE00_80_0000_0C08_FF2A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a529_4 ( .OUT(na529_2_i), .IN1(na109_1), .IN2(1'b1), .IN3(na107_1), .IN4(~na104_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a529_5 ( .OUT(na529_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na529_2_i) ); +// C_OR////D x46y43 80'h00_FE18_00_0000_0EEE_B000 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a530_1 ( .OUT(na530_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3346_1), .IN8(~na526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a530_5 ( .OUT(na530_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na530_1) ); +// C_ORAND*/D/// x36y75 80'h00_FE00_00_0000_0788_5FD3 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a531_1 ( .OUT(na531_1_i), .IN1(1'b0), .IN2(~na424_2), .IN3(~na531_1), .IN4(na1539_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a531_2 ( .OUT(na531_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na531_1_i) ); +// C_MX4b/D/// x40y88 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a532_1 ( .OUT(na532_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4225_2), + .IN8(na532_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a532_2 ( .OUT(na532_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na532_1_i) ); +// C_MX4b/D/// x29y81 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a533_1 ( .OUT(na533_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na533_1), .IN6(na1320_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a533_2 ( .OUT(na533_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na533_1_i) ); +// C_ANDXOR/D//AND/D x69y79 80'h00_FA00_80_0000_0C68_CEFA +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a534_1 ( .OUT(na534_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na4590_2), .IN6(~na1986_2), .IN7(1'b1), .IN8(~na4216_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a534_2 ( .OUT(na534_1), .CLK(na1739_1), .EN(na1435_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na534_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a534_4 ( .OUT(na534_2_i), .IN1(na534_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a534_5 ( .OUT(na534_2), .CLK(na1739_1), .EN(na1435_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na534_2_i) ); +// C_MX2b/D/// x65y63 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a535_1 ( .OUT(na535_1_i), .IN1(1'b1), .IN2(~na536_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3718_1), .IN8(na537_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a535_2 ( .OUT(na535_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na535_1_i) ); +// C_AND////D x51y46 80'h00_FE18_00_0000_0888_53FC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a536_1 ( .OUT(na536_1), .IN1(1'b1), .IN2(na88_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na88_1), .IN7(~na87_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a536_5 ( .OUT(na536_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na536_1) ); +// C_MX2b/D/// x52y48 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a537_1 ( .OUT(na537_1_i), .IN1(1'b1), .IN2(~na536_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3717_2), .IN8(na538_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a537_2 ( .OUT(na537_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na537_1_i) ); +// C_MX2b/D/// x48y40 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a538_1 ( .OUT(na538_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4227_2), .IN5(1'b0), .IN6(na539_1), .IN7(1'b0), .IN8(na3716_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a538_2 ( .OUT(na538_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na538_1_i) ); +// C_MX2b/D/// x45y38 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a539_1 ( .OUT(na539_1_i), .IN1(1'b1), .IN2(na536_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na540_1), .IN8(na3715_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a539_2 ( .OUT(na539_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na539_1_i) ); +// C_MX2b/D/// x46y39 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a540_1 ( .OUT(na540_1_i), .IN1(1'b1), .IN2(~na536_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3714_1), .IN8(na541_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a540_2 ( .OUT(na540_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na540_1_i) ); +// C_MX2b/D/// x46y40 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a541_1 ( .OUT(na541_1_i), .IN1(1'b1), .IN2(~na536_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3713_2), .IN8(na542_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a541_2 ( .OUT(na541_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na541_1_i) ); +// C_MX2b/D/// x42y40 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a542_1 ( .OUT(na542_1_i), .IN1(1'b1), .IN2(na536_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na695_1), .IN8(na3712_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a542_2 ( .OUT(na542_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na542_1_i) ); +// C_ORAND*/D//ORAND*/D x61y51 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a543_1 ( .OUT(na543_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na543_2), .IN6(~na91_1), .IN7(~na2118_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a543_2 ( .OUT(na543_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na543_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a543_4 ( .OUT(na543_2_i), .IN1(~na545_1), .IN2(~na91_1), .IN3(~na2118_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a543_5 ( .OUT(na543_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na543_2_i) ); +// C_ORAND*/D//ORAND*/D x63y53 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a545_1 ( .OUT(na545_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na545_2), .IN6(~na91_1), .IN7(~na2120_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a545_2 ( .OUT(na545_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na545_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a545_4 ( .OUT(na545_2_i), .IN1(~na4231_2), .IN2(~na91_1), .IN3(~na2120_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a545_5 ( .OUT(na545_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na545_2_i) ); +// C_ORAND*/D//ORAND*/D x68y53 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a547_1 ( .OUT(na547_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4232_2), .IN6(~na91_1), .IN7(~na4501_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a547_2 ( .OUT(na547_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na547_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a547_4 ( .OUT(na547_2_i), .IN1(~na4233_2), .IN2(~na91_1), .IN3(~na4500_2), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a547_5 ( .OUT(na547_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na547_2_i) ); +// C_ORAND*/D//ORAND*/D x66y51 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a549_1 ( .OUT(na549_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4234_2), .IN6(~na91_1), .IN7(~na2124_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a549_2 ( .OUT(na549_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na549_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a549_4 ( .OUT(na549_2_i), .IN1(~na4235_2), .IN2(~na91_1), .IN3(~na2124_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a549_5 ( .OUT(na549_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na549_2_i) ); +// C_ORAND*/D//ORAND*/D x66y53 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a551_1 ( .OUT(na551_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4236_2), .IN6(~na91_1), .IN7(~na4482_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a551_2 ( .OUT(na551_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na551_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a551_4 ( .OUT(na551_2_i), .IN1(~na4237_2), .IN2(~na91_1), .IN3(~na4481_2), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a551_5 ( .OUT(na551_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na551_2_i) ); +// C_ORAND*/D//ORAND*/D x67y50 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a553_1 ( .OUT(na553_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4238_2), .IN6(~na91_1), .IN7(~na1889_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a553_2 ( .OUT(na553_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na553_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a553_4 ( .OUT(na553_2_i), .IN1(~na555_1), .IN2(~na91_1), .IN3(~na1889_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a553_5 ( .OUT(na553_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na553_2_i) ); +// C_ORAND*/D//ORAND*/D x67y51 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a555_1 ( .OUT(na555_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na555_2), .IN6(~na91_1), .IN7(~na1891_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a555_2 ( .OUT(na555_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na555_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a555_4 ( .OUT(na555_2_i), .IN1(~na557_1), .IN2(~na91_1), .IN3(~na1891_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a555_5 ( .OUT(na555_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na555_2_i) ); +// C_ORAND*/D//ORAND*/D x69y51 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a557_1 ( .OUT(na557_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na557_2), .IN6(~na91_1), .IN7(~na1893_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a557_2 ( .OUT(na557_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na557_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a557_4 ( .OUT(na557_2_i), .IN1(~na4243_2), .IN2(~na91_1), .IN3(~na1893_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a557_5 ( .OUT(na557_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na557_2_i) ); +// C_ORAND*/D//ORAND*/D x71y52 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a559_1 ( .OUT(na559_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4244_2), .IN6(~na91_1), .IN7(~na1862_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a559_2 ( .OUT(na559_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na559_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a559_4 ( .OUT(na559_2_i), .IN1(~na4245_2), .IN2(~na91_1), .IN3(~na1862_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a559_5 ( .OUT(na559_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na559_2_i) ); +// C_ORAND*/D//ORAND*/D x70y47 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a561_1 ( .OUT(na561_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4246_2), .IN6(~na91_1), .IN7(~na1864_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a561_2 ( .OUT(na561_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na561_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a561_4 ( .OUT(na561_2_i), .IN1(~na563_1), .IN2(~na91_1), .IN3(~na1864_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a561_5 ( .OUT(na561_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na561_2_i) ); +// C_ORAND*/D//ORAND*/D x67y49 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a563_1 ( .OUT(na563_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na563_2), .IN6(~na91_1), .IN7(~na1866_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a563_2 ( .OUT(na563_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na563_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a563_4 ( .OUT(na563_2_i), .IN1(~na565_1), .IN2(~na91_1), .IN3(~na1866_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a563_5 ( .OUT(na563_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na563_2_i) ); +// C_ORAND*/D//ORAND*/D x67y43 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a565_1 ( .OUT(na565_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na565_2), .IN6(~na91_1), .IN7(~na1868_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a565_2 ( .OUT(na565_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na565_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a565_4 ( .OUT(na565_2_i), .IN1(~na567_1), .IN2(~na91_1), .IN3(~na1868_1), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a565_5 ( .OUT(na565_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na565_2_i) ); +// C_ORAND*/D//ORAND*/D x63y43 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a567_1 ( .OUT(na567_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na567_2), .IN6(~na91_1), .IN7(~na3718_1), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a567_2 ( .OUT(na567_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na567_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a567_4 ( .OUT(na567_2_i), .IN1(~na569_1), .IN2(~na91_1), .IN3(~na3717_2), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a567_5 ( .OUT(na567_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na567_2_i) ); +// C_ORAND*/D//ORAND*/D x59y43 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a569_1 ( .OUT(na569_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na569_2), .IN6(~na91_1), .IN7(~na4617_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a569_2 ( .OUT(na569_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na569_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a569_4 ( .OUT(na569_2_i), .IN1(~na571_1), .IN2(~na91_1), .IN3(~na4616_2), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a569_5 ( .OUT(na569_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na569_2_i) ); +// C_ORAND*/D//ORAND*/D x59y45 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a571_1 ( .OUT(na571_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na571_2), .IN6(~na91_1), .IN7(~na3714_1), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a571_2 ( .OUT(na571_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na571_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a571_4 ( .OUT(na571_2_i), .IN1(~na573_1), .IN2(~na91_1), .IN3(~na3713_2), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a571_5 ( .OUT(na571_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na571_2_i) ); +// C_ORAND*/D//ORAND*/D x61y45 80'h00_F600_80_0000_0387_777B +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a573_1 ( .OUT(na573_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na573_2), .IN6(~na91_1), .IN7(~na4615_2), + .IN8(~na92_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a573_2 ( .OUT(na573_1), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na573_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a573_4 ( .OUT(na573_2_i), .IN1(na516_1), .IN2(~na91_1), .IN3(~na4614_2), .IN4(~na92_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a573_5 ( .OUT(na573_2), .CLK(na1739_1), .EN(~na1406_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na573_2_i) ); +// C_ORAND//// x70y69 80'h00_0018_00_0000_0C88_E3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a575_1 ( .OUT(na575_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na1986_1), .IN7(na38_1), .IN8(na3415_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/D x48y55 80'h00_FE00_80_0000_0C0E_FFD0 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a576_4 ( .OUT(na576_2_i), .IN1(1'b0), .IN2(1'b0), .IN3(~na3343_1), .IN4(na577_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a576_5 ( .OUT(na576_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na576_2_i) ); +// C_AND//// x58y62 80'h00_0018_00_0000_0888_3C23 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a577_1 ( .OUT(na577_1), .IN1(1'b1), .IN2(~na1451_1), .IN3(na1991_1), .IN4(~na55_1), .IN5(1'b1), .IN6(na3196_1), .IN7(1'b1), + .IN8(~na55_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x52y57 80'h00_FE00_00_0040_0AA2_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a578_1 ( .OUT(na578_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na526_1), .IN5(1'b0), .IN6(~na428_1), .IN7(1'b0), .IN8(na1544_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a578_2 ( .OUT(na578_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na578_1_i) ); +// C_MX2b/D/// x52y54 80'h00_FE00_00_0040_0AA2_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a579_1 ( .OUT(na579_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na526_1), .IN5(1'b0), .IN6(~na4096_2), .IN7(1'b0), .IN8(na1544_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a579_2 ( .OUT(na579_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na579_1_i) ); +// C_ORAND/D/// x47y52 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a580_1 ( .OUT(na580_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4494_2), .IN6(~na3418_1), .IN7(~na3419_1), + .IN8(~na526_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a580_2 ( .OUT(na580_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na580_1_i) ); +// C_///ORAND/D x48y49 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a582_4 ( .OUT(na582_2_i), .IN1(~na4495_2), .IN2(~na3418_1), .IN3(~na3422_1), .IN4(~na526_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a582_5 ( .OUT(na582_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na582_2_i) ); +// C_ORAND/D/// x44y49 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a584_1 ( .OUT(na584_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2001_1), .IN6(~na3418_1), .IN7(~na3425_1), + .IN8(~na526_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a584_2 ( .OUT(na584_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na584_1_i) ); +// C_ORAND/D/// x46y51 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a586_1 ( .OUT(na586_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4496_2), .IN6(~na3418_1), .IN7(~na3428_1), + .IN8(~na526_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a586_2 ( .OUT(na586_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na586_1_i) ); +// C_ORAND/D/// x45y49 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a588_1 ( .OUT(na588_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2001_2), .IN6(~na3418_1), .IN7(~na3431_1), + .IN8(~na526_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a588_2 ( .OUT(na588_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na588_1_i) ); +// C_MX2b/D/// x57y48 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a590_1 ( .OUT(na590_1_i), .IN1(1'b1), .IN2(na4223_2), .IN3(1'b0), .IN4(1'b0), .IN5(na3432_1), .IN6(na3165_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a590_2 ( .OUT(na590_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na590_1_i) ); +// C_MX2b/D/// x58y45 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a591_1 ( .OUT(na591_1_i), .IN1(1'b1), .IN2(na4223_2), .IN3(1'b0), .IN4(1'b0), .IN5(na3433_2), .IN6(na3166_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a591_2 ( .OUT(na591_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na591_1_i) ); +// C_MX2b/D/// x57y49 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a592_1 ( .OUT(na592_1_i), .IN1(1'b1), .IN2(~na4223_2), .IN3(1'b0), .IN4(1'b0), .IN5(na3167_1), .IN6(na3434_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a592_2 ( .OUT(na592_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na592_1_i) ); +// C_MX2b/D/// x55y45 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a593_1 ( .OUT(na593_1_i), .IN1(1'b1), .IN2(na4223_2), .IN3(1'b0), .IN4(1'b0), .IN5(na3435_2), .IN6(na3168_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a593_2 ( .OUT(na593_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na593_1_i) ); +// C_MX2b/D/// x56y54 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a594_1 ( .OUT(na594_1_i), .IN1(1'b1), .IN2(~na4223_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3169_1), .IN8(na3436_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a594_2 ( .OUT(na594_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na594_1_i) ); +// C_MX2b/D/// x58y47 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a595_1 ( .OUT(na595_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na526_1), .IN5(1'b0), .IN6(na3437_1), .IN7(1'b0), .IN8(na3170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a595_2 ( .OUT(na595_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na595_1_i) ); +// C_MX2b/D/// x54y50 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a596_1 ( .OUT(na596_1_i), .IN1(1'b1), .IN2(na4223_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3438_1), .IN8(na3171_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a596_2 ( .OUT(na596_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na596_1_i) ); +// C_ORAND*////D x66y68 80'h00_FE18_00_0000_0788_D55D +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a597_1 ( .OUT(na597_1), .IN1(~na95_1), .IN2(na3440_1), .IN3(~na603_1), .IN4(1'b0), .IN5(~na95_2), .IN6(1'b0), .IN7(~na603_2), + .IN8(na614_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a597_5 ( .OUT(na597_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na597_1) ); +// C_AND///AND/ x70y71 80'h00_0078_00_0000_0C88_12C3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a598_1 ( .OUT(na598_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3441_2), .IN6(~na1986_1), .IN7(~na4485_2), + .IN8(~na1985_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a598_4 ( .OUT(na598_2), .IN1(1'b1), .IN2(~na1986_1), .IN3(1'b1), .IN4(na1985_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ANDXOR/ x67y70 80'h00_0060_00_0000_0C06_FFB3 +C_ANDXOR #(.CPE_CFG (9'b0_1000_0000)) + _a599_4 ( .OUT(na599_2), .IN1(1'b1), .IN2(na512_1), .IN3(~na3348_1), .IN4(na600_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x64y62 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a600_4 ( .OUT(na600_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1991_1), .IN4(na1984_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x64y73 80'h00_0078_00_0000_0C88_8C31 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a603_1 ( .OUT(na603_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3445_2), .IN7(na3451_2), .IN8(na56_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a603_4 ( .OUT(na603_2), .IN1(~na4489_2), .IN2(~na1993_2), .IN3(1'b1), .IN4(~na1990_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x66y78 80'h00_0018_00_0000_0C88_CBFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a605_1 ( .OUT(na605_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3447_2), .IN6(~na606_1), .IN7(1'b0), .IN8(na46_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x67y76 80'h00_0018_00_0040_0C68_3300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a606_1 ( .OUT(na606_1), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(na1990_1), .IN5(1'b1), .IN6(~na1989_2), .IN7(1'b1), .IN8(~na1990_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x67y77 80'h00_0018_00_0000_0C88_B5FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a607_1 ( .OUT(na607_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3448_1), .IN6(1'b0), .IN7(na3451_2), .IN8(~na2011_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x64y84 80'h00_0018_00_0000_0C66_6A00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a612_1 ( .OUT(na612_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4080_2), .IN6(1'b0), .IN7(na613_2), .IN8(na1440_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x62y81 80'h00_0060_00_0000_0C08_FFA4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a613_4 ( .OUT(na613_2), .IN1(~na360_2), .IN2(na523_1), .IN3(na4086_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x68y66 80'h00_0018_00_0040_0AAA_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a614_1 ( .OUT(na614_1), .IN1(1'b1), .IN2(1'b1), .IN3(~na575_1), .IN4(1'b1), .IN5(1'b0), .IN6(~na3452_2), .IN7(1'b0), .IN8(~na1581_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x68y77 80'h00_0018_00_0000_0C66_CC00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a618_1 ( .OUT(na618_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1986_2), .IN7(1'b0), .IN8(na79_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y67 80'h00_0018_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a619_1 ( .OUT(na619_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4484_2), .IN5(na3164_1), .IN6(1'b0), .IN7(na3163_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x55y48 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a620_1 ( .OUT(na620_1_i), .IN1(1'b1), .IN2(na4223_2), .IN3(1'b0), .IN4(1'b0), .IN5(na3458_2), .IN6(na3172_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a620_2 ( .OUT(na620_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na620_1_i) ); +// C_MX2b//// x56y44 80'h00_0018_00_0040_0AA2_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a621_1 ( .OUT(na621_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na526_1), .IN5(1'b0), .IN6(~na89_2), .IN7(1'b0), .IN8(na1544_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x57y43 80'h00_0018_00_0040_0AA2_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a622_1 ( .OUT(na622_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na526_1), .IN5(1'b0), .IN6(~na89_1), .IN7(1'b0), .IN8(na1544_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x53y55 80'h00_0060_00_0000_0C08_FF75 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a623_4 ( .OUT(na623_2), .IN1(~na624_1), .IN2(1'b0), .IN3(~na3419_1), .IN4(~na526_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x59y55 80'h00_0018_00_0040_0A30_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a624_1 ( .OUT(na624_1), .IN1(1'b1), .IN2(na536_1), .IN3(1'b1), .IN4(na526_1), .IN5(na496_1), .IN6(na1994_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x52y49 80'h00_0060_00_0000_0C08_FF73 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a625_4 ( .OUT(na625_2), .IN1(1'b0), .IN2(~na626_1), .IN3(~na3422_1), .IN4(~na526_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x55y56 80'h00_0018_00_0040_0A30_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a626_1 ( .OUT(na626_1), .IN1(1'b1), .IN2(na536_1), .IN3(1'b1), .IN4(na526_1), .IN5(na499_1), .IN6(na1995_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x50y49 80'h00_0018_00_0000_0C88_75FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a627_1 ( .OUT(na627_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na628_1), .IN6(1'b0), .IN7(~na3425_1), .IN8(~na526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x57y53 80'h00_0018_00_0040_0A30_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a628_1 ( .OUT(na628_1), .IN1(1'b1), .IN2(na536_1), .IN3(1'b1), .IN4(na526_1), .IN5(na501_1), .IN6(na1996_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x48y51 80'h00_0018_00_0000_0C88_75FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a629_1 ( .OUT(na629_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na630_1), .IN6(1'b0), .IN7(~na3428_1), .IN8(~na526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x57y51 80'h00_0018_00_0040_0A30_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a630_1 ( .OUT(na630_1), .IN1(1'b1), .IN2(na536_1), .IN3(1'b1), .IN4(na526_1), .IN5(na503_1), .IN6(na1997_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x47y50 80'h00_0060_00_0000_0C08_FF75 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a631_4 ( .OUT(na631_2), .IN1(~na632_1), .IN2(1'b0), .IN3(~na3431_1), .IN4(~na526_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x57y47 80'h00_0018_00_0040_0A30_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a632_1 ( .OUT(na632_1), .IN1(1'b1), .IN2(na536_1), .IN3(1'b1), .IN4(na526_1), .IN5(na505_1), .IN6(na1998_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x17y78 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a633_1 ( .OUT(na633_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na634_1), .IN6(na633_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a633_2 ( .OUT(na633_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na633_1_i) ); +// C_MX4b/D/// x19y75 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a634_1 ( .OUT(na634_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na634_1), .IN6(na635_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a634_2 ( .OUT(na634_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na634_1_i) ); +// C_MX4b/D/// x19y76 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a635_1 ( .OUT(na635_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1319_1), .IN6(na635_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a635_2 ( .OUT(na635_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na635_1_i) ); +// C_ORAND//// x54y43 80'h00_0018_00_0000_0888_F5EA +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a636_1 ( .OUT(na636_1), .IN1(na3459_1), .IN2(1'b0), .IN3(na276_1), .IN4(na3462_1), .IN5(~na1473_2), .IN6(1'b0), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x51y55 80'h00_FE00_80_0000_0C08_FF2A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a638_4 ( .OUT(na638_2_i), .IN1(na1387_1), .IN2(1'b1), .IN3(na283_1), .IN4(~na282_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a638_5 ( .OUT(na638_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na638_2_i) ); +// C_OR////D x39y39 80'h00_FE18_00_0000_0EEE_50A0 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a639_1 ( .OUT(na639_1), .IN1(1'b0), .IN2(1'b0), .IN3(na3463_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na636_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a639_5 ( .OUT(na639_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na639_1) ); +// C_MX4b/D/// x19y78 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a640_1 ( .OUT(na640_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na641_1), .IN6(na640_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a640_2 ( .OUT(na640_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na640_1_i) ); +// C_MX4b/D/// x21y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a641_1 ( .OUT(na641_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na641_1), .IN6(na642_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a641_2 ( .OUT(na641_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na641_1_i) ); +// C_MX4b/D/// x23y78 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a642_1 ( .OUT(na642_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na674_1), .IN6(na642_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a642_2 ( .OUT(na642_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na642_1_i) ); +// C_///AND/ x19y71 80'h00_0060_00_0000_0C08_FFA3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a643_4 ( .OUT(na643_2), .IN1(1'b1), .IN2(~na405_2), .IN3(na317_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x16y69 80'h00_0018_00_0000_0C88_53FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a644_1 ( .OUT(na644_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na2_2), .IN7(~na318_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D/// x36y70 80'h00_FE00_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a645_1 ( .OUT(na645_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3465_1), .IN6(~na3464_1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a645_2 ( .OUT(na645_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na645_1_i) ); +// C_MX4b/D/// x19y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a647_1 ( .OUT(na647_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na647_1), .IN6(na685_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a647_2 ( .OUT(na647_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na647_1_i) ); +// C_MX2b/D/// x56y56 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a648_1 ( .OUT(na648_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na2358_1), .IN7(1'b0), .IN8(na649_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a648_2 ( .OUT(na648_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na648_1_i) ); +// C_MX2b/D/// x56y52 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a649_1 ( .OUT(na649_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1741_2), .IN7(1'b0), .IN8(na650_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a649_2 ( .OUT(na649_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na649_1_i) ); +// C_MX2b/D/// x56y50 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a650_1 ( .OUT(na650_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1741_1), .IN7(1'b0), .IN8(na651_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a650_2 ( .OUT(na650_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na650_1_i) ); +// C_MX2b/D/// x60y48 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a651_1 ( .OUT(na651_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1743_2), .IN7(1'b0), .IN8(na652_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a651_2 ( .OUT(na651_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na651_1_i) ); +// C_MX2b/D/// x56y46 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a652_1 ( .OUT(na652_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1743_1), .IN7(1'b0), .IN8(na658_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a652_2 ( .OUT(na652_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na652_1_i) ); +// C_MX2b/D/// x56y55 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a653_1 ( .OUT(na653_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1882_2), .IN7(1'b0), .IN8(na654_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a653_2 ( .OUT(na653_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na653_1_i) ); +// C_MX2b/D/// x54y52 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a654_1 ( .OUT(na654_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1882_1), .IN7(1'b0), .IN8(na655_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a654_2 ( .OUT(na654_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na654_1_i) ); +// C_MX2b/D/// x58y48 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a655_1 ( .OUT(na655_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1884_2), .IN7(1'b0), .IN8(na656_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a655_2 ( .OUT(na655_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na655_1_i) ); +// C_MX2b/D/// x58y46 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a656_1 ( .OUT(na656_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1884_1), .IN7(1'b0), .IN8(na657_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a656_2 ( .OUT(na656_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na656_1_i) ); +// C_MX2b/D/// x50y44 80'h00_F600_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a657_1 ( .OUT(na657_1_i), .IN1(na1465_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3726_1), .IN8(na658_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a657_2 ( .OUT(na657_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na657_1_i) ); +// C_MX2b/D/// x50y42 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a658_1 ( .OUT(na658_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4432_2), .IN5(na659_1), .IN6(1'b0), .IN7(na3725_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a658_2 ( .OUT(na658_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na658_1_i) ); +// C_MX2b/D/// x47y41 80'h00_F600_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a659_1 ( .OUT(na659_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4432_2), .IN5(1'b0), .IN6(na660_1), .IN7(1'b0), .IN8(na3724_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a659_2 ( .OUT(na659_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na659_1_i) ); +// C_MX2a/D/// x49y40 80'h00_F600_00_0040_0C0C_F500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a660_1 ( .OUT(na660_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na661_1), .IN4(na3723_2), .IN5(~na1465_2), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a660_2 ( .OUT(na660_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na660_1_i) ); +// C_MX2b/D/// x48y41 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a661_1 ( .OUT(na661_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4432_2), .IN5(na662_1), .IN6(1'b0), .IN7(na3722_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a661_2 ( .OUT(na661_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na661_1_i) ); +// C_MX2a/D/// x47y43 80'h00_F600_00_0040_0C0C_FA00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a662_1 ( .OUT(na662_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na3721_2), .IN4(na1585_1), .IN5(na1465_2), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a662_2 ( .OUT(na662_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na662_1_i) ); +// C_MX2b/D/// x55y52 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a663_1 ( .OUT(na663_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na2358_1), .IN7(1'b0), .IN8(na2230_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a663_2 ( .OUT(na663_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na663_1_i) ); +// C_MX2a/D/// x59y56 80'h00_F600_00_0040_0C03_0500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a664_1 ( .OUT(na664_1_i), .IN1(na665_1), .IN2(na1882_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na1465_2), .IN6(1'b1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a664_2 ( .OUT(na664_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na664_1_i) ); +// C_MX2b/D/// x59y53 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a665_1 ( .OUT(na665_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1745_2), .IN7(1'b0), .IN8(na666_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a665_2 ( .OUT(na665_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na665_1_i) ); +// C_MX2b/D/// x62y52 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a666_1 ( .OUT(na666_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1745_1), .IN7(1'b0), .IN8(na667_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a666_2 ( .OUT(na666_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na666_1_i) ); +// C_MX2b/D/// x58y50 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a667_1 ( .OUT(na667_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1747_2), .IN7(1'b0), .IN8(na668_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a667_2 ( .OUT(na667_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na667_1_i) ); +// C_MX2b/D/// x58y54 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a668_1 ( .OUT(na668_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1747_1), .IN7(1'b0), .IN8(na669_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a668_2 ( .OUT(na668_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na668_1_i) ); +// C_MX2a/D/// x56y48 80'h00_F600_00_0040_0C03_0500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a669_1 ( .OUT(na669_1_i), .IN1(na670_1), .IN2(na1878_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na1465_2), .IN6(1'b1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a669_2 ( .OUT(na669_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na669_1_i) ); +// C_MX2b/D/// x61y49 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a670_1 ( .OUT(na670_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1878_1), .IN7(1'b0), .IN8(na671_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a670_2 ( .OUT(na670_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na670_1_i) ); +// C_MX2a/D/// x54y48 80'h00_F600_00_0040_0C03_0500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a671_1 ( .OUT(na671_1_i), .IN1(na672_1), .IN2(na1880_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na1465_2), .IN6(1'b1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a671_2 ( .OUT(na671_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na671_1_i) ); +// C_MX2b/D/// x59y51 80'h00_F600_00_0040_0AA8_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a672_1 ( .OUT(na672_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4432_2), .IN5(1'b0), .IN6(na1880_1), .IN7(1'b0), .IN8(~na673_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a672_2 ( .OUT(na672_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na672_1_i) ); +// C_MX2b//// x54y58 80'h00_0018_00_0040_0ACC_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a673_1 ( .OUT(na673_1), .IN1(na2229_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na653_1), .IN8(~na2230_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x25y77 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a674_1 ( .OUT(na674_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na674_1), .IN6(na4256_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a674_2 ( .OUT(na674_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na674_1_i) ); +// C_MX2b/D/// x65y41 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a675_1 ( .OUT(na675_1_i), .IN1(1'b1), .IN2(~na4258_2), .IN3(1'b0), .IN4(1'b0), .IN5(na678_1), .IN6(na676_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a675_2 ( .OUT(na675_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na675_1_i) ); +// C_MX2a//// x63y42 80'h00_0018_00_0040_0C03_0A00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a676_1 ( .OUT(na676_1), .IN1(na675_1), .IN2(na1747_1), .IN3(1'b0), .IN4(1'b0), .IN5(na275_2), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x62y48 80'h00_0060_00_0000_0C08_FF88 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a677_4 ( .OUT(na677_2), .IN1(na2229_1), .IN2(na2228_2), .IN3(na2223_2), .IN4(na4432_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x67y41 80'h00_FE00_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a678_1 ( .OUT(na678_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na677_2), .IN5(na680_1), .IN6(1'b0), .IN7(na679_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a678_2 ( .OUT(na678_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na678_1_i) ); +// C_MX2b//// x58y43 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a679_1 ( .OUT(na679_1), .IN1(na275_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na678_1), .IN6(na1878_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x65y43 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a680_1 ( .OUT(na680_1_i), .IN1(1'b1), .IN2(~na4258_2), .IN3(1'b0), .IN4(1'b0), .IN5(na682_1), .IN6(na681_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a680_2 ( .OUT(na680_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na680_1_i) ); +// C_MX2b//// x59y46 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a681_1 ( .OUT(na681_1), .IN1(na275_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na680_1), .IN6(na1878_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x65y45 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a682_1 ( .OUT(na682_1_i), .IN1(1'b1), .IN2(~na4258_2), .IN3(1'b0), .IN4(1'b0), .IN5(na684_1), .IN6(na683_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a682_2 ( .OUT(na682_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na682_1_i) ); +// C_MX2a//// x57y46 80'h00_0018_00_0040_0C03_0A00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a683_1 ( .OUT(na683_1), .IN1(na682_1), .IN2(na1880_2), .IN3(1'b0), .IN4(1'b0), .IN5(na275_2), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x59y47 80'h00_FE00_00_0040_0A30_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a684_1 ( .OUT(na684_1_i), .IN1(na275_2), .IN2(1'b1), .IN3(1'b1), .IN4(na677_2), .IN5(na684_1), .IN6(na1880_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a684_2 ( .OUT(na684_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na684_1_i) ); +// C_MX4b/D/// x21y80 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a685_1 ( .OUT(na685_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na686_1), .IN6(na685_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a685_2 ( .OUT(na685_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na685_1_i) ); +// C_MX4b/D/// x23y81 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a686_1 ( .OUT(na686_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na686_1), .IN6(na1318_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a686_2 ( .OUT(na686_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na686_1_i) ); +// C_///AND/ x23y70 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a687_4 ( .OUT(na687_2), .IN1(1'b1), .IN2(na405_2), .IN3(1'b1), .IN4(na688_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x20y72 80'h00_0018_00_0000_0C88_3CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a688_1 ( .OUT(na688_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4072_2), .IN7(1'b1), .IN8(~na26_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x16y74 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a689_1 ( .OUT(na689_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2_2), .IN7(na319_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D/// x29y70 80'h00_FE00_00_0000_0C88_5DFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a690_1 ( .OUT(na690_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3466_2), .IN6(na3467_2), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a690_2 ( .OUT(na690_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na690_1_i) ); +// C_MX4b/D/// x21y87 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a692_1 ( .OUT(na692_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na692_1), .IN6(na4259_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a692_2 ( .OUT(na692_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na692_1_i) ); +// C_MX4b/D/// x23y87 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a693_1 ( .OUT(na693_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na693_1), .IN6(na694_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a693_2 ( .OUT(na693_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na693_1_i) ); +// C_MX4b/D/// x19y88 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a694_1 ( .OUT(na694_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na696_1), .IN6(na694_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a694_2 ( .OUT(na694_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na694_1_i) ); +// C_AND/D/// x44y39 80'h00_FE00_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a695_1 ( .OUT(na695_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na536_1), .IN7(1'b1), .IN8(na3711_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a695_2 ( .OUT(na695_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na695_1_i) ); +// C_MX4b/D/// x19y87 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a696_1 ( .OUT(na696_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na697_1), .IN6(na4260_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a696_2 ( .OUT(na696_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na696_1_i) ); +// C_MX4b/D/// x21y85 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a697_1 ( .OUT(na697_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na697_1), .IN6(na710_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a697_2 ( .OUT(na697_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na697_1_i) ); +// C_MX2a/D/// x25y37 80'h00_FE00_00_0040_0C05_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a698_1 ( .OUT(na698_1_i), .IN1(na699_1), .IN2(1'b0), .IN3(na3531_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na203_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a698_2 ( .OUT(na698_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na698_1_i) ); +// C_MX2a/D/// x25y35 80'h00_FE00_00_0040_0C0A_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a699_1 ( .OUT(na699_1_i), .IN1(1'b0), .IN2(na700_1), .IN3(1'b0), .IN4(na3530_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na203_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a699_2 ( .OUT(na699_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na699_1_i) ); +// C_MX2a/D/// x25y40 80'h00_FE00_00_0040_0C0A_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a700_1 ( .OUT(na700_1_i), .IN1(1'b0), .IN2(na701_1), .IN3(1'b0), .IN4(na3529_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na203_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a700_2 ( .OUT(na700_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na700_1_i) ); +// C_MX2b/D/// x33y40 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a701_1 ( .OUT(na701_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na203_2), .IN5(na702_1), .IN6(1'b0), .IN7(na3528_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a701_2 ( .OUT(na701_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na701_1_i) ); +// C_MX2a/D/// x35y39 80'h00_FE00_00_0040_0C05_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a702_1 ( .OUT(na702_1_i), .IN1(na703_1), .IN2(1'b0), .IN3(na3527_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na203_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a702_2 ( .OUT(na702_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na702_1_i) ); +// C_MX2b/D/// x35y37 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a703_1 ( .OUT(na703_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na203_2), .IN5(1'b0), .IN6(na205_2), .IN7(1'b0), .IN8(na3526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a703_2 ( .OUT(na703_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na703_1_i) ); +// C_ANDXOR////D x69y53 80'h00_FA18_00_0000_0666_3FB3 +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a704_1 ( .OUT(na704_1), .IN1(1'b1), .IN2(na705_1), .IN3(~na3470_1), .IN4(na720_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na1460_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a704_5 ( .OUT(na704_2), .CLK(na1739_1), .EN(na1459_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na704_1) ); +// C_AND//// x63y62 80'h00_0018_00_0000_0C88_31FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a705_1 ( .OUT(na705_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na706_1), .IN6(~na3276_1), .IN7(1'b1), .IN8(~na4508_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x63y63 80'h00_0018_00_0000_0888_F9AA +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a706_1 ( .OUT(na706_1), .IN1(~na2229_1), .IN2(1'b0), .IN3(~na4263_2), .IN4(1'b0), .IN5(na2229_2), .IN6(na4505_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x59y61 80'h00_0018_00_0000_0C88_A2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a707_1 ( .OUT(na707_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na329_1), .IN6(~na295_1), .IN7(na262_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x65y55 80'h00_0060_00_0000_0C08_FFCD +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a708_4 ( .OUT(na708_2), .IN1(~na2229_1), .IN2(na3471_2), .IN3(1'b0), .IN4(na720_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x55y59 80'h00_F600_00_0040_0C03_0400 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a709_1 ( .OUT(na709_1_i), .IN1(na704_1), .IN2(na2248_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na333_1), .IN6(na341_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a709_2 ( .OUT(na709_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na709_1_i) ); +// C_MX4b/D/// x25y86 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a710_1 ( .OUT(na710_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na711_1), .IN6(na710_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a710_2 ( .OUT(na710_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na710_1_i) ); +// C_MX4b/D/// x23y83 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a711_1 ( .OUT(na711_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na711_1), .IN6(na4264_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a711_2 ( .OUT(na711_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na711_1_i) ); +// C_MX4b/D/// x25y83 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a712_1 ( .OUT(na712_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na712_1), .IN6(na1317_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a712_2 ( .OUT(na712_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na712_1_i) ); +// C_ANDXOR/D//AND/D x52y59 80'h00_FA00_80_0000_0C68_ECAF +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a713_1 ( .OUT(na713_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na4175_2), .IN7(~na2223_2), .IN8(~na3472_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a713_2 ( .OUT(na713_1), .CLK(na1739_1), .EN(na1457_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na713_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a713_4 ( .OUT(na713_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na713_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a713_5 ( .OUT(na713_2), .CLK(na1739_1), .EN(na1457_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na713_2_i) ); +// C_MX2b/D/// x48y38 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a714_1 ( .OUT(na714_1_i), .IN1(1'b1), .IN2(~na273_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3725_2), .IN8(na715_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a714_2 ( .OUT(na714_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na714_1_i) ); +// C_MX2a/D/// x50y36 80'h00_FE00_00_0040_0C0C_FC00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a715_1 ( .OUT(na715_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na716_1), .IN4(na3724_1), .IN5(1'b1), .IN6(na273_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a715_2 ( .OUT(na715_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na715_1_i) ); +// C_MX2b/D/// x46y35 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a716_1 ( .OUT(na716_1_i), .IN1(1'b1), .IN2(na273_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na717_1), .IN8(na3723_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a716_2 ( .OUT(na716_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na716_1_i) ); +// C_MX2a/D/// x46y37 80'h00_FE00_00_0040_0C0C_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a717_1 ( .OUT(na717_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na3722_1), .IN4(na718_1), .IN5(1'b1), .IN6(~na273_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a717_2 ( .OUT(na717_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na717_1_i) ); +// C_MX2b/D/// x46y38 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a718_1 ( .OUT(na718_1_i), .IN1(1'b1), .IN2(~na273_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3721_2), .IN8(na719_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a718_2 ( .OUT(na718_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na718_1_i) ); +// C_MX2a/D/// x44y38 80'h00_FE00_00_0040_0C0C_FC00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a719_1 ( .OUT(na719_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na269_2), .IN4(na3720_1), .IN5(1'b1), .IN6(na273_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a719_2 ( .OUT(na719_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na719_1_i) ); +// C_MX2b/D/// x60y50 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a720_1 ( .OUT(na720_1_i), .IN1(1'b1), .IN2(~na273_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3726_1), .IN8(na721_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a720_2 ( .OUT(na720_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na720_1_i) ); +// C_MX2b/D/// x50y38 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a721_1 ( .OUT(na721_1_i), .IN1(1'b1), .IN2(~na273_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3725_2), .IN8(na722_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a721_2 ( .OUT(na721_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na721_1_i) ); +// C_MX2a/D/// x52y36 80'h00_FE00_00_0040_0C0C_FC00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a722_1 ( .OUT(na722_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na723_1), .IN4(na3724_1), .IN5(1'b1), .IN6(na273_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a722_2 ( .OUT(na722_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na722_1_i) ); +// C_MX2b/D/// x48y37 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a723_1 ( .OUT(na723_1_i), .IN1(1'b1), .IN2(na273_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na724_1), .IN8(na3723_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a723_2 ( .OUT(na723_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na723_1_i) ); +// C_MX2a/D/// x42y39 80'h00_FE00_00_0040_0C0C_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a724_1 ( .OUT(na724_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na3722_1), .IN4(na725_1), .IN5(1'b1), .IN6(~na273_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a724_2 ( .OUT(na724_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na724_1_i) ); +// C_MX2b/D/// x42y38 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a725_1 ( .OUT(na725_1_i), .IN1(1'b1), .IN2(~na273_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3721_2), .IN8(na726_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a725_2 ( .OUT(na725_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na725_1_i) ); +// C_MX2b/D/// x44y36 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a726_1 ( .OUT(na726_1_i), .IN1(1'b1), .IN2(na273_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na272_1), .IN8(na3720_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a726_2 ( .OUT(na726_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na726_1_i) ); +// C_MX4b/D/// x19y85 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a727_1 ( .OUT(na727_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na760_1), .IN6(na4266_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a727_2 ( .OUT(na727_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na727_1_i) ); +// C_ORAND*/D//ORAND*/D x64y42 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a728_1 ( .OUT(na728_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na2352_2), .IN7(~na4268_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a728_2 ( .OUT(na728_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na728_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a728_4 ( .OUT(na728_2_i), .IN1(~na337_2), .IN2(~na2352_1), .IN3(~na730_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a728_5 ( .OUT(na728_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na728_2_i) ); +// C_ORAND*/D//ORAND*/D x62y41 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a730_1 ( .OUT(na730_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na2354_2), .IN7(~na730_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a730_2 ( .OUT(na730_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na730_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a730_4 ( .OUT(na730_2_i), .IN1(~na337_2), .IN2(~na2354_1), .IN3(~na732_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a730_5 ( .OUT(na730_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na730_2_i) ); +// C_ORAND*/D//ORAND*/D x62y43 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a732_1 ( .OUT(na732_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na2356_2), .IN7(~na732_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a732_2 ( .OUT(na732_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na732_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a732_4 ( .OUT(na732_2_i), .IN1(~na337_2), .IN2(~na2356_1), .IN3(~na4269_2), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a732_5 ( .OUT(na732_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na732_2_i) ); +// C_ORAND*/D//ORAND*/D x61y43 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a734_1 ( .OUT(na734_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na2358_2), .IN7(~na4270_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a734_2 ( .OUT(na734_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na734_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a734_4 ( .OUT(na734_2_i), .IN1(~na337_2), .IN2(~na2358_1), .IN3(~na736_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a734_5 ( .OUT(na734_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na734_2_i) ); +// C_ORAND*/D//ORAND*/D x66y41 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a736_1 ( .OUT(na736_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1741_2), .IN7(~na736_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a736_2 ( .OUT(na736_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na736_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a736_4 ( .OUT(na736_2_i), .IN1(~na337_2), .IN2(~na1741_1), .IN3(~na738_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a736_5 ( .OUT(na736_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na736_2_i) ); +// C_ORAND*/D//ORAND*/D x68y39 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a738_1 ( .OUT(na738_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1743_2), .IN7(~na738_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a738_2 ( .OUT(na738_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na738_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a738_4 ( .OUT(na738_2_i), .IN1(~na337_2), .IN2(~na1743_1), .IN3(~na740_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a738_5 ( .OUT(na738_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na738_2_i) ); +// C_ORAND*/D//ORAND*/D x72y39 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a740_1 ( .OUT(na740_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1745_2), .IN7(~na740_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a740_2 ( .OUT(na740_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na740_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a740_4 ( .OUT(na740_2_i), .IN1(~na337_2), .IN2(~na1745_1), .IN3(~na742_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a740_5 ( .OUT(na740_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na740_2_i) ); +// C_ORAND*/D//ORAND*/D x70y41 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a742_1 ( .OUT(na742_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1747_2), .IN7(~na742_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a742_2 ( .OUT(na742_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na742_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a742_4 ( .OUT(na742_2_i), .IN1(~na337_2), .IN2(~na1747_1), .IN3(~na744_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a742_5 ( .OUT(na742_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na742_2_i) ); +// C_ORAND*/D//ORAND*/D x70y37 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a744_1 ( .OUT(na744_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1878_2), .IN7(~na744_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a744_2 ( .OUT(na744_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na744_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a744_4 ( .OUT(na744_2_i), .IN1(~na337_2), .IN2(~na1878_1), .IN3(~na746_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a744_5 ( .OUT(na744_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na744_2_i) ); +// C_ORAND*/D//ORAND*/D x68y37 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a746_1 ( .OUT(na746_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1880_2), .IN7(~na746_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a746_2 ( .OUT(na746_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na746_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a746_4 ( .OUT(na746_2_i), .IN1(~na337_2), .IN2(~na1880_1), .IN3(~na748_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a746_5 ( .OUT(na746_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na746_2_i) ); +// C_ORAND*/D//ORAND*/D x70y39 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a748_1 ( .OUT(na748_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1882_2), .IN7(~na748_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a748_2 ( .OUT(na748_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na748_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a748_4 ( .OUT(na748_2_i), .IN1(~na337_2), .IN2(~na1882_1), .IN3(~na750_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a748_5 ( .OUT(na748_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na748_2_i) ); +// C_ORAND*/D//ORAND*/D x66y39 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a750_1 ( .OUT(na750_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na1884_2), .IN7(~na750_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a750_2 ( .OUT(na750_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na750_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a750_4 ( .OUT(na750_2_i), .IN1(~na337_2), .IN2(~na1884_1), .IN3(~na4283_2), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a750_5 ( .OUT(na750_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na750_2_i) ); +// C_ORAND*/D//ORAND*/D x65y35 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a752_1 ( .OUT(na752_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na4625_2), .IN7(~na4284_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a752_2 ( .OUT(na752_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na752_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a752_4 ( .OUT(na752_2_i), .IN1(~na337_2), .IN2(~na4624_2), .IN3(~na4285_2), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a752_5 ( .OUT(na752_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na752_2_i) ); +// C_ORAND*/D//ORAND*/D x59y38 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a754_1 ( .OUT(na754_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na4623_2), .IN7(~na4286_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a754_2 ( .OUT(na754_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na754_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a754_4 ( .OUT(na754_2_i), .IN1(~na337_2), .IN2(~na4622_2), .IN3(~na4287_2), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a754_5 ( .OUT(na754_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na754_2_i) ); +// C_ORAND*/D//ORAND*/D x61y38 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a756_1 ( .OUT(na756_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na4621_2), .IN7(~na4288_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a756_2 ( .OUT(na756_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na756_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a756_4 ( .OUT(na756_2_i), .IN1(~na337_2), .IN2(~na4620_2), .IN3(~na758_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a756_5 ( .OUT(na756_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na756_2_i) ); +// C_ORAND*/D//ORAND*/D x58y35 80'h00_F600_80_0000_0387_77B7 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a758_1 ( .OUT(na758_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na337_2), .IN6(~na4619_2), .IN7(~na758_2), + .IN8(~na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a758_2 ( .OUT(na758_1), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na758_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a758_4 ( .OUT(na758_2_i), .IN1(~na337_2), .IN2(~na4618_2), .IN3(na354_1), .IN4(~na336_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a758_5 ( .OUT(na758_2), .CLK(na1739_1), .EN(~na1407_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na758_2_i) ); +// C_MX4b/D/// x23y85 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a760_1 ( .OUT(na760_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na760_1), .IN6(na4291_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a760_2 ( .OUT(na760_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na760_1_i) ); +// C_///ORAND/ x67y53 80'h00_0060_00_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a761_4 ( .OUT(na761_2), .IN1(na4161_2), .IN2(na3539_1), .IN3(~na2223_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x21y81 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a762_1 ( .OUT(na762_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na762_1), .IN6(na814_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a762_2 ( .OUT(na762_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na762_1_i) ); +// C_///OR/D x43y47 80'h00_FE00_80_0000_0C0E_FFA5 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a763_4 ( .OUT(na763_2_i), .IN1(~na3459_1), .IN2(1'b0), .IN3(na764_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a763_5 ( .OUT(na763_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na763_2_i) ); +// C_AND//// x58y51 80'h00_0018_00_0000_0888_4CF4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a764_1 ( .OUT(na764_1), .IN1(~na1473_2), .IN2(na2228_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3461_1), .IN7(~na276_1), + .IN8(na3162_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x50y46 80'h00_FE00_00_0040_0AA8_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a765_1 ( .OUT(na765_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na636_1), .IN4(1'b1), .IN5(1'b0), .IN6(na1542_2), .IN7(1'b0), .IN8(~na4418_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a765_2 ( .OUT(na765_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na765_1_i) ); +// C_MX2b/D/// x50y45 80'h00_FE00_00_0040_0AA8_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a766_1 ( .OUT(na766_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na636_1), .IN4(1'b1), .IN5(1'b0), .IN6(na1542_1), .IN7(1'b0), .IN8(~na284_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a766_2 ( .OUT(na766_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na766_1_i) ); +// C_ORAND/D/// x48y48 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a767_1 ( .OUT(na767_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3542_1), .IN6(~na4513_2), .IN7(~na636_1), + .IN8(~na3543_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a767_2 ( .OUT(na767_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na767_1_i) ); +// C_ORAND/D/// x44y47 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a769_1 ( .OUT(na769_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3542_1), .IN6(~na4514_2), .IN7(~na636_1), + .IN8(~na3546_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a769_2 ( .OUT(na769_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na769_1_i) ); +// C_///ORAND/D x46y48 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a771_4 ( .OUT(na771_2_i), .IN1(~na3542_1), .IN2(~na2238_1), .IN3(~na636_1), .IN4(~na3549_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a771_5 ( .OUT(na771_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na771_2_i) ); +// C_///ORAND/D x48y48 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a773_4 ( .OUT(na773_2_i), .IN1(~na3542_1), .IN2(~na4515_2), .IN3(~na636_1), .IN4(~na3552_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a773_5 ( .OUT(na773_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na773_2_i) ); +// C_///ORAND/D x44y47 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a775_4 ( .OUT(na775_2_i), .IN1(~na3542_1), .IN2(~na2238_2), .IN3(~na636_1), .IN4(~na3555_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a775_5 ( .OUT(na775_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na775_2_i) ); +// C_MX2b/D/// x56y38 80'h00_FE00_00_0040_0A50_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a777_1 ( .OUT(na777_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na636_1), .IN4(1'b1), .IN5(na3556_2), .IN6(1'b0), .IN7(na3177_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a777_2 ( .OUT(na777_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na777_1_i) ); +// C_MX2b/D/// x56y35 80'h00_FE00_00_0040_0AA0_00AF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a778_1 ( .OUT(na778_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(na636_1), .IN4(1'b1), .IN5(1'b0), .IN6(na3557_2), .IN7(1'b0), .IN8(na3178_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a778_2 ( .OUT(na778_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na778_1_i) ); +// C_MX2b/D/// x52y37 80'h00_FE00_00_0040_0A50_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a779_1 ( .OUT(na779_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na636_1), .IN4(1'b1), .IN5(na3558_2), .IN6(1'b0), .IN7(na3179_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a779_2 ( .OUT(na779_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na779_1_i) ); +// C_MX2b/D/// x55y37 80'h00_FE00_00_0040_0AA0_00AF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a780_1 ( .OUT(na780_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(na636_1), .IN4(1'b1), .IN5(1'b0), .IN6(na3559_1), .IN7(1'b0), .IN8(na3180_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a780_2 ( .OUT(na780_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na780_1_i) ); +// C_MX2b/D/// x56y42 80'h00_FE00_00_0040_0A50_0050 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a781_1 ( .OUT(na781_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(~na636_1), .IN4(1'b1), .IN5(na3181_1), .IN6(1'b0), .IN7(na3560_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a781_2 ( .OUT(na781_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na781_1_i) ); +// C_MX2b/D/// x56y39 80'h00_FE00_00_0040_0AA0_00AF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a782_1 ( .OUT(na782_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(na636_1), .IN4(1'b1), .IN5(1'b0), .IN6(na3561_1), .IN7(1'b0), .IN8(na3182_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a782_2 ( .OUT(na782_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na782_1_i) ); +// C_MX2b/D/// x52y39 80'h00_FE00_00_0040_0A50_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a783_1 ( .OUT(na783_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na636_1), .IN4(1'b1), .IN5(na3562_2), .IN6(1'b0), .IN7(na3183_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a783_2 ( .OUT(na783_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na783_1_i) ); +// C_ORAND*////D x62y55 80'h00_FE18_00_0000_0788_D35B +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a784_1 ( .OUT(na784_1), .IN1(na3564_1), .IN2(~na341_1), .IN3(~na790_1), .IN4(1'b0), .IN5(1'b0), .IN6(~na341_2), .IN7(~na790_2), + .IN8(na792_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a784_5 ( .OUT(na784_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na784_1) ); +// C_AND///AND/ x67y55 80'h00_0078_00_0000_0C88_145A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a785_1 ( .OUT(na785_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2222_1), .IN6(na3565_2), .IN7(~na2223_1), + .IN8(~na4504_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a785_4 ( .OUT(na785_2), .IN1(na2222_1), .IN2(1'b1), .IN3(~na2223_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ANDXOR//// x61y54 80'h00_0018_00_0000_0C66_5D00 +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a786_1 ( .OUT(na786_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na787_1), .IN6(~na4604_2), .IN7(na353_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x59y49 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a787_1 ( .OUT(na787_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2228_1), .IN7(1'b1), .IN8(na2221_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x54y61 80'h00_0078_00_0000_0C88_8A31 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a790_1 ( .OUT(na790_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3278_2), .IN6(1'b1), .IN7(na326_1), .IN8(na3272_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a790_4 ( .OUT(na790_2), .IN1(~na2229_1), .IN2(~na2228_2), .IN3(1'b1), .IN4(~na4511_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x70y52 80'h00_0018_00_0040_0A33_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a792_1 ( .OUT(na792_1), .IN1(~na761_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(~na3570_2), .IN6(~na1587_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x57y58 80'h00_0060_00_0000_0C06_FFAC +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a796_4 ( .OUT(na796_2), .IN1(1'b0), .IN2(na268_2), .IN3(na2223_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x70y55 80'h00_0018_00_0040_0A50_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a797_1 ( .OUT(na797_1), .IN1(1'b0), .IN2(1'b0), .IN3(na2223_1), .IN4(1'b1), .IN5(na3175_1), .IN6(1'b0), .IN7(na3176_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x53y39 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a798_1 ( .OUT(na798_1_i), .IN1(1'b1), .IN2(na4255_2), .IN3(1'b0), .IN4(1'b0), .IN5(na3576_2), .IN6(na3184_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a798_2 ( .OUT(na798_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na798_1_i) ); +// C_MX2b//// x59y36 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a799_1 ( .OUT(na799_1), .IN1(1'b1), .IN2(na4255_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na4150_2), .IN6(na1542_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x60y35 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a800_1 ( .OUT(na800_1), .IN1(1'b1), .IN2(na4255_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na4149_2), .IN6(na1542_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x49y43 80'h00_0060_00_0000_0C08_FF75 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a801_4 ( .OUT(na801_2), .IN1(~na802_1), .IN2(1'b0), .IN3(~na636_1), .IN4(~na3543_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x55y41 80'h00_0018_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a802_1 ( .OUT(na802_1), .IN1(1'b1), .IN2(na273_1), .IN3(na636_1), .IN4(1'b1), .IN5(na675_1), .IN6(na2231_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x50y43 80'h00_0018_00_0000_0C88_73FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a803_1 ( .OUT(na803_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na804_1), .IN7(~na636_1), .IN8(~na3546_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x55y44 80'h00_0018_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a804_1 ( .OUT(na804_1), .IN1(1'b1), .IN2(na273_1), .IN3(na636_1), .IN4(1'b1), .IN5(na678_1), .IN6(na2232_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x49y43 80'h00_0018_00_0000_0C88_75FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a805_1 ( .OUT(na805_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na806_1), .IN6(1'b0), .IN7(~na636_1), .IN8(~na3549_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x55y39 80'h00_0018_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a806_1 ( .OUT(na806_1), .IN1(1'b1), .IN2(na273_1), .IN3(na636_1), .IN4(1'b1), .IN5(na680_1), .IN6(na2233_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x48y43 80'h00_0060_00_0000_0C08_FF75 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a807_4 ( .OUT(na807_2), .IN1(~na808_1), .IN2(1'b0), .IN3(~na636_1), .IN4(~na3552_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x55y43 80'h00_0018_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a808_1 ( .OUT(na808_1), .IN1(1'b1), .IN2(na273_1), .IN3(na636_1), .IN4(1'b1), .IN5(na682_1), .IN6(na2234_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x48y43 80'h00_0018_00_0000_0C88_73FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a809_1 ( .OUT(na809_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na810_1), .IN7(~na636_1), .IN8(~na3555_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x51y40 80'h00_0018_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a810_1 ( .OUT(na810_1), .IN1(1'b1), .IN2(na273_1), .IN3(na636_1), .IN4(1'b1), .IN5(na684_1), .IN6(na2235_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x48y85 80'h00_FE00_00_0040_0AC8_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a811_1 ( .OUT(na811_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na811_1), .IN8(~na812_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a811_2 ( .OUT(na811_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na811_1_i) ); +// C_MX2b//// x58y86 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a812_1 ( .OUT(na812_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1085_1), .IN5(1'b0), .IN6(~na813_1), .IN7(1'b0), .IN8(~na612_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x63y78 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a813_1 ( .OUT(na813_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3445_2), .IN7(1'b1), .IN8(na56_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x23y80 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a814_1 ( .OUT(na814_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na815_1), .IN6(na814_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a814_2 ( .OUT(na814_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na814_1_i) ); +// C_MX4b/D/// x23y79 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a815_1 ( .OUT(na815_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na816_1), .IN6(na4292_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a815_2 ( .OUT(na815_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na815_1_i) ); +// C_MX4b/D/// x25y81 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a816_1 ( .OUT(na816_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na816_1), .IN6(na4294_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a816_2 ( .OUT(na816_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na816_1_i) ); +// C_ORAND//// x47y76 80'h00_0018_00_0000_0888_5FAD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a817_1 ( .OUT(na817_1), .IN1(~na4610_2), .IN2(na219_2), .IN3(na4609_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(~na1517_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x45y84 80'h00_0060_00_0000_0C08_FFA3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a819_4 ( .OUT(na819_2), .IN1(1'b1), .IN2(~na219_2), .IN3(na3580_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y83 80'h00_0018_00_0000_0888_53A1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a820_1 ( .OUT(na820_1), .IN1(~na2712_2), .IN2(~na232_1), .IN3(na1340_1), .IN4(1'b1), .IN5(1'b1), .IN6(~na4553_2), .IN7(~na2713_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x51y85 80'h00_FE00_00_0000_0C88_2CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a821_1 ( .OUT(na821_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1325_1), .IN7(na1326_1), .IN8(~na409_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a821_2 ( .OUT(na821_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na821_1_i) ); +// C_OR////D x33y60 80'h00_FE18_00_0000_0EEE_C003 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a822_1 ( .OUT(na822_1), .IN1(1'b0), .IN2(~na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na3582_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a822_5 ( .OUT(na822_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na822_1) ); +// C_MX4b/D/// x28y82 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a823_1 ( .OUT(na823_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1309_1), + .IN8(na823_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a823_2 ( .OUT(na823_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na823_1_i) ); +// C_AND/D/// x69y90 80'h00_FE00_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a825_1 ( .OUT(na825_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1633_1), .IN6(1'b1), .IN7(~na443_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a825_2 ( .OUT(na825_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na825_1_i) ); +// C_AND/D//AND/D x70y90 80'h00_FE00_80_0000_0C88_5A1F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a826_1 ( .OUT(na826_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1633_2), .IN6(1'b1), .IN7(~na443_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a826_2 ( .OUT(na826_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na826_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a826_4 ( .OUT(na826_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na443_1), .IN4(~na826_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a826_5 ( .OUT(na826_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na826_2_i) ); +// C_MX2b/D/// x23y52 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a827_1 ( .OUT(na827_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na828_1), .IN6(1'b0), .IN7(na2599_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a827_2 ( .OUT(na827_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na827_1_i) ); +// C_MX2b/D/// x23y49 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a828_1 ( .OUT(na828_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1819_2), .IN8(na829_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a828_2 ( .OUT(na828_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na828_1_i) ); +// C_MX2b/D/// x22y48 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a829_1 ( .OUT(na829_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na830_1), .IN6(1'b0), .IN7(na1819_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a829_2 ( .OUT(na829_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na829_1_i) ); +// C_MX2b/D/// x21y47 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a830_1 ( .OUT(na830_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na831_1), .IN6(1'b0), .IN7(na1821_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a830_2 ( .OUT(na830_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na830_1_i) ); +// C_MX2b/D/// x21y45 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a831_1 ( .OUT(na831_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na837_1), .IN6(1'b0), .IN7(na1821_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a831_2 ( .OUT(na831_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na831_1_i) ); +// C_MX2b/D/// x21y53 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a832_1 ( .OUT(na832_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na833_1), .IN6(1'b0), .IN7(na1815_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a832_2 ( .OUT(na832_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na832_1_i) ); +// C_MX2b/D/// x27y49 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a833_1 ( .OUT(na833_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1815_1), .IN8(na834_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a833_2 ( .OUT(na833_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na833_1_i) ); +// C_MX2b/D/// x24y52 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a834_1 ( .OUT(na834_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1817_2), .IN8(na835_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a834_2 ( .OUT(na834_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na834_1_i) ); +// C_MX2b/D/// x24y46 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a835_1 ( .OUT(na835_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na836_1), .IN6(1'b0), .IN7(na1817_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a835_2 ( .OUT(na835_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na835_1_i) ); +// C_MX2b/D/// x21y41 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a836_1 ( .OUT(na836_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na837_1), .IN6(1'b0), .IN7(na3532_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a836_2 ( .OUT(na836_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na836_1_i) ); +// C_MX2b/D/// x21y39 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a837_1 ( .OUT(na837_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3531_2), .IN8(na838_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a837_2 ( .OUT(na837_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na837_1_i) ); +// C_MX2b/D/// x24y40 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a838_1 ( .OUT(na838_1_i), .IN1(1'b1), .IN2(~na1487_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na839_1), .IN8(na3530_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a838_2 ( .OUT(na838_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na838_1_i) ); +// C_MX2b/D/// x22y37 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a839_1 ( .OUT(na839_1_i), .IN1(1'b1), .IN2(~na1487_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na840_1), .IN8(na3529_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a839_2 ( .OUT(na839_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na839_1_i) ); +// C_MX2b/D/// x24y37 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a840_1 ( .OUT(na840_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na841_1), .IN6(1'b0), .IN7(na3528_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a840_2 ( .OUT(na840_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na840_1_i) ); +// C_MX2b/D/// x23y41 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a841_1 ( .OUT(na841_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3527_2), .IN8(na1591_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a841_2 ( .OUT(na841_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na841_1_i) ); +// C_MX2b/D/// x19y46 80'h00_F600_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a842_1 ( .OUT(na842_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4442_2), .IN5(na4543_2), .IN6(1'b0), .IN7(na2481_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a842_2 ( .OUT(na842_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na842_1_i) ); +// C_MX2b/D/// x19y53 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a843_1 ( .OUT(na843_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na844_1), .IN6(1'b0), .IN7(na1815_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a843_2 ( .OUT(na843_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na843_1_i) ); +// C_MX2b/D/// x25y57 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a844_1 ( .OUT(na844_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na845_1), .IN6(1'b0), .IN7(na1823_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a844_2 ( .OUT(na844_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na844_1_i) ); +// C_MX2b/D/// x29y55 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a845_1 ( .OUT(na845_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na846_1), .IN6(1'b0), .IN7(na1823_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a845_2 ( .OUT(na845_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na845_1_i) ); +// C_MX2b/D/// x23y53 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a846_1 ( .OUT(na846_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na847_1), .IN6(1'b0), .IN7(na1825_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a846_2 ( .OUT(na846_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na846_1_i) ); +// C_MX2b/D/// x27y53 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a847_1 ( .OUT(na847_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na848_1), .IN6(1'b0), .IN7(na1825_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a847_2 ( .OUT(na847_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na847_1_i) ); +// C_MX2b/D/// x27y51 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a848_1 ( .OUT(na848_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na849_1), .IN6(1'b0), .IN7(na1811_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a848_2 ( .OUT(na848_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na848_1_i) ); +// C_MX2a/D/// x29y53 80'h00_F600_00_0040_0C05_3000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a849_1 ( .OUT(na849_1_i), .IN1(na850_1), .IN2(1'b0), .IN3(na1811_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(~na4442_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a849_2 ( .OUT(na849_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na849_1_i) ); +// C_MX2b/D/// x27y55 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a850_1 ( .OUT(na850_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(na851_1), .IN6(1'b0), .IN7(na1813_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a850_2 ( .OUT(na850_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na850_1_i) ); +// C_MX2b/D/// x23y47 80'h00_F600_00_0040_0A51_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a851_1 ( .OUT(na851_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4442_2), .IN5(~na852_1), .IN6(1'b0), .IN7(na1813_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a851_2 ( .OUT(na851_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na851_1_i) ); +// C_MX2b//// x19y47 80'h00_0018_00_0040_0A55_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a852_1 ( .OUT(na852_1), .IN1(1'b0), .IN2(1'b0), .IN3(na2481_2), .IN4(1'b1), .IN5(~na832_1), .IN6(1'b0), .IN7(~na2481_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x28y56 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a853_1 ( .OUT(na853_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na855_1), .IN5(na854_1), .IN6(1'b0), .IN7(na856_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a853_2 ( .OUT(na853_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na853_1_i) ); +// C_MX2a//// x29y51 80'h00_0018_00_0040_0C0C_F500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a854_1 ( .OUT(na854_1), .IN1(1'b0), .IN2(1'b0), .IN3(na1825_1), .IN4(na853_1), .IN5(~na121_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x26y54 80'h00_0018_00_0000_0C88_88FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a855_1 ( .OUT(na855_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4522_2), .IN6(na2478_1), .IN7(na2481_2), .IN8(na4442_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x30y55 80'h00_FE00_00_0040_0C05_3000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a856_1 ( .OUT(na856_1_i), .IN1(na858_1), .IN2(1'b0), .IN3(na857_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(~na855_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a856_2 ( .OUT(na856_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na856_1_i) ); +// C_MX2b//// x30y51 80'h00_0018_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a857_1 ( .OUT(na857_1), .IN1(na121_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na856_1), .IN8(na4479_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x31y55 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a858_1 ( .OUT(na858_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na855_1), .IN5(1'b0), .IN6(na859_1), .IN7(1'b0), .IN8(na860_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a858_2 ( .OUT(na858_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na858_1_i) ); +// C_MX2a//// x27y50 80'h00_0018_00_0040_0C03_0A00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a859_1 ( .OUT(na859_1), .IN1(na858_1), .IN2(na4478_2), .IN3(1'b0), .IN4(1'b0), .IN5(na121_2), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x30y56 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a860_1 ( .OUT(na860_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na855_1), .IN5(1'b0), .IN6(na861_1), .IN7(1'b0), .IN8(na862_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a860_2 ( .OUT(na860_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na860_1_i) ); +// C_MX2a//// x29y50 80'h00_0018_00_0040_0C0C_F500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a861_1 ( .OUT(na861_1), .IN1(1'b0), .IN2(1'b0), .IN3(na1813_2), .IN4(na860_1), .IN5(~na121_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x30y52 80'h00_FE00_00_0040_0AC0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a862_1 ( .OUT(na862_1_i), .IN1(~na121_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na855_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1813_1), + .IN8(na862_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a862_2 ( .OUT(na862_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na862_1_i) ); +// C_MX2b/D/// x26y52 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a864_1 ( .OUT(na864_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na203_1), .IN5(na865_1), .IN6(1'b0), .IN7(na3532_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a864_2 ( .OUT(na864_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na864_1_i) ); +// C_MX2b/D/// x23y39 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a865_1 ( .OUT(na865_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na203_1), .IN5(na866_1), .IN6(1'b0), .IN7(na3531_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a865_2 ( .OUT(na865_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na865_1_i) ); +// C_MX2b/D/// x23y37 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a866_1 ( .OUT(na866_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na203_1), .IN5(1'b0), .IN6(na867_1), .IN7(1'b0), .IN8(na3530_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a866_2 ( .OUT(na866_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na866_1_i) ); +// C_MX2a/D/// x23y36 80'h00_FE00_00_0040_0C0A_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a867_1 ( .OUT(na867_1_i), .IN1(1'b0), .IN2(na868_1), .IN3(1'b0), .IN4(na3529_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na203_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a867_2 ( .OUT(na867_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na867_1_i) ); +// C_MX2b/D/// x27y40 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a868_1 ( .OUT(na868_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na203_1), .IN5(na869_1), .IN6(1'b0), .IN7(na3528_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a868_2 ( .OUT(na868_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na868_1_i) ); +// C_MX2a/D/// x27y37 80'h00_FE00_00_0040_0C05_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a869_1 ( .OUT(na869_1_i), .IN1(na870_1), .IN2(1'b0), .IN3(na3527_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na203_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a869_2 ( .OUT(na869_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na869_1_i) ); +// C_MX2b/D/// x29y35 80'h00_FE00_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a870_1 ( .OUT(na870_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na203_1), .IN5(1'b0), .IN6(na202_1), .IN7(1'b0), .IN8(na3526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a870_2 ( .OUT(na870_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na870_1_i) ); +// C_MX2b/D/// x40y56 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a871_1 ( .OUT(na871_1_i), .IN1(~na399_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3423_2), .IN8(na872_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a871_2 ( .OUT(na871_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na871_1_i) ); +// C_MX2b/D/// x40y52 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a872_1 ( .OUT(na872_1_i), .IN1(na399_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na873_1), .IN8(na3421_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a872_2 ( .OUT(na872_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na872_1_i) ); +// C_MX2b/D/// x42y51 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a873_1 ( .OUT(na873_1_i), .IN1(na399_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na874_1), .IN8(na3420_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a873_2 ( .OUT(na873_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na873_1_i) ); +// C_MX2a/D/// x40y53 80'h00_FE00_00_0040_0C0C_F500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a874_1 ( .OUT(na874_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na3417_1), .IN4(na875_1), .IN5(~na399_2), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a874_2 ( .OUT(na874_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na874_1_i) ); +// C_MX2b/D/// x42y54 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a875_1 ( .OUT(na875_1_i), .IN1(~na399_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3416_2), .IN8(na876_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a875_2 ( .OUT(na875_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na875_1_i) ); +// C_MX2a/D/// x38y54 80'h00_FE00_00_0040_0C0C_FA00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a876_1 ( .OUT(na876_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na397_1), .IN4(na3414_1), .IN5(na399_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a876_2 ( .OUT(na876_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na876_1_i) ); +// C_MX4b////D x23y63 80'h00_FA18_00_0040_0AF4_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a877_1 ( .OUT(na877_1), .IN1(1'b1), .IN2(na878_1), .IN3(1'b1), .IN4(~na864_1), .IN5(na1488_1), .IN6(na4301_2), .IN7(~na880_2), + .IN8(na4443_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a877_5 ( .OUT(na877_2), .CLK(na1739_1), .EN(na1487_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na877_1) ); +// C_MX2b//// x21y52 80'h00_0018_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a878_1 ( .OUT(na878_1), .IN1(~na2479_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4300_2), .IN8(na3256_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x35y40 80'h00_0018_00_0040_0A55_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a879_1 ( .OUT(na879_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na203_2), .IN5(~na698_1), .IN6(1'b0), .IN7(~na3532_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x26y59 80'h00_0060_00_0000_0C08_FFCB +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a880_4 ( .OUT(na880_2), .IN1(na3585_1), .IN2(~na2474_1), .IN3(1'b0), .IN4(na214_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ANDXOR////D x35y52 80'h00_FA18_00_0000_0666_F3B5 +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a881_1 ( .OUT(na881_1), .IN1(na882_2), .IN2(1'b1), .IN3(~na3588_1), .IN4(na864_1), .IN5(1'b1), .IN6(na1482_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a881_5 ( .OUT(na881_2), .CLK(na1739_1), .EN(na1481_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na881_1) ); +// C_///AND/ x19y59 80'h00_0060_00_0000_0C08_FF31 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a882_4 ( .OUT(na882_2), .IN1(~na883_1), .IN2(~na2478_1), .IN3(1'b1), .IN4(~na3256_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x19y57 80'h00_0018_00_0000_0888_F9AC +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a883_1 ( .OUT(na883_1), .IN1(1'b0), .IN2(~na4303_2), .IN3(~na2481_2), .IN4(1'b0), .IN5(na4524_2), .IN6(na2478_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x16y64 80'h00_0060_00_0000_0C08_FF2C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a884_4 ( .OUT(na884_2), .IN1(1'b1), .IN2(na4119_2), .IN3(na1369_1), .IN4(~na214_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x20y52 80'h00_0018_00_0000_0C88_DCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a885_1 ( .OUT(na885_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na4297_2), .IN7(~na2481_2), .IN8(na3589_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x25y59 80'h00_F600_00_0040_0C0A_2F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a886_1 ( .OUT(na886_1_i), .IN1(1'b0), .IN2(na881_1), .IN3(1'b0), .IN4(na2499_1), .IN5(1'b1), .IN6(1'b1), .IN7(na304_1), .IN8(~na4164_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a886_2 ( .OUT(na886_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na886_1_i) ); +// C_///AND/D x24y51 80'h00_FE00_80_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a887_4 ( .OUT(na887_2_i), .IN1(na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(na3426_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a887_5 ( .OUT(na887_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na887_2_i) ); +// C_AND////D x23y57 80'h00_FE18_00_0000_0888_33FC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a888_1 ( .OUT(na888_1), .IN1(1'b1), .IN2(na927_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na927_1), .IN7(1'b1), .IN8(~na1303_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a888_5 ( .OUT(na888_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na888_1) ); +// C_ANDXOR/D//AND/D x16y49 80'h00_FA00_80_0000_0C68_CEAF +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a891_1 ( .OUT(na891_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na3590_1), .IN6(~na2474_2), .IN7(1'b1), .IN8(~na4299_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a891_2 ( .OUT(na891_1), .CLK(na1739_1), .EN(na1479_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na891_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a891_4 ( .OUT(na891_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na891_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a891_5 ( .OUT(na891_2), .CLK(na1739_1), .EN(na1479_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na891_2_i) ); +// C_ORAND*/D//ORAND*/D x46y49 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a892_1 ( .OUT(na892_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na4305_2), .IN7(~na2593_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a892_2 ( .OUT(na892_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na892_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a892_4 ( .OUT(na892_2_i), .IN1(~na301_1), .IN2(~na894_1), .IN3(~na2593_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a892_5 ( .OUT(na892_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na892_2_i) ); +// C_ORAND*/D//ORAND*/D x43y50 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a894_1 ( .OUT(na894_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na894_2), .IN7(~na2595_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a894_2 ( .OUT(na894_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na894_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a894_4 ( .OUT(na894_2_i), .IN1(~na301_1), .IN2(~na4308_2), .IN3(~na2595_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a894_5 ( .OUT(na894_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na894_2_i) ); +// C_ORAND*/D//ORAND*/D x46y50 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a896_1 ( .OUT(na896_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na4309_2), .IN7(~na2597_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a896_2 ( .OUT(na896_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na896_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a896_4 ( .OUT(na896_2_i), .IN1(~na301_1), .IN2(~na898_1), .IN3(~na2597_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a896_5 ( .OUT(na896_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na896_2_i) ); +// C_ORAND*/D//ORAND*/D x39y50 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a898_1 ( .OUT(na898_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na898_2), .IN7(~na2599_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a898_2 ( .OUT(na898_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na898_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a898_4 ( .OUT(na898_2_i), .IN1(~na301_1), .IN2(~na900_1), .IN3(~na2599_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a898_5 ( .OUT(na898_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na898_2_i) ); +// C_ORAND*/D//ORAND*/D x41y50 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a900_1 ( .OUT(na900_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na900_2), .IN7(~na1819_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a900_2 ( .OUT(na900_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na900_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a900_4 ( .OUT(na900_2_i), .IN1(~na301_1), .IN2(~na902_1), .IN3(~na1819_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a900_5 ( .OUT(na900_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na900_2_i) ); +// C_ORAND*/D//ORAND*/D x41y46 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a902_1 ( .OUT(na902_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na902_2), .IN7(~na1821_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a902_2 ( .OUT(na902_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na902_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a902_4 ( .OUT(na902_2_i), .IN1(~na301_1), .IN2(~na904_1), .IN3(~na1821_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a902_5 ( .OUT(na902_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na902_2_i) ); +// C_ORAND*/D//ORAND*/D x45y48 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a904_1 ( .OUT(na904_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na904_2), .IN7(~na1823_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a904_2 ( .OUT(na904_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na904_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a904_4 ( .OUT(na904_2_i), .IN1(~na301_1), .IN2(~na906_1), .IN3(~na1823_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a904_5 ( .OUT(na904_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na904_2_i) ); +// C_ORAND*/D//ORAND*/D x41y48 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a906_1 ( .OUT(na906_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na906_2), .IN7(~na1825_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a906_2 ( .OUT(na906_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na906_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a906_4 ( .OUT(na906_2_i), .IN1(~na301_1), .IN2(~na4318_2), .IN3(~na1825_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a906_5 ( .OUT(na906_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na906_2_i) ); +// C_ORAND*/D//ORAND*/D x45y47 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a908_1 ( .OUT(na908_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na4319_2), .IN7(~na1811_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a908_2 ( .OUT(na908_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na908_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a908_4 ( .OUT(na908_2_i), .IN1(~na301_1), .IN2(~na910_1), .IN3(~na1811_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a908_5 ( .OUT(na908_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na908_2_i) ); +// C_ORAND*/D//ORAND*/D x47y46 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a910_1 ( .OUT(na910_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na910_2), .IN7(~na1813_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a910_2 ( .OUT(na910_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na910_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a910_4 ( .OUT(na910_2_i), .IN1(~na301_1), .IN2(~na912_1), .IN3(~na1813_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a910_5 ( .OUT(na910_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na910_2_i) ); +// C_ORAND*/D//ORAND*/D x43y46 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a912_1 ( .OUT(na912_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na912_2), .IN7(~na1815_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a912_2 ( .OUT(na912_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na912_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a912_4 ( .OUT(na912_2_i), .IN1(~na301_1), .IN2(~na914_1), .IN3(~na1815_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a912_5 ( .OUT(na912_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na912_2_i) ); +// C_ORAND*/D//ORAND*/D x45y46 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a914_1 ( .OUT(na914_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na914_2), .IN7(~na1817_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a914_2 ( .OUT(na914_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na914_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a914_4 ( .OUT(na914_2_i), .IN1(~na301_1), .IN2(~na916_1), .IN3(~na1817_1), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a914_5 ( .OUT(na914_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na914_2_i) ); +// C_ORAND*/D//ORAND*/D x45y42 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a916_1 ( .OUT(na916_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na916_2), .IN7(~na3532_1), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a916_2 ( .OUT(na916_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na916_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a916_4 ( .OUT(na916_2_i), .IN1(~na301_1), .IN2(~na4324_2), .IN3(~na3531_2), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a916_5 ( .OUT(na916_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na916_2_i) ); +// C_ORAND*/D//ORAND*/D x46y41 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a918_1 ( .OUT(na918_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na4325_2), .IN7(~na4608_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a918_2 ( .OUT(na918_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na918_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a918_4 ( .OUT(na918_2_i), .IN1(~na301_1), .IN2(~na920_1), .IN3(~na4607_2), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a918_5 ( .OUT(na918_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na918_2_i) ); +// C_ORAND*/D//ORAND*/D x43y42 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a920_1 ( .OUT(na920_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na920_2), .IN7(~na3528_1), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a920_2 ( .OUT(na920_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na920_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a920_4 ( .OUT(na920_2_i), .IN1(~na301_1), .IN2(~na4328_2), .IN3(~na3527_2), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a920_5 ( .OUT(na920_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na920_2_i) ); +// C_ORAND*/D//ORAND*/D x40y41 80'h00_F600_80_0000_0387_777D +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a922_1 ( .OUT(na922_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na301_1), .IN6(~na4329_2), .IN7(~na4606_2), + .IN8(~na302_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a922_2 ( .OUT(na922_1), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na922_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a922_4 ( .OUT(na922_2_i), .IN1(~na301_1), .IN2(na879_1), .IN3(~na4605_2), .IN4(~na302_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a922_5 ( .OUT(na922_2), .CLK(na1739_1), .EN(~na1404_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na922_2_i) ); +// C_ORAND//// x33y53 80'h00_0018_00_0000_0C88_E3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a924_1 ( .OUT(na924_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na2474_1), .IN7(na4133_2), .IN8(na3657_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x26y70 80'h00_FE00_00_0040_0AC8_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a926_1 ( .OUT(na926_1_i), .IN1(1'b1), .IN2(na978_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4330_2), + .IN8(~na926_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a926_2 ( .OUT(na926_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na926_1_i) ); +// C_AND/D//AND/D x17y62 80'h00_FE00_80_0000_0C88_A5F1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a927_1 ( .OUT(na927_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na436_1), .IN6(1'b1), .IN7(na1653_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a927_2 ( .OUT(na927_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na927_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a927_4 ( .OUT(na927_2_i), .IN1(~na436_1), .IN2(~na927_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a927_5 ( .OUT(na927_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na927_2_i) ); +// C_MX4b/D/// x26y71 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a928_1 ( .OUT(na928_1_i), .IN1(1'b1), .IN2(~na978_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1658_1), .IN6(na4332_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a928_2 ( .OUT(na928_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na928_1_i) ); +// C_MX4b/D/// x27y72 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a929_1 ( .OUT(na929_1_i), .IN1(1'b1), .IN2(~na978_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1658_2), .IN6(na929_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a929_2 ( .OUT(na929_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na929_1_i) ); +// C_///OR/D x13y47 80'h00_FE00_80_0000_0C0E_FFA5 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a930_4 ( .OUT(na930_2_i), .IN1(~na3259_1), .IN2(1'b0), .IN3(na931_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a930_5 ( .OUT(na930_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na930_2_i) ); +// C_AND//// x22y53 80'h00_0018_00_0000_0888_32F2 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a931_1 ( .OUT(na931_1), .IN1(na2479_2), .IN2(~na122_2), .IN3(1'b1), .IN4(1'b1), .IN5(na3218_1), .IN6(~na122_1), .IN7(1'b1), + .IN8(~na1495_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x21y44 80'h00_FE00_00_0040_0AC4_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a932_1 ( .OUT(na932_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na211_1), .IN8(na1545_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a932_2 ( .OUT(na932_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na932_1_i) ); +// C_MX2b/D/// x23y42 80'h00_FE00_00_0040_0AC4_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a933_1 ( .OUT(na933_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na4414_2), .IN8(na1545_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a933_2 ( .OUT(na933_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na933_1_i) ); +// C_ORAND/D/// x20y37 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a934_1 ( .OUT(na934_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3661_1), .IN6(~na194_1), .IN7(~na3660_2), + .IN8(~na4536_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a934_2 ( .OUT(na934_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na934_1_i) ); +// C_///ORAND/D x20y35 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a936_4 ( .OUT(na936_2_i), .IN1(~na3664_1), .IN2(~na194_1), .IN3(~na3660_2), .IN4(~na4537_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a936_5 ( .OUT(na936_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na936_2_i) ); +// C_ORAND/D/// x19y36 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a938_1 ( .OUT(na938_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3667_1), .IN6(~na194_1), .IN7(~na3660_2), + .IN8(~na2489_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a938_2 ( .OUT(na938_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na938_1_i) ); +// C_///ORAND/D x19y36 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a940_4 ( .OUT(na940_2_i), .IN1(~na3670_1), .IN2(~na194_1), .IN3(~na3660_2), .IN4(~na4538_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a940_5 ( .OUT(na940_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na940_2_i) ); +// C_ORAND/D/// x20y35 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a942_1 ( .OUT(na942_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3673_1), .IN6(~na194_1), .IN7(~na3660_2), + .IN8(~na2489_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a942_2 ( .OUT(na942_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na942_1_i) ); +// C_MX2b/D/// x42y41 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a944_1 ( .OUT(na944_1_i), .IN1(1'b1), .IN2(~na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3187_1), .IN6(na3674_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a944_2 ( .OUT(na944_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na944_1_i) ); +// C_MX2b/D/// x39y37 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a945_1 ( .OUT(na945_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3675_1), .IN6(na3188_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a945_2 ( .OUT(na945_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na945_1_i) ); +// C_MX2b/D/// x38y37 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a946_1 ( .OUT(na946_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3676_1), .IN6(na3189_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a946_2 ( .OUT(na946_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na946_1_i) ); +// C_MX2b/D/// x40y37 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a947_1 ( .OUT(na947_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3677_1), .IN8(na3190_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a947_2 ( .OUT(na947_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na947_1_i) ); +// C_MX2b/D/// x38y42 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a948_1 ( .OUT(na948_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3678_2), .IN6(na3191_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a948_2 ( .OUT(na948_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na948_1_i) ); +// C_MX2b/D/// x39y41 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a949_1 ( .OUT(na949_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3679_1), .IN6(na3192_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a949_2 ( .OUT(na949_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na949_1_i) ); +// C_MX2b/D/// x33y42 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a950_1 ( .OUT(na950_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3680_1), .IN6(na3193_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a950_2 ( .OUT(na950_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na950_1_i) ); +// C_ORAND*////D x22y59 80'h00_FE18_00_0000_0788_5BD3 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a951_1 ( .OUT(na951_1), .IN1(1'b0), .IN2(~na957_1), .IN3(~na304_1), .IN4(na3682_1), .IN5(na959_1), .IN6(~na957_2), .IN7(~na304_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a951_5 ( .OUT(na951_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na951_1) ); +// C_AND///AND/ x26y61 80'h00_0078_00_0000_0C88_12C3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a952_1 ( .OUT(na952_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3683_1), .IN6(~na2474_1), .IN7(~na4523_2), + .IN8(~na2473_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a952_4 ( .OUT(na952_2), .IN1(1'b1), .IN2(~na2474_1), .IN3(1'b1), .IN4(na2473_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ANDXOR/ x17y54 80'h00_0060_00_0000_0C06_FFB3 +C_ANDXOR #(.CPE_CFG (9'b0_1000_0000)) + _a953_4 ( .OUT(na953_2), .IN1(1'b1), .IN2(na878_1), .IN3(~na4611_2), .IN4(na954_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x22y50 80'h00_0018_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a954_1 ( .OUT(na954_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2472_1), .IN6(na4531_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x19y58 80'h00_0078_00_0000_0C88_8C51 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a957_1 ( .OUT(na957_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3258_2), .IN7(na123_1), .IN8(na3252_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a957_4 ( .OUT(na957_2), .IN1(~na4528_2), .IN2(~na2478_1), .IN3(~na2481_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x37y51 80'h00_0018_00_0040_0A33_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a959_1 ( .OUT(na959_1), .IN1(~na924_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(~na3688_2), .IN6(~na1593_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x21y54 80'h00_0060_00_0000_0C06_FFAC +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a963_4 ( .OUT(na963_2), .IN1(1'b0), .IN2(na193_2), .IN3(na4523_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x27y59 80'h00_0018_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a964_1 ( .OUT(na964_1), .IN1(1'b1), .IN2(na2474_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3185_1), .IN8(na3186_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x33y43 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a965_1 ( .OUT(na965_1_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3694_2), .IN6(na3194_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a965_2 ( .OUT(na965_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na965_1_i) ); +// C_MX2b//// x40y40 80'h00_0018_00_0040_0AC4_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a966_1 ( .OUT(na966_1), .IN1(1'b1), .IN2(na194_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na4127_2), .IN8(na1545_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x39y40 80'h00_0018_00_0040_0AC4_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a967_1 ( .OUT(na967_1), .IN1(1'b1), .IN2(na194_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na4126_2), .IN8(na1545_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x25y42 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a968_4 ( .OUT(na968_2), .IN1(~na3661_1), .IN2(~na194_1), .IN3(~na969_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x26y45 80'h00_0018_00_0040_0AA0_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a969_1 ( .OUT(na969_1), .IN1(1'b1), .IN2(~na194_1), .IN3(1'b1), .IN4(~na203_1), .IN5(1'b0), .IN6(na2482_1), .IN7(1'b0), .IN8(na853_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x22y46 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a970_4 ( .OUT(na970_2), .IN1(~na3664_1), .IN2(~na194_1), .IN3(~na971_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x26y43 80'h00_0018_00_0040_0AC0_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a971_1 ( .OUT(na971_1), .IN1(1'b1), .IN2(na4124_2), .IN3(1'b1), .IN4(~na4122_2), .IN5(1'b0), .IN6(1'b0), .IN7(na856_1), .IN8(na2483_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x24y43 80'h00_0060_00_0000_0C08_FF37 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a972_4 ( .OUT(na972_2), .IN1(~na3667_1), .IN2(~na194_1), .IN3(1'b0), .IN4(~na973_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x26y44 80'h00_0018_00_0040_0A50_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a973_1 ( .OUT(na973_1), .IN1(1'b1), .IN2(na194_1), .IN3(1'b1), .IN4(na203_1), .IN5(na858_1), .IN6(1'b0), .IN7(na2484_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x25y42 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a974_1 ( .OUT(na974_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3670_1), .IN6(~na194_1), .IN7(~na975_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x30y45 80'h00_0018_00_0040_0AA0_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a975_1 ( .OUT(na975_1), .IN1(1'b1), .IN2(~na194_1), .IN3(1'b1), .IN4(~na203_1), .IN5(1'b0), .IN6(na2485_2), .IN7(1'b0), .IN8(na860_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x25y41 80'h00_0060_00_0000_0C08_FF37 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a976_4 ( .OUT(na976_2), .IN1(~na3673_1), .IN2(~na194_1), .IN3(1'b0), .IN4(~na977_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x26y42 80'h00_0018_00_0040_0AA0_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a977_1 ( .OUT(na977_1), .IN1(1'b1), .IN2(~na194_1), .IN3(1'b1), .IN4(~na203_1), .IN5(1'b0), .IN6(na2486_1), .IN7(1'b0), .IN8(na862_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D/// x27y70 80'h00_FE00_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a978_1 ( .OUT(na978_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na445_2), .IN6(na978_1), .IN7(1'b0), .IN8(na3695_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a978_2 ( .OUT(na978_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na978_1_i) ); +// C_///AND/D x62y87 80'h00_FE00_80_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a980_4 ( .OUT(na980_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na1649_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a980_5 ( .OUT(na980_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na980_2_i) ); +// C_///AND/ x36y69 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a982_4 ( .OUT(na982_2), .IN1(na408_1), .IN2(1'b1), .IN3(~na407_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x29y71 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a983_4 ( .OUT(na983_2), .IN1(~na7_2), .IN2(1'b1), .IN3(na11_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D/// x31y73 80'h00_FE00_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a984_1 ( .OUT(na984_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3698_1), .IN6(~na3697_2), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a984_2 ( .OUT(na984_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na984_1_i) ); +// C_AND/D//AND/D x56y92 80'h00_FE00_80_0000_0C88_2F4F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a986_1 ( .OUT(na986_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1651_1), .IN8(~na4366_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a986_2 ( .OUT(na986_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na986_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a986_4 ( .OUT(na986_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na1149_2), .IN4(na1649_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a986_5 ( .OUT(na986_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na986_2_i) ); +// C_AND/D/// x59y69 80'h00_FE00_00_0000_0888_8141 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a987_1 ( .OUT(na987_1_i), .IN1(~na4423_2), .IN2(~na285_2), .IN3(~na1149_2), .IN4(na4153_2), .IN5(~na987_1), .IN6(~na22_2), + .IN7(na4070_2), .IN8(na4111_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a987_2 ( .OUT(na987_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na987_1_i) ); +// C_AND//// x20y89 80'h00_0018_00_0000_0888_1125 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a990_1 ( .OUT(na990_1), .IN1(~na411_1), .IN2(1'b1), .IN3(na992_1), .IN4(~na413_1), .IN5(~na418_1), .IN6(~na412_1), .IN7(~na1351_2), + .IN8(~na1350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x22y81 80'h00_0018_00_0000_0C88_11FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a992_1 ( .OUT(na992_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na414_1), .IN6(~na415_1), .IN7(~na416_1), .IN8(~na417_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x40y78 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a993_1 ( .OUT(na993_1_i), .IN1(~na399_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3424_1), .IN8(na994_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a993_2 ( .OUT(na993_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na993_1_i) ); +// C_MX2b/D/// x38y60 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a994_1 ( .OUT(na994_1_i), .IN1(~na399_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3423_2), .IN8(na995_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a994_2 ( .OUT(na994_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na994_1_i) ); +// C_MX2b/D/// x38y56 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a995_1 ( .OUT(na995_1_i), .IN1(na399_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na996_1), .IN8(na3421_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a995_2 ( .OUT(na995_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na995_1_i) ); +// C_MX2b/D/// x40y51 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a996_1 ( .OUT(na996_1_i), .IN1(na399_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na997_1), .IN8(na3420_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a996_2 ( .OUT(na996_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na996_1_i) ); +// C_MX2b/D/// x36y53 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a997_1 ( .OUT(na997_1_i), .IN1(~na399_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3417_1), .IN8(na998_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a997_2 ( .OUT(na997_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na997_1_i) ); +// C_MX2b/D/// x34y54 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a998_1 ( .OUT(na998_1_i), .IN1(~na399_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3416_2), .IN8(na999_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a998_2 ( .OUT(na998_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na998_1_i) ); +// C_MX2b/D/// x40y54 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a999_1 ( .OUT(na999_1_i), .IN1(na399_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na398_1), .IN8(na3414_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a999_2 ( .OUT(na999_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na999_1_i) ); +// C_MX2b/D/// x39y75 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1000_1 ( .OUT(na1000_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1001_1), .IN8(na2846_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1000_2 ( .OUT(na1000_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1000_1_i) ); +// C_MX2b/D/// x42y79 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1001_1 ( .OUT(na1001_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1002_1), .IN8(na1780_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1001_2 ( .OUT(na1001_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1001_1_i) ); +// C_MX2b/D/// x44y79 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1002_1 ( .OUT(na1002_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1003_1), .IN8(na1780_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1002_2 ( .OUT(na1002_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1002_1_i) ); +// C_MX2b/D/// x42y77 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1003_1 ( .OUT(na1003_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1004_1), .IN8(na1782_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1003_2 ( .OUT(na1003_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1003_1_i) ); +// C_MX2b/D/// x40y71 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1004_1 ( .OUT(na1004_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4335_2), .IN8(na1782_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1004_2 ( .OUT(na1004_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1004_1_i) ); +// C_MX2b/D/// x43y82 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1005_1 ( .OUT(na1005_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1006_1), .IN8(na1792_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1005_2 ( .OUT(na1005_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1005_1_i) ); +// C_MX2b/D/// x44y81 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1006_1 ( .OUT(na1006_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1007_1), .IN8(na1792_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1006_2 ( .OUT(na1006_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1006_1_i) ); +// C_MX2b/D/// x46y77 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1007_1 ( .OUT(na1007_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1008_1), .IN8(na1794_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1007_2 ( .OUT(na1007_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1007_1_i) ); +// C_MX2b/D/// x44y73 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1008_1 ( .OUT(na1008_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1009_1), .IN8(na1794_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1008_2 ( .OUT(na1008_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1008_1_i) ); +// C_MX2b/D/// x40y65 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1009_1 ( .OUT(na1009_1_i), .IN1(1'b1), .IN2(na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3424_1), .IN8(na1010_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1009_2 ( .OUT(na1009_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1009_1_i) ); +// C_MX2b/D/// x40y66 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1010_1 ( .OUT(na1010_1_i), .IN1(1'b1), .IN2(na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3423_2), .IN8(na1011_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1010_2 ( .OUT(na1010_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1010_1_i) ); +// C_MX2b/D/// x40y60 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1011_1 ( .OUT(na1011_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1012_1), .IN8(na3421_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1011_2 ( .OUT(na1011_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1011_1_i) ); +// C_MX2b/D/// x38y59 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1012_1 ( .OUT(na1012_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1013_1), .IN8(na3420_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1012_2 ( .OUT(na1012_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1012_1_i) ); +// C_MX2b/D/// x36y61 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1013_1 ( .OUT(na1013_1_i), .IN1(1'b1), .IN2(na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3417_1), .IN8(na1014_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1013_2 ( .OUT(na1013_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1013_1_i) ); +// C_MX2b/D/// x36y66 80'h00_F600_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1014_1 ( .OUT(na1014_1_i), .IN1(1'b1), .IN2(na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3416_2), .IN8(na1597_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1014_2 ( .OUT(na1014_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1014_1_i) ); +// C_MX2b/D/// x40y75 80'h00_F600_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1015_1 ( .OUT(na1015_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b0), .IN4(1'b0), .IN5(na2714_1), .IN6(na4562_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1015_2 ( .OUT(na1015_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1015_1_i) ); +// C_MX2b/D/// x41y82 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1016_1 ( .OUT(na1016_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1017_1), .IN8(na1792_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1016_2 ( .OUT(na1016_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1016_1_i) ); +// C_MX2b/D/// x42y81 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1017_1 ( .OUT(na1017_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1018_1), .IN8(na1784_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1017_2 ( .OUT(na1017_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1017_1_i) ); +// C_MX2b/D/// x40y79 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1018_1 ( .OUT(na1018_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1019_1), .IN8(na1784_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1018_2 ( .OUT(na1018_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1018_1_i) ); +// C_MX2b/D/// x50y87 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1019_1 ( .OUT(na1019_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1020_1), .IN8(na1786_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1019_2 ( .OUT(na1019_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1019_1_i) ); +// C_MX2b/D/// x46y81 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1020_1 ( .OUT(na1020_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1021_1), .IN8(na1786_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1020_2 ( .OUT(na1020_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1020_1_i) ); +// C_MX2b/D/// x48y81 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1021_1 ( .OUT(na1021_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1022_1), .IN8(na1788_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1021_2 ( .OUT(na1021_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1021_1_i) ); +// C_MX2b/D/// x44y77 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1022_1 ( .OUT(na1022_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1023_1), .IN8(na1788_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1022_2 ( .OUT(na1022_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1022_1_i) ); +// C_MX2b/D/// x48y77 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1023_1 ( .OUT(na1023_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1024_1), .IN8(na1790_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1023_2 ( .OUT(na1023_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1023_1_i) ); +// C_MX2b/D/// x40y77 80'h00_F600_00_0040_0AC4_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1024_1 ( .OUT(na1024_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1025_1), .IN8(na1790_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1024_2 ( .OUT(na1024_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1024_1_i) ); +// C_MX2b//// x38y75 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1025_1 ( .OUT(na1025_1), .IN1(1'b1), .IN2(~na4551_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na2714_1), .IN6(~na1005_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x50y85 80'h00_FE00_00_0040_0C0A_3F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1026_1 ( .OUT(na1026_1_i), .IN1(1'b0), .IN2(na1029_1), .IN3(1'b0), .IN4(na1027_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(~na1028_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1026_2 ( .OUT(na1026_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1026_1_i) ); +// C_MX2b//// x48y82 80'h00_0018_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1027_1 ( .OUT(na1027_1), .IN1(na218_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1026_1), .IN8(na1786_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x46y86 80'h00_0018_00_0000_0C88_88FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1028_1 ( .OUT(na1028_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2712_2), .IN6(na232_1), .IN7(na2713_1), .IN8(na2707_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x47y82 80'h00_FE00_00_0040_0C05_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1029_1 ( .OUT(na1029_1_i), .IN1(na1030_1), .IN2(1'b0), .IN3(na1031_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na1028_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1029_2 ( .OUT(na1029_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1029_1_i) ); +// C_MX2b//// x49y79 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1030_1 ( .OUT(na1030_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4135_2), .IN5(1'b0), .IN6(na1029_1), .IN7(1'b0), .IN8(na1788_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x50y81 80'h00_FE00_00_0040_0C05_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1031_1 ( .OUT(na1031_1_i), .IN1(na1032_1), .IN2(1'b0), .IN3(na1033_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na1028_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1031_2 ( .OUT(na1031_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1031_1_i) ); +// C_MX2b//// x49y81 80'h00_0018_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1032_1 ( .OUT(na1032_1), .IN1(na218_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1031_1), .IN8(na1788_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x48y83 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1033_1 ( .OUT(na1033_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1028_1), .IN5(na1034_1), .IN6(1'b0), .IN7(na1035_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1033_2 ( .OUT(na1033_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1033_1_i) ); +// C_MX2b//// x47y77 80'h00_0018_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1034_1 ( .OUT(na1034_1), .IN1(na218_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1033_1), .IN8(na1790_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x48y79 80'h00_FE00_00_0040_0AC0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1035_1 ( .OUT(na1035_1_i), .IN1(na218_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1028_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1035_1), + .IN8(na1790_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1035_2 ( .OUT(na1035_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1035_1_i) ); +// C_MX4b/D/// x35y75 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1036_1 ( .OUT(na1036_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1036_1), .IN6(na66_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1036_2 ( .OUT(na1036_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1036_1_i) ); +// C_MX4b////D x39y89 80'h00_FA18_00_0040_0AF4_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1037_1 ( .OUT(na1037_1), .IN1(1'b1), .IN2(na4338_2), .IN3(1'b1), .IN4(~na993_1), .IN5(na1510_1), .IN6(na4339_2), .IN7(~na1043_1), + .IN8(na4450_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1037_5 ( .OUT(na1037_2), .CLK(na1739_1), .EN(na232_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1037_1) ); +// C_MX2a//// x36y85 80'h00_0018_00_0040_0C03_0500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1038_1 ( .OUT(na1038_1), .IN1(na1042_1), .IN2(na3701_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na2712_1), .IN6(1'b1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x40y80 80'h00_0018_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1039_1 ( .OUT(na1039_1), .IN1(~na1040_2), .IN2(1'b1), .IN3(na4141_2), .IN4(1'b1), .IN5(na1000_1), .IN6(na1005_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x45y83 80'h00_0060_00_0000_0C08_FF12 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1040_4 ( .OUT(na1040_2), .IN1(na2712_1), .IN2(~na4550_2), .IN3(~na2713_2), .IN4(~na2710_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x41y63 80'h00_0018_00_0040_0ACC_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1042_1 ( .OUT(na1042_1), .IN1(~na399_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na3424_1), .IN8(~na871_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x42y89 80'h00_0018_00_0000_0C88_BCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1043_1 ( .OUT(na1043_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na232_2), .IN7(na3703_1), .IN8(~na2707_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ANDXOR////D x49y92 80'h00_FA18_00_0000_0666_F3B5 +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a1044_1 ( .OUT(na1044_1), .IN1(na1045_2), .IN2(1'b1), .IN3(~na3706_1), .IN4(na993_1), .IN5(1'b1), .IN6(na1504_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1044_5 ( .OUT(na1044_2), .CLK(na1739_1), .EN(na1503_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1044_1) ); +// C_///AND/ x49y87 80'h00_0060_00_0000_0C08_FF31 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1045_4 ( .OUT(na1045_2), .IN1(~na2712_2), .IN2(~na3701_2), .IN3(1'b1), .IN4(~na1046_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x38y88 80'h00_0018_00_0000_0888_9FAC +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a1046_1 ( .OUT(na1046_1), .IN1(1'b0), .IN2(~na1047_1), .IN3(~na2713_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2713_2), + .IN8(na2710_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x35y92 80'h00_0018_00_0000_0C88_4CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1047_1 ( .OUT(na1047_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1048_1), .IN7(~na432_2), .IN8(na239_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x33y92 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1048_1 ( .OUT(na1048_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na434_2), .IN6(1'b1), .IN7(~na4199_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x40y84 80'h00_0018_00_0000_0C88_DCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1049_1 ( .OUT(na1049_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na4334_2), .IN7(~na2713_1), .IN8(na3707_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x48y92 80'h00_F600_00_0040_0C0A_2F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1050_1 ( .OUT(na1050_1_i), .IN1(1'b0), .IN2(na1044_1), .IN3(1'b0), .IN4(na2739_1), .IN5(1'b1), .IN6(1'b1), .IN7(na226_1), + .IN8(~na1347_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1050_2 ( .OUT(na1050_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1050_1_i) ); +// C_ANDXOR/D//AND/D x29y92 80'h00_FA00_80_0000_0C68_EAFC +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a1051_1 ( .OUT(na1051_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na4337_2), .IN6(1'b1), .IN7(~na3708_2), + .IN8(~na2707_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1051_2 ( .OUT(na1051_1), .CLK(na1739_1), .EN(na1501_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1051_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1051_4 ( .OUT(na1051_2_i), .IN1(1'b1), .IN2(na1051_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1051_5 ( .OUT(na1051_2), .CLK(na1739_1), .EN(na1501_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1051_2_i) ); +// C_ORAND*/D//ORAND*/D x59y72 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1052_1 ( .OUT(na1052_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4341_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na2840_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1052_2 ( .OUT(na1052_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1052_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1052_4 ( .OUT(na1052_2_i), .IN1(~na1054_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na2840_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1052_5 ( .OUT(na1052_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1052_2_i) ); +// C_ORAND*/D//ORAND*/D x57y71 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1054_1 ( .OUT(na1054_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1054_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na2842_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1054_2 ( .OUT(na1054_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1054_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1054_4 ( .OUT(na1054_2_i), .IN1(~na1056_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na2842_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1054_5 ( .OUT(na1054_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1054_2_i) ); +// C_ORAND*/D//ORAND*/D x57y75 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1056_1 ( .OUT(na1056_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1056_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na2844_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1056_2 ( .OUT(na1056_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1056_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1056_4 ( .OUT(na1056_2_i), .IN1(~na4342_2), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na2844_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1056_5 ( .OUT(na1056_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1056_2_i) ); +// C_ORAND*/D//ORAND*/D x56y75 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1058_1 ( .OUT(na1058_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4343_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na2846_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1058_2 ( .OUT(na1058_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1058_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1058_4 ( .OUT(na1058_2_i), .IN1(~na1060_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na2846_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1058_5 ( .OUT(na1058_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1058_2_i) ); +// C_ORAND*/D//ORAND*/D x57y79 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1060_1 ( .OUT(na1060_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1060_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1780_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1060_2 ( .OUT(na1060_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1060_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1060_4 ( .OUT(na1060_2_i), .IN1(~na1062_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1780_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1060_5 ( .OUT(na1060_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1060_2_i) ); +// C_ORAND*/D//ORAND*/D x55y79 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1062_1 ( .OUT(na1062_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1062_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1782_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1062_2 ( .OUT(na1062_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1062_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1062_4 ( .OUT(na1062_2_i), .IN1(~na1064_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1782_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1062_5 ( .OUT(na1062_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1062_2_i) ); +// C_ORAND*/D//ORAND*/D x55y81 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1064_1 ( .OUT(na1064_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1784_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1064_2 ( .OUT(na1064_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1064_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1064_4 ( .OUT(na1064_2_i), .IN1(~na1066_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1784_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1064_5 ( .OUT(na1064_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1064_2_i) ); +// C_ORAND*/D//ORAND*/D x53y81 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1066_1 ( .OUT(na1066_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1066_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1786_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1066_2 ( .OUT(na1066_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1066_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1066_4 ( .OUT(na1066_2_i), .IN1(~na1068_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1786_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1066_5 ( .OUT(na1066_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1066_2_i) ); +// C_ORAND*/D//ORAND*/D x61y79 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1068_1 ( .OUT(na1068_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1068_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1788_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1068_2 ( .OUT(na1068_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1068_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1068_4 ( .OUT(na1068_2_i), .IN1(~na1070_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1788_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1068_5 ( .OUT(na1068_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1068_2_i) ); +// C_ORAND*/D//ORAND*/D x59y79 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1070_1 ( .OUT(na1070_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1070_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1790_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1070_2 ( .OUT(na1070_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1070_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1070_4 ( .OUT(na1070_2_i), .IN1(~na1072_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1790_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1070_5 ( .OUT(na1070_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1070_2_i) ); +// C_ORAND*/D//ORAND*/D x57y81 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1072_1 ( .OUT(na1072_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1072_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1792_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1072_2 ( .OUT(na1072_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1072_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1072_4 ( .OUT(na1072_2_i), .IN1(~na1074_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1792_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1072_5 ( .OUT(na1072_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1072_2_i) ); +// C_ORAND*/D//ORAND*/D x57y77 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1074_1 ( .OUT(na1074_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1074_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na1794_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1074_2 ( .OUT(na1074_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1074_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1074_4 ( .OUT(na1074_2_i), .IN1(~na1076_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na1794_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1074_5 ( .OUT(na1074_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1074_2_i) ); +// C_ORAND*/D//ORAND*/D x55y71 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1076_1 ( .OUT(na1076_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1076_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na4594_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1076_2 ( .OUT(na1076_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1076_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1076_4 ( .OUT(na1076_2_i), .IN1(~na1078_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na4593_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1076_5 ( .OUT(na1076_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1076_2_i) ); +// C_ORAND*/D//ORAND*/D x55y69 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1078_1 ( .OUT(na1078_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1078_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na3421_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1078_2 ( .OUT(na1078_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1078_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1078_4 ( .OUT(na1078_2_i), .IN1(~na4361_2), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na3420_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1078_5 ( .OUT(na1078_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1078_2_i) ); +// C_ORAND*/D//ORAND*/D x56y72 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1080_1 ( .OUT(na1080_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4362_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na4592_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1080_2 ( .OUT(na1080_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1080_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1080_4 ( .OUT(na1080_2_i), .IN1(~na1082_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na4591_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1080_5 ( .OUT(na1080_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1080_2_i) ); +// C_ORAND*/D//ORAND*/D x51y71 80'h00_F600_80_0000_0387_777B +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1082_1 ( .OUT(na1082_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1082_2), .IN6(~na223_2), .IN7(~na224_1), + .IN8(~na3414_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1082_2 ( .OUT(na1082_1), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1082_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1082_4 ( .OUT(na1082_2_i), .IN1(na1042_1), .IN2(~na223_2), .IN3(~na224_1), .IN4(~na3413_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1082_5 ( .OUT(na1082_2), .CLK(na1739_1), .EN(~na1401_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1082_2_i) ); +// C_///ORAND/ x60y87 80'h00_0060_00_0000_0C08_FF3E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1084_4 ( .OUT(na1084_2), .IN1(na434_1), .IN2(na3775_2), .IN3(1'b0), .IN4(~na2707_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D/// x58y82 80'h00_FE00_00_0000_0C88_5EFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1085_1 ( .OUT(na1085_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1086_1), .IN6(na3777_2), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1085_2 ( .OUT(na1085_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1085_1_i) ); +// C_MX4a//// x61y75 80'h00_0018_00_0040_0C82_CA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1086_1 ( .OUT(na1086_1), .IN1(1'b0), .IN2(na3778_1), .IN3(1'b0), .IN4(1'b1), .IN5(na1089_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1990_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x67y74 80'h00_0018_00_0040_0CCC_F100 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1087_1 ( .OUT(na1087_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na511_1), .IN4(~na1088_1), .IN5(~na4483_2), .IN6(~na1986_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x64y66 80'h00_0018_00_0000_0C88_C6FF +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a1088_1 ( .OUT(na1088_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na535_1), .IN6(~na512_1), .IN7(1'b0), .IN8(~na1443_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x67y77 80'h00_0060_00_0000_0C08_FF28 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1089_4 ( .OUT(na1089_2), .IN1(na4101_2), .IN2(na1993_2), .IN3(na38_2), .IN4(~na1990_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x62y72 80'h00_FE00_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1090_1 ( .OUT(na1090_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4101_2), .IN6(1'b1), .IN7(na38_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1090_2 ( .OUT(na1090_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1090_1_i) ); +// C_///OR/D x41y70 80'h00_FE00_80_0000_0C0E_FF0D +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1091_4 ( .OUT(na1091_2_i), .IN1(~na3578_1), .IN2(na1092_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1091_5 ( .OUT(na1091_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1091_2_i) ); +// C_AND//// x43y86 80'h00_0018_00_0000_0888_53A2 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1092_1 ( .OUT(na1092_1), .IN1(na2712_1), .IN2(~na819_2), .IN3(na3146_1), .IN4(1'b1), .IN5(1'b1), .IN6(~na219_2), .IN7(~na1517_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x41y71 80'h00_FE00_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1093_1 ( .OUT(na1093_1_i), .IN1(1'b1), .IN2(na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na410_1), .IN6(na1543_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1093_2 ( .OUT(na1093_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1093_1_i) ); +// C_MX2b/D/// x43y72 80'h00_FE00_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1094_1 ( .OUT(na1094_1_i), .IN1(1'b1), .IN2(na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na4197_2), .IN6(na1543_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1094_2 ( .OUT(na1094_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1094_1_i) ); +// C_ORAND/D/// x37y68 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1095_1 ( .OUT(na1095_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3783_1), .IN6(~na817_1), .IN7(~na3782_1), + .IN8(~na2720_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1095_2 ( .OUT(na1095_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1095_1_i) ); +// C_///ORAND/D x39y68 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1097_4 ( .OUT(na1097_2_i), .IN1(~na3786_1), .IN2(~na817_1), .IN3(~na3782_1), .IN4(~na2721_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1097_5 ( .OUT(na1097_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1097_2_i) ); +// C_///ORAND/D x39y65 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1099_4 ( .OUT(na1099_2_i), .IN1(~na3789_1), .IN2(~na817_1), .IN3(~na3782_1), .IN4(~na2722_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1099_5 ( .OUT(na1099_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1099_2_i) ); +// C_///ORAND/D x37y68 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1101_4 ( .OUT(na1101_2_i), .IN1(~na3792_1), .IN2(~na817_1), .IN3(~na3782_1), .IN4(~na2723_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1101_5 ( .OUT(na1101_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1101_2_i) ); +// C_ORAND/D/// x35y59 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1103_1 ( .OUT(na1103_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3795_1), .IN6(~na817_1), .IN7(~na3782_1), + .IN8(~na2722_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1103_2 ( .OUT(na1103_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1103_1_i) ); +// C_MX2b/D/// x49y68 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1105_1 ( .OUT(na1105_1_i), .IN1(1'b1), .IN2(~na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3199_1), .IN6(na3796_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1105_2 ( .OUT(na1105_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1105_1_i) ); +// C_MX2b/D/// x49y65 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1106_1 ( .OUT(na1106_1_i), .IN1(1'b1), .IN2(~na817_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3200_1), .IN8(na3797_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1106_2 ( .OUT(na1106_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1106_1_i) ); +// C_MX2b/D/// x50y67 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1107_1 ( .OUT(na1107_1_i), .IN1(1'b1), .IN2(na817_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3798_2), .IN8(na3201_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1107_2 ( .OUT(na1107_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1107_1_i) ); +// C_MX2b/D/// x49y69 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1108_1 ( .OUT(na1108_1_i), .IN1(1'b1), .IN2(na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3799_2), .IN6(na3202_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1108_2 ( .OUT(na1108_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1108_1_i) ); +// C_MX2b/D/// x45y68 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1109_1 ( .OUT(na1109_1_i), .IN1(1'b1), .IN2(na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3800_1), .IN6(na3203_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1109_2 ( .OUT(na1109_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1109_1_i) ); +// C_MX2b/D/// x43y64 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1110_1 ( .OUT(na1110_1_i), .IN1(1'b1), .IN2(na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3801_1), .IN6(na3204_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1110_2 ( .OUT(na1110_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1110_1_i) ); +// C_MX2b/D/// x46y69 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1111_1 ( .OUT(na1111_1_i), .IN1(1'b1), .IN2(na817_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3802_1), .IN8(na3205_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1111_2 ( .OUT(na1111_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1111_1_i) ); +// C_ORAND*////D x49y90 80'h00_FE18_00_0000_0788_5DD5 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1112_1 ( .OUT(na1112_1), .IN1(~na1118_1), .IN2(1'b0), .IN3(~na226_1), .IN4(na3804_1), .IN5(~na1118_2), .IN6(na1129_1), .IN7(~na226_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1112_5 ( .OUT(na1112_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1112_1) ); +// C_AND///AND/ x44y92 80'h00_0078_00_0000_0C88_123C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1113_1 ( .OUT(na1113_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3805_2), .IN6(~na2706_1), .IN7(~na4548_2), + .IN8(~na2707_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1113_4 ( .OUT(na1113_2), .IN1(1'b1), .IN2(na2706_1), .IN3(1'b1), .IN4(~na2707_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ANDXOR//// x35y85 80'h00_0018_00_0000_0C66_5B00 +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a1114_1 ( .OUT(na1114_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na4613_2), .IN6(na1115_2), .IN7(na1038_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y76 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1115_4 ( .OUT(na1115_2), .IN1(na2712_1), .IN2(1'b1), .IN3(na2705_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x35y87 80'h00_0078_00_0000_0C88_8A51 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1118_1 ( .OUT(na1118_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3809_1), .IN6(1'b1), .IN7(na3815_2), .IN8(na1337_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1118_4 ( .OUT(na1118_2), .IN1(~na2712_2), .IN2(~na4553_2), .IN3(~na2713_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x33y89 80'h00_0060_00_0000_0C08_FFBA +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1120_4 ( .OUT(na1120_2), .IN1(na1292_1), .IN2(1'b0), .IN3(na3811_2), .IN4(~na1121_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x38y84 80'h00_0018_00_0040_0C61_CC00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1121_1 ( .OUT(na1121_1), .IN1(na2712_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b0), .IN5(1'b1), .IN6(na4553_2), .IN7(1'b1), .IN8(na2710_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x38y91 80'h00_0060_00_0000_0C08_FFB5 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1122_4 ( .OUT(na1122_2), .IN1(~na3812_1), .IN2(1'b0), .IN3(na3815_2), .IN4(~na2739_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x34y92 80'h00_0060_00_0000_0C06_FFC6 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a1127_4 ( .OUT(na1127_2), .IN1(na1292_1), .IN2(na1506_1), .IN3(1'b0), .IN4(na1128_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x36y90 80'h00_0060_00_0000_0C08_FF4C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1128_4 ( .OUT(na1128_2), .IN1(1'b1), .IN2(na1048_1), .IN3(~na432_2), .IN4(na240_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x51y90 80'h00_0018_00_0040_0A55_0050 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1129_1 ( .OUT(na1129_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na1084_2), .IN4(1'b1), .IN5(~na3816_2), .IN6(1'b0), .IN7(~na1599_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x37y91 80'h00_0018_00_0000_0C66_CC00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1133_1 ( .OUT(na1133_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na391_2), .IN7(1'b0), .IN8(na2707_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x41y89 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1134_1 ( .OUT(na1134_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2707_1), .IN5(1'b0), .IN6(na3197_1), .IN7(1'b0), .IN8(na3198_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x48y69 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1135_1 ( .OUT(na1135_1_i), .IN1(1'b1), .IN2(~na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3206_1), .IN6(na3822_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1135_2 ( .OUT(na1135_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1135_1_i) ); +// C_MX2b//// x47y72 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1136_1 ( .OUT(na1136_1), .IN1(1'b1), .IN2(na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na4409_2), .IN6(na1543_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x50y71 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1137_1 ( .OUT(na1137_1), .IN1(1'b1), .IN2(na817_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na4408_2), .IN6(na1543_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x41y66 80'h00_0018_00_0000_0C88_37FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1138_1 ( .OUT(na1138_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3783_1), .IN6(~na817_1), .IN7(1'b0), .IN8(~na1139_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x48y74 80'h00_0018_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1139_1 ( .OUT(na1139_1), .IN1(na399_1), .IN2(1'b1), .IN3(~na4293_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1026_1), + .IN8(na2715_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x39y68 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1140_1 ( .OUT(na1140_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3786_1), .IN6(~na817_1), .IN7(~na1141_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x48y73 80'h00_0018_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1141_1 ( .OUT(na1141_1), .IN1(~na399_1), .IN2(1'b1), .IN3(na4293_2), .IN4(1'b1), .IN5(na2716_1), .IN6(na1029_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x42y55 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1142_4 ( .OUT(na1142_2), .IN1(~na3789_1), .IN2(~na817_1), .IN3(~na1143_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x48y71 80'h00_0018_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1143_1 ( .OUT(na1143_1), .IN1(na399_1), .IN2(1'b1), .IN3(~na4293_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1031_1), + .IN8(na2717_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x51y72 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1144_4 ( .OUT(na1144_2), .IN1(~na3792_1), .IN2(~na817_1), .IN3(~na1145_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x44y71 80'h00_0018_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1145_1 ( .OUT(na1145_1), .IN1(na399_1), .IN2(1'b1), .IN3(~na4293_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1033_1), + .IN8(na2718_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x39y65 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1146_1 ( .OUT(na1146_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3795_1), .IN6(~na817_1), .IN7(~na1147_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x42y67 80'h00_0018_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1147_1 ( .OUT(na1147_1), .IN1(na399_1), .IN2(1'b1), .IN3(~na4293_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1035_1), + .IN8(na2719_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x25y71 80'h00_0060_00_0000_0C08_FF3C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1148_4 ( .OUT(na1148_2), .IN1(1'b1), .IN2(na405_2), .IN3(1'b1), .IN4(~na688_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND*/D//AND*/D x30y79 80'h00_FE00_80_0000_0387_F858 +C_AND #(.CPE_CFG (9'b1_0000_0000)) + _a1149_1 ( .OUT(na1149_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3220_1), .IN6(na3231_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1149_2 ( .OUT(na1149_1), .CLK(na1739_2), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1149_1_i) ); +C_AND #(.CPE_CFG (9'b1_1000_0000)) + _a1149_4 ( .OUT(na1149_2_i), .IN1(na3220_1), .IN2(na3231_2), .IN3(~na1149_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1149_5 ( .OUT(na1149_2), .CLK(na1739_2), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1149_2_i) ); +// C_MX2b/D/// x53y72 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1151_1 ( .OUT(na1151_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na3104_1), .IN7(1'b0), .IN8(na1152_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1151_2 ( .OUT(na1151_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1151_1_i) ); +// C_MX2b/D/// x44y72 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1152_1 ( .OUT(na1152_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1763_2), .IN7(1'b0), .IN8(na1153_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1152_2 ( .OUT(na1152_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1152_1_i) ); +// C_MX2b/D/// x44y62 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1153_1 ( .OUT(na1153_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1763_1), .IN7(1'b0), .IN8(na1154_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1153_2 ( .OUT(na1153_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1153_1_i) ); +// C_MX2b/D/// x42y70 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1154_1 ( .OUT(na1154_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1765_2), .IN7(1'b0), .IN8(na1155_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1154_2 ( .OUT(na1154_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1154_1_i) ); +// C_MX2b/D/// x42y68 80'h00_F600_00_0040_0A30_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1155_1 ( .OUT(na1155_1_i), .IN1(~na456_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na1161_1), .IN6(na1765_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1155_2 ( .OUT(na1155_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1155_1_i) ); +// C_MX2b/D/// x51y73 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1156_1 ( .OUT(na1156_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1775_2), .IN7(1'b0), .IN8(na1157_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1156_2 ( .OUT(na1156_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1156_1_i) ); +// C_MX2b/D/// x50y70 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1157_1 ( .OUT(na1157_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1775_1), .IN7(1'b0), .IN8(na1158_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1157_2 ( .OUT(na1157_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1157_1_i) ); +// C_MX2b/D/// x48y70 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1158_1 ( .OUT(na1158_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1777_2), .IN7(1'b0), .IN8(na1159_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1158_2 ( .OUT(na1158_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1158_1_i) ); +// C_MX2b/D/// x44y64 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1159_1 ( .OUT(na1159_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1777_1), .IN7(1'b0), .IN8(na1160_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1159_2 ( .OUT(na1159_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1159_1_i) ); +// C_MX2b/D/// x44y54 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1160_1 ( .OUT(na1160_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4205_2), .IN5(na1161_1), .IN6(1'b0), .IN7(na3444_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1160_2 ( .OUT(na1160_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1160_1_i) ); +// C_MX2b/D/// x41y53 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1161_1 ( .OUT(na1161_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4205_2), .IN5(na1162_1), .IN6(1'b0), .IN7(na3443_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1161_2 ( .OUT(na1161_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1161_1_i) ); +// C_MX2b/D/// x43y53 80'h00_F600_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1162_1 ( .OUT(na1162_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4205_2), .IN5(1'b0), .IN6(na1163_1), .IN7(1'b0), .IN8(na3442_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1162_2 ( .OUT(na1162_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1162_1_i) ); +// C_MX2b/D/// x45y54 80'h00_F600_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1163_1 ( .OUT(na1163_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4205_2), .IN5(1'b0), .IN6(na1164_1), .IN7(1'b0), .IN8(na3439_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1163_2 ( .OUT(na1163_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1163_1_i) ); +// C_MX2b/D/// x43y54 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1164_1 ( .OUT(na1164_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4205_2), .IN5(na1165_1), .IN6(1'b0), .IN7(na3430_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1164_2 ( .OUT(na1164_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1164_1_i) ); +// C_MX2b/D/// x43y55 80'h00_F600_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1165_1 ( .OUT(na1165_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4205_2), .IN5(na1603_1), .IN6(1'b0), .IN7(na3429_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1165_2 ( .OUT(na1165_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1165_1_i) ); +// C_MX2b/D/// x59y78 80'h00_F600_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1166_1 ( .OUT(na1166_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4205_2), .IN5(1'b0), .IN6(na2965_1), .IN7(1'b0), .IN8(na4580_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1166_2 ( .OUT(na1166_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1166_1_i) ); +// C_MX2b/D/// x56y80 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1167_1 ( .OUT(na1167_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1775_2), .IN7(1'b0), .IN8(na1168_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1167_2 ( .OUT(na1167_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1167_1_i) ); +// C_MX2b/D/// x54y72 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1168_1 ( .OUT(na1168_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1767_2), .IN7(1'b0), .IN8(na1169_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1168_2 ( .OUT(na1168_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1168_1_i) ); +// C_MX2b/D/// x52y72 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1169_1 ( .OUT(na1169_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1767_1), .IN7(1'b0), .IN8(na1170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1169_2 ( .OUT(na1169_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1169_1_i) ); +// C_MX2b/D/// x54y70 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1170_1 ( .OUT(na1170_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1769_2), .IN7(1'b0), .IN8(na1171_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1170_2 ( .OUT(na1170_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1170_1_i) ); +// C_MX2b/D/// x50y74 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1171_1 ( .OUT(na1171_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1769_1), .IN7(1'b0), .IN8(na1172_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1171_2 ( .OUT(na1171_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1171_1_i) ); +// C_MX2b/D/// x50y66 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1172_1 ( .OUT(na1172_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1771_2), .IN7(1'b0), .IN8(na1173_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1172_2 ( .OUT(na1172_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1172_1_i) ); +// C_MX2b/D/// x48y64 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1173_1 ( .OUT(na1173_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1771_1), .IN7(1'b0), .IN8(na1174_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1173_2 ( .OUT(na1173_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1173_1_i) ); +// C_MX2b/D/// x52y74 80'h00_F600_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1174_1 ( .OUT(na1174_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1773_2), .IN7(1'b0), .IN8(na1175_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1174_2 ( .OUT(na1174_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1174_1_i) ); +// C_MX2b/D/// x50y76 80'h00_F600_00_0040_0AA8_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1175_1 ( .OUT(na1175_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b0), .IN6(na1773_1), .IN7(1'b0), .IN8(~na1176_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1175_2 ( .OUT(na1175_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1175_1_i) ); +// C_MX2b//// x54y82 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1176_1 ( .OUT(na1176_1), .IN1(1'b1), .IN2(na2965_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na1156_1), .IN6(~na2965_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x31y67 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1177_1 ( .OUT(na1177_1_i), .IN1(1'b1), .IN2(~na4369_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1180_1), .IN6(na1178_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1177_2 ( .OUT(na1177_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1177_1_i) ); +// C_MX2b//// x35y66 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1178_1 ( .OUT(na1178_1), .IN1(na436_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na1177_1), .IN6(na1769_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x44y76 80'h00_0018_00_0000_0C88_88FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1179_1 ( .OUT(na1179_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2962_1), .IN6(na2965_2), .IN7(na2958_2), + .IN8(na4205_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x27y65 80'h00_FE00_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1180_1 ( .OUT(na1180_1_i), .IN1(1'b1), .IN2(na4369_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1181_1), .IN8(na1182_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1180_2 ( .OUT(na1180_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1180_1_i) ); +// C_MX2b//// x32y65 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1181_1 ( .OUT(na1181_1), .IN1(na436_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na1180_1), .IN6(na1771_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x28y68 80'h00_FE00_00_0040_0C0A_3F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1182_1 ( .OUT(na1182_1_i), .IN1(1'b0), .IN2(na1184_1), .IN3(1'b0), .IN4(na1183_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(~na1179_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1182_2 ( .OUT(na1182_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1182_1_i) ); +// C_MX2b//// x32y66 80'h00_0018_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1183_1 ( .OUT(na1183_1), .IN1(~na436_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4475_2), .IN8(na1182_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x27y66 80'h00_FE00_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1184_1 ( .OUT(na1184_1_i), .IN1(1'b1), .IN2(~na4369_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1186_1), .IN8(na1185_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1184_2 ( .OUT(na1184_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1184_1_i) ); +// C_MX2b//// x34y66 80'h00_0018_00_0040_0A30_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1185_1 ( .OUT(na1185_1), .IN1(~na436_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na4477_2), .IN6(na1184_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x30y65 80'h00_FE00_00_0040_0AC0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1186_1 ( .OUT(na1186_1_i), .IN1(na436_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1179_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1186_1), + .IN8(na4476_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1186_2 ( .OUT(na1186_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1186_1_i) ); +// C_MX4b/D/// x37y77 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1187_1 ( .OUT(na1187_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1187_1), .IN6(na30_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1187_2 ( .OUT(na1187_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1187_1_i) ); +// C_MX4b/D/// x33y77 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1188_1 ( .OUT(na1188_1_i), .IN1(na1191_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1188_1), .IN6(na3943_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1188_2 ( .OUT(na1188_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1188_1_i) ); +// C_MX4a//// x29y79 80'h00_0018_00_0040_0C18_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1191_1 ( .OUT(na1191_1), .IN1(1'b1), .IN2(1'b0), .IN3(1'b0), .IN4(na1296_1), .IN5(na4400_2), .IN6(1'b1), .IN7(~na287_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ANDXOR////D x59y87 80'h00_FA18_00_0000_0666_3FB5 +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a1192_1 ( .OUT(na1192_1), .IN1(na1193_1), .IN2(1'b1), .IN3(~na3826_1), .IN4(na1388_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na1526_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1192_5 ( .OUT(na1192_2), .CLK(na1739_1), .EN(na1525_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1192_1) ); +// C_AND//// x63y87 80'h00_0018_00_0000_0C88_31FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1193_1 ( .OUT(na1193_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2962_1), .IN6(~na4589_2), .IN7(1'b1), .IN8(~na1194_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ICOMP//// x58y84 80'h00_0018_00_0000_0888_F9CC +C_ICOMP #(.CPE_CFG (9'b0_0000_0000)) + _a1194_1 ( .OUT(na1194_1), .IN1(1'b0), .IN2(~na2965_2), .IN3(1'b0), .IN4(~na1195_2), .IN5(na2962_2), .IN6(na4567_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x68y90 80'h00_0060_00_0000_0C08_FF4C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1195_4 ( .OUT(na1195_2), .IN1(1'b1), .IN2(na1196_1), .IN3(~na980_2), .IN4(na1322_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x59y92 80'h00_0018_00_0000_0C88_33FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1196_1 ( .OUT(na1196_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na4333_2), .IN7(1'b1), .IN8(~na986_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x61y85 80'h00_0018_00_0000_0C88_CBFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1197_1 ( .OUT(na1197_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3827_1), .IN6(~na2965_2), .IN7(1'b0), .IN8(na1388_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x46y83 80'h00_F600_00_0040_0C05_4000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1198_1 ( .OUT(na1198_1_i), .IN1(na1192_1), .IN2(1'b0), .IN3(na2984_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na443_1), + .IN8(na450_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1198_2 ( .OUT(na1198_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1198_1_i) ); +// C_ANDXOR/D//AND/D x65y89 80'h00_FA00_80_0000_0C68_EAFA +C_ANDXOR #(.CPE_CFG (9'b0_0000_0000)) + _a1199_1 ( .OUT(na1199_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na4208_2), .IN6(1'b1), .IN7(~na2958_2), + .IN8(~na4627_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1199_2 ( .OUT(na1199_1), .CLK(na1739_1), .EN(na1523_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1199_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1199_4 ( .OUT(na1199_2_i), .IN1(na1199_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1199_5 ( .OUT(na1199_2), .CLK(na1739_1), .EN(na1523_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1199_2_i) ); +// C_ORAND*/D//ORAND*/D x41y59 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1200_1 ( .OUT(na1200_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na3098_2), .IN7(~na446_2), + .IN8(~na4374_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1200_2 ( .OUT(na1200_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1200_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1200_4 ( .OUT(na1200_2_i), .IN1(~na447_2), .IN2(~na3098_1), .IN3(~na446_2), .IN4(~na1202_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1200_5 ( .OUT(na1200_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1200_2_i) ); +// C_ORAND*/D//ORAND*/D x42y60 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1202_1 ( .OUT(na1202_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na3100_2), .IN7(~na446_2), + .IN8(~na1202_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1202_2 ( .OUT(na1202_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1202_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1202_4 ( .OUT(na1202_2_i), .IN1(~na447_2), .IN2(~na3100_1), .IN3(~na446_2), .IN4(~na4377_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1202_5 ( .OUT(na1202_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1202_2_i) ); +// C_ORAND*/D//ORAND*/D x41y62 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1204_1 ( .OUT(na1204_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na3102_2), .IN7(~na446_2), + .IN8(~na4378_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1204_2 ( .OUT(na1204_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1204_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1204_4 ( .OUT(na1204_2_i), .IN1(~na447_2), .IN2(~na3102_1), .IN3(~na446_2), .IN4(~na1206_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1204_5 ( .OUT(na1204_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1204_2_i) ); +// C_ORAND*/D//ORAND*/D x42y64 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1206_1 ( .OUT(na1206_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na3104_2), .IN7(~na446_2), + .IN8(~na1206_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1206_2 ( .OUT(na1206_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1206_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1206_4 ( .OUT(na1206_2_i), .IN1(~na447_2), .IN2(~na3104_1), .IN3(~na446_2), .IN4(~na1208_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1206_5 ( .OUT(na1206_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1206_2_i) ); +// C_ORAND*/D//ORAND*/D x38y66 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1208_1 ( .OUT(na1208_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1763_2), .IN7(~na446_2), + .IN8(~na1208_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1208_2 ( .OUT(na1208_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1208_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1208_4 ( .OUT(na1208_2_i), .IN1(~na447_2), .IN2(~na1763_1), .IN3(~na446_2), .IN4(~na4381_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1208_5 ( .OUT(na1208_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1208_2_i) ); +// C_ORAND*/D//ORAND*/D x31y63 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1210_1 ( .OUT(na1210_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1765_2), .IN7(~na446_2), + .IN8(~na4382_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1210_2 ( .OUT(na1210_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1210_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1210_4 ( .OUT(na1210_2_i), .IN1(~na447_2), .IN2(~na1765_1), .IN3(~na446_2), .IN4(~na1212_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1210_5 ( .OUT(na1210_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1210_2_i) ); +// C_ORAND*/D//ORAND*/D x40y64 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1212_1 ( .OUT(na1212_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1767_2), .IN7(~na446_2), + .IN8(~na1212_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1212_2 ( .OUT(na1212_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1212_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1212_4 ( .OUT(na1212_2_i), .IN1(~na447_2), .IN2(~na1767_1), .IN3(~na446_2), .IN4(~na1214_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1212_5 ( .OUT(na1212_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1212_2_i) ); +// C_ORAND*/D//ORAND*/D x40y62 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1214_1 ( .OUT(na1214_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1769_2), .IN7(~na446_2), + .IN8(~na1214_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1214_2 ( .OUT(na1214_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1214_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1214_4 ( .OUT(na1214_2_i), .IN1(~na447_2), .IN2(~na1769_1), .IN3(~na446_2), .IN4(~na1216_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1214_5 ( .OUT(na1214_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1214_2_i) ); +// C_ORAND*/D//ORAND*/D x38y64 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1216_1 ( .OUT(na1216_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1771_2), .IN7(~na446_2), + .IN8(~na1216_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1216_2 ( .OUT(na1216_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1216_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1216_4 ( .OUT(na1216_2_i), .IN1(~na447_2), .IN2(~na1771_1), .IN3(~na446_2), .IN4(~na1218_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1216_5 ( .OUT(na1216_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1216_2_i) ); +// C_ORAND*/D//ORAND*/D x34y64 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1218_1 ( .OUT(na1218_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1773_2), .IN7(~na446_2), + .IN8(~na1218_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1218_2 ( .OUT(na1218_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1218_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1218_4 ( .OUT(na1218_2_i), .IN1(~na447_2), .IN2(~na1773_1), .IN3(~na446_2), .IN4(~na1220_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1218_5 ( .OUT(na1218_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1218_2_i) ); +// C_ORAND*/D//ORAND*/D x36y64 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1220_1 ( .OUT(na1220_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1775_2), .IN7(~na446_2), + .IN8(~na1220_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1220_2 ( .OUT(na1220_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1220_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1220_4 ( .OUT(na1220_2_i), .IN1(~na447_2), .IN2(~na1775_1), .IN3(~na446_2), .IN4(~na1222_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1220_5 ( .OUT(na1220_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1220_2_i) ); +// C_ORAND*/D//ORAND*/D x34y62 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1222_1 ( .OUT(na1222_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na1777_2), .IN7(~na446_2), + .IN8(~na1222_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1222_2 ( .OUT(na1222_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1222_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1222_4 ( .OUT(na1222_2_i), .IN1(~na447_2), .IN2(~na1777_1), .IN3(~na446_2), .IN4(~na1224_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1222_5 ( .OUT(na1222_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1222_2_i) ); +// C_ORAND*/D//ORAND*/D x36y58 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1224_1 ( .OUT(na1224_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na4602_2), .IN7(~na446_2), + .IN8(~na1224_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1224_2 ( .OUT(na1224_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1224_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1224_4 ( .OUT(na1224_2_i), .IN1(~na447_2), .IN2(~na4601_2), .IN3(~na446_2), .IN4(~na4392_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1224_5 ( .OUT(na1224_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1224_2_i) ); +// C_ORAND*/D//ORAND*/D x36y57 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1226_1 ( .OUT(na1226_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na4600_2), .IN7(~na446_2), + .IN8(~na4393_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1226_2 ( .OUT(na1226_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1226_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1226_4 ( .OUT(na1226_2_i), .IN1(~na447_2), .IN2(~na4599_2), .IN3(~na446_2), .IN4(~na1228_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1226_5 ( .OUT(na1226_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1226_2_i) ); +// C_ORAND*/D//ORAND*/D x36y56 80'h00_F600_80_0000_0387_7777 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1228_1 ( .OUT(na1228_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na4598_2), .IN7(~na446_2), + .IN8(~na1228_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1228_2 ( .OUT(na1228_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1228_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1228_4 ( .OUT(na1228_2_i), .IN1(~na447_2), .IN2(~na4597_2), .IN3(~na446_2), .IN4(~na4396_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1228_5 ( .OUT(na1228_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1228_2_i) ); +// C_ORAND*/D//ORAND*/D x35y53 80'h00_F600_80_0000_0387_77D7 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1230_1 ( .OUT(na1230_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na447_2), .IN6(~na4596_2), .IN7(~na446_2), + .IN8(~na4397_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1230_2 ( .OUT(na1230_1), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1230_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1230_4 ( .OUT(na1230_2_i), .IN1(~na447_2), .IN2(~na4595_2), .IN3(~na446_2), .IN4(na4210_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1230_5 ( .OUT(na1230_2), .CLK(na1739_1), .EN(~na1399_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1230_2_i) ); +// C_///ORAND/ x66y87 80'h00_0060_00_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1232_4 ( .OUT(na1232_2), .IN1(na3895_1), .IN2(na4333_2), .IN3(~na2958_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR/D/// x32y61 80'h00_FE00_00_0000_0CEE_0D00 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1233_1 ( .OUT(na1233_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na4588_2), .IN6(na1234_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1233_2 ( .OUT(na1233_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1233_1_i) ); +// C_AND//// x35y70 80'h00_0018_00_0000_0888_32F2 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1234_1 ( .OUT(na1234_1), .IN1(na2963_2), .IN2(~na423_1), .IN3(1'b1), .IN4(1'b1), .IN5(na3145_1), .IN6(~na423_2), .IN7(1'b1), + .IN8(~na1539_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x27y60 80'h00_FE00_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1235_1 ( .OUT(na1235_1_i), .IN1(1'b1), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1302_1), .IN6(na1541_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1235_2 ( .OUT(na1235_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1235_1_i) ); +// C_MX2b/D/// x28y60 80'h00_FE00_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1236_1 ( .OUT(na1236_1_i), .IN1(1'b1), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1301_1), .IN6(na1541_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1236_2 ( .OUT(na1236_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1236_1_i) ); +// C_///ORAND/D x21y64 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1237_4 ( .OUT(na1237_2_i), .IN1(~na3899_1), .IN2(~na421_1), .IN3(~na3898_2), .IN4(~na2971_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1237_5 ( .OUT(na1237_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1237_2_i) ); +// C_ORAND/D/// x21y62 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1239_1 ( .OUT(na1239_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3902_1), .IN6(~na421_1), .IN7(~na2972_1), + .IN8(~na4628_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1239_2 ( .OUT(na1239_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1239_1_i) ); +// C_///ORAND/D x14y63 80'h00_FE00_80_0000_0C08_FF77 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1241_4 ( .OUT(na1241_2_i), .IN1(~na3905_1), .IN2(~na421_1), .IN3(~na3898_2), .IN4(~na4574_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1241_5 ( .OUT(na1241_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1241_2_i) ); +// C_ORAND/D/// x19y59 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1243_1 ( .OUT(na1243_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3908_1), .IN6(~na421_1), .IN7(~na3898_2), + .IN8(~na4576_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1243_2 ( .OUT(na1243_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1243_1_i) ); +// C_ORAND/D/// x21y64 80'h00_FE00_00_0000_0C88_77FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1245_1 ( .OUT(na1245_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3911_1), .IN6(~na421_1), .IN7(~na3898_2), + .IN8(~na4575_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1245_2 ( .OUT(na1245_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1245_1_i) ); +// C_MX2b/D/// x32y50 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1247_1 ( .OUT(na1247_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4194_2), .IN5(na3912_2), .IN6(1'b0), .IN7(na3209_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1247_2 ( .OUT(na1247_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1247_1_i) ); +// C_MX2b/D/// x33y50 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1248_1 ( .OUT(na1248_1_i), .IN1(1'b1), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3913_2), .IN6(na3210_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1248_2 ( .OUT(na1248_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1248_1_i) ); +// C_MX2b/D/// x31y54 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1249_1 ( .OUT(na1249_1_i), .IN1(1'b1), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3914_1), .IN6(na3211_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1249_2 ( .OUT(na1249_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1249_1_i) ); +// C_MX2b/D/// x33y51 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1250_1 ( .OUT(na1250_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4194_2), .IN5(na3915_1), .IN6(1'b0), .IN7(na3212_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1250_2 ( .OUT(na1250_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1250_1_i) ); +// C_MX2b/D/// x33y55 80'h00_FE00_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1251_1 ( .OUT(na1251_1_i), .IN1(1'b1), .IN2(~na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3213_1), .IN6(na3916_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1251_2 ( .OUT(na1251_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1251_1_i) ); +// C_MX2b/D/// x32y53 80'h00_FE00_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1252_1 ( .OUT(na1252_1_i), .IN1(1'b1), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(na3917_2), .IN6(na3214_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1252_2 ( .OUT(na1252_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1252_1_i) ); +// C_MX2b/D/// x34y58 80'h00_FE00_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1253_1 ( .OUT(na1253_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4194_2), .IN5(1'b0), .IN6(na3215_1), .IN7(1'b0), .IN8(na3918_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1253_2 ( .OUT(na1253_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1253_1_i) ); +// C_ORAND*////D x55y84 80'h00_FE18_00_0000_0788_3BB3 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1254_1 ( .OUT(na1254_1), .IN1(1'b0), .IN2(~na1260_1), .IN3(na3920_1), .IN4(~na450_1), .IN5(na1271_1), .IN6(~na1260_2), .IN7(1'b0), + .IN8(~na450_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1254_5 ( .OUT(na1254_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1254_1) ); +// C_AND///AND/ x67y87 80'h00_0078_00_0000_0C88_415A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1255_1 ( .OUT(na1255_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2957_2), .IN6(~na4566_2), .IN7(~na2958_1), + .IN8(na3921_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1255_4 ( .OUT(na1255_2), .IN1(na2957_2), .IN2(1'b1), .IN3(~na2958_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ANDXOR/ x69y84 80'h00_0060_00_0000_0C06_FF5B +C_ANDXOR #(.CPE_CFG (9'b0_1000_0000)) + _a1256_4 ( .OUT(na1256_2), .IN1(~na3828_1), .IN2(na1257_1), .IN3(na461_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x63y76 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1257_1 ( .OUT(na1257_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2956_1), .IN6(1'b1), .IN7(na4572_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x55y88 80'h00_0078_00_0000_0C88_8A31 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1260_1 ( .OUT(na1260_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3931_2), .IN6(1'b1), .IN7(na531_1), .IN8(na3925_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1260_4 ( .OUT(na1260_2), .IN1(~na2962_1), .IN2(~na2965_2), .IN3(1'b1), .IN4(~na4571_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x52y92 80'h00_0018_00_0000_0C88_CBFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1262_1 ( .OUT(na1262_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3927_2), .IN6(~na1263_1), .IN7(1'b0), .IN8(na532_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x59y90 80'h00_0018_00_0040_0C61_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1263_1 ( .OUT(na1263_1), .IN1(na2962_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b0), .IN5(na2962_2), .IN6(1'b1), .IN7(na2961_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x55y92 80'h00_0018_00_0000_0C88_D3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1264_1 ( .OUT(na1264_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na3928_1), .IN7(~na2984_1), .IN8(na4630_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x50y89 80'h00_0018_00_0000_0C66_C600 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1269_1 ( .OUT(na1269_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1270_2), .IN6(na1528_2), .IN7(1'b0), .IN8(na532_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y85 80'h00_0060_00_0000_0C08_FF58 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1270_4 ( .OUT(na1270_2), .IN1(na507_1), .IN2(na1196_1), .IN3(~na980_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x51y79 80'h00_0018_00_0040_0AAA_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1271_1 ( .OUT(na1271_1), .IN1(1'b1), .IN2(1'b1), .IN3(~na1232_2), .IN4(1'b1), .IN5(1'b0), .IN6(~na3932_1), .IN7(1'b0), .IN8(~na1605_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x65y88 80'h00_0018_00_0000_0C66_6000 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1275_1 ( .OUT(na1275_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2958_2), .IN8(na1306_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x66y84 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1276_1 ( .OUT(na1276_1), .IN1(1'b1), .IN2(na4564_2), .IN3(1'b0), .IN4(1'b0), .IN5(na3207_1), .IN6(na3208_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x34y55 80'h00_FE00_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1277_1 ( .OUT(na1277_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na4194_2), .IN5(na3938_1), .IN6(1'b0), .IN7(na3216_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1277_2 ( .OUT(na1277_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1277_1_i) ); +// C_MX2b//// x29y57 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1278_1 ( .OUT(na1278_1), .IN1(1'b1), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1304_2), .IN6(na1541_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x30y58 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1279_1 ( .OUT(na1279_1), .IN1(1'b1), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1304_1), .IN6(na1541_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x29y60 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1280_1 ( .OUT(na1280_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3899_1), .IN6(~na421_1), .IN7(~na1281_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x28y65 80'h00_0018_00_0040_0A30_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1281_1 ( .OUT(na1281_1), .IN1(na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(na4194_2), .IN5(na1177_1), .IN6(na2966_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x25y58 80'h00_0060_00_0000_0C08_FF37 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1282_4 ( .OUT(na1282_2), .IN1(~na3902_1), .IN2(~na421_1), .IN3(1'b0), .IN4(~na1283_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x30y64 80'h00_0018_00_0040_0A30_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1283_1 ( .OUT(na1283_1), .IN1(na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(na4194_2), .IN5(na1180_1), .IN6(na2967_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x25y64 80'h00_0060_00_0000_0C08_FF37 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1284_4 ( .OUT(na1284_2), .IN1(~na3905_1), .IN2(~na421_1), .IN3(1'b0), .IN4(~na1285_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x28y62 80'h00_0018_00_0040_0AC0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1285_1 ( .OUT(na1285_1), .IN1(~na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4194_2), .IN5(1'b0), .IN6(1'b0), .IN7(na2968_1), + .IN8(na1182_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x22y62 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1286_4 ( .OUT(na1286_2), .IN1(~na3908_1), .IN2(~na421_1), .IN3(~na1287_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x26y63 80'h00_0018_00_0040_0A30_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1287_1 ( .OUT(na1287_1), .IN1(~na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(na4194_2), .IN5(na2969_2), .IN6(na1184_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x25y64 80'h00_0018_00_0000_0C88_37FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1288_1 ( .OUT(na1288_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3911_1), .IN6(~na421_1), .IN7(1'b0), .IN8(~na1289_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x28y58 80'h00_0018_00_0040_0AC0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1289_1 ( .OUT(na1289_1), .IN1(na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4194_2), .IN5(1'b0), .IN6(1'b0), .IN7(na1186_1), + .IN8(na2970_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND/D/// x33y71 80'h00_FE00_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1290_1 ( .OUT(na1290_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3940_2), .IN6(~na3939_1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1290_2 ( .OUT(na1290_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1290_1_i) ); +// C_MX4b/D/// x31y89 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1292_1 ( .OUT(na1292_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1292_1), .IN6(na1293_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1292_2 ( .OUT(na1292_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1292_1_i) ); +// C_MX4b/D/// x29y84 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1293_1 ( .OUT(na1293_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1294_1), .IN6(na1293_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1293_2 ( .OUT(na1293_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1293_1_i) ); +// C_MX4b/D/// x31y81 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1294_1 ( .OUT(na1294_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1294_1), .IN6(na1338_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1294_2 ( .OUT(na1294_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1294_1_i) ); +// C_MX4b/D/// x27y79 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1295_1 ( .OUT(na1295_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1295_1), .IN6(na1298_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1295_2 ( .OUT(na1295_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1295_1_i) ); +// C_ORAND/D//ORAND/D x32y76 80'h00_FE00_80_0000_0C88_5E5E +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1296_1 ( .OUT(na1296_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3307_2), .IN6(na1297_1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1296_2 ( .OUT(na1296_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1296_1_i) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1296_4 ( .OUT(na1296_2_i), .IN1(na3944_2), .IN2(na4155_2), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1296_5 ( .OUT(na1296_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1296_2_i) ); +// C_MX4a//// x31y82 80'h00_0018_00_0040_0C29_5C00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1297_1 ( .OUT(na1297_1), .IN1(na4631_2), .IN2(1'b1), .IN3(1'b0), .IN4(na1296_2), .IN5(1'b1), .IN6(na3943_2), .IN7(~na287_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x25y80 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1298_1 ( .OUT(na1298_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1308_1), .IN6(na1298_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1298_2 ( .OUT(na1298_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1298_1_i) ); +// C_MX4b/D/// x25y67 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1301_1 ( .OUT(na1301_1_i), .IN1(1'b1), .IN2(na978_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1301_1), .IN6(na1660_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1301_2 ( .OUT(na1301_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1301_1_i) ); +// C_MX4b/D/// x27y67 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1302_1 ( .OUT(na1302_1_i), .IN1(1'b1), .IN2(na978_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1302_1), .IN6(na1660_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1302_2 ( .OUT(na1302_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1302_1_i) ); +// C_AND/D/// x16y62 80'h00_FE00_00_0000_0C88_A5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1303_1 ( .OUT(na1303_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na436_1), .IN6(1'b1), .IN7(na1653_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1303_2 ( .OUT(na1303_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1303_1_i) ); +// C_AND/D//AND/D x17y63 80'h00_FE00_80_0000_0C88_C5C5 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1304_1 ( .OUT(na1304_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na436_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1655_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1304_2 ( .OUT(na1304_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1304_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1304_4 ( .OUT(na1304_2_i), .IN1(~na436_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1655_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1304_5 ( .OUT(na1304_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1304_2_i) ); +// C_///AND/D x26y51 80'h00_FE00_80_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1305_4 ( .OUT(na1305_2_i), .IN1(na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(na3426_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1305_5 ( .OUT(na1305_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1305_2_i) ); +// C_AND/D//ORAND*/D x66y90 80'h00_FE00_80_0000_0C87_5AB3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1306_1 ( .OUT(na1306_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1637_1), .IN6(1'b1), .IN7(~na443_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1306_2 ( .OUT(na1306_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1306_1_i) ); +C_ORAND #(.CPE_CFG (9'b1_1000_0000)) + _a1306_4 ( .OUT(na1306_2_i), .IN1(1'b0), .IN2(~na4402_2), .IN3(na2958_2), .IN4(~na4457_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1306_5 ( .OUT(na1306_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1306_2_i) ); +// C_AND/D//AND/D x65y92 80'h00_FE00_80_0000_0C88_5C5C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1307_1 ( .OUT(na1307_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1635_2), .IN7(~na443_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1307_2 ( .OUT(na1307_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1307_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1307_4 ( .OUT(na1307_2_i), .IN1(1'b1), .IN2(na1635_1), .IN3(~na443_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1307_5 ( .OUT(na1307_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1307_2_i) ); +// C_MX4b/D/// x27y81 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1308_1 ( .OUT(na1308_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1308_1), .IN6(na1312_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1308_2 ( .OUT(na1308_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1308_1_i) ); +// C_MX4b/D/// x32y81 80'h00_FE00_00_0040_0AC8_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1309_1 ( .OUT(na1309_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1309_1), + .IN8(~na1310_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1309_2 ( .OUT(na1309_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1309_1_i) ); +// C_MX2b//// x48y88 80'h00_0018_00_0040_0ACC_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1310_1 ( .OUT(na1310_1), .IN1(na457_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1269_1), .IN8(~na1311_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x50y86 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1311_4 ( .OUT(na1311_2), .IN1(1'b1), .IN2(1'b1), .IN3(na531_1), .IN4(na3925_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x29y82 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1312_1 ( .OUT(na1312_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4403_2), .IN6(na1312_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1312_2 ( .OUT(na1312_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1312_1_i) ); +// C_MX4b/D/// x30y84 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1313_1 ( .OUT(na1313_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1336_1), + .IN8(na1313_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1313_2 ( .OUT(na1313_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1313_1_i) ); +// C_///ORAND/D x59y65 80'h00_FE00_80_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1314_4 ( .OUT(na1314_2_i), .IN1(na3948_1), .IN2(na1315_2), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1314_5 ( .OUT(na1314_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1314_2_i) ); +// C_///ORAND/ x31y68 80'h00_0060_00_0000_0C08_FFEC +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1315_4 ( .OUT(na1315_2), .IN1(1'b0), .IN2(na137_2), .IN3(na3950_2), .IN4(na420_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x14y73 80'h00_0018_00_0000_0C88_2FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1316_1 ( .OUT(na1316_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na318_1), .IN8(~na420_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x25y84 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1317_1 ( .OUT(na1317_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na727_1), .IN6(na1317_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1317_2 ( .OUT(na1317_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1317_1_i) ); +// C_MX4b/D/// x25y82 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1318_1 ( .OUT(na1318_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na692_1), .IN6(na1318_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1318_2 ( .OUT(na1318_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1318_1_i) ); +// C_MX4b/D/// x21y73 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1319_1 ( .OUT(na1319_1_i), .IN1(1'b1), .IN2(na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1319_1), .IN6(na640_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1319_2 ( .OUT(na1319_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1319_1_i) ); +// C_MX4b/D/// x19y74 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1320_1 ( .OUT(na1320_1_i), .IN1(1'b1), .IN2(~na424_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na4254_2), .IN6(na1320_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1320_2 ( .OUT(na1320_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1320_1_i) ); +// C_MX4b/D/// x51y88 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1321_1 ( .OUT(na1321_1_i), .IN1(na456_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4404_2), + .IN8(na1322_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1321_2 ( .OUT(na1321_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1321_1_i) ); +// C_MX4b/D/// x54y88 80'h00_FE00_00_0040_0AC3_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1322_1 ( .OUT(na1322_1_i), .IN1(~na456_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na4214_2), + .IN8(na1322_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1322_2 ( .OUT(na1322_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1322_1_i) ); +// C_MX4b/D/// x26y90 80'h00_FE00_00_0040_0AC0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1323_1 ( .OUT(na1323_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4405_2), + .IN8(na1323_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1323_2 ( .OUT(na1323_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1323_1_i) ); +// C_MX4b/D/// x25y88 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1324_1 ( .OUT(na1324_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1327_1), .IN6(na1324_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1324_2 ( .OUT(na1324_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1324_1_i) ); +// C_MX4b/D/// x43y88 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1325_1 ( .OUT(na1325_1_i), .IN1(na430_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4406_2), + .IN8(na1683_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1325_2 ( .OUT(na1325_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1325_1_i) ); +// C_MX4b/D/// x44y89 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1326_1 ( .OUT(na1326_1_i), .IN1(na430_2), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1326_1), + .IN8(na1683_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1326_2 ( .OUT(na1326_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1326_1_i) ); +// C_MX4b/D/// x27y85 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1327_1 ( .OUT(na1327_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1327_1), .IN6(na1328_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1327_2 ( .OUT(na1327_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1327_1_i) ); +// C_MX4b/D/// x27y86 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1328_1 ( .OUT(na1328_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1329_1), .IN6(na1328_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1328_2 ( .OUT(na1328_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1328_1_i) ); +// C_MX4b/D/// x29y89 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1329_1 ( .OUT(na1329_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1329_1), .IN6(na1331_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1329_2 ( .OUT(na1329_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1329_1_i) ); +// C_AND/D//AND/D x48y86 80'h00_FE00_80_0000_0C88_A5A5 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1330_1 ( .OUT(na1330_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na218_1), .IN6(1'b1), .IN7(na1680_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1330_2 ( .OUT(na1330_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1330_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1330_4 ( .OUT(na1330_2_i), .IN1(~na218_1), .IN2(1'b1), .IN3(na1680_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1330_5 ( .OUT(na1330_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1330_2_i) ); +// C_MX4b/D/// x31y88 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1331_1 ( .OUT(na1331_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4410_2), .IN6(na1352_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1331_2 ( .OUT(na1331_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1331_1_i) ); +// C_MX4b/D/// x28y90 80'h00_FE00_00_0040_0AC4_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1332_1 ( .OUT(na1332_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1333_1), + .IN8(na1332_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1332_2 ( .OUT(na1332_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1332_1_i) ); +// C_MX2b//// x32y87 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1333_1 ( .OUT(na1333_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1341_2), .IN5(1'b0), .IN6(~na1334_2), .IN7(1'b0), .IN8(~na1127_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x35y84 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1334_4 ( .OUT(na1334_2), .IN1(na3809_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1337_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b/D/// x27y89 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1335_1 ( .OUT(na1335_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1335_1), .IN6(na1376_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1335_2 ( .OUT(na1335_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1335_1_i) ); +// C_MX4b/D/// x28y83 80'h00_FE00_00_0040_0AC0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1336_1 ( .OUT(na1336_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1336_1), + .IN8(na1323_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1336_2 ( .OUT(na1336_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1336_1_i) ); +// C_ORAND*/D/// x34y84 80'h00_FE00_00_0000_0788_5FB5 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1337_1 ( .OUT(na1337_1_i), .IN1(~na220_1), .IN2(1'b0), .IN3(na1517_2), .IN4(~na1337_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1149_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1337_2 ( .OUT(na1337_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1337_1_i) ); +// C_MX4b/D/// x29y80 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1338_1 ( .OUT(na1338_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1295_1), .IN6(na1338_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1338_2 ( .OUT(na1338_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1338_1_i) ); +// C_MX4b/D/// x45y75 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1339_1 ( .OUT(na1339_1_i), .IN1(na31_2), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1339_1), .IN6(na44_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1339_2 ( .OUT(na1339_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1339_1_i) ); +// C_MX4b/D/// x34y85 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1340_1 ( .OUT(na1340_1_i), .IN1(1'b1), .IN2(na232_1), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1340_1), + .IN8(na1347_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1340_2 ( .OUT(na1340_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1340_1_i) ); +// C_///ORAND/D x38y86 80'h00_FE00_80_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1341_4 ( .OUT(na1341_2_i), .IN1(na3954_1), .IN2(na1342_1), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1341_5 ( .OUT(na1341_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1341_2_i) ); +// C_MX4a//// x37y88 80'h00_0018_00_0040_0C82_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1342_1 ( .OUT(na1342_1), .IN1(1'b0), .IN2(na3955_2), .IN3(1'b0), .IN4(1'b1), .IN5(na1345_1), .IN6(1'b1), .IN7(na2713_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x45y91 80'h00_0018_00_0040_0C55_1000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1343_1 ( .OUT(na1343_1), .IN1(~na1037_1), .IN2(1'b0), .IN3(~na1344_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na4545_2), + .IN8(~na2707_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ICOMP/ x42y85 80'h00_0060_00_0000_0C08_FF6C +C_ICOMP #(.CPE_CFG (9'b0_1000_0000)) + _a1344_4 ( .OUT(na1344_2), .IN1(1'b0), .IN2(~na1509_2), .IN3(~na1038_1), .IN4(na993_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x33y85 80'h00_0018_00_0000_0C88_84FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1345_1 ( .OUT(na1345_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2712_2), .IN6(na232_2), .IN7(na2713_1), + .IN8(na1347_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x34y89 80'h00_FE00_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1346_1 ( .OUT(na1346_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na232_2), .IN7(1'b1), .IN8(na1347_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1346_2 ( .OUT(na1346_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1346_1_i) ); +// C_MX4b/D/// x30y92 80'h00_FE00_00_0040_0AC4_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1347_1 ( .OUT(na1347_1_i), .IN1(1'b1), .IN2(~na4412_2), .IN3(~na4141_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1349_1), + .IN8(na1347_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1347_2 ( .OUT(na1347_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1347_1_i) ); +// C_AND///AND/ x34y91 80'h00_0078_00_0000_0C88_C15A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1349_1 ( .OUT(na1349_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1118_2), .IN6(~na225_2), .IN7(1'b1), .IN8(na229_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1349_4 ( .OUT(na1349_2), .IN1(na222_1), .IN2(1'b1), .IN3(~na1340_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x22y82 80'h00_F600_80_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1350_4 ( .OUT(na1350_2_i), .IN1(na411_1), .IN2(na288_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1350_5 ( .OUT(na1350_2), .CLK(na1739_1), .EN(~na1418_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1350_2_i) ); +// C_///ORAND/D x26y83 80'h00_FE00_80_0000_0C08_FFE3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1351_4 ( .OUT(na1351_2_i), .IN1(1'b0), .IN2(~na288_2), .IN3(na1351_2), .IN4(na3958_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1351_5 ( .OUT(na1351_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1351_2_i) ); +// C_MX4b/D/// x29y86 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1352_1 ( .OUT(na1352_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1335_1), .IN6(na1352_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1352_2 ( .OUT(na1352_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1352_1_i) ); +// C_MX4b/D/// x15y54 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1353_1 ( .OUT(na1353_1_i), .IN1(~na212_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1716_2), .IN6(na1353_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1353_2 ( .OUT(na1353_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1353_1_i) ); +// C_AND/D/// x45y81 80'h00_FE00_00_0000_0888_5122 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1354_1 ( .OUT(na1354_1_i), .IN1(na820_1), .IN2(~na285_1), .IN3(na83_2), .IN4(~na3230_2), .IN5(~na1354_1), .IN6(~na285_2), + .IN7(~na1149_2), .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1354_2 ( .OUT(na1354_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1354_1_i) ); +// C_MX4b/D/// x19y79 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1355_1 ( .OUT(na1355_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1355_1), .IN6(na4117_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1355_2 ( .OUT(na1355_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1355_1_i) ); +// C_MX4b/D/// x19y80 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1356_1 ( .OUT(na1356_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na163_1), .IN6(na1356_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1356_2 ( .OUT(na1356_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1356_1_i) ); +// C_MX4b/D/// x21y79 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1357_1 ( .OUT(na1357_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1357_1), .IN6(na1356_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1357_2 ( .OUT(na1357_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1357_1_i) ); +// C_MX2b/D/// x30y54 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1358_1 ( .OUT(na1358_1_i), .IN1(~na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3443_2), .IN8(na1359_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1358_2 ( .OUT(na1358_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1358_1_i) ); +// C_MX2b/D/// x24y48 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1359_1 ( .OUT(na1359_1_i), .IN1(na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1360_1), .IN8(na3442_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1359_2 ( .OUT(na1359_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1359_1_i) ); +// C_MX2b/D/// x24y45 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1360_1 ( .OUT(na1360_1_i), .IN1(na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1361_1), .IN8(na3439_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1360_2 ( .OUT(na1360_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1360_1_i) ); +// C_MX2b/D/// x24y47 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1361_1 ( .OUT(na1361_1_i), .IN1(~na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3430_1), .IN8(na1362_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1361_2 ( .OUT(na1361_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1361_1_i) ); +// C_MX2b/D/// x26y48 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1362_1 ( .OUT(na1362_1_i), .IN1(~na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3429_2), .IN8(na1363_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1362_2 ( .OUT(na1362_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1362_1_i) ); +// C_MX2b/D/// x28y50 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1363_1 ( .OUT(na1363_1_i), .IN1(na888_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1305_2), .IN8(na3427_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1363_2 ( .OUT(na1363_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1363_1_i) ); +// C_MX4b/D/// x19y81 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1364_1 ( .OUT(na1364_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1364_1), .IN6(na158_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1364_2 ( .OUT(na1364_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1364_1_i) ); +// C_MX4b/D/// x18y78 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1365_1 ( .OUT(na1365_1_i), .IN1(1'b1), .IN2(~na120_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na134_1), + .IN8(na1365_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1365_2 ( .OUT(na1365_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1365_1_i) ); +// C_MX4b/D/// x19y69 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1366_1 ( .OUT(na1366_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1366_1), .IN6(na130_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1366_2 ( .OUT(na1366_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1366_1_i) ); +// C_MX4b/D/// x19y67 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1367_1 ( .OUT(na1367_1_i), .IN1(1'b1), .IN2(na120_2), .IN3(na1149_2), .IN4(1'b1), .IN5(na1367_1), .IN6(na4415_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1367_2 ( .OUT(na1367_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1367_1_i) ); +// C_MX4b/D/// x29y91 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1368_1 ( .OUT(na1368_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1368_1), .IN6(na1377_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1368_2 ( .OUT(na1368_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1368_1_i) ); +// C_MX4b/D/// x20y63 80'h00_FE00_00_0040_0AC3_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1369_1 ( .OUT(na1369_1_i), .IN1(1'b1), .IN2(na1487_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1369_1), + .IN8(na4100_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1369_2 ( .OUT(na1369_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1369_1_i) ); +// C_///ORAND/D x27y69 80'h00_FE00_80_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1370_4 ( .OUT(na1370_2_i), .IN1(na1371_1), .IN2(na3960_2), .IN3(~na1149_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1370_5 ( .OUT(na1370_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1370_2_i) ); +// C_MX4a//// x21y61 80'h00_0018_00_0040_0C41_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1371_1 ( .OUT(na1371_1), .IN1(na3961_2), .IN2(1'b0), .IN3(1'b1), .IN4(1'b0), .IN5(~na1374_2), .IN6(1'b1), .IN7(na4529_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x23y65 80'h00_0018_00_0040_0C33_0100 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1372_1 ( .OUT(na1372_1), .IN1(~na877_1), .IN2(~na1373_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na4521_2), .IN6(~na2474_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ICOMP/ x19y52 80'h00_0060_00_0000_0C08_FF6C +C_ICOMP #(.CPE_CFG (9'b0_1000_0000)) + _a1373_4 ( .OUT(na1373_2), .IN1(1'b0), .IN2(~na1487_1), .IN3(~na4298_2), .IN4(na864_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x15y61 80'h00_0060_00_0000_0C08_FF82 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1374_4 ( .OUT(na1374_2), .IN1(na4163_2), .IN2(~na2478_1), .IN3(na2481_2), .IN4(na214_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x15y53 80'h00_FE00_80_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1375_4 ( .OUT(na1375_2_i), .IN1(1'b1), .IN2(na299_1), .IN3(1'b1), .IN4(na214_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1375_5 ( .OUT(na1375_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1375_2_i) ); +// C_MX4b/D/// x29y88 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1376_1 ( .OUT(na1376_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1368_1), .IN6(na1376_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1376_2 ( .OUT(na1376_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1376_1_i) ); +// C_MX4b/D/// x31y86 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1377_1 ( .OUT(na1377_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na4417_2), .IN6(na1381_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1377_2 ( .OUT(na1377_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1377_1_i) ); +// C_MX4b/D/// x25y87 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1378_1 ( .OUT(na1378_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1378_1), .IN6(na1379_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1378_2 ( .OUT(na1378_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1378_1_i) ); +// C_MX4b/D/// x23y86 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1379_1 ( .OUT(na1379_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1397_1), .IN6(na1379_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1379_2 ( .OUT(na1379_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1379_1_i) ); +// C_MX4b/D/// x27y82 80'h00_FE00_00_0040_0A30_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1381_1 ( .OUT(na1381_1_i), .IN1(~na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1378_1), .IN6(na1381_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1381_2 ( .OUT(na1381_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1381_1_i) ); +// C_///ORAND/D x47y56 80'h00_FE00_80_0000_0C08_FFAE +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1383_4 ( .OUT(na1383_2_i), .IN1(na335_2), .IN2(na1383_2), .IN3(na3964_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1383_5 ( .OUT(na1383_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1383_2_i) ); +// C_OR/D//OR/D x16y86 80'h00_FE00_80_0000_0CEE_AEBC +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1385_1 ( .OUT(na1385_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1618_2), .IN6(na288_2), .IN7(na287_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1385_2 ( .OUT(na1385_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1385_1_i) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1385_4 ( .OUT(na1385_2_i), .IN1(1'b0), .IN2(na288_2), .IN3(na287_2), .IN4(~na1385_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1385_5 ( .OUT(na1385_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1385_2_i) ); +// C_MX4b/D/// x43y62 80'h00_FE00_00_0040_0AC0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1386_1 ( .OUT(na1386_1_i), .IN1(1'b1), .IN2(~na1383_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1730_1), + .IN8(na4418_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1386_2 ( .OUT(na1386_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1386_1_i) ); +// C_MX4b/D/// x45y63 80'h00_FE00_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1387_1 ( .OUT(na1387_1_i), .IN1(1'b1), .IN2(na1383_2), .IN3(~na1149_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na4419_2), + .IN8(na1728_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1387_2 ( .OUT(na1387_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1387_1_i) ); +// C_MX2b/D/// x56y74 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1388_1 ( .OUT(na1388_1_i), .IN1(~na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3444_1), .IN8(na1389_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1388_2 ( .OUT(na1388_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1388_1_i) ); +// C_MX2b/D/// x34y52 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1389_1 ( .OUT(na1389_1_i), .IN1(~na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3443_2), .IN8(na1390_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1389_2 ( .OUT(na1389_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1389_1_i) ); +// C_MX2b/D/// x32y54 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1390_1 ( .OUT(na1390_1_i), .IN1(na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1391_1), .IN8(na3442_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1390_2 ( .OUT(na1390_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1390_1_i) ); +// C_MX2b/D/// x26y47 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1391_1 ( .OUT(na1391_1_i), .IN1(na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1392_1), .IN8(na3439_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1391_2 ( .OUT(na1391_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1391_1_i) ); +// C_MX2b/D/// x26y49 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1392_1 ( .OUT(na1392_1_i), .IN1(~na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3430_1), .IN8(na1393_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1392_2 ( .OUT(na1392_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1392_1_i) ); +// C_MX2b/D/// x28y52 80'h00_FE00_00_0040_0AC0_00F5 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1393_1 ( .OUT(na1393_1_i), .IN1(~na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na3429_2), .IN8(na1394_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1393_2 ( .OUT(na1393_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1393_1_i) ); +// C_MX2b/D/// x32y52 80'h00_FE00_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1394_1 ( .OUT(na1394_1_i), .IN1(na888_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na887_2), .IN8(na3427_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1394_2 ( .OUT(na1394_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1394_1_i) ); +// C_MX4b/D/// x29y75 80'h00_FE00_00_0040_0A30_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1395_1 ( .OUT(na1395_1_i), .IN1(1'b1), .IN2(na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1395_1), .IN6(na4168_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1395_2 ( .OUT(na1395_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1395_1_i) ); +// C_MX4b/D/// x27y74 80'h00_FE00_00_0040_0A30_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1396_1 ( .OUT(na1396_1_i), .IN1(1'b1), .IN2(~na33_1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1395_1), .IN6(na1396_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1396_2 ( .OUT(na1396_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1396_1_i) ); +// C_MX4b/D/// x25y85 80'h00_FE00_00_0040_0A30_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1397_1 ( .OUT(na1397_1_i), .IN1(na220_1), .IN2(1'b1), .IN3(na1149_2), .IN4(1'b1), .IN5(na1397_1), .IN6(na361_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1397_2 ( .OUT(na1397_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1397_1_i) ); +// C_ORAND//// x38y74 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1398_1 ( .OUT(na1398_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4399_2), .IN6(~na4401_2), .IN7(~na287_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x40y63 80'h00_0018_00_0000_0C88_ADFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1399_1 ( .OUT(na1399_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na456_1), .IN6(na4584_2), .IN7(na446_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x47y66 80'h00_0018_00_0000_0C88_35FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1400_1 ( .OUT(na1400_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na436_1), .IN6(1'b1), .IN7(1'b1), .IN8(~na4205_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x60y78 80'h00_0060_00_0000_0C08_FFDC +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1401_4 ( .OUT(na1401_2), .IN1(1'b0), .IN2(na223_2), .IN3(~na4140_2), .IN4(na3285_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x49y75 80'h00_0060_00_0000_0C08_FFF1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1402_4 ( .OUT(na1402_2), .IN1(~na218_1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x22y46 80'h00_0018_00_0000_0C88_35FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1403_1 ( .OUT(na1403_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na121_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na4442_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x43y48 80'h00_0018_00_0000_0C88_BAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1404_1 ( .OUT(na1404_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na301_1), .IN6(1'b0), .IN7(na4587_2), .IN8(~na4442_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x58y57 80'h00_0060_00_0000_0C08_FF33 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1405_4 ( .OUT(na1405_2), .IN1(1'b1), .IN2(~na4424_2), .IN3(1'b1), .IN4(~na54_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x69y49 80'h00_0060_00_0000_0C08_FFCB +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1406_4 ( .OUT(na1406_2), .IN1(na4585_2), .IN2(~na4424_2), .IN3(1'b0), .IN4(na4091_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x66y42 80'h00_0018_00_0000_0C88_CDFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1407_1 ( .OUT(na1407_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1465_2), .IN6(na4586_2), .IN7(1'b0), .IN8(na336_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y45 80'h00_0018_00_0000_0C88_35FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1408_1 ( .OUT(na1408_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na275_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na4432_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y52 80'h00_0018_00_0000_0C88_3AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1409_1 ( .OUT(na1409_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4467_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na1544_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x61y47 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1410_1 ( .OUT(na1410_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4467_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1544_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x62y48 80'h00_0018_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1411_1 ( .OUT(na1411_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4467_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1544_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y40 80'h00_0018_00_0000_0C88_F2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1412_1 ( .OUT(na1412_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4464_2), .IN6(~na1542_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x61y40 80'h00_0018_00_0000_0C88_F4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1413_1 ( .OUT(na1413_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4464_2), .IN6(na1542_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y36 80'h00_0060_00_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1414_4 ( .OUT(na1414_2), .IN1(na4464_2), .IN2(na1542_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x36y46 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1415_4 ( .OUT(na1415_2), .IN1(na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1545_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x39y46 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1416_1 ( .OUT(na1416_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4468_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1545_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x36y48 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1417_4 ( .OUT(na1417_2), .IN1(na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1545_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x29y87 80'h00_0060_00_0000_0C08_FF73 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1418_4 ( .OUT(na1418_2), .IN1(1'b0), .IN2(~na288_2), .IN3(~na287_2), .IN4(~na1296_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x57y70 80'h00_0060_00_0000_0C08_FFF2 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1419_4 ( .OUT(na1419_2), .IN1(na4466_2), .IN2(~na1543_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x51y75 80'h00_0018_00_0000_0C88_F4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1420_1 ( .OUT(na1420_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4466_2), .IN6(na1543_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x51y76 80'h00_0018_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1421_1 ( .OUT(na1421_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4466_2), .IN6(na1543_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x39y59 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1422_1 ( .OUT(na1422_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1541_1), .IN7(1'b1), .IN8(na4462_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x39y59 80'h00_0060_00_0000_0C08_FF3C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1423_4 ( .OUT(na1423_2), .IN1(1'b1), .IN2(na1541_1), .IN3(1'b1), .IN4(~na4462_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x32y57 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1424_4 ( .OUT(na1424_2), .IN1(1'b1), .IN2(na1541_1), .IN3(1'b1), .IN4(na4462_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x68y64 80'h00_0060_00_0000_0C08_FF33 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1425_4 ( .OUT(na1425_2), .IN1(1'b1), .IN2(~na2350_2), .IN3(1'b1), .IN4(~na519_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y45 80'h00_0060_00_0000_0C08_FFF1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1426_4 ( .OUT(na1426_2), .IN1(~na704_2), .IN2(~na2246_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x39y55 80'h00_0060_00_0000_0C08_FF33 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1427_4 ( .OUT(na1427_2), .IN1(1'b1), .IN2(~na881_2), .IN3(1'b1), .IN4(~na2497_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x53y92 80'h00_0018_00_0000_0C88_33FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1428_1 ( .OUT(na1428_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1044_2), .IN7(1'b1), .IN8(~na2730_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y81 80'h00_0060_00_0000_0C08_FFF1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1429_4 ( .OUT(na1429_2), .IN1(~na1192_2), .IN2(~na2981_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x36y55 80'h00_0018_00_0000_0C88_D3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1431_1 ( .OUT(na1431_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na4424_2), .IN7(~na4093_2), .IN8(na1090_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x61y64 80'h00_FE00_00_0000_0C88_34FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1432_1 ( .OUT(na1432_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na3975_1), .IN6(na4075_2), .IN7(1'b1), .IN8(~na1434_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1432_2 ( .OUT(na1432_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1432_1_i) ); +// C_MX4b//// x66y70 80'h00_0018_00_0040_0A32_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1434_1 ( .OUT(na1434_1), .IN1(na4489_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1990_1), .IN5(na4490_2), .IN6(~na1993_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x66y79 80'h00_0018_00_0000_0888_FDAC +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1435_1 ( .OUT(na1435_1), .IN1(1'b0), .IN2(na523_1), .IN3(na115_1), .IN4(1'b0), .IN5(~na360_2), .IN6(na103_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x67y79 80'h00_0060_00_0000_0C08_FF84 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1436_4 ( .OUT(na1436_2), .IN1(~na360_2), .IN2(na57_1), .IN3(na115_1), .IN4(na4222_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x70y75 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1437_1 ( .OUT(na1437_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na522_2), .IN6(1'b1), .IN7(na115_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x69y76 80'h00_FE00_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1438_1 ( .OUT(na1438_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3977_1), .IN7(na115_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1438_2 ( .OUT(na1438_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1438_1_i) ); +// C_AND/D/// x66y81 80'h00_FE00_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1439_1 ( .OUT(na1439_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na31_2), .IN6(na3978_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1439_2 ( .OUT(na1439_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1439_1_i) ); +// C_///AND/D x64y88 80'h00_FE00_80_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1440_4 ( .OUT(na1440_2_i), .IN1(na31_2), .IN2(na3979_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1440_5 ( .OUT(na1440_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1440_2_i) ); +// C_///AND/D x67y62 80'h00_FA00_80_0000_0C08_FFC8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1441_4 ( .OUT(na1441_2_i), .IN1(na535_1), .IN2(na1986_2), .IN3(1'b1), .IN4(na1984_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1441_5 ( .OUT(na1441_2), .CLK(na1739_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1441_2_i) ); +// C_AND*/D//ORAND/D x58y64 80'h00_FE00_80_0000_0388_3C5E +C_AND #(.CPE_CFG (9'b1_0000_0000)) + _a1443_1 ( .OUT(na1443_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4424_2), .IN7(1'b1), .IN8(~na1088_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1443_2 ( .OUT(na1443_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1443_1_i) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1443_4 ( .OUT(na1443_2_i), .IN1(na90_1), .IN2(na4424_2), .IN3(~na38_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1443_5 ( .OUT(na1443_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1443_2_i) ); +// C_AND/D/// x66y67 80'h00_FE00_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1444_1 ( .OUT(na1444_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4424_2), .IN7(na511_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1444_2 ( .OUT(na1444_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1444_1_i) ); +// C_MX4a////D x69y77 80'h00_FA18_00_0040_0C49_A300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1445_1 ( .OUT(na1445_1), .IN1(na4426_2), .IN2(1'b0), .IN3(1'b1), .IN4(na1446_2), .IN5(1'b1), .IN6(~na512_1), .IN7(na4221_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1445_5 ( .OUT(na1445_2), .CLK(na1739_1), .EN(na1435_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1445_1) ); +// C_///AND/D x70y76 80'h00_FE00_80_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1446_4 ( .OUT(na1446_2_i), .IN1(na1445_1), .IN2(na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1446_5 ( .OUT(na1446_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1446_2_i) ); +// C_AND/D/// x66y65 80'h00_FE00_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1447_1 ( .OUT(na1447_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3981_1), .IN6(na4424_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1447_2 ( .OUT(na1447_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1447_1_i) ); +// C_ORAND//// x70y65 80'h00_0018_00_0000_0C88_E3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1448_1 ( .OUT(na1448_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na1986_1), .IN7(na3983_1), .IN8(na519_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x69y66 80'h00_0060_00_0000_0C08_FFB3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1449_4 ( .OUT(na1449_2), .IN1(1'b0), .IN2(~na1986_1), .IN3(na4519_2), .IN4(~na519_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x69y67 80'h00_0060_00_0000_0C08_FFB3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1450_4 ( .OUT(na1450_2), .IN1(1'b0), .IN2(~na1986_1), .IN3(na3983_1), .IN4(~na519_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x57y58 80'h00_FE00_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1451_1 ( .OUT(na1451_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4223_2), .IN7(1'b1), .IN8(na1411_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1451_2 ( .OUT(na1451_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1451_1_i) ); +// C_///ORAND/ x23y56 80'h00_0060_00_0000_0C08_FFB5 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1453_4 ( .OUT(na1453_2), .IN1(~na1465_2), .IN2(1'b0), .IN3(na4179_2), .IN4(~na340_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x52y55 80'h00_FE00_80_0000_0C08_FF34 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1454_4 ( .OUT(na1454_2_i), .IN1(~na1456_1), .IN2(na33_1), .IN3(1'b1), .IN4(~na3988_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1454_5 ( .OUT(na1454_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1454_2_i) ); +// C_MX4b//// x53y61 80'h00_0018_00_0040_0A51_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1456_1 ( .OUT(na1456_1), .IN1(1'b1), .IN2(na2228_2), .IN3(1'b1), .IN4(~na4511_2), .IN5(~na2229_1), .IN6(1'b0), .IN7(na4506_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x49y61 80'h00_0018_00_0000_0888_FBAA +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1457_1 ( .OUT(na1457_1), .IN1(na333_1), .IN2(1'b0), .IN3(na262_1), .IN4(1'b0), .IN5(na329_1), .IN6(~na295_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x53y63 80'h00_0060_00_0000_0C08_FF28 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1458_4 ( .OUT(na1458_2), .IN1(na333_1), .IN2(na330_1), .IN3(na262_1), .IN4(~na4159_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x55y64 80'h00_0060_00_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1459_4 ( .OUT(na1459_2), .IN1(na707_1), .IN2(na4173_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x64y60 80'h00_FE00_80_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1460_4 ( .OUT(na1460_2_i), .IN1(na3990_1), .IN2(na4173_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1460_5 ( .OUT(na1460_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1460_2_i) ); +// C_AND/D/// x60y72 80'h00_FE00_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1461_1 ( .OUT(na1461_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3991_1), .IN7(1'b1), .IN8(na4076_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1461_2 ( .OUT(na1461_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1461_1_i) ); +// C_///AND/D x54y75 80'h00_FE00_80_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1462_4 ( .OUT(na1462_2_i), .IN1(na3992_1), .IN2(na33_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1462_5 ( .OUT(na1462_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1462_2_i) ); +// C_AND/D/// x65y47 80'h00_FA00_00_0000_0C88_8AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1463_1 ( .OUT(na1463_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4265_2), .IN6(1'b1), .IN7(na2223_2), .IN8(na2221_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1463_2 ( .OUT(na1463_1), .CLK(na1739_1), .EN(na333_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1463_1_i) ); +// C_AND*/D//ORAND/D x55y55 80'h00_FE00_80_0000_0388_5A3E +C_AND #(.CPE_CFG (9'b1_0000_0000)) + _a1465_1 ( .OUT(na1465_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1465_2), .IN6(1'b1), .IN7(~na356_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1465_2 ( .OUT(na1465_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1465_1_i) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1465_4 ( .OUT(na1465_2_i), .IN1(na1465_2), .IN2(na4174_2), .IN3(1'b0), .IN4(~na4160_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1465_5 ( .OUT(na1465_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1465_2_i) ); +// C_AND/D/// x63y52 80'h00_FE00_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1466_1 ( .OUT(na1466_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1465_2), .IN6(na352_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1466_2 ( .OUT(na1466_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1466_1_i) ); +// C_MX4a////D x56y63 80'h00_FA18_00_0040_0C86_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1467_1 ( .OUT(na1467_1), .IN1(1'b0), .IN2(na4435_2), .IN3(na1468_1), .IN4(1'b1), .IN5(na707_1), .IN6(1'b1), .IN7(na353_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1467_5 ( .OUT(na1467_2), .CLK(na1739_1), .EN(na1457_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1467_1) ); +// C_AND/D/// x54y59 80'h00_FE00_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1468_1 ( .OUT(na1468_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1465_2), .IN6(1'b1), .IN7(na1467_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1468_2 ( .OUT(na1468_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1468_1_i) ); +// C_AND/D/// x62y49 80'h00_FE00_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1469_1 ( .OUT(na1469_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1465_2), .IN6(na3994_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1469_2 ( .OUT(na1469_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1469_1_i) ); +// C_ORAND//// x69y46 80'h00_0018_00_0000_0C88_5EFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1470_1 ( .OUT(na1470_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3996_2), .IN6(na2246_2), .IN7(~na2223_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x68y47 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1471_4 ( .OUT(na1471_2), .IN1(na704_2), .IN2(~na2246_2), .IN3(~na2223_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x70y48 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1472_1 ( .OUT(na1472_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3996_2), .IN6(~na2246_2), .IN7(~na2223_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x51y41 80'h00_FE00_80_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1473_4 ( .OUT(na1473_2_i), .IN1(1'b1), .IN2(na1414_2), .IN3(na636_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1473_5 ( .OUT(na1473_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1473_2_i) ); +// C_ORAND//// x18y42 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1475_1 ( .OUT(na1475_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1375_2), .IN6(~na4165_2), .IN7(1'b0), .IN8(~na4442_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x13y56 80'h00_FE00_80_0000_0C08_FF34 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1476_4 ( .OUT(na1476_2_i), .IN1(~na1478_1), .IN2(na120_2), .IN3(1'b1), .IN4(~na4001_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1476_5 ( .OUT(na1476_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1476_2_i) ); +// C_MX4b//// x17y55 80'h00_0018_00_0040_0AC4_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1478_1 ( .OUT(na1478_1), .IN1(1'b1), .IN2(~na2478_2), .IN3(~na4526_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na2481_2), + .IN8(na4532_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x15y55 80'h00_0018_00_0000_0888_BFAC +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1479_1 ( .OUT(na1479_1), .IN1(1'b0), .IN2(na299_1), .IN3(na189_2), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(na1369_1), .IN8(~na214_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x22y64 80'h00_0018_00_0000_0C88_84FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1480_1 ( .OUT(na1480_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4131_2), .IN6(na299_1), .IN7(na189_2), .IN8(na110_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x21y55 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1481_4 ( .OUT(na1481_2), .IN1(1'b1), .IN2(na299_1), .IN3(1'b1), .IN4(na884_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x15y62 80'h00_FE00_80_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1482_4 ( .OUT(na1482_2_i), .IN1(1'b1), .IN2(na299_1), .IN3(na4003_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1482_5 ( .OUT(na1482_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1482_2_i) ); +// C_///AND/D x13y67 80'h00_FE00_80_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1483_4 ( .OUT(na1483_2_i), .IN1(1'b1), .IN2(na4004_1), .IN3(na4104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1483_5 ( .OUT(na1483_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1483_2_i) ); +// C_///AND/D x15y71 80'h00_FE00_80_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1484_4 ( .OUT(na1484_2_i), .IN1(1'b1), .IN2(na4005_1), .IN3(na4104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1484_5 ( .OUT(na1484_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1484_2_i) ); +// C_AND/D/// x28y51 80'h00_FA00_00_0000_0C88_C8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1485_1 ( .OUT(na1485_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2472_1), .IN6(na2474_2), .IN7(1'b1), .IN8(na864_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1485_2 ( .OUT(na1485_1), .CLK(na1739_1), .EN(na299_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1485_1_i) ); +// C_AND*/D//ORAND/D x25y54 80'h00_FE00_80_0000_0388_C3E3 +C_AND #(.CPE_CFG (9'b1_0000_0000)) + _a1487_1 ( .OUT(na1487_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1373_2), .IN7(1'b1), .IN8(na4442_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1487_2 ( .OUT(na1487_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1487_1_i) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1487_4 ( .OUT(na1487_2_i), .IN1(1'b0), .IN2(~na4132_2), .IN3(na1567_1), .IN4(na4442_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1487_5 ( .OUT(na1487_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1487_2_i) ); +// C_AND/D/// x23y59 80'h00_FE00_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1488_1 ( .OUT(na1488_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na877_1), .IN6(1'b1), .IN7(1'b1), .IN8(na4442_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1488_2 ( .OUT(na1488_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1488_1_i) ); +// C_MX4a////D x18y50 80'h00_FA18_00_0040_0C29_3C00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1489_1 ( .OUT(na1489_1), .IN1(na1490_2), .IN2(1'b1), .IN3(1'b0), .IN4(na4445_2), .IN5(1'b1), .IN6(na878_1), .IN7(1'b1), .IN8(~na884_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1489_5 ( .OUT(na1489_2), .CLK(na1739_1), .EN(na1479_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1489_1) ); +// C_///AND/D x15y49 80'h00_FE00_80_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1490_4 ( .OUT(na1490_2_i), .IN1(1'b1), .IN2(na4441_2), .IN3(1'b1), .IN4(na1489_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1490_5 ( .OUT(na1490_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1490_2_i) ); +// C_AND/D/// x24y55 80'h00_FE00_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1491_1 ( .OUT(na1491_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1487_2), .IN7(1'b1), .IN8(na4007_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1491_2 ( .OUT(na1491_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1491_1_i) ); +// C_ORAND//// x35y50 80'h00_0018_00_0000_0C88_E3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1492_1 ( .OUT(na1492_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na2474_1), .IN7(na4009_1), .IN8(na2497_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x36y55 80'h00_0060_00_0000_0C08_FFB3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1493_4 ( .OUT(na1493_2), .IN1(1'b0), .IN2(~na2474_1), .IN3(na4302_2), .IN4(~na2497_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x42y56 80'h00_0060_00_0000_0C08_FFB3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1494_4 ( .OUT(na1494_2), .IN1(1'b0), .IN2(~na2474_1), .IN3(na4009_1), .IN4(~na2497_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x26y54 80'h00_FE00_80_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1495_4 ( .OUT(na1495_2_i), .IN1(1'b1), .IN2(na194_1), .IN3(1'b1), .IN4(na1417_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1495_5 ( .OUT(na1495_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1495_2_i) ); +// C_///ORAND/ x25y89 80'h00_0060_00_0000_0C08_FFB3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1497_4 ( .OUT(na1497_2), .IN1(1'b0), .IN2(~na232_1), .IN3(na1346_1), .IN4(~na4139_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x35y81 80'h00_FE00_00_0000_0C88_1AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1498_1 ( .OUT(na1498_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na220_1), .IN6(1'b1), .IN7(~na1500_1), .IN8(~na4014_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1498_2 ( .OUT(na1498_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1498_1_i) ); +// C_MX4b//// x36y83 80'h00_0018_00_0040_0A54_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1500_1 ( .OUT(na1500_1), .IN1(na2712_2), .IN2(1'b1), .IN3(na2713_2), .IN4(1'b1), .IN5(na2712_1), .IN6(1'b0), .IN7(~na2713_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x28y91 80'h00_0018_00_0000_0888_DFCC +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1501_1 ( .OUT(na1501_1), .IN1(1'b0), .IN2(na1048_1), .IN3(1'b0), .IN4(na1347_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na432_2), + .IN8(na239_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x39y92 80'h00_0018_00_0000_0C88_84FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1502_1 ( .OUT(na1502_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4198_2), .IN6(na1048_1), .IN7(na238_1), + .IN8(na1347_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x39y92 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1503_4 ( .OUT(na1503_2), .IN1(1'b1), .IN2(na1047_1), .IN3(1'b1), .IN4(na1347_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x41y90 80'h00_FE00_80_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1504_4 ( .OUT(na1504_2_i), .IN1(na4411_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4016_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1504_5 ( .OUT(na1504_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1504_2_i) ); +// C_///AND/D x31y90 80'h00_FE00_80_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1505_4 ( .OUT(na1505_2_i), .IN1(na4017_1), .IN2(1'b1), .IN3(1'b1), .IN4(na4137_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1505_5 ( .OUT(na1505_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1505_2_i) ); +// C_AND/D/// x25y90 80'h00_FE00_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1506_1 ( .OUT(na1506_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4018_1), .IN6(1'b1), .IN7(1'b1), .IN8(na4137_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1506_2 ( .OUT(na1506_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1506_1_i) ); +// C_AND/D/// x36y81 80'h00_FA00_00_0000_0C88_8AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1507_1 ( .OUT(na1507_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4547_2), .IN6(1'b1), .IN7(na2705_2), .IN8(na993_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1507_2 ( .OUT(na1507_1), .CLK(na1739_1), .EN(na1347_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1507_1_i) ); +// C_///AND*/D x39y84 80'h00_FE00_80_0000_0C07_FF5C +C_AND #(.CPE_CFG (9'b1_1000_0000)) + _a1509_4 ( .OUT(na1509_2_i), .IN1(1'b1), .IN2(na232_1), .IN3(~na1344_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1509_5 ( .OUT(na1509_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1509_2_i) ); +// C_AND/D/// x37y87 80'h00_FE00_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1510_1 ( .OUT(na1510_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1037_1), .IN6(na232_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1510_2 ( .OUT(na1510_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1510_1_i) ); +// C_MX4a////D x36y89 80'h00_FA18_00_0040_0C29_5C00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1511_1 ( .OUT(na1511_1), .IN1(na4451_2), .IN2(1'b1), .IN3(1'b0), .IN4(na1512_1), .IN5(1'b1), .IN6(na1047_1), .IN7(~na1038_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1511_5 ( .OUT(na1511_2), .CLK(na1739_1), .EN(na1501_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1511_1) ); +// C_AND/D/// x36y90 80'h00_FE00_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1512_1 ( .OUT(na1512_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na232_1), .IN7(na1511_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1512_2 ( .OUT(na1512_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1512_1_i) ); +// C_AND/D/// x35y84 80'h00_FE00_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1513_1 ( .OUT(na1513_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4020_1), .IN6(na232_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1513_2 ( .OUT(na1513_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1513_1_i) ); +// C_///ORAND/ x55y91 80'h00_0060_00_0000_0C08_FF3E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1514_4 ( .OUT(na1514_2), .IN1(na4558_2), .IN2(na4022_2), .IN3(1'b0), .IN4(~na2707_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x54y92 80'h00_0060_00_0000_0C08_FF3D +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1515_4 ( .OUT(na1515_2), .IN1(~na4558_2), .IN2(na1044_2), .IN3(1'b0), .IN4(~na2707_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x56y89 80'h00_0060_00_0000_0C08_FF3D +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1516_4 ( .OUT(na1516_2), .IN1(~na4558_2), .IN2(na4022_2), .IN3(1'b0), .IN4(~na2707_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x52y81 80'h00_FE00_80_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1517_4 ( .OUT(na1517_2_i), .IN1(1'b1), .IN2(na1421_1), .IN3(na4293_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1517_5 ( .OUT(na1517_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1517_2_i) ); +// C_ORAND//// x18y75 80'h00_0018_00_0000_0C88_D5FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1519_1 ( .OUT(na1519_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na456_1), .IN6(1'b0), .IN7(~na449_2), .IN8(na4212_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x37y71 80'h00_FE00_80_0000_0C08_FF43 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1520_4 ( .OUT(na1520_2_i), .IN1(1'b1), .IN2(~na4027_1), .IN3(~na1522_1), .IN4(na4195_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1520_5 ( .OUT(na1520_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1520_2_i) ); +// C_MX4b//// x54y83 80'h00_0018_00_0040_0A32_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1522_1 ( .OUT(na1522_1), .IN1(na2962_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4568_2), .IN5(na2963_2), .IN6(~na2965_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x61y91 80'h00_0018_00_0000_0888_DFAC +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1523_1 ( .OUT(na1523_1), .IN1(1'b0), .IN2(na1196_1), .IN3(na443_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(~na980_2), .IN8(na1322_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x62y88 80'h00_0060_00_0000_0C08_FF48 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1524_4 ( .OUT(na1524_2), .IN1(na4371_2), .IN2(na1321_1), .IN3(~na980_2), .IN4(na4201_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x62y88 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1525_1 ( .OUT(na1525_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na443_1), .IN8(na1195_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x64y88 80'h00_FE00_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1526_1 ( .OUT(na1526_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4029_1), .IN7(na443_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1526_2 ( .OUT(na1526_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1526_1_i) ); +// C_///AND/D x52y91 80'h00_FE00_80_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1527_4 ( .OUT(na1527_2_i), .IN1(na4030_1), .IN2(na424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1527_5 ( .OUT(na1527_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1527_2_i) ); +// C_///AND/D x43y90 80'h00_FE00_80_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1528_4 ( .OUT(na1528_2_i), .IN1(1'b1), .IN2(na424_2), .IN3(na4031_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1528_5 ( .OUT(na1528_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1528_2_i) ); +// C_///AND/D x62y78 80'h00_FA00_80_0000_0C08_FF8A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1529_4 ( .OUT(na1529_2_i), .IN1(na2956_1), .IN2(1'b1), .IN3(na2958_2), .IN4(na1388_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1529_5 ( .OUT(na1529_2), .CLK(na1739_1), .EN(na443_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1529_2_i) ); +// C_///AND*/D x63y79 80'h00_FE00_80_0000_0C07_FF5A +C_AND #(.CPE_CFG (9'b1_1000_0000)) + _a1531_4 ( .OUT(na1531_2_i), .IN1(na456_1), .IN2(1'b1), .IN3(~na467_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1531_5 ( .OUT(na1531_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1531_2_i) ); +// C_AND/D/// x61y81 80'h00_FE00_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1532_1 ( .OUT(na1532_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na460_1), .IN6(1'b1), .IN7(1'b1), .IN8(na4205_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1532_2 ( .OUT(na1532_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1532_1_i) ); +// C_MX4a////D x67y85 80'h00_FA18_00_0040_0C86_CC00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1533_1 ( .OUT(na1533_1), .IN1(1'b0), .IN2(na4458_2), .IN3(na1534_2), .IN4(1'b1), .IN5(1'b1), .IN6(na4209_2), .IN7(1'b1), + .IN8(na1195_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1533_5 ( .OUT(na1533_2), .CLK(na1739_1), .EN(na1523_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1533_1) ); +// C_///AND/D x70y87 80'h00_FE00_80_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1534_4 ( .OUT(na1534_2_i), .IN1(na1533_1), .IN2(1'b1), .IN3(1'b1), .IN4(na4205_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1534_5 ( .OUT(na1534_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1534_2_i) ); +// C_AND/D/// x63y79 80'h00_FE00_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1535_1 ( .OUT(na1535_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na456_1), .IN6(na4033_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1535_2 ( .OUT(na1535_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1535_1_i) ); +// C_ORAND//// x59y86 80'h00_0018_00_0000_0C88_5EFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1536_1 ( .OUT(na1536_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4035_2), .IN6(na2981_1), .IN7(~na2958_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x66y81 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1537_4 ( .OUT(na1537_2), .IN1(na1192_2), .IN2(~na2981_1), .IN3(~na2958_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x64y84 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1538_4 ( .OUT(na1538_2), .IN1(na4035_2), .IN2(~na2981_1), .IN3(~na2958_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x30y66 80'h00_FE00_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1539_1 ( .OUT(na1539_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na421_1), .IN7(na1424_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1539_2 ( .OUT(na1539_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1539_1_i) ); +// C_///AND/ x13y71 80'h00_0060_00_0000_0C08_FF1F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1540_4 ( .OUT(na1540_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na990_1), .IN4(~na1350_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR/D//AND/D x31y62 80'h00_FA00_80_0000_0C68_CCF3 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1541_1 ( .OUT(na1541_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1541_1), .IN7(1'b0), .IN8(na4462_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1541_2 ( .OUT(na1541_1), .CLK(na1739_1), .EN(na421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1541_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1541_4 ( .OUT(na1541_2_i), .IN1(1'b1), .IN2(~na1541_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1541_5 ( .OUT(na1541_2), .CLK(na1739_1), .EN(na421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1541_2_i) ); +// C_XOR/D//AND/D x69y36 80'h00_FA00_80_0000_0C68_06F3 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1542_1 ( .OUT(na1542_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4464_2), .IN6(na1542_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1542_2 ( .OUT(na1542_1), .CLK(na1739_1), .EN(na636_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1542_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1542_4 ( .OUT(na1542_2_i), .IN1(1'b1), .IN2(~na1542_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1542_5 ( .OUT(na1542_2), .CLK(na1739_1), .EN(na636_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1542_2_i) ); +// C_XOR/D//AND/D x55y78 80'h00_FA00_80_0000_0C68_06F3 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1543_1 ( .OUT(na1543_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4466_2), .IN6(na1543_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1543_2 ( .OUT(na1543_1), .CLK(na1739_1), .EN(na817_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1543_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1543_4 ( .OUT(na1543_2_i), .IN1(1'b1), .IN2(~na1543_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1543_5 ( .OUT(na1543_2), .CLK(na1739_1), .EN(na817_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1543_2_i) ); +// C_XOR/D//AND/D x68y46 80'h00_FA00_80_0000_0C68_CA3F +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1544_1 ( .OUT(na1544_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4467_2), .IN6(1'b0), .IN7(1'b0), .IN8(na1544_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1544_2 ( .OUT(na1544_1), .CLK(na1739_1), .EN(na526_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1544_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1544_4 ( .OUT(na1544_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1544_5 ( .OUT(na1544_2), .CLK(na1739_1), .EN(na526_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1544_2_i) ); +// C_XOR/D//AND/D x40y48 80'h00_FA00_80_0000_0C68_CA3F +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a1545_1 ( .OUT(na1545_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4468_2), .IN6(1'b0), .IN7(1'b0), .IN8(na1545_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1545_2 ( .OUT(na1545_1), .CLK(na1739_1), .EN(na194_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1545_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1545_4 ( .OUT(na1545_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1545_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1545_5 ( .OUT(na1545_2), .CLK(na1739_1), .EN(na194_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1545_2_i) ); +// C_OR//// x23y91 80'h00_0018_00_0000_0EEE_7577 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1564_1 ( .OUT(na1564_1), .IN1(~na4045_2), .IN2(~na225_2), .IN3(~na1340_1), .IN4(~na3268_1), .IN5(~na4045_1), .IN6(1'b0), + .IN7(~na4046_1), .IN8(~na3268_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND*////D x20y53 80'h00_FE18_00_0000_0788_CB3B +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a1567_1 ( .OUT(na1567_1), .IN1(na301_1), .IN2(~na957_2), .IN3(1'b0), .IN4(~na200_1), .IN5(na307_1), .IN6(~na4416_2), .IN7(1'b0), + .IN8(na1608_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1567_5 ( .OUT(na1567_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1567_1) ); +// C_OR//// x44y53 80'h00_0018_00_0000_0EEE_5777 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1570_1 ( .OUT(na1570_1), .IN1(~na3296_1), .IN2(~na4053_2), .IN3(~na4054_2), .IN4(~na340_2), .IN5(~na3296_2), .IN6(~na4053_1), + .IN7(~na332_1), .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x64y89 80'h00_0018_00_0000_0EEE_7757 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1574_1 ( .OUT(na1574_1), .IN1(~na3322_1), .IN2(~na4058_2), .IN3(~na449_2), .IN4(1'b0), .IN5(~na3322_2), .IN6(~na4058_1), + .IN7(~na4059_2), .IN8(~na518_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x64y72 80'h00_0018_00_0040_0C98_C300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1576_1 ( .OUT(na1576_1), .IN1(1'b1), .IN2(1'b0), .IN3(1'b0), .IN4(~na1990_1), .IN5(1'b1), .IN6(~na1989_2), .IN7(1'b1), .IN8(na1990_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x64y67 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1577_1 ( .OUT(na1577_1), .IN1(~na4489_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1576_1), .IN5(na486_1), .IN6(na1993_1), .IN7(na4491_2), + .IN8(na4213_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x66y63 80'h00_0018_00_0040_0C0C_F400 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1578_1 ( .OUT(na1578_1), .IN1(1'b0), .IN2(1'b0), .IN3(na1577_1), .IN4(na485_1), .IN5(~na4489_2), .IN6(na1993_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x49y53 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1579_1 ( .OUT(na1579_1_i), .IN1(1'b1), .IN2(~na4424_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1578_1), .IN8(na3712_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1579_2 ( .OUT(na1579_1), .CLK(na1739_1), .EN(~na1405_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1579_1_i) ); +// C_MX4a//// x70y59 80'h00_0018_00_0040_0C43_3300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1580_1 ( .OUT(na1580_1), .IN1(na567_1), .IN2(na559_1), .IN3(1'b1), .IN4(1'b0), .IN5(1'b1), .IN6(~na2350_2), .IN7(1'b1), .IN8(~na519_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b////D x70y64 80'h00_F618_00_0040_0A58_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1581_1 ( .OUT(na1581_1), .IN1(1'b1), .IN2(na4220_2), .IN3(na1580_1), .IN4(1'b1), .IN5(na543_1), .IN6(1'b0), .IN7(na551_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1581_5 ( .OUT(na1581_2), .CLK(na1739_1), .EN(~na575_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1581_1) ); +// C_MX4a//// x62y60 80'h00_0018_00_0040_0C62_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1582_1 ( .OUT(na1582_1), .IN1(1'b0), .IN2(~na2228_2), .IN3(1'b1), .IN4(1'b0), .IN5(na2229_2), .IN6(1'b1), .IN7(na2226_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x53y59 80'h00_0018_00_0040_0AF0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1583_1 ( .OUT(na1583_1), .IN1(na2229_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1582_1), .IN5(na4512_2), .IN6(na664_1), .IN7(na4257_2), + .IN8(na2230_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x53y58 80'h00_0018_00_0040_0C03_0400 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1584_1 ( .OUT(na1584_1), .IN1(na1583_1), .IN2(na663_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na2229_2), .IN6(na4509_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x48y44 80'h00_F600_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1585_1 ( .OUT(na1585_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4432_2), .IN5(1'b0), .IN6(na1584_1), .IN7(1'b0), .IN8(na3720_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1585_2 ( .OUT(na1585_1), .CLK(na1739_1), .EN(~na1408_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1585_1_i) ); +// C_MX4a//// x72y44 80'h00_0018_00_0040_0C25_5300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1586_1 ( .OUT(na1586_1), .IN1(na752_1), .IN2(1'b1), .IN3(na744_1), .IN4(1'b0), .IN5(1'b1), .IN6(~na2246_2), .IN7(~na4261_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b////D x71y44 80'h00_F618_00_0040_0A58_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1587_1 ( .OUT(na1587_1), .IN1(1'b1), .IN2(na2246_2), .IN3(1'b1), .IN4(na1586_1), .IN5(na4267_2), .IN6(1'b0), .IN7(na736_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1587_5 ( .OUT(na1587_2), .CLK(na1739_1), .EN(~na761_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1587_1) ); +// C_MX4a//// x14y53 80'h00_0018_00_0040_0C62_CC00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1588_1 ( .OUT(na1588_1), .IN1(1'b0), .IN2(~na2478_1), .IN3(1'b1), .IN4(1'b0), .IN5(1'b1), .IN6(na2478_2), .IN7(1'b1), .IN8(na4525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x17y49 80'h00_0018_00_0040_0AF0_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1589_1 ( .OUT(na1589_1), .IN1(1'b1), .IN2(~na2478_2), .IN3(na1588_1), .IN4(1'b1), .IN5(na843_1), .IN6(na4533_2), .IN7(na2481_1), + .IN8(na4295_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x21y46 80'h00_0018_00_0040_0C03_0200 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1590_1 ( .OUT(na1590_1), .IN1(na1589_1), .IN2(na842_1), .IN3(1'b0), .IN4(1'b0), .IN5(na4534_2), .IN6(~na2478_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x22y42 80'h00_F600_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1591_1 ( .OUT(na1591_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na4442_2), .IN5(1'b0), .IN6(na1590_1), .IN7(1'b0), .IN8(na3526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1591_2 ( .OUT(na1591_1), .CLK(na1739_1), .EN(~na1403_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1591_1_i) ); +// C_MX4a//// x41y51 80'h00_0018_00_0040_0C83_3C00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1592_1 ( .OUT(na1592_1), .IN1(na908_1), .IN2(na916_1), .IN3(1'b0), .IN4(1'b1), .IN5(1'b1), .IN6(na881_2), .IN7(1'b1), .IN8(~na2497_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b////D x39y52 80'h00_F618_00_0040_0A38_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1593_1 ( .OUT(na1593_1), .IN1(na1592_1), .IN2(1'b1), .IN3(1'b1), .IN4(na2497_1), .IN5(na4304_2), .IN6(na900_1), .IN7(1'b0), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1593_5 ( .OUT(na1593_2), .CLK(na1739_1), .EN(~na924_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1593_1) ); +// C_MX4a//// x40y83 80'h00_0018_00_0040_0C91_C300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1594_1 ( .OUT(na1594_1), .IN1(~na2712_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b1), .IN5(1'b1), .IN6(~na4553_2), .IN7(1'b1), .IN8(na2710_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x41y79 80'h00_0018_00_0040_0AF0_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1595_1 ( .OUT(na1595_1), .IN1(1'b1), .IN2(na4553_2), .IN3(na1594_1), .IN4(1'b1), .IN5(na2714_1), .IN6(na1016_1), .IN7(na4336_2), + .IN8(na4554_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x38y77 80'h00_0018_00_0040_0C05_4000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1596_1 ( .OUT(na1596_1), .IN1(na1595_1), .IN2(1'b0), .IN3(na1015_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na2713_2), + .IN8(na4552_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b/D/// x36y68 80'h00_F600_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1597_1 ( .OUT(na1597_1_i), .IN1(1'b1), .IN2(~na232_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1596_1), .IN8(na3414_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1597_2 ( .OUT(na1597_1), .CLK(na1739_1), .EN(~na1402_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1597_1_i) ); +// C_MX4a//// x57y85 80'h00_0018_00_0040_0C43_3300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1598_1 ( .OUT(na1598_1), .IN1(na1076_1), .IN2(na4350_2), .IN3(1'b1), .IN4(1'b0), .IN5(1'b1), .IN6(~na1044_2), .IN7(1'b1), + .IN8(~na2730_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b////D x54y85 80'h00_F618_00_0040_0A34_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1599_1 ( .OUT(na1599_1), .IN1(~na1598_1), .IN2(1'b1), .IN3(1'b1), .IN4(na2730_2), .IN5(na1060_1), .IN6(na1052_1), .IN7(1'b1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1599_5 ( .OUT(na1599_2), .CLK(na1739_1), .EN(~na1084_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1599_1) ); +// C_MX4a//// x58y89 80'h00_0018_00_0040_0C91_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1600_1 ( .OUT(na1600_1), .IN1(~na2962_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b1), .IN5(~na2962_2), .IN6(1'b1), .IN7(na2961_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x53y83 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1601_1 ( .OUT(na1601_1), .IN1(~na2962_2), .IN2(1'b1), .IN3(na1600_1), .IN4(1'b1), .IN5(na4368_2), .IN6(na2965_1), .IN7(na4573_2), + .IN8(na1167_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x56y79 80'h00_0018_00_0040_0C03_0400 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1602_1 ( .OUT(na1602_1), .IN1(na1601_1), .IN2(na1166_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na2962_2), .IN6(na2965_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a/D/// x43y59 80'h00_F600_00_0040_0C0C_F500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a1603_1 ( .OUT(na1603_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(na1602_1), .IN4(na3427_1), .IN5(~na456_1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1603_2 ( .OUT(na1603_1), .CLK(na1739_1), .EN(~na1400_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1603_1_i) ); +// C_MX4a//// x52y73 80'h00_0018_00_0040_0C1C_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a1604_1 ( .OUT(na1604_1), .IN1(1'b1), .IN2(1'b0), .IN3(na4391_2), .IN4(na1216_1), .IN5(~na1192_2), .IN6(1'b1), .IN7(na4577_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b////D x54y78 80'h00_F618_00_0040_0AA4_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1605_1 ( .OUT(na1605_1), .IN1(1'b1), .IN2(~na2981_1), .IN3(na1604_1), .IN4(1'b1), .IN5(1'b0), .IN6(na4373_2), .IN7(1'b1), + .IN8(na1208_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1605_5 ( .OUT(na1605_2), .CLK(na1739_1), .EN(~na1232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1605_1) ); +// C_OR//// x14y54 80'h00_0018_00_0000_0EEE_7775 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1608_1 ( .OUT(na1608_1), .IN1(~na4063_1), .IN2(1'b0), .IN3(~na4050_1), .IN4(~na303_2), .IN5(~na4063_2), .IN6(~na4064_1), + .IN7(~na4050_2), .IN8(~na124_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x14y62 80'h00_0078_00_0020_0C66_530C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1610_1 ( .OUT(na1610_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na2_2), .IN7(~na318_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1612_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1610_4 ( .OUT(na1610_2), .COUTY1(na1610_4), .IN1(1'b1), .IN2(na2_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na2_2), .IN7(~na318_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na1612_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x14y61 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1612_2 ( .OUT(na1612_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1612_6 ( .COUTY1(na1612_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1612_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_Route1//// x14y63 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a1613_1 ( .OUT(na1613_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1610_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x13y59 80'h00_0078_00_0020_0C66_A3C0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1614_1 ( .OUT(na1614_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na405_2), .IN7(na317_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1616_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1614_4 ( .OUT(na1614_2), .COUTY1(na1614_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na26_1), .IN5(1'b1), .IN6(~na405_2), + .IN7(na317_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1616_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x13y58 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1616_2 ( .OUT(na1616_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1616_6 ( .COUTY1(na1616_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1616_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_Route1//// x13y60 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a1617_1 ( .OUT(na1617_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1614_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x15y83 80'h00_0078_00_0020_0C66_CCCF +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1618_1 ( .OUT(na1618_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na288_1), .IN7(1'b1), .IN8(na1385_2), + .CINX(1'b0), .CINY1(na1627_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1618_4 ( .OUT(na1618_2), .COUTY1(na1618_4), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1385_1), .IN5(1'b1), .IN6(na288_1), + .IN7(1'b1), .IN8(na1385_2), .CINX(1'b0), .CINY1(na1627_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x15y84 80'h00_0078_00_0020_0C66_AFCF +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1620_1 ( .OUT(na1620_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(na287_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1618_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1620_4 ( .OUT(na1620_2), .COUTY1(na1620_4), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na289_1), .IN5(1'b1), .IN6(1'b1), .IN7(na287_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na1618_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x15y85 80'h00_0078_00_0020_0C66_CFCF +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1622_1 ( .OUT(na1622_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na292_2), + .CINX(1'b0), .CINY1(na1620_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1622_4 ( .OUT(na1622_2), .COUTY1(na1622_4), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na292_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(na292_2), .CINX(1'b0), .CINY1(na1620_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x15y86 80'h00_0078_00_0020_0C66_FCAF +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1624_1 ( .OUT(na1624_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na293_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1622_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1624_4 ( .OUT(na1624_2), .COUTY1(na1624_4), .IN1(1'b1), .IN2(1'b1), .IN3(na294_2), .IN4(1'b1), .IN5(1'b1), .IN6(na293_2), + .IN7(1'b1), .IN8(1'b1), .CINX(1'b0), .CINY1(na1622_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x15y87 80'h00_0018_00_0010_0666_00FC +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1626_1 ( .OUT(na1626_1), .IN1(1'b1), .IN2(na288_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1624_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x15y82 80'h00_3F00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1627_2 ( .OUT(na1627_1), .CLK(1'b1), .EN(1'b0), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1627_6 ( .COUTY1(na1627_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1627_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x60y76 80'h00_0078_00_0020_0C66_CA0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1628_1 ( .OUT(na1628_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4095_2), .IN6(1'b1), .IN7(1'b1), .IN8(na104_1), + .CINX(1'b0), .CINY1(na1632_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1628_4 ( .OUT(na1628_2), .COUTY1(na1628_4), .IN1(na109_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na4095_2), .IN6(1'b1), + .IN7(1'b1), .IN8(na104_1), .CINX(1'b0), .CINY1(na1632_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x60y77 80'h00_0078_00_0020_0C66_0CC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1630_1 ( .OUT(na1630_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na428_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1628_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1630_4 ( .OUT(na1630_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na108_1), .IN5(1'b1), .IN6(na428_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1628_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x60y75 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1632_2 ( .OUT(na1632_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1632_6 ( .COUTY1(na1632_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1632_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x67y89 80'h00_0078_00_0020_0C66_CCC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1633_1 ( .OUT(na1633_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na825_1), .IN7(1'b1), .IN8(na826_2), + .CINX(1'b0), .CINY1(na1638_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1633_4 ( .OUT(na1633_2), .COUTY1(na1633_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na826_1), .IN5(1'b1), .IN6(na825_1), + .IN7(1'b1), .IN8(na826_2), .CINX(1'b0), .CINY1(na1638_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x67y90 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1635_1 ( .OUT(na1635_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1307_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1633_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1635_4 ( .OUT(na1635_2), .COUTY1(na1635_4), .IN1(1'b1), .IN2(na1307_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1307_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na1633_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x67y91 80'h00_0018_00_0010_0666_00C0 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1637_1 ( .OUT(na1637_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1306_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1635_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x67y88 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1638_2 ( .OUT(na1638_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1638_6 ( .COUTY1(na1638_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1638_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x63y48 80'h00_0078_00_0020_0C66_AC0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1639_1 ( .OUT(na1639_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na88_2), .IN7(na87_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1648_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1639_4 ( .OUT(na1639_2), .COUTY1(na1639_4), .IN1(1'b1), .IN2(na88_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na88_2), .IN7(na87_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na1648_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x63y49 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1641_1 ( .OUT(na1641_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na89_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1639_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1641_4 ( .OUT(na1641_2), .IN1(1'b1), .IN2(na89_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na89_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1639_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x64y81 80'h00_0078_00_0020_0C66_AA0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1643_1 ( .OUT(na1643_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na360_2), .IN6(1'b1), .IN7(na246_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1652_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1643_4 ( .OUT(na1643_2), .COUTY1(na1643_4), .IN1(na360_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na360_2), .IN6(1'b1), + .IN7(na246_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na1652_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x64y82 80'h00_0018_00_0010_0666_00A0 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1645_1 ( .OUT(na1645_1), .IN1(1'b0), .IN2(1'b0), .IN3(na38_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1643_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x52y80 80'h00_0078_00_0020_0C66_CACC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1646_1 ( .OUT(na1646_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1192_2), .IN6(1'b1), .IN7(1'b1), .IN8(na986_2), + .CINX(1'b0), .CINY1(na1657_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1646_4 ( .OUT(na1646_2), .COUTY1(na1646_4), .IN1(1'b1), .IN2(na2981_1), .IN3(1'b1), .IN4(na986_1), .IN5(na1192_2), .IN6(1'b1), + .IN7(1'b1), .IN8(na986_2), .CINX(1'b0), .CINY1(na1657_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x63y47 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1648_2 ( .OUT(na1648_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1648_6 ( .COUTY1(na1648_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1648_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x56y90 80'h00_0078_00_0020_0C66_ACC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1649_1 ( .OUT(na1649_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na510_1), .IN7(na980_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1664_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1649_4 ( .OUT(na1649_2), .COUTY1(na1649_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na986_2), .IN5(1'b1), .IN6(na510_1), + .IN7(na980_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1664_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x56y91 80'h00_0018_00_0010_0666_00C0 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1651_1 ( .OUT(na1651_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na986_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1649_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x64y80 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1652_2 ( .OUT(na1652_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1652_6 ( .COUTY1(na1652_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1652_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x14y57 80'h00_0078_00_0020_0C66_CC0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1653_1 ( .OUT(na1653_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na927_2), .IN7(1'b1), .IN8(na1303_1), + .CINX(1'b0), .CINY1(na1665_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1653_4 ( .OUT(na1653_2), .COUTY1(na1653_4), .IN1(1'b1), .IN2(na927_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na927_2), + .IN7(1'b1), .IN8(na1303_1), .CINX(1'b0), .CINY1(na1665_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x14y58 80'h00_0078_00_0020_0C66_0A0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1655_1 ( .OUT(na1655_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1304_2), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1653_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1655_4 ( .OUT(na1655_2), .IN1(na1304_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na1304_2), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1653_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x52y79 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1657_2 ( .OUT(na1657_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1657_6 ( .COUTY1(na1657_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1657_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x31y71 80'h00_0078_00_0020_0C66_CA0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1658_1 ( .OUT(na1658_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4331_2), .IN6(1'b1), .IN7(1'b1), .IN8(na926_1), + .CINX(1'b0), .CINY1(na1673_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1658_4 ( .OUT(na1658_2), .COUTY1(na1658_4), .IN1(1'b1), .IN2(na929_1), .IN3(1'b0), .IN4(1'b0), .IN5(na4331_2), .IN6(1'b1), + .IN7(1'b1), .IN8(na926_1), .CINX(1'b0), .CINY1(na1673_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x31y72 80'h00_0078_00_0020_0C66_0A0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1660_1 ( .OUT(na1660_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1302_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1658_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1660_4 ( .OUT(na1660_2), .IN1(na1301_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na1302_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1658_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x67y69 80'h00_0078_00_0020_0C66_AACA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1662_1 ( .OUT(na1662_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na360_1), .IN6(1'b1), .IN7(na4519_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1677_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1662_4 ( .OUT(na1662_2), .COUTY1(na1662_4), .IN1(na4077_2), .IN2(1'b1), .IN3(1'b1), .IN4(na519_2), .IN5(na360_1), .IN6(1'b1), + .IN7(na4519_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1677_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x56y89 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1664_2 ( .OUT(na1664_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1664_6 ( .COUTY1(na1664_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1664_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x14y56 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1665_2 ( .OUT(na1665_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1665_6 ( .COUTY1(na1665_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1665_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x17y89 80'h00_0078_00_0020_0C66_ACA0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1666_1 ( .OUT(na1666_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na387_2), .IN7(na388_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1682_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1666_4 ( .OUT(na1666_2), .COUTY1(na1666_4), .IN1(1'b0), .IN2(1'b0), .IN3(na388_1), .IN4(1'b1), .IN5(1'b1), .IN6(na387_2), + .IN7(na388_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1682_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x17y90 80'h00_0078_00_0020_0C66_0A0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1668_1 ( .OUT(na1668_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na390_2), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1666_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1668_4 ( .OUT(na1668_2), .COUTY1(na1668_4), .IN1(na390_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na390_2), .IN6(1'b1), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na1666_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x17y91 80'h00_0018_00_0010_0666_000C +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1670_1 ( .OUT(na1670_1), .IN1(1'b1), .IN2(na391_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1668_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x46y89 80'h00_0078_00_0020_0C66_CACA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1671_1 ( .OUT(na1671_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na434_2), .IN6(1'b1), .IN7(1'b1), .IN8(na4340_2), + .CINX(1'b0), .CINY1(na1687_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1671_4 ( .OUT(na1671_2), .COUTY1(na1671_4), .IN1(na434_1), .IN2(1'b1), .IN3(1'b1), .IN4(na2730_2), .IN5(na434_2), .IN6(1'b1), + .IN7(1'b1), .IN8(na4340_2), .CINX(1'b0), .CINY1(na1687_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x31y70 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1673_2 ( .OUT(na1673_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1673_6 ( .COUTY1(na1673_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1673_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x30y88 80'h00_0078_00_0020_0C66_AA0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1674_1 ( .OUT(na1674_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4145_2), .IN6(1'b1), .IN7(na432_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1693_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1674_4 ( .OUT(na1674_2), .COUTY1(na1674_4), .IN1(na434_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na4145_2), .IN6(1'b1), + .IN7(na432_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1693_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x30y89 80'h00_0018_00_0010_0666_000A +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1676_1 ( .OUT(na1676_1), .IN1(na434_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1674_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x67y68 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1677_2 ( .OUT(na1677_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1677_6 ( .COUTY1(na1677_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1677_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x44y84 80'h00_0078_00_0020_0C66_AC0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1678_1 ( .OUT(na1678_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na403_2), .IN7(na402_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1701_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1678_4 ( .OUT(na1678_2), .COUTY1(na1678_4), .IN1(1'b1), .IN2(na403_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na403_2), + .IN7(na402_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1701_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x44y85 80'h00_0078_00_0020_0C66_C0C0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1680_1 ( .OUT(na1680_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na1330_2), + .CINX(1'b0), .CINY1(na1678_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1680_4 ( .OUT(na1680_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1330_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na1330_2), + .CINX(1'b0), .CINY1(na1678_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x17y88 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1682_2 ( .OUT(na1682_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1682_6 ( .COUTY1(na1682_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1682_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x40y86 80'h00_0078_00_0020_0C66_CA0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1683_1 ( .OUT(na1683_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4407_2), .IN6(1'b1), .IN7(1'b1), .IN8(na409_1), + .CINX(1'b0), .CINY1(na1704_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1683_4 ( .OUT(na1683_2), .COUTY1(na1683_4), .IN1(1'b1), .IN2(na1325_1), .IN3(1'b0), .IN4(1'b0), .IN5(na4407_2), .IN6(1'b1), + .IN7(1'b1), .IN8(na409_1), .CINX(1'b0), .CINY1(na1704_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x40y87 80'h00_0078_00_0020_0C66_0AC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1685_1 ( .OUT(na1685_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na410_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1683_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1685_4 ( .OUT(na1685_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na429_1), .IN5(na410_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1683_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x46y88 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1687_2 ( .OUT(na1687_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1687_6 ( .COUTY1(na1687_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1687_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x18y47 80'h00_0078_00_0020_0C66_CAC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1688_1 ( .OUT(na1688_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na173_1), .IN6(1'b1), .IN7(1'b1), .IN8(na190_2), + .CINX(1'b0), .CINY1(na1708_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1688_4 ( .OUT(na1688_2), .COUTY1(na1688_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na190_1), .IN5(na173_1), .IN6(1'b1), + .IN7(1'b1), .IN8(na190_2), .CINX(1'b0), .CINY1(na1708_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x18y48 80'h00_0078_00_0020_0C66_0A0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1690_1 ( .OUT(na1690_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na192_2), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1688_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1690_4 ( .OUT(na1690_2), .COUTY1(na1690_4), .IN1(na192_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na192_2), .IN6(1'b1), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na1688_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x18y49 80'h00_0018_00_0010_0666_000C +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1692_1 ( .OUT(na1692_1), .IN1(1'b1), .IN2(na193_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1690_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x30y87 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1693_2 ( .OUT(na1693_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1693_6 ( .COUTY1(na1693_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1693_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x69y85 80'h00_0078_00_0020_0C66_CCC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1694_1 ( .OUT(na1694_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na75_1), .IN7(1'b1), .IN8(na76_2), + .CINX(1'b0), .CINY1(na1713_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1694_4 ( .OUT(na1694_2), .COUTY1(na1694_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na76_1), .IN5(1'b1), .IN6(na75_1), .IN7(1'b1), + .IN8(na76_2), .CINX(1'b0), .CINY1(na1713_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x69y86 80'h00_0078_00_0020_0C66_C0C0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1696_1 ( .OUT(na1696_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na78_2), + .CINX(1'b0), .CINY1(na1694_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1696_4 ( .OUT(na1696_2), .COUTY1(na1696_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na78_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na78_2), .CINX(1'b0), .CINY1(na1694_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x69y87 80'h00_0018_00_0010_0666_00C0 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1698_1 ( .OUT(na1698_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na79_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1696_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x64y48 80'h00_0078_00_0020_0C66_AAAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1699_1 ( .OUT(na1699_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na704_2), .IN6(1'b1), .IN7(na297_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1721_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1699_4 ( .OUT(na1699_2), .COUTY1(na1699_4), .IN1(1'b1), .IN2(na2246_2), .IN3(na297_1), .IN4(1'b1), .IN5(na704_2), .IN6(1'b1), + .IN7(na297_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1721_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x44y83 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1701_2 ( .OUT(na1701_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1701_6 ( .COUTY1(na1701_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1701_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x47y54 80'h00_0078_00_0020_0C66_AACA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1702_1 ( .OUT(na1702_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na216_2), .IN6(1'b1), .IN7(na4302_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1727_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1702_4 ( .OUT(na1702_2), .COUTY1(na1702_4), .IN1(na216_1), .IN2(1'b1), .IN3(1'b1), .IN4(na2497_1), .IN5(na216_2), .IN6(1'b1), + .IN7(na4302_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na1727_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x40y85 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1704_2 ( .OUT(na1704_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1704_6 ( .COUTY1(na1704_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1704_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x30y60 80'h00_0078_00_0020_0C66_CA0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1705_1 ( .OUT(na1705_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na114_1), .IN6(1'b1), .IN7(1'b1), .IN8(na214_1), + .CINX(1'b0), .CINY1(na1732_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1705_4 ( .OUT(na1705_2), .COUTY1(na1705_4), .IN1(na216_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na114_1), .IN6(1'b1), + .IN7(1'b1), .IN8(na214_1), .CINX(1'b0), .CINY1(na1732_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x30y61 80'h00_0018_00_0010_0666_000A +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1707_1 ( .OUT(na1707_1), .IN1(na216_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1705_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x18y46 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1708_2 ( .OUT(na1708_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1708_6 ( .COUTY1(na1708_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1708_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x46y45 80'h00_0078_00_0020_0C66_AC0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1709_1 ( .OUT(na1709_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na204_2), .IN7(na201_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na3234_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1709_4 ( .OUT(na1709_2), .COUTY1(na1709_4), .IN1(1'b1), .IN2(na204_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na204_2), + .IN7(na201_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na3234_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x46y46 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1711_1 ( .OUT(na1711_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na207_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1709_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1711_4 ( .OUT(na1711_2), .IN1(1'b1), .IN2(na207_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na207_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1709_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x69y84 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1713_2 ( .OUT(na1713_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1713_6 ( .COUTY1(na1713_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1713_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x13y50 80'h00_0078_00_0020_0C66_CC0A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1714_1 ( .OUT(na1714_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na209_1), .IN7(1'b1), .IN8(na208_1), + .CINX(1'b0), .CINY1(na3235_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1714_4 ( .OUT(na1714_2), .COUTY1(na1714_4), .IN1(na210_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na209_1), + .IN7(1'b1), .IN8(na208_1), .CINX(1'b0), .CINY1(na3235_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x13y51 80'h00_0078_00_0020_0C66_A00C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1716_1 ( .OUT(na1716_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na211_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1714_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1716_4 ( .OUT(na1716_2), .IN1(1'b1), .IN2(na1353_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na211_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1714_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x56y66 80'h00_0078_00_0020_0C66_CCA0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1718_1 ( .OUT(na1718_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na295_1), .IN7(1'b1), .IN8(na4171_2), + .CINX(1'b0), .CINY1(na3247_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1718_4 ( .OUT(na1718_2), .COUTY1(na1718_4), .IN1(1'b0), .IN2(1'b0), .IN3(na297_2), .IN4(1'b1), .IN5(1'b1), .IN6(na295_1), + .IN7(1'b1), .IN8(na4171_2), .CINX(1'b0), .CINY1(na3247_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x56y67 80'h00_0018_00_0010_0666_00A0 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1720_1 ( .OUT(na1720_1), .IN1(1'b0), .IN2(1'b0), .IN3(na297_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1718_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x64y47 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1721_2 ( .OUT(na1721_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1721_6 ( .COUTY1(na1721_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1721_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x24y57 80'h00_0078_00_0020_0C66_AC0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1722_1 ( .OUT(na1722_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na265_2), .IN7(na264_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na3260_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1722_4 ( .OUT(na1722_2), .COUTY1(na1722_4), .IN1(1'b1), .IN2(na265_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na265_2), + .IN7(na264_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na3260_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x24y58 80'h00_0078_00_0020_0C66_C0C0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1724_1 ( .OUT(na1724_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na270_2), + .CINX(1'b0), .CINY1(na1722_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1724_4 ( .OUT(na1724_2), .COUTY1(na1724_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na270_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na270_2), .CINX(1'b0), .CINY1(na1722_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x24y59 80'h00_0018_00_0010_0666_000C +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a1726_1 ( .OUT(na1726_1), .IN1(1'b1), .IN2(na268_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1724_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x47y53 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1727_2 ( .OUT(na1727_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1727_6 ( .COUTY1(na1727_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1727_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x38y62 80'h00_0078_00_0020_0C66_CAA0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1728_1 ( .OUT(na1728_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1387_1), .IN6(1'b1), .IN7(1'b1), .IN8(na282_1), + .CINX(1'b0), .CINY1(na3267_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1728_4 ( .OUT(na1728_2), .COUTY1(na1728_4), .IN1(1'b0), .IN2(1'b0), .IN3(na283_1), .IN4(1'b1), .IN5(na1387_1), .IN6(1'b1), + .IN7(1'b1), .IN8(na282_1), .CINX(1'b0), .CINY1(na3267_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x38y63 80'h00_0078_00_0020_0C66_0CC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1730_1 ( .OUT(na1730_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1386_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1728_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1730_4 ( .OUT(na1730_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na284_1), .IN5(1'b1), .IN6(na1386_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1728_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x30y59 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1732_2 ( .OUT(na1732_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1732_6 ( .COUTY1(na1732_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1732_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x62y37 80'h00_0078_00_0020_0C66_CC0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1733_1 ( .OUT(na1733_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na274_2), .IN7(1'b1), .IN8(na277_1), + .CINX(1'b0), .CINY1(na3281_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1733_4 ( .OUT(na1733_2), .COUTY1(na1733_4), .IN1(1'b1), .IN2(na274_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na274_2), + .IN7(1'b1), .IN8(na277_1), .CINX(1'b0), .CINY1(na3281_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x62y38 80'h00_0078_00_0020_0C66_A0A0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1735_1 ( .OUT(na1735_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na280_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1733_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1735_4 ( .OUT(na1735_2), .IN1(1'b0), .IN2(1'b0), .IN3(na280_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na280_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1733_4), .PINX(1'b0), .PINY1(1'b0) ); +GLBOUT #(.GLBOUT_CFG (64'h0000_0000_0010_0014)) + _a1739 ( .GLB0(na1739_1), .GLB1(na1739_2), .GLB2(_d0), .GLB3(_d1), .CLK_FB0(_d2), .CLK_FB1(_d3), .CLK_FB2(_d4), .CLK_FB3(_d5), + .CLK0_0(na3222_6), .CLK0_90(na3222_5), .CLK0_180(na3222_4), .CLK0_270(na3222_3), .CLK0_BYP(1'b0), .CLK1_0(1'b0), + .CLK1_90(1'b0), .CLK1_180(1'b0), .CLK1_270(1'b0), .CLK1_BYP(na3229_2), .CLK2_0(1'b0), .CLK2_90(1'b0), .CLK2_180(1'b0), + .CLK2_270(1'b0), .CLK2_BYP(1'b0), .CLK3_0(1'b0), .CLK3_90(1'b0), .CLK3_180(1'b0), .CLK3_270(1'b0), .CLK3_BYP(1'b0), + .USR_GLB0(1'b0), .USR_GLB1(1'b0), .USR_GLB2(1'b0), .USR_GLB3(1'b0), .USR_FB0(1'b0), .USR_FB1(1'b0), .USR_FB2(1'b0), + .USR_FB3(1'b0) ); +// C_AND/D//AND/D x53y40 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1741_1 ( .OUT(na1741_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3725_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1741_2 ( .OUT(na1741_1), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1741_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1741_4 ( .OUT(na1741_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3726_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1741_5 ( .OUT(na1741_2), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1741_2_i) ); +// C_AND/D//AND/D x51y38 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1743_1 ( .OUT(na1743_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3723_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1743_2 ( .OUT(na1743_1), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1743_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1743_4 ( .OUT(na1743_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3724_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1743_5 ( .OUT(na1743_2), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1743_2_i) ); +// C_AND/D//AND/D x57y42 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1745_1 ( .OUT(na1745_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3721_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1745_2 ( .OUT(na1745_1), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1745_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1745_4 ( .OUT(na1745_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3722_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1745_5 ( .OUT(na1745_2), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1745_2_i) ); +// C_AND/D//AND/D x59y42 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1747_1 ( .OUT(na1747_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3719_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1747_2 ( .OUT(na1747_1), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1747_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1747_4 ( .OUT(na1747_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3720_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1747_5 ( .OUT(na1747_2), .CLK(na1739_1), .EN(na1413_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1747_2_i) ); +// C_AND/D//AND/D x35y56 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1763_1 ( .OUT(na1763_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3443_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1763_2 ( .OUT(na1763_1), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1763_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1763_4 ( .OUT(na1763_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3444_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1763_5 ( .OUT(na1763_2), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1763_2_i) ); +// C_AND/D//AND/D x31y56 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1765_1 ( .OUT(na1765_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3439_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1765_2 ( .OUT(na1765_1), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1765_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1765_4 ( .OUT(na1765_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3442_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1765_5 ( .OUT(na1765_2), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1765_2_i) ); +// C_AND/D//AND/D x45y64 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1767_1 ( .OUT(na1767_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3429_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1767_2 ( .OUT(na1767_1), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1767_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1767_4 ( .OUT(na1767_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3430_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1767_5 ( .OUT(na1767_2), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1767_2_i) ); +// C_AND/D//AND/D x43y60 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1769_1 ( .OUT(na1769_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3426_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1769_2 ( .OUT(na1769_1), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1769_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1769_4 ( .OUT(na1769_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3427_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1769_5 ( .OUT(na1769_2), .CLK(na1739_1), .EN(na1423_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1769_2_i) ); +// C_AND/D//AND/D x41y58 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1771_1 ( .OUT(na1771_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3443_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1771_2 ( .OUT(na1771_1), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1771_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1771_4 ( .OUT(na1771_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3444_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1771_5 ( .OUT(na1771_2), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1771_2_i) ); +// C_AND/D//AND/D x39y58 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1773_1 ( .OUT(na1773_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3439_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1773_2 ( .OUT(na1773_1), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1773_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1773_4 ( .OUT(na1773_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3442_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1773_5 ( .OUT(na1773_2), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1773_2_i) ); +// C_AND/D//AND/D x39y60 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1775_1 ( .OUT(na1775_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3429_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1775_2 ( .OUT(na1775_1), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1775_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1775_4 ( .OUT(na1775_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3430_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1775_5 ( .OUT(na1775_2), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1775_2_i) ); +// C_AND/D//AND/D x35y54 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1777_1 ( .OUT(na1777_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3426_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1777_2 ( .OUT(na1777_1), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1777_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1777_4 ( .OUT(na1777_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3427_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1777_5 ( .OUT(na1777_2), .CLK(na1739_1), .EN(na1424_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1777_2_i) ); +// C_AND/D//AND/D x48y68 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1780_1 ( .OUT(na1780_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3423_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1780_2 ( .OUT(na1780_1), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1780_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1780_4 ( .OUT(na1780_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3424_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1780_5 ( .OUT(na1780_2), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1780_2_i) ); +// C_AND/D//AND/D x44y66 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1782_1 ( .OUT(na1782_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3420_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1782_2 ( .OUT(na1782_1), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1782_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1782_4 ( .OUT(na1782_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3421_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1782_5 ( .OUT(na1782_2), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1782_2_i) ); +// C_AND/D//AND/D x46y74 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1784_1 ( .OUT(na1784_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3416_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1784_2 ( .OUT(na1784_1), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1784_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1784_4 ( .OUT(na1784_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3417_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1784_5 ( .OUT(na1784_2), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1784_2_i) ); +// C_AND/D//AND/D x46y76 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1786_1 ( .OUT(na1786_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3413_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1786_2 ( .OUT(na1786_1), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1786_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1786_4 ( .OUT(na1786_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3414_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1786_5 ( .OUT(na1786_2), .CLK(na1739_1), .EN(na1420_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1786_2_i) ); +// C_AND/D//AND/D x48y66 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1788_1 ( .OUT(na1788_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3423_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1788_2 ( .OUT(na1788_1), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1788_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1788_4 ( .OUT(na1788_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3424_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1788_5 ( .OUT(na1788_2), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1788_2_i) ); +// C_AND/D//AND/D x46y70 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1790_1 ( .OUT(na1790_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3420_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1790_2 ( .OUT(na1790_1), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1790_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1790_4 ( .OUT(na1790_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3421_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1790_5 ( .OUT(na1790_2), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1790_2_i) ); +// C_AND/D//AND/D x48y72 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1792_1 ( .OUT(na1792_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3416_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1792_2 ( .OUT(na1792_1), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1792_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1792_4 ( .OUT(na1792_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3417_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1792_5 ( .OUT(na1792_2), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1792_2_i) ); +// C_AND/D//AND/D x46y66 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1794_1 ( .OUT(na1794_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3413_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1794_2 ( .OUT(na1794_1), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1794_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1794_4 ( .OUT(na1794_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3414_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1794_5 ( .OUT(na1794_2), .CLK(na1739_1), .EN(na1421_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1794_2_i) ); +// C_AND/D//AND/D x40y43 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1811_1 ( .OUT(na1811_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3531_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1811_2 ( .OUT(na1811_1), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1811_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1811_4 ( .OUT(na1811_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3532_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1811_5 ( .OUT(na1811_2), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1811_2_i) ); +// C_AND/D//AND/D x38y43 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1813_1 ( .OUT(na1813_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3529_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1813_2 ( .OUT(na1813_1), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1813_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1813_4 ( .OUT(na1813_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3530_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1813_5 ( .OUT(na1813_2), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1813_2_i) ); +// C_AND/D//AND/D x36y45 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1815_1 ( .OUT(na1815_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3527_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1815_2 ( .OUT(na1815_1), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1815_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1815_4 ( .OUT(na1815_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3528_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1815_5 ( .OUT(na1815_2), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1815_2_i) ); +// C_AND/D//AND/D x38y39 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1817_1 ( .OUT(na1817_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1817_2 ( .OUT(na1817_1), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1817_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1817_4 ( .OUT(na1817_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3526_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1817_5 ( .OUT(na1817_2), .CLK(na1739_1), .EN(na1417_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1817_2_i) ); +// C_AND/D//AND/D x26y39 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1819_1 ( .OUT(na1819_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3531_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1819_2 ( .OUT(na1819_1), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1819_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1819_4 ( .OUT(na1819_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3532_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1819_5 ( .OUT(na1819_2), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1819_2_i) ); +// C_AND/D//AND/D x24y39 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1821_1 ( .OUT(na1821_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3529_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1821_2 ( .OUT(na1821_1), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1821_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1821_4 ( .OUT(na1821_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3530_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1821_5 ( .OUT(na1821_2), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1821_2_i) ); +// C_AND/D//AND/D x40y45 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1823_1 ( .OUT(na1823_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3527_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1823_2 ( .OUT(na1823_1), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1823_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1823_4 ( .OUT(na1823_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3528_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1823_5 ( .OUT(na1823_2), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1823_2_i) ); +// C_AND/D//AND/D x38y47 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1825_1 ( .OUT(na1825_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1825_2 ( .OUT(na1825_1), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1825_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1825_4 ( .OUT(na1825_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3526_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1825_5 ( .OUT(na1825_2), .CLK(na1739_1), .EN(na1416_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1825_2_i) ); +// C_AND/D//AND/D x56y49 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1862_1 ( .OUT(na1862_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3717_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1862_2 ( .OUT(na1862_1), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1862_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1862_4 ( .OUT(na1862_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3718_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1862_5 ( .OUT(na1862_2), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1862_2_i) ); +// C_AND/D//AND/D x58y49 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1864_1 ( .OUT(na1864_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3715_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1864_2 ( .OUT(na1864_1), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1864_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1864_4 ( .OUT(na1864_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3716_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1864_5 ( .OUT(na1864_2), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1864_2_i) ); +// C_AND/D//AND/D x58y53 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1866_1 ( .OUT(na1866_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3713_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1866_2 ( .OUT(na1866_1), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1866_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1866_4 ( .OUT(na1866_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3714_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1866_5 ( .OUT(na1866_2), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1866_2_i) ); +// C_AND/D//AND/D x54y47 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1868_1 ( .OUT(na1868_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3711_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1868_2 ( .OUT(na1868_1), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1868_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1868_4 ( .OUT(na1868_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3712_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1868_5 ( .OUT(na1868_2), .CLK(na1739_1), .EN(na1411_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1868_2_i) ); +// C_AND/D//AND/D x59y40 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1878_1 ( .OUT(na1878_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3725_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1878_2 ( .OUT(na1878_1), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1878_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1878_4 ( .OUT(na1878_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3726_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1878_5 ( .OUT(na1878_2), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1878_2_i) ); +// C_AND/D//AND/D x57y38 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1880_1 ( .OUT(na1880_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3723_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1880_2 ( .OUT(na1880_1), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1880_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1880_4 ( .OUT(na1880_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3724_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1880_5 ( .OUT(na1880_2), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1880_2_i) ); +// C_AND/D//AND/D x57y40 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1882_1 ( .OUT(na1882_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3721_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1882_2 ( .OUT(na1882_1), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1882_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1882_4 ( .OUT(na1882_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3722_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1882_5 ( .OUT(na1882_2), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1882_2_i) ); +// C_AND/D//AND/D x55y40 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1884_1 ( .OUT(na1884_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3719_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1884_2 ( .OUT(na1884_1), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1884_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1884_4 ( .OUT(na1884_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3720_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1884_5 ( .OUT(na1884_2), .CLK(na1739_1), .EN(na1414_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1884_2_i) ); +// C_AND/D//AND/D x51y49 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1887_1 ( .OUT(na1887_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3717_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1887_2 ( .OUT(na1887_1), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1887_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1887_4 ( .OUT(na1887_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3718_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1887_5 ( .OUT(na1887_2), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1887_2_i) ); +// C_AND/D//AND/D x52y47 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1889_1 ( .OUT(na1889_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3715_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1889_2 ( .OUT(na1889_1), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1889_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1889_4 ( .OUT(na1889_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3716_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1889_5 ( .OUT(na1889_2), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1889_2_i) ); +// C_AND/D//AND/D x60y55 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1891_1 ( .OUT(na1891_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3713_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1891_2 ( .OUT(na1891_1), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1891_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1891_4 ( .OUT(na1891_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3714_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1891_5 ( .OUT(na1891_2), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1891_2_i) ); +// C_AND/D//AND/D x60y53 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1893_1 ( .OUT(na1893_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3711_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1893_2 ( .OUT(na1893_1), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1893_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1893_4 ( .OUT(na1893_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3712_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1893_5 ( .OUT(na1893_2), .CLK(na1739_1), .EN(na1410_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1893_2_i) ); +// C_///AND/D x52y60 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1984_4 ( .OUT(na1984_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3712_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1984_5 ( .OUT(na1984_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1984_2_i) ); +// C_AND/D/// x66y66 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1985_1 ( .OUT(na1985_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1891_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1985_2 ( .OUT(na1985_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1985_1_i) ); +// C_AND/D//AND/D x65y68 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1986_1 ( .OUT(na1986_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1891_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1986_2 ( .OUT(na1986_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1986_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1986_4 ( .OUT(na1986_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1893_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1986_5 ( .OUT(na1986_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1986_2_i) ); +// C_///AND/D x61y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1989_4 ( .OUT(na1989_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2120_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1989_5 ( .OUT(na1989_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1989_2_i) ); +// C_AND/D//AND/D x62y70 80'h00_FA00_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1990_1 ( .OUT(na1990_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2122_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1990_2 ( .OUT(na1990_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1990_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1990_4 ( .OUT(na1990_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2120_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1990_5 ( .OUT(na1990_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1990_2_i) ); +// C_AND/D/// x62y65 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1991_1 ( .OUT(na1991_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2122_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1991_2 ( .OUT(na1991_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1991_1_i) ); +// C_AND/D//AND/D x61y68 80'h00_FA00_80_0000_0C88_CFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1993_1 ( .OUT(na1993_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3711_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1993_2 ( .OUT(na1993_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1993_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1993_4 ( .OUT(na1993_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2124_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1993_5 ( .OUT(na1993_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1993_2_i) ); +// C_///AND/D x59y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1994_4 ( .OUT(na1994_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1866_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1994_5 ( .OUT(na1994_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1994_2_i) ); +// C_AND/D/// x55y54 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1995_1 ( .OUT(na1995_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1866_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1995_2 ( .OUT(na1995_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1995_1_i) ); +// C_///AND/D x53y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1996_4 ( .OUT(na1996_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1868_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1996_5 ( .OUT(na1996_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1996_2_i) ); +// C_AND/D/// x53y52 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1997_1 ( .OUT(na1997_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1868_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1997_2 ( .OUT(na1997_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1997_1_i) ); +// C_///AND/D x43y48 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1998_4 ( .OUT(na1998_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3718_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1998_5 ( .OUT(na1998_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1998_2_i) ); +// C_AND/D/// x54y57 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1999_1 ( .OUT(na1999_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2124_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1999_2 ( .OUT(na1999_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1999_1_i) ); +// C_///AND/D x50y52 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2000_4 ( .OUT(na2000_2_i), .IN1(na1887_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2000_5 ( .OUT(na2000_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2000_2_i) ); +// C_AND/D//AND/D x49y51 80'h00_FA00_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2001_1 ( .OUT(na2001_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1887_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2001_2 ( .OUT(na2001_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2001_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2001_4 ( .OUT(na2001_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1889_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2001_5 ( .OUT(na2001_2), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2001_2_i) ); +// C_AND/D/// x50y51 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2002_1 ( .OUT(na2002_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1889_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2002_2 ( .OUT(na2002_1), .CLK(na1739_1), .EN(na54_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2002_1_i) ); +// C_AND/D//AND/D x66y76 80'h00_F600_80_0000_0C88_CFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2011_1 ( .OUT(na2011_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2011_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2011_2 ( .OUT(na2011_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2011_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2011_4 ( .OUT(na2011_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2013_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2011_5 ( .OUT(na2011_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2011_2_i) ); +// C_AND/D//AND/D x60y65 80'h00_F600_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2013_1 ( .OUT(na2013_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2013_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2013_2 ( .OUT(na2013_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2013_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2013_4 ( .OUT(na2013_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2015_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2013_5 ( .OUT(na2013_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2013_2_i) ); +// C_AND/D//AND/D x50y60 80'h00_F600_80_0000_0C88_CFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2015_1 ( .OUT(na2015_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2015_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2015_2 ( .OUT(na2015_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2015_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2015_4 ( .OUT(na2015_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2017_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2015_5 ( .OUT(na2015_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2015_2_i) ); +// C_AND/D//AND/D x44y55 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2017_1 ( .OUT(na2017_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2017_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2017_2 ( .OUT(na2017_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2017_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2017_4 ( .OUT(na2017_2_i), .IN1(na2019_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2017_5 ( .OUT(na2017_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2017_2_i) ); +// C_AND/D//AND/D x21y57 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2019_1 ( .OUT(na2019_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2019_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2019_2 ( .OUT(na2019_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2019_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2019_4 ( .OUT(na2019_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2021_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2019_5 ( .OUT(na2019_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2019_2_i) ); +// C_AND/D//AND/D x16y47 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2021_1 ( .OUT(na2021_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2021_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2021_2 ( .OUT(na2021_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2021_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2021_4 ( .OUT(na2021_2_i), .IN1(na2023_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2021_5 ( .OUT(na2021_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2021_2_i) ); +// C_AND/D//AND/D x13y45 80'h00_F600_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2023_1 ( .OUT(na2023_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2023_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2023_2 ( .OUT(na2023_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2023_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2023_4 ( .OUT(na2023_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2025_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2023_5 ( .OUT(na2023_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2023_2_i) ); +// C_AND/D//AND/D x14y44 80'h00_F600_80_0000_0C88_CFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2025_1 ( .OUT(na2025_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2025_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2025_2 ( .OUT(na2025_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2025_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2025_4 ( .OUT(na2025_2_i), .IN1(1'b1), .IN2(na2027_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2025_5 ( .OUT(na2025_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2025_2_i) ); +// C_AND/D//AND/D x15y40 80'h00_F600_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2027_1 ( .OUT(na2027_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2027_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2027_2 ( .OUT(na2027_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2027_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2027_4 ( .OUT(na2027_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2029_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2027_5 ( .OUT(na2027_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2027_2_i) ); +// C_AND/D//AND/D x14y39 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2029_1 ( .OUT(na2029_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2029_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2029_2 ( .OUT(na2029_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2029_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2029_4 ( .OUT(na2029_2_i), .IN1(na2031_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2029_5 ( .OUT(na2029_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2029_2_i) ); +// C_AND/D//AND/D x13y37 80'h00_F600_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2031_1 ( .OUT(na2031_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2031_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2031_2 ( .OUT(na2031_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2031_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2031_4 ( .OUT(na2031_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2033_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2031_5 ( .OUT(na2031_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2031_2_i) ); +// C_AND/D//AND/D x14y42 80'h00_F600_80_0000_0C88_CFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2033_1 ( .OUT(na2033_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2033_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2033_2 ( .OUT(na2033_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2033_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2033_4 ( .OUT(na2033_2_i), .IN1(na2035_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2033_5 ( .OUT(na2033_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2033_2_i) ); +// C_AND/D//AND/D x15y45 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2035_1 ( .OUT(na2035_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2035_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2035_2 ( .OUT(na2035_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2035_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2035_4 ( .OUT(na2035_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2037_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2035_5 ( .OUT(na2035_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2035_2_i) ); +// C_AND/D//AND/D x24y61 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2037_1 ( .OUT(na2037_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2037_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2037_2 ( .OUT(na2037_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2037_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2037_4 ( .OUT(na2037_2_i), .IN1(na2039_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2037_5 ( .OUT(na2037_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2037_2_i) ); +// C_AND/D//AND/D x47y57 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2039_1 ( .OUT(na2039_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2039_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2039_2 ( .OUT(na2039_1), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2039_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2039_4 ( .OUT(na2039_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2041_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2039_5 ( .OUT(na2039_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2039_2_i) ); +// C_///AND/D x62y61 80'h00_F600_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2041_4 ( .OUT(na2041_2_i), .IN1(na525_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2041_5 ( .OUT(na2041_2), .CLK(na1739_1), .EN(~na1431_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2041_2_i) ); +// C_AND/D//AND/D x69y83 80'h00_FA00_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2091_1 ( .OUT(na2091_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2091_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2091_2 ( .OUT(na2091_1), .CLK(na1739_1), .EN(na1435_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2091_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2091_4 ( .OUT(na2091_2_i), .IN1(1'b1), .IN2(na2093_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2091_5 ( .OUT(na2091_2), .CLK(na1739_1), .EN(na1435_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2091_2_i) ); +// C_AND/D/// x69y82 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2093_1 ( .OUT(na2093_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na534_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2093_2 ( .OUT(na2093_1), .CLK(na1739_1), .EN(na1435_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2093_1_i) ); +// C_AND/D//AND/D x50y41 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2118_1 ( .OUT(na2118_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3717_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2118_2 ( .OUT(na2118_1), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2118_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2118_4 ( .OUT(na2118_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3718_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2118_5 ( .OUT(na2118_2), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2118_2_i) ); +// C_AND/D//AND/D x52y51 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2120_1 ( .OUT(na2120_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3715_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2120_2 ( .OUT(na2120_1), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2120_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2120_4 ( .OUT(na2120_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3716_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2120_5 ( .OUT(na2120_2), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2120_2_i) ); +// C_AND/D//AND/D x51y51 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2122_1 ( .OUT(na2122_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3713_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2122_2 ( .OUT(na2122_1), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2122_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2122_4 ( .OUT(na2122_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3714_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2122_5 ( .OUT(na2122_2), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2122_2_i) ); +// C_AND/D//AND/D x54y55 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2124_1 ( .OUT(na2124_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3711_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2124_2 ( .OUT(na2124_1), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2124_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2124_4 ( .OUT(na2124_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3712_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2124_5 ( .OUT(na2124_2), .CLK(na1739_1), .EN(na1409_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2124_2_i) ); +// C_AND/D//AND/D x69y58 80'h00_FE00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2125_1 ( .OUT(na2125_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2125_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2125_2 ( .OUT(na2125_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2125_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2125_4 ( .OUT(na2125_2_i), .IN1(1'b1), .IN2(na2127_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2125_5 ( .OUT(na2125_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2125_2_i) ); +// C_AND/D//AND/D x69y60 80'h00_FE00_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2127_1 ( .OUT(na2127_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2127_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2127_2 ( .OUT(na2127_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2127_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2127_4 ( .OUT(na2127_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2129_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2127_5 ( .OUT(na2127_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2127_2_i) ); +// C_AND/D//AND/D x70y63 80'h00_FE00_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2129_1 ( .OUT(na2129_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2129_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2129_2 ( .OUT(na2129_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2129_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2129_4 ( .OUT(na2129_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na597_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2129_5 ( .OUT(na2129_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2129_2_i) ); +// C_///AND/D x58y40 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2221_4 ( .OUT(na2221_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3720_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2221_5 ( .OUT(na2221_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2221_2_i) ); +// C_AND/D/// x67y53 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2222_1 ( .OUT(na2222_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1745_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2222_2 ( .OUT(na2222_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2222_1_i) ); +// C_AND/D//AND/D x68y51 80'h00_FA00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2223_1 ( .OUT(na2223_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1745_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2223_2 ( .OUT(na2223_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2223_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2223_4 ( .OUT(na2223_2_i), .IN1(1'b1), .IN2(na1747_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2223_5 ( .OUT(na2223_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2223_2_i) ); +// C_///AND/D x60y61 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2226_4 ( .OUT(na2226_2_i), .IN1(1'b1), .IN2(na2354_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2226_5 ( .OUT(na2226_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2226_2_i) ); +// C_AND/D//AND/D x55y60 80'h00_FA00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2228_1 ( .OUT(na2228_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2356_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2228_2 ( .OUT(na2228_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2228_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2228_4 ( .OUT(na2228_2_i), .IN1(1'b1), .IN2(na2356_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2228_5 ( .OUT(na2228_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2228_2_i) ); +// C_AND/D//AND/D x57y59 80'h00_FA00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2229_1 ( .OUT(na2229_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2358_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2229_2 ( .OUT(na2229_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2229_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2229_4 ( .OUT(na2229_2_i), .IN1(1'b1), .IN2(na2354_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2229_5 ( .OUT(na2229_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2229_2_i) ); +// C_AND/D/// x52y50 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2230_1 ( .OUT(na2230_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3719_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2230_2 ( .OUT(na2230_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2230_1_i) ); +// C_AND/D/// x61y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2231_1 ( .OUT(na2231_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1882_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2231_2 ( .OUT(na2231_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2231_1_i) ); +// C_AND/D/// x55y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2232_1 ( .OUT(na2232_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1882_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2232_2 ( .OUT(na2232_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2232_1_i) ); +// C_///AND/D x61y40 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2233_4 ( .OUT(na2233_2_i), .IN1(1'b1), .IN2(na1884_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2233_5 ( .OUT(na2233_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2233_2_i) ); +// C_AND/D/// x55y38 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2234_1 ( .OUT(na2234_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1884_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2234_2 ( .OUT(na2234_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2234_1_i) ); +// C_///AND/D x43y40 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2235_4 ( .OUT(na2235_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3726_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2235_5 ( .OUT(na2235_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2235_2_i) ); +// C_AND/D/// x52y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2236_1 ( .OUT(na2236_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2358_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2236_2 ( .OUT(na2236_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2236_1_i) ); +// C_///AND/D x56y40 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2237_4 ( .OUT(na2237_2_i), .IN1(1'b1), .IN2(na1741_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2237_5 ( .OUT(na2237_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2237_2_i) ); +// C_AND/D//AND/D x53y44 80'h00_FA00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2238_1 ( .OUT(na2238_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1741_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2238_2 ( .OUT(na2238_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2238_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2238_4 ( .OUT(na2238_2_i), .IN1(1'b1), .IN2(na1743_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2238_5 ( .OUT(na2238_2), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2238_2_i) ); +// C_AND/D/// x52y41 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2239_1 ( .OUT(na2239_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1743_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2239_2 ( .OUT(na2239_1), .CLK(na1739_1), .EN(na275_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2239_1_i) ); +// C_///AND/D x65y48 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2246_4 ( .OUT(na2246_2_i), .IN1(na704_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2246_5 ( .OUT(na2246_2), .CLK(na1739_1), .EN(na1458_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2246_2_i) ); +// C_AND/D//AND/D x57y62 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2248_1 ( .OUT(na2248_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2248_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2248_2 ( .OUT(na2248_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2248_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2248_4 ( .OUT(na2248_2_i), .IN1(na2250_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2248_5 ( .OUT(na2248_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2248_2_i) ); +// C_AND/D//AND/D x49y55 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2250_1 ( .OUT(na2250_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2250_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2250_2 ( .OUT(na2250_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2250_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2250_4 ( .OUT(na2250_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2252_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2250_5 ( .OUT(na2250_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2250_2_i) ); +// C_AND/D//AND/D x46y53 80'h00_F600_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2252_1 ( .OUT(na2252_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2252_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2252_2 ( .OUT(na2252_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2252_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2252_4 ( .OUT(na2252_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2254_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2252_5 ( .OUT(na2252_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2252_2_i) ); +// C_AND/D//AND/D x38y52 80'h00_F600_80_0000_0C88_CFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2254_1 ( .OUT(na2254_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2254_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2254_2 ( .OUT(na2254_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2254_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2254_4 ( .OUT(na2254_2_i), .IN1(na2256_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2254_5 ( .OUT(na2254_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2254_2_i) ); +// C_AND/D//AND/D x19y41 80'h00_F600_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2256_1 ( .OUT(na2256_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2256_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2256_2 ( .OUT(na2256_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2256_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2256_4 ( .OUT(na2256_2_i), .IN1(na2258_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2256_5 ( .OUT(na2256_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2256_2_i) ); +// C_AND/D//AND/D x19y39 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2258_1 ( .OUT(na2258_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2258_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2258_2 ( .OUT(na2258_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2258_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2258_4 ( .OUT(na2258_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2260_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2258_5 ( .OUT(na2258_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2258_2_i) ); +// C_AND/D//AND/D x16y39 80'h00_F600_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2260_1 ( .OUT(na2260_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2260_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2260_2 ( .OUT(na2260_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2260_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2260_4 ( .OUT(na2260_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2262_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2260_5 ( .OUT(na2260_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2260_2_i) ); +// C_AND/D//AND/D x16y38 80'h00_F600_80_0000_0C88_CFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2262_1 ( .OUT(na2262_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2262_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2262_2 ( .OUT(na2262_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2262_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2262_4 ( .OUT(na2262_2_i), .IN1(na2264_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2262_5 ( .OUT(na2262_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2262_2_i) ); +// C_AND/D//AND/D x15y37 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2264_1 ( .OUT(na2264_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2264_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2264_2 ( .OUT(na2264_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2264_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2264_4 ( .OUT(na2264_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2266_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2264_5 ( .OUT(na2264_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2264_2_i) ); +// C_AND/D//AND/D x16y35 80'h00_F600_80_0000_0C88_AFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2266_1 ( .OUT(na2266_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2266_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2266_2 ( .OUT(na2266_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2266_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2266_4 ( .OUT(na2266_2_i), .IN1(1'b1), .IN2(na2268_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2266_5 ( .OUT(na2266_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2266_2_i) ); +// C_AND/D//AND/D x15y38 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2268_1 ( .OUT(na2268_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2268_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2268_2 ( .OUT(na2268_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2268_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2268_4 ( .OUT(na2268_2_i), .IN1(na2270_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2268_5 ( .OUT(na2268_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2268_2_i) ); +// C_AND/D//AND/D x15y39 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2270_1 ( .OUT(na2270_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2270_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2270_2 ( .OUT(na2270_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2270_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2270_4 ( .OUT(na2270_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2272_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2270_5 ( .OUT(na2270_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2270_2_i) ); +// C_AND/D//AND/D x16y43 80'h00_F600_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2272_1 ( .OUT(na2272_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2272_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2272_2 ( .OUT(na2272_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2272_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2272_4 ( .OUT(na2272_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2274_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2272_5 ( .OUT(na2272_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2272_2_i) ); +// C_AND/D//AND/D x16y46 80'h00_F600_80_0000_0C88_CFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2274_1 ( .OUT(na2274_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2274_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2274_2 ( .OUT(na2274_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2274_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2274_4 ( .OUT(na2274_2_i), .IN1(na2276_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2274_5 ( .OUT(na2274_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2274_2_i) ); +// C_AND/D//AND/D x31y49 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2276_1 ( .OUT(na2276_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2276_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2276_2 ( .OUT(na2276_1), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2276_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2276_4 ( .OUT(na2276_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2278_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2276_5 ( .OUT(na2276_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2276_2_i) ); +// C_///AND/D x48y51 80'h00_F600_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2278_4 ( .OUT(na2278_2_i), .IN1(na709_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2278_5 ( .OUT(na2278_2), .CLK(na1739_1), .EN(~na1453_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2278_2_i) ); +// C_AND/D//AND/D x32y62 80'h00_FA00_80_0000_0C88_CFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2337_1 ( .OUT(na2337_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2337_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2337_2 ( .OUT(na2337_1), .CLK(na1739_1), .EN(na1457_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2337_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2337_4 ( .OUT(na2337_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2339_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2337_5 ( .OUT(na2337_2), .CLK(na1739_1), .EN(na1457_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2337_2_i) ); +// C_AND/D/// x42y57 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2339_1 ( .OUT(na2339_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na713_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2339_2 ( .OUT(na2339_1), .CLK(na1739_1), .EN(na1457_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2339_1_i) ); +// C_///AND/D x67y66 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2350_4 ( .OUT(na2350_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na519_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2350_5 ( .OUT(na2350_2), .CLK(na1739_1), .EN(na1437_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2350_2_i) ); +// C_AND/D//AND/D x49y38 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2352_1 ( .OUT(na2352_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3725_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2352_2 ( .OUT(na2352_1), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2352_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2352_4 ( .OUT(na2352_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3726_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2352_5 ( .OUT(na2352_2), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2352_2_i) ); +// C_AND/D//AND/D x53y42 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2354_1 ( .OUT(na2354_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3723_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2354_2 ( .OUT(na2354_1), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2354_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2354_4 ( .OUT(na2354_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3724_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2354_5 ( .OUT(na2354_2), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2354_2_i) ); +// C_AND/D//AND/D x51y42 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2356_1 ( .OUT(na2356_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3721_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2356_2 ( .OUT(na2356_1), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2356_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2356_4 ( .OUT(na2356_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3722_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2356_5 ( .OUT(na2356_2), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2356_2_i) ); +// C_AND/D//AND/D x53y46 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2358_1 ( .OUT(na2358_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3719_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2358_2 ( .OUT(na2358_1), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2358_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2358_4 ( .OUT(na2358_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3720_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2358_5 ( .OUT(na2358_2), .CLK(na1739_1), .EN(na1412_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2358_2_i) ); +// C_AND/D//AND/D x69y42 80'h00_FE00_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2359_1 ( .OUT(na2359_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2359_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2359_2 ( .OUT(na2359_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2359_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2359_4 ( .OUT(na2359_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2361_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2359_5 ( .OUT(na2359_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2359_2_i) ); +// C_AND/D//AND/D x68y41 80'h00_FE00_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2361_1 ( .OUT(na2361_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2361_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2361_2 ( .OUT(na2361_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2361_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2361_4 ( .OUT(na2361_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2363_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2361_5 ( .OUT(na2361_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2361_2_i) ); +// C_AND/D//AND/D x66y44 80'h00_FE00_80_0000_0C88_CFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2363_1 ( .OUT(na2363_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2363_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2363_2 ( .OUT(na2363_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2363_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2363_4 ( .OUT(na2363_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na784_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2363_5 ( .OUT(na2363_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2363_2_i) ); +// C_AND/D/// x25y41 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2472_1 ( .OUT(na2472_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2472_2 ( .OUT(na2472_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2472_1_i) ); +// C_///AND/D x34y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2473_4 ( .OUT(na2473_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1823_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2473_5 ( .OUT(na2473_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2473_2_i) ); +// C_AND/D//AND/D x29y58 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2474_1 ( .OUT(na2474_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1823_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2474_2 ( .OUT(na2474_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2474_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2474_4 ( .OUT(na2474_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1825_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2474_5 ( .OUT(na2474_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2474_2_i) ); +// C_AND/D/// x19y52 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2477_1 ( .OUT(na2477_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2595_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2477_2 ( .OUT(na2477_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2477_1_i) ); +// C_AND/D//AND/D x19y56 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2478_1 ( .OUT(na2478_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2597_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2478_2 ( .OUT(na2478_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2478_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2478_4 ( .OUT(na2478_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2595_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2478_5 ( .OUT(na2478_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2478_2_i) ); +// C_///AND/D x19y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2479_4 ( .OUT(na2479_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2597_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2479_5 ( .OUT(na2479_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2479_2_i) ); +// C_AND/D//AND/D x20y49 80'h00_FA00_80_0000_0C88_CFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2481_1 ( .OUT(na2481_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2481_2 ( .OUT(na2481_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2481_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2481_4 ( .OUT(na2481_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2599_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2481_5 ( .OUT(na2481_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2481_2_i) ); +// C_AND/D/// x29y44 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2482_1 ( .OUT(na2482_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1815_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2482_2 ( .OUT(na2482_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2482_1_i) ); +// C_///AND/D x26y46 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2483_4 ( .OUT(na2483_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1815_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2483_5 ( .OUT(na2483_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2483_2_i) ); +// C_AND/D/// x38y45 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2484_1 ( .OUT(na2484_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1817_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2484_2 ( .OUT(na2484_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2484_1_i) ); +// C_///AND/D x35y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2485_4 ( .OUT(na2485_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1817_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2485_5 ( .OUT(na2485_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2485_2_i) ); +// C_AND/D/// x35y38 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2486_1 ( .OUT(na2486_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3532_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2486_2 ( .OUT(na2486_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2486_1_i) ); +// C_///AND/D x20y45 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2487_4 ( .OUT(na2487_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2599_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2487_5 ( .OUT(na2487_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2487_2_i) ); +// C_AND/D/// x22y43 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2488_1 ( .OUT(na2488_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1819_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2488_2 ( .OUT(na2488_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2488_1_i) ); +// C_AND/D//AND/D x22y44 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2489_1 ( .OUT(na2489_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1819_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2489_2 ( .OUT(na2489_1), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2489_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2489_4 ( .OUT(na2489_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1821_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2489_5 ( .OUT(na2489_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2489_2_i) ); +// C_///AND/D x13y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2490_4 ( .OUT(na2490_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1821_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2490_5 ( .OUT(na2490_2), .CLK(na1739_1), .EN(na121_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2490_2_i) ); +// C_AND/D/// x38y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2497_1 ( .OUT(na2497_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na881_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2497_2 ( .OUT(na2497_1), .CLK(na1739_1), .EN(na1480_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2497_1_i) ); +// C_AND/D//AND/D x18y52 80'h00_F600_80_0000_0C88_CFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2499_1 ( .OUT(na2499_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2499_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2499_2 ( .OUT(na2499_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2499_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2499_4 ( .OUT(na2499_2_i), .IN1(na2501_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2499_5 ( .OUT(na2499_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2499_2_i) ); +// C_AND/D//AND/D x15y43 80'h00_F600_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2501_1 ( .OUT(na2501_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2501_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2501_2 ( .OUT(na2501_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2501_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2501_4 ( .OUT(na2501_2_i), .IN1(1'b1), .IN2(na2503_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2501_5 ( .OUT(na2501_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2501_2_i) ); +// C_AND/D//AND/D x15y44 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2503_1 ( .OUT(na2503_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2503_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2503_2 ( .OUT(na2503_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2503_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2503_4 ( .OUT(na2503_2_i), .IN1(na2505_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2503_5 ( .OUT(na2503_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2503_2_i) ); +// C_AND/D//AND/D x13y41 80'h00_F600_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2505_1 ( .OUT(na2505_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2505_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2505_2 ( .OUT(na2505_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2505_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2505_4 ( .OUT(na2505_2_i), .IN1(1'b1), .IN2(na2507_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2505_5 ( .OUT(na2505_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2505_2_i) ); +// C_AND/D//AND/D x15y42 80'h00_F600_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2507_1 ( .OUT(na2507_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2507_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2507_2 ( .OUT(na2507_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2507_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2507_4 ( .OUT(na2507_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2509_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2507_5 ( .OUT(na2507_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2507_2_i) ); +// C_AND/D//AND/D x18y39 80'h00_F600_80_0000_0C88_AFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2509_1 ( .OUT(na2509_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2509_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2509_2 ( .OUT(na2509_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2509_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2509_4 ( .OUT(na2509_2_i), .IN1(1'b1), .IN2(na2511_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2509_5 ( .OUT(na2509_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2509_2_i) ); +// C_AND/D//AND/D x17y38 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2511_1 ( .OUT(na2511_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2511_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2511_2 ( .OUT(na2511_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2511_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2511_4 ( .OUT(na2511_2_i), .IN1(na2513_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2511_5 ( .OUT(na2511_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2511_2_i) ); +// C_AND/D//AND/D x17y37 80'h00_F600_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2513_1 ( .OUT(na2513_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2513_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2513_2 ( .OUT(na2513_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2513_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2513_4 ( .OUT(na2513_2_i), .IN1(1'b1), .IN2(na2515_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2513_5 ( .OUT(na2513_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2513_2_i) ); +// C_AND/D//AND/D x19y38 80'h00_F600_80_0000_0C88_FCCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2515_1 ( .OUT(na2515_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2515_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2515_2 ( .OUT(na2515_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2515_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2515_4 ( .OUT(na2515_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2517_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2515_5 ( .OUT(na2515_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2515_2_i) ); +// C_AND/D//AND/D x20y38 80'h00_F600_80_0000_0C88_CFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2517_1 ( .OUT(na2517_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2517_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2517_2 ( .OUT(na2517_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2517_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2517_4 ( .OUT(na2517_2_i), .IN1(1'b1), .IN2(na2519_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2517_5 ( .OUT(na2517_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2517_2_i) ); +// C_AND/D//AND/D x19y40 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2519_1 ( .OUT(na2519_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2519_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2519_2 ( .OUT(na2519_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2519_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2519_4 ( .OUT(na2519_2_i), .IN1(na2521_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2519_5 ( .OUT(na2519_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2519_2_i) ); +// C_AND/D//AND/D x17y39 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2521_1 ( .OUT(na2521_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2521_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2521_2 ( .OUT(na2521_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2521_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2521_4 ( .OUT(na2521_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2523_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2521_5 ( .OUT(na2521_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2521_2_i) ); +// C_AND/D//AND/D x18y41 80'h00_F600_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2523_1 ( .OUT(na2523_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2523_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2523_2 ( .OUT(na2523_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2523_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2523_4 ( .OUT(na2523_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2525_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2523_5 ( .OUT(na2523_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2523_2_i) ); +// C_AND/D//AND/D x16y44 80'h00_F600_80_0000_0C88_CFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2525_1 ( .OUT(na2525_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2525_2 ( .OUT(na2525_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2525_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2525_4 ( .OUT(na2525_2_i), .IN1(1'b1), .IN2(na2527_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2525_5 ( .OUT(na2525_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2525_2_i) ); +// C_AND/D//AND/D x19y44 80'h00_F600_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2527_1 ( .OUT(na2527_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2527_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2527_2 ( .OUT(na2527_1), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2527_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2527_4 ( .OUT(na2527_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2529_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2527_5 ( .OUT(na2527_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2527_2_i) ); +// C_///AND/D x22y55 80'h00_F600_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2529_4 ( .OUT(na2529_2_i), .IN1(na886_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2529_5 ( .OUT(na2529_2), .CLK(na1739_1), .EN(~na1475_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2529_2_i) ); +// C_AND/D//AND/D x16y45 80'h00_FA00_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2579_1 ( .OUT(na2579_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2579_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2579_2 ( .OUT(na2579_1), .CLK(na1739_1), .EN(na1479_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2579_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2579_4 ( .OUT(na2579_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2581_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2579_5 ( .OUT(na2579_2), .CLK(na1739_1), .EN(na1479_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2579_2_i) ); +// C_AND/D/// x16y48 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2581_1 ( .OUT(na2581_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na891_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2581_2 ( .OUT(na2581_1), .CLK(na1739_1), .EN(na1479_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2581_1_i) ); +// C_AND/D//AND/D x40y35 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2593_1 ( .OUT(na2593_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3531_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2593_2 ( .OUT(na2593_1), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2593_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2593_4 ( .OUT(na2593_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3532_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2593_5 ( .OUT(na2593_2), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2593_2_i) ); +// C_AND/D//AND/D x36y43 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2595_1 ( .OUT(na2595_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3529_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2595_2 ( .OUT(na2595_1), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2595_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2595_4 ( .OUT(na2595_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3530_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2595_5 ( .OUT(na2595_2), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2595_2_i) ); +// C_AND/D//AND/D x42y43 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2597_1 ( .OUT(na2597_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3527_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2597_2 ( .OUT(na2597_1), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2597_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2597_4 ( .OUT(na2597_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3528_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2597_5 ( .OUT(na2597_2), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2597_2_i) ); +// C_AND/D//AND/D x30y43 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2599_1 ( .OUT(na2599_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3525_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2599_2 ( .OUT(na2599_1), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2599_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2599_4 ( .OUT(na2599_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3526_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2599_5 ( .OUT(na2599_2), .CLK(na1739_1), .EN(na1415_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2599_2_i) ); +// C_AND/D//AND/D x39y49 80'h00_FE00_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2600_1 ( .OUT(na2600_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2600_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2600_2 ( .OUT(na2600_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2600_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2600_4 ( .OUT(na2600_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2602_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2600_5 ( .OUT(na2600_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2600_2_i) ); +// C_AND/D//AND/D x36y50 80'h00_FE00_80_0000_0C88_CFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2602_1 ( .OUT(na2602_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2602_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2602_2 ( .OUT(na2602_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2602_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2602_4 ( .OUT(na2602_2_i), .IN1(1'b1), .IN2(na2604_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2602_5 ( .OUT(na2602_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2602_2_i) ); +// C_AND/D//AND/D x31y50 80'h00_FE00_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2604_1 ( .OUT(na2604_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2604_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2604_2 ( .OUT(na2604_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2604_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2604_4 ( .OUT(na2604_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na951_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2604_5 ( .OUT(na2604_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2604_2_i) ); +// C_///AND/D x36y65 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2705_4 ( .OUT(na2705_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3414_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2705_5 ( .OUT(na2705_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2705_2_i) ); +// C_AND/D/// x45y90 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2706_1 ( .OUT(na2706_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1784_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2706_2 ( .OUT(na2706_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2706_1_i) ); +// C_AND/D//AND/D x48y90 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2707_1 ( .OUT(na2707_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1784_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2707_2 ( .OUT(na2707_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2707_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2707_4 ( .OUT(na2707_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1786_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2707_5 ( .OUT(na2707_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2707_2_i) ); +// C_///AND/D x46y86 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2710_4 ( .OUT(na2710_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2842_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2710_5 ( .OUT(na2710_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2710_2_i) ); +// C_AND/D//AND/D x37y79 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2712_1 ( .OUT(na2712_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2844_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2712_2 ( .OUT(na2712_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2712_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2712_4 ( .OUT(na2712_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2844_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2712_5 ( .OUT(na2712_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2712_2_i) ); +// C_AND/D//AND/D x38y83 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2713_1 ( .OUT(na2713_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2846_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2713_2 ( .OUT(na2713_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2713_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2713_4 ( .OUT(na2713_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2842_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2713_5 ( .OUT(na2713_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2713_2_i) ); +// C_AND/D/// x39y73 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2714_1 ( .OUT(na2714_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3413_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2714_2 ( .OUT(na2714_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2714_1_i) ); +// C_///AND/D x58y66 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2715_4 ( .OUT(na2715_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1792_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2715_5 ( .OUT(na2715_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2715_2_i) ); +// C_AND/D/// x45y71 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2716_1 ( .OUT(na2716_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1792_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2716_2 ( .OUT(na2716_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2716_1_i) ); +// C_///AND/D x62y68 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2717_4 ( .OUT(na2717_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1794_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2717_5 ( .OUT(na2717_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2717_2_i) ); +// C_AND/D/// x50y72 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2718_1 ( .OUT(na2718_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1794_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2718_2 ( .OUT(na2718_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2718_1_i) ); +// C_///AND/D x46y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2719_4 ( .OUT(na2719_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3424_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2719_5 ( .OUT(na2719_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2719_2_i) ); +// C_AND/D/// x40y70 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2720_1 ( .OUT(na2720_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2846_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2720_2 ( .OUT(na2720_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2720_1_i) ); +// C_///AND/D x42y74 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2721_4 ( .OUT(na2721_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1780_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2721_5 ( .OUT(na2721_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2721_2_i) ); +// C_AND/D//AND/D x40y68 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2722_1 ( .OUT(na2722_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1780_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2722_2 ( .OUT(na2722_1), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2722_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2722_4 ( .OUT(na2722_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1782_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2722_5 ( .OUT(na2722_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2722_2_i) ); +// C_///AND/D x50y72 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2723_4 ( .OUT(na2723_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1782_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2723_5 ( .OUT(na2723_2), .CLK(na1739_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2723_2_i) ); +// C_///AND/D x60y86 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2730_4 ( .OUT(na2730_2_i), .IN1(1'b1), .IN2(na1044_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2730_5 ( .OUT(na2730_2), .CLK(na1739_1), .EN(na1502_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2730_2_i) ); +// C_AND/D//AND/D x38y90 80'h00_F600_80_0000_0C88_CFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2739_1 ( .OUT(na2739_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2739_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2739_2 ( .OUT(na2739_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2739_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2739_4 ( .OUT(na2739_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2741_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2739_5 ( .OUT(na2739_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2739_2_i) ); +// C_AND/D//AND/D x32y79 80'h00_F600_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2741_1 ( .OUT(na2741_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2741_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2741_2 ( .OUT(na2741_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2741_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2741_4 ( .OUT(na2741_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2743_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2741_5 ( .OUT(na2741_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2741_2_i) ); +// C_AND/D//AND/D x30y75 80'h00_F600_80_0000_0C88_AFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2743_1 ( .OUT(na2743_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2743_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2743_2 ( .OUT(na2743_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2743_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2743_4 ( .OUT(na2743_2_i), .IN1(1'b1), .IN2(na2745_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2743_5 ( .OUT(na2743_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2743_2_i) ); +// C_AND/D//AND/D x21y74 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2745_1 ( .OUT(na2745_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2745_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2745_2 ( .OUT(na2745_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2745_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2745_4 ( .OUT(na2745_2_i), .IN1(na2747_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2745_5 ( .OUT(na2745_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2745_2_i) ); +// C_AND/D//AND/D x15y81 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2747_1 ( .OUT(na2747_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2747_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2747_2 ( .OUT(na2747_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2747_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2747_4 ( .OUT(na2747_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2749_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2747_5 ( .OUT(na2747_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2747_2_i) ); +// C_AND/D//AND/D x14y85 80'h00_F600_80_0000_0C88_AFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2749_1 ( .OUT(na2749_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2749_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2749_2 ( .OUT(na2749_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2749_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2749_4 ( .OUT(na2749_2_i), .IN1(1'b1), .IN2(na2751_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2749_5 ( .OUT(na2749_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2749_2_i) ); +// C_AND/D//AND/D x15y88 80'h00_F600_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2751_1 ( .OUT(na2751_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2751_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2751_2 ( .OUT(na2751_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2751_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2751_4 ( .OUT(na2751_2_i), .IN1(1'b1), .IN2(na2753_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2751_5 ( .OUT(na2751_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2751_2_i) ); +// C_AND/D//AND/D x13y88 80'h00_F600_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2753_1 ( .OUT(na2753_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2753_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2753_2 ( .OUT(na2753_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2753_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2753_4 ( .OUT(na2753_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2755_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2753_5 ( .OUT(na2753_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2753_2_i) ); +// C_AND/D//AND/D x14y89 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2755_1 ( .OUT(na2755_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2755_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2755_2 ( .OUT(na2755_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2755_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2755_4 ( .OUT(na2755_2_i), .IN1(na2757_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2755_5 ( .OUT(na2755_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2755_2_i) ); +// C_AND/D//AND/D x15y89 80'h00_F600_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2757_1 ( .OUT(na2757_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2757_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2757_2 ( .OUT(na2757_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2757_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2757_4 ( .OUT(na2757_2_i), .IN1(1'b1), .IN2(na2759_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2757_5 ( .OUT(na2757_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2757_2_i) ); +// C_AND/D//AND/D x15y90 80'h00_F600_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2759_1 ( .OUT(na2759_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2759_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2759_2 ( .OUT(na2759_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2759_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2759_4 ( .OUT(na2759_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2761_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2759_5 ( .OUT(na2759_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2759_2_i) ); +// C_AND/D//AND/D x14y91 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2761_1 ( .OUT(na2761_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2761_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2761_2 ( .OUT(na2761_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2761_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2761_4 ( .OUT(na2761_2_i), .IN1(na2763_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2761_5 ( .OUT(na2761_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2761_2_i) ); +// C_AND/D//AND/D x15y91 80'h00_F600_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2763_1 ( .OUT(na2763_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2763_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2763_2 ( .OUT(na2763_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2763_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2763_4 ( .OUT(na2763_2_i), .IN1(1'b1), .IN2(na2765_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2763_5 ( .OUT(na2763_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2763_2_i) ); +// C_AND/D//AND/D x19y92 80'h00_F600_80_0000_0C88_FCAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2765_1 ( .OUT(na2765_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2765_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2765_2 ( .OUT(na2765_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2765_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2765_4 ( .OUT(na2765_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2767_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2765_5 ( .OUT(na2765_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2765_2_i) ); +// C_AND/D//AND/D x32y91 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2767_1 ( .OUT(na2767_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2767_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2767_2 ( .OUT(na2767_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2767_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2767_4 ( .OUT(na2767_2_i), .IN1(na2769_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2767_5 ( .OUT(na2767_2), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2767_2_i) ); +// C_AND/D/// x47y87 80'h00_F600_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2769_1 ( .OUT(na2769_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1050_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2769_2 ( .OUT(na2769_1), .CLK(na1739_1), .EN(~na1497_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2769_1_i) ); +// C_AND/D//AND/D x19y91 80'h00_FA00_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2819_1 ( .OUT(na2819_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2819_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2819_2 ( .OUT(na2819_1), .CLK(na1739_1), .EN(na1501_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2819_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2819_4 ( .OUT(na2819_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2821_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2819_5 ( .OUT(na2819_2), .CLK(na1739_1), .EN(na1501_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2819_2_i) ); +// C_///AND/D x22y92 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2821_4 ( .OUT(na2821_2_i), .IN1(1'b1), .IN2(na1051_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2821_5 ( .OUT(na2821_2), .CLK(na1739_1), .EN(na1501_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2821_2_i) ); +// C_AND/D//AND/D x46y56 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2840_1 ( .OUT(na2840_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3423_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2840_2 ( .OUT(na2840_1), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2840_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2840_4 ( .OUT(na2840_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3424_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2840_5 ( .OUT(na2840_2), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2840_2_i) ); +// C_AND/D//AND/D x46y68 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2842_1 ( .OUT(na2842_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3420_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2842_2 ( .OUT(na2842_1), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2842_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2842_4 ( .OUT(na2842_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3421_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2842_5 ( .OUT(na2842_2), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2842_2_i) ); +// C_AND/D//AND/D x44y68 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2844_1 ( .OUT(na2844_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3416_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2844_2 ( .OUT(na2844_1), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2844_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2844_4 ( .OUT(na2844_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3417_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2844_5 ( .OUT(na2844_2), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2844_2_i) ); +// C_AND/D//AND/D x44y70 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2846_1 ( .OUT(na2846_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3413_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2846_2 ( .OUT(na2846_1), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2846_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2846_4 ( .OUT(na2846_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3414_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2846_5 ( .OUT(na2846_2), .CLK(na1739_1), .EN(na1419_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2846_2_i) ); +// C_AND/D//AND/D x60y91 80'h00_FE00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2847_1 ( .OUT(na2847_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2847_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2847_2 ( .OUT(na2847_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2847_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2847_4 ( .OUT(na2847_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2849_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2847_5 ( .OUT(na2847_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2847_2_i) ); +// C_AND/D//AND/D x60y89 80'h00_FE00_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2849_1 ( .OUT(na2849_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2849_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2849_2 ( .OUT(na2849_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2849_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2849_4 ( .OUT(na2849_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2851_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2849_5 ( .OUT(na2849_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2849_2_i) ); +// C_AND/D//AND/D x54y90 80'h00_FE00_80_0000_0C88_CFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2851_1 ( .OUT(na2851_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2851_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2851_2 ( .OUT(na2851_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2851_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2851_4 ( .OUT(na2851_2_i), .IN1(1'b1), .IN2(na1112_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2851_5 ( .OUT(na2851_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na2851_2_i) ); +// C_AND/D/// x49y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2956_1 ( .OUT(na2956_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3427_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2956_2 ( .OUT(na2956_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2956_1_i) ); +// C_///AND/D x65y87 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2957_4 ( .OUT(na2957_2_i), .IN1(1'b1), .IN2(na1767_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2957_5 ( .OUT(na2957_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2957_2_i) ); +// C_AND/D//AND/D x62y85 80'h00_FA00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2958_1 ( .OUT(na2958_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1767_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2958_2 ( .OUT(na2958_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2958_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2958_4 ( .OUT(na2958_2_i), .IN1(1'b1), .IN2(na1769_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2958_5 ( .OUT(na2958_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2958_2_i) ); +// C_AND/D/// x62y83 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2961_1 ( .OUT(na2961_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3100_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2961_2 ( .OUT(na2961_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2961_1_i) ); +// C_AND/D//AND/D x55y83 80'h00_FA00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2962_1 ( .OUT(na2962_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3102_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2962_2 ( .OUT(na2962_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2962_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2962_4 ( .OUT(na2962_2_i), .IN1(1'b1), .IN2(na3100_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2962_5 ( .OUT(na2962_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2962_2_i) ); +// C_///AND/D x59y83 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2963_4 ( .OUT(na2963_2_i), .IN1(1'b1), .IN2(na3102_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2963_5 ( .OUT(na2963_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2963_2_i) ); +// C_AND/D//AND/D x51y82 80'h00_FA00_80_0000_0C88_CFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2965_1 ( .OUT(na2965_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3426_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2965_2 ( .OUT(na2965_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2965_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2965_4 ( .OUT(na2965_2_i), .IN1(1'b1), .IN2(na3104_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2965_5 ( .OUT(na2965_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2965_2_i) ); +// C_AND/D/// x33y58 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2966_1 ( .OUT(na2966_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1775_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2966_2 ( .OUT(na2966_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2966_1_i) ); +// C_///AND/D x33y54 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2967_4 ( .OUT(na2967_2_i), .IN1(1'b1), .IN2(na1775_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2967_5 ( .OUT(na2967_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2967_2_i) ); +// C_AND/D/// x34y57 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2968_1 ( .OUT(na2968_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1777_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2968_2 ( .OUT(na2968_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2968_1_i) ); +// C_///AND/D x33y49 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2969_4 ( .OUT(na2969_2_i), .IN1(1'b1), .IN2(na1777_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2969_5 ( .OUT(na2969_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2969_2_i) ); +// C_AND/D/// x30y46 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2970_1 ( .OUT(na2970_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3444_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2970_2 ( .OUT(na2970_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2970_1_i) ); +// C_///AND/D x32y58 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2971_4 ( .OUT(na2971_2_i), .IN1(1'b1), .IN2(na3104_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2971_5 ( .OUT(na2971_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2971_2_i) ); +// C_AND/D/// x28y63 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2972_1 ( .OUT(na2972_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1763_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2972_2 ( .OUT(na2972_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2972_1_i) ); +// C_AND/D//AND/D x25y62 80'h00_FA00_80_0000_0C88_FCFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2973_1 ( .OUT(na2973_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1763_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2973_2 ( .OUT(na2973_1), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2973_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2973_4 ( .OUT(na2973_2_i), .IN1(1'b1), .IN2(na1765_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2973_5 ( .OUT(na2973_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2973_2_i) ); +// C_///AND/D x29y63 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2974_4 ( .OUT(na2974_2_i), .IN1(1'b1), .IN2(na1765_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2974_5 ( .OUT(na2974_2), .CLK(na1739_1), .EN(na436_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2974_2_i) ); +// C_AND/D/// x57y84 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2981_1 ( .OUT(na2981_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1192_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2981_2 ( .OUT(na2981_1), .CLK(na1739_1), .EN(na1524_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2981_1_i) ); +// C_AND/D//AND/D x48y87 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2984_1 ( .OUT(na2984_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2984_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2984_2 ( .OUT(na2984_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2984_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2984_4 ( .OUT(na2984_2_i), .IN1(na2986_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2984_5 ( .OUT(na2984_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2984_2_i) ); +// C_AND/D//AND/D x23y71 80'h00_F600_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2986_1 ( .OUT(na2986_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2986_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2986_2 ( .OUT(na2986_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2986_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2986_4 ( .OUT(na2986_2_i), .IN1(na2988_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2986_5 ( .OUT(na2986_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2986_2_i) ); +// C_AND/D//AND/D x15y73 80'h00_F600_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2988_1 ( .OUT(na2988_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2988_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2988_2 ( .OUT(na2988_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2988_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2988_4 ( .OUT(na2988_2_i), .IN1(1'b1), .IN2(na2990_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2988_5 ( .OUT(na2988_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2988_2_i) ); +// C_AND/D//AND/D x13y74 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2990_1 ( .OUT(na2990_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2990_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2990_2 ( .OUT(na2990_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2990_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2990_4 ( .OUT(na2990_2_i), .IN1(na2992_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2990_5 ( .OUT(na2990_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2990_2_i) ); +// C_AND/D//AND/D x13y79 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2992_1 ( .OUT(na2992_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2992_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2992_2 ( .OUT(na2992_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2992_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2992_4 ( .OUT(na2992_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2994_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2992_5 ( .OUT(na2992_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2992_2_i) ); +// C_AND/D//AND/D x14y81 80'h00_F600_80_0000_0C88_AFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2994_1 ( .OUT(na2994_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2994_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2994_2 ( .OUT(na2994_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2994_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2994_4 ( .OUT(na2994_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2996_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2994_5 ( .OUT(na2994_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2994_2_i) ); +// C_AND/D//AND/D x14y78 80'h00_F600_80_0000_0C88_CFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2996_1 ( .OUT(na2996_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2996_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2996_2 ( .OUT(na2996_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2996_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2996_4 ( .OUT(na2996_2_i), .IN1(na2998_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2996_5 ( .OUT(na2996_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2996_2_i) ); +// C_AND/D//AND/D x15y75 80'h00_F600_80_0000_0C88_FAAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2998_1 ( .OUT(na2998_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2998_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a2998_2 ( .OUT(na2998_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2998_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2998_4 ( .OUT(na2998_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3000_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a2998_5 ( .OUT(na2998_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na2998_2_i) ); +// C_AND/D//AND/D x14y71 80'h00_F600_80_0000_0C88_AFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3000_1 ( .OUT(na3000_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3000_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3000_2 ( .OUT(na3000_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3000_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3000_4 ( .OUT(na3000_2_i), .IN1(na3002_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3000_5 ( .OUT(na3000_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3000_2_i) ); +// C_AND/D//AND/D x15y69 80'h00_F600_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3002_1 ( .OUT(na3002_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3002_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3002_2 ( .OUT(na3002_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3002_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3002_4 ( .OUT(na3002_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3004_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3002_5 ( .OUT(na3002_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3002_2_i) ); +// C_AND/D//AND/D x14y70 80'h00_F600_80_0000_0C88_CFFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3004_1 ( .OUT(na3004_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3004_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3004_2 ( .OUT(na3004_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3004_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3004_4 ( .OUT(na3004_2_i), .IN1(na3006_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3004_5 ( .OUT(na3004_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3004_2_i) ); +// C_AND/D//AND/D x13y75 80'h00_F600_80_0000_0C88_FAFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3006_1 ( .OUT(na3006_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3006_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3006_2 ( .OUT(na3006_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3006_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3006_4 ( .OUT(na3006_2_i), .IN1(1'b1), .IN2(na3008_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3006_5 ( .OUT(na3006_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3006_2_i) ); +// C_AND/D//AND/D x15y78 80'h00_F600_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3008_1 ( .OUT(na3008_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na3008_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3008_2 ( .OUT(na3008_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3008_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3008_4 ( .OUT(na3008_2_i), .IN1(na3010_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3008_5 ( .OUT(na3008_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3008_2_i) ); +// C_AND/D//AND/D x15y79 80'h00_F600_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3010_1 ( .OUT(na3010_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3010_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3010_2 ( .OUT(na3010_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3010_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3010_4 ( .OUT(na3010_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3012_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3010_5 ( .OUT(na3010_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3010_2_i) ); +// C_AND/D//AND/D x22y76 80'h00_F600_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3012_1 ( .OUT(na3012_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3012_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3012_2 ( .OUT(na3012_1), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3012_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3012_4 ( .OUT(na3012_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3014_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3012_5 ( .OUT(na3012_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3012_2_i) ); +// C_///AND/D x44y76 80'h00_F600_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3014_4 ( .OUT(na3014_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1198_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3014_5 ( .OUT(na3014_2), .CLK(na1739_1), .EN(~na1519_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3014_2_i) ); +// C_AND/D//AND/D x70y91 80'h00_FA00_80_0000_0C88_AFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3064_1 ( .OUT(na3064_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3064_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3064_2 ( .OUT(na3064_1), .CLK(na1739_1), .EN(na1523_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3064_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3064_4 ( .OUT(na3064_2_i), .IN1(1'b1), .IN2(na3066_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3064_5 ( .OUT(na3064_2), .CLK(na1739_1), .EN(na1523_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3064_2_i) ); +// C_AND/D/// x67y92 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3066_1 ( .OUT(na3066_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1199_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3066_2 ( .OUT(na3066_1), .CLK(na1739_1), .EN(na1523_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3066_1_i) ); +// C_AND/D//AND/D x37y50 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3098_1 ( .OUT(na3098_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3443_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3098_2 ( .OUT(na3098_1), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3098_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3098_4 ( .OUT(na3098_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3444_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3098_5 ( .OUT(na3098_2), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3098_2_i) ); +// C_AND/D//AND/D x43y58 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3100_1 ( .OUT(na3100_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3439_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3100_2 ( .OUT(na3100_1), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3100_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3100_4 ( .OUT(na3100_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3442_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3100_5 ( .OUT(na3100_2), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3100_2_i) ); +// C_AND/D//AND/D x41y56 80'h00_FA00_80_0000_0C88_AFAF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3102_1 ( .OUT(na3102_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na3429_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3102_2 ( .OUT(na3102_1), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3102_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3102_4 ( .OUT(na3102_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na3430_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3102_5 ( .OUT(na3102_2), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3102_2_i) ); +// C_AND/D//AND/D x43y56 80'h00_FA00_80_0000_0C88_CFCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3104_1 ( .OUT(na3104_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3426_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3104_2 ( .OUT(na3104_1), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3104_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3104_4 ( .OUT(na3104_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3427_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3104_5 ( .OUT(na3104_2), .CLK(na1739_1), .EN(na1422_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na3104_2_i) ); +// C_AND/D//AND/D x43y63 80'h00_FE00_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3105_1 ( .OUT(na3105_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3105_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3105_2 ( .OUT(na3105_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na3105_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3105_4 ( .OUT(na3105_2_i), .IN1(na3107_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3105_5 ( .OUT(na3105_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na3105_2_i) ); +// C_AND/D//AND/D x43y65 80'h00_FE00_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3107_1 ( .OUT(na3107_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3107_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3107_2 ( .OUT(na3107_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na3107_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3107_4 ( .OUT(na3107_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na3109_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3107_5 ( .OUT(na3107_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na3107_2_i) ); +// C_AND/D//AND/D x46y72 80'h00_FE00_80_0000_0C88_CFFC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3109_1 ( .OUT(na3109_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na3109_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a3109_2 ( .OUT(na3109_1), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na3109_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3109_4 ( .OUT(na3109_2_i), .IN1(1'b1), .IN2(na1254_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a3109_5 ( .OUT(na3109_2), .CLK(na1739_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na3109_2_i) ); +// C_MX4b//// x51y77 80'h00_0018_00_0040_0AFE_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3145_1 ( .OUT(na3145_1), .IN1(1'b1), .IN2(na1541_2), .IN3(na4461_2), .IN4(1'b1), .IN5(na1429_2), .IN6(~na1536_1), .IN7(~na1537_2), + .IN8(~na1538_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x52y87 80'h00_0018_00_0040_0AFD_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3146_1 ( .OUT(na3146_1), .IN1(1'b1), .IN2(~na1543_2), .IN3(na4465_2), .IN4(1'b1), .IN5(~na1514_2), .IN6(na1428_1), .IN7(~na1516_2), + .IN8(~na1515_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x13y68 80'h00_0018_00_0040_0A55_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3147_1 ( .OUT(na3147_1), .IN1(1'b1), .IN2(na24_1), .IN3(~na233_2), .IN4(1'b1), .IN5(~na1614_2), .IN6(1'b0), .IN7(~na4472_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x17y68 80'h00_0018_00_0040_0AA0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3148_1 ( .OUT(na3148_1), .IN1(1'b1), .IN2(~na24_1), .IN3(~na233_2), .IN4(1'b1), .IN5(1'b0), .IN6(na155_2), .IN7(1'b0), .IN8(na156_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x17y69 80'h00_0018_00_0040_0A50_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3149_1 ( .OUT(na3149_1), .IN1(1'b1), .IN2(na24_1), .IN3(na233_2), .IN4(1'b1), .IN5(na235_2), .IN6(1'b0), .IN7(na233_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x16y70 80'h00_0018_00_0040_0A50_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3150_1 ( .OUT(na3150_1), .IN1(1'b1), .IN2(na24_1), .IN3(~na233_2), .IN4(1'b1), .IN5(na234_1), .IN6(1'b0), .IN7(na236_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x48y59 80'h00_0018_00_0040_0AF0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3151_1 ( .OUT(na3151_1), .IN1(na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4154_2), .IN5(na1200_1), .IN6(na1052_1), .IN7(na892_1), + .IN8(na728_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x46y55 80'h00_0018_00_0040_0AF0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3152_1 ( .OUT(na3152_1), .IN1(na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4154_2), .IN5(na1200_2), .IN6(na1052_2), .IN7(na892_2), + .IN8(na728_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x47y60 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3153_1 ( .OUT(na3153_1), .IN1(~na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4154_2), .IN5(na1054_1), .IN6(na4375_2), .IN7(na730_1), + .IN8(na4306_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x49y60 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3154_1 ( .OUT(na3154_1), .IN1(~na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4154_2), .IN5(na1054_2), .IN6(na4376_2), .IN7(na730_2), + .IN8(na4307_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x53y65 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3155_1 ( .OUT(na3155_1), .IN1(~na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4154_2), .IN5(na1056_1), .IN6(na1204_1), .IN7(na732_1), + .IN8(na896_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x52y62 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3156_1 ( .OUT(na3156_1), .IN1(~na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(na4154_2), .IN5(na1056_2), .IN6(na1204_2), .IN7(na732_2), + .IN8(na896_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x48y60 80'h00_0018_00_0040_0AF0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3157_1 ( .OUT(na3157_1), .IN1(~na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na4154_2), .IN5(na734_1), .IN6(na898_1), .IN7(na1058_1), + .IN8(na1206_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x46y64 80'h00_0018_00_0040_0AF0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3158_1 ( .OUT(na3158_1), .IN1(~na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na4154_2), .IN5(na734_2), .IN6(na898_2), .IN7(na1058_2), + .IN8(na1206_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x49y72 80'h00_0018_00_0040_0AF0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3159_1 ( .OUT(na3159_1), .IN1(na1314_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na4154_2), .IN5(na4067_2), .IN6(na4_1), .IN7(na8_1), + .IN8(na4066_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x18y67 80'h00_0018_00_0040_0A55_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3160_1 ( .OUT(na3160_1), .IN1(1'b1), .IN2(na24_1), .IN3(~na233_2), .IN4(1'b1), .IN5(~na394_1), .IN6(1'b0), .IN7(~na395_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x18y73 80'h00_0018_00_0040_0A50_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3161_1 ( .OUT(na3161_1), .IN1(1'b1), .IN2(~na25_2), .IN3(~na233_2), .IN4(1'b1), .IN5(na1148_2), .IN6(1'b0), .IN7(na1316_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x70y44 80'h00_0018_00_0040_0AFE_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3162_1 ( .OUT(na3162_1), .IN1(1'b1), .IN2(na1542_2), .IN3(1'b1), .IN4(na4463_2), .IN5(na1426_2), .IN6(~na1470_1), .IN7(~na1471_2), + .IN8(~na1472_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x66y65 80'h00_0060_00_0000_0C06_FFC9 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3163_4 ( .OUT(na3163_2), .IN1(na535_1), .IN2(~na512_1), .IN3(1'b0), .IN4(na1985_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x65y67 80'h00_0018_00_0040_0A67_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3164_1 ( .OUT(na3164_1), .IN1(~na535_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1985_1), .IN5(1'b1), .IN6(~na512_1), .IN7(~na4215_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x67y48 80'h00_0018_00_0040_0AF0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3165_1 ( .OUT(na3165_1), .IN1(~na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_1), .IN5(na567_1), .IN6(na559_1), .IN7(na551_1), + .IN8(na4229_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x69y48 80'h00_0018_00_0040_0AF0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3166_1 ( .OUT(na3166_1), .IN1(~na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_1), .IN5(na567_2), .IN6(na559_2), .IN7(na551_2), + .IN8(na4230_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x63y45 80'h00_0018_00_0040_0AF0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3167_1 ( .OUT(na3167_1), .IN1(na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1544_1), .IN5(na545_1), .IN6(na553_1), .IN7(na561_1), + .IN8(na4247_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x65y46 80'h00_0018_00_0040_0AF0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3168_1 ( .OUT(na3168_1), .IN1(na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1544_1), .IN5(na545_2), .IN6(na553_2), .IN7(na561_2), + .IN8(na4248_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x66y45 80'h00_0018_00_0040_0AF0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3169_1 ( .OUT(na3169_1), .IN1(na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_1), .IN5(na563_1), .IN6(na4249_2), .IN7(na547_1), + .IN8(na4239_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x70y46 80'h00_0018_00_0040_0AF0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3170_1 ( .OUT(na3170_1), .IN1(na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_1), .IN5(na563_2), .IN6(na4250_2), .IN7(na547_2), + .IN8(na4240_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x64y46 80'h00_0018_00_0040_0AF0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3171_1 ( .OUT(na3171_1), .IN1(na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_1), .IN5(na565_1), .IN6(na4251_2), .IN7(na549_1), + .IN8(na4241_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x63y46 80'h00_0018_00_0040_0AF0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3172_1 ( .OUT(na3172_1), .IN1(na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_1), .IN5(na565_2), .IN6(na4252_2), .IN7(na549_2), + .IN8(na4242_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x20y74 80'h00_0018_00_0040_0C05_5C00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3173_1 ( .OUT(na3173_1), .IN1(na643_2), .IN2(1'b0), .IN3(na644_1), .IN4(1'b0), .IN5(1'b1), .IN6(na25_2), .IN7(~na233_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x18y74 80'h00_0018_00_0040_0C0A_5300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3174_1 ( .OUT(na3174_1), .IN1(1'b0), .IN2(na687_2), .IN3(1'b0), .IN4(na689_1), .IN5(1'b1), .IN6(~na25_2), .IN7(~na233_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x63y51 80'h00_0018_00_0000_0C66_9A00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3175_1 ( .OUT(na3175_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2222_1), .IN6(1'b0), .IN7(~na353_1), .IN8(na720_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x62y51 80'h00_0018_00_0040_0A67_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3176_1 ( .OUT(na3176_1), .IN1(na2222_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na720_1), .IN5(1'b1), .IN6(~na4175_2), .IN7(~na353_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x66y37 80'h00_0018_00_0040_0AF0_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3177_1 ( .OUT(na3177_1), .IN1(1'b1), .IN2(~na1542_2), .IN3(1'b1), .IN4(~na4463_2), .IN5(na752_1), .IN6(na4277_2), .IN7(na736_1), + .IN8(na728_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x64y38 80'h00_0018_00_0040_0AF0_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3178_1 ( .OUT(na3178_1), .IN1(1'b1), .IN2(~na1542_2), .IN3(1'b1), .IN4(~na4463_2), .IN5(na752_2), .IN6(na4278_2), .IN7(na736_2), + .IN8(na728_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x64y37 80'h00_0018_00_0040_0AF0_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3179_1 ( .OUT(na3179_1), .IN1(1'b1), .IN2(na1542_2), .IN3(1'b1), .IN4(~na4463_2), .IN5(na4279_2), .IN6(na754_1), .IN7(na730_1), + .IN8(na4271_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x66y38 80'h00_0018_00_0040_0AF0_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3180_1 ( .OUT(na3180_1), .IN1(1'b1), .IN2(na1542_2), .IN3(1'b1), .IN4(~na4463_2), .IN5(na4280_2), .IN6(na754_2), .IN7(na730_2), + .IN8(na4272_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x65y39 80'h00_0018_00_0040_0AF0_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3181_1 ( .OUT(na3181_1), .IN1(1'b1), .IN2(na1542_2), .IN3(1'b1), .IN4(~na4463_2), .IN5(na4281_2), .IN6(na756_1), .IN7(na732_1), + .IN8(na4273_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x66y40 80'h00_0018_00_0040_0AF0_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3182_1 ( .OUT(na3182_1), .IN1(1'b1), .IN2(na1542_2), .IN3(1'b1), .IN4(~na4463_2), .IN5(na4282_2), .IN6(na756_2), .IN7(na732_2), + .IN8(na4274_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x64y39 80'h00_0018_00_0040_0AF0_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3183_1 ( .OUT(na3183_1), .IN1(1'b1), .IN2(na1542_2), .IN3(1'b1), .IN4(na4463_2), .IN5(na734_1), .IN6(na4275_2), .IN7(na750_1), + .IN8(na4289_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x63y40 80'h00_0018_00_0040_0AF0_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3184_1 ( .OUT(na3184_1), .IN1(1'b1), .IN2(na1542_2), .IN3(1'b1), .IN4(na4463_2), .IN5(na734_2), .IN6(na4276_2), .IN7(na750_2), + .IN8(na4290_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x26y53 80'h00_0018_00_0000_0C66_C900 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3185_1 ( .OUT(na3185_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na4296_2), .IN6(~na878_1), .IN7(1'b0), .IN8(na2473_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x26y56 80'h00_0018_00_0040_0A67_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3186_1 ( .OUT(na3186_1), .IN1(na4520_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na864_1), .IN5(1'b1), .IN6(~na878_1), .IN7(~na4298_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x43y43 80'h00_0018_00_0040_0AF0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3187_1 ( .OUT(na3187_1), .IN1(na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1545_1), .IN5(na908_1), .IN6(na916_1), .IN7(na892_1), + .IN8(na4310_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x45y44 80'h00_0018_00_0040_0AF0_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3188_1 ( .OUT(na3188_1), .IN1(na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1545_1), .IN5(na908_2), .IN6(na916_2), .IN7(na892_2), + .IN8(na4311_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x41y42 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3189_1 ( .OUT(na3189_1), .IN1(~na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1545_1), .IN5(na4312_2), .IN6(na894_1), .IN7(na918_1), + .IN8(na4320_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x42y42 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3190_1 ( .OUT(na3190_1), .IN1(~na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1545_1), .IN5(na4313_2), .IN6(na894_2), .IN7(na918_2), + .IN8(na4321_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x43y44 80'h00_0018_00_0040_0AF0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3191_1 ( .OUT(na3191_1), .IN1(~na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1545_1), .IN5(na4326_2), .IN6(na912_1), .IN7(na4314_2), + .IN8(na896_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x39y44 80'h00_0018_00_0040_0AF0_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3192_1 ( .OUT(na3192_1), .IN1(~na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1545_1), .IN5(na4327_2), .IN6(na912_2), .IN7(na4315_2), + .IN8(na896_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x35y46 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3193_1 ( .OUT(na3193_1), .IN1(~na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1545_1), .IN5(na4316_2), .IN6(na898_1), .IN7(na922_1), + .IN8(na4322_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x43y52 80'h00_0018_00_0040_0AF0_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3194_1 ( .OUT(na3194_1), .IN1(~na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1545_1), .IN5(na4317_2), .IN6(na898_2), .IN7(na922_2), + .IN8(na4323_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x23y69 80'h00_0018_00_0040_0C05_AC00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3195_1 ( .OUT(na3195_1), .IN1(na983_2), .IN2(1'b0), .IN3(na982_2), .IN4(1'b0), .IN5(1'b1), .IN6(na25_2), .IN7(na233_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x69y62 80'h00_0018_00_0040_0AF7_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3196_1 ( .OUT(na3196_1), .IN1(~na4467_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1544_1), .IN5(~na1450_2), .IN6(~na1449_2), .IN7(~na1448_1), + .IN8(na1425_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x39y86 80'h00_0018_00_0000_0C66_9C00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3197_1 ( .OUT(na3197_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na2706_1), .IN7(~na1038_1), .IN8(na993_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x36y84 80'h00_0018_00_0040_0A67_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3198_1 ( .OUT(na3198_1), .IN1(1'b1), .IN2(na2706_1), .IN3(1'b1), .IN4(~na993_1), .IN5(1'b1), .IN6(~na4338_2), .IN7(~na1038_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x55y75 80'h00_0018_00_0040_0AF0_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3199_1 ( .OUT(na3199_1), .IN1(1'b1), .IN2(~na1543_2), .IN3(na4465_2), .IN4(1'b1), .IN5(na1060_1), .IN6(na1052_1), .IN7(na4357_2), + .IN8(na4351_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x56y73 80'h00_0018_00_0040_0AF0_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3200_1 ( .OUT(na3200_1), .IN1(1'b1), .IN2(~na1543_2), .IN3(na4465_2), .IN4(1'b1), .IN5(na1060_2), .IN6(na1052_2), .IN7(na4358_2), + .IN8(na4352_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x56y76 80'h00_0018_00_0040_0AF0_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3201_1 ( .OUT(na3201_1), .IN1(1'b1), .IN2(na1543_2), .IN3(na4465_2), .IN4(1'b1), .IN5(na1054_1), .IN6(na4344_2), .IN7(na4353_2), + .IN8(na4359_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x53y74 80'h00_0018_00_0040_0AF0_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3202_1 ( .OUT(na3202_1), .IN1(1'b1), .IN2(na1543_2), .IN3(na4465_2), .IN4(1'b1), .IN5(na1054_2), .IN6(na4345_2), .IN7(na4354_2), + .IN8(na4360_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x53y78 80'h00_0018_00_0040_0AF0_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3203_1 ( .OUT(na3203_1), .IN1(1'b1), .IN2(na1543_2), .IN3(na4465_2), .IN4(1'b1), .IN5(na1056_1), .IN6(na4346_2), .IN7(na4355_2), + .IN8(na1080_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x57y78 80'h00_0018_00_0040_0AF0_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3204_1 ( .OUT(na3204_1), .IN1(1'b1), .IN2(na1543_2), .IN3(na4465_2), .IN4(1'b1), .IN5(na1056_2), .IN6(na4347_2), .IN7(na4356_2), + .IN8(na1080_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x54y76 80'h00_0018_00_0040_0AF0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3205_1 ( .OUT(na3205_1), .IN1(1'b1), .IN2(na1543_2), .IN3(~na4465_2), .IN4(1'b1), .IN5(na1074_1), .IN6(na4363_2), .IN7(na1058_1), + .IN8(na4348_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x53y75 80'h00_0018_00_0040_0AF0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3206_1 ( .OUT(na3206_1), .IN1(1'b1), .IN2(na1543_2), .IN3(~na4465_2), .IN4(1'b1), .IN5(na1074_2), .IN6(na4364_2), .IN7(na1058_2), + .IN8(na4349_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x61y77 80'h00_0018_00_0000_0C66_9A00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3207_1 ( .OUT(na3207_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2957_2), .IN6(1'b0), .IN7(~na461_1), .IN8(na1388_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x61y82 80'h00_0018_00_0040_0A67_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3208_1 ( .OUT(na3208_1), .IN1(na2957_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1388_1), .IN5(1'b1), .IN6(~na4209_2), .IN7(~na461_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x40y59 80'h00_0018_00_0040_0AF0_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3209_1 ( .OUT(na3209_1), .IN1(1'b1), .IN2(na1541_2), .IN3(na4461_2), .IN4(1'b1), .IN5(na1200_1), .IN6(na4379_2), .IN7(na4387_2), + .IN8(na1224_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x37y58 80'h00_0018_00_0040_0AF0_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3210_1 ( .OUT(na3210_1), .IN1(1'b1), .IN2(na1541_2), .IN3(na4461_2), .IN4(1'b1), .IN5(na1200_2), .IN6(na4380_2), .IN7(na4388_2), + .IN8(na1224_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x37y64 80'h00_0018_00_0040_0AF0_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3211_1 ( .OUT(na3211_1), .IN1(1'b1), .IN2(~na1541_2), .IN3(na4461_2), .IN4(1'b1), .IN5(na1210_1), .IN6(na4375_2), .IN7(na1226_1), + .IN8(na1218_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x32y55 80'h00_0018_00_0040_0AF0_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3212_1 ( .OUT(na3212_1), .IN1(1'b1), .IN2(~na1541_2), .IN3(na4461_2), .IN4(1'b1), .IN5(na1210_2), .IN6(na4376_2), .IN7(na1226_2), + .IN8(na1218_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x33y59 80'h00_0018_00_0040_0AF0_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3213_1 ( .OUT(na3213_1), .IN1(1'b1), .IN2(~na1541_2), .IN3(na4461_2), .IN4(1'b1), .IN5(na4383_2), .IN6(na1204_1), .IN7(na4394_2), + .IN8(na1220_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x35y60 80'h00_0018_00_0040_0AF0_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3214_1 ( .OUT(na3214_1), .IN1(1'b1), .IN2(~na1541_2), .IN3(na4461_2), .IN4(1'b1), .IN5(na4384_2), .IN6(na1204_2), .IN7(na4395_2), + .IN8(na1220_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x35y64 80'h00_0018_00_0040_0AF0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3215_1 ( .OUT(na3215_1), .IN1(1'b1), .IN2(~na1541_2), .IN3(~na4461_2), .IN4(1'b1), .IN5(na1230_1), .IN6(na4389_2), .IN7(na4385_2), + .IN8(na1206_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x34y61 80'h00_0018_00_0040_0AF0_0053 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3216_1 ( .OUT(na3216_1), .IN1(1'b1), .IN2(~na1541_2), .IN3(~na4461_2), .IN4(1'b1), .IN5(na1230_2), .IN6(na4390_2), .IN7(na4386_2), + .IN8(na1206_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x17y74 80'h00_0018_00_0040_0C05_5C00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3217_1 ( .OUT(na3217_1), .IN1(na1148_2), .IN2(1'b0), .IN3(na1316_1), .IN4(1'b0), .IN5(1'b1), .IN6(na25_2), .IN7(~na233_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x35y49 80'h00_0018_00_0040_0AFE_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3218_1 ( .OUT(na3218_1), .IN1(na4468_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1545_1), .IN5(na1427_2), .IN6(~na1492_1), .IN7(~na1493_2), + .IN8(~na1494_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000090)) + _a3219 ( .Y(na3219_1), .I(i_clk) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a3220 ( .Y(na3220_1), .I(i_rstn) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010902)) + _a3221 ( .O(o_uart_tx), .A(na4065_10) ); +CC_PLL #(.PLL_CFG (96'h01_CB_01_10_64_00_04_0A_08_08_20_82), + .REF_CLK(10.00), + .OUT_CLK(16.00), + .LOW_JITTER(1), + .CI_FILTER_CONST(0), + .CP_FILTER_CONST(0)) + _a3222 ( .USR_PLL_LOCKED_STDY(_d6), .USR_PLL_LOCKED(na3222_2), .CLK270(na3222_3), .CLK180(na3222_4), .CLK90(na3222_5), .CLK0(na3222_6), + .CLK_REF_OUT(_d7), .CLK_REF(na3229_1), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0), .USR_LOCKED_STDY_RST(1'b0), .USR_SET_SEL(1'b0) ); +FPGA_RAM #(.RAM_CFG (216'h00_05_00_00_00_00_00_00_0F_04_80_00_91_03_13_23_03_13_23_00_13_23_00_13_23_00_00), + .INIT_00(320'h30000014b730000014b700cc50141300cc5014130000001417000000141700000000130000000013), + .INIT_01(320'h00015014130001501413000050088300005008830005520023000552002302c700089302c7000893), + .INIT_02(320'h00000088b700000088b700055240230005524023040023889304002388933f802268e33f802268e3), + .INIT_03(320'h3f05f3c06f3f05f3c06f3f802278e33f802278e33fcf2208933fcf2208931c402208931c40220893), + .INIT_04(320'h080731e461080731e4611cc200c4301cc200c0300c0300c0200c0300c020194721bc43194721bc43), + .INIT_05(320'h0000000000000000000000000000000000000000000000286f000000286f1b06c194681b06c19468), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000)) + _a3223 ( .DOA({_d8, _d9, _d10, _d11, _d12, _d13, _d14, _d15, _d16, _d17, _d18, _d19, _d20, _d21, _d22, _d23, _d24, _d25, + _d26, _d27, _d28, _d29, _d30, _d31, _d32, _d33, _d34, _d35, _d36, _d37, _d38, _d39, _d40, _d41, _d42, _d43, _d44, + _d45, _d46, _d47}), + .DOAX({_d48, _d49, _d50, _d51, _d52, _d53, _d54, _d55, _d56, _d57, _d58, _d59, _d60, _d61, _d62, _d63, _d64, _d65, + _d66, _d67, _d68, _d69, _d70, _d71, _d72, _d73, _d74, _d75, _d76, _d77, _d78, _d79, _d80, _d81, _d82, _d83, _d84, + _d85, _d86, _d87}), + .DOB({_d88, _d89, _d90, _d91, _d92, _d93, _d94, _d95, _d96, _d97, _d98, _d99, na3223_93, na3223_94, na3223_95, na3223_96, + na3223_97, na3223_98, na3223_99, na3223_100, _d100, _d101, _d102, _d103, _d104, _d105, _d106, _d107, _d108, _d109, + _d110, _d111, na3223_113, na3223_114, na3223_115, na3223_116, na3223_117, na3223_118, na3223_119, na3223_120}), + .DOBX({_d112, _d113, _d114, _d115, _d116, _d117, _d118, _d119, _d120, _d121, _d122, _d123, _d124, _d125, _d126, + _d127, _d128, _d129, _d130, _d131, _d132, _d133, _d134, _d135, _d136, _d137, _d138, _d139, _d140, _d141, _d142, _d143, + _d144, _d145, _d146, _d147, _d148, _d149, _d150, _d151}), + .ECC1B_ERRA({_d152, _d153, _d154, _d155}), + .ECC1B_ERRB({_d156, _d157, _d158, _d159}), + .ECC2B_ERRA({_d160, _d161, _d162, _d163}), + .ECC2B_ERRB({_d164, _d165, _d166, _d167}), + .FORW_CAS_WRAO(_d168), .FORW_CAS_WRBO(_d169), .FORW_CAS_BMAO(_d170), .FORW_CAS_BMBO(_d171), .FORW_CAS_RDAO(_d172), + .FORW_CAS_RDBO(_d173), .FORW_UADDRAO({_d174, _d175, _d176, _d177, _d178, _d179, _d180, _d181, _d182, _d183, _d184, + _d185, _d186, _d187, _d188, _d189}), + .FORW_LADDRAO({_d190, _d191, _d192, _d193, _d194, _d195, _d196, _d197, _d198, _d199, _d200, _d201, _d202, _d203, + _d204, _d205}), + .FORW_UADDRBO({_d206, _d207, _d208, _d209, _d210, _d211, _d212, _d213, _d214, _d215, _d216, _d217, _d218, _d219, + _d220, _d221}), + .FORW_LADDRBO({_d222, _d223, _d224, _d225, _d226, _d227, _d228, _d229, _d230, _d231, _d232, _d233, _d234, _d235, + _d236, _d237}), + .FORW_UA0CLKO(_d238), .FORW_UA0ENO(_d239), .FORW_UA0WEO(_d240), .FORW_LA0CLKO(_d241), .FORW_LA0ENO(_d242), .FORW_LA0WEO(_d243), + .FORW_UA1CLKO(_d244), .FORW_UA1ENO(_d245), .FORW_UA1WEO(_d246), .FORW_LA1CLKO(_d247), .FORW_LA1ENO(_d248), .FORW_LA1WEO(_d249), + .FORW_UB0CLKO(_d250), .FORW_UB0ENO(_d251), .FORW_UB0WEO(_d252), .FORW_LB0CLKO(_d253), .FORW_LB0ENO(_d254), .FORW_LB0WEO(_d255), + .FORW_UB1CLKO(_d256), .FORW_UB1ENO(_d257), .FORW_UB1WEO(_d258), .FORW_LB1CLKO(_d259), .FORW_LB1ENO(_d260), .FORW_LB1WEO(_d261), + .CLOCKA({_d262, _d263, _d264, _d265}), + .CLOCKB({_d266, _d267, _d268, _d269}), + .CLKA({1'b1, 1'b1, 1'b1, 1'b1}), + .CLKB({1'b1, 1'b1, 1'b1, 1'b1}), + .ENA({1'b1, 1'b1, 1'b1, 1'b1}), + .ENB({1'b1, 1'b1, 1'b1, 1'b1}), + .GLWEA({1'b1, na3224_10, 1'b1, na3227_10}), + .GLWEB({1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA0({na3232_10, na3233_9, na3236_10, na3237_9, na3238_10, na3239_9, na3240_10, na3242_9, na3244_10, na3245_9, + na3250_10, na3251_9, na3253_10, na3257_9, na3261_10, na3264_9}), + .ADDRA1({na3265_10, na3266_9, na3269_10, na3271_9, na3273_10, na3277_9, na3280_10, na3284_9, na3286_10, na3289_9, + na3291_10, na3293_9, na3294_10, na3295_9, na3297_10, na3299_9}), + .ADDRA0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB0({na3300_10, na3304_9, na3306_10, na3308_9, na3309_10, na3311_9, na3314_10, na3315_9, na3318_10, na3319_9, + na3320_10, na3321_9, na3323_10, na3325_9, na3326_10, na3330_9}), + .ADDRB0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB1({na3332_10, na3333_9, na3337_10, na3339_9, na3340_10, na3344_9, na3345_10, na3347_9, na3349_10, na3350_9, + na3351_10, na3352_9, na3353_10, na3354_9, na3355_10, na3356_9}), + .ADDRB1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .DIA({na3357_10, na3358_9, na3359_10, na3360_9, na3361_10, na3362_9, na3363_10, na3364_9, na3365_10, na3366_9, 1'b1, + 1'b1, na3367_10, na3368_9, na3369_10, na3370_9, na3371_10, na3372_9, na3373_10, na3374_9, na3375_10, na3376_9, na3377_10, + na3378_9, na3379_10, na3380_9, na3381_10, na3382_9, na3383_10, na3384_9, 1'b1, 1'b1, na3385_10, na3386_9, na3387_10, + na3388_9, na3389_10, na3390_9, na3391_10, na3392_9}), + .DIB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .WEA({na3393_10, na3394_9, na3395_10, na3396_9, na3397_10, na3398_9, na3399_10, na3400_9, na3401_10, na3402_9, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, na3403_10, na3404_9, na3405_10, na3406_9, na3407_10, na3408_9, + na3409_10, na3410_9, na3411_10, na3412_9, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .WEB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .CLOCK1(na1739_1), .CLOCK2(1'b1), .CLOCK3(1'b1), .CLOCK4(1'b1), .FORW_CAS_WRAI(1'b1), .FORW_CAS_WRBI(1'b1), .FORW_CAS_BMAI(1'b1), + .FORW_CAS_BMBI(1'b1), .FORW_CAS_RDAI(1'b1), .FORW_CAS_RDBI(1'b1), .FORW_LADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LA0CLKI(1'b1), .FORW_LA0ENI(1'b1), .FORW_LA0WEI(1'b1), .FORW_UA0CLKI(1'b1), .FORW_UA0ENI(1'b1), .FORW_UA0WEI(1'b1), + .FORW_LA1CLKI(1'b1), .FORW_LA1ENI(1'b1), .FORW_LA1WEI(1'b1), .FORW_UA1CLKI(1'b1), .FORW_UA1ENI(1'b1), .FORW_UA1WEI(1'b1), + .FORW_LB0CLKI(1'b1), .FORW_LB0ENI(1'b1), .FORW_LB0WEI(1'b1), .FORW_UB0CLKI(1'b1), .FORW_UB0ENI(1'b1), .FORW_UB0WEI(1'b1), + .FORW_LB1CLKI(1'b1), .FORW_LB1ENI(1'b1), .FORW_LB1WEI(1'b1), .FORW_UB1CLKI(1'b1), .FORW_UB1ENI(1'b1), .FORW_UB1WEI(1'b1) ); +// C_///AND/ x27y41 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3224_4 ( .OUT(na3224_2), .IN1(1'b1), .IN2(na1091_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3224_6 ( .RAM_O2(na3224_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3224_2), .COMP_OUT(1'b0) ); +FPGA_RAM #(.RAM_CFG (216'h00_05_00_00_00_00_00_00_0A_04_00_00_81_03_13_23_00_00_23_00_13_23_00_00_23_00_00), + .INIT_00(320'h30000014b7000000000000cc50141300000000000000001417000000000000000000130000000000), + .INIT_01(320'h00015014130000000000000050088300000000000005520023000000000002c70008930000000000), + .INIT_02(320'h00000088b7000000000000055240230000000000040023889300000000003f802268e30000000000), + .INIT_03(320'h3f05f3c06f00000000003f802278e300000000003fcf22089300000000001c402208930000000000), + .INIT_04(320'h080731e46100000000001cc200c83000000000000c0300c0200000000000194721bc430000000000), + .INIT_05(320'h0000000000000000000000000000000000000000000000286f00000000001b06c194680000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000)) + _a3225 ( .DOA({_d270, _d271, _d272, _d273, _d274, _d275, _d276, _d277, _d278, _d279, _d280, _d281, _d282, _d283, _d284, _d285, + _d286, _d287, _d288, _d289, _d290, _d291, _d292, _d293, _d294, _d295, _d296, _d297, _d298, _d299, _d300, _d301, _d302, + _d303, _d304, _d305, _d306, _d307, _d308, _d309}), + .DOAX({_d310, _d311, _d312, _d313, _d314, _d315, _d316, _d317, _d318, _d319, _d320, _d321, _d322, _d323, _d324, + _d325, _d326, _d327, _d328, _d329, _d330, _d331, _d332, _d333, _d334, _d335, _d336, _d337, _d338, _d339, _d340, _d341, + _d342, _d343, _d344, _d345, _d346, _d347, _d348, _d349}), + .DOB({_d350, _d351, _d352, _d353, _d354, _d355, _d356, _d357, _d358, _d359, _d360, _d361, na3225_93, na3225_94, + na3225_95, na3225_96, na3225_97, na3225_98, na3225_99, na3225_100, _d362, _d363, _d364, _d365, _d366, _d367, _d368, + _d369, _d370, _d371, _d372, _d373, _d374, _d375, _d376, _d377, _d378, _d379, _d380, _d381}), + .DOBX({_d382, _d383, _d384, _d385, _d386, _d387, _d388, _d389, _d390, _d391, _d392, _d393, _d394, _d395, _d396, + _d397, _d398, _d399, _d400, _d401, _d402, _d403, _d404, _d405, _d406, _d407, _d408, _d409, _d410, _d411, _d412, _d413, + _d414, _d415, _d416, _d417, _d418, _d419, _d420, _d421}), + .ECC1B_ERRA({_d422, _d423, _d424, _d425}), + .ECC1B_ERRB({_d426, _d427, _d428, _d429}), + .ECC2B_ERRA({_d430, _d431, _d432, _d433}), + .ECC2B_ERRB({_d434, _d435, _d436, _d437}), + .FORW_CAS_WRAO(_d438), .FORW_CAS_WRBO(_d439), .FORW_CAS_BMAO(_d440), .FORW_CAS_BMBO(_d441), .FORW_CAS_RDAO(_d442), + .FORW_CAS_RDBO(_d443), .FORW_UADDRAO({_d444, _d445, _d446, _d447, _d448, _d449, _d450, _d451, _d452, _d453, _d454, + _d455, _d456, _d457, _d458, _d459}), + .FORW_LADDRAO({_d460, _d461, _d462, _d463, _d464, _d465, _d466, _d467, _d468, _d469, _d470, _d471, _d472, _d473, + _d474, _d475}), + .FORW_UADDRBO({_d476, _d477, _d478, _d479, _d480, _d481, _d482, _d483, _d484, _d485, _d486, _d487, _d488, _d489, + _d490, _d491}), + .FORW_LADDRBO({_d492, _d493, _d494, _d495, _d496, _d497, _d498, _d499, _d500, _d501, _d502, _d503, _d504, _d505, + _d506, _d507}), + .FORW_UA0CLKO(_d508), .FORW_UA0ENO(_d509), .FORW_UA0WEO(_d510), .FORW_LA0CLKO(_d511), .FORW_LA0ENO(_d512), .FORW_LA0WEO(_d513), + .FORW_UA1CLKO(_d514), .FORW_UA1ENO(_d515), .FORW_UA1WEO(_d516), .FORW_LA1CLKO(_d517), .FORW_LA1ENO(_d518), .FORW_LA1WEO(_d519), + .FORW_UB0CLKO(_d520), .FORW_UB0ENO(_d521), .FORW_UB0WEO(_d522), .FORW_LB0CLKO(_d523), .FORW_LB0ENO(_d524), .FORW_LB0WEO(_d525), + .FORW_UB1CLKO(_d526), .FORW_UB1ENO(_d527), .FORW_UB1WEO(_d528), .FORW_LB1CLKO(_d529), .FORW_LB1ENO(_d530), .FORW_LB1WEO(_d531), + .CLOCKA({_d532, _d533, _d534, _d535}), + .CLOCKB({_d536, _d537, _d538, _d539}), + .CLKA({1'b1, 1'b1, 1'b1, 1'b1}), + .CLKB({1'b1, 1'b1, 1'b1, 1'b1}), + .ENA({1'b1, 1'b1, 1'b1, 1'b1}), + .ENB({1'b1, 1'b1, 1'b1, 1'b1}), + .GLWEA({1'b1, na3446_10, 1'b1, 1'b1}), + .GLWEB({1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA0({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA1({na3449_10, na3450_9, na3454_10, na3455_9, na3456_10, na3460_9, na3468_10, na3469_9, na3473_10, na3474_9, + na3475_10, na3476_9, na3477_10, na3478_9, na3479_10, na3480_9}), + .ADDRA0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB0({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB1({na3481_10, na3482_9, na3483_10, na3484_9, na3485_10, na3486_9, na3487_10, na3488_9, na3489_10, na3490_9, + na3491_10, na3492_9, na3493_10, na3494_9, na3495_10, na3496_9}), + .ADDRB1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .DIA({na3497_10, na3498_9, na3499_10, na3500_9, na3501_10, na3502_9, na3503_10, na3504_9, na3505_10, na3506_9, 1'b1, + 1'b1, na3507_10, na3508_9, na3509_10, na3510_9, na3511_10, na3512_9, na3513_10, na3514_9, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .DIB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .WEA({na3515_10, na3516_9, na3517_10, na3518_9, na3519_10, na3520_9, na3521_10, na3522_9, na3523_10, na3524_9, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .WEB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .CLOCK1(na1739_1), .CLOCK2(1'b1), .CLOCK3(1'b1), .CLOCK4(1'b1), .FORW_CAS_WRAI(1'b1), .FORW_CAS_WRBI(1'b1), .FORW_CAS_BMAI(1'b1), + .FORW_CAS_BMBI(1'b1), .FORW_CAS_RDAI(1'b1), .FORW_CAS_RDBI(1'b1), .FORW_LADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LA0CLKI(1'b1), .FORW_LA0ENI(1'b1), .FORW_LA0WEI(1'b1), .FORW_UA0CLKI(1'b1), .FORW_UA0ENI(1'b1), .FORW_UA0WEI(1'b1), + .FORW_LA1CLKI(1'b1), .FORW_LA1ENI(1'b1), .FORW_LA1WEI(1'b1), .FORW_UA1CLKI(1'b1), .FORW_UA1ENI(1'b1), .FORW_UA1WEI(1'b1), + .FORW_LB0CLKI(1'b1), .FORW_LB0ENI(1'b1), .FORW_LB0WEI(1'b1), .FORW_UB0CLKI(1'b1), .FORW_UB0ENI(1'b1), .FORW_UB0WEI(1'b1), + .FORW_LB1CLKI(1'b1), .FORW_LB1ENI(1'b1), .FORW_LB1WEI(1'b1), .FORW_UB1CLKI(1'b1), .FORW_UB1ENI(1'b1), .FORW_UB1WEI(1'b1) ); +FPGA_RAM #(.RAM_CFG (216'h00_05_00_00_00_00_00_00_0F_04_80_00_91_03_13_23_03_13_23_00_13_23_00_13_23_00_00), + .INIT_00(320'h30000014b730000014b700cc50141300cc5014130000001417000000141700000000130000000013), + .INIT_01(320'h00015014130001501413000050088300005008830005520023000552002302c700089302c7000893), + .INIT_02(320'h00000088b700000088b700055240230005524023040023889304002388933f802268e33f802268e3), + .INIT_03(320'h3f05f3c06f3f05f3c06f3f802278e33f802278e33fcf2208933fcf2208931c402208931c40220893), + .INIT_04(320'h080731e461080731e4611cc200d0301cc200cc300c0300c0200c0300c020194721bc43194721bc43), + .INIT_05(320'h0000000000000000000000000000000000000000000000286f000000286f1b06c194681b06c19468), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000)) + _a3226 ( .DOA({_d540, _d541, _d542, _d543, _d544, _d545, _d546, _d547, _d548, _d549, _d550, _d551, _d552, _d553, _d554, _d555, + _d556, _d557, _d558, _d559, _d560, _d561, _d562, _d563, _d564, _d565, _d566, _d567, _d568, _d569, _d570, _d571, _d572, + _d573, _d574, _d575, _d576, _d577, _d578, _d579}), + .DOAX({_d580, _d581, _d582, _d583, _d584, _d585, _d586, _d587, _d588, _d589, _d590, _d591, _d592, _d593, _d594, + _d595, _d596, _d597, _d598, _d599, _d600, _d601, _d602, _d603, _d604, _d605, _d606, _d607, _d608, _d609, _d610, _d611, + _d612, _d613, _d614, _d615, _d616, _d617, _d618, _d619}), + .DOB({_d620, _d621, _d622, _d623, _d624, _d625, _d626, _d627, _d628, _d629, _d630, _d631, na3226_93, na3226_94, + na3226_95, na3226_96, na3226_97, na3226_98, na3226_99, na3226_100, _d632, _d633, _d634, _d635, _d636, _d637, _d638, + _d639, _d640, _d641, _d642, _d643, na3226_113, na3226_114, na3226_115, na3226_116, na3226_117, na3226_118, na3226_119, + na3226_120}), + .DOBX({_d644, _d645, _d646, _d647, _d648, _d649, _d650, _d651, _d652, _d653, _d654, _d655, _d656, _d657, _d658, + _d659, _d660, _d661, _d662, _d663, _d664, _d665, _d666, _d667, _d668, _d669, _d670, _d671, _d672, _d673, _d674, _d675, + _d676, _d677, _d678, _d679, _d680, _d681, _d682, _d683}), + .ECC1B_ERRA({_d684, _d685, _d686, _d687}), + .ECC1B_ERRB({_d688, _d689, _d690, _d691}), + .ECC2B_ERRA({_d692, _d693, _d694, _d695}), + .ECC2B_ERRB({_d696, _d697, _d698, _d699}), + .FORW_CAS_WRAO(_d700), .FORW_CAS_WRBO(_d701), .FORW_CAS_BMAO(_d702), .FORW_CAS_BMBO(_d703), .FORW_CAS_RDAO(_d704), + .FORW_CAS_RDBO(_d705), .FORW_UADDRAO({_d706, _d707, _d708, _d709, _d710, _d711, _d712, _d713, _d714, _d715, _d716, + _d717, _d718, _d719, _d720, _d721}), + .FORW_LADDRAO({_d722, _d723, _d724, _d725, _d726, _d727, _d728, _d729, _d730, _d731, _d732, _d733, _d734, _d735, + _d736, _d737}), + .FORW_UADDRBO({_d738, _d739, _d740, _d741, _d742, _d743, _d744, _d745, _d746, _d747, _d748, _d749, _d750, _d751, + _d752, _d753}), + .FORW_LADDRBO({_d754, _d755, _d756, _d757, _d758, _d759, _d760, _d761, _d762, _d763, _d764, _d765, _d766, _d767, + _d768, _d769}), + .FORW_UA0CLKO(_d770), .FORW_UA0ENO(_d771), .FORW_UA0WEO(_d772), .FORW_LA0CLKO(_d773), .FORW_LA0ENO(_d774), .FORW_LA0WEO(_d775), + .FORW_UA1CLKO(_d776), .FORW_UA1ENO(_d777), .FORW_UA1WEO(_d778), .FORW_LA1CLKO(_d779), .FORW_LA1ENO(_d780), .FORW_LA1WEO(_d781), + .FORW_UB0CLKO(_d782), .FORW_UB0ENO(_d783), .FORW_UB0WEO(_d784), .FORW_LB0CLKO(_d785), .FORW_LB0ENO(_d786), .FORW_LB0WEO(_d787), + .FORW_UB1CLKO(_d788), .FORW_UB1ENO(_d789), .FORW_UB1WEO(_d790), .FORW_LB1CLKO(_d791), .FORW_LB1ENO(_d792), .FORW_LB1WEO(_d793), + .CLOCKA({_d794, _d795, _d796, _d797}), + .CLOCKB({_d798, _d799, _d800, _d801}), + .CLKA({1'b1, 1'b1, 1'b1, 1'b1}), + .CLKB({1'b1, 1'b1, 1'b1, 1'b1}), + .ENA({1'b1, 1'b1, 1'b1, 1'b1}), + .ENB({1'b1, 1'b1, 1'b1, 1'b1}), + .GLWEA({1'b1, na3533_10, 1'b1, na3534_10}), + .GLWEB({1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA0({na3535_10, na3536_9, na3537_10, na3538_9, na3540_10, na3541_9, na3544_10, na3545_9, na3547_10, na3548_9, + na3550_10, na3551_9, na3553_10, na3554_9, na3563_10, na3566_9}), + .ADDRA1({na3567_10, na3568_9, na3569_10, na3572_9, na3573_10, na3574_9, na3577_10, na3579_9, na3581_10, na3583_9, + na3584_10, na3586_9, na3587_10, na3591_9, na3592_10, na3593_9}), + .ADDRA0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB0({na3594_10, na3595_9, na3596_10, na3597_9, na3598_10, na3599_9, na3600_10, na3601_9, na3602_10, na3603_9, + na3604_10, na3605_9, na3606_10, na3607_9, na3608_10, na3609_9}), + .ADDRB0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB1({na3610_10, na3611_9, na3612_10, na3613_9, na3614_10, na3615_9, na3616_10, na3617_9, na3618_10, na3619_9, + na3620_10, na3621_9, na3622_10, na3623_9, na3624_10, na3625_9}), + .ADDRB1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .DIA({na3626_10, na3627_9, na3628_10, na3629_9, na3630_10, na3631_9, na3632_10, na3633_9, na3634_10, na3635_9, 1'b1, + 1'b1, na3636_10, na3637_9, na3638_10, na3639_9, na3640_10, na3641_9, na3642_10, na3643_9, na3644_10, na3645_9, na3646_10, + na3647_9, na3648_10, na3649_9, na3650_10, na3651_9, na3652_10, na3653_9, 1'b1, 1'b1, na3654_10, na3655_9, na3656_10, + na3658_9, na3659_10, na3662_9, na3663_10, na3665_9}), + .DIB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .WEA({na3666_10, na3668_9, na3669_10, na3671_9, na3672_10, na3681_9, na3684_10, na3685_9, na3686_10, na3687_9, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, na3690_10, na3691_9, na3692_10, na3696_9, na3699_10, na3702_9, + na3704_10, na3705_9, na3709_10, na3710_9, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .WEB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .CLOCK1(na1739_1), .CLOCK2(1'b1), .CLOCK3(1'b1), .CLOCK4(1'b1), .FORW_CAS_WRAI(1'b1), .FORW_CAS_WRBI(1'b1), .FORW_CAS_BMAI(1'b1), + .FORW_CAS_BMBI(1'b1), .FORW_CAS_RDAI(1'b1), .FORW_CAS_RDBI(1'b1), .FORW_LADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LA0CLKI(1'b1), .FORW_LA0ENI(1'b1), .FORW_LA0WEI(1'b1), .FORW_UA0CLKI(1'b1), .FORW_UA0ENI(1'b1), .FORW_UA0WEI(1'b1), + .FORW_LA1CLKI(1'b1), .FORW_LA1ENI(1'b1), .FORW_LA1WEI(1'b1), .FORW_UA1CLKI(1'b1), .FORW_UA1ENI(1'b1), .FORW_UA1WEI(1'b1), + .FORW_LB0CLKI(1'b1), .FORW_LB0ENI(1'b1), .FORW_LB0WEI(1'b1), .FORW_UB0CLKI(1'b1), .FORW_UB0ENI(1'b1), .FORW_UB0WEI(1'b1), + .FORW_LB1CLKI(1'b1), .FORW_LB1ENI(1'b1), .FORW_LB1WEI(1'b1), .FORW_UB1CLKI(1'b1), .FORW_UB1ENI(1'b1), .FORW_UB1WEI(1'b1) ); +// C_///AND/ x27y33 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3227_4 ( .OUT(na3227_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1233_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3227_6 ( .RAM_O2(na3227_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3227_2), .COMP_OUT(1'b0) ); +// C_AND//// x53y63 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3228_1 ( .OUT(na3228_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na709_1), .IN6(1'b1), .IN7(~na2278_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +CLKIN #(.CLKIN_CFG (32'h0000_0000)) + _a3229 ( .PCLK0(na3229_1), .PCLK1(na3229_2), .PCLK2(_d802), .PCLK3(_d803), .CLK0(na3219_1), .CLK1(1'b0), .CLK2(1'b0), .CLK3(1'b0), + .SER_CLK(1'b0), .SPI_CLK(1'b0), .JTAG_CLK(1'b0) ); +// C_///AND/ x52y88 80'h00_0060_00_0000_0C08_FF35 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3230_4 ( .OUT(na3230_2), .IN1(~na2769_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1050_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_////RAM_I2 x1y128 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3231_5 ( .OUT(na3231_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3222_2), .CP_O(1'b0) ); +// C_///AND/ x28y40 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3232_4 ( .OUT(na3232_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3232_6 ( .RAM_O2(na3232_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3232_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y40 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3233_1 ( .OUT(na3233_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3233_6 ( .RAM_O1(na3233_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3233_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x46y44 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a3234_2 ( .OUT(na3234_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a3234_6 ( .COUTY1(na3234_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3234_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x13y49 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a3235_2 ( .OUT(na3235_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a3235_6 ( .COUTY1(na3235_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3235_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y39 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3236_4 ( .OUT(na3236_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3236_6 ( .RAM_O2(na3236_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3236_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y39 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3237_1 ( .OUT(na3237_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na427_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3237_6 ( .RAM_O1(na3237_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3237_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y38 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3238_4 ( .OUT(na3238_2), .IN1(1'b1), .IN2(na1245_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3238_6 ( .RAM_O2(na3238_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3238_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y38 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3239_1 ( .OUT(na3239_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1243_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3239_6 ( .RAM_O1(na3239_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3239_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y37 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3240_4 ( .OUT(na3240_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1241_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3240_6 ( .RAM_O2(na3240_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3240_2), .COMP_OUT(1'b0) ); +// C_///AND/ x65y72 80'h00_0060_00_0000_0C08_FF1C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3241_4 ( .OUT(na3241_2), .IN1(1'b1), .IN2(na1986_1), .IN3(~na4485_2), .IN4(~na1990_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y37 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3242_1 ( .OUT(na3242_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1239_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3242_6 ( .RAM_O1(na3242_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3242_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_OR//// x64y74 80'h00_0018_00_0000_0EEE_3770 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3243_1 ( .OUT(na3243_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na107_1), .IN4(~na104_1), .IN5(~na109_1), .IN6(~na428_1), .IN7(1'b0), + .IN8(~na108_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y36 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3244_4 ( .OUT(na3244_2), .IN1(1'b1), .IN2(na1237_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3244_6 ( .RAM_O2(na3244_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3244_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y36 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3245_1 ( .OUT(na3245_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3245_6 ( .RAM_O1(na3245_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3245_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_OR//// x45y77 80'h00_0018_00_0000_0EEE_C75D +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3246_1 ( .OUT(na3246_1), .IN1(~na984_1), .IN2(na285_2), .IN3(~na83_2), .IN4(1'b0), .IN5(~na1060_1), .IN6(~na12_1), .IN7(1'b0), + .IN8(na4153_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x56y65 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a3247_2 ( .OUT(na3247_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a3247_6 ( .COUTY1(na3247_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3247_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_OR//// x52y68 80'h00_0018_00_0000_0EEE_7C73 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3248_1 ( .OUT(na3248_1), .IN1(1'b0), .IN2(~na4_1), .IN3(~na83_2), .IN4(~na645_1), .IN5(1'b0), .IN6(na285_1), .IN7(~na736_1), + .IN8(~na4154_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x48y76 80'h00_0018_00_0000_0888_A2C2 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3249_1 ( .OUT(na3249_1), .IN1(na1290_1), .IN2(~na285_1), .IN3(1'b1), .IN4(na1208_1), .IN5(na145_1), .IN6(~na285_2), .IN7(na8_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y35 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3250_4 ( .OUT(na3250_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1236_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3250_6 ( .RAM_O2(na3250_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3250_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y35 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3251_1 ( .OUT(na3251_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1235_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3251_6 ( .RAM_O1(na3251_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3251_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_XOR//// x16y64 80'h00_0018_00_0000_0C66_C900 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3252_1 ( .OUT(na3252_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1483_2), .IN6(~na180_1), .IN7(1'b0), .IN8(na178_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y34 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3253_4 ( .OUT(na3253_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3253_6 ( .RAM_O2(na3253_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3253_2), .COMP_OUT(1'b0) ); +// C_///AND/ x16y60 80'h00_0060_00_0000_0C08_FF55 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3254_4 ( .OUT(na3254_2), .IN1(~na2479_2), .IN2(1'b1), .IN3(~na2481_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x17y61 80'h00_0018_00_0000_0888_FC3E +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3255_1 ( .OUT(na3255_1), .IN1(na216_1), .IN2(na3258_1), .IN3(1'b0), .IN4(~na3256_2), .IN5(1'b0), .IN6(na3258_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x16y58 80'h00_0060_00_0000_0C08_FF75 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a3256_4 ( .OUT(na3256_2), .IN1(~na181_1), .IN2(1'b0), .IN3(~na2481_1), .IN4(~na214_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y34 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3257_1 ( .OUT(na3257_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3257_6 ( .RAM_O1(na3257_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3257_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND///AND/ x19y60 80'h00_0078_00_0000_0C88_CA58 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3258_1 ( .OUT(na3258_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na216_2), .IN6(1'b1), .IN7(1'b1), .IN8(na214_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3258_4 ( .OUT(na3258_2), .IN1(na4528_2), .IN2(na2478_1), .IN3(~na2481_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x17y47 80'h00_0018_00_0000_0EEE_07C7 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3259_1 ( .OUT(na3259_1), .IN1(~na212_1), .IN2(~na209_1), .IN3(1'b0), .IN4(na208_1), .IN5(~na210_1), .IN6(~na1476_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x24y56 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a3260_2 ( .OUT(na3260_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a3260_6 ( .COUTY1(na3260_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3260_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y33 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3261_4 ( .OUT(na3261_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3261_6 ( .RAM_O2(na3261_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3261_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x17y46 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3262_1 ( .OUT(na3262_1), .IN1(1'b1), .IN2(na122_1), .IN3(1'b0), .IN4(1'b0), .IN5(na2505_2), .IN6(na132_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x14y59 80'h00_0018_00_0000_0EEE_5733 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3263_1 ( .OUT(na3263_1), .IN1(1'b0), .IN2(~na209_1), .IN3(1'b0), .IN4(~na208_1), .IN5(~na210_1), .IN6(~na1353_1), .IN7(~na211_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y33 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3264_1 ( .OUT(na3264_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3264_6 ( .RAM_O1(na3264_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3264_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y48 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3265_4 ( .OUT(na3265_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3265_6 ( .RAM_O2(na3265_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3265_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y48 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3266_1 ( .OUT(na3266_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3266_6 ( .RAM_O1(na3266_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3266_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x38y61 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a3267_2 ( .OUT(na3267_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a3267_6 ( .COUTY1(na3267_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3267_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_XOR///XOR/ x20y90 80'h00_0078_00_0000_0C66_0990 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3268_1 ( .OUT(na3268_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2819_2), .IN6(~na387_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3268_4 ( .OUT(na3268_2), .IN1(1'b0), .IN2(1'b0), .IN3(~na388_1), .IN4(na2821_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y47 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3269_4 ( .OUT(na3269_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3269_6 ( .RAM_O2(na3269_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3269_2), .COMP_OUT(1'b0) ); +// C_///AND/ x46y88 80'h00_0060_00_0000_0C08_FF43 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3270_4 ( .OUT(na3270_2), .IN1(1'b1), .IN2(~na4546_2), .IN3(~na2713_2), .IN4(na2707_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y47 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3271_1 ( .OUT(na3271_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na822_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3271_6 ( .RAM_O1(na3271_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3271_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_XOR//// x60y66 80'h00_0018_00_0000_0C66_6500 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3272_1 ( .OUT(na3272_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na253_1), .IN6(1'b0), .IN7(na251_2), .IN8(na1461_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y46 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3273_4 ( .OUT(na3273_2), .IN1(na1103_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3273_6 ( .RAM_O2(na3273_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3273_2), .COMP_OUT(1'b0) ); +// C_///AND/ x57y60 80'h00_0060_00_0000_0C08_FFF1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3274_4 ( .OUT(na3274_2), .IN1(~na2229_1), .IN2(~na2228_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x60y64 80'h00_0018_00_0000_0888_FAE3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3275_1 ( .OUT(na3275_1), .IN1(1'b0), .IN2(~na3276_1), .IN3(na297_1), .IN4(na4583_2), .IN5(na3278_2), .IN6(1'b0), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x57y60 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3276_1 ( .OUT(na3276_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4512_2), .IN6(~na295_2), .IN7(~na254_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y46 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3277_1 ( .OUT(na3277_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1101_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3277_6 ( .RAM_O1(na3277_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3277_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND///AND/ x57y61 80'h00_0078_00_0000_0C88_ACC4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3278_1 ( .OUT(na3278_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na295_1), .IN7(na297_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3278_4 ( .OUT(na3278_2), .IN1(~na2229_1), .IN2(na2228_2), .IN3(1'b1), .IN4(na4511_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x31y68 80'h00_0018_00_0000_0CEE_5300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3279_1 ( .OUT(na3279_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na25_2), .IN7(~na4109_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y45 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3280_4 ( .OUT(na3280_2), .IN1(na1099_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3280_6 ( .RAM_O2(na3280_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3280_2), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x62y36 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a3281_2 ( .OUT(na3281_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a3281_6 ( .COUTY1(na3281_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3281_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_Route1//// x52y81 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a3282_1 ( .OUT(na3282_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1646_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_Route1//// x67y70 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a3283_1 ( .OUT(na3283_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1662_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y45 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3284_1 ( .OUT(na3284_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1097_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3284_6 ( .RAM_O1(na3284_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3284_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_Route1//// x46y90 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a3285_1 ( .OUT(na3285_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1671_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y44 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3286_4 ( .OUT(na3286_2), .IN1(1'b1), .IN2(na1095_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3286_6 ( .RAM_O2(na3286_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3286_2), .COMP_OUT(1'b0) ); +// C_AND//// x21y59 80'h00_0018_00_0000_0C88_54FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3287_1 ( .OUT(na3287_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na4528_2), .IN6(na2474_1), .IN7(~na4523_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_Route1//// x64y49 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a3288_1 ( .OUT(na3288_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1699_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y44 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3289_1 ( .OUT(na3289_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3289_6 ( .RAM_O1(na3289_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3289_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND///AND/ x49y71 80'h00_0078_00_0000_0C88_ACAC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3290_1 ( .OUT(na3290_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na285_2), .IN7(na139_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3290_4 ( .OUT(na3290_2), .IN1(1'b1), .IN2(na285_1), .IN3(na139_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y43 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3291_4 ( .OUT(na3291_2), .IN1(1'b1), .IN2(na1094_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3291_6 ( .RAM_O2(na3291_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3291_2), .COMP_OUT(1'b0) ); +// C_AND//// x22y74 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3292_1 ( .OUT(na3292_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na317_2), .IN8(na4142_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y43 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3293_1 ( .OUT(na3293_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1093_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3293_6 ( .RAM_O1(na3293_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3293_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y42 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3294_4 ( .OUT(na3294_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3294_6 ( .RAM_O2(na3294_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3294_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y42 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3295_1 ( .OUT(na3295_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3295_6 ( .RAM_O1(na3295_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3295_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_XOR///XOR/ x45y57 80'h00_0078_00_0000_0C66_9090 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3296_1 ( .OUT(na3296_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na713_2), .IN8(~na270_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3296_4 ( .OUT(na3296_2), .IN1(1'b0), .IN2(1'b0), .IN3(na713_1), .IN4(~na270_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y41 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3297_4 ( .OUT(na3297_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3297_6 ( .RAM_O2(na3297_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3297_2), .COMP_OUT(1'b0) ); +// C_AND//// x61y57 80'h00_0018_00_0000_0C88_25FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3298_1 ( .OUT(na3298_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2229_2), .IN6(1'b1), .IN7(na2223_1), .IN8(~na4504_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y41 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3299_1 ( .OUT(na3299_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3299_6 ( .RAM_O1(na3299_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3299_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y40 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3300_4 ( .OUT(na3300_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3300_6 ( .RAM_O2(na3300_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3300_2), .COMP_OUT(1'b0) ); +// C_AND//// x57y70 80'h00_0018_00_0000_0C88_F2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3301_1 ( .OUT(na3301_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na349_2), .IN6(~na295_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x68y59 80'h00_0060_00_0000_0C06_FFC5 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3302_4 ( .OUT(na3302_2), .IN1(~na351_1), .IN2(1'b0), .IN3(1'b0), .IN4(na4503_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_Route1//// x47y55 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a3303_1 ( .OUT(na3303_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1702_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y40 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3304_1 ( .OUT(na3304_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3304_6 ( .RAM_O1(na3304_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3304_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x66y48 80'h00_0060_00_0000_0C08_FF55 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3305_4 ( .OUT(na3305_2), .IN1(~na2222_1), .IN2(1'b1), .IN3(~na2223_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y39 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3306_4 ( .OUT(na3306_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3306_6 ( .RAM_O2(na3306_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3306_2), .COMP_OUT(1'b0) ); +// C_///AND/ x35y81 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3307_4 ( .OUT(na3307_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na287_2), .IN4(na1296_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y39 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3308_1 ( .OUT(na3308_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na427_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3308_6 ( .RAM_O1(na3308_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3308_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y38 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3309_4 ( .OUT(na3309_2), .IN1(1'b1), .IN2(na1288_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3309_6 ( .RAM_O2(na3309_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3309_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x22y68 80'h00_0018_00_0000_0C88_B5FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3310_1 ( .OUT(na3310_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na408_1), .IN6(1'b0), .IN7(na4073_2), .IN8(~na27_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y38 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3311_1 ( .OUT(na3311_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1286_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3311_6 ( .RAM_O1(na3311_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3311_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x22y67 80'h00_0018_00_0000_0C88_42FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3312_1 ( .OUT(na3312_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na157_1), .IN6(~na690_1), .IN7(~na11_1), .IN8(na16_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x23y66 80'h00_0018_00_0000_0EEE_57C3 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3313_1 ( .OUT(na3313_1), .IN1(1'b0), .IN2(~na978_1), .IN3(1'b0), .IN4(na926_1), .IN5(~na1520_2), .IN6(~na929_1), .IN7(~na928_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y37 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3314_4 ( .OUT(na3314_2), .IN1(1'b1), .IN2(na1284_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3314_6 ( .RAM_O2(na3314_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3314_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y37 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3315_1 ( .OUT(na3315_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1282_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3315_6 ( .RAM_O1(na3315_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3315_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x20y68 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3316_1 ( .OUT(na3316_1), .IN1(1'b1), .IN2(na423_1), .IN3(1'b0), .IN4(1'b0), .IN5(na4579_2), .IN6(na640_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x44y87 80'h00_0018_00_0000_0EEE_7730 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3317_1 ( .OUT(na3317_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(~na409_1), .IN5(~na410_1), .IN6(~na1325_1), .IN7(~na1326_1), + .IN8(~na429_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y36 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3318_4 ( .OUT(na3318_2), .IN1(1'b1), .IN2(na1280_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3318_6 ( .RAM_O2(na3318_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3318_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y36 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3319_1 ( .OUT(na3319_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3319_6 ( .RAM_O1(na3319_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3319_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y35 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3320_4 ( .OUT(na3320_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1279_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3320_6 ( .RAM_O2(na3320_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3320_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y35 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3321_1 ( .OUT(na3321_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1278_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3321_6 ( .RAM_O1(na3321_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3321_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_XOR///XOR/ x63y89 80'h00_0078_00_0000_0C66_0909 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3322_1 ( .OUT(na3322_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1199_2), .IN6(~na1307_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3322_4 ( .OUT(na3322_2), .IN1(na1199_1), .IN2(~na1307_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y34 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3323_4 ( .OUT(na3323_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3323_6 ( .RAM_O2(na3323_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3323_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y85 80'h00_0018_00_0000_0C88_A1FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3324_1 ( .OUT(na3324_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2962_2), .IN6(~na4566_2), .IN7(na2958_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y34 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3325_1 ( .OUT(na3325_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3325_6 ( .RAM_O1(na3325_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3325_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y33 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3326_4 ( .OUT(na3326_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3326_6 ( .RAM_O2(na3326_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3326_2), .COMP_OUT(1'b0) ); +// C_AND//// x49y88 80'h00_0018_00_0000_0C88_3AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3327_1 ( .OUT(na3327_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na457_1), .IN6(1'b1), .IN7(1'b1), .IN8(~na4207_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x66y88 80'h00_0060_00_0000_0C06_FFA5 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3328_4 ( .OUT(na3328_2), .IN1(~na2957_2), .IN2(1'b0), .IN3(na459_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x62y84 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a3329_4 ( .OUT(na3329_2), .IN1(~na456_2), .IN2(~na2965_1), .IN3(~na462_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y33 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3330_1 ( .OUT(na3330_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3330_6 ( .RAM_O1(na3330_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3330_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x62y82 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3331_1 ( .OUT(na3331_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2957_2), .IN6(1'b1), .IN7(~na2958_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y48 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3332_4 ( .OUT(na3332_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3332_6 ( .RAM_O2(na3332_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3332_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y48 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3333_1 ( .OUT(na3333_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3333_6 ( .RAM_O1(na3333_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3333_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_OR//// x25y71 80'h00_0018_00_0000_0CEE_5300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3334_1 ( .OUT(na3334_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na137_2), .IN7(~na3161_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y70 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3335_1 ( .OUT(na3335_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na508_2), .IN7(na139_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x65y74 80'h00_0018_00_0000_0C88_75FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3336_1 ( .OUT(na3336_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na513_1), .IN6(1'b0), .IN7(~na38_2), .IN8(~na4492_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y47 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3337_4 ( .OUT(na3337_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3337_6 ( .RAM_O2(na3337_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3337_2), .COMP_OUT(1'b0) ); +// C_///AND/ x71y69 80'h00_0060_00_0000_0C08_FF33 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3338_4 ( .OUT(na3338_2), .IN1(1'b1), .IN2(~na1986_2), .IN3(1'b1), .IN4(~na1985_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y47 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3339_1 ( .OUT(na3339_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na822_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3339_6 ( .RAM_O1(na3339_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3339_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y46 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3340_4 ( .OUT(na3340_2), .IN1(na1146_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3340_6 ( .RAM_O2(na3340_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3340_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x63y70 80'h00_0018_00_0000_0C88_BCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3341_1 ( .OUT(na3341_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na1993_2), .IN7(na4487_2), .IN8(~na1990_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x65y69 80'h00_0060_00_0000_0C08_FFC3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3342_4 ( .OUT(na3342_2), .IN1(1'b1), .IN2(~na1989_2), .IN3(1'b1), .IN4(na1990_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x62y67 80'h00_0018_00_0000_0EEE_57C5 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3343_1 ( .OUT(na3343_1), .IN1(~na109_1), .IN2(1'b0), .IN3(1'b0), .IN4(na104_1), .IN5(~na105_1), .IN6(~na1432_1), .IN7(~na107_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y46 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3344_1 ( .OUT(na3344_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1144_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3344_6 ( .RAM_O1(na3344_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3344_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y45 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3345_4 ( .OUT(na3345_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1142_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3345_6 ( .RAM_O2(na3345_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3345_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x50y57 80'h00_0018_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3346_1 ( .OUT(na3346_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na55_1), .IN5(1'b0), .IN6(na34_1), .IN7(1'b0), .IN8(na4499_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y45 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3347_1 ( .OUT(na3347_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1140_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3347_6 ( .RAM_O1(na3347_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3347_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_XOR//// x68y75 80'h00_0018_00_0000_0C66_CA00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3348_1 ( .OUT(na3348_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na522_2), .IN6(1'b0), .IN7(1'b0), .IN8(na1446_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x37y44 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3349_4 ( .OUT(na3349_2), .IN1(1'b1), .IN2(na1138_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3349_6 ( .RAM_O2(na3349_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3349_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y44 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3350_1 ( .OUT(na3350_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3350_6 ( .RAM_O1(na3350_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3350_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y43 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3351_4 ( .OUT(na3351_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1137_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3351_6 ( .RAM_O2(na3351_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3351_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y43 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3352_1 ( .OUT(na3352_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1136_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3352_6 ( .RAM_O1(na3352_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3352_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y42 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3353_4 ( .OUT(na3353_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3353_6 ( .RAM_O2(na3353_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3353_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y42 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3354_1 ( .OUT(na3354_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3354_6 ( .RAM_O1(na3354_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3354_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y41 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3355_4 ( .OUT(na3355_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3355_6 ( .RAM_O2(na3355_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3355_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y41 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3356_1 ( .OUT(na3356_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3356_6 ( .RAM_O1(na3356_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3356_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y48 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3357_4 ( .OUT(na3357_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3357_6 ( .RAM_O2(na3357_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3357_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y48 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3358_1 ( .OUT(na3358_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3358_6 ( .RAM_O1(na3358_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3358_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y47 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3359_4 ( .OUT(na3359_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3359_6 ( .RAM_O2(na3359_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3359_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y47 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3360_1 ( .OUT(na3360_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3360_6 ( .RAM_O1(na3360_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3360_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y48 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3361_4 ( .OUT(na3361_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3361_6 ( .RAM_O2(na3361_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3361_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y48 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3362_1 ( .OUT(na3362_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3362_6 ( .RAM_O1(na3362_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3362_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y47 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3363_4 ( .OUT(na3363_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3363_6 ( .RAM_O2(na3363_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3363_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y47 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3364_1 ( .OUT(na3364_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3364_6 ( .RAM_O1(na3364_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3364_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y46 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3365_4 ( .OUT(na3365_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3365_6 ( .RAM_O2(na3365_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3365_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y46 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3366_1 ( .OUT(na3366_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3366_6 ( .RAM_O1(na3366_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3366_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y44 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3367_4 ( .OUT(na3367_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1135_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3367_6 ( .RAM_O2(na3367_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3367_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y44 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3368_1 ( .OUT(na3368_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1111_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3368_6 ( .RAM_O1(na3368_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3368_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y43 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3369_4 ( .OUT(na3369_2), .IN1(1'b1), .IN2(na1110_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3369_6 ( .RAM_O2(na3369_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3369_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y43 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3370_1 ( .OUT(na3370_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1109_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3370_6 ( .RAM_O1(na3370_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3370_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y42 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3371_4 ( .OUT(na3371_2), .IN1(na1108_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3371_6 ( .RAM_O2(na3371_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3371_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y42 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3372_1 ( .OUT(na3372_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na1107_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3372_6 ( .RAM_O1(na3372_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3372_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y41 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3373_4 ( .OUT(na3373_2), .IN1(na1106_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3373_6 ( .RAM_O2(na3373_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3373_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y41 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3374_1 ( .OUT(na3374_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1105_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3374_6 ( .RAM_O1(na3374_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3374_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y40 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3375_4 ( .OUT(na3375_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3375_6 ( .RAM_O2(na3375_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3375_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y40 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3376_1 ( .OUT(na3376_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3376_6 ( .RAM_O1(na3376_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3376_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y39 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3377_4 ( .OUT(na3377_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3377_6 ( .RAM_O2(na3377_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3377_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y39 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3378_1 ( .OUT(na3378_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3378_6 ( .RAM_O1(na3378_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3378_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y40 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3379_4 ( .OUT(na3379_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3379_6 ( .RAM_O2(na3379_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3379_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y40 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3380_1 ( .OUT(na3380_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3380_6 ( .RAM_O1(na3380_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3380_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y39 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3381_4 ( .OUT(na3381_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3381_6 ( .RAM_O2(na3381_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3381_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y39 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3382_1 ( .OUT(na3382_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3382_6 ( .RAM_O1(na3382_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3382_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y38 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3383_4 ( .OUT(na3383_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3383_6 ( .RAM_O2(na3383_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3383_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y38 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3384_1 ( .OUT(na3384_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3384_6 ( .RAM_O1(na3384_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3384_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y36 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3385_4 ( .OUT(na3385_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1277_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3385_6 ( .RAM_O2(na3385_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3385_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y36 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3386_1 ( .OUT(na3386_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1253_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3386_6 ( .RAM_O1(na3386_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3386_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y35 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3387_4 ( .OUT(na3387_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1252_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3387_6 ( .RAM_O2(na3387_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3387_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y35 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3388_1 ( .OUT(na3388_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1251_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3388_6 ( .RAM_O1(na3388_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3388_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y34 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3389_4 ( .OUT(na3389_2), .IN1(na1250_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3389_6 ( .RAM_O2(na3389_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3389_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y34 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3390_1 ( .OUT(na3390_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1249_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3390_6 ( .RAM_O1(na3390_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3390_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y33 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3391_4 ( .OUT(na3391_2), .IN1(1'b1), .IN2(na1248_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3391_6 ( .RAM_O2(na3391_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3391_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y33 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3392_1 ( .OUT(na3392_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1247_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3392_6 ( .RAM_O1(na3392_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3392_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y48 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3393_4 ( .OUT(na3393_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3393_6 ( .RAM_O2(na3393_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3393_2), .COMP_OUT(1'b0) ); +// C_AND//// x29y48 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3394_1 ( .OUT(na3394_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3394_6 ( .RAM_O1(na3394_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3394_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y47 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3395_4 ( .OUT(na3395_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3395_6 ( .RAM_O2(na3395_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3395_2), .COMP_OUT(1'b0) ); +// C_AND//// x29y47 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3396_1 ( .OUT(na3396_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3396_6 ( .RAM_O1(na3396_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3396_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y48 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3397_4 ( .OUT(na3397_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3397_6 ( .RAM_O2(na3397_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3397_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y48 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3398_1 ( .OUT(na3398_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3398_6 ( .RAM_O1(na3398_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3398_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y47 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3399_4 ( .OUT(na3399_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3399_6 ( .RAM_O2(na3399_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3399_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y47 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3400_1 ( .OUT(na3400_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3400_6 ( .RAM_O1(na3400_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3400_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y46 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3401_4 ( .OUT(na3401_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3401_6 ( .RAM_O2(na3401_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3401_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y46 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3402_1 ( .OUT(na3402_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3402_6 ( .RAM_O1(na3402_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3402_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y40 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3403_4 ( .OUT(na3403_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3403_6 ( .RAM_O2(na3403_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3403_2), .COMP_OUT(1'b0) ); +// C_AND//// x29y40 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3404_1 ( .OUT(na3404_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3404_6 ( .RAM_O1(na3404_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3404_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y39 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3405_4 ( .OUT(na3405_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3405_6 ( .RAM_O2(na3405_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3405_2), .COMP_OUT(1'b0) ); +// C_AND//// x29y39 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3406_1 ( .OUT(na3406_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3406_6 ( .RAM_O1(na3406_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3406_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y40 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3407_4 ( .OUT(na3407_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3407_6 ( .RAM_O2(na3407_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3407_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y40 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3408_1 ( .OUT(na3408_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3408_6 ( .RAM_O1(na3408_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3408_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y39 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3409_4 ( .OUT(na3409_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3409_6 ( .RAM_O2(na3409_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3409_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y39 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3410_1 ( .OUT(na3410_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3410_6 ( .RAM_O1(na3410_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3410_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y38 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3411_4 ( .OUT(na3411_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3411_6 ( .RAM_O2(na3411_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3411_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y38 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3412_1 ( .OUT(na3412_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3412_6 ( .RAM_O1(na3412_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3412_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_////RAM_I2 x34y44 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3413_5 ( .OUT(na3413_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_93), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y44 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3414_2 ( .OUT(na3414_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_94), .CP_O(1'b0) ); +// C_AND//// x70y76 80'h00_0018_00_0000_0C88_3AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3415_1 ( .OUT(na3415_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na360_1), .IN6(1'b1), .IN7(1'b1), .IN8(~na1985_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_////RAM_I2 x34y43 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3416_5 ( .OUT(na3416_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_95), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y43 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3417_2 ( .OUT(na3417_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_96), .CP_O(1'b0) ); +// C_AND//// x49y54 80'h00_0018_00_0000_0C88_1FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3418_1 ( .OUT(na3418_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na529_2), .IN8(~na526_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x48y57 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3419_1 ( .OUT(na3419_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na55_1), .IN5(~na48_1), .IN6(1'b0), .IN7(~na2013_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_////RAM_I2 x34y42 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3420_5 ( .OUT(na3420_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_97), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y42 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3421_2 ( .OUT(na3421_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_98), .CP_O(1'b0) ); +// C_MX2b//// x50y59 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3422_1 ( .OUT(na3422_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na55_1), .IN5(1'b0), .IN6(~na49_1), .IN7(1'b0), .IN8(~na4497_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_////RAM_I2 x34y41 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3423_5 ( .OUT(na3423_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_99), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y41 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3424_2 ( .OUT(na3424_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_100), .CP_O(1'b0) ); +// C_MX2b//// x56y59 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3425_1 ( .OUT(na3425_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na55_1), .IN5(~na1339_1), .IN6(1'b0), .IN7(~na4498_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_////RAM_I2 x34y36 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3426_5 ( .OUT(na3426_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_113), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y36 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3427_2 ( .OUT(na3427_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_114), .CP_O(1'b0) ); +// C_MX2b//// x46y59 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3428_1 ( .OUT(na3428_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na55_1), .IN5(1'b0), .IN6(~na44_1), .IN7(1'b0), .IN8(~na2015_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_////RAM_I2 x34y35 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3429_5 ( .OUT(na3429_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_115), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y35 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3430_2 ( .OUT(na3430_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_116), .CP_O(1'b0) ); +// C_MX2b//// x42y53 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3431_1 ( .OUT(na3431_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na55_1), .IN5(~na45_1), .IN6(1'b0), .IN7(~na2017_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x65y55 80'h00_0018_00_0000_0C88_5CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3432_1 ( .OUT(na3432_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2125_1), .IN7(~na529_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y51 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3433_4 ( .OUT(na3433_2), .IN1(1'b1), .IN2(na2125_2), .IN3(~na529_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y50 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3434_4 ( .OUT(na3434_2), .IN1(1'b1), .IN2(na2127_1), .IN3(~na529_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y53 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3435_4 ( .OUT(na3435_2), .IN1(1'b1), .IN2(na2127_2), .IN3(~na529_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x62y58 80'h00_0018_00_0000_0C88_2FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3436_1 ( .OUT(na3436_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2129_1), .IN8(~na4224_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x61y60 80'h00_0018_00_0000_0C88_2FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3437_1 ( .OUT(na3437_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2129_2), .IN8(~na4224_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x62y61 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3438_1 ( .OUT(na3438_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na529_2), .IN8(na597_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_////RAM_I2 x34y34 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3439_5 ( .OUT(na3439_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_117), .CP_O(1'b0) ); +// C_ORAND//// x71y72 80'h00_0018_00_0000_0888_7C5C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3440_1 ( .OUT(na3440_1), .IN1(1'b0), .IN2(na3453_1), .IN3(~na598_1), .IN4(1'b0), .IN5(1'b0), .IN6(na3453_2), .IN7(~na598_2), + .IN8(~na3457_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x63y65 80'h00_0060_00_0000_0C06_FF56 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3441_4 ( .OUT(na3441_2), .IN1(na535_1), .IN2(na599_2), .IN3(~na1447_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_/RAM_I1/// x34y34 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3442_2 ( .OUT(na3442_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_118), .CP_O(1'b0) ); +// C_////RAM_I2 x34y33 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3443_5 ( .OUT(na3443_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_119), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y33 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3444_2 ( .OUT(na3444_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3223_120), .CP_O(1'b0) ); +// C_///XOR/ x65y78 80'h00_0060_00_0000_0C06_FF65 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3445_4 ( .OUT(na3445_2), .IN1(~na607_1), .IN2(1'b0), .IN3(na1439_1), .IN4(na605_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x27y9 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3446_4 ( .OUT(na3446_2), .IN1(na930_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3446_6 ( .RAM_O2(na3446_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3446_2), .COMP_OUT(1'b0) ); +// C_///AND/ x65y73 80'h00_0060_00_0000_0C08_FF53 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3447_4 ( .OUT(na3447_2), .IN1(1'b1), .IN2(~na1993_2), .IN3(~na1991_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x63y77 80'h00_0018_00_0000_0888_AFE3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3448_1 ( .OUT(na3448_1), .IN1(1'b0), .IN2(~na3336_1), .IN3(na38_1), .IN4(na4603_2), .IN5(1'b1), .IN6(1'b1), .IN7(na3451_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y16 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3449_4 ( .OUT(na3449_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3449_6 ( .RAM_O2(na3449_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3449_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y16 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3450_1 ( .OUT(na3450_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3450_6 ( .RAM_O1(na3450_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3450_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND///AND/ x64y75 80'h00_0078_00_0000_0C88_CAC2 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3451_1 ( .OUT(na3451_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na360_1), .IN6(1'b1), .IN7(1'b1), .IN8(na4180_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3451_4 ( .OUT(na3451_2), .IN1(na4489_2), .IN2(~na1993_2), .IN3(1'b1), .IN4(na1990_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x65y66 80'h00_0060_00_0000_0C08_FFC3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3452_4 ( .OUT(na3452_2), .IN1(1'b1), .IN2(~na1986_2), .IN3(1'b1), .IN4(na1581_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x69y72 80'h00_0078_00_0000_0CEE_A7D7 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3453_1 ( .OUT(na3453_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na619_1), .IN6(~na1986_2), .IN7(na598_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a3453_4 ( .OUT(na3453_2), .IN1(~na522_2), .IN2(~na1986_1), .IN3(~na511_2), .IN4(na4486_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y15 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3454_4 ( .OUT(na3454_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3454_6 ( .RAM_O2(na3454_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3454_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y15 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3455_1 ( .OUT(na3455_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na198_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3455_6 ( .RAM_O1(na3455_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3455_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y14 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3456_4 ( .OUT(na3456_2), .IN1(1'b1), .IN2(1'b1), .IN3(na942_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3456_6 ( .RAM_O2(na3456_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3456_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x68y72 80'h00_0018_00_0040_0AA0_00AF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3457_1 ( .OUT(na3457_1), .IN1(1'b1), .IN2(1'b1), .IN3(na618_1), .IN4(1'b1), .IN5(1'b0), .IN6(na1441_2), .IN7(1'b0), .IN8(na2011_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y57 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3458_4 ( .OUT(na3458_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na529_2), .IN4(na597_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x45y55 80'h00_0018_00_0000_0EEE_50D7 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3459_1 ( .OUT(na3459_1), .IN1(~na1387_1), .IN2(~na1383_2), .IN3(~na1454_2), .IN4(na282_1), .IN5(1'b0), .IN6(1'b0), .IN7(~na283_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y14 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3460_1 ( .OUT(na3460_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na940_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3460_6 ( .RAM_O1(na3460_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3460_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_OR//// x53y56 80'h00_0018_00_0000_0CEE_E000 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3461_1 ( .OUT(na3461_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na276_1), .IN8(na3462_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x52y58 80'h00_0018_00_0000_0888_25C1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3462_1 ( .OUT(na3462_1), .IN1(~na2229_1), .IN2(~na2228_2), .IN3(1'b1), .IN4(na338_2), .IN5(~na2229_2), .IN6(1'b1), .IN7(na332_1), + .IN8(~na4432_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x44y51 80'h00_0018_00_0040_0A50_0050 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3463_1 ( .OUT(na3463_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na276_1), .IN4(1'b1), .IN5(na36_1), .IN6(1'b0), .IN7(na4518_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x23y70 80'h00_0018_00_0000_0CEE_3300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3464_1 ( .OUT(na3464_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na137_2), .IN7(1'b0), .IN8(~na3173_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y71 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3465_1 ( .OUT(na3465_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na139_1), .IN8(na645_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x29y69 80'h00_0060_00_0000_0C0E_FF33 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a3466_4 ( .OUT(na3466_2), .IN1(1'b0), .IN2(~na137_2), .IN3(1'b0), .IN4(~na3174_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x39y70 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3467_4 ( .OUT(na3467_2), .IN1(1'b1), .IN2(na690_1), .IN3(na139_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y13 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3468_4 ( .OUT(na3468_2), .IN1(1'b1), .IN2(na938_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3468_6 ( .RAM_O2(na3468_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3468_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y13 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3469_1 ( .OUT(na3469_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na936_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3469_6 ( .RAM_O1(na3469_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3469_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x62y59 80'h00_0018_00_0000_0C88_BAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3470_1 ( .OUT(na3470_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2229_1), .IN6(1'b0), .IN7(na2226_2), .IN8(~na4511_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y56 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3471_4 ( .OUT(na3471_2), .IN1(na2229_2), .IN2(1'b1), .IN3(~na2226_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x54y60 80'h00_0018_00_0000_0C66_AA00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3472_1 ( .OUT(na3472_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na707_1), .IN6(1'b0), .IN7(na1468_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y12 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3473_4 ( .OUT(na3473_2), .IN1(1'b1), .IN2(1'b1), .IN3(na934_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3473_6 ( .RAM_O2(na3473_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3473_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y12 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3474_1 ( .OUT(na3474_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3474_6 ( .RAM_O1(na3474_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3474_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y11 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3475_4 ( .OUT(na3475_2), .IN1(1'b1), .IN2(na933_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3475_6 ( .RAM_O2(na3475_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3475_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y11 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3476_1 ( .OUT(na3476_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na932_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3476_6 ( .RAM_O1(na3476_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3476_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y10 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3477_4 ( .OUT(na3477_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3477_6 ( .RAM_O2(na3477_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3477_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y10 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3478_1 ( .OUT(na3478_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3478_6 ( .RAM_O1(na3478_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3478_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y9 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3479_4 ( .OUT(na3479_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3479_6 ( .RAM_O2(na3479_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3479_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y9 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3480_1 ( .OUT(na3480_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3480_6 ( .RAM_O1(na3480_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3480_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y16 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3481_4 ( .OUT(na3481_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3481_6 ( .RAM_O2(na3481_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3481_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y16 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3482_1 ( .OUT(na3482_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3482_6 ( .RAM_O1(na3482_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3482_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y15 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3483_4 ( .OUT(na3483_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3483_6 ( .RAM_O2(na3483_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3483_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y15 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3484_1 ( .OUT(na3484_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na198_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3484_6 ( .RAM_O1(na3484_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3484_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y14 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3485_4 ( .OUT(na3485_2), .IN1(na976_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3485_6 ( .RAM_O2(na3485_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3485_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y14 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3486_1 ( .OUT(na3486_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na974_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3486_6 ( .RAM_O1(na3486_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3486_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y13 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3487_4 ( .OUT(na3487_2), .IN1(1'b1), .IN2(1'b1), .IN3(na972_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3487_6 ( .RAM_O2(na3487_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3487_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y13 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3488_1 ( .OUT(na3488_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na970_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3488_6 ( .RAM_O1(na3488_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3488_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y12 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3489_4 ( .OUT(na3489_2), .IN1(1'b1), .IN2(na968_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3489_6 ( .RAM_O2(na3489_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3489_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y12 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3490_1 ( .OUT(na3490_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3490_6 ( .RAM_O1(na3490_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3490_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y11 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3491_4 ( .OUT(na3491_2), .IN1(1'b1), .IN2(na967_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3491_6 ( .RAM_O2(na3491_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3491_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y11 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3492_1 ( .OUT(na3492_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na966_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3492_6 ( .RAM_O1(na3492_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3492_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y10 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3493_4 ( .OUT(na3493_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3493_6 ( .RAM_O2(na3493_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3493_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y10 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3494_1 ( .OUT(na3494_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3494_6 ( .RAM_O1(na3494_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3494_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y9 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3495_4 ( .OUT(na3495_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3495_6 ( .RAM_O2(na3495_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3495_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y9 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3496_1 ( .OUT(na3496_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3496_6 ( .RAM_O1(na3496_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3496_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y16 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3497_4 ( .OUT(na3497_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3497_6 ( .RAM_O2(na3497_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3497_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y16 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3498_1 ( .OUT(na3498_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3498_6 ( .RAM_O1(na3498_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3498_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y15 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3499_4 ( .OUT(na3499_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3499_6 ( .RAM_O2(na3499_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3499_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y15 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3500_1 ( .OUT(na3500_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3500_6 ( .RAM_O1(na3500_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3500_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y16 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3501_4 ( .OUT(na3501_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3501_6 ( .RAM_O2(na3501_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3501_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y16 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3502_1 ( .OUT(na3502_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3502_6 ( .RAM_O1(na3502_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3502_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y15 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3503_4 ( .OUT(na3503_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3503_6 ( .RAM_O2(na3503_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3503_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y15 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3504_1 ( .OUT(na3504_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3504_6 ( .RAM_O1(na3504_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3504_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y14 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3505_4 ( .OUT(na3505_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3505_6 ( .RAM_O2(na3505_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3505_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y14 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3506_1 ( .OUT(na3506_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3506_6 ( .RAM_O1(na3506_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3506_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y12 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3507_4 ( .OUT(na3507_2), .IN1(na965_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3507_6 ( .RAM_O2(na3507_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3507_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y12 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3508_1 ( .OUT(na3508_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na950_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3508_6 ( .RAM_O1(na3508_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3508_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y11 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3509_4 ( .OUT(na3509_2), .IN1(na949_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3509_6 ( .RAM_O2(na3509_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3509_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y11 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3510_1 ( .OUT(na3510_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na948_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3510_6 ( .RAM_O1(na3510_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3510_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y10 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3511_4 ( .OUT(na3511_2), .IN1(1'b1), .IN2(1'b1), .IN3(na947_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3511_6 ( .RAM_O2(na3511_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3511_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y10 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3512_1 ( .OUT(na3512_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na946_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3512_6 ( .RAM_O1(na3512_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3512_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y9 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3513_4 ( .OUT(na3513_2), .IN1(na945_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3513_6 ( .RAM_O2(na3513_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3513_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y9 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3514_1 ( .OUT(na3514_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na944_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3514_6 ( .RAM_O1(na3514_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3514_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y16 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3515_4 ( .OUT(na3515_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3515_6 ( .RAM_O2(na3515_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3515_2), .COMP_OUT(1'b0) ); +// C_AND//// x29y16 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3516_1 ( .OUT(na3516_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3516_6 ( .RAM_O1(na3516_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3516_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y15 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3517_4 ( .OUT(na3517_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3517_6 ( .RAM_O2(na3517_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3517_2), .COMP_OUT(1'b0) ); +// C_AND//// x29y15 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3518_1 ( .OUT(na3518_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3518_6 ( .RAM_O1(na3518_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3518_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y16 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3519_4 ( .OUT(na3519_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3519_6 ( .RAM_O2(na3519_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3519_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y16 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3520_1 ( .OUT(na3520_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3520_6 ( .RAM_O1(na3520_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3520_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y15 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3521_4 ( .OUT(na3521_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3521_6 ( .RAM_O2(na3521_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3521_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y15 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3522_1 ( .OUT(na3522_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3522_6 ( .RAM_O1(na3522_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3522_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y14 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3523_4 ( .OUT(na3523_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3523_6 ( .RAM_O2(na3523_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3523_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y14 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3524_1 ( .OUT(na3524_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3524_6 ( .RAM_O1(na3524_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3524_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_////RAM_I2 x34y12 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3525_5 ( .OUT(na3525_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_93), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y12 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3526_2 ( .OUT(na3526_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_94), .CP_O(1'b0) ); +// C_////RAM_I2 x34y11 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3527_5 ( .OUT(na3527_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_95), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y11 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3528_2 ( .OUT(na3528_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_96), .CP_O(1'b0) ); +// C_////RAM_I2 x34y10 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3529_5 ( .OUT(na3529_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_97), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y10 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3530_2 ( .OUT(na3530_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_98), .CP_O(1'b0) ); +// C_////RAM_I2 x34y9 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3531_5 ( .OUT(na3531_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_99), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y9 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3532_2 ( .OUT(na3532_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3225_100), .CP_O(1'b0) ); +// C_///AND/ x27y25 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3533_4 ( .OUT(na3533_2), .IN1(1'b1), .IN2(1'b1), .IN3(na576_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3533_6 ( .RAM_O2(na3533_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3533_2), .COMP_OUT(1'b0) ); +// C_///AND/ x27y17 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3534_4 ( .OUT(na3534_2), .IN1(na763_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3534_6 ( .RAM_O2(na3534_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3534_2), .COMP_OUT(1'b0) ); +// C_///AND/ x28y24 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3535_4 ( .OUT(na3535_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3535_6 ( .RAM_O2(na3535_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3535_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y24 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3536_1 ( .OUT(na3536_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3536_6 ( .RAM_O1(na3536_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3536_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y23 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3537_4 ( .OUT(na3537_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3537_6 ( .RAM_O2(na3537_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3537_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y23 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3538_1 ( .OUT(na3538_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na639_2), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3538_6 ( .RAM_O1(na3538_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3538_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x65y58 80'h00_0018_00_0000_0C88_A5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3539_1 ( .OUT(na3539_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2222_1), .IN6(1'b1), .IN7(na297_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y22 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3540_4 ( .OUT(na3540_2), .IN1(1'b1), .IN2(1'b1), .IN3(na775_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3540_6 ( .RAM_O2(na3540_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3540_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y22 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3541_1 ( .OUT(na3541_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na773_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3541_6 ( .RAM_O1(na3541_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3541_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x49y47 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3542_1 ( .OUT(na3542_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na638_2), .IN6(1'b1), .IN7(~na636_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x48y54 80'h00_0018_00_0040_0A55_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3543_1 ( .OUT(na3543_1), .IN1(1'b0), .IN2(1'b0), .IN3(na276_1), .IN4(1'b1), .IN5(~na2250_1), .IN6(1'b0), .IN7(~na323_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y21 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3544_4 ( .OUT(na3544_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na771_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3544_6 ( .RAM_O2(na3544_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3544_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y21 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3545_1 ( .OUT(na3545_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na769_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3545_6 ( .RAM_O1(na3545_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3545_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x48y56 80'h00_0018_00_0040_0AAA_00AF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3546_1 ( .OUT(na3546_1), .IN1(1'b1), .IN2(1'b1), .IN3(na276_1), .IN4(1'b1), .IN5(1'b0), .IN6(~na4516_2), .IN7(1'b0), .IN8(~na162_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y20 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3547_4 ( .OUT(na3547_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na767_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3547_6 ( .RAM_O2(na3547_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3547_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y20 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3548_1 ( .OUT(na3548_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3548_6 ( .RAM_O1(na3548_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3548_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x48y52 80'h00_0018_00_0040_0AAA_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3549_1 ( .OUT(na3549_1), .IN1(1'b1), .IN2(1'b1), .IN3(~na276_1), .IN4(1'b1), .IN5(1'b0), .IN6(~na324_1), .IN7(1'b0), .IN8(~na4517_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y19 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3550_4 ( .OUT(na3550_2), .IN1(1'b1), .IN2(1'b1), .IN3(na766_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3550_6 ( .RAM_O2(na3550_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3550_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y19 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3551_1 ( .OUT(na3551_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na765_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3551_6 ( .RAM_O1(na3551_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3551_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x44y52 80'h00_0018_00_0040_0A55_0050 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3552_1 ( .OUT(na3552_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na276_1), .IN4(1'b1), .IN5(~na325_1), .IN6(1'b0), .IN7(~na2252_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y18 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3553_4 ( .OUT(na3553_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3553_6 ( .RAM_O2(na3553_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3553_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y18 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3554_1 ( .OUT(na3554_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3554_6 ( .RAM_O1(na3554_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3554_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x42y52 80'h00_0018_00_0040_0AAA_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3555_1 ( .OUT(na3555_1), .IN1(1'b1), .IN2(1'b1), .IN3(~na276_1), .IN4(1'b1), .IN5(1'b0), .IN6(~na315_1), .IN7(1'b0), .IN8(~na2254_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x59y41 80'h00_0060_00_0000_0C08_FFF4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3556_4 ( .OUT(na3556_2), .IN1(~na638_2), .IN2(na2359_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y42 80'h00_0060_00_0000_0C08_FFF4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3557_4 ( .OUT(na3557_2), .IN1(~na638_2), .IN2(na2359_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x57y41 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3558_4 ( .OUT(na3558_2), .IN1(~na638_2), .IN2(1'b1), .IN3(na2361_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x57y44 80'h00_0018_00_0000_0C88_A5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3559_1 ( .OUT(na3559_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na638_2), .IN6(1'b1), .IN7(na2361_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x58y41 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3560_1 ( .OUT(na3560_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na638_2), .IN6(1'b1), .IN7(1'b1), .IN8(na2363_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x61y44 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3561_1 ( .OUT(na3561_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na638_2), .IN6(1'b1), .IN7(1'b1), .IN8(na2363_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x51y43 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3562_4 ( .OUT(na3562_2), .IN1(~na638_2), .IN2(1'b1), .IN3(na784_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y17 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3563_4 ( .OUT(na3563_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3563_6 ( .RAM_O2(na3563_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3563_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x67y57 80'h00_0018_00_0000_0888_A7A5 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3564_1 ( .OUT(na3564_1), .IN1(~na785_1), .IN2(1'b0), .IN3(na3571_1), .IN4(1'b0), .IN5(~na785_2), .IN6(~na3575_1), .IN7(na3571_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x61y50 80'h00_0060_00_0000_0C06_FF9C +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3565_4 ( .OUT(na3565_2), .IN1(1'b0), .IN2(na786_1), .IN3(~na1469_1), .IN4(na720_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y17 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3566_1 ( .OUT(na3566_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3566_6 ( .RAM_O1(na3566_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3566_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y32 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3567_4 ( .OUT(na3567_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3567_6 ( .RAM_O2(na3567_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3567_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y32 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3568_1 ( .OUT(na3568_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3568_6 ( .RAM_O1(na3568_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3568_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y31 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3569_4 ( .OUT(na3569_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3569_6 ( .RAM_O2(na3569_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3569_2), .COMP_OUT(1'b0) ); +// C_///AND/ x61y47 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3570_4 ( .OUT(na3570_2), .IN1(1'b1), .IN2(na1587_2), .IN3(~na2223_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x68y55 80'h00_0078_00_0000_0CEE_7AD7 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3571_1 ( .OUT(na3571_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na785_2), .IN6(1'b0), .IN7(~na797_1), .IN8(~na4504_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a3571_4 ( .OUT(na3571_2), .IN1(~na707_1), .IN2(~na352_2), .IN3(~na2223_1), .IN4(na4504_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y31 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3572_1 ( .OUT(na3572_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na530_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3572_6 ( .RAM_O1(na3572_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3572_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y30 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3573_4 ( .OUT(na3573_2), .IN1(na588_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3573_6 ( .RAM_O2(na3573_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3573_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y30 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3574_1 ( .OUT(na3574_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na586_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3574_6 ( .RAM_O1(na3574_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3574_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x61y56 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3575_1 ( .OUT(na3575_1), .IN1(1'b1), .IN2(na796_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1463_1), .IN6(na2248_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x55y53 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3576_4 ( .OUT(na3576_2), .IN1(~na638_2), .IN2(1'b1), .IN3(na784_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y29 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3577_4 ( .OUT(na3577_2), .IN1(1'b1), .IN2(1'b1), .IN3(na584_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3577_6 ( .RAM_O2(na3577_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3577_2), .COMP_OUT(1'b0) ); +// C_OR//// x41y85 80'h00_0018_00_0000_0EEE_55C7 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3578_1 ( .OUT(na3578_1), .IN1(~na1498_1), .IN2(~na1325_1), .IN3(1'b0), .IN4(na409_1), .IN5(~na430_2), .IN6(1'b0), .IN7(~na1326_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y29 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3579_1 ( .OUT(na3579_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na582_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3579_6 ( .RAM_O1(na3579_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3579_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_OR//// x40y81 80'h00_0018_00_0000_0EEE_7EAC +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3580_1 ( .OUT(na3580_1), .IN1(1'b0), .IN2(na4553_2), .IN3(na2713_1), .IN4(1'b0), .IN5(na2712_2), .IN6(na232_1), .IN7(~na1340_1), + .IN8(~na3230_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x28y28 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3581_4 ( .OUT(na3581_2), .IN1(1'b1), .IN2(na580_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3581_6 ( .RAM_O2(na3581_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3581_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x30y72 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3582_1 ( .OUT(na3582_1), .IN1(1'b1), .IN2(na219_2), .IN3(1'b0), .IN4(1'b0), .IN5(na4561_2), .IN6(na1312_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y28 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3583_1 ( .OUT(na3583_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3583_6 ( .RAM_O1(na3583_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3583_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y27 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3584_4 ( .OUT(na3584_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na579_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3584_6 ( .RAM_O2(na3584_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3584_2), .COMP_OUT(1'b0) ); +// C_AND//// x27y57 80'h00_0018_00_0000_0C88_33FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3585_1 ( .OUT(na3585_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na2474_2), .IN7(1'b1), .IN8(~na2473_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y27 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3586_1 ( .OUT(na3586_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na578_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3586_6 ( .RAM_O1(na3586_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3586_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y26 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3587_4 ( .OUT(na3587_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3587_6 ( .RAM_O2(na3587_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3587_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x22y57 80'h00_0018_00_0000_0C88_ABFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3588_1 ( .OUT(na3588_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4524_2), .IN6(~na2478_2), .IN7(na2481_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x22y54 80'h00_0018_00_0000_0C88_F2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3589_1 ( .OUT(na3589_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na4530_2), .IN6(~na2477_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x15y53 80'h00_0018_00_0000_0C66_CA00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3590_1 ( .OUT(na3590_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1490_2), .IN6(1'b0), .IN7(1'b0), .IN8(na884_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x28y26 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3591_1 ( .OUT(na3591_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3591_6 ( .RAM_O1(na3591_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3591_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x28y25 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3592_4 ( .OUT(na3592_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3592_6 ( .RAM_O2(na3592_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3592_2), .COMP_OUT(1'b0) ); +// C_AND//// x28y25 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3593_1 ( .OUT(na3593_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3593_6 ( .RAM_O1(na3593_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3593_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y24 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3594_4 ( .OUT(na3594_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3594_6 ( .RAM_O2(na3594_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3594_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y24 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3595_1 ( .OUT(na3595_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3595_6 ( .RAM_O1(na3595_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3595_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y23 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3596_4 ( .OUT(na3596_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3596_6 ( .RAM_O2(na3596_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3596_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y23 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3597_1 ( .OUT(na3597_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na639_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3597_6 ( .RAM_O1(na3597_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3597_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y22 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3598_4 ( .OUT(na3598_2), .IN1(1'b1), .IN2(1'b1), .IN3(na809_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3598_6 ( .RAM_O2(na3598_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3598_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y22 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3599_1 ( .OUT(na3599_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na807_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3599_6 ( .RAM_O1(na3599_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3599_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y21 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3600_4 ( .OUT(na3600_2), .IN1(na805_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3600_6 ( .RAM_O2(na3600_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3600_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y21 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3601_1 ( .OUT(na3601_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na803_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3601_6 ( .RAM_O1(na3601_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3601_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y20 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3602_4 ( .OUT(na3602_2), .IN1(na801_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3602_6 ( .RAM_O2(na3602_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3602_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y20 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3603_1 ( .OUT(na3603_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3603_6 ( .RAM_O1(na3603_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3603_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y19 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3604_4 ( .OUT(na3604_2), .IN1(1'b1), .IN2(1'b1), .IN3(na800_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3604_6 ( .RAM_O2(na3604_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3604_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y19 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3605_1 ( .OUT(na3605_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na799_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3605_6 ( .RAM_O1(na3605_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3605_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y18 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3606_4 ( .OUT(na3606_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3606_6 ( .RAM_O2(na3606_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3606_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y18 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3607_1 ( .OUT(na3607_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3607_6 ( .RAM_O1(na3607_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3607_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y17 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3608_4 ( .OUT(na3608_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3608_6 ( .RAM_O2(na3608_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3608_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y17 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3609_1 ( .OUT(na3609_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3609_6 ( .RAM_O1(na3609_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3609_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y32 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3610_4 ( .OUT(na3610_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3610_6 ( .RAM_O2(na3610_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3610_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y32 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3611_1 ( .OUT(na3611_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3611_6 ( .RAM_O1(na3611_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3611_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y31 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3612_4 ( .OUT(na3612_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3612_6 ( .RAM_O2(na3612_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3612_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y31 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3613_1 ( .OUT(na3613_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na530_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3613_6 ( .RAM_O1(na3613_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3613_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y30 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3614_4 ( .OUT(na3614_2), .IN1(1'b1), .IN2(na631_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3614_6 ( .RAM_O2(na3614_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3614_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y30 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3615_1 ( .OUT(na3615_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na629_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3615_6 ( .RAM_O1(na3615_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3615_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y29 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3616_4 ( .OUT(na3616_2), .IN1(1'b1), .IN2(1'b1), .IN3(na627_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3616_6 ( .RAM_O2(na3616_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3616_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y29 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3617_1 ( .OUT(na3617_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na625_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3617_6 ( .RAM_O1(na3617_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3617_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y28 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3618_4 ( .OUT(na3618_2), .IN1(na623_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3618_6 ( .RAM_O2(na3618_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3618_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y28 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3619_1 ( .OUT(na3619_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3619_6 ( .RAM_O1(na3619_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3619_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y27 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3620_4 ( .OUT(na3620_2), .IN1(na622_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3620_6 ( .RAM_O2(na3620_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3620_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y27 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3621_1 ( .OUT(na3621_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na621_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3621_6 ( .RAM_O1(na3621_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3621_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y26 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3622_4 ( .OUT(na3622_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3622_6 ( .RAM_O2(na3622_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3622_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y26 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3623_1 ( .OUT(na3623_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3623_6 ( .RAM_O1(na3623_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3623_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y25 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3624_4 ( .OUT(na3624_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3624_6 ( .RAM_O2(na3624_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3624_2), .COMP_OUT(1'b0) ); +// C_AND//// x37y25 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3625_1 ( .OUT(na3625_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3625_6 ( .RAM_O1(na3625_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3625_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y32 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3626_4 ( .OUT(na3626_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3626_6 ( .RAM_O2(na3626_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3626_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y32 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3627_1 ( .OUT(na3627_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3627_6 ( .RAM_O1(na3627_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3627_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y31 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3628_4 ( .OUT(na3628_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3628_6 ( .RAM_O2(na3628_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3628_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y31 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3629_1 ( .OUT(na3629_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3629_6 ( .RAM_O1(na3629_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3629_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y32 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3630_4 ( .OUT(na3630_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3630_6 ( .RAM_O2(na3630_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3630_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y32 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3631_1 ( .OUT(na3631_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3631_6 ( .RAM_O1(na3631_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3631_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y31 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3632_4 ( .OUT(na3632_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3632_6 ( .RAM_O2(na3632_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3632_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y31 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3633_1 ( .OUT(na3633_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3633_6 ( .RAM_O1(na3633_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3633_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y30 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3634_4 ( .OUT(na3634_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3634_6 ( .RAM_O2(na3634_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3634_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y30 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3635_1 ( .OUT(na3635_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3635_6 ( .RAM_O1(na3635_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3635_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y28 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3636_4 ( .OUT(na3636_2), .IN1(1'b1), .IN2(na620_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3636_6 ( .RAM_O2(na3636_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3636_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y28 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3637_1 ( .OUT(na3637_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na596_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3637_6 ( .RAM_O1(na3637_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3637_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y27 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3638_4 ( .OUT(na3638_2), .IN1(1'b1), .IN2(1'b1), .IN3(na595_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3638_6 ( .RAM_O2(na3638_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3638_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y27 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3639_1 ( .OUT(na3639_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na594_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3639_6 ( .RAM_O1(na3639_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3639_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y26 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3640_4 ( .OUT(na3640_2), .IN1(na593_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3640_6 ( .RAM_O2(na3640_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3640_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y26 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3641_1 ( .OUT(na3641_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na592_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3641_6 ( .RAM_O1(na3641_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3641_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y25 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3642_4 ( .OUT(na3642_2), .IN1(1'b1), .IN2(1'b1), .IN3(na591_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3642_6 ( .RAM_O2(na3642_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3642_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y25 80'h04_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3643_1 ( .OUT(na3643_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na590_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3643_6 ( .RAM_O1(na3643_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3643_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y24 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3644_4 ( .OUT(na3644_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3644_6 ( .RAM_O2(na3644_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3644_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y24 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3645_1 ( .OUT(na3645_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3645_6 ( .RAM_O1(na3645_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3645_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x30y23 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3646_4 ( .OUT(na3646_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3646_6 ( .RAM_O2(na3646_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3646_2), .COMP_OUT(1'b0) ); +// C_AND//// x30y23 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3647_1 ( .OUT(na3647_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3647_6 ( .RAM_O1(na3647_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3647_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y24 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3648_4 ( .OUT(na3648_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3648_6 ( .RAM_O2(na3648_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3648_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y24 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3649_1 ( .OUT(na3649_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3649_6 ( .RAM_O1(na3649_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3649_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y23 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3650_4 ( .OUT(na3650_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3650_6 ( .RAM_O2(na3650_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3650_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y23 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3651_1 ( .OUT(na3651_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3651_6 ( .RAM_O1(na3651_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3651_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y22 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3652_4 ( .OUT(na3652_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3652_6 ( .RAM_O2(na3652_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3652_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y22 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3653_1 ( .OUT(na3653_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3653_6 ( .RAM_O1(na3653_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3653_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y20 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3654_4 ( .OUT(na3654_2), .IN1(na798_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3654_6 ( .RAM_O2(na3654_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3654_2), .COMP_OUT(1'b0) ); +// C_AND//// x32y20 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3655_1 ( .OUT(na3655_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na783_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3655_6 ( .RAM_O1(na3655_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3655_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y19 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3656_4 ( .OUT(na3656_2), .IN1(1'b1), .IN2(1'b1), .IN3(na782_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3656_6 ( .RAM_O2(na3656_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3656_2), .COMP_OUT(1'b0) ); +// C_///AND/ x30y62 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3657_4 ( .OUT(na3657_2), .IN1(na216_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na2473_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x32y19 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3658_1 ( .OUT(na3658_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na781_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3658_6 ( .RAM_O1(na3658_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3658_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y18 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3659_4 ( .OUT(na3659_2), .IN1(na780_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3659_6 ( .RAM_O2(na3659_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3659_2), .COMP_OUT(1'b0) ); +// C_///AND/ x14y47 80'h00_0060_00_0000_0C08_FF33 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3660_4 ( .OUT(na3660_2), .IN1(1'b1), .IN2(~na194_1), .IN3(1'b1), .IN4(~na197_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x19y43 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3661_1 ( .OUT(na3661_1), .IN1(1'b1), .IN2(na122_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na2501_1), .IN6(~na126_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x32y18 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3662_1 ( .OUT(na3662_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na779_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3662_6 ( .RAM_O1(na3662_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3662_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x32y17 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3663_4 ( .OUT(na3663_2), .IN1(1'b1), .IN2(1'b1), .IN3(na778_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3663_6 ( .RAM_O2(na3663_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3663_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x21y43 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3664_1 ( .OUT(na3664_1), .IN1(1'b1), .IN2(~na122_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1367_1), .IN6(~na4539_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x32y17 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3665_1 ( .OUT(na3665_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na777_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3665_6 ( .RAM_O1(na3665_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3665_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y32 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3666_4 ( .OUT(na3666_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3666_6 ( .RAM_O2(na3666_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3666_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x17y41 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3667_1 ( .OUT(na3667_1), .IN1(1'b1), .IN2(~na122_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1366_1), .IN6(~na2503_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x29y32 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3668_1 ( .OUT(na3668_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3668_6 ( .RAM_O1(na3668_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3668_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y31 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3669_4 ( .OUT(na3669_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3669_6 ( .RAM_O2(na3669_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3669_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x17y43 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3670_1 ( .OUT(na3670_1), .IN1(1'b1), .IN2(na122_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na4540_2), .IN6(~na130_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x29y31 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3671_1 ( .OUT(na3671_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3671_6 ( .RAM_O1(na3671_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3671_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y32 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3672_4 ( .OUT(na3672_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3672_6 ( .RAM_O2(na3672_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3672_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x15y41 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3673_1 ( .OUT(na3673_1), .IN1(1'b1), .IN2(~na122_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na131_1), .IN6(~na4541_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x35y48 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3674_4 ( .OUT(na3674_2), .IN1(na2600_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na197_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x35y47 80'h00_0018_00_0000_0C88_3AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3675_1 ( .OUT(na3675_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2600_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na197_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x33y47 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3676_1 ( .OUT(na3676_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na4123_2), .IN7(1'b1), .IN8(na2602_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x36y47 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3677_1 ( .OUT(na3677_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na4123_2), .IN7(1'b1), .IN8(na2602_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x25y49 80'h00_0060_00_0000_0C08_FF3C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3678_4 ( .OUT(na3678_2), .IN1(1'b1), .IN2(na2604_1), .IN3(1'b1), .IN4(~na197_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x27y45 80'h00_0018_00_0000_0C88_3CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3679_1 ( .OUT(na3679_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2604_2), .IN7(1'b1), .IN8(~na197_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x25y49 80'h00_0018_00_0000_0C88_2FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3680_1 ( .OUT(na3680_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na951_2), .IN8(~na197_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x31y32 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3681_1 ( .OUT(na3681_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3681_6 ( .RAM_O1(na3681_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3681_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x24y62 80'h00_0018_00_0000_0888_7A5A +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3682_1 ( .OUT(na3682_1), .IN1(na3689_1), .IN2(1'b0), .IN3(~na952_1), .IN4(1'b0), .IN5(na3689_2), .IN6(1'b0), .IN7(~na952_2), + .IN8(~na3693_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x23y55 80'h00_0018_00_0000_0C66_9C00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3683_1 ( .OUT(na3683_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na953_2), .IN7(~na1491_1), .IN8(na864_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x31y31 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3684_4 ( .OUT(na3684_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3684_6 ( .RAM_O2(na3684_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3684_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y31 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3685_1 ( .OUT(na3685_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3685_6 ( .RAM_O1(na3685_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3685_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x31y30 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3686_4 ( .OUT(na3686_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3686_6 ( .RAM_O2(na3686_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3686_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y30 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3687_1 ( .OUT(na3687_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3687_6 ( .RAM_O1(na3687_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3687_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x37y49 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3688_4 ( .OUT(na3688_2), .IN1(1'b1), .IN2(na1593_2), .IN3(~na4523_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x23y61 80'h00_0078_00_0000_0CEE_A7B7 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3689_1 ( .OUT(na3689_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na964_1), .IN6(~na2474_2), .IN7(na952_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a3689_4 ( .OUT(na3689_2), .IN1(~na877_2), .IN2(~na2474_1), .IN3(na4523_2), .IN4(~na884_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x29y24 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3690_4 ( .OUT(na3690_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3690_6 ( .RAM_O2(na3690_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3690_2), .COMP_OUT(1'b0) ); +// C_AND//// x29y24 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3691_1 ( .OUT(na3691_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3691_6 ( .RAM_O1(na3691_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3691_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x29y23 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3692_4 ( .OUT(na3692_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3692_6 ( .RAM_O2(na3692_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3692_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x20y54 80'h00_0018_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3693_1 ( .OUT(na3693_1), .IN1(1'b1), .IN2(na963_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1485_1), .IN8(na2499_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x23y51 80'h00_0060_00_0000_0C08_FF2F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3694_4 ( .OUT(na3694_2), .IN1(1'b1), .IN2(1'b1), .IN3(na951_1), .IN4(~na197_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x26y72 80'h00_0018_00_0000_0EEE_3557 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3695_1 ( .OUT(na3695_1), .IN1(~na1302_1), .IN2(~na929_1), .IN3(~na928_1), .IN4(1'b0), .IN5(~na1301_1), .IN6(1'b0), .IN7(1'b0), + .IN8(~na926_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x29y23 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3696_1 ( .OUT(na3696_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3696_6 ( .RAM_O1(na3696_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3696_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///OR/ x33y72 80'h00_0060_00_0000_0C0E_FF07 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a3697_4 ( .OUT(na3697_2), .IN1(~na3195_1), .IN2(~na137_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x39y71 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3698_1 ( .OUT(na3698_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na984_1), .IN6(1'b1), .IN7(na139_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x31y24 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3699_4 ( .OUT(na3699_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3699_6 ( .RAM_O2(na3699_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3699_2), .COMP_OUT(1'b0) ); +// C_AND//// x13y85 80'h00_0018_00_0000_0888_2121 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3700_1 ( .OUT(na3700_1), .IN1(~na418_1), .IN2(~na412_1), .IN3(na4157_2), .IN4(~na413_1), .IN5(~na411_1), .IN6(~na4413_2), + .IN7(na992_1), .IN8(~na1350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x35y82 80'h00_0060_00_0000_0C08_FF37 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a3701_4 ( .OUT(na3701_2), .IN1(~na2714_1), .IN2(~na232_2), .IN3(1'b0), .IN4(~na1039_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x31y24 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3702_1 ( .OUT(na3702_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3702_6 ( .RAM_O1(na3702_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3702_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x44y91 80'h00_0018_00_0000_0C88_33FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3703_1 ( .OUT(na3703_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na2706_1), .IN7(1'b1), .IN8(~na2707_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x31y23 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3704_4 ( .OUT(na3704_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3704_6 ( .RAM_O2(na3704_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3704_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y23 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3705_1 ( .OUT(na3705_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3705_6 ( .RAM_O1(na3705_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3705_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x42y85 80'h00_0018_00_0000_0C88_DCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3706_1 ( .OUT(na3706_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na4551_2), .IN7(~na2713_2), .IN8(na2710_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x38y82 80'h00_0018_00_0000_0C88_2FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3707_1 ( .OUT(na3707_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2713_2), .IN8(~na2710_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x38y85 80'h00_0060_00_0000_0C06_FFCC +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3708_4 ( .OUT(na3708_2), .IN1(1'b0), .IN2(na1047_1), .IN3(1'b0), .IN4(na1512_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x31y22 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3709_4 ( .OUT(na3709_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3709_6 ( .RAM_O2(na3709_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na3709_2), .COMP_OUT(1'b0) ); +// C_AND//// x31y22 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3710_1 ( .OUT(na3710_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a3710_6 ( .RAM_O1(na3710_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na3710_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_////RAM_I2 x34y28 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3711_5 ( .OUT(na3711_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_93), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y28 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3712_2 ( .OUT(na3712_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_94), .CP_O(1'b0) ); +// C_////RAM_I2 x34y27 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3713_5 ( .OUT(na3713_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_95), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y27 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3714_2 ( .OUT(na3714_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_96), .CP_O(1'b0) ); +// C_////RAM_I2 x34y26 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3715_5 ( .OUT(na3715_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_97), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y26 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3716_2 ( .OUT(na3716_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_98), .CP_O(1'b0) ); +// C_////RAM_I2 x34y25 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3717_5 ( .OUT(na3717_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_99), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y25 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3718_2 ( .OUT(na3718_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_100), .CP_O(1'b0) ); +// C_////RAM_I2 x34y20 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3719_5 ( .OUT(na3719_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_113), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y20 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3720_2 ( .OUT(na3720_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_114), .CP_O(1'b0) ); +// C_////RAM_I2 x34y19 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3721_5 ( .OUT(na3721_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_115), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y19 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3722_2 ( .OUT(na3722_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_116), .CP_O(1'b0) ); +// C_////RAM_I2 x34y18 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3723_5 ( .OUT(na3723_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_117), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y18 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3724_2 ( .OUT(na3724_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_118), .CP_O(1'b0) ); +// C_////RAM_I2 x34y17 80'h02_0000_00_0000_0C00_FFFF +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0000)) + _a3725_5 ( .OUT(na3725_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_119), .CP_O(1'b0) ); +// C_/RAM_I1/// x34y17 80'h01_0000_00_0000_0C00_FFFF +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0000)) + _a3726_2 ( .OUT(na3726_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na3226_120), .CP_O(1'b0) ); +// C_///AND/ x45y90 80'h00_0060_00_0000_0C08_FFF2 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3775_4 ( .OUT(na3775_2), .IN1(na434_2), .IN2(~na2706_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x63y80 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3777_4 ( .OUT(na3777_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na38_2), .IN4(na1085_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x65y72 80'h00_0018_00_0000_0C66_C300 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3778_1 ( .OUT(na3778_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na1087_1), .IN7(1'b0), .IN8(na1985_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x40y69 80'h00_0018_00_0000_0C88_F1FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3782_1 ( .OUT(na3782_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na821_1), .IN6(~na817_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x35y71 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3783_1 ( .OUT(na3783_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4136_2), .IN5(~na1294_1), .IN6(1'b0), .IN7(~na2741_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x31y69 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3786_1 ( .OUT(na3786_1), .IN1(1'b1), .IN2(na219_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na4559_2), .IN6(~na1338_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x35y69 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3789_1 ( .OUT(na3789_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na4136_2), .IN5(~na1295_1), .IN6(1'b0), .IN7(~na2743_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x37y69 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3792_1 ( .OUT(na3792_1), .IN1(1'b1), .IN2(na219_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na4560_2), .IN6(~na1298_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x33y67 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3795_1 ( .OUT(na3795_1), .IN1(1'b1), .IN2(~na219_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na1308_1), .IN6(~na2745_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x51y84 80'h00_0018_00_0000_0C88_A5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3796_1 ( .OUT(na3796_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na821_1), .IN6(1'b1), .IN7(na2847_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x58y82 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3797_4 ( .OUT(na3797_2), .IN1(~na821_1), .IN2(1'b1), .IN3(na2847_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y81 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3798_4 ( .OUT(na3798_2), .IN1(~na821_1), .IN2(1'b1), .IN3(na2849_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x59y85 80'h00_0060_00_0000_0C08_FFA5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3799_4 ( .OUT(na3799_2), .IN1(~na821_1), .IN2(1'b1), .IN3(na2849_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x49y83 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3800_1 ( .OUT(na3800_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na821_1), .IN6(1'b1), .IN7(1'b1), .IN8(na2851_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x47y83 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3801_1 ( .OUT(na3801_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na821_1), .IN6(1'b1), .IN7(1'b1), .IN8(na2851_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x46y85 80'h00_0018_00_0000_0C88_F4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3802_1 ( .OUT(na3802_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na821_1), .IN6(na1112_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x42y92 80'h00_0018_00_0000_0888_7A3A +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3804_1 ( .OUT(na3804_1), .IN1(na3817_1), .IN2(1'b0), .IN3(1'b0), .IN4(~na1113_1), .IN5(na3817_2), .IN6(1'b0), .IN7(~na3821_1), + .IN8(~na1113_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x39y85 80'h00_0060_00_0000_0C06_FFC9 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3805_4 ( .OUT(na3805_2), .IN1(na1114_1), .IN2(~na1513_1), .IN3(1'b0), .IN4(na993_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x33y89 80'h00_0018_00_0000_0C66_5600 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3809_1 ( .OUT(na3809_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1120_2), .IN6(na1505_2), .IN7(~na1122_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x38y87 80'h00_0060_00_0000_0C08_FF55 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3811_4 ( .OUT(na3811_2), .IN1(~na2712_1), .IN2(1'b1), .IN3(~na2713_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x33y87 80'h00_0018_00_0000_0888_AF3E +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3812_1 ( .OUT(na3812_1), .IN1(na434_1), .IN2(na4626_2), .IN3(1'b0), .IN4(~na4612_2), .IN5(1'b1), .IN6(1'b1), .IN7(na3815_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x34y87 80'h00_0078_00_0000_0C88_AA58 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3815_1 ( .OUT(na3815_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na434_2), .IN6(1'b1), .IN7(na432_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3815_4 ( .OUT(na3815_2), .IN1(na2712_2), .IN2(na4553_2), .IN3(~na2713_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x59y81 80'h00_0060_00_0000_0C08_FF2F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3816_4 ( .OUT(na3816_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1599_2), .IN4(~na2707_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x39y91 80'h00_0078_00_0000_0CEE_D5B7 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3817_1 ( .OUT(na3817_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1134_1), .IN6(1'b0), .IN7(~na4548_2), .IN8(na1113_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a3817_4 ( .OUT(na3817_2), .IN1(~na1037_2), .IN2(~na1047_1), .IN3(na4548_2), .IN4(~na2707_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x40y91 80'h00_0018_00_0040_0AC0_00FA +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3821_1 ( .OUT(na3821_1), .IN1(na1133_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1507_1), .IN8(na2739_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x51y84 80'h00_0060_00_0000_0C08_FFF4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3822_4 ( .OUT(na3822_2), .IN1(~na821_1), .IN2(na1112_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x49y76 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3823_1 ( .OUT(na3823_1), .IN1(1'b1), .IN2(~na285_1), .IN3(1'b0), .IN4(1'b0), .IN5(na21_1), .IN6(na3159_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x58y83 80'h00_0018_00_0000_0C88_BCFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3826_1 ( .OUT(na3826_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na2965_2), .IN7(na2961_1), .IN8(~na4571_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x59y83 80'h00_0018_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3827_1 ( .OUT(na3827_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2962_2), .IN6(1'b1), .IN7(~na2961_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x65y87 80'h00_0018_00_0000_0C66_6000 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3828_1 ( .OUT(na3828_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1534_2), .IN8(na1195_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x61y87 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3895_1 ( .OUT(na3895_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2957_2), .IN6(1'b1), .IN7(1'b1), .IN8(na986_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x20y61 80'h00_0060_00_0000_0C08_FF53 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3898_4 ( .OUT(na3898_2), .IN1(1'b1), .IN2(~na421_1), .IN3(~na426_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x21y65 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3899_1 ( .OUT(na3899_1), .IN1(1'b1), .IN2(na423_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na2986_1), .IN6(~na1320_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x21y67 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3902_1 ( .OUT(na3902_1), .IN1(1'b1), .IN2(na423_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na2986_2), .IN6(~na633_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x25y63 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3905_1 ( .OUT(na3905_1), .IN1(1'b1), .IN2(~na423_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na634_1), .IN6(~na4578_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x19y65 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3908_1 ( .OUT(na3908_1), .IN1(1'b1), .IN2(na423_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na2988_2), .IN6(~na635_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x17y65 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3911_1 ( .OUT(na3911_1), .IN1(1'b1), .IN2(~na423_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1319_1), .IN6(~na2990_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x33y63 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3912_4 ( .OUT(na3912_2), .IN1(na3105_1), .IN2(1'b1), .IN3(~na426_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x35y63 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3913_4 ( .OUT(na3913_2), .IN1(na3105_2), .IN2(1'b1), .IN3(~na426_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x33y63 80'h00_0018_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3914_1 ( .OUT(na3914_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3107_1), .IN6(1'b1), .IN7(~na426_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x35y63 80'h00_0018_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3915_1 ( .OUT(na3915_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na3107_2), .IN6(1'b1), .IN7(~na426_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x37y62 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3916_1 ( .OUT(na3916_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na426_1), .IN8(na3109_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x39y61 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3917_4 ( .OUT(na3917_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na426_1), .IN4(na3109_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x42y66 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3918_4 ( .OUT(na3918_2), .IN1(1'b1), .IN2(na1254_2), .IN3(~na426_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x64y85 80'h00_0018_00_0000_0888_C7C5 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3920_1 ( .OUT(na3920_1), .IN1(~na1255_1), .IN2(1'b0), .IN3(1'b0), .IN4(na3933_1), .IN5(~na1255_2), .IN6(~na3937_1), .IN7(1'b0), + .IN8(na3933_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x64y80 80'h00_0060_00_0000_0C06_FFC9 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3921_4 ( .OUT(na3921_2), .IN1(~na1535_1), .IN2(na1256_2), .IN3(1'b0), .IN4(na1388_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x50y88 80'h00_0018_00_0000_0C66_6300 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a3925_1 ( .OUT(na3925_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na1264_1), .IN7(na1527_2), .IN8(na1262_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x61y83 80'h00_0060_00_0000_0C08_FFF1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3927_4 ( .OUT(na3927_2), .IN1(~na2963_2), .IN2(~na2965_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x57y90 80'h00_0018_00_0000_0888_FAE3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a3928_1 ( .OUT(na3928_1), .IN1(1'b0), .IN2(~na4589_2), .IN3(na4629_2), .IN4(na986_1), .IN5(na3931_2), .IN6(1'b0), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x55y87 80'h00_0078_00_0000_0C88_8FC2 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3931_1 ( .OUT(na3931_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na980_2), .IN8(na986_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3931_4 ( .OUT(na3931_2), .IN1(na2962_1), .IN2(~na2965_2), .IN3(1'b1), .IN4(na4571_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x55y82 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3932_1 ( .OUT(na3932_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na2958_2), .IN8(na1605_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x66y86 80'h00_0078_00_0000_0CEE_7A7D +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3933_1 ( .OUT(na3933_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1255_2), .IN6(1'b0), .IN7(~na2958_2), .IN8(~na1276_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a3933_4 ( .OUT(na3933_2), .IN1(~na460_2), .IN2(na4566_2), .IN3(~na2958_1), .IN4(~na1195_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x59y88 80'h00_0018_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a3937_1 ( .OUT(na3937_1), .IN1(1'b1), .IN2(~na1275_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na2984_1), .IN8(na1529_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x39y67 80'h00_0018_00_0000_0C88_5CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3938_1 ( .OUT(na3938_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1254_1), .IN7(~na426_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x25y72 80'h00_0018_00_0000_0CEE_5300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3939_1 ( .OUT(na3939_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na3217_1), .IN7(~na4109_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x39y71 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3940_4 ( .OUT(na3940_2), .IN1(na1290_1), .IN2(1'b1), .IN3(na139_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x37y78 80'h00_0078_00_0000_0C88_3A8C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3943_1 ( .OUT(na3943_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1188_1), .IN6(1'b1), .IN7(1'b1), .IN8(~na1296_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3943_4 ( .OUT(na3943_2), .IN1(1'b1), .IN2(na3823_1), .IN3(na506_2), .IN4(na1296_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x31y73 80'h00_0060_00_0000_0C08_FF75 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a3944_4 ( .OUT(na3944_2), .IN1(~na1188_1), .IN2(1'b0), .IN3(~na4632_2), .IN4(~na1296_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x49y67 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3948_1 ( .OUT(na3948_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1314_2), .IN6(1'b1), .IN7(na139_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x24y67 80'h00_0060_00_0000_0C08_FFA3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3950_4 ( .OUT(na3950_2), .IN1(1'b1), .IN2(~na405_2), .IN3(na233_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x33y81 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3954_1 ( .OUT(na3954_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na232_2), .IN7(1'b1), .IN8(na1341_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x47y88 80'h00_0060_00_0000_0C06_FF09 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3955_4 ( .OUT(na3955_2), .IN1(~na1343_1), .IN2(na2706_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x26y84 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3958_1 ( .OUT(na3958_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na287_2), .IN8(na1296_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x29y66 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3960_4 ( .OUT(na3960_2), .IN1(na1370_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na214_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x23y59 80'h00_0060_00_0000_0C06_FFC5 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a3961_4 ( .OUT(na3961_2), .IN1(~na1372_1), .IN2(1'b0), .IN3(1'b0), .IN4(na2473_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x48y61 80'h00_0018_00_0000_0EEE_3077 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a3964_1 ( .OUT(na3964_1), .IN1(~na1387_1), .IN2(~na1386_1), .IN3(~na283_1), .IN4(~na284_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(~na282_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x51y59 80'h00_0018_00_0000_0888_1555 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3975_1 ( .OUT(na3975_1), .IN1(~na2001_2), .IN2(1'b1), .IN3(~na2002_1), .IN4(1'b1), .IN5(~na2001_1), .IN6(1'b1), .IN7(~na1999_1), + .IN8(~na2000_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x69y74 80'h00_0018_00_0040_0C86_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3977_1 ( .OUT(na3977_1), .IN1(1'b0), .IN2(na1438_1), .IN3(na4420_2), .IN4(1'b1), .IN5(na524_1), .IN6(1'b1), .IN7(na520_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x67y80 80'h00_0018_00_0040_0C86_C500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3978_1 ( .OUT(na3978_1), .IN1(1'b0), .IN2(na4421_2), .IN3(na1439_1), .IN4(1'b1), .IN5(~na607_1), .IN6(1'b1), .IN7(1'b1), + .IN8(na605_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x55y86 80'h00_0018_00_0040_0C49_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3979_1 ( .OUT(na3979_1), .IN1(na4422_2), .IN2(1'b0), .IN3(1'b1), .IN4(na1440_2), .IN5(~na4080_2), .IN6(1'b1), .IN7(na613_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x65y65 80'h00_0018_00_0040_0A68_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3981_1 ( .OUT(na3981_1), .IN1(1'b1), .IN2(~na599_2), .IN3(na4226_2), .IN4(1'b1), .IN5(1'b0), .IN6(na4427_2), .IN7(na1447_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x68y65 80'h00_0018_00_0000_0C88_33FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3983_1 ( .OUT(na3983_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na2350_2), .IN7(1'b1), .IN8(~na1985_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x52y46 80'h00_0018_00_0000_0888_3313 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a3988_1 ( .OUT(na3988_1), .IN1(1'b1), .IN2(~na2238_1), .IN3(~na2239_1), .IN4(~na2237_2), .IN5(1'b1), .IN6(~na2238_2), .IN7(1'b1), + .IN8(~na2236_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x61y59 80'h00_0018_00_0040_0C49_C500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3990_1 ( .OUT(na3990_1), .IN1(na4429_2), .IN2(1'b0), .IN3(1'b1), .IN4(na1460_2), .IN5(~na708_2), .IN6(1'b1), .IN7(1'b1), + .IN8(na4262_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x61y70 80'h00_0018_00_0040_0C49_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3991_1 ( .OUT(na3991_1), .IN1(na4430_2), .IN2(1'b0), .IN3(1'b1), .IN4(na1461_1), .IN5(na253_1), .IN6(1'b1), .IN7(na251_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x53y73 80'h00_0018_00_0040_0C86_CC00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a3992_1 ( .OUT(na3992_1), .IN1(1'b0), .IN2(na4431_2), .IN3(na1462_2), .IN4(1'b1), .IN5(1'b1), .IN6(na261_2), .IN7(1'b1), .IN8(na327_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x59y50 80'h00_0018_00_0040_0A68_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a3994_1 ( .OUT(na3994_1), .IN1(1'b1), .IN2(~na786_1), .IN3(1'b1), .IN4(na720_1), .IN5(1'b0), .IN6(na4436_2), .IN7(na1469_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x65y47 80'h00_0060_00_0000_0C08_FF35 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a3996_4 ( .OUT(na3996_2), .IN1(~na704_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na4503_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x20y40 80'h00_0018_00_0000_0888_1F15 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a4001_1 ( .OUT(na4001_1), .IN1(~na2490_2), .IN2(1'b1), .IN3(~na2488_1), .IN4(~na2489_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na2487_2), + .IN8(~na2489_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x18y57 80'h00_0018_00_0040_0C86_CA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4003_1 ( .OUT(na4003_1), .IN1(1'b0), .IN2(na1482_2), .IN3(na4438_2), .IN4(1'b1), .IN5(na882_2), .IN6(1'b1), .IN7(1'b1), .IN8(na885_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x19y66 80'h00_0018_00_0040_0C49_CC00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4004_1 ( .OUT(na4004_1), .IN1(na1483_2), .IN2(1'b0), .IN3(1'b1), .IN4(na4439_2), .IN5(1'b1), .IN6(na180_1), .IN7(1'b1), .IN8(na178_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x15y72 80'h00_0018_00_0040_0C49_C300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4005_1 ( .OUT(na4005_1), .IN1(na1484_2), .IN2(1'b0), .IN3(1'b1), .IN4(na4440_2), .IN5(1'b1), .IN6(~na119_1), .IN7(1'b1), + .IN8(na188_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x22y56 80'h00_0018_00_0040_0A68_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a4007_1 ( .OUT(na4007_1), .IN1(1'b1), .IN2(~na953_2), .IN3(1'b1), .IN4(na864_1), .IN5(1'b0), .IN6(na4446_2), .IN7(na1491_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x34y49 80'h00_0018_00_0000_0C88_33FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a4009_1 ( .OUT(na4009_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na881_2), .IN7(1'b1), .IN8(~na2473_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x38y70 80'h00_0018_00_0000_0888_1535 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a4014_1 ( .OUT(na4014_1), .IN1(~na4556_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na2722_1), .IN5(~na4555_2), .IN6(1'b1), .IN7(~na4557_2), + .IN8(~na2723_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x40y90 80'h00_0018_00_0040_0C86_CA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4016_1 ( .OUT(na4016_1), .IN1(1'b0), .IN2(na1504_2), .IN3(na4447_2), .IN4(1'b1), .IN5(na1045_2), .IN6(1'b1), .IN7(1'b1), + .IN8(na1049_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x31y91 80'h00_0018_00_0040_0C86_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4017_1 ( .OUT(na4017_1), .IN1(1'b0), .IN2(na1505_2), .IN3(na4448_2), .IN4(1'b1), .IN5(na1120_2), .IN6(1'b1), .IN7(~na1122_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x27y91 80'h00_0018_00_0040_0C16_3500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4018_1 ( .OUT(na4018_1), .IN1(1'b1), .IN2(na1506_1), .IN3(na4449_2), .IN4(1'b0), .IN5(~na1292_1), .IN6(1'b1), .IN7(1'b1), + .IN8(~na1128_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x35y83 80'h00_0018_00_0040_0A68_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a4020_1 ( .OUT(na4020_1), .IN1(~na1114_1), .IN2(1'b1), .IN3(1'b1), .IN4(na993_1), .IN5(1'b0), .IN6(na1513_1), .IN7(na4452_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x57y86 80'h00_0060_00_0000_0C08_FF33 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a4022_4 ( .OUT(na4022_2), .IN1(1'b1), .IN2(~na1044_2), .IN3(1'b1), .IN4(~na4544_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x31y66 80'h00_0018_00_0000_0888_3351 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a4027_1 ( .OUT(na4027_1), .IN1(~na2974_2), .IN2(~na2973_2), .IN3(~na2972_1), .IN4(1'b1), .IN5(1'b1), .IN6(~na2973_1), .IN7(1'b1), + .IN8(~na2971_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x63y88 80'h00_0018_00_0040_0C49_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4029_1 ( .OUT(na4029_1), .IN1(na4453_2), .IN2(1'b0), .IN3(1'b1), .IN4(na1526_1), .IN5(~na1197_1), .IN6(1'b1), .IN7(na4370_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x49y91 80'h00_0018_00_0040_0C86_C300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4030_1 ( .OUT(na4030_1), .IN1(1'b0), .IN2(na4454_2), .IN3(na1527_2), .IN4(1'b1), .IN5(1'b1), .IN6(~na1264_1), .IN7(1'b1), + .IN8(na1262_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x48y91 80'h00_0018_00_0040_0C86_CA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a4031_1 ( .OUT(na4031_1), .IN1(1'b0), .IN2(na1528_2), .IN3(na4455_2), .IN4(1'b1), .IN5(na1270_2), .IN6(1'b1), .IN7(1'b1), + .IN8(na532_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x61y80 80'h00_0018_00_0040_0A94_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a4033_1 ( .OUT(na4033_1), .IN1(1'b1), .IN2(na1256_2), .IN3(1'b1), .IN4(na1388_1), .IN5(na1535_1), .IN6(1'b0), .IN7(1'b1), + .IN8(na4459_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x67y81 80'h00_0060_00_0000_0C08_FFF1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a4035_4 ( .OUT(na4035_2), .IN1(~na1192_2), .IN2(~na4563_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR///XOR/ x68y81 80'h00_0078_00_0000_0C66_3ACC +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4039_1 ( .OUT(na4039_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2091_1), .IN6(1'b0), .IN7(1'b0), .IN8(~na76_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4039_4 ( .OUT(na4039_2), .IN1(1'b0), .IN2(na2093_1), .IN3(1'b0), .IN4(na76_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x67y83 80'h00_0018_00_0000_0C66_0900 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4040_1 ( .OUT(na4040_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2091_2), .IN6(~na75_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x65y81 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a4041_1 ( .OUT(na4041_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na534_2), .IN6(1'b1), .IN7(1'b1), .IN8(na78_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x70y82 80'h00_0060_00_0000_0C06_FFCA +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4042_4 ( .OUT(na4042_2), .IN1(na534_1), .IN2(1'b0), .IN3(1'b0), .IN4(na78_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x71y79 80'h00_0018_00_0000_0EEE_ED7B +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a4043_1 ( .OUT(na4043_1), .IN1(na4041_1), .IN2(~na94_1), .IN3(~na4039_1), .IN4(~na50_1), .IN5(~na4040_1), .IN6(na94_2), .IN7(na4039_2), + .IN8(na4042_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR///XOR/ x17y87 80'h00_0078_00_0000_0C66_095A +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4045_1 ( .OUT(na4045_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na390_2), .IN6(na1051_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4045_4 ( .OUT(na4045_2), .IN1(na2819_1), .IN2(1'b0), .IN3(~na388_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x22y91 80'h00_0018_00_0000_0C66_0900 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4046_1 ( .OUT(na4046_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na390_1), .IN6(na1051_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR///XOR/ x16y53 80'h00_0078_00_0000_0C66_A5A5 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4050_1 ( .OUT(na4050_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na192_2), .IN6(1'b0), .IN7(na891_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4050_4 ( .OUT(na4050_2), .IN1(~na192_1), .IN2(1'b0), .IN3(na891_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR///XOR/ x37y60 80'h00_0078_00_0000_0C66_90C3 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4053_1 ( .OUT(na4053_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na264_1), .IN8(na2337_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4053_4 ( .OUT(na4053_2), .IN1(1'b0), .IN2(~na265_2), .IN3(1'b0), .IN4(na2337_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x48y53 80'h00_0060_00_0000_0C06_FFA3 +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4054_4 ( .OUT(na4054_2), .IN1(1'b0), .IN2(~na265_1), .IN3(na2339_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR///XOR/ x63y92 80'h00_0078_00_0000_0C66_A390 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4058_1 ( .OUT(na4058_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na825_1), .IN7(na3064_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4058_4 ( .OUT(na4058_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3064_1), .IN4(~na826_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///XOR/ x68y91 80'h00_0060_00_0000_0C06_FF3C +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4059_4 ( .OUT(na4059_2), .IN1(1'b0), .IN2(na3066_1), .IN3(1'b0), .IN4(~na826_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR///XOR/ x15y47 80'h00_0078_00_0000_0C66_A590 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4063_1 ( .OUT(na4063_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na173_1), .IN6(1'b0), .IN7(na2579_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_XOR #(.CPE_CFG (9'b0_1000_0000)) + _a4063_4 ( .OUT(na4063_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2579_1), .IN4(~na190_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x15y52 80'h00_0018_00_0000_0C66_9000 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a4064_1 ( .OUT(na4064_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na4120_2), .IN8(na2581_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x1y51 80'h08_0060_00_0000_0C08_FFF5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a4065_4 ( .OUT(na4065_2), .IN1(~na1540_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a4065_6 ( .RAM_O2(na4065_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na4065_2), .COMP_OUT(1'b0) ); +// C_////Bridge x52y70 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4066_5 ( .OUT(na4066_2), .IN1(1'b0), .IN2(na12_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x51y69 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4067_5 ( .OUT(na4067_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na16_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y62 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4068_5 ( .OUT(na4068_2), .IN1(1'b0), .IN2(1'b0), .IN3(na17_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y48 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4069_5 ( .OUT(na4069_2), .IN1(1'b0), .IN2(1'b0), .IN3(na17_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4070_5 ( .OUT(na4070_2), .IN1(1'b0), .IN2(na22_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y68 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4071_5 ( .OUT(na4071_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na27_1) ); +// C_////Bridge x21y70 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4072_5 ( .OUT(na4072_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na27_2) ); +// C_////Bridge x24y65 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4073_5 ( .OUT(na4073_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na28_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y79 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4074_5 ( .OUT(na4074_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na30_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y62 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4075_5 ( .OUT(na4075_2), .IN1(na31_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x60y70 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4076_5 ( .OUT(na4076_2), .IN1(1'b0), .IN2(na33_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y71 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4077_5 ( .OUT(na4077_2), .IN1(1'b0), .IN2(1'b0), .IN3(na38_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y77 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4078_5 ( .OUT(na4078_2), .IN1(1'b0), .IN2(1'b0), .IN3(na38_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y75 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4079_5 ( .OUT(na4079_2), .IN1(1'b0), .IN2(na40_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y85 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4080_5 ( .OUT(na4080_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na46_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y85 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4081_5 ( .OUT(na4081_2), .IN1(1'b0), .IN2(na47_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x26y75 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4082_5 ( .OUT(na4082_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na51_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y75 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4083_5 ( .OUT(na4083_2), .IN1(na53_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y57 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4084_5 ( .OUT(na4084_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na54_2) ); +// C_////Bridge x61y81 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4085_5 ( .OUT(na4085_2), .IN1(1'b0), .IN2(na57_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y83 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4086_5 ( .OUT(na4086_2), .IN1(1'b0), .IN2(na58_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y75 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4087_5 ( .OUT(na4087_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na67_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x35y71 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4088_5 ( .OUT(na4088_2), .IN1(1'b0), .IN2(1'b0), .IN3(na70_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y72 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4089_5 ( .OUT(na4089_2), .IN1(1'b0), .IN2(1'b0), .IN3(na85_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y74 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4090_5 ( .OUT(na4090_2), .IN1(na90_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y50 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4091_5 ( .OUT(na4091_2), .IN1(1'b0), .IN2(na91_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y50 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4092_5 ( .OUT(na4092_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na93_1), .IN8(1'b0) ); +// C_////Bridge x38y55 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4093_5 ( .OUT(na4093_2), .IN1(1'b0), .IN2(na94_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y71 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4094_5 ( .OUT(na4094_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na104_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y75 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4095_5 ( .OUT(na4095_2), .IN1(1'b0), .IN2(1'b0), .IN3(na107_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x53y54 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4096_5 ( .OUT(na4096_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na108_1) ); +// C_////Bridge x62y75 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4097_5 ( .OUT(na4097_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na109_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y65 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4098_5 ( .OUT(na4098_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na110_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x29y73 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4099_5 ( .OUT(na4099_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na112_1) ); +// C_////Bridge x18y62 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4100_5 ( .OUT(na4100_2), .IN1(na114_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y75 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4101_5 ( .OUT(na4101_2), .IN1(1'b0), .IN2(1'b0), .IN3(na115_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y70 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4102_5 ( .OUT(na4102_2), .IN1(1'b0), .IN2(1'b0), .IN3(na115_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y80 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4103_5 ( .OUT(na4103_2), .IN1(na117_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x14y69 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4104_5 ( .OUT(na4104_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na120_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y57 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4105_5 ( .OUT(na4105_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na124_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y74 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4106_5 ( .OUT(na4106_2), .IN1(na129_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y75 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4107_5 ( .OUT(na4107_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na133_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y84 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4108_5 ( .OUT(na4108_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na135_1) ); +// C_////Bridge x30y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4109_5 ( .OUT(na4109_2), .IN1(1'b0), .IN2(na137_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x47y79 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4110_5 ( .OUT(na4110_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na139_1), .IN8(1'b0) ); +// C_////Bridge x60y68 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4111_5 ( .OUT(na4111_2), .IN1(na145_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x22y85 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4112_5 ( .OUT(na4112_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na158_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x22y83 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4113_5 ( .OUT(na4113_2), .IN1(na160_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x15y82 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4114_5 ( .OUT(na4114_2), .IN1(na163_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y80 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4115_5 ( .OUT(na4115_2), .IN1(na166_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y78 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4116_5 ( .OUT(na4116_2), .IN1(na167_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y78 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4117_5 ( .OUT(na4117_2), .IN1(na169_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y79 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4118_5 ( .OUT(na4118_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na170_1) ); +// C_////Bridge x15y64 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4119_5 ( .OUT(na4119_2), .IN1(1'b0), .IN2(1'b0), .IN3(na189_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x16y51 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4120_5 ( .OUT(na4120_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na190_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x16y48 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4121_5 ( .OUT(na4121_2), .IN1(1'b0), .IN2(na193_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y42 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4122_5 ( .OUT(na4122_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na194_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y46 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4123_5 ( .OUT(na4123_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na197_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y38 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4124_5 ( .OUT(na4124_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na203_1) ); +// C_////Bridge x27y45 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4125_5 ( .OUT(na4125_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na203_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y39 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4126_5 ( .OUT(na4126_2), .IN1(1'b0), .IN2(na207_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y37 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4127_5 ( .OUT(na4127_2), .IN1(1'b0), .IN2(na207_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4128_5 ( .OUT(na4128_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na208_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x15y59 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4129_5 ( .OUT(na4129_2), .IN1(1'b0), .IN2(na209_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y54 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4130_5 ( .OUT(na4130_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na211_1), .IN8(1'b0) ); +// C_////Bridge x21y61 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4131_5 ( .OUT(na4131_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na214_1) ); +// C_////Bridge x27y54 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4132_5 ( .OUT(na4132_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na214_2) ); +// C_////Bridge x36y51 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4133_5 ( .OUT(na4133_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na216_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x18y59 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4134_5 ( .OUT(na4134_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na216_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y78 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4135_5 ( .OUT(na4135_2), .IN1(na218_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x38y70 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4136_5 ( .OUT(na4136_2), .IN1(1'b0), .IN2(na219_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x28y88 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4137_5 ( .OUT(na4137_2), .IN1(na220_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y88 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4138_5 ( .OUT(na4138_2), .IN1(na222_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x28y90 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4139_5 ( .OUT(na4139_2), .IN1(1'b0), .IN2(na225_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y77 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4140_5 ( .OUT(na4140_2), .IN1(1'b0), .IN2(na232_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x38y81 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4141_5 ( .OUT(na4141_2), .IN1(1'b0), .IN2(na232_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y70 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4142_5 ( .OUT(na4142_2), .IN1(1'b0), .IN2(1'b0), .IN3(na233_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x13y66 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4143_5 ( .OUT(na4143_2), .IN1(1'b0), .IN2(1'b0), .IN3(na233_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x43y80 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4144_5 ( .OUT(na4144_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na240_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x31y87 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4145_5 ( .OUT(na4145_2), .IN1(1'b0), .IN2(1'b0), .IN3(na241_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x25y74 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4146_5 ( .OUT(na4146_2), .IN1(na243_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y71 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4147_5 ( .OUT(na4147_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na245_1) ); +// C_////Bridge x61y77 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4148_5 ( .OUT(na4148_2), .IN1(1'b0), .IN2(1'b0), .IN3(na246_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y33 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4149_5 ( .OUT(na4149_2), .IN1(1'b0), .IN2(1'b0), .IN3(na280_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y35 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4150_5 ( .OUT(na4150_2), .IN1(1'b0), .IN2(1'b0), .IN3(na280_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4151_5 ( .OUT(na4151_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na282_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4152_5 ( .OUT(na4152_2), .IN1(1'b0), .IN2(na285_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y68 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4153_5 ( .OUT(na4153_2), .IN1(1'b0), .IN2(na285_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y64 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4154_5 ( .OUT(na4154_2), .IN1(1'b0), .IN2(na285_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y76 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4155_5 ( .OUT(na4155_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na287_2), .IN8(1'b0) ); +// C_////Bridge x18y80 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4156_5 ( .OUT(na4156_2), .IN1(1'b0), .IN2(na288_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x16y85 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4157_5 ( .OUT(na4157_2), .IN1(1'b0), .IN2(na288_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x18y82 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4158_5 ( .OUT(na4158_2), .IN1(1'b0), .IN2(na288_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y62 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4159_5 ( .OUT(na4159_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na295_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y58 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4160_5 ( .OUT(na4160_2), .IN1(1'b0), .IN2(na295_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y55 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4161_5 ( .OUT(na4161_2), .IN1(1'b0), .IN2(1'b0), .IN3(na297_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y62 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4162_5 ( .OUT(na4162_2), .IN1(1'b0), .IN2(1'b0), .IN3(na297_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x13y61 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4163_5 ( .OUT(na4163_2), .IN1(1'b0), .IN2(na299_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x28y58 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4164_5 ( .OUT(na4164_2), .IN1(1'b0), .IN2(na299_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y42 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4165_5 ( .OUT(na4165_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na303_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x16y52 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4166_5 ( .OUT(na4166_2), .IN1(1'b0), .IN2(1'b0), .IN3(na304_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x29y76 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4167_5 ( .OUT(na4167_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na311_1), .IN8(1'b0) ); +// C_////Bridge x29y74 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4168_5 ( .OUT(na4168_2), .IN1(na316_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y77 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4169_5 ( .OUT(na4169_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na322_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y67 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4170_5 ( .OUT(na4170_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na324_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y64 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4171_5 ( .OUT(na4171_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na331_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x51y62 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4172_5 ( .OUT(na4172_2), .IN1(1'b0), .IN2(1'b0), .IN3(na332_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y62 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4173_5 ( .OUT(na4173_2), .IN1(na333_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y56 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4174_5 ( .OUT(na4174_2), .IN1(na335_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y54 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4175_5 ( .OUT(na4175_2), .IN1(1'b0), .IN2(1'b0), .IN3(na353_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y55 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4176_5 ( .OUT(na4176_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na354_1), .IN8(1'b0) ); +// C_////Bridge x70y54 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4177_5 ( .OUT(na4177_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na355_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y56 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4178_5 ( .OUT(na4178_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na356_1), .IN8(1'b0) ); +// C_////Bridge x26y55 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4179_5 ( .OUT(na4179_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na358_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y76 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4180_5 ( .OUT(na4180_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na360_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y77 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4181_5 ( .OUT(na4181_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na362_2), .IN8(1'b0) ); +// C_////Bridge x43y75 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4182_5 ( .OUT(na4182_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na363_2), .IN8(1'b0) ); +// C_////Bridge x35y70 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4183_5 ( .OUT(na4183_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na364_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x43y71 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4184_5 ( .OUT(na4184_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na365_2), .IN8(1'b0) ); +// C_////Bridge x45y74 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4185_5 ( .OUT(na4185_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na366_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x43y73 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4186_5 ( .OUT(na4186_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na367_2), .IN8(1'b0) ); +// C_////Bridge x45y75 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4187_5 ( .OUT(na4187_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na368_2), .IN8(1'b0) ); +// C_////Bridge x43y78 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4188_5 ( .OUT(na4188_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na369_2) ); +// C_////Bridge x26y89 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4189_5 ( .OUT(na4189_2), .IN1(na370_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y87 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4190_5 ( .OUT(na4190_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na371_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y90 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4191_5 ( .OUT(na4191_2), .IN1(na374_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y89 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4192_5 ( .OUT(na4192_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na409_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y86 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4193_5 ( .OUT(na4193_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na410_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x32y56 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4194_5 ( .OUT(na4194_2), .IN1(1'b0), .IN2(na421_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y72 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4195_5 ( .OUT(na4195_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na424_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y72 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4196_5 ( .OUT(na4196_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na428_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y71 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4197_5 ( .OUT(na4197_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na429_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y91 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4198_5 ( .OUT(na4198_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na432_2), .IN8(1'b0) ); +// C_////Bridge x34y93 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4199_5 ( .OUT(na4199_2), .IN1(na434_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y78 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4200_5 ( .OUT(na4200_2), .IN1(na434_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y86 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4201_5 ( .OUT(na4201_2), .IN1(1'b0), .IN2(1'b0), .IN3(na443_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x51y76 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4202_5 ( .OUT(na4202_2), .IN1(na445_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y88 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4203_5 ( .OUT(na4203_2), .IN1(na445_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y90 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4204_5 ( .OUT(na4204_2), .IN1(na455_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y68 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4205_5 ( .OUT(na4205_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na456_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y77 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4206_5 ( .OUT(na4206_2), .IN1(na456_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y86 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4207_5 ( .OUT(na4207_2), .IN1(na456_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y87 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4208_5 ( .OUT(na4208_2), .IN1(1'b0), .IN2(1'b0), .IN3(na461_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y84 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4209_5 ( .OUT(na4209_2), .IN1(1'b0), .IN2(1'b0), .IN3(na461_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x36y52 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4210_5 ( .OUT(na4210_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na465_1), .IN8(1'b0) ); +// C_////Bridge x68y85 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4211_5 ( .OUT(na4211_2), .IN1(1'b0), .IN2(na466_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y76 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4212_5 ( .OUT(na4212_2), .IN1(1'b0), .IN2(na469_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y66 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4213_5 ( .OUT(na4213_2), .IN1(na486_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y87 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4214_5 ( .OUT(na4214_2), .IN1(1'b0), .IN2(na510_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y65 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4215_5 ( .OUT(na4215_2), .IN1(1'b0), .IN2(na512_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y80 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4216_5 ( .OUT(na4216_2), .IN1(1'b0), .IN2(na512_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y72 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4217_5 ( .OUT(na4217_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na516_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x69y69 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4218_5 ( .OUT(na4218_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na517_2) ); +// C_////Bridge x66y71 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4219_5 ( .OUT(na4219_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na519_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y64 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4220_5 ( .OUT(na4220_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na519_2) ); +// C_////Bridge x72y75 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4221_5 ( .OUT(na4221_2), .IN1(na522_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y78 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4222_5 ( .OUT(na4222_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na523_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y50 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4223_5 ( .OUT(na4223_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na526_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y60 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4224_5 ( .OUT(na4224_2), .IN1(1'b0), .IN2(1'b0), .IN3(na529_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y85 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4225_5 ( .OUT(na4225_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na533_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y67 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4226_5 ( .OUT(na4226_2), .IN1(na535_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y38 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4227_5 ( .OUT(na4227_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na536_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y40 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4228_5 ( .OUT(na4228_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na536_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y50 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4229_5 ( .OUT(na4229_2), .IN1(na543_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y48 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4230_5 ( .OUT(na4230_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na543_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y53 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4231_5 ( .OUT(na4231_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na547_1), .IN8(1'b0) ); +// C_////Bridge x71y53 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4232_5 ( .OUT(na4232_2), .IN1(1'b0), .IN2(1'b0), .IN3(na547_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y49 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4233_5 ( .OUT(na4233_2), .IN1(1'b0), .IN2(1'b0), .IN3(na549_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y47 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4234_5 ( .OUT(na4234_2), .IN1(1'b0), .IN2(1'b0), .IN3(na549_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y49 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4235_5 ( .OUT(na4235_2), .IN1(1'b0), .IN2(1'b0), .IN3(na551_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x69y55 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4236_5 ( .OUT(na4236_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na551_2), .IN8(1'b0) ); +// C_////Bridge x65y51 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4237_5 ( .OUT(na4237_2), .IN1(1'b0), .IN2(na553_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x69y47 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4238_5 ( .OUT(na4238_2), .IN1(1'b0), .IN2(na553_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y44 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4239_5 ( .OUT(na4239_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na555_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y46 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4240_5 ( .OUT(na4240_2), .IN1(na555_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y44 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4241_5 ( .OUT(na4241_2), .IN1(na557_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y44 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4242_5 ( .OUT(na4242_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na557_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y51 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4243_5 ( .OUT(na4243_2), .IN1(1'b0), .IN2(na559_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y51 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4244_5 ( .OUT(na4244_2), .IN1(1'b0), .IN2(na559_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y49 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4245_5 ( .OUT(na4245_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na561_1), .IN8(1'b0) ); +// C_////Bridge x71y47 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4246_5 ( .OUT(na4246_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na561_2), .IN8(1'b0) ); +// C_////Bridge x66y46 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4247_5 ( .OUT(na4247_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na569_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y48 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4248_5 ( .OUT(na4248_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na569_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y46 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4249_5 ( .OUT(na4249_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na571_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y46 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4250_5 ( .OUT(na4250_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na571_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y44 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4251_5 ( .OUT(na4251_2), .IN1(na573_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y44 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4252_5 ( .OUT(na4252_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na573_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y73 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4253_5 ( .OUT(na4253_2), .IN1(1'b0), .IN2(1'b0), .IN3(na603_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y71 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4254_5 ( .OUT(na4254_2), .IN1(1'b0), .IN2(na633_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x55y34 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4255_5 ( .OUT(na4255_2), .IN1(1'b0), .IN2(1'b0), .IN3(na636_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y78 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4256_5 ( .OUT(na4256_2), .IN1(na647_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y59 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4257_5 ( .OUT(na4257_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na664_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y44 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4258_5 ( .OUT(na4258_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na677_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y86 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4259_5 ( .OUT(na4259_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na693_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y88 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4260_5 ( .OUT(na4260_2), .IN1(na696_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y43 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4261_5 ( .OUT(na4261_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na704_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y58 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4262_5 ( .OUT(na4262_2), .IN1(1'b0), .IN2(na705_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y61 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4263_5 ( .OUT(na4263_2), .IN1(na707_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x25y84 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4264_5 ( .OUT(na4264_2), .IN1(na712_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y45 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4265_5 ( .OUT(na4265_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na720_1) ); +// C_////Bridge x21y86 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4266_5 ( .OUT(na4266_2), .IN1(na727_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y43 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4267_5 ( .OUT(na4267_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na728_1) ); +// C_////Bridge x62y39 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4268_5 ( .OUT(na4268_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na728_2) ); +// C_////Bridge x60y43 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4269_5 ( .OUT(na4269_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na734_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y41 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4270_5 ( .OUT(na4270_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na734_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y36 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4271_5 ( .OUT(na4271_2), .IN1(1'b0), .IN2(1'b0), .IN3(na738_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y36 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4272_5 ( .OUT(na4272_2), .IN1(1'b0), .IN2(1'b0), .IN3(na738_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y38 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4273_5 ( .OUT(na4273_2), .IN1(1'b0), .IN2(1'b0), .IN3(na740_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y38 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4274_5 ( .OUT(na4274_2), .IN1(1'b0), .IN2(1'b0), .IN3(na740_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y38 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4275_5 ( .OUT(na4275_2), .IN1(1'b0), .IN2(1'b0), .IN3(na742_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y40 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4276_5 ( .OUT(na4276_2), .IN1(1'b0), .IN2(1'b0), .IN3(na742_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y38 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4277_5 ( .OUT(na4277_2), .IN1(1'b0), .IN2(1'b0), .IN3(na744_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y40 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4278_5 ( .OUT(na4278_2), .IN1(1'b0), .IN2(1'b0), .IN3(na744_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y37 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4279_5 ( .OUT(na4279_2), .IN1(1'b0), .IN2(1'b0), .IN3(na746_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y35 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4280_5 ( .OUT(na4280_2), .IN1(1'b0), .IN2(1'b0), .IN3(na746_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y39 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4281_5 ( .OUT(na4281_2), .IN1(1'b0), .IN2(1'b0), .IN3(na748_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y37 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4282_5 ( .OUT(na4282_2), .IN1(1'b0), .IN2(1'b0), .IN3(na748_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y37 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4283_5 ( .OUT(na4283_2), .IN1(na752_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y33 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4284_5 ( .OUT(na4284_2), .IN1(na752_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y33 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4285_5 ( .OUT(na4285_2), .IN1(1'b0), .IN2(na754_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y37 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4286_5 ( .OUT(na4286_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na754_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y35 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4287_5 ( .OUT(na4287_2), .IN1(1'b0), .IN2(na756_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y35 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4288_5 ( .OUT(na4288_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na756_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y38 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4289_5 ( .OUT(na4289_2), .IN1(1'b0), .IN2(1'b0), .IN3(na758_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y40 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4290_5 ( .OUT(na4290_2), .IN1(1'b0), .IN2(1'b0), .IN3(na758_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x25y86 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4291_5 ( .OUT(na4291_2), .IN1(na762_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x25y78 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4292_5 ( .OUT(na4292_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na815_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y69 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4293_5 ( .OUT(na4293_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na817_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y82 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4294_5 ( .OUT(na4294_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na823_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y48 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4295_5 ( .OUT(na4295_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na843_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x25y51 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4296_5 ( .OUT(na4296_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na864_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y52 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4297_5 ( .OUT(na4297_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na864_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y53 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4298_5 ( .OUT(na4298_2), .IN1(1'b0), .IN2(na878_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x14y48 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4299_5 ( .OUT(na4299_2), .IN1(1'b0), .IN2(na878_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y49 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4300_5 ( .OUT(na4300_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na879_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y62 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4301_5 ( .OUT(na4301_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na880_2), .IN8(1'b0) ); +// C_////Bridge x44y51 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4302_5 ( .OUT(na4302_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na881_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y58 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4303_5 ( .OUT(na4303_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na884_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y51 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4304_5 ( .OUT(na4304_2), .IN1(1'b0), .IN2(1'b0), .IN3(na892_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y52 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4305_5 ( .OUT(na4305_2), .IN1(1'b0), .IN2(1'b0), .IN3(na892_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y58 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4306_5 ( .OUT(na4306_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na894_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y58 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4307_5 ( .OUT(na4307_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na894_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y50 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4308_5 ( .OUT(na4308_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na896_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x47y48 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4309_5 ( .OUT(na4309_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na896_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x46y44 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4310_5 ( .OUT(na4310_2), .IN1(1'b0), .IN2(na900_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x48y44 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4311_5 ( .OUT(na4311_2), .IN1(1'b0), .IN2(na900_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x43y39 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4312_5 ( .OUT(na4312_2), .IN1(1'b0), .IN2(na902_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x43y41 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4313_5 ( .OUT(na4313_2), .IN1(1'b0), .IN2(na902_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y45 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4314_5 ( .OUT(na4314_2), .IN1(1'b0), .IN2(na904_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x38y41 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4315_5 ( .OUT(na4315_2), .IN1(1'b0), .IN2(na904_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x35y43 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4316_5 ( .OUT(na4316_2), .IN1(1'b0), .IN2(na906_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y51 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4317_5 ( .OUT(na4317_2), .IN1(1'b0), .IN2(na906_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y46 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4318_5 ( .OUT(na4318_2), .IN1(na908_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y50 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4319_5 ( .OUT(na4319_2), .IN1(na908_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y42 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4320_5 ( .OUT(na4320_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na910_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y40 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4321_5 ( .OUT(na4321_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na910_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x38y46 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4322_5 ( .OUT(na4322_2), .IN1(1'b0), .IN2(na914_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y50 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4323_5 ( .OUT(na4323_2), .IN1(1'b0), .IN2(na914_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x47y42 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4324_5 ( .OUT(na4324_2), .IN1(1'b0), .IN2(1'b0), .IN3(na918_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x47y40 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4325_5 ( .OUT(na4325_2), .IN1(1'b0), .IN2(1'b0), .IN3(na918_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y43 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4326_5 ( .OUT(na4326_2), .IN1(1'b0), .IN2(na920_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y43 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4327_5 ( .OUT(na4327_2), .IN1(1'b0), .IN2(na920_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y40 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4328_5 ( .OUT(na4328_2), .IN1(1'b0), .IN2(1'b0), .IN3(na922_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y42 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4329_5 ( .OUT(na4329_2), .IN1(1'b0), .IN2(1'b0), .IN3(na922_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x28y69 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4330_5 ( .OUT(na4330_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na926_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y71 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4331_5 ( .OUT(na4331_2), .IN1(1'b0), .IN2(1'b0), .IN3(na928_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y70 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4332_5 ( .OUT(na4332_2), .IN1(1'b0), .IN2(1'b0), .IN3(na928_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y86 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4333_5 ( .OUT(na4333_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na986_1) ); +// C_////Bridge x41y84 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4334_5 ( .OUT(na4334_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na993_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y71 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4335_5 ( .OUT(na4335_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1010_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x46y75 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4336_5 ( .OUT(na4336_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1016_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y93 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4337_5 ( .OUT(na4337_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1038_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y86 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4338_5 ( .OUT(na4338_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1038_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y88 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4339_5 ( .OUT(na4339_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1043_1), .IN8(1'b0) ); +// C_////Bridge x48y88 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4340_5 ( .OUT(na4340_2), .IN1(1'b0), .IN2(na1044_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y71 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4341_5 ( .OUT(na4341_2), .IN1(1'b0), .IN2(na1052_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y73 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4342_5 ( .OUT(na4342_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1058_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y73 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4343_5 ( .OUT(na4343_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1058_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y76 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4344_5 ( .OUT(na4344_2), .IN1(na1062_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x55y72 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4345_5 ( .OUT(na4345_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1062_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x53y76 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4346_5 ( .OUT(na4346_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1064_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y78 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4347_5 ( .OUT(na4347_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1064_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y76 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4348_5 ( .OUT(na4348_2), .IN1(na1066_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y74 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4349_5 ( .OUT(na4349_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1066_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y86 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4350_5 ( .OUT(na4350_2), .IN1(na1068_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y76 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4351_5 ( .OUT(na4351_2), .IN1(na1068_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y74 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4352_5 ( .OUT(na4352_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1068_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y77 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4353_5 ( .OUT(na4353_2), .IN1(na1070_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y71 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4354_5 ( .OUT(na4354_2), .IN1(na1070_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y77 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4355_5 ( .OUT(na4355_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1072_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x60y75 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4356_5 ( .OUT(na4356_2), .IN1(na1072_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y75 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4357_5 ( .OUT(na4357_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1076_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y73 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4358_5 ( .OUT(na4358_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1076_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y76 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4359_5 ( .OUT(na4359_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1078_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y72 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4360_5 ( .OUT(na4360_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1078_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y69 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4361_5 ( .OUT(na4361_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1080_1) ); +// C_////Bridge x53y69 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4362_5 ( .OUT(na4362_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1080_2) ); +// C_////Bridge x55y76 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4363_5 ( .OUT(na4363_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1082_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x51y74 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4364_5 ( .OUT(na4364_2), .IN1(na1082_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y71 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4365_5 ( .OUT(na4365_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1090_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y74 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4366_5 ( .OUT(na4366_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1149_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y76 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4367_5 ( .OUT(na4367_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1149_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x51y85 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4368_5 ( .OUT(na4368_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1167_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x29y64 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4369_5 ( .OUT(na4369_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1179_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y89 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4370_5 ( .OUT(na4370_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1193_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y89 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4371_5 ( .OUT(na4371_2), .IN1(1'b0), .IN2(na1196_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x53y82 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4372_5 ( .OUT(na4372_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1198_1), .IN8(1'b0) ); +// C_////Bridge x51y78 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4373_5 ( .OUT(na4373_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1200_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y58 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4374_5 ( .OUT(na4374_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1200_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x43y62 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4375_5 ( .OUT(na4375_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1202_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y56 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4376_5 ( .OUT(na4376_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1202_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y60 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4377_5 ( .OUT(na4377_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1204_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y62 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4378_5 ( .OUT(na4378_2), .IN1(1'b0), .IN2(na1204_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y60 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4379_5 ( .OUT(na4379_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1208_1) ); +// C_////Bridge x35y58 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4380_5 ( .OUT(na4380_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1208_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y66 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4381_5 ( .OUT(na4381_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1210_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x30y66 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4382_5 ( .OUT(na4382_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1210_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x35y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4383_5 ( .OUT(na4383_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1212_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4384_5 ( .OUT(na4384_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1212_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x38y61 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4385_5 ( .OUT(na4385_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1214_1) ); +// C_////Bridge x36y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4386_5 ( .OUT(na4386_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1214_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4387_5 ( .OUT(na4387_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1216_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y57 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4388_5 ( .OUT(na4388_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1216_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y62 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4389_5 ( .OUT(na4389_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1222_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x35y62 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4390_5 ( .OUT(na4390_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1222_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y71 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4391_5 ( .OUT(na4391_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1224_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x38y58 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4392_5 ( .OUT(na4392_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1226_1), .IN8(1'b0) ); +// C_////Bridge x34y56 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4393_5 ( .OUT(na4393_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1226_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x34y57 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4394_5 ( .OUT(na4394_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1228_1) ); +// C_////Bridge x38y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4395_5 ( .OUT(na4395_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1228_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x36y54 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4396_5 ( .OUT(na4396_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1230_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x38y54 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4397_5 ( .OUT(na4397_2), .IN1(na1230_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y84 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4398_5 ( .OUT(na4398_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1260_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y73 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4399_5 ( .OUT(na4399_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1296_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y75 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4400_5 ( .OUT(na4400_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1296_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y74 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4401_5 ( .OUT(na4401_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1296_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y88 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4402_5 ( .OUT(na4402_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1306_1) ); +// C_////Bridge x31y81 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4403_5 ( .OUT(na4403_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1313_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y87 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4404_5 ( .OUT(na4404_2), .IN1(1'b0), .IN2(na1321_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x28y89 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4405_5 ( .OUT(na4405_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1324_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x46y87 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4406_5 ( .OUT(na4406_2), .IN1(1'b0), .IN2(na1325_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y85 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4407_5 ( .OUT(na4407_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1326_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x47y69 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4408_5 ( .OUT(na4408_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1330_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y69 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4409_5 ( .OUT(na4409_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1330_2) ); +// C_////Bridge x31y85 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4410_5 ( .OUT(na4410_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1331_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x43y89 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4411_5 ( .OUT(na4411_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1347_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x31y92 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4412_5 ( .OUT(na4412_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1349_2), .IN8(1'b0) ); +// C_////Bridge x11y84 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4413_5 ( .OUT(na4413_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1351_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x26y41 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4414_5 ( .OUT(na4414_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1353_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y68 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4415_5 ( .OUT(na4415_2), .IN1(na1366_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y56 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4416_5 ( .OUT(na4416_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1375_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y85 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4417_5 ( .OUT(na4417_2), .IN1(1'b0), .IN2(na1377_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x48y54 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4418_5 ( .OUT(na4418_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1386_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x48y63 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4419_5 ( .OUT(na4419_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1387_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y73 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4420_5 ( .OUT(na4420_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1438_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x69y80 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4421_5 ( .OUT(na4421_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1439_1), .IN8(1'b0) ); +// C_////Bridge x57y83 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4422_5 ( .OUT(na4422_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1440_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y65 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4423_5 ( .OUT(na4423_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1443_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y64 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4424_5 ( .OUT(na4424_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1443_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x69y70 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4425_5 ( .OUT(na4425_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1444_1), .IN8(1'b0) ); +// C_////Bridge x71y75 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4426_5 ( .OUT(na4426_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1446_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y64 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4427_5 ( .OUT(na4427_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1447_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x60y73 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4428_5 ( .OUT(na4428_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1451_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y57 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4429_5 ( .OUT(na4429_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1460_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y67 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4430_5 ( .OUT(na4430_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1461_1) ); +// C_////Bridge x55y74 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4431_5 ( .OUT(na4431_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1462_2), .IN8(1'b0) ); +// C_////Bridge x54y50 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4432_5 ( .OUT(na4432_2), .IN1(na1465_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y53 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4433_5 ( .OUT(na4433_2), .IN1(1'b0), .IN2(na1466_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x48y58 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4434_5 ( .OUT(na4434_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1467_2), .IN8(1'b0) ); +// C_////Bridge x57y64 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4435_5 ( .OUT(na4435_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1468_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y48 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4436_5 ( .OUT(na4436_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1469_1), .IN8(1'b0) ); +// C_////Bridge x50y62 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4437_5 ( .OUT(na4437_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1473_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y55 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4438_5 ( .OUT(na4438_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1482_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x22y66 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4439_5 ( .OUT(na4439_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1483_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x18y72 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4440_5 ( .OUT(na4440_2), .IN1(na1484_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x15y48 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4441_5 ( .OUT(na4441_2), .IN1(1'b0), .IN2(na1487_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x26y52 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4442_5 ( .OUT(na4442_2), .IN1(1'b0), .IN2(na1487_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x26y64 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4443_5 ( .OUT(na4443_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1488_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y47 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4444_5 ( .OUT(na4444_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1489_2) ); +// C_////Bridge x20y50 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4445_5 ( .OUT(na4445_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1490_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y54 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4446_5 ( .OUT(na4446_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1491_1), .IN8(1'b0) ); +// C_////Bridge x42y87 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4447_5 ( .OUT(na4447_2), .IN1(1'b0), .IN2(na1504_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x34y89 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4448_5 ( .OUT(na4448_2), .IN1(1'b0), .IN2(na1505_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x30y91 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4449_5 ( .OUT(na4449_2), .IN1(1'b0), .IN2(na1506_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y90 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4450_5 ( .OUT(na4450_2), .IN1(na1510_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y87 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4451_5 ( .OUT(na4451_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1512_1) ); +// C_////Bridge x34y81 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4452_5 ( .OUT(na4452_2), .IN1(1'b0), .IN2(na1513_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y85 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4453_5 ( .OUT(na4453_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1526_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x51y92 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4454_5 ( .OUT(na4454_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1527_2), .IN8(1'b0) ); +// C_////Bridge x50y91 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4455_5 ( .OUT(na4455_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1528_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y86 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4456_5 ( .OUT(na4456_2), .IN1(na1532_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y92 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4457_5 ( .OUT(na4457_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1533_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y86 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4458_5 ( .OUT(na4458_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1534_2), .IN8(1'b0) ); +// C_////Bridge x64y78 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4459_5 ( .OUT(na4459_2), .IN1(na1535_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x35y61 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4460_5 ( .OUT(na4460_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1539_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y61 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4461_5 ( .OUT(na4461_2), .IN1(1'b0), .IN2(na1541_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x36y60 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4462_5 ( .OUT(na4462_2), .IN1(1'b0), .IN2(na1541_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y40 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4463_5 ( .OUT(na4463_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1542_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y37 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4464_5 ( .OUT(na4464_2), .IN1(1'b0), .IN2(na1542_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x52y73 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4465_5 ( .OUT(na4465_2), .IN1(1'b0), .IN2(na1543_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x55y73 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4466_5 ( .OUT(na4466_2), .IN1(1'b0), .IN2(na1543_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y47 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4467_5 ( .OUT(na4467_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1544_2) ); +// C_////Bridge x41y45 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4468_5 ( .OUT(na4468_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1545_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x15y56 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4469_5 ( .OUT(na4469_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1567_2), .IN8(1'b0) ); +// C_////Bridge x15y63 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4470_5 ( .OUT(na4470_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1610_1) ); +// C_////Bridge x13y63 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4471_5 ( .OUT(na4471_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1610_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x12y63 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4472_5 ( .OUT(na4472_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1610_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y67 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4473_5 ( .OUT(na4473_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1613_1), .IN8(1'b0) ); +// C_////Bridge x16y65 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4474_5 ( .OUT(na4474_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1614_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x34y65 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4475_5 ( .OUT(na4475_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1771_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x32y66 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4476_5 ( .OUT(na4476_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1773_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x31y65 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4477_5 ( .OUT(na4477_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1773_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y48 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4478_5 ( .OUT(na4478_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1811_1), .IN8(1'b0) ); +// C_////Bridge x30y50 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4479_5 ( .OUT(na4479_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1811_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y58 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4480_5 ( .OUT(na4480_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1864_1), .IN8(1'b0) ); +// C_////Bridge x64y51 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4481_5 ( .OUT(na4481_2), .IN1(na1887_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y53 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4482_5 ( .OUT(na4482_2), .IN1(na1887_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x69y73 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4483_5 ( .OUT(na4483_2), .IN1(1'b0), .IN2(na1986_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y66 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4484_5 ( .OUT(na4484_2), .IN1(1'b0), .IN2(na1986_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4485_5 ( .OUT(na4485_2), .IN1(1'b0), .IN2(na1986_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y72 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4486_5 ( .OUT(na4486_2), .IN1(1'b0), .IN2(na1986_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y71 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4487_5 ( .OUT(na4487_2), .IN1(1'b0), .IN2(na1989_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y69 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4488_5 ( .OUT(na4488_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1990_1) ); +// C_////Bridge x65y67 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4489_5 ( .OUT(na4489_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1990_2) ); +// C_////Bridge x67y67 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4490_5 ( .OUT(na4490_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1991_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y67 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4491_5 ( .OUT(na4491_2), .IN1(1'b0), .IN2(na1993_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y74 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4492_5 ( .OUT(na4492_2), .IN1(1'b0), .IN2(na1993_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y61 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4493_5 ( .OUT(na4493_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1993_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x47y49 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4494_5 ( .OUT(na4494_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1999_1), .IN8(1'b0) ); +// C_////Bridge x49y49 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4495_5 ( .OUT(na4495_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na2000_2) ); +// C_////Bridge x47y51 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4496_5 ( .OUT(na4496_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2002_1), .IN8(1'b0) ); +// C_////Bridge x54y56 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4497_5 ( .OUT(na4497_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2013_2), .IN8(1'b0) ); +// C_////Bridge x56y57 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4498_5 ( .OUT(na4498_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na2015_1) ); +// C_////Bridge x52y56 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4499_5 ( .OUT(na4499_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2017_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y51 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4500_5 ( .OUT(na4500_2), .IN1(na2122_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y55 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4501_5 ( .OUT(na4501_2), .IN1(na2122_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y63 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4502_5 ( .OUT(na4502_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2124_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x66y52 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4503_5 ( .OUT(na4503_2), .IN1(na2222_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y56 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4504_5 ( .OUT(na4504_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2223_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y64 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4505_5 ( .OUT(na4505_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2226_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y61 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4506_5 ( .OUT(na4506_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na2228_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y63 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4507_5 ( .OUT(na4507_2), .IN1(1'b0), .IN2(na2228_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x60y60 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4508_5 ( .OUT(na4508_2), .IN1(1'b0), .IN2(na2228_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x55y58 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4509_5 ( .OUT(na4509_2), .IN1(na2229_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x60y64 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4510_5 ( .OUT(na4510_2), .IN1(na2229_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y62 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4511_5 ( .OUT(na4511_2), .IN1(na2229_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y57 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4512_5 ( .OUT(na4512_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2230_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y46 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4513_5 ( .OUT(na4513_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2236_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y52 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4514_5 ( .OUT(na4514_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2237_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x51y50 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4515_5 ( .OUT(na4515_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2239_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y56 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4516_5 ( .OUT(na4516_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2250_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x46y54 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4517_5 ( .OUT(na4517_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2252_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x46y51 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4518_5 ( .OUT(na4518_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2254_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x70y67 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4519_5 ( .OUT(na4519_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na2350_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y55 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4520_5 ( .OUT(na4520_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2473_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x25y65 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4521_5 ( .OUT(na4521_2), .IN1(1'b0), .IN2(na2474_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x27y53 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4522_5 ( .OUT(na4522_2), .IN1(1'b0), .IN2(na2474_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x28y55 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4523_5 ( .OUT(na4523_2), .IN1(1'b0), .IN2(na2474_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y55 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4524_5 ( .OUT(na4524_2), .IN1(1'b0), .IN2(na2477_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x18y56 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4525_5 ( .OUT(na4525_2), .IN1(1'b0), .IN2(na2477_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y51 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4526_5 ( .OUT(na4526_2), .IN1(1'b0), .IN2(na2478_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y56 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4527_5 ( .OUT(na4527_2), .IN1(1'b0), .IN2(na2478_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y61 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4528_5 ( .OUT(na4528_2), .IN1(1'b0), .IN2(na2478_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y55 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4529_5 ( .OUT(na4529_2), .IN1(1'b0), .IN2(na2478_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y53 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4530_5 ( .OUT(na4530_2), .IN1(1'b0), .IN2(na2478_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y48 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4531_5 ( .OUT(na4531_2), .IN1(na2479_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x20y56 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4532_5 ( .OUT(na4532_2), .IN1(na2479_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x19y50 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4533_5 ( .OUT(na4533_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2481_1), .IN8(1'b0) ); +// C_////Bridge x23y45 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4534_5 ( .OUT(na4534_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2481_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y52 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4535_5 ( .OUT(na4535_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2481_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x22y38 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4536_5 ( .OUT(na4536_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2487_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x22y34 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4537_5 ( .OUT(na4537_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2488_1), .IN8(1'b0) ); +// C_////Bridge x22y36 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4538_5 ( .OUT(na4538_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2490_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y44 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4539_5 ( .OUT(na4539_2), .IN1(na2501_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y45 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4540_5 ( .OUT(na4540_2), .IN1(1'b0), .IN2(na2503_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x17y42 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4541_5 ( .OUT(na4541_2), .IN1(na2505_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y60 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4542_5 ( .OUT(na4542_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2529_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y45 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4543_5 ( .OUT(na4543_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2599_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y84 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4544_5 ( .OUT(na4544_2), .IN1(1'b0), .IN2(na2706_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x48y91 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4545_5 ( .OUT(na4545_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2707_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x45y86 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4546_5 ( .OUT(na4546_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2707_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y83 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4547_5 ( .OUT(na4547_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2707_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y91 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4548_5 ( .OUT(na4548_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2707_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x42y80 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4549_5 ( .OUT(na4549_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2712_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x47y84 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4550_5 ( .OUT(na4550_2), .IN1(na2712_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y78 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4551_5 ( .OUT(na4551_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2713_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y78 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4552_5 ( .OUT(na4552_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2713_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y82 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4553_5 ( .OUT(na4553_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2713_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x44y80 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4554_5 ( .OUT(na4554_2), .IN1(na2714_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y67 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4555_5 ( .OUT(na4555_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na2720_1) ); +// C_////Bridge x37y69 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4556_5 ( .OUT(na4556_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2721_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y69 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4557_5 ( .OUT(na4557_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na2722_2) ); +// C_////Bridge x57y87 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4558_5 ( .OUT(na4558_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na2730_2) ); +// C_////Bridge x33y67 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4559_5 ( .OUT(na4559_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2741_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x39y69 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4560_5 ( .OUT(na4560_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2743_2), .IN8(1'b0) ); +// C_////Bridge x27y73 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4561_5 ( .OUT(na4561_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na2745_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y76 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4562_5 ( .OUT(na4562_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na2846_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y80 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4563_5 ( .OUT(na4563_2), .IN1(na2957_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y84 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4564_5 ( .OUT(na4564_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2958_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y86 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4565_5 ( .OUT(na4565_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2958_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y86 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4566_5 ( .OUT(na4566_2), .IN1(1'b0), .IN2(1'b0), .IN3(na2958_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y84 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4567_5 ( .OUT(na4567_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na2961_1), .IN8(1'b0) ); +// C_////Bridge x60y84 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4568_5 ( .OUT(na4568_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2962_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y84 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4569_5 ( .OUT(na4569_2), .IN1(na2962_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x48y81 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4570_5 ( .OUT(na4570_2), .IN1(na2962_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y86 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4571_5 ( .OUT(na4571_2), .IN1(na2962_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y77 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4572_5 ( .OUT(na4572_2), .IN1(na2963_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x56y83 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4573_5 ( .OUT(na4573_2), .IN1(1'b0), .IN2(na2965_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x16y62 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4574_5 ( .OUT(na4574_2), .IN1(1'b0), .IN2(na2973_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y64 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4575_5 ( .OUT(na4575_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na2973_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x22y60 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4576_5 ( .OUT(na4576_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2974_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y73 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4577_5 ( .OUT(na4577_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na2981_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x21y66 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4578_5 ( .OUT(na4578_2), .IN1(na2988_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x23y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4579_5 ( .OUT(na4579_2), .IN1(1'b0), .IN2(na2990_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y76 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4580_5 ( .OUT(na4580_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na3104_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y76 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4581_5 ( .OUT(na4581_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3230_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x18y63 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4582_5 ( .OUT(na4582_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na3258_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x62y64 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4583_5 ( .OUT(na4583_2), .IN1(na3278_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x41y64 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4584_5 ( .OUT(na4584_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3282_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y49 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4585_5 ( .OUT(na4585_2), .IN1(1'b0), .IN2(na3283_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y42 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4586_5 ( .OUT(na4586_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3288_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x46y47 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4587_5 ( .OUT(na4587_2), .IN1(na3303_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y61 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4588_5 ( .OUT(na4588_2), .IN1(1'b0), .IN2(na3313_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y88 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4589_5 ( .OUT(na4589_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na3329_2) ); +// C_////Bridge x69y81 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4590_5 ( .OUT(na4590_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3348_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x60y74 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4591_5 ( .OUT(na4591_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3416_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y70 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4592_5 ( .OUT(na4592_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3417_1), .IN8(1'b0) ); +// C_////Bridge x58y70 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4593_5 ( .OUT(na4593_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3423_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x54y74 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4594_5 ( .OUT(na4594_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3424_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y52 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4595_5 ( .OUT(na4595_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3426_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y52 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4596_5 ( .OUT(na4596_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3427_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x33y58 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4597_5 ( .OUT(na4597_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3429_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y54 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4598_5 ( .OUT(na4598_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3430_1), .IN8(1'b0) ); +// C_////Bridge x35y60 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4599_5 ( .OUT(na4599_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3439_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y58 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4600_5 ( .OUT(na4600_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3442_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y56 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4601_5 ( .OUT(na4601_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3443_2), .IN8(1'b0) ); +// C_////Bridge x33y56 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4602_5 ( .OUT(na4602_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3444_1), .IN8(1'b0) ); +// C_////Bridge x66y78 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4603_5 ( .OUT(na4603_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3451_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y54 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4604_5 ( .OUT(na4604_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3472_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x40y39 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4605_5 ( .OUT(na4605_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na3525_2) ); +// C_////Bridge x42y41 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4606_5 ( .OUT(na4606_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3526_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x48y41 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4607_5 ( .OUT(na4607_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na3529_2) ); +// C_////Bridge x44y41 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4608_5 ( .OUT(na4608_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3530_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x50y73 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4609_5 ( .OUT(na4609_2), .IN1(na3578_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x49y73 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4610_5 ( .OUT(na4610_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3580_1), .IN8(1'b0) ); +// C_////Bridge x18y51 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4611_5 ( .OUT(na4611_2), .IN1(na3590_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x36y88 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4612_5 ( .OUT(na4612_2), .IN1(1'b0), .IN2(na3701_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x37y85 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4613_5 ( .OUT(na4613_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3708_2), .IN8(1'b0) ); +// C_////Bridge x64y45 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4614_5 ( .OUT(na4614_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3711_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x64y43 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4615_5 ( .OUT(na4615_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na3712_1) ); +// C_////Bridge x58y41 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4616_5 ( .OUT(na4616_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3715_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x60y41 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4617_5 ( .OUT(na4617_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3716_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x57y34 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4618_5 ( .OUT(na4618_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3719_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y34 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4619_5 ( .OUT(na4619_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na3720_1) ); +// C_////Bridge x65y36 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4620_5 ( .OUT(na4620_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3721_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x63y40 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4621_5 ( .OUT(na4621_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3722_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x61y36 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4622_5 ( .OUT(na4622_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na3723_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x59y36 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4623_5 ( .OUT(na4623_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na3724_1) ); +// C_////Bridge x67y36 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4624_5 ( .OUT(na4624_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3725_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y34 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4625_5 ( .OUT(na4625_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3726_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x35y88 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4626_5 ( .OUT(na4626_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na3815_1), .IN8(1'b0) ); +// C_////Bridge x64y92 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4627_5 ( .OUT(na4627_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na3828_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x24y60 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4628_5 ( .OUT(na4628_2), .IN1(1'b0), .IN2(1'b0), .IN3(na3898_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y87 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4629_5 ( .OUT(na4629_2), .IN1(na3931_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x58y92 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4630_5 ( .OUT(na4630_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na3931_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x31y79 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4631_5 ( .OUT(na4631_2), .IN1(1'b0), .IN2(na3943_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x34y73 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a4632_5 ( .OUT(na4632_2), .IN1(1'b0), .IN2(na3943_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0_synth.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0_synth.v new file mode 100644 index 0000000000000000000000000000000000000000..dd2d24eb1ede96ddd94f99df9bf3f1a9b933931f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/corescore_0_synth.v @@ -0,0 +1,45015 @@ +/* Generated by Yosys 0.50+56 (git sha1 176131b50, g++ 11.4.0-1ubuntu1~22.04 -fPIC -O3) */ + +(* keep = 1 *) +(* hdlname = "corescore_gatemate" *) +(* top = 1 *) +(* src = "src/corescore_0/rtl/corescore_gatemate.v:1.1-38.10" *) +module corescore_gatemate(i_clk, i_rstn, o_uart_tx); + wire _0000_; + wire _0001_; + wire _0002_; + wire _0003_; + wire _0004_; + wire _0005_; + wire _0006_; + wire _0007_; + wire _0008_; + wire _0009_; + wire _0010_; + wire _0011_; + wire _0012_; + wire _0013_; + wire _0014_; + wire _0015_; + wire _0016_; + wire _0017_; + wire _0018_; + wire _0019_; + wire _0020_; + wire _0021_; + wire _0022_; + wire _0023_; + wire _0024_; + wire _0025_; + wire _0026_; + wire _0027_; + wire _0028_; + wire _0029_; + wire _0030_; + wire _0031_; + wire _0032_; + wire _0033_; + wire _0034_; + wire _0035_; + wire _0036_; + wire _0037_; + wire _0038_; + wire _0039_; + wire _0040_; + wire _0041_; + wire _0042_; + wire _0043_; + wire _0044_; + wire _0045_; + wire _0046_; + wire _0047_; + wire _0048_; + wire _0049_; + wire _0050_; + wire _0051_; + wire _0052_; + wire _0053_; + wire _0054_; + wire _0055_; + wire _0056_; + wire _0057_; + wire _0058_; + wire _0059_; + wire _0060_; + wire _0061_; + wire _0062_; + wire _0063_; + wire _0064_; + wire _0065_; + wire _0066_; + wire _0067_; + wire _0068_; + wire _0069_; + wire _0070_; + wire _0071_; + wire _0072_; + wire _0073_; + wire _0074_; + wire _0075_; + wire _0076_; + wire _0077_; + wire _0078_; + wire _0079_; + wire _0080_; + wire _0081_; + wire _0082_; + wire _0083_; + wire _0084_; + wire _0085_; + wire _0086_; + wire _0087_; + wire _0088_; + wire _0089_; + wire _0090_; + wire _0091_; + wire _0092_; + wire _0093_; + wire _0094_; + wire _0095_; + wire _0096_; + wire _0097_; + wire _0098_; + wire _0099_; + wire _0100_; + wire _0101_; + wire _0102_; + wire _0103_; + wire _0104_; + wire _0105_; + wire _0106_; + wire _0107_; + wire _0108_; + wire _0109_; + wire _0110_; + wire _0111_; + wire _0112_; + wire _0113_; + wire _0114_; + wire _0115_; + wire _0116_; + wire _0117_; + wire _0118_; + wire _0119_; + wire _0120_; + wire _0121_; + wire _0122_; + wire _0123_; + wire _0124_; + wire _0125_; + wire _0126_; + wire _0127_; + wire _0128_; + wire _0129_; + wire _0130_; + wire _0131_; + wire _0132_; + wire _0133_; + wire _0134_; + wire _0135_; + wire _0136_; + wire _0137_; + wire _0138_; + wire _0139_; + wire _0140_; + wire _0141_; + wire _0142_; + wire _0143_; + wire _0144_; + wire _0145_; + wire _0146_; + wire _0147_; + wire _0148_; + wire _0149_; + wire _0150_; + wire _0151_; + wire _0152_; + wire _0153_; + wire _0154_; + wire _0155_; + wire _0156_; + wire _0157_; + wire _0158_; + wire _0159_; + wire _0160_; + wire _0161_; + wire _0162_; + wire _0163_; + wire _0164_; + wire _0165_; + wire _0166_; + wire _0167_; + wire _0168_; + wire _0169_; + wire _0170_; + wire _0171_; + wire _0172_; + wire _0173_; + wire _0174_; + wire _0175_; + wire _0176_; + wire _0177_; + wire _0178_; + wire _0179_; + wire _0180_; + wire _0181_; + wire _0182_; + wire _0183_; + wire _0184_; + wire _0185_; + wire _0186_; + wire _0187_; + wire _0188_; + wire _0189_; + wire _0190_; + wire _0191_; + wire _0192_; + wire _0193_; + wire _0194_; + wire _0195_; + wire _0196_; + wire _0197_; + wire _0198_; + wire _0199_; + wire _0200_; + wire _0201_; + wire _0202_; + wire _0203_; + wire _0204_; + wire _0205_; + wire _0206_; + wire _0207_; + wire _0208_; + wire _0209_; + wire _0210_; + wire _0211_; + wire _0212_; + wire _0213_; + wire _0214_; + wire _0215_; + wire _0216_; + wire _0217_; + wire _0218_; + wire _0219_; + wire _0220_; + wire _0221_; + wire _0222_; + wire _0223_; + wire _0224_; + wire _0225_; + wire _0226_; + wire _0227_; + wire _0228_; + wire _0229_; + wire _0230_; + wire _0231_; + wire _0232_; + wire _0233_; + wire _0234_; + wire _0235_; + wire _0236_; + wire _0237_; + wire _0238_; + wire _0239_; + wire _0240_; + wire _0241_; + wire _0242_; + wire _0243_; + wire _0244_; + wire _0245_; + wire _0246_; + wire _0247_; + wire _0248_; + wire _0249_; + wire _0250_; + wire _0251_; + wire _0252_; + wire _0253_; + wire _0254_; + wire _0255_; + wire _0256_; + wire _0257_; + wire _0258_; + wire _0259_; + wire _0260_; + wire _0261_; + wire _0262_; + wire _0263_; + wire _0264_; + wire _0265_; + wire _0266_; + wire _0267_; + wire _0268_; + wire _0269_; + wire _0270_; + wire _0271_; + wire _0272_; + wire _0273_; + wire _0274_; + wire _0275_; + wire _0276_; + wire _0277_; + wire _0278_; + wire _0279_; + wire _0280_; + wire _0281_; + wire _0282_; + wire _0283_; + wire _0284_; + wire _0285_; + wire _0286_; + wire _0287_; + wire _0288_; + wire _0289_; + wire _0290_; + wire _0291_; + wire _0292_; + wire _0293_; + wire _0294_; + wire _0295_; + wire _0296_; + wire _0297_; + wire _0298_; + wire _0299_; + wire _0300_; + wire _0301_; + wire _0302_; + wire _0303_; + wire _0304_; + wire _0305_; + wire _0306_; + wire _0307_; + wire _0308_; + wire _0309_; + wire _0310_; + wire _0311_; + wire _0312_; + wire _0313_; + wire _0314_; + wire _0315_; + wire _0316_; + wire _0317_; + wire _0318_; + wire _0319_; + wire _0320_; + wire _0321_; + wire _0322_; + wire _0323_; + wire _0324_; + wire _0325_; + wire _0326_; + wire _0327_; + wire _0328_; + wire _0329_; + wire _0330_; + wire _0331_; + wire _0332_; + wire _0333_; + wire _0334_; + wire _0335_; + wire _0336_; + wire _0337_; + wire _0338_; + wire _0339_; + wire _0340_; + wire _0341_; + wire _0342_; + wire _0343_; + wire _0344_; + wire _0345_; + wire _0346_; + wire _0347_; + wire _0348_; + wire _0349_; + wire _0350_; + wire _0351_; + wire _0352_; + wire _0353_; + wire _0354_; + wire _0355_; + wire _0356_; + wire _0357_; + wire _0358_; + wire _0359_; + wire _0360_; + wire _0361_; + wire _0362_; + wire _0363_; + wire _0364_; + wire _0365_; + wire _0366_; + wire _0367_; + wire _0368_; + wire _0369_; + wire _0370_; + wire _0371_; + wire _0372_; + wire _0373_; + wire _0374_; + wire _0375_; + wire _0376_; + wire _0377_; + wire _0378_; + wire _0379_; + wire _0380_; + wire _0381_; + wire _0382_; + wire _0383_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0384_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0385_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0386_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0387_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0388_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0389_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0390_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0391_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0392_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0393_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0394_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0395_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0396_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0397_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0398_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0399_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0400_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0401_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0402_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0403_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0404_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0405_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0406_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0407_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0408_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0409_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0410_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0411_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0412_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0413_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0414_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0415_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0416_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0417_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0418_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0419_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0420_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0421_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0422_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0423_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0424_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0425_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0426_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0427_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0428_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0429_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0430_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0431_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0432_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0433_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0434_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0435_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0436_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0437_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0438_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0439_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0440_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0441_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7" *) + wire _0442_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0443_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0444_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0445_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0446_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0447_; + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9" *) + wire _0448_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0449_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0450_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0451_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0452_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0453_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0454_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0455_; + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7" *) + wire _0456_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0457_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0458_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0459_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0460_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0461_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0462_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0463_; + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4" *) + wire _0464_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0465_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0466_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0467_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0468_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7" *) + wire _0469_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:22.14-22.33" *) + wire _0470_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7" *) + wire _0471_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:33.11-33.26" *) + wire _0472_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:35.11-35.26" *) + wire _0473_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:31.11-31.39" *) + wire _0474_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0475_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0476_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0477_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0478_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0479_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0480_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0481_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0482_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0483_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0484_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0485_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0486_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0487_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0488_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0489_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0490_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0491_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0492_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0493_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0494_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0495_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0496_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0497_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0498_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0499_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0500_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0501_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0502_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0503_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0504_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0505_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0506_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0507_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0508_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0509_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0510_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0511_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0512_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0513_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0514_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0515_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0516_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0517_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0518_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0519_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0520_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0521_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0522_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0523_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0524_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0525_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0526_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0527_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0528_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0529_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0530_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0531_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0532_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0533_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0534_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0535_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0536_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0537_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0538_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0539_; + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7" *) + wire _0540_; + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7" *) + wire _0541_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0542_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0543_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0544_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0545_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7" *) + wire _0546_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:22.14-22.33" *) + wire _0547_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7" *) + wire _0548_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:33.11-33.26" *) + wire _0549_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:35.11-35.26" *) + wire _0550_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:31.11-31.39" *) + wire _0551_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0552_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0553_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0554_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0555_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0556_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0557_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0558_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0559_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0560_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0561_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0562_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0563_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0564_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0565_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0566_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0567_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0568_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0569_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0570_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0571_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0572_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0573_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0574_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0575_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0576_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0577_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0578_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0579_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0580_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0581_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0582_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0583_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0584_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0585_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0586_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0587_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0588_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0589_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0590_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0591_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0592_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0593_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0594_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0595_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0596_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0597_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0598_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0599_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0600_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0601_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0602_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0603_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0604_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0605_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0606_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0607_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0608_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0609_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0610_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0611_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0612_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0613_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0614_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0615_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0616_; + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7" *) + wire _0617_; + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7" *) + wire _0618_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0619_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0620_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0621_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0622_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7" *) + wire _0623_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:22.14-22.33" *) + wire _0624_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7" *) + wire _0625_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:33.11-33.26" *) + wire _0626_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:35.11-35.26" *) + wire _0627_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:31.11-31.39" *) + wire _0628_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0629_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0630_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0631_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0632_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0633_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0634_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0635_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0636_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0637_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0638_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0639_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0640_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0641_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0642_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0643_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0644_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0645_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0646_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0647_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0648_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0649_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0650_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0651_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0652_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0653_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0654_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0655_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0656_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0657_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0658_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0659_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0660_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0661_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0662_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0663_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0664_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0665_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0666_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0667_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0668_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0669_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0670_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0671_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0672_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0673_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0674_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0675_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0676_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0677_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0678_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0679_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0680_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0681_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0682_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0683_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0684_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0685_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0686_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0687_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0688_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0689_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0690_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0691_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0692_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0693_; + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7" *) + wire _0694_; + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7" *) + wire _0695_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0696_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0697_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0698_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0699_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7" *) + wire _0700_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:22.14-22.33" *) + wire _0701_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7" *) + wire _0702_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:33.11-33.26" *) + wire _0703_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:35.11-35.26" *) + wire _0704_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:31.11-31.39" *) + wire _0705_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0706_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0707_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0708_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0709_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0710_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0711_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0712_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0713_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0714_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0715_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0716_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0717_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0718_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0719_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0720_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0721_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0722_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0723_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0724_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0725_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0726_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0727_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0728_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0729_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0730_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0731_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0732_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0733_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0734_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0735_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0736_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0737_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0738_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0739_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0740_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0741_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0742_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0743_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0744_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0745_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0746_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0747_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0748_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0749_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0750_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0751_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0752_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0753_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0754_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0755_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0756_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0757_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0758_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0759_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0760_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0761_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0762_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0763_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0764_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0765_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0766_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0767_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0768_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0769_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0770_; + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7" *) + wire _0771_; + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7" *) + wire _0772_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0773_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0774_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0775_; + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7" *) + wire _0776_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7" *) + wire _0777_; + (* src = "src/serv_1.0.2/rtl/serv_shift.v:22.14-22.33" *) + wire _0778_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7" *) + wire _0779_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:33.11-33.26" *) + wire _0780_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:35.11-35.26" *) + wire _0781_; + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:31.11-31.39" *) + wire _0782_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0783_; + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7" *) + wire _0784_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0785_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0786_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0787_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0788_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0789_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0790_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0791_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0792_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0793_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0794_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0795_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0796_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0797_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0798_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0799_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0800_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0801_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0802_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0803_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0804_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0805_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0806_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0807_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0808_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0809_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0810_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0811_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0812_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0813_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0814_; + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7" *) + wire _0815_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0816_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0817_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0818_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0819_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0820_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0821_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0822_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0823_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0824_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0825_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0826_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0827_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0828_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0829_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0830_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0831_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0832_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0833_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0834_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0835_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0836_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0837_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0838_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0839_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0840_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0841_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0842_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0843_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0844_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0845_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0846_; + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7" *) + wire _0847_; + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7" *) + wire _0848_; + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7" *) + wire _0849_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.33-123.76|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0850_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.33-123.76|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0851_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.33-123.76|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0852_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.33-123.76|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0853_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.33-132.69|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0854_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.33-132.69|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0855_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.33-132.69|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0856_; + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.33-132.69|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0857_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0858_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0859_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0860_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0861_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0862_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0863_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0864_; + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:98.27-98.46|/usr/local/bin/../share/yosys/techmap.v:106.2-119.5" *) + wire _0865_; + (* force_downto = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.51-123.75|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [3:0] _0866_; + (* force_downto = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.51-123.75|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "3" *) + wire [3:0] _0867_; + (* force_downto = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.51-123.75|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [3:0] _0868_; + (* force_downto = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.51-132.68|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [3:0] _0869_; + (* force_downto = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.51-132.68|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "3" *) + wire [3:0] _0870_; + (* force_downto = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.51-132.68|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [3:0] _0871_; + (* force_downto = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [9:0] _0872_; + (* force_downto = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "9" *) + wire [9:0] _0873_; + (* force_downto = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [9:0] _0874_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0875_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0876_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0877_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:64.44-64.81|/usr/local/bin/../share/yosys/techmap.v:266.22-266.23" *) + wire _0878_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [5:0] _0879_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "5" *) + wire [5:0] _0880_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [5:0] _0881_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0882_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0883_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0884_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.23-270.24" *) + wire [1:0] _0885_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27" *) + wire [1:0] _0886_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0887_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0888_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [2:0] _0889_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0890_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0891_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0892_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0893_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [2:0] _0894_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.23-270.24" *) + wire [1:0] _0895_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27" *) + wire [1:0] _0896_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0897_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0898_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0899_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0900_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0901_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0902_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0903_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0904_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:64.44-64.81|/usr/local/bin/../share/yosys/techmap.v:268.22-268.23" *) + wire _0905_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [5:0] _0906_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "5" *) + wire [5:0] _0907_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [5:0] _0908_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.23-270.24" *) + wire [1:0] _0909_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27" *) + wire [1:0] _0910_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0911_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0912_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0913_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0914_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [2:0] _0915_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.23-270.24" *) + wire [1:0] _0916_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27" *) + wire [1:0] _0917_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0918_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0919_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0920_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0921_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0922_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0923_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:64.44-64.81|/usr/local/bin/../share/yosys/techmap.v:266.22-266.23" *) + wire _0924_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [5:0] _0925_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "5" *) + wire [5:0] _0926_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [5:0] _0927_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [5:0] _0928_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "5" *) + wire [5:0] _0929_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [5:0] _0930_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:64.44-64.81|/usr/local/bin/../share/yosys/techmap.v:268.22-268.23" *) + wire _0931_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0932_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0933_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0934_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0935_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0936_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0937_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [2:0] _0938_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.23-270.24" *) + wire [1:0] _0939_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:61.26-61.37|/usr/local/bin/../share/yosys/techmap.v:270.26-270.27" *) + wire [1:0] _0940_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0941_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0942_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0943_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0944_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0945_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0946_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [2:0] _0947_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "2" *) + wire [2:0] _0948_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [2:0] _0949_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:64.44-64.81|/usr/local/bin/../share/yosys/techmap.v:268.22-268.23" *) + wire _0950_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [5:0] _0951_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "5" *) + wire [5:0] _0952_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [5:0] _0953_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0954_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0955_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0956_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:51.21-51.22" *) + wire [4:0] _0957_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:37.23-37.25" *) + (* unused_bits = "4" *) + wire [4:0] _0958_; + (* force_downto = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:33.26-33.27" *) + wire [4:0] _0959_; + wire _0960_; + wire _0961_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9" *) + wire [9:0] _0962_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9" *) + wire [9:0] _0963_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9" *) + wire [9:0] _0964_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9" *) + wire [9:0] _0965_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9" *) + wire [9:0] _0966_; + wire [7:0] _0967_; + wire [7:0] _0968_; + wire [7:0] _0969_; + wire [7:0] _0970_; + wire [7:0] _0971_; + wire [7:0] _0972_; + wire [7:0] _0973_; + wire [7:0] _0974_; + wire [7:0] _0975_; + wire [7:0] _0976_; + wire _0977_; + wire _0978_; + wire _0979_; + wire _0980_; + wire _0981_; + (* unused_bits = "8 9" *) + wire [9:0] _0982_; + (* unused_bits = "8 9" *) + wire [9:0] _0983_; + (* unused_bits = "8 9" *) + wire [9:0] _0984_; + (* unused_bits = "8 9" *) + wire [9:0] _0985_; + (* unused_bits = "8 9" *) + wire [9:0] _0986_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19" *) + wire [19:0] _0987_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19" *) + wire [19:0] _0988_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19" *) + wire [19:0] _0989_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19" *) + wire [19:0] _0990_; + (* unused_bits = "0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19" *) + wire [19:0] _0991_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire _0992_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire [7:0] _0993_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire _0994_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire [7:0] _0995_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire _0996_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire [7:0] _0997_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire _0998_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire [7:0] _0999_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire _1000_; + (* force_downto = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:0.0-0.0|/usr/local/bin/../share/yosys/techmap.v:137.23-137.24" *) + wire [7:0] _1001_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1002_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1003_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1004_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1005_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1006_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1007_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1008_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1009_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1010_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1011_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1012_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1013_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1014_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1015_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1016_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1017_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1018_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1019_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1020_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1021_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1022_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1023_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1024_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1025_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1026_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1027_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1028_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1029_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1030_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1031_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1032_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1033_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1034_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1035_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1036_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1037_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1038_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1039_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1040_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1041_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1042_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1043_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1044_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1045_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1046_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1047_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1048_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1049_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1050_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1051_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1052_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1053_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1054_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1055_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1056_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1057_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1058_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1059_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1060_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1061_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1062_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1063_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1064_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1065_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1066_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1067_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1068_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1069_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1070_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1071_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1072_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1073_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1074_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1075_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1076_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1077_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1078_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1079_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1080_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1081_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1082_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1083_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1084_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1085_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1086_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1087_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1088_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1089_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1090_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1091_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1092_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1093_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1094_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1095_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1096_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1097_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1098_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1099_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1100_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1101_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1102_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1103_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1104_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1105_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1106_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1107_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1108_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1109_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1110_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1111_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1112_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1113_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1114_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1115_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1116_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1117_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1118_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1119_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1120_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1121_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1122_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1123_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1124_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1125_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1126_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1127_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1128_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1129_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1130_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1131_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1132_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1133_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1134_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1135_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1136_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1137_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1138_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1139_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1140_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1141_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1142_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1143_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1144_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1145_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1146_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1147_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1148_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1149_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1150_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1151_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1152_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1153_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1154_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1155_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1156_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1157_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1158_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1159_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1160_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1161_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1162_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1163_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1164_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1165_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1166_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1167_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1168_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1169_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1170_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1171_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1172_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1173_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1174_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1175_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1176_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1177_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1178_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1179_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1180_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1181_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1182_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1183_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1184_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1185_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1186_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1187_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1188_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1189_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1190_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1191_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1192_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1193_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1194_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1195_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1196_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1197_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1198_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1199_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1200_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1201_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1202_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1203_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1204_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1205_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1206_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1207_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1208_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1209_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1210_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1211_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1212_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1213_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1214_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1215_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1216_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1217_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1218_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1219_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1220_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1221_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1222_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1223_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1224_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1225_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1226_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1227_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1228_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1229_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1230_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1231_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1232_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1233_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1234_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1235_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1236_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1237_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1238_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1239_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1240_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1241_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1242_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1243_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1244_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1245_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1246_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1247_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1248_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1249_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1250_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1251_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1252_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1253_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1254_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1255_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1256_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1257_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1258_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1259_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1260_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1261_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1262_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1263_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1264_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1265_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1266_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1267_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1268_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1269_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1270_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1271_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1272_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1273_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1274_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1275_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1276_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1277_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1278_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1279_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1280_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1281_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1282_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1283_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1284_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1285_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1286_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1287_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1288_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1289_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1290_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1291_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1292_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1293_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1294_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1295_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1296_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1297_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1298_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1299_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1300_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1301_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1302_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1303_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1304_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1305_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1306_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1307_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1308_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1309_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1310_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1311_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1312_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1313_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1314_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1315_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1316_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1317_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1318_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1319_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1320_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1321_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1322_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1323_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1324_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1325_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1326_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1327_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1328_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1329_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1330_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1331_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1332_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1333_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1334_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1335_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1336_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1337_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1338_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1339_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1340_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1341_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1342_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1343_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1344_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1345_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1346_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1347_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1348_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1349_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1350_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1351_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1352_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1353_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1354_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1355_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1356_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1357_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1358_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1359_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1360_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1361_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1362_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1363_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1364_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1365_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1366_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1367_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1368_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1369_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1370_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1371_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1372_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1373_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1374_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [1:0] _1375_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1376_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [2:0] _1377_; + (* force_downto = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:25.20-25.21" *) + wire [3:0] _1378_; + (* src = "src/corescore_0/rtl/corescore_gatemate.v:7.16-7.19" *) + wire clk; + (* hdlname = "clkgen i_clk" *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:4.15-4.20" *) + wire \clkgen.i_clk ; + (* hdlname = "clkgen i_rstn" *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:5.15-5.21" *) + wire \clkgen.i_rstn ; + (* hdlname = "clkgen o_rst_core" *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:7.16-7.26" *) + wire \clkgen.o_rst_core ; + (* hdlname = "clkgen rst_reg1" *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:10.5-10.13" *) + wire \clkgen.rst_reg1 ; + (* hdlname = "clkgen usr_pll_lock_1" *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:14.6-14.20" *) + wire \clkgen.usr_pll_lock_1 ; + (* hdlname = "corescorecore axis_mux arb_inst grant" *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:49.37-49.42" *) + wire [4:0] \corescorecore.axis_mux.arb_inst.grant ; + (* hdlname = "corescorecore axis_mux arb_inst grant_encoded" *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:51.37-51.50" *) + wire [2:0] \corescorecore.axis_mux.arb_inst.grant_encoded ; + (* hdlname = "corescorecore axis_mux arb_inst grant_valid" *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:50.37-50.48" *) + wire \corescorecore.axis_mux.arb_inst.grant_valid ; + (* hdlname = "corescorecore axis_mux arb_inst mask_reg" *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:77.17-77.25" *) + wire [4:0] \corescorecore.axis_mux.arb_inst.mask_reg ; + (* hdlname = "corescorecore axis_mux arb_inst masked_request_index" *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:80.26-80.46" *) + wire [2:0] \corescorecore.axis_mux.arb_inst.masked_request_index ; + (* hdlname = "corescorecore axis_mux arb_inst masked_request_valid" *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:79.6-79.26" *) + wire \corescorecore.axis_mux.arb_inst.masked_request_valid ; + (* hdlname = "corescorecore axis_mux arb_inst priority_encoder_inst output_encoded" *) + (* src = "src/verilog-axis_0-r3/rtl/priority_encoder.v:41.37-41.51" *) + wire [2:0] \corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded ; + (* hdlname = "corescorecore axis_mux current_s_tdata" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:110.23-110.38" *) + wire [7:0] \corescorecore.axis_mux.current_s_tdata ; + (* hdlname = "corescorecore axis_mux m_axis_tdata" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:78.42-78.54" *) + wire [7:0] \corescorecore.axis_mux.m_axis_tdata ; + (* hdlname = "corescorecore axis_mux m_axis_tready" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:81.42-81.55" *) + wire \corescorecore.axis_mux.m_axis_tready ; + (* hdlname = "corescorecore axis_mux m_axis_tready_int_reg" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:100.23-100.44" *) + wire \corescorecore.axis_mux.m_axis_tready_int_reg ; + (* hdlname = "corescorecore axis_mux m_axis_tvalid" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:80.42-80.55" *) + wire \corescorecore.axis_mux.m_axis_tvalid ; + (* hdlname = "corescorecore axis_mux s_axis_tdata" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:66.42-66.54" *) + wire [39:0] \corescorecore.axis_mux.s_axis_tdata ; + (* hdlname = "corescorecore axis_mux store_axis_int_to_temp" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:169.5-169.27" *) + wire \corescorecore.axis_mux.store_axis_int_to_temp ; + (* hdlname = "corescorecore axis_mux temp_m_axis_tdata_reg" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:159.22-159.43" *) + wire [7:0] \corescorecore.axis_mux.temp_m_axis_tdata_reg ; + (* hdlname = "corescorecore axis_mux temp_m_axis_tvalid_reg" *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:161.22-161.44" *) + wire \corescorecore.axis_mux.temp_m_axis_tvalid_reg ; + (* hdlname = "corescorecore core_0 o_tlast" *) + (* src = "src/corescore_0/rtl/base.v:5.22-5.29" *) + wire \corescorecore.core_0.o_tlast ; + (* hdlname = "corescorecore core_0 o_tvalid" *) + (* src = "src/corescore_0/rtl/base.v:6.22-6.30" *) + wire \corescorecore.core_0.o_tvalid ; + (* hdlname = "corescorecore core_0 serving arbiter i_wb_cpu_dbus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:23.23-23.40" *) + wire [31:0] \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr ; + (* hdlname = "corescorecore core_0 serving arbiter i_wb_cpu_dbus_dat" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:24.23-24.40" *) + wire [31:0] \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat ; + (* hdlname = "corescorecore core_0 serving arbiter i_wb_cpu_dbus_sel" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:25.23-25.40" *) + wire [3:0] \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel ; + (* hdlname = "corescorecore core_0 serving arbiter i_wb_cpu_dbus_we" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:26.22-26.38" *) + wire \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ; + (* hdlname = "corescorecore core_0 serving arbiter i_wb_cpu_ibus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:31.23-31.40" *) + wire [31:0] \corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr ; + (* hdlname = "corescorecore core_0 serving arbiter i_wb_mem_ack" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:42.22-42.34" *) + wire \corescorecore.core_0.serving.arbiter.i_wb_mem_ack ; + (* hdlname = "corescorecore core_0 serving arbiter i_wb_mem_rdt" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:41.23-41.35" *) + wire [31:0] \corescorecore.core_0.serving.arbiter.i_wb_mem_rdt ; + (* hdlname = "corescorecore core_0 serving cpu alu add_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:41.16-41.24" *) + wire \corescorecore.core_0.serving.cpu.alu.add_cy_r ; + (* hdlname = "corescorecore core_0 serving cpu alu b_inv_plus_1_cy" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:44.16-44.31" *) + wire \corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy ; + (* hdlname = "corescorecore core_0 serving cpu alu b_inv_plus_1_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:45.16-45.33" *) + wire \corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy_r ; + (* hdlname = "corescorecore core_0 serving cpu alu eq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:68.15-68.19" *) + wire \corescorecore.core_0.serving.cpu.alu.eq_r ; + (* hdlname = "corescorecore core_0 serving cpu alu i_buf" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:12.20-12.25" *) + wire \corescorecore.core_0.serving.cpu.alu.i_buf ; + (* hdlname = "corescorecore core_0 serving cpu alu i_cnt_done" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:14.20-14.30" *) + wire \corescorecore.core_0.serving.cpu.alu.i_cnt_done ; + (* hdlname = "corescorecore core_0 serving cpu alu i_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:6.20-6.24" *) + wire \corescorecore.core_0.serving.cpu.alu.i_en ; + (* hdlname = "corescorecore core_0 serving cpu alu i_init" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:13.20-13.26" *) + wire \corescorecore.core_0.serving.cpu.alu.i_init ; + (* hdlname = "corescorecore core_0 serving cpu alu i_rs1" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:8.20-8.25" *) + wire \corescorecore.core_0.serving.cpu.alu.i_rs1 ; + (* hdlname = "corescorecore core_0 serving cpu alu i_sh_right" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:21.20-21.30" *) + wire \corescorecore.core_0.serving.cpu.alu.i_sh_right ; + (* hdlname = "corescorecore core_0 serving cpu alu i_sh_signed" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:22.20-22.31" *) + wire \corescorecore.core_0.serving.cpu.alu.i_sh_signed ; + (* hdlname = "corescorecore core_0 serving cpu alu i_shamt_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:20.20-20.30" *) + wire \corescorecore.core_0.serving.cpu.alu.i_shamt_en ; + (* hdlname = "corescorecore core_0 serving cpu alu lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:66.15-66.19" *) + wire \corescorecore.core_0.serving.cpu.alu.lt_r ; + (* hdlname = "corescorecore core_0 serving cpu alu op_b" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:47.9-47.13" *) + wire \corescorecore.core_0.serving.cpu.alu.op_b ; + (* hdlname = "corescorecore core_0 serving cpu alu result_lt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:29.16-29.25" *) + wire \corescorecore.core_0.serving.cpu.alu.result_lt ; + (* hdlname = "corescorecore core_0 serving cpu alu result_lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:32.16-32.27" *) + wire \corescorecore.core_0.serving.cpu.alu.result_lt_r ; + (* hdlname = "corescorecore core_0 serving cpu alu shamt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:34.16-34.21" *) + wire [4:0] \corescorecore.core_0.serving.cpu.alu.shamt ; + (* hdlname = "corescorecore core_0 serving cpu alu shamt_msb" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:35.16-35.25" *) + wire \corescorecore.core_0.serving.cpu.alu.shamt_msb ; + (* hdlname = "corescorecore core_0 serving cpu alu shamt_ser" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:37.16-37.25" *) + wire \corescorecore.core_0.serving.cpu.alu.shamt_ser ; + (* hdlname = "corescorecore core_0 serving cpu alu shift cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:15.19-15.22" *) + wire [5:0] \corescorecore.core_0.serving.cpu.alu.shift.cnt ; + (* hdlname = "corescorecore core_0 serving cpu alu shift signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:14.14-14.21" *) + wire \corescorecore.core_0.serving.cpu.alu.shift.signbit ; + (* hdlname = "corescorecore core_0 serving cpu alu shift wrapped" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:16.14-16.21" *) + wire \corescorecore.core_0.serving.cpu.alu.shift.wrapped ; + (* hdlname = "corescorecore core_0 serving cpu bufreg c_r" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:19.16-19.19" *) + wire \corescorecore.core_0.serving.cpu.bufreg.c_r ; + (* hdlname = "corescorecore core_0 serving cpu bufreg data" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:20.22-20.26" *) + wire [31:0] \corescorecore.core_0.serving.cpu.bufreg.data ; + (* hdlname = "corescorecore core_0 serving cpu bufreg o_lsb" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:14.23-14.28" *) + wire [1:0] \corescorecore.core_0.serving.cpu.bufreg.o_lsb ; + (* hdlname = "corescorecore core_0 serving cpu bufreg q" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:18.19-18.20" *) + wire \corescorecore.core_0.serving.cpu.bufreg.q ; + (* hdlname = "corescorecore core_0 serving cpu bufreg_hold" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:101.11-101.22" *) + wire \corescorecore.core_0.serving.cpu.bufreg_hold ; + (* hdlname = "corescorecore core_0 serving cpu csr_imm" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:138.11-138.18" *) + wire \corescorecore.core_0.serving.cpu.csr_imm ; + (* hdlname = "corescorecore core_0 serving cpu ctrl en_pc_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:31.15-31.22" *) + wire \corescorecore.core_0.serving.cpu.ctrl.en_pc_r ; + (* hdlname = "corescorecore core_0 serving cpu ctrl i_jump" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:12.22-12.28" *) + wire \corescorecore.core_0.serving.cpu.ctrl.i_jump ; + (* hdlname = "corescorecore core_0 serving cpu ctrl pc" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:42.15-42.17" *) + wire \corescorecore.core_0.serving.cpu.ctrl.pc ; + (* hdlname = "corescorecore core_0 serving cpu ctrl pc_plus_4_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:35.15-35.29" *) + wire \corescorecore.core_0.serving.cpu.ctrl.pc_plus_4_cy_r ; + (* hdlname = "corescorecore core_0 serving cpu ctrl pc_plus_offset_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:38.15-38.34" *) + wire \corescorecore.core_0.serving.cpu.ctrl.pc_plus_offset_cy_r ; + (* hdlname = "corescorecore core_0 serving cpu decode i_wb_en" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:9.21-9.28" *) + wire \corescorecore.core_0.serving.cpu.decode.i_wb_en ; + (* hdlname = "corescorecore core_0 serving cpu decode imm11_7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:181.15-181.22" *) + wire [4:0] \corescorecore.core_0.serving.cpu.decode.imm11_7 ; + (* hdlname = "corescorecore core_0 serving cpu decode imm19_12_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:177.15-177.26" *) + wire [8:0] \corescorecore.core_0.serving.cpu.decode.imm19_12_20 ; + (* hdlname = "corescorecore core_0 serving cpu decode imm24_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:180.15-180.23" *) + wire [4:0] \corescorecore.core_0.serving.cpu.decode.imm24_20 ; + (* hdlname = "corescorecore core_0 serving cpu decode imm30_25" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:179.15-179.23" *) + wire [5:0] \corescorecore.core_0.serving.cpu.decode.imm30_25 ; + (* hdlname = "corescorecore core_0 serving cpu decode imm7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:178.15-178.19" *) + wire \corescorecore.core_0.serving.cpu.decode.imm7 ; + (* hdlname = "corescorecore core_0 serving cpu decode m3" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:188.9-188.11" *) + wire \corescorecore.core_0.serving.cpu.decode.m3 ; + (* hdlname = "corescorecore core_0 serving cpu decode o_mem_half" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:45.22-45.32" *) + wire \corescorecore.core_0.serving.cpu.decode.o_mem_half ; + (* hdlname = "corescorecore core_0 serving cpu decode o_mem_word" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:44.22-44.32" *) + wire \corescorecore.core_0.serving.cpu.decode.o_mem_word ; + (* hdlname = "corescorecore core_0 serving cpu decode o_rf_rd_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:39.22-39.34" *) + wire [4:0] \corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr ; + (* hdlname = "corescorecore core_0 serving cpu decode o_rf_rs1_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:40.22-40.35" *) + wire [4:0] \corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr ; + (* hdlname = "corescorecore core_0 serving cpu decode o_rf_rs2_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:41.22-41.35" *) + wire [4:0] \corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr ; + (* hdlname = "corescorecore core_0 serving cpu decode opcode" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:64.14-64.20" *) + wire [4:0] \corescorecore.core_0.serving.cpu.decode.opcode ; + (* hdlname = "corescorecore core_0 serving cpu decode signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:175.15-175.22" *) + wire \corescorecore.core_0.serving.cpu.decode.signbit ; + (* hdlname = "corescorecore core_0 serving cpu i_rf_ready" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:36.23-36.33" *) + wire \corescorecore.core_0.serving.cpu.i_rf_ready ; + (* hdlname = "corescorecore core_0 serving cpu mem_bytecnt" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:128.17-128.28" *) + wire [1:0] \corescorecore.core_0.serving.cpu.mem_bytecnt ; + (* hdlname = "corescorecore core_0 serving cpu mem_if dat_cur" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:30.11-30.18" *) + wire \corescorecore.core_0.serving.cpu.mem_if.dat_cur ; + (* hdlname = "corescorecore core_0 serving cpu mem_if dat_valid" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:36.9-36.18" *) + wire \corescorecore.core_0.serving.cpu.mem_if.dat_valid ; + (* hdlname = "corescorecore core_0 serving cpu mem_if signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:22.18-22.25" *) + wire \corescorecore.core_0.serving.cpu.mem_if.signbit ; + (* hdlname = "corescorecore core_0 serving cpu mem_if tmp" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.17-24.20" *) + (* unused_bits = "0 1" *) + wire [2:0] \corescorecore.core_0.serving.cpu.mem_if.tmp ; + (* hdlname = "corescorecore core_0 serving cpu o_wdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:41.24-41.32" *) + wire \corescorecore.core_0.serving.cpu.o_wdata0 ; + (* hdlname = "corescorecore core_0 serving cpu o_wen0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:39.24-39.30" *) + wire \corescorecore.core_0.serving.cpu.o_wen0 ; + (* hdlname = "corescorecore core_0 serving cpu state i_ctrl_misalign" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:33.21-33.36" *) + wire \corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ; + (* hdlname = "corescorecore core_0 serving cpu state o_cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:48.14-48.19" *) + wire [4:2] \corescorecore.core_0.serving.cpu.state.o_cnt ; + (* hdlname = "corescorecore core_0 serving cpu state o_cnt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:49.14-49.21" *) + wire [3:0] \corescorecore.core_0.serving.cpu.state.o_cnt_r ; + (* hdlname = "corescorecore core_0 serving cpu state stage_two_pending" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:72.9-72.26" *) + wire \corescorecore.core_0.serving.cpu.state.stage_two_pending ; + (* hdlname = "corescorecore core_0 serving cpu state stage_two_req" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:46.9-46.22" *) + wire \corescorecore.core_0.serving.cpu.state.stage_two_req ; + (* hdlname = "corescorecore core_0 serving i_wb_ack" *) + (* src = "src/serving_1.0.2/serving/serving.v:33.22-33.30" *) + wire \corescorecore.core_0.serving.i_wb_ack ; + (* hdlname = "corescorecore core_0 serving raddr" *) + (* src = "src/serving_1.0.2/serving/serving.v:76.24-76.29" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_0.serving.raddr ; + (* hdlname = "corescorecore core_0 serving ram bsel" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:55.16-55.20" *) + wire [1:0] \corescorecore.core_0.serving.ram.bsel ; + (* hdlname = "corescorecore core_0 serving ram raddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:51.19-51.24" *) + wire [7:0] \corescorecore.core_0.serving.ram.raddr ; + (* hdlname = "corescorecore core_0 serving ram waddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:49.19-49.24" *) + wire [7:0] \corescorecore.core_0.serving.ram.waddr ; + (* hdlname = "corescorecore core_0 serving ram wb_en" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:41.11-41.16" *) + wire \corescorecore.core_0.serving.ram.wb_en ; + (* hdlname = "corescorecore core_0 serving ram wdata" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:50.17-50.22" *) + wire [7:0] \corescorecore.core_0.serving.ram.wdata ; + (* hdlname = "corescorecore core_0 serving ram we" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:45.12-45.14" *) + wire \corescorecore.core_0.serving.ram.we ; + (* hdlname = "corescorecore core_0 serving rf_ram_if genblk1.wtrig0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:54.11-54.19" *) + wire \corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ; + (* hdlname = "corescorecore core_0 serving rf_ram_if o_waddr" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:25.37-25.44" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_0.serving.rf_ram_if.o_waddr ; + (* hdlname = "corescorecore core_0 serving rf_ram_if rcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:108.17-108.21" *) + wire [4:0] \corescorecore.core_0.serving.rf_ram_if.rcnt ; + (* hdlname = "corescorecore core_0 serving rf_ram_if rdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:120.21-120.27" *) + wire [7:0] \corescorecore.core_0.serving.rf_ram_if.rdata0 ; + (* hdlname = "corescorecore core_0 serving rf_ram_if rdata1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:121.21-121.27" *) + wire [6:0] \corescorecore.core_0.serving.rf_ram_if.rdata1 ; + (* hdlname = "corescorecore core_0 serving rf_ram_if rgnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:31.15-31.19" *) + wire \corescorecore.core_0.serving.rf_ram_if.rgnt ; + (* hdlname = "corescorecore core_0 serving rf_ram_if rreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:128.15-128.21" *) + wire \corescorecore.core_0.serving.rf_ram_if.rreq_r ; + (* hdlname = "corescorecore core_0 serving rf_ram_if rtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:110.12-110.18" *) + wire \corescorecore.core_0.serving.rf_ram_if.rtrig0 ; + (* hdlname = "corescorecore core_0 serving rf_ram_if rtrig1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:111.12-111.18" *) + wire \corescorecore.core_0.serving.rf_ram_if.rtrig1 ; + (* hdlname = "corescorecore core_0 serving rf_ram_if wcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:38.20-38.24" *) + wire [4:0] \corescorecore.core_0.serving.rf_ram_if.wcnt ; + (* hdlname = "corescorecore core_0 serving rf_ram_if wdata0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:42.22-42.30" *) + wire [6:0] \corescorecore.core_0.serving.rf_ram_if.wdata0_r ; + (* hdlname = "corescorecore core_0 serving rf_ram_if wen0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:45.15-45.21" *) + wire \corescorecore.core_0.serving.rf_ram_if.wen0_r ; + (* hdlname = "corescorecore core_0 serving rf_ram_if wgo" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:39.15-39.18" *) + wire \corescorecore.core_0.serving.rf_ram_if.wgo ; + (* hdlname = "corescorecore core_0 serving rf_ram_if wreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:74.15-74.21" *) + wire \corescorecore.core_0.serving.rf_ram_if.wreq_r ; + (* hdlname = "corescorecore core_0 serving rf_ram_if wtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:47.15-47.21" *) + wire \corescorecore.core_0.serving.rf_ram_if.wtrig0 ; + (* hdlname = "corescorecore core_1 o_tlast" *) + (* src = "src/corescore_0/rtl/base.v:5.22-5.29" *) + wire \corescorecore.core_1.o_tlast ; + (* hdlname = "corescorecore core_1 o_tvalid" *) + (* src = "src/corescore_0/rtl/base.v:6.22-6.30" *) + wire \corescorecore.core_1.o_tvalid ; + (* hdlname = "corescorecore core_1 serving arbiter i_wb_cpu_dbus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:23.23-23.40" *) + wire [31:0] \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr ; + (* hdlname = "corescorecore core_1 serving arbiter i_wb_cpu_dbus_dat" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:24.23-24.40" *) + wire [31:0] \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat ; + (* hdlname = "corescorecore core_1 serving arbiter i_wb_cpu_dbus_sel" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:25.23-25.40" *) + wire [3:0] \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel ; + (* hdlname = "corescorecore core_1 serving arbiter i_wb_cpu_dbus_we" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:26.22-26.38" *) + wire \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ; + (* hdlname = "corescorecore core_1 serving arbiter i_wb_cpu_ibus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:31.23-31.40" *) + wire [31:0] \corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr ; + (* hdlname = "corescorecore core_1 serving arbiter i_wb_mem_ack" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:42.22-42.34" *) + wire \corescorecore.core_1.serving.arbiter.i_wb_mem_ack ; + (* hdlname = "corescorecore core_1 serving arbiter i_wb_mem_rdt" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:41.23-41.35" *) + wire [31:0] \corescorecore.core_1.serving.arbiter.i_wb_mem_rdt ; + (* hdlname = "corescorecore core_1 serving cpu alu add_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:41.16-41.24" *) + wire \corescorecore.core_1.serving.cpu.alu.add_cy_r ; + (* hdlname = "corescorecore core_1 serving cpu alu b_inv_plus_1_cy" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:44.16-44.31" *) + wire \corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy ; + (* hdlname = "corescorecore core_1 serving cpu alu b_inv_plus_1_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:45.16-45.33" *) + wire \corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy_r ; + (* hdlname = "corescorecore core_1 serving cpu alu eq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:68.15-68.19" *) + wire \corescorecore.core_1.serving.cpu.alu.eq_r ; + (* hdlname = "corescorecore core_1 serving cpu alu i_buf" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:12.20-12.25" *) + wire \corescorecore.core_1.serving.cpu.alu.i_buf ; + (* hdlname = "corescorecore core_1 serving cpu alu i_cnt_done" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:14.20-14.30" *) + wire \corescorecore.core_1.serving.cpu.alu.i_cnt_done ; + (* hdlname = "corescorecore core_1 serving cpu alu i_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:6.20-6.24" *) + wire \corescorecore.core_1.serving.cpu.alu.i_en ; + (* hdlname = "corescorecore core_1 serving cpu alu i_init" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:13.20-13.26" *) + wire \corescorecore.core_1.serving.cpu.alu.i_init ; + (* hdlname = "corescorecore core_1 serving cpu alu i_rs1" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:8.20-8.25" *) + wire \corescorecore.core_1.serving.cpu.alu.i_rs1 ; + (* hdlname = "corescorecore core_1 serving cpu alu i_sh_right" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:21.20-21.30" *) + wire \corescorecore.core_1.serving.cpu.alu.i_sh_right ; + (* hdlname = "corescorecore core_1 serving cpu alu i_sh_signed" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:22.20-22.31" *) + wire \corescorecore.core_1.serving.cpu.alu.i_sh_signed ; + (* hdlname = "corescorecore core_1 serving cpu alu i_shamt_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:20.20-20.30" *) + wire \corescorecore.core_1.serving.cpu.alu.i_shamt_en ; + (* hdlname = "corescorecore core_1 serving cpu alu lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:66.15-66.19" *) + wire \corescorecore.core_1.serving.cpu.alu.lt_r ; + (* hdlname = "corescorecore core_1 serving cpu alu op_b" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:47.9-47.13" *) + wire \corescorecore.core_1.serving.cpu.alu.op_b ; + (* hdlname = "corescorecore core_1 serving cpu alu result_lt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:29.16-29.25" *) + wire \corescorecore.core_1.serving.cpu.alu.result_lt ; + (* hdlname = "corescorecore core_1 serving cpu alu result_lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:32.16-32.27" *) + wire \corescorecore.core_1.serving.cpu.alu.result_lt_r ; + (* hdlname = "corescorecore core_1 serving cpu alu shamt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:34.16-34.21" *) + wire [4:0] \corescorecore.core_1.serving.cpu.alu.shamt ; + (* hdlname = "corescorecore core_1 serving cpu alu shamt_msb" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:35.16-35.25" *) + wire \corescorecore.core_1.serving.cpu.alu.shamt_msb ; + (* hdlname = "corescorecore core_1 serving cpu alu shamt_ser" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:37.16-37.25" *) + wire \corescorecore.core_1.serving.cpu.alu.shamt_ser ; + (* hdlname = "corescorecore core_1 serving cpu alu shift cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:15.19-15.22" *) + wire [5:0] \corescorecore.core_1.serving.cpu.alu.shift.cnt ; + (* hdlname = "corescorecore core_1 serving cpu alu shift signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:14.14-14.21" *) + wire \corescorecore.core_1.serving.cpu.alu.shift.signbit ; + (* hdlname = "corescorecore core_1 serving cpu alu shift wrapped" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:16.14-16.21" *) + wire \corescorecore.core_1.serving.cpu.alu.shift.wrapped ; + (* hdlname = "corescorecore core_1 serving cpu bufreg c_r" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:19.16-19.19" *) + wire \corescorecore.core_1.serving.cpu.bufreg.c_r ; + (* hdlname = "corescorecore core_1 serving cpu bufreg data" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:20.22-20.26" *) + wire [31:0] \corescorecore.core_1.serving.cpu.bufreg.data ; + (* hdlname = "corescorecore core_1 serving cpu bufreg o_lsb" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:14.23-14.28" *) + wire [1:0] \corescorecore.core_1.serving.cpu.bufreg.o_lsb ; + (* hdlname = "corescorecore core_1 serving cpu bufreg q" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:18.19-18.20" *) + wire \corescorecore.core_1.serving.cpu.bufreg.q ; + (* hdlname = "corescorecore core_1 serving cpu bufreg_hold" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:101.11-101.22" *) + wire \corescorecore.core_1.serving.cpu.bufreg_hold ; + (* hdlname = "corescorecore core_1 serving cpu csr_imm" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:138.11-138.18" *) + wire \corescorecore.core_1.serving.cpu.csr_imm ; + (* hdlname = "corescorecore core_1 serving cpu ctrl en_pc_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:31.15-31.22" *) + wire \corescorecore.core_1.serving.cpu.ctrl.en_pc_r ; + (* hdlname = "corescorecore core_1 serving cpu ctrl i_jump" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:12.22-12.28" *) + wire \corescorecore.core_1.serving.cpu.ctrl.i_jump ; + (* hdlname = "corescorecore core_1 serving cpu ctrl pc" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:42.15-42.17" *) + wire \corescorecore.core_1.serving.cpu.ctrl.pc ; + (* hdlname = "corescorecore core_1 serving cpu ctrl pc_plus_4_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:35.15-35.29" *) + wire \corescorecore.core_1.serving.cpu.ctrl.pc_plus_4_cy_r ; + (* hdlname = "corescorecore core_1 serving cpu ctrl pc_plus_offset_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:38.15-38.34" *) + wire \corescorecore.core_1.serving.cpu.ctrl.pc_plus_offset_cy_r ; + (* hdlname = "corescorecore core_1 serving cpu decode i_wb_en" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:9.21-9.28" *) + wire \corescorecore.core_1.serving.cpu.decode.i_wb_en ; + (* hdlname = "corescorecore core_1 serving cpu decode imm11_7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:181.15-181.22" *) + wire [4:0] \corescorecore.core_1.serving.cpu.decode.imm11_7 ; + (* hdlname = "corescorecore core_1 serving cpu decode imm19_12_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:177.15-177.26" *) + wire [8:0] \corescorecore.core_1.serving.cpu.decode.imm19_12_20 ; + (* hdlname = "corescorecore core_1 serving cpu decode imm24_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:180.15-180.23" *) + wire [4:0] \corescorecore.core_1.serving.cpu.decode.imm24_20 ; + (* hdlname = "corescorecore core_1 serving cpu decode imm30_25" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:179.15-179.23" *) + wire [5:0] \corescorecore.core_1.serving.cpu.decode.imm30_25 ; + (* hdlname = "corescorecore core_1 serving cpu decode imm7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:178.15-178.19" *) + wire \corescorecore.core_1.serving.cpu.decode.imm7 ; + (* hdlname = "corescorecore core_1 serving cpu decode m3" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:188.9-188.11" *) + wire \corescorecore.core_1.serving.cpu.decode.m3 ; + (* hdlname = "corescorecore core_1 serving cpu decode o_mem_half" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:45.22-45.32" *) + wire \corescorecore.core_1.serving.cpu.decode.o_mem_half ; + (* hdlname = "corescorecore core_1 serving cpu decode o_mem_word" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:44.22-44.32" *) + wire \corescorecore.core_1.serving.cpu.decode.o_mem_word ; + (* hdlname = "corescorecore core_1 serving cpu decode o_rf_rd_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:39.22-39.34" *) + wire [4:0] \corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr ; + (* hdlname = "corescorecore core_1 serving cpu decode o_rf_rs1_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:40.22-40.35" *) + wire [4:0] \corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr ; + (* hdlname = "corescorecore core_1 serving cpu decode o_rf_rs2_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:41.22-41.35" *) + wire [4:0] \corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr ; + (* hdlname = "corescorecore core_1 serving cpu decode opcode" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:64.14-64.20" *) + wire [4:0] \corescorecore.core_1.serving.cpu.decode.opcode ; + (* hdlname = "corescorecore core_1 serving cpu decode signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:175.15-175.22" *) + wire \corescorecore.core_1.serving.cpu.decode.signbit ; + (* hdlname = "corescorecore core_1 serving cpu i_rf_ready" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:36.23-36.33" *) + wire \corescorecore.core_1.serving.cpu.i_rf_ready ; + (* hdlname = "corescorecore core_1 serving cpu mem_bytecnt" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:128.17-128.28" *) + wire [1:0] \corescorecore.core_1.serving.cpu.mem_bytecnt ; + (* hdlname = "corescorecore core_1 serving cpu mem_if dat_cur" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:30.11-30.18" *) + wire \corescorecore.core_1.serving.cpu.mem_if.dat_cur ; + (* hdlname = "corescorecore core_1 serving cpu mem_if dat_valid" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:36.9-36.18" *) + wire \corescorecore.core_1.serving.cpu.mem_if.dat_valid ; + (* hdlname = "corescorecore core_1 serving cpu mem_if signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:22.18-22.25" *) + wire \corescorecore.core_1.serving.cpu.mem_if.signbit ; + (* hdlname = "corescorecore core_1 serving cpu mem_if tmp" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.17-24.20" *) + (* unused_bits = "0 1" *) + wire [2:0] \corescorecore.core_1.serving.cpu.mem_if.tmp ; + (* hdlname = "corescorecore core_1 serving cpu o_wdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:41.24-41.32" *) + wire \corescorecore.core_1.serving.cpu.o_wdata0 ; + (* hdlname = "corescorecore core_1 serving cpu o_wen0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:39.24-39.30" *) + wire \corescorecore.core_1.serving.cpu.o_wen0 ; + (* hdlname = "corescorecore core_1 serving cpu state i_ctrl_misalign" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:33.21-33.36" *) + wire \corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ; + (* hdlname = "corescorecore core_1 serving cpu state o_cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:48.14-48.19" *) + wire [4:2] \corescorecore.core_1.serving.cpu.state.o_cnt ; + (* hdlname = "corescorecore core_1 serving cpu state o_cnt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:49.14-49.21" *) + wire [3:0] \corescorecore.core_1.serving.cpu.state.o_cnt_r ; + (* hdlname = "corescorecore core_1 serving cpu state stage_two_pending" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:72.9-72.26" *) + wire \corescorecore.core_1.serving.cpu.state.stage_two_pending ; + (* hdlname = "corescorecore core_1 serving cpu state stage_two_req" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:46.9-46.22" *) + wire \corescorecore.core_1.serving.cpu.state.stage_two_req ; + (* hdlname = "corescorecore core_1 serving i_wb_ack" *) + (* src = "src/serving_1.0.2/serving/serving.v:33.22-33.30" *) + wire \corescorecore.core_1.serving.i_wb_ack ; + (* hdlname = "corescorecore core_1 serving raddr" *) + (* src = "src/serving_1.0.2/serving/serving.v:76.24-76.29" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_1.serving.raddr ; + (* hdlname = "corescorecore core_1 serving ram bsel" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:55.16-55.20" *) + wire [1:0] \corescorecore.core_1.serving.ram.bsel ; + (* hdlname = "corescorecore core_1 serving ram raddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:51.19-51.24" *) + wire [7:0] \corescorecore.core_1.serving.ram.raddr ; + (* hdlname = "corescorecore core_1 serving ram waddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:49.19-49.24" *) + wire [7:0] \corescorecore.core_1.serving.ram.waddr ; + (* hdlname = "corescorecore core_1 serving ram wb_en" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:41.11-41.16" *) + wire \corescorecore.core_1.serving.ram.wb_en ; + (* hdlname = "corescorecore core_1 serving ram wdata" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:50.17-50.22" *) + wire [7:0] \corescorecore.core_1.serving.ram.wdata ; + (* hdlname = "corescorecore core_1 serving ram we" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:45.12-45.14" *) + wire \corescorecore.core_1.serving.ram.we ; + (* hdlname = "corescorecore core_1 serving rf_ram_if genblk1.wtrig0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:54.11-54.19" *) + wire \corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ; + (* hdlname = "corescorecore core_1 serving rf_ram_if o_waddr" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:25.37-25.44" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_1.serving.rf_ram_if.o_waddr ; + (* hdlname = "corescorecore core_1 serving rf_ram_if rcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:108.17-108.21" *) + wire [4:0] \corescorecore.core_1.serving.rf_ram_if.rcnt ; + (* hdlname = "corescorecore core_1 serving rf_ram_if rdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:120.21-120.27" *) + wire [7:0] \corescorecore.core_1.serving.rf_ram_if.rdata0 ; + (* hdlname = "corescorecore core_1 serving rf_ram_if rdata1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:121.21-121.27" *) + wire [6:0] \corescorecore.core_1.serving.rf_ram_if.rdata1 ; + (* hdlname = "corescorecore core_1 serving rf_ram_if rgnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:31.15-31.19" *) + wire \corescorecore.core_1.serving.rf_ram_if.rgnt ; + (* hdlname = "corescorecore core_1 serving rf_ram_if rreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:128.15-128.21" *) + wire \corescorecore.core_1.serving.rf_ram_if.rreq_r ; + (* hdlname = "corescorecore core_1 serving rf_ram_if rtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:110.12-110.18" *) + wire \corescorecore.core_1.serving.rf_ram_if.rtrig0 ; + (* hdlname = "corescorecore core_1 serving rf_ram_if rtrig1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:111.12-111.18" *) + wire \corescorecore.core_1.serving.rf_ram_if.rtrig1 ; + (* hdlname = "corescorecore core_1 serving rf_ram_if wcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:38.20-38.24" *) + wire [4:0] \corescorecore.core_1.serving.rf_ram_if.wcnt ; + (* hdlname = "corescorecore core_1 serving rf_ram_if wdata0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:42.22-42.30" *) + wire [6:0] \corescorecore.core_1.serving.rf_ram_if.wdata0_r ; + (* hdlname = "corescorecore core_1 serving rf_ram_if wen0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:45.15-45.21" *) + wire \corescorecore.core_1.serving.rf_ram_if.wen0_r ; + (* hdlname = "corescorecore core_1 serving rf_ram_if wgo" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:39.15-39.18" *) + wire \corescorecore.core_1.serving.rf_ram_if.wgo ; + (* hdlname = "corescorecore core_1 serving rf_ram_if wreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:74.15-74.21" *) + wire \corescorecore.core_1.serving.rf_ram_if.wreq_r ; + (* hdlname = "corescorecore core_1 serving rf_ram_if wtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:47.15-47.21" *) + wire \corescorecore.core_1.serving.rf_ram_if.wtrig0 ; + (* hdlname = "corescorecore core_2 o_tlast" *) + (* src = "src/corescore_0/rtl/base.v:5.22-5.29" *) + wire \corescorecore.core_2.o_tlast ; + (* hdlname = "corescorecore core_2 o_tvalid" *) + (* src = "src/corescore_0/rtl/base.v:6.22-6.30" *) + wire \corescorecore.core_2.o_tvalid ; + (* hdlname = "corescorecore core_2 serving arbiter i_wb_cpu_dbus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:23.23-23.40" *) + wire [31:0] \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr ; + (* hdlname = "corescorecore core_2 serving arbiter i_wb_cpu_dbus_dat" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:24.23-24.40" *) + wire [31:0] \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat ; + (* hdlname = "corescorecore core_2 serving arbiter i_wb_cpu_dbus_sel" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:25.23-25.40" *) + wire [3:0] \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel ; + (* hdlname = "corescorecore core_2 serving arbiter i_wb_cpu_dbus_we" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:26.22-26.38" *) + wire \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ; + (* hdlname = "corescorecore core_2 serving arbiter i_wb_cpu_ibus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:31.23-31.40" *) + wire [31:0] \corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr ; + (* hdlname = "corescorecore core_2 serving arbiter i_wb_mem_ack" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:42.22-42.34" *) + wire \corescorecore.core_2.serving.arbiter.i_wb_mem_ack ; + (* hdlname = "corescorecore core_2 serving arbiter i_wb_mem_rdt" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:41.23-41.35" *) + wire [31:0] \corescorecore.core_2.serving.arbiter.i_wb_mem_rdt ; + (* hdlname = "corescorecore core_2 serving cpu alu add_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:41.16-41.24" *) + wire \corescorecore.core_2.serving.cpu.alu.add_cy_r ; + (* hdlname = "corescorecore core_2 serving cpu alu b_inv_plus_1_cy" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:44.16-44.31" *) + wire \corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy ; + (* hdlname = "corescorecore core_2 serving cpu alu b_inv_plus_1_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:45.16-45.33" *) + wire \corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy_r ; + (* hdlname = "corescorecore core_2 serving cpu alu eq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:68.15-68.19" *) + wire \corescorecore.core_2.serving.cpu.alu.eq_r ; + (* hdlname = "corescorecore core_2 serving cpu alu i_buf" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:12.20-12.25" *) + wire \corescorecore.core_2.serving.cpu.alu.i_buf ; + (* hdlname = "corescorecore core_2 serving cpu alu i_cnt_done" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:14.20-14.30" *) + wire \corescorecore.core_2.serving.cpu.alu.i_cnt_done ; + (* hdlname = "corescorecore core_2 serving cpu alu i_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:6.20-6.24" *) + wire \corescorecore.core_2.serving.cpu.alu.i_en ; + (* hdlname = "corescorecore core_2 serving cpu alu i_init" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:13.20-13.26" *) + wire \corescorecore.core_2.serving.cpu.alu.i_init ; + (* hdlname = "corescorecore core_2 serving cpu alu i_rs1" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:8.20-8.25" *) + wire \corescorecore.core_2.serving.cpu.alu.i_rs1 ; + (* hdlname = "corescorecore core_2 serving cpu alu i_sh_right" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:21.20-21.30" *) + wire \corescorecore.core_2.serving.cpu.alu.i_sh_right ; + (* hdlname = "corescorecore core_2 serving cpu alu i_sh_signed" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:22.20-22.31" *) + wire \corescorecore.core_2.serving.cpu.alu.i_sh_signed ; + (* hdlname = "corescorecore core_2 serving cpu alu i_shamt_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:20.20-20.30" *) + wire \corescorecore.core_2.serving.cpu.alu.i_shamt_en ; + (* hdlname = "corescorecore core_2 serving cpu alu lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:66.15-66.19" *) + wire \corescorecore.core_2.serving.cpu.alu.lt_r ; + (* hdlname = "corescorecore core_2 serving cpu alu op_b" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:47.9-47.13" *) + wire \corescorecore.core_2.serving.cpu.alu.op_b ; + (* hdlname = "corescorecore core_2 serving cpu alu result_lt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:29.16-29.25" *) + wire \corescorecore.core_2.serving.cpu.alu.result_lt ; + (* hdlname = "corescorecore core_2 serving cpu alu result_lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:32.16-32.27" *) + wire \corescorecore.core_2.serving.cpu.alu.result_lt_r ; + (* hdlname = "corescorecore core_2 serving cpu alu shamt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:34.16-34.21" *) + wire [4:0] \corescorecore.core_2.serving.cpu.alu.shamt ; + (* hdlname = "corescorecore core_2 serving cpu alu shamt_msb" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:35.16-35.25" *) + wire \corescorecore.core_2.serving.cpu.alu.shamt_msb ; + (* hdlname = "corescorecore core_2 serving cpu alu shamt_ser" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:37.16-37.25" *) + wire \corescorecore.core_2.serving.cpu.alu.shamt_ser ; + (* hdlname = "corescorecore core_2 serving cpu alu shift cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:15.19-15.22" *) + wire [5:0] \corescorecore.core_2.serving.cpu.alu.shift.cnt ; + (* hdlname = "corescorecore core_2 serving cpu alu shift signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:14.14-14.21" *) + wire \corescorecore.core_2.serving.cpu.alu.shift.signbit ; + (* hdlname = "corescorecore core_2 serving cpu alu shift wrapped" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:16.14-16.21" *) + wire \corescorecore.core_2.serving.cpu.alu.shift.wrapped ; + (* hdlname = "corescorecore core_2 serving cpu bufreg c_r" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:19.16-19.19" *) + wire \corescorecore.core_2.serving.cpu.bufreg.c_r ; + (* hdlname = "corescorecore core_2 serving cpu bufreg data" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:20.22-20.26" *) + wire [31:0] \corescorecore.core_2.serving.cpu.bufreg.data ; + (* hdlname = "corescorecore core_2 serving cpu bufreg o_lsb" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:14.23-14.28" *) + wire [1:0] \corescorecore.core_2.serving.cpu.bufreg.o_lsb ; + (* hdlname = "corescorecore core_2 serving cpu bufreg q" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:18.19-18.20" *) + wire \corescorecore.core_2.serving.cpu.bufreg.q ; + (* hdlname = "corescorecore core_2 serving cpu bufreg_hold" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:101.11-101.22" *) + wire \corescorecore.core_2.serving.cpu.bufreg_hold ; + (* hdlname = "corescorecore core_2 serving cpu csr_imm" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:138.11-138.18" *) + wire \corescorecore.core_2.serving.cpu.csr_imm ; + (* hdlname = "corescorecore core_2 serving cpu ctrl en_pc_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:31.15-31.22" *) + wire \corescorecore.core_2.serving.cpu.ctrl.en_pc_r ; + (* hdlname = "corescorecore core_2 serving cpu ctrl i_jump" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:12.22-12.28" *) + wire \corescorecore.core_2.serving.cpu.ctrl.i_jump ; + (* hdlname = "corescorecore core_2 serving cpu ctrl pc" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:42.15-42.17" *) + wire \corescorecore.core_2.serving.cpu.ctrl.pc ; + (* hdlname = "corescorecore core_2 serving cpu ctrl pc_plus_4_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:35.15-35.29" *) + wire \corescorecore.core_2.serving.cpu.ctrl.pc_plus_4_cy_r ; + (* hdlname = "corescorecore core_2 serving cpu ctrl pc_plus_offset_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:38.15-38.34" *) + wire \corescorecore.core_2.serving.cpu.ctrl.pc_plus_offset_cy_r ; + (* hdlname = "corescorecore core_2 serving cpu decode i_wb_en" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:9.21-9.28" *) + wire \corescorecore.core_2.serving.cpu.decode.i_wb_en ; + (* hdlname = "corescorecore core_2 serving cpu decode imm11_7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:181.15-181.22" *) + wire [4:0] \corescorecore.core_2.serving.cpu.decode.imm11_7 ; + (* hdlname = "corescorecore core_2 serving cpu decode imm19_12_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:177.15-177.26" *) + wire [8:0] \corescorecore.core_2.serving.cpu.decode.imm19_12_20 ; + (* hdlname = "corescorecore core_2 serving cpu decode imm24_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:180.15-180.23" *) + wire [4:0] \corescorecore.core_2.serving.cpu.decode.imm24_20 ; + (* hdlname = "corescorecore core_2 serving cpu decode imm30_25" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:179.15-179.23" *) + wire [5:0] \corescorecore.core_2.serving.cpu.decode.imm30_25 ; + (* hdlname = "corescorecore core_2 serving cpu decode imm7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:178.15-178.19" *) + wire \corescorecore.core_2.serving.cpu.decode.imm7 ; + (* hdlname = "corescorecore core_2 serving cpu decode m3" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:188.9-188.11" *) + wire \corescorecore.core_2.serving.cpu.decode.m3 ; + (* hdlname = "corescorecore core_2 serving cpu decode o_mem_half" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:45.22-45.32" *) + wire \corescorecore.core_2.serving.cpu.decode.o_mem_half ; + (* hdlname = "corescorecore core_2 serving cpu decode o_mem_word" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:44.22-44.32" *) + wire \corescorecore.core_2.serving.cpu.decode.o_mem_word ; + (* hdlname = "corescorecore core_2 serving cpu decode o_rf_rd_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:39.22-39.34" *) + wire [4:0] \corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr ; + (* hdlname = "corescorecore core_2 serving cpu decode o_rf_rs1_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:40.22-40.35" *) + wire [4:0] \corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr ; + (* hdlname = "corescorecore core_2 serving cpu decode o_rf_rs2_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:41.22-41.35" *) + wire [4:0] \corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr ; + (* hdlname = "corescorecore core_2 serving cpu decode opcode" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:64.14-64.20" *) + wire [4:0] \corescorecore.core_2.serving.cpu.decode.opcode ; + (* hdlname = "corescorecore core_2 serving cpu decode signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:175.15-175.22" *) + wire \corescorecore.core_2.serving.cpu.decode.signbit ; + (* hdlname = "corescorecore core_2 serving cpu i_rf_ready" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:36.23-36.33" *) + wire \corescorecore.core_2.serving.cpu.i_rf_ready ; + (* hdlname = "corescorecore core_2 serving cpu mem_bytecnt" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:128.17-128.28" *) + wire [1:0] \corescorecore.core_2.serving.cpu.mem_bytecnt ; + (* hdlname = "corescorecore core_2 serving cpu mem_if dat_cur" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:30.11-30.18" *) + wire \corescorecore.core_2.serving.cpu.mem_if.dat_cur ; + (* hdlname = "corescorecore core_2 serving cpu mem_if dat_valid" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:36.9-36.18" *) + wire \corescorecore.core_2.serving.cpu.mem_if.dat_valid ; + (* hdlname = "corescorecore core_2 serving cpu mem_if signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:22.18-22.25" *) + wire \corescorecore.core_2.serving.cpu.mem_if.signbit ; + (* hdlname = "corescorecore core_2 serving cpu mem_if tmp" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.17-24.20" *) + (* unused_bits = "0 1" *) + wire [2:0] \corescorecore.core_2.serving.cpu.mem_if.tmp ; + (* hdlname = "corescorecore core_2 serving cpu o_wdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:41.24-41.32" *) + wire \corescorecore.core_2.serving.cpu.o_wdata0 ; + (* hdlname = "corescorecore core_2 serving cpu o_wen0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:39.24-39.30" *) + wire \corescorecore.core_2.serving.cpu.o_wen0 ; + (* hdlname = "corescorecore core_2 serving cpu state i_ctrl_misalign" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:33.21-33.36" *) + wire \corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ; + (* hdlname = "corescorecore core_2 serving cpu state o_cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:48.14-48.19" *) + wire [4:2] \corescorecore.core_2.serving.cpu.state.o_cnt ; + (* hdlname = "corescorecore core_2 serving cpu state o_cnt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:49.14-49.21" *) + wire [3:0] \corescorecore.core_2.serving.cpu.state.o_cnt_r ; + (* hdlname = "corescorecore core_2 serving cpu state stage_two_pending" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:72.9-72.26" *) + wire \corescorecore.core_2.serving.cpu.state.stage_two_pending ; + (* hdlname = "corescorecore core_2 serving cpu state stage_two_req" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:46.9-46.22" *) + wire \corescorecore.core_2.serving.cpu.state.stage_two_req ; + (* hdlname = "corescorecore core_2 serving i_wb_ack" *) + (* src = "src/serving_1.0.2/serving/serving.v:33.22-33.30" *) + wire \corescorecore.core_2.serving.i_wb_ack ; + (* hdlname = "corescorecore core_2 serving raddr" *) + (* src = "src/serving_1.0.2/serving/serving.v:76.24-76.29" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_2.serving.raddr ; + (* hdlname = "corescorecore core_2 serving ram bsel" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:55.16-55.20" *) + wire [1:0] \corescorecore.core_2.serving.ram.bsel ; + (* hdlname = "corescorecore core_2 serving ram raddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:51.19-51.24" *) + wire [7:0] \corescorecore.core_2.serving.ram.raddr ; + (* hdlname = "corescorecore core_2 serving ram waddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:49.19-49.24" *) + wire [7:0] \corescorecore.core_2.serving.ram.waddr ; + (* hdlname = "corescorecore core_2 serving ram wb_en" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:41.11-41.16" *) + wire \corescorecore.core_2.serving.ram.wb_en ; + (* hdlname = "corescorecore core_2 serving ram wdata" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:50.17-50.22" *) + wire [7:0] \corescorecore.core_2.serving.ram.wdata ; + (* hdlname = "corescorecore core_2 serving ram we" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:45.12-45.14" *) + wire \corescorecore.core_2.serving.ram.we ; + (* hdlname = "corescorecore core_2 serving rf_ram_if genblk1.wtrig0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:54.11-54.19" *) + wire \corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ; + (* hdlname = "corescorecore core_2 serving rf_ram_if o_waddr" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:25.37-25.44" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_2.serving.rf_ram_if.o_waddr ; + (* hdlname = "corescorecore core_2 serving rf_ram_if rcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:108.17-108.21" *) + wire [4:0] \corescorecore.core_2.serving.rf_ram_if.rcnt ; + (* hdlname = "corescorecore core_2 serving rf_ram_if rdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:120.21-120.27" *) + wire [7:0] \corescorecore.core_2.serving.rf_ram_if.rdata0 ; + (* hdlname = "corescorecore core_2 serving rf_ram_if rdata1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:121.21-121.27" *) + wire [6:0] \corescorecore.core_2.serving.rf_ram_if.rdata1 ; + (* hdlname = "corescorecore core_2 serving rf_ram_if rgnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:31.15-31.19" *) + wire \corescorecore.core_2.serving.rf_ram_if.rgnt ; + (* hdlname = "corescorecore core_2 serving rf_ram_if rreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:128.15-128.21" *) + wire \corescorecore.core_2.serving.rf_ram_if.rreq_r ; + (* hdlname = "corescorecore core_2 serving rf_ram_if rtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:110.12-110.18" *) + wire \corescorecore.core_2.serving.rf_ram_if.rtrig0 ; + (* hdlname = "corescorecore core_2 serving rf_ram_if rtrig1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:111.12-111.18" *) + wire \corescorecore.core_2.serving.rf_ram_if.rtrig1 ; + (* hdlname = "corescorecore core_2 serving rf_ram_if wcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:38.20-38.24" *) + wire [4:0] \corescorecore.core_2.serving.rf_ram_if.wcnt ; + (* hdlname = "corescorecore core_2 serving rf_ram_if wdata0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:42.22-42.30" *) + wire [6:0] \corescorecore.core_2.serving.rf_ram_if.wdata0_r ; + (* hdlname = "corescorecore core_2 serving rf_ram_if wen0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:45.15-45.21" *) + wire \corescorecore.core_2.serving.rf_ram_if.wen0_r ; + (* hdlname = "corescorecore core_2 serving rf_ram_if wgo" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:39.15-39.18" *) + wire \corescorecore.core_2.serving.rf_ram_if.wgo ; + (* hdlname = "corescorecore core_2 serving rf_ram_if wreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:74.15-74.21" *) + wire \corescorecore.core_2.serving.rf_ram_if.wreq_r ; + (* hdlname = "corescorecore core_2 serving rf_ram_if wtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:47.15-47.21" *) + wire \corescorecore.core_2.serving.rf_ram_if.wtrig0 ; + (* hdlname = "corescorecore core_3 o_tlast" *) + (* src = "src/corescore_0/rtl/base.v:5.22-5.29" *) + wire \corescorecore.core_3.o_tlast ; + (* hdlname = "corescorecore core_3 o_tvalid" *) + (* src = "src/corescore_0/rtl/base.v:6.22-6.30" *) + wire \corescorecore.core_3.o_tvalid ; + (* hdlname = "corescorecore core_3 serving arbiter i_wb_cpu_dbus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:23.23-23.40" *) + wire [31:0] \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr ; + (* hdlname = "corescorecore core_3 serving arbiter i_wb_cpu_dbus_dat" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:24.23-24.40" *) + wire [31:0] \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat ; + (* hdlname = "corescorecore core_3 serving arbiter i_wb_cpu_dbus_sel" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:25.23-25.40" *) + wire [3:0] \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel ; + (* hdlname = "corescorecore core_3 serving arbiter i_wb_cpu_dbus_we" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:26.22-26.38" *) + wire \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ; + (* hdlname = "corescorecore core_3 serving arbiter i_wb_cpu_ibus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:31.23-31.40" *) + wire [31:0] \corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr ; + (* hdlname = "corescorecore core_3 serving arbiter i_wb_mem_ack" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:42.22-42.34" *) + wire \corescorecore.core_3.serving.arbiter.i_wb_mem_ack ; + (* hdlname = "corescorecore core_3 serving arbiter i_wb_mem_rdt" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:41.23-41.35" *) + wire [31:0] \corescorecore.core_3.serving.arbiter.i_wb_mem_rdt ; + (* hdlname = "corescorecore core_3 serving cpu alu add_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:41.16-41.24" *) + wire \corescorecore.core_3.serving.cpu.alu.add_cy_r ; + (* hdlname = "corescorecore core_3 serving cpu alu b_inv_plus_1_cy" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:44.16-44.31" *) + wire \corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy ; + (* hdlname = "corescorecore core_3 serving cpu alu b_inv_plus_1_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:45.16-45.33" *) + wire \corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy_r ; + (* hdlname = "corescorecore core_3 serving cpu alu eq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:68.15-68.19" *) + wire \corescorecore.core_3.serving.cpu.alu.eq_r ; + (* hdlname = "corescorecore core_3 serving cpu alu i_buf" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:12.20-12.25" *) + wire \corescorecore.core_3.serving.cpu.alu.i_buf ; + (* hdlname = "corescorecore core_3 serving cpu alu i_cnt_done" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:14.20-14.30" *) + wire \corescorecore.core_3.serving.cpu.alu.i_cnt_done ; + (* hdlname = "corescorecore core_3 serving cpu alu i_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:6.20-6.24" *) + wire \corescorecore.core_3.serving.cpu.alu.i_en ; + (* hdlname = "corescorecore core_3 serving cpu alu i_init" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:13.20-13.26" *) + wire \corescorecore.core_3.serving.cpu.alu.i_init ; + (* hdlname = "corescorecore core_3 serving cpu alu i_rs1" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:8.20-8.25" *) + wire \corescorecore.core_3.serving.cpu.alu.i_rs1 ; + (* hdlname = "corescorecore core_3 serving cpu alu i_sh_right" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:21.20-21.30" *) + wire \corescorecore.core_3.serving.cpu.alu.i_sh_right ; + (* hdlname = "corescorecore core_3 serving cpu alu i_sh_signed" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:22.20-22.31" *) + wire \corescorecore.core_3.serving.cpu.alu.i_sh_signed ; + (* hdlname = "corescorecore core_3 serving cpu alu i_shamt_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:20.20-20.30" *) + wire \corescorecore.core_3.serving.cpu.alu.i_shamt_en ; + (* hdlname = "corescorecore core_3 serving cpu alu lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:66.15-66.19" *) + wire \corescorecore.core_3.serving.cpu.alu.lt_r ; + (* hdlname = "corescorecore core_3 serving cpu alu op_b" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:47.9-47.13" *) + wire \corescorecore.core_3.serving.cpu.alu.op_b ; + (* hdlname = "corescorecore core_3 serving cpu alu result_lt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:29.16-29.25" *) + wire \corescorecore.core_3.serving.cpu.alu.result_lt ; + (* hdlname = "corescorecore core_3 serving cpu alu result_lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:32.16-32.27" *) + wire \corescorecore.core_3.serving.cpu.alu.result_lt_r ; + (* hdlname = "corescorecore core_3 serving cpu alu shamt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:34.16-34.21" *) + wire [4:0] \corescorecore.core_3.serving.cpu.alu.shamt ; + (* hdlname = "corescorecore core_3 serving cpu alu shamt_msb" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:35.16-35.25" *) + wire \corescorecore.core_3.serving.cpu.alu.shamt_msb ; + (* hdlname = "corescorecore core_3 serving cpu alu shamt_ser" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:37.16-37.25" *) + wire \corescorecore.core_3.serving.cpu.alu.shamt_ser ; + (* hdlname = "corescorecore core_3 serving cpu alu shift cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:15.19-15.22" *) + wire [5:0] \corescorecore.core_3.serving.cpu.alu.shift.cnt ; + (* hdlname = "corescorecore core_3 serving cpu alu shift signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:14.14-14.21" *) + wire \corescorecore.core_3.serving.cpu.alu.shift.signbit ; + (* hdlname = "corescorecore core_3 serving cpu alu shift wrapped" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:16.14-16.21" *) + wire \corescorecore.core_3.serving.cpu.alu.shift.wrapped ; + (* hdlname = "corescorecore core_3 serving cpu bufreg c_r" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:19.16-19.19" *) + wire \corescorecore.core_3.serving.cpu.bufreg.c_r ; + (* hdlname = "corescorecore core_3 serving cpu bufreg data" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:20.22-20.26" *) + wire [31:0] \corescorecore.core_3.serving.cpu.bufreg.data ; + (* hdlname = "corescorecore core_3 serving cpu bufreg o_lsb" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:14.23-14.28" *) + wire [1:0] \corescorecore.core_3.serving.cpu.bufreg.o_lsb ; + (* hdlname = "corescorecore core_3 serving cpu bufreg q" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:18.19-18.20" *) + wire \corescorecore.core_3.serving.cpu.bufreg.q ; + (* hdlname = "corescorecore core_3 serving cpu bufreg_hold" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:101.11-101.22" *) + wire \corescorecore.core_3.serving.cpu.bufreg_hold ; + (* hdlname = "corescorecore core_3 serving cpu csr_imm" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:138.11-138.18" *) + wire \corescorecore.core_3.serving.cpu.csr_imm ; + (* hdlname = "corescorecore core_3 serving cpu ctrl en_pc_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:31.15-31.22" *) + wire \corescorecore.core_3.serving.cpu.ctrl.en_pc_r ; + (* hdlname = "corescorecore core_3 serving cpu ctrl i_jump" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:12.22-12.28" *) + wire \corescorecore.core_3.serving.cpu.ctrl.i_jump ; + (* hdlname = "corescorecore core_3 serving cpu ctrl pc" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:42.15-42.17" *) + wire \corescorecore.core_3.serving.cpu.ctrl.pc ; + (* hdlname = "corescorecore core_3 serving cpu ctrl pc_plus_4_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:35.15-35.29" *) + wire \corescorecore.core_3.serving.cpu.ctrl.pc_plus_4_cy_r ; + (* hdlname = "corescorecore core_3 serving cpu ctrl pc_plus_offset_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:38.15-38.34" *) + wire \corescorecore.core_3.serving.cpu.ctrl.pc_plus_offset_cy_r ; + (* hdlname = "corescorecore core_3 serving cpu decode i_wb_en" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:9.21-9.28" *) + wire \corescorecore.core_3.serving.cpu.decode.i_wb_en ; + (* hdlname = "corescorecore core_3 serving cpu decode imm11_7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:181.15-181.22" *) + wire [4:0] \corescorecore.core_3.serving.cpu.decode.imm11_7 ; + (* hdlname = "corescorecore core_3 serving cpu decode imm19_12_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:177.15-177.26" *) + wire [8:0] \corescorecore.core_3.serving.cpu.decode.imm19_12_20 ; + (* hdlname = "corescorecore core_3 serving cpu decode imm24_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:180.15-180.23" *) + wire [4:0] \corescorecore.core_3.serving.cpu.decode.imm24_20 ; + (* hdlname = "corescorecore core_3 serving cpu decode imm30_25" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:179.15-179.23" *) + wire [5:0] \corescorecore.core_3.serving.cpu.decode.imm30_25 ; + (* hdlname = "corescorecore core_3 serving cpu decode imm7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:178.15-178.19" *) + wire \corescorecore.core_3.serving.cpu.decode.imm7 ; + (* hdlname = "corescorecore core_3 serving cpu decode m3" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:188.9-188.11" *) + wire \corescorecore.core_3.serving.cpu.decode.m3 ; + (* hdlname = "corescorecore core_3 serving cpu decode o_mem_half" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:45.22-45.32" *) + wire \corescorecore.core_3.serving.cpu.decode.o_mem_half ; + (* hdlname = "corescorecore core_3 serving cpu decode o_mem_word" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:44.22-44.32" *) + wire \corescorecore.core_3.serving.cpu.decode.o_mem_word ; + (* hdlname = "corescorecore core_3 serving cpu decode o_rf_rd_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:39.22-39.34" *) + wire [4:0] \corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr ; + (* hdlname = "corescorecore core_3 serving cpu decode o_rf_rs1_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:40.22-40.35" *) + wire [4:0] \corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr ; + (* hdlname = "corescorecore core_3 serving cpu decode o_rf_rs2_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:41.22-41.35" *) + wire [4:0] \corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr ; + (* hdlname = "corescorecore core_3 serving cpu decode opcode" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:64.14-64.20" *) + wire [4:0] \corescorecore.core_3.serving.cpu.decode.opcode ; + (* hdlname = "corescorecore core_3 serving cpu decode signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:175.15-175.22" *) + wire \corescorecore.core_3.serving.cpu.decode.signbit ; + (* hdlname = "corescorecore core_3 serving cpu i_rf_ready" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:36.23-36.33" *) + wire \corescorecore.core_3.serving.cpu.i_rf_ready ; + (* hdlname = "corescorecore core_3 serving cpu mem_bytecnt" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:128.17-128.28" *) + wire [1:0] \corescorecore.core_3.serving.cpu.mem_bytecnt ; + (* hdlname = "corescorecore core_3 serving cpu mem_if dat_cur" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:30.11-30.18" *) + wire \corescorecore.core_3.serving.cpu.mem_if.dat_cur ; + (* hdlname = "corescorecore core_3 serving cpu mem_if dat_valid" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:36.9-36.18" *) + wire \corescorecore.core_3.serving.cpu.mem_if.dat_valid ; + (* hdlname = "corescorecore core_3 serving cpu mem_if signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:22.18-22.25" *) + wire \corescorecore.core_3.serving.cpu.mem_if.signbit ; + (* hdlname = "corescorecore core_3 serving cpu mem_if tmp" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.17-24.20" *) + (* unused_bits = "0 1" *) + wire [2:0] \corescorecore.core_3.serving.cpu.mem_if.tmp ; + (* hdlname = "corescorecore core_3 serving cpu o_wdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:41.24-41.32" *) + wire \corescorecore.core_3.serving.cpu.o_wdata0 ; + (* hdlname = "corescorecore core_3 serving cpu o_wen0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:39.24-39.30" *) + wire \corescorecore.core_3.serving.cpu.o_wen0 ; + (* hdlname = "corescorecore core_3 serving cpu state i_ctrl_misalign" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:33.21-33.36" *) + wire \corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ; + (* hdlname = "corescorecore core_3 serving cpu state o_cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:48.14-48.19" *) + wire [4:2] \corescorecore.core_3.serving.cpu.state.o_cnt ; + (* hdlname = "corescorecore core_3 serving cpu state o_cnt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:49.14-49.21" *) + wire [3:0] \corescorecore.core_3.serving.cpu.state.o_cnt_r ; + (* hdlname = "corescorecore core_3 serving cpu state stage_two_pending" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:72.9-72.26" *) + wire \corescorecore.core_3.serving.cpu.state.stage_two_pending ; + (* hdlname = "corescorecore core_3 serving cpu state stage_two_req" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:46.9-46.22" *) + wire \corescorecore.core_3.serving.cpu.state.stage_two_req ; + (* hdlname = "corescorecore core_3 serving i_wb_ack" *) + (* src = "src/serving_1.0.2/serving/serving.v:33.22-33.30" *) + wire \corescorecore.core_3.serving.i_wb_ack ; + (* hdlname = "corescorecore core_3 serving raddr" *) + (* src = "src/serving_1.0.2/serving/serving.v:76.24-76.29" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_3.serving.raddr ; + (* hdlname = "corescorecore core_3 serving ram bsel" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:55.16-55.20" *) + wire [1:0] \corescorecore.core_3.serving.ram.bsel ; + (* hdlname = "corescorecore core_3 serving ram raddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:51.19-51.24" *) + wire [7:0] \corescorecore.core_3.serving.ram.raddr ; + (* hdlname = "corescorecore core_3 serving ram waddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:49.19-49.24" *) + wire [7:0] \corescorecore.core_3.serving.ram.waddr ; + (* hdlname = "corescorecore core_3 serving ram wb_en" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:41.11-41.16" *) + wire \corescorecore.core_3.serving.ram.wb_en ; + (* hdlname = "corescorecore core_3 serving ram wdata" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:50.17-50.22" *) + wire [7:0] \corescorecore.core_3.serving.ram.wdata ; + (* hdlname = "corescorecore core_3 serving ram we" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:45.12-45.14" *) + wire \corescorecore.core_3.serving.ram.we ; + (* hdlname = "corescorecore core_3 serving rf_ram_if genblk1.wtrig0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:54.11-54.19" *) + wire \corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ; + (* hdlname = "corescorecore core_3 serving rf_ram_if o_waddr" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:25.37-25.44" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_3.serving.rf_ram_if.o_waddr ; + (* hdlname = "corescorecore core_3 serving rf_ram_if rcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:108.17-108.21" *) + wire [4:0] \corescorecore.core_3.serving.rf_ram_if.rcnt ; + (* hdlname = "corescorecore core_3 serving rf_ram_if rdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:120.21-120.27" *) + wire [7:0] \corescorecore.core_3.serving.rf_ram_if.rdata0 ; + (* hdlname = "corescorecore core_3 serving rf_ram_if rdata1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:121.21-121.27" *) + wire [6:0] \corescorecore.core_3.serving.rf_ram_if.rdata1 ; + (* hdlname = "corescorecore core_3 serving rf_ram_if rgnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:31.15-31.19" *) + wire \corescorecore.core_3.serving.rf_ram_if.rgnt ; + (* hdlname = "corescorecore core_3 serving rf_ram_if rreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:128.15-128.21" *) + wire \corescorecore.core_3.serving.rf_ram_if.rreq_r ; + (* hdlname = "corescorecore core_3 serving rf_ram_if rtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:110.12-110.18" *) + wire \corescorecore.core_3.serving.rf_ram_if.rtrig0 ; + (* hdlname = "corescorecore core_3 serving rf_ram_if rtrig1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:111.12-111.18" *) + wire \corescorecore.core_3.serving.rf_ram_if.rtrig1 ; + (* hdlname = "corescorecore core_3 serving rf_ram_if wcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:38.20-38.24" *) + wire [4:0] \corescorecore.core_3.serving.rf_ram_if.wcnt ; + (* hdlname = "corescorecore core_3 serving rf_ram_if wdata0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:42.22-42.30" *) + wire [6:0] \corescorecore.core_3.serving.rf_ram_if.wdata0_r ; + (* hdlname = "corescorecore core_3 serving rf_ram_if wen0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:45.15-45.21" *) + wire \corescorecore.core_3.serving.rf_ram_if.wen0_r ; + (* hdlname = "corescorecore core_3 serving rf_ram_if wgo" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:39.15-39.18" *) + wire \corescorecore.core_3.serving.rf_ram_if.wgo ; + (* hdlname = "corescorecore core_3 serving rf_ram_if wreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:74.15-74.21" *) + wire \corescorecore.core_3.serving.rf_ram_if.wreq_r ; + (* hdlname = "corescorecore core_3 serving rf_ram_if wtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:47.15-47.21" *) + wire \corescorecore.core_3.serving.rf_ram_if.wtrig0 ; + (* hdlname = "corescorecore core_4 o_tlast" *) + (* src = "src/corescore_0/rtl/base.v:5.22-5.29" *) + wire \corescorecore.core_4.o_tlast ; + (* hdlname = "corescorecore core_4 serving arbiter i_wb_cpu_dbus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:23.23-23.40" *) + wire [31:0] \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr ; + (* hdlname = "corescorecore core_4 serving arbiter i_wb_cpu_dbus_dat" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:24.23-24.40" *) + wire [31:0] \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat ; + (* hdlname = "corescorecore core_4 serving arbiter i_wb_cpu_dbus_sel" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:25.23-25.40" *) + wire [3:0] \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel ; + (* hdlname = "corescorecore core_4 serving arbiter i_wb_cpu_dbus_we" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:26.22-26.38" *) + wire \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ; + (* hdlname = "corescorecore core_4 serving arbiter i_wb_cpu_ibus_adr" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:31.23-31.40" *) + wire [31:0] \corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr ; + (* hdlname = "corescorecore core_4 serving arbiter i_wb_mem_ack" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:42.22-42.34" *) + wire \corescorecore.core_4.serving.arbiter.i_wb_mem_ack ; + (* hdlname = "corescorecore core_4 serving arbiter i_wb_mem_rdt" *) + (* src = "src/serving_1.0.2/serving/serving_arbiter.v:41.23-41.35" *) + wire [31:0] \corescorecore.core_4.serving.arbiter.i_wb_mem_rdt ; + (* hdlname = "corescorecore core_4 serving cpu alu add_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:41.16-41.24" *) + wire \corescorecore.core_4.serving.cpu.alu.add_cy_r ; + (* hdlname = "corescorecore core_4 serving cpu alu b_inv_plus_1_cy" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:44.16-44.31" *) + wire \corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy ; + (* hdlname = "corescorecore core_4 serving cpu alu b_inv_plus_1_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:45.16-45.33" *) + wire \corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy_r ; + (* hdlname = "corescorecore core_4 serving cpu alu eq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:68.15-68.19" *) + wire \corescorecore.core_4.serving.cpu.alu.eq_r ; + (* hdlname = "corescorecore core_4 serving cpu alu i_buf" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:12.20-12.25" *) + wire \corescorecore.core_4.serving.cpu.alu.i_buf ; + (* hdlname = "corescorecore core_4 serving cpu alu i_cnt_done" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:14.20-14.30" *) + wire \corescorecore.core_4.serving.cpu.alu.i_cnt_done ; + (* hdlname = "corescorecore core_4 serving cpu alu i_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:6.20-6.24" *) + wire \corescorecore.core_4.serving.cpu.alu.i_en ; + (* hdlname = "corescorecore core_4 serving cpu alu i_init" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:13.20-13.26" *) + wire \corescorecore.core_4.serving.cpu.alu.i_init ; + (* hdlname = "corescorecore core_4 serving cpu alu i_rs1" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:8.20-8.25" *) + wire \corescorecore.core_4.serving.cpu.alu.i_rs1 ; + (* hdlname = "corescorecore core_4 serving cpu alu i_sh_right" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:21.20-21.30" *) + wire \corescorecore.core_4.serving.cpu.alu.i_sh_right ; + (* hdlname = "corescorecore core_4 serving cpu alu i_sh_signed" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:22.20-22.31" *) + wire \corescorecore.core_4.serving.cpu.alu.i_sh_signed ; + (* hdlname = "corescorecore core_4 serving cpu alu i_shamt_en" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:20.20-20.30" *) + wire \corescorecore.core_4.serving.cpu.alu.i_shamt_en ; + (* hdlname = "corescorecore core_4 serving cpu alu lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:66.15-66.19" *) + wire \corescorecore.core_4.serving.cpu.alu.lt_r ; + (* hdlname = "corescorecore core_4 serving cpu alu op_b" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:47.9-47.13" *) + wire \corescorecore.core_4.serving.cpu.alu.op_b ; + (* hdlname = "corescorecore core_4 serving cpu alu result_lt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:29.16-29.25" *) + wire \corescorecore.core_4.serving.cpu.alu.result_lt ; + (* hdlname = "corescorecore core_4 serving cpu alu result_lt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:32.16-32.27" *) + wire \corescorecore.core_4.serving.cpu.alu.result_lt_r ; + (* hdlname = "corescorecore core_4 serving cpu alu shamt" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:34.16-34.21" *) + wire [4:0] \corescorecore.core_4.serving.cpu.alu.shamt ; + (* hdlname = "corescorecore core_4 serving cpu alu shamt_msb" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:35.16-35.25" *) + wire \corescorecore.core_4.serving.cpu.alu.shamt_msb ; + (* hdlname = "corescorecore core_4 serving cpu alu shamt_ser" *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:37.16-37.25" *) + wire \corescorecore.core_4.serving.cpu.alu.shamt_ser ; + (* hdlname = "corescorecore core_4 serving cpu alu shift cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:15.19-15.22" *) + wire [5:0] \corescorecore.core_4.serving.cpu.alu.shift.cnt ; + (* hdlname = "corescorecore core_4 serving cpu alu shift signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:14.14-14.21" *) + wire \corescorecore.core_4.serving.cpu.alu.shift.signbit ; + (* hdlname = "corescorecore core_4 serving cpu alu shift wrapped" *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:16.14-16.21" *) + wire \corescorecore.core_4.serving.cpu.alu.shift.wrapped ; + (* hdlname = "corescorecore core_4 serving cpu bufreg c_r" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:19.16-19.19" *) + wire \corescorecore.core_4.serving.cpu.bufreg.c_r ; + (* hdlname = "corescorecore core_4 serving cpu bufreg data" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:20.22-20.26" *) + wire [31:0] \corescorecore.core_4.serving.cpu.bufreg.data ; + (* hdlname = "corescorecore core_4 serving cpu bufreg o_lsb" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:14.23-14.28" *) + wire [1:0] \corescorecore.core_4.serving.cpu.bufreg.o_lsb ; + (* hdlname = "corescorecore core_4 serving cpu bufreg q" *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:18.19-18.20" *) + wire \corescorecore.core_4.serving.cpu.bufreg.q ; + (* hdlname = "corescorecore core_4 serving cpu bufreg_hold" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:101.11-101.22" *) + wire \corescorecore.core_4.serving.cpu.bufreg_hold ; + (* hdlname = "corescorecore core_4 serving cpu csr_imm" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:138.11-138.18" *) + wire \corescorecore.core_4.serving.cpu.csr_imm ; + (* hdlname = "corescorecore core_4 serving cpu ctrl en_pc_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:31.15-31.22" *) + wire \corescorecore.core_4.serving.cpu.ctrl.en_pc_r ; + (* hdlname = "corescorecore core_4 serving cpu ctrl i_jump" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:12.22-12.28" *) + wire \corescorecore.core_4.serving.cpu.ctrl.i_jump ; + (* hdlname = "corescorecore core_4 serving cpu ctrl pc" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:42.15-42.17" *) + wire \corescorecore.core_4.serving.cpu.ctrl.pc ; + (* hdlname = "corescorecore core_4 serving cpu ctrl pc_plus_4_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:35.15-35.29" *) + wire \corescorecore.core_4.serving.cpu.ctrl.pc_plus_4_cy_r ; + (* hdlname = "corescorecore core_4 serving cpu ctrl pc_plus_offset_cy_r" *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:38.15-38.34" *) + wire \corescorecore.core_4.serving.cpu.ctrl.pc_plus_offset_cy_r ; + (* hdlname = "corescorecore core_4 serving cpu decode i_wb_en" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:9.21-9.28" *) + wire \corescorecore.core_4.serving.cpu.decode.i_wb_en ; + (* hdlname = "corescorecore core_4 serving cpu decode imm11_7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:181.15-181.22" *) + wire [4:0] \corescorecore.core_4.serving.cpu.decode.imm11_7 ; + (* hdlname = "corescorecore core_4 serving cpu decode imm19_12_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:177.15-177.26" *) + wire [8:0] \corescorecore.core_4.serving.cpu.decode.imm19_12_20 ; + (* hdlname = "corescorecore core_4 serving cpu decode imm24_20" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:180.15-180.23" *) + wire [4:0] \corescorecore.core_4.serving.cpu.decode.imm24_20 ; + (* hdlname = "corescorecore core_4 serving cpu decode imm30_25" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:179.15-179.23" *) + wire [5:0] \corescorecore.core_4.serving.cpu.decode.imm30_25 ; + (* hdlname = "corescorecore core_4 serving cpu decode imm7" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:178.15-178.19" *) + wire \corescorecore.core_4.serving.cpu.decode.imm7 ; + (* hdlname = "corescorecore core_4 serving cpu decode m3" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:188.9-188.11" *) + wire \corescorecore.core_4.serving.cpu.decode.m3 ; + (* hdlname = "corescorecore core_4 serving cpu decode o_mem_half" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:45.22-45.32" *) + wire \corescorecore.core_4.serving.cpu.decode.o_mem_half ; + (* hdlname = "corescorecore core_4 serving cpu decode o_mem_word" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:44.22-44.32" *) + wire \corescorecore.core_4.serving.cpu.decode.o_mem_word ; + (* hdlname = "corescorecore core_4 serving cpu decode o_rf_rd_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:39.22-39.34" *) + wire [4:0] \corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr ; + (* hdlname = "corescorecore core_4 serving cpu decode o_rf_rs1_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:40.22-40.35" *) + wire [4:0] \corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr ; + (* hdlname = "corescorecore core_4 serving cpu decode o_rf_rs2_addr" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:41.22-41.35" *) + wire [4:0] \corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr ; + (* hdlname = "corescorecore core_4 serving cpu decode opcode" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:64.14-64.20" *) + wire [4:0] \corescorecore.core_4.serving.cpu.decode.opcode ; + (* hdlname = "corescorecore core_4 serving cpu decode signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:175.15-175.22" *) + wire \corescorecore.core_4.serving.cpu.decode.signbit ; + (* hdlname = "corescorecore core_4 serving cpu i_rf_ready" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:36.23-36.33" *) + wire \corescorecore.core_4.serving.cpu.i_rf_ready ; + (* hdlname = "corescorecore core_4 serving cpu mem_bytecnt" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:128.17-128.28" *) + wire [1:0] \corescorecore.core_4.serving.cpu.mem_bytecnt ; + (* hdlname = "corescorecore core_4 serving cpu mem_if dat_cur" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:30.11-30.18" *) + wire \corescorecore.core_4.serving.cpu.mem_if.dat_cur ; + (* hdlname = "corescorecore core_4 serving cpu mem_if dat_valid" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:36.9-36.18" *) + wire \corescorecore.core_4.serving.cpu.mem_if.dat_valid ; + (* hdlname = "corescorecore core_4 serving cpu mem_if signbit" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:22.18-22.25" *) + wire \corescorecore.core_4.serving.cpu.mem_if.signbit ; + (* hdlname = "corescorecore core_4 serving cpu mem_if tmp" *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.17-24.20" *) + (* unused_bits = "0 1" *) + wire [2:0] \corescorecore.core_4.serving.cpu.mem_if.tmp ; + (* hdlname = "corescorecore core_4 serving cpu o_wdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:41.24-41.32" *) + wire \corescorecore.core_4.serving.cpu.o_wdata0 ; + (* hdlname = "corescorecore core_4 serving cpu o_wen0" *) + (* src = "src/serv_1.0.2/rtl/serv_top.v:39.24-39.30" *) + wire \corescorecore.core_4.serving.cpu.o_wen0 ; + (* hdlname = "corescorecore core_4 serving cpu state i_ctrl_misalign" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:33.21-33.36" *) + wire \corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ; + (* hdlname = "corescorecore core_4 serving cpu state o_cnt" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:48.14-48.19" *) + wire [4:2] \corescorecore.core_4.serving.cpu.state.o_cnt ; + (* hdlname = "corescorecore core_4 serving cpu state o_cnt_r" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:49.14-49.21" *) + wire [3:0] \corescorecore.core_4.serving.cpu.state.o_cnt_r ; + (* hdlname = "corescorecore core_4 serving cpu state stage_two_pending" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:72.9-72.26" *) + wire \corescorecore.core_4.serving.cpu.state.stage_two_pending ; + (* hdlname = "corescorecore core_4 serving cpu state stage_two_req" *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:46.9-46.22" *) + wire \corescorecore.core_4.serving.cpu.state.stage_two_req ; + (* hdlname = "corescorecore core_4 serving i_wb_ack" *) + (* src = "src/serving_1.0.2/serving/serving.v:33.22-33.30" *) + wire \corescorecore.core_4.serving.i_wb_ack ; + (* hdlname = "corescorecore core_4 serving raddr" *) + (* src = "src/serving_1.0.2/serving/serving.v:76.24-76.29" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_4.serving.raddr ; + (* hdlname = "corescorecore core_4 serving ram bsel" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:55.16-55.20" *) + wire [1:0] \corescorecore.core_4.serving.ram.bsel ; + (* hdlname = "corescorecore core_4 serving ram raddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:51.19-51.24" *) + wire [7:0] \corescorecore.core_4.serving.ram.raddr ; + (* hdlname = "corescorecore core_4 serving ram waddr" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:49.19-49.24" *) + wire [7:0] \corescorecore.core_4.serving.ram.waddr ; + (* hdlname = "corescorecore core_4 serving ram wb_en" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:41.11-41.16" *) + wire \corescorecore.core_4.serving.ram.wb_en ; + (* hdlname = "corescorecore core_4 serving ram wdata" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:50.17-50.22" *) + wire [7:0] \corescorecore.core_4.serving.ram.wdata ; + (* hdlname = "corescorecore core_4 serving ram we" *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:45.12-45.14" *) + wire \corescorecore.core_4.serving.ram.we ; + (* hdlname = "corescorecore core_4 serving rf_ram_if genblk1.wtrig0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:54.11-54.19" *) + wire \corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ; + (* hdlname = "corescorecore core_4 serving rf_ram_if o_waddr" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:25.37-25.44" *) + (* unused_bits = "2 3 4 5 6" *) + wire [6:0] \corescorecore.core_4.serving.rf_ram_if.o_waddr ; + (* hdlname = "corescorecore core_4 serving rf_ram_if rcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:108.17-108.21" *) + wire [4:0] \corescorecore.core_4.serving.rf_ram_if.rcnt ; + (* hdlname = "corescorecore core_4 serving rf_ram_if rdata0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:120.21-120.27" *) + wire [7:0] \corescorecore.core_4.serving.rf_ram_if.rdata0 ; + (* hdlname = "corescorecore core_4 serving rf_ram_if rdata1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:121.21-121.27" *) + wire [6:0] \corescorecore.core_4.serving.rf_ram_if.rdata1 ; + (* hdlname = "corescorecore core_4 serving rf_ram_if rgnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:31.15-31.19" *) + wire \corescorecore.core_4.serving.rf_ram_if.rgnt ; + (* hdlname = "corescorecore core_4 serving rf_ram_if rreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:128.15-128.21" *) + wire \corescorecore.core_4.serving.rf_ram_if.rreq_r ; + (* hdlname = "corescorecore core_4 serving rf_ram_if rtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:110.12-110.18" *) + wire \corescorecore.core_4.serving.rf_ram_if.rtrig0 ; + (* hdlname = "corescorecore core_4 serving rf_ram_if rtrig1" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:111.12-111.18" *) + wire \corescorecore.core_4.serving.rf_ram_if.rtrig1 ; + (* hdlname = "corescorecore core_4 serving rf_ram_if wcnt" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:38.20-38.24" *) + wire [4:0] \corescorecore.core_4.serving.rf_ram_if.wcnt ; + (* hdlname = "corescorecore core_4 serving rf_ram_if wdata0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:42.22-42.30" *) + wire [6:0] \corescorecore.core_4.serving.rf_ram_if.wdata0_r ; + (* hdlname = "corescorecore core_4 serving rf_ram_if wen0_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:45.15-45.21" *) + wire \corescorecore.core_4.serving.rf_ram_if.wen0_r ; + (* hdlname = "corescorecore core_4 serving rf_ram_if wgo" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:39.15-39.18" *) + wire \corescorecore.core_4.serving.rf_ram_if.wgo ; + (* hdlname = "corescorecore core_4 serving rf_ram_if wreq_r" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:74.15-74.21" *) + wire \corescorecore.core_4.serving.rf_ram_if.wreq_r ; + (* hdlname = "corescorecore core_4 serving rf_ram_if wtrig0" *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:47.15-47.21" *) + wire \corescorecore.core_4.serving.rf_ram_if.wtrig0 ; + (* hdlname = "emitter cnt" *) + (* src = "src/corescore_0/rtl/emitter_uart.v:22.18-22.21" *) + wire [9:0] \emitter.cnt ; + (* hdlname = "emitter data" *) + (* src = "src/corescore_0/rtl/emitter_uart.v:24.15-24.19" *) + wire [9:0] \emitter.data ; + (* hdlname = "emitter o_uart_tx" *) + (* src = "src/corescore_0/rtl/emitter_uart.v:16.22-16.31" *) + wire \emitter.o_uart_tx ; + (* src = "src/corescore_0/rtl/corescore_gatemate.v:3.10-3.15" *) + input i_clk; + wire i_clk; + (* src = "src/corescore_0/rtl/corescore_gatemate.v:4.10-4.16" *) + input i_rstn; + wire i_rstn; + (* src = "src/corescore_0/rtl/corescore_gatemate.v:5.16-5.25" *) + output o_uart_tx; + wire o_uart_tx; + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _1379_ ( + .I0(_1112_[0]), + .I1(\corescorecore.axis_mux.arb_inst.masked_request_index [2]), + .O(\corescorecore.axis_mux.arb_inst.masked_request_valid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _1380_ ( + .I0(_1049_[0]), + .I1(_1049_[1]), + .I2(_1049_[2]), + .I3(_1049_[3]), + .O(\corescorecore.axis_mux.arb_inst.masked_request_index [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1381_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [3]), + .I1(\corescorecore.axis_mux.arb_inst.mask_reg [3]), + .I2(\corescorecore.core_3.o_tvalid ), + .O(_1049_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1382_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_en ), + .I1(_1048_[1]), + .I2(_1048_[2]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .O(\corescorecore.core_3.o_tvalid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1383_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_3.serving.cpu.state.stage_two_pending ), + .O(_1048_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1384_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_3.serving.i_wb_ack ), + .O(_1048_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1385_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [0]), + .I1(\corescorecore.axis_mux.arb_inst.mask_reg [0]), + .I2(\corescorecore.core_0.o_tvalid ), + .O(_1049_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1386_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_en ), + .I1(_1046_[1]), + .I2(_1018_[3]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .O(\corescorecore.core_0.o_tvalid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1387_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_0.serving.cpu.state.stage_two_pending ), + .O(_1018_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1388_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_0.serving.i_wb_ack ), + .O(_1046_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1389_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [1]), + .I1(\corescorecore.axis_mux.arb_inst.mask_reg [1]), + .I2(\corescorecore.core_1.o_tvalid ), + .O(_1049_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1390_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_en ), + .I1(_1045_[1]), + .I2(_1024_[1]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .O(\corescorecore.core_1.o_tvalid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1391_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_1.serving.cpu.state.stage_two_pending ), + .O(_1024_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1392_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_1.serving.i_wb_ack ), + .O(_1045_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1393_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [2]), + .I1(\corescorecore.axis_mux.arb_inst.mask_reg [2]), + .I2(\corescorecore.core_2.o_tvalid ), + .O(_1049_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1394_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_en ), + .I1(_1047_[1]), + .I2(_1047_[2]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .O(\corescorecore.core_2.o_tvalid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1395_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_2.serving.cpu.state.stage_two_pending ), + .O(_1047_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1396_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_2.serving.i_wb_ack ), + .O(_1047_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1397_ ( + .I0(_1061_[2]), + .I1(\corescorecore.axis_mux.arb_inst.mask_reg [4]), + .O(_1112_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1398_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [4]), + .I1(_1059_[0]), + .O(_1061_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1399_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_en ), + .I1(_1058_[1]), + .I2(_1058_[2]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_1059_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1400_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_4.serving.cpu.state.stage_two_pending ), + .O(_1058_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1401_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_4.serving.i_wb_ack ), + .O(_1058_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1402_ ( + .I0(_0871_[3]), + .I1(_0868_[3]), + .I2(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .O(_0000_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1f) + ) _1403_ ( + .I0(_1112_[0]), + .I1(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [2]), + .I2(\corescorecore.axis_mux.arb_inst.masked_request_index [2]), + .O(_1113_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1404_ ( + .I0(_1061_[0]), + .I1(_1061_[1]), + .I2(_1061_[3]), + .O(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1405_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [3]), + .I1(\corescorecore.core_3.o_tvalid ), + .O(_1061_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1406_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [2]), + .I1(\corescorecore.core_2.o_tvalid ), + .O(_1061_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb0bb) + ) _1407_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [1]), + .I1(\corescorecore.core_1.o_tvalid ), + .I2(\corescorecore.axis_mux.arb_inst.grant [0]), + .I3(\corescorecore.core_0.o_tvalid ), + .O(_1061_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1408_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0014_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1409_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_1081_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1410_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0092_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1411_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_1089_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1412_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0368_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1413_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0084_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1414_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0073_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1415_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0074_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1416_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0889_[2]), + .O(_0055_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1417_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0369_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1418_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0370_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1419_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0371_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1420_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0372_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1421_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0373_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1422_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0366_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1423_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0367_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1424_ ( + .I0(\corescorecore.core_4.serving.cpu.ctrl.pc ), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0361_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1425_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0362_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1426_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0363_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1427_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0364_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1428_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_4.serving.cpu.state.stage_two_pending ), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0359_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1429_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0075_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1430_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0076_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1431_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0085_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1432_ ( + .I0(_1082_[0]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_ack ), + .O(\corescorecore.core_4.serving.cpu.decode.i_wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1433_ ( + .I0(_1081_[0]), + .I1(\corescorecore.core_4.serving.cpu.ctrl.en_pc_r ), + .O(_1082_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfff4) + ) _1434_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_ack ), + .I1(\corescorecore.core_4.serving.cpu.ctrl.en_pc_r ), + .I2(_1081_[0]), + .I3(\clkgen.o_rst_core ), + .O(_0360_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1435_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt_r [1]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt_r [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0356_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1436_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt_r [1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0357_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1437_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0015_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1438_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0016_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1439_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0017_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1440_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0018_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1441_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0019_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1442_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0020_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1443_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0021_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1444_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0023_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1445_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0024_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1446_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0025_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1447_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0026_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1448_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0027_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1449_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0028_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1450_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0029_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1451_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0030_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1452_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(_0930_[0]), + .O(_0032_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1453_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(_0930_[1]), + .O(_0033_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1454_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(_0930_[2]), + .O(_0034_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1455_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(_0930_[3]), + .O(_0035_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1456_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(_0930_[4]), + .O(_0036_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1457_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(_0930_[5]), + .O(_0037_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1458_ ( + .I0(\clkgen.o_rst_core ), + .I1(_1268_[1]), + .I2(_1048_[1]), + .I3(_1192_[0]), + .O(_0038_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1459_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_en ), + .I1(_1048_[2]), + .O(_1192_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1460_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I1(_1055_[2]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .O(_1268_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _1461_ ( + .I0(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .I1(\corescorecore.axis_mux.arb_inst.grant_valid ), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .O(_1055_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1462_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0039_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1463_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_4.serving.rf_ram_if.rreq_r ), + .O(_0041_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1464_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .I1(_0884_[0]), + .O(_0042_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1465_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .I1(_0884_[1]), + .O(_0043_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1466_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .I1(_0884_[2]), + .O(_0044_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1467_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .I1(_0884_[4]), + .O(_0046_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf2ff) + ) _1468_ ( + .I0(_1253_[1]), + .I1(_1255_[1]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rgnt ), + .I3(_1255_[3]), + .O(\corescorecore.core_4.serving.cpu.i_rf_ready ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0d) + ) _1469_ ( + .I0(\corescorecore.core_4.serving.i_wb_ack ), + .I1(_1199_[1]), + .I2(_1254_[2]), + .O(_1255_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1470_ ( + .I0(_1082_[0]), + .I1(_1199_[1]), + .I2(\corescorecore.core_4.serving.arbiter.i_wb_mem_ack ), + .O(_1254_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1471_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .O(_1199_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1472_ ( + .I0(_1195_[0]), + .I1(_1195_[1]), + .O(_1196_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1473_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .O(_1195_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1474_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .O(_1195_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb00b) + ) _1475_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.shift.cnt [3]), + .I1(\corescorecore.core_4.serving.cpu.alu.shamt [3]), + .I2(\corescorecore.core_4.serving.cpu.alu.shift.cnt [2]), + .I3(\corescorecore.core_4.serving.cpu.alu.shamt [2]), + .O(_1238_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfb0f) + ) _1476_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I1(_1239_[1]), + .I2(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .O(_1240_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1477_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .O(_1239_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _1478_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .O(_1253_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1479_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_4.serving.cpu.i_rf_ready ), + .I2(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .O(_0353_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1480_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .I1(_0884_[3]), + .O(_0045_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfcfa) + ) _1481_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt_r [0]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt_r [3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0355_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1482_ ( + .I0(_0877_[0]), + .I1(\corescorecore.core_4.serving.rf_ram_if.wcnt [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .O(_0047_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0eee) + ) _1483_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.wreq_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .I2(_1284_[2]), + .I3(\corescorecore.core_4.serving.rf_ram_if.o_waddr [1]), + .O(_0052_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _1484_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_4.serving.rf_ram_if.wcnt [1]), + .I2(\corescorecore.core_4.serving.rf_ram_if.wcnt [2]), + .I3(\corescorecore.core_4.serving.rf_ram_if.o_waddr [0]), + .O(_1284_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1485_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.wcnt [1]), + .I1(_0877_[1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .O(_0048_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1486_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.o_waddr [1]), + .I1(_0877_[4]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .O(_0051_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1487_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.wcnt [2]), + .I1(_0877_[2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .O(_0049_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1488_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt_r [0]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0137_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1489_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0087_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1490_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0086_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1491_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0138_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1492_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt_r [3]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0139_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _1493_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(_1256_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .I3(_1256_[3]), + .O(_0352_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1494_ ( + .I0(\corescorecore.core_4.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_4.serving.cpu.i_rf_ready ), + .O(_1256_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1495_ ( + .I0(_1196_[1]), + .I1(_1253_[1]), + .I2(_1240_[0]), + .O(_1256_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1496_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0088_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1497_ ( + .I0(\corescorecore.core_2.serving.cpu.ctrl.pc ), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0142_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1498_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_1095_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1499_ ( + .I0(_1096_[0]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_ack ), + .O(\corescorecore.core_2.serving.cpu.decode.i_wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1500_ ( + .I0(_1095_[0]), + .I1(\corescorecore.core_2.serving.cpu.ctrl.en_pc_r ), + .O(_1096_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfff4) + ) _1501_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_ack ), + .I1(\corescorecore.core_2.serving.cpu.ctrl.en_pc_r ), + .I2(_1095_[0]), + .I3(\clkgen.o_rst_core ), + .O(_0141_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1502_ ( + .I0(\corescorecore.core_2.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0140_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1503_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0143_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1504_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0144_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1505_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0089_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1506_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0090_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1507_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0091_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1508_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0147_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1509_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0148_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1510_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0149_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1511_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0150_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1512_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0152_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1513_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0153_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1514_ ( + .I0(\corescorecore.axis_mux.arb_inst.mask_reg [3]), + .I1(_1261_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1063_[3]), + .O(_0349_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1515_ ( + .I0(_1062_[0]), + .I1(_1062_[1]), + .O(_1063_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1516_ ( + .I0(_1061_[0]), + .I1(_1061_[1]), + .I2(_1061_[2]), + .I3(_1061_[3]), + .O(_1062_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1000) + ) _1517_ ( + .I0(_1060_[0]), + .I1(_1060_[1]), + .I2(_1060_[2]), + .I3(_1060_[3]), + .O(_1062_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7f00) + ) _1518_ ( + .I0(\corescorecore.core_1.o_tvalid ), + .I1(_1057_[1]), + .I2(_1057_[2]), + .I3(\corescorecore.axis_mux.arb_inst.grant_valid ), + .O(_1060_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1519_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .I2(_1055_[2]), + .O(_1057_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1520_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [1]), + .I1(\corescorecore.core_1.o_tlast ), + .O(_1057_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _1521_ ( + .I0(\corescorecore.core_2.o_tvalid ), + .I1(_1053_[1]), + .I2(\corescorecore.axis_mux.arb_inst.grant [2]), + .I3(\corescorecore.core_2.o_tlast ), + .O(_1060_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1522_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I1(_1052_[1]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .O(_1053_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1523_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .I1(\corescorecore.axis_mux.arb_inst.grant_valid ), + .I2(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .O(_1052_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _1524_ ( + .I0(_1059_[0]), + .I1(_1059_[1]), + .I2(\corescorecore.axis_mux.arb_inst.grant [4]), + .I3(\corescorecore.core_4.o_tlast ), + .O(_1060_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1525_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .I1(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I2(_1052_[1]), + .O(_1059_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0777) + ) _1526_ ( + .I0(\corescorecore.core_0.o_tvalid ), + .I1(_1056_[1]), + .I2(\corescorecore.core_3.o_tvalid ), + .I3(_1056_[3]), + .O(_1060_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1527_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I1(_1055_[1]), + .I2(_1055_[2]), + .I3(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .O(_1056_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1528_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [3]), + .I1(\corescorecore.core_3.o_tlast ), + .O(_1055_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1000) + ) _1529_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .I2(_1052_[1]), + .I3(_1054_[3]), + .O(_1056_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1530_ ( + .I0(\corescorecore.core_0.o_tlast ), + .I1(\corescorecore.axis_mux.arb_inst.grant [0]), + .O(_1054_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1531_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0154_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1532_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0155_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h07) + ) _1533_ ( + .I0(_0871_[0]), + .I1(_0871_[1]), + .I2(_0871_[2]), + .O(_0855_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h07) + ) _1534_ ( + .I0(_0868_[0]), + .I1(_0868_[1]), + .I2(_0868_[2]), + .O(_0851_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1535_ ( + .I0(\corescorecore.axis_mux.arb_inst.mask_reg [2]), + .I1(_1252_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1063_[3]), + .O(_0348_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1536_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0157_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1537_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0158_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1538_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0159_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1539_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0160_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1540_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0069_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1541_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0163_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1542_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0164_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1543_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0166_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1544_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0165_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1545_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0167_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1546_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0170_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1547_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0169_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1548_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0171_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1549_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0172_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1550_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(_0927_[0]), + .O(_0174_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1551_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(_0927_[1]), + .O(_0175_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _1552_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I1(_1260_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0173_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _1553_ ( + .I0(_1259_[0]), + .I1(_1259_[1]), + .I2(\corescorecore.core_2.serving.cpu.ctrl.i_jump ), + .O(_1260_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _1554_ ( + .I0(_1258_[0]), + .I1(_1223_[0]), + .I2(\corescorecore.core_2.serving.cpu.ctrl.en_pc_r ), + .O(_1259_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _1555_ ( + .I0(_1223_[1]), + .I1(\corescorecore.core_2.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .O(_1258_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _1556_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .I2(_1222_[2]), + .I3(\corescorecore.core_2.serving.cpu.ctrl.pc ), + .O(_1223_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3e) + ) _1557_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [1]), + .O(_1222_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _1558_ ( + .I0(_1177_[1]), + .I1(_1177_[0]), + .I2(_1221_[2]), + .I3(_1221_[3]), + .O(_1223_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1559_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm11_7 [0]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .I3(_1176_[3]), + .O(_1177_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1560_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_1176_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1561_ ( + .I0(_1220_[3]), + .I1(\corescorecore.core_2.serving.cpu.alu.i_buf ), + .O(_1221_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1562_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .O(_1220_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf800) + ) _1563_ ( + .I0(\corescorecore.core_2.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .I2(\corescorecore.core_2.serving.cpu.mem_bytecnt [1]), + .I3(_1220_[3]), + .O(_1221_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1564_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_2.serving.cpu.decode.signbit ), + .O(_1177_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _1565_ ( + .I0(_1257_[0]), + .I1(\corescorecore.core_2.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_2.serving.cpu.ctrl.pc_plus_4_cy_r ), + .O(_1259_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1566_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [2]), + .I2(_1214_[2]), + .O(_1257_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1567_ ( + .I0(\corescorecore.core_2.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_2.serving.cpu.mem_bytecnt [1]), + .O(_1214_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1568_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(_0927_[2]), + .O(_0176_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1569_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(_0927_[3]), + .O(_0177_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1570_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(_0927_[4]), + .O(_0178_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1571_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(_0927_[5]), + .O(_0179_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7f00) + ) _1572_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .I3(_1212_[3]), + .O(\corescorecore.core_2.serving.ram.wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1573_ ( + .I0(_1211_[0]), + .I1(_1096_[0]), + .I2(\corescorecore.core_2.serving.arbiter.i_wb_mem_ack ), + .O(_1212_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1574_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I3(_1047_[2]), + .O(_1211_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1575_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_2.serving.rf_ram_if.wcnt [1]), + .I2(\corescorecore.core_2.serving.rf_ram_if.wcnt [2]), + .O(\corescorecore.core_2.serving.rf_ram_if.wtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaff) + ) _1576_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(_1096_[0]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.raddr [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1577_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .I1(_0943_[0]), + .O(_0184_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1578_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_2.serving.rf_ram_if.rreq_r ), + .O(_0183_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1579_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .I1(_0943_[1]), + .O(_0185_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1580_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0182_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1581_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rcnt [1]), + .I1(\corescorecore.core_2.serving.rf_ram_if.rcnt [2]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rcnt [0]), + .O(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1582_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .I1(_0943_[2]), + .O(_0186_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1583_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31]), + .I1(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_0181_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1584_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .I1(_0943_[3]), + .O(_0187_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1585_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .I1(_0943_[4]), + .O(_0188_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1586_ ( + .I0(_0946_[0]), + .I1(\corescorecore.core_2.serving.rf_ram_if.wcnt [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .O(_0189_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1587_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.wcnt [1]), + .I1(_0946_[1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .O(_0190_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1588_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.wcnt [2]), + .I1(_0946_[2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .O(_0191_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1589_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.o_waddr [0]), + .I1(_0946_[3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .O(_0192_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0eee) + ) _1590_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wreq_r ), + .I2(_1269_[2]), + .I3(\corescorecore.core_2.serving.rf_ram_if.o_waddr [0]), + .O(_0194_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _1591_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_2.serving.rf_ram_if.wcnt [1]), + .I2(\corescorecore.core_2.serving.rf_ram_if.wcnt [2]), + .I3(\corescorecore.core_2.serving.rf_ram_if.o_waddr [1]), + .O(_1269_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1592_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0938_[0]), + .O(_0196_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1593_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0938_[1]), + .O(_0197_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1594_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0938_[2]), + .O(_0198_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1595_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .O(_0199_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1596_ ( + .I0(_1007_[0]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_ack ), + .O(\corescorecore.core_1.serving.cpu.decode.i_wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1597_ ( + .I0(_1006_[0]), + .I1(\corescorecore.core_1.serving.cpu.ctrl.en_pc_r ), + .O(_1007_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1598_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_1006_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1599_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt_r [1]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0062_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf2ff) + ) _1600_ ( + .I0(_1135_[0]), + .I1(_1009_[2]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rgnt ), + .I3(_1171_[3]), + .O(\corescorecore.core_1.serving.cpu.i_rf_ready ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h001f) + ) _1601_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I2(\corescorecore.core_1.serving.i_wb_ack ), + .I3(_1008_[3]), + .O(_1009_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1602_ ( + .I0(_1007_[0]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_mem_ack ), + .O(_1008_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1603_ ( + .I0(_1120_[3]), + .I1(_1137_[3]), + .O(_1169_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1604_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .O(_1120_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1605_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .O(_1137_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _1606_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.shift.cnt [1]), + .I1(\corescorecore.core_1.serving.cpu.alu.shamt [1]), + .I2(\corescorecore.core_1.serving.cpu.alu.shift.cnt [2]), + .I3(\corescorecore.core_1.serving.cpu.alu.shamt [2]), + .O(_1168_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfb0f) + ) _1607_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I1(_1127_[1]), + .I2(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .O(_1170_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1608_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .O(_1127_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _1609_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .O(_1135_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1610_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_1.serving.cpu.i_rf_ready ), + .I2(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .O(_0201_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1611_ ( + .I0(_0871_[0]), + .I1(_1126_[1]), + .O(_0854_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1612_ ( + .I0(_0871_[1]), + .I1(_0871_[2]), + .O(_1126_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1613_ ( + .I0(_0868_[0]), + .I1(_1128_[1]), + .O(_0850_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1614_ ( + .I0(_0868_[1]), + .I1(_0868_[2]), + .O(_1128_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1615_ ( + .I0(\corescorecore.axis_mux.arb_inst.mask_reg [0]), + .I1(_1264_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1063_[3]), + .O(_0346_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1616_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt_r [1]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0204_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfcfa) + ) _1617_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt_r [0]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0203_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1618_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0205_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1619_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt_r [3]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0206_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1620_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0093_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1621_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0094_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1622_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0095_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1623_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0096_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1624_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt_r [3]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt_r [2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0358_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _1625_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I1(_1373_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0097_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _1626_ ( + .I0(_1270_[0]), + .I1(_1270_[1]), + .I2(\corescorecore.core_3.serving.cpu.ctrl.i_jump ), + .O(_1373_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _1627_ ( + .I0(_1125_[0]), + .I1(_1125_[1]), + .I2(\corescorecore.core_3.serving.cpu.ctrl.en_pc_r ), + .O(_1270_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _1628_ ( + .I0(_1124_[0]), + .I1(\corescorecore.core_3.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .O(_1125_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _1629_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .I2(_1123_[2]), + .I3(\corescorecore.core_3.serving.cpu.ctrl.pc ), + .O(_1124_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3e) + ) _1630_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [1]), + .O(_1123_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _1631_ ( + .I0(_1122_[0]), + .I1(_1122_[1]), + .I2(_1122_[2]), + .I3(_1122_[3]), + .O(_1125_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1632_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm11_7 [0]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .I3(_1121_[3]), + .O(_1122_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1633_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_1121_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1634_ ( + .I0(_1116_[3]), + .I1(\corescorecore.core_3.serving.cpu.alu.i_buf ), + .O(_1122_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1635_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .O(_1116_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf800) + ) _1636_ ( + .I0(\corescorecore.core_3.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .I2(\corescorecore.core_3.serving.cpu.mem_bytecnt [1]), + .I3(_1116_[3]), + .O(_1122_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1637_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_3.serving.cpu.decode.signbit ), + .O(_1122_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _1638_ ( + .I0(_1198_[0]), + .I1(\corescorecore.core_3.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_3.serving.cpu.ctrl.pc_plus_4_cy_r ), + .O(_1270_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1639_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [2]), + .I2(_1129_[2]), + .O(_1198_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1640_ ( + .I0(\corescorecore.core_3.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_3.serving.cpu.mem_bytecnt [1]), + .O(_1129_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1641_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(_0953_[0]), + .O(_0098_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1642_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(_0953_[1]), + .O(_0099_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1643_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(_0953_[2]), + .O(_0100_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1644_ ( + .I0(\clkgen.o_rst_core ), + .I1(_1053_[1]), + .I2(_1271_[2]), + .O(_0104_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1645_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_en ), + .I1(_1047_[1]), + .I2(_1047_[2]), + .O(_1271_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1646_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(_0953_[5]), + .O(_0103_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1647_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0105_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1648_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(_0953_[4]), + .O(_0102_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1649_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(_0953_[3]), + .O(_0101_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1650_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0106_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1651_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rcnt [1]), + .I1(\corescorecore.core_3.serving.rf_ram_if.rcnt [2]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rcnt [0]), + .O(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1652_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .I1(_0959_[2]), + .O(_0110_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1653_ ( + .I0(_1090_[0]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_ack ), + .O(\corescorecore.core_3.serving.cpu.decode.i_wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1654_ ( + .I0(_1089_[0]), + .I1(\corescorecore.core_3.serving.cpu.ctrl.en_pc_r ), + .O(_1090_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1655_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .I1(_0959_[1]), + .O(_0109_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1656_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .I1(_0959_[3]), + .O(_0111_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1657_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .I1(_0959_[0]), + .O(_0108_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1658_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .I1(_0959_[4]), + .O(_0112_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1659_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_3.serving.rf_ram_if.rreq_r ), + .O(_0107_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1660_ ( + .I0(_0956_[0]), + .I1(\corescorecore.core_3.serving.rf_ram_if.wcnt [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .O(_0113_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1661_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.wcnt [2]), + .I1(_0956_[2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .O(_0115_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1662_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.o_waddr [1]), + .I1(_0956_[4]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .O(_0117_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1663_ ( + .I0(_1114_[0]), + .I1(\clkgen.o_rst_core ), + .O(_0345_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7077) + ) _1664_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I2(_1113_[2]), + .I3(_1063_[3]), + .O(_1114_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1665_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\emitter.cnt [9]), + .I2(_0874_[3]), + .O(_0122_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1666_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\emitter.cnt [9]), + .I2(_0874_[1]), + .O(_0120_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hfe) + ) _1667_ ( + .I0(_0874_[4]), + .I1(\corescorecore.axis_mux.m_axis_tready ), + .I2(\emitter.cnt [9]), + .O(_0123_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1668_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\emitter.cnt [9]), + .I2(_0874_[5]), + .O(_0124_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hfe) + ) _1669_ ( + .I0(_0874_[0]), + .I1(\corescorecore.axis_mux.m_axis_tready ), + .I2(\emitter.cnt [9]), + .O(_0119_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1670_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\emitter.cnt [9]), + .I2(_0874_[6]), + .O(_0125_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1671_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\emitter.cnt [9]), + .I2(_0874_[7]), + .O(_0126_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hfe) + ) _1672_ ( + .I0(_0874_[8]), + .I1(\corescorecore.axis_mux.m_axis_tready ), + .I2(\emitter.cnt [9]), + .O(_0127_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1673_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0949_[0]), + .O(_0129_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1674_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0949_[1]), + .O(_0130_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1675_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0949_[2]), + .O(_0131_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1676_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .O(_0132_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _1677_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(_1105_[1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .I3(_1105_[3]), + .O(_0133_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1678_ ( + .I0(\corescorecore.core_2.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_2.serving.cpu.i_rf_ready ), + .O(_1105_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h001f) + ) _1679_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I2(\corescorecore.core_2.serving.i_wb_ack ), + .I3(_1097_[3]), + .O(_1104_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1680_ ( + .I0(_1096_[0]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_mem_ack ), + .O(_1097_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1681_ ( + .I0(_1101_[0]), + .I1(_1101_[1]), + .O(_1103_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1682_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .O(_1101_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1683_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .O(_1101_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0d) + ) _1684_ ( + .I0(\corescorecore.core_2.serving.cpu.state.stage_two_req ), + .I1(_1100_[1]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rgnt ), + .O(_1104_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfb0f) + ) _1685_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I1(_1099_[1]), + .I2(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .O(_1100_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1686_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .O(_1099_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _1687_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .O(_1104_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1688_ ( + .I0(_1103_[2]), + .I1(_1104_[0]), + .I2(_1100_[1]), + .O(_1105_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1689_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0077_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1690_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0078_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1691_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0079_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1692_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0080_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1693_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0072_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1694_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0083_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _1695_ ( + .I0(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [2]), + .I1(_1061_[3]), + .I2(_1062_[0]), + .O(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _1696_ ( + .I0(_1115_[2]), + .I1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .O(\corescorecore.axis_mux.arb_inst.masked_request_index [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _1697_ ( + .I0(\corescorecore.axis_mux.arb_inst.masked_request_index [2]), + .I1(_1049_[1]), + .I2(_1049_[2]), + .O(_1115_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f8) + ) _1698_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .I2(_1272_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0344_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf400) + ) _1699_ ( + .I0(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .I1(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [1]), + .I2(_1115_[2]), + .I3(_1063_[3]), + .O(_1272_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1700_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0067_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1701_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0068_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1702_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0070_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1703_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0071_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfff4) + ) _1704_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_ack ), + .I1(\corescorecore.core_3.serving.cpu.ctrl.en_pc_r ), + .I2(_1089_[0]), + .I3(\clkgen.o_rst_core ), + .O(_0065_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1705_ ( + .I0(\corescorecore.core_3.serving.cpu.ctrl.pc ), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0066_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1706_ ( + .I0(\corescorecore.axis_mux.arb_inst.mask_reg [1]), + .I1(_1286_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1063_[3]), + .O(_0347_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfcfa) + ) _1707_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt_r [0]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0060_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1708_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt_r [0]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0061_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1709_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt_r [3]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0063_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1710_ ( + .I0(\corescorecore.core_3.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0064_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _1711_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(_1285_[1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .I3(_1285_[3]), + .O(_0057_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1712_ ( + .I0(\corescorecore.core_3.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_3.serving.cpu.i_rf_ready ), + .O(_1285_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf2ff) + ) _1713_ ( + .I0(_1092_[0]), + .I1(_1092_[1]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rgnt ), + .I3(_1092_[3]), + .O(\corescorecore.core_3.serving.cpu.i_rf_ready ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0d) + ) _1714_ ( + .I0(\corescorecore.core_3.serving.i_wb_ack ), + .I1(_1090_[1]), + .I2(_1091_[2]), + .O(_1092_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1715_ ( + .I0(_1090_[0]), + .I1(_1090_[1]), + .I2(\corescorecore.core_3.serving.arbiter.i_wb_mem_ack ), + .O(_1091_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1716_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .O(_1090_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _1717_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.shift.cnt [3]), + .I1(\corescorecore.core_3.serving.cpu.alu.shamt [3]), + .I2(\corescorecore.core_3.serving.cpu.alu.shift.cnt [4]), + .I3(\corescorecore.core_3.serving.cpu.alu.shamt [4]), + .O(_1085_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1718_ ( + .I0(_1086_[0]), + .I1(_1086_[1]), + .O(_1087_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1719_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .O(_1086_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1720_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .O(_1086_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfb0f) + ) _1721_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I1(_1084_[1]), + .I2(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .O(_1088_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1722_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .O(_1084_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _1723_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .O(_1092_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1724_ ( + .I0(_1087_[2]), + .I1(_1092_[0]), + .I2(_1088_[0]), + .O(_1285_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1725_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_3.serving.cpu.i_rf_ready ), + .I2(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .O(_0058_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1726_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .O(_0056_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f4) + ) _1727_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_3.serving.cpu.ctrl.i_jump ), + .I2(_1267_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0059_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'heb00) + ) _1728_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I1(_1266_[1]), + .I2(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .I3(_1266_[3]), + .O(_1267_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3335) + ) _1729_ ( + .I0(_1245_[0]), + .I1(\corescorecore.core_3.serving.cpu.alu.result_lt ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .O(_1266_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hacc5) + ) _1730_ ( + .I0(_1265_[0]), + .I1(\corescorecore.core_3.serving.cpu.alu.lt_r ), + .I2(_0950_), + .I3(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .O(\corescorecore.core_3.serving.cpu.alu.result_lt ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf011) + ) _1731_ ( + .I0(_1122_[1]), + .I1(_1122_[0]), + .I2(_1197_[2]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_0950_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _1732_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata1 [0]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .O(_1197_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _1733_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .O(_1265_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _1734_ ( + .I0(_0950_), + .I1(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_3.serving.cpu.alu.eq_r ), + .O(_1245_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1735_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I2(_1093_[2]), + .O(_1266_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1736_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .O(_1093_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1737_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .O(_0351_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1738_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0889_[1]), + .O(_0054_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1739_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0234_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1740_ ( + .I0(_1083_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [32]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1741_ ( + .I0(_1076_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [33]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1742_ ( + .I0(_1075_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [34]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1743_ ( + .I0(_1080_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [35]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1744_ ( + .I0(_1079_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [36]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1745_ ( + .I0(_1078_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [37]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1746_ ( + .I0(_1077_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [38]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1747_ ( + .I0(_1068_[0]), + .I1(\corescorecore.axis_mux.s_axis_tdata [39]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .O(\corescorecore.axis_mux.current_s_tdata [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1748_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0235_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1749_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0236_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1750_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .I2(\corescorecore.axis_mux.m_axis_tvalid ), + .O(\corescorecore.axis_mux.store_axis_int_to_temp ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1751_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0237_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1752_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0238_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1753_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [0]), + .I1(\corescorecore.axis_mux.current_s_tdata [0]), + .I2(_1069_[2]), + .O(_0457_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hd0) + ) _1754_ ( + .I0(\corescorecore.axis_mux.m_axis_tvalid ), + .I1(\corescorecore.axis_mux.m_axis_tready ), + .I2(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .O(_1069_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1755_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [1]), + .I1(\corescorecore.axis_mux.current_s_tdata [1]), + .I2(_1069_[2]), + .O(_0458_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1756_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [2]), + .I1(\corescorecore.axis_mux.current_s_tdata [2]), + .I2(_1069_[2]), + .O(_0459_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1757_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [3]), + .I1(\corescorecore.axis_mux.current_s_tdata [3]), + .I2(_1069_[2]), + .O(_0460_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1758_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [4]), + .I1(\corescorecore.axis_mux.current_s_tdata [4]), + .I2(_1069_[2]), + .O(_0461_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1759_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [5]), + .I1(\corescorecore.axis_mux.current_s_tdata [5]), + .I2(_1069_[2]), + .O(_0462_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1760_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [6]), + .I1(\corescorecore.axis_mux.current_s_tdata [6]), + .I2(_1069_[2]), + .O(_0463_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1761_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tdata_reg [7]), + .I1(\corescorecore.axis_mux.current_s_tdata [7]), + .I2(_1069_[2]), + .O(_0464_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1762_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0239_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1763_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0889_[0]), + .O(_0053_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1764_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(_0908_[0]), + .O(_0241_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1765_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(_0908_[1]), + .O(_0242_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1766_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(_0908_[2]), + .O(_0243_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1767_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(_0908_[3]), + .O(_0244_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1768_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(_0908_[4]), + .O(_0245_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1769_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(_0908_[5]), + .O(_0246_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1770_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_en ), + .I1(_1018_[3]), + .I2(_1046_[1]), + .I3(_1273_[3]), + .O(_0247_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1771_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .I3(_1052_[1]), + .O(_1273_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1f) + ) _1772_ ( + .I0(_0871_[1]), + .I1(_0871_[0]), + .I2(_0871_[2]), + .O(_0857_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1f) + ) _1773_ ( + .I0(_0868_[1]), + .I1(_0868_[0]), + .I2(_0868_[2]), + .O(_0853_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1774_ ( + .I0(\corescorecore.axis_mux.arb_inst.mask_reg [4]), + .I1(_1063_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1063_[3]), + .O(_0350_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1775_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0248_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1776_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0249_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1777_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rcnt [1]), + .I1(\corescorecore.core_1.serving.rf_ram_if.rcnt [2]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rcnt [0]), + .O(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1778_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_1.serving.rf_ram_if.rreq_r ), + .O(_0250_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1779_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .I1(_0920_[0]), + .O(_0251_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1780_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .I1(_0920_[1]), + .O(_0252_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1781_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .I1(_0920_[2]), + .O(_0253_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1782_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .I1(_0920_[3]), + .O(_0254_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _1783_ ( + .I0(_1062_[0]), + .I1(_1065_[1]), + .O(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f4) + ) _1784_ ( + .I0(_1061_[1]), + .I1(_1061_[0]), + .I2(_1064_[2]), + .I3(_1064_[3]), + .O(_1065_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1785_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [0]), + .I1(\corescorecore.core_0.o_tvalid ), + .O(_1064_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1786_ ( + .I0(\corescorecore.axis_mux.arb_inst.grant [1]), + .I1(\corescorecore.core_1.o_tvalid ), + .O(_1064_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _1787_ ( + .I0(_0923_[0]), + .I1(\corescorecore.core_1.serving.rf_ram_if.wcnt [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .O(_0256_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1788_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.o_waddr [0]), + .I1(_0923_[3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .O(_0259_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _1789_ ( + .I0(\emitter.data [2]), + .I1(\corescorecore.axis_mux.m_axis_tdata [0]), + .I2(\emitter.cnt [9]), + .O(_0449_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1790_ ( + .I0(\corescorecore.axis_mux.m_axis_tdata [1]), + .I1(\emitter.data [3]), + .I2(\emitter.cnt [9]), + .O(_0450_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1791_ ( + .I0(\corescorecore.axis_mux.m_axis_tdata [2]), + .I1(\emitter.data [4]), + .I2(\emitter.cnt [9]), + .O(_0451_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1792_ ( + .I0(\corescorecore.axis_mux.m_axis_tdata [3]), + .I1(\emitter.data [5]), + .I2(\emitter.cnt [9]), + .O(_0452_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1793_ ( + .I0(\corescorecore.axis_mux.m_axis_tdata [4]), + .I1(\emitter.data [6]), + .I2(\emitter.cnt [9]), + .O(_0453_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1794_ ( + .I0(\corescorecore.axis_mux.m_axis_tdata [5]), + .I1(\emitter.data [7]), + .I2(\emitter.cnt [9]), + .O(_0454_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1795_ ( + .I0(\corescorecore.axis_mux.m_axis_tdata [6]), + .I1(\emitter.data [8]), + .I2(\emitter.cnt [9]), + .O(_0455_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1796_ ( + .I0(\corescorecore.axis_mux.m_axis_tdata [7]), + .I1(\emitter.data [9]), + .I2(\emitter.cnt [9]), + .O(_0456_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _1797_ ( + .I0(_1117_[0]), + .I1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .O(\corescorecore.axis_mux.arb_inst.masked_request_index [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000d) + ) _1798_ ( + .I0(_1049_[3]), + .I1(_1049_[2]), + .I2(\corescorecore.axis_mux.arb_inst.masked_request_index [2]), + .I3(_1049_[1]), + .O(_1117_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7f00) + ) _1799_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .I3(_1067_[3]), + .O(\corescorecore.core_0.serving.ram.wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1800_ ( + .I0(_1066_[0]), + .I1(_1003_[0]), + .I2(\corescorecore.core_0.serving.arbiter.i_wb_mem_ack ), + .O(_1067_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1801_ ( + .I0(_1002_[0]), + .I1(\corescorecore.core_0.serving.cpu.ctrl.en_pc_r ), + .O(_1003_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1802_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_1002_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1803_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I3(_1018_[3]), + .O(_1066_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1804_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_0.serving.rf_ram_if.wcnt [1]), + .I2(\corescorecore.core_0.serving.rf_ram_if.wcnt [2]), + .O(\corescorecore.core_0.serving.rf_ram_if.wtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaff) + ) _1805_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(_1003_[0]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.raddr [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1806_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.o_waddr [0]), + .I1(_0877_[3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .O(_0050_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1807_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.o_waddr [1]), + .I1(_0923_[4]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .O(_0260_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0eee) + ) _1808_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wreq_r ), + .I2(_1251_[2]), + .I3(\corescorecore.core_1.serving.rf_ram_if.o_waddr [0]), + .O(_0261_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _1809_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_1.serving.rf_ram_if.o_waddr [1]), + .I2(\corescorecore.core_1.serving.rf_ram_if.wcnt [2]), + .I3(\corescorecore.core_1.serving.rf_ram_if.wcnt [1]), + .O(_1251_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1810_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0915_[0]), + .O(_0262_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1811_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0915_[1]), + .O(_0263_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1812_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0915_[2]), + .O(_0264_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1813_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .O(_0265_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1814_ ( + .I0(_1003_[0]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_ack ), + .O(\corescorecore.core_0.serving.cpu.decode.i_wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1815_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata1 [1]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .O(_0443_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1816_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata1 [2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .O(_0444_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1817_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata1 [3]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .O(_0445_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1818_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata1 [4]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .O(_0446_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1819_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata1 [5]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .O(_0447_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1820_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata1 [6]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .O(_0448_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _1821_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(_1094_[1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .I3(_1094_[3]), + .O(_0266_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1822_ ( + .I0(\corescorecore.core_0.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_0.serving.cpu.i_rf_ready ), + .O(_1094_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf2ff) + ) _1823_ ( + .I0(_1015_[0]), + .I1(_1005_[2]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rgnt ), + .I3(_1015_[3]), + .O(\corescorecore.core_0.serving.cpu.i_rf_ready ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h001f) + ) _1824_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I2(\corescorecore.core_0.serving.i_wb_ack ), + .I3(_1004_[3]), + .O(_1005_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1825_ ( + .I0(_1003_[0]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_mem_ack ), + .O(_1004_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _1826_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.shift.cnt [3]), + .I1(\corescorecore.core_0.serving.cpu.alu.shamt [3]), + .I2(\corescorecore.core_0.serving.cpu.alu.shift.cnt [4]), + .I3(\corescorecore.core_0.serving.cpu.alu.shamt [4]), + .O(_1012_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1827_ ( + .I0(_1011_[0]), + .I1(_1011_[1]), + .O(_1013_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1828_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .O(_1011_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1829_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .O(_1011_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfb0f) + ) _1830_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I1(_1010_[1]), + .I2(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .O(_1014_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1831_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .O(_1010_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _1832_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .O(_1015_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1833_ ( + .I0(_1013_[2]), + .I1(_1015_[0]), + .I2(_1014_[0]), + .O(_1094_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1834_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_0.serving.cpu.i_rf_ready ), + .I2(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .O(_0267_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f4) + ) _1835_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_0.serving.cpu.ctrl.i_jump ), + .I2(_1023_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0268_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'heb00) + ) _1836_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I1(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .I2(_1022_[2]), + .I3(_1022_[3]), + .O(_1023_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3335) + ) _1837_ ( + .I0(_1020_[0]), + .I1(\corescorecore.core_0.serving.cpu.alu.result_lt ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .O(_1022_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hacc5) + ) _1838_ ( + .I0(_1019_[0]), + .I1(\corescorecore.core_0.serving.cpu.alu.lt_r ), + .I2(_0878_), + .I3(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .O(\corescorecore.core_0.serving.cpu.alu.result_lt ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf011) + ) _1839_ ( + .I0(_1017_[0]), + .I1(_1017_[1]), + .I2(_1017_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_0878_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1840_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm11_7 [0]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .I3(_1016_[3]), + .O(_1017_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1841_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_1016_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1842_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_0.serving.cpu.decode.signbit ), + .O(_1017_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _1843_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata1 [0]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_1017_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _1844_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .O(_1019_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _1845_ ( + .I0(_0878_), + .I1(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_0.serving.cpu.alu.eq_r ), + .O(_1020_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1846_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I2(_1021_[2]), + .O(_1022_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1847_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .O(_1021_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1848_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm11_7 [1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0785_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1849_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [8]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm11_7 [2]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0786_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1850_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [9]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm11_7 [3]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0787_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1851_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [10]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm11_7 [4]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0788_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1852_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [11]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0789_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1853_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm24_20 [1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0799_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1854_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [21]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm24_20 [2]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0800_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1855_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [22]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm24_20 [3]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0801_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1856_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [23]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm24_20 [4]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0802_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1857_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0803_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1858_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [25]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm30_25 [1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0804_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1859_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [26]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm30_25 [2]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0805_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1860_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [27]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm30_25 [3]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0806_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1861_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [28]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm30_25 [4]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0807_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1862_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [29]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm30_25 [5]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0808_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1863_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_4.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0810_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1864_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0790_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1865_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [12]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [2]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0791_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1866_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [13]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [3]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0792_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1867_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [14]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [4]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0793_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1868_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [15]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [5]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0794_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1869_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [16]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [6]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0795_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1870_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [17]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [7]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0796_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1871_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [18]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [8]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0797_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3a) + ) _1872_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1289_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0798_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _1873_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_4.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_4.serving.cpu.decode.m3 ), + .O(_1289_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'ha3) + ) _1874_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(_1372_[1]), + .I2(_1288_[2]), + .O(_0811_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _1875_ ( + .I0(\corescorecore.core_4.serving.cpu.csr_imm ), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [15]), + .I2(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .O(_1372_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _1876_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I3(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .O(_1288_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _1877_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(_1288_[1]), + .I2(_1288_[2]), + .O(_0812_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1878_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [16]), + .I2(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .O(_1288_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _1879_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(_1337_[1]), + .I2(_1288_[2]), + .O(_0813_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1880_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [17]), + .I2(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .O(_1337_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _1881_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(_1377_[1]), + .I2(_1288_[2]), + .O(_0814_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1882_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [18]), + .I2(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .O(_1377_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1883_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [19]), + .I2(_1288_[2]), + .I3(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .O(_0815_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0b) + ) _1884_ ( + .I0(_1062_[1]), + .I1(_1062_[0]), + .I2(\clkgen.o_rst_core ), + .O(_0342_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1885_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt_r [1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0271_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1886_ ( + .I0(_1344_[0]), + .I1(\clkgen.o_rst_core ), + .O(_0341_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0777) + ) _1887_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant [4]), + .I2(_1063_[3]), + .I3(_1343_[3]), + .O(_1344_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1888_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt_r [3]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt_r [2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0272_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hacc5) + ) _1889_ ( + .I0(_1040_[0]), + .I1(\corescorecore.core_4.serving.cpu.alu.lt_r ), + .I2(_0931_), + .I3(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .O(\corescorecore.core_4.serving.cpu.alu.result_lt ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf011) + ) _1890_ ( + .I0(_1039_[0]), + .I1(_1039_[1]), + .I2(_1039_[2]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_0931_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1891_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_4.serving.cpu.decode.imm11_7 [0]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .I3(_1038_[3]), + .O(_1039_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _1892_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_1038_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1893_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_4.serving.cpu.decode.signbit ), + .O(_1039_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _1894_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata1 [0]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .O(_1039_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _1895_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .O(_1040_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1896_ ( + .I0(\corescorecore.core_0.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0273_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _1897_ ( + .I0(_1263_[0]), + .I1(_1263_[1]), + .I2(\corescorecore.core_4.serving.cpu.bufreg.c_r ), + .O(\corescorecore.core_4.serving.cpu.bufreg.q ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000e) + ) _1898_ ( + .I0(_1039_[0]), + .I1(_1039_[1]), + .I2(_1262_[2]), + .I3(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .O(_1263_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _1899_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(_1204_[1]), + .I3(\corescorecore.core_4.serving.cpu.decode.m3 ), + .O(_1262_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1900_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt_r [0]), + .I2(_1203_[2]), + .O(_1204_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _1901_ ( + .I0(\corescorecore.core_4.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_4.serving.cpu.mem_bytecnt [1]), + .O(_1203_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4f00) + ) _1902_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .O(_1263_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _1903_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_buf ), + .I1(\corescorecore.core_4.serving.cpu.bufreg.q ), + .I2(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I3(_1195_[0]), + .O(_0782_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7f00) + ) _1904_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .I3(_1201_[3]), + .O(\corescorecore.core_4.serving.ram.wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _1905_ ( + .I0(_1200_[0]), + .I1(_1082_[0]), + .I2(\corescorecore.core_4.serving.arbiter.i_wb_mem_ack ), + .O(_1201_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1906_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_en ), + .I1(_1199_[1]), + .I2(_1058_[2]), + .O(_1200_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1907_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_4.serving.rf_ram_if.wcnt [1]), + .I2(\corescorecore.core_4.serving.rf_ram_if.wcnt [2]), + .O(\corescorecore.core_4.serving.rf_ram_if.wtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaff) + ) _1908_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(_1082_[0]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.raddr [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfff4) + ) _1909_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_ack ), + .I1(\corescorecore.core_0.serving.cpu.ctrl.en_pc_r ), + .I2(_1002_[0]), + .I3(\clkgen.o_rst_core ), + .O(_0274_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1910_ ( + .I0(\corescorecore.core_0.serving.cpu.ctrl.pc ), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0275_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _1911_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0276_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h41be) + ) _1912_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I1(_1204_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0931_), + .O(\corescorecore.core_4.serving.cpu.alu.shamt_ser ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1913_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata0 [1]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_0436_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _1914_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rcnt [1]), + .I1(\corescorecore.core_4.serving.rf_ram_if.rcnt [2]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rcnt [0]), + .O(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1915_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata0 [2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_0437_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1916_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata0 [3]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_0438_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1917_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata0 [4]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_0439_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1918_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata0 [5]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_0440_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1919_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata0 [6]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_0441_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _1920_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rdata0 [7]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_0442_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1921_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [0]), + .I2(_1255_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [33]), + .O(_0816_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1922_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [1]), + .I2(_1255_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [34]), + .O(_0827_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1923_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [2]), + .I2(_1255_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [35]), + .O(_0838_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1924_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [3]), + .I2(_1255_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [36]), + .O(_0841_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1925_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [4]), + .I2(_1255_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [37]), + .O(_0842_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1926_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [5]), + .I2(_1255_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [38]), + .O(_0843_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1927_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [6]), + .I2(_1255_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [39]), + .O(_0844_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1928_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [7]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.o_tlast ), + .O(_0845_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1929_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [8]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .O(_0846_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1930_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [9]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .O(_0847_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1931_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [10]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .O(_0817_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1932_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [11]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .O(_0818_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1933_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [12]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .O(_0819_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1934_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [13]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .O(_0820_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1935_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [14]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .O(_0821_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1936_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [15]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .O(_0822_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1937_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [16]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .O(_0823_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1938_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [17]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .O(_0824_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1939_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [18]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .O(_0825_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1940_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .O(_0826_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1941_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [20]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .O(_0828_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1942_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [21]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .O(_0829_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1943_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [22]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .O(_0830_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1944_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [23]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .O(_0831_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1945_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .O(_0832_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1946_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [25]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .O(_0833_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1947_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [26]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .O(_0834_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1948_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [27]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .O(_0835_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1949_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [28]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .O(_0836_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1950_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [29]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .O(_0837_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _1951_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1254_[2]), + .I2(_1255_[1]), + .I3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .O(_0839_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8f88) + ) _1952_ ( + .I0(_1254_[2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31]), + .I2(_1039_[2]), + .I3(_1255_[1]), + .O(_0840_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0b) + ) _1953_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_4.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_4.serving.cpu.mem_bytecnt [1]), + .I3(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_4.serving.cpu.mem_if.dat_valid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff80) + ) _1954_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .I3(_1331_[3]), + .O(\corescorecore.core_4.serving.ram.we ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _1955_ ( + .I0(_1082_[0]), + .I1(_1201_[3]), + .I2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .I3(_1000_), + .O(_1331_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _1956_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.o_waddr [0]), + .I1(\corescorecore.core_4.serving.ram.bsel [0]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.waddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _1957_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.o_waddr [1]), + .I1(\corescorecore.core_4.serving.ram.bsel [1]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.waddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _1958_ ( + .I0(\corescorecore.core_4.serving.ram.wb_en ), + .I1(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [0]), + .I3(_1327_[0]), + .O(\corescorecore.core_4.serving.ram.waddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _1959_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(_1082_[0]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(_1327_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _1960_ ( + .I0(\corescorecore.core_4.serving.ram.wb_en ), + .I1(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [1]), + .I3(_1319_[0]), + .O(\corescorecore.core_4.serving.ram.waddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _1961_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(_1082_[0]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(_1319_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _1962_ ( + .I0(\corescorecore.core_4.serving.ram.wb_en ), + .I1(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [2]), + .I3(_1293_[3]), + .O(\corescorecore.core_4.serving.ram.waddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _1963_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(_1082_[0]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(_1293_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _1964_ ( + .I0(\corescorecore.core_4.serving.ram.wb_en ), + .I1(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(_1336_[3]), + .O(\corescorecore.core_4.serving.ram.waddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _1965_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(_1082_[0]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(_1336_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _1966_ ( + .I0(\corescorecore.core_4.serving.ram.wb_en ), + .I1(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [4]), + .I3(_1290_[0]), + .O(\corescorecore.core_4.serving.ram.waddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _1967_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(_1082_[0]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(_1290_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1968_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [0]), + .I2(_1001_[0]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1969_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [1]), + .I2(_1001_[1]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1970_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [2]), + .I2(_1001_[2]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1971_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [3]), + .I2(_1001_[3]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1972_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [4]), + .I2(_1001_[4]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1973_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [5]), + .I2(_1001_[5]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1974_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [6]), + .I2(_1001_[6]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1975_ ( + .I0(_1302_[0]), + .I1(_1302_[1]), + .I2(_1195_[0]), + .I3(_1302_[3]), + .O(\corescorecore.core_4.serving.cpu.o_wdata0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6900) + ) _1976_ ( + .I0(_1205_[0]), + .I1(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_4.serving.cpu.alu.add_cy_r ), + .I3(_1297_[3]), + .O(_1302_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7d82) + ) _1977_ ( + .I0(_1204_[0]), + .I1(_1204_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0931_), + .O(_1205_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _1978_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_sh_signed ), + .O(_1204_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _1979_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .O(_1297_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000d) + ) _1980_ ( + .I0(_1253_[1]), + .I1(_1296_[1]), + .I2(_1296_[2]), + .I3(_1296_[3]), + .O(_1302_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6000) + ) _1981_ ( + .I0(_1294_[0]), + .I1(_1210_[0]), + .I2(_1208_[0]), + .I3(\corescorecore.core_4.serving.cpu.ctrl.en_pc_r ), + .O(_1296_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _1982_ ( + .I0(_1210_[1]), + .I1(\corescorecore.core_4.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .O(_1294_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _1983_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .I2(_1207_[2]), + .I3(\corescorecore.core_4.serving.cpu.ctrl.pc ), + .O(_1210_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3e) + ) _1984_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [1]), + .O(_1207_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _1985_ ( + .I0(_1039_[1]), + .I1(_1039_[0]), + .I2(_1209_[2]), + .I3(_1209_[3]), + .O(_1210_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _1986_ ( + .I0(_1208_[0]), + .I1(\corescorecore.core_4.serving.cpu.alu.i_buf ), + .O(_1209_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1987_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .O(_1208_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf800) + ) _1988_ ( + .I0(\corescorecore.core_4.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .I2(\corescorecore.core_4.serving.cpu.mem_bytecnt [1]), + .I3(_1208_[0]), + .O(_1209_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _1989_ ( + .I0(_1295_[0]), + .I1(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .O(_1296_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _1990_ ( + .I0(_1206_[0]), + .I1(\corescorecore.core_4.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_4.serving.cpu.ctrl.pc_plus_4_cy_r ), + .O(_1295_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _1991_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt_r [2]), + .I2(_1203_[2]), + .O(_1206_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0fbb) + ) _1992_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_4.serving.cpu.mem_if.signbit ), + .I2(\corescorecore.core_4.serving.cpu.mem_if.dat_cur ), + .I3(\corescorecore.core_4.serving.cpu.mem_if.dat_valid ), + .O(_1296_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hbf00) + ) _1993_ ( + .I0(_1195_[1]), + .I1(_1301_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I3(_1301_[3]), + .O(_1302_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h007f) + ) _1994_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.result_lt_r ), + .I1(_1204_[1]), + .I2(_1239_[1]), + .I3(_1299_[3]), + .O(_1301_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hca00) + ) _1995_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.shift.signbit ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_buf ), + .I2(_1298_[2]), + .I3(_1195_[1]), + .O(_1299_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _1996_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_4.serving.cpu.alu.shift.wrapped ), + .O(_1298_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _1997_ ( + .I0(_1300_[0]), + .I1(_1300_[1]), + .I2(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .O(_1301_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _1998_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_4.serving.cpu.o_wdata0 ), + .I2(_1001_[7]), + .I3(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.wdata [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _1999_ ( + .I0(\corescorecore.core_4.serving.raddr [0]), + .I1(\corescorecore.core_4.serving.ram.bsel [0]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.raddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2000_ ( + .I0(\corescorecore.core_4.serving.raddr [1]), + .I1(\corescorecore.core_4.serving.ram.bsel [1]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .O(\corescorecore.core_4.serving.ram.raddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2001_ ( + .I0(_1327_[0]), + .I1(_1327_[1]), + .O(\corescorecore.core_4.serving.ram.raddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2002_ ( + .I0(\corescorecore.core_4.serving.cpu.csr_imm ), + .I1(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [0]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .I3(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_1327_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2003_ ( + .I0(_1319_[0]), + .I1(_1319_[1]), + .O(\corescorecore.core_4.serving.ram.raddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2004_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [1]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .I3(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_1319_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2005_ ( + .I0(_1293_[3]), + .I1(_1342_[1]), + .O(\corescorecore.core_4.serving.ram.raddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2006_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [2]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .I3(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_1342_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2007_ ( + .I0(_1336_[3]), + .I1(_1341_[1]), + .O(\corescorecore.core_4.serving.ram.raddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2008_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [3]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .I3(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_1341_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2009_ ( + .I0(_1290_[0]), + .I1(_1290_[1]), + .O(\corescorecore.core_4.serving.ram.raddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2010_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [4]), + .I2(\corescorecore.core_4.serving.ram.wb_en ), + .I3(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .O(_1290_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2011_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0278_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2012_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0279_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2013_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0280_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7f00) + ) _2014_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .I3(_1193_[3]), + .O(\corescorecore.core_3.serving.ram.wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f8) + ) _2015_ ( + .I0(_1192_[0]), + .I1(_1090_[1]), + .I2(_1090_[0]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_mem_ack ), + .O(_1193_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2016_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_3.serving.rf_ram_if.wcnt [2]), + .I2(\corescorecore.core_3.serving.rf_ram_if.wcnt [1]), + .O(\corescorecore.core_3.serving.rf_ram_if.wtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaff) + ) _2017_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(_1090_[0]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.raddr [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2018_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0282_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2019_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0283_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2020_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0284_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2021_ ( + .I0(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [1]), + .I1(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [0]), + .O(_0861_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2022_ ( + .I0(\corescorecore.axis_mux.arb_inst.masked_request_index [1]), + .I1(\corescorecore.axis_mux.arb_inst.masked_request_index [0]), + .O(_0865_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2023_ ( + .I0(_1374_[0]), + .I1(\clkgen.o_rst_core ), + .O(_0340_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0777) + ) _2024_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant [3]), + .I2(_1063_[3]), + .I3(_1340_[3]), + .O(_1374_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2025_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0286_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2026_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm11_7 [1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0708_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2027_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [8]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm11_7 [2]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0709_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2028_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [9]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm11_7 [3]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0710_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2029_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [10]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm11_7 [4]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0711_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2030_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [11]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0712_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2031_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm24_20 [1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0722_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2032_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [21]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm24_20 [2]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0723_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2033_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [22]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm24_20 [3]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0724_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2034_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [23]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm24_20 [4]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0725_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2035_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0726_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2036_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [25]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm30_25 [1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0727_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2037_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [26]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm30_25 [2]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0728_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2038_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [27]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm30_25 [3]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0729_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2039_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [28]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm30_25 [4]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0730_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2040_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [29]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm30_25 [5]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0731_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2041_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_3.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0733_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2042_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0713_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2043_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [12]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [2]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0714_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2044_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [13]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [3]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0715_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2045_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [14]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [4]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0716_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2046_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [15]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [5]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0717_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2047_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [16]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [6]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0718_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2048_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [17]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [7]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0719_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2049_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [18]), + .I1(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [8]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0720_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3a) + ) _2050_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1369_[1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0721_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2051_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_3.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_3.serving.cpu.decode.m3 ), + .O(_1369_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2052_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0285_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2053_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(_1339_[1]), + .I2(_1303_[2]), + .O(_0734_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2054_ ( + .I0(\corescorecore.core_3.serving.cpu.csr_imm ), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [15]), + .I2(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .O(_1339_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2055_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I3(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .O(_1303_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2056_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(_1332_[1]), + .I2(_1303_[2]), + .O(_0735_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2057_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [16]), + .I2(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .O(_1332_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2058_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(_1303_[1]), + .I2(_1303_[2]), + .O(_0736_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2059_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [17]), + .I2(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .O(_1303_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2060_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(_1376_[1]), + .I2(_1303_[2]), + .O(_0737_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2061_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [18]), + .I2(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .O(_1376_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2062_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [19]), + .I2(_1303_[2]), + .I3(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .O(_0738_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2063_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0287_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2064_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0288_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2065_ ( + .I0(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [0]), + .I1(_1315_[0]), + .O(_0860_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2066_ ( + .I0(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [2]), + .I1(_1061_[3]), + .O(_1315_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2067_ ( + .I0(\corescorecore.axis_mux.arb_inst.masked_request_index [0]), + .I1(_1115_[2]), + .O(_0864_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2068_ ( + .I0(_1333_[0]), + .I1(\clkgen.o_rst_core ), + .O(_0339_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0777) + ) _2069_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant [2]), + .I2(_1063_[3]), + .I3(_1328_[3]), + .O(_1333_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2070_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0290_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2071_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0291_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2072_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0292_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2073_ ( + .I0(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0040_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2074_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0293_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2075_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0294_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2076_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata1 [1]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_0417_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2077_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata1 [2]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_0418_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2078_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata1 [3]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_0419_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2079_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata1 [4]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_0420_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2080_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata1 [5]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_0421_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2081_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata1 [6]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_0422_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _2082_ ( + .I0(_1305_[0]), + .I1(_1305_[1]), + .I2(\corescorecore.core_3.serving.cpu.bufreg.c_r ), + .O(\corescorecore.core_3.serving.cpu.bufreg.q ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000e) + ) _2083_ ( + .I0(_1122_[1]), + .I1(_1122_[0]), + .I2(_1304_[2]), + .I3(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .O(_1305_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2084_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(_1190_[0]), + .I3(\corescorecore.core_3.serving.cpu.decode.m3 ), + .O(_1304_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2085_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [0]), + .I2(_1129_[2]), + .O(_1190_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4f00) + ) _2086_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .O(_1305_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2087_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_buf ), + .I1(\corescorecore.core_3.serving.cpu.bufreg.q ), + .I2(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I3(_1086_[0]), + .O(_0705_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2088_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0295_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2089_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0296_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2090_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0297_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h41be) + ) _2091_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I1(_1190_[0]), + .I2(\corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0950_), + .O(\corescorecore.core_3.serving.cpu.alu.shamt_ser ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2092_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata1 [1]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .O(_0430_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2093_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata1 [2]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .O(_0431_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2094_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata1 [3]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .O(_0432_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2095_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata1 [4]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .O(_0433_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2096_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata1 [5]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .O(_0434_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2097_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata1 [6]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .O(_0435_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2098_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata0 [1]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_0423_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2099_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata0 [2]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_0424_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2100_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata0 [3]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_0425_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2101_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata0 [4]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_0426_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2102_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata0 [5]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_0427_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2103_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata0 [6]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_0428_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2104_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.rdata0 [7]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_0429_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2105_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0299_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2106_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [0]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [25]), + .O(_0739_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2107_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [1]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [26]), + .O(_0750_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2108_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [2]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [27]), + .O(_0761_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2109_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [3]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [28]), + .O(_0764_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2110_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [4]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [29]), + .O(_0765_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2111_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [5]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [30]), + .O(_0766_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2112_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [6]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [31]), + .O(_0767_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2113_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [7]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.o_tlast ), + .O(_0768_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2114_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [8]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .O(_0769_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2115_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [9]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .O(_0770_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2116_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [10]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .O(_0740_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2117_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [11]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .O(_0741_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2118_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [12]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .O(_0742_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2119_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [13]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .O(_0743_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2120_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [14]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .O(_0744_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2121_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [15]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .O(_0745_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2122_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [16]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .O(_0746_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2123_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [17]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .O(_0747_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2124_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [18]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .O(_0748_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2125_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .O(_0749_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2126_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [20]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .O(_0751_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2127_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [21]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .O(_0752_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2128_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [22]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .O(_0753_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2129_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [23]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .O(_0754_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2130_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .O(_0755_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2131_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [25]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .O(_0756_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2132_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [26]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .O(_0757_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2133_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [27]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .O(_0758_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2134_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [28]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .O(_0759_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2135_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [29]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .O(_0760_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2136_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1091_[2]), + .I2(_1092_[1]), + .I3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .O(_0762_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8f88) + ) _2137_ ( + .I0(_1091_[2]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31]), + .I2(_1197_[2]), + .I3(_1092_[1]), + .O(_0763_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2138_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0300_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0b) + ) _2139_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_3.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_3.serving.cpu.mem_bytecnt [1]), + .I3(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_3.serving.cpu.mem_if.dat_valid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2140_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0301_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff80) + ) _2141_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .I3(_1364_[3]), + .O(\corescorecore.core_3.serving.ram.we ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2142_ ( + .I0(_1090_[0]), + .I1(_1193_[3]), + .I2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .I3(_0998_), + .O(_1364_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2143_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.o_waddr [0]), + .I1(\corescorecore.core_3.serving.ram.bsel [0]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.waddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2144_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.o_waddr [1]), + .I1(\corescorecore.core_3.serving.ram.bsel [1]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.waddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2145_ ( + .I0(\corescorecore.core_3.serving.ram.wb_en ), + .I1(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [0]), + .I3(_1355_[0]), + .O(\corescorecore.core_3.serving.ram.waddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2146_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(_1090_[0]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(_1355_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2147_ ( + .I0(\corescorecore.core_3.serving.ram.wb_en ), + .I1(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [1]), + .I3(_1357_[0]), + .O(\corescorecore.core_3.serving.ram.waddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2148_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(_1090_[0]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(_1357_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2149_ ( + .I0(\corescorecore.core_3.serving.ram.wb_en ), + .I1(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [2]), + .I3(_1287_[0]), + .O(\corescorecore.core_3.serving.ram.waddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2150_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(_1090_[0]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(_1287_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2151_ ( + .I0(\corescorecore.core_3.serving.ram.wb_en ), + .I1(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(_1362_[3]), + .O(\corescorecore.core_3.serving.ram.waddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2152_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(_1090_[0]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(_1362_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2153_ ( + .I0(\corescorecore.core_3.serving.ram.wb_en ), + .I1(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [4]), + .I3(_1363_[3]), + .O(\corescorecore.core_3.serving.ram.waddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2154_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(_1090_[0]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(_1363_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2155_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [0]), + .I2(_0999_[0]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2156_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [1]), + .I2(_0999_[1]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2157_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [2]), + .I2(_0999_[2]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2158_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [3]), + .I2(_0999_[3]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2159_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [4]), + .I2(_0999_[4]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2160_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [5]), + .I2(_0999_[5]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2161_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [6]), + .I2(_0999_[6]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb0ff) + ) _2162_ ( + .I0(_1361_[0]), + .I1(_1361_[1]), + .I2(_1086_[0]), + .I3(_1361_[3]), + .O(\corescorecore.core_3.serving.cpu.o_wdata0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6900) + ) _2163_ ( + .I0(_1244_[0]), + .I1(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_3.serving.cpu.alu.add_cy_r ), + .I3(_1356_[3]), + .O(_1361_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7d82) + ) _2164_ ( + .I0(_1243_[0]), + .I1(_1190_[0]), + .I2(\corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0950_), + .O(_1244_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2165_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_sh_signed ), + .O(_1243_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _2166_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .O(_1356_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000d) + ) _2167_ ( + .I0(_1092_[0]), + .I1(_1358_[1]), + .I2(_1358_[2]), + .I3(_1358_[3]), + .O(_1361_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6000) + ) _2168_ ( + .I0(_1125_[0]), + .I1(_1125_[1]), + .I2(_1116_[3]), + .I3(\corescorecore.core_3.serving.cpu.ctrl.en_pc_r ), + .O(_1358_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2169_ ( + .I0(_1270_[0]), + .I1(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .O(_1358_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0fbb) + ) _2170_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_3.serving.cpu.mem_if.signbit ), + .I2(\corescorecore.core_3.serving.cpu.mem_if.dat_cur ), + .I3(\corescorecore.core_3.serving.cpu.mem_if.dat_valid ), + .O(_1358_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hbf00) + ) _2171_ ( + .I0(_1086_[1]), + .I1(_1360_[1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I3(_1360_[3]), + .O(_1361_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h007f) + ) _2172_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.result_lt_r ), + .I1(_1190_[0]), + .I2(_1084_[1]), + .I3(_1307_[3]), + .O(_1360_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hca00) + ) _2173_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.shift.signbit ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_buf ), + .I2(_1306_[2]), + .I3(_1086_[1]), + .O(_1307_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2174_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_3.serving.cpu.alu.shift.wrapped ), + .O(_1306_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2175_ ( + .I0(_1359_[0]), + .I1(_1359_[1]), + .I2(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .O(_1360_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2176_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_3.serving.cpu.o_wdata0 ), + .I2(_0999_[7]), + .I3(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.wdata [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2177_ ( + .I0(\corescorecore.core_3.serving.raddr [0]), + .I1(\corescorecore.core_3.serving.ram.bsel [0]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.raddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2178_ ( + .I0(\corescorecore.core_3.serving.raddr [1]), + .I1(\corescorecore.core_3.serving.ram.bsel [1]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .O(\corescorecore.core_3.serving.ram.raddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2179_ ( + .I0(_1355_[0]), + .I1(_1355_[1]), + .O(\corescorecore.core_3.serving.ram.raddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2180_ ( + .I0(\corescorecore.core_3.serving.cpu.csr_imm ), + .I1(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [0]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .I3(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_1355_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2181_ ( + .I0(_1357_[0]), + .I1(_1357_[1]), + .O(\corescorecore.core_3.serving.ram.raddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2182_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [1]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .I3(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_1357_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2183_ ( + .I0(_1287_[0]), + .I1(_1287_[1]), + .O(\corescorecore.core_3.serving.ram.raddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2184_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [2]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .I3(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_1287_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2185_ ( + .I0(_1362_[3]), + .I1(_1368_[1]), + .O(\corescorecore.core_3.serving.ram.raddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2186_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [3]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .I3(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_1368_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2187_ ( + .I0(_1363_[3]), + .I1(_1366_[1]), + .O(\corescorecore.core_3.serving.ram.raddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2188_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [4]), + .I2(\corescorecore.core_3.serving.ram.wb_en ), + .I3(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .O(_1366_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2189_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I1(_1324_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0031_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2190_ ( + .I0(_1295_[0]), + .I1(_1308_[1]), + .I2(\corescorecore.core_4.serving.cpu.ctrl.i_jump ), + .O(_1324_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _2191_ ( + .I0(_1294_[0]), + .I1(_1210_[0]), + .I2(\corescorecore.core_4.serving.cpu.ctrl.en_pc_r ), + .O(_1308_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2192_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0302_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2193_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0303_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2194_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0304_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7f00) + ) _2195_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .I3(_1027_[3]), + .O(\corescorecore.core_1.serving.ram.wb_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2196_ ( + .I0(_1026_[0]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_ack ), + .O(_1027_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2197_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .I2(_1025_[2]), + .I3(_1007_[0]), + .O(_1026_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2198_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_en ), + .I1(_1024_[1]), + .O(_1025_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2199_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_1.serving.rf_ram_if.wcnt [2]), + .I2(\corescorecore.core_1.serving.rf_ram_if.wcnt [1]), + .O(\corescorecore.core_1.serving.rf_ram_if.wtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaff) + ) _2200_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(_1007_[0]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.raddr [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2201_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0305_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2202_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(_0881_[0]), + .O(_0307_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2203_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(_0881_[1]), + .O(_0308_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2204_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(_0881_[2]), + .O(_0309_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2205_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm11_7 [1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0631_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2206_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [8]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm11_7 [2]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0632_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2207_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [9]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm11_7 [3]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0633_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2208_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [10]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm11_7 [4]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0634_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2209_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [11]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0635_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2210_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm24_20 [1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0645_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2211_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [21]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm24_20 [2]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0646_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2212_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [22]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm24_20 [3]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0647_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2213_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [23]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm24_20 [4]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0648_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2214_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0649_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2215_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [25]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm30_25 [1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0650_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2216_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [26]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm30_25 [2]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0651_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2217_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [27]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm30_25 [3]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0652_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2218_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [28]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm30_25 [4]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0653_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2219_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [29]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm30_25 [5]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0654_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2220_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_2.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0656_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2221_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0636_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2222_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [12]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [2]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0637_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2223_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [13]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [3]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0638_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2224_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [14]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [4]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0639_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2225_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [15]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [5]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0640_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2226_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [16]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [6]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0641_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2227_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [17]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [7]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0642_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2228_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [18]), + .I1(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [8]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0643_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3a) + ) _2229_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1329_[1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0644_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2230_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_2.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_2.serving.cpu.decode.m3 ), + .O(_1329_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2231_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(_1330_[1]), + .I2(_1309_[2]), + .O(_0657_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2232_ ( + .I0(\corescorecore.core_2.serving.cpu.csr_imm ), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [15]), + .I2(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .O(_1330_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2233_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I3(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .O(_1309_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2234_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(_1334_[1]), + .I2(_1309_[2]), + .O(_0658_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2235_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [16]), + .I2(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .O(_1334_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2236_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(_1335_[1]), + .I2(_1309_[2]), + .O(_0659_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2237_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [17]), + .I2(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .O(_1335_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2238_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(_1309_[1]), + .I2(_1309_[2]), + .O(_0660_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2239_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [18]), + .I2(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .O(_1309_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2240_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [19]), + .I2(_1309_[2]), + .I3(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .O(_0661_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2241_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(_0881_[3]), + .O(_0310_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2242_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata0 [1]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_0410_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2243_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata0 [2]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_0411_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2244_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata0 [3]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_0412_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2245_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata0 [4]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_0413_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2246_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata0 [5]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_0414_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2247_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata0 [6]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_0415_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2248_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata0 [7]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_0416_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2249_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata1 [1]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .O(_0404_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2250_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata1 [2]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .O(_0405_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2251_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata1 [3]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .O(_0406_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2252_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata1 [4]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .O(_0407_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2253_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata1 [5]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .O(_0408_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2254_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata1 [6]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .O(_0409_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hacc5) + ) _2255_ ( + .I0(_1184_[0]), + .I1(\corescorecore.core_2.serving.cpu.alu.lt_r ), + .I2(_0924_), + .I3(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .O(\corescorecore.core_2.serving.cpu.alu.result_lt ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf011) + ) _2256_ ( + .I0(_1177_[0]), + .I1(_1177_[1]), + .I2(_1177_[2]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_0924_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2257_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.rdata1 [0]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .O(_1177_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _2258_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .O(_1184_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _2259_ ( + .I0(_1225_[0]), + .I1(_1225_[1]), + .I2(\corescorecore.core_2.serving.cpu.bufreg.c_r ), + .O(\corescorecore.core_2.serving.cpu.bufreg.q ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000e) + ) _2260_ ( + .I0(_1177_[0]), + .I1(_1177_[1]), + .I2(_1224_[2]), + .I3(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .O(_1225_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2261_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(_1215_[1]), + .I3(\corescorecore.core_2.serving.cpu.decode.m3 ), + .O(_1224_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2262_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [0]), + .I2(_1214_[2]), + .O(_1215_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4f00) + ) _2263_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .O(_1225_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2264_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_buf ), + .I1(\corescorecore.core_2.serving.cpu.bufreg.q ), + .I2(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I3(_1101_[0]), + .O(_0628_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2265_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31]), + .O(_0314_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _2266_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rcnt [1]), + .I1(\corescorecore.core_0.serving.rf_ram_if.rcnt [2]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rcnt [0]), + .O(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2267_ ( + .I0(\clkgen.o_rst_core ), + .I1(\corescorecore.core_0.serving.rf_ram_if.rreq_r ), + .O(_0315_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2268_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .I1(_0899_[0]), + .O(_0316_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h41be) + ) _2269_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I1(_1215_[1]), + .I2(\corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0924_), + .O(\corescorecore.core_2.serving.cpu.alu.shamt_ser ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2270_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [0]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [17]), + .O(_0662_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2271_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [1]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [18]), + .O(_0673_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2272_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [2]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [19]), + .O(_0684_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2273_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [3]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [20]), + .O(_0687_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2274_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [4]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [21]), + .O(_0688_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2275_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [5]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [22]), + .O(_0689_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2276_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [6]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.axis_mux.s_axis_tdata [23]), + .O(_0690_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2277_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [7]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.o_tlast ), + .O(_0691_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2278_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [8]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .O(_0692_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2279_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [9]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .O(_0693_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2280_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [10]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .O(_0663_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2281_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [11]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .O(_0664_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2282_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [12]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .O(_0665_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2283_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [13]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .O(_0666_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2284_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [14]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .O(_0667_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2285_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [15]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .O(_0668_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2286_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [16]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .O(_0669_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2287_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [17]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .O(_0670_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2288_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [18]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .O(_0671_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2289_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .O(_0672_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2290_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [20]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .O(_0674_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2291_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [21]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .O(_0675_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2292_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [22]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .O(_0676_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2293_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [23]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .O(_0677_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2294_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .O(_0678_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2295_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [25]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .O(_0679_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2296_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [26]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .O(_0680_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2297_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [27]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .O(_0681_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2298_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [28]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .O(_0682_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2299_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [29]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .O(_0683_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2300_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1097_[3]), + .I2(_1104_[1]), + .I3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .O(_0685_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8f88) + ) _2301_ ( + .I0(_1097_[3]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31]), + .I2(_1177_[2]), + .I3(_1104_[1]), + .O(_0686_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0b) + ) _2302_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_2.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_2.serving.cpu.mem_bytecnt [1]), + .I3(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_2.serving.cpu.mem_if.dat_valid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2303_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .I1(_0899_[3]), + .O(_0319_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0a0c) + ) _2304_ ( + .I0(_0902_[0]), + .I1(\corescorecore.core_0.serving.rf_ram_if.wcnt [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .O(_0321_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2305_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .I1(_0899_[2]), + .O(_0318_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2306_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.wcnt [1]), + .I1(_0902_[1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .O(_0322_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2307_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.wcnt [2]), + .I1(_0902_[2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .O(_0323_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff80) + ) _2308_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .I3(_1353_[3]), + .O(\corescorecore.core_2.serving.ram.we ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2309_ ( + .I0(_1096_[0]), + .I1(_1212_[3]), + .I2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .I3(_0996_), + .O(_1353_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2310_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.o_waddr [0]), + .I1(\corescorecore.core_2.serving.ram.bsel [0]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.waddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2311_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.o_waddr [1]), + .I1(\corescorecore.core_2.serving.ram.bsel [1]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.waddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2312_ ( + .I0(\corescorecore.core_2.serving.ram.wb_en ), + .I1(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [0]), + .I3(_1354_[3]), + .O(\corescorecore.core_2.serving.ram.waddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2313_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(_1096_[0]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(_1354_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2314_ ( + .I0(\corescorecore.core_2.serving.ram.wb_en ), + .I1(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [1]), + .I3(_1338_[3]), + .O(\corescorecore.core_2.serving.ram.waddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2315_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(_1096_[0]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(_1338_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2316_ ( + .I0(\corescorecore.core_2.serving.ram.wb_en ), + .I1(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [2]), + .I3(_1310_[3]), + .O(\corescorecore.core_2.serving.ram.waddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2317_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(_1096_[0]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(_1310_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2318_ ( + .I0(\corescorecore.core_2.serving.ram.wb_en ), + .I1(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(_1313_[0]), + .O(\corescorecore.core_2.serving.ram.waddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2319_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(_1096_[0]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(_1313_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2320_ ( + .I0(\corescorecore.core_2.serving.ram.wb_en ), + .I1(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [4]), + .I3(_1291_[3]), + .O(\corescorecore.core_2.serving.ram.waddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2321_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(_1096_[0]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(_1291_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2322_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [0]), + .I2(_0997_[0]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2323_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [1]), + .I2(_0997_[1]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2324_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [2]), + .I2(_0997_[2]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2325_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [3]), + .I2(_0997_[3]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2326_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [4]), + .I2(_0997_[4]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2327_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [5]), + .I2(_0997_[5]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2328_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [6]), + .I2(_0997_[6]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb0ff) + ) _2329_ ( + .I0(_1350_[0]), + .I1(_1350_[1]), + .I2(_1101_[0]), + .I3(_1350_[3]), + .O(\corescorecore.core_2.serving.cpu.o_wdata0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6900) + ) _2330_ ( + .I0(_1227_[0]), + .I1(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_2.serving.cpu.alu.add_cy_r ), + .I3(_1292_[3]), + .O(_1350_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7d82) + ) _2331_ ( + .I0(_1226_[0]), + .I1(_1215_[1]), + .I2(\corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0924_), + .O(_1227_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2332_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_sh_signed ), + .O(_1226_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _2333_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .O(_1292_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000d) + ) _2334_ ( + .I0(_1104_[0]), + .I1(_1311_[1]), + .I2(_1311_[2]), + .I3(_1311_[3]), + .O(_1350_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6000) + ) _2335_ ( + .I0(_1258_[0]), + .I1(_1223_[0]), + .I2(_1220_[3]), + .I3(\corescorecore.core_2.serving.cpu.ctrl.en_pc_r ), + .O(_1311_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2336_ ( + .I0(_1259_[0]), + .I1(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .O(_1311_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0fbb) + ) _2337_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_2.serving.cpu.mem_if.signbit ), + .I2(\corescorecore.core_2.serving.cpu.mem_if.dat_cur ), + .I3(\corescorecore.core_2.serving.cpu.mem_if.dat_valid ), + .O(_1311_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hbf00) + ) _2338_ ( + .I0(_1101_[1]), + .I1(_1349_[1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I3(_1349_[3]), + .O(_1350_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h007f) + ) _2339_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.result_lt_r ), + .I1(_1215_[1]), + .I2(_1099_[1]), + .I3(_1347_[3]), + .O(_1349_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hca00) + ) _2340_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.shift.signbit ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_buf ), + .I2(_1312_[2]), + .I3(_1101_[1]), + .O(_1347_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2341_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_2.serving.cpu.alu.shift.wrapped ), + .O(_1312_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2342_ ( + .I0(_1348_[0]), + .I1(_1348_[1]), + .I2(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .O(_1349_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2343_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_2.serving.cpu.o_wdata0 ), + .I2(_0997_[7]), + .I3(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.wdata [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2344_ ( + .I0(\corescorecore.core_2.serving.raddr [0]), + .I1(\corescorecore.core_2.serving.ram.bsel [0]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.raddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2345_ ( + .I0(\corescorecore.core_2.serving.raddr [1]), + .I1(\corescorecore.core_2.serving.ram.bsel [1]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .O(\corescorecore.core_2.serving.ram.raddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2346_ ( + .I0(_1354_[3]), + .I1(_1375_[1]), + .O(\corescorecore.core_2.serving.ram.raddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2347_ ( + .I0(\corescorecore.core_2.serving.cpu.csr_imm ), + .I1(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [0]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .I3(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_1375_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2348_ ( + .I0(_1338_[3]), + .I1(_1351_[1]), + .O(\corescorecore.core_2.serving.ram.raddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2349_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [1]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .I3(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_1351_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2350_ ( + .I0(_1310_[3]), + .I1(_1346_[1]), + .O(\corescorecore.core_2.serving.ram.raddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2351_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [2]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .I3(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_1346_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2352_ ( + .I0(_1313_[0]), + .I1(_1313_[1]), + .O(\corescorecore.core_2.serving.ram.raddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2353_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [3]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .I3(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_1313_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2354_ ( + .I0(_1291_[3]), + .I1(_1352_[1]), + .O(\corescorecore.core_2.serving.ram.raddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2355_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [4]), + .I2(\corescorecore.core_2.serving.ram.wb_en ), + .I3(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .O(_1352_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0eee) + ) _2356_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.wreq_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .I2(_1378_[2]), + .I3(\corescorecore.core_0.serving.rf_ram_if.o_waddr [1]), + .O(_0326_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2357_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_0.serving.rf_ram_if.wcnt [1]), + .I2(\corescorecore.core_0.serving.rf_ram_if.wcnt [2]), + .I3(\corescorecore.core_0.serving.rf_ram_if.o_waddr [0]), + .O(_1378_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2358_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0894_[0]), + .O(_0327_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2359_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0894_[1]), + .O(_0328_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2360_ ( + .I0(_1064_[3]), + .I1(_1064_[2]), + .O(_0859_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2361_ ( + .I0(_1049_[1]), + .I1(_1049_[2]), + .O(_0863_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2362_ ( + .I0(_1371_[0]), + .I1(\clkgen.o_rst_core ), + .O(_0338_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0777) + ) _2363_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant [1]), + .I2(_1063_[3]), + .I3(_1370_[3]), + .O(_1371_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2364_ ( + .I0(\clkgen.o_rst_core ), + .I1(_0894_[2]), + .O(_0329_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2365_ ( + .I0(\clkgen.o_rst_core ), + .I1(_1059_[1]), + .I2(_1345_[2]), + .O(_0330_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2366_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_en ), + .I1(_1058_[1]), + .I2(_1058_[2]), + .O(_1345_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf444) + ) _2367_ ( + .I0(\corescorecore.axis_mux.m_axis_tvalid ), + .I1(\corescorecore.axis_mux.m_axis_tready ), + .I2(_1217_[0]), + .I3(\emitter.cnt [9]), + .O(_0331_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1000) + ) _2368_ ( + .I0(\emitter.data [2]), + .I1(\emitter.data [3]), + .I2(_1216_[2]), + .I3(_1216_[3]), + .O(_1217_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _2369_ ( + .I0(\emitter.data [8]), + .I1(\emitter.data [9]), + .I2(\emitter.data [1]), + .I3(\emitter.data [0]), + .O(_1216_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _2370_ ( + .I0(\emitter.data [4]), + .I1(\emitter.data [5]), + .I2(\emitter.data [6]), + .I3(\emitter.data [7]), + .O(_1216_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2371_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata0 [1]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_0397_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2372_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata0 [2]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_0398_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2373_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata0 [3]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_0399_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2374_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata0 [4]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_0400_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2375_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata0 [5]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_0401_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2376_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata0 [6]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_0402_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2377_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata0 [7]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_0403_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2378_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm11_7 [1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0554_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2379_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [8]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm11_7 [2]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0555_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2380_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [9]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm11_7 [3]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0556_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2381_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [10]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm11_7 [4]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0557_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2382_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [11]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0558_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2383_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm24_20 [1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0568_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2384_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [21]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm24_20 [2]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0569_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2385_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [22]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm24_20 [3]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0570_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2386_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [23]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm24_20 [4]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0571_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2387_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0572_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2388_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [25]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm30_25 [1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0573_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2389_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [26]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm30_25 [2]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0574_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2390_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [27]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm30_25 [3]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0575_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2391_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [28]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm30_25 [4]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0576_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2392_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [29]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm30_25 [5]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0577_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2393_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_1.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0579_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2394_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0559_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2395_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [12]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [2]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0560_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2396_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [13]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [3]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0561_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2397_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [14]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [4]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0562_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2398_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [15]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [5]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0563_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2399_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [16]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [6]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0564_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2400_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [17]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [7]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0565_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2401_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [18]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [8]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0566_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3a) + ) _2402_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1367_[1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0567_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2403_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_1.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_1.serving.cpu.decode.m3 ), + .O(_1367_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2404_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(_1322_[1]), + .I2(_1322_[2]), + .O(_0580_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2405_ ( + .I0(\corescorecore.core_1.serving.cpu.csr_imm ), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [15]), + .I2(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .O(_1322_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2406_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I3(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .O(_1322_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2407_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(_1365_[1]), + .I2(_1322_[2]), + .O(_0581_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2408_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [16]), + .I2(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .O(_1365_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2409_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(_1323_[1]), + .I2(_1322_[2]), + .O(_0582_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2410_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [17]), + .I2(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .O(_1323_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2411_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(_1325_[1]), + .I2(_1322_[2]), + .O(_0583_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2412_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [18]), + .I2(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .O(_1325_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2413_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [19]), + .I2(_1322_[2]), + .I3(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .O(_0584_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2414_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0022_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hacc5) + ) _2415_ ( + .I0(_1179_[0]), + .I1(\corescorecore.core_1.serving.cpu.alu.lt_r ), + .I2(_0905_), + .I3(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .O(\corescorecore.core_1.serving.cpu.alu.result_lt ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf011) + ) _2416_ ( + .I0(_1033_[0]), + .I1(_1033_[1]), + .I2(_1033_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_0905_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2417_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_1.serving.cpu.decode.imm11_7 [0]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .I3(_1032_[3]), + .O(_1033_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0100) + ) _2418_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .O(_1032_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2419_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_1.serving.cpu.decode.signbit ), + .O(_1033_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2420_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.rdata1 [0]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .O(_1033_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _2421_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .O(_1179_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _2422_ ( + .I0(_1119_[0]), + .I1(_1119_[1]), + .I2(\corescorecore.core_1.serving.cpu.bufreg.c_r ), + .O(\corescorecore.core_1.serving.cpu.bufreg.q ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000e) + ) _2423_ ( + .I0(_1033_[0]), + .I1(_1033_[1]), + .I2(_1118_[2]), + .I3(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .O(_1119_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2424_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(_1034_[1]), + .I3(\corescorecore.core_1.serving.cpu.decode.m3 ), + .O(_1118_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2425_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [0]), + .I2(_1031_[2]), + .O(_1034_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2426_ ( + .I0(\corescorecore.core_1.serving.cpu.mem_bytecnt [1]), + .I1(\corescorecore.core_1.serving.cpu.mem_bytecnt [0]), + .O(_1031_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4f00) + ) _2427_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .O(_1119_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2428_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_buf ), + .I1(\corescorecore.core_1.serving.cpu.bufreg.q ), + .I2(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I3(_1120_[3]), + .O(_0551_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h41be) + ) _2429_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I1(_1034_[1]), + .I2(\corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0905_), + .O(\corescorecore.core_1.serving.cpu.alu.shamt_ser ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2430_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [0]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [9]), + .O(_0585_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2431_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [1]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [10]), + .O(_0596_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2432_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [2]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [11]), + .O(_0607_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2433_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [3]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [12]), + .O(_0610_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2434_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [4]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [13]), + .O(_0611_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2435_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [5]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [14]), + .O(_0612_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2436_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [6]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [15]), + .O(_0613_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2437_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [7]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.o_tlast ), + .O(_0614_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2438_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [8]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .O(_0615_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2439_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [9]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .O(_0616_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2440_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [10]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .O(_0586_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2441_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [11]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .O(_0587_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2442_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [12]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .O(_0588_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2443_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [13]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .O(_0589_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2444_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [14]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .O(_0590_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2445_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [15]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .O(_0591_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2446_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [16]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .O(_0592_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2447_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [17]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .O(_0593_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2448_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [18]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .O(_0594_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2449_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .O(_0595_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2450_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [20]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .O(_0597_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2451_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [21]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .O(_0598_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2452_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [22]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .O(_0599_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2453_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [23]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .O(_0600_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2454_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .O(_0601_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2455_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [25]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .O(_0602_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2456_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [26]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .O(_0603_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2457_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [27]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .O(_0604_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2458_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [28]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .O(_0605_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2459_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [29]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .O(_0606_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2460_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1008_[3]), + .I2(_1009_[2]), + .I3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .O(_0608_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8f88) + ) _2461_ ( + .I0(_1008_[3]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31]), + .I2(_1033_[2]), + .I3(_1009_[2]), + .O(_0609_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0b) + ) _2462_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_1.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_1.serving.cpu.mem_bytecnt [1]), + .I3(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_1.serving.cpu.mem_if.dat_valid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f4) + ) _2463_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_4.serving.cpu.ctrl.i_jump ), + .I2(_1043_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0354_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'heb00) + ) _2464_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I1(_1042_[1]), + .I2(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .I3(_1042_[3]), + .O(_1043_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3335) + ) _2465_ ( + .I0(_1041_[0]), + .I1(\corescorecore.core_4.serving.cpu.alu.result_lt ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .O(_1042_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _2466_ ( + .I0(_0931_), + .I1(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_4.serving.cpu.alu.eq_r ), + .O(_1041_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2467_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I2(_1036_[2]), + .O(_1042_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2468_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .O(_1036_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff80) + ) _2469_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .I3(_1130_[3]), + .O(\corescorecore.core_1.serving.ram.we ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2470_ ( + .I0(_1007_[0]), + .I1(_1027_[3]), + .I2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .I3(_0994_), + .O(_1130_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2471_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.o_waddr [0]), + .I1(\corescorecore.core_1.serving.ram.bsel [0]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.waddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2472_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.o_waddr [1]), + .I1(\corescorecore.core_1.serving.ram.bsel [1]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.waddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2473_ ( + .I0(\corescorecore.core_1.serving.ram.wb_en ), + .I1(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [0]), + .I3(_1044_[3]), + .O(\corescorecore.core_1.serving.ram.waddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2474_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(_1007_[0]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(_1044_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2475_ ( + .I0(\corescorecore.core_1.serving.ram.wb_en ), + .I1(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [1]), + .I3(_1140_[3]), + .O(\corescorecore.core_1.serving.ram.waddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2476_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(_1007_[0]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(_1140_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2477_ ( + .I0(\corescorecore.core_1.serving.ram.wb_en ), + .I1(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [2]), + .I3(_1136_[3]), + .O(\corescorecore.core_1.serving.ram.waddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2478_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(_1007_[0]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(_1136_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2479_ ( + .I0(\corescorecore.core_1.serving.ram.wb_en ), + .I1(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(_1037_[3]), + .O(\corescorecore.core_1.serving.ram.waddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2480_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(_1007_[0]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(_1037_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2481_ ( + .I0(\corescorecore.core_1.serving.ram.wb_en ), + .I1(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [4]), + .I3(_1035_[3]), + .O(\corescorecore.core_1.serving.ram.waddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2482_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(_1007_[0]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(_1035_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2483_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [0]), + .I2(_0995_[0]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2484_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [1]), + .I2(_0995_[1]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2485_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [2]), + .I2(_0995_[2]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2486_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [3]), + .I2(_0995_[3]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2487_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [4]), + .I2(_0995_[4]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2488_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [5]), + .I2(_0995_[5]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2489_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [6]), + .I2(_0995_[6]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb0ff) + ) _2490_ ( + .I0(_1280_[0]), + .I1(_1280_[1]), + .I2(_1120_[3]), + .I3(_1280_[3]), + .O(\corescorecore.core_1.serving.cpu.o_wdata0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6900) + ) _2491_ ( + .I0(_1139_[0]), + .I1(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_1.serving.cpu.alu.add_cy_r ), + .I3(_1139_[3]), + .O(_1280_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7d82) + ) _2492_ ( + .I0(_1034_[0]), + .I1(_1034_[1]), + .I2(\corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0905_), + .O(_1139_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2493_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_sh_signed ), + .O(_1034_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _2494_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .O(_1139_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000d) + ) _2495_ ( + .I0(_1135_[0]), + .I1(_1135_[1]), + .I2(_1135_[2]), + .I3(_1135_[3]), + .O(_1280_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6000) + ) _2496_ ( + .I0(_1134_[0]), + .I1(_1051_[0]), + .I2(_1028_[3]), + .I3(\corescorecore.core_1.serving.cpu.ctrl.en_pc_r ), + .O(_1135_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2497_ ( + .I0(_1030_[0]), + .I1(\corescorecore.core_1.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .O(_1134_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _2498_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .I2(_1029_[2]), + .I3(\corescorecore.core_1.serving.cpu.ctrl.pc ), + .O(_1030_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3e) + ) _2499_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [1]), + .O(_1029_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _2500_ ( + .I0(_1033_[1]), + .I1(_1033_[0]), + .I2(_1050_[2]), + .I3(_1050_[3]), + .O(_1051_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2501_ ( + .I0(_1028_[3]), + .I1(\corescorecore.core_1.serving.cpu.alu.i_buf ), + .O(_1050_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2502_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .O(_1028_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf800) + ) _2503_ ( + .I0(\corescorecore.core_1.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .I2(\corescorecore.core_1.serving.cpu.mem_bytecnt [1]), + .I3(_1028_[3]), + .O(_1050_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2504_ ( + .I0(_1132_[0]), + .I1(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .O(_1135_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _2505_ ( + .I0(_1131_[0]), + .I1(\corescorecore.core_1.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_1.serving.cpu.ctrl.pc_plus_4_cy_r ), + .O(_1132_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2506_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [2]), + .I2(_1031_[2]), + .O(_1131_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0fbb) + ) _2507_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_1.serving.cpu.mem_if.signbit ), + .I2(\corescorecore.core_1.serving.cpu.mem_if.dat_cur ), + .I3(\corescorecore.core_1.serving.cpu.mem_if.dat_valid ), + .O(_1135_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hbf00) + ) _2508_ ( + .I0(_1137_[3]), + .I1(_1279_[1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I3(_1279_[3]), + .O(_1280_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h007f) + ) _2509_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.result_lt_r ), + .I1(_1034_[1]), + .I2(_1127_[1]), + .I3(_1138_[3]), + .O(_1279_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hca00) + ) _2510_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.shift.signbit ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_buf ), + .I2(_1137_[2]), + .I3(_1137_[3]), + .O(_1138_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2511_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_1.serving.cpu.alu.shift.wrapped ), + .O(_1137_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2512_ ( + .I0(_1278_[0]), + .I1(_1278_[1]), + .I2(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .O(_1279_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2513_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_1.serving.cpu.o_wdata0 ), + .I2(_0995_[7]), + .I3(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.wdata [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2514_ ( + .I0(\corescorecore.core_1.serving.raddr [0]), + .I1(\corescorecore.core_1.serving.ram.bsel [0]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.raddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2515_ ( + .I0(\corescorecore.core_1.serving.raddr [1]), + .I1(\corescorecore.core_1.serving.ram.bsel [1]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .O(\corescorecore.core_1.serving.ram.raddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2516_ ( + .I0(_1044_[3]), + .I1(_1282_[1]), + .O(\corescorecore.core_1.serving.ram.raddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2517_ ( + .I0(\corescorecore.core_1.serving.cpu.csr_imm ), + .I1(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [0]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .I3(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_1282_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2518_ ( + .I0(_1140_[3]), + .I1(_1276_[1]), + .O(\corescorecore.core_1.serving.ram.raddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2519_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [1]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .I3(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_1276_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2520_ ( + .I0(_1136_[3]), + .I1(_1314_[1]), + .O(\corescorecore.core_1.serving.ram.raddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2521_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [2]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .I3(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_1314_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2522_ ( + .I0(_1037_[3]), + .I1(_1281_[1]), + .O(\corescorecore.core_1.serving.ram.raddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2523_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [3]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .I3(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_1281_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2524_ ( + .I0(_1035_[3]), + .I1(_1274_[1]), + .O(\corescorecore.core_1.serving.ram.raddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2525_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [4]), + .I2(\corescorecore.core_1.serving.ram.wb_en ), + .I3(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .O(_1274_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2526_ ( + .I0(_1315_[0]), + .I1(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [0]), + .O(_0858_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h7) + ) _2527_ ( + .I0(\clkgen.i_rstn ), + .I1(\clkgen.usr_pll_lock_1 ), + .O(_1277_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _2528_ ( + .I0(_1277_[0]), + .I1(\clkgen.rst_reg1 ), + .O(_0333_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2529_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm11_7 [1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0477_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2530_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [8]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm11_7 [2]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0478_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2531_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [9]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm11_7 [3]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0479_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2532_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [10]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm11_7 [4]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0480_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2533_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [11]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0481_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2534_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm24_20 [1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0491_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2535_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [21]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm24_20 [2]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0492_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2536_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [22]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm24_20 [3]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0493_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2537_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [23]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm24_20 [4]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0494_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2538_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm30_25 [0]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0495_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2539_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [25]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm30_25 [1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0496_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2540_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [26]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm30_25 [2]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0497_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2541_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [27]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm30_25 [3]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0498_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2542_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [28]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm30_25 [4]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0499_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2543_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [29]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm30_25 [5]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0500_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2544_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [7]), + .I1(\corescorecore.core_0.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0502_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2545_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [20]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0482_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2546_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [12]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [2]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0483_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2547_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [13]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [3]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0484_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2548_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [14]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [4]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0485_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2549_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [15]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [5]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0486_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2550_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [16]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [6]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0487_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2551_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [17]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [7]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0488_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2552_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [18]), + .I1(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [8]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0489_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3a) + ) _2553_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1141_[1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0490_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2554_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.imm24_20 [0]), + .I1(\corescorecore.core_0.serving.cpu.decode.signbit ), + .I2(\corescorecore.core_0.serving.cpu.decode.m3 ), + .O(_1141_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2555_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(_1074_[1]), + .I2(_1074_[2]), + .O(_0503_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2556_ ( + .I0(\corescorecore.core_0.serving.cpu.csr_imm ), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [15]), + .I2(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .O(_1074_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2557_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I3(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .O(_1074_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2558_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(_1275_[1]), + .I2(_1074_[2]), + .O(_0504_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2559_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [16]), + .I2(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .O(_1275_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2560_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(_1142_[1]), + .I2(_1074_[2]), + .O(_0505_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2561_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [17]), + .I2(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .O(_1142_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2562_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(_1316_[1]), + .I2(_1074_[2]), + .O(_0506_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2563_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [18]), + .I2(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .O(_1316_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2564_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [19]), + .I2(_1074_[2]), + .I3(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .O(_0507_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2565_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0013_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2566_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tvalid_reg ), + .I1(_1162_[0]), + .I2(\clkgen.o_rst_core ), + .I3(_1283_[3]), + .O(_0336_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hca00) + ) _2567_ ( + .I0(_1161_[0]), + .I1(_1059_[0]), + .I2(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .I3(_1161_[3]), + .O(_1162_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2568_ ( + .I0(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .I1(\corescorecore.axis_mux.arb_inst.grant_valid ), + .O(_1161_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h2c) + ) _2569_ ( + .I0(\corescorecore.axis_mux.m_axis_tvalid ), + .I1(\corescorecore.axis_mux.m_axis_tready ), + .I2(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .O(_1283_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _2570_ ( + .I0(_1073_[0]), + .I1(_1073_[1]), + .I2(\corescorecore.core_0.serving.cpu.bufreg.c_r ), + .O(\corescorecore.core_0.serving.cpu.bufreg.q ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000e) + ) _2571_ ( + .I0(_1017_[0]), + .I1(_1017_[1]), + .I2(_1072_[2]), + .I3(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .O(_1073_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2572_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(_1071_[2]), + .I3(\corescorecore.core_0.serving.cpu.decode.m3 ), + .O(_1072_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2573_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt_r [0]), + .I2(_1070_[2]), + .O(_1071_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2574_ ( + .I0(\corescorecore.core_0.serving.cpu.mem_bytecnt [1]), + .I1(\corescorecore.core_0.serving.cpu.mem_bytecnt [0]), + .O(_1070_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4f00) + ) _2575_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [1]), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .O(_1073_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2576_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_buf ), + .I1(\corescorecore.core_0.serving.cpu.bufreg.q ), + .I2(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I3(_1011_[0]), + .O(_0474_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h41be) + ) _2577_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I1(_1071_[2]), + .I2(\corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0878_), + .O(\corescorecore.core_0.serving.cpu.alu.shamt_ser ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2578_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [0]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [1]), + .O(_0508_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2579_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [1]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [2]), + .O(_0519_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2580_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [2]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [3]), + .O(_0530_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2581_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [3]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [4]), + .O(_0533_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2582_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [4]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [5]), + .O(_0534_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2583_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [5]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [6]), + .O(_0535_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2584_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [6]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.axis_mux.s_axis_tdata [7]), + .O(_0536_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2585_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [7]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.o_tlast ), + .O(_0537_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2586_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [8]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .O(_0538_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2587_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [9]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .O(_0539_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2588_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [10]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .O(_0509_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2589_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [11]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .O(_0510_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2590_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [12]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .O(_0511_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2591_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [13]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .O(_0512_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2592_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [14]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .O(_0513_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2593_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [15]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .O(_0514_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2594_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [16]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .O(_0515_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2595_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [17]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .O(_0516_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2596_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [18]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .O(_0517_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2597_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [19]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .O(_0518_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2598_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [20]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .O(_0520_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2599_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [21]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .O(_0521_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2600_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [22]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .O(_0522_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2601_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [23]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .O(_0523_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2602_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .O(_0524_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2603_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [25]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .O(_0525_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2604_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [26]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .O(_0526_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2605_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [27]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .O(_0527_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2606_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [28]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .O(_0528_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2607_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [29]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .O(_0529_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf888) + ) _2608_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1004_[3]), + .I2(_1005_[2]), + .I3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .O(_0531_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8f88) + ) _2609_ ( + .I0(_1004_[3]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31]), + .I2(_1017_[2]), + .I3(_1005_[2]), + .O(_0532_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0b) + ) _2610_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_0.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_0.serving.cpu.mem_bytecnt [1]), + .I3(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_0.serving.cpu.mem_if.dat_valid ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff80) + ) _2611_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.wen0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wtrig0 ), + .I2(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .I3(_1250_[3]), + .O(\corescorecore.core_0.serving.ram.we ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2612_ ( + .I0(_1003_[0]), + .I1(_1067_[3]), + .I2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .I3(_0992_), + .O(_1250_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2613_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.o_waddr [0]), + .I1(\corescorecore.core_0.serving.ram.bsel [0]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.waddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2614_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.o_waddr [1]), + .I1(\corescorecore.core_0.serving.ram.bsel [1]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.waddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2615_ ( + .I0(\corescorecore.core_0.serving.ram.wb_en ), + .I1(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [0]), + .I3(_1166_[3]), + .O(\corescorecore.core_0.serving.ram.waddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2616_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(_1003_[0]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(_1166_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2617_ ( + .I0(\corescorecore.core_0.serving.ram.wb_en ), + .I1(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [1]), + .I3(_1248_[3]), + .O(\corescorecore.core_0.serving.ram.waddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2618_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(_1003_[0]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(_1248_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2619_ ( + .I0(\corescorecore.core_0.serving.ram.wb_en ), + .I1(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [2]), + .I3(_1165_[0]), + .O(\corescorecore.core_0.serving.ram.waddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2620_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(_1003_[0]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(_1165_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2621_ ( + .I0(\corescorecore.core_0.serving.ram.wb_en ), + .I1(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(_1164_[3]), + .O(\corescorecore.core_0.serving.ram.waddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2622_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(_1003_[0]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(_1164_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00ef) + ) _2623_ ( + .I0(\corescorecore.core_0.serving.ram.wb_en ), + .I1(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [4]), + .I3(_1167_[0]), + .O(\corescorecore.core_0.serving.ram.waddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3500) + ) _2624_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(_1003_[0]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(_1167_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2625_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [0]), + .I2(_0993_[0]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2626_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [1]), + .I2(_0993_[1]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2627_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [2]), + .I2(_0993_[2]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2628_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [3]), + .I2(_0993_[3]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2629_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [4]), + .I2(_0993_[4]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2630_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [5]), + .I2(_0993_[5]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2631_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [6]), + .I2(_0993_[6]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb0ff) + ) _2632_ ( + .I0(_1158_[0]), + .I1(_1158_[1]), + .I2(_1011_[0]), + .I3(_1158_[3]), + .O(\corescorecore.core_0.serving.cpu.o_wdata0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6900) + ) _2633_ ( + .I0(_1157_[0]), + .I1(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_0.serving.cpu.alu.add_cy_r ), + .I3(_1157_[3]), + .O(_1158_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h7d82) + ) _2634_ ( + .I0(_1156_[0]), + .I1(_1071_[2]), + .I2(\corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy_r ), + .I3(_0878_), + .O(_1157_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2635_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_sh_signed ), + .O(_1156_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h01) + ) _2636_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .O(_1157_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h000d) + ) _2637_ ( + .I0(_1015_[0]), + .I1(_1155_[1]), + .I2(_1155_[2]), + .I3(_1155_[3]), + .O(_1158_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h6000) + ) _2638_ ( + .I0(_1153_[0]), + .I1(_1153_[1]), + .I2(_1149_[3]), + .I3(\corescorecore.core_0.serving.cpu.ctrl.en_pc_r ), + .O(_1155_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2639_ ( + .I0(_1152_[0]), + .I1(\corescorecore.core_0.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .O(_1153_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h1f00) + ) _2640_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .I2(_1151_[2]), + .I3(\corescorecore.core_0.serving.cpu.ctrl.pc ), + .O(_1152_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h3e) + ) _2641_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [1]), + .O(_1151_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _2642_ ( + .I0(_1017_[1]), + .I1(_1017_[0]), + .I2(_1150_[2]), + .I3(_1150_[3]), + .O(_1153_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2643_ ( + .I0(_1149_[3]), + .I1(\corescorecore.core_0.serving.cpu.alu.i_buf ), + .O(_1150_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2644_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .O(_1149_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf800) + ) _2645_ ( + .I0(\corescorecore.core_0.serving.cpu.mem_bytecnt [0]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .I2(\corescorecore.core_0.serving.cpu.mem_bytecnt [1]), + .I3(_1149_[3]), + .O(_1150_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2646_ ( + .I0(_1154_[0]), + .I1(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .O(_1155_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h96) + ) _2647_ ( + .I0(_1143_[0]), + .I1(\corescorecore.core_0.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_0.serving.cpu.ctrl.pc_plus_4_cy_r ), + .O(_1154_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2648_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt_r [2]), + .I2(_1070_[2]), + .O(_1143_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0fbb) + ) _2649_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_0.serving.cpu.mem_if.signbit ), + .I2(\corescorecore.core_0.serving.cpu.mem_if.dat_cur ), + .I3(\corescorecore.core_0.serving.cpu.mem_if.dat_valid ), + .O(_1155_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hbf00) + ) _2650_ ( + .I0(_1011_[1]), + .I1(_1147_[1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I3(_1147_[3]), + .O(_1158_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h007f) + ) _2651_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.result_lt_r ), + .I1(_1071_[2]), + .I2(_1010_[1]), + .I3(_1145_[3]), + .O(_1147_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hca00) + ) _2652_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.shift.signbit ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_buf ), + .I2(_1144_[2]), + .I3(_1011_[1]), + .O(_1145_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2653_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_0.serving.cpu.alu.shift.wrapped ), + .O(_1144_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hac) + ) _2654_ ( + .I0(_1146_[0]), + .I1(_1146_[1]), + .I2(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .O(_1147_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf044) + ) _2655_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .I1(\corescorecore.core_0.serving.cpu.o_wdata0 ), + .I2(_0993_[7]), + .I3(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.wdata [7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2656_ ( + .I0(\corescorecore.core_0.serving.raddr [0]), + .I1(\corescorecore.core_0.serving.ram.bsel [0]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.raddr [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hc5) + ) _2657_ ( + .I0(\corescorecore.core_0.serving.raddr [1]), + .I1(\corescorecore.core_0.serving.ram.bsel [1]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .O(\corescorecore.core_0.serving.ram.raddr [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2658_ ( + .I0(_1166_[3]), + .I1(_1317_[1]), + .O(\corescorecore.core_0.serving.ram.raddr [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2659_ ( + .I0(\corescorecore.core_0.serving.cpu.csr_imm ), + .I1(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [0]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .I3(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_1317_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2660_ ( + .I0(_1248_[3]), + .I1(_1249_[1]), + .O(\corescorecore.core_0.serving.ram.raddr [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2661_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [1]), + .I1(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [1]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .I3(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_1249_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2662_ ( + .I0(_1165_[0]), + .I1(_1165_[1]), + .O(\corescorecore.core_0.serving.ram.raddr [4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2663_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [2]), + .I1(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [2]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .I3(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_1165_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2664_ ( + .I0(_1164_[3]), + .I1(_1318_[1]), + .O(\corescorecore.core_0.serving.ram.raddr [5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2665_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [3]), + .I1(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [3]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .I3(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_1318_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2666_ ( + .I0(_1167_[0]), + .I1(_1167_[1]), + .O(\corescorecore.core_0.serving.ram.raddr [6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2667_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [4]), + .I1(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [4]), + .I2(\corescorecore.core_0.serving.ram.wb_en ), + .I3(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_1167_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2668_ ( + .I0(_1160_[0]), + .I1(\clkgen.o_rst_core ), + .O(_0337_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0777) + ) _2669_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant [0]), + .I2(_1063_[3]), + .I3(_1159_[3]), + .O(_1160_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2670_ ( + .I0(\corescorecore.core_1.serving.cpu.ctrl.pc ), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0209_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2671_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0210_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2672_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0211_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2673_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0213_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f4) + ) _2674_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\corescorecore.axis_mux.m_axis_tvalid ), + .I2(_1247_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0335_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcec0) + ) _2675_ ( + .I0(\corescorecore.axis_mux.temp_m_axis_tvalid_reg ), + .I1(_1162_[0]), + .I2(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .I3(\corescorecore.axis_mux.m_axis_tready ), + .O(_1247_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2676_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0214_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2677_ ( + .I0(_1163_[0]), + .I1(\clkgen.o_rst_core ), + .O(_0334_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f8) + ) _2678_ ( + .I0(_1162_[0]), + .I1(\corescorecore.axis_mux.m_axis_tvalid ), + .I2(\corescorecore.axis_mux.temp_m_axis_tvalid_reg ), + .I3(\corescorecore.axis_mux.m_axis_tready ), + .O(_1163_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2679_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.o_waddr [1]), + .I1(_0902_[4]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .O(_0325_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2680_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.o_waddr [0]), + .I1(_0902_[3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .O(_0324_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2681_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .I1(_0899_[1]), + .O(_0317_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2682_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .I1(_0899_[4]), + .O(_0320_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2683_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31]), + .I1(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_0313_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2684_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(_0881_[5]), + .O(_0312_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2685_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I1(_0881_[4]), + .O(_0311_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2686_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0215_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2687_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I1(_1189_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0306_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2688_ ( + .I0(_1154_[0]), + .I1(_1188_[1]), + .I2(\corescorecore.core_0.serving.cpu.ctrl.i_jump ), + .O(_1189_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _2689_ ( + .I0(_1153_[0]), + .I1(_1153_[1]), + .I2(\corescorecore.core_0.serving.cpu.ctrl.en_pc_r ), + .O(_1188_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2690_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0216_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2691_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0217_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f8) + ) _2692_ ( + .I0(_1062_[1]), + .I1(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .I2(_1186_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0343_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hf400) + ) _2693_ ( + .I0(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .I1(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [0]), + .I2(_1117_[0]), + .I3(_1063_[3]), + .O(_1186_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2694_ ( + .I0(\corescorecore.axis_mux.arb_inst.masked_request_index [1]), + .I1(_1117_[0]), + .O(_0862_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2695_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0298_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2696_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0289_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2697_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0281_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2698_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I2(\clkgen.o_rst_core ), + .I3(_1002_[0]), + .O(_0277_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2699_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt_r [1]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt_r [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0270_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfcfa) + ) _2700_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt_r [0]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt_r [3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0269_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2701_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0219_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2702_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0220_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2703_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.wcnt [2]), + .I1(_0923_[2]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .O(_0258_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2704_ ( + .I0(\corescorecore.core_1.serving.rf_ram_if.wcnt [1]), + .I1(_0923_[1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .O(_0257_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2705_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0221_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2706_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0222_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2707_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0223_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2708_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .I1(_0920_[4]), + .O(_0255_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2709_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0224_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2710_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .I1(_1175_[1]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0240_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h35) + ) _2711_ ( + .I0(_1132_[0]), + .I1(_1172_[1]), + .I2(\corescorecore.core_1.serving.cpu.ctrl.i_jump ), + .O(_1175_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _2712_ ( + .I0(_1134_[0]), + .I1(_1051_[0]), + .I2(\corescorecore.core_1.serving.cpu.ctrl.en_pc_r ), + .O(_1172_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2713_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0226_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2714_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0218_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfff4) + ) _2715_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_ack ), + .I1(\corescorecore.core_1.serving.cpu.ctrl.en_pc_r ), + .I2(_1006_[0]), + .I3(\clkgen.o_rst_core ), + .O(_0208_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2716_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0212_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2717_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(\clkgen.o_rst_core ), + .I3(_1081_[0]), + .O(_0365_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2718_ ( + .I0(\corescorecore.core_1.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0207_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f4) + ) _2719_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_1.serving.cpu.ctrl.i_jump ), + .I2(_1183_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0202_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'heb00) + ) _2720_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I1(_1181_[1]), + .I2(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .I3(_1181_[3]), + .O(_1183_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3335) + ) _2721_ ( + .I0(_1180_[0]), + .I1(\corescorecore.core_1.serving.cpu.alu.result_lt ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .O(_1181_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _2722_ ( + .I0(_0905_), + .I1(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_1.serving.cpu.alu.eq_r ), + .O(_1180_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2723_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I2(_1178_[2]), + .O(_1181_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2724_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_init ), + .O(_1178_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2725_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I1(_1174_[1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .I3(_1174_[3]), + .O(_0200_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2726_ ( + .I0(\corescorecore.core_1.serving.cpu.state.stage_two_pending ), + .I1(\corescorecore.core_1.serving.cpu.i_rf_ready ), + .O(_1174_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _2727_ ( + .I0(_1169_[2]), + .I1(_1135_[0]), + .I2(_1170_[0]), + .O(_1174_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2728_ ( + .I0(\emitter.cnt [9]), + .I1(\emitter.data [1]), + .O(_0195_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f8) + ) _2729_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\corescorecore.axis_mux.m_axis_tvalid ), + .I2(\emitter.data [9]), + .I3(\emitter.cnt [9]), + .O(_0332_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2730_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0225_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2731_ ( + .I0(\corescorecore.core_2.serving.rf_ram_if.o_waddr [1]), + .I1(_0946_[4]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .O(_0193_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2732_ ( + .I0(\clkgen.o_rst_core ), + .I1(_1057_[1]), + .I2(_1045_[1]), + .I3(_1025_[2]), + .O(_0180_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2733_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0168_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2734_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0162_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2735_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0161_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2736_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata1 [1]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_0391_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2737_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata1 [2]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_0392_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2738_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata1 [3]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_0393_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2739_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata1 [4]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_0394_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2740_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata1 [5]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_0395_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2741_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata1 [6]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .O(_0396_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2742_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0156_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2743_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0151_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2744_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0146_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2745_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .I2(\clkgen.o_rst_core ), + .I3(_1095_[0]), + .O(_0145_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2746_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0228_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfafc) + ) _2747_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt_r [3]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [0]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0136_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h00f4) + ) _2748_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .I1(\corescorecore.core_2.serving.cpu.ctrl.i_jump ), + .I2(_1320_[2]), + .I3(\clkgen.o_rst_core ), + .O(_0135_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'heb00) + ) _2749_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I1(_1187_[1]), + .I2(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .I3(_1187_[3]), + .O(_1320_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h3335) + ) _2750_ ( + .I0(_1185_[0]), + .I1(\corescorecore.core_2.serving.cpu.alu.result_lt ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .O(_1187_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h60) + ) _2751_ ( + .I0(_0924_), + .I1(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_2.serving.cpu.alu.eq_r ), + .O(_1185_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h40) + ) _2752_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I2(_1173_[2]), + .O(_1187_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2753_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .O(_1173_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2754_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0227_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2755_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0229_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2756_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0231_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2757_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0232_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0e) + ) _2758_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_en ), + .I1(\corescorecore.core_2.serving.cpu.i_rf_ready ), + .I2(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .O(_0134_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2759_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0230_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h10) + ) _2760_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\emitter.cnt [9]), + .I2(_0874_[9]), + .O(_0128_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0eee) + ) _2761_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .I1(\corescorecore.core_3.serving.rf_ram_if.wreq_r ), + .I2(_1182_[2]), + .I3(\corescorecore.core_3.serving.rf_ram_if.o_waddr [1]), + .O(_0118_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2762_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.wcnt [0]), + .I1(\corescorecore.core_3.serving.rf_ram_if.wcnt [2]), + .I2(\corescorecore.core_3.serving.rf_ram_if.o_waddr [0]), + .I3(\corescorecore.core_3.serving.rf_ram_if.wcnt [1]), + .O(_1182_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hfe) + ) _2763_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\emitter.cnt [9]), + .I2(_0874_[2]), + .O(_0121_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2764_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.o_waddr [0]), + .I1(_0956_[3]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .O(_0116_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2765_ ( + .I0(\corescorecore.core_3.serving.rf_ram_if.wcnt [1]), + .I1(_0956_[1]), + .I2(\clkgen.o_rst_core ), + .I3(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .O(_0114_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2766_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata0 [1]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_0384_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2767_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata0 [2]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [25]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_0385_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2768_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata0 [3]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [26]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_0386_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2769_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata0 [4]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [27]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_0387_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2770_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata0 [5]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [28]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_0388_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2771_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata0 [6]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [29]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_0389_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2772_ ( + .I0(\corescorecore.core_0.serving.rf_ram_if.rdata0 [7]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .I2(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .O(_0390_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2773_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0082_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2774_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .I2(\clkgen.o_rst_core ), + .I3(_1089_[0]), + .O(_0081_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0c0a) + ) _2775_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .I2(\clkgen.o_rst_core ), + .I3(_1006_[0]), + .O(_0233_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2776_ ( + .I0(\corescorecore.axis_mux.m_axis_tvalid ), + .I1(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .I2(\corescorecore.axis_mux.m_axis_tready ), + .O(_0012_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h4f) + ) _2777_ ( + .I0(\corescorecore.core_0.serving.cpu.mem_if.tmp [2]), + .I1(\corescorecore.core_0.serving.cpu.alu.i_en ), + .I2(_1005_[2]), + .O(_0010_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _2778_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0011_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h4f) + ) _2779_ ( + .I0(\corescorecore.core_1.serving.cpu.mem_if.tmp [2]), + .I1(\corescorecore.core_1.serving.cpu.alu.i_en ), + .I2(_1009_[2]), + .O(_0008_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _2780_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0009_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _2781_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0007_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h4f) + ) _2782_ ( + .I0(\corescorecore.core_2.serving.cpu.mem_if.tmp [2]), + .I1(\corescorecore.core_2.serving.cpu.alu.i_en ), + .I2(_1104_[1]), + .O(_0006_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _2783_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0003_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h4f) + ) _2784_ ( + .I0(\corescorecore.core_4.serving.cpu.mem_if.tmp [2]), + .I1(\corescorecore.core_4.serving.cpu.alu.i_en ), + .I2(_1255_[1]), + .O(_0002_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h4f) + ) _2785_ ( + .I0(\corescorecore.core_3.serving.cpu.mem_if.tmp [2]), + .I1(\corescorecore.core_3.serving.cpu.alu.i_en ), + .I2(_1092_[1]), + .O(_0004_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _2786_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0005_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2787_ ( + .I0(\corescorecore.core_4.serving.ram.bsel [1]), + .I1(\corescorecore.core_4.serving.ram.bsel [0]), + .O(_0374_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2788_ ( + .I0(\corescorecore.core_4.serving.ram.bsel [0]), + .I1(\corescorecore.core_4.serving.ram.bsel [1]), + .O(_0375_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h7) + ) _2789_ ( + .I0(\corescorecore.core_4.serving.ram.bsel [0]), + .I1(\corescorecore.core_4.serving.ram.bsel [1]), + .O(_1202_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2790_ ( + .I0(\corescorecore.core_3.serving.ram.bsel [1]), + .I1(\corescorecore.core_3.serving.ram.bsel [0]), + .O(_0376_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2791_ ( + .I0(\corescorecore.core_3.serving.ram.bsel [0]), + .I1(\corescorecore.core_3.serving.ram.bsel [1]), + .O(_0377_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h7) + ) _2792_ ( + .I0(\corescorecore.core_3.serving.ram.bsel [0]), + .I1(\corescorecore.core_3.serving.ram.bsel [1]), + .O(_1194_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2793_ ( + .I0(\corescorecore.core_2.serving.ram.bsel [1]), + .I1(\corescorecore.core_2.serving.ram.bsel [0]), + .O(_0378_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2794_ ( + .I0(\corescorecore.core_2.serving.ram.bsel [0]), + .I1(\corescorecore.core_2.serving.ram.bsel [1]), + .O(_0379_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h7) + ) _2795_ ( + .I0(\corescorecore.core_2.serving.ram.bsel [0]), + .I1(\corescorecore.core_2.serving.ram.bsel [1]), + .O(_1213_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf8) + ) _2796_ ( + .I0(\corescorecore.axis_mux.m_axis_tready ), + .I1(\corescorecore.axis_mux.m_axis_tvalid ), + .I2(\emitter.cnt [9]), + .O(_0001_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2797_ ( + .I0(\corescorecore.core_1.serving.ram.bsel [1]), + .I1(\corescorecore.core_1.serving.ram.bsel [0]), + .O(_0380_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2798_ ( + .I0(\corescorecore.core_1.serving.ram.bsel [0]), + .I1(\corescorecore.core_1.serving.ram.bsel [1]), + .O(_0381_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h7) + ) _2799_ ( + .I0(\corescorecore.core_1.serving.ram.bsel [0]), + .I1(\corescorecore.core_1.serving.ram.bsel [1]), + .O(_1246_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2800_ ( + .I0(\corescorecore.core_0.serving.ram.bsel [1]), + .I1(\corescorecore.core_0.serving.ram.bsel [0]), + .O(_0382_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2801_ ( + .I0(\corescorecore.core_0.serving.ram.bsel [0]), + .I1(\corescorecore.core_0.serving.ram.bsel [1]), + .O(_0383_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h7) + ) _2802_ ( + .I0(\corescorecore.core_0.serving.ram.bsel [0]), + .I1(\corescorecore.core_0.serving.ram.bsel [1]), + .O(_1219_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2803_ ( + .I0(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .I1(\corescorecore.core_4.serving.cpu.bufreg.o_lsb [0]), + .O(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2804_ ( + .I0(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .I1(\corescorecore.core_3.serving.cpu.bufreg.o_lsb [0]), + .O(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2805_ ( + .I0(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .I1(\corescorecore.core_2.serving.cpu.bufreg.o_lsb [0]), + .O(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2806_ ( + .I0(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .I1(\corescorecore.core_1.serving.cpu.bufreg.o_lsb [0]), + .O(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h1) + ) _2807_ ( + .I0(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .I1(\corescorecore.core_0.serving.cpu.bufreg.o_lsb [0]), + .O(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2808_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_4.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_4.serving.cpu.mem_bytecnt [1]), + .I3(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .O(_0848_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0b) + ) _2809_ ( + .I0(\corescorecore.core_4.serving.cpu.state.stage_two_req ), + .I1(_1196_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(\corescorecore.core_4.serving.cpu.bufreg_hold ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0b00) + ) _2810_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [2]), + .I1(_1191_[1]), + .I2(_1191_[2]), + .I3(_1081_[0]), + .O(\corescorecore.core_4.serving.cpu.o_wen0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _2811_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [0]), + .I1(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [1]), + .I2(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [4]), + .O(_1191_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2812_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_4.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .O(_1191_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd000) + ) _2813_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_4.serving.cpu.state.o_cnt_r [0]), + .I2(_1203_[2]), + .I3(\corescorecore.core_4.serving.cpu.alu.i_init ), + .O(\corescorecore.core_4.serving.cpu.alu.i_shamt_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2814_ ( + .I0(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_4.serving.cpu.alu.i_init ), + .I2(\corescorecore.core_4.serving.cpu.state.o_cnt_r [1]), + .I3(_1203_[2]), + .O(_0781_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2815_ ( + .I0(_1204_[1]), + .I1(\corescorecore.core_4.serving.cpu.alu.i_init ), + .O(_0780_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2816_ ( + .I0(_1263_[0]), + .I1(_1263_[1]), + .I2(\corescorecore.core_4.serving.cpu.bufreg.c_r ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_init ), + .O(_0779_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2817_ ( + .I0(_1210_[0]), + .I1(_1210_[1]), + .I2(\corescorecore.core_4.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .I3(_1081_[0]), + .O(_0784_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2818_ ( + .I0(_1206_[0]), + .I1(\corescorecore.core_4.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_4.serving.cpu.ctrl.pc_plus_4_cy_r ), + .I3(_1081_[0]), + .O(_0783_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2819_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_sh_signed ), + .I2(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .O(_0778_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2820_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_4.serving.cpu.alu.shamt_msb ), + .I2(\corescorecore.core_4.serving.cpu.alu.shift.cnt [5]), + .O(_0777_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2821_ ( + .I0(_1041_[0]), + .I1(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0775_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2822_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.result_lt ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0776_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'he8) + ) _2823_ ( + .I0(_0931_), + .I1(_1204_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy_r ), + .O(\corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2824_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy ), + .I1(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0774_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd400) + ) _2825_ ( + .I0(_1205_[0]), + .I1(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_4.serving.cpu.alu.add_cy_r ), + .I3(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0773_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0e) + ) _2826_ ( + .I0(\corescorecore.core_4.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2827_ ( + .I0(\corescorecore.core_4.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .I2(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _2828_ ( + .I0(\corescorecore.core_4.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2829_ ( + .I0(_1202_[0]), + .I1(\corescorecore.core_4.serving.ram.wb_en ), + .O(_0849_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2830_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_3.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_3.serving.cpu.mem_bytecnt [1]), + .I3(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .O(_0771_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0b) + ) _2831_ ( + .I0(\corescorecore.core_3.serving.cpu.state.stage_two_req ), + .I1(_1087_[2]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(\corescorecore.core_3.serving.cpu.bufreg_hold ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0b00) + ) _2832_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [2]), + .I1(_1321_[1]), + .I2(_1321_[2]), + .I3(_1089_[0]), + .O(\corescorecore.core_3.serving.cpu.o_wen0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _2833_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [0]), + .I1(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [1]), + .I2(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [4]), + .O(_1321_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2834_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_3.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .O(_1321_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd000) + ) _2835_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [0]), + .I2(_1129_[2]), + .I3(\corescorecore.core_3.serving.cpu.alu.i_init ), + .O(\corescorecore.core_3.serving.cpu.alu.i_shamt_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2836_ ( + .I0(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_3.serving.cpu.state.o_cnt_r [1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_init ), + .I3(_1129_[2]), + .O(_0704_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2837_ ( + .I0(_1190_[0]), + .I1(\corescorecore.core_3.serving.cpu.alu.i_init ), + .O(_0703_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2838_ ( + .I0(_1305_[0]), + .I1(_1305_[1]), + .I2(\corescorecore.core_3.serving.cpu.bufreg.c_r ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_init ), + .O(_0702_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2839_ ( + .I0(_1125_[1]), + .I1(_1124_[0]), + .I2(\corescorecore.core_3.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .I3(_1089_[0]), + .O(_0707_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2840_ ( + .I0(_1198_[0]), + .I1(\corescorecore.core_3.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_3.serving.cpu.ctrl.pc_plus_4_cy_r ), + .I3(_1089_[0]), + .O(_0706_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2841_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_sh_signed ), + .I2(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .O(_0701_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2842_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_3.serving.cpu.alu.shamt_msb ), + .I2(\corescorecore.core_3.serving.cpu.alu.shift.cnt [5]), + .O(_0700_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2843_ ( + .I0(_1245_[0]), + .I1(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0698_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2844_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.result_lt ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0699_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'he8) + ) _2845_ ( + .I0(_0950_), + .I1(_1190_[0]), + .I2(\corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy_r ), + .O(\corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2846_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy ), + .I1(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0697_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd400) + ) _2847_ ( + .I0(_1244_[0]), + .I1(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_3.serving.cpu.alu.add_cy_r ), + .I3(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0696_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0e) + ) _2848_ ( + .I0(\corescorecore.core_3.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2849_ ( + .I0(\corescorecore.core_3.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .I2(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _2850_ ( + .I0(\corescorecore.core_3.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .I2(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2851_ ( + .I0(_1194_[0]), + .I1(\corescorecore.core_3.serving.ram.wb_en ), + .O(_0772_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2852_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_2.serving.cpu.mem_bytecnt [0]), + .I2(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .I3(\corescorecore.core_2.serving.cpu.mem_bytecnt [1]), + .O(_0694_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0b) + ) _2853_ ( + .I0(\corescorecore.core_2.serving.cpu.state.stage_two_req ), + .I1(_1103_[2]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(\corescorecore.core_2.serving.cpu.bufreg_hold ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0b00) + ) _2854_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [2]), + .I1(_1228_[1]), + .I2(_1228_[2]), + .I3(_1095_[0]), + .O(\corescorecore.core_2.serving.cpu.o_wen0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _2855_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [0]), + .I1(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [1]), + .I2(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [4]), + .O(_1228_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2856_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_2.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .O(_1228_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd000) + ) _2857_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [0]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I3(_1214_[2]), + .O(\corescorecore.core_2.serving.cpu.alu.i_shamt_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2858_ ( + .I0(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_2.serving.cpu.state.o_cnt_r [1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_init ), + .I3(_1214_[2]), + .O(_0627_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2859_ ( + .I0(_1215_[1]), + .I1(\corescorecore.core_2.serving.cpu.alu.i_init ), + .O(_0626_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2860_ ( + .I0(_1225_[0]), + .I1(_1225_[1]), + .I2(\corescorecore.core_2.serving.cpu.bufreg.c_r ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_init ), + .O(_0625_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2861_ ( + .I0(_1223_[0]), + .I1(_1223_[1]), + .I2(\corescorecore.core_2.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .I3(_1095_[0]), + .O(_0630_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2862_ ( + .I0(_1257_[0]), + .I1(\corescorecore.core_2.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_2.serving.cpu.ctrl.pc_plus_4_cy_r ), + .I3(_1095_[0]), + .O(_0629_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2863_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_sh_signed ), + .I2(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .O(_0624_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2864_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_2.serving.cpu.alu.shamt_msb ), + .I2(\corescorecore.core_2.serving.cpu.alu.shift.cnt [5]), + .O(_0623_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2865_ ( + .I0(_1185_[0]), + .I1(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0621_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2866_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.result_lt ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0622_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'he8) + ) _2867_ ( + .I0(_0924_), + .I1(_1215_[1]), + .I2(\corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy_r ), + .O(\corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2868_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy ), + .I1(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0620_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd400) + ) _2869_ ( + .I0(_1227_[0]), + .I1(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_2.serving.cpu.alu.add_cy_r ), + .I3(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0619_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0e) + ) _2870_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_2.serving.cpu.bufreg.o_lsb [0]), + .I2(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2871_ ( + .I0(\corescorecore.core_2.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .I2(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _2872_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_2.serving.cpu.bufreg.o_lsb [0]), + .I2(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2873_ ( + .I0(_1213_[0]), + .I1(\corescorecore.core_2.serving.ram.wb_en ), + .O(_0695_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2874_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_1.serving.cpu.mem_bytecnt [1]), + .I2(\corescorecore.core_1.serving.cpu.mem_bytecnt [0]), + .I3(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .O(_0617_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0b) + ) _2875_ ( + .I0(\corescorecore.core_1.serving.cpu.state.stage_two_req ), + .I1(_1169_[2]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(\corescorecore.core_1.serving.cpu.bufreg_hold ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0b00) + ) _2876_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [2]), + .I1(_1218_[1]), + .I2(_1218_[2]), + .I3(_1006_[0]), + .O(\corescorecore.core_1.serving.cpu.o_wen0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _2877_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [0]), + .I1(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [1]), + .I2(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [4]), + .O(_1218_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2878_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_1.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .O(_1218_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd000) + ) _2879_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [0]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I3(_1031_[2]), + .O(\corescorecore.core_1.serving.cpu.alu.i_shamt_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2880_ ( + .I0(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_1.serving.cpu.state.o_cnt_r [1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_init ), + .I3(_1031_[2]), + .O(_0550_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2881_ ( + .I0(_1034_[1]), + .I1(\corescorecore.core_1.serving.cpu.alu.i_init ), + .O(_0549_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2882_ ( + .I0(_1119_[0]), + .I1(_1119_[1]), + .I2(\corescorecore.core_1.serving.cpu.bufreg.c_r ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_init ), + .O(_0548_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2883_ ( + .I0(_1051_[0]), + .I1(_1030_[0]), + .I2(\corescorecore.core_1.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .I3(_1006_[0]), + .O(_0553_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2884_ ( + .I0(_1131_[0]), + .I1(\corescorecore.core_1.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_1.serving.cpu.ctrl.pc_plus_4_cy_r ), + .I3(_1006_[0]), + .O(_0552_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2885_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_sh_signed ), + .I2(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .O(_0547_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2886_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_1.serving.cpu.alu.shamt_msb ), + .I2(\corescorecore.core_1.serving.cpu.alu.shift.cnt [5]), + .O(_0546_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2887_ ( + .I0(_1180_[0]), + .I1(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0544_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2888_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.result_lt ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0545_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'he8) + ) _2889_ ( + .I0(_0905_), + .I1(_1034_[1]), + .I2(\corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy_r ), + .O(\corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2890_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy ), + .I1(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0543_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd400) + ) _2891_ ( + .I0(_1139_[0]), + .I1(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_1.serving.cpu.alu.add_cy_r ), + .I3(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0542_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0e) + ) _2892_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_1.serving.cpu.bufreg.o_lsb [0]), + .I2(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2893_ ( + .I0(\corescorecore.core_1.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .I2(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _2894_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_1.serving.cpu.bufreg.o_lsb [0]), + .I2(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2895_ ( + .I0(_1246_[0]), + .I1(\corescorecore.core_1.serving.ram.wb_en ), + .O(_0618_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2896_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt_r [2]), + .I1(\corescorecore.core_0.serving.cpu.mem_bytecnt [1]), + .I2(\corescorecore.core_0.serving.cpu.mem_bytecnt [0]), + .I3(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .O(_0540_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h0b) + ) _2897_ ( + .I0(\corescorecore.core_0.serving.cpu.state.stage_two_req ), + .I1(_1013_[2]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(\corescorecore.core_0.serving.cpu.bufreg_hold ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0b00) + ) _2898_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [2]), + .I1(_1326_[1]), + .I2(_1326_[2]), + .I3(_1002_[0]), + .O(\corescorecore.core_0.serving.cpu.o_wen0 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0001) + ) _2899_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [0]), + .I1(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [1]), + .I2(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [3]), + .I3(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [4]), + .O(_1326_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h030a) + ) _2900_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .I1(\corescorecore.core_0.serving.cpu.decode.m3 ), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .I3(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .O(_1326_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd000) + ) _2901_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_0.serving.cpu.state.o_cnt_r [0]), + .I2(_1070_[2]), + .I3(\corescorecore.core_0.serving.cpu.alu.i_init ), + .O(\corescorecore.core_0.serving.cpu.alu.i_shamt_en ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h4000) + ) _2902_ ( + .I0(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .I1(\corescorecore.core_0.serving.cpu.alu.i_init ), + .I2(\corescorecore.core_0.serving.cpu.state.o_cnt_r [1]), + .I3(_1070_[2]), + .O(_0473_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2903_ ( + .I0(_1071_[2]), + .I1(\corescorecore.core_0.serving.cpu.alu.i_init ), + .O(_0472_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2904_ ( + .I0(_1073_[0]), + .I1(_1073_[1]), + .I2(\corescorecore.core_0.serving.cpu.bufreg.c_r ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_init ), + .O(_0471_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2905_ ( + .I0(_1153_[1]), + .I1(_1152_[0]), + .I2(\corescorecore.core_0.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .I3(_1002_[0]), + .O(_0476_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'he800) + ) _2906_ ( + .I0(_1143_[0]), + .I1(\corescorecore.core_0.serving.cpu.ctrl.pc ), + .I2(\corescorecore.core_0.serving.cpu.ctrl.pc_plus_4_cy_r ), + .I3(_1002_[0]), + .O(_0475_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h80) + ) _2907_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_sh_signed ), + .I2(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .O(_0470_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2908_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .I1(\corescorecore.core_0.serving.cpu.alu.shamt_msb ), + .I2(\corescorecore.core_0.serving.cpu.alu.shift.cnt [5]), + .O(_0469_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'hb) + ) _2909_ ( + .I0(_1020_[0]), + .I1(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0467_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2910_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.result_lt ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0468_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'he8) + ) _2911_ ( + .I0(_0878_), + .I1(_1071_[2]), + .I2(\corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy_r ), + .O(\corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h8) + ) _2912_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy ), + .I1(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0466_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hd400) + ) _2913_ ( + .I0(_1157_[0]), + .I1(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .I2(\corescorecore.core_0.serving.cpu.alu.add_cy_r ), + .I3(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0465_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hff0e) + ) _2914_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_0.serving.cpu.bufreg.o_lsb [0]), + .I2(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hf4) + ) _2915_ ( + .I0(\corescorecore.core_0.serving.cpu.bufreg.o_lsb [0]), + .I1(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .I2(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hffe0) + ) _2916_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .I1(\corescorecore.core_0.serving.cpu.bufreg.o_lsb [0]), + .I2(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .O(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h4) + ) _2917_ ( + .I0(_1219_[0]), + .I1(\corescorecore.core_0.serving.ram.wb_en ), + .O(_0541_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'he) + ) _2918_ ( + .I0(_1217_[0]), + .I1(\emitter.data [0]), + .O(\emitter.o_uart_tx ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2919_ ( + .I0(\corescorecore.core_0.serving.ram.bsel [0]), + .I1(\corescorecore.core_0.serving.ram.bsel [1]), + .O(_0896_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2920_ ( + .I0(\corescorecore.core_3.serving.ram.bsel [0]), + .I1(\corescorecore.core_3.serving.ram.bsel [1]), + .O(_0910_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2921_ ( + .I0(\corescorecore.core_1.serving.ram.bsel [0]), + .I1(\corescorecore.core_1.serving.ram.bsel [1]), + .O(_0917_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2922_ ( + .I0(\corescorecore.core_4.serving.ram.bsel [0]), + .I1(\corescorecore.core_4.serving.ram.bsel [1]), + .O(_0886_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:33.26-33.73" *) + CC_LUT2 #( + .INIT(4'h6) + ) _2923_ ( + .I0(\corescorecore.core_2.serving.ram.bsel [0]), + .I1(\corescorecore.core_2.serving.ram.bsel [1]), + .O(_0940_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2924_ ( + .I0(_0931_), + .O(\corescorecore.core_4.serving.cpu.alu.op_b ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2925_ ( + .I0(_0950_), + .O(\corescorecore.core_3.serving.cpu.alu.op_b ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2926_ ( + .I0(_0924_), + .O(\corescorecore.core_2.serving.cpu.alu.op_b ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2927_ ( + .I0(_0905_), + .O(\corescorecore.core_1.serving.cpu.alu.op_b ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2928_ ( + .I0(_0878_), + .O(\corescorecore.core_0.serving.cpu.alu.op_b ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2929_ ( + .I0(\corescorecore.core_0.serving.ram.bsel [0]), + .O(_0895_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2930_ ( + .I0(\corescorecore.core_3.serving.ram.bsel [0]), + .O(_0909_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2931_ ( + .I0(\corescorecore.core_1.serving.ram.bsel [0]), + .O(_0916_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2932_ ( + .I0(\corescorecore.core_4.serving.ram.bsel [0]), + .O(_0885_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2933_ ( + .I0(\corescorecore.core_2.serving.ram.bsel [0]), + .O(_0939_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2934_ ( + .I0(_0868_[2]), + .O(_0852_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:30.26-30.62" *) + CC_LUT1 #( + .INIT(2'h1) + ) _2935_ ( + .I0(_0871_[2]), + .O(_0856_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _2936_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.shift.cnt [0]), + .I1(\corescorecore.core_4.serving.cpu.alu.shamt [0]), + .I2(\corescorecore.core_4.serving.cpu.alu.shift.cnt [1]), + .I3(\corescorecore.core_4.serving.cpu.alu.shamt [1]), + .O(_1238_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hb00b) + ) _2937_ ( + .I0(\corescorecore.core_4.serving.cpu.alu.shamt [3]), + .I1(\corescorecore.core_4.serving.cpu.alu.shift.cnt [3]), + .I2(\corescorecore.core_4.serving.cpu.alu.shift.cnt [4]), + .I3(\corescorecore.core_4.serving.cpu.alu.shamt [4]), + .O(_1238_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h8000) + ) _2938_ ( + .I0(\corescorecore.core_4.serving.cpu.state.stage_two_pending ), + .I1(_1238_[1]), + .I2(_1238_[2]), + .I3(_1238_[3]), + .O(_1240_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h0bbb) + ) _2939_ ( + .I0(_1240_[0]), + .I1(\corescorecore.core_4.serving.cpu.state.stage_two_req ), + .I2(_1240_[2]), + .I3(_1196_[1]), + .O(_1255_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _2940_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.shift.cnt [3]), + .I1(\corescorecore.core_1.serving.cpu.alu.shamt [3]), + .I2(\corescorecore.core_1.serving.cpu.alu.shift.cnt [4]), + .I3(\corescorecore.core_1.serving.cpu.alu.shamt [4]), + .O(_1168_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2941_ ( + .I0(\corescorecore.core_1.serving.cpu.alu.shift.cnt [0]), + .I1(\corescorecore.core_1.serving.cpu.alu.shamt [0]), + .I2(_1168_[2]), + .I3(_1168_[3]), + .O(_1169_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h7f) + ) _2942_ ( + .I0(\corescorecore.core_1.serving.cpu.state.stage_two_pending ), + .I1(_1169_[1]), + .I2(_1169_[2]), + .O(_1170_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hb0) + ) _2943_ ( + .I0(_1170_[0]), + .I1(\corescorecore.core_1.serving.cpu.state.stage_two_req ), + .I2(_1170_[2]), + .O(_1171_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _2944_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.shift.cnt [3]), + .I1(\corescorecore.core_2.serving.cpu.alu.shamt [3]), + .I2(\corescorecore.core_2.serving.cpu.alu.shift.cnt [4]), + .I3(\corescorecore.core_2.serving.cpu.alu.shamt [4]), + .O(_1102_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h2fff) + ) _2945_ ( + .I0(_1104_[0]), + .I1(_1104_[1]), + .I2(_1104_[2]), + .I3(_1104_[3]), + .O(\corescorecore.core_2.serving.cpu.i_rf_ready ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _2946_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.shift.cnt [1]), + .I1(\corescorecore.core_3.serving.cpu.alu.shamt [1]), + .I2(\corescorecore.core_3.serving.cpu.alu.shift.cnt [2]), + .I3(\corescorecore.core_3.serving.cpu.alu.shamt [2]), + .O(_1085_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2947_ ( + .I0(\corescorecore.core_3.serving.cpu.alu.shift.cnt [0]), + .I1(\corescorecore.core_3.serving.cpu.alu.shamt [0]), + .I2(_1085_[2]), + .I3(_1085_[3]), + .O(_1087_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h7f) + ) _2948_ ( + .I0(\corescorecore.core_3.serving.cpu.state.stage_two_pending ), + .I1(_1087_[1]), + .I2(_1087_[2]), + .O(_1088_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hb0) + ) _2949_ ( + .I0(_1088_[0]), + .I1(\corescorecore.core_3.serving.cpu.state.stage_two_req ), + .I2(_1088_[2]), + .O(_1092_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _2950_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.shift.cnt [1]), + .I1(\corescorecore.core_0.serving.cpu.alu.shamt [1]), + .I2(\corescorecore.core_0.serving.cpu.alu.shift.cnt [2]), + .I3(\corescorecore.core_0.serving.cpu.alu.shamt [2]), + .O(_1012_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2951_ ( + .I0(\corescorecore.core_0.serving.cpu.alu.shift.cnt [0]), + .I1(\corescorecore.core_0.serving.cpu.alu.shamt [0]), + .I2(_1012_[2]), + .I3(_1012_[3]), + .O(_1013_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h7f) + ) _2952_ ( + .I0(\corescorecore.core_0.serving.cpu.state.stage_two_pending ), + .I1(_1013_[1]), + .I2(_1013_[2]), + .O(_1014_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hb0) + ) _2953_ ( + .I0(_1014_[0]), + .I1(\corescorecore.core_0.serving.cpu.state.stage_two_req ), + .I2(_1014_[2]), + .O(_1015_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1c) + ) _2954_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_4.serving.cpu.decode.opcode [1]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .O(_1232_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaac) + ) _2955_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [0]), + .I1(\corescorecore.core_4.serving.cpu.decode.signbit ), + .I2(_1232_[2]), + .I3(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .O(_1233_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2956_ ( + .I0(\corescorecore.core_4.serving.cpu.decode.imm7 ), + .I1(_1233_[1]), + .I2(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .I3(\corescorecore.core_4.serving.cpu.decode.m3 ), + .O(_1234_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2957_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1234_[1]), + .I2(\corescorecore.core_4.serving.cpu.alu.i_en ), + .O(_0809_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcfa0) + ) _2958_ ( + .I0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .I1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .I2(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_4.serving.cpu.bufreg.o_lsb [0]), + .O(_1237_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfc0a) + ) _2959_ ( + .I0(\corescorecore.axis_mux.s_axis_tdata [32]), + .I1(\corescorecore.core_4.o_tlast ), + .I2(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .I3(_1237_[3]), + .O(\corescorecore.core_4.serving.cpu.mem_if.dat_cur ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1c) + ) _2960_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_3.serving.cpu.decode.opcode [1]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .O(_1229_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaac) + ) _2961_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [0]), + .I1(\corescorecore.core_3.serving.cpu.decode.signbit ), + .I2(_1229_[2]), + .I3(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .O(_1230_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2962_ ( + .I0(\corescorecore.core_3.serving.cpu.decode.imm7 ), + .I1(_1230_[1]), + .I2(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .I3(\corescorecore.core_3.serving.cpu.decode.m3 ), + .O(_1231_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2963_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1231_[1]), + .I2(\corescorecore.core_3.serving.cpu.alu.i_en ), + .O(_0732_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcfa0) + ) _2964_ ( + .I0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .I1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .I2(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_3.serving.cpu.bufreg.o_lsb [0]), + .O(_1236_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfc0a) + ) _2965_ ( + .I0(\corescorecore.axis_mux.s_axis_tdata [24]), + .I1(\corescorecore.core_3.o_tlast ), + .I2(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .I3(_1236_[3]), + .O(\corescorecore.core_3.serving.cpu.mem_if.dat_cur ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1c) + ) _2966_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_2.serving.cpu.decode.opcode [1]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .O(_1109_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaac) + ) _2967_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [0]), + .I1(\corescorecore.core_2.serving.cpu.decode.signbit ), + .I2(_1109_[2]), + .I3(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .O(_1110_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2968_ ( + .I0(\corescorecore.core_2.serving.cpu.decode.imm7 ), + .I1(_1110_[1]), + .I2(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .I3(\corescorecore.core_2.serving.cpu.decode.m3 ), + .O(_1111_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2969_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1111_[1]), + .I2(\corescorecore.core_2.serving.cpu.alu.i_en ), + .O(_0655_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcfa0) + ) _2970_ ( + .I0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .I1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .I2(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_2.serving.cpu.bufreg.o_lsb [0]), + .O(_1235_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfc0a) + ) _2971_ ( + .I0(\corescorecore.axis_mux.s_axis_tdata [16]), + .I1(\corescorecore.core_2.o_tlast ), + .I2(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .I3(_1235_[3]), + .O(\corescorecore.core_2.serving.cpu.mem_if.dat_cur ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1c) + ) _2972_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_1.serving.cpu.decode.opcode [1]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .O(_1106_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaac) + ) _2973_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [0]), + .I1(\corescorecore.core_1.serving.cpu.decode.signbit ), + .I2(_1106_[2]), + .I3(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .O(_1107_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2974_ ( + .I0(\corescorecore.core_1.serving.cpu.decode.imm7 ), + .I1(_1107_[1]), + .I2(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .I3(\corescorecore.core_1.serving.cpu.decode.m3 ), + .O(_1108_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2975_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1108_[1]), + .I2(\corescorecore.core_1.serving.cpu.alu.i_en ), + .O(_0578_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcfa0) + ) _2976_ ( + .I0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .I1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .I2(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_1.serving.cpu.bufreg.o_lsb [0]), + .O(_1133_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfc0a) + ) _2977_ ( + .I0(\corescorecore.axis_mux.s_axis_tdata [8]), + .I1(\corescorecore.core_1.o_tlast ), + .I2(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .I3(_1133_[3]), + .O(\corescorecore.core_1.serving.cpu.mem_if.dat_cur ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h1c) + ) _2978_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .I1(\corescorecore.core_0.serving.cpu.decode.opcode [1]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .O(_1098_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcaac) + ) _2979_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [0]), + .I1(\corescorecore.core_0.serving.cpu.decode.signbit ), + .I2(_1098_[2]), + .I3(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .O(_1241_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcacc) + ) _2980_ ( + .I0(\corescorecore.core_0.serving.cpu.decode.imm7 ), + .I1(_1241_[1]), + .I2(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .I3(\corescorecore.core_0.serving.cpu.decode.m3 ), + .O(_1242_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'hca) + ) _2981_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .I1(_1242_[1]), + .I2(\corescorecore.core_0.serving.cpu.alu.i_en ), + .O(_0501_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hcfa0) + ) _2982_ ( + .I0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .I1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .I2(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .I3(\corescorecore.core_0.serving.cpu.bufreg.o_lsb [0]), + .O(_1148_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'hfc0a) + ) _2983_ ( + .I0(\corescorecore.axis_mux.s_axis_tdata [0]), + .I1(\corescorecore.core_0.o_tlast ), + .I2(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .I3(_1148_[3]), + .O(\corescorecore.core_0.serving.cpu.mem_if.dat_cur ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9009) + ) _2984_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.shift.cnt [1]), + .I1(\corescorecore.core_2.serving.cpu.alu.shamt [1]), + .I2(\corescorecore.core_2.serving.cpu.alu.shift.cnt [2]), + .I3(\corescorecore.core_2.serving.cpu.alu.shamt [2]), + .O(_1102_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:39.26-39.95" *) + CC_LUT4 #( + .INIT(16'h9000) + ) _2985_ ( + .I0(\corescorecore.core_2.serving.cpu.alu.shift.cnt [0]), + .I1(\corescorecore.core_2.serving.cpu.alu.shamt [0]), + .I2(_1102_[2]), + .I3(_1102_[3]), + .O(_1103_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/lut_map.v:36.26-36.84" *) + CC_LUT3 #( + .INIT(8'h7f) + ) _2986_ ( + .I0(\corescorecore.core_2.serving.cpu.state.stage_two_pending ), + .I1(_1103_[1]), + .I2(_1103_[2]), + .O(_1104_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.51-123.75|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2987_ ( + .A(1'h1), + .B(\corescorecore.axis_mux.arb_inst.masked_request_index [0]), + .CI(1'h0), + .CO(_0866_[1]), + .S(_0868_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.51-123.75|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2988_ ( + .A(1'h0), + .B(\corescorecore.axis_mux.arb_inst.masked_request_index [1]), + .CI(_0866_[1]), + .CO(_0866_[2]), + .S(_0868_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.51-123.75|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2989_ ( + .A(1'h0), + .B(\corescorecore.axis_mux.arb_inst.masked_request_index [2]), + .CI(_0866_[2]), + .CO(_0866_[3]), + .S(_0868_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:123.51-123.75|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2990_ ( + .A(1'h0), + .B(1'h0), + .CI(_0866_[3]), + .CO(_0867_[3]), + .S(_0868_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.51-132.68|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2991_ ( + .A(1'h1), + .B(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [0]), + .CI(1'h0), + .CO(_0869_[1]), + .S(_0871_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.51-132.68|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2992_ ( + .A(1'h0), + .B(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [1]), + .CI(_0869_[1]), + .CO(_0869_[2]), + .S(_0871_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.51-132.68|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2993_ ( + .A(1'h0), + .B(\corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [2]), + .CI(_0869_[2]), + .CO(_0869_[3]), + .S(_0871_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:132.51-132.68|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2994_ ( + .A(1'h0), + .B(1'h0), + .CI(_0869_[3]), + .CO(_0870_[3]), + .S(_0871_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2995_ ( + .A(\emitter.cnt [0]), + .B(1'h0), + .CI(1'h1), + .CO(_0872_[1]), + .S(_0874_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2996_ ( + .A(\emitter.cnt [1]), + .B(1'h1), + .CI(_0872_[1]), + .CO(_0872_[2]), + .S(_0874_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2997_ ( + .A(\emitter.cnt [2]), + .B(1'h1), + .CI(_0872_[2]), + .CO(_0872_[3]), + .S(_0874_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2998_ ( + .A(\emitter.cnt [3]), + .B(1'h1), + .CI(_0872_[3]), + .CO(_0872_[4]), + .S(_0874_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _2999_ ( + .A(\emitter.cnt [4]), + .B(1'h1), + .CI(_0872_[4]), + .CO(_0872_[5]), + .S(_0874_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3000_ ( + .A(\emitter.cnt [5]), + .B(1'h1), + .CI(_0872_[5]), + .CO(_0872_[6]), + .S(_0874_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3001_ ( + .A(\emitter.cnt [6]), + .B(1'h1), + .CI(_0872_[6]), + .CO(_0872_[7]), + .S(_0874_[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3002_ ( + .A(\emitter.cnt [7]), + .B(1'h1), + .CI(_0872_[7]), + .CO(_0872_[8]), + .S(_0874_[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3003_ ( + .A(\emitter.cnt [8]), + .B(1'h1), + .CI(_0872_[8]), + .CO(_0872_[9]), + .S(_0874_[8]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:37.16-37.21|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3004_ ( + .A(\emitter.cnt [9]), + .B(1'h1), + .CI(_0872_[9]), + .CO(_0873_[9]), + .S(_0874_[9]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3005_ ( + .A(1'h1), + .B(\corescorecore.core_4.serving.rf_ram_if.wcnt [0]), + .CI(1'h0), + .CO(_0875_[1]), + .S(_0877_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3006_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.rf_ram_if.wcnt [1]), + .CI(_0875_[1]), + .CO(_0875_[2]), + .S(_0877_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3007_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.rf_ram_if.wcnt [2]), + .CI(_0875_[2]), + .CO(_0875_[3]), + .S(_0877_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3008_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.rf_ram_if.o_waddr [0]), + .CI(_0875_[3]), + .CO(_0875_[4]), + .S(_0877_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3009_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.rf_ram_if.o_waddr [1]), + .CI(_0875_[4]), + .CO(_0876_[4]), + .S(_0877_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3010_ ( + .A(1'h1), + .B(\corescorecore.core_0.serving.cpu.alu.shift.cnt [0]), + .CI(1'h0), + .CO(_0879_[1]), + .S(_0881_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3011_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.cpu.alu.shift.cnt [1]), + .CI(_0879_[1]), + .CO(_0879_[2]), + .S(_0881_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3012_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.cpu.alu.shift.cnt [2]), + .CI(_0879_[2]), + .CO(_0879_[3]), + .S(_0881_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3013_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.cpu.alu.shift.cnt [3]), + .CI(_0879_[3]), + .CO(_0879_[4]), + .S(_0881_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3014_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.cpu.alu.shift.cnt [4]), + .CI(_0879_[4]), + .CO(_0879_[5]), + .S(_0881_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3015_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.cpu.alu.shift.cnt [5]), + .CI(_0879_[5]), + .CO(_0880_[5]), + .S(_0881_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3016_ ( + .A(1'h1), + .B(\corescorecore.core_4.serving.rf_ram_if.rcnt [0]), + .CI(1'h0), + .CO(_0882_[1]), + .S(_0884_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3017_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.rf_ram_if.rcnt [1]), + .CI(_0882_[1]), + .CO(_0882_[2]), + .S(_0884_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3018_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.rf_ram_if.rcnt [2]), + .CI(_0882_[2]), + .CO(_0882_[3]), + .S(_0884_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3019_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.raddr [0]), + .CI(_0882_[3]), + .CO(_0882_[4]), + .S(_0884_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3020_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.raddr [1]), + .CI(_0882_[4]), + .CO(_0883_[4]), + .S(_0884_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3021_ ( + .A(\corescorecore.core_4.serving.cpu.state.o_cnt_r [3]), + .B(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .CI(1'h0), + .CO(_0887_[1]), + .S(_0889_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3022_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.cpu.mem_bytecnt [0]), + .CI(_0887_[1]), + .CO(_0887_[2]), + .S(_0889_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3023_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.cpu.mem_bytecnt [1]), + .CI(_0887_[2]), + .CO(_0888_[2]), + .S(_0889_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3024_ ( + .A(\corescorecore.core_0.serving.cpu.mem_bytecnt [0]), + .B(\corescorecore.core_0.serving.cpu.bufreg.o_lsb [0]), + .CI(1'h0), + .CO(_0890_[1]), + .S(\corescorecore.core_0.serving.cpu.mem_if.tmp [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3025_ ( + .A(\corescorecore.core_0.serving.cpu.mem_bytecnt [1]), + .B(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .CI(_0890_[1]), + .CO(_0890_[2]), + .S(\corescorecore.core_0.serving.cpu.mem_if.tmp [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3026_ ( + .A(1'h0), + .B(1'h0), + .CI(_0890_[2]), + .CO(_0891_[2]), + .S(\corescorecore.core_0.serving.cpu.mem_if.tmp [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3027_ ( + .A(\corescorecore.core_0.serving.cpu.state.o_cnt_r [3]), + .B(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .CI(1'h0), + .CO(_0892_[1]), + .S(_0894_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3028_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.cpu.mem_bytecnt [0]), + .CI(_0892_[1]), + .CO(_0892_[2]), + .S(_0894_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3029_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.cpu.mem_bytecnt [1]), + .CI(_0892_[2]), + .CO(_0893_[2]), + .S(_0894_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3030_ ( + .A(1'h1), + .B(\corescorecore.core_0.serving.rf_ram_if.rcnt [0]), + .CI(1'h0), + .CO(_0897_[1]), + .S(_0899_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3031_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.rf_ram_if.rcnt [1]), + .CI(_0897_[1]), + .CO(_0897_[2]), + .S(_0899_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3032_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.rf_ram_if.rcnt [2]), + .CI(_0897_[2]), + .CO(_0897_[3]), + .S(_0899_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3033_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.raddr [0]), + .CI(_0897_[3]), + .CO(_0897_[4]), + .S(_0899_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3034_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.raddr [1]), + .CI(_0897_[4]), + .CO(_0898_[4]), + .S(_0899_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3035_ ( + .A(1'h1), + .B(\corescorecore.core_0.serving.rf_ram_if.wcnt [0]), + .CI(1'h0), + .CO(_0900_[1]), + .S(_0902_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3036_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.rf_ram_if.wcnt [1]), + .CI(_0900_[1]), + .CO(_0900_[2]), + .S(_0902_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3037_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.rf_ram_if.wcnt [2]), + .CI(_0900_[2]), + .CO(_0900_[3]), + .S(_0902_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3038_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.rf_ram_if.o_waddr [0]), + .CI(_0900_[3]), + .CO(_0900_[4]), + .S(_0902_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3039_ ( + .A(1'h0), + .B(\corescorecore.core_0.serving.rf_ram_if.o_waddr [1]), + .CI(_0900_[4]), + .CO(_0901_[4]), + .S(_0902_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3040_ ( + .A(\corescorecore.core_4.serving.cpu.bufreg.o_lsb [0]), + .B(\corescorecore.core_4.serving.cpu.mem_bytecnt [0]), + .CI(1'h0), + .CO(_0903_[1]), + .S(\corescorecore.core_4.serving.cpu.mem_if.tmp [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3041_ ( + .A(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .B(\corescorecore.core_4.serving.cpu.mem_bytecnt [1]), + .CI(_0903_[1]), + .CO(_0903_[2]), + .S(\corescorecore.core_4.serving.cpu.mem_if.tmp [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3042_ ( + .A(1'h0), + .B(1'h0), + .CI(_0903_[2]), + .CO(_0904_[2]), + .S(\corescorecore.core_4.serving.cpu.mem_if.tmp [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3043_ ( + .A(1'h1), + .B(\corescorecore.core_1.serving.cpu.alu.shift.cnt [0]), + .CI(1'h0), + .CO(_0906_[1]), + .S(_0908_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3044_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.cpu.alu.shift.cnt [1]), + .CI(_0906_[1]), + .CO(_0906_[2]), + .S(_0908_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3045_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.cpu.alu.shift.cnt [2]), + .CI(_0906_[2]), + .CO(_0906_[3]), + .S(_0908_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3046_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.cpu.alu.shift.cnt [3]), + .CI(_0906_[3]), + .CO(_0906_[4]), + .S(_0908_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3047_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.cpu.alu.shift.cnt [4]), + .CI(_0906_[4]), + .CO(_0906_[5]), + .S(_0908_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3048_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.cpu.alu.shift.cnt [5]), + .CI(_0906_[5]), + .CO(_0907_[5]), + .S(_0908_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3049_ ( + .A(\corescorecore.core_1.serving.cpu.mem_bytecnt [0]), + .B(\corescorecore.core_1.serving.cpu.bufreg.o_lsb [0]), + .CI(1'h0), + .CO(_0911_[1]), + .S(\corescorecore.core_1.serving.cpu.mem_if.tmp [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3050_ ( + .A(\corescorecore.core_1.serving.cpu.mem_bytecnt [1]), + .B(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .CI(_0911_[1]), + .CO(_0911_[2]), + .S(\corescorecore.core_1.serving.cpu.mem_if.tmp [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3051_ ( + .A(1'h0), + .B(1'h0), + .CI(_0911_[2]), + .CO(_0912_[2]), + .S(\corescorecore.core_1.serving.cpu.mem_if.tmp [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3052_ ( + .A(\corescorecore.core_1.serving.cpu.state.o_cnt_r [3]), + .B(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .CI(1'h0), + .CO(_0913_[1]), + .S(_0915_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3053_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.cpu.mem_bytecnt [0]), + .CI(_0913_[1]), + .CO(_0913_[2]), + .S(_0915_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3054_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.cpu.mem_bytecnt [1]), + .CI(_0913_[2]), + .CO(_0914_[2]), + .S(_0915_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3055_ ( + .A(1'h1), + .B(\corescorecore.core_1.serving.rf_ram_if.rcnt [0]), + .CI(1'h0), + .CO(_0918_[1]), + .S(_0920_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3056_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.rf_ram_if.rcnt [1]), + .CI(_0918_[1]), + .CO(_0918_[2]), + .S(_0920_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3057_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.rf_ram_if.rcnt [2]), + .CI(_0918_[2]), + .CO(_0918_[3]), + .S(_0920_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3058_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.raddr [0]), + .CI(_0918_[3]), + .CO(_0918_[4]), + .S(_0920_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3059_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.raddr [1]), + .CI(_0918_[4]), + .CO(_0919_[4]), + .S(_0920_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3060_ ( + .A(1'h1), + .B(\corescorecore.core_1.serving.rf_ram_if.wcnt [0]), + .CI(1'h0), + .CO(_0921_[1]), + .S(_0923_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3061_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.rf_ram_if.wcnt [1]), + .CI(_0921_[1]), + .CO(_0921_[2]), + .S(_0923_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3062_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.rf_ram_if.wcnt [2]), + .CI(_0921_[2]), + .CO(_0921_[3]), + .S(_0923_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3063_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.rf_ram_if.o_waddr [0]), + .CI(_0921_[3]), + .CO(_0921_[4]), + .S(_0923_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3064_ ( + .A(1'h0), + .B(\corescorecore.core_1.serving.rf_ram_if.o_waddr [1]), + .CI(_0921_[4]), + .CO(_0922_[4]), + .S(_0923_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3065_ ( + .A(1'h1), + .B(\corescorecore.core_2.serving.cpu.alu.shift.cnt [0]), + .CI(1'h0), + .CO(_0925_[1]), + .S(_0927_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3066_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.cpu.alu.shift.cnt [1]), + .CI(_0925_[1]), + .CO(_0925_[2]), + .S(_0927_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3067_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.cpu.alu.shift.cnt [2]), + .CI(_0925_[2]), + .CO(_0925_[3]), + .S(_0927_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3068_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.cpu.alu.shift.cnt [3]), + .CI(_0925_[3]), + .CO(_0925_[4]), + .S(_0927_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3069_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.cpu.alu.shift.cnt [4]), + .CI(_0925_[4]), + .CO(_0925_[5]), + .S(_0927_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3070_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.cpu.alu.shift.cnt [5]), + .CI(_0925_[5]), + .CO(_0926_[5]), + .S(_0927_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3071_ ( + .A(1'h1), + .B(\corescorecore.core_4.serving.cpu.alu.shift.cnt [0]), + .CI(1'h0), + .CO(_0928_[1]), + .S(_0930_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3072_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.cpu.alu.shift.cnt [1]), + .CI(_0928_[1]), + .CO(_0928_[2]), + .S(_0930_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3073_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.cpu.alu.shift.cnt [2]), + .CI(_0928_[2]), + .CO(_0928_[3]), + .S(_0930_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3074_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.cpu.alu.shift.cnt [3]), + .CI(_0928_[3]), + .CO(_0928_[4]), + .S(_0930_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3075_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.cpu.alu.shift.cnt [4]), + .CI(_0928_[4]), + .CO(_0928_[5]), + .S(_0930_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3076_ ( + .A(1'h0), + .B(\corescorecore.core_4.serving.cpu.alu.shift.cnt [5]), + .CI(_0928_[5]), + .CO(_0929_[5]), + .S(_0930_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3077_ ( + .A(\corescorecore.core_3.serving.cpu.bufreg.o_lsb [0]), + .B(\corescorecore.core_3.serving.cpu.mem_bytecnt [0]), + .CI(1'h0), + .CO(_0932_[1]), + .S(\corescorecore.core_3.serving.cpu.mem_if.tmp [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3078_ ( + .A(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .B(\corescorecore.core_3.serving.cpu.mem_bytecnt [1]), + .CI(_0932_[1]), + .CO(_0932_[2]), + .S(\corescorecore.core_3.serving.cpu.mem_if.tmp [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3079_ ( + .A(1'h0), + .B(1'h0), + .CI(_0932_[2]), + .CO(_0933_[2]), + .S(\corescorecore.core_3.serving.cpu.mem_if.tmp [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3080_ ( + .A(\corescorecore.core_2.serving.cpu.mem_bytecnt [0]), + .B(\corescorecore.core_2.serving.cpu.bufreg.o_lsb [0]), + .CI(1'h0), + .CO(_0934_[1]), + .S(\corescorecore.core_2.serving.cpu.mem_if.tmp [0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3081_ ( + .A(\corescorecore.core_2.serving.cpu.mem_bytecnt [1]), + .B(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .CI(_0934_[1]), + .CO(_0934_[2]), + .S(\corescorecore.core_2.serving.cpu.mem_if.tmp [1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:24.23-24.52|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3082_ ( + .A(1'h0), + .B(1'h0), + .CI(_0934_[2]), + .CO(_0935_[2]), + .S(\corescorecore.core_2.serving.cpu.mem_if.tmp [2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3083_ ( + .A(\corescorecore.core_2.serving.cpu.state.o_cnt_r [3]), + .B(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .CI(1'h0), + .CO(_0936_[1]), + .S(_0938_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3084_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.cpu.mem_bytecnt [0]), + .CI(_0936_[1]), + .CO(_0936_[2]), + .S(_0938_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3085_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.cpu.mem_bytecnt [1]), + .CI(_0936_[2]), + .CO(_0937_[2]), + .S(_0938_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3086_ ( + .A(1'h1), + .B(\corescorecore.core_2.serving.rf_ram_if.rcnt [0]), + .CI(1'h0), + .CO(_0941_[1]), + .S(_0943_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3087_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.rf_ram_if.rcnt [1]), + .CI(_0941_[1]), + .CO(_0941_[2]), + .S(_0943_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3088_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.rf_ram_if.rcnt [2]), + .CI(_0941_[2]), + .CO(_0941_[3]), + .S(_0943_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3089_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.raddr [0]), + .CI(_0941_[3]), + .CO(_0941_[4]), + .S(_0943_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3090_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.raddr [1]), + .CI(_0941_[4]), + .CO(_0942_[4]), + .S(_0943_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3091_ ( + .A(1'h1), + .B(\corescorecore.core_2.serving.rf_ram_if.wcnt [0]), + .CI(1'h0), + .CO(_0944_[1]), + .S(_0946_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3092_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.rf_ram_if.wcnt [1]), + .CI(_0944_[1]), + .CO(_0944_[2]), + .S(_0946_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3093_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.rf_ram_if.wcnt [2]), + .CI(_0944_[2]), + .CO(_0944_[3]), + .S(_0946_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3094_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.rf_ram_if.o_waddr [0]), + .CI(_0944_[3]), + .CO(_0944_[4]), + .S(_0946_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3095_ ( + .A(1'h0), + .B(\corescorecore.core_2.serving.rf_ram_if.o_waddr [1]), + .CI(_0944_[4]), + .CO(_0945_[4]), + .S(_0946_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3096_ ( + .A(\corescorecore.core_3.serving.cpu.state.o_cnt_r [3]), + .B(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .CI(1'h0), + .CO(_0947_[1]), + .S(_0949_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3097_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.cpu.mem_bytecnt [0]), + .CI(_0947_[1]), + .CO(_0947_[2]), + .S(_0949_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:114.16-114.41|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3098_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.cpu.mem_bytecnt [1]), + .CI(_0947_[2]), + .CO(_0948_[2]), + .S(_0949_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3099_ ( + .A(1'h1), + .B(\corescorecore.core_3.serving.cpu.alu.shift.cnt [0]), + .CI(1'h0), + .CO(_0951_[1]), + .S(_0953_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3100_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.cpu.alu.shift.cnt [1]), + .CI(_0951_[1]), + .CO(_0951_[2]), + .S(_0953_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3101_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.cpu.alu.shift.cnt [2]), + .CI(_0951_[2]), + .CO(_0951_[3]), + .S(_0953_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3102_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.cpu.alu.shift.cnt [3]), + .CI(_0951_[3]), + .CO(_0951_[4]), + .S(_0953_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3103_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.cpu.alu.shift.cnt [4]), + .CI(_0951_[4]), + .CO(_0951_[5]), + .S(_0953_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:19.14-19.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3104_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.cpu.alu.shift.cnt [5]), + .CI(_0951_[5]), + .CO(_0952_[5]), + .S(_0953_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3105_ ( + .A(1'h1), + .B(\corescorecore.core_3.serving.rf_ram_if.wcnt [0]), + .CI(1'h0), + .CO(_0954_[1]), + .S(_0956_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3106_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.rf_ram_if.wcnt [1]), + .CI(_0954_[1]), + .CO(_0954_[2]), + .S(_0956_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3107_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.rf_ram_if.wcnt [2]), + .CI(_0954_[2]), + .CO(_0954_[3]), + .S(_0956_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3108_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.rf_ram_if.o_waddr [0]), + .CI(_0954_[3]), + .CO(_0954_[4]), + .S(_0956_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:90.10-90.19|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3109_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.rf_ram_if.o_waddr [1]), + .CI(_0954_[4]), + .CO(_0955_[4]), + .S(_0956_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3110_ ( + .A(1'h1), + .B(\corescorecore.core_3.serving.rf_ram_if.rcnt [0]), + .CI(1'h0), + .CO(_0957_[1]), + .S(_0959_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3111_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.rf_ram_if.rcnt [1]), + .CI(_0957_[1]), + .CO(_0957_[2]), + .S(_0959_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3112_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.rf_ram_if.rcnt [2]), + .CI(_0957_[2]), + .CO(_0957_[3]), + .S(_0959_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3113_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.raddr [0]), + .CI(_0957_[3]), + .CO(_0957_[4]), + .S(_0959_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:142.15-142.24|/usr/local/bin/../share/yosys/gatemate/arith_map.v:57.12-63.5" *) + CC_ADDF _3114_ ( + .A(1'h0), + .B(\corescorecore.core_3.serving.raddr [1]), + .CI(_0957_[4]), + .CO(_0958_[4]), + .S(_0959_[4]) + ); + CC_BUFG _3115_ ( + .I(_0960_), + .O(\clkgen.i_clk ) + ); + CC_BUFG _3116_ ( + .I(_0961_), + .O(clk) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:34.1-42.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3117_ ( + .CLK(\clkgen.i_clk ), + .D(_1277_[0]), + .EN(1'h1), + .Q(\clkgen.rst_reg1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3118_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3119_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3120_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3121_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3122_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3123_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3124_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3125_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0377_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3126_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.bufreg.q ), + .EN(_0549_), + .Q(\corescorecore.core_1.serving.cpu.bufreg.o_lsb [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3127_ ( + .CLK(clk), + .D(_0384_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3128_ ( + .CLK(clk), + .D(_0385_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata0 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3129_ ( + .CLK(clk), + .D(_0386_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata0 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3130_ ( + .CLK(clk), + .D(_0387_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata0 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3131_ ( + .CLK(clk), + .D(_0388_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata0 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3132_ ( + .CLK(clk), + .D(_0389_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata0 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3133_ ( + .CLK(clk), + .D(_0390_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata0 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3134_ ( + .CLK(clk), + .D(_0391_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata1 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3135_ ( + .CLK(clk), + .D(_0392_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata1 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3136_ ( + .CLK(clk), + .D(_0393_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata1 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3137_ ( + .CLK(clk), + .D(_0394_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata1 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3138_ ( + .CLK(clk), + .D(_0395_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata1 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3139_ ( + .CLK(clk), + .D(_0396_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata1 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3140_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3141_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3142_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3143_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3144_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3145_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3146_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3147_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0383_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3148_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3149_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3150_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3151_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3152_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3153_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3154_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3155_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_1219_[0]), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3156_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.bufreg.q ), + .EN(_0472_), + .Q(\corescorecore.core_0.serving.cpu.bufreg.o_lsb [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3157_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3158_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3159_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3160_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3161_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3162_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3163_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3164_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0381_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3165_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3166_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3167_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3168_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3169_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3170_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3171_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3172_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_1246_[0]), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3173_ ( + .CLK(clk), + .D(_0397_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3174_ ( + .CLK(clk), + .D(_0398_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata0 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3175_ ( + .CLK(clk), + .D(_0399_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata0 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3176_ ( + .CLK(clk), + .D(_0400_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata0 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3177_ ( + .CLK(clk), + .D(_0401_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata0 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3178_ ( + .CLK(clk), + .D(_0402_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata0 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3179_ ( + .CLK(clk), + .D(_0403_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata0 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3180_ ( + .CLK(clk), + .D(_0404_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata1 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3181_ ( + .CLK(clk), + .D(_0405_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata1 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3182_ ( + .CLK(clk), + .D(_0406_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata1 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3183_ ( + .CLK(clk), + .D(_0407_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata1 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3184_ ( + .CLK(clk), + .D(_0408_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata1 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3185_ ( + .CLK(clk), + .D(_0409_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata1 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3186_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.bufreg.q ), + .EN(_0626_), + .Q(\corescorecore.core_2.serving.cpu.bufreg.o_lsb [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3187_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.we ), + .EN(1'h1), + .Q(_0979_), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3188_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3189_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3190_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3191_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3192_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3193_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3194_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3195_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_1213_[0]), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3196_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3197_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3198_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3199_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3200_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3201_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3202_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3203_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0379_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3204_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [0]), + .EN(1'h1), + .Q(_0968_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3205_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [1]), + .EN(1'h1), + .Q(_0968_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3206_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [2]), + .EN(1'h1), + .Q(_0968_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3207_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [3]), + .EN(1'h1), + .Q(_0968_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3208_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [4]), + .EN(1'h1), + .Q(_0968_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3209_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [5]), + .EN(1'h1), + .Q(_0968_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3210_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [6]), + .EN(1'h1), + .Q(_0968_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3211_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.wdata [7]), + .EN(1'h1), + .Q(_0968_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3212_ ( + .CLK(clk), + .D(_0410_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3213_ ( + .CLK(clk), + .D(_0411_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata0 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3214_ ( + .CLK(clk), + .D(_0412_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata0 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3215_ ( + .CLK(clk), + .D(_0413_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata0 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3216_ ( + .CLK(clk), + .D(_0414_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata0 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3217_ ( + .CLK(clk), + .D(_0415_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata0 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3218_ ( + .CLK(clk), + .D(_0416_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata0 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3219_ ( + .CLK(clk), + .D(_0417_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata1 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3220_ ( + .CLK(clk), + .D(_0418_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata1 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3221_ ( + .CLK(clk), + .D(_0419_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata1 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3222_ ( + .CLK(clk), + .D(_0420_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata1 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3223_ ( + .CLK(clk), + .D(_0421_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata1 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3224_ ( + .CLK(clk), + .D(_0422_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata1 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3225_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.bufreg.q ), + .EN(_0703_), + .Q(\corescorecore.core_3.serving.cpu.bufreg.o_lsb [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3226_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.raddr [7]), + .EN(1'h1), + .Q(_0973_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3227_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.we ), + .EN(1'h1), + .Q(_0981_), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3228_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.raddr [7]), + .EN(1'h1), + .Q(_0975_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3229_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [0]), + .EN(1'h1), + .Q(_0971_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3230_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [1]), + .EN(1'h1), + .Q(_0971_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3231_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [2]), + .EN(1'h1), + .Q(_0971_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3232_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [3]), + .EN(1'h1), + .Q(_0971_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3233_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [4]), + .EN(1'h1), + .Q(_0971_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3234_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [5]), + .EN(1'h1), + .Q(_0971_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3235_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [6]), + .EN(1'h1), + .Q(_0971_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3236_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.wdata [7]), + .EN(1'h1), + .Q(_0971_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3237_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.raddr [7]), + .EN(1'h1), + .Q(_0972_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3238_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.we ), + .EN(1'h1), + .Q(_0978_), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3239_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3240_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3241_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3242_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3243_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3244_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3245_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3246_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_1202_[0]), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3247_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [0]), + .EN(1'h1), + .Q(_0969_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3248_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [1]), + .EN(1'h1), + .Q(_0969_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3249_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [2]), + .EN(1'h1), + .Q(_0969_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3250_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [3]), + .EN(1'h1), + .Q(_0969_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3251_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [4]), + .EN(1'h1), + .Q(_0969_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3252_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [5]), + .EN(1'h1), + .Q(_0969_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3253_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [6]), + .EN(1'h1), + .Q(_0969_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3254_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.wdata [7]), + .EN(1'h1), + .Q(_0969_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3255_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3256_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3257_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3258_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3259_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3260_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3261_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3262_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_1194_[0]), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3263_ ( + .CLK(clk), + .D(_0332_), + .EN(1'h1), + .Q(\emitter.data [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3264_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3265_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3266_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3267_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3268_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3269_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3270_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3271_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0375_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:34.1-42.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3272_ ( + .CLK(\clkgen.i_clk ), + .D(_0333_), + .EN(1'h1), + .Q(\clkgen.o_rst_core ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3273_ ( + .CLK(clk), + .D(_0334_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.m_axis_tready_int_reg ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3274_ ( + .CLK(clk), + .D(_0335_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.m_axis_tvalid ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3275_ ( + .CLK(clk), + .D(_0457_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3276_ ( + .CLK(clk), + .D(_0458_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3277_ ( + .CLK(clk), + .D(_0459_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3278_ ( + .CLK(clk), + .D(_0460_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3279_ ( + .CLK(clk), + .D(_0461_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3280_ ( + .CLK(clk), + .D(_0462_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3281_ ( + .CLK(clk), + .D(_0463_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3282_ ( + .CLK(clk), + .D(_0464_), + .EN(_0012_), + .Q(\corescorecore.axis_mux.m_axis_tdata [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3283_ ( + .CLK(clk), + .D(_0336_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.temp_m_axis_tvalid_reg ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3284_ ( + .CLK(clk), + .D(_0337_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3285_ ( + .CLK(clk), + .D(_0338_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3286_ ( + .CLK(clk), + .D(_0339_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3287_ ( + .CLK(clk), + .D(_0340_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3288_ ( + .CLK(clk), + .D(_0341_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3289_ ( + .CLK(clk), + .D(_0342_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant_valid ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3290_ ( + .CLK(clk), + .D(_0343_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3291_ ( + .CLK(clk), + .D(_0344_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3292_ ( + .CLK(clk), + .D(_0345_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.grant_encoded [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3293_ ( + .CLK(clk), + .D(_0346_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.mask_reg [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3294_ ( + .CLK(clk), + .D(_0347_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.mask_reg [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3295_ ( + .CLK(clk), + .D(_0348_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.mask_reg [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3296_ ( + .CLK(clk), + .D(_0349_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.mask_reg [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/arbiter.v:139.1-151.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3297_ ( + .CLK(clk), + .D(_0350_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.arb_inst.mask_reg [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3298_ ( + .CLK(clk), + .D(_0351_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3299_ ( + .CLK(clk), + .D(_0352_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.i_init ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3300_ ( + .CLK(clk), + .D(_0353_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.i_en ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3301_ ( + .CLK(clk), + .D(_0848_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.i_cnt_done ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3302_ ( + .CLK(clk), + .D(_0354_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.ctrl.i_jump ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3303_ ( + .CLK(clk), + .D(_1036_[2]), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.state.stage_two_req ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3304_ ( + .CLK(clk), + .D(_0816_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [32]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3305_ ( + .CLK(clk), + .D(_0827_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [33]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3306_ ( + .CLK(clk), + .D(_0838_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [34]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3307_ ( + .CLK(clk), + .D(_0841_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [35]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3308_ ( + .CLK(clk), + .D(_0842_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [36]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3309_ ( + .CLK(clk), + .D(_0843_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [37]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3310_ ( + .CLK(clk), + .D(_0844_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [38]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3311_ ( + .CLK(clk), + .D(_0845_), + .EN(_0002_), + .Q(\corescorecore.axis_mux.s_axis_tdata [39]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3312_ ( + .CLK(clk), + .D(_0846_), + .EN(_0002_), + .Q(\corescorecore.core_4.o_tlast ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3313_ ( + .CLK(clk), + .D(_0847_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3314_ ( + .CLK(clk), + .D(_0817_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3315_ ( + .CLK(clk), + .D(_0818_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3316_ ( + .CLK(clk), + .D(_0819_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3317_ ( + .CLK(clk), + .D(_0820_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3318_ ( + .CLK(clk), + .D(_0821_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3319_ ( + .CLK(clk), + .D(_0822_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3320_ ( + .CLK(clk), + .D(_0823_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3321_ ( + .CLK(clk), + .D(_0824_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3322_ ( + .CLK(clk), + .D(_0825_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3323_ ( + .CLK(clk), + .D(_0826_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3324_ ( + .CLK(clk), + .D(_0828_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3325_ ( + .CLK(clk), + .D(_0829_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3326_ ( + .CLK(clk), + .D(_0830_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3327_ ( + .CLK(clk), + .D(_0831_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3328_ ( + .CLK(clk), + .D(_0832_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3329_ ( + .CLK(clk), + .D(_0833_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3330_ ( + .CLK(clk), + .D(_0834_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3331_ ( + .CLK(clk), + .D(_0835_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3332_ ( + .CLK(clk), + .D(_0836_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3333_ ( + .CLK(clk), + .D(_0837_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3334_ ( + .CLK(clk), + .D(_0839_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3335_ ( + .CLK(clk), + .D(_0840_), + .EN(_0002_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3336_ ( + .CLK(clk), + .D(_0355_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.state.o_cnt_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3337_ ( + .CLK(clk), + .D(_0356_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.state.o_cnt_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3338_ ( + .CLK(clk), + .D(_0357_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.state.o_cnt_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3339_ ( + .CLK(clk), + .D(_0358_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.state.o_cnt_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3340_ ( + .CLK(clk), + .D(_0359_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.state.stage_two_pending ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3341_ ( + .CLK(clk), + .D(_0799_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm24_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3342_ ( + .CLK(clk), + .D(_0800_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm24_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3343_ ( + .CLK(clk), + .D(_0801_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm24_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3344_ ( + .CLK(clk), + .D(_0802_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm24_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3345_ ( + .CLK(clk), + .D(_0803_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm24_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3346_ ( + .CLK(clk), + .D(_0804_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm30_25 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3347_ ( + .CLK(clk), + .D(_0805_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm30_25 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3348_ ( + .CLK(clk), + .D(_0806_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm30_25 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3349_ ( + .CLK(clk), + .D(_0807_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm30_25 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3350_ ( + .CLK(clk), + .D(_0808_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm30_25 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3351_ ( + .CLK(clk), + .D(_0809_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm30_25 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3352_ ( + .CLK(clk), + .D(_0810_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm7 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3353_ ( + .CLK(clk), + .D(_0790_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3354_ ( + .CLK(clk), + .D(_0791_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3355_ ( + .CLK(clk), + .D(_0792_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3356_ ( + .CLK(clk), + .D(_0793_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3357_ ( + .CLK(clk), + .D(_0794_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3358_ ( + .CLK(clk), + .D(_0795_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3359_ ( + .CLK(clk), + .D(_0796_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3360_ ( + .CLK(clk), + .D(_0797_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3361_ ( + .CLK(clk), + .D(_0798_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm19_12_20 [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3362_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.i_sh_signed ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3363_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [12]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3364_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [13]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_mem_word ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3365_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [14]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.i_sh_right ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3366_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [2]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.opcode [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3367_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [3]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.opcode [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3368_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [4]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.opcode [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3369_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [5]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3370_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [6]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.m3 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3371_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3372_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [20]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3373_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [21]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3374_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [22]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3375_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [23]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3376_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs2_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3377_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [7]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3378_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [8]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3379_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [9]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3380_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [10]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3381_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [11]), + .EN(\corescorecore.core_4.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3382_ ( + .CLK(clk), + .D(_0811_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.csr_imm ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3383_ ( + .CLK(clk), + .D(_0812_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3384_ ( + .CLK(clk), + .D(_0813_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3385_ ( + .CLK(clk), + .D(_0814_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3386_ ( + .CLK(clk), + .D(_0815_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3387_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.bufreg.q ), + .EN(_0781_), + .Q(\corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3388_ ( + .CLK(clk), + .D(_0779_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.bufreg.c_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3389_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.bufreg.data [1]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.cpu.alu.i_buf ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3390_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.cpu.bufreg.data [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3391_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3392_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3393_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3394_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3395_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3396_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3397_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3398_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3399_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3400_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3401_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3402_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3403_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3404_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3405_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3406_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3407_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3408_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3409_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3410_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3411_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3412_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3413_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3414_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3415_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3416_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3417_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3418_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3419_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3420_ ( + .CLK(clk), + .D(_0782_), + .EN(\corescorecore.core_4.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3421_ ( + .CLK(clk), + .D(_0778_), + .EN(\corescorecore.core_4.serving.cpu.alu.i_init ), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3422_ ( + .CLK(clk), + .D(_0784_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3423_ ( + .CLK(clk), + .D(_0783_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.ctrl.pc_plus_4_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3424_ ( + .CLK(clk), + .D(_0360_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.ctrl.en_pc_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3425_ ( + .CLK(clk), + .D(_0361_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.ctrl.pc ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3426_ ( + .CLK(clk), + .D(_0362_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3427_ ( + .CLK(clk), + .D(_0363_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3428_ ( + .CLK(clk), + .D(_0364_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3429_ ( + .CLK(clk), + .D(_0365_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3430_ ( + .CLK(clk), + .D(_0366_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3431_ ( + .CLK(clk), + .D(_0367_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3432_ ( + .CLK(clk), + .D(_0368_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3433_ ( + .CLK(clk), + .D(_0369_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3434_ ( + .CLK(clk), + .D(_0370_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3435_ ( + .CLK(clk), + .D(_0371_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3436_ ( + .CLK(clk), + .D(_0372_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3437_ ( + .CLK(clk), + .D(_0373_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3438_ ( + .CLK(clk), + .D(_0013_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3439_ ( + .CLK(clk), + .D(_0014_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3440_ ( + .CLK(clk), + .D(_0015_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3441_ ( + .CLK(clk), + .D(_0016_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3442_ ( + .CLK(clk), + .D(_0017_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3443_ ( + .CLK(clk), + .D(_0018_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3444_ ( + .CLK(clk), + .D(_0019_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3445_ ( + .CLK(clk), + .D(_0020_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3446_ ( + .CLK(clk), + .D(_0021_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3447_ ( + .CLK(clk), + .D(_0022_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3448_ ( + .CLK(clk), + .D(_0023_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3449_ ( + .CLK(clk), + .D(_0024_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3450_ ( + .CLK(clk), + .D(_0025_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3451_ ( + .CLK(clk), + .D(_0026_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3452_ ( + .CLK(clk), + .D(_0027_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3453_ ( + .CLK(clk), + .D(_0028_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3454_ ( + .CLK(clk), + .D(_0029_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3455_ ( + .CLK(clk), + .D(_0030_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3456_ ( + .CLK(clk), + .D(_0031_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3457_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy ), + .EN(\corescorecore.core_4.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.shamt_msb ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3458_ ( + .CLK(clk), + .D(_0777_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.wrapped ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3459_ ( + .CLK(clk), + .D(_0032_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.cnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3460_ ( + .CLK(clk), + .D(_0033_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.cnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3461_ ( + .CLK(clk), + .D(_0034_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3462_ ( + .CLK(clk), + .D(_0035_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.cnt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3463_ ( + .CLK(clk), + .D(_0036_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.cnt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3464_ ( + .CLK(clk), + .D(_0037_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.shift.cnt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3465_ ( + .CLK(clk), + .D(_0775_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.eq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3466_ ( + .CLK(clk), + .D(_0776_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3467_ ( + .CLK(clk), + .D(_0774_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3468_ ( + .CLK(clk), + .D(_0773_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.add_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3469_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.alu.shamt [1]), + .EN(\corescorecore.core_4.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.shamt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3470_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.alu.shamt [2]), + .EN(\corescorecore.core_4.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.shamt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3471_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.alu.shamt [3]), + .EN(\corescorecore.core_4.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.shamt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3472_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.alu.shamt [4]), + .EN(\corescorecore.core_4.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.shamt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3473_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.alu.shamt_ser ), + .EN(\corescorecore.core_4.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.shamt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3474_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.alu.result_lt ), + .EN(\corescorecore.core_4.serving.cpu.alu.i_en ), + .Q(\corescorecore.core_4.serving.cpu.alu.result_lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/wb2axis.v:15.4-19.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3475_ ( + .CLK(clk), + .D(_0038_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.i_wb_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3476_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.mem_if.dat_cur ), + .EN(\corescorecore.core_4.serving.cpu.mem_if.dat_valid ), + .Q(\corescorecore.core_4.serving.cpu.mem_if.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3477_ ( + .CLK(clk), + .D(_0785_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm11_7 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3478_ ( + .CLK(clk), + .D(_0786_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm11_7 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3479_ ( + .CLK(clk), + .D(_0787_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm11_7 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3480_ ( + .CLK(clk), + .D(_0788_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm11_7 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3481_ ( + .CLK(clk), + .D(_0789_), + .EN(_0003_), + .Q(\corescorecore.core_4.serving.cpu.decode.imm11_7 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3482_ ( + .CLK(clk), + .D(_0430_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata1 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3483_ ( + .CLK(clk), + .D(_0431_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata1 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3484_ ( + .CLK(clk), + .D(_0432_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata1 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3485_ ( + .CLK(clk), + .D(_0433_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata1 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3486_ ( + .CLK(clk), + .D(_0434_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata1 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3487_ ( + .CLK(clk), + .D(_0435_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata1 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3488_ ( + .CLK(clk), + .D(_0423_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3489_ ( + .CLK(clk), + .D(_0424_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata0 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3490_ ( + .CLK(clk), + .D(_0425_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata0 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3491_ ( + .CLK(clk), + .D(_0426_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata0 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3492_ ( + .CLK(clk), + .D(_0427_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata0 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3493_ ( + .CLK(clk), + .D(_0428_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata0 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3494_ ( + .CLK(clk), + .D(_0429_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata0 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3495_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3496_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3497_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3498_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3499_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3500_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3501_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3502_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0374_), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3503_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [1]), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3504_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [2]), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3505_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [3]), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3506_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [4]), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3507_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [5]), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3508_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [6]), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3509_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.o_wdata0 ), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wdata0_r [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:55.7-55.50|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3510_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.wtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3511_ ( + .CLK(clk), + .D(_0039_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata1 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3512_ ( + .CLK(clk), + .D(_0040_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata0 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3513_ ( + .CLK(clk), + .D(_0041_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rgnt ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3514_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.rf_ram_if.rtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rtrig1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3515_ ( + .CLK(clk), + .D(_0042_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3516_ ( + .CLK(clk), + .D(_0043_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3517_ ( + .CLK(clk), + .D(_0044_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3518_ ( + .CLK(clk), + .D(_0045_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.raddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3519_ ( + .CLK(clk), + .D(_0046_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.raddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3520_ ( + .CLK(clk), + .D(_0047_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3521_ ( + .CLK(clk), + .D(_0048_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3522_ ( + .CLK(clk), + .D(_0049_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3523_ ( + .CLK(clk), + .D(_0050_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.o_waddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3524_ ( + .CLK(clk), + .D(_0051_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.o_waddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3525_ ( + .CLK(clk), + .D(_0052_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wgo ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3526_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.o_wen0 ), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wen0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3527_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.i_rf_ready ), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.wreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3528_ ( + .CLK(clk), + .D(_0849_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.arbiter.i_wb_mem_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3529_ ( + .CLK(clk), + .D(_0053_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.state.o_cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3530_ ( + .CLK(clk), + .D(_0054_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.mem_bytecnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3531_ ( + .CLK(clk), + .D(_0055_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.mem_bytecnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3532_ ( + .CLK(clk), + .D(_0885_[0]), + .EN(\corescorecore.core_4.serving.ram.wb_en ), + .Q(\corescorecore.core_4.serving.ram.bsel [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3533_ ( + .CLK(clk), + .D(_0886_[1]), + .EN(\corescorecore.core_4.serving.ram.wb_en ), + .Q(\corescorecore.core_4.serving.ram.bsel [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3534_ ( + .CLK(clk), + .D(_0056_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3535_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.we ), + .EN(1'h1), + .Q(_0980_), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3536_ ( + .CLK(clk), + .D(_0057_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.i_init ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3537_ ( + .CLK(clk), + .D(_0058_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.i_en ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3538_ ( + .CLK(clk), + .D(_0771_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.i_cnt_done ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3539_ ( + .CLK(clk), + .D(_0059_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.ctrl.i_jump ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3540_ ( + .CLK(clk), + .D(_1093_[2]), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.state.stage_two_req ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3541_ ( + .CLK(clk), + .D(_0739_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3542_ ( + .CLK(clk), + .D(_0750_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3543_ ( + .CLK(clk), + .D(_0761_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3544_ ( + .CLK(clk), + .D(_0764_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3545_ ( + .CLK(clk), + .D(_0765_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3546_ ( + .CLK(clk), + .D(_0766_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3547_ ( + .CLK(clk), + .D(_0767_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3548_ ( + .CLK(clk), + .D(_0768_), + .EN(_0004_), + .Q(\corescorecore.axis_mux.s_axis_tdata [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3549_ ( + .CLK(clk), + .D(_0769_), + .EN(_0004_), + .Q(\corescorecore.core_3.o_tlast ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3550_ ( + .CLK(clk), + .D(_0770_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3551_ ( + .CLK(clk), + .D(_0740_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3552_ ( + .CLK(clk), + .D(_0741_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3553_ ( + .CLK(clk), + .D(_0742_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3554_ ( + .CLK(clk), + .D(_0743_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3555_ ( + .CLK(clk), + .D(_0744_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3556_ ( + .CLK(clk), + .D(_0745_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3557_ ( + .CLK(clk), + .D(_0746_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3558_ ( + .CLK(clk), + .D(_0747_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3559_ ( + .CLK(clk), + .D(_0748_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3560_ ( + .CLK(clk), + .D(_0749_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3561_ ( + .CLK(clk), + .D(_0751_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3562_ ( + .CLK(clk), + .D(_0752_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3563_ ( + .CLK(clk), + .D(_0753_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3564_ ( + .CLK(clk), + .D(_0754_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3565_ ( + .CLK(clk), + .D(_0755_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3566_ ( + .CLK(clk), + .D(_0756_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3567_ ( + .CLK(clk), + .D(_0757_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3568_ ( + .CLK(clk), + .D(_0758_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3569_ ( + .CLK(clk), + .D(_0759_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3570_ ( + .CLK(clk), + .D(_0760_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3571_ ( + .CLK(clk), + .D(_0762_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3572_ ( + .CLK(clk), + .D(_0763_), + .EN(_0004_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3573_ ( + .CLK(clk), + .D(_0060_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.state.o_cnt_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3574_ ( + .CLK(clk), + .D(_0061_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.state.o_cnt_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3575_ ( + .CLK(clk), + .D(_0062_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.state.o_cnt_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3576_ ( + .CLK(clk), + .D(_0063_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.state.o_cnt_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3577_ ( + .CLK(clk), + .D(_0064_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.state.stage_two_pending ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3578_ ( + .CLK(clk), + .D(_0722_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm24_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3579_ ( + .CLK(clk), + .D(_0723_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm24_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3580_ ( + .CLK(clk), + .D(_0724_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm24_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3581_ ( + .CLK(clk), + .D(_0725_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm24_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3582_ ( + .CLK(clk), + .D(_0726_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm24_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3583_ ( + .CLK(clk), + .D(_0727_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm30_25 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3584_ ( + .CLK(clk), + .D(_0728_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm30_25 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3585_ ( + .CLK(clk), + .D(_0729_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm30_25 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3586_ ( + .CLK(clk), + .D(_0730_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm30_25 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3587_ ( + .CLK(clk), + .D(_0731_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm30_25 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3588_ ( + .CLK(clk), + .D(_0732_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm30_25 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3589_ ( + .CLK(clk), + .D(_0733_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm7 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3590_ ( + .CLK(clk), + .D(_0713_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3591_ ( + .CLK(clk), + .D(_0714_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3592_ ( + .CLK(clk), + .D(_0715_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3593_ ( + .CLK(clk), + .D(_0716_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3594_ ( + .CLK(clk), + .D(_0717_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3595_ ( + .CLK(clk), + .D(_0718_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3596_ ( + .CLK(clk), + .D(_0719_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3597_ ( + .CLK(clk), + .D(_0720_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3598_ ( + .CLK(clk), + .D(_0721_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm19_12_20 [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3599_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.i_sh_signed ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3600_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [12]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3601_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [13]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_mem_word ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3602_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [14]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.i_sh_right ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3603_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [2]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.opcode [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3604_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [3]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.opcode [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3605_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [4]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.opcode [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3606_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [5]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3607_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [6]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.m3 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3608_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3609_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [20]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3610_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [21]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3611_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [22]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3612_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [23]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3613_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs2_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3614_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [7]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3615_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [8]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3616_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [9]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3617_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [10]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3618_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [11]), + .EN(\corescorecore.core_3.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3619_ ( + .CLK(clk), + .D(_0734_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.csr_imm ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3620_ ( + .CLK(clk), + .D(_0735_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3621_ ( + .CLK(clk), + .D(_0736_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3622_ ( + .CLK(clk), + .D(_0737_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3623_ ( + .CLK(clk), + .D(_0738_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3624_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.bufreg.q ), + .EN(_0704_), + .Q(\corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3625_ ( + .CLK(clk), + .D(_0702_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.bufreg.c_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3626_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.bufreg.data [1]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.cpu.alu.i_buf ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3627_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.cpu.bufreg.data [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3628_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3629_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3630_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3631_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3632_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3633_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3634_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3635_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3636_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3637_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3638_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3639_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3640_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3641_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3642_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3643_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3644_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3645_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3646_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3647_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3648_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3649_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3650_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3651_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3652_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3653_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3654_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3655_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3656_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3657_ ( + .CLK(clk), + .D(_0705_), + .EN(\corescorecore.core_3.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3658_ ( + .CLK(clk), + .D(_0701_), + .EN(\corescorecore.core_3.serving.cpu.alu.i_init ), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3659_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.raddr [7]), + .EN(1'h1), + .Q(_0974_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3660_ ( + .CLK(clk), + .D(_0707_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3661_ ( + .CLK(clk), + .D(_0706_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.ctrl.pc_plus_4_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3662_ ( + .CLK(clk), + .D(_0065_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.ctrl.en_pc_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3663_ ( + .CLK(clk), + .D(_0066_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.ctrl.pc ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3664_ ( + .CLK(clk), + .D(_0067_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3665_ ( + .CLK(clk), + .D(_0068_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3666_ ( + .CLK(clk), + .D(_0069_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3667_ ( + .CLK(clk), + .D(_0070_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3668_ ( + .CLK(clk), + .D(_0071_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3669_ ( + .CLK(clk), + .D(_0072_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3670_ ( + .CLK(clk), + .D(_0073_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3671_ ( + .CLK(clk), + .D(_0074_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3672_ ( + .CLK(clk), + .D(_0075_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3673_ ( + .CLK(clk), + .D(_0076_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3674_ ( + .CLK(clk), + .D(_0077_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3675_ ( + .CLK(clk), + .D(_0078_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3676_ ( + .CLK(clk), + .D(_0079_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3677_ ( + .CLK(clk), + .D(_0080_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3678_ ( + .CLK(clk), + .D(_0081_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3679_ ( + .CLK(clk), + .D(_0082_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3680_ ( + .CLK(clk), + .D(_0083_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3681_ ( + .CLK(clk), + .D(_0084_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3682_ ( + .CLK(clk), + .D(_0085_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3683_ ( + .CLK(clk), + .D(_0086_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3684_ ( + .CLK(clk), + .D(_0087_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3685_ ( + .CLK(clk), + .D(_0088_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3686_ ( + .CLK(clk), + .D(_0089_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3687_ ( + .CLK(clk), + .D(_0090_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3688_ ( + .CLK(clk), + .D(_0091_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3689_ ( + .CLK(clk), + .D(_0092_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3690_ ( + .CLK(clk), + .D(_0093_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3691_ ( + .CLK(clk), + .D(_0094_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3692_ ( + .CLK(clk), + .D(_0095_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3693_ ( + .CLK(clk), + .D(_0096_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3694_ ( + .CLK(clk), + .D(_0097_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3695_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [0]), + .EN(1'h1), + .Q(_0970_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3696_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [1]), + .EN(1'h1), + .Q(_0970_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3697_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [2]), + .EN(1'h1), + .Q(_0970_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3698_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [3]), + .EN(1'h1), + .Q(_0970_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3699_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [4]), + .EN(1'h1), + .Q(_0970_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3700_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [5]), + .EN(1'h1), + .Q(_0970_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3701_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [6]), + .EN(1'h1), + .Q(_0970_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3702_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.wdata [7]), + .EN(1'h1), + .Q(_0970_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3703_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy ), + .EN(\corescorecore.core_3.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.shamt_msb ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3704_ ( + .CLK(clk), + .D(_0700_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.wrapped ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3705_ ( + .CLK(clk), + .D(_0098_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.cnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3706_ ( + .CLK(clk), + .D(_0099_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.cnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3707_ ( + .CLK(clk), + .D(_0100_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3708_ ( + .CLK(clk), + .D(_0101_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.cnt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3709_ ( + .CLK(clk), + .D(_0102_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.cnt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3710_ ( + .CLK(clk), + .D(_0103_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.shift.cnt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3711_ ( + .CLK(clk), + .D(_0698_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.eq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3712_ ( + .CLK(clk), + .D(_0699_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3713_ ( + .CLK(clk), + .D(_0697_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3714_ ( + .CLK(clk), + .D(_0696_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.alu.add_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3715_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.alu.shamt [1]), + .EN(\corescorecore.core_3.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.shamt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3716_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.alu.shamt [2]), + .EN(\corescorecore.core_3.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.shamt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3717_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.alu.shamt [3]), + .EN(\corescorecore.core_3.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.shamt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3718_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.alu.shamt [4]), + .EN(\corescorecore.core_3.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.shamt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3719_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.alu.shamt_ser ), + .EN(\corescorecore.core_3.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.shamt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3720_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.alu.result_lt ), + .EN(\corescorecore.core_3.serving.cpu.alu.i_en ), + .Q(\corescorecore.core_3.serving.cpu.alu.result_lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/wb2axis.v:15.4-19.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3721_ ( + .CLK(clk), + .D(_0104_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.i_wb_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3722_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.mem_if.dat_cur ), + .EN(\corescorecore.core_3.serving.cpu.mem_if.dat_valid ), + .Q(\corescorecore.core_3.serving.cpu.mem_if.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3723_ ( + .CLK(clk), + .D(_0708_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm11_7 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3724_ ( + .CLK(clk), + .D(_0709_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm11_7 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3725_ ( + .CLK(clk), + .D(_0710_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm11_7 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3726_ ( + .CLK(clk), + .D(_0711_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm11_7 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3727_ ( + .CLK(clk), + .D(_0712_), + .EN(_0005_), + .Q(\corescorecore.core_3.serving.cpu.decode.imm11_7 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3728_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.cpu.bufreg.q ), + .EN(_0780_), + .Q(\corescorecore.core_4.serving.cpu.bufreg.o_lsb [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3729_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3730_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3731_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3732_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3733_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3734_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3735_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3736_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0376_), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3737_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [1]), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3738_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [2]), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3739_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [3]), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3740_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [4]), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3741_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [5]), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3742_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [6]), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3743_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.o_wdata0 ), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wdata0_r [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:55.7-55.50|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3744_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.wtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3745_ ( + .CLK(clk), + .D(_0105_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata1 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3746_ ( + .CLK(clk), + .D(_0106_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rdata0 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3747_ ( + .CLK(clk), + .D(_0107_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rgnt ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3748_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.rf_ram_if.rtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rtrig1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3749_ ( + .CLK(clk), + .D(_0108_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3750_ ( + .CLK(clk), + .D(_0109_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3751_ ( + .CLK(clk), + .D(_0110_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.rcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3752_ ( + .CLK(clk), + .D(_0111_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.raddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3753_ ( + .CLK(clk), + .D(_0112_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.raddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3754_ ( + .CLK(clk), + .D(_0113_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3755_ ( + .CLK(clk), + .D(_0114_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3756_ ( + .CLK(clk), + .D(_0115_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3757_ ( + .CLK(clk), + .D(_0116_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.o_waddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3758_ ( + .CLK(clk), + .D(_0117_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.o_waddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3759_ ( + .CLK(clk), + .D(_0118_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wgo ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3760_ ( + .CLK(clk), + .D(_0119_), + .EN(1'h1), + .Q(\emitter.cnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3761_ ( + .CLK(clk), + .D(_0120_), + .EN(1'h1), + .Q(\emitter.cnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3762_ ( + .CLK(clk), + .D(_0121_), + .EN(1'h1), + .Q(\emitter.cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3763_ ( + .CLK(clk), + .D(_0122_), + .EN(1'h1), + .Q(\emitter.cnt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3764_ ( + .CLK(clk), + .D(_0123_), + .EN(1'h1), + .Q(\emitter.cnt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3765_ ( + .CLK(clk), + .D(_0124_), + .EN(1'h1), + .Q(\emitter.cnt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3766_ ( + .CLK(clk), + .D(_0125_), + .EN(1'h1), + .Q(\emitter.cnt [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3767_ ( + .CLK(clk), + .D(_0126_), + .EN(1'h1), + .Q(\emitter.cnt [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3768_ ( + .CLK(clk), + .D(_0127_), + .EN(1'h1), + .Q(\emitter.cnt [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3769_ ( + .CLK(clk), + .D(_0128_), + .EN(1'h1), + .Q(\emitter.cnt [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3770_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.o_wen0 ), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wen0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3771_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.cpu.i_rf_ready ), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.rf_ram_if.wreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3772_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [0]), + .EN(1'h1), + .Q(_0967_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3773_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [1]), + .EN(1'h1), + .Q(_0967_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3774_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [2]), + .EN(1'h1), + .Q(_0967_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3775_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [3]), + .EN(1'h1), + .Q(_0967_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3776_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [4]), + .EN(1'h1), + .Q(_0967_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3777_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [5]), + .EN(1'h1), + .Q(_0967_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3778_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [6]), + .EN(1'h1), + .Q(_0967_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3779_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.wdata [7]), + .EN(1'h1), + .Q(_0967_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3780_ ( + .CLK(clk), + .D(_0772_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.arbiter.i_wb_mem_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3781_ ( + .CLK(clk), + .D(_0129_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.state.o_cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3782_ ( + .CLK(clk), + .D(_0130_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.mem_bytecnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3783_ ( + .CLK(clk), + .D(_0131_), + .EN(1'h1), + .Q(\corescorecore.core_3.serving.cpu.mem_bytecnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3784_ ( + .CLK(clk), + .D(_0909_[0]), + .EN(\corescorecore.core_3.serving.ram.wb_en ), + .Q(\corescorecore.core_3.serving.ram.bsel [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3785_ ( + .CLK(clk), + .D(_0910_[1]), + .EN(\corescorecore.core_3.serving.ram.wb_en ), + .Q(\corescorecore.core_3.serving.ram.bsel [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3786_ ( + .CLK(clk), + .D(_0132_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3787_ ( + .CLK(clk), + .D(_0133_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.i_init ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3788_ ( + .CLK(clk), + .D(_0134_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.i_en ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3789_ ( + .CLK(clk), + .D(_0694_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.i_cnt_done ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3790_ ( + .CLK(clk), + .D(_0135_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.ctrl.i_jump ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3791_ ( + .CLK(clk), + .D(_1173_[2]), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.state.stage_two_req ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3792_ ( + .CLK(clk), + .D(_0662_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3793_ ( + .CLK(clk), + .D(_0673_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3794_ ( + .CLK(clk), + .D(_0684_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3795_ ( + .CLK(clk), + .D(_0687_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3796_ ( + .CLK(clk), + .D(_0688_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3797_ ( + .CLK(clk), + .D(_0689_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3798_ ( + .CLK(clk), + .D(_0690_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3799_ ( + .CLK(clk), + .D(_0691_), + .EN(_0006_), + .Q(\corescorecore.axis_mux.s_axis_tdata [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3800_ ( + .CLK(clk), + .D(_0692_), + .EN(_0006_), + .Q(\corescorecore.core_2.o_tlast ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3801_ ( + .CLK(clk), + .D(_0693_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3802_ ( + .CLK(clk), + .D(_0663_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3803_ ( + .CLK(clk), + .D(_0664_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3804_ ( + .CLK(clk), + .D(_0665_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3805_ ( + .CLK(clk), + .D(_0666_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3806_ ( + .CLK(clk), + .D(_0667_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3807_ ( + .CLK(clk), + .D(_0668_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3808_ ( + .CLK(clk), + .D(_0669_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3809_ ( + .CLK(clk), + .D(_0670_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3810_ ( + .CLK(clk), + .D(_0671_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3811_ ( + .CLK(clk), + .D(_0672_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3812_ ( + .CLK(clk), + .D(_0674_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3813_ ( + .CLK(clk), + .D(_0675_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3814_ ( + .CLK(clk), + .D(_0676_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3815_ ( + .CLK(clk), + .D(_0677_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3816_ ( + .CLK(clk), + .D(_0678_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3817_ ( + .CLK(clk), + .D(_0679_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3818_ ( + .CLK(clk), + .D(_0680_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3819_ ( + .CLK(clk), + .D(_0681_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3820_ ( + .CLK(clk), + .D(_0682_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3821_ ( + .CLK(clk), + .D(_0683_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3822_ ( + .CLK(clk), + .D(_0685_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3823_ ( + .CLK(clk), + .D(_0686_), + .EN(_0006_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3824_ ( + .CLK(clk), + .D(_0136_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.state.o_cnt_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3825_ ( + .CLK(clk), + .D(_0137_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.state.o_cnt_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3826_ ( + .CLK(clk), + .D(_0138_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.state.o_cnt_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3827_ ( + .CLK(clk), + .D(_0139_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.state.o_cnt_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3828_ ( + .CLK(clk), + .D(_0140_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.state.stage_two_pending ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3829_ ( + .CLK(clk), + .D(_0645_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm24_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3830_ ( + .CLK(clk), + .D(_0646_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm24_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3831_ ( + .CLK(clk), + .D(_0647_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm24_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3832_ ( + .CLK(clk), + .D(_0648_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm24_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3833_ ( + .CLK(clk), + .D(_0649_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm24_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3834_ ( + .CLK(clk), + .D(_0650_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm30_25 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3835_ ( + .CLK(clk), + .D(_0651_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm30_25 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3836_ ( + .CLK(clk), + .D(_0652_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm30_25 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3837_ ( + .CLK(clk), + .D(_0653_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm30_25 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3838_ ( + .CLK(clk), + .D(_0654_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm30_25 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3839_ ( + .CLK(clk), + .D(_0655_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm30_25 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3840_ ( + .CLK(clk), + .D(_0656_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm7 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3841_ ( + .CLK(clk), + .D(_0636_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3842_ ( + .CLK(clk), + .D(_0637_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3843_ ( + .CLK(clk), + .D(_0638_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3844_ ( + .CLK(clk), + .D(_0639_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3845_ ( + .CLK(clk), + .D(_0640_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3846_ ( + .CLK(clk), + .D(_0641_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3847_ ( + .CLK(clk), + .D(_0642_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3848_ ( + .CLK(clk), + .D(_0643_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3849_ ( + .CLK(clk), + .D(_0644_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm19_12_20 [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3850_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.i_sh_signed ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3851_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [12]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3852_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [13]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_mem_word ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3853_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [14]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.i_sh_right ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3854_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [2]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.opcode [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3855_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [3]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.opcode [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3856_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [4]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.opcode [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3857_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [5]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3858_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [6]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.m3 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3859_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3860_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [20]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3861_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [21]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3862_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [22]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3863_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [23]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3864_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs2_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3865_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [7]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3866_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [8]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3867_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [9]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3868_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [10]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3869_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [11]), + .EN(\corescorecore.core_2.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3870_ ( + .CLK(clk), + .D(_0657_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.csr_imm ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3871_ ( + .CLK(clk), + .D(_0658_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3872_ ( + .CLK(clk), + .D(_0659_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3873_ ( + .CLK(clk), + .D(_0660_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3874_ ( + .CLK(clk), + .D(_0661_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3875_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.bufreg.q ), + .EN(_0627_), + .Q(\corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3876_ ( + .CLK(clk), + .D(_0625_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.bufreg.c_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3877_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.bufreg.data [1]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.cpu.alu.i_buf ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3878_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.cpu.bufreg.data [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3879_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3880_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3881_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3882_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3883_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3884_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3885_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3886_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3887_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3888_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3889_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3890_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3891_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3892_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3893_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3894_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3895_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3896_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3897_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3898_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3899_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3900_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3901_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3902_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3903_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3904_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3905_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3906_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3907_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3908_ ( + .CLK(clk), + .D(_0628_), + .EN(\corescorecore.core_2.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3909_ ( + .CLK(clk), + .D(_0624_), + .EN(\corescorecore.core_2.serving.cpu.alu.i_init ), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3910_ ( + .CLK(clk), + .D(_0630_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3911_ ( + .CLK(clk), + .D(_0629_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.ctrl.pc_plus_4_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3912_ ( + .CLK(clk), + .D(_0141_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.ctrl.en_pc_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3913_ ( + .CLK(clk), + .D(_0142_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.ctrl.pc ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3914_ ( + .CLK(clk), + .D(_0143_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3915_ ( + .CLK(clk), + .D(_0144_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3916_ ( + .CLK(clk), + .D(_0145_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3917_ ( + .CLK(clk), + .D(_0146_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3918_ ( + .CLK(clk), + .D(_0147_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3919_ ( + .CLK(clk), + .D(_0148_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3920_ ( + .CLK(clk), + .D(_0149_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3921_ ( + .CLK(clk), + .D(_0150_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3922_ ( + .CLK(clk), + .D(_0151_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3923_ ( + .CLK(clk), + .D(_0152_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3924_ ( + .CLK(clk), + .D(_0153_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3925_ ( + .CLK(clk), + .D(_0154_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3926_ ( + .CLK(clk), + .D(_0155_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3927_ ( + .CLK(clk), + .D(_0156_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3928_ ( + .CLK(clk), + .D(_0157_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3929_ ( + .CLK(clk), + .D(_0158_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3930_ ( + .CLK(clk), + .D(_0159_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3931_ ( + .CLK(clk), + .D(_0160_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3932_ ( + .CLK(clk), + .D(_0161_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3933_ ( + .CLK(clk), + .D(_0162_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3934_ ( + .CLK(clk), + .D(_0163_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3935_ ( + .CLK(clk), + .D(_0164_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3936_ ( + .CLK(clk), + .D(_0165_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3937_ ( + .CLK(clk), + .D(_0166_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3938_ ( + .CLK(clk), + .D(_0167_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3939_ ( + .CLK(clk), + .D(_0168_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3940_ ( + .CLK(clk), + .D(_0169_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3941_ ( + .CLK(clk), + .D(_0170_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3942_ ( + .CLK(clk), + .D(_0171_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3943_ ( + .CLK(clk), + .D(_0172_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3944_ ( + .CLK(clk), + .D(_0173_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3945_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy ), + .EN(\corescorecore.core_2.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.shamt_msb ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3946_ ( + .CLK(clk), + .D(_0623_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.wrapped ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3947_ ( + .CLK(clk), + .D(_0174_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.cnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3948_ ( + .CLK(clk), + .D(_0175_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.cnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3949_ ( + .CLK(clk), + .D(_0176_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3950_ ( + .CLK(clk), + .D(_0177_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.cnt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3951_ ( + .CLK(clk), + .D(_0178_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.cnt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3952_ ( + .CLK(clk), + .D(_0179_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.shift.cnt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3953_ ( + .CLK(clk), + .D(_0621_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.eq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3954_ ( + .CLK(clk), + .D(_0622_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3955_ ( + .CLK(clk), + .D(_0620_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3956_ ( + .CLK(clk), + .D(_0619_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.alu.add_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3957_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.alu.shamt [1]), + .EN(\corescorecore.core_2.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.shamt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3958_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.alu.shamt [2]), + .EN(\corescorecore.core_2.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.shamt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3959_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.alu.shamt [3]), + .EN(\corescorecore.core_2.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.shamt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3960_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.alu.shamt [4]), + .EN(\corescorecore.core_2.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.shamt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3961_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.alu.shamt_ser ), + .EN(\corescorecore.core_2.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.shamt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3962_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.alu.result_lt ), + .EN(\corescorecore.core_2.serving.cpu.alu.i_en ), + .Q(\corescorecore.core_2.serving.cpu.alu.result_lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/wb2axis.v:15.4-19.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3963_ ( + .CLK(clk), + .D(_0180_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.i_wb_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3964_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.mem_if.dat_cur ), + .EN(\corescorecore.core_2.serving.cpu.mem_if.dat_valid ), + .Q(\corescorecore.core_2.serving.cpu.mem_if.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3965_ ( + .CLK(clk), + .D(_0631_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm11_7 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3966_ ( + .CLK(clk), + .D(_0632_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm11_7 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3967_ ( + .CLK(clk), + .D(_0633_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm11_7 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3968_ ( + .CLK(clk), + .D(_0634_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm11_7 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3969_ ( + .CLK(clk), + .D(_0635_), + .EN(_0007_), + .Q(\corescorecore.core_2.serving.cpu.decode.imm11_7 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3970_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3971_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3972_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3973_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3974_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3975_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3976_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3977_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0378_), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3978_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [1]), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3979_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [2]), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3980_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [3]), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3981_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [4]), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3982_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [5]), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3983_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [6]), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3984_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.o_wdata0 ), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wdata0_r [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:55.7-55.50|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3985_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.wtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3986_ ( + .CLK(clk), + .D(_0181_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata1 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3987_ ( + .CLK(clk), + .D(_0182_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rdata0 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3988_ ( + .CLK(clk), + .D(_0183_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rgnt ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3989_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.rf_ram_if.rtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rtrig1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3990_ ( + .CLK(clk), + .D(_0184_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3991_ ( + .CLK(clk), + .D(_0185_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3992_ ( + .CLK(clk), + .D(_0186_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.rcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3993_ ( + .CLK(clk), + .D(_0187_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.raddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3994_ ( + .CLK(clk), + .D(_0188_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.raddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3995_ ( + .CLK(clk), + .D(_0189_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3996_ ( + .CLK(clk), + .D(_0190_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3997_ ( + .CLK(clk), + .D(_0191_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3998_ ( + .CLK(clk), + .D(_0192_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.o_waddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _3999_ ( + .CLK(clk), + .D(_0193_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.o_waddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4000_ ( + .CLK(clk), + .D(_0194_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wgo ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4001_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.o_wen0 ), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wen0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4002_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.cpu.i_rf_ready ), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.rf_ram_if.wreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4003_ ( + .CLK(clk), + .D(_0195_), + .EN(_0001_), + .Q(\emitter.data [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4004_ ( + .CLK(clk), + .D(_0449_), + .EN(_0001_), + .Q(\emitter.data [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4005_ ( + .CLK(clk), + .D(_0450_), + .EN(_0001_), + .Q(\emitter.data [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4006_ ( + .CLK(clk), + .D(_0451_), + .EN(_0001_), + .Q(\emitter.data [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4007_ ( + .CLK(clk), + .D(_0452_), + .EN(_0001_), + .Q(\emitter.data [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4008_ ( + .CLK(clk), + .D(_0453_), + .EN(_0001_), + .Q(\emitter.data [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4009_ ( + .CLK(clk), + .D(_0454_), + .EN(_0001_), + .Q(\emitter.data [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4010_ ( + .CLK(clk), + .D(_0455_), + .EN(_0001_), + .Q(\emitter.data [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4011_ ( + .CLK(clk), + .D(_0456_), + .EN(_0001_), + .Q(\emitter.data [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4012_ ( + .CLK(clk), + .D(_0695_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.arbiter.i_wb_mem_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4013_ ( + .CLK(clk), + .D(_0196_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.state.o_cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4014_ ( + .CLK(clk), + .D(_0197_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.mem_bytecnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4015_ ( + .CLK(clk), + .D(_0198_), + .EN(1'h1), + .Q(\corescorecore.core_2.serving.cpu.mem_bytecnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4016_ ( + .CLK(clk), + .D(_0939_[0]), + .EN(\corescorecore.core_2.serving.ram.wb_en ), + .Q(\corescorecore.core_2.serving.ram.bsel [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4017_ ( + .CLK(clk), + .D(_0940_[1]), + .EN(\corescorecore.core_2.serving.ram.wb_en ), + .Q(\corescorecore.core_2.serving.ram.bsel [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4018_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.we ), + .EN(1'h1), + .Q(_0977_), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4019_ ( + .CLK(clk), + .D(_0199_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4020_ ( + .CLK(clk), + .D(_0200_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.i_init ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4021_ ( + .CLK(clk), + .D(_0201_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.i_en ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4022_ ( + .CLK(clk), + .D(_0617_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.i_cnt_done ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4023_ ( + .CLK(clk), + .D(_0202_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.ctrl.i_jump ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4024_ ( + .CLK(clk), + .D(_1178_[2]), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.state.stage_two_req ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4025_ ( + .CLK(clk), + .D(_0585_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4026_ ( + .CLK(clk), + .D(_0596_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4027_ ( + .CLK(clk), + .D(_0607_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4028_ ( + .CLK(clk), + .D(_0610_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4029_ ( + .CLK(clk), + .D(_0611_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4030_ ( + .CLK(clk), + .D(_0612_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4031_ ( + .CLK(clk), + .D(_0613_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4032_ ( + .CLK(clk), + .D(_0614_), + .EN(_0008_), + .Q(\corescorecore.axis_mux.s_axis_tdata [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4033_ ( + .CLK(clk), + .D(_0615_), + .EN(_0008_), + .Q(\corescorecore.core_1.o_tlast ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4034_ ( + .CLK(clk), + .D(_0616_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4035_ ( + .CLK(clk), + .D(_0586_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4036_ ( + .CLK(clk), + .D(_0587_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4037_ ( + .CLK(clk), + .D(_0588_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4038_ ( + .CLK(clk), + .D(_0589_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4039_ ( + .CLK(clk), + .D(_0590_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4040_ ( + .CLK(clk), + .D(_0591_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4041_ ( + .CLK(clk), + .D(_0592_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4042_ ( + .CLK(clk), + .D(_0593_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4043_ ( + .CLK(clk), + .D(_0594_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4044_ ( + .CLK(clk), + .D(_0595_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4045_ ( + .CLK(clk), + .D(_0597_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4046_ ( + .CLK(clk), + .D(_0598_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4047_ ( + .CLK(clk), + .D(_0599_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4048_ ( + .CLK(clk), + .D(_0600_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4049_ ( + .CLK(clk), + .D(_0601_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4050_ ( + .CLK(clk), + .D(_0602_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4051_ ( + .CLK(clk), + .D(_0603_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4052_ ( + .CLK(clk), + .D(_0604_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4053_ ( + .CLK(clk), + .D(_0605_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4054_ ( + .CLK(clk), + .D(_0606_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4055_ ( + .CLK(clk), + .D(_0608_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4056_ ( + .CLK(clk), + .D(_0609_), + .EN(_0008_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4057_ ( + .CLK(clk), + .D(_0203_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.state.o_cnt_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4058_ ( + .CLK(clk), + .D(_0204_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.state.o_cnt_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4059_ ( + .CLK(clk), + .D(_0205_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.state.o_cnt_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4060_ ( + .CLK(clk), + .D(_0206_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.state.o_cnt_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4061_ ( + .CLK(clk), + .D(_0207_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.state.stage_two_pending ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4062_ ( + .CLK(clk), + .D(_0568_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm24_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4063_ ( + .CLK(clk), + .D(_0569_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm24_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4064_ ( + .CLK(clk), + .D(_0570_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm24_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4065_ ( + .CLK(clk), + .D(_0571_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm24_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4066_ ( + .CLK(clk), + .D(_0572_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm24_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4067_ ( + .CLK(clk), + .D(_0573_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm30_25 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4068_ ( + .CLK(clk), + .D(_0574_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm30_25 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4069_ ( + .CLK(clk), + .D(_0575_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm30_25 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4070_ ( + .CLK(clk), + .D(_0576_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm30_25 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4071_ ( + .CLK(clk), + .D(_0577_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm30_25 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4072_ ( + .CLK(clk), + .D(_0578_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm30_25 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4073_ ( + .CLK(clk), + .D(_0579_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm7 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4074_ ( + .CLK(clk), + .D(_0559_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4075_ ( + .CLK(clk), + .D(_0560_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4076_ ( + .CLK(clk), + .D(_0561_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4077_ ( + .CLK(clk), + .D(_0562_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4078_ ( + .CLK(clk), + .D(_0563_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4079_ ( + .CLK(clk), + .D(_0564_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4080_ ( + .CLK(clk), + .D(_0565_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4081_ ( + .CLK(clk), + .D(_0566_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4082_ ( + .CLK(clk), + .D(_0567_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm19_12_20 [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4083_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.i_sh_signed ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4084_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [12]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4085_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [13]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_mem_word ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4086_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [14]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.i_sh_right ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4087_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [2]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.opcode [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4088_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [3]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.opcode [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4089_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [4]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.opcode [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4090_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [5]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4091_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [6]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.m3 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4092_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4093_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [20]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4094_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [21]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4095_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [22]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4096_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [23]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4097_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs2_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4098_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [7]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4099_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [8]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4100_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [9]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4101_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [10]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4102_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [11]), + .EN(\corescorecore.core_1.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4103_ ( + .CLK(clk), + .D(_0580_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.csr_imm ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4104_ ( + .CLK(clk), + .D(_0581_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4105_ ( + .CLK(clk), + .D(_0582_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4106_ ( + .CLK(clk), + .D(_0583_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4107_ ( + .CLK(clk), + .D(_0584_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4108_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.bufreg.q ), + .EN(_0550_), + .Q(\corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4109_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.waddr [0]), + .EN(1'h1), + .Q(_0973_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4110_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.waddr [1]), + .EN(1'h1), + .Q(_0973_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4111_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.waddr [2]), + .EN(1'h1), + .Q(_0973_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4112_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.waddr [3]), + .EN(1'h1), + .Q(_0973_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4113_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.waddr [4]), + .EN(1'h1), + .Q(_0973_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4114_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.waddr [5]), + .EN(1'h1), + .Q(_0973_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4115_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.ram.waddr [6]), + .EN(1'h1), + .Q(_0973_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4116_ ( + .CLK(clk), + .D(_0548_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.bufreg.c_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4117_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.bufreg.data [1]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.cpu.alu.i_buf ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4118_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.cpu.bufreg.data [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4119_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4120_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4121_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4122_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4123_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4124_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4125_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4126_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4127_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4128_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4129_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4130_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4131_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4132_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4133_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4134_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4135_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4136_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4137_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4138_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4139_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4140_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4141_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4142_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4143_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4144_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4145_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4146_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4147_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4148_ ( + .CLK(clk), + .D(_0551_), + .EN(\corescorecore.core_1.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4149_ ( + .CLK(clk), + .D(_0547_), + .EN(\corescorecore.core_1.serving.cpu.alu.i_init ), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4150_ ( + .CLK(clk), + .D(_0553_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4151_ ( + .CLK(clk), + .D(_0552_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.ctrl.pc_plus_4_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4152_ ( + .CLK(clk), + .D(_0208_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.ctrl.en_pc_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4153_ ( + .CLK(clk), + .D(_0209_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.ctrl.pc ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4154_ ( + .CLK(clk), + .D(_0210_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4155_ ( + .CLK(clk), + .D(_0211_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4156_ ( + .CLK(clk), + .D(_0212_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4157_ ( + .CLK(clk), + .D(_0213_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4158_ ( + .CLK(clk), + .D(_0214_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4159_ ( + .CLK(clk), + .D(_0215_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4160_ ( + .CLK(clk), + .D(_0216_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4161_ ( + .CLK(clk), + .D(_0217_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4162_ ( + .CLK(clk), + .D(_0218_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4163_ ( + .CLK(clk), + .D(_0219_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4164_ ( + .CLK(clk), + .D(_0220_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4165_ ( + .CLK(clk), + .D(_0221_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4166_ ( + .CLK(clk), + .D(_0222_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4167_ ( + .CLK(clk), + .D(_0223_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4168_ ( + .CLK(clk), + .D(_0224_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4169_ ( + .CLK(clk), + .D(_0225_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4170_ ( + .CLK(clk), + .D(_0226_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4171_ ( + .CLK(clk), + .D(_0227_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4172_ ( + .CLK(clk), + .D(_0228_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4173_ ( + .CLK(clk), + .D(_0229_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4174_ ( + .CLK(clk), + .D(_0230_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4175_ ( + .CLK(clk), + .D(_0231_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4176_ ( + .CLK(clk), + .D(_0232_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4177_ ( + .CLK(clk), + .D(_0233_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4178_ ( + .CLK(clk), + .D(_0234_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4179_ ( + .CLK(clk), + .D(_0235_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4180_ ( + .CLK(clk), + .D(_0236_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4181_ ( + .CLK(clk), + .D(_0237_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4182_ ( + .CLK(clk), + .D(_0238_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4183_ ( + .CLK(clk), + .D(_0239_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4184_ ( + .CLK(clk), + .D(_0240_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4185_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy ), + .EN(\corescorecore.core_1.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.shamt_msb ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4186_ ( + .CLK(clk), + .D(_0546_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.wrapped ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4187_ ( + .CLK(clk), + .D(_0241_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.cnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4188_ ( + .CLK(clk), + .D(_0242_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.cnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4189_ ( + .CLK(clk), + .D(_0243_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4190_ ( + .CLK(clk), + .D(_0244_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.cnt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4191_ ( + .CLK(clk), + .D(_0245_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.cnt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4192_ ( + .CLK(clk), + .D(_0246_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.shift.cnt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4193_ ( + .CLK(clk), + .D(_0544_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.eq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4194_ ( + .CLK(clk), + .D(_0545_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4195_ ( + .CLK(clk), + .D(_0543_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4196_ ( + .CLK(clk), + .D(_0542_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.alu.add_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4197_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.alu.shamt [1]), + .EN(\corescorecore.core_1.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.shamt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4198_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.alu.shamt [2]), + .EN(\corescorecore.core_1.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.shamt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4199_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.alu.shamt [3]), + .EN(\corescorecore.core_1.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.shamt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4200_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.alu.shamt [4]), + .EN(\corescorecore.core_1.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.shamt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4201_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.alu.shamt_ser ), + .EN(\corescorecore.core_1.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.shamt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4202_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.alu.result_lt ), + .EN(\corescorecore.core_1.serving.cpu.alu.i_en ), + .Q(\corescorecore.core_1.serving.cpu.alu.result_lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/wb2axis.v:15.4-19.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4203_ ( + .CLK(clk), + .D(_0247_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.i_wb_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4204_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.mem_if.dat_cur ), + .EN(\corescorecore.core_1.serving.cpu.mem_if.dat_valid ), + .Q(\corescorecore.core_1.serving.cpu.mem_if.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4205_ ( + .CLK(clk), + .D(_0554_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm11_7 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4206_ ( + .CLK(clk), + .D(_0555_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm11_7 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4207_ ( + .CLK(clk), + .D(_0556_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm11_7 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4208_ ( + .CLK(clk), + .D(_0557_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm11_7 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4209_ ( + .CLK(clk), + .D(_0558_), + .EN(_0009_), + .Q(\corescorecore.core_1.serving.cpu.decode.imm11_7 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4210_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.waddr [0]), + .EN(1'h1), + .Q(_0972_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4211_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.waddr [1]), + .EN(1'h1), + .Q(_0972_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4212_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.waddr [2]), + .EN(1'h1), + .Q(_0972_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4213_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.waddr [3]), + .EN(1'h1), + .Q(_0972_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4214_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.waddr [4]), + .EN(1'h1), + .Q(_0972_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4215_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.waddr [5]), + .EN(1'h1), + .Q(_0972_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4216_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.ram.waddr [6]), + .EN(1'h1), + .Q(_0972_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4217_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4218_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4219_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4220_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4221_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4222_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4223_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4224_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0380_), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4225_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [1]), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4226_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [2]), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4227_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [3]), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4228_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [4]), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4229_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [5]), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4230_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [6]), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4231_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.o_wdata0 ), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wdata0_r [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:55.7-55.50|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4232_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.wtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4233_ ( + .CLK(clk), + .D(_0248_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata1 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4234_ ( + .CLK(clk), + .D(_0249_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rdata0 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4235_ ( + .CLK(clk), + .D(_0250_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rgnt ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4236_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.rf_ram_if.rtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rtrig1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4237_ ( + .CLK(clk), + .D(_0251_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4238_ ( + .CLK(clk), + .D(_0252_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4239_ ( + .CLK(clk), + .D(_0253_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.rcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4240_ ( + .CLK(clk), + .D(_0254_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.raddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4241_ ( + .CLK(clk), + .D(_0255_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.raddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4242_ ( + .CLK(clk), + .D(_0256_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4243_ ( + .CLK(clk), + .D(_0257_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4244_ ( + .CLK(clk), + .D(_0258_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4245_ ( + .CLK(clk), + .D(_0259_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.o_waddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4246_ ( + .CLK(clk), + .D(_0260_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.o_waddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4247_ ( + .CLK(clk), + .D(_0261_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wgo ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4248_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.o_wen0 ), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wen0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4249_ ( + .CLK(clk), + .D(\corescorecore.core_1.serving.cpu.i_rf_ready ), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.rf_ram_if.wreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4250_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.waddr [0]), + .EN(1'h1), + .Q(_0975_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4251_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.waddr [1]), + .EN(1'h1), + .Q(_0975_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4252_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.waddr [2]), + .EN(1'h1), + .Q(_0975_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4253_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.waddr [3]), + .EN(1'h1), + .Q(_0975_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4254_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.waddr [4]), + .EN(1'h1), + .Q(_0975_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4255_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.waddr [5]), + .EN(1'h1), + .Q(_0975_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4256_ ( + .CLK(clk), + .D(\corescorecore.core_3.serving.ram.waddr [6]), + .EN(1'h1), + .Q(_0975_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4257_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.waddr [0]), + .EN(1'h1), + .Q(_0974_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4258_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.waddr [1]), + .EN(1'h1), + .Q(_0974_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4259_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.waddr [2]), + .EN(1'h1), + .Q(_0974_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4260_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.waddr [3]), + .EN(1'h1), + .Q(_0974_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4261_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.waddr [4]), + .EN(1'h1), + .Q(_0974_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4262_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.waddr [5]), + .EN(1'h1), + .Q(_0974_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4263_ ( + .CLK(clk), + .D(\corescorecore.core_2.serving.ram.waddr [6]), + .EN(1'h1), + .Q(_0974_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4264_ ( + .CLK(clk), + .D(_0618_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.arbiter.i_wb_mem_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4265_ ( + .CLK(clk), + .D(_0262_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.state.o_cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4266_ ( + .CLK(clk), + .D(_0263_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.mem_bytecnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4267_ ( + .CLK(clk), + .D(_0264_), + .EN(1'h1), + .Q(\corescorecore.core_1.serving.cpu.mem_bytecnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4268_ ( + .CLK(clk), + .D(_0916_[0]), + .EN(\corescorecore.core_1.serving.ram.wb_en ), + .Q(\corescorecore.core_1.serving.ram.bsel [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4269_ ( + .CLK(clk), + .D(_0917_[1]), + .EN(\corescorecore.core_1.serving.ram.wb_en ), + .Q(\corescorecore.core_1.serving.ram.bsel [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4270_ ( + .CLK(clk), + .D(_0265_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4271_ ( + .CLK(clk), + .D(_0266_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.i_init ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4272_ ( + .CLK(clk), + .D(_0267_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.i_en ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4273_ ( + .CLK(clk), + .D(_0540_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.i_cnt_done ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4274_ ( + .CLK(clk), + .D(_0268_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.ctrl.i_jump ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4275_ ( + .CLK(clk), + .D(_1021_[2]), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.state.stage_two_req ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4276_ ( + .CLK(clk), + .D(_0508_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4277_ ( + .CLK(clk), + .D(_0519_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4278_ ( + .CLK(clk), + .D(_0530_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4279_ ( + .CLK(clk), + .D(_0533_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4280_ ( + .CLK(clk), + .D(_0534_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4281_ ( + .CLK(clk), + .D(_0535_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4282_ ( + .CLK(clk), + .D(_0536_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4283_ ( + .CLK(clk), + .D(_0537_), + .EN(_0010_), + .Q(\corescorecore.axis_mux.s_axis_tdata [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4284_ ( + .CLK(clk), + .D(_0538_), + .EN(_0010_), + .Q(\corescorecore.core_0.o_tlast ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4285_ ( + .CLK(clk), + .D(_0539_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4286_ ( + .CLK(clk), + .D(_0509_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4287_ ( + .CLK(clk), + .D(_0510_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4288_ ( + .CLK(clk), + .D(_0511_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4289_ ( + .CLK(clk), + .D(_0512_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4290_ ( + .CLK(clk), + .D(_0513_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4291_ ( + .CLK(clk), + .D(_0514_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4292_ ( + .CLK(clk), + .D(_0515_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4293_ ( + .CLK(clk), + .D(_0516_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4294_ ( + .CLK(clk), + .D(_0517_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4295_ ( + .CLK(clk), + .D(_0518_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4296_ ( + .CLK(clk), + .D(_0520_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4297_ ( + .CLK(clk), + .D(_0521_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4298_ ( + .CLK(clk), + .D(_0522_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4299_ ( + .CLK(clk), + .D(_0523_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4300_ ( + .CLK(clk), + .D(_0524_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4301_ ( + .CLK(clk), + .D(_0525_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4302_ ( + .CLK(clk), + .D(_0526_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4303_ ( + .CLK(clk), + .D(_0527_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4304_ ( + .CLK(clk), + .D(_0528_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4305_ ( + .CLK(clk), + .D(_0529_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4306_ ( + .CLK(clk), + .D(_0531_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4307_ ( + .CLK(clk), + .D(_0532_), + .EN(_0010_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4308_ ( + .CLK(clk), + .D(_0269_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.state.o_cnt_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4309_ ( + .CLK(clk), + .D(_0270_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.state.o_cnt_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4310_ ( + .CLK(clk), + .D(_0271_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.state.o_cnt_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4311_ ( + .CLK(clk), + .D(_0272_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.state.o_cnt_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4312_ ( + .CLK(clk), + .D(_0273_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.state.stage_two_pending ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4313_ ( + .CLK(clk), + .D(_0491_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm24_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4314_ ( + .CLK(clk), + .D(_0492_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm24_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4315_ ( + .CLK(clk), + .D(_0493_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm24_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4316_ ( + .CLK(clk), + .D(_0494_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm24_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4317_ ( + .CLK(clk), + .D(_0495_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm24_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4318_ ( + .CLK(clk), + .D(_0496_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm30_25 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4319_ ( + .CLK(clk), + .D(_0497_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm30_25 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4320_ ( + .CLK(clk), + .D(_0498_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm30_25 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4321_ ( + .CLK(clk), + .D(_0499_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm30_25 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4322_ ( + .CLK(clk), + .D(_0500_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm30_25 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4323_ ( + .CLK(clk), + .D(_0501_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm30_25 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4324_ ( + .CLK(clk), + .D(_0502_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm7 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4325_ ( + .CLK(clk), + .D(_0482_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4326_ ( + .CLK(clk), + .D(_0483_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4327_ ( + .CLK(clk), + .D(_0484_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4328_ ( + .CLK(clk), + .D(_0485_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4329_ ( + .CLK(clk), + .D(_0486_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4330_ ( + .CLK(clk), + .D(_0487_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4331_ ( + .CLK(clk), + .D(_0488_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4332_ ( + .CLK(clk), + .D(_0489_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4333_ ( + .CLK(clk), + .D(_0490_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm19_12_20 [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4334_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.i_sh_signed ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4335_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [12]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4336_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [13]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_mem_word ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4337_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [14]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.i_sh_right ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4338_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [2]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.opcode [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4339_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [3]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.opcode [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4340_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [4]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.opcode [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4341_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [5]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4342_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [6]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.m3 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4343_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4344_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [20]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4345_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [21]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4346_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [22]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4347_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [23]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4348_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs2_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4349_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [7]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4350_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [8]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4351_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [9]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4352_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [10]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4353_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [11]), + .EN(\corescorecore.core_0.serving.cpu.decode.i_wb_en ), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4354_ ( + .CLK(clk), + .D(_0503_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.csr_imm ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4355_ ( + .CLK(clk), + .D(_0504_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4356_ ( + .CLK(clk), + .D(_0505_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4357_ ( + .CLK(clk), + .D(_0506_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4358_ ( + .CLK(clk), + .D(_0507_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4359_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.bufreg.q ), + .EN(_0473_), + .Q(\corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4360_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.raddr [7]), + .EN(1'h1), + .Q(_0976_[7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4361_ ( + .CLK(clk), + .D(_0471_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.bufreg.c_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4362_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.bufreg.data [1]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.cpu.alu.i_buf ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4363_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.cpu.bufreg.data [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4364_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4365_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4366_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4367_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4368_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4369_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4370_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4371_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4372_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4373_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4374_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4375_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4376_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4377_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4378_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4379_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4380_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4381_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4382_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4383_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4384_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4385_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4386_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4387_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4388_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4389_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4390_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4391_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4392_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_bufreg.v:26.4-37.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4393_ ( + .CLK(clk), + .D(_0474_), + .EN(\corescorecore.core_0.serving.cpu.bufreg_hold ), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4394_ ( + .CLK(clk), + .D(_0470_), + .EN(\corescorecore.core_0.serving.cpu.alu.i_init ), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4395_ ( + .CLK(clk), + .D(_0476_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.ctrl.pc_plus_offset_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4396_ ( + .CLK(clk), + .D(_0475_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.ctrl.pc_plus_4_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4397_ ( + .CLK(clk), + .D(_0274_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.ctrl.en_pc_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4398_ ( + .CLK(clk), + .D(_0275_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.ctrl.pc ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4399_ ( + .CLK(clk), + .D(_0276_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4400_ ( + .CLK(clk), + .D(_0277_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4401_ ( + .CLK(clk), + .D(_0278_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4402_ ( + .CLK(clk), + .D(_0279_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4403_ ( + .CLK(clk), + .D(_0280_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4404_ ( + .CLK(clk), + .D(_0281_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4405_ ( + .CLK(clk), + .D(_0282_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4406_ ( + .CLK(clk), + .D(_0283_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [8]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4407_ ( + .CLK(clk), + .D(_0284_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [9]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4408_ ( + .CLK(clk), + .D(_0285_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [10]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4409_ ( + .CLK(clk), + .D(_0286_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [11]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4410_ ( + .CLK(clk), + .D(_0287_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [12]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4411_ ( + .CLK(clk), + .D(_0288_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [13]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4412_ ( + .CLK(clk), + .D(_0289_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [14]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4413_ ( + .CLK(clk), + .D(_0290_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [15]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4414_ ( + .CLK(clk), + .D(_0291_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [16]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4415_ ( + .CLK(clk), + .D(_0292_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [17]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4416_ ( + .CLK(clk), + .D(_0293_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [18]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4417_ ( + .CLK(clk), + .D(_0294_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [19]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4418_ ( + .CLK(clk), + .D(_0295_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [20]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4419_ ( + .CLK(clk), + .D(_0296_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [21]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4420_ ( + .CLK(clk), + .D(_0297_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [22]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4421_ ( + .CLK(clk), + .D(_0298_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [23]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4422_ ( + .CLK(clk), + .D(_0299_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [24]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4423_ ( + .CLK(clk), + .D(_0300_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [25]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4424_ ( + .CLK(clk), + .D(_0301_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [26]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4425_ ( + .CLK(clk), + .D(_0302_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [27]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4426_ ( + .CLK(clk), + .D(_0303_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [28]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4427_ ( + .CLK(clk), + .D(_0304_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [29]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4428_ ( + .CLK(clk), + .D(_0305_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [30]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_ctrl.v:71.4-85.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4429_ ( + .CLK(clk), + .D(_0306_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [31]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4430_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy ), + .EN(\corescorecore.core_0.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.shamt_msb ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4431_ ( + .CLK(clk), + .D(_0469_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.wrapped ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4432_ ( + .CLK(clk), + .D(_0307_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.cnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4433_ ( + .CLK(clk), + .D(_0308_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.cnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4434_ ( + .CLK(clk), + .D(_0309_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4435_ ( + .CLK(clk), + .D(_0310_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.cnt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4436_ ( + .CLK(clk), + .D(_0311_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.cnt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_shift.v:18.4-25.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4437_ ( + .CLK(clk), + .D(_0312_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.shift.cnt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4438_ ( + .CLK(clk), + .D(_0467_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.eq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4439_ ( + .CLK(clk), + .D(_0468_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4440_ ( + .CLK(clk), + .D(_0466_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4441_ ( + .CLK(clk), + .D(_0465_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.alu.add_cy_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4442_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.alu.shamt [1]), + .EN(\corescorecore.core_0.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.shamt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4443_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.alu.shamt [2]), + .EN(\corescorecore.core_0.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.shamt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4444_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.alu.shamt [3]), + .EN(\corescorecore.core_0.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.shamt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4445_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.alu.shamt [4]), + .EN(\corescorecore.core_0.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.shamt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4446_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.alu.shamt_ser ), + .EN(\corescorecore.core_0.serving.cpu.alu.i_shamt_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.shamt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_alu.v:89.4-104.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4447_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.alu.result_lt ), + .EN(\corescorecore.core_0.serving.cpu.alu.i_en ), + .Q(\corescorecore.core_0.serving.cpu.alu.result_lt_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4448_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [0]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4449_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [1]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4450_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [2]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4451_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [3]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4452_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [4]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4453_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [5]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4454_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [6]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/verilog-axis_0-r3/rtl/axis_arb_mux.v:211.1-247.4|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4455_ ( + .CLK(clk), + .D(\corescorecore.axis_mux.current_s_tdata [7]), + .EN(\corescorecore.axis_mux.store_axis_int_to_temp ), + .Q(\corescorecore.axis_mux.temp_m_axis_tdata_reg [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_mem_if.v:47.4-56.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4456_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.mem_if.dat_cur ), + .EN(\corescorecore.core_0.serving.cpu.mem_if.dat_valid ), + .Q(\corescorecore.core_0.serving.cpu.mem_if.signbit ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4457_ ( + .CLK(clk), + .D(_0477_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm11_7 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4458_ ( + .CLK(clk), + .D(_0478_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm11_7 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4459_ ( + .CLK(clk), + .D(_0479_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm11_7 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4460_ ( + .CLK(clk), + .D(_0480_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm11_7 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_decode.v:194.4-224.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4461_ ( + .CLK(clk), + .D(_0481_), + .EN(_0011_), + .Q(\corescorecore.core_0.serving.cpu.decode.imm11_7 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4462_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.waddr [0]), + .EN(1'h1), + .Q(_0976_[0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4463_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.waddr [1]), + .EN(1'h1), + .Q(_0976_[1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4464_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.waddr [2]), + .EN(1'h1), + .Q(_0976_[2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4465_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.waddr [3]), + .EN(1'h1), + .Q(_0976_[3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4466_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.waddr [4]), + .EN(1'h1), + .Q(_0976_[4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4467_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.waddr [5]), + .EN(1'h1), + .Q(_0976_[5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4468_ ( + .CLK(clk), + .D(\corescorecore.core_4.serving.ram.waddr [6]), + .EN(1'h1), + .Q(_0976_[6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4469_ ( + .CLK(clk), + .D(_0443_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata1 [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4470_ ( + .CLK(clk), + .D(_0444_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata1 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4471_ ( + .CLK(clk), + .D(_0445_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata1 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4472_ ( + .CLK(clk), + .D(_0446_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata1 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4473_ ( + .CLK(clk), + .D(_0447_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata1 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4474_ ( + .CLK(clk), + .D(_0448_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata1 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4475_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [24]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4476_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [25]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4477_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [26]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4478_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [27]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4479_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [28]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4480_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [29]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4481_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h1), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4482_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31]), + .EN(_0382_), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4483_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [1]), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4484_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [2]), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4485_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [3]), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4486_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [4]), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4487_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [5]), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4488_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [6]), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:77.6-77.75|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4489_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.o_wdata0 ), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wdata0_r [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:55.7-55.50|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4490_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.wtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:131.6-135.9|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4491_ ( + .CLK(clk), + .D(_0313_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata1 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4492_ ( + .CLK(clk), + .D(_0314_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rdata0 [7]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4493_ ( + .CLK(clk), + .D(_0315_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rgnt ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4494_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.rf_ram_if.rtrig0 ), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rtrig1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4495_ ( + .CLK(clk), + .D(_0316_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4496_ ( + .CLK(clk), + .D(_0317_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4497_ ( + .CLK(clk), + .D(_0318_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.rcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4498_ ( + .CLK(clk), + .D(_0319_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.raddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4499_ ( + .CLK(clk), + .D(_0320_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.raddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4500_ ( + .CLK(clk), + .D(_0321_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wcnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4501_ ( + .CLK(clk), + .D(_0322_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wcnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4502_ ( + .CLK(clk), + .D(_0323_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wcnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4503_ ( + .CLK(clk), + .D(_0324_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.o_waddr [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4504_ ( + .CLK(clk), + .D(_0325_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.o_waddr [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4505_ ( + .CLK(clk), + .D(_0326_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wgo ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4506_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.o_wen0 ), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wen0_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:82.4-102.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4507_ ( + .CLK(clk), + .D(\corescorecore.core_0.serving.cpu.i_rf_ready ), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.rf_ram_if.wreq_r ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4508_ ( + .CLK(clk), + .D(_0541_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.arbiter.i_wb_mem_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4509_ ( + .CLK(clk), + .D(_0327_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.state.o_cnt [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4510_ ( + .CLK(clk), + .D(_0328_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.mem_bytecnt [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_state.v:90.4-124.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4511_ ( + .CLK(clk), + .D(_0329_), + .EN(1'h1), + .Q(\corescorecore.core_0.serving.cpu.mem_bytecnt [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4512_ ( + .CLK(clk), + .D(_0895_[0]), + .EN(\corescorecore.core_0.serving.ram.wb_en ), + .Q(\corescorecore.core_0.serving.ram.bsel [0]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serving_1.0.2/serving/serving_ram.v:60.4-67.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4513_ ( + .CLK(clk), + .D(_0896_[1]), + .EN(\corescorecore.core_0.serving.ram.wb_en ), + .Q(\corescorecore.core_0.serving.ram.bsel [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4514_ ( + .CLK(clk), + .D(_0436_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4515_ ( + .CLK(clk), + .D(_0437_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata0 [1]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4516_ ( + .CLK(clk), + .D(_0438_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata0 [2]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4517_ ( + .CLK(clk), + .D(_0439_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata0 [3]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4518_ ( + .CLK(clk), + .D(_0440_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata0 [4]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4519_ ( + .CLK(clk), + .D(_0441_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata0 [5]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/serv_1.0.2/rtl/serv_rf_ram_if.v:140.4-157.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4520_ ( + .CLK(clk), + .D(_0442_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.rf_ram_if.rdata0 [6]), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/wb2axis.v:15.4-19.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4521_ ( + .CLK(clk), + .D(_0330_), + .EN(1'h1), + .Q(\corescorecore.core_4.serving.i_wb_ack ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/emitter_uart.v:28.4-43.7|/usr/local/bin/../share/yosys/gatemate/reg_map.v:32.4-32.61" *) + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _4522_ ( + .CLK(clk), + .D(_0331_), + .EN(1'h1), + .Q(\corescorecore.axis_mux.m_axis_tready ), + .SR(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4523_ ( + .D0(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [0]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [1]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [2]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_sel [3]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0992_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4524_ ( + .D0(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [0]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [1]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [2]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_sel [3]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0994_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4525_ ( + .D0(_0856_), + .D1(1'h0), + .D2(_0852_), + .D3(1'h0), + .S0(_0000_), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1261_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4526_ ( + .D0(_0855_), + .D1(1'h0), + .D2(_0851_), + .D3(1'h0), + .S0(_0000_), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1252_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4527_ ( + .D0(_0854_), + .D1(1'h0), + .D2(_0850_), + .D3(1'h0), + .S0(_0000_), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1264_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4528_ ( + .D0(_1126_[1]), + .D1(1'h0), + .D2(_1128_[1]), + .D3(1'h0), + .S0(_0000_), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1286_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4529_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [0]), + .D1(\corescorecore.axis_mux.s_axis_tdata [8]), + .D2(\corescorecore.axis_mux.s_axis_tdata [16]), + .D3(\corescorecore.axis_mux.s_axis_tdata [24]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1083_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4530_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [1]), + .D1(\corescorecore.axis_mux.s_axis_tdata [9]), + .D2(\corescorecore.axis_mux.s_axis_tdata [17]), + .D3(\corescorecore.axis_mux.s_axis_tdata [25]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1076_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4531_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [2]), + .D1(\corescorecore.axis_mux.s_axis_tdata [10]), + .D2(\corescorecore.axis_mux.s_axis_tdata [18]), + .D3(\corescorecore.axis_mux.s_axis_tdata [26]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1075_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4532_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [3]), + .D1(\corescorecore.axis_mux.s_axis_tdata [11]), + .D2(\corescorecore.axis_mux.s_axis_tdata [19]), + .D3(\corescorecore.axis_mux.s_axis_tdata [27]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1080_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4533_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [4]), + .D1(\corescorecore.axis_mux.s_axis_tdata [12]), + .D2(\corescorecore.axis_mux.s_axis_tdata [20]), + .D3(\corescorecore.axis_mux.s_axis_tdata [28]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1079_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4534_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [5]), + .D1(\corescorecore.axis_mux.s_axis_tdata [13]), + .D2(\corescorecore.axis_mux.s_axis_tdata [21]), + .D3(\corescorecore.axis_mux.s_axis_tdata [29]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1078_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4535_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [6]), + .D1(\corescorecore.axis_mux.s_axis_tdata [14]), + .D2(\corescorecore.axis_mux.s_axis_tdata [22]), + .D3(\corescorecore.axis_mux.s_axis_tdata [30]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1077_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4536_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [7]), + .D1(\corescorecore.axis_mux.s_axis_tdata [15]), + .D2(\corescorecore.axis_mux.s_axis_tdata [23]), + .D3(\corescorecore.axis_mux.s_axis_tdata [31]), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1068_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4537_ ( + .D0(\corescorecore.core_0.o_tvalid ), + .D1(\corescorecore.core_1.o_tvalid ), + .D2(\corescorecore.core_2.o_tvalid ), + .D3(\corescorecore.core_3.o_tvalid ), + .S0(\corescorecore.axis_mux.arb_inst.grant_encoded [0]), + .S1(\corescorecore.axis_mux.arb_inst.grant_encoded [1]), + .Y(_1161_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4538_ ( + .D0(_0857_), + .D1(1'h0), + .D2(_0853_), + .D3(1'h0), + .S0(_0000_), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1063_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4539_ ( + .D0(_0858_), + .D1(1'h0), + .D2(_0862_), + .D3(1'h0), + .S0(_1113_[2]), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1343_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4540_ ( + .D0(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [0]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [1]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [2]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_sel [3]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0998_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4541_ ( + .D0(\corescorecore.core_4.serving.cpu.alu.op_b ), + .D1(_0931_), + .D2(_0931_), + .D3(\corescorecore.core_4.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .Y(_1300_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4542_ ( + .D0(\corescorecore.core_4.serving.cpu.alu.op_b ), + .D1(1'h1), + .D2(1'h0), + .D3(\corescorecore.core_4.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_4.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_4.serving.cpu.decode.o_mem_half ), + .Y(_1300_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4543_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [32]), + .D1(\corescorecore.core_4.o_tlast ), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4544_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [33]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4545_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [34]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4546_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [35]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4547_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [36]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4548_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [37]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4549_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [38]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4550_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [39]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1001_[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4551_ ( + .D0(1'h0), + .D1(_0861_), + .D2(1'h0), + .D3(_0865_), + .S0(_1113_[2]), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1340_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4552_ ( + .D0(1'h0), + .D1(_0860_), + .D2(1'h0), + .D3(_0864_), + .S0(_1113_[2]), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1328_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4553_ ( + .D0(\corescorecore.core_3.serving.cpu.alu.op_b ), + .D1(_0950_), + .D2(_0950_), + .D3(\corescorecore.core_3.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .Y(_1359_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4554_ ( + .D0(\corescorecore.core_3.serving.cpu.alu.op_b ), + .D1(1'h1), + .D2(1'h0), + .D3(\corescorecore.core_3.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_3.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_3.serving.cpu.decode.o_mem_half ), + .Y(_1359_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4555_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [24]), + .D1(\corescorecore.core_3.o_tlast ), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4556_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [25]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4557_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [26]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4558_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [27]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4559_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [28]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4560_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [29]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4561_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [30]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4562_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [31]), + .D1(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .D2(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .D3(\corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .S0(\corescorecore.core_3.serving.ram.bsel [0]), + .S1(\corescorecore.core_3.serving.ram.bsel [1]), + .Y(_0999_[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4563_ ( + .D0(\corescorecore.core_2.serving.cpu.alu.op_b ), + .D1(_0924_), + .D2(_0924_), + .D3(\corescorecore.core_2.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .Y(_1348_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4564_ ( + .D0(\corescorecore.core_2.serving.cpu.alu.op_b ), + .D1(1'h1), + .D2(1'h0), + .D3(\corescorecore.core_2.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_2.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_2.serving.cpu.decode.o_mem_half ), + .Y(_1348_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4565_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [16]), + .D1(\corescorecore.core_2.o_tlast ), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4566_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [17]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4567_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [18]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4568_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [19]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4569_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [20]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4570_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [21]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4571_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [22]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4572_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [23]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0997_[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4573_ ( + .D0(1'h0), + .D1(_0859_), + .D2(1'h0), + .D3(_0863_), + .S0(_1113_[2]), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1370_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4574_ ( + .D0(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [0]), + .D1(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [1]), + .D2(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [2]), + .D3(\corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_sel [3]), + .S0(\corescorecore.core_4.serving.ram.bsel [0]), + .S1(\corescorecore.core_4.serving.ram.bsel [1]), + .Y(_1000_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4575_ ( + .D0(\corescorecore.core_1.serving.cpu.alu.op_b ), + .D1(_0905_), + .D2(_0905_), + .D3(\corescorecore.core_1.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .Y(_1278_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4576_ ( + .D0(\corescorecore.core_1.serving.cpu.alu.op_b ), + .D1(1'h1), + .D2(1'h0), + .D3(\corescorecore.core_1.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_1.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_1.serving.cpu.decode.o_mem_half ), + .Y(_1278_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4577_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [8]), + .D1(\corescorecore.core_1.o_tlast ), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4578_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [9]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4579_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [10]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4580_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [11]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4581_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [12]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4582_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [13]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4583_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [14]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4584_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [15]), + .D1(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .D2(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .D3(\corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .S0(\corescorecore.core_1.serving.ram.bsel [0]), + .S1(\corescorecore.core_1.serving.ram.bsel [1]), + .Y(_0995_[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4585_ ( + .D0(\corescorecore.core_0.serving.cpu.alu.op_b ), + .D1(_0878_), + .D2(_0878_), + .D3(\corescorecore.core_0.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .Y(_1146_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4586_ ( + .D0(\corescorecore.core_0.serving.cpu.alu.op_b ), + .D1(1'h1), + .D2(1'h0), + .D3(\corescorecore.core_0.serving.cpu.alu.op_b ), + .S0(\corescorecore.core_0.serving.cpu.alu.i_rs1 ), + .S1(\corescorecore.core_0.serving.cpu.decode.o_mem_half ), + .Y(_1146_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4587_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [0]), + .D1(\corescorecore.core_0.o_tlast ), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [16]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [24]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4588_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [1]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [9]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [17]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [25]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4589_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [2]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [10]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [18]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [26]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4590_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [3]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [11]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [19]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [27]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4591_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [4]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [12]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [20]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [28]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4592_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [5]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [13]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [21]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [29]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4593_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [6]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [14]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [22]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [30]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4594_ ( + .D0(\corescorecore.axis_mux.s_axis_tdata [7]), + .D1(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [15]), + .D2(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [23]), + .D3(\corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [31]), + .S0(\corescorecore.core_0.serving.ram.bsel [0]), + .S1(\corescorecore.core_0.serving.ram.bsel [1]), + .Y(_0993_[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4595_ ( + .D0(1'h0), + .D1(_0858_), + .D2(1'h0), + .D3(_0862_), + .S0(_1113_[2]), + .S1(\corescorecore.axis_mux.arb_inst.masked_request_valid ), + .Y(_1159_[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/mux_map.v:37.9-41.3" *) + CC_MX4 _4596_ ( + .D0(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [0]), + .D1(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [1]), + .D2(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [2]), + .D3(\corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_sel [3]), + .S0(\corescorecore.core_2.serving.ram.bsel [0]), + .S1(\corescorecore.core_2.serving.ram.bsel [1]), + .Y(_0996_) + ); + (* keep = 32'd1 *) + CC_IBUF _4602_ ( + .I(i_clk), + .Y(_0960_) + ); + (* keep = 32'd1 *) + CC_IBUF _4603_ ( + .I(i_rstn), + .Y(\clkgen.i_rstn ) + ); + (* keep = 32'd1 *) + CC_OBUF _4604_ ( + .A(\emitter.o_uart_tx ), + .O(o_uart_tx) + ); + (* hdlname = "clkgen pll_inst_ila" *) + (* module_not_derived = 32'd1 *) + (* src = "src/corescore_0/rtl/cc_gatemate_clock_gen.v:22.3-31.2" *) + CC_PLL #( + .LOCK_REQ(32'sd1), + .LOW_JITTER(32'sd1), + .OUT_CLK(5'h10), + .PERF_MD("ECONOMY"), + .REF_CLK("10.0") + ) \clkgen.pll_inst_ila ( + .CLK0(_0961_), + .CLK_FEEDBACK(1'h0), + .CLK_REF(\clkgen.i_clk ), + .USR_CLK_REF(1'h0), + .USR_LOCKED_STDY_RST(1'h0), + .USR_PLL_LOCKED(\clkgen.usr_pll_lock_1 ) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/brams_map.v:114.5-129.4" *) + CC_BRAM_20K #( + .A_CLK_INV(1'h0), + .A_RD_WIDTH(32'd0), + .A_WR_MODE("WRITE_THROUGH"), + .A_WR_WIDTH(32'd10), + .B_CLK_INV(1'h0), + .B_RD_WIDTH(32'd10), + .B_WR_MODE("WRITE_THROUGH"), + .B_WR_WIDTH(32'd0), + .INIT_00(320'h00015014130000500883000552002302c700089330000014b700cc50141300000014170000000013), + .INIT_01(320'h3f05f3c06f3f802278e33fcf2208931c4022089300000088b7000552402304002388933f802268e3), + .INIT_02(320'h00000000000000000000000000286f1b06c19468080731e4611cc200c0300c0300c020194721bc43), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .RAM_MODE("TDP") + ) \corescorecore.core_0.serving.ram.mem.0.0 ( + .A_ADDR({ 3'h0, _0972_[7:2], 1'h0, _0972_[1:0], 4'h0 }), + .A_BM({ 12'h000, _0977_, _0977_, _0977_, _0977_, _0977_, _0977_, _0977_, _0977_ }), + .A_CLK(clk), + .A_DI({ 12'b0000000000xx, _0967_ }), + .A_DO(_0987_), + .A_EN(1'h1), + .A_WE(_0977_), + .B_ADDR({ 3'h0, \corescorecore.core_0.serving.ram.raddr [7:2], 1'h0, \corescorecore.core_0.serving.ram.raddr [1:0], 4'h0 }), + .B_BM(20'h00000), + .B_CLK(clk), + .B_DI(20'hxxxxx), + .B_DO({ _0962_, _0982_[9:8], \corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31:24] }), + .B_EN(1'h1), + .B_WE(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/brams_map.v:114.5-129.4" *) + CC_BRAM_20K #( + .A_CLK_INV(1'h0), + .A_RD_WIDTH(32'd0), + .A_WR_MODE("WRITE_THROUGH"), + .A_WR_WIDTH(32'd10), + .B_CLK_INV(1'h0), + .B_RD_WIDTH(32'd10), + .B_WR_MODE("WRITE_THROUGH"), + .B_WR_WIDTH(32'd0), + .INIT_00(320'h00015014130000500883000552002302c700089330000014b700cc50141300000014170000000013), + .INIT_01(320'h3f05f3c06f3f802278e33fcf2208931c4022089300000088b7000552402304002388933f802268e3), + .INIT_02(320'h00000000000000000000000000286f1b06c19468080731e4611cc200c4300c0300c020194721bc43), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .RAM_MODE("TDP") + ) \corescorecore.core_1.serving.ram.mem.0.0 ( + .A_ADDR({ 3'h0, _0973_[7:2], 1'h0, _0973_[1:0], 4'h0 }), + .A_BM({ 12'h000, _0978_, _0978_, _0978_, _0978_, _0978_, _0978_, _0978_, _0978_ }), + .A_CLK(clk), + .A_DI({ 12'b0000000000xx, _0968_ }), + .A_DO(_0988_), + .A_EN(1'h1), + .A_WE(_0978_), + .B_ADDR({ 3'h0, \corescorecore.core_1.serving.ram.raddr [7:2], 1'h0, \corescorecore.core_1.serving.ram.raddr [1:0], 4'h0 }), + .B_BM(20'h00000), + .B_CLK(clk), + .B_DI(20'hxxxxx), + .B_DO({ _0963_, _0983_[9:8], \corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31:24] }), + .B_EN(1'h1), + .B_WE(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/brams_map.v:114.5-129.4" *) + CC_BRAM_20K #( + .A_CLK_INV(1'h0), + .A_RD_WIDTH(32'd0), + .A_WR_MODE("WRITE_THROUGH"), + .A_WR_WIDTH(32'd10), + .B_CLK_INV(1'h0), + .B_RD_WIDTH(32'd10), + .B_WR_MODE("WRITE_THROUGH"), + .B_WR_WIDTH(32'd0), + .INIT_00(320'h00015014130000500883000552002302c700089330000014b700cc50141300000014170000000013), + .INIT_01(320'h3f05f3c06f3f802278e33fcf2208931c4022089300000088b7000552402304002388933f802268e3), + .INIT_02(320'h00000000000000000000000000286f1b06c19468080731e4611cc200c8300c0300c020194721bc43), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .RAM_MODE("TDP") + ) \corescorecore.core_2.serving.ram.mem.0.0 ( + .A_ADDR({ 3'h0, _0974_[7:2], 1'h0, _0974_[1:0], 4'h0 }), + .A_BM({ 12'h000, _0979_, _0979_, _0979_, _0979_, _0979_, _0979_, _0979_, _0979_ }), + .A_CLK(clk), + .A_DI({ 12'b0000000000xx, _0969_ }), + .A_DO(_0989_), + .A_EN(1'h1), + .A_WE(_0979_), + .B_ADDR({ 3'h0, \corescorecore.core_2.serving.ram.raddr [7:2], 1'h0, \corescorecore.core_2.serving.ram.raddr [1:0], 4'h0 }), + .B_BM(20'h00000), + .B_CLK(clk), + .B_DI(20'hxxxxx), + .B_DO({ _0964_, _0984_[9:8], \corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31:24] }), + .B_EN(1'h1), + .B_WE(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/brams_map.v:114.5-129.4" *) + CC_BRAM_20K #( + .A_CLK_INV(1'h0), + .A_RD_WIDTH(32'd0), + .A_WR_MODE("WRITE_THROUGH"), + .A_WR_WIDTH(32'd10), + .B_CLK_INV(1'h0), + .B_RD_WIDTH(32'd10), + .B_WR_MODE("WRITE_THROUGH"), + .B_WR_WIDTH(32'd0), + .INIT_00(320'h00015014130000500883000552002302c700089330000014b700cc50141300000014170000000013), + .INIT_01(320'h3f05f3c06f3f802278e33fcf2208931c4022089300000088b7000552402304002388933f802268e3), + .INIT_02(320'h00000000000000000000000000286f1b06c19468080731e4611cc200cc300c0300c020194721bc43), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .RAM_MODE("TDP") + ) \corescorecore.core_3.serving.ram.mem.0.0 ( + .A_ADDR({ 3'h0, _0975_[7:2], 1'h0, _0975_[1:0], 4'h0 }), + .A_BM({ 12'h000, _0980_, _0980_, _0980_, _0980_, _0980_, _0980_, _0980_, _0980_ }), + .A_CLK(clk), + .A_DI({ 12'b0000000000xx, _0970_ }), + .A_DO(_0990_), + .A_EN(1'h1), + .A_WE(_0980_), + .B_ADDR({ 3'h0, \corescorecore.core_3.serving.ram.raddr [7:2], 1'h0, \corescorecore.core_3.serving.ram.raddr [1:0], 4'h0 }), + .B_BM(20'h00000), + .B_CLK(clk), + .B_DI(20'hxxxxx), + .B_DO({ _0965_, _0985_[9:8], \corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31:24] }), + .B_EN(1'h1), + .B_WE(1'h0) + ); + (* module_not_derived = 32'd1 *) + (* src = "/usr/local/bin/../share/yosys/gatemate/brams_map.v:114.5-129.4" *) + CC_BRAM_20K #( + .A_CLK_INV(1'h0), + .A_RD_WIDTH(32'd0), + .A_WR_MODE("WRITE_THROUGH"), + .A_WR_WIDTH(32'd10), + .B_CLK_INV(1'h0), + .B_RD_WIDTH(32'd10), + .B_WR_MODE("WRITE_THROUGH"), + .B_WR_WIDTH(32'd0), + .INIT_00(320'h00015014130000500883000552002302c700089330000014b700cc50141300000014170000000013), + .INIT_01(320'h3f05f3c06f3f802278e33fcf2208931c4022089300000088b7000552402304002388933f802268e3), + .INIT_02(320'h00000000000000000000000000286f1b06c19468080731e4611cc200d0300c0300c020194721bc43), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .RAM_MODE("TDP") + ) \corescorecore.core_4.serving.ram.mem.0.0 ( + .A_ADDR({ 3'h0, _0976_[7:2], 1'h0, _0976_[1:0], 4'h0 }), + .A_BM({ 12'h000, _0981_, _0981_, _0981_, _0981_, _0981_, _0981_, _0981_, _0981_ }), + .A_CLK(clk), + .A_DI({ 12'b0000000000xx, _0971_ }), + .A_DO(_0991_), + .A_EN(1'h1), + .A_WE(_0981_), + .B_ADDR({ 3'h0, \corescorecore.core_4.serving.ram.raddr [7:2], 1'h0, \corescorecore.core_4.serving.ram.raddr [1:0], 4'h0 }), + .B_BM(20'h00000), + .B_CLK(clk), + .B_DI(20'hxxxxx), + .B_DO({ _0966_, _0986_[9:8], \corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31:24] }), + .B_EN(1'h1), + .B_WE(1'h0) + ); + initial begin + if (1'h1) begin + $write("Preloading $paramod$8816468be330918baff437714bf1bfb0ee411954\\serving_ram from %s\n", $unsigned(80'h636f72655f302e686578)); + end + if (1'h1) begin + $write("Preloading $paramod$695536bf7e64eac63687045115fd1cb71315cdca\\serving_ram from %s\n", $unsigned(80'h636f72655f312e686578)); + end + if (1'h1) begin + $write("Preloading $paramod$eb5afe7743decc89c16fd0958ba0167c77b7da1c\\serving_ram from %s\n", $unsigned(80'h636f72655f322e686578)); + end + if (1'h1) begin + $write("Preloading $paramod$b5dfc6750142ce72487821be1cc9408055af45a7\\serving_ram from %s\n", $unsigned(80'h636f72655f332e686578)); + end + if (1'h1) begin + $write("Preloading $paramod$165daad42e85011cef3d0a8b9a71d37205f9baea\\serving_ram from %s\n", $unsigned(80'h636f72655f342e686578)); + end + end + assign { _1199_[2], _1199_[0] } = { _1058_[2], \corescorecore.core_4.serving.cpu.alu.i_en }; + assign _1200_[2:1] = { \corescorecore.core_4.serving.arbiter.i_wb_mem_ack , _1082_[0] }; + assign _1201_[2:0] = { \corescorecore.core_4.serving.rf_ram_if.wgo , \corescorecore.core_4.serving.rf_ram_if.wtrig0 , \corescorecore.core_4.serving.rf_ram_if.wen0_r }; + assign _1202_[1] = \corescorecore.core_4.serving.ram.wb_en ; + assign _1203_[1:0] = { \corescorecore.core_4.serving.cpu.state.o_cnt_r [0], \corescorecore.core_4.serving.cpu.state.o_cnt [2] }; + assign _1204_[3:2] = { _0931_, \corescorecore.core_4.serving.cpu.alu.b_inv_plus_1_cy_r }; + assign _1205_[3:1] = { \corescorecore.core_4.serving.cpu.alu.i_en , \corescorecore.core_4.serving.cpu.alu.add_cy_r , \corescorecore.core_4.serving.cpu.alu.i_rs1 }; + assign _1206_[3:1] = { _1081_[0], \corescorecore.core_4.serving.cpu.ctrl.pc_plus_4_cy_r , \corescorecore.core_4.serving.cpu.ctrl.pc }; + assign { _1207_[3], _1207_[1:0] } = { \corescorecore.core_4.serving.cpu.ctrl.pc , \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_4.serving.cpu.decode.m3 }; + assign _1208_[1] = \corescorecore.core_4.serving.cpu.alu.i_buf ; + assign _1209_[1:0] = { _1039_[0], _1039_[1] }; + assign _1210_[3:2] = { _1081_[0], \corescorecore.core_4.serving.cpu.ctrl.pc_plus_offset_cy_r }; + assign _1211_[2:1] = { \corescorecore.core_2.serving.arbiter.i_wb_mem_ack , _1096_[0] }; + assign _1212_[2:0] = { \corescorecore.core_2.serving.rf_ram_if.wgo , \corescorecore.core_2.serving.rf_ram_if.wtrig0 , \corescorecore.core_2.serving.rf_ram_if.wen0_r }; + assign _1213_[1] = \corescorecore.core_2.serving.ram.wb_en ; + assign _1214_[1:0] = { \corescorecore.core_2.serving.cpu.state.o_cnt_r [0], \corescorecore.core_2.serving.cpu.state.o_cnt [2] }; + assign { _1215_[2], _1215_[0] } = { \corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy_r , _0924_ }; + assign _1216_[1:0] = \emitter.data [3:2]; + assign _1217_[1] = \emitter.data [0]; + assign { _1218_[3], _1218_[0] } = { _1006_[0], \corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [2] }; + assign _1219_[1] = \corescorecore.core_0.serving.ram.wb_en ; + assign _1220_[2:0] = { \corescorecore.core_2.serving.cpu.mem_bytecnt [1], \corescorecore.core_2.serving.cpu.state.o_cnt [2], \corescorecore.core_2.serving.cpu.mem_bytecnt [0] }; + assign _1221_[1:0] = { _1177_[0], _1177_[1] }; + assign { _1222_[3], _1222_[1:0] } = { \corescorecore.core_2.serving.cpu.ctrl.pc , \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_2.serving.cpu.decode.m3 }; + assign _1223_[3:2] = { _1095_[0], \corescorecore.core_2.serving.cpu.ctrl.pc_plus_offset_cy_r }; + assign { _1224_[3], _1224_[1:0] } = { \corescorecore.core_2.serving.cpu.decode.opcode [2], _1177_[1:0] }; + assign _1225_[3:2] = { \corescorecore.core_2.serving.cpu.alu.i_init , \corescorecore.core_2.serving.cpu.bufreg.c_r }; + assign _1226_[3:1] = { _0924_, \corescorecore.core_2.serving.cpu.alu.b_inv_plus_1_cy_r , _1215_[1] }; + assign _1227_[3:1] = { \corescorecore.core_2.serving.cpu.alu.i_en , \corescorecore.core_2.serving.cpu.alu.add_cy_r , \corescorecore.core_2.serving.cpu.alu.i_rs1 }; + assign { _1228_[3], _1228_[0] } = { _1095_[0], \corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [2] }; + assign { _1229_[3], _1229_[1:0] } = { \corescorecore.core_3.serving.cpu.decode.opcode [0], \corescorecore.core_3.serving.cpu.decode.signbit , \corescorecore.core_3.serving.cpu.decode.imm19_12_20 [0] }; + assign { _1230_[3:2], _1230_[0] } = { \corescorecore.core_3.serving.cpu.decode.m3 , \corescorecore.core_3.serving.cpu.decode.opcode [0], \corescorecore.core_3.serving.cpu.decode.imm7 }; + assign { _1231_[2], _1231_[0] } = { \corescorecore.core_3.serving.cpu.alu.i_en , \corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [30] }; + assign { _1232_[3], _1232_[1:0] } = { \corescorecore.core_4.serving.cpu.decode.opcode [0], \corescorecore.core_4.serving.cpu.decode.signbit , \corescorecore.core_4.serving.cpu.decode.imm19_12_20 [0] }; + assign { _1233_[3:2], _1233_[0] } = { \corescorecore.core_4.serving.cpu.decode.m3 , \corescorecore.core_4.serving.cpu.decode.opcode [0], \corescorecore.core_4.serving.cpu.decode.imm7 }; + assign { _1234_[2], _1234_[0] } = { \corescorecore.core_4.serving.cpu.alu.i_en , \corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [30] }; + assign _1235_[2:0] = { \corescorecore.core_2.serving.cpu.state.i_ctrl_misalign , \corescorecore.core_2.o_tlast , \corescorecore.axis_mux.s_axis_tdata [16] }; + assign _1236_[2:0] = { \corescorecore.core_3.serving.cpu.state.i_ctrl_misalign , \corescorecore.core_3.o_tlast , \corescorecore.axis_mux.s_axis_tdata [24] }; + assign _1237_[2:0] = { \corescorecore.core_4.serving.cpu.state.i_ctrl_misalign , \corescorecore.core_4.o_tlast , \corescorecore.axis_mux.s_axis_tdata [32] }; + assign _1238_[0] = \corescorecore.core_4.serving.cpu.state.stage_two_pending ; + assign { _1239_[3:2], _1239_[0] } = { \corescorecore.core_4.serving.cpu.decode.opcode [2], \corescorecore.core_4.serving.cpu.decode.m3 , \corescorecore.core_4.serving.cpu.decode.opcode [0] }; + assign { _1240_[3], _1240_[1] } = { _1196_[1], \corescorecore.core_4.serving.cpu.state.stage_two_req }; + assign { _1241_[3:2], _1241_[0] } = { \corescorecore.core_0.serving.cpu.decode.m3 , \corescorecore.core_0.serving.cpu.decode.opcode [0], \corescorecore.core_0.serving.cpu.decode.imm7 }; + assign { _1242_[2], _1242_[0] } = { \corescorecore.core_0.serving.cpu.alu.i_en , \corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [30] }; + assign _1243_[3:1] = { _0950_, \corescorecore.core_3.serving.cpu.alu.b_inv_plus_1_cy_r , _1190_[0] }; + assign _1244_[3:1] = { \corescorecore.core_3.serving.cpu.alu.i_en , \corescorecore.core_3.serving.cpu.alu.add_cy_r , \corescorecore.core_3.serving.cpu.alu.i_rs1 }; + assign _1245_[1] = \corescorecore.core_3.serving.cpu.alu.i_en ; + assign _1246_[1] = \corescorecore.core_1.serving.ram.wb_en ; + assign { _1247_[3], _1247_[1:0] } = { \clkgen.o_rst_core , \corescorecore.axis_mux.m_axis_tvalid , \corescorecore.axis_mux.m_axis_tready }; + assign _1248_[2:0] = { \corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [1], \corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_0.serving.ram.wb_en }; + assign _1249_[0] = _1248_[3]; + assign _1250_[2:0] = { \corescorecore.core_0.serving.rf_ram_if.wgo , \corescorecore.core_0.serving.rf_ram_if.wtrig0 , \corescorecore.core_0.serving.rf_ram_if.wen0_r }; + assign { _1251_[3], _1251_[1:0] } = { \corescorecore.core_1.serving.rf_ram_if.o_waddr [0], \corescorecore.core_1.serving.rf_ram_if.wreq_r , \corescorecore.core_1.serving.rf_ram_if.wgo }; + assign { _1252_[3:2], _1252_[0] } = { _1063_[3], \clkgen.o_rst_core , \corescorecore.axis_mux.arb_inst.mask_reg [2] }; + assign { _1253_[2], _1253_[0] } = { _1240_[0], _1196_[1] }; + assign _1254_[1:0] = { _1199_[1], \corescorecore.core_4.serving.i_wb_ack }; + assign { _1255_[2], _1255_[0] } = { \corescorecore.core_4.serving.rf_ram_if.rgnt , _1253_[1] }; + assign { _1256_[2], _1256_[0] } = { \corescorecore.core_4.serving.cpu.alu.i_cnt_done , \corescorecore.core_4.serving.cpu.alu.i_init }; + assign _1257_[2:1] = { \corescorecore.core_2.serving.cpu.ctrl.pc_plus_4_cy_r , \corescorecore.core_2.serving.cpu.ctrl.pc }; + assign _1258_[2:1] = { \corescorecore.core_2.serving.cpu.ctrl.en_pc_r , _1223_[0] }; + assign _1259_[2] = \corescorecore.core_2.serving.cpu.ctrl.i_jump ; + assign { _1260_[3:2], _1260_[0] } = { _1095_[0], \clkgen.o_rst_core , \corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [31] }; + assign { _1261_[3:2], _1261_[0] } = { _1063_[3], \clkgen.o_rst_core , \corescorecore.axis_mux.arb_inst.mask_reg [3] }; + assign { _1262_[3], _1262_[1:0] } = { \corescorecore.core_4.serving.cpu.decode.opcode [2], _1039_[1:0] }; + assign _1263_[3:2] = { \corescorecore.core_4.serving.cpu.alu.i_init , \corescorecore.core_4.serving.cpu.bufreg.c_r }; + assign { _1264_[3:2], _1264_[0] } = { _1063_[3], \clkgen.o_rst_core , \corescorecore.axis_mux.arb_inst.mask_reg [0] }; + assign _1265_[3:1] = { \corescorecore.core_3.serving.cpu.alu.i_rs1 , _0950_, \corescorecore.core_3.serving.cpu.alu.lt_r }; + assign { _1266_[2], _1266_[0] } = { \corescorecore.core_3.serving.cpu.decode.o_mem_half , \corescorecore.core_3.serving.cpu.decode.opcode [0] }; + assign { _1267_[3], _1267_[1:0] } = { \clkgen.o_rst_core , \corescorecore.core_3.serving.cpu.ctrl.i_jump , \corescorecore.core_3.serving.cpu.alu.i_cnt_done }; + assign { _1268_[3:2], _1268_[0] } = { _1192_[0], _1048_[1], \clkgen.o_rst_core }; + assign { _1269_[3], _1269_[1:0] } = { \corescorecore.core_2.serving.rf_ram_if.o_waddr [0], \corescorecore.core_2.serving.rf_ram_if.wreq_r , \corescorecore.core_2.serving.rf_ram_if.wgo }; + assign _1270_[2] = \corescorecore.core_3.serving.cpu.ctrl.i_jump ; + assign _1271_[1:0] = { _1053_[1], \clkgen.o_rst_core }; + assign { _1272_[3], _1272_[1:0] } = { \clkgen.o_rst_core , \corescorecore.axis_mux.arb_inst.grant_encoded [1], _1062_[1] }; + assign _1273_[2:0] = { _1046_[1], _1018_[3], \corescorecore.core_0.serving.cpu.alu.i_en }; + assign _1274_[0] = _1035_[3]; + assign { _1275_[2], _1275_[0] } = { _1074_[2], \corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [2] }; + assign _1276_[0] = _1140_[3]; + assign _1277_[1] = \clkgen.rst_reg1 ; + assign _1278_[2] = \corescorecore.core_1.serving.cpu.decode.o_mem_word ; + assign { _1279_[2], _1279_[0] } = { \corescorecore.core_1.serving.cpu.alu.i_sh_right , _1137_[3] }; + assign _1280_[2] = _1120_[3]; + assign _1281_[0] = _1037_[3]; + assign _1282_[0] = _1044_[3]; + assign _1283_[2:0] = { \clkgen.o_rst_core , _1162_[0], \corescorecore.axis_mux.temp_m_axis_tvalid_reg }; + assign { _1284_[3], _1284_[1:0] } = { \corescorecore.core_4.serving.rf_ram_if.o_waddr [1], \corescorecore.core_4.serving.rf_ram_if.wgo , \corescorecore.core_4.serving.rf_ram_if.wreq_r }; + assign { _1285_[2], _1285_[0] } = { \corescorecore.core_3.serving.cpu.alu.i_cnt_done , \corescorecore.core_3.serving.cpu.alu.i_init }; + assign { _1286_[3:2], _1286_[0] } = { _1063_[3], \clkgen.o_rst_core , \corescorecore.axis_mux.arb_inst.mask_reg [1] }; + assign _1288_[0] = \corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [2]; + assign { _1289_[2], _1289_[0] } = { \corescorecore.core_4.serving.cpu.alu.i_en , \corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [19] }; + assign _1291_[2:0] = { \corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [4], \corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_2.serving.ram.wb_en }; + assign _1292_[2:0] = { \corescorecore.core_2.serving.cpu.alu.add_cy_r , \corescorecore.core_2.serving.cpu.alu.i_rs1 , _1227_[0] }; + assign _1293_[2:0] = { \corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [2], \corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_4.serving.ram.wb_en }; + assign _1294_[3:1] = { \corescorecore.core_4.serving.cpu.ctrl.en_pc_r , _1208_[0], _1210_[0] }; + assign _1295_[2:1] = { \corescorecore.core_4.serving.cpu.decode.opcode [0], \corescorecore.core_4.serving.cpu.decode.m3 }; + assign _1296_[0] = _1253_[1]; + assign _1297_[2:0] = { \corescorecore.core_4.serving.cpu.alu.add_cy_r , \corescorecore.core_4.serving.cpu.alu.i_rs1 , _1205_[0] }; + assign { _1298_[3], _1298_[1:0] } = { _1195_[1], \corescorecore.core_4.serving.cpu.alu.i_buf , \corescorecore.core_4.serving.cpu.alu.shift.signbit }; + assign _1299_[2:0] = { _1239_[1], _1204_[1], \corescorecore.core_4.serving.cpu.alu.result_lt_r }; + assign _1300_[2] = \corescorecore.core_4.serving.cpu.decode.o_mem_word ; + assign { _1301_[2], _1301_[0] } = { \corescorecore.core_4.serving.cpu.alu.i_sh_right , _1195_[1] }; + assign _1302_[2] = _1195_[0]; + assign _1303_[0] = \corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [3]; + assign { _1304_[3], _1304_[1:0] } = { \corescorecore.core_3.serving.cpu.decode.opcode [2], _1122_[0], _1122_[1] }; + assign _1305_[2] = \corescorecore.core_3.serving.cpu.bufreg.c_r ; + assign { _1306_[3], _1306_[1:0] } = { _1086_[1], \corescorecore.core_3.serving.cpu.alu.i_buf , \corescorecore.core_3.serving.cpu.alu.shift.signbit }; + assign _1307_[2:0] = { _1084_[1], _1190_[0], \corescorecore.core_3.serving.cpu.alu.result_lt_r }; + assign { _1308_[2], _1308_[0] } = { \corescorecore.core_4.serving.cpu.ctrl.i_jump , _1295_[0] }; + assign _1309_[0] = \corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [4]; + assign _1310_[2:0] = { \corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [2], \corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_2.serving.ram.wb_en }; + assign _1311_[0] = _1104_[0]; + assign { _1312_[3], _1312_[1:0] } = { _1101_[1], \corescorecore.core_2.serving.cpu.alu.i_buf , \corescorecore.core_2.serving.cpu.alu.shift.signbit }; + assign _1314_[0] = _1136_[3]; + assign _1315_[1] = \corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [0]; + assign { _1316_[2], _1316_[0] } = { _1074_[2], \corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [4] }; + assign _1317_[0] = _1166_[3]; + assign _1318_[0] = _1164_[3]; + assign { _1320_[3], _1320_[1:0] } = { \clkgen.o_rst_core , \corescorecore.core_2.serving.cpu.ctrl.i_jump , \corescorecore.core_2.serving.cpu.alu.i_cnt_done }; + assign { _1321_[3], _1321_[0] } = { _1089_[0], \corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [2] }; + assign _1322_[0] = \corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [1]; + assign { _1323_[2], _1323_[0] } = { _1322_[2], \corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [3] }; + assign { _1324_[3:2], _1324_[0] } = { _1081_[0], \clkgen.o_rst_core , \corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [31] }; + assign { _1325_[2], _1325_[0] } = { _1322_[2], \corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [4] }; + assign { _1326_[3], _1326_[0] } = { _1002_[0], \corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [2] }; + assign _1328_[2:0] = { _1063_[3], \corescorecore.axis_mux.arb_inst.grant [2], _1062_[1] }; + assign { _1329_[2], _1329_[0] } = { \corescorecore.core_2.serving.cpu.alu.i_en , \corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [19] }; + assign { _1330_[2], _1330_[0] } = { _1309_[2], \corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [1] }; + assign _1331_[2:0] = { \corescorecore.core_4.serving.rf_ram_if.wgo , \corescorecore.core_4.serving.rf_ram_if.wtrig0 , \corescorecore.core_4.serving.rf_ram_if.wen0_r }; + assign { _1332_[2], _1332_[0] } = { _1303_[2], \corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [2] }; + assign _1333_[1] = \clkgen.o_rst_core ; + assign { _1334_[2], _1334_[0] } = { _1309_[2], \corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [2] }; + assign { _1335_[2], _1335_[0] } = { _1309_[2], \corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [3] }; + assign _1336_[2:0] = { \corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [3], \corescorecore.core_4.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_4.serving.ram.wb_en }; + assign { _1337_[2], _1337_[0] } = { _1288_[2], \corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [3] }; + assign _1338_[2:0] = { \corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [1], \corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_2.serving.ram.wb_en }; + assign { _1339_[2], _1339_[0] } = { _1303_[2], \corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [1] }; + assign _1340_[2:0] = { _1063_[3], \corescorecore.axis_mux.arb_inst.grant [3], _1062_[1] }; + assign _1341_[0] = _1336_[3]; + assign _1342_[0] = _1293_[3]; + assign _1343_[2:0] = { _1063_[3], \corescorecore.axis_mux.arb_inst.grant [4], _1062_[1] }; + assign _1344_[1] = \clkgen.o_rst_core ; + assign _1345_[1:0] = { _1059_[1], \clkgen.o_rst_core }; + assign _1346_[0] = _1310_[3]; + assign _1347_[2:0] = { _1099_[1], _1215_[1], \corescorecore.core_2.serving.cpu.alu.result_lt_r }; + assign _1348_[2] = \corescorecore.core_2.serving.cpu.decode.o_mem_word ; + assign { _1349_[2], _1349_[0] } = { \corescorecore.core_2.serving.cpu.alu.i_sh_right , _1101_[1] }; + assign _1350_[2] = _1101_[0]; + assign _1351_[0] = _1338_[3]; + assign _1352_[0] = _1291_[3]; + assign _1353_[2:0] = { \corescorecore.core_2.serving.rf_ram_if.wgo , \corescorecore.core_2.serving.rf_ram_if.wtrig0 , \corescorecore.core_2.serving.rf_ram_if.wen0_r }; + assign _1354_[2:0] = { \corescorecore.core_2.serving.cpu.decode.o_rf_rd_addr [0], \corescorecore.core_2.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_2.serving.ram.wb_en }; + assign _1356_[2:0] = { \corescorecore.core_3.serving.cpu.alu.add_cy_r , \corescorecore.core_3.serving.cpu.alu.i_rs1 , _1244_[0] }; + assign _1358_[0] = _1092_[0]; + assign _1359_[2] = \corescorecore.core_3.serving.cpu.decode.o_mem_word ; + assign { _1360_[2], _1360_[0] } = { \corescorecore.core_3.serving.cpu.alu.i_sh_right , _1086_[1] }; + assign _1361_[2] = _1086_[0]; + assign _1362_[2:0] = { \corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [3], \corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_3.serving.ram.wb_en }; + assign _1363_[2:0] = { \corescorecore.core_3.serving.cpu.decode.o_rf_rd_addr [4], \corescorecore.core_3.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_3.serving.ram.wb_en }; + assign _1364_[2:0] = { \corescorecore.core_3.serving.rf_ram_if.wgo , \corescorecore.core_3.serving.rf_ram_if.wtrig0 , \corescorecore.core_3.serving.rf_ram_if.wen0_r }; + assign { _1365_[2], _1365_[0] } = { _1322_[2], \corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [2] }; + assign _1366_[0] = _1363_[3]; + assign { _1367_[2], _1367_[0] } = { \corescorecore.core_1.serving.cpu.alu.i_en , \corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [19] }; + assign _1368_[0] = _1362_[3]; + assign { _1369_[2], _1369_[0] } = { \corescorecore.core_3.serving.cpu.alu.i_en , \corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [19] }; + assign _1370_[2:0] = { _1063_[3], \corescorecore.axis_mux.arb_inst.grant [1], _1062_[1] }; + assign _1371_[1] = \clkgen.o_rst_core ; + assign { _1372_[2], _1372_[0] } = { _1288_[2], \corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [1] }; + assign { _1373_[3:2], _1373_[0] } = { _1089_[0], \clkgen.o_rst_core , \corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [31] }; + assign _1374_[1] = \clkgen.o_rst_core ; + assign _1375_[0] = _1354_[3]; + assign { _1376_[2], _1376_[0] } = { _1303_[2], \corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [4] }; + assign { _1377_[2], _1377_[0] } = { _1288_[2], \corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [4] }; + assign { _1378_[3], _1378_[1:0] } = { \corescorecore.core_0.serving.rf_ram_if.o_waddr [1], \corescorecore.core_0.serving.rf_ram_if.wgo , \corescorecore.core_0.serving.rf_ram_if.wreq_r }; + assign _1198_[3:1] = { _1089_[0], \corescorecore.core_3.serving.cpu.ctrl.pc_plus_4_cy_r , \corescorecore.core_3.serving.cpu.ctrl.pc }; + assign { _1197_[3], _1197_[1:0] } = { \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we , _1122_[0], _1122_[1] }; + assign { _1196_[2], _1196_[0] } = { \corescorecore.core_4.serving.cpu.alu.i_en , \corescorecore.core_4.serving.cpu.state.stage_two_req }; + assign _1194_[1] = \corescorecore.core_3.serving.ram.wb_en ; + assign _1193_[2:0] = { \corescorecore.core_3.serving.rf_ram_if.wgo , \corescorecore.core_3.serving.rf_ram_if.wtrig0 , \corescorecore.core_3.serving.rf_ram_if.wen0_r }; + assign _1192_[3:1] = { \corescorecore.core_3.serving.arbiter.i_wb_mem_ack , _1090_[0], _1090_[1] }; + assign { _1191_[3], _1191_[0] } = { _1081_[0], \corescorecore.core_4.serving.cpu.decode.o_rf_rd_addr [2] }; + assign _1190_[1] = \corescorecore.core_3.serving.cpu.alu.i_init ; + assign { _1189_[3:2], _1189_[0] } = { _1002_[0], \clkgen.o_rst_core , \corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [31] }; + assign { _1188_[2], _1188_[0] } = { \corescorecore.core_0.serving.cpu.ctrl.i_jump , _1154_[0] }; + assign { _1187_[2], _1187_[0] } = { \corescorecore.core_2.serving.cpu.decode.o_mem_half , \corescorecore.core_2.serving.cpu.decode.opcode [0] }; + assign { _1186_[3], _1186_[1:0] } = { \clkgen.o_rst_core , \corescorecore.axis_mux.arb_inst.grant_encoded [0], _1062_[1] }; + assign _1185_[3:1] = { \corescorecore.core_2.serving.cpu.alu.i_sh_right , \corescorecore.core_2.serving.cpu.decode.o_mem_word , \corescorecore.core_2.serving.cpu.alu.result_lt }; + assign _1184_[3:1] = { \corescorecore.core_2.serving.cpu.alu.i_rs1 , _0924_, \corescorecore.core_2.serving.cpu.alu.lt_r }; + assign { _1183_[3], _1183_[1:0] } = { \clkgen.o_rst_core , \corescorecore.core_1.serving.cpu.ctrl.i_jump , \corescorecore.core_1.serving.cpu.alu.i_cnt_done }; + assign { _1182_[3], _1182_[1:0] } = { \corescorecore.core_3.serving.rf_ram_if.o_waddr [1], \corescorecore.core_3.serving.rf_ram_if.wreq_r , \corescorecore.core_3.serving.rf_ram_if.wgo }; + assign { _1181_[2], _1181_[0] } = { \corescorecore.core_1.serving.cpu.decode.o_mem_half , \corescorecore.core_1.serving.cpu.decode.opcode [0] }; + assign _1180_[3:1] = { \corescorecore.core_1.serving.cpu.alu.i_sh_right , \corescorecore.core_1.serving.cpu.decode.o_mem_word , \corescorecore.core_1.serving.cpu.alu.result_lt }; + assign _1179_[3:1] = { \corescorecore.core_1.serving.cpu.alu.i_rs1 , _0905_, \corescorecore.core_1.serving.cpu.alu.lt_r }; + assign _1178_[1:0] = { \corescorecore.core_1.serving.cpu.decode.m3 , \corescorecore.core_1.serving.cpu.decode.opcode [2] }; + assign _1177_[3] = \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we ; + assign _1176_[2:0] = { \corescorecore.core_2.serving.cpu.alu.i_cnt_done , \corescorecore.core_2.serving.cpu.decode.imm11_7 [0], \corescorecore.core_2.serving.cpu.decode.imm24_20 [0] }; + assign { _1175_[3:2], _1175_[0] } = { _1006_[0], \clkgen.o_rst_core , \corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [31] }; + assign { _1174_[2], _1174_[0] } = { \corescorecore.core_1.serving.cpu.alu.i_cnt_done , \corescorecore.core_1.serving.cpu.alu.i_init }; + assign _1173_[1:0] = { \corescorecore.core_2.serving.cpu.decode.m3 , \corescorecore.core_2.serving.cpu.decode.opcode [2] }; + assign { _1172_[2], _1172_[0] } = { \corescorecore.core_1.serving.cpu.ctrl.i_jump , _1132_[0] }; + assign _1171_[2:0] = { \corescorecore.core_1.serving.rf_ram_if.rgnt , _1009_[2], _1135_[0] }; + assign _1170_[1] = \corescorecore.core_1.serving.cpu.state.stage_two_req ; + assign _1169_[0] = \corescorecore.core_1.serving.cpu.state.stage_two_pending ; + assign _1168_[1:0] = { \corescorecore.core_1.serving.cpu.alu.shamt [0], \corescorecore.core_1.serving.cpu.alu.shift.cnt [0] }; + assign _1166_[2:0] = { \corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [0], \corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_0.serving.ram.wb_en }; + assign _1164_[2:0] = { \corescorecore.core_0.serving.cpu.decode.o_rf_rd_addr [3], \corescorecore.core_0.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_0.serving.ram.wb_en }; + assign _1163_[1] = \clkgen.o_rst_core ; + assign _1162_[3:1] = { \corescorecore.axis_mux.m_axis_tready , \corescorecore.axis_mux.temp_m_axis_tvalid_reg , \corescorecore.axis_mux.m_axis_tvalid }; + assign _1161_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], _1059_[0] }; + assign _1160_[1] = \clkgen.o_rst_core ; + assign _1159_[2:0] = { _1063_[3], \corescorecore.axis_mux.arb_inst.grant [0], _1062_[1] }; + assign _1158_[2] = _1011_[0]; + assign _1157_[2:1] = { \corescorecore.core_0.serving.cpu.alu.add_cy_r , \corescorecore.core_0.serving.cpu.alu.i_rs1 }; + assign _1156_[3:1] = { _0878_, \corescorecore.core_0.serving.cpu.alu.b_inv_plus_1_cy_r , _1071_[2] }; + assign _1155_[0] = _1015_[0]; + assign _1154_[2:1] = { \corescorecore.core_0.serving.cpu.decode.opcode [0], \corescorecore.core_0.serving.cpu.decode.m3 }; + assign _1153_[3:2] = { \corescorecore.core_0.serving.cpu.ctrl.en_pc_r , _1149_[3] }; + assign _1152_[1] = \corescorecore.core_0.serving.cpu.ctrl.pc_plus_offset_cy_r ; + assign { _1151_[3], _1151_[1:0] } = { \corescorecore.core_0.serving.cpu.ctrl.pc , \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_0.serving.cpu.decode.m3 }; + assign _1150_[1:0] = { _1017_[0], _1017_[1] }; + assign _1149_[2:0] = { \corescorecore.core_0.serving.cpu.mem_bytecnt [1], \corescorecore.core_0.serving.cpu.state.o_cnt [2], \corescorecore.core_0.serving.cpu.mem_bytecnt [0] }; + assign _1148_[2:0] = { \corescorecore.core_0.serving.cpu.state.i_ctrl_misalign , \corescorecore.core_0.o_tlast , \corescorecore.axis_mux.s_axis_tdata [0] }; + assign { _1147_[2], _1147_[0] } = { \corescorecore.core_0.serving.cpu.alu.i_sh_right , _1011_[1] }; + assign _1146_[2] = \corescorecore.core_0.serving.cpu.decode.o_mem_word ; + assign _1145_[2:0] = { _1010_[1], _1071_[2], \corescorecore.core_0.serving.cpu.alu.result_lt_r }; + assign { _1144_[3], _1144_[1:0] } = { _1011_[1], \corescorecore.core_0.serving.cpu.alu.i_buf , \corescorecore.core_0.serving.cpu.alu.shift.signbit }; + assign _1143_[2:1] = { \corescorecore.core_0.serving.cpu.ctrl.pc_plus_4_cy_r , \corescorecore.core_0.serving.cpu.ctrl.pc }; + assign { _1142_[2], _1142_[0] } = { _1074_[2], \corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [3] }; + assign { _1141_[2], _1141_[0] } = { \corescorecore.core_0.serving.cpu.alu.i_en , \corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [19] }; + assign _1140_[2:0] = { \corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [1], \corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_1.serving.ram.wb_en }; + assign _1139_[2:1] = { \corescorecore.core_1.serving.cpu.alu.add_cy_r , \corescorecore.core_1.serving.cpu.alu.i_rs1 }; + assign _1138_[2:0] = { _1127_[1], _1034_[1], \corescorecore.core_1.serving.cpu.alu.result_lt_r }; + assign _1137_[1:0] = { \corescorecore.core_1.serving.cpu.alu.i_buf , \corescorecore.core_1.serving.cpu.alu.shift.signbit }; + assign _1136_[2:0] = { \corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [2], \corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_1.serving.ram.wb_en }; + assign \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [1:0] = 2'h0; + assign \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [8:0] = { \corescorecore.core_0.o_tlast , \corescorecore.axis_mux.s_axis_tdata [7:0] }; + assign \corescorecore.core_0.serving.arbiter.i_wb_cpu_ibus_adr [0] = \corescorecore.core_0.serving.cpu.ctrl.pc ; + assign _1134_[3:1] = { \corescorecore.core_1.serving.cpu.ctrl.en_pc_r , _1028_[3], _1051_[0] }; + assign _1133_[2:0] = { \corescorecore.core_1.serving.cpu.state.i_ctrl_misalign , \corescorecore.core_1.o_tlast , \corescorecore.axis_mux.s_axis_tdata [8] }; + assign _1132_[2:1] = { \corescorecore.core_1.serving.cpu.decode.opcode [0], \corescorecore.core_1.serving.cpu.decode.m3 }; + assign _1131_[2:1] = { \corescorecore.core_1.serving.cpu.ctrl.pc_plus_4_cy_r , \corescorecore.core_1.serving.cpu.ctrl.pc }; + assign _1130_[2:0] = { \corescorecore.core_1.serving.rf_ram_if.wgo , \corescorecore.core_1.serving.rf_ram_if.wtrig0 , \corescorecore.core_1.serving.rf_ram_if.wen0_r }; + assign _1129_[1:0] = { \corescorecore.core_3.serving.cpu.state.o_cnt_r [2], \corescorecore.core_3.serving.cpu.state.o_cnt [2] }; + assign _1128_[0] = _0868_[0]; + assign { _1127_[3:2], _1127_[0] } = { \corescorecore.core_1.serving.cpu.decode.opcode [2], \corescorecore.core_1.serving.cpu.decode.m3 , \corescorecore.core_1.serving.cpu.decode.opcode [0] }; + assign _1126_[0] = _0871_[0]; + assign _1125_[2] = \corescorecore.core_3.serving.cpu.ctrl.en_pc_r ; + assign _1124_[1] = \corescorecore.core_3.serving.cpu.ctrl.pc_plus_offset_cy_r ; + assign { _1123_[3], _1123_[1:0] } = { \corescorecore.core_3.serving.cpu.ctrl.pc , \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_3.serving.cpu.decode.m3 }; + assign _1121_[2:0] = { \corescorecore.core_3.serving.cpu.alu.i_cnt_done , \corescorecore.core_3.serving.cpu.decode.imm11_7 [0], \corescorecore.core_3.serving.cpu.decode.imm24_20 [0] }; + assign _1120_[2:0] = { \corescorecore.core_1.serving.cpu.alu.i_init , \corescorecore.core_1.serving.cpu.bufreg.q , \corescorecore.core_1.serving.cpu.alu.i_buf }; + assign _1119_[2] = \corescorecore.core_1.serving.cpu.bufreg.c_r ; + assign { _1118_[3], _1118_[1:0] } = { \corescorecore.core_1.serving.cpu.decode.opcode [2], _1033_[1:0] }; + assign _1117_[1] = \corescorecore.axis_mux.arb_inst.masked_request_valid ; + assign _1116_[2:0] = { \corescorecore.core_3.serving.cpu.mem_bytecnt [1], \corescorecore.core_3.serving.cpu.state.o_cnt [2], \corescorecore.core_3.serving.cpu.mem_bytecnt [0] }; + assign { \corescorecore.core_0.serving.cpu.bufreg.data [31:2], \corescorecore.core_0.serving.cpu.bufreg.data [0] } = { \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31:2], \corescorecore.core_0.serving.cpu.alu.i_buf }; + assign { _1115_[3], _1115_[1:0] } = { _1063_[3], \corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [1], \corescorecore.axis_mux.arb_inst.masked_request_valid }; + assign _1114_[1] = \clkgen.o_rst_core ; + assign { _1113_[3], _1113_[1:0] } = { _1063_[3], \corescorecore.axis_mux.arb_inst.grant_encoded [2], _1062_[1] }; + assign _1112_[2:1] = { \corescorecore.axis_mux.arb_inst.masked_request_index [2], \corescorecore.axis_mux.arb_inst.priority_encoder_inst.output_encoded [2] }; + assign \corescorecore.core_0.serving.cpu.bufreg.o_lsb [1] = \corescorecore.core_0.serving.cpu.state.i_ctrl_misalign ; + assign { _1111_[2], _1111_[0] } = { \corescorecore.core_2.serving.cpu.alu.i_en , \corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [30] }; + assign { _1110_[3:2], _1110_[0] } = { \corescorecore.core_2.serving.cpu.decode.m3 , \corescorecore.core_2.serving.cpu.decode.opcode [0], \corescorecore.core_2.serving.cpu.decode.imm7 }; + assign { _1109_[3], _1109_[1:0] } = { \corescorecore.core_2.serving.cpu.decode.opcode [0], \corescorecore.core_2.serving.cpu.decode.signbit , \corescorecore.core_2.serving.cpu.decode.imm19_12_20 [0] }; + assign { _1108_[2], _1108_[0] } = { \corescorecore.core_1.serving.cpu.alu.i_en , \corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [30] }; + assign { _1107_[3:2], _1107_[0] } = { \corescorecore.core_1.serving.cpu.decode.m3 , \corescorecore.core_1.serving.cpu.decode.opcode [0], \corescorecore.core_1.serving.cpu.decode.imm7 }; + assign { _1106_[3], _1106_[1:0] } = { \corescorecore.core_1.serving.cpu.decode.opcode [0], \corescorecore.core_1.serving.cpu.decode.signbit , \corescorecore.core_1.serving.cpu.decode.imm19_12_20 [0] }; + assign { _1105_[2], _1105_[0] } = { \corescorecore.core_2.serving.cpu.alu.i_cnt_done , \corescorecore.core_2.serving.cpu.alu.i_init }; + assign _1103_[0] = \corescorecore.core_2.serving.cpu.state.stage_two_pending ; + assign _1102_[1:0] = { \corescorecore.core_2.serving.cpu.alu.shamt [0], \corescorecore.core_2.serving.cpu.alu.shift.cnt [0] }; + assign { _1100_[2], _1100_[0] } = { \corescorecore.core_2.serving.rf_ram_if.rgnt , \corescorecore.core_2.serving.cpu.state.stage_two_req }; + assign { _1099_[3:2], _1099_[0] } = { \corescorecore.core_2.serving.cpu.decode.opcode [2], \corescorecore.core_2.serving.cpu.decode.m3 , \corescorecore.core_2.serving.cpu.decode.opcode [0] }; + assign { _1098_[3], _1098_[1:0] } = { \corescorecore.core_0.serving.cpu.decode.opcode [0], \corescorecore.core_0.serving.cpu.decode.signbit , \corescorecore.core_0.serving.cpu.decode.imm19_12_20 [0] }; + assign _1097_[2:0] = { \corescorecore.core_2.serving.i_wb_ack , \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31:30] }; + assign _1096_[3:1] = { \corescorecore.core_2.serving.arbiter.i_wb_mem_ack , \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31:30] }; + assign _1095_[1] = \corescorecore.core_2.serving.cpu.ctrl.en_pc_r ; + assign { _1094_[2], _1094_[0] } = { \corescorecore.core_0.serving.cpu.alu.i_cnt_done , \corescorecore.core_0.serving.cpu.alu.i_init }; + assign _1093_[1:0] = { \corescorecore.core_3.serving.cpu.decode.m3 , \corescorecore.core_3.serving.cpu.decode.opcode [2] }; + assign _1092_[2] = \corescorecore.core_3.serving.rf_ram_if.rgnt ; + assign _1091_[1:0] = { _1090_[1], \corescorecore.core_3.serving.i_wb_ack }; + assign _1090_[2] = \corescorecore.core_3.serving.arbiter.i_wb_mem_ack ; + assign _1089_[1] = \corescorecore.core_3.serving.cpu.ctrl.en_pc_r ; + assign _1088_[1] = \corescorecore.core_3.serving.cpu.state.stage_two_req ; + assign _1087_[0] = \corescorecore.core_3.serving.cpu.state.stage_two_pending ; + assign _1085_[1:0] = { \corescorecore.core_3.serving.cpu.alu.shamt [0], \corescorecore.core_3.serving.cpu.alu.shift.cnt [0] }; + assign { _1084_[3:2], _1084_[0] } = { \corescorecore.core_3.serving.cpu.decode.opcode [2], \corescorecore.core_3.serving.cpu.decode.m3 , \corescorecore.core_3.serving.cpu.decode.opcode [0] }; + assign \corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [0] = \corescorecore.core_0.serving.cpu.csr_imm ; + assign \corescorecore.core_0.serving.cpu.decode.opcode [4:3] = { \corescorecore.core_0.serving.cpu.decode.m3 , \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we }; + assign _1083_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [32] }; + assign _1082_[1] = \corescorecore.core_4.serving.arbiter.i_wb_mem_ack ; + assign _1081_[1] = \corescorecore.core_4.serving.cpu.ctrl.en_pc_r ; + assign _1080_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [35] }; + assign _1079_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [36] }; + assign _1078_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [37] }; + assign _1077_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [38] }; + assign _1076_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [33] }; + assign _1075_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [34] }; + assign _1074_[0] = \corescorecore.core_0.serving.cpu.decode.o_rf_rs1_addr [1]; + assign _1073_[2] = \corescorecore.core_0.serving.cpu.bufreg.c_r ; + assign { _1072_[3], _1072_[1:0] } = { \corescorecore.core_0.serving.cpu.decode.opcode [2], _1017_[1:0] }; + assign { _1071_[3], _1071_[1:0] } = { \corescorecore.core_0.serving.cpu.decode.m3 , \corescorecore.core_0.serving.cpu.decode.opcode [0], \corescorecore.core_0.serving.cpu.decode.opcode [1] }; + assign _1070_[1:0] = { \corescorecore.core_0.serving.cpu.state.o_cnt_r [0], \corescorecore.core_0.serving.cpu.state.o_cnt [2] }; + assign _1069_[1:0] = { \corescorecore.axis_mux.current_s_tdata [7], \corescorecore.axis_mux.temp_m_axis_tdata_reg [7] }; + assign _1068_[2:1] = { \corescorecore.axis_mux.arb_inst.grant_encoded [2], \corescorecore.axis_mux.s_axis_tdata [39] }; + assign _1067_[2:0] = { \corescorecore.core_0.serving.rf_ram_if.wgo , \corescorecore.core_0.serving.rf_ram_if.wtrig0 , \corescorecore.core_0.serving.rf_ram_if.wen0_r }; + assign _1066_[2:1] = { \corescorecore.core_0.serving.arbiter.i_wb_mem_ack , _1003_[0] }; + assign _1065_[0] = _1062_[0]; + assign _1064_[1:0] = { _1061_[0], _1061_[1] }; + assign { _1063_[2], _1063_[0] } = { \clkgen.o_rst_core , \corescorecore.axis_mux.arb_inst.mask_reg [4] }; + assign _1059_[3:2] = { \corescorecore.core_4.o_tlast , \corescorecore.axis_mux.arb_inst.grant [4] }; + assign { _1058_[3], _1058_[0] } = { \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_4.serving.cpu.alu.i_en }; + assign { _1057_[3], _1057_[0] } = { \corescorecore.axis_mux.arb_inst.grant_valid , \corescorecore.core_1.o_tvalid }; + assign { _1056_[2], _1056_[0] } = { \corescorecore.core_3.o_tvalid , \corescorecore.core_0.o_tvalid }; + assign { _1055_[3], _1055_[0] } = { \corescorecore.axis_mux.arb_inst.grant_encoded [1], \corescorecore.axis_mux.arb_inst.grant_encoded [2] }; + assign _1054_[2:0] = { _1052_[1], \corescorecore.axis_mux.arb_inst.grant_encoded [1], \corescorecore.axis_mux.arb_inst.grant_encoded [2] }; + assign { _1053_[3:2], _1053_[0] } = { \corescorecore.core_2.o_tlast , \corescorecore.axis_mux.arb_inst.grant [2], \corescorecore.core_2.o_tvalid }; + assign { _1052_[2], _1052_[0] } = { \corescorecore.axis_mux.arb_inst.grant_encoded [1], \corescorecore.axis_mux.arb_inst.grant_encoded [2] }; + assign _1051_[3:1] = { _1006_[0], \corescorecore.core_1.serving.cpu.ctrl.pc_plus_offset_cy_r , _1030_[0] }; + assign _1050_[1:0] = { _1033_[0], _1033_[1] }; + assign { _1048_[3], _1048_[0] } = { \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_3.serving.cpu.alu.i_en }; + assign { _1047_[3], _1047_[0] } = { \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_2.serving.cpu.alu.i_en }; + assign { _1046_[3:2], _1046_[0] } = { \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we , _1018_[3], \corescorecore.core_0.serving.cpu.alu.i_en }; + assign { _1045_[3:2], _1045_[0] } = { \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we , _1024_[1], \corescorecore.core_1.serving.cpu.alu.i_en }; + assign _1044_[2:0] = { \corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [0], \corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_1.serving.ram.wb_en }; + assign { _1043_[3], _1043_[1:0] } = { \clkgen.o_rst_core , \corescorecore.core_4.serving.cpu.ctrl.i_jump , \corescorecore.core_4.serving.cpu.alu.i_cnt_done }; + assign { _1042_[2], _1042_[0] } = { \corescorecore.core_4.serving.cpu.decode.o_mem_half , \corescorecore.core_4.serving.cpu.decode.opcode [0] }; + assign _1041_[3:1] = { \corescorecore.core_4.serving.cpu.alu.i_sh_right , \corescorecore.core_4.serving.cpu.decode.o_mem_word , \corescorecore.core_4.serving.cpu.alu.result_lt }; + assign _1040_[3:1] = { \corescorecore.core_4.serving.cpu.alu.i_rs1 , _0931_, \corescorecore.core_4.serving.cpu.alu.lt_r }; + assign _1039_[3] = \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we ; + assign _1038_[2:0] = { \corescorecore.core_4.serving.cpu.alu.i_cnt_done , \corescorecore.core_4.serving.cpu.decode.imm11_7 [0], \corescorecore.core_4.serving.cpu.decode.imm24_20 [0] }; + assign _1037_[2:0] = { \corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [3], \corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_1.serving.ram.wb_en }; + assign _1036_[1:0] = { \corescorecore.core_4.serving.cpu.decode.m3 , \corescorecore.core_4.serving.cpu.decode.opcode [2] }; + assign _1035_[2:0] = { \corescorecore.core_1.serving.cpu.decode.o_rf_rd_addr [4], \corescorecore.core_1.serving.rf_ram_if.genblk1.wtrig0_r , \corescorecore.core_1.serving.ram.wb_en }; + assign _1034_[3:2] = { _0905_, \corescorecore.core_1.serving.cpu.alu.b_inv_plus_1_cy_r }; + assign _1033_[3] = \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we ; + assign _1032_[2:0] = { \corescorecore.core_1.serving.cpu.alu.i_cnt_done , \corescorecore.core_1.serving.cpu.decode.imm11_7 [0], \corescorecore.core_1.serving.cpu.decode.imm24_20 [0] }; + assign _1031_[1:0] = { \corescorecore.core_1.serving.cpu.state.o_cnt_r [0], \corescorecore.core_1.serving.cpu.state.o_cnt [2] }; + assign _1030_[1] = \corescorecore.core_1.serving.cpu.ctrl.pc_plus_offset_cy_r ; + assign { _1029_[3], _1029_[1:0] } = { \corescorecore.core_1.serving.cpu.ctrl.pc , \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we , \corescorecore.core_1.serving.cpu.decode.m3 }; + assign _1028_[2:0] = { \corescorecore.core_1.serving.cpu.mem_bytecnt [1], \corescorecore.core_1.serving.cpu.state.o_cnt [2], \corescorecore.core_1.serving.cpu.mem_bytecnt [0] }; + assign _1027_[2:0] = { \corescorecore.core_1.serving.rf_ram_if.wgo , \corescorecore.core_1.serving.rf_ram_if.wtrig0 , \corescorecore.core_1.serving.rf_ram_if.wen0_r }; + assign _1026_[1] = \corescorecore.core_1.serving.arbiter.i_wb_mem_ack ; + assign { _1025_[3], _1025_[1:0] } = { _1007_[0], \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31:30] }; + assign _1024_[0] = \corescorecore.core_1.serving.cpu.alu.i_en ; + assign { _1023_[3], _1023_[1:0] } = { \clkgen.o_rst_core , \corescorecore.core_0.serving.cpu.ctrl.i_jump , \corescorecore.core_0.serving.cpu.alu.i_cnt_done }; + assign _1022_[1:0] = { \corescorecore.core_0.serving.cpu.decode.o_mem_half , \corescorecore.core_0.serving.cpu.decode.opcode [0] }; + assign _1021_[1:0] = { \corescorecore.core_0.serving.cpu.decode.m3 , \corescorecore.core_0.serving.cpu.decode.opcode [2] }; + assign _1020_[3:1] = { \corescorecore.core_0.serving.cpu.alu.i_sh_right , \corescorecore.core_0.serving.cpu.decode.o_mem_word , \corescorecore.core_0.serving.cpu.alu.result_lt }; + assign _1019_[3:1] = { \corescorecore.core_0.serving.cpu.alu.i_rs1 , _0878_, \corescorecore.core_0.serving.cpu.alu.lt_r }; + assign _1018_[2:0] = { \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31:30], \corescorecore.core_0.serving.cpu.alu.i_en }; + assign \corescorecore.core_0.serving.cpu.state.o_cnt [4:3] = \corescorecore.core_0.serving.cpu.mem_bytecnt ; + assign _1017_[3] = \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_we ; + assign _1016_[2:0] = { \corescorecore.core_0.serving.cpu.alu.i_cnt_done , \corescorecore.core_0.serving.cpu.decode.imm11_7 [0], \corescorecore.core_0.serving.cpu.decode.imm24_20 [0] }; + assign _1015_[2:1] = { \corescorecore.core_0.serving.rf_ram_if.rgnt , _1005_[2] }; + assign _1014_[1] = \corescorecore.core_0.serving.cpu.state.stage_two_req ; + assign _1013_[0] = \corescorecore.core_0.serving.cpu.state.stage_two_pending ; + assign _1012_[1:0] = { \corescorecore.core_0.serving.cpu.alu.shamt [0], \corescorecore.core_0.serving.cpu.alu.shift.cnt [0] }; + assign { _1010_[3:2], _1010_[0] } = { \corescorecore.core_0.serving.cpu.decode.opcode [2], \corescorecore.core_0.serving.cpu.decode.m3 , \corescorecore.core_0.serving.cpu.decode.opcode [0] }; + assign { _1009_[3], _1009_[1:0] } = { \corescorecore.axis_mux.s_axis_tdata [14], _1008_[3], \corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [5] }; + assign _1008_[2:0] = { \corescorecore.core_1.serving.i_wb_ack , \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31:30] }; + assign _1007_[3:1] = { \corescorecore.core_1.serving.arbiter.i_wb_mem_ack , \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31:30] }; + assign _1006_[1] = \corescorecore.core_1.serving.cpu.ctrl.en_pc_r ; + assign { _1005_[3], _1005_[1:0] } = { \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_dat [23], _1004_[3], \corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [22] }; + assign _1004_[2:0] = { \corescorecore.core_0.serving.i_wb_ack , \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31:30] }; + assign _1003_[3:1] = { \corescorecore.core_0.serving.arbiter.i_wb_mem_ack , \corescorecore.core_0.serving.arbiter.i_wb_cpu_dbus_adr [31:30] }; + assign _1002_[1] = \corescorecore.core_0.serving.cpu.ctrl.en_pc_r ; + assign _0986_[7:0] = \corescorecore.core_4.serving.arbiter.i_wb_mem_rdt [31:24]; + assign _0985_[7:0] = \corescorecore.core_3.serving.arbiter.i_wb_mem_rdt [31:24]; + assign _0984_[7:0] = \corescorecore.core_2.serving.arbiter.i_wb_mem_rdt [31:24]; + assign _0983_[7:0] = \corescorecore.core_1.serving.arbiter.i_wb_mem_rdt [31:24]; + assign _0982_[7:0] = \corescorecore.core_0.serving.arbiter.i_wb_mem_rdt [31:24]; + assign \corescorecore.core_0.serving.ram.waddr [7] = \corescorecore.core_0.serving.ram.raddr [7]; + assign _0958_[3:0] = _0957_[4:1]; + assign _0957_[0] = 1'h0; + assign _0955_[3:0] = _0954_[4:1]; + assign _0954_[0] = 1'h0; + assign _0952_[4:0] = _0951_[5:1]; + assign \corescorecore.core_0.serving.rf_ram_if.rcnt [4:3] = \corescorecore.core_0.serving.raddr [1:0]; + assign \corescorecore.core_0.serving.rf_ram_if.rdata0 [0] = \corescorecore.core_0.serving.cpu.alu.i_rs1 ; + assign _0951_[0] = 1'h0; + assign \corescorecore.core_0.serving.rf_ram_if.wcnt [4:3] = \corescorecore.core_0.serving.rf_ram_if.o_waddr [1:0]; + assign _0948_[1:0] = _0947_[2:1]; + assign _0947_[0] = 1'h0; + assign _0945_[3:0] = _0944_[4:1]; + assign _0944_[0] = 1'h0; + assign _0942_[3:0] = _0941_[4:1]; + assign _0941_[0] = 1'h0; + assign _0940_[0] = _0939_[0]; + assign _0939_[1] = \corescorecore.core_2.serving.ram.bsel [1]; + assign _0937_[1:0] = _0936_[2:1]; + assign _0936_[0] = 1'h0; + assign _0935_[1:0] = _0934_[2:1]; + assign _0934_[0] = 1'h0; + assign _0933_[1:0] = _0932_[2:1]; + assign _0932_[0] = 1'h0; + assign _0929_[4:0] = _0928_[5:1]; + assign _0928_[0] = 1'h0; + assign _0926_[4:0] = _0925_[5:1]; + assign _0925_[0] = 1'h0; + assign _0922_[3:0] = _0921_[4:1]; + assign _0921_[0] = 1'h0; + assign _0919_[3:0] = _0918_[4:1]; + assign _0918_[0] = 1'h0; + assign _0917_[0] = _0916_[0]; + assign _0916_[1] = \corescorecore.core_1.serving.ram.bsel [1]; + assign _0914_[1:0] = _0913_[2:1]; + assign _0913_[0] = 1'h0; + assign _0912_[1:0] = _0911_[2:1]; + assign _0911_[0] = 1'h0; + assign _0910_[0] = _0909_[0]; + assign _0909_[1] = \corescorecore.core_3.serving.ram.bsel [1]; + assign _0907_[4:0] = _0906_[5:1]; + assign _0906_[0] = 1'h0; + assign \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [1:0] = 2'h0; + assign \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_dat [8:0] = { \corescorecore.core_1.o_tlast , \corescorecore.axis_mux.s_axis_tdata [15:8] }; + assign \corescorecore.core_1.serving.arbiter.i_wb_cpu_ibus_adr [0] = \corescorecore.core_1.serving.cpu.ctrl.pc ; + assign _0904_[1:0] = _0903_[2:1]; + assign _0903_[0] = 1'h0; + assign _0901_[3:0] = _0900_[4:1]; + assign _0900_[0] = 1'h0; + assign _0898_[3:0] = _0897_[4:1]; + assign _0897_[0] = 1'h0; + assign _0896_[0] = _0895_[0]; + assign _0895_[1] = \corescorecore.core_0.serving.ram.bsel [1]; + assign _0893_[1:0] = _0892_[2:1]; + assign _0892_[0] = 1'h0; + assign _0891_[1:0] = _0890_[2:1]; + assign _0890_[0] = 1'h0; + assign _0888_[1:0] = _0887_[2:1]; + assign _0887_[0] = 1'h0; + assign { \corescorecore.core_1.serving.cpu.bufreg.data [31:2], \corescorecore.core_1.serving.cpu.bufreg.data [0] } = { \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_adr [31:2], \corescorecore.core_1.serving.cpu.alu.i_buf }; + assign _0886_[0] = _0885_[0]; + assign _0885_[1] = \corescorecore.core_4.serving.ram.bsel [1]; + assign _0883_[3:0] = _0882_[4:1]; + assign \corescorecore.core_1.serving.cpu.bufreg.o_lsb [1] = \corescorecore.core_1.serving.cpu.state.i_ctrl_misalign ; + assign _0882_[0] = 1'h0; + assign _0880_[4:0] = _0879_[5:1]; + assign _0879_[0] = 1'h0; + assign _0876_[3:0] = _0875_[4:1]; + assign _0875_[0] = 1'h0; + assign _0873_[8:0] = _0872_[9:1]; + assign _0872_[0] = 1'h1; + assign _0870_[2:0] = _0869_[3:1]; + assign _0869_[0] = 1'h0; + assign _0867_[2:0] = _0866_[3:1]; + assign _0866_[0] = 1'h0; + assign \corescorecore.core_1.serving.cpu.decode.o_rf_rs1_addr [0] = \corescorecore.core_1.serving.cpu.csr_imm ; + assign \corescorecore.core_1.serving.cpu.decode.opcode [4:3] = { \corescorecore.core_1.serving.cpu.decode.m3 , \corescorecore.core_1.serving.arbiter.i_wb_cpu_dbus_we }; + assign \corescorecore.core_1.serving.cpu.state.o_cnt [4:3] = \corescorecore.core_1.serving.cpu.mem_bytecnt ; + assign \corescorecore.core_1.serving.ram.waddr [7] = \corescorecore.core_1.serving.ram.raddr [7]; + assign \corescorecore.core_1.serving.rf_ram_if.rcnt [4:3] = \corescorecore.core_1.serving.raddr [1:0]; + assign \corescorecore.core_1.serving.rf_ram_if.rdata0 [0] = \corescorecore.core_1.serving.cpu.alu.i_rs1 ; + assign \corescorecore.core_1.serving.rf_ram_if.wcnt [4:3] = \corescorecore.core_1.serving.rf_ram_if.o_waddr [1:0]; + assign \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [1:0] = 2'h0; + assign \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_dat [8:0] = { \corescorecore.core_2.o_tlast , \corescorecore.axis_mux.s_axis_tdata [23:16] }; + assign \corescorecore.core_2.serving.arbiter.i_wb_cpu_ibus_adr [0] = \corescorecore.core_2.serving.cpu.ctrl.pc ; + assign { \corescorecore.core_2.serving.cpu.bufreg.data [31:2], \corescorecore.core_2.serving.cpu.bufreg.data [0] } = { \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_adr [31:2], \corescorecore.core_2.serving.cpu.alu.i_buf }; + assign \corescorecore.core_2.serving.cpu.bufreg.o_lsb [1] = \corescorecore.core_2.serving.cpu.state.i_ctrl_misalign ; + assign \corescorecore.core_2.serving.cpu.decode.o_rf_rs1_addr [0] = \corescorecore.core_2.serving.cpu.csr_imm ; + assign \corescorecore.core_2.serving.cpu.decode.opcode [4:3] = { \corescorecore.core_2.serving.cpu.decode.m3 , \corescorecore.core_2.serving.arbiter.i_wb_cpu_dbus_we }; + assign \corescorecore.core_2.serving.cpu.state.o_cnt [4:3] = \corescorecore.core_2.serving.cpu.mem_bytecnt ; + assign \corescorecore.core_2.serving.ram.waddr [7] = \corescorecore.core_2.serving.ram.raddr [7]; + assign \corescorecore.core_2.serving.rf_ram_if.rcnt [4:3] = \corescorecore.core_2.serving.raddr [1:0]; + assign \corescorecore.core_2.serving.rf_ram_if.rdata0 [0] = \corescorecore.core_2.serving.cpu.alu.i_rs1 ; + assign \corescorecore.core_2.serving.rf_ram_if.wcnt [4:3] = \corescorecore.core_2.serving.rf_ram_if.o_waddr [1:0]; + assign \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [1:0] = 2'h0; + assign \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_dat [8:0] = { \corescorecore.core_3.o_tlast , \corescorecore.axis_mux.s_axis_tdata [31:24] }; + assign \corescorecore.core_3.serving.arbiter.i_wb_cpu_ibus_adr [0] = \corescorecore.core_3.serving.cpu.ctrl.pc ; + assign { \corescorecore.core_3.serving.cpu.bufreg.data [31:2], \corescorecore.core_3.serving.cpu.bufreg.data [0] } = { \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_adr [31:2], \corescorecore.core_3.serving.cpu.alu.i_buf }; + assign \corescorecore.core_3.serving.cpu.bufreg.o_lsb [1] = \corescorecore.core_3.serving.cpu.state.i_ctrl_misalign ; + assign \corescorecore.core_3.serving.cpu.decode.o_rf_rs1_addr [0] = \corescorecore.core_3.serving.cpu.csr_imm ; + assign \corescorecore.core_3.serving.cpu.decode.opcode [4:3] = { \corescorecore.core_3.serving.cpu.decode.m3 , \corescorecore.core_3.serving.arbiter.i_wb_cpu_dbus_we }; + assign \corescorecore.core_3.serving.cpu.state.o_cnt [4:3] = \corescorecore.core_3.serving.cpu.mem_bytecnt ; + assign \corescorecore.core_3.serving.ram.waddr [7] = \corescorecore.core_3.serving.ram.raddr [7]; + assign \corescorecore.core_3.serving.rf_ram_if.rcnt [4:3] = \corescorecore.core_3.serving.raddr [1:0]; + assign \corescorecore.core_3.serving.rf_ram_if.rdata0 [0] = \corescorecore.core_3.serving.cpu.alu.i_rs1 ; + assign \corescorecore.core_3.serving.rf_ram_if.wcnt [4:3] = \corescorecore.core_3.serving.rf_ram_if.o_waddr [1:0]; + assign \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [1:0] = 2'h0; + assign \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_dat [8:0] = { \corescorecore.core_4.o_tlast , \corescorecore.axis_mux.s_axis_tdata [39:32] }; + assign \corescorecore.core_4.serving.arbiter.i_wb_cpu_ibus_adr [0] = \corescorecore.core_4.serving.cpu.ctrl.pc ; + assign { \corescorecore.core_4.serving.cpu.bufreg.data [31:2], \corescorecore.core_4.serving.cpu.bufreg.data [0] } = { \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_adr [31:2], \corescorecore.core_4.serving.cpu.alu.i_buf }; + assign \corescorecore.core_4.serving.cpu.bufreg.o_lsb [1] = \corescorecore.core_4.serving.cpu.state.i_ctrl_misalign ; + assign \corescorecore.core_4.serving.cpu.decode.o_rf_rs1_addr [0] = \corescorecore.core_4.serving.cpu.csr_imm ; + assign \corescorecore.core_4.serving.cpu.decode.opcode [4:3] = { \corescorecore.core_4.serving.cpu.decode.m3 , \corescorecore.core_4.serving.arbiter.i_wb_cpu_dbus_we }; + assign \corescorecore.core_4.serving.cpu.state.o_cnt [4:3] = \corescorecore.core_4.serving.cpu.mem_bytecnt ; + assign \corescorecore.core_4.serving.ram.waddr [7] = \corescorecore.core_4.serving.ram.raddr [7]; + assign \corescorecore.core_4.serving.rf_ram_if.rcnt [4:3] = \corescorecore.core_4.serving.raddr [1:0]; + assign \corescorecore.core_4.serving.rf_ram_if.rdata0 [0] = \corescorecore.core_4.serving.cpu.alu.i_rs1 ; + assign \corescorecore.core_4.serving.rf_ram_if.wcnt [4:3] = \corescorecore.core_4.serving.rf_ram_if.o_waddr [1:0]; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/edalize_yosys_procs.tcl b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/edalize_yosys_procs.tcl new file mode 100644 index 0000000000000000000000000000000000000000..30e01bc97e25ceabcdb96f2a5a5b7aa16ad24aae --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/edalize_yosys_procs.tcl @@ -0,0 +1,51 @@ +proc read_files {} { +read_verilog {src/serv_1.0.2/rtl/serv_shift.v} +read_verilog {src/serv_1.0.2/rtl/serv_bufreg.v} +read_verilog {src/serv_1.0.2/rtl/serv_alu.v} +read_verilog {src/serv_1.0.2/rtl/serv_csr.v} +read_verilog {src/serv_1.0.2/rtl/serv_ctrl.v} +read_verilog {src/serv_1.0.2/rtl/serv_decode.v} +read_verilog {src/serv_1.0.2/rtl/serv_mem_if.v} +read_verilog {src/serv_1.0.2/rtl/serv_rf_if.v} +read_verilog {src/serv_1.0.2/rtl/serv_rf_ram_if.v} +read_verilog {src/serv_1.0.2/rtl/serv_rf_ram.v} +read_verilog {src/serv_1.0.2/rtl/serv_state.v} +read_verilog {src/serv_1.0.2/rtl/serv_top.v} +read_verilog {src/serv_1.0.2/rtl/serv_rf_top.v} +read_verilog {src/verilog-axis_0-r3/rtl/arbiter.v} +read_verilog {src/verilog-axis_0-r3/rtl/priority_encoder.v} +read_verilog {src/verilog-axis_0-r3/rtl/axis_arb_mux.v} +read_verilog {src/verilog-axis_0-r3/rtl/axis_async_fifo.v} +read_verilog {src/serving_1.0.2/serving/serving_arbiter.v} +read_verilog {src/serving_1.0.2/serving/serving_mux.v} +read_verilog {src/serving_1.0.2/serving/serving_ram.v} +read_verilog {src/serving_1.0.2/serving/serving.v} +read_verilog {src/corescore_0/rtl/wb2axis.v} +read_verilog {src/corescore_0/rtl/base.v} +read_verilog {src/corescore_0/rtl/emitter_uart.v} +read_verilog {src/corescore_0/rtl/cc_gatemate_clock_gen.v} +read_verilog {src/corescore_0/rtl/corescore_gatemate.v} +read_verilog {src/corescore-corescorecore_0/corescorecore.v} +} + +proc set_defines {} { +set defines {{CCGM 1}} + +foreach d ${defines} { + set key [lindex $d 0] + set val [lindex $d 1] + verilog_defines "-D$key=$val" +}} + +proc set_incdirs {} { +verilog_defaults -add -Isrc/serv_1.0.2/rtl} + +proc set_params {} { +} + +proc synth {top} { +synth_gatemate -nomx8 -top $top +} + +set top corescore_gatemate +set name corescore_0 diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/generator_cache/corescore-corescorecore_0-74191c27a08ab212740fbebfd133ec752b0d1793bbf6f7c086d8a99a1c975264/corescorecore.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/generator_cache/corescore-corescorecore_0-74191c27a08ab212740fbebfd133ec752b0d1793bbf6f7c086d8a99a1c975264/corescorecore.v new file mode 100644 index 0000000000000000000000000000000000000000..68cd408cdc26b360000936ab379cd887f85f6b9c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/generator_cache/corescore-corescorecore_0-74191c27a08ab212740fbebfd133ec752b0d1793bbf6f7c086d8a99a1c975264/corescorecore.v @@ -0,0 +1,105 @@ +// THIS FILE IS AUTOGENERATED BY corescorecore_gen +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module corescorecore + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + +wire [39:0] tdata; +wire [4:0] tlast; +wire [4:0] tvalid; +wire [4:0] tready; + +base + #(.memfile ("core_0.hex"), + .memsize (256)) + core_0 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[7:0]), + .o_tlast (tlast[0]), + .o_tvalid (tvalid[0]), + .i_tready (tready[0])); + +base + #(.memfile ("core_1.hex"), + .memsize (256)) + core_1 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[15:8]), + .o_tlast (tlast[1]), + .o_tvalid (tvalid[1]), + .i_tready (tready[1])); + +base + #(.memfile ("core_2.hex"), + .memsize (256)) + core_2 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[23:16]), + .o_tlast (tlast[2]), + .o_tvalid (tvalid[2]), + .i_tready (tready[2])); + +base + #(.memfile ("core_3.hex"), + .memsize (256)) + core_3 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[31:24]), + .o_tlast (tlast[3]), + .o_tvalid (tvalid[3]), + .i_tready (tready[3])); + +base + #(.memfile ("core_4.hex"), + .memsize (256)) + core_4 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[39:32]), + .o_tlast (tlast[4]), + .o_tvalid (tvalid[4]), + .i_tready (tready[4])); + +axis_arb_mux + #(.S_COUNT (5), + .DATA_WIDTH (8), + .KEEP_ENABLE (0), + .KEEP_WIDTH (1), + .ID_ENABLE (0), + .ID_WIDTH (8), + .DEST_ENABLE (0), + .DEST_WIDTH (8), + .USER_ENABLE (0), + .USER_WIDTH (1), + .ARB_TYPE ("ROUND_ROBIN"), + .LSB_PRIORITY ("HIGH")) + axis_mux + (.clk (i_clk), + .rst (i_rst), + .s_axis_tdata (tdata), + .s_axis_tkeep (5'd0), + .s_axis_tvalid (tvalid), + .s_axis_tready (tready), + .s_axis_tlast (tlast), + .s_axis_tid (40'd0), + .s_axis_tdest (40'd0), + .s_axis_tuser (5'd0), + .m_axis_tdata (o_tdata), + .m_axis_tkeep (), + .m_axis_tvalid (o_tvalid), + .m_axis_tready (i_tready), + .m_axis_tlast (o_tlast), + .m_axis_tid (), + .m_axis_tdest (), + .m_axis_tuser ()); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/generator_cache/corescore-corescorecore_0-74191c27a08ab212740fbebfd133ec752b0d1793bbf6f7c086d8a99a1c975264/corescorecore_input.yml b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/generator_cache/corescore-corescorecore_0-74191c27a08ab212740fbebfd133ec752b0d1793bbf6f7c086d8a99a1c975264/corescorecore_input.yml new file mode 100644 index 0000000000000000000000000000000000000000..61b5226da47a33db348801927f2eac898d34c349 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/generator_cache/corescore-corescorecore_0-74191c27a08ab212740fbebfd133ec752b0d1793bbf6f7c086d8a99a1c975264/corescorecore_input.yml @@ -0,0 +1,5 @@ +files_root: /home/tarik/0.git-repo/openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore +gapi: '1.0' +parameters: + count: 5 +vlnv: ::corescore-corescorecore:0 diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut3.txt b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut3.txt new file mode 100644 index 0000000000000000000000000000000000000000..b761bf4584fe2b01ac3239034b1b413f12f8199f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut3.txt @@ -0,0 +1,29 @@ +0001 11 abc +0007 2 c/AB\ +000B 6 c/aB\ +000D 3 c/Ab\ +000E 13 c/ab\ +0010 23 abC +001C 5 BC?0:1:a:0 +001F 3 (ab)+c +002C 1 BC?0:1:A:0 +0035 16 c?b:a +003A 5 c?b:A +003E 5 BC?A:1:1:0 +0040 41 aBC +004F 5 (aB)+c +0060 10 C(A^B) +007F 4 /AB\+c +0080 11 ABC +0096 10 A^B^C +00A3 1 C?b:A +00AC 25 c?A:B +00B0 3 C/aB\ +00C5 20 C?a:B +00CA 233 C?A:B +00D0 1 C/Ab\ +00E8 5 AB?0:C:C:1 +00F4 12 (aB)+C +00F8 1 (AB)+C +00FE 4 /ab\+C + Gesamt: 479 DS4: 4 diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut4.txt b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut4.txt new file mode 100644 index 0000000000000000000000000000000000000000..e54f267ba5c861b074a84a1a82f1ec5812e66d39 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut4.txt @@ -0,0 +1,66 @@ +0001 8 abcd +000D 6 cd/Ab\ +000E 5 cd/ab\ +001F 3 ((ab)+c)d +007F 5 ((/AB\)+c)d +00EF 26 ((/ab\)+c)d +00F4 7 ((aB)+C)d +00F8 5 ((AB)+C)d +0100 17 abcD +030A 15 DC?A:b:0:0 +0777 6 /AB\(d+c) +0A0C 9 DC?B:A:0:0 +0B00 5 cD/aB\ +0BBB 1 /aB\(d+c) +0C0A 232 DC?A:B:0:0 +0EEE 5 /ab\(d+c) +0FBB 5 D?/aB\:c +1000 3 abCD +1F00 10 ((ab)+c)D +2FFF 1 (Ab)+c+d +3335 5 DC?a:b:b:b +3500 25 D(c?b:a) +4000 19 aBCD +41BE 5 AD?B^C:1:b^C:0 +4F00 5 ((aB)+c)D +6000 5 CD(A^B) +6900 5 D(A^B^c) +7077 1 /AB\(d+C) +7D82 5 AD?0:b^C:1:B^C +7F00 6 ((/AB\)+c)D +8000 18 ABCD +8F88 5 (AB)+(cD) +9000 9 CD(a^B) +9009 9 (a^B)(D^c) +ACC5 5 DC?a:B:B:A +B00B 2 /aB\/D^C\ +B0BB 1 /aB\(d+C) +B0FF 5 (C/aB\)+d +BF00 5 ((/aB\)+c)D +CA00 6 D(C?A:B) +CAAC 5 DC?B:A:A:B +CACC 10 DC?B:A:B:B +CAFF 5 (C?A:B)+d +CEC0 1 BD?0:C:Ac:1 +CFA0 5 DC?0:1:A:B +D000 5 CD/Ab\ +D400 5 D(AB?C:0:1:C) +E800 15 D(AB?0:C:C:1) +EB00 5 AD?0:0:b^C:1 +F011 5 D?ab:C +F044 40 D?aB:C +F2FF 4 (Ab)+C+d +F400 2 ((aB)+C)D +F444 1 (aB)+(CD) +F800 5 ((AB)+C)D +F888 155 (AB)+(CD) +FAFC 1 DC?B:A:1:1 +FB0F 5 DC?1:/aB\:0:1 +FC0A 5 DC?A:B:0:1 +FCFA 4 DC?A:B:1:1 +FF0B 5 (c/aB\)+D +FF0E 5 (c/ab\)+D +FF80 5 (ABC)+D +FFE0 10 (C/ab\)+D +FFF4 5 (aB)+C+D + Gesamt: 833 DS4: 17 diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut_report.txt b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut_report.txt new file mode 100644 index 0000000000000000000000000000000000000000..0e9658f43bf9fc9cef440333e4ceb247db98191e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/lut_report.txt @@ -0,0 +1,1608 @@ + 1 LUT2 B /aB\ + 2 LUT4 0001 abcd + 3 LUT3 40 aBC + 4 LUT4 4000 aBCD + 5 LUT4 0100 abcD + 6 LUT3 0E c/ab\ + 7 LUT3 40 aBC + 8 LUT4 4000 aBCD + 9 LUT4 0100 abcD + 10 LUT3 0E c/ab\ + 11 LUT3 40 aBC + 12 LUT4 4000 aBCD + 13 LUT4 0100 abcD + 14 LUT3 0E c/ab\ + 15 LUT3 40 aBC + 16 LUT4 4000 aBCD + 17 LUT4 0100 abcD + 18 LUT3 0E c/ab\ + 19 LUT2 8 AB + 20 LUT2 4 aB + 21 LUT4 4000 aBCD + 22 LUT4 0100 abcD + 23 LUT3 0E c/ab\ + 24 LUT3 CA C?A:B + 25 LUT3 1F (ab)+c + 26 LUT3 10 abC + 27 LUT2 4 aB + 28 LUT2 4 aB + 29 LUT4 B0BB /aB\(d+C) + 30 LUT4 0C0A DC?A:B:0:0 + 31 LUT2 4 aB + 32 LUT4 0C0A DC?A:B:0:0 + 33 LUT2 4 aB + 34 LUT4 0C0A DC?A:B:0:0 + 35 LUT4 0C0A DC?A:B:0:0 + 36 LUT4 0C0A DC?A:B:0:0 + 37 LUT4 0C0A DC?A:B:0:0 + 38 LUT2 4 aB + 39 LUT4 0C0A DC?A:B:0:0 + 40 LUT4 0C0A DC?A:B:0:0 + 41 LUT4 0C0A DC?A:B:0:0 + 42 LUT4 0C0A DC?A:B:0:0 + 43 LUT4 0C0A DC?A:B:0:0 + 44 LUT4 0C0A DC?A:B:0:0 + 45 LUT4 0C0A DC?A:B:0:0 + 46 LUT4 0C0A DC?A:B:0:0 + 47 LUT4 0C0A DC?A:B:0:0 + 48 LUT4 0C0A DC?A:B:0:0 + 49 LUT4 0C0A DC?A:B:0:0 + 50 LUT4 0A0C DC?B:A:0:0 + 51 LUT4 0C0A DC?A:B:0:0 + 52 LUT4 0C0A DC?A:B:0:0 + 53 LUT4 0C0A DC?A:B:0:0 + 54 LUT2 8 AB + 55 LUT2 4 aB + 56 LUT4 FFF4 (aB)+C+D + 57 LUT4 0C0A DC?A:B:0:0 + 58 LUT4 0C0A DC?A:B:0:0 + 59 LUT4 0C0A DC?A:B:0:0 + 60 LUT4 0C0A DC?A:B:0:0 + 61 LUT4 0C0A DC?A:B:0:0 + 62 LUT4 0C0A DC?A:B:0:0 + 63 LUT4 0C0A DC?A:B:0:0 + 64 LUT4 0C0A DC?A:B:0:0 + 65 LUT4 0C0A DC?A:B:0:0 + 66 LUT4 0C0A DC?A:B:0:0 + 67 LUT4 0C0A DC?A:B:0:0 + 68 LUT4 0C0A DC?A:B:0:0 + 69 LUT4 0C0A DC?A:B:0:0 + 70 LUT4 0C0A DC?A:B:0:0 + 71 LUT4 0C0A DC?A:B:0:0 + 72 LUT4 0C0A DC?A:B:0:0 + 73 LUT4 0C0A DC?A:B:0:0 + 74 LUT2 4 aB + 75 LUT2 4 aB + 76 LUT2 4 aB + 77 LUT2 4 aB + 78 LUT2 4 aB + 79 LUT2 4 aB + 80 LUT4 4000 aBCD + 81 LUT2 4 aB + 82 LUT3 40 aBC + 83 LUT3 80 ABC + 84 LUT2 8 AB + 85 LUT2 4 aB + 86 LUT2 4 aB + 87 LUT2 4 aB + 88 LUT2 4 aB + 89 LUT2 4 aB + 90 LUT4 F2FF (Ab)+C+d + 91 LUT3 0D c/Ab\ + 92 LUT3 40 aBC + 93 LUT2 1 ab + 94 LUT2 8 AB + 95 LUT3 10 abC + 96 LUT2 4 aB + 97 LUT4 B00B /aB\/D^C\ + 98 LUT4 FB0F DC?1:/aB\:0:1 + 99 LUT2 4 aB + 100 LUT3 01 abc + 101 LUT3 0E c/ab\ + 102 LUT2 4 aB + 103 LUT4 FCFA DC?A:B:1:1 + 104 LUT4 0A0C DC?B:A:0:0 + 105 LUT4 0EEE /ab\(d+c) + 106 LUT4 8000 ABCD + 107 LUT4 0C0A DC?A:B:0:0 + 108 LUT4 0C0A DC?A:B:0:0 + 109 LUT4 0C0A DC?A:B:0:0 + 110 LUT4 0A0C DC?B:A:0:0 + 111 LUT4 0C0A DC?A:B:0:0 + 112 LUT4 0C0A DC?A:B:0:0 + 113 LUT4 0C0A DC?A:B:0:0 + 114 LUT4 0C0A DC?A:B:0:0 + 115 LUT4 030A DC?A:b:0:0 + 116 LUT2 4 aB + 117 LUT3 10 abC + 118 LUT4 0C0A DC?A:B:0:0 + 119 LUT4 0C0A DC?A:B:0:0 + 120 LUT2 4 aB + 121 LUT2 8 AB + 122 LUT2 4 aB + 123 LUT4 FFF4 (aB)+C+D + 124 LUT4 0C0A DC?A:B:0:0 + 125 LUT4 0C0A DC?A:B:0:0 + 126 LUT4 0C0A DC?A:B:0:0 + 127 LUT4 0C0A DC?A:B:0:0 + 128 LUT4 0C0A DC?A:B:0:0 + 129 LUT4 0C0A DC?A:B:0:0 + 130 LUT4 0C0A DC?A:B:0:0 + 131 LUT4 0C0A DC?A:B:0:0 + 132 LUT4 0C0A DC?A:B:0:0 + 133 LUT4 0C0A DC?A:B:0:0 + 134 LUT4 0C0A DC?A:B:0:0 + 135 LUT4 0C0A DC?A:B:0:0 + 136 LUT4 0C0A DC?A:B:0:0 + 137 LUT2 1 ab + 138 LUT4 0100 abcD + 139 LUT4 1000 abCD + 140 LUT4 7F00 ((/AB\)+c)D + 141 LUT3 10 abC + 142 LUT2 8 AB + 143 LUT4 8000 ABCD + 144 LUT3 40 aBC + 145 LUT3 40 aBC + 146 LUT4 8000 ABCD + 147 LUT3 40 aBC + 148 LUT4 0777 /AB\(d+c) + 149 LUT4 4000 aBCD + 150 LUT2 8 AB + 151 LUT4 1000 abCD + 152 LUT2 8 AB + 153 LUT4 0C0A DC?A:B:0:0 + 154 LUT4 0C0A DC?A:B:0:0 + 155 LUT3 07 c/AB\ + 156 LUT3 07 c/AB\ + 157 LUT4 0C0A DC?A:B:0:0 + 158 LUT4 0C0A DC?A:B:0:0 + 159 LUT4 0C0A DC?A:B:0:0 + 160 LUT4 0C0A DC?A:B:0:0 + 161 LUT4 0C0A DC?A:B:0:0 + 162 LUT4 0C0A DC?A:B:0:0 + 163 LUT4 0C0A DC?A:B:0:0 + 164 LUT4 0C0A DC?A:B:0:0 + 165 LUT4 0C0A DC?A:B:0:0 + 166 LUT4 0C0A DC?A:B:0:0 + 167 LUT4 0C0A DC?A:B:0:0 + 168 LUT4 0C0A DC?A:B:0:0 + 169 LUT4 0C0A DC?A:B:0:0 + 170 LUT4 0C0A DC?A:B:0:0 + 171 LUT4 0C0A DC?A:B:0:0 + 172 LUT2 4 aB + 173 LUT2 4 aB + 174 LUT4 030A DC?A:b:0:0 + 175 LUT3 35 c?b:a + 176 LUT3 60 C(A^B) + 177 LUT2 6 A^B + 178 LUT4 1F00 ((ab)+c)D + 179 LUT3 3E BC?A:1:1:0 + 180 LUT4 FFE0 (C/ab\)+D + 181 LUT4 0C0A DC?A:B:0:0 + 182 LUT4 0100 abcD + 183 LUT2 4 aB + 184 LUT3 40 aBC + 185 LUT4 F800 ((AB)+C)D + 186 LUT2 8 AB + 187 LUT3 96 A^B^C + 188 LUT3 40 aBC + 189 LUT2 1 ab + 190 LUT2 4 aB + 191 LUT2 4 aB + 192 LUT2 4 aB + 193 LUT2 4 aB + 194 LUT4 7F00 ((/AB\)+c)D + 195 LUT3 0E c/ab\ + 196 LUT4 0100 abcD + 197 LUT3 40 aBC + 198 LUT4 CAFF (C?A:B)+d + 199 LUT2 4 aB + 200 LUT2 4 aB + 201 LUT2 4 aB + 202 LUT2 8 AB + 203 LUT3 10 abC + 204 LUT2 4 aB + 205 LUT2 8 AB + 206 LUT2 4 aB + 207 LUT2 4 aB + 208 LUT4 0A0C DC?B:A:0:0 + 209 LUT4 0C0A DC?A:B:0:0 + 210 LUT4 0C0A DC?A:B:0:0 + 211 LUT4 0C0A DC?A:B:0:0 + 212 LUT4 0EEE /ab\(d+c) + 213 LUT4 8000 ABCD + 214 LUT2 4 aB + 215 LUT2 4 aB + 216 LUT2 4 aB + 217 LUT2 4 aB + 218 LUT2 8 AB + 219 LUT2 4 aB + 220 LUT2 4 aB + 221 LUT4 0A0C DC?B:A:0:0 + 222 LUT4 F2FF (Ab)+C+d + 223 LUT4 001F ((ab)+c)d + 224 LUT4 0100 abcD + 225 LUT2 8 AB + 226 LUT3 10 abC + 227 LUT2 4 aB + 228 LUT4 9009 (a^B)(D^c) + 229 LUT4 FB0F DC?1:/aB\:0:1 + 230 LUT2 4 aB + 231 LUT3 01 abc + 232 LUT3 0E c/ab\ + 233 LUT2 4 aB + 234 LUT2 1 ab + 235 LUT2 4 aB + 236 LUT2 1 ab + 237 LUT4 0C0A DC?A:B:0:0 + 238 LUT4 0C0A DC?A:B:0:0 + 239 LUT4 FCFA DC?A:B:1:1 + 240 LUT4 0C0A DC?A:B:0:0 + 241 LUT4 0C0A DC?A:B:0:0 + 242 LUT4 0C0A DC?A:B:0:0 + 243 LUT4 0C0A DC?A:B:0:0 + 244 LUT4 0C0A DC?A:B:0:0 + 245 LUT4 0C0A DC?A:B:0:0 + 246 LUT4 0C0A DC?A:B:0:0 + 247 LUT4 030A DC?A:b:0:0 + 248 LUT3 35 c?b:a + 249 LUT3 60 C(A^B) + 250 LUT2 6 A^B + 251 LUT4 1F00 ((ab)+c)D + 252 LUT3 3E BC?A:1:1:0 + 253 LUT4 FFE0 (C/ab\)+D + 254 LUT4 0C0A DC?A:B:0:0 + 255 LUT4 0100 abcD + 256 LUT2 4 aB + 257 LUT3 40 aBC + 258 LUT4 F800 ((AB)+C)D + 259 LUT2 8 AB + 260 LUT3 96 A^B^C + 261 LUT3 40 aBC + 262 LUT2 1 ab + 263 LUT2 4 aB + 264 LUT2 4 aB + 265 LUT2 4 aB + 266 LUT3 40 aBC + 267 LUT3 40 aBC + 268 LUT2 4 aB + 269 LUT2 8 AB + 270 LUT2 4 aB + 271 LUT2 4 aB + 272 LUT2 8 AB + 273 LUT3 10 abC + 274 LUT2 4 aB + 275 LUT2 8 AB + 276 LUT2 4 aB + 277 LUT2 4 aB + 278 LUT2 4 aB + 279 LUT2 4 aB + 280 LUT2 4 aB + 281 LUT2 4 aB + 282 LUT4 0A0C DC?B:A:0:0 + 283 LUT4 0C0A DC?A:B:0:0 + 284 LUT4 0C0A DC?A:B:0:0 + 285 LUT2 1 ab + 286 LUT4 7077 /AB\(d+C) + 287 LUT3 10 abC + 288 LUT3 10 abC + 289 LUT3 FE /ab\+C + 290 LUT3 10 abC + 291 LUT3 FE /ab\+C + 292 LUT3 10 abC + 293 LUT3 10 abC + 294 LUT3 FE /ab\+C + 295 LUT2 4 aB + 296 LUT2 4 aB + 297 LUT2 4 aB + 298 LUT2 4 aB + 299 LUT4 030A DC?A:b:0:0 + 300 LUT2 4 aB + 301 LUT4 001F ((ab)+c)d + 302 LUT4 0100 abcD + 303 LUT2 8 AB + 304 LUT3 10 abC + 305 LUT2 4 aB + 306 LUT3 0D c/Ab\ + 307 LUT4 FB0F DC?1:/aB\:0:1 + 308 LUT2 4 aB + 309 LUT3 01 abc + 310 LUT3 10 abC + 311 LUT4 0C0A DC?A:B:0:0 + 312 LUT4 0C0A DC?A:B:0:0 + 313 LUT4 0C0A DC?A:B:0:0 + 314 LUT4 0C0A DC?A:B:0:0 + 315 LUT4 0C0A DC?A:B:0:0 + 316 LUT4 0C0A DC?A:B:0:0 + 317 LUT3 F4 (aB)+C + 318 LUT2 B /aB\ + 319 LUT3 01 abc + 320 LUT4 00F8 ((AB)+C)d + 321 LUT4 F400 ((aB)+C)D + 322 LUT4 0C0A DC?A:B:0:0 + 323 LUT4 0C0A DC?A:B:0:0 + 324 LUT4 0C0A DC?A:B:0:0 + 325 LUT4 0C0A DC?A:B:0:0 + 326 LUT4 FFF4 (aB)+C+D + 327 LUT4 0C0A DC?A:B:0:0 + 328 LUT4 0C0A DC?A:B:0:0 + 329 LUT4 FCFA DC?A:B:1:1 + 330 LUT4 0A0C DC?B:A:0:0 + 331 LUT4 0C0A DC?A:B:0:0 + 332 LUT4 0C0A DC?A:B:0:0 + 333 LUT4 030A DC?A:b:0:0 + 334 LUT2 4 aB + 335 LUT4 F2FF (Ab)+C+d + 336 LUT3 0D c/Ab\ + 337 LUT3 40 aBC + 338 LUT2 1 ab + 339 LUT4 9009 (a^B)(D^c) + 340 LUT2 8 AB + 341 LUT3 10 abC + 342 LUT2 4 aB + 343 LUT4 FB0F DC?1:/aB\:0:1 + 344 LUT2 4 aB + 345 LUT3 01 abc + 346 LUT3 10 abC + 347 LUT3 0E c/ab\ + 348 LUT2 4 aB + 349 LUT4 00F4 ((aB)+C)d + 350 LUT4 EB00 AD?0:0:b^C:1 + 351 LUT4 3335 DC?a:b:b:b + 352 LUT4 ACC5 DC?a:B:B:A + 353 LUT4 F011 D?ab:C + 354 LUT3 35 c?b:a + 355 LUT4 1F00 ((ab)+c)D + 356 LUT3 60 C(A^B) + 357 LUT3 40 aBC + 358 LUT2 8 AB + 359 LUT2 4 aB + 360 LUT2 4 aB + 361 LUT4 0C0A DC?A:B:0:0 + 362 LUT3 CA C?A:B + 363 LUT3 CA C?A:B + 364 LUT3 CA C?A:B + 365 LUT3 CA C?A:B + 366 LUT3 CA C?A:B + 367 LUT3 CA C?A:B + 368 LUT3 CA C?A:B + 369 LUT3 CA C?A:B + 370 LUT4 0C0A DC?A:B:0:0 + 371 LUT4 0C0A DC?A:B:0:0 + 372 LUT3 40 aBC + 373 LUT4 0C0A DC?A:B:0:0 + 374 LUT4 0C0A DC?A:B:0:0 + 375 LUT3 CA C?A:B + 376 LUT3 D0 C/Ab\ + 377 LUT3 CA C?A:B + 378 LUT3 CA C?A:B + 379 LUT3 CA C?A:B + 380 LUT3 CA C?A:B + 381 LUT3 CA C?A:B + 382 LUT3 CA C?A:B + 383 LUT3 CA C?A:B + 384 LUT4 0C0A DC?A:B:0:0 + 385 LUT2 4 aB + 386 LUT2 4 aB + 387 LUT2 4 aB + 388 LUT2 4 aB + 389 LUT2 4 aB + 390 LUT2 4 aB + 391 LUT2 4 aB + 392 LUT4 4000 aBCD + 393 LUT4 0100 abcD + 394 LUT3 1F (ab)+c + 395 LUT3 1F (ab)+c + 396 LUT4 0C0A DC?A:B:0:0 + 397 LUT2 8 AB + 398 LUT2 8 AB + 399 LUT3 10 abC + 400 LUT2 4 aB + 401 LUT2 4 aB + 402 LUT2 4 aB + 403 LUT2 4 aB + 404 LUT2 4 aB + 405 LUT2 E /ab\ + 406 LUT4 00F4 ((aB)+C)d + 407 LUT2 4 aB + 408 LUT2 4 aB + 409 LUT4 0A0C DC?B:A:0:0 + 410 LUT4 0C0A DC?A:B:0:0 + 411 LUT3 AC c?A:B + 412 LUT3 CA C?A:B + 413 LUT3 CA C?A:B + 414 LUT3 CA C?A:B + 415 LUT3 CA C?A:B + 416 LUT3 CA C?A:B + 417 LUT3 CA C?A:B + 418 LUT3 CA C?A:B + 419 LUT2 B /aB\ + 420 LUT4 000D cd/Ab\ + 421 LUT4 7F00 ((/AB\)+c)D + 422 LUT3 0E c/ab\ + 423 LUT2 4 aB + 424 LUT2 4 aB + 425 LUT4 0100 abcD + 426 LUT3 40 aBC + 427 LUT4 CAFF (C?A:B)+d + 428 LUT4 0C0A DC?A:B:0:0 + 429 LUT4 0C0A DC?A:B:0:0 + 430 LUT4 0EEE /ab\(d+c) + 431 LUT4 8000 ABCD + 432 LUT2 4 aB + 433 LUT2 4 aB + 434 LUT2 4 aB + 435 LUT2 4 aB + 436 LUT2 8 AB + 437 LUT3 CA C?A:B + 438 LUT3 CA C?A:B + 439 LUT3 CA C?A:B + 440 LUT3 CA C?A:B + 441 LUT3 CA C?A:B + 442 LUT3 CA C?A:B + 443 LUT4 030A DC?A:b:0:0 + 444 LUT2 4 aB + 445 LUT4 F2FF (Ab)+C+d + 446 LUT4 001F ((ab)+c)d + 447 LUT4 0100 abcD + 448 LUT4 9009 (a^B)(D^c) + 449 LUT2 8 AB + 450 LUT3 10 abC + 451 LUT2 4 aB + 452 LUT4 FB0F DC?1:/aB\:0:1 + 453 LUT2 4 aB + 454 LUT3 01 abc + 455 LUT3 10 abC + 456 LUT3 0E c/ab\ + 457 LUT4 00F4 ((aB)+C)d + 458 LUT4 EB00 AD?0:0:b^C:1 + 459 LUT4 3335 DC?a:b:b:b + 460 LUT4 ACC5 DC?a:B:B:A + 461 LUT4 F011 D?ab:C + 462 LUT4 0C0A DC?A:B:0:0 + 463 LUT4 0100 abcD + 464 LUT2 8 AB + 465 LUT3 35 c?b:a + 466 LUT4 1F00 ((ab)+c)D + 467 LUT3 60 C(A^B) + 468 LUT3 40 aBC + 469 LUT2 8 AB + 470 LUT3 CA C?A:B + 471 LUT3 CA C?A:B + 472 LUT3 CA C?A:B + 473 LUT3 CA C?A:B + 474 LUT3 CA C?A:B + 475 LUT3 CA C?A:B + 476 LUT3 CA C?A:B + 477 LUT3 CA C?A:B + 478 LUT3 CA C?A:B + 479 LUT3 CA C?A:B + 480 LUT3 CA C?A:B + 481 LUT3 CA C?A:B + 482 LUT3 CA C?A:B + 483 LUT3 CA C?A:B + 484 LUT3 CA C?A:B + 485 LUT3 CA C?A:B + 486 LUT3 CA C?A:B + 487 LUT3 CA C?A:B + 488 LUT3 CA C?A:B + 489 LUT3 CA C?A:B + 490 LUT3 CA C?A:B + 491 LUT3 CA C?A:B + 492 LUT3 CA C?A:B + 493 LUT3 CA C?A:B + 494 LUT3 3A c?b:A + 495 LUT3 35 c?b:a + 496 LUT3 A3 C?b:A + 497 LUT3 35 c?b:a + 498 LUT4 8000 ABCD + 499 LUT3 AC c?A:B + 500 LUT3 CA C?A:B + 501 LUT3 AC c?A:B + 502 LUT3 CA C?A:B + 503 LUT3 AC c?A:B + 504 LUT3 CA C?A:B + 505 LUT4 0C0A DC?A:B:0:0 + 506 LUT3 0B c/aB\ + 507 LUT4 0C0A DC?A:B:0:0 + 508 LUT2 1 ab + 509 LUT4 0777 /AB\(d+c) + 510 LUT4 0C0A DC?A:B:0:0 + 511 LUT4 ACC5 DC?a:B:B:A + 512 LUT4 F011 D?ab:C + 513 LUT4 0C0A DC?A:B:0:0 + 514 LUT4 0100 abcD + 515 LUT2 8 AB + 516 LUT3 35 c?b:a + 517 LUT4 1F00 ((ab)+c)D + 518 LUT4 0C0A DC?A:B:0:0 + 519 LUT3 96 A^B^C + 520 LUT4 000E cd/ab\ + 521 LUT4 9000 CD(a^B) + 522 LUT3 40 aBC + 523 LUT2 1 ab + 524 LUT4 4F00 ((aB)+c)D + 525 LUT4 CACC DC?B:A:B:B + 526 LUT4 7F00 ((/AB\)+c)D + 527 LUT3 0E c/ab\ + 528 LUT3 40 aBC + 529 LUT3 40 aBC + 530 LUT4 CAFF (C?A:B)+d + 531 LUT4 FFF4 (aB)+C+D + 532 LUT4 0C0A DC?A:B:0:0 + 533 LUT4 0C0A DC?A:B:0:0 + 534 LUT4 41BE AD?B^C:1:b^C:0 + 535 LUT3 CA C?A:B + 536 LUT3 10 abC + 537 LUT3 CA C?A:B + 538 LUT3 CA C?A:B + 539 LUT3 CA C?A:B + 540 LUT3 CA C?A:B + 541 LUT3 CA C?A:B + 542 LUT3 CA C?A:B + 543 LUT4 F888 (AB)+(CD) + 544 LUT4 F888 (AB)+(CD) + 545 LUT4 F888 (AB)+(CD) + 546 LUT4 F888 (AB)+(CD) + 547 LUT4 F888 (AB)+(CD) + 548 LUT4 F888 (AB)+(CD) + 549 LUT4 F888 (AB)+(CD) + 550 LUT4 F888 (AB)+(CD) + 551 LUT4 F888 (AB)+(CD) + 552 LUT4 F888 (AB)+(CD) + 553 LUT4 F888 (AB)+(CD) + 554 LUT4 F888 (AB)+(CD) + 555 LUT4 F888 (AB)+(CD) + 556 LUT4 F888 (AB)+(CD) + 557 LUT4 F888 (AB)+(CD) + 558 LUT4 F888 (AB)+(CD) + 559 LUT4 F888 (AB)+(CD) + 560 LUT4 F888 (AB)+(CD) + 561 LUT4 F888 (AB)+(CD) + 562 LUT4 F888 (AB)+(CD) + 563 LUT4 F888 (AB)+(CD) + 564 LUT4 F888 (AB)+(CD) + 565 LUT4 F888 (AB)+(CD) + 566 LUT4 F888 (AB)+(CD) + 567 LUT4 F888 (AB)+(CD) + 568 LUT4 F888 (AB)+(CD) + 569 LUT4 F888 (AB)+(CD) + 570 LUT4 F888 (AB)+(CD) + 571 LUT4 F888 (AB)+(CD) + 572 LUT4 F888 (AB)+(CD) + 573 LUT4 F888 (AB)+(CD) + 574 LUT4 8F88 (AB)+(cD) + 575 LUT4 FF0B (c/aB\)+D + 576 LUT4 FF80 (ABC)+D + 577 LUT4 4000 aBCD + 578 LUT3 C5 C?a:B + 579 LUT3 C5 C?a:B + 580 LUT4 00EF ((/ab\)+c)d + 581 LUT4 3500 D(c?b:a) + 582 LUT4 00EF ((/ab\)+c)d + 583 LUT4 3500 D(c?b:a) + 584 LUT4 00EF ((/ab\)+c)d + 585 LUT4 3500 D(c?b:a) + 586 LUT4 00EF ((/ab\)+c)d + 587 LUT4 3500 D(c?b:a) + 588 LUT4 00EF ((/ab\)+c)d + 589 LUT4 3500 D(c?b:a) + 590 LUT4 F044 D?aB:C + 591 LUT4 F044 D?aB:C + 592 LUT4 F044 D?aB:C + 593 LUT4 F044 D?aB:C + 594 LUT4 F044 D?aB:C + 595 LUT4 F044 D?aB:C + 596 LUT4 F044 D?aB:C + 597 LUT4 B0FF (C/aB\)+d + 598 LUT4 6900 D(A^B^c) + 599 LUT4 7D82 AD?0:b^C:1:B^C + 600 LUT2 8 AB + 601 LUT3 01 abc + 602 LUT4 000D cd/Ab\ + 603 LUT4 6000 CD(A^B) + 604 LUT2 6 A^B + 605 LUT4 1F00 ((ab)+c)D + 606 LUT3 3E BC?A:1:1:0 + 607 LUT4 FFE0 (C/ab\)+D + 608 LUT2 4 aB + 609 LUT3 40 aBC + 610 LUT4 F800 ((AB)+C)D + 611 LUT3 80 ABC + 612 LUT3 96 A^B^C + 613 LUT3 40 aBC + 614 LUT4 0FBB D?/aB\:c + 615 LUT4 BF00 ((/aB\)+c)D + 616 LUT4 007F ((/AB\)+c)d + 617 LUT4 CA00 D(C?A:B) + 618 LUT2 6 A^B + 619 LUT3 AC c?A:B + 620 LUT4 F044 D?aB:C + 621 LUT3 C5 C?a:B + 622 LUT3 C5 C?a:B + 623 LUT2 1 ab + 624 LUT4 0C0A DC?A:B:0:0 + 625 LUT2 1 ab + 626 LUT4 0C0A DC?A:B:0:0 + 627 LUT2 1 ab + 628 LUT4 0C0A DC?A:B:0:0 + 629 LUT2 1 ab + 630 LUT4 0C0A DC?A:B:0:0 + 631 LUT2 1 ab + 632 LUT4 0C0A DC?A:B:0:0 + 633 LUT4 0C0A DC?A:B:0:0 + 634 LUT4 0C0A DC?A:B:0:0 + 635 LUT4 0C0A DC?A:B:0:0 + 636 LUT4 7F00 ((/AB\)+c)D + 637 LUT4 00F8 ((AB)+C)d + 638 LUT3 40 aBC + 639 LUT4 CAFF (C?A:B)+d + 640 LUT4 0C0A DC?A:B:0:0 + 641 LUT4 0C0A DC?A:B:0:0 + 642 LUT4 0C0A DC?A:B:0:0 + 643 LUT2 8 AB + 644 LUT2 8 AB + 645 LUT2 1 ab + 646 LUT4 0777 /AB\(d+c) + 647 LUT4 0C0A DC?A:B:0:0 + 648 LUT3 CA C?A:B + 649 LUT3 CA C?A:B + 650 LUT3 CA C?A:B + 651 LUT3 CA C?A:B + 652 LUT3 CA C?A:B + 653 LUT3 CA C?A:B + 654 LUT3 CA C?A:B + 655 LUT3 CA C?A:B + 656 LUT3 CA C?A:B + 657 LUT3 CA C?A:B + 658 LUT3 CA C?A:B + 659 LUT3 CA C?A:B + 660 LUT3 CA C?A:B + 661 LUT3 CA C?A:B + 662 LUT3 CA C?A:B + 663 LUT3 CA C?A:B + 664 LUT3 CA C?A:B + 665 LUT3 CA C?A:B + 666 LUT3 CA C?A:B + 667 LUT3 CA C?A:B + 668 LUT3 CA C?A:B + 669 LUT3 CA C?A:B + 670 LUT3 CA C?A:B + 671 LUT3 CA C?A:B + 672 LUT3 3A c?b:A + 673 LUT3 35 c?b:a + 674 LUT4 0C0A DC?A:B:0:0 + 675 LUT3 AC c?A:B + 676 LUT3 CA C?A:B + 677 LUT4 8000 ABCD + 678 LUT3 AC c?A:B + 679 LUT3 CA C?A:B + 680 LUT3 AC c?A:B + 681 LUT3 CA C?A:B + 682 LUT3 AC c?A:B + 683 LUT3 CA C?A:B + 684 LUT4 0C0A DC?A:B:0:0 + 685 LUT4 0C0A DC?A:B:0:0 + 686 LUT4 0C0A DC?A:B:0:0 + 687 LUT2 4 aB + 688 LUT2 4 aB + 689 LUT2 4 aB + 690 LUT2 1 ab + 691 LUT4 0777 /AB\(d+c) + 692 LUT4 0C0A DC?A:B:0:0 + 693 LUT4 0C0A DC?A:B:0:0 + 694 LUT4 0C0A DC?A:B:0:0 + 695 LUT2 8 AB + 696 LUT4 0C0A DC?A:B:0:0 + 697 LUT4 0C0A DC?A:B:0:0 + 698 LUT3 CA C?A:B + 699 LUT3 CA C?A:B + 700 LUT3 CA C?A:B + 701 LUT3 CA C?A:B + 702 LUT3 CA C?A:B + 703 LUT3 CA C?A:B + 704 LUT3 96 A^B^C + 705 LUT4 000E cd/ab\ + 706 LUT4 9000 CD(a^B) + 707 LUT3 40 aBC + 708 LUT4 4F00 ((aB)+c)D + 709 LUT4 CACC DC?B:A:B:B + 710 LUT4 0C0A DC?A:B:0:0 + 711 LUT4 0C0A DC?A:B:0:0 + 712 LUT4 0C0A DC?A:B:0:0 + 713 LUT4 41BE AD?B^C:1:b^C:0 + 714 LUT3 CA C?A:B + 715 LUT3 CA C?A:B + 716 LUT3 CA C?A:B + 717 LUT3 CA C?A:B + 718 LUT3 CA C?A:B + 719 LUT3 CA C?A:B + 720 LUT3 CA C?A:B + 721 LUT3 CA C?A:B + 722 LUT3 CA C?A:B + 723 LUT3 CA C?A:B + 724 LUT3 CA C?A:B + 725 LUT3 CA C?A:B + 726 LUT3 CA C?A:B + 727 LUT4 0C0A DC?A:B:0:0 + 728 LUT4 F888 (AB)+(CD) + 729 LUT4 F888 (AB)+(CD) + 730 LUT4 F888 (AB)+(CD) + 731 LUT4 F888 (AB)+(CD) + 732 LUT4 F888 (AB)+(CD) + 733 LUT4 F888 (AB)+(CD) + 734 LUT4 F888 (AB)+(CD) + 735 LUT4 F888 (AB)+(CD) + 736 LUT4 F888 (AB)+(CD) + 737 LUT4 F888 (AB)+(CD) + 738 LUT4 F888 (AB)+(CD) + 739 LUT4 F888 (AB)+(CD) + 740 LUT4 F888 (AB)+(CD) + 741 LUT4 F888 (AB)+(CD) + 742 LUT4 F888 (AB)+(CD) + 743 LUT4 F888 (AB)+(CD) + 744 LUT4 F888 (AB)+(CD) + 745 LUT4 F888 (AB)+(CD) + 746 LUT4 F888 (AB)+(CD) + 747 LUT4 F888 (AB)+(CD) + 748 LUT4 F888 (AB)+(CD) + 749 LUT4 F888 (AB)+(CD) + 750 LUT4 F888 (AB)+(CD) + 751 LUT4 F888 (AB)+(CD) + 752 LUT4 F888 (AB)+(CD) + 753 LUT4 F888 (AB)+(CD) + 754 LUT4 F888 (AB)+(CD) + 755 LUT4 F888 (AB)+(CD) + 756 LUT4 F888 (AB)+(CD) + 757 LUT4 F888 (AB)+(CD) + 758 LUT4 F888 (AB)+(CD) + 759 LUT4 8F88 (AB)+(cD) + 760 LUT4 0C0A DC?A:B:0:0 + 761 LUT4 FF0B (c/aB\)+D + 762 LUT4 0C0A DC?A:B:0:0 + 763 LUT4 FF80 (ABC)+D + 764 LUT4 4000 aBCD + 765 LUT3 C5 C?a:B + 766 LUT3 C5 C?a:B + 767 LUT4 00EF ((/ab\)+c)d + 768 LUT4 3500 D(c?b:a) + 769 LUT4 00EF ((/ab\)+c)d + 770 LUT4 3500 D(c?b:a) + 771 LUT4 00EF ((/ab\)+c)d + 772 LUT4 3500 D(c?b:a) + 773 LUT4 00EF ((/ab\)+c)d + 774 LUT4 3500 D(c?b:a) + 775 LUT4 00EF ((/ab\)+c)d + 776 LUT4 3500 D(c?b:a) + 777 LUT4 F044 D?aB:C + 778 LUT4 F044 D?aB:C + 779 LUT4 F044 D?aB:C + 780 LUT4 F044 D?aB:C + 781 LUT4 F044 D?aB:C + 782 LUT4 F044 D?aB:C + 783 LUT4 F044 D?aB:C + 784 LUT4 B0FF (C/aB\)+d + 785 LUT4 6900 D(A^B^c) + 786 LUT4 7D82 AD?0:b^C:1:B^C + 787 LUT2 8 AB + 788 LUT3 01 abc + 789 LUT4 000D cd/Ab\ + 790 LUT4 6000 CD(A^B) + 791 LUT3 80 ABC + 792 LUT4 0FBB D?/aB\:c + 793 LUT4 BF00 ((/aB\)+c)D + 794 LUT4 007F ((/AB\)+c)d + 795 LUT4 CA00 D(C?A:B) + 796 LUT2 6 A^B + 797 LUT3 AC c?A:B + 798 LUT4 F044 D?aB:C + 799 LUT3 C5 C?a:B + 800 LUT3 C5 C?a:B + 801 LUT2 1 ab + 802 LUT4 0C0A DC?A:B:0:0 + 803 LUT2 1 ab + 804 LUT4 0C0A DC?A:B:0:0 + 805 LUT2 1 ab + 806 LUT4 0C0A DC?A:B:0:0 + 807 LUT2 1 ab + 808 LUT4 0C0A DC?A:B:0:0 + 809 LUT2 1 ab + 810 LUT4 0C0A DC?A:B:0:0 + 811 LUT4 030A DC?A:b:0:0 + 812 LUT3 35 c?b:a + 813 LUT3 60 C(A^B) + 814 LUT4 0C0A DC?A:B:0:0 + 815 LUT4 0C0A DC?A:B:0:0 + 816 LUT4 0C0A DC?A:B:0:0 + 817 LUT4 7F00 ((/AB\)+c)D + 818 LUT2 1 ab + 819 LUT4 00EF ((/ab\)+c)d + 820 LUT2 4 aB + 821 LUT3 40 aBC + 822 LUT4 CAFF (C?A:B)+d + 823 LUT4 0C0A DC?A:B:0:0 + 824 LUT2 4 aB + 825 LUT2 4 aB + 826 LUT2 4 aB + 827 LUT3 CA C?A:B + 828 LUT3 CA C?A:B + 829 LUT3 CA C?A:B + 830 LUT3 CA C?A:B + 831 LUT3 CA C?A:B + 832 LUT3 CA C?A:B + 833 LUT3 CA C?A:B + 834 LUT3 CA C?A:B + 835 LUT3 CA C?A:B + 836 LUT3 CA C?A:B + 837 LUT3 CA C?A:B + 838 LUT3 CA C?A:B + 839 LUT3 CA C?A:B + 840 LUT3 CA C?A:B + 841 LUT3 CA C?A:B + 842 LUT3 CA C?A:B + 843 LUT3 CA C?A:B + 844 LUT3 CA C?A:B + 845 LUT3 CA C?A:B + 846 LUT3 CA C?A:B + 847 LUT3 CA C?A:B + 848 LUT3 CA C?A:B + 849 LUT3 CA C?A:B + 850 LUT3 CA C?A:B + 851 LUT3 3A c?b:A + 852 LUT3 35 c?b:a + 853 LUT3 AC c?A:B + 854 LUT3 CA C?A:B + 855 LUT4 8000 ABCD + 856 LUT3 AC c?A:B + 857 LUT3 CA C?A:B + 858 LUT3 AC c?A:B + 859 LUT3 CA C?A:B + 860 LUT3 AC c?A:B + 861 LUT3 CA C?A:B + 862 LUT4 0C0A DC?A:B:0:0 + 863 LUT2 4 aB + 864 LUT3 CA C?A:B + 865 LUT3 CA C?A:B + 866 LUT3 CA C?A:B + 867 LUT3 CA C?A:B + 868 LUT3 CA C?A:B + 869 LUT3 CA C?A:B + 870 LUT3 CA C?A:B + 871 LUT3 CA C?A:B + 872 LUT3 CA C?A:B + 873 LUT3 CA C?A:B + 874 LUT3 CA C?A:B + 875 LUT3 CA C?A:B + 876 LUT3 CA C?A:B + 877 LUT4 ACC5 DC?a:B:B:A + 878 LUT4 F011 D?ab:C + 879 LUT3 35 c?b:a + 880 LUT4 1F00 ((ab)+c)D + 881 LUT3 96 A^B^C + 882 LUT4 000E cd/ab\ + 883 LUT4 9000 CD(a^B) + 884 LUT3 40 aBC + 885 LUT4 4F00 ((aB)+c)D + 886 LUT4 CACC DC?B:A:B:B + 887 LUT2 8 AB + 888 LUT3 10 abC + 889 LUT2 4 aB + 890 LUT2 4 aB + 891 LUT4 41BE AD?B^C:1:b^C:0 + 892 LUT4 F888 (AB)+(CD) + 893 LUT4 F888 (AB)+(CD) + 894 LUT4 F888 (AB)+(CD) + 895 LUT4 F888 (AB)+(CD) + 896 LUT4 F888 (AB)+(CD) + 897 LUT4 F888 (AB)+(CD) + 898 LUT4 F888 (AB)+(CD) + 899 LUT4 F888 (AB)+(CD) + 900 LUT4 F888 (AB)+(CD) + 901 LUT4 F888 (AB)+(CD) + 902 LUT4 F888 (AB)+(CD) + 903 LUT4 F888 (AB)+(CD) + 904 LUT4 F888 (AB)+(CD) + 905 LUT4 F888 (AB)+(CD) + 906 LUT4 F888 (AB)+(CD) + 907 LUT4 F888 (AB)+(CD) + 908 LUT4 F888 (AB)+(CD) + 909 LUT4 F888 (AB)+(CD) + 910 LUT4 F888 (AB)+(CD) + 911 LUT4 F888 (AB)+(CD) + 912 LUT4 F888 (AB)+(CD) + 913 LUT4 F888 (AB)+(CD) + 914 LUT4 F888 (AB)+(CD) + 915 LUT4 F888 (AB)+(CD) + 916 LUT4 F888 (AB)+(CD) + 917 LUT4 F888 (AB)+(CD) + 918 LUT4 F888 (AB)+(CD) + 919 LUT4 F888 (AB)+(CD) + 920 LUT4 F888 (AB)+(CD) + 921 LUT4 F888 (AB)+(CD) + 922 LUT4 F888 (AB)+(CD) + 923 LUT4 8F88 (AB)+(cD) + 924 LUT4 FF0B (c/aB\)+D + 925 LUT2 4 aB + 926 LUT4 0A0C DC?B:A:0:0 + 927 LUT2 4 aB + 928 LUT4 0C0A DC?A:B:0:0 + 929 LUT4 0C0A DC?A:B:0:0 + 930 LUT4 FF80 (ABC)+D + 931 LUT4 4000 aBCD + 932 LUT3 C5 C?a:B + 933 LUT3 C5 C?a:B + 934 LUT4 00EF ((/ab\)+c)d + 935 LUT4 3500 D(c?b:a) + 936 LUT4 00EF ((/ab\)+c)d + 937 LUT4 3500 D(c?b:a) + 938 LUT4 00EF ((/ab\)+c)d + 939 LUT4 3500 D(c?b:a) + 940 LUT4 00EF ((/ab\)+c)d + 941 LUT4 3500 D(c?b:a) + 942 LUT4 00EF ((/ab\)+c)d + 943 LUT4 3500 D(c?b:a) + 944 LUT4 F044 D?aB:C + 945 LUT4 F044 D?aB:C + 946 LUT4 F044 D?aB:C + 947 LUT4 F044 D?aB:C + 948 LUT4 F044 D?aB:C + 949 LUT4 F044 D?aB:C + 950 LUT4 F044 D?aB:C + 951 LUT4 B0FF (C/aB\)+d + 952 LUT4 6900 D(A^B^c) + 953 LUT4 7D82 AD?0:b^C:1:B^C + 954 LUT2 8 AB + 955 LUT3 01 abc + 956 LUT4 000D cd/Ab\ + 957 LUT4 6000 CD(A^B) + 958 LUT3 80 ABC + 959 LUT4 0FBB D?/aB\:c + 960 LUT4 BF00 ((/aB\)+c)D + 961 LUT4 007F ((/AB\)+c)d + 962 LUT4 CA00 D(C?A:B) + 963 LUT2 6 A^B + 964 LUT3 AC c?A:B + 965 LUT4 F044 D?aB:C + 966 LUT3 C5 C?a:B + 967 LUT3 C5 C?a:B + 968 LUT2 1 ab + 969 LUT4 0C0A DC?A:B:0:0 + 970 LUT2 1 ab + 971 LUT4 0C0A DC?A:B:0:0 + 972 LUT2 1 ab + 973 LUT4 0C0A DC?A:B:0:0 + 974 LUT2 1 ab + 975 LUT4 0C0A DC?A:B:0:0 + 976 LUT2 1 ab + 977 LUT4 0C0A DC?A:B:0:0 + 978 LUT4 0EEE /ab\(d+c) + 979 LUT4 8000 ABCD + 980 LUT2 4 aB + 981 LUT2 4 aB + 982 LUT2 4 aB + 983 LUT2 4 aB + 984 LUT2 1 ab + 985 LUT4 0777 /AB\(d+c) + 986 LUT2 4 aB + 987 LUT3 40 aBC + 988 LUT3 40 aBC + 989 LUT4 F444 (aB)+(CD) + 990 LUT4 1000 abCD + 991 LUT4 0001 abcd + 992 LUT4 0001 abcd + 993 LUT3 CA C?A:B + 994 LUT3 CA C?A:B + 995 LUT3 CA C?A:B + 996 LUT3 CA C?A:B + 997 LUT3 CA C?A:B + 998 LUT3 CA C?A:B + 999 LUT3 CA C?A:B + 1000 LUT3 CA C?A:B + 1001 LUT3 CA C?A:B + 1002 LUT3 CA C?A:B + 1003 LUT3 CA C?A:B + 1004 LUT3 CA C?A:B + 1005 LUT3 CA C?A:B + 1006 LUT3 CA C?A:B + 1007 LUT3 CA C?A:B + 1008 LUT3 CA C?A:B + 1009 LUT3 CA C?A:B + 1010 LUT3 CA C?A:B + 1011 LUT3 CA C?A:B + 1012 LUT3 CA C?A:B + 1013 LUT3 CA C?A:B + 1014 LUT3 CA C?A:B + 1015 LUT3 CA C?A:B + 1016 LUT3 CA C?A:B + 1017 LUT3 CA C?A:B + 1018 LUT3 CA C?A:B + 1019 LUT3 CA C?A:B + 1020 LUT3 CA C?A:B + 1021 LUT3 CA C?A:B + 1022 LUT3 CA C?A:B + 1023 LUT3 CA C?A:B + 1024 LUT3 3A c?b:A + 1025 LUT3 35 c?b:a + 1026 LUT3 AC c?A:B + 1027 LUT3 CA C?A:B + 1028 LUT4 8000 ABCD + 1029 LUT3 AC c?A:B + 1030 LUT3 CA C?A:B + 1031 LUT3 AC c?A:B + 1032 LUT3 CA C?A:B + 1033 LUT3 AC c?A:B + 1034 LUT3 CA C?A:B + 1035 LUT4 0C0A DC?A:B:0:0 + 1036 LUT4 0C0A DC?A:B:0:0 + 1037 LUT4 ACC5 DC?a:B:B:A + 1038 LUT4 F011 D?ab:C + 1039 LUT4 0C0A DC?A:B:0:0 + 1040 LUT4 0100 abcD + 1041 LUT2 8 AB + 1042 LUT3 35 c?b:a + 1043 LUT4 1F00 ((ab)+c)D + 1044 LUT3 96 A^B^C + 1045 LUT4 000E cd/ab\ + 1046 LUT4 9000 CD(a^B) + 1047 LUT3 40 aBC + 1048 LUT2 1 ab + 1049 LUT4 4F00 ((aB)+c)D + 1050 LUT4 CACC DC?B:A:B:B + 1051 LUT4 41BE AD?B^C:1:b^C:0 + 1052 LUT4 F888 (AB)+(CD) + 1053 LUT4 F888 (AB)+(CD) + 1054 LUT4 F888 (AB)+(CD) + 1055 LUT4 F888 (AB)+(CD) + 1056 LUT4 F888 (AB)+(CD) + 1057 LUT4 F888 (AB)+(CD) + 1058 LUT4 F888 (AB)+(CD) + 1059 LUT4 F888 (AB)+(CD) + 1060 LUT4 F888 (AB)+(CD) + 1061 LUT4 F888 (AB)+(CD) + 1062 LUT4 F888 (AB)+(CD) + 1063 LUT4 F888 (AB)+(CD) + 1064 LUT4 F888 (AB)+(CD) + 1065 LUT4 F888 (AB)+(CD) + 1066 LUT4 F888 (AB)+(CD) + 1067 LUT4 F888 (AB)+(CD) + 1068 LUT4 F888 (AB)+(CD) + 1069 LUT4 F888 (AB)+(CD) + 1070 LUT4 F888 (AB)+(CD) + 1071 LUT4 F888 (AB)+(CD) + 1072 LUT4 F888 (AB)+(CD) + 1073 LUT4 F888 (AB)+(CD) + 1074 LUT4 F888 (AB)+(CD) + 1075 LUT4 F888 (AB)+(CD) + 1076 LUT4 F888 (AB)+(CD) + 1077 LUT4 F888 (AB)+(CD) + 1078 LUT4 F888 (AB)+(CD) + 1079 LUT4 F888 (AB)+(CD) + 1080 LUT4 F888 (AB)+(CD) + 1081 LUT4 F888 (AB)+(CD) + 1082 LUT4 F888 (AB)+(CD) + 1083 LUT4 8F88 (AB)+(cD) + 1084 LUT4 FF0B (c/aB\)+D + 1085 LUT4 00F4 ((aB)+C)d + 1086 LUT4 EB00 AD?0:0:b^C:1 + 1087 LUT4 3335 DC?a:b:b:b + 1088 LUT3 60 C(A^B) + 1089 LUT3 40 aBC + 1090 LUT2 8 AB + 1091 LUT4 FF80 (ABC)+D + 1092 LUT4 4000 aBCD + 1093 LUT3 C5 C?a:B + 1094 LUT3 C5 C?a:B + 1095 LUT4 00EF ((/ab\)+c)d + 1096 LUT4 3500 D(c?b:a) + 1097 LUT4 00EF ((/ab\)+c)d + 1098 LUT4 3500 D(c?b:a) + 1099 LUT4 00EF ((/ab\)+c)d + 1100 LUT4 3500 D(c?b:a) + 1101 LUT4 00EF ((/ab\)+c)d + 1102 LUT4 3500 D(c?b:a) + 1103 LUT4 00EF ((/ab\)+c)d + 1104 LUT4 3500 D(c?b:a) + 1105 LUT4 F044 D?aB:C + 1106 LUT4 F044 D?aB:C + 1107 LUT4 F044 D?aB:C + 1108 LUT4 F044 D?aB:C + 1109 LUT4 F044 D?aB:C + 1110 LUT4 F044 D?aB:C + 1111 LUT4 F044 D?aB:C + 1112 LUT4 B0FF (C/aB\)+d + 1113 LUT4 6900 D(A^B^c) + 1114 LUT4 7D82 AD?0:b^C:1:B^C + 1115 LUT2 8 AB + 1116 LUT3 01 abc + 1117 LUT4 000D cd/Ab\ + 1118 LUT4 6000 CD(A^B) + 1119 LUT2 6 A^B + 1120 LUT4 1F00 ((ab)+c)D + 1121 LUT3 3E BC?A:1:1:0 + 1122 LUT4 FFE0 (C/ab\)+D + 1123 LUT2 4 aB + 1124 LUT3 40 aBC + 1125 LUT4 F800 ((AB)+C)D + 1126 LUT3 80 ABC + 1127 LUT3 96 A^B^C + 1128 LUT3 40 aBC + 1129 LUT4 0FBB D?/aB\:c + 1130 LUT4 BF00 ((/aB\)+c)D + 1131 LUT4 007F ((/AB\)+c)d + 1132 LUT4 CA00 D(C?A:B) + 1133 LUT2 6 A^B + 1134 LUT3 AC c?A:B + 1135 LUT4 F044 D?aB:C + 1136 LUT3 C5 C?a:B + 1137 LUT3 C5 C?a:B + 1138 LUT2 1 ab + 1139 LUT4 0C0A DC?A:B:0:0 + 1140 LUT2 1 ab + 1141 LUT4 0C0A DC?A:B:0:0 + 1142 LUT2 1 ab + 1143 LUT4 0C0A DC?A:B:0:0 + 1144 LUT2 1 ab + 1145 LUT4 0C0A DC?A:B:0:0 + 1146 LUT2 1 ab + 1147 LUT4 0C0A DC?A:B:0:0 + 1148 LUT2 1 ab + 1149 LUT2 7 /AB\ + 1150 LUT2 E /ab\ + 1151 LUT3 CA C?A:B + 1152 LUT3 CA C?A:B + 1153 LUT3 CA C?A:B + 1154 LUT3 CA C?A:B + 1155 LUT3 CA C?A:B + 1156 LUT3 CA C?A:B + 1157 LUT3 CA C?A:B + 1158 LUT3 CA C?A:B + 1159 LUT3 CA C?A:B + 1160 LUT3 CA C?A:B + 1161 LUT3 CA C?A:B + 1162 LUT3 CA C?A:B + 1163 LUT3 CA C?A:B + 1164 LUT3 CA C?A:B + 1165 LUT3 CA C?A:B + 1166 LUT3 CA C?A:B + 1167 LUT3 CA C?A:B + 1168 LUT3 CA C?A:B + 1169 LUT3 CA C?A:B + 1170 LUT3 CA C?A:B + 1171 LUT3 CA C?A:B + 1172 LUT3 CA C?A:B + 1173 LUT3 CA C?A:B + 1174 LUT3 CA C?A:B + 1175 LUT3 3A c?b:A + 1176 LUT3 35 c?b:a + 1177 LUT3 AC c?A:B + 1178 LUT3 CA C?A:B + 1179 LUT4 8000 ABCD + 1180 LUT3 AC c?A:B + 1181 LUT3 CA C?A:B + 1182 LUT3 AC c?A:B + 1183 LUT3 CA C?A:B + 1184 LUT3 AC c?A:B + 1185 LUT3 CA C?A:B + 1186 LUT4 0C0A DC?A:B:0:0 + 1187 LUT4 0C0A DC?A:B:0:0 + 1188 LUT4 0C0A DC?A:B:0:0 + 1189 LUT4 CA00 D(C?A:B) + 1190 LUT2 8 AB + 1191 LUT3 2C BC?0:1:A:0 + 1192 LUT3 96 A^B^C + 1193 LUT4 000E cd/ab\ + 1194 LUT4 9000 CD(a^B) + 1195 LUT3 40 aBC + 1196 LUT2 1 ab + 1197 LUT4 4F00 ((aB)+c)D + 1198 LUT4 CACC DC?B:A:B:B + 1199 LUT4 41BE AD?B^C:1:b^C:0 + 1200 LUT4 F888 (AB)+(CD) + 1201 LUT4 F888 (AB)+(CD) + 1202 LUT4 F888 (AB)+(CD) + 1203 LUT4 F888 (AB)+(CD) + 1204 LUT4 F888 (AB)+(CD) + 1205 LUT4 F888 (AB)+(CD) + 1206 LUT4 F888 (AB)+(CD) + 1207 LUT4 F888 (AB)+(CD) + 1208 LUT4 F888 (AB)+(CD) + 1209 LUT4 F888 (AB)+(CD) + 1210 LUT4 F888 (AB)+(CD) + 1211 LUT4 F888 (AB)+(CD) + 1212 LUT4 F888 (AB)+(CD) + 1213 LUT4 F888 (AB)+(CD) + 1214 LUT4 F888 (AB)+(CD) + 1215 LUT4 F888 (AB)+(CD) + 1216 LUT4 F888 (AB)+(CD) + 1217 LUT4 F888 (AB)+(CD) + 1218 LUT4 F888 (AB)+(CD) + 1219 LUT4 F888 (AB)+(CD) + 1220 LUT4 F888 (AB)+(CD) + 1221 LUT4 F888 (AB)+(CD) + 1222 LUT4 F888 (AB)+(CD) + 1223 LUT4 F888 (AB)+(CD) + 1224 LUT4 F888 (AB)+(CD) + 1225 LUT4 F888 (AB)+(CD) + 1226 LUT4 F888 (AB)+(CD) + 1227 LUT4 F888 (AB)+(CD) + 1228 LUT4 F888 (AB)+(CD) + 1229 LUT4 F888 (AB)+(CD) + 1230 LUT4 F888 (AB)+(CD) + 1231 LUT4 8F88 (AB)+(cD) + 1232 LUT4 FF0B (c/aB\)+D + 1233 LUT4 FF80 (ABC)+D + 1234 LUT4 4000 aBCD + 1235 LUT3 C5 C?a:B + 1236 LUT3 C5 C?a:B + 1237 LUT4 00EF ((/ab\)+c)d + 1238 LUT4 3500 D(c?b:a) + 1239 LUT4 00EF ((/ab\)+c)d + 1240 LUT4 3500 D(c?b:a) + 1241 LUT4 00EF ((/ab\)+c)d + 1242 LUT4 3500 D(c?b:a) + 1243 LUT4 00EF ((/ab\)+c)d + 1244 LUT4 3500 D(c?b:a) + 1245 LUT4 00EF ((/ab\)+c)d + 1246 LUT4 3500 D(c?b:a) + 1247 LUT4 F044 D?aB:C + 1248 LUT4 F044 D?aB:C + 1249 LUT4 F044 D?aB:C + 1250 LUT4 F044 D?aB:C + 1251 LUT4 F044 D?aB:C + 1252 LUT4 F044 D?aB:C + 1253 LUT4 F044 D?aB:C + 1254 LUT4 B0FF (C/aB\)+d + 1255 LUT4 6900 D(A^B^c) + 1256 LUT4 7D82 AD?0:b^C:1:B^C + 1257 LUT2 8 AB + 1258 LUT3 01 abc + 1259 LUT4 000D cd/Ab\ + 1260 LUT4 6000 CD(A^B) + 1261 LUT2 6 A^B + 1262 LUT4 1F00 ((ab)+c)D + 1263 LUT3 3E BC?A:1:1:0 + 1264 LUT4 FFE0 (C/ab\)+D + 1265 LUT2 4 aB + 1266 LUT3 40 aBC + 1267 LUT4 F800 ((AB)+C)D + 1268 LUT3 80 ABC + 1269 LUT3 96 A^B^C + 1270 LUT3 40 aBC + 1271 LUT4 0FBB D?/aB\:c + 1272 LUT4 BF00 ((/aB\)+c)D + 1273 LUT4 007F ((/AB\)+c)d + 1274 LUT4 CA00 D(C?A:B) + 1275 LUT2 6 A^B + 1276 LUT3 AC c?A:B + 1277 LUT4 F044 D?aB:C + 1278 LUT3 C5 C?a:B + 1279 LUT3 C5 C?a:B + 1280 LUT2 1 ab + 1281 LUT4 0C0A DC?A:B:0:0 + 1282 LUT2 1 ab + 1283 LUT4 0C0A DC?A:B:0:0 + 1284 LUT2 1 ab + 1285 LUT4 0C0A DC?A:B:0:0 + 1286 LUT2 1 ab + 1287 LUT4 0C0A DC?A:B:0:0 + 1288 LUT2 1 ab + 1289 LUT4 0C0A DC?A:B:0:0 + 1290 LUT2 1 ab + 1291 LUT4 0777 /AB\(d+c) + 1292 LUT4 0C0A DC?A:B:0:0 + 1293 LUT4 0C0A DC?A:B:0:0 + 1294 LUT4 0C0A DC?A:B:0:0 + 1295 LUT4 0C0A DC?A:B:0:0 + 1296 LUT4 00F4 ((aB)+C)d + 1297 LUT4 CEC0 BD?0:C:Ac:1 + 1298 LUT4 0C0A DC?A:B:0:0 + 1299 LUT2 1 ab + 1300 LUT4 00F8 ((AB)+C)d + 1301 LUT4 0C0A DC?A:B:0:0 + 1302 LUT4 0C0A DC?A:B:0:0 + 1303 LUT2 4 aB + 1304 LUT2 4 aB + 1305 LUT2 8 AB + 1306 LUT2 4 aB + 1307 LUT2 4 aB + 1308 LUT4 0C0A DC?A:B:0:0 + 1309 LUT4 030A DC?A:b:0:0 + 1310 LUT3 35 c?b:a + 1311 LUT3 60 C(A^B) + 1312 LUT4 0C0A DC?A:B:0:0 + 1313 LUT4 0C0A DC?A:B:0:0 + 1314 LUT4 00F8 ((AB)+C)d + 1315 LUT4 F400 ((aB)+C)D + 1316 LUT2 1 ab + 1317 LUT4 0C0A DC?A:B:0:0 + 1318 LUT4 0C0A DC?A:B:0:0 + 1319 LUT4 0C0A DC?A:B:0:0 + 1320 LUT4 0C0A DC?A:B:0:0 + 1321 LUT4 0C0A DC?A:B:0:0 + 1322 LUT4 FCFA DC?A:B:1:1 + 1323 LUT4 0C0A DC?A:B:0:0 + 1324 LUT4 0C0A DC?A:B:0:0 + 1325 LUT4 0C0A DC?A:B:0:0 + 1326 LUT4 0C0A DC?A:B:0:0 + 1327 LUT4 0C0A DC?A:B:0:0 + 1328 LUT4 0C0A DC?A:B:0:0 + 1329 LUT4 0C0A DC?A:B:0:0 + 1330 LUT2 4 aB + 1331 LUT4 0C0A DC?A:B:0:0 + 1332 LUT4 030A DC?A:b:0:0 + 1333 LUT3 35 c?b:a + 1334 LUT3 60 C(A^B) + 1335 LUT4 0C0A DC?A:B:0:0 + 1336 LUT4 0C0A DC?A:B:0:0 + 1337 LUT4 FFF4 (aB)+C+D + 1338 LUT4 0C0A DC?A:B:0:0 + 1339 LUT4 0C0A DC?A:B:0:0 + 1340 LUT4 0C0A DC?A:B:0:0 + 1341 LUT4 00F4 ((aB)+C)d + 1342 LUT4 EB00 AD?0:0:b^C:1 + 1343 LUT4 3335 DC?a:b:b:b + 1344 LUT3 60 C(A^B) + 1345 LUT3 40 aBC + 1346 LUT2 8 AB + 1347 LUT4 030A DC?A:b:0:0 + 1348 LUT2 4 aB + 1349 LUT3 10 abC + 1350 LUT2 8 AB + 1351 LUT4 00F8 ((AB)+C)d + 1352 LUT4 0C0A DC?A:B:0:0 + 1353 LUT4 0C0A DC?A:B:0:0 + 1354 LUT4 4000 aBCD + 1355 LUT4 0C0A DC?A:B:0:0 + 1356 LUT4 0C0A DC?A:B:0:0 + 1357 LUT4 0C0A DC?A:B:0:0 + 1358 LUT3 CA C?A:B + 1359 LUT3 CA C?A:B + 1360 LUT3 CA C?A:B + 1361 LUT3 CA C?A:B + 1362 LUT3 CA C?A:B + 1363 LUT3 CA C?A:B + 1364 LUT4 0C0A DC?A:B:0:0 + 1365 LUT4 0C0A DC?A:B:0:0 + 1366 LUT4 0C0A DC?A:B:0:0 + 1367 LUT4 0C0A DC?A:B:0:0 + 1368 LUT4 0C0A DC?A:B:0:0 + 1369 LUT4 FAFC DC?B:A:1:1 + 1370 LUT4 00F4 ((aB)+C)d + 1371 LUT4 EB00 AD?0:0:b^C:1 + 1372 LUT4 3335 DC?a:b:b:b + 1373 LUT3 60 C(A^B) + 1374 LUT3 40 aBC + 1375 LUT2 8 AB + 1376 LUT4 0C0A DC?A:B:0:0 + 1377 LUT4 0C0A DC?A:B:0:0 + 1378 LUT4 0C0A DC?A:B:0:0 + 1379 LUT4 0C0A DC?A:B:0:0 + 1380 LUT3 0E c/ab\ + 1381 LUT4 0C0A DC?A:B:0:0 + 1382 LUT3 10 abC + 1383 LUT4 0EEE /ab\(d+c) + 1384 LUT4 8000 ABCD + 1385 LUT3 FE /ab\+C + 1386 LUT4 0C0A DC?A:B:0:0 + 1387 LUT4 0C0A DC?A:B:0:0 + 1388 LUT3 CA C?A:B + 1389 LUT3 CA C?A:B + 1390 LUT3 CA C?A:B + 1391 LUT3 CA C?A:B + 1392 LUT3 CA C?A:B + 1393 LUT3 CA C?A:B + 1394 LUT3 CA C?A:B + 1395 LUT4 0C0A DC?A:B:0:0 + 1396 LUT4 0C0A DC?A:B:0:0 + 1397 LUT4 0C0A DC?A:B:0:0 + 1398 LUT3 F4 (aB)+C + 1399 LUT3 4F (aB)+c + 1400 LUT2 E /ab\ + 1401 LUT3 4F (aB)+c + 1402 LUT2 E /ab\ + 1403 LUT2 E /ab\ + 1404 LUT3 4F (aB)+c + 1405 LUT2 E /ab\ + 1406 LUT3 4F (aB)+c + 1407 LUT3 4F (aB)+c + 1408 LUT2 E /ab\ + 1409 LUT2 B /aB\ + 1410 LUT2 B /aB\ + 1411 LUT2 7 /AB\ + 1412 LUT2 B /aB\ + 1413 LUT2 B /aB\ + 1414 LUT2 7 /AB\ + 1415 LUT2 B /aB\ + 1416 LUT2 B /aB\ + 1417 LUT2 7 /AB\ + 1418 LUT3 F8 (AB)+C + 1419 LUT2 B /aB\ + 1420 LUT2 B /aB\ + 1421 LUT2 7 /AB\ + 1422 LUT2 B /aB\ + 1423 LUT2 B /aB\ + 1424 LUT2 7 /AB\ + 1425 LUT2 1 ab + 1426 LUT2 1 ab + 1427 LUT2 1 ab + 1428 LUT2 1 ab + 1429 LUT2 1 ab + 1430 LUT4 8000 ABCD + 1431 LUT3 0B c/aB\ + 1432 LUT4 0B00 cD/aB\ + 1433 LUT4 0001 abcd + 1434 LUT4 030A DC?A:b:0:0 + 1435 LUT4 D000 CD/Ab\ + 1436 LUT4 4000 aBCD + 1437 LUT2 8 AB + 1438 LUT4 E800 D(AB?0:C:C:1) + 1439 LUT4 E800 D(AB?0:C:C:1) + 1440 LUT4 E800 D(AB?0:C:C:1) + 1441 LUT3 80 ABC + 1442 LUT3 F4 (aB)+C + 1443 LUT2 B /aB\ + 1444 LUT2 8 AB + 1445 LUT3 E8 AB?0:C:C:1 + 1446 LUT2 8 AB + 1447 LUT4 D400 D(AB?C:0:1:C) + 1448 LUT4 FF0E (c/ab\)+D + 1449 LUT3 F4 (aB)+C + 1450 LUT4 FFE0 (C/ab\)+D + 1451 LUT2 4 aB + 1452 LUT4 8000 ABCD + 1453 LUT3 0B c/aB\ + 1454 LUT4 0B00 cD/aB\ + 1455 LUT4 0001 abcd + 1456 LUT4 030A DC?A:b:0:0 + 1457 LUT4 D000 CD/Ab\ + 1458 LUT4 4000 aBCD + 1459 LUT2 8 AB + 1460 LUT4 E800 D(AB?0:C:C:1) + 1461 LUT4 E800 D(AB?0:C:C:1) + 1462 LUT4 E800 D(AB?0:C:C:1) + 1463 LUT3 80 ABC + 1464 LUT3 F4 (aB)+C + 1465 LUT2 B /aB\ + 1466 LUT2 8 AB + 1467 LUT3 E8 AB?0:C:C:1 + 1468 LUT2 8 AB + 1469 LUT4 D400 D(AB?C:0:1:C) + 1470 LUT4 FF0E (c/ab\)+D + 1471 LUT3 F4 (aB)+C + 1472 LUT4 FFE0 (C/ab\)+D + 1473 LUT2 4 aB + 1474 LUT4 8000 ABCD + 1475 LUT3 0B c/aB\ + 1476 LUT4 0B00 cD/aB\ + 1477 LUT4 0001 abcd + 1478 LUT4 030A DC?A:b:0:0 + 1479 LUT4 D000 CD/Ab\ + 1480 LUT4 4000 aBCD + 1481 LUT2 8 AB + 1482 LUT4 E800 D(AB?0:C:C:1) + 1483 LUT4 E800 D(AB?0:C:C:1) + 1484 LUT4 E800 D(AB?0:C:C:1) + 1485 LUT3 80 ABC + 1486 LUT3 F4 (aB)+C + 1487 LUT2 B /aB\ + 1488 LUT2 8 AB + 1489 LUT3 E8 AB?0:C:C:1 + 1490 LUT2 8 AB + 1491 LUT4 D400 D(AB?C:0:1:C) + 1492 LUT4 FF0E (c/ab\)+D + 1493 LUT3 F4 (aB)+C + 1494 LUT4 FFE0 (C/ab\)+D + 1495 LUT2 4 aB + 1496 LUT4 8000 ABCD + 1497 LUT3 0B c/aB\ + 1498 LUT4 0B00 cD/aB\ + 1499 LUT4 0001 abcd + 1500 LUT4 030A DC?A:b:0:0 + 1501 LUT4 D000 CD/Ab\ + 1502 LUT4 4000 aBCD + 1503 LUT2 8 AB + 1504 LUT4 E800 D(AB?0:C:C:1) + 1505 LUT4 E800 D(AB?0:C:C:1) + 1506 LUT4 E800 D(AB?0:C:C:1) + 1507 LUT3 80 ABC + 1508 LUT3 F4 (aB)+C + 1509 LUT2 B /aB\ + 1510 LUT2 8 AB + 1511 LUT3 E8 AB?0:C:C:1 + 1512 LUT2 8 AB + 1513 LUT4 D400 D(AB?C:0:1:C) + 1514 LUT4 FF0E (c/ab\)+D + 1515 LUT3 F4 (aB)+C + 1516 LUT4 FFE0 (C/ab\)+D + 1517 LUT2 4 aB + 1518 LUT4 8000 ABCD + 1519 LUT3 0B c/aB\ + 1520 LUT4 0B00 cD/aB\ + 1521 LUT4 0001 abcd + 1522 LUT4 030A DC?A:b:0:0 + 1523 LUT4 D000 CD/Ab\ + 1524 LUT4 4000 aBCD + 1525 LUT2 8 AB + 1526 LUT4 E800 D(AB?0:C:C:1) + 1527 LUT4 E800 D(AB?0:C:C:1) + 1528 LUT4 E800 D(AB?0:C:C:1) + 1529 LUT3 80 ABC + 1530 LUT3 F4 (aB)+C + 1531 LUT2 B /aB\ + 1532 LUT2 8 AB + 1533 LUT3 E8 AB?0:C:C:1 + 1534 LUT2 8 AB + 1535 LUT4 D400 D(AB?C:0:1:C) + 1536 LUT4 FF0E (c/ab\)+D + 1537 LUT3 F4 (aB)+C + 1538 LUT4 FFE0 (C/ab\)+D + 1539 LUT2 4 aB + 1540 LUT2 E /ab\ + 1541 LUT2 6 A^B + 1542 LUT2 6 A^B + 1543 LUT2 6 A^B + 1544 LUT2 6 A^B + 1545 LUT2 6 A^B + 1546 LUT1 1 a deleted + 1547 LUT1 1 a deleted + 1548 LUT1 1 a deleted + 1549 LUT1 1 a deleted + 1550 LUT1 1 a deleted + 1551 LUT1 1 a deleted + 1552 LUT1 1 a deleted + 1553 LUT1 1 a deleted + 1554 LUT1 1 a deleted + 1555 LUT1 1 a deleted + 1556 LUT1 1 a deleted + 1557 LUT1 1 a deleted + 1558 LUT4 9009 (a^B)(D^c) + 1559 LUT4 B00B /aB\/D^C\ + 1560 LUT4 8000 ABCD + 1561 LUT4 0BBB /aB\(d+c) + 1562 LUT4 9009 (a^B)(D^c) + 1563 LUT4 9000 CD(a^B) + 1564 LUT3 7F /AB\+c + 1565 LUT3 B0 C/aB\ + 1566 LUT4 9009 (a^B)(D^c) + 1567 LUT4 2FFF (Ab)+c+d + 1568 LUT4 9009 (a^B)(D^c) + 1569 LUT4 9000 CD(a^B) + 1570 LUT3 7F /AB\+c + 1571 LUT3 B0 C/aB\ + 1572 LUT4 9009 (a^B)(D^c) + 1573 LUT4 9000 CD(a^B) + 1574 LUT3 7F /AB\+c + 1575 LUT3 B0 C/aB\ + 1576 LUT3 1C BC?0:1:a:0 + 1577 LUT4 CAAC DC?B:A:A:B + 1578 LUT4 CACC DC?B:A:B:B + 1579 LUT3 CA C?A:B + 1580 LUT4 CFA0 DC?0:1:A:B + 1581 LUT4 FC0A DC?A:B:0:1 + 1582 LUT3 1C BC?0:1:a:0 + 1583 LUT4 CAAC DC?B:A:A:B + 1584 LUT4 CACC DC?B:A:B:B + 1585 LUT3 CA C?A:B + 1586 LUT4 CFA0 DC?0:1:A:B + 1587 LUT4 FC0A DC?A:B:0:1 + 1588 LUT3 1C BC?0:1:a:0 + 1589 LUT4 CAAC DC?B:A:A:B + 1590 LUT4 CACC DC?B:A:B:B + 1591 LUT3 CA C?A:B + 1592 LUT4 CFA0 DC?0:1:A:B + 1593 LUT4 FC0A DC?A:B:0:1 + 1594 LUT3 1C BC?0:1:a:0 + 1595 LUT4 CAAC DC?B:A:A:B + 1596 LUT4 CACC DC?B:A:B:B + 1597 LUT3 CA C?A:B + 1598 LUT4 CFA0 DC?0:1:A:B + 1599 LUT4 FC0A DC?A:B:0:1 + 1600 LUT3 1C BC?0:1:a:0 + 1601 LUT4 CAAC DC?B:A:A:B + 1602 LUT4 CACC DC?B:A:B:B + 1603 LUT3 CA C?A:B + 1604 LUT4 CFA0 DC?0:1:A:B + 1605 LUT4 FC0A DC?A:B:0:1 + 1606 LUT4 9009 (a^B)(D^c) + 1607 LUT4 9000 CD(a^B) + 1608 LUT3 7F /AB\+c diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore-corescorecore_0/corescorecore.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore-corescorecore_0/corescorecore.v new file mode 100644 index 0000000000000000000000000000000000000000..68cd408cdc26b360000936ab379cd887f85f6b9c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore-corescorecore_0/corescorecore.v @@ -0,0 +1,105 @@ +// THIS FILE IS AUTOGENERATED BY corescorecore_gen +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module corescorecore + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + +wire [39:0] tdata; +wire [4:0] tlast; +wire [4:0] tvalid; +wire [4:0] tready; + +base + #(.memfile ("core_0.hex"), + .memsize (256)) + core_0 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[7:0]), + .o_tlast (tlast[0]), + .o_tvalid (tvalid[0]), + .i_tready (tready[0])); + +base + #(.memfile ("core_1.hex"), + .memsize (256)) + core_1 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[15:8]), + .o_tlast (tlast[1]), + .o_tvalid (tvalid[1]), + .i_tready (tready[1])); + +base + #(.memfile ("core_2.hex"), + .memsize (256)) + core_2 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[23:16]), + .o_tlast (tlast[2]), + .o_tvalid (tvalid[2]), + .i_tready (tready[2])); + +base + #(.memfile ("core_3.hex"), + .memsize (256)) + core_3 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[31:24]), + .o_tlast (tlast[3]), + .o_tvalid (tvalid[3]), + .i_tready (tready[3])); + +base + #(.memfile ("core_4.hex"), + .memsize (256)) + core_4 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[39:32]), + .o_tlast (tlast[4]), + .o_tvalid (tvalid[4]), + .i_tready (tready[4])); + +axis_arb_mux + #(.S_COUNT (5), + .DATA_WIDTH (8), + .KEEP_ENABLE (0), + .KEEP_WIDTH (1), + .ID_ENABLE (0), + .ID_WIDTH (8), + .DEST_ENABLE (0), + .DEST_WIDTH (8), + .USER_ENABLE (0), + .USER_WIDTH (1), + .ARB_TYPE ("ROUND_ROBIN"), + .LSB_PRIORITY ("HIGH")) + axis_mux + (.clk (i_clk), + .rst (i_rst), + .s_axis_tdata (tdata), + .s_axis_tkeep (5'd0), + .s_axis_tvalid (tvalid), + .s_axis_tready (tready), + .s_axis_tlast (tlast), + .s_axis_tid (40'd0), + .s_axis_tdest (40'd0), + .s_axis_tuser (5'd0), + .m_axis_tdata (o_tdata), + .m_axis_tkeep (), + .m_axis_tvalid (o_tvalid), + .m_axis_tready (i_tready), + .m_axis_tlast (o_tlast), + .m_axis_tid (), + .m_axis_tdest (), + .m_axis_tuser ()); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/base.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/base.v new file mode 100644 index 0000000000000000000000000000000000000000..ba75ad9dc0c15e734cf479e693d9c6c449bf5ed7 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/base.v @@ -0,0 +1,46 @@ +module base + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + parameter memfile = ""; + parameter memsize = 8192; + + wire [31:0] wb_dat; + wire wb_we; + wire wb_stb; + wire wb_ack; + + wb2axis w2s + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wb_dat (wb_dat[8:0]), + .i_wb_we (wb_we), + .i_wb_stb (wb_stb), + .o_wb_ack (wb_ack), + .o_tdata (o_tdata), + .o_tlast (o_tlast), + .o_tvalid (o_tvalid), + .i_tready (i_tready)); + + serving + #(.memfile (memfile), + .memsize (memsize), + .WITH_CSR (0)) + serving + (.i_clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (1'b0), + + .o_wb_adr (), + .o_wb_dat (wb_dat), + .o_wb_sel (), + .o_wb_we (wb_we), + .o_wb_stb (wb_stb), + .i_wb_rdt (32'd0), + .i_wb_ack (wb_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/cc_gatemate_clock_gen.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/cc_gatemate_clock_gen.v new file mode 100644 index 0000000000000000000000000000000000000000..99398e3644c0c92d06b79ea7aa5b6462a4756d0e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/cc_gatemate_clock_gen.v @@ -0,0 +1,48 @@ +/* verilator lint_off PINMISSING */ +/* verilator lint_off ASCRANGE */ +module clkgen ( + input wire i_clk, + input wire i_rstn, + output wire o_clk_core, + output wire o_rst_core +); + +reg rst_reg1; +reg rst_reg2; + +wire o_clk_pll; +wire usr_pll_lock_1; + +CC_PLL #( + .REF_CLK("10.0"), // reference input in MHz + .OUT_CLK(5'd16), // pll output frequency in MHz + .PERF_MD("ECONOMY"), // LOWPOWER, ECONOMY, SPEED + .LOCK_REQ(1), // 0: disable, 1: enable lock request + .LOW_JITTER(1) // 0: disable, 1: enable low jitter mode +) pll_inst_ila ( + .CLK_REF(i_clk), + .CLK_FEEDBACK(1'b0), + .USR_CLK_REF(1'b0), + .USR_LOCKED_STDY_RST(1'b0), + .USR_PLL_LOCKED_STDY(), + .USR_PLL_LOCKED(usr_pll_lock_1), + .CLK270(), .CLK180(), .CLK90(), .CLK0(o_clk_pll), + .CLK_REF_OUT() +); + +// reset synchronizing +always @(posedge i_clk) begin + if(!usr_pll_lock_1 || !i_rstn) begin + rst_reg1 <= 1'b1; + rst_reg2 <= 1'b1; + end else begin + rst_reg1 <= 1'b0; + rst_reg2 <= rst_reg1; + end +end + +assign o_rst_core = rst_reg2; +assign o_clk_core = o_clk_pll; + + +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/corescore_gatemate.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/corescore_gatemate.v new file mode 100644 index 0000000000000000000000000000000000000000..74d3a414f1305550b18d2ba93001fa220caf5f04 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/corescore_gatemate.v @@ -0,0 +1,38 @@ +module corescore_gatemate + ( + input i_clk, + input i_rstn, + output wire o_uart_tx); + + wire clk; + wire o_rst; + + //Create a 16MHz clock from 10MHz using PLL + clkgen clkgen + (.i_clk (i_clk), + .i_rstn (i_rstn), + .o_clk_core(clk), + .o_rst_core(o_rst)); + + wire [7:0] tdata; + wire tlast; + wire tvalid; + wire tready; + + corescorecore corescorecore + (.i_clk (clk), + .i_rst (o_rst), + .o_tdata (tdata), + .o_tlast (tlast), + .o_tvalid (tvalid), + .i_tready (tready)); + + emitter_uart emitter + (.i_clk (clk), + .i_rst (o_rst), + .i_tdata (tdata), + .i_tvalid (tvalid), + .o_tready (tready), + .o_uart_tx (o_uart_tx)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/emitter_uart.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/emitter_uart.v new file mode 100644 index 0000000000000000000000000000000000000000..87146563eb9490b4a236e25e4bc0b1438d0aa2c0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/emitter_uart.v @@ -0,0 +1,45 @@ +/* + * emitter_uart.v : Simple UA(R)T used as emitter in CoreScore + * + * SPDX-FileCopyrightText: 2023 Olof Kindgren + * SPDX-License-Identifier: Apache-2.0 + */ + +module emitter_uart + #(parameter clk_freq_hz = 16_000_000, + parameter baud_rate = 57600) + (input wire i_clk, + input wire i_rst, + input wire [7:0] i_tdata, + input wire i_tvalid, + output reg o_tready, + output wire o_uart_tx); + + localparam START_VALUE = clk_freq_hz/baud_rate; + + localparam WIDTH = $clog2(START_VALUE); + + reg [WIDTH:0] cnt; + + reg [9:0] data; + + assign o_uart_tx = data[0] | !(|data); + + always @(posedge i_clk) begin + if (cnt[WIDTH] & !(|data)) + o_tready <= 1'b1; + else if (i_tvalid & o_tready) + o_tready <= 1'b0; + + if (o_tready | cnt[WIDTH]) + cnt <= {1'b0,START_VALUE[WIDTH-1:0]}; + else + cnt <= cnt-1; + + if (cnt[WIDTH]) + data <= {1'b0, data[9:1]}; + else if (i_tvalid & o_tready) + data <= {1'b1, i_tdata, 1'b0}; + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/wb2axis.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/wb2axis.v new file mode 100644 index 0000000000000000000000000000000000000000..10d983e13c230ac1367215aa64b7511b490590db --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/corescore_0/rtl/wb2axis.v @@ -0,0 +1,25 @@ +`default_nettype none +module wb2axis + ( + input wire i_clk, + input wire i_rst, + input wire [8:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_stb, + output reg o_wb_ack, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + always @(posedge i_clk) begin + o_wb_ack <= i_wb_stb & i_tready & !o_wb_ack; + if (i_rst) + o_wb_ack <= 1'b0; + end + + assign o_tvalid = i_wb_stb & i_wb_we & !o_wb_ack; + assign o_tdata = i_wb_dat[7:0]; + assign o_tlast = i_wb_dat[8]; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_alu.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_alu.v new file mode 100644 index 0000000000000000000000000000000000000000..b5e1164c5358ca5878f08fed3991759c7a6215f0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_alu.v @@ -0,0 +1,106 @@ +`default_nettype none +module serv_alu + ( + input wire clk, + input wire i_rst, + input wire i_en, + input wire i_cnt0, + input wire i_rs1, + input wire i_rs2, + input wire i_imm, + input wire i_op_b_rs2, + input wire i_buf, + input wire i_init, + input wire i_cnt_done, + input wire i_sub, + input wire [1:0] i_bool_op, + input wire i_cmp_eq, + input wire i_cmp_uns, + output wire o_cmp, + input wire i_shamt_en, + input wire i_sh_right, + input wire i_sh_signed, + output wire o_sh_done, + input wire [3:0] i_rd_sel, + output wire o_rd); + + wire result_add; + wire result_eq; + wire result_lt; + wire result_sh; + + reg result_lt_r; + + reg [4:0] shamt; + reg shamt_msb; + + wire shamt_ser; + wire plus_1; + + wire add_cy; + reg add_cy_r; + + wire b_inv_plus_1; + wire b_inv_plus_1_cy; + reg b_inv_plus_1_cy_r; + + wire op_b = i_op_b_rs2 ? i_rs2 : i_imm; + assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1; + + serv_shift shift + ( + .i_clk (clk), + .i_load (i_init), + .i_shamt (shamt), + .i_shamt_msb (shamt_msb), + .i_signbit (i_sh_signed & i_rs1), + .i_right (i_sh_right), + .o_done (o_sh_done), + .i_d (i_buf), + .o_q (result_sh)); + + wire add_b = i_sub ? b_inv_plus_1 : op_b; + assign {add_cy,result_add} = i_rs1+add_b+add_cy_r; + assign {b_inv_plus_1_cy,b_inv_plus_1} = {1'b0,~op_b}+plus_1+b_inv_plus_1_cy_r; + + reg lt_r; + + reg eq_r; + + wire lt_sign = i_cnt_done & !i_cmp_uns; + + wire eq = (i_rs1 == op_b); + + assign result_eq = eq & eq_r; + assign result_lt = eq ? lt_r : op_b^lt_sign; + + assign plus_1 = i_cnt0; + assign o_cmp = i_cmp_eq ? result_eq : result_lt; + + localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor + wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}]; + + assign o_rd = (i_rd_sel[0] & result_add) | + (i_rd_sel[1] & result_sh) | + (i_rd_sel[2] & result_lt_r & plus_1) | + (i_rd_sel[3] & result_bool); + + + always @(posedge clk) begin + add_cy_r <= i_en & add_cy; + b_inv_plus_1_cy_r <= i_en & b_inv_plus_1_cy; + + lt_r <= result_lt & i_en; + + if (i_en) begin + result_lt_r <= result_lt; + end + eq_r <= result_eq | ~i_en; + + if (i_shamt_en) begin + shamt_msb <= b_inv_plus_1_cy; + shamt <= {shamt_ser,shamt[4:1]}; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_bufreg.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_bufreg.v new file mode 100644 index 0000000000000000000000000000000000000000..1f8c70cd720cf2bc9a8266797ef8290b0e4dd9d4 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_bufreg.v @@ -0,0 +1,42 @@ +module serv_bufreg + ( + input wire i_clk, + input wire i_cnt0, + input wire i_cnt1, + input wire i_en, + input wire i_init, + input wire i_loop, + input wire i_rs1, + input wire i_rs1_en, + input wire i_imm, + input wire i_imm_en, + input wire i_clr_lsb, + output reg [1:0] o_lsb, + output wire [31:0] o_dbus_adr, + output wire o_q); + + wire c, q; + reg c_r; + reg [31:0] data; + + wire clr_lsb = i_cnt0 & i_clr_lsb; + + assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r; + + always @(posedge i_clk) begin + //Clear carry when not in INIT state + c_r <= c & i_init; + + if (i_en) + data <= {(i_loop & !i_init) ? o_q : q, data[31:1]}; + + if (i_cnt0 & i_init) + o_lsb[0] <= q; + if (i_cnt1 & i_init) + o_lsb[1] <= q; + end + + assign o_q = data[0]; + assign o_dbus_adr = {data[31:2], 2'b00}; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_csr.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_csr.v new file mode 100644 index 0000000000000000000000000000000000000000..897e2728f60784fe39e6819869554b10ee0aec76 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_csr.v @@ -0,0 +1,108 @@ +`default_nettype none +module serv_csr + ( + input wire i_clk, + input wire i_en, + input wire i_cnt0to3, + input wire i_cnt2, + input wire i_cnt3, + input wire i_cnt7, + input wire i_cnt_done, + input wire i_e_op, + input wire i_ebreak, + input wire i_mem_cmd, + input wire i_mem_misalign, + //From mpram + input wire i_rf_csr_out, + //to mpram + output wire o_csr_in, + //Stuff + input wire i_mtip, + output wire o_new_irq, + input wire i_pending_irq, + input wire i_trap_taken, + input wire i_mstatus_en, + input wire i_mie_en, + input wire i_mcause_en, + input wire [1:0] i_csr_source, + input wire i_mret, + input wire i_d, + output wire o_q); + +`include "serv_params.vh" + + reg mstatus; + reg mstatus_mie; + reg mstatus_mpie; + reg mie_mtie; + + reg mcause31; + reg [3:0] mcause3_0; + wire mcause; + + wire csr_in; + wire csr_out; + + reg timer_irq_r; + + assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? i_d : + (i_csr_source == CSR_SOURCE_SET) ? csr_out | i_d : + (i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~i_d : + (i_csr_source == CSR_SOURCE_CSR) ? csr_out : + 1'bx; + + assign csr_out = (i_mstatus_en & i_en & mstatus) | + i_rf_csr_out | + (i_mcause_en & i_en & mcause); + + assign o_q = csr_out; + + wire timer_irq = i_mtip & mstatus_mie & mie_mtie; + + assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0] + i_cnt_done ? mcause31 //[31] + : 1'b0; + + assign o_csr_in = csr_in; + + assign o_new_irq = !timer_irq_r & timer_irq; + + + always @(posedge i_clk) begin + /* + Note: To save resources mstatus_mpie (mstatus bit 7) is not + readable or writable from sw + */ + if (i_mstatus_en & i_cnt3) + mstatus_mie <= csr_in; + + if (i_mie_en & i_cnt7) + mie_mtie <= csr_in; + + mstatus <= i_cnt2 & mstatus_mie; + + timer_irq_r <= timer_irq; + + if (i_mret) begin + mstatus_mie <= mstatus_mpie; + end + + if (i_trap_taken) begin + mstatus_mpie <= mstatus_mie; + mstatus_mie <= 1'b0; + mcause31 <= i_pending_irq; + mcause3_0 <= i_pending_irq ? 4'd7 : + i_e_op ? {!i_ebreak, 3'b011} : + i_mem_misalign ? {2'b01, i_mem_cmd, 1'b0} : + 4'd0; + end + + if (i_mcause_en & i_en) begin + if (i_cnt0to3) + mcause3_0 <= {csr_in, mcause3_0[3:1]}; + if (i_cnt_done) + mcause31 <= csr_in; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_ctrl.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..f5899a58aa0df8db394b05decf6f46ecfd41df11 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_ctrl.v @@ -0,0 +1,87 @@ +`default_nettype none +module serv_ctrl + ( + input wire clk, + input wire i_rst, + //State + input wire i_pc_en, + input wire i_cnt12to31, + input wire i_cnt2, + input wire i_cnt_done, + //Control + input wire i_jump, + input wire i_jal_or_jalr, + input wire i_utype, + input wire i_pc_rel, + input wire i_trap, + //Data + input wire i_imm, + input wire i_buf, + input wire i_csr_pc, + output wire o_rd, + output wire o_bad_pc, + //External + output reg [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire i_ibus_ack); + + parameter RESET_PC = 32'd0; + parameter WITH_CSR = 1; + + reg en_pc_r; + + wire pc_plus_4; + wire pc_plus_4_cy; + reg pc_plus_4_cy_r; + wire pc_plus_offset; + wire pc_plus_offset_cy; + reg pc_plus_offset_cy_r; + wire pc_plus_offset_aligned; + wire plus_4; + + wire pc = o_ibus_adr[0]; + + wire new_pc; + + wire offset_a; + wire offset_b; + + assign plus_4 = i_cnt2; + + assign o_bad_pc = pc_plus_offset_aligned; + + assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r; + + generate + if (WITH_CSR) + assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4; + else + assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4; + endgenerate + assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr); + + assign offset_a = i_pc_rel & pc; + assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf; + assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r; + + assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r; + + assign o_ibus_cyc = en_pc_r & !i_pc_en; + + always @(posedge clk) begin + pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; + pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; + + if (i_pc_en) begin + en_pc_r <= 1'b1; + o_ibus_adr <= {new_pc, o_ibus_adr[31:1]}; + end else if (o_ibus_cyc & i_ibus_ack) + en_pc_r <= 1'b0; + + if (i_rst) begin + en_pc_r <= 1'b1; + o_ibus_adr <= RESET_PC; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_decode.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_decode.v new file mode 100644 index 0000000000000000000000000000000000000000..d66a1e046f47cafac6113e7d9c138c31fa82253c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_decode.v @@ -0,0 +1,239 @@ +`default_nettype none +module serv_decode + ( + input wire clk, + //Input + input wire i_cnt_en, + input wire i_cnt_done, + input wire [31:2] i_wb_rdt, + input wire i_wb_en, + input wire i_alu_cmp, + //To state + output wire o_take_branch, + output wire o_e_op, + output wire o_ebreak, + output wire o_branch_op, + output wire o_mem_op, + output wire o_shift_op, + output wire o_slt_op, + output wire o_rd_op, + //To bufreg + output wire o_bufreg_loop, + output wire o_bufreg_rs1_en, + output wire o_bufreg_imm_en, + output wire o_bufreg_clr_lsb, + //To ctrl + output wire o_ctrl_jal_or_jalr, + output wire o_ctrl_utype, + output wire o_ctrl_pc_rel, + output wire o_ctrl_mret, + //To alu + output wire o_alu_sub, + output wire [1:0] o_alu_bool_op, + output wire o_alu_cmp_eq, + output wire o_alu_cmp_uns, + output wire o_alu_sh_signed, + output wire o_alu_sh_right, + output wire [3:0] o_alu_rd_sel, + //To RF + output reg [4:0] o_rf_rd_addr, + output reg [4:0] o_rf_rs1_addr, + output reg [4:0] o_rf_rs2_addr, + //To mem IF + output wire o_mem_signed, + output wire o_mem_word, + output wire o_mem_half, + output wire o_mem_cmd, + //To CSR + output wire o_csr_en, + output wire [1:0] o_csr_addr, + output wire o_csr_mstatus_en, + output wire o_csr_mie_en, + output wire o_csr_mcause_en, + output wire [1:0] o_csr_source, + output wire o_csr_d_sel, + output wire o_csr_imm, + //To top + output wire o_imm, + output wire o_op_b_source, + output wire o_rd_csr_en, + output wire o_rd_alu_en); + +`include "serv_params.vh" + + reg [4:0] opcode; + reg [2:0] funct3; + reg op20; + reg op21; + reg op22; + reg op26; + + reg imm30; + + wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]); + + assign o_mem_op = !opcode[4] & !opcode[2] & !opcode[0]; + assign o_shift_op = op_or_opimm & (funct3[1:0] == 2'b01); + assign o_slt_op = op_or_opimm & (funct3[2:1] == 2'b01); + assign o_branch_op = opcode[4] & !opcode[2]; + + //Matches system opcodes except CSR accesses (funct3 == 0) + //No idea anymore why the !op21 condition is needed here + assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3); + + assign o_ebreak = op20; + + //jal,branch = imm + //jalr = rs1+imm + //mem = rs1+imm + //shift = rs1 + assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]); + assign o_bufreg_imm_en = !opcode[2]; + + //Loop bufreg contents for shift operations + assign o_bufreg_loop = op_or_opimm; + + //Clear LSB of immediate for BRANCH and JAL ops + //True for BRANCH and JAL + //False for JALR/LOAD/STORE/OP/OPIMM? + assign o_bufreg_clr_lsb = opcode[4] & ((opcode[1:0] == 2'b00) | (opcode[1:0] == 2'b11)); + + //Take branch for jump or branch instructions (opcode == 1x0xx) if + //a) It's an unconditional branch (opcode[0] == 1) + //b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true + //c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false + //Only valid during the last cycle of INIT, when the branch condition has + //been calculated. + assign o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^funct3[0])); + + assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0]; + assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0]; + + //True for jal, b* auipc + //False for jalr, lui + assign o_ctrl_pc_rel = (opcode[2:0] == 3'b000) | + (opcode[1:0] == 2'b11) | + (opcode[4:3] == 2'b00); + + assign o_ctrl_mret = (opcode[4] & opcode[2] & op21 & !(|funct3)); + + //Write to RD + //True for OP-IMM, AUIPC, OP, LUI, SYSTEM, JALR, JAL, LOAD + //False for STORE, BRANCH, MISC-MEM + assign o_rd_op = (opcode[2] | + (!opcode[2] & opcode[4] & opcode[0]) | + (!opcode[2] & !opcode[3] & !opcode[0])) & (|o_rf_rd_addr); + + assign o_alu_sub = opcode[3] & imm30/*alu_sub_r*/; + + /* + 300 0_000 mstatus RWSC + 304 0_100 mie SCWi + 305 0_101 mtvec RW + 340 1_000 mscratch + 341 1_001 mepc RW + 342 1_010 mcause R + 343 1_011 mtval + 344 1_100 mip CWi + */ + + //true for mtvec,mscratch,mepc and mtval + //false for mstatus, mie, mcause, mip + wire csr_valid = op20 | (op26 & !op22 & !op21); + + //Matches system ops except eceall/ebreak + wire csr_op = opcode[4] & opcode[2] & (|funct3); + assign o_rd_csr_en = csr_op; + + assign o_csr_en = csr_op & csr_valid; + assign o_csr_mstatus_en = csr_op & !op26 & !op22; + assign o_csr_mie_en = csr_op & !op26 & op22 & !op20; + assign o_csr_mcause_en = csr_op & op21 & !op20; + + assign o_csr_source = funct3[1:0]; + assign o_csr_d_sel = funct3[2]; + assign o_csr_imm = o_rf_rs1_addr[0]; + + assign o_csr_addr = (op26 & !op20) ? CSR_MSCRATCH : + (op26 & !op21) ? CSR_MEPC : + (op26) ? CSR_MTVAL : + CSR_MTVEC; + + assign o_alu_cmp_eq = funct3[2:1] == 2'b00; + + assign o_alu_cmp_uns = (funct3[0] & funct3[1]) | (funct3[1] & funct3[2]); + assign o_alu_sh_signed = imm30; + assign o_alu_sh_right = funct3[2]; + + assign o_mem_cmd = opcode[3]; + assign o_mem_signed = ~funct3[2]; + assign o_mem_word = funct3[1]; + assign o_mem_half = funct3[0]; + + assign o_alu_bool_op = funct3[1:0]; + + reg signbit; + + reg [8:0] imm19_12_20; + reg imm7; + reg [5:0] imm30_25; + reg [4:0] imm24_20; + reg [4:0] imm11_7; + + wire [1:0] m2; + //True for OP-IMM, LOAD, STORE, JALR + //False for LUI, AUIPC, JAL + assign m2[0] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00); + assign m2[1] = opcode[4] & !opcode[0]; + wire m3 = opcode[4]; + + assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub + assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift + assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT* + assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool + always @(posedge clk) begin + if (i_wb_en) begin + o_rf_rd_addr <= i_wb_rdt[11:7]; + o_rf_rs1_addr <= i_wb_rdt[19:15]; + o_rf_rs2_addr <= i_wb_rdt[24:20]; + funct3 <= i_wb_rdt[14:12]; + imm30 <= i_wb_rdt[30]; + opcode <= i_wb_rdt[6:2]; + op20 <= i_wb_rdt[20]; + op21 <= i_wb_rdt[21]; + op22 <= i_wb_rdt[22]; + op26 <= i_wb_rdt[26]; + + //Immediate decoder + signbit <= i_wb_rdt[31]; + imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]}; + imm7 <= i_wb_rdt[7]; + imm30_25 <= i_wb_rdt[30:25]; + imm24_20 <= i_wb_rdt[24:20]; + imm11_7 <= i_wb_rdt[11:7]; + end + if (i_cnt_en) begin + imm19_12_20 <= {m3 ? signbit : imm24_20[0], imm19_12_20[8:1]}; + imm7 <= signbit; + imm30_25 <= {m2[1] ? imm7 : m2[0] ? signbit : imm19_12_20[0], imm30_25[5:1]}; + imm24_20 <= {imm30_25[0], imm24_20[4:1]}; + imm11_7 <= {imm30_25[0], imm11_7[4:1]}; + if (csr_op & o_csr_d_sel) + o_rf_rs1_addr <= {1'b0,o_rf_rs1_addr[4:1]}; + end + end + + //True for S (STORE) or B (BRANCH) type instructions + //False for J type instructions + wire m1 = opcode[3:0] == 4'b1000; + + assign o_imm = i_cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]; + + //0 (OP_B_SOURCE_IMM) when OPIMM + //1 (OP_B_SOURCE_RS2) when BRANCH or OP + assign o_op_b_source = opcode[3]; + + assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4]; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_mem_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_mem_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b9ea5cb50b5b09c2119fad52b413e2dc880afdea --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_mem_if.v @@ -0,0 +1,68 @@ +`default_nettype none +module serv_mem_if + #(parameter WITH_CSR = 1) + ( + input wire i_clk, + input wire i_en, + input wire i_mem_op, + input wire i_signed, + input wire i_word, + input wire i_half, + input wire [1:0] i_bytecnt, + input wire i_rs2, + output wire o_rd, + input wire [1:0] i_lsb, + output wire o_misalign, + //External interface + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + reg signbit; + + wire [2:0] tmp = {1'b0,i_bytecnt}+{1'b0,i_lsb}; + + reg [31:0] dat; + + wire dat_en = i_en & !tmp[2]; + + wire dat_cur = + ((i_lsb == 2'd3) & dat[24]) | + ((i_lsb == 2'd2) & dat[16]) | + ((i_lsb == 2'd1) & dat[8]) | + ((i_lsb == 2'd0) & dat[0]); + + wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]); + + assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed); + + assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]); + assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word; + assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]); + assign o_wb_sel[0] = (i_lsb == 2'b00); + + assign o_wb_dat = dat; + + always @(posedge i_clk) begin + if (dat_en) + dat <= {i_rs2, dat[31:1]}; + + if (i_wb_ack) + dat <= i_wb_rdt; + + if (dat_valid) + signbit <= dat_cur; + end + generate + if (WITH_CSR) begin + reg misalign; + always @(posedge i_clk) + misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word); + assign o_misalign = misalign & i_mem_op; + end else begin + assign o_misalign = 1'b0; + end + endgenerate + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_params.vh b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_params.vh new file mode 100644 index 0000000000000000000000000000000000000000..0cf79d96ed485f0846d52efac5338c6a7d9d6552 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_params.vh @@ -0,0 +1,11 @@ +localparam [1:0] + CSR_SOURCE_CSR = 2'b00, + CSR_SOURCE_EXT = 2'b01, + CSR_SOURCE_SET = 2'b10, + CSR_SOURCE_CLR = 2'b11; + +localparam [1:0] + CSR_MSCRATCH = 2'b00, + CSR_MTVEC = 2'b01, + CSR_MEPC = 2'b10, + CSR_MTVAL = 2'b11; diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b26e75f1dba95334cfbf1eaa467facdc6833cb42 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_if.v @@ -0,0 +1,122 @@ +`default_nettype none +module serv_rf_if + #(parameter WITH_CSR = 1) + (//RF Interface + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + //Trap interface + input wire i_trap, + input wire i_mret, + input wire i_mepc, + input wire i_mem_misalign, + input wire i_bufreg_q, + input wire i_bad_pc, + output wire o_csr_pc, + //CSR interface + input wire i_csr_en, + input wire [1:0] i_csr_addr, + input wire i_csr, + output wire o_csr, + //RD write port + input wire i_rd_wen, + input wire [4:0] i_rd_waddr, + input wire i_ctrl_rd, + input wire i_alu_rd, + input wire i_rd_alu_en, + input wire i_csr_rd, + input wire i_rd_csr_en, + input wire i_mem_rd, + + //RS1 read port + input wire [4:0] i_rs1_raddr, + output wire o_rs1, + //RS2 read port + input wire [4:0] i_rs2_raddr, + output wire o_rs2); + + +`include "serv_params.vh" + + /* + ********** Write side *********** + */ + + generate + if (WITH_CSR) begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_csr_rd & i_rd_csr_en) | + (i_mem_rd); + + wire mtval = i_mem_misalign ? i_bufreg_q : i_bad_pc; + + assign o_wdata0 = i_trap ? mtval : rd; + assign o_wdata1 = i_trap ? i_mepc : i_csr; + + //port 0 rd mtval + //port 1 csr mepc + //mepc 100010 + //mtval 100011 + //csr 1000xx + //rd 0xxxxx + assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr}; + assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr}; + + assign o_wen0 = i_trap | i_rd_wen; + assign o_wen1 = i_trap | i_csr_en; + + /* + ********** Read side *********** + */ + + //0 : RS1 + //1 : RS2 / CSR + + + assign o_rreg0 = {1'b0, i_rs1_raddr}; + assign o_rreg1 = + i_trap ? {4'b1000, CSR_MTVEC} : + i_mret ? {4'b1000, CSR_MEPC} : + i_csr_en ? {4'b1000, i_csr_addr} : + {1'b0,i_rs2_raddr}; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + assign o_csr = i_rdata1 & i_csr_en; + assign o_csr_pc = i_rdata1; + + end else begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_mem_rd); + + assign o_wdata0 = rd; + assign o_wdata1 = 1'b0; + + assign o_wreg0 = i_rd_waddr; + assign o_wreg1 = 5'd0; + + assign o_wen0 =i_rd_wen; + assign o_wen1 = 1'b0; + + /* + ********** Read side *********** + */ + + assign o_rreg0 = i_rs1_raddr; + assign o_rreg1 = i_rs2_raddr; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + end // else: !if(WITH_CSR) + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..9bbc503d88e5f71471fc58603c0f87c1b127f092 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_ram.v @@ -0,0 +1,26 @@ +module serv_rf_ram + #(parameter width=0, + parameter csr_regs=4, + parameter depth=32*(32+csr_regs)/width) + (input wire i_clk, + input wire [$clog2(depth)-1:0] i_waddr, + input wire [width-1:0] i_wdata, + input wire i_wen, + input wire [$clog2(depth)-1:0] i_raddr, + output reg [width-1:0] o_rdata); + + reg [width-1:0] memory [0:depth-1]; + + always @(posedge i_clk) begin + if (i_wen) + memory[i_waddr] <= i_wdata; + o_rdata <= memory[i_raddr]; + end + +`ifdef SERV_CLEAR_RAM + integer i; + initial + for (i=0;i 2) + always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]}; + else + always @(posedge i_clk) wdata0_r <= i_wdata0; + endgenerate + + always @(posedge i_clk) begin + wen0_r <= i_wen0; + wen1_r <= i_wen1; + wreq_r <= i_wreq | rgnt; + + wdata1_r <= {i_wdata1,wdata1_r[width-1:1]}; + + if (wgo) + wcnt <= wcnt+5'd1; + + if (wreq_r) begin + wgo <= 1'b1; + end + + if (wcnt == 5'b11111) + wgo <= 1'b0; + + if (i_rst) begin + wcnt <= 5'd0; + end + end + + /* + ********** Read side *********** + */ + + reg [4:0] rcnt; + + wire rtrig0; + reg rtrig1; + + wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0; + generate if (width == 32) + assign o_raddr = rreg; + else + assign o_raddr = {rreg, rcnt[4:l2w]}; + endgenerate + + reg [width-1:0] rdata0; + reg [width-2:0] rdata1; + + assign o_rdata0 = rdata0[0]; + assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0]; + + assign rtrig0 = (rcnt[l2w-1:0] == 1); + + reg rreq_r; + + generate if (width>2) + always @(posedge i_clk) begin + rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize? + if (rtrig1) + rdata1[width-2:0] <= i_rdata[width-1:1]; + end + else + always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1]; + endgenerate + + always @(posedge i_clk) begin + rtrig1 <= rtrig0; + rcnt <= rcnt+5'd1; + if (i_rreq) + rcnt <= 5'd0; + + rreq_r <= i_rreq; + rgnt <= rreq_r; + + rdata0 <= {1'b0,rdata0[width-1:1]}; + if (rtrig0) + rdata0 <= i_rdata; + + if (i_rst) begin + rgnt <= 1'b0; + rreq_r <= 1'b0; + end + end + + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_top.v new file mode 100644 index 0000000000000000000000000000000000000000..ef0ae413261884b55b6fefb4cf18ed5e35a4905b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_rf_top.v @@ -0,0 +1,164 @@ +`default_nettype none + +module serv_rf_top + #(parameter RESET_PC = 32'd0, + parameter WITH_CSR = 1, + parameter RF_WIDTH = 2, + parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH)) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output wire rvfi_valid, + output wire [63:0] rvfi_order, + output wire [31:0] rvfi_insn, + output wire rvfi_trap, + output wire rvfi_halt, + output wire rvfi_intr, + output wire [1:0] rvfi_mode, + output wire [1:0] rvfi_ixl, + output wire [4:0] rvfi_rs1_addr, + output wire [4:0] rvfi_rs2_addr, + output wire [31:0] rvfi_rs1_rdata, + output wire [31:0] rvfi_rs2_rdata, + output wire [4:0] rvfi_rd_addr, + output wire [31:0] rvfi_rd_wdata, + output wire [31:0] rvfi_pc_rdata, + output wire [31:0] rvfi_pc_wdata, + output wire [31:0] rvfi_mem_addr, + output wire [3:0] rvfi_mem_rmask, + output wire [3:0] rvfi_mem_wmask, + output wire [31:0] rvfi_mem_rdata, + output wire [31:0] rvfi_mem_wdata, +`endif + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + localparam CSR_REGS = WITH_CSR*4; + + wire rf_wreq; + wire rf_rreq; + wire [4+WITH_CSR:0] wreg0; + wire [4+WITH_CSR:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [4+WITH_CSR:0] rreg0; + wire [4+WITH_CSR:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + wire [RF_L2D-1:0] waddr; + wire [RF_WIDTH-1:0] wdata; + wire wen; + wire [RF_L2D-1:0] raddr; + wire [RF_WIDTH-1:0] rdata; + + serv_rf_ram_if + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram_if + (.i_clk (clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_rf_ram + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram + (.i_clk (clk), + .i_waddr (waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (raddr), + .o_rdata (rdata)); + + serv_top + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_mode (rvfi_mode ), + .rvfi_ixl (rvfi_ixl ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata (rvfi_rs1_rdata), + .rvfi_rs2_rdata (rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask (rvfi_mem_rmask), + .rvfi_mem_wmask (rvfi_mem_wmask), + .rvfi_mem_rdata (rvfi_mem_rdata), + .rvfi_mem_wdata (rvfi_mem_wdata), +`endif + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_rdt (i_ibus_rdt), + .i_ibus_ack (i_ibus_ack), + + .o_dbus_adr (o_dbus_adr), + .o_dbus_dat (o_dbus_dat), + .o_dbus_sel (o_dbus_sel), + .o_dbus_we (o_dbus_we), + .o_dbus_cyc (o_dbus_cyc), + .i_dbus_rdt (i_dbus_rdt), + .i_dbus_ack (i_dbus_ack)); + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_shift.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_shift.v new file mode 100644 index 0000000000000000000000000000000000000000..70a80db813e0564f80df71c676ba266cf6055d90 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_shift.v @@ -0,0 +1,30 @@ +`default_nettype none +module serv_shift + ( + input wire i_clk, + input wire i_load, + input wire [4:0] i_shamt, + input wire i_shamt_msb, + input wire i_signbit, + input wire i_right, + output wire o_done, + input wire i_d, + output wire o_q); + + reg signbit; + reg [5:0] cnt; + reg wrapped; + + always @(posedge i_clk) begin + cnt <= cnt + 6'd1; + if (i_load) begin + cnt <= 6'd0; + signbit <= i_signbit & i_right; + end + wrapped <= cnt[5] | (i_shamt_msb & !i_right); + end + + assign o_done = (cnt[4:0] == i_shamt); + assign o_q = (i_right^wrapped) ? i_d : signbit; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_state.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_state.v new file mode 100644 index 0000000000000000000000000000000000000000..b919264f8899a6a4b9c93d9ad6bb43c149f6faa6 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_state.v @@ -0,0 +1,153 @@ +module serv_state + ( + input wire i_clk, + input wire i_rst, + input wire i_new_irq, + output wire o_trap_taken, + output reg o_pending_irq, + input wire i_dbus_ack, + input wire i_ibus_ack, + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire o_rf_rd_en, + input wire i_take_branch, + input wire i_branch_op, + input wire i_mem_op, + input wire i_shift_op, + input wire i_slt_op, + input wire i_e_op, + input wire i_rd_op, + output reg o_init, + output reg o_cnt_en, + output wire o_cnt0, + output wire o_cnt0to3, + output wire o_cnt12to31, + output wire o_cnt1, + output wire o_cnt2, + output wire o_cnt3, + output wire o_cnt7, + output wire o_ctrl_pc_en, + output reg o_ctrl_jump, + output wire o_ctrl_trap, + input wire i_ctrl_misalign, + output wire o_alu_shamt_en, + input wire i_alu_sh_done, + output wire o_dbus_cyc, + output wire [1:0] o_mem_bytecnt, + input wire i_mem_misalign, + output reg o_cnt_done, + output wire o_bufreg_hold); + + parameter WITH_CSR = 1; + + wire cnt4; + + reg stage_two_req; + + reg [4:2] o_cnt; + reg [3:0] o_cnt_r; + + //Update PC in RUN or TRAP states + assign o_ctrl_pc_en = o_cnt_en & !o_init; + + + assign o_mem_bytecnt = o_cnt[4:3]; + + assign o_cnt0to3 = (o_cnt[4:2] == 3'd0); + assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11)); + assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0]; + assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1]; + assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2]; + assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3]; + assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0]; + assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3]; + + assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init; + + + //slt*, branch/jump, shift, load/store + wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op; + + reg stage_two_pending; + + assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign; + + wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign); + + //Prepare RF for reads when a new instruction is fetched + // or when stage one caused an exception (rreq implies a write request too) + assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending); + + //Prepare RF for writes when everything is ready to enter stage two + assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending; + + assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init; + + //Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting + assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op); + + always @(posedge i_clk) begin + if (o_cnt_done) + o_ctrl_jump <= o_init & i_take_branch; + + if (o_cnt_en) + stage_two_pending <= o_init; + + o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2]; + + //Need a strobe for the first cycle in the IDLE state after INIT + stage_two_req <= o_cnt_done & o_init; + + if (i_rf_ready & !stage_two_pending) + o_init <= two_stage_op & !o_pending_irq; + + if (o_cnt_done) + o_init <= 1'b0; + + if (i_rf_ready) + o_cnt_en <= 1'b1; + + if (o_cnt_done) + o_cnt_en <= 1'b0; + + o_cnt <= o_cnt + {2'd0,o_cnt_r[3]}; + if (o_cnt_en) + o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]}; + + if (i_rst) begin + o_cnt <= 3'd0; + stage_two_pending <= 1'b0; + o_ctrl_jump <= 1'b0; + o_cnt_r <= 4'b0001; + end + end + + generate + if (WITH_CSR) begin + reg irq_sync; + reg misalign_trap_sync; + + assign o_ctrl_trap = i_e_op | o_pending_irq | misalign_trap_sync; + assign o_trap_taken = i_ibus_ack & o_ctrl_trap; + + always @(posedge i_clk) begin + if (i_ibus_ack) + irq_sync <= 1'b0; + if (i_new_irq) + irq_sync <= 1'b1; + + if (i_ibus_ack) + o_pending_irq <= irq_sync; + + if (stage_two_req) + misalign_trap_sync <= trap_pending; + if (i_ibus_ack) + misalign_trap_sync <= 1'b0; + end // always @ (posedge i_clk) + end else begin + always @(*) + o_pending_irq = 1'b0; + end + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_top.v new file mode 100644 index 0000000000000000000000000000000000000000..65b59b05bc9f9da4d8f99551ebb5fee73f9b5f26 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serv_1.0.2/rtl/serv_top.v @@ -0,0 +1,495 @@ +`default_nettype none + +module serv_top + #(parameter WITH_CSR = 1, + parameter RESET_PC = 32'd0) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output reg rvfi_valid = 1'b0, + output reg [63:0] rvfi_order = 64'd0, + output reg [31:0] rvfi_insn = 32'd0, + output reg rvfi_trap = 1'b0, + output reg rvfi_halt = 1'b0, + output reg rvfi_intr = 1'b0, + output reg [1:0] rvfi_mode = 2'b11, + output reg [1:0] rvfi_ixl = 2'b01, + output reg [4:0] rvfi_rs1_addr, + output reg [4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [3:0] rvfi_mem_rmask, + output reg [3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, +`endif + //RF Interface + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + wire [4:0] rd_addr; + wire [4:0] rs1_addr; + wire [4:0] rs2_addr; + + wire take_branch; + wire e_op; + wire ebreak; + wire branch_op; + wire mem_op; + wire shift_op; + wire slt_op; + wire rd_op; + + wire rd_alu_en; + wire rd_csr_en; + wire ctrl_rd; + wire alu_rd; + wire mem_rd; + wire csr_rd; + + wire ctrl_pc_en; + wire jump; + wire jal_or_jalr; + wire utype; + wire mret; + wire imm; + wire trap; + wire pc_rel; + + wire init; + wire cnt_en; + wire cnt0to3; + wire cnt12to31; + wire cnt0; + wire cnt1; + wire cnt2; + wire cnt3; + wire cnt7; + + wire cnt_done; + + wire bufreg_hold; + wire bufreg_rs1_en; + wire bufreg_imm_en; + wire bufreg_loop; + wire bufreg_q; + + wire alu_sub; + wire [1:0] alu_bool_op; + wire alu_cmp_eq; + wire alu_cmp_uns; + wire alu_cmp; + wire alu_shamt_en; + wire alu_sh_signed; + wire alu_sh_right; + wire alu_sh_done; + wire [3:0] alu_rd_sel; + + wire rs1; + wire rs2; + wire rd_en; + + wire op_b_source; + wire op_b; + + wire mem_signed; + wire mem_word; + wire mem_half; + wire [1:0] mem_bytecnt; + + wire mem_misalign; + + wire bad_pc; + + wire csr_mstatus_en; + wire csr_mie_en; + wire csr_mcause_en; + wire [1:0] csr_source; + wire csr_imm; + wire csr_d_sel; + wire csr_en; + wire [1:0] csr_addr; + wire csr_pc; + + + wire new_irq; + wire trap_taken; + wire pending_irq; + + wire [1:0] lsb; + + serv_state + #(.WITH_CSR (WITH_CSR)) + state + ( + .i_clk (clk), + .i_rst (i_rst), + .i_new_irq (new_irq), + .o_trap_taken (trap_taken), + .o_pending_irq (pending_irq), + .i_dbus_ack (i_dbus_ack), + .i_ibus_ack (i_ibus_ack), + .o_rf_rreq (o_rf_rreq), + .o_rf_wreq (o_rf_wreq), + .i_rf_ready (i_rf_ready), + .o_rf_rd_en (rd_en), + .i_take_branch (take_branch), + .i_branch_op (branch_op), + .i_mem_op (mem_op), + .i_shift_op (shift_op), + .i_slt_op (slt_op), + .i_e_op (e_op), + .i_rd_op (rd_op), + .o_init (init), + .o_cnt_en (cnt_en), + .o_cnt0to3 (cnt0to3), + .o_cnt12to31 (cnt12to31), + .o_cnt0 (cnt0), + .o_cnt1 (cnt1), + .o_cnt2 (cnt2), + .o_cnt3 (cnt3), + .o_cnt7 (cnt7), + .o_cnt_done (cnt_done), + .o_bufreg_hold (bufreg_hold), + .o_ctrl_pc_en (ctrl_pc_en), + .o_ctrl_jump (jump), + .o_ctrl_trap (trap), + .i_ctrl_misalign(lsb[1]), + .o_alu_shamt_en (alu_shamt_en), + .i_alu_sh_done (alu_sh_done), + .o_dbus_cyc (o_dbus_cyc), + .o_mem_bytecnt (mem_bytecnt), + .i_mem_misalign (mem_misalign)); + + wire bufreg_clr_lsb; + + serv_decode decode + ( + .clk (clk), + //Input + .i_cnt_en (cnt_en), + .i_cnt_done (cnt_done), + .i_wb_rdt (i_ibus_rdt[31:2]), + .i_wb_en (o_ibus_cyc & i_ibus_ack), + .i_alu_cmp (alu_cmp), + //To state + .o_take_branch (take_branch), + .o_e_op (e_op), + .o_ebreak (ebreak), + .o_branch_op (branch_op), + .o_mem_op (mem_op), + .o_shift_op (shift_op), + .o_slt_op (slt_op), + .o_rd_op (rd_op), + //To bufreg + .o_bufreg_loop (bufreg_loop), + .o_bufreg_rs1_en (bufreg_rs1_en), + .o_bufreg_imm_en (bufreg_imm_en), + .o_bufreg_clr_lsb (bufreg_clr_lsb), + //To ctrl + .o_ctrl_jal_or_jalr (jal_or_jalr), + .o_ctrl_utype (utype), + .o_ctrl_pc_rel (pc_rel), + .o_ctrl_mret (mret), + //To alu + .o_op_b_source (op_b_source), + .o_alu_sub (alu_sub), + .o_alu_bool_op (alu_bool_op), + .o_alu_cmp_eq (alu_cmp_eq), + .o_alu_cmp_uns (alu_cmp_uns), + .o_alu_sh_signed (alu_sh_signed), + .o_alu_sh_right (alu_sh_right), + .o_alu_rd_sel (alu_rd_sel), + //To RF + .o_rf_rd_addr (rd_addr), + .o_rf_rs1_addr (rs1_addr), + .o_rf_rs2_addr (rs2_addr), + //To mem IF + .o_mem_cmd (o_dbus_we), + .o_mem_signed (mem_signed), + .o_mem_word (mem_word), + .o_mem_half (mem_half), + //To CSR + .o_csr_en (csr_en), + .o_csr_addr (csr_addr), + .o_csr_mstatus_en (csr_mstatus_en), + .o_csr_mie_en (csr_mie_en), + .o_csr_mcause_en (csr_mcause_en), + .o_csr_source (csr_source), + .o_csr_d_sel (csr_d_sel), + .o_csr_imm (csr_imm), + //To top + .o_imm (imm), + .o_rd_csr_en (rd_csr_en), + .o_rd_alu_en (rd_alu_en)); + + serv_bufreg bufreg + ( + .i_clk (clk), + .i_cnt0 (cnt0), + .i_cnt1 (cnt1), + .i_en (!bufreg_hold), + .i_init (init), + .i_loop (bufreg_loop), + .i_rs1 (rs1), + .i_rs1_en (bufreg_rs1_en), + .i_imm (imm), + .i_imm_en (bufreg_imm_en), + .i_clr_lsb (bufreg_clr_lsb), + .o_lsb (lsb), + .o_dbus_adr (o_dbus_adr), + .o_q (bufreg_q)); + + serv_ctrl + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + ctrl + ( + .clk (clk), + .i_rst (i_rst), + //State + .i_pc_en (ctrl_pc_en), + .i_cnt12to31 (cnt12to31), + .i_cnt2 (cnt2), + .i_cnt_done (cnt_done), + //Control + .i_jump (jump), + .i_jal_or_jalr (jal_or_jalr), + .i_utype (utype), + .i_pc_rel (pc_rel), + .i_trap (trap | mret), + //Data + .i_imm (imm), + .i_buf (bufreg_q), + .i_csr_pc (csr_pc), + .o_rd (ctrl_rd), + .o_bad_pc (bad_pc), + //External + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_ack (i_ibus_ack)); + + + serv_alu alu + ( + .clk (clk), + .i_rst (i_rst), + .i_en (cnt_en), + .i_cnt0 (cnt0), + .i_rs1 (rs1), + .i_rs2 (rs2), + .i_imm (imm), + .i_op_b_rs2 (op_b_source), + .i_buf (bufreg_q), + .i_init (init), + .i_cnt_done (cnt_done), + .i_sub (alu_sub), + .i_bool_op (alu_bool_op), + .i_cmp_eq (alu_cmp_eq), + .i_cmp_uns (alu_cmp_uns), + .o_cmp (alu_cmp), + .i_shamt_en (alu_shamt_en), + .i_sh_right (alu_sh_right), + .i_sh_signed (alu_sh_signed), + .o_sh_done (alu_sh_done), + .i_rd_sel (alu_rd_sel), + .o_rd (alu_rd)); + + wire csr_in; + wire rf_csr_out; + + serv_rf_if + #(.WITH_CSR (WITH_CSR)) + rf_if + (//RF interface + .o_wreg0 (o_wreg0), + .o_wreg1 (o_wreg1), + .o_wen0 (o_wen0), + .o_wen1 (o_wen1), + .o_wdata0 (o_wdata0), + .o_wdata1 (o_wdata1), + .o_rreg0 (o_rreg0), + .o_rreg1 (o_rreg1), + .i_rdata0 (i_rdata0), + .i_rdata1 (i_rdata1), + + //Trap interface + .i_trap (trap), + .i_mret (mret), + .i_mepc (o_ibus_adr[0]), + .i_mem_misalign (mem_misalign), + .i_bufreg_q (bufreg_q), + .i_bad_pc (bad_pc), + .o_csr_pc (csr_pc), + //CSR write port + .i_csr_en (csr_en), + .i_csr_addr (csr_addr), + .i_csr (csr_in), + //RD write port + .i_rd_wen (rd_en), + .i_rd_waddr (rd_addr), + .i_ctrl_rd (ctrl_rd), + .i_alu_rd (alu_rd), + .i_rd_alu_en (rd_alu_en), + .i_csr_rd (csr_rd), + .i_rd_csr_en (rd_csr_en), + .i_mem_rd (mem_rd), + + //RS1 read port + .i_rs1_raddr (rs1_addr), + .o_rs1 (rs1), + //RS2 read port + .i_rs2_raddr (rs2_addr), + .o_rs2 (rs2), + + //CSR read port + .o_csr (rf_csr_out)); + + serv_mem_if + #(.WITH_CSR (WITH_CSR)) + mem_if + ( + .i_clk (clk), + .i_en (cnt_en), + .i_mem_op (mem_op), + .i_signed (mem_signed), + .i_word (mem_word), + .i_half (mem_half), + .i_bytecnt (mem_bytecnt), + .i_rs2 (rs2), + .o_rd (mem_rd), + .i_lsb (lsb), + .o_misalign (mem_misalign), + //External interface + .o_wb_dat (o_dbus_dat), + .o_wb_sel (o_dbus_sel), + .i_wb_rdt (i_dbus_rdt), + .i_wb_ack (i_dbus_ack)); + + generate + if (WITH_CSR) begin + serv_csr csr + ( + .i_clk (clk), + .i_en (cnt_en), + .i_cnt0to3 (cnt0to3), + .i_cnt2 (cnt2), + .i_cnt3 (cnt3), + .i_cnt7 (cnt7), + .i_cnt_done (cnt_done), + .i_e_op (e_op), + .i_ebreak (ebreak), + .i_mem_cmd (o_dbus_we), + .i_mem_misalign (mem_misalign), + .i_rf_csr_out (rf_csr_out), + .o_csr_in (csr_in), + .i_mtip (i_timer_irq), + .o_new_irq (new_irq), + .i_trap_taken (trap_taken), + .i_pending_irq (pending_irq), + .i_mstatus_en (csr_mstatus_en), + .i_mie_en (csr_mie_en ), + .i_mcause_en (csr_mcause_en ), + .i_csr_source (csr_source), + .i_mret (mret), + .i_d (csr_d_sel ? csr_imm : rs1), + .o_q (csr_rd)); + end else begin + assign csr_in = 1'b0; + assign csr_rd = 1'b0; + assign new_irq = 1'b0; + end + endgenerate + + +`ifdef RISCV_FORMAL + reg [31:0] pc = RESET_PC; + + wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en; + + always @(posedge clk) begin + rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst; + rvfi_order <= rvfi_order + {63'd0,rvfi_valid}; + if (o_ibus_cyc & i_ibus_ack) + rvfi_insn <= i_ibus_rdt; + if (o_wen0) + rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]}; + if (cnt_done & ctrl_pc_en) begin + rvfi_pc_rdata <= pc; + if (!rd_en) + rvfi_rd_addr <= 5'd0; + if (!rd_en | !(|rd_addr)) + rvfi_rd_wdata <= 32'd0; + end + rvfi_trap <= trap; + if (rvfi_valid) begin + rvfi_trap <= 1'b0; + pc <= rvfi_pc_wdata; + end + + rvfi_halt <= 1'b0; + rvfi_intr <= 1'b0; + rvfi_mode <= 2'd3; + rvfi_ixl = 2'd1; + if (i_rf_ready) begin + rvfi_rs1_addr <= rs1_addr; + rvfi_rs2_addr <= rs2_addr; + rvfi_rd_addr <= rd_addr; + end + if (rs_en) begin + rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]}; + rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]}; + end + + if (i_dbus_ack) begin + rvfi_mem_addr <= o_dbus_adr; + rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel; + rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000; + rvfi_mem_rdata <= i_dbus_rdt; + rvfi_mem_wdata <= o_dbus_dat; + end + if (i_ibus_ack) begin + rvfi_mem_rmask <= 4'b0000; + rvfi_mem_wmask <= 4'b0000; + end + end + /* verilator lint_off COMBDLY */ + always @(o_ibus_adr) + rvfi_pc_wdata <= o_ibus_adr; + /* verilator lint_on COMBDLY */ + + +`endif + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving.v new file mode 100644 index 0000000000000000000000000000000000000000..374bab40a12ffd914db04336c0c9a3516b30b556 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving.v @@ -0,0 +1,232 @@ +/* serving.v : Top-level for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving + ( + input wire i_clk, + input wire i_rst, + input wire i_timer_irq, + + output wire [31:0] o_wb_adr, + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + output wire o_wb_we , + output wire o_wb_stb, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + parameter memfile = ""; + parameter memsize = 8192; + parameter WITH_CSR = 1; + localparam regs = 32+WITH_CSR*4; + + localparam rf_width = 8; + + localparam aw = $clog2(memsize); + + wire [31:0] wb_ibus_adr; + wire wb_ibus_stb; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_ack; + + wire [31:0] wb_dbus_adr; + wire [31:0] wb_dbus_dat; + wire [3:0] wb_dbus_sel; + wire wb_dbus_we; + wire wb_dbus_stb; + wire [31:0] wb_dbus_rdt; + wire wb_dbus_ack; + + wire [31:0] wb_dmem_adr; + wire [31:0] wb_dmem_dat; + wire [3:0] wb_dmem_sel; + wire wb_dmem_we; + wire wb_dmem_stb; + wire [31:0] wb_dmem_rdt; + wire wb_dmem_ack; + + wire [31:0] wb_mem_adr; + wire [31:0] wb_mem_dat; + wire [3:0] wb_mem_sel; + wire wb_mem_we; + wire wb_mem_stb; + wire [31:0] wb_mem_rdt; + wire wb_mem_ack; + + wire [6+WITH_CSR:0] waddr; + wire [rf_width-1:0] wdata; + wire wen; + wire [6+WITH_CSR:0] raddr; + wire [rf_width-1:0] rdata; + + + wire [aw-1:0] rf_waddr = ~{{aw-2-5-WITH_CSR{1'b0}},waddr}; + wire [aw-1:0] rf_raddr = ~{{aw-2-5-WITH_CSR{1'b0}},raddr}; + + serving_arbiter arbiter + (.i_wb_cpu_dbus_adr (wb_dmem_adr), + .i_wb_cpu_dbus_dat (wb_dmem_dat), + .i_wb_cpu_dbus_sel (wb_dmem_sel), + .i_wb_cpu_dbus_we (wb_dmem_we ), + .i_wb_cpu_dbus_stb (wb_dmem_stb), + .o_wb_cpu_dbus_rdt (wb_dmem_rdt), + .o_wb_cpu_dbus_ack (wb_dmem_ack), + + .i_wb_cpu_ibus_adr (wb_ibus_adr), + .i_wb_cpu_ibus_stb (wb_ibus_stb), + .o_wb_cpu_ibus_rdt (wb_ibus_rdt), + .o_wb_cpu_ibus_ack (wb_ibus_ack), + + .o_wb_mem_adr (wb_mem_adr), + .o_wb_mem_dat (wb_mem_dat), + .o_wb_mem_sel (wb_mem_sel), + .o_wb_mem_we (wb_mem_we ), + .o_wb_mem_stb (wb_mem_stb), + .i_wb_mem_rdt (wb_mem_rdt), + .i_wb_mem_ack (wb_mem_ack)); + + serving_mux mux + (.i_clk (i_clk), + .i_rst (i_rst), + + .i_wb_cpu_adr (wb_dbus_adr), + .i_wb_cpu_dat (wb_dbus_dat), + .i_wb_cpu_sel (wb_dbus_sel), + .i_wb_cpu_we (wb_dbus_we), + .i_wb_cpu_stb (wb_dbus_stb), + .o_wb_cpu_rdt (wb_dbus_rdt), + .o_wb_cpu_ack (wb_dbus_ack), + + .o_wb_mem_adr (wb_dmem_adr), + .o_wb_mem_dat (wb_dmem_dat), + .o_wb_mem_sel (wb_dmem_sel), + .o_wb_mem_we (wb_dmem_we), + .o_wb_mem_stb (wb_dmem_stb), + .i_wb_mem_rdt (wb_dmem_rdt), + .i_wb_mem_ack (wb_dmem_ack), + + .o_wb_ext_adr (o_wb_adr), + .o_wb_ext_dat (o_wb_dat), + .o_wb_ext_sel (o_wb_sel), + .o_wb_ext_we (o_wb_we), + .o_wb_ext_stb (o_wb_stb), + .i_wb_ext_rdt (i_wb_rdt), + .i_wb_ext_ack (i_wb_ack)); + + serving_ram + #(.memfile (memfile), + .depth (memsize)) + ram + (// Wishbone interface + .i_clk (i_clk), + .i_waddr (rf_waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (rf_raddr), + .o_rdata (rdata), + .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), + .i_wb_stb (wb_mem_stb), + .i_wb_we (wb_mem_we) , + .i_wb_sel (wb_mem_sel), + .i_wb_dat (wb_mem_dat), + .o_wb_rdt (wb_mem_rdt), + .o_wb_ack (wb_mem_ack)); + + localparam RF_L2W = $clog2(rf_width); + + wire rf_wreq; + wire rf_rreq; + wire [$clog2(regs)-1:0] wreg0; + wire [$clog2(regs)-1:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [$clog2(regs)-1:0] rreg0; + wire [$clog2(regs)-1:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + + serv_rf_ram_if + #(.width (rf_width), + .csr_regs (WITH_CSR*4)) + rf_ram_if + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_top + #(.RESET_PC (32'h0000_0000), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), + //RF IF + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + //Instruction bus + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_stb), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + //Data bus + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_stb), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_arbiter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..9d537d4a46297b5f8902f134ada0dcba4a8cae2d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_arbiter.v @@ -0,0 +1,57 @@ +/* serving_arbiter.v : I/D arbiter for the serving SoC + * Relies on the fact that not both masters are active at the same time + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_arbiter + ( + input wire [31:0] i_wb_cpu_dbus_adr, + input wire [31:0] i_wb_cpu_dbus_dat, + input wire [3:0] i_wb_cpu_dbus_sel, + input wire i_wb_cpu_dbus_we, + input wire i_wb_cpu_dbus_stb, + output wire [31:0] o_wb_cpu_dbus_rdt, + output wire o_wb_cpu_dbus_ack, + + input wire [31:0] i_wb_cpu_ibus_adr, + input wire i_wb_cpu_ibus_stb, + output wire [31:0] o_wb_cpu_ibus_rdt, + output wire o_wb_cpu_ibus_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack); + + assign o_wb_cpu_dbus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_dbus_ack = i_wb_mem_ack & !i_wb_cpu_ibus_stb; + + assign o_wb_cpu_ibus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_ibus_ack = i_wb_mem_ack & i_wb_cpu_ibus_stb; + + assign o_wb_mem_adr = i_wb_cpu_ibus_stb ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr; + assign o_wb_mem_dat = i_wb_cpu_dbus_dat; + assign o_wb_mem_sel = i_wb_cpu_dbus_sel; + assign o_wb_mem_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_stb; + assign o_wb_mem_stb = i_wb_cpu_ibus_stb | i_wb_cpu_dbus_stb; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..daa1be8e3a714496eb611905cd1070f3f4610548 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_mux.v @@ -0,0 +1,66 @@ +/* serving_mux.v : Simple Wishbone mux for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_mux + ( + input wire i_clk, + input wire i_rst, + + input wire [31:0] i_wb_cpu_adr, + input wire [31:0] i_wb_cpu_dat, + input wire [3:0] i_wb_cpu_sel, + input wire i_wb_cpu_we, + input wire i_wb_cpu_stb, + output wire [31:0] o_wb_cpu_rdt, + output wire o_wb_cpu_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack, + + output wire [31:0] o_wb_ext_adr, + output wire [31:0] o_wb_ext_dat, + output wire [3:0] o_wb_ext_sel, + output wire o_wb_ext_we, + output wire o_wb_ext_stb, + input wire [31:0] i_wb_ext_rdt, + input wire i_wb_ext_ack); + + wire ext = (i_wb_cpu_adr[31:30] != 2'b00); + + assign o_wb_cpu_rdt = ext ? i_wb_ext_rdt : i_wb_mem_rdt; + assign o_wb_cpu_ack = ext ? i_wb_ext_ack : i_wb_mem_ack; + + assign o_wb_mem_adr = i_wb_cpu_adr; + assign o_wb_mem_dat = i_wb_cpu_dat; + assign o_wb_mem_sel = i_wb_cpu_sel; + assign o_wb_mem_we = i_wb_cpu_we; + assign o_wb_mem_stb = i_wb_cpu_stb & !ext; + + assign o_wb_ext_adr = i_wb_cpu_adr; + assign o_wb_ext_dat = i_wb_cpu_dat; + assign o_wb_ext_sel = i_wb_cpu_sel; + assign o_wb_ext_we = i_wb_cpu_we; + assign o_wb_ext_stb = i_wb_cpu_stb & ext; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..b58c22458ee44e8055be281376ce33697b624b79 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/serving_1.0.2/serving/serving_ram.v @@ -0,0 +1,83 @@ +/* serving_ram.v : Shared RF I/D SRAM for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving_ram + #(//Memory parameters + parameter depth = 256, + parameter aw = $clog2(depth), + parameter memfile = "") + (input wire i_clk, + input wire [aw-1:0] i_waddr, + input wire [7:0] i_wdata, + input wire i_wen, + input wire [aw-1:0] i_raddr, + output wire [7:0] o_rdata, + + input wire [aw-1:2] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire [3:0] i_wb_sel, + input wire i_wb_we, + input wire i_wb_stb, + output wire [31:0] o_wb_rdt, + output reg o_wb_ack); + + wire wb_en = i_wb_stb & !i_wen & !o_wb_ack; + + wire wb_we = i_wb_we & i_wb_sel[bsel]; + + wire we = wb_en ? wb_we : i_wen; + + reg [7:0] mem [0:depth-1] /* verilator public */; + + wire [aw-1:0] waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_waddr; + wire [7:0] wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata; + wire [aw-1:0] raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr; + + reg [2:0] wb_en_r; + + reg [1:0] bsel; + + reg [23:0] wb_rdt; + assign o_wb_rdt = {rdata, wb_rdt}; + + always @(posedge i_clk) begin + if (wb_en) bsel <= bsel + 2'd1; + wb_en_r <= {wb_en_r[1:0], wb_en}; + o_wb_ack <= wb_en & &bsel; + if (bsel == 2'b01) wb_rdt[7:0] <= rdata; + if (bsel == 2'b10) wb_rdt[15:8] <= rdata; + if (bsel == 2'b11) wb_rdt[23:16] <= rdata; + end + + reg [7:0] rdata; + + always @(posedge i_clk) begin + if (we) mem[waddr] <= wdata; + rdata <= mem[raddr]; + end + + initial + if(|memfile) begin + $display("Preloading %m from %s", memfile); + $readmemh(memfile, mem); + end + + assign o_rdata = rdata; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/arbiter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..3612fc45948a4e436e9d4333f8edc8ab4af79c75 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/arbiter.v @@ -0,0 +1,153 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Arbiter module + */ +module arbiter # +( + parameter PORTS = 4, + // arbitration type: "PRIORITY" or "ROUND_ROBIN" + parameter TYPE = "PRIORITY", + // block type: "NONE", "REQUEST", "ACKNOWLEDGE" + parameter BLOCK = "NONE", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" +) +( + input wire clk, + input wire rst, + + input wire [PORTS-1:0] request, + input wire [PORTS-1:0] acknowledge, + + output wire [PORTS-1:0] grant, + output wire grant_valid, + output wire [$clog2(PORTS)-1:0] grant_encoded +); + +reg [PORTS-1:0] grant_reg = 0, grant_next; +reg grant_valid_reg = 0, grant_valid_next; +reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next; + +assign grant_valid = grant_valid_reg; +assign grant = grant_reg; +assign grant_encoded = grant_encoded_reg; + +wire request_valid; +wire [$clog2(PORTS)-1:0] request_index; +wire [PORTS-1:0] request_mask; + +priority_encoder #( + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) +) +priority_encoder_inst ( + .input_unencoded(request), + .output_valid(request_valid), + .output_encoded(request_index), + .output_unencoded(request_mask) +); + +reg [PORTS-1:0] mask_reg = 0, mask_next; + +wire masked_request_valid; +wire [$clog2(PORTS)-1:0] masked_request_index; +wire [PORTS-1:0] masked_request_mask; + +priority_encoder #( + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) +) +priority_encoder_masked ( + .input_unencoded(request & mask_reg), + .output_valid(masked_request_valid), + .output_encoded(masked_request_index), + .output_unencoded(masked_request_mask) +); + +always @* begin + grant_next = 0; + grant_valid_next = 0; + grant_encoded_next = 0; + mask_next = mask_reg; + + if (BLOCK == "REQUEST" && |(grant_reg & request)) begin + // granted request still asserted; hold it + grant_valid_next = grant_valid_reg; + grant_next = grant_reg; + grant_encoded_next = grant_encoded_reg; + end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(|(grant_reg & acknowledge))) begin + // granted request not yet acknowledged; hold it + grant_valid_next = grant_valid_reg; + grant_next = grant_reg; + grant_encoded_next = grant_encoded_reg; + end else if (request_valid) begin + if (TYPE == "PRIORITY") begin + grant_valid_next = 1; + grant_next = request_mask; + grant_encoded_next = request_index; + end else if (TYPE == "ROUND_ROBIN") begin + if (masked_request_valid) begin + grant_valid_next = 1; + grant_next = masked_request_mask; + grant_encoded_next = masked_request_index; + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index); + end else begin + mask_next = {PORTS{1'b1}} << (masked_request_index + 1); + end + end else begin + grant_valid_next = 1; + grant_next = request_mask; + grant_encoded_next = request_index; + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - request_index); + end else begin + mask_next = {PORTS{1'b1}} << (request_index + 1); + end + end + end + end +end + +always @(posedge clk) begin + if (rst) begin + grant_reg <= 0; + grant_valid_reg <= 0; + grant_encoded_reg <= 0; + mask_reg <= 0; + end else begin + grant_reg <= grant_next; + grant_valid_reg <= grant_valid_next; + grant_encoded_reg <= grant_encoded_next; + mask_reg <= mask_next; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/axis_arb_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/axis_arb_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..56b9cc8d8eabb5cad59561fb27a24586f347bbc8 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/axis_arb_mux.v @@ -0,0 +1,249 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * AXI4-Stream arbitrated multiplexer + */ +module axis_arb_mux # +( + // Number of AXI stream inputs + parameter S_COUNT = 4, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = (DATA_WIDTH/8), + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // arbitration type: "PRIORITY" or "ROUND_ROBIN" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" +) +( + input wire clk, + input wire rst, + + /* + * AXI Stream inputs + */ + input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata, + input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep, + input wire [S_COUNT-1:0] s_axis_tvalid, + output wire [S_COUNT-1:0] s_axis_tready, + input wire [S_COUNT-1:0] s_axis_tlast, + input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid, + input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest, + input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI Stream output + */ + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser +); + +parameter CL_S_COUNT = $clog2(S_COUNT); + +wire [S_COUNT-1:0] request; +wire [S_COUNT-1:0] acknowledge; +wire [S_COUNT-1:0] grant; +wire grant_valid; +wire [CL_S_COUNT-1:0] grant_encoded; + +// internal datapath +reg [DATA_WIDTH-1:0] m_axis_tdata_int; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; +reg m_axis_tvalid_int; +reg m_axis_tready_int_reg = 1'b0; +reg m_axis_tlast_int; +reg [ID_WIDTH-1:0] m_axis_tid_int; +reg [DEST_WIDTH-1:0] m_axis_tdest_int; +reg [USER_WIDTH-1:0] m_axis_tuser_int; +wire m_axis_tready_int_early; + +assign s_axis_tready = {{S_COUNT-1{1'b0}},(m_axis_tready_int_reg && grant_valid)} << grant_encoded; + +// mux for incoming packet +wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH]; +wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH]; +wire current_s_tvalid = s_axis_tvalid[grant_encoded]; +wire current_s_tready = s_axis_tready[grant_encoded]; +wire current_s_tlast = s_axis_tlast[grant_encoded]; +wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH]; +wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; +wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; + +// arbiter instance +arbiter #( + .PORTS(S_COUNT), + .TYPE(ARB_TYPE), + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) +) +arb_inst ( + .clk(clk), + .rst(rst), + .request(request), + .acknowledge(acknowledge), + .grant(grant), + .grant_valid(grant_valid), + .grant_encoded(grant_encoded) +); + +assign request = s_axis_tvalid & ~grant; +assign acknowledge = grant & s_axis_tvalid & s_axis_tready & s_axis_tlast; + +always @* begin + // pass through selected packet data + m_axis_tdata_int = current_s_tdata; + m_axis_tkeep_int = current_s_tkeep; + m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid; + m_axis_tlast_int = current_s_tlast; + m_axis_tid_int = current_s_tid; + m_axis_tdest_int = current_s_tdest; + m_axis_tuser_int = current_s_tuser; +end + +// output datapath logic +reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; +reg m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; +reg temp_m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +// datapath control +reg store_axis_int_to_output; +reg store_axis_int_to_temp; +reg store_axis_temp_to_output; + +assign m_axis_tdata = m_axis_tdata_reg; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; +assign m_axis_tvalid = m_axis_tvalid_reg; +assign m_axis_tlast = m_axis_tlast_reg; +assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); + +always @* begin + // transfer sink ready state to source + m_axis_tvalid_next = m_axis_tvalid_reg; + temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_axis_temp_to_output = 1'b0; + + if (m_axis_tready_int_reg) begin + // input is ready + if (m_axis_tready || !m_axis_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_axis_tready) begin + // input is not ready, but output is ready + m_axis_tvalid_next = temp_m_axis_tvalid_reg; + temp_m_axis_tvalid_next = 1'b0; + store_axis_temp_to_output = 1'b1; + end +end + +always @(posedge clk) begin + if (rst) begin + m_axis_tvalid_reg <= 1'b0; + m_axis_tready_int_reg <= 1'b0; + temp_m_axis_tvalid_reg <= 1'b0; + end else begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + m_axis_tready_int_reg <= m_axis_tready_int_early; + temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; + end + + // datapath + if (store_axis_int_to_output) begin + m_axis_tdata_reg <= m_axis_tdata_int; + m_axis_tkeep_reg <= m_axis_tkeep_int; + m_axis_tlast_reg <= m_axis_tlast_int; + m_axis_tid_reg <= m_axis_tid_int; + m_axis_tdest_reg <= m_axis_tdest_int; + m_axis_tuser_reg <= m_axis_tuser_int; + end else if (store_axis_temp_to_output) begin + m_axis_tdata_reg <= temp_m_axis_tdata_reg; + m_axis_tkeep_reg <= temp_m_axis_tkeep_reg; + m_axis_tlast_reg <= temp_m_axis_tlast_reg; + m_axis_tid_reg <= temp_m_axis_tid_reg; + m_axis_tdest_reg <= temp_m_axis_tdest_reg; + m_axis_tuser_reg <= temp_m_axis_tuser_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_axis_tdata_reg <= m_axis_tdata_int; + temp_m_axis_tkeep_reg <= m_axis_tkeep_int; + temp_m_axis_tlast_reg <= m_axis_tlast_int; + temp_m_axis_tid_reg <= m_axis_tid_int; + temp_m_axis_tdest_reg <= m_axis_tdest_int; + temp_m_axis_tuser_reg <= m_axis_tuser_int; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/axis_async_fifo.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/axis_async_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..39ac3498d5b4ac6b5a395831d85d82f0441798ff --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/axis_async_fifo.v @@ -0,0 +1,538 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * AXI4-Stream asynchronous FIFO + */ +module axis_async_fifo # +( + // FIFO depth in words + // KEEP_WIDTH words per cycle if KEEP_ENABLE set + // Rounded up to nearest power of 2 cycles + parameter DEPTH = 4096, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + // If disabled, tkeep assumed to be 1'b1 + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = (DATA_WIDTH/8), + // Propagate tlast signal + parameter LAST_ENABLE = 1, + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // Frame FIFO mode - operate on frames instead of cycles + // When set, m_axis_tvalid will not be deasserted within a frame + // Requires LAST_ENABLE set + parameter FRAME_FIFO = 0, + // tuser value for bad frame marker + parameter USER_BAD_FRAME_VALUE = 1'b1, + // tuser mask for bad frame marker + parameter USER_BAD_FRAME_MASK = 1'b1, + // Drop frames marked bad + // Requires FRAME_FIFO set + parameter DROP_BAD_FRAME = 0, + // Drop incoming frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO set + parameter DROP_WHEN_FULL = 0 +) +( + /* + * Common asynchronous reset + */ + input wire async_rst, + + /* + * AXI input + */ + input wire s_clk, + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI output + */ + input wire m_clk, + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser, + + /* + * Status + */ + output wire s_status_overflow, + output wire s_status_bad_frame, + output wire s_status_good_frame, + output wire m_status_overflow, + output wire m_status_bad_frame, + output wire m_status_good_frame +); + +parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH); + +// check configuration +initial begin + if (FRAME_FIFO && !LAST_ENABLE) begin + $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && !FRAME_FIFO) begin + $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)"); + $finish; + end + + if (DROP_WHEN_FULL && !FRAME_FIFO) begin + $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin + $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); + $finish; + end +end + +localparam KEEP_OFFSET = DATA_WIDTH; +localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0); +localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0); +localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0); +localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); +localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); + +reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next; +reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next; +reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next; +reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_sync_gray_next; +reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_gray_next; +reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next; +reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next; +reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}}; + +reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; + +reg wr_ptr_update_valid_reg = 1'b0, wr_ptr_update_valid_next; +reg wr_ptr_update_reg = 1'b0, wr_ptr_update_next; +reg wr_ptr_update_sync1_reg = 1'b0; +reg wr_ptr_update_sync2_reg = 1'b0; +reg wr_ptr_update_sync3_reg = 1'b0; +reg wr_ptr_update_ack_sync1_reg = 1'b0; +reg wr_ptr_update_ack_sync2_reg = 1'b0; + +reg s_rst_sync1_reg = 1'b1; +reg s_rst_sync2_reg = 1'b1; +reg s_rst_sync3_reg = 1'b1; +reg m_rst_sync1_reg = 1'b1; +reg m_rst_sync2_reg = 1'b1; +reg m_rst_sync3_reg = 1'b1; + +reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; +reg [WIDTH-1:0] mem_read_data_reg; +reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; + +wire [WIDTH-1:0] s_axis; + +reg [WIDTH-1:0] m_axis_reg; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; + +// full when first TWO MSBs do NOT match, but rest matches +// (gray code equivalent of first MSB different but rest same) +wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && + (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && + (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); +wire full_cur = ((wr_ptr_cur_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && + (wr_ptr_cur_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && + (wr_ptr_cur_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); +// empty when pointers match exactly +wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg); +// overflow within packet +wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) && + (wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0])); + +// control signals +reg write; +reg read; +reg store_output; + +reg drop_frame_reg = 1'b0, drop_frame_next; +reg overflow_reg = 1'b0, overflow_next; +reg bad_frame_reg = 1'b0, bad_frame_next; +reg good_frame_reg = 1'b0, good_frame_next; + +reg overflow_sync1_reg = 1'b0; +reg overflow_sync2_reg = 1'b0; +reg overflow_sync3_reg = 1'b0; +reg overflow_sync4_reg = 1'b0; +reg bad_frame_sync1_reg = 1'b0; +reg bad_frame_sync2_reg = 1'b0; +reg bad_frame_sync3_reg = 1'b0; +reg bad_frame_sync4_reg = 1'b0; +reg good_frame_sync1_reg = 1'b0; +reg good_frame_sync2_reg = 1'b0; +reg good_frame_sync3_reg = 1'b0; +reg good_frame_sync4_reg = 1'b0; + +assign s_axis_tready = (FRAME_FIFO ? (!full_cur || full_wr || DROP_WHEN_FULL) : !full) && !s_rst_sync3_reg; + +generate + assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; + if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; + if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast; + if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; + if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; + if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; +endgenerate + +assign m_axis_tvalid = m_axis_tvalid_reg; + +assign m_axis_tdata = m_axis_reg[DATA_WIDTH-1:0]; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; +assign m_axis_tlast = LAST_ENABLE ? m_axis_reg[LAST_OFFSET] : 1'b1; +assign m_axis_tid = ID_ENABLE ? m_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; + +assign s_status_overflow = overflow_reg; +assign s_status_bad_frame = bad_frame_reg; +assign s_status_good_frame = good_frame_reg; + +assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg; +assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg; +assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg; + +// reset synchronization +always @(posedge s_clk or posedge async_rst) begin + if (async_rst) begin + s_rst_sync1_reg <= 1'b1; + s_rst_sync2_reg <= 1'b1; + s_rst_sync3_reg <= 1'b1; + end else begin + s_rst_sync1_reg <= 1'b0; + s_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg; + s_rst_sync3_reg <= s_rst_sync2_reg; + end +end + +always @(posedge m_clk or posedge async_rst) begin + if (async_rst) begin + m_rst_sync1_reg <= 1'b1; + m_rst_sync2_reg <= 1'b1; + m_rst_sync3_reg <= 1'b1; + end else begin + m_rst_sync1_reg <= 1'b0; + m_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg; + m_rst_sync3_reg <= m_rst_sync2_reg; + end +end + +// Write logic +always @* begin + write = 1'b0; + + drop_frame_next = drop_frame_reg; + overflow_next = 1'b0; + bad_frame_next = 1'b0; + good_frame_next = 1'b0; + + wr_ptr_next = wr_ptr_reg; + wr_ptr_cur_next = wr_ptr_cur_reg; + wr_ptr_gray_next = wr_ptr_gray_reg; + wr_ptr_sync_gray_next = wr_ptr_sync_gray_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_gray_reg; + + wr_ptr_update_valid_next = wr_ptr_update_valid_reg; + wr_ptr_update_next = wr_ptr_update_reg; + + if (FRAME_FIFO && wr_ptr_update_valid_reg) begin + // have updated pointer to sync + if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_next = 1'b0; + wr_ptr_sync_gray_next = wr_ptr_gray_reg; + wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg; + end + end + + if (s_axis_tready && s_axis_tvalid) begin + // transfer in + if (!FRAME_FIFO) begin + // normal FIFO mode + write = 1'b1; + wr_ptr_next = wr_ptr_reg + 1; + wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); + end else if (full_cur || full_wr || drop_frame_reg) begin + // full, packet overflow, or currently dropping frame + // drop frame + drop_frame_next = 1'b1; + if (s_axis_tlast) begin + // end of frame, reset write pointer + wr_ptr_cur_next = wr_ptr_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + drop_frame_next = 1'b0; + overflow_next = 1'b1; + end + end else begin + write = 1'b1; + wr_ptr_cur_next = wr_ptr_cur_reg + 1; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + if (s_axis_tlast) begin + // end of frame + if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin + // bad packet, reset write pointer + wr_ptr_cur_next = wr_ptr_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + bad_frame_next = 1'b1; + end else begin + // good packet, update write pointer + wr_ptr_next = wr_ptr_cur_reg + 1; + wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); + + if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_next = 1'b0; + wr_ptr_sync_gray_next = wr_ptr_gray_next; + wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg; + end else begin + // sync in progress; flag it for later + wr_ptr_update_valid_next = 1'b1; + end + + good_frame_next = 1'b1; + end + end + end + end +end + +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_update_reg <= 1'b0; + + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b0; + bad_frame_reg <= 1'b0; + good_frame_reg <= 1'b0; + end else begin + wr_ptr_reg <= wr_ptr_next; + wr_ptr_cur_reg <= wr_ptr_cur_next; + wr_ptr_gray_reg <= wr_ptr_gray_next; + wr_ptr_sync_gray_reg <= wr_ptr_sync_gray_next; + wr_ptr_cur_gray_reg <= wr_ptr_cur_gray_next; + + wr_ptr_update_valid_reg <= wr_ptr_update_valid_next; + wr_ptr_update_reg <= wr_ptr_update_next; + + drop_frame_reg <= drop_frame_next; + overflow_reg <= overflow_next; + bad_frame_reg <= bad_frame_next; + good_frame_reg <= good_frame_next; + end + + if (FRAME_FIFO) begin + wr_addr_reg <= wr_ptr_cur_next; + end else begin + wr_addr_reg <= wr_ptr_next; + end + + if (write) begin + mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= s_axis; + end +end + +// pointer synchronization +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}}; + rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_update_ack_sync1_reg <= 1'b0; + wr_ptr_update_ack_sync2_reg <= 1'b0; + end else begin + rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg; + rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg; + wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg; + wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_update_sync1_reg <= 1'b0; + wr_ptr_update_sync2_reg <= 1'b0; + wr_ptr_update_sync3_reg <= 1'b0; + end else begin + if (!FRAME_FIFO) begin + wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg; + end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin + wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg; + end + wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg; + wr_ptr_update_sync1_reg <= wr_ptr_update_reg; + wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg; + wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg; + end +end + +// status synchronization +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + overflow_sync1_reg <= 1'b0; + bad_frame_sync1_reg <= 1'b0; + good_frame_sync1_reg <= 1'b0; + end else begin + overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg; + bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg; + good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + overflow_sync2_reg <= 1'b0; + overflow_sync3_reg <= 1'b0; + overflow_sync4_reg <= 1'b0; + bad_frame_sync2_reg <= 1'b0; + bad_frame_sync3_reg <= 1'b0; + bad_frame_sync4_reg <= 1'b0; + good_frame_sync2_reg <= 1'b0; + good_frame_sync3_reg <= 1'b0; + good_frame_sync4_reg <= 1'b0; + end else begin + overflow_sync2_reg <= overflow_sync1_reg; + overflow_sync3_reg <= overflow_sync2_reg; + overflow_sync4_reg <= overflow_sync3_reg; + bad_frame_sync2_reg <= bad_frame_sync1_reg; + bad_frame_sync3_reg <= bad_frame_sync2_reg; + bad_frame_sync4_reg <= bad_frame_sync3_reg; + good_frame_sync2_reg <= good_frame_sync1_reg; + good_frame_sync3_reg <= good_frame_sync2_reg; + good_frame_sync4_reg <= good_frame_sync3_reg; + end +end + +// Read logic +always @* begin + read = 1'b0; + + rd_ptr_next = rd_ptr_reg; + rd_ptr_gray_next = rd_ptr_gray_reg; + + mem_read_data_valid_next = mem_read_data_valid_reg; + + if (store_output || !mem_read_data_valid_reg) begin + // output data not valid OR currently being transferred + if (!empty) begin + // not empty, perform read + read = 1'b1; + mem_read_data_valid_next = 1'b1; + rd_ptr_next = rd_ptr_reg + 1; + rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1); + end else begin + // empty, invalidate + mem_read_data_valid_next = 1'b0; + end + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + mem_read_data_valid_reg <= 1'b0; + end else begin + rd_ptr_reg <= rd_ptr_next; + rd_ptr_gray_reg <= rd_ptr_gray_next; + mem_read_data_valid_reg <= mem_read_data_valid_next; + end + + rd_addr_reg <= rd_ptr_next; + + if (read) begin + mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]]; + end +end + +// Output register +always @* begin + store_output = 1'b0; + + m_axis_tvalid_next = m_axis_tvalid_reg; + + if (m_axis_tready || !m_axis_tvalid) begin + store_output = 1'b1; + m_axis_tvalid_next = mem_read_data_valid_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + m_axis_tvalid_reg <= 1'b0; + end else begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + end + + if (store_output) begin + m_axis_reg <= mem_read_data_reg; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/priority_encoder.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/priority_encoder.v new file mode 100644 index 0000000000000000000000000000000000000000..6d7f31b5ec28e0db6ab77f2179bedd69d547003d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/cc_gatemate-gatemate/src/verilog-axis_0-r3/rtl/priority_encoder.v @@ -0,0 +1,100 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Priority encoder module + */ +module priority_encoder # +( + parameter WIDTH = 4, + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" +) +( + input wire [WIDTH-1:0] input_unencoded, + output wire output_valid, + output wire [$clog2(WIDTH)-1:0] output_encoded, + output wire [WIDTH-1:0] output_unencoded +); + +// power-of-two width +parameter W1 = 2**$clog2(WIDTH); +parameter W2 = W1/2; + +generate + if (WIDTH == 1) begin + // one input + assign output_valid = input_unencoded; + assign output_encoded = 0; + end else if (WIDTH == 2) begin + // two inputs - just an OR gate + assign output_valid = |input_unencoded; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = input_unencoded[1]; + end else begin + assign output_encoded = ~input_unencoded[0]; + end + end else begin + // more than two inputs - split into two parts and recurse + // also pad input to correct power-of-two width + wire [$clog2(W2)-1:0] out1, out2; + wire valid1, valid2; + priority_encoder #( + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) + ) + priority_encoder_inst1 ( + .input_unencoded(input_unencoded[W2-1:0]), + .output_valid(valid1), + .output_unencoded(), + .output_encoded(out1) + ); + priority_encoder #( + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) + ) + priority_encoder_inst2 ( + .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}), + .output_valid(valid2), + .output_unencoded(), + .output_encoded(out2) + ); + // multiplexer to select part + assign output_valid = valid1 | valid2; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1}; + end else begin + assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2}; + end + end +endgenerate + +// unencoded output +assign output_unencoded = 1 << output_encoded; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/corescore_0.eda.yml b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/corescore_0.eda.yml new file mode 100644 index 0000000000000000000000000000000000000000..aa8257e3319959c967ac02f1f66348b4b15b416c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/corescore_0.eda.yml @@ -0,0 +1,261 @@ +version: 0.2.1 +name: corescore_0 +toplevel: corescore_gowin_yosys +dependencies: + ::serv:1.0.2: [] + ::verilog-axis:0-r3: [] + ::serving:1.0.2: + - ::serv:1.0.2 + ::corescore:0: + - ::serv:1.0.2 + - ::serving:1.0.2 + - ::verilog-axis:0-r3 + - ::corescore-corescorecore:0 + ::corescore-corescorecore:0: [] +parameters: + RISCV_FORMAL: + datatype: bool + paramtype: vlogdefine + SERV_CLEAR_RAM: + datatype: bool + paramtype: vlogdefine +tool_options: + yosys: + arch: gowin +filters: [] +flow_options: {} +hooks: {} +files: +- file_type: verilogSource + is_include_file: true + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_params.vh + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_shift.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_bufreg.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_alu.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_csr.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_ctrl.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_decode.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_mem_if.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_if.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_ram_if.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_ram.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_state.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_top.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_top.v + core: ::serv:1.0.2 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/arbiter.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/priority_encoder.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/axis_arb_mux.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/verilog-axis_0-r3/rtl/axis_async_fifo.v + core: ::verilog-axis:0-r3 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving_arbiter.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving_mux.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving_ram.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/serving_1.0.2/serving/serving.v + core: ::serving:1.0.2 +- file_type: verilogSource + name: src/corescore_0/rtl/wb2axis.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/base.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/emitter_uart.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/corescore_gowin_yosys.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore_0/rtl/gw2a18_clk_gen.v + core: ::corescore:0 +- file_type: verilogSource + name: src/corescore-corescorecore_0/corescorecore.v + core: ::corescore-corescorecore:0 +- file_type: user + name: core_0.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_1.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_2.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_3.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_4.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_5.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_6.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_7.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_8.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_9.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_10.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_11.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_12.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_13.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_14.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_15.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_16.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_17.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_18.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_19.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_20.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_21.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_22.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_23.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_24.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_25.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_26.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_27.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_28.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_29.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_30.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_31.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_32.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_33.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_34.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_35.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_36.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_37.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_38.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_39.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_40.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_41.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_42.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_43.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_44.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_45.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_46.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_47.hex + core: ::corescore-corescorecore:0 +- file_type: user + name: core_48.hex + core: ::corescore-corescorecore:0 +vpi: [] diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/edalize_yosys_procs.tcl b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/edalize_yosys_procs.tcl new file mode 100644 index 0000000000000000000000000000000000000000..ee9531d69a475f7ba3766eb199b642d01593ac81 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/edalize_yosys_procs.tcl @@ -0,0 +1,51 @@ +proc read_files {} { +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_shift.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_bufreg.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_alu.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_csr.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_ctrl.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_decode.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_mem_if.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_if.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_ram_if.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_ram.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_state.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_top.v} +read_verilog {src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_top.v} +read_verilog {src/verilog-axis_0-r3/rtl/arbiter.v} +read_verilog {src/verilog-axis_0-r3/rtl/priority_encoder.v} +read_verilog {src/verilog-axis_0-r3/rtl/axis_arb_mux.v} +read_verilog {src/verilog-axis_0-r3/rtl/axis_async_fifo.v} +read_verilog {src/serving_1.0.2/serving/serving_arbiter.v} +read_verilog {src/serving_1.0.2/serving/serving_mux.v} +read_verilog {src/serving_1.0.2/serving/serving_ram.v} +read_verilog {src/serving_1.0.2/serving/serving.v} +read_verilog {src/corescore_0/rtl/wb2axis.v} +read_verilog {src/corescore_0/rtl/base.v} +read_verilog {src/corescore_0/rtl/emitter_uart.v} +read_verilog {src/corescore_0/rtl/corescore_gowin_yosys.v} +read_verilog {src/corescore_0/rtl/gw2a18_clk_gen.v} +read_verilog {src/corescore-corescorecore_0/corescorecore.v} +} + +proc set_defines {} { +set defines {} + +foreach d ${defines} { + set key [lindex $d 0] + set val [lindex $d 1] + verilog_defines "-D$key=$val" +}} + +proc set_incdirs {} { +verilog_defaults -add -Isrc/serv_1.0.2/serv_1.0.2/rtl} + +proc set_params {} { +} + +proc synth {top} { +synth_gowin -top $top +} + +set top corescore_gowin_yosys +set name corescore_0 diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/generator_cache/corescore-corescorecore_0-819d8ba66e9e19bcee2b7bad4708f165f57c14995815735d79793d53ab0b0d42/corescorecore.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/generator_cache/corescore-corescorecore_0-819d8ba66e9e19bcee2b7bad4708f165f57c14995815735d79793d53ab0b0d42/corescorecore.v new file mode 100644 index 0000000000000000000000000000000000000000..1155806e5d1068382d0efb6af43d2239bb9ba06b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/generator_cache/corescore-corescorecore_0-819d8ba66e9e19bcee2b7bad4708f165f57c14995815735d79793d53ab0b0d42/corescorecore.v @@ -0,0 +1,589 @@ +// THIS FILE IS AUTOGENERATED BY corescorecore_gen +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module corescorecore + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + +wire [391:0] tdata; +wire [48:0] tlast; +wire [48:0] tvalid; +wire [48:0] tready; + +base + #(.memfile ("core_0.hex"), + .memsize (256)) + core_0 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[7:0]), + .o_tlast (tlast[0]), + .o_tvalid (tvalid[0]), + .i_tready (tready[0])); + +base + #(.memfile ("core_1.hex"), + .memsize (256)) + core_1 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[15:8]), + .o_tlast (tlast[1]), + .o_tvalid (tvalid[1]), + .i_tready (tready[1])); + +base + #(.memfile ("core_2.hex"), + .memsize (256)) + core_2 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[23:16]), + .o_tlast (tlast[2]), + .o_tvalid (tvalid[2]), + .i_tready (tready[2])); + +base + #(.memfile ("core_3.hex"), + .memsize (256)) + core_3 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[31:24]), + .o_tlast (tlast[3]), + .o_tvalid (tvalid[3]), + .i_tready (tready[3])); + +base + #(.memfile ("core_4.hex"), + .memsize (256)) + core_4 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[39:32]), + .o_tlast (tlast[4]), + .o_tvalid (tvalid[4]), + .i_tready (tready[4])); + +base + #(.memfile ("core_5.hex"), + .memsize (256)) + core_5 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[47:40]), + .o_tlast (tlast[5]), + .o_tvalid (tvalid[5]), + .i_tready (tready[5])); + +base + #(.memfile ("core_6.hex"), + .memsize (256)) + core_6 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[55:48]), + .o_tlast (tlast[6]), + .o_tvalid (tvalid[6]), + .i_tready (tready[6])); + +base + #(.memfile ("core_7.hex"), + .memsize (256)) + core_7 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[63:56]), + .o_tlast (tlast[7]), + .o_tvalid (tvalid[7]), + .i_tready (tready[7])); + +base + #(.memfile ("core_8.hex"), + .memsize (256)) + core_8 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[71:64]), + .o_tlast (tlast[8]), + .o_tvalid (tvalid[8]), + .i_tready (tready[8])); + +base + #(.memfile ("core_9.hex"), + .memsize (256)) + core_9 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[79:72]), + .o_tlast (tlast[9]), + .o_tvalid (tvalid[9]), + .i_tready (tready[9])); + +base + #(.memfile ("core_10.hex"), + .memsize (256)) + core_10 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[87:80]), + .o_tlast (tlast[10]), + .o_tvalid (tvalid[10]), + .i_tready (tready[10])); + +base + #(.memfile ("core_11.hex"), + .memsize (256)) + core_11 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[95:88]), + .o_tlast (tlast[11]), + .o_tvalid (tvalid[11]), + .i_tready (tready[11])); + +base + #(.memfile ("core_12.hex"), + .memsize (256)) + core_12 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[103:96]), + .o_tlast (tlast[12]), + .o_tvalid (tvalid[12]), + .i_tready (tready[12])); + +base + #(.memfile ("core_13.hex"), + .memsize (256)) + core_13 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[111:104]), + .o_tlast (tlast[13]), + .o_tvalid (tvalid[13]), + .i_tready (tready[13])); + +base + #(.memfile ("core_14.hex"), + .memsize (256)) + core_14 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[119:112]), + .o_tlast (tlast[14]), + .o_tvalid (tvalid[14]), + .i_tready (tready[14])); + +base + #(.memfile ("core_15.hex"), + .memsize (256)) + core_15 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[127:120]), + .o_tlast (tlast[15]), + .o_tvalid (tvalid[15]), + .i_tready (tready[15])); + +base + #(.memfile ("core_16.hex"), + .memsize (256)) + core_16 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[135:128]), + .o_tlast (tlast[16]), + .o_tvalid (tvalid[16]), + .i_tready (tready[16])); + +base + #(.memfile ("core_17.hex"), + .memsize (256)) + core_17 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[143:136]), + .o_tlast (tlast[17]), + .o_tvalid (tvalid[17]), + .i_tready (tready[17])); + +base + #(.memfile ("core_18.hex"), + .memsize (256)) + core_18 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[151:144]), + .o_tlast (tlast[18]), + .o_tvalid (tvalid[18]), + .i_tready (tready[18])); + +base + #(.memfile ("core_19.hex"), + .memsize (256)) + core_19 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[159:152]), + .o_tlast (tlast[19]), + .o_tvalid (tvalid[19]), + .i_tready (tready[19])); + +base + #(.memfile ("core_20.hex"), + .memsize (256)) + core_20 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[167:160]), + .o_tlast (tlast[20]), + .o_tvalid (tvalid[20]), + .i_tready (tready[20])); + +base + #(.memfile ("core_21.hex"), + .memsize (256)) + core_21 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[175:168]), + .o_tlast (tlast[21]), + .o_tvalid (tvalid[21]), + .i_tready (tready[21])); + +base + #(.memfile ("core_22.hex"), + .memsize (256)) + core_22 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[183:176]), + .o_tlast (tlast[22]), + .o_tvalid (tvalid[22]), + .i_tready (tready[22])); + +base + #(.memfile ("core_23.hex"), + .memsize (256)) + core_23 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[191:184]), + .o_tlast (tlast[23]), + .o_tvalid (tvalid[23]), + .i_tready (tready[23])); + +base + #(.memfile ("core_24.hex"), + .memsize (256)) + core_24 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[199:192]), + .o_tlast (tlast[24]), + .o_tvalid (tvalid[24]), + .i_tready (tready[24])); + +base + #(.memfile ("core_25.hex"), + .memsize (256)) + core_25 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[207:200]), + .o_tlast (tlast[25]), + .o_tvalid (tvalid[25]), + .i_tready (tready[25])); + +base + #(.memfile ("core_26.hex"), + .memsize (256)) + core_26 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[215:208]), + .o_tlast (tlast[26]), + .o_tvalid (tvalid[26]), + .i_tready (tready[26])); + +base + #(.memfile ("core_27.hex"), + .memsize (256)) + core_27 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[223:216]), + .o_tlast (tlast[27]), + .o_tvalid (tvalid[27]), + .i_tready (tready[27])); + +base + #(.memfile ("core_28.hex"), + .memsize (256)) + core_28 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[231:224]), + .o_tlast (tlast[28]), + .o_tvalid (tvalid[28]), + .i_tready (tready[28])); + +base + #(.memfile ("core_29.hex"), + .memsize (256)) + core_29 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[239:232]), + .o_tlast (tlast[29]), + .o_tvalid (tvalid[29]), + .i_tready (tready[29])); + +base + #(.memfile ("core_30.hex"), + .memsize (256)) + core_30 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[247:240]), + .o_tlast (tlast[30]), + .o_tvalid (tvalid[30]), + .i_tready (tready[30])); + +base + #(.memfile ("core_31.hex"), + .memsize (256)) + core_31 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[255:248]), + .o_tlast (tlast[31]), + .o_tvalid (tvalid[31]), + .i_tready (tready[31])); + +base + #(.memfile ("core_32.hex"), + .memsize (256)) + core_32 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[263:256]), + .o_tlast (tlast[32]), + .o_tvalid (tvalid[32]), + .i_tready (tready[32])); + +base + #(.memfile ("core_33.hex"), + .memsize (256)) + core_33 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[271:264]), + .o_tlast (tlast[33]), + .o_tvalid (tvalid[33]), + .i_tready (tready[33])); + +base + #(.memfile ("core_34.hex"), + .memsize (256)) + core_34 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[279:272]), + .o_tlast (tlast[34]), + .o_tvalid (tvalid[34]), + .i_tready (tready[34])); + +base + #(.memfile ("core_35.hex"), + .memsize (256)) + core_35 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[287:280]), + .o_tlast (tlast[35]), + .o_tvalid (tvalid[35]), + .i_tready (tready[35])); + +base + #(.memfile ("core_36.hex"), + .memsize (256)) + core_36 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[295:288]), + .o_tlast (tlast[36]), + .o_tvalid (tvalid[36]), + .i_tready (tready[36])); + +base + #(.memfile ("core_37.hex"), + .memsize (256)) + core_37 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[303:296]), + .o_tlast (tlast[37]), + .o_tvalid (tvalid[37]), + .i_tready (tready[37])); + +base + #(.memfile ("core_38.hex"), + .memsize (256)) + core_38 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[311:304]), + .o_tlast (tlast[38]), + .o_tvalid (tvalid[38]), + .i_tready (tready[38])); + +base + #(.memfile ("core_39.hex"), + .memsize (256)) + core_39 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[319:312]), + .o_tlast (tlast[39]), + .o_tvalid (tvalid[39]), + .i_tready (tready[39])); + +base + #(.memfile ("core_40.hex"), + .memsize (256)) + core_40 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[327:320]), + .o_tlast (tlast[40]), + .o_tvalid (tvalid[40]), + .i_tready (tready[40])); + +base + #(.memfile ("core_41.hex"), + .memsize (256)) + core_41 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[335:328]), + .o_tlast (tlast[41]), + .o_tvalid (tvalid[41]), + .i_tready (tready[41])); + +base + #(.memfile ("core_42.hex"), + .memsize (256)) + core_42 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[343:336]), + .o_tlast (tlast[42]), + .o_tvalid (tvalid[42]), + .i_tready (tready[42])); + +base + #(.memfile ("core_43.hex"), + .memsize (256)) + core_43 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[351:344]), + .o_tlast (tlast[43]), + .o_tvalid (tvalid[43]), + .i_tready (tready[43])); + +base + #(.memfile ("core_44.hex"), + .memsize (256)) + core_44 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[359:352]), + .o_tlast (tlast[44]), + .o_tvalid (tvalid[44]), + .i_tready (tready[44])); + +base + #(.memfile ("core_45.hex"), + .memsize (256)) + core_45 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[367:360]), + .o_tlast (tlast[45]), + .o_tvalid (tvalid[45]), + .i_tready (tready[45])); + +base + #(.memfile ("core_46.hex"), + .memsize (256)) + core_46 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[375:368]), + .o_tlast (tlast[46]), + .o_tvalid (tvalid[46]), + .i_tready (tready[46])); + +base + #(.memfile ("core_47.hex"), + .memsize (256)) + core_47 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[383:376]), + .o_tlast (tlast[47]), + .o_tvalid (tvalid[47]), + .i_tready (tready[47])); + +base + #(.memfile ("core_48.hex"), + .memsize (256)) + core_48 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[391:384]), + .o_tlast (tlast[48]), + .o_tvalid (tvalid[48]), + .i_tready (tready[48])); + +axis_arb_mux + #(.S_COUNT (49), + .DATA_WIDTH (8), + .KEEP_ENABLE (0), + .KEEP_WIDTH (1), + .ID_ENABLE (0), + .ID_WIDTH (8), + .DEST_ENABLE (0), + .DEST_WIDTH (8), + .USER_ENABLE (0), + .USER_WIDTH (1), + .ARB_TYPE ("ROUND_ROBIN"), + .LSB_PRIORITY ("HIGH")) + axis_mux + (.clk (i_clk), + .rst (i_rst), + .s_axis_tdata (tdata), + .s_axis_tkeep (49'd0), + .s_axis_tvalid (tvalid), + .s_axis_tready (tready), + .s_axis_tlast (tlast), + .s_axis_tid (392'd0), + .s_axis_tdest (392'd0), + .s_axis_tuser (49'd0), + .m_axis_tdata (o_tdata), + .m_axis_tkeep (), + .m_axis_tvalid (o_tvalid), + .m_axis_tready (i_tready), + .m_axis_tlast (o_tlast), + .m_axis_tid (), + .m_axis_tdest (), + .m_axis_tuser ()); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/generator_cache/corescore-corescorecore_0-819d8ba66e9e19bcee2b7bad4708f165f57c14995815735d79793d53ab0b0d42/corescorecore_input.yml b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/generator_cache/corescore-corescorecore_0-819d8ba66e9e19bcee2b7bad4708f165f57c14995815735d79793d53ab0b0d42/corescorecore_input.yml new file mode 100644 index 0000000000000000000000000000000000000000..767db62052b63947c3160234f8a3d1446e82fb3f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/generator_cache/corescore-corescorecore_0-819d8ba66e9e19bcee2b7bad4708f165f57c14995815735d79793d53ab0b0d42/corescorecore_input.yml @@ -0,0 +1,5 @@ +files_root: /home/tarik/0.git-repo/openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore +gapi: '1.0' +parameters: + count: 49 +vlnv: ::corescore-corescorecore:0 diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore-corescorecore_0/corescorecore.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore-corescorecore_0/corescorecore.v new file mode 100644 index 0000000000000000000000000000000000000000..1155806e5d1068382d0efb6af43d2239bb9ba06b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore-corescorecore_0/corescorecore.v @@ -0,0 +1,589 @@ +// THIS FILE IS AUTOGENERATED BY corescorecore_gen +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module corescorecore + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + +wire [391:0] tdata; +wire [48:0] tlast; +wire [48:0] tvalid; +wire [48:0] tready; + +base + #(.memfile ("core_0.hex"), + .memsize (256)) + core_0 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[7:0]), + .o_tlast (tlast[0]), + .o_tvalid (tvalid[0]), + .i_tready (tready[0])); + +base + #(.memfile ("core_1.hex"), + .memsize (256)) + core_1 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[15:8]), + .o_tlast (tlast[1]), + .o_tvalid (tvalid[1]), + .i_tready (tready[1])); + +base + #(.memfile ("core_2.hex"), + .memsize (256)) + core_2 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[23:16]), + .o_tlast (tlast[2]), + .o_tvalid (tvalid[2]), + .i_tready (tready[2])); + +base + #(.memfile ("core_3.hex"), + .memsize (256)) + core_3 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[31:24]), + .o_tlast (tlast[3]), + .o_tvalid (tvalid[3]), + .i_tready (tready[3])); + +base + #(.memfile ("core_4.hex"), + .memsize (256)) + core_4 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[39:32]), + .o_tlast (tlast[4]), + .o_tvalid (tvalid[4]), + .i_tready (tready[4])); + +base + #(.memfile ("core_5.hex"), + .memsize (256)) + core_5 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[47:40]), + .o_tlast (tlast[5]), + .o_tvalid (tvalid[5]), + .i_tready (tready[5])); + +base + #(.memfile ("core_6.hex"), + .memsize (256)) + core_6 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[55:48]), + .o_tlast (tlast[6]), + .o_tvalid (tvalid[6]), + .i_tready (tready[6])); + +base + #(.memfile ("core_7.hex"), + .memsize (256)) + core_7 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[63:56]), + .o_tlast (tlast[7]), + .o_tvalid (tvalid[7]), + .i_tready (tready[7])); + +base + #(.memfile ("core_8.hex"), + .memsize (256)) + core_8 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[71:64]), + .o_tlast (tlast[8]), + .o_tvalid (tvalid[8]), + .i_tready (tready[8])); + +base + #(.memfile ("core_9.hex"), + .memsize (256)) + core_9 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[79:72]), + .o_tlast (tlast[9]), + .o_tvalid (tvalid[9]), + .i_tready (tready[9])); + +base + #(.memfile ("core_10.hex"), + .memsize (256)) + core_10 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[87:80]), + .o_tlast (tlast[10]), + .o_tvalid (tvalid[10]), + .i_tready (tready[10])); + +base + #(.memfile ("core_11.hex"), + .memsize (256)) + core_11 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[95:88]), + .o_tlast (tlast[11]), + .o_tvalid (tvalid[11]), + .i_tready (tready[11])); + +base + #(.memfile ("core_12.hex"), + .memsize (256)) + core_12 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[103:96]), + .o_tlast (tlast[12]), + .o_tvalid (tvalid[12]), + .i_tready (tready[12])); + +base + #(.memfile ("core_13.hex"), + .memsize (256)) + core_13 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[111:104]), + .o_tlast (tlast[13]), + .o_tvalid (tvalid[13]), + .i_tready (tready[13])); + +base + #(.memfile ("core_14.hex"), + .memsize (256)) + core_14 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[119:112]), + .o_tlast (tlast[14]), + .o_tvalid (tvalid[14]), + .i_tready (tready[14])); + +base + #(.memfile ("core_15.hex"), + .memsize (256)) + core_15 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[127:120]), + .o_tlast (tlast[15]), + .o_tvalid (tvalid[15]), + .i_tready (tready[15])); + +base + #(.memfile ("core_16.hex"), + .memsize (256)) + core_16 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[135:128]), + .o_tlast (tlast[16]), + .o_tvalid (tvalid[16]), + .i_tready (tready[16])); + +base + #(.memfile ("core_17.hex"), + .memsize (256)) + core_17 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[143:136]), + .o_tlast (tlast[17]), + .o_tvalid (tvalid[17]), + .i_tready (tready[17])); + +base + #(.memfile ("core_18.hex"), + .memsize (256)) + core_18 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[151:144]), + .o_tlast (tlast[18]), + .o_tvalid (tvalid[18]), + .i_tready (tready[18])); + +base + #(.memfile ("core_19.hex"), + .memsize (256)) + core_19 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[159:152]), + .o_tlast (tlast[19]), + .o_tvalid (tvalid[19]), + .i_tready (tready[19])); + +base + #(.memfile ("core_20.hex"), + .memsize (256)) + core_20 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[167:160]), + .o_tlast (tlast[20]), + .o_tvalid (tvalid[20]), + .i_tready (tready[20])); + +base + #(.memfile ("core_21.hex"), + .memsize (256)) + core_21 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[175:168]), + .o_tlast (tlast[21]), + .o_tvalid (tvalid[21]), + .i_tready (tready[21])); + +base + #(.memfile ("core_22.hex"), + .memsize (256)) + core_22 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[183:176]), + .o_tlast (tlast[22]), + .o_tvalid (tvalid[22]), + .i_tready (tready[22])); + +base + #(.memfile ("core_23.hex"), + .memsize (256)) + core_23 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[191:184]), + .o_tlast (tlast[23]), + .o_tvalid (tvalid[23]), + .i_tready (tready[23])); + +base + #(.memfile ("core_24.hex"), + .memsize (256)) + core_24 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[199:192]), + .o_tlast (tlast[24]), + .o_tvalid (tvalid[24]), + .i_tready (tready[24])); + +base + #(.memfile ("core_25.hex"), + .memsize (256)) + core_25 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[207:200]), + .o_tlast (tlast[25]), + .o_tvalid (tvalid[25]), + .i_tready (tready[25])); + +base + #(.memfile ("core_26.hex"), + .memsize (256)) + core_26 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[215:208]), + .o_tlast (tlast[26]), + .o_tvalid (tvalid[26]), + .i_tready (tready[26])); + +base + #(.memfile ("core_27.hex"), + .memsize (256)) + core_27 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[223:216]), + .o_tlast (tlast[27]), + .o_tvalid (tvalid[27]), + .i_tready (tready[27])); + +base + #(.memfile ("core_28.hex"), + .memsize (256)) + core_28 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[231:224]), + .o_tlast (tlast[28]), + .o_tvalid (tvalid[28]), + .i_tready (tready[28])); + +base + #(.memfile ("core_29.hex"), + .memsize (256)) + core_29 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[239:232]), + .o_tlast (tlast[29]), + .o_tvalid (tvalid[29]), + .i_tready (tready[29])); + +base + #(.memfile ("core_30.hex"), + .memsize (256)) + core_30 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[247:240]), + .o_tlast (tlast[30]), + .o_tvalid (tvalid[30]), + .i_tready (tready[30])); + +base + #(.memfile ("core_31.hex"), + .memsize (256)) + core_31 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[255:248]), + .o_tlast (tlast[31]), + .o_tvalid (tvalid[31]), + .i_tready (tready[31])); + +base + #(.memfile ("core_32.hex"), + .memsize (256)) + core_32 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[263:256]), + .o_tlast (tlast[32]), + .o_tvalid (tvalid[32]), + .i_tready (tready[32])); + +base + #(.memfile ("core_33.hex"), + .memsize (256)) + core_33 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[271:264]), + .o_tlast (tlast[33]), + .o_tvalid (tvalid[33]), + .i_tready (tready[33])); + +base + #(.memfile ("core_34.hex"), + .memsize (256)) + core_34 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[279:272]), + .o_tlast (tlast[34]), + .o_tvalid (tvalid[34]), + .i_tready (tready[34])); + +base + #(.memfile ("core_35.hex"), + .memsize (256)) + core_35 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[287:280]), + .o_tlast (tlast[35]), + .o_tvalid (tvalid[35]), + .i_tready (tready[35])); + +base + #(.memfile ("core_36.hex"), + .memsize (256)) + core_36 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[295:288]), + .o_tlast (tlast[36]), + .o_tvalid (tvalid[36]), + .i_tready (tready[36])); + +base + #(.memfile ("core_37.hex"), + .memsize (256)) + core_37 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[303:296]), + .o_tlast (tlast[37]), + .o_tvalid (tvalid[37]), + .i_tready (tready[37])); + +base + #(.memfile ("core_38.hex"), + .memsize (256)) + core_38 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[311:304]), + .o_tlast (tlast[38]), + .o_tvalid (tvalid[38]), + .i_tready (tready[38])); + +base + #(.memfile ("core_39.hex"), + .memsize (256)) + core_39 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[319:312]), + .o_tlast (tlast[39]), + .o_tvalid (tvalid[39]), + .i_tready (tready[39])); + +base + #(.memfile ("core_40.hex"), + .memsize (256)) + core_40 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[327:320]), + .o_tlast (tlast[40]), + .o_tvalid (tvalid[40]), + .i_tready (tready[40])); + +base + #(.memfile ("core_41.hex"), + .memsize (256)) + core_41 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[335:328]), + .o_tlast (tlast[41]), + .o_tvalid (tvalid[41]), + .i_tready (tready[41])); + +base + #(.memfile ("core_42.hex"), + .memsize (256)) + core_42 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[343:336]), + .o_tlast (tlast[42]), + .o_tvalid (tvalid[42]), + .i_tready (tready[42])); + +base + #(.memfile ("core_43.hex"), + .memsize (256)) + core_43 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[351:344]), + .o_tlast (tlast[43]), + .o_tvalid (tvalid[43]), + .i_tready (tready[43])); + +base + #(.memfile ("core_44.hex"), + .memsize (256)) + core_44 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[359:352]), + .o_tlast (tlast[44]), + .o_tvalid (tvalid[44]), + .i_tready (tready[44])); + +base + #(.memfile ("core_45.hex"), + .memsize (256)) + core_45 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[367:360]), + .o_tlast (tlast[45]), + .o_tvalid (tvalid[45]), + .i_tready (tready[45])); + +base + #(.memfile ("core_46.hex"), + .memsize (256)) + core_46 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[375:368]), + .o_tlast (tlast[46]), + .o_tvalid (tvalid[46]), + .i_tready (tready[46])); + +base + #(.memfile ("core_47.hex"), + .memsize (256)) + core_47 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[383:376]), + .o_tlast (tlast[47]), + .o_tvalid (tvalid[47]), + .i_tready (tready[47])); + +base + #(.memfile ("core_48.hex"), + .memsize (256)) + core_48 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[391:384]), + .o_tlast (tlast[48]), + .o_tvalid (tvalid[48]), + .i_tready (tready[48])); + +axis_arb_mux + #(.S_COUNT (49), + .DATA_WIDTH (8), + .KEEP_ENABLE (0), + .KEEP_WIDTH (1), + .ID_ENABLE (0), + .ID_WIDTH (8), + .DEST_ENABLE (0), + .DEST_WIDTH (8), + .USER_ENABLE (0), + .USER_WIDTH (1), + .ARB_TYPE ("ROUND_ROBIN"), + .LSB_PRIORITY ("HIGH")) + axis_mux + (.clk (i_clk), + .rst (i_rst), + .s_axis_tdata (tdata), + .s_axis_tkeep (49'd0), + .s_axis_tvalid (tvalid), + .s_axis_tready (tready), + .s_axis_tlast (tlast), + .s_axis_tid (392'd0), + .s_axis_tdest (392'd0), + .s_axis_tuser (49'd0), + .m_axis_tdata (o_tdata), + .m_axis_tkeep (), + .m_axis_tvalid (o_tvalid), + .m_axis_tready (i_tready), + .m_axis_tlast (o_tlast), + .m_axis_tid (), + .m_axis_tdest (), + .m_axis_tuser ()); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/base.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/base.v new file mode 100644 index 0000000000000000000000000000000000000000..ba75ad9dc0c15e734cf479e693d9c6c449bf5ed7 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/base.v @@ -0,0 +1,46 @@ +module base + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + parameter memfile = ""; + parameter memsize = 8192; + + wire [31:0] wb_dat; + wire wb_we; + wire wb_stb; + wire wb_ack; + + wb2axis w2s + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wb_dat (wb_dat[8:0]), + .i_wb_we (wb_we), + .i_wb_stb (wb_stb), + .o_wb_ack (wb_ack), + .o_tdata (o_tdata), + .o_tlast (o_tlast), + .o_tvalid (o_tvalid), + .i_tready (i_tready)); + + serving + #(.memfile (memfile), + .memsize (memsize), + .WITH_CSR (0)) + serving + (.i_clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (1'b0), + + .o_wb_adr (), + .o_wb_dat (wb_dat), + .o_wb_sel (), + .o_wb_we (wb_we), + .o_wb_stb (wb_stb), + .i_wb_rdt (32'd0), + .i_wb_ack (wb_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/corescore_gowin_yosys.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/corescore_gowin_yosys.v new file mode 100644 index 0000000000000000000000000000000000000000..c11e8ad8b39b81ea46821361bedfcfdb10c1ef13 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/corescore_gowin_yosys.v @@ -0,0 +1,39 @@ +(* keep = 1 *) +module corescore_gowin_yosys + ( + input i_clk, + input i_rstn, + output wire o_uart_tx); + + wire clk; + wire o_rst; + + //Create a 16MHz clock from 10MHz using PLL + clkgen clkgen + (.i_clk (i_clk), + .i_rstn (i_rstn), + .o_clk_core(clk), + .o_rst_core(o_rst)); + + wire [7:0] tdata; + wire tlast; + wire tvalid; + wire tready; + + corescorecore corescorecore + (.i_clk (clk), + .i_rst (o_rst), + .o_tdata (tdata), + .o_tlast (tlast), + .o_tvalid (tvalid), + .i_tready (tready)); + + emitter_uart emitter + (.i_clk (clk), + .i_rst (o_rst), + .i_tdata (tdata), + .i_tvalid (tvalid), + .o_tready (tready), + .o_uart_tx (o_uart_tx)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/emitter_uart.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/emitter_uart.v new file mode 100644 index 0000000000000000000000000000000000000000..87146563eb9490b4a236e25e4bc0b1438d0aa2c0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/emitter_uart.v @@ -0,0 +1,45 @@ +/* + * emitter_uart.v : Simple UA(R)T used as emitter in CoreScore + * + * SPDX-FileCopyrightText: 2023 Olof Kindgren + * SPDX-License-Identifier: Apache-2.0 + */ + +module emitter_uart + #(parameter clk_freq_hz = 16_000_000, + parameter baud_rate = 57600) + (input wire i_clk, + input wire i_rst, + input wire [7:0] i_tdata, + input wire i_tvalid, + output reg o_tready, + output wire o_uart_tx); + + localparam START_VALUE = clk_freq_hz/baud_rate; + + localparam WIDTH = $clog2(START_VALUE); + + reg [WIDTH:0] cnt; + + reg [9:0] data; + + assign o_uart_tx = data[0] | !(|data); + + always @(posedge i_clk) begin + if (cnt[WIDTH] & !(|data)) + o_tready <= 1'b1; + else if (i_tvalid & o_tready) + o_tready <= 1'b0; + + if (o_tready | cnt[WIDTH]) + cnt <= {1'b0,START_VALUE[WIDTH-1:0]}; + else + cnt <= cnt-1; + + if (cnt[WIDTH]) + data <= {1'b0, data[9:1]}; + else if (i_tvalid & o_tready) + data <= {1'b1, i_tdata, 1'b0}; + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/gw2a18_clk_gen.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/gw2a18_clk_gen.v new file mode 100644 index 0000000000000000000000000000000000000000..e62f7470c75aa66230ce0fa0d5e811064e99520a --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/gw2a18_clk_gen.v @@ -0,0 +1,89 @@ +module clkgen ( + input wire i_clk, + input wire i_rstn, + output wire o_clk_core, + output wire o_rst_core +); + +wire pll_lock; + + rPLL #( + //.DEVICE ("GW1NR-9C"), + //.DEVICE ("GW2AR-18C"), + .DEVICE ("GW2AR-18C"), + .FCLKIN ("27"), + .DYN_IDIV_SEL ("false"), + .IDIV_SEL (4), + .DYN_FBDIV_SEL ("false"), + .FBDIV_SEL (2), + .DYN_ODIV_SEL ("false"), + .ODIV_SEL (32), + .PSDA_SEL ("0000"), + .DYN_DA_EN ("true"), + .DUTYDA_SEL ("1000"), + .CLKOUT_FT_DIR (1'b1), + .CLKOUTP_FT_DIR (1'b1), + .CLKOUT_DLY_STEP (0), + .CLKOUTP_DLY_STEP (0), + .CLKFB_SEL ("internal"), + .CLKOUT_BYPASS ("false"), + .CLKOUTP_BYPASS ("false"), + .CLKOUTD_BYPASS ("false"), + .DYN_SDIV_SEL (2), + .CLKOUTD_SRC ("CLKOUT"), + .CLKOUTD3_SRC ("CLKOUT") + ) + u_pll ( + .CLKOUT (o_clk_core), + .LOCK (pll_lock), + .CLKOUTP (), + .CLKOUTD (), + .CLKOUTD3 (), + + .RESET (1'b0), + .RESET_P (1'b0), + .CLKIN (i_clk), + .CLKFB (1'b0), + .FBDSEL ('0), + .IDSEL ('0), + .ODSEL ('0), + .PSDA ('0), + .DUTYDA ('0), + .FDLY ('0) + ); + +//-------------------------------------------------- +// Clock divider: 108MHz -> 54MHz +//-------------------------------------------------- + CLKDIV #( + .DIV_MODE ("2"), + .GSREN ("false") + ) + u_clkdiv ( + .CLKOUT (clk_54), + .HCLKIN (clk_108), + .RESETN (pll_lock), + .CALIB (1'b0) + ); + +//-------------------------------------------------- +// Reset synchronizer +//-------------------------------------------------- + reg srst_n_pipe; + wire final_rst; + assign final_rst = ~i_rstn | ~pll_lock; + reg srst_n; + + always @(posedge final_rst or posedge clk_54) begin + if (final_rst == 1'b1) begin + srst_n_pipe <= 1'b0; + srst_n <= 1'b0; + end + else begin + srst_n_pipe <= 1'b1; + srst_n <= srst_n_pipe; + end + end + + assign o_rst_core = ~srst_n; +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/wb2axis.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/wb2axis.v new file mode 100644 index 0000000000000000000000000000000000000000..10d983e13c230ac1367215aa64b7511b490590db --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/corescore_0/rtl/wb2axis.v @@ -0,0 +1,25 @@ +`default_nettype none +module wb2axis + ( + input wire i_clk, + input wire i_rst, + input wire [8:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_stb, + output reg o_wb_ack, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + always @(posedge i_clk) begin + o_wb_ack <= i_wb_stb & i_tready & !o_wb_ack; + if (i_rst) + o_wb_ack <= 1'b0; + end + + assign o_tvalid = i_wb_stb & i_wb_we & !o_wb_ack; + assign o_tdata = i_wb_dat[7:0]; + assign o_tlast = i_wb_dat[8]; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_alu.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_alu.v new file mode 100644 index 0000000000000000000000000000000000000000..b5e1164c5358ca5878f08fed3991759c7a6215f0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_alu.v @@ -0,0 +1,106 @@ +`default_nettype none +module serv_alu + ( + input wire clk, + input wire i_rst, + input wire i_en, + input wire i_cnt0, + input wire i_rs1, + input wire i_rs2, + input wire i_imm, + input wire i_op_b_rs2, + input wire i_buf, + input wire i_init, + input wire i_cnt_done, + input wire i_sub, + input wire [1:0] i_bool_op, + input wire i_cmp_eq, + input wire i_cmp_uns, + output wire o_cmp, + input wire i_shamt_en, + input wire i_sh_right, + input wire i_sh_signed, + output wire o_sh_done, + input wire [3:0] i_rd_sel, + output wire o_rd); + + wire result_add; + wire result_eq; + wire result_lt; + wire result_sh; + + reg result_lt_r; + + reg [4:0] shamt; + reg shamt_msb; + + wire shamt_ser; + wire plus_1; + + wire add_cy; + reg add_cy_r; + + wire b_inv_plus_1; + wire b_inv_plus_1_cy; + reg b_inv_plus_1_cy_r; + + wire op_b = i_op_b_rs2 ? i_rs2 : i_imm; + assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1; + + serv_shift shift + ( + .i_clk (clk), + .i_load (i_init), + .i_shamt (shamt), + .i_shamt_msb (shamt_msb), + .i_signbit (i_sh_signed & i_rs1), + .i_right (i_sh_right), + .o_done (o_sh_done), + .i_d (i_buf), + .o_q (result_sh)); + + wire add_b = i_sub ? b_inv_plus_1 : op_b; + assign {add_cy,result_add} = i_rs1+add_b+add_cy_r; + assign {b_inv_plus_1_cy,b_inv_plus_1} = {1'b0,~op_b}+plus_1+b_inv_plus_1_cy_r; + + reg lt_r; + + reg eq_r; + + wire lt_sign = i_cnt_done & !i_cmp_uns; + + wire eq = (i_rs1 == op_b); + + assign result_eq = eq & eq_r; + assign result_lt = eq ? lt_r : op_b^lt_sign; + + assign plus_1 = i_cnt0; + assign o_cmp = i_cmp_eq ? result_eq : result_lt; + + localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor + wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}]; + + assign o_rd = (i_rd_sel[0] & result_add) | + (i_rd_sel[1] & result_sh) | + (i_rd_sel[2] & result_lt_r & plus_1) | + (i_rd_sel[3] & result_bool); + + + always @(posedge clk) begin + add_cy_r <= i_en & add_cy; + b_inv_plus_1_cy_r <= i_en & b_inv_plus_1_cy; + + lt_r <= result_lt & i_en; + + if (i_en) begin + result_lt_r <= result_lt; + end + eq_r <= result_eq | ~i_en; + + if (i_shamt_en) begin + shamt_msb <= b_inv_plus_1_cy; + shamt <= {shamt_ser,shamt[4:1]}; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_bufreg.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_bufreg.v new file mode 100644 index 0000000000000000000000000000000000000000..e7172a2a1a47d416569802a5c113b19e849caca5 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_bufreg.v @@ -0,0 +1,42 @@ +module serv_bufreg + ( + input wire i_clk, + input wire i_cnt0, + input wire i_cnt1, + input wire i_en, + input wire i_init, + input wire i_loop, + input wire i_rs1, + input wire i_rs1_en, + input wire i_imm, + input wire i_imm_en, + input wire i_clr_lsb, + output reg [1:0] o_lsb, + output wire [31:0] o_dbus_adr, + output wire o_q); + + wire c, q; + reg c_r; + (* ram_style = "distributed" *) reg [31:0] data; + + wire clr_lsb = i_cnt0 & i_clr_lsb; + + assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r; + + always @(posedge i_clk) begin + //Clear carry when not in INIT state + c_r <= c & i_init; + + if (i_en) + data <= {(i_loop & !i_init) ? o_q : q, data[31:1]}; + + if (i_cnt0 & i_init) + o_lsb[0] <= q; + if (i_cnt1 & i_init) + o_lsb[1] <= q; + end + + assign o_q = data[0]; + assign o_dbus_adr = {data[31:2], 2'b00}; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_csr.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_csr.v new file mode 100644 index 0000000000000000000000000000000000000000..897e2728f60784fe39e6819869554b10ee0aec76 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_csr.v @@ -0,0 +1,108 @@ +`default_nettype none +module serv_csr + ( + input wire i_clk, + input wire i_en, + input wire i_cnt0to3, + input wire i_cnt2, + input wire i_cnt3, + input wire i_cnt7, + input wire i_cnt_done, + input wire i_e_op, + input wire i_ebreak, + input wire i_mem_cmd, + input wire i_mem_misalign, + //From mpram + input wire i_rf_csr_out, + //to mpram + output wire o_csr_in, + //Stuff + input wire i_mtip, + output wire o_new_irq, + input wire i_pending_irq, + input wire i_trap_taken, + input wire i_mstatus_en, + input wire i_mie_en, + input wire i_mcause_en, + input wire [1:0] i_csr_source, + input wire i_mret, + input wire i_d, + output wire o_q); + +`include "serv_params.vh" + + reg mstatus; + reg mstatus_mie; + reg mstatus_mpie; + reg mie_mtie; + + reg mcause31; + reg [3:0] mcause3_0; + wire mcause; + + wire csr_in; + wire csr_out; + + reg timer_irq_r; + + assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? i_d : + (i_csr_source == CSR_SOURCE_SET) ? csr_out | i_d : + (i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~i_d : + (i_csr_source == CSR_SOURCE_CSR) ? csr_out : + 1'bx; + + assign csr_out = (i_mstatus_en & i_en & mstatus) | + i_rf_csr_out | + (i_mcause_en & i_en & mcause); + + assign o_q = csr_out; + + wire timer_irq = i_mtip & mstatus_mie & mie_mtie; + + assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0] + i_cnt_done ? mcause31 //[31] + : 1'b0; + + assign o_csr_in = csr_in; + + assign o_new_irq = !timer_irq_r & timer_irq; + + + always @(posedge i_clk) begin + /* + Note: To save resources mstatus_mpie (mstatus bit 7) is not + readable or writable from sw + */ + if (i_mstatus_en & i_cnt3) + mstatus_mie <= csr_in; + + if (i_mie_en & i_cnt7) + mie_mtie <= csr_in; + + mstatus <= i_cnt2 & mstatus_mie; + + timer_irq_r <= timer_irq; + + if (i_mret) begin + mstatus_mie <= mstatus_mpie; + end + + if (i_trap_taken) begin + mstatus_mpie <= mstatus_mie; + mstatus_mie <= 1'b0; + mcause31 <= i_pending_irq; + mcause3_0 <= i_pending_irq ? 4'd7 : + i_e_op ? {!i_ebreak, 3'b011} : + i_mem_misalign ? {2'b01, i_mem_cmd, 1'b0} : + 4'd0; + end + + if (i_mcause_en & i_en) begin + if (i_cnt0to3) + mcause3_0 <= {csr_in, mcause3_0[3:1]}; + if (i_cnt_done) + mcause31 <= csr_in; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_ctrl.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..f5899a58aa0df8db394b05decf6f46ecfd41df11 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_ctrl.v @@ -0,0 +1,87 @@ +`default_nettype none +module serv_ctrl + ( + input wire clk, + input wire i_rst, + //State + input wire i_pc_en, + input wire i_cnt12to31, + input wire i_cnt2, + input wire i_cnt_done, + //Control + input wire i_jump, + input wire i_jal_or_jalr, + input wire i_utype, + input wire i_pc_rel, + input wire i_trap, + //Data + input wire i_imm, + input wire i_buf, + input wire i_csr_pc, + output wire o_rd, + output wire o_bad_pc, + //External + output reg [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire i_ibus_ack); + + parameter RESET_PC = 32'd0; + parameter WITH_CSR = 1; + + reg en_pc_r; + + wire pc_plus_4; + wire pc_plus_4_cy; + reg pc_plus_4_cy_r; + wire pc_plus_offset; + wire pc_plus_offset_cy; + reg pc_plus_offset_cy_r; + wire pc_plus_offset_aligned; + wire plus_4; + + wire pc = o_ibus_adr[0]; + + wire new_pc; + + wire offset_a; + wire offset_b; + + assign plus_4 = i_cnt2; + + assign o_bad_pc = pc_plus_offset_aligned; + + assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r; + + generate + if (WITH_CSR) + assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4; + else + assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4; + endgenerate + assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr); + + assign offset_a = i_pc_rel & pc; + assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf; + assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r; + + assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r; + + assign o_ibus_cyc = en_pc_r & !i_pc_en; + + always @(posedge clk) begin + pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; + pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; + + if (i_pc_en) begin + en_pc_r <= 1'b1; + o_ibus_adr <= {new_pc, o_ibus_adr[31:1]}; + end else if (o_ibus_cyc & i_ibus_ack) + en_pc_r <= 1'b0; + + if (i_rst) begin + en_pc_r <= 1'b1; + o_ibus_adr <= RESET_PC; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_decode.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_decode.v new file mode 100644 index 0000000000000000000000000000000000000000..d66a1e046f47cafac6113e7d9c138c31fa82253c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_decode.v @@ -0,0 +1,239 @@ +`default_nettype none +module serv_decode + ( + input wire clk, + //Input + input wire i_cnt_en, + input wire i_cnt_done, + input wire [31:2] i_wb_rdt, + input wire i_wb_en, + input wire i_alu_cmp, + //To state + output wire o_take_branch, + output wire o_e_op, + output wire o_ebreak, + output wire o_branch_op, + output wire o_mem_op, + output wire o_shift_op, + output wire o_slt_op, + output wire o_rd_op, + //To bufreg + output wire o_bufreg_loop, + output wire o_bufreg_rs1_en, + output wire o_bufreg_imm_en, + output wire o_bufreg_clr_lsb, + //To ctrl + output wire o_ctrl_jal_or_jalr, + output wire o_ctrl_utype, + output wire o_ctrl_pc_rel, + output wire o_ctrl_mret, + //To alu + output wire o_alu_sub, + output wire [1:0] o_alu_bool_op, + output wire o_alu_cmp_eq, + output wire o_alu_cmp_uns, + output wire o_alu_sh_signed, + output wire o_alu_sh_right, + output wire [3:0] o_alu_rd_sel, + //To RF + output reg [4:0] o_rf_rd_addr, + output reg [4:0] o_rf_rs1_addr, + output reg [4:0] o_rf_rs2_addr, + //To mem IF + output wire o_mem_signed, + output wire o_mem_word, + output wire o_mem_half, + output wire o_mem_cmd, + //To CSR + output wire o_csr_en, + output wire [1:0] o_csr_addr, + output wire o_csr_mstatus_en, + output wire o_csr_mie_en, + output wire o_csr_mcause_en, + output wire [1:0] o_csr_source, + output wire o_csr_d_sel, + output wire o_csr_imm, + //To top + output wire o_imm, + output wire o_op_b_source, + output wire o_rd_csr_en, + output wire o_rd_alu_en); + +`include "serv_params.vh" + + reg [4:0] opcode; + reg [2:0] funct3; + reg op20; + reg op21; + reg op22; + reg op26; + + reg imm30; + + wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]); + + assign o_mem_op = !opcode[4] & !opcode[2] & !opcode[0]; + assign o_shift_op = op_or_opimm & (funct3[1:0] == 2'b01); + assign o_slt_op = op_or_opimm & (funct3[2:1] == 2'b01); + assign o_branch_op = opcode[4] & !opcode[2]; + + //Matches system opcodes except CSR accesses (funct3 == 0) + //No idea anymore why the !op21 condition is needed here + assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3); + + assign o_ebreak = op20; + + //jal,branch = imm + //jalr = rs1+imm + //mem = rs1+imm + //shift = rs1 + assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]); + assign o_bufreg_imm_en = !opcode[2]; + + //Loop bufreg contents for shift operations + assign o_bufreg_loop = op_or_opimm; + + //Clear LSB of immediate for BRANCH and JAL ops + //True for BRANCH and JAL + //False for JALR/LOAD/STORE/OP/OPIMM? + assign o_bufreg_clr_lsb = opcode[4] & ((opcode[1:0] == 2'b00) | (opcode[1:0] == 2'b11)); + + //Take branch for jump or branch instructions (opcode == 1x0xx) if + //a) It's an unconditional branch (opcode[0] == 1) + //b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true + //c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false + //Only valid during the last cycle of INIT, when the branch condition has + //been calculated. + assign o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^funct3[0])); + + assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0]; + assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0]; + + //True for jal, b* auipc + //False for jalr, lui + assign o_ctrl_pc_rel = (opcode[2:0] == 3'b000) | + (opcode[1:0] == 2'b11) | + (opcode[4:3] == 2'b00); + + assign o_ctrl_mret = (opcode[4] & opcode[2] & op21 & !(|funct3)); + + //Write to RD + //True for OP-IMM, AUIPC, OP, LUI, SYSTEM, JALR, JAL, LOAD + //False for STORE, BRANCH, MISC-MEM + assign o_rd_op = (opcode[2] | + (!opcode[2] & opcode[4] & opcode[0]) | + (!opcode[2] & !opcode[3] & !opcode[0])) & (|o_rf_rd_addr); + + assign o_alu_sub = opcode[3] & imm30/*alu_sub_r*/; + + /* + 300 0_000 mstatus RWSC + 304 0_100 mie SCWi + 305 0_101 mtvec RW + 340 1_000 mscratch + 341 1_001 mepc RW + 342 1_010 mcause R + 343 1_011 mtval + 344 1_100 mip CWi + */ + + //true for mtvec,mscratch,mepc and mtval + //false for mstatus, mie, mcause, mip + wire csr_valid = op20 | (op26 & !op22 & !op21); + + //Matches system ops except eceall/ebreak + wire csr_op = opcode[4] & opcode[2] & (|funct3); + assign o_rd_csr_en = csr_op; + + assign o_csr_en = csr_op & csr_valid; + assign o_csr_mstatus_en = csr_op & !op26 & !op22; + assign o_csr_mie_en = csr_op & !op26 & op22 & !op20; + assign o_csr_mcause_en = csr_op & op21 & !op20; + + assign o_csr_source = funct3[1:0]; + assign o_csr_d_sel = funct3[2]; + assign o_csr_imm = o_rf_rs1_addr[0]; + + assign o_csr_addr = (op26 & !op20) ? CSR_MSCRATCH : + (op26 & !op21) ? CSR_MEPC : + (op26) ? CSR_MTVAL : + CSR_MTVEC; + + assign o_alu_cmp_eq = funct3[2:1] == 2'b00; + + assign o_alu_cmp_uns = (funct3[0] & funct3[1]) | (funct3[1] & funct3[2]); + assign o_alu_sh_signed = imm30; + assign o_alu_sh_right = funct3[2]; + + assign o_mem_cmd = opcode[3]; + assign o_mem_signed = ~funct3[2]; + assign o_mem_word = funct3[1]; + assign o_mem_half = funct3[0]; + + assign o_alu_bool_op = funct3[1:0]; + + reg signbit; + + reg [8:0] imm19_12_20; + reg imm7; + reg [5:0] imm30_25; + reg [4:0] imm24_20; + reg [4:0] imm11_7; + + wire [1:0] m2; + //True for OP-IMM, LOAD, STORE, JALR + //False for LUI, AUIPC, JAL + assign m2[0] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00); + assign m2[1] = opcode[4] & !opcode[0]; + wire m3 = opcode[4]; + + assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub + assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift + assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT* + assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool + always @(posedge clk) begin + if (i_wb_en) begin + o_rf_rd_addr <= i_wb_rdt[11:7]; + o_rf_rs1_addr <= i_wb_rdt[19:15]; + o_rf_rs2_addr <= i_wb_rdt[24:20]; + funct3 <= i_wb_rdt[14:12]; + imm30 <= i_wb_rdt[30]; + opcode <= i_wb_rdt[6:2]; + op20 <= i_wb_rdt[20]; + op21 <= i_wb_rdt[21]; + op22 <= i_wb_rdt[22]; + op26 <= i_wb_rdt[26]; + + //Immediate decoder + signbit <= i_wb_rdt[31]; + imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]}; + imm7 <= i_wb_rdt[7]; + imm30_25 <= i_wb_rdt[30:25]; + imm24_20 <= i_wb_rdt[24:20]; + imm11_7 <= i_wb_rdt[11:7]; + end + if (i_cnt_en) begin + imm19_12_20 <= {m3 ? signbit : imm24_20[0], imm19_12_20[8:1]}; + imm7 <= signbit; + imm30_25 <= {m2[1] ? imm7 : m2[0] ? signbit : imm19_12_20[0], imm30_25[5:1]}; + imm24_20 <= {imm30_25[0], imm24_20[4:1]}; + imm11_7 <= {imm30_25[0], imm11_7[4:1]}; + if (csr_op & o_csr_d_sel) + o_rf_rs1_addr <= {1'b0,o_rf_rs1_addr[4:1]}; + end + end + + //True for S (STORE) or B (BRANCH) type instructions + //False for J type instructions + wire m1 = opcode[3:0] == 4'b1000; + + assign o_imm = i_cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]; + + //0 (OP_B_SOURCE_IMM) when OPIMM + //1 (OP_B_SOURCE_RS2) when BRANCH or OP + assign o_op_b_source = opcode[3]; + + assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4]; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_mem_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_mem_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b9ea5cb50b5b09c2119fad52b413e2dc880afdea --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_mem_if.v @@ -0,0 +1,68 @@ +`default_nettype none +module serv_mem_if + #(parameter WITH_CSR = 1) + ( + input wire i_clk, + input wire i_en, + input wire i_mem_op, + input wire i_signed, + input wire i_word, + input wire i_half, + input wire [1:0] i_bytecnt, + input wire i_rs2, + output wire o_rd, + input wire [1:0] i_lsb, + output wire o_misalign, + //External interface + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + reg signbit; + + wire [2:0] tmp = {1'b0,i_bytecnt}+{1'b0,i_lsb}; + + reg [31:0] dat; + + wire dat_en = i_en & !tmp[2]; + + wire dat_cur = + ((i_lsb == 2'd3) & dat[24]) | + ((i_lsb == 2'd2) & dat[16]) | + ((i_lsb == 2'd1) & dat[8]) | + ((i_lsb == 2'd0) & dat[0]); + + wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]); + + assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed); + + assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]); + assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word; + assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]); + assign o_wb_sel[0] = (i_lsb == 2'b00); + + assign o_wb_dat = dat; + + always @(posedge i_clk) begin + if (dat_en) + dat <= {i_rs2, dat[31:1]}; + + if (i_wb_ack) + dat <= i_wb_rdt; + + if (dat_valid) + signbit <= dat_cur; + end + generate + if (WITH_CSR) begin + reg misalign; + always @(posedge i_clk) + misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word); + assign o_misalign = misalign & i_mem_op; + end else begin + assign o_misalign = 1'b0; + end + endgenerate + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_params.vh b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_params.vh new file mode 100644 index 0000000000000000000000000000000000000000..0cf79d96ed485f0846d52efac5338c6a7d9d6552 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_params.vh @@ -0,0 +1,11 @@ +localparam [1:0] + CSR_SOURCE_CSR = 2'b00, + CSR_SOURCE_EXT = 2'b01, + CSR_SOURCE_SET = 2'b10, + CSR_SOURCE_CLR = 2'b11; + +localparam [1:0] + CSR_MSCRATCH = 2'b00, + CSR_MTVEC = 2'b01, + CSR_MEPC = 2'b10, + CSR_MTVAL = 2'b11; diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b26e75f1dba95334cfbf1eaa467facdc6833cb42 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_if.v @@ -0,0 +1,122 @@ +`default_nettype none +module serv_rf_if + #(parameter WITH_CSR = 1) + (//RF Interface + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + //Trap interface + input wire i_trap, + input wire i_mret, + input wire i_mepc, + input wire i_mem_misalign, + input wire i_bufreg_q, + input wire i_bad_pc, + output wire o_csr_pc, + //CSR interface + input wire i_csr_en, + input wire [1:0] i_csr_addr, + input wire i_csr, + output wire o_csr, + //RD write port + input wire i_rd_wen, + input wire [4:0] i_rd_waddr, + input wire i_ctrl_rd, + input wire i_alu_rd, + input wire i_rd_alu_en, + input wire i_csr_rd, + input wire i_rd_csr_en, + input wire i_mem_rd, + + //RS1 read port + input wire [4:0] i_rs1_raddr, + output wire o_rs1, + //RS2 read port + input wire [4:0] i_rs2_raddr, + output wire o_rs2); + + +`include "serv_params.vh" + + /* + ********** Write side *********** + */ + + generate + if (WITH_CSR) begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_csr_rd & i_rd_csr_en) | + (i_mem_rd); + + wire mtval = i_mem_misalign ? i_bufreg_q : i_bad_pc; + + assign o_wdata0 = i_trap ? mtval : rd; + assign o_wdata1 = i_trap ? i_mepc : i_csr; + + //port 0 rd mtval + //port 1 csr mepc + //mepc 100010 + //mtval 100011 + //csr 1000xx + //rd 0xxxxx + assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr}; + assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr}; + + assign o_wen0 = i_trap | i_rd_wen; + assign o_wen1 = i_trap | i_csr_en; + + /* + ********** Read side *********** + */ + + //0 : RS1 + //1 : RS2 / CSR + + + assign o_rreg0 = {1'b0, i_rs1_raddr}; + assign o_rreg1 = + i_trap ? {4'b1000, CSR_MTVEC} : + i_mret ? {4'b1000, CSR_MEPC} : + i_csr_en ? {4'b1000, i_csr_addr} : + {1'b0,i_rs2_raddr}; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + assign o_csr = i_rdata1 & i_csr_en; + assign o_csr_pc = i_rdata1; + + end else begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_mem_rd); + + assign o_wdata0 = rd; + assign o_wdata1 = 1'b0; + + assign o_wreg0 = i_rd_waddr; + assign o_wreg1 = 5'd0; + + assign o_wen0 =i_rd_wen; + assign o_wen1 = 1'b0; + + /* + ********** Read side *********** + */ + + assign o_rreg0 = i_rs1_raddr; + assign o_rreg1 = i_rs2_raddr; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + end // else: !if(WITH_CSR) + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..9bbc503d88e5f71471fc58603c0f87c1b127f092 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_ram.v @@ -0,0 +1,26 @@ +module serv_rf_ram + #(parameter width=0, + parameter csr_regs=4, + parameter depth=32*(32+csr_regs)/width) + (input wire i_clk, + input wire [$clog2(depth)-1:0] i_waddr, + input wire [width-1:0] i_wdata, + input wire i_wen, + input wire [$clog2(depth)-1:0] i_raddr, + output reg [width-1:0] o_rdata); + + reg [width-1:0] memory [0:depth-1]; + + always @(posedge i_clk) begin + if (i_wen) + memory[i_waddr] <= i_wdata; + o_rdata <= memory[i_raddr]; + end + +`ifdef SERV_CLEAR_RAM + integer i; + initial + for (i=0;i 2) + always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]}; + else + always @(posedge i_clk) wdata0_r <= i_wdata0; + endgenerate + + always @(posedge i_clk) begin + wen0_r <= i_wen0; + wen1_r <= i_wen1; + wreq_r <= i_wreq | rgnt; + + wdata1_r <= {i_wdata1,wdata1_r[width-1:1]}; + + if (wgo) + wcnt <= wcnt+5'd1; + + if (wreq_r) begin + wgo <= 1'b1; + end + + if (wcnt == 5'b11111) + wgo <= 1'b0; + + if (i_rst) begin + wcnt <= 5'd0; + end + end + + /* + ********** Read side *********** + */ + + reg [4:0] rcnt; + + wire rtrig0; + reg rtrig1; + + wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0; + generate if (width == 32) + assign o_raddr = rreg; + else + assign o_raddr = {rreg, rcnt[4:l2w]}; + endgenerate + + reg [width-1:0] rdata0; + reg [width-2:0] rdata1; + + assign o_rdata0 = rdata0[0]; + assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0]; + + assign rtrig0 = (rcnt[l2w-1:0] == 1); + + reg rreq_r; + + generate if (width>2) + always @(posedge i_clk) begin + rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize? + if (rtrig1) + rdata1[width-2:0] <= i_rdata[width-1:1]; + end + else + always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1]; + endgenerate + + always @(posedge i_clk) begin + rtrig1 <= rtrig0; + rcnt <= rcnt+5'd1; + if (i_rreq) + rcnt <= 5'd0; + + rreq_r <= i_rreq; + rgnt <= rreq_r; + + rdata0 <= {1'b0,rdata0[width-1:1]}; + if (rtrig0) + rdata0 <= i_rdata; + + if (i_rst) begin + rgnt <= 1'b0; + rreq_r <= 1'b0; + end + end + + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_top.v new file mode 100644 index 0000000000000000000000000000000000000000..ef0ae413261884b55b6fefb4cf18ed5e35a4905b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_rf_top.v @@ -0,0 +1,164 @@ +`default_nettype none + +module serv_rf_top + #(parameter RESET_PC = 32'd0, + parameter WITH_CSR = 1, + parameter RF_WIDTH = 2, + parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH)) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output wire rvfi_valid, + output wire [63:0] rvfi_order, + output wire [31:0] rvfi_insn, + output wire rvfi_trap, + output wire rvfi_halt, + output wire rvfi_intr, + output wire [1:0] rvfi_mode, + output wire [1:0] rvfi_ixl, + output wire [4:0] rvfi_rs1_addr, + output wire [4:0] rvfi_rs2_addr, + output wire [31:0] rvfi_rs1_rdata, + output wire [31:0] rvfi_rs2_rdata, + output wire [4:0] rvfi_rd_addr, + output wire [31:0] rvfi_rd_wdata, + output wire [31:0] rvfi_pc_rdata, + output wire [31:0] rvfi_pc_wdata, + output wire [31:0] rvfi_mem_addr, + output wire [3:0] rvfi_mem_rmask, + output wire [3:0] rvfi_mem_wmask, + output wire [31:0] rvfi_mem_rdata, + output wire [31:0] rvfi_mem_wdata, +`endif + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + localparam CSR_REGS = WITH_CSR*4; + + wire rf_wreq; + wire rf_rreq; + wire [4+WITH_CSR:0] wreg0; + wire [4+WITH_CSR:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [4+WITH_CSR:0] rreg0; + wire [4+WITH_CSR:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + wire [RF_L2D-1:0] waddr; + wire [RF_WIDTH-1:0] wdata; + wire wen; + wire [RF_L2D-1:0] raddr; + wire [RF_WIDTH-1:0] rdata; + + serv_rf_ram_if + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram_if + (.i_clk (clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_rf_ram + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram + (.i_clk (clk), + .i_waddr (waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (raddr), + .o_rdata (rdata)); + + serv_top + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_mode (rvfi_mode ), + .rvfi_ixl (rvfi_ixl ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata (rvfi_rs1_rdata), + .rvfi_rs2_rdata (rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask (rvfi_mem_rmask), + .rvfi_mem_wmask (rvfi_mem_wmask), + .rvfi_mem_rdata (rvfi_mem_rdata), + .rvfi_mem_wdata (rvfi_mem_wdata), +`endif + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_rdt (i_ibus_rdt), + .i_ibus_ack (i_ibus_ack), + + .o_dbus_adr (o_dbus_adr), + .o_dbus_dat (o_dbus_dat), + .o_dbus_sel (o_dbus_sel), + .o_dbus_we (o_dbus_we), + .o_dbus_cyc (o_dbus_cyc), + .i_dbus_rdt (i_dbus_rdt), + .i_dbus_ack (i_dbus_ack)); + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_shift.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_shift.v new file mode 100644 index 0000000000000000000000000000000000000000..70a80db813e0564f80df71c676ba266cf6055d90 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_shift.v @@ -0,0 +1,30 @@ +`default_nettype none +module serv_shift + ( + input wire i_clk, + input wire i_load, + input wire [4:0] i_shamt, + input wire i_shamt_msb, + input wire i_signbit, + input wire i_right, + output wire o_done, + input wire i_d, + output wire o_q); + + reg signbit; + reg [5:0] cnt; + reg wrapped; + + always @(posedge i_clk) begin + cnt <= cnt + 6'd1; + if (i_load) begin + cnt <= 6'd0; + signbit <= i_signbit & i_right; + end + wrapped <= cnt[5] | (i_shamt_msb & !i_right); + end + + assign o_done = (cnt[4:0] == i_shamt); + assign o_q = (i_right^wrapped) ? i_d : signbit; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_state.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_state.v new file mode 100644 index 0000000000000000000000000000000000000000..b919264f8899a6a4b9c93d9ad6bb43c149f6faa6 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_state.v @@ -0,0 +1,153 @@ +module serv_state + ( + input wire i_clk, + input wire i_rst, + input wire i_new_irq, + output wire o_trap_taken, + output reg o_pending_irq, + input wire i_dbus_ack, + input wire i_ibus_ack, + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire o_rf_rd_en, + input wire i_take_branch, + input wire i_branch_op, + input wire i_mem_op, + input wire i_shift_op, + input wire i_slt_op, + input wire i_e_op, + input wire i_rd_op, + output reg o_init, + output reg o_cnt_en, + output wire o_cnt0, + output wire o_cnt0to3, + output wire o_cnt12to31, + output wire o_cnt1, + output wire o_cnt2, + output wire o_cnt3, + output wire o_cnt7, + output wire o_ctrl_pc_en, + output reg o_ctrl_jump, + output wire o_ctrl_trap, + input wire i_ctrl_misalign, + output wire o_alu_shamt_en, + input wire i_alu_sh_done, + output wire o_dbus_cyc, + output wire [1:0] o_mem_bytecnt, + input wire i_mem_misalign, + output reg o_cnt_done, + output wire o_bufreg_hold); + + parameter WITH_CSR = 1; + + wire cnt4; + + reg stage_two_req; + + reg [4:2] o_cnt; + reg [3:0] o_cnt_r; + + //Update PC in RUN or TRAP states + assign o_ctrl_pc_en = o_cnt_en & !o_init; + + + assign o_mem_bytecnt = o_cnt[4:3]; + + assign o_cnt0to3 = (o_cnt[4:2] == 3'd0); + assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11)); + assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0]; + assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1]; + assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2]; + assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3]; + assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0]; + assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3]; + + assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init; + + + //slt*, branch/jump, shift, load/store + wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op; + + reg stage_two_pending; + + assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign; + + wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign); + + //Prepare RF for reads when a new instruction is fetched + // or when stage one caused an exception (rreq implies a write request too) + assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending); + + //Prepare RF for writes when everything is ready to enter stage two + assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending; + + assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init; + + //Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting + assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op); + + always @(posedge i_clk) begin + if (o_cnt_done) + o_ctrl_jump <= o_init & i_take_branch; + + if (o_cnt_en) + stage_two_pending <= o_init; + + o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2]; + + //Need a strobe for the first cycle in the IDLE state after INIT + stage_two_req <= o_cnt_done & o_init; + + if (i_rf_ready & !stage_two_pending) + o_init <= two_stage_op & !o_pending_irq; + + if (o_cnt_done) + o_init <= 1'b0; + + if (i_rf_ready) + o_cnt_en <= 1'b1; + + if (o_cnt_done) + o_cnt_en <= 1'b0; + + o_cnt <= o_cnt + {2'd0,o_cnt_r[3]}; + if (o_cnt_en) + o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]}; + + if (i_rst) begin + o_cnt <= 3'd0; + stage_two_pending <= 1'b0; + o_ctrl_jump <= 1'b0; + o_cnt_r <= 4'b0001; + end + end + + generate + if (WITH_CSR) begin + reg irq_sync; + reg misalign_trap_sync; + + assign o_ctrl_trap = i_e_op | o_pending_irq | misalign_trap_sync; + assign o_trap_taken = i_ibus_ack & o_ctrl_trap; + + always @(posedge i_clk) begin + if (i_ibus_ack) + irq_sync <= 1'b0; + if (i_new_irq) + irq_sync <= 1'b1; + + if (i_ibus_ack) + o_pending_irq <= irq_sync; + + if (stage_two_req) + misalign_trap_sync <= trap_pending; + if (i_ibus_ack) + misalign_trap_sync <= 1'b0; + end // always @ (posedge i_clk) + end else begin + always @(*) + o_pending_irq = 1'b0; + end + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_top.v new file mode 100644 index 0000000000000000000000000000000000000000..65b59b05bc9f9da4d8f99551ebb5fee73f9b5f26 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serv_1.0.2/serv_1.0.2/rtl/serv_top.v @@ -0,0 +1,495 @@ +`default_nettype none + +module serv_top + #(parameter WITH_CSR = 1, + parameter RESET_PC = 32'd0) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output reg rvfi_valid = 1'b0, + output reg [63:0] rvfi_order = 64'd0, + output reg [31:0] rvfi_insn = 32'd0, + output reg rvfi_trap = 1'b0, + output reg rvfi_halt = 1'b0, + output reg rvfi_intr = 1'b0, + output reg [1:0] rvfi_mode = 2'b11, + output reg [1:0] rvfi_ixl = 2'b01, + output reg [4:0] rvfi_rs1_addr, + output reg [4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [3:0] rvfi_mem_rmask, + output reg [3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, +`endif + //RF Interface + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + wire [4:0] rd_addr; + wire [4:0] rs1_addr; + wire [4:0] rs2_addr; + + wire take_branch; + wire e_op; + wire ebreak; + wire branch_op; + wire mem_op; + wire shift_op; + wire slt_op; + wire rd_op; + + wire rd_alu_en; + wire rd_csr_en; + wire ctrl_rd; + wire alu_rd; + wire mem_rd; + wire csr_rd; + + wire ctrl_pc_en; + wire jump; + wire jal_or_jalr; + wire utype; + wire mret; + wire imm; + wire trap; + wire pc_rel; + + wire init; + wire cnt_en; + wire cnt0to3; + wire cnt12to31; + wire cnt0; + wire cnt1; + wire cnt2; + wire cnt3; + wire cnt7; + + wire cnt_done; + + wire bufreg_hold; + wire bufreg_rs1_en; + wire bufreg_imm_en; + wire bufreg_loop; + wire bufreg_q; + + wire alu_sub; + wire [1:0] alu_bool_op; + wire alu_cmp_eq; + wire alu_cmp_uns; + wire alu_cmp; + wire alu_shamt_en; + wire alu_sh_signed; + wire alu_sh_right; + wire alu_sh_done; + wire [3:0] alu_rd_sel; + + wire rs1; + wire rs2; + wire rd_en; + + wire op_b_source; + wire op_b; + + wire mem_signed; + wire mem_word; + wire mem_half; + wire [1:0] mem_bytecnt; + + wire mem_misalign; + + wire bad_pc; + + wire csr_mstatus_en; + wire csr_mie_en; + wire csr_mcause_en; + wire [1:0] csr_source; + wire csr_imm; + wire csr_d_sel; + wire csr_en; + wire [1:0] csr_addr; + wire csr_pc; + + + wire new_irq; + wire trap_taken; + wire pending_irq; + + wire [1:0] lsb; + + serv_state + #(.WITH_CSR (WITH_CSR)) + state + ( + .i_clk (clk), + .i_rst (i_rst), + .i_new_irq (new_irq), + .o_trap_taken (trap_taken), + .o_pending_irq (pending_irq), + .i_dbus_ack (i_dbus_ack), + .i_ibus_ack (i_ibus_ack), + .o_rf_rreq (o_rf_rreq), + .o_rf_wreq (o_rf_wreq), + .i_rf_ready (i_rf_ready), + .o_rf_rd_en (rd_en), + .i_take_branch (take_branch), + .i_branch_op (branch_op), + .i_mem_op (mem_op), + .i_shift_op (shift_op), + .i_slt_op (slt_op), + .i_e_op (e_op), + .i_rd_op (rd_op), + .o_init (init), + .o_cnt_en (cnt_en), + .o_cnt0to3 (cnt0to3), + .o_cnt12to31 (cnt12to31), + .o_cnt0 (cnt0), + .o_cnt1 (cnt1), + .o_cnt2 (cnt2), + .o_cnt3 (cnt3), + .o_cnt7 (cnt7), + .o_cnt_done (cnt_done), + .o_bufreg_hold (bufreg_hold), + .o_ctrl_pc_en (ctrl_pc_en), + .o_ctrl_jump (jump), + .o_ctrl_trap (trap), + .i_ctrl_misalign(lsb[1]), + .o_alu_shamt_en (alu_shamt_en), + .i_alu_sh_done (alu_sh_done), + .o_dbus_cyc (o_dbus_cyc), + .o_mem_bytecnt (mem_bytecnt), + .i_mem_misalign (mem_misalign)); + + wire bufreg_clr_lsb; + + serv_decode decode + ( + .clk (clk), + //Input + .i_cnt_en (cnt_en), + .i_cnt_done (cnt_done), + .i_wb_rdt (i_ibus_rdt[31:2]), + .i_wb_en (o_ibus_cyc & i_ibus_ack), + .i_alu_cmp (alu_cmp), + //To state + .o_take_branch (take_branch), + .o_e_op (e_op), + .o_ebreak (ebreak), + .o_branch_op (branch_op), + .o_mem_op (mem_op), + .o_shift_op (shift_op), + .o_slt_op (slt_op), + .o_rd_op (rd_op), + //To bufreg + .o_bufreg_loop (bufreg_loop), + .o_bufreg_rs1_en (bufreg_rs1_en), + .o_bufreg_imm_en (bufreg_imm_en), + .o_bufreg_clr_lsb (bufreg_clr_lsb), + //To ctrl + .o_ctrl_jal_or_jalr (jal_or_jalr), + .o_ctrl_utype (utype), + .o_ctrl_pc_rel (pc_rel), + .o_ctrl_mret (mret), + //To alu + .o_op_b_source (op_b_source), + .o_alu_sub (alu_sub), + .o_alu_bool_op (alu_bool_op), + .o_alu_cmp_eq (alu_cmp_eq), + .o_alu_cmp_uns (alu_cmp_uns), + .o_alu_sh_signed (alu_sh_signed), + .o_alu_sh_right (alu_sh_right), + .o_alu_rd_sel (alu_rd_sel), + //To RF + .o_rf_rd_addr (rd_addr), + .o_rf_rs1_addr (rs1_addr), + .o_rf_rs2_addr (rs2_addr), + //To mem IF + .o_mem_cmd (o_dbus_we), + .o_mem_signed (mem_signed), + .o_mem_word (mem_word), + .o_mem_half (mem_half), + //To CSR + .o_csr_en (csr_en), + .o_csr_addr (csr_addr), + .o_csr_mstatus_en (csr_mstatus_en), + .o_csr_mie_en (csr_mie_en), + .o_csr_mcause_en (csr_mcause_en), + .o_csr_source (csr_source), + .o_csr_d_sel (csr_d_sel), + .o_csr_imm (csr_imm), + //To top + .o_imm (imm), + .o_rd_csr_en (rd_csr_en), + .o_rd_alu_en (rd_alu_en)); + + serv_bufreg bufreg + ( + .i_clk (clk), + .i_cnt0 (cnt0), + .i_cnt1 (cnt1), + .i_en (!bufreg_hold), + .i_init (init), + .i_loop (bufreg_loop), + .i_rs1 (rs1), + .i_rs1_en (bufreg_rs1_en), + .i_imm (imm), + .i_imm_en (bufreg_imm_en), + .i_clr_lsb (bufreg_clr_lsb), + .o_lsb (lsb), + .o_dbus_adr (o_dbus_adr), + .o_q (bufreg_q)); + + serv_ctrl + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + ctrl + ( + .clk (clk), + .i_rst (i_rst), + //State + .i_pc_en (ctrl_pc_en), + .i_cnt12to31 (cnt12to31), + .i_cnt2 (cnt2), + .i_cnt_done (cnt_done), + //Control + .i_jump (jump), + .i_jal_or_jalr (jal_or_jalr), + .i_utype (utype), + .i_pc_rel (pc_rel), + .i_trap (trap | mret), + //Data + .i_imm (imm), + .i_buf (bufreg_q), + .i_csr_pc (csr_pc), + .o_rd (ctrl_rd), + .o_bad_pc (bad_pc), + //External + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_ack (i_ibus_ack)); + + + serv_alu alu + ( + .clk (clk), + .i_rst (i_rst), + .i_en (cnt_en), + .i_cnt0 (cnt0), + .i_rs1 (rs1), + .i_rs2 (rs2), + .i_imm (imm), + .i_op_b_rs2 (op_b_source), + .i_buf (bufreg_q), + .i_init (init), + .i_cnt_done (cnt_done), + .i_sub (alu_sub), + .i_bool_op (alu_bool_op), + .i_cmp_eq (alu_cmp_eq), + .i_cmp_uns (alu_cmp_uns), + .o_cmp (alu_cmp), + .i_shamt_en (alu_shamt_en), + .i_sh_right (alu_sh_right), + .i_sh_signed (alu_sh_signed), + .o_sh_done (alu_sh_done), + .i_rd_sel (alu_rd_sel), + .o_rd (alu_rd)); + + wire csr_in; + wire rf_csr_out; + + serv_rf_if + #(.WITH_CSR (WITH_CSR)) + rf_if + (//RF interface + .o_wreg0 (o_wreg0), + .o_wreg1 (o_wreg1), + .o_wen0 (o_wen0), + .o_wen1 (o_wen1), + .o_wdata0 (o_wdata0), + .o_wdata1 (o_wdata1), + .o_rreg0 (o_rreg0), + .o_rreg1 (o_rreg1), + .i_rdata0 (i_rdata0), + .i_rdata1 (i_rdata1), + + //Trap interface + .i_trap (trap), + .i_mret (mret), + .i_mepc (o_ibus_adr[0]), + .i_mem_misalign (mem_misalign), + .i_bufreg_q (bufreg_q), + .i_bad_pc (bad_pc), + .o_csr_pc (csr_pc), + //CSR write port + .i_csr_en (csr_en), + .i_csr_addr (csr_addr), + .i_csr (csr_in), + //RD write port + .i_rd_wen (rd_en), + .i_rd_waddr (rd_addr), + .i_ctrl_rd (ctrl_rd), + .i_alu_rd (alu_rd), + .i_rd_alu_en (rd_alu_en), + .i_csr_rd (csr_rd), + .i_rd_csr_en (rd_csr_en), + .i_mem_rd (mem_rd), + + //RS1 read port + .i_rs1_raddr (rs1_addr), + .o_rs1 (rs1), + //RS2 read port + .i_rs2_raddr (rs2_addr), + .o_rs2 (rs2), + + //CSR read port + .o_csr (rf_csr_out)); + + serv_mem_if + #(.WITH_CSR (WITH_CSR)) + mem_if + ( + .i_clk (clk), + .i_en (cnt_en), + .i_mem_op (mem_op), + .i_signed (mem_signed), + .i_word (mem_word), + .i_half (mem_half), + .i_bytecnt (mem_bytecnt), + .i_rs2 (rs2), + .o_rd (mem_rd), + .i_lsb (lsb), + .o_misalign (mem_misalign), + //External interface + .o_wb_dat (o_dbus_dat), + .o_wb_sel (o_dbus_sel), + .i_wb_rdt (i_dbus_rdt), + .i_wb_ack (i_dbus_ack)); + + generate + if (WITH_CSR) begin + serv_csr csr + ( + .i_clk (clk), + .i_en (cnt_en), + .i_cnt0to3 (cnt0to3), + .i_cnt2 (cnt2), + .i_cnt3 (cnt3), + .i_cnt7 (cnt7), + .i_cnt_done (cnt_done), + .i_e_op (e_op), + .i_ebreak (ebreak), + .i_mem_cmd (o_dbus_we), + .i_mem_misalign (mem_misalign), + .i_rf_csr_out (rf_csr_out), + .o_csr_in (csr_in), + .i_mtip (i_timer_irq), + .o_new_irq (new_irq), + .i_trap_taken (trap_taken), + .i_pending_irq (pending_irq), + .i_mstatus_en (csr_mstatus_en), + .i_mie_en (csr_mie_en ), + .i_mcause_en (csr_mcause_en ), + .i_csr_source (csr_source), + .i_mret (mret), + .i_d (csr_d_sel ? csr_imm : rs1), + .o_q (csr_rd)); + end else begin + assign csr_in = 1'b0; + assign csr_rd = 1'b0; + assign new_irq = 1'b0; + end + endgenerate + + +`ifdef RISCV_FORMAL + reg [31:0] pc = RESET_PC; + + wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en; + + always @(posedge clk) begin + rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst; + rvfi_order <= rvfi_order + {63'd0,rvfi_valid}; + if (o_ibus_cyc & i_ibus_ack) + rvfi_insn <= i_ibus_rdt; + if (o_wen0) + rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]}; + if (cnt_done & ctrl_pc_en) begin + rvfi_pc_rdata <= pc; + if (!rd_en) + rvfi_rd_addr <= 5'd0; + if (!rd_en | !(|rd_addr)) + rvfi_rd_wdata <= 32'd0; + end + rvfi_trap <= trap; + if (rvfi_valid) begin + rvfi_trap <= 1'b0; + pc <= rvfi_pc_wdata; + end + + rvfi_halt <= 1'b0; + rvfi_intr <= 1'b0; + rvfi_mode <= 2'd3; + rvfi_ixl = 2'd1; + if (i_rf_ready) begin + rvfi_rs1_addr <= rs1_addr; + rvfi_rs2_addr <= rs2_addr; + rvfi_rd_addr <= rd_addr; + end + if (rs_en) begin + rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]}; + rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]}; + end + + if (i_dbus_ack) begin + rvfi_mem_addr <= o_dbus_adr; + rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel; + rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000; + rvfi_mem_rdata <= i_dbus_rdt; + rvfi_mem_wdata <= o_dbus_dat; + end + if (i_ibus_ack) begin + rvfi_mem_rmask <= 4'b0000; + rvfi_mem_wmask <= 4'b0000; + end + end + /* verilator lint_off COMBDLY */ + always @(o_ibus_adr) + rvfi_pc_wdata <= o_ibus_adr; + /* verilator lint_on COMBDLY */ + + +`endif + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving.v new file mode 100644 index 0000000000000000000000000000000000000000..374bab40a12ffd914db04336c0c9a3516b30b556 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving.v @@ -0,0 +1,232 @@ +/* serving.v : Top-level for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving + ( + input wire i_clk, + input wire i_rst, + input wire i_timer_irq, + + output wire [31:0] o_wb_adr, + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + output wire o_wb_we , + output wire o_wb_stb, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + parameter memfile = ""; + parameter memsize = 8192; + parameter WITH_CSR = 1; + localparam regs = 32+WITH_CSR*4; + + localparam rf_width = 8; + + localparam aw = $clog2(memsize); + + wire [31:0] wb_ibus_adr; + wire wb_ibus_stb; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_ack; + + wire [31:0] wb_dbus_adr; + wire [31:0] wb_dbus_dat; + wire [3:0] wb_dbus_sel; + wire wb_dbus_we; + wire wb_dbus_stb; + wire [31:0] wb_dbus_rdt; + wire wb_dbus_ack; + + wire [31:0] wb_dmem_adr; + wire [31:0] wb_dmem_dat; + wire [3:0] wb_dmem_sel; + wire wb_dmem_we; + wire wb_dmem_stb; + wire [31:0] wb_dmem_rdt; + wire wb_dmem_ack; + + wire [31:0] wb_mem_adr; + wire [31:0] wb_mem_dat; + wire [3:0] wb_mem_sel; + wire wb_mem_we; + wire wb_mem_stb; + wire [31:0] wb_mem_rdt; + wire wb_mem_ack; + + wire [6+WITH_CSR:0] waddr; + wire [rf_width-1:0] wdata; + wire wen; + wire [6+WITH_CSR:0] raddr; + wire [rf_width-1:0] rdata; + + + wire [aw-1:0] rf_waddr = ~{{aw-2-5-WITH_CSR{1'b0}},waddr}; + wire [aw-1:0] rf_raddr = ~{{aw-2-5-WITH_CSR{1'b0}},raddr}; + + serving_arbiter arbiter + (.i_wb_cpu_dbus_adr (wb_dmem_adr), + .i_wb_cpu_dbus_dat (wb_dmem_dat), + .i_wb_cpu_dbus_sel (wb_dmem_sel), + .i_wb_cpu_dbus_we (wb_dmem_we ), + .i_wb_cpu_dbus_stb (wb_dmem_stb), + .o_wb_cpu_dbus_rdt (wb_dmem_rdt), + .o_wb_cpu_dbus_ack (wb_dmem_ack), + + .i_wb_cpu_ibus_adr (wb_ibus_adr), + .i_wb_cpu_ibus_stb (wb_ibus_stb), + .o_wb_cpu_ibus_rdt (wb_ibus_rdt), + .o_wb_cpu_ibus_ack (wb_ibus_ack), + + .o_wb_mem_adr (wb_mem_adr), + .o_wb_mem_dat (wb_mem_dat), + .o_wb_mem_sel (wb_mem_sel), + .o_wb_mem_we (wb_mem_we ), + .o_wb_mem_stb (wb_mem_stb), + .i_wb_mem_rdt (wb_mem_rdt), + .i_wb_mem_ack (wb_mem_ack)); + + serving_mux mux + (.i_clk (i_clk), + .i_rst (i_rst), + + .i_wb_cpu_adr (wb_dbus_adr), + .i_wb_cpu_dat (wb_dbus_dat), + .i_wb_cpu_sel (wb_dbus_sel), + .i_wb_cpu_we (wb_dbus_we), + .i_wb_cpu_stb (wb_dbus_stb), + .o_wb_cpu_rdt (wb_dbus_rdt), + .o_wb_cpu_ack (wb_dbus_ack), + + .o_wb_mem_adr (wb_dmem_adr), + .o_wb_mem_dat (wb_dmem_dat), + .o_wb_mem_sel (wb_dmem_sel), + .o_wb_mem_we (wb_dmem_we), + .o_wb_mem_stb (wb_dmem_stb), + .i_wb_mem_rdt (wb_dmem_rdt), + .i_wb_mem_ack (wb_dmem_ack), + + .o_wb_ext_adr (o_wb_adr), + .o_wb_ext_dat (o_wb_dat), + .o_wb_ext_sel (o_wb_sel), + .o_wb_ext_we (o_wb_we), + .o_wb_ext_stb (o_wb_stb), + .i_wb_ext_rdt (i_wb_rdt), + .i_wb_ext_ack (i_wb_ack)); + + serving_ram + #(.memfile (memfile), + .depth (memsize)) + ram + (// Wishbone interface + .i_clk (i_clk), + .i_waddr (rf_waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (rf_raddr), + .o_rdata (rdata), + .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), + .i_wb_stb (wb_mem_stb), + .i_wb_we (wb_mem_we) , + .i_wb_sel (wb_mem_sel), + .i_wb_dat (wb_mem_dat), + .o_wb_rdt (wb_mem_rdt), + .o_wb_ack (wb_mem_ack)); + + localparam RF_L2W = $clog2(rf_width); + + wire rf_wreq; + wire rf_rreq; + wire [$clog2(regs)-1:0] wreg0; + wire [$clog2(regs)-1:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [$clog2(regs)-1:0] rreg0; + wire [$clog2(regs)-1:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + + serv_rf_ram_if + #(.width (rf_width), + .csr_regs (WITH_CSR*4)) + rf_ram_if + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_top + #(.RESET_PC (32'h0000_0000), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), + //RF IF + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + //Instruction bus + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_stb), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + //Data bus + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_stb), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_arbiter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..9d537d4a46297b5f8902f134ada0dcba4a8cae2d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_arbiter.v @@ -0,0 +1,57 @@ +/* serving_arbiter.v : I/D arbiter for the serving SoC + * Relies on the fact that not both masters are active at the same time + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_arbiter + ( + input wire [31:0] i_wb_cpu_dbus_adr, + input wire [31:0] i_wb_cpu_dbus_dat, + input wire [3:0] i_wb_cpu_dbus_sel, + input wire i_wb_cpu_dbus_we, + input wire i_wb_cpu_dbus_stb, + output wire [31:0] o_wb_cpu_dbus_rdt, + output wire o_wb_cpu_dbus_ack, + + input wire [31:0] i_wb_cpu_ibus_adr, + input wire i_wb_cpu_ibus_stb, + output wire [31:0] o_wb_cpu_ibus_rdt, + output wire o_wb_cpu_ibus_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack); + + assign o_wb_cpu_dbus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_dbus_ack = i_wb_mem_ack & !i_wb_cpu_ibus_stb; + + assign o_wb_cpu_ibus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_ibus_ack = i_wb_mem_ack & i_wb_cpu_ibus_stb; + + assign o_wb_mem_adr = i_wb_cpu_ibus_stb ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr; + assign o_wb_mem_dat = i_wb_cpu_dbus_dat; + assign o_wb_mem_sel = i_wb_cpu_dbus_sel; + assign o_wb_mem_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_stb; + assign o_wb_mem_stb = i_wb_cpu_ibus_stb | i_wb_cpu_dbus_stb; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..daa1be8e3a714496eb611905cd1070f3f4610548 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_mux.v @@ -0,0 +1,66 @@ +/* serving_mux.v : Simple Wishbone mux for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_mux + ( + input wire i_clk, + input wire i_rst, + + input wire [31:0] i_wb_cpu_adr, + input wire [31:0] i_wb_cpu_dat, + input wire [3:0] i_wb_cpu_sel, + input wire i_wb_cpu_we, + input wire i_wb_cpu_stb, + output wire [31:0] o_wb_cpu_rdt, + output wire o_wb_cpu_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack, + + output wire [31:0] o_wb_ext_adr, + output wire [31:0] o_wb_ext_dat, + output wire [3:0] o_wb_ext_sel, + output wire o_wb_ext_we, + output wire o_wb_ext_stb, + input wire [31:0] i_wb_ext_rdt, + input wire i_wb_ext_ack); + + wire ext = (i_wb_cpu_adr[31:30] != 2'b00); + + assign o_wb_cpu_rdt = ext ? i_wb_ext_rdt : i_wb_mem_rdt; + assign o_wb_cpu_ack = ext ? i_wb_ext_ack : i_wb_mem_ack; + + assign o_wb_mem_adr = i_wb_cpu_adr; + assign o_wb_mem_dat = i_wb_cpu_dat; + assign o_wb_mem_sel = i_wb_cpu_sel; + assign o_wb_mem_we = i_wb_cpu_we; + assign o_wb_mem_stb = i_wb_cpu_stb & !ext; + + assign o_wb_ext_adr = i_wb_cpu_adr; + assign o_wb_ext_dat = i_wb_cpu_dat; + assign o_wb_ext_sel = i_wb_cpu_sel; + assign o_wb_ext_we = i_wb_cpu_we; + assign o_wb_ext_stb = i_wb_cpu_stb & ext; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..b58c22458ee44e8055be281376ce33697b624b79 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/serving_1.0.2/serving/serving_ram.v @@ -0,0 +1,83 @@ +/* serving_ram.v : Shared RF I/D SRAM for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving_ram + #(//Memory parameters + parameter depth = 256, + parameter aw = $clog2(depth), + parameter memfile = "") + (input wire i_clk, + input wire [aw-1:0] i_waddr, + input wire [7:0] i_wdata, + input wire i_wen, + input wire [aw-1:0] i_raddr, + output wire [7:0] o_rdata, + + input wire [aw-1:2] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire [3:0] i_wb_sel, + input wire i_wb_we, + input wire i_wb_stb, + output wire [31:0] o_wb_rdt, + output reg o_wb_ack); + + wire wb_en = i_wb_stb & !i_wen & !o_wb_ack; + + wire wb_we = i_wb_we & i_wb_sel[bsel]; + + wire we = wb_en ? wb_we : i_wen; + + reg [7:0] mem [0:depth-1] /* verilator public */; + + wire [aw-1:0] waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_waddr; + wire [7:0] wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata; + wire [aw-1:0] raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr; + + reg [2:0] wb_en_r; + + reg [1:0] bsel; + + reg [23:0] wb_rdt; + assign o_wb_rdt = {rdata, wb_rdt}; + + always @(posedge i_clk) begin + if (wb_en) bsel <= bsel + 2'd1; + wb_en_r <= {wb_en_r[1:0], wb_en}; + o_wb_ack <= wb_en & &bsel; + if (bsel == 2'b01) wb_rdt[7:0] <= rdata; + if (bsel == 2'b10) wb_rdt[15:8] <= rdata; + if (bsel == 2'b11) wb_rdt[23:16] <= rdata; + end + + reg [7:0] rdata; + + always @(posedge i_clk) begin + if (we) mem[waddr] <= wdata; + rdata <= mem[raddr]; + end + + initial + if(|memfile) begin + $display("Preloading %m from %s", memfile); + $readmemh(memfile, mem); + end + + assign o_rdata = rdata; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/arbiter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..3612fc45948a4e436e9d4333f8edc8ab4af79c75 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/arbiter.v @@ -0,0 +1,153 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Arbiter module + */ +module arbiter # +( + parameter PORTS = 4, + // arbitration type: "PRIORITY" or "ROUND_ROBIN" + parameter TYPE = "PRIORITY", + // block type: "NONE", "REQUEST", "ACKNOWLEDGE" + parameter BLOCK = "NONE", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" +) +( + input wire clk, + input wire rst, + + input wire [PORTS-1:0] request, + input wire [PORTS-1:0] acknowledge, + + output wire [PORTS-1:0] grant, + output wire grant_valid, + output wire [$clog2(PORTS)-1:0] grant_encoded +); + +reg [PORTS-1:0] grant_reg = 0, grant_next; +reg grant_valid_reg = 0, grant_valid_next; +reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next; + +assign grant_valid = grant_valid_reg; +assign grant = grant_reg; +assign grant_encoded = grant_encoded_reg; + +wire request_valid; +wire [$clog2(PORTS)-1:0] request_index; +wire [PORTS-1:0] request_mask; + +priority_encoder #( + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) +) +priority_encoder_inst ( + .input_unencoded(request), + .output_valid(request_valid), + .output_encoded(request_index), + .output_unencoded(request_mask) +); + +reg [PORTS-1:0] mask_reg = 0, mask_next; + +wire masked_request_valid; +wire [$clog2(PORTS)-1:0] masked_request_index; +wire [PORTS-1:0] masked_request_mask; + +priority_encoder #( + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) +) +priority_encoder_masked ( + .input_unencoded(request & mask_reg), + .output_valid(masked_request_valid), + .output_encoded(masked_request_index), + .output_unencoded(masked_request_mask) +); + +always @* begin + grant_next = 0; + grant_valid_next = 0; + grant_encoded_next = 0; + mask_next = mask_reg; + + if (BLOCK == "REQUEST" && |(grant_reg & request)) begin + // granted request still asserted; hold it + grant_valid_next = grant_valid_reg; + grant_next = grant_reg; + grant_encoded_next = grant_encoded_reg; + end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(|(grant_reg & acknowledge))) begin + // granted request not yet acknowledged; hold it + grant_valid_next = grant_valid_reg; + grant_next = grant_reg; + grant_encoded_next = grant_encoded_reg; + end else if (request_valid) begin + if (TYPE == "PRIORITY") begin + grant_valid_next = 1; + grant_next = request_mask; + grant_encoded_next = request_index; + end else if (TYPE == "ROUND_ROBIN") begin + if (masked_request_valid) begin + grant_valid_next = 1; + grant_next = masked_request_mask; + grant_encoded_next = masked_request_index; + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index); + end else begin + mask_next = {PORTS{1'b1}} << (masked_request_index + 1); + end + end else begin + grant_valid_next = 1; + grant_next = request_mask; + grant_encoded_next = request_index; + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - request_index); + end else begin + mask_next = {PORTS{1'b1}} << (request_index + 1); + end + end + end + end +end + +always @(posedge clk) begin + if (rst) begin + grant_reg <= 0; + grant_valid_reg <= 0; + grant_encoded_reg <= 0; + mask_reg <= 0; + end else begin + grant_reg <= grant_next; + grant_valid_reg <= grant_valid_next; + grant_encoded_reg <= grant_encoded_next; + mask_reg <= mask_next; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/axis_arb_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/axis_arb_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..56b9cc8d8eabb5cad59561fb27a24586f347bbc8 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/axis_arb_mux.v @@ -0,0 +1,249 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * AXI4-Stream arbitrated multiplexer + */ +module axis_arb_mux # +( + // Number of AXI stream inputs + parameter S_COUNT = 4, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = (DATA_WIDTH/8), + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // arbitration type: "PRIORITY" or "ROUND_ROBIN" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" +) +( + input wire clk, + input wire rst, + + /* + * AXI Stream inputs + */ + input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata, + input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep, + input wire [S_COUNT-1:0] s_axis_tvalid, + output wire [S_COUNT-1:0] s_axis_tready, + input wire [S_COUNT-1:0] s_axis_tlast, + input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid, + input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest, + input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI Stream output + */ + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser +); + +parameter CL_S_COUNT = $clog2(S_COUNT); + +wire [S_COUNT-1:0] request; +wire [S_COUNT-1:0] acknowledge; +wire [S_COUNT-1:0] grant; +wire grant_valid; +wire [CL_S_COUNT-1:0] grant_encoded; + +// internal datapath +reg [DATA_WIDTH-1:0] m_axis_tdata_int; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; +reg m_axis_tvalid_int; +reg m_axis_tready_int_reg = 1'b0; +reg m_axis_tlast_int; +reg [ID_WIDTH-1:0] m_axis_tid_int; +reg [DEST_WIDTH-1:0] m_axis_tdest_int; +reg [USER_WIDTH-1:0] m_axis_tuser_int; +wire m_axis_tready_int_early; + +assign s_axis_tready = {{S_COUNT-1{1'b0}},(m_axis_tready_int_reg && grant_valid)} << grant_encoded; + +// mux for incoming packet +wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH]; +wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH]; +wire current_s_tvalid = s_axis_tvalid[grant_encoded]; +wire current_s_tready = s_axis_tready[grant_encoded]; +wire current_s_tlast = s_axis_tlast[grant_encoded]; +wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH]; +wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; +wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; + +// arbiter instance +arbiter #( + .PORTS(S_COUNT), + .TYPE(ARB_TYPE), + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) +) +arb_inst ( + .clk(clk), + .rst(rst), + .request(request), + .acknowledge(acknowledge), + .grant(grant), + .grant_valid(grant_valid), + .grant_encoded(grant_encoded) +); + +assign request = s_axis_tvalid & ~grant; +assign acknowledge = grant & s_axis_tvalid & s_axis_tready & s_axis_tlast; + +always @* begin + // pass through selected packet data + m_axis_tdata_int = current_s_tdata; + m_axis_tkeep_int = current_s_tkeep; + m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid; + m_axis_tlast_int = current_s_tlast; + m_axis_tid_int = current_s_tid; + m_axis_tdest_int = current_s_tdest; + m_axis_tuser_int = current_s_tuser; +end + +// output datapath logic +reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; +reg m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; +reg temp_m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +// datapath control +reg store_axis_int_to_output; +reg store_axis_int_to_temp; +reg store_axis_temp_to_output; + +assign m_axis_tdata = m_axis_tdata_reg; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; +assign m_axis_tvalid = m_axis_tvalid_reg; +assign m_axis_tlast = m_axis_tlast_reg; +assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); + +always @* begin + // transfer sink ready state to source + m_axis_tvalid_next = m_axis_tvalid_reg; + temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_axis_temp_to_output = 1'b0; + + if (m_axis_tready_int_reg) begin + // input is ready + if (m_axis_tready || !m_axis_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_axis_tready) begin + // input is not ready, but output is ready + m_axis_tvalid_next = temp_m_axis_tvalid_reg; + temp_m_axis_tvalid_next = 1'b0; + store_axis_temp_to_output = 1'b1; + end +end + +always @(posedge clk) begin + if (rst) begin + m_axis_tvalid_reg <= 1'b0; + m_axis_tready_int_reg <= 1'b0; + temp_m_axis_tvalid_reg <= 1'b0; + end else begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + m_axis_tready_int_reg <= m_axis_tready_int_early; + temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; + end + + // datapath + if (store_axis_int_to_output) begin + m_axis_tdata_reg <= m_axis_tdata_int; + m_axis_tkeep_reg <= m_axis_tkeep_int; + m_axis_tlast_reg <= m_axis_tlast_int; + m_axis_tid_reg <= m_axis_tid_int; + m_axis_tdest_reg <= m_axis_tdest_int; + m_axis_tuser_reg <= m_axis_tuser_int; + end else if (store_axis_temp_to_output) begin + m_axis_tdata_reg <= temp_m_axis_tdata_reg; + m_axis_tkeep_reg <= temp_m_axis_tkeep_reg; + m_axis_tlast_reg <= temp_m_axis_tlast_reg; + m_axis_tid_reg <= temp_m_axis_tid_reg; + m_axis_tdest_reg <= temp_m_axis_tdest_reg; + m_axis_tuser_reg <= temp_m_axis_tuser_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_axis_tdata_reg <= m_axis_tdata_int; + temp_m_axis_tkeep_reg <= m_axis_tkeep_int; + temp_m_axis_tlast_reg <= m_axis_tlast_int; + temp_m_axis_tid_reg <= m_axis_tid_int; + temp_m_axis_tdest_reg <= m_axis_tdest_int; + temp_m_axis_tuser_reg <= m_axis_tuser_int; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/axis_async_fifo.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/axis_async_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..39ac3498d5b4ac6b5a395831d85d82f0441798ff --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/axis_async_fifo.v @@ -0,0 +1,538 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * AXI4-Stream asynchronous FIFO + */ +module axis_async_fifo # +( + // FIFO depth in words + // KEEP_WIDTH words per cycle if KEEP_ENABLE set + // Rounded up to nearest power of 2 cycles + parameter DEPTH = 4096, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + // If disabled, tkeep assumed to be 1'b1 + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = (DATA_WIDTH/8), + // Propagate tlast signal + parameter LAST_ENABLE = 1, + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // Frame FIFO mode - operate on frames instead of cycles + // When set, m_axis_tvalid will not be deasserted within a frame + // Requires LAST_ENABLE set + parameter FRAME_FIFO = 0, + // tuser value for bad frame marker + parameter USER_BAD_FRAME_VALUE = 1'b1, + // tuser mask for bad frame marker + parameter USER_BAD_FRAME_MASK = 1'b1, + // Drop frames marked bad + // Requires FRAME_FIFO set + parameter DROP_BAD_FRAME = 0, + // Drop incoming frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO set + parameter DROP_WHEN_FULL = 0 +) +( + /* + * Common asynchronous reset + */ + input wire async_rst, + + /* + * AXI input + */ + input wire s_clk, + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI output + */ + input wire m_clk, + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser, + + /* + * Status + */ + output wire s_status_overflow, + output wire s_status_bad_frame, + output wire s_status_good_frame, + output wire m_status_overflow, + output wire m_status_bad_frame, + output wire m_status_good_frame +); + +parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH); + +// check configuration +initial begin + if (FRAME_FIFO && !LAST_ENABLE) begin + $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && !FRAME_FIFO) begin + $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)"); + $finish; + end + + if (DROP_WHEN_FULL && !FRAME_FIFO) begin + $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin + $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); + $finish; + end +end + +localparam KEEP_OFFSET = DATA_WIDTH; +localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0); +localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0); +localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0); +localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); +localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); + +reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next; +reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next; +reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next; +reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_sync_gray_next; +reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_gray_next; +reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next; +reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next; +reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}}; + +reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; + +reg wr_ptr_update_valid_reg = 1'b0, wr_ptr_update_valid_next; +reg wr_ptr_update_reg = 1'b0, wr_ptr_update_next; +reg wr_ptr_update_sync1_reg = 1'b0; +reg wr_ptr_update_sync2_reg = 1'b0; +reg wr_ptr_update_sync3_reg = 1'b0; +reg wr_ptr_update_ack_sync1_reg = 1'b0; +reg wr_ptr_update_ack_sync2_reg = 1'b0; + +reg s_rst_sync1_reg = 1'b1; +reg s_rst_sync2_reg = 1'b1; +reg s_rst_sync3_reg = 1'b1; +reg m_rst_sync1_reg = 1'b1; +reg m_rst_sync2_reg = 1'b1; +reg m_rst_sync3_reg = 1'b1; + +reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; +reg [WIDTH-1:0] mem_read_data_reg; +reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; + +wire [WIDTH-1:0] s_axis; + +reg [WIDTH-1:0] m_axis_reg; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; + +// full when first TWO MSBs do NOT match, but rest matches +// (gray code equivalent of first MSB different but rest same) +wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && + (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && + (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); +wire full_cur = ((wr_ptr_cur_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && + (wr_ptr_cur_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && + (wr_ptr_cur_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); +// empty when pointers match exactly +wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg); +// overflow within packet +wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) && + (wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0])); + +// control signals +reg write; +reg read; +reg store_output; + +reg drop_frame_reg = 1'b0, drop_frame_next; +reg overflow_reg = 1'b0, overflow_next; +reg bad_frame_reg = 1'b0, bad_frame_next; +reg good_frame_reg = 1'b0, good_frame_next; + +reg overflow_sync1_reg = 1'b0; +reg overflow_sync2_reg = 1'b0; +reg overflow_sync3_reg = 1'b0; +reg overflow_sync4_reg = 1'b0; +reg bad_frame_sync1_reg = 1'b0; +reg bad_frame_sync2_reg = 1'b0; +reg bad_frame_sync3_reg = 1'b0; +reg bad_frame_sync4_reg = 1'b0; +reg good_frame_sync1_reg = 1'b0; +reg good_frame_sync2_reg = 1'b0; +reg good_frame_sync3_reg = 1'b0; +reg good_frame_sync4_reg = 1'b0; + +assign s_axis_tready = (FRAME_FIFO ? (!full_cur || full_wr || DROP_WHEN_FULL) : !full) && !s_rst_sync3_reg; + +generate + assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; + if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; + if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast; + if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; + if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; + if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; +endgenerate + +assign m_axis_tvalid = m_axis_tvalid_reg; + +assign m_axis_tdata = m_axis_reg[DATA_WIDTH-1:0]; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; +assign m_axis_tlast = LAST_ENABLE ? m_axis_reg[LAST_OFFSET] : 1'b1; +assign m_axis_tid = ID_ENABLE ? m_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; + +assign s_status_overflow = overflow_reg; +assign s_status_bad_frame = bad_frame_reg; +assign s_status_good_frame = good_frame_reg; + +assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg; +assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg; +assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg; + +// reset synchronization +always @(posedge s_clk or posedge async_rst) begin + if (async_rst) begin + s_rst_sync1_reg <= 1'b1; + s_rst_sync2_reg <= 1'b1; + s_rst_sync3_reg <= 1'b1; + end else begin + s_rst_sync1_reg <= 1'b0; + s_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg; + s_rst_sync3_reg <= s_rst_sync2_reg; + end +end + +always @(posedge m_clk or posedge async_rst) begin + if (async_rst) begin + m_rst_sync1_reg <= 1'b1; + m_rst_sync2_reg <= 1'b1; + m_rst_sync3_reg <= 1'b1; + end else begin + m_rst_sync1_reg <= 1'b0; + m_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg; + m_rst_sync3_reg <= m_rst_sync2_reg; + end +end + +// Write logic +always @* begin + write = 1'b0; + + drop_frame_next = drop_frame_reg; + overflow_next = 1'b0; + bad_frame_next = 1'b0; + good_frame_next = 1'b0; + + wr_ptr_next = wr_ptr_reg; + wr_ptr_cur_next = wr_ptr_cur_reg; + wr_ptr_gray_next = wr_ptr_gray_reg; + wr_ptr_sync_gray_next = wr_ptr_sync_gray_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_gray_reg; + + wr_ptr_update_valid_next = wr_ptr_update_valid_reg; + wr_ptr_update_next = wr_ptr_update_reg; + + if (FRAME_FIFO && wr_ptr_update_valid_reg) begin + // have updated pointer to sync + if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_next = 1'b0; + wr_ptr_sync_gray_next = wr_ptr_gray_reg; + wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg; + end + end + + if (s_axis_tready && s_axis_tvalid) begin + // transfer in + if (!FRAME_FIFO) begin + // normal FIFO mode + write = 1'b1; + wr_ptr_next = wr_ptr_reg + 1; + wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); + end else if (full_cur || full_wr || drop_frame_reg) begin + // full, packet overflow, or currently dropping frame + // drop frame + drop_frame_next = 1'b1; + if (s_axis_tlast) begin + // end of frame, reset write pointer + wr_ptr_cur_next = wr_ptr_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + drop_frame_next = 1'b0; + overflow_next = 1'b1; + end + end else begin + write = 1'b1; + wr_ptr_cur_next = wr_ptr_cur_reg + 1; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + if (s_axis_tlast) begin + // end of frame + if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin + // bad packet, reset write pointer + wr_ptr_cur_next = wr_ptr_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + bad_frame_next = 1'b1; + end else begin + // good packet, update write pointer + wr_ptr_next = wr_ptr_cur_reg + 1; + wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); + + if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_next = 1'b0; + wr_ptr_sync_gray_next = wr_ptr_gray_next; + wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg; + end else begin + // sync in progress; flag it for later + wr_ptr_update_valid_next = 1'b1; + end + + good_frame_next = 1'b1; + end + end + end + end +end + +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_update_reg <= 1'b0; + + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b0; + bad_frame_reg <= 1'b0; + good_frame_reg <= 1'b0; + end else begin + wr_ptr_reg <= wr_ptr_next; + wr_ptr_cur_reg <= wr_ptr_cur_next; + wr_ptr_gray_reg <= wr_ptr_gray_next; + wr_ptr_sync_gray_reg <= wr_ptr_sync_gray_next; + wr_ptr_cur_gray_reg <= wr_ptr_cur_gray_next; + + wr_ptr_update_valid_reg <= wr_ptr_update_valid_next; + wr_ptr_update_reg <= wr_ptr_update_next; + + drop_frame_reg <= drop_frame_next; + overflow_reg <= overflow_next; + bad_frame_reg <= bad_frame_next; + good_frame_reg <= good_frame_next; + end + + if (FRAME_FIFO) begin + wr_addr_reg <= wr_ptr_cur_next; + end else begin + wr_addr_reg <= wr_ptr_next; + end + + if (write) begin + mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= s_axis; + end +end + +// pointer synchronization +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}}; + rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_update_ack_sync1_reg <= 1'b0; + wr_ptr_update_ack_sync2_reg <= 1'b0; + end else begin + rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg; + rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg; + wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg; + wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_update_sync1_reg <= 1'b0; + wr_ptr_update_sync2_reg <= 1'b0; + wr_ptr_update_sync3_reg <= 1'b0; + end else begin + if (!FRAME_FIFO) begin + wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg; + end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin + wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg; + end + wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg; + wr_ptr_update_sync1_reg <= wr_ptr_update_reg; + wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg; + wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg; + end +end + +// status synchronization +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + overflow_sync1_reg <= 1'b0; + bad_frame_sync1_reg <= 1'b0; + good_frame_sync1_reg <= 1'b0; + end else begin + overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg; + bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg; + good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + overflow_sync2_reg <= 1'b0; + overflow_sync3_reg <= 1'b0; + overflow_sync4_reg <= 1'b0; + bad_frame_sync2_reg <= 1'b0; + bad_frame_sync3_reg <= 1'b0; + bad_frame_sync4_reg <= 1'b0; + good_frame_sync2_reg <= 1'b0; + good_frame_sync3_reg <= 1'b0; + good_frame_sync4_reg <= 1'b0; + end else begin + overflow_sync2_reg <= overflow_sync1_reg; + overflow_sync3_reg <= overflow_sync2_reg; + overflow_sync4_reg <= overflow_sync3_reg; + bad_frame_sync2_reg <= bad_frame_sync1_reg; + bad_frame_sync3_reg <= bad_frame_sync2_reg; + bad_frame_sync4_reg <= bad_frame_sync3_reg; + good_frame_sync2_reg <= good_frame_sync1_reg; + good_frame_sync3_reg <= good_frame_sync2_reg; + good_frame_sync4_reg <= good_frame_sync3_reg; + end +end + +// Read logic +always @* begin + read = 1'b0; + + rd_ptr_next = rd_ptr_reg; + rd_ptr_gray_next = rd_ptr_gray_reg; + + mem_read_data_valid_next = mem_read_data_valid_reg; + + if (store_output || !mem_read_data_valid_reg) begin + // output data not valid OR currently being transferred + if (!empty) begin + // not empty, perform read + read = 1'b1; + mem_read_data_valid_next = 1'b1; + rd_ptr_next = rd_ptr_reg + 1; + rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1); + end else begin + // empty, invalidate + mem_read_data_valid_next = 1'b0; + end + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + mem_read_data_valid_reg <= 1'b0; + end else begin + rd_ptr_reg <= rd_ptr_next; + rd_ptr_gray_reg <= rd_ptr_gray_next; + mem_read_data_valid_reg <= mem_read_data_valid_next; + end + + rd_addr_reg <= rd_ptr_next; + + if (read) begin + mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]]; + end +end + +// Output register +always @* begin + store_output = 1'b0; + + m_axis_tvalid_next = m_axis_tvalid_reg; + + if (m_axis_tready || !m_axis_tvalid) begin + store_output = 1'b1; + m_axis_tvalid_next = mem_read_data_valid_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + m_axis_tvalid_reg <= 1'b0; + end else begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + end + + if (store_output) begin + m_axis_reg <= mem_read_data_reg; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/priority_encoder.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/priority_encoder.v new file mode 100644 index 0000000000000000000000000000000000000000..6d7f31b5ec28e0db6ab77f2179bedd69d547003d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/build/corescore_0/gowin_yosys-yosys/src/verilog-axis_0-r3/rtl/priority_encoder.v @@ -0,0 +1,100 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Priority encoder module + */ +module priority_encoder # +( + parameter WIDTH = 4, + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" +) +( + input wire [WIDTH-1:0] input_unencoded, + output wire output_valid, + output wire [$clog2(WIDTH)-1:0] output_encoded, + output wire [WIDTH-1:0] output_unencoded +); + +// power-of-two width +parameter W1 = 2**$clog2(WIDTH); +parameter W2 = W1/2; + +generate + if (WIDTH == 1) begin + // one input + assign output_valid = input_unencoded; + assign output_encoded = 0; + end else if (WIDTH == 2) begin + // two inputs - just an OR gate + assign output_valid = |input_unencoded; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = input_unencoded[1]; + end else begin + assign output_encoded = ~input_unencoded[0]; + end + end else begin + // more than two inputs - split into two parts and recurse + // also pad input to correct power-of-two width + wire [$clog2(W2)-1:0] out1, out2; + wire valid1, valid2; + priority_encoder #( + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) + ) + priority_encoder_inst1 ( + .input_unencoded(input_unencoded[W2-1:0]), + .output_valid(valid1), + .output_unencoded(), + .output_encoded(out1) + ); + priority_encoder #( + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) + ) + priority_encoder_inst2 ( + .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}), + .output_valid(valid2), + .output_unencoded(), + .output_encoded(out2) + ); + // multiplexer to select part + assign output_valid = valid1 | valid2; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1}; + end else begin + assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2}; + end + end +endgenerate + +// unencoded output +assign output_unencoded = 1 << output_encoded; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/README.md b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/README.md new file mode 100644 index 0000000000000000000000000000000000000000..393c3692fe99184e9fbdf2d98c5af9fa1e251f6f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/README.md @@ -0,0 +1,39 @@ +![CoreScore logo](corescore.png) + +## Background + +CoreScore is an award-giving benchmark for FPGAs and their synthesis/P&R tools. It tests how many [SERV](https://github.com/olofk/serv) cores that can be put into a particular FPGA. + +Some more background about CoreScore can be found in the [SERV introduction video](https://diode.zone/videos/watch/0230a518-e207-4cf6-b5e2-69cc09411013). + +Check out the [CoreScore World Ranking](https://corescore.store/)! + +## Quick start + +1. Install [FuseSoC](https://github.com/olofk/fusesoc) + + pip install fusesoc + +2. Set up a workspace directory and get the FuseSoC base library + + mkdir workspace + cd workspace + fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores + +3. Add CoreScore as a library in your workspace + + fusesoc library add corescore https://github.com/olofk/corescore + +4. Check available corescore targets + + fusesoc core show corescore + +5. Build one of the supported targets (cyc1000 is one of the currently supported cores) + + fusesoc run --target=cyc1000 corescore + +6. If the board is connected it will be automatically programmed. Otherwise connect it and run `fusesoc run --run --target=cyc1000 corescore` to program without rebuilding + +7. Run the corecount utility (Might need to adjust for the correct UART port) + + python3 fusesoc_libraries/corescore/sw/corecount.py /dev/ttyUSB0 diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/axis2wb.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/axis2wb.v new file mode 100644 index 0000000000000000000000000000000000000000..2698154f0e1b6ac8a5d0dfa17ce23501e40d31c2 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/axis2wb.v @@ -0,0 +1,24 @@ +`default_nettype none +module axis2wb + ( + input wire i_clk, + input wire i_rst, + input wire [0:0] i_wb_sel, + input wire i_wb_stb, + output wire [9:0] o_wb_rdt, + output reg o_wb_ack, + input wire [7:0] i_tdata, + input wire i_tlast, + input wire i_tvalid, + output wire o_tready); + + always @(posedge i_clk) begin + o_wb_ack <= i_wb_stb & !o_wb_ack; + if (i_rst) + o_wb_ack <= 1'b0; + end + + assign o_tready = i_wb_sel[0] & o_wb_ack; + assign o_wb_rdt = {i_tvalid, i_tlast, i_tdata}; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/base.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/base.v new file mode 100644 index 0000000000000000000000000000000000000000..ba75ad9dc0c15e734cf479e693d9c6c449bf5ed7 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/base.v @@ -0,0 +1,46 @@ +module base + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + parameter memfile = ""; + parameter memsize = 8192; + + wire [31:0] wb_dat; + wire wb_we; + wire wb_stb; + wire wb_ack; + + wb2axis w2s + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wb_dat (wb_dat[8:0]), + .i_wb_we (wb_we), + .i_wb_stb (wb_stb), + .o_wb_ack (wb_ack), + .o_tdata (o_tdata), + .o_tlast (o_tlast), + .o_tvalid (o_tvalid), + .i_tready (i_tready)); + + serving + #(.memfile (memfile), + .memsize (memsize), + .WITH_CSR (0)) + serving + (.i_clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (1'b0), + + .o_wb_adr (), + .o_wb_dat (wb_dat), + .o_wb_sel (), + .o_wb_we (wb_we), + .o_wb_stb (wb_stb), + .i_wb_rdt (32'd0), + .i_wb_ack (wb_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/cc_gatemate_clock_gen.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/cc_gatemate_clock_gen.v new file mode 100644 index 0000000000000000000000000000000000000000..99398e3644c0c92d06b79ea7aa5b6462a4756d0e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/cc_gatemate_clock_gen.v @@ -0,0 +1,48 @@ +/* verilator lint_off PINMISSING */ +/* verilator lint_off ASCRANGE */ +module clkgen ( + input wire i_clk, + input wire i_rstn, + output wire o_clk_core, + output wire o_rst_core +); + +reg rst_reg1; +reg rst_reg2; + +wire o_clk_pll; +wire usr_pll_lock_1; + +CC_PLL #( + .REF_CLK("10.0"), // reference input in MHz + .OUT_CLK(5'd16), // pll output frequency in MHz + .PERF_MD("ECONOMY"), // LOWPOWER, ECONOMY, SPEED + .LOCK_REQ(1), // 0: disable, 1: enable lock request + .LOW_JITTER(1) // 0: disable, 1: enable low jitter mode +) pll_inst_ila ( + .CLK_REF(i_clk), + .CLK_FEEDBACK(1'b0), + .USR_CLK_REF(1'b0), + .USR_LOCKED_STDY_RST(1'b0), + .USR_PLL_LOCKED_STDY(), + .USR_PLL_LOCKED(usr_pll_lock_1), + .CLK270(), .CLK180(), .CLK90(), .CLK0(o_clk_pll), + .CLK_REF_OUT() +); + +// reset synchronizing +always @(posedge i_clk) begin + if(!usr_pll_lock_1 || !i_rstn) begin + rst_reg1 <= 1'b1; + rst_reg2 <= 1'b1; + end else begin + rst_reg1 <= 1'b0; + rst_reg2 <= rst_reg1; + end +end + +assign o_rst_core = rst_reg2; +assign o_clk_core = o_clk_pll; + + +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/corescore_gatemate.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/corescore_gatemate.v new file mode 100644 index 0000000000000000000000000000000000000000..74d3a414f1305550b18d2ba93001fa220caf5f04 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/corescore_gatemate.v @@ -0,0 +1,38 @@ +module corescore_gatemate + ( + input i_clk, + input i_rstn, + output wire o_uart_tx); + + wire clk; + wire o_rst; + + //Create a 16MHz clock from 10MHz using PLL + clkgen clkgen + (.i_clk (i_clk), + .i_rstn (i_rstn), + .o_clk_core(clk), + .o_rst_core(o_rst)); + + wire [7:0] tdata; + wire tlast; + wire tvalid; + wire tready; + + corescorecore corescorecore + (.i_clk (clk), + .i_rst (o_rst), + .o_tdata (tdata), + .o_tlast (tlast), + .o_tvalid (tvalid), + .i_tready (tready)); + + emitter_uart emitter + (.i_clk (clk), + .i_rst (o_rst), + .i_tdata (tdata), + .i_tvalid (tvalid), + .o_tready (tready), + .o_uart_tx (o_uart_tx)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/corescore_gowin_yosys.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/corescore_gowin_yosys.v new file mode 100644 index 0000000000000000000000000000000000000000..c11e8ad8b39b81ea46821361bedfcfdb10c1ef13 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/corescore_gowin_yosys.v @@ -0,0 +1,39 @@ +(* keep = 1 *) +module corescore_gowin_yosys + ( + input i_clk, + input i_rstn, + output wire o_uart_tx); + + wire clk; + wire o_rst; + + //Create a 16MHz clock from 10MHz using PLL + clkgen clkgen + (.i_clk (i_clk), + .i_rstn (i_rstn), + .o_clk_core(clk), + .o_rst_core(o_rst)); + + wire [7:0] tdata; + wire tlast; + wire tvalid; + wire tready; + + corescorecore corescorecore + (.i_clk (clk), + .i_rst (o_rst), + .o_tdata (tdata), + .o_tlast (tlast), + .o_tvalid (tvalid), + .i_tready (tready)); + + emitter_uart emitter + (.i_clk (clk), + .i_rst (o_rst), + .i_tdata (tdata), + .i_tvalid (tvalid), + .o_tready (tready), + .o_uart_tx (o_uart_tx)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/cpelib.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/cpelib.v new file mode 100644 index 0000000000000000000000000000000000000000..54600aa2d98cb5d6920762fb2fc9808e2a260d01 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/cpelib.v @@ -0,0 +1,130 @@ +/* + * cpelib.v + * + * Gate level description of a CPE using a set of simplified library elements + * for post-implementation simulation with back annotated timings. + * + * Copyright (C) 2024 Cologne Chip AG + * + * Revision history: + * 2024-07-24 - Check that CC_PLL OUT_CLK parameter is not zero. + * 2024-07-12 - Improved simplified CC_PLL simulation model. + * 2024-03-27 - Fixed CPE_TOBF enable polarity. + * 2024-01-31 - Added missing C_D, C_DST and C_DRS specify timing constraints. + * 2023-12-20 - Added CINY2 path for timing simulation. + * 2023-12-20 - Added CC_PLL lock in time and specify block. + * 2023-12-19 - Fixed C_ADDF2 and C_ADDF2x CIN signal declaration. + * 2023-12-19 - Fixed CC_IO_SEL GPIO_EN signal. + * 2023-12-19 - Added CPE_TOBF module. + * 2023-06-19 - Prevent implicit declarations. + * 2023-05-18 - Add FIFO status signals to Block RAM. + * 2023-03-20 - Enable Block RAM initialization. + * 2023-02-21 - Added C_D, C_DST and C_DRS initial values. + * 2023-02-13 - Fixed CADD_{A,S} in C_ADDFx. + * 2022-12-02 - Added CC_IO_SEL module. + * 2022-11-01 - C_D, C_DST, C_DRS revision. + * 2022-08-29 - C_MULT, C_AND and C_OR revision. + * 2022-06-01 - Initial version. + */ + +`timescale 1 ps / 1 ps +module CC_PLL #( + parameter PLL_CFG = "", + parameter REF_CLK = 10.0, // e.g. "10.0" + parameter OUT_CLK = 50.0, // e.g. "50.0" + parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED + parameter LOCK_REQ = 0, + parameter LOW_JITTER = 1, + parameter CI_FILTER_CONST = 2, + parameter CP_FILTER_CONST = 4 +)( + input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, + input USR_LOCKED_STDY_RST, USR_SET_SEL, + output reg USR_PLL_LOCKED_STDY, + output reg USR_PLL_LOCKED, + output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT +); + + initial begin + if (OUT_CLK == 0.0) begin + $display("ERROR: CC_PLL OUT_CLK parameter may not be zero."); + $finish(); + end + end + + // Calculate the delay for the output clock + // Clock generation + reg CLK0_reg, CLK90_reg, CLK180_reg, CLK270_reg; + initial begin + CLK0_reg = 0; + CLK90_reg = 0; + CLK180_reg = 0; + CLK270_reg = 0; + end + + reg baseclk; + localparam real clk_period = 1000000.0 / OUT_CLK; // 15,000 ps (15 ns) + initial begin + baseclk = 0; + forever begin + #(clk_period/4.0 * 1ps) baseclk = ~baseclk; + end + end + + reg [31:0] clkcnt = 0; + always @(baseclk) + begin + if ((clkcnt > 1) && (clkcnt % 2 == 0)) begin + CLK0_reg = ~CLK0_reg; + end + if ((clkcnt > 2) && ((clkcnt-1) % 2 == 0)) begin + CLK90_reg = ~CLK90_reg; + end + if ((clkcnt > 3) && ((clkcnt-2) % 2 == 0)) begin + CLK180_reg = ~CLK180_reg; + end + if ((clkcnt > 4) && ((clkcnt-3) % 2 == 0)) begin + CLK270_reg = ~CLK270_reg; + end + clkcnt = clkcnt + 1; + end + + assign CLK0 = LOCK_REQ ? CLK0_reg & USR_PLL_LOCKED : CLK0_reg; + assign CLK90 = LOCK_REQ ? CLK90_reg & USR_PLL_LOCKED : CLK90_reg; + assign CLK180 = LOCK_REQ ? CLK180_reg & USR_PLL_LOCKED : CLK180_reg; + assign CLK270 = LOCK_REQ ? CLK270_reg & USR_PLL_LOCKED : CLK270_reg; + assign CLK_REF_OUT = CLK_REF; + + // USR_PLL_LOCKED and USR_PLL_LOCKED_STDY generation + integer counter; + initial begin + counter = 0; + USR_PLL_LOCKED = 0; + USR_PLL_LOCKED_STDY = 0; + end + + always @(posedge CLK_REF) begin + if (counter < 57) begin + counter = counter + 1; + end else begin + USR_PLL_LOCKED = 1; + end + end + + always @(posedge CLK_REF or posedge USR_LOCKED_STDY_RST) begin + if (USR_LOCKED_STDY_RST) begin + USR_PLL_LOCKED_STDY <= 0; + end else if (USR_PLL_LOCKED) begin + USR_PLL_LOCKED_STDY <= 1; + end + end + +`ifdef USE_TIMING + specify + (CLK_REF => CLK270) = 0; + (CLK_REF => CLK180) = 0; + (CLK_REF => CLK90) = 0; + (CLK_REF => CLK0) = 0; + endspecify +`endif +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter.v new file mode 100644 index 0000000000000000000000000000000000000000..d4566bf4cbbfc7b9b10ce2f95de613dca1522690 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter.v @@ -0,0 +1,188 @@ +module emitter + (input wire i_clk, + input wire i_rst, + input wire [7:0] i_tdata, + input wire i_tlast, + input wire i_tvalid, + output wire o_tready, + output wire o_uart_tx); + + parameter memfile = ""; + parameter memsize = 256; + parameter sim = 0; + + wire [31:0] wb_ibus_adr; + wire wb_ibus_cyc; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_ack; + + wire [31:0] wb_dbus_adr; + wire [31:0] wb_dbus_dat; + wire [3:0] wb_dbus_sel; + wire wb_dbus_we; + wire wb_dbus_cyc; + wire [31:0] wb_dbus_rdt; + wire wb_dbus_ack; + + wire [31:0] wb_dmem_adr; + wire [31:0] wb_dmem_dat; + wire [3:0] wb_dmem_sel; + wire wb_dmem_we; + wire wb_dmem_cyc; + wire [31:0] wb_dmem_rdt; + wire wb_dmem_ack; + + wire [31:0] wb_mem_adr; + wire [31:0] wb_mem_dat; + wire [3:0] wb_mem_sel; + wire wb_mem_we; + wire wb_mem_cyc; + wire [31:0] wb_mem_rdt; + wire wb_mem_ack; + + wire wb_gpio_dat; + wire wb_gpio_cyc; +// wire wb_gpio_rdt; + + wire [0:0] wb_fifo_sel; + wire wb_fifo_stb; + wire [9:0] wb_fifo_rdt; + wire wb_fifo_ack; + + servant_arbiter arbiter + (.i_wb_cpu_dbus_adr (wb_dmem_adr), + .i_wb_cpu_dbus_dat (wb_dmem_dat), + .i_wb_cpu_dbus_sel (wb_dmem_sel), + .i_wb_cpu_dbus_we (wb_dmem_we ), + .i_wb_cpu_dbus_cyc (wb_dmem_cyc), + .o_wb_cpu_dbus_rdt (wb_dmem_rdt), + .o_wb_cpu_dbus_ack (wb_dmem_ack), + + .i_wb_cpu_ibus_adr (wb_ibus_adr), + .i_wb_cpu_ibus_cyc (wb_ibus_cyc), + .o_wb_cpu_ibus_rdt (wb_ibus_rdt), + .o_wb_cpu_ibus_ack (wb_ibus_ack), + + .o_wb_cpu_adr (wb_mem_adr), + .o_wb_cpu_dat (wb_mem_dat), + .o_wb_cpu_sel (wb_mem_sel), + .o_wb_cpu_we (wb_mem_we ), + .o_wb_cpu_cyc (wb_mem_cyc), + .i_wb_cpu_rdt (wb_mem_rdt), + .i_wb_cpu_ack (wb_mem_ack)); + + emitter_mux #(sim) dmux + ( + .i_clk (i_clk), + .i_rst (i_rst), + .i_wb_cpu_adr (wb_dbus_adr), + .i_wb_cpu_dat (wb_dbus_dat), + .i_wb_cpu_sel (wb_dbus_sel), + .i_wb_cpu_we (wb_dbus_we), + .i_wb_cpu_cyc (wb_dbus_cyc), + .o_wb_cpu_rdt (wb_dbus_rdt), + .o_wb_cpu_ack (wb_dbus_ack), + + .o_wb_mem_adr (wb_dmem_adr), + .o_wb_mem_dat (wb_dmem_dat), + .o_wb_mem_sel (wb_dmem_sel), + .o_wb_mem_we (wb_dmem_we), + .o_wb_mem_cyc (wb_dmem_cyc), + .i_wb_mem_rdt (wb_dmem_rdt), + + .o_wb_gpio_dat (wb_gpio_dat), + .o_wb_gpio_cyc (wb_gpio_cyc), +// .i_wb_gpio_rdt (wb_gpio_rdt), + + .o_wb_timer_dat (), + .o_wb_timer_we (), + .o_wb_timer_cyc (), + .i_wb_timer_rdt (32'd0), + + .o_wb_fifo_sel (wb_fifo_sel), + .o_wb_fifo_stb (wb_fifo_stb), + .i_wb_fifo_rdt (wb_fifo_rdt), + .i_wb_fifo_ack (wb_fifo_ack)); + + servant_ram + #(.memfile (memfile), + .RESET_STRATEGY ("MINI"), + .depth (memsize)) + ram + (// Wishbone interface + .i_wb_clk (i_clk), + .i_wb_rst (i_rst), + .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), + .i_wb_cyc (wb_mem_cyc), + .i_wb_we (wb_mem_we) , + .i_wb_sel (wb_mem_sel), + .i_wb_dat (wb_mem_dat), + .o_wb_rdt (wb_mem_rdt), + .o_wb_ack (wb_mem_ack)); + + servant_gpio gpio + (.i_wb_clk (i_clk), + .i_wb_dat (wb_gpio_dat), + .i_wb_we (1'b1), + .i_wb_cyc (wb_gpio_cyc), + .o_wb_rdt (), + .o_gpio (o_uart_tx)); + + axis2wb s2w + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wb_sel (wb_fifo_sel), + .i_wb_stb (wb_fifo_stb), + .o_wb_rdt (wb_fifo_rdt), + .o_wb_ack (wb_fifo_ack), + .i_tdata (i_tdata), + .i_tlast (i_tlast), + .i_tvalid (i_tvalid), + .o_tready (o_tready)); + + serv_rf_top + #(.RESET_PC (32'h0000_0000), + .WITH_CSR (0)) + cpu + ( + .clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (1'b0), +`ifdef RISCV_FORMAL + .rvfi_valid (), + .rvfi_order (), + .rvfi_insn (), + .rvfi_trap (), + .rvfi_halt (), + .rvfi_intr (), + .rvfi_mode (), + .rvfi_ixl (), + .rvfi_rs1_addr (), + .rvfi_rs2_addr (), + .rvfi_rs1_rdata (), + .rvfi_rs2_rdata (), + .rvfi_rd_addr (), + .rvfi_rd_wdata (), + .rvfi_pc_rdata (), + .rvfi_pc_wdata (), + .rvfi_mem_addr (), + .rvfi_mem_rmask (), + .rvfi_mem_wmask (), + .rvfi_mem_rdata (), + .rvfi_mem_wdata (), +`endif + + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_cyc), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_cyc), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..23c4ffaab76892b918e087c3aaffd7598acadf27 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter_mux.v @@ -0,0 +1,85 @@ +/* + mem = 00 + gpio = 01 + timer = 10 + FIFO = 11 + */ +module emitter_mux + ( + input wire i_clk, + input wire i_rst, + input wire [31:0] i_wb_cpu_adr, + input wire [31:0] i_wb_cpu_dat, + input wire [3:0] i_wb_cpu_sel, + input wire i_wb_cpu_we, + input wire i_wb_cpu_cyc, + output wire [31:0] o_wb_cpu_rdt, + output wire o_wb_cpu_ack, + //RW + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_cyc, + input wire [31:0] i_wb_mem_rdt, + //W + output wire o_wb_gpio_dat, + output wire o_wb_gpio_cyc, + //RW + output wire [31:0] o_wb_timer_dat, + output wire o_wb_timer_we, + output wire o_wb_timer_cyc, + input wire [31:0] i_wb_timer_rdt, + //R + output wire [0:0] o_wb_fifo_sel, + output wire o_wb_fifo_stb, + input wire [9:0] i_wb_fifo_rdt, + input wire i_wb_fifo_ack); + + parameter sim = 0; + + reg ack; + + wire [1:0] s = i_wb_cpu_adr[31:30]; + + assign o_wb_cpu_rdt = !s[1] ? i_wb_mem_rdt : + s[0] ? {22'd0, i_wb_fifo_rdt} : + i_wb_timer_rdt; + assign o_wb_cpu_ack = (s == 2'b11) ? i_wb_fifo_ack : ack; + + always @(posedge i_clk) begin + ack <= 1'b0; + if (i_wb_cpu_cyc & (s != 2'b11) & !ack) + ack <= 1'b1; + if (i_rst) + ack <= 1'b0; + end + + assign o_wb_mem_adr = i_wb_cpu_adr; + assign o_wb_mem_dat = i_wb_cpu_dat; + assign o_wb_mem_sel = i_wb_cpu_sel; + assign o_wb_mem_we = i_wb_cpu_we; + assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00); + + assign o_wb_gpio_dat = i_wb_cpu_dat[0]; + assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01); + + assign o_wb_timer_dat = i_wb_cpu_dat; + assign o_wb_timer_we = i_wb_cpu_we; + assign o_wb_timer_cyc = i_wb_cpu_cyc & (s == 2'b10); + + assign o_wb_fifo_sel = i_wb_cpu_sel[0]; + assign o_wb_fifo_stb = i_wb_cpu_cyc & (s == 2'b11); + + generate + if (sim) begin + wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack; + + always @(posedge i_clk) + if(halt_en) begin + $display("Finito"); + $finish; + end + end + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter_uart.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter_uart.v new file mode 100644 index 0000000000000000000000000000000000000000..87146563eb9490b4a236e25e4bc0b1438d0aa2c0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/emitter_uart.v @@ -0,0 +1,45 @@ +/* + * emitter_uart.v : Simple UA(R)T used as emitter in CoreScore + * + * SPDX-FileCopyrightText: 2023 Olof Kindgren + * SPDX-License-Identifier: Apache-2.0 + */ + +module emitter_uart + #(parameter clk_freq_hz = 16_000_000, + parameter baud_rate = 57600) + (input wire i_clk, + input wire i_rst, + input wire [7:0] i_tdata, + input wire i_tvalid, + output reg o_tready, + output wire o_uart_tx); + + localparam START_VALUE = clk_freq_hz/baud_rate; + + localparam WIDTH = $clog2(START_VALUE); + + reg [WIDTH:0] cnt; + + reg [9:0] data; + + assign o_uart_tx = data[0] | !(|data); + + always @(posedge i_clk) begin + if (cnt[WIDTH] & !(|data)) + o_tready <= 1'b1; + else if (i_tvalid & o_tready) + o_tready <= 1'b0; + + if (o_tready | cnt[WIDTH]) + cnt <= {1'b0,START_VALUE[WIDTH-1:0]}; + else + cnt <= cnt-1; + + if (cnt[WIDTH]) + data <= {1'b0, data[9:1]}; + else if (i_tvalid & o_tready) + data <= {1'b1, i_tdata, 1'b0}; + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/gw2a18_clk_gen.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/gw2a18_clk_gen.v new file mode 100644 index 0000000000000000000000000000000000000000..e62f7470c75aa66230ce0fa0d5e811064e99520a --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/gw2a18_clk_gen.v @@ -0,0 +1,89 @@ +module clkgen ( + input wire i_clk, + input wire i_rstn, + output wire o_clk_core, + output wire o_rst_core +); + +wire pll_lock; + + rPLL #( + //.DEVICE ("GW1NR-9C"), + //.DEVICE ("GW2AR-18C"), + .DEVICE ("GW2AR-18C"), + .FCLKIN ("27"), + .DYN_IDIV_SEL ("false"), + .IDIV_SEL (4), + .DYN_FBDIV_SEL ("false"), + .FBDIV_SEL (2), + .DYN_ODIV_SEL ("false"), + .ODIV_SEL (32), + .PSDA_SEL ("0000"), + .DYN_DA_EN ("true"), + .DUTYDA_SEL ("1000"), + .CLKOUT_FT_DIR (1'b1), + .CLKOUTP_FT_DIR (1'b1), + .CLKOUT_DLY_STEP (0), + .CLKOUTP_DLY_STEP (0), + .CLKFB_SEL ("internal"), + .CLKOUT_BYPASS ("false"), + .CLKOUTP_BYPASS ("false"), + .CLKOUTD_BYPASS ("false"), + .DYN_SDIV_SEL (2), + .CLKOUTD_SRC ("CLKOUT"), + .CLKOUTD3_SRC ("CLKOUT") + ) + u_pll ( + .CLKOUT (o_clk_core), + .LOCK (pll_lock), + .CLKOUTP (), + .CLKOUTD (), + .CLKOUTD3 (), + + .RESET (1'b0), + .RESET_P (1'b0), + .CLKIN (i_clk), + .CLKFB (1'b0), + .FBDSEL ('0), + .IDSEL ('0), + .ODSEL ('0), + .PSDA ('0), + .DUTYDA ('0), + .FDLY ('0) + ); + +//-------------------------------------------------- +// Clock divider: 108MHz -> 54MHz +//-------------------------------------------------- + CLKDIV #( + .DIV_MODE ("2"), + .GSREN ("false") + ) + u_clkdiv ( + .CLKOUT (clk_54), + .HCLKIN (clk_108), + .RESETN (pll_lock), + .CALIB (1'b0) + ); + +//-------------------------------------------------- +// Reset synchronizer +//-------------------------------------------------- + reg srst_n_pipe; + wire final_rst; + assign final_rst = ~i_rstn | ~pll_lock; + reg srst_n; + + always @(posedge final_rst or posedge clk_54) begin + if (final_rst == 1'b1) begin + srst_n_pipe <= 1'b0; + srst_n <= 1'b0; + end + else begin + srst_n_pipe <= 1'b1; + srst_n <= srst_n_pipe; + end + end + + assign o_rst_core = ~srst_n; +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/wb2axis.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/wb2axis.v new file mode 100644 index 0000000000000000000000000000000000000000..10d983e13c230ac1367215aa64b7511b490590db --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/rtl/wb2axis.v @@ -0,0 +1,25 @@ +`default_nettype none +module wb2axis + ( + input wire i_clk, + input wire i_rst, + input wire [8:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_stb, + output reg o_wb_ack, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + always @(posedge i_clk) begin + o_wb_ack <= i_wb_stb & i_tready & !o_wb_ack; + if (i_rst) + o_wb_ack <= 1'b0; + end + + assign o_tvalid = i_wb_stb & i_wb_we & !o_wb_ack; + assign o_tdata = i_wb_dat[7:0]; + assign o_tlast = i_wb_dat[8]; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/corecount.py b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/corecount.py new file mode 100644 index 0000000000000000000000000000000000000000..73b21078d016852d4b6348e34827f2c507cf24da --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/corecount.py @@ -0,0 +1,59 @@ +import curses +import serial +import sys +import msgpack + +COREY = r''' +/---------\ +| Hi! | +|I'm Corey|---------\ +\---------- | + | O" O" | + | _________ | + | \_______/ | + \___________------------\ + |Let's count| + | cores! | + \-----------/ +''' + + +def main(stdscr): + dev = sys.argv[1] if len(sys.argv) > 1 else '/dev/ttyUSB0' + + stdscr = curses.initscr() + curses.curs_set(0) + y = 0 + for l in COREY.split('\n'): + try: + stdscr.addstr(y, 0, l) + except curses.error: + pass + y += 1 + stdscr.box(0, 0) + stdscr.refresh() + win = curses.newwin(curses.LINES//2-2, curses.COLS-2, curses.LINES//2+1, 1) + win.scrollok(True) + win.addstr(1, 10, '') + win.refresh() + + found_cores = [] + with serial.Serial(dev, 57600) as ser: + unpacker = msgpack.Unpacker(raw=False) + while(True): + buf = ser.read() + unpacker.feed(buf) + for o in unpacker: + if type(o) == str: + (y, x) = win.getyx() + win.addstr(curses.LINES//2-3, 6, o[0:-1]) + win.refresh() + n = int(o[5:10]) + if not (n in found_cores): + found_cores.append(n) + stdscr.addstr( + 10, 35, "Found {} cores".format(len(found_cores))) + stdscr.refresh() + + +curses.wrapper(main) diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/corescorecore_gen.py b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/corescorecore_gen.py new file mode 100644 index 0000000000000000000000000000000000000000..48f0049cf0dec3950cb084cb5d0779e4d4ce7600 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/corescorecore_gen.py @@ -0,0 +1,178 @@ +#!/usr/bin/python3 +from fusesoc.capi2.generator import Generator +import os +import shutil +import subprocess + +from verilogwriter import Instance, ModulePort, Parameter, Port, VerilogWriter, Wire + +#HEX_TEMPLATE implements the following program +#/* +#* Read a string and send as packet to emitter +#* +#* +#*/ +##define AXIS_ADDR 0xC0000000 +# +# /* +# a0 = String address +# a1 = Emitter FIFO address +# t0 = Character to write +# */ +# +#.globl _start +#_start: +# nop +# /* Load string address to a0 */ +# la a0, str +# +# /* Load axis address to a1 */ +# li a1, AXIS_ADDR +# +# /* Write MSGPack string header (0b101xxxxx + len) */ +# li t0, 0xa0+23 +# +#next: /* Write to FIFO */ +# sb t0, 0(a1) +# +# /* Read byte from str */ +# lb t0, 0(a0) +# +# /* Load next address */ +# addi a0, a0, 1 +# +# /* Check if this was last byte in packet */ +# bnez t0, next +# +# /* Write packet end to FIFO */ +# ori t0, t0, 0x100 +# sh t0, 0(a1) +# +# li t0, 10000 +#loop: addi t0, t0, -1 +# bnez t0, loop +# j _start +# +#str: +# .string "Core XXXXX says hello\n" + +HEX_TEMPLATE = '''@0000 +13 00 00 00 +17 05 00 00 +13 05 c5 03 +b7 05 00 c0 +93 02 70 0b +23 80 55 00 +83 02 05 00 +13 05 15 00 +e3 9a 02 fe +93 e2 02 10 +23 90 55 00 +b7 22 00 00 +93 82 02 71 +93 82 f2 ff +e3 9e 02 fe +6f f0 5f fc +43 6F 72 65 +20 {} {} {} +{} {} 20 73 +61 79 73 20 +68 65 6C 6C +6F 0A 00 00 +''' + + +class CoreScoreCoreGenerator(Generator): + def run(self): + files = [{'corescorecore.v': {'file_type': 'verilogSource'}}] + count = self.config.get('count') + + for idx in range(count): + name = 'core_{}'.format(idx) + memfile = name+'.hex' + + # Create hex file + with open(memfile, 'w') as f: + _s = '{:05}'.format(idx) + f.write(HEX_TEMPLATE.format(hex(ord(_s[0]))[2:], + hex(ord(_s[1]))[2:], + hex(ord(_s[2]))[2:], + hex(ord(_s[3]))[2:], + hex(ord(_s[4]))[2:])) + files.append({memfile: {'file_type': 'user', 'copyto': memfile}}) + + self.gen_corescorecore(count) + self.add_files(files) + + def gen_corescorecore(self, count): + corescorecore = VerilogWriter('corescorecore') + + corescorecore.add(ModulePort('i_clk', 'input')) + corescorecore.add(ModulePort('i_rst', 'input')) + corescorecore.add(ModulePort('o_tdata', 'output', 8)) + corescorecore.add(ModulePort('o_tlast', 'output')) + corescorecore.add(ModulePort('o_tvalid', 'output')) + corescorecore.add(ModulePort('i_tready', 'input')) + + corescorecore.add(Wire('tdata', count*8)) + corescorecore.add(Wire('tlast', count)) + corescorecore.add(Wire('tvalid', count)) + corescorecore.add(Wire('tready', count)) + + for idx in range(count): + base_ports = [ + Port('i_clk', 'i_clk'), + Port('i_rst', 'i_rst'), + Port('o_tdata', 'tdata[{}:{}]'.format(idx*8+7, idx*8)), + Port('o_tlast', 'tlast[{}]'.format(idx)), + Port('o_tvalid', 'tvalid[{}]'.format(idx)), + Port('i_tready', 'tready[{}]'.format(idx)), + ] + corescorecore.add(Instance('base', 'core_'+str(idx), + [Parameter('memfile', '"core_{}.hex"'.format(idx)), + Parameter('memsize', '256')], + base_ports)) + + arbports = [ + Port('clk', 'i_clk'), + Port('rst', 'i_rst'), + Port("s_axis_tdata".format(idx), "tdata"), + Port("s_axis_tkeep".format(idx), "{}'d0".format(count)), + Port("s_axis_tvalid".format(idx), 'tvalid'), + Port("s_axis_tready".format(idx), 'tready'), + Port("s_axis_tlast".format(idx), 'tlast'), + Port("s_axis_tid".format(idx), "{}'d0".format(count*8)), + Port("s_axis_tdest".format(idx), "{}'d0".format(count*8)), + Port("s_axis_tuser".format(idx), "{}'d0".format(count)), + Port('m_axis_tdata ', 'o_tdata'), + Port('m_axis_tkeep ', ''), + Port('m_axis_tvalid', 'o_tvalid'), + Port('m_axis_tready', 'i_tready'), + Port('m_axis_tlast ', 'o_tlast'), + Port('m_axis_tid ', ''), + Port('m_axis_tdest ', ''), + Port('m_axis_tuser ', ''), + ] + arbparams = [ + Parameter('S_COUNT', count), + Parameter('DATA_WIDTH', 8), + Parameter('KEEP_ENABLE', 0), + Parameter('KEEP_WIDTH', 1), + Parameter('ID_ENABLE', 0), + Parameter('ID_WIDTH', 8), + Parameter('DEST_ENABLE', 0), + Parameter('DEST_WIDTH', 8), + Parameter('USER_ENABLE', 0), + Parameter('USER_WIDTH', 1), + Parameter('ARB_TYPE', '"ROUND_ROBIN"'), + Parameter('LSB_PRIORITY', '"HIGH"'), + ] + + corescorecore.add( + Instance('axis_arb_mux', 'axis_mux', arbparams, arbports)) + corescorecore.write('corescorecore.v') + + +g = CoreScoreCoreGenerator() +g.run() +g.write() diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/makehex.py b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/makehex.py new file mode 100644 index 0000000000000000000000000000000000000000..0f9132d3935e1c4cedc271ebf69c743d68be29f6 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/makehex.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# +# This is free and unencumbered software released into the public domain. +# +# Anyone is free to copy, modify, publish, use, compile, sell, or +# distribute this software, either in source code form or as a compiled +# binary, for any purpose, commercial or non-commercial, and by any +# means. + +from sys import argv + +binfile = argv[1] +nwords = int(argv[2]) + +with open(binfile, "rb") as f: + bindata = f.read() + +assert len(bindata) < 4*nwords +assert len(bindata) % 4 == 0 + +for i in range(nwords): + if i < len(bindata) // 4: + w = bindata[4*i: 4*i+4] + print("%02x%02x%02x%02x" % (w[3], w[2], w[1], w[0])) + else: + print("0") diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/requirements.txt b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/requirements.txt new file mode 100644 index 0000000000000000000000000000000000000000..3aae276bcd9d36403f6ea98de540624ae6b974cf --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/requirements.txt @@ -0,0 +1 @@ +msgpack diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/verilogwriter.py b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/verilogwriter.py new file mode 100644 index 0000000000000000000000000000000000000000..2538bcbbbb4a87c36e90bd30d6906f1cda7c152d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/sw/verilogwriter.py @@ -0,0 +1,117 @@ +class Signal(object): + def __init__(self, name, width=0, low=0, asc=False, vec=0): + self.name = name + self.width = width + self.low = low + self.asc = asc + + def range(self): + if self.width > 0: + l = self.width+self.low-1 + r = self.low + if self.asc: + return '['+str(r)+':'+str(l)+']' + else: + return '['+str(l)+':'+str(r)+']' + return '' + + +class Wire(Signal): + def write(self, width): + return 'wire{range} {name};\n'.format(range=self.range().rjust(width), name=self.name) + + +class Parameter: + def __init__(self, name, value): + self.name = name + self.value = value + + +class Port: + def __init__(self, name, value): + self.name = name + self.value = value + + +class ModulePort(Signal): + def __init__(self, name, dir, width=0, low=0, asc=False): + super(ModulePort, self).__init__(name, width, low, asc) + self.dir = dir + + def write(self, range_width=0): + return '{dir} wire {range} {name}'.format(dir=self.dir.ljust(6), range=self.range().rjust(range_width), name=self.name) + + +class Instance: + def __init__(self, module, name, parameters, ports): + self.module = module + self.name = name + self.parameters = parameters + self.ports = ports + + def write(self): + s = self.module + if self.parameters: + max_len = max([len(p.name) for p in self.parameters]) + s += '\n #(' + s += ',\n '.join(['.' + p.name.ljust(max_len) + + ' (' + str(p.value) + ')' for p in self.parameters]) + s += ')\n' + s += ' ' + self.name + + if self.ports: + s += '\n (' + max_len = max([len(p.name) for p in self.ports]) + s += ',\n '.join(['.' + p.name.ljust(max_len) + + ' (' + str(p.value) + ')' for p in self.ports]) + s += ')' + s += ';\n' + return s + + +class VerilogWriter: + raw = "" + + def __init__(self, name): + self.name = name + self.instances = [] + self.ports = [] + self.wires = [] + + def add(self, obj): + if isinstance(obj, Instance): + self.instances += [obj] + elif isinstance(obj, ModulePort): + self.ports += [obj] + elif isinstance(obj, Wire): + self.wires += [obj] + else: + raise Exception("Invalid type!" + str(obj)) + + def write(self, file=None): + s = ("// THIS FILE IS AUTOGENERATED BY corescorecore_gen\n" + "// ANY MANUAL CHANGES WILL BE LOST\n") + if self.ports: + s += "`default_nettype none\n" + s += "module {name}\n".format(name=self.name) + max_len = max([len(p.range()) for p in self.ports]) + s += ' (' + s += ',\n '.join([p.write(max_len) for p in self.ports]) + s += ')' + s += ';\n\n' + if self.wires: + max_len = max([len(w.range()) for w in self.wires]) + for w in self.wires: + s += w.write(max_len + 1) + s += '\n' + s += self.raw + for i in self.instances: + s += i.write() + s += '\n' + if self.ports: + s += 'endmodule\n' + if file is None: + return s + else: + f = open(file, 'w') + f.write(s) diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/tb/corescore_tb.cpp b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/tb/corescore_tb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e44ba568eb86b50a1382192b8c6d0ec82c60c64e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/tb/corescore_tb.cpp @@ -0,0 +1,118 @@ +#include "verilated.h" +#include "Vtb.h" +#include + + +double sc_time_stamp() { return 0; } + +// This is a 64-bit integer to reduce wrap over issues and +// allow modulus. You can also use a double, if you wish. +/* +ofstream file ("msgpack.bin", ios::out|ios::binary); + +double sc_time_stamp () { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does +} + +void INThandler(int signal) +{ + printf("\nCaught ctrl-c\n"); + done = true; +} + +typedef struct { + uint8_t state; + char ch; + uint32_t baud_t; + vluint64_t last_update; +} uart_context_t; + +void uart_init(uart_context_t *context, uint32_t baud_rate) { + context->baud_t = 1000*1000*1000/baud_rate; + context->state = 0; +} + +void do_uart(uart_context_t *context, bool rx) { + if (context->state == 0) { + if (rx) + context->state++; + } + else if (context->state == 1) { + if (!rx) { + context->last_update = main_time + context->baud_t/2; + context->state++; + } + } + else if(context->state == 2) { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + context->ch = 0; + context->state++; + } + } + else if (context->state < 11) { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + context->ch |= rx << (context->state-3); + context->state++; + } + } + else { + if (main_time > context->last_update) { + context->last_update += context->baud_t; + file.write (&context->ch, 1); + putchar(context->ch); + context->state=1; + } + } +} +*/ + +int main(int argc, char **argv, char **env) +{ + Verilated::debug(0); + const std::unique_ptr contextp{new VerilatedContext}; + + contextp->traceEverOn(true); + contextp->commandArgs(argc, argv); + + VerilatedFstC *m_trace = new VerilatedFstC; + + const std::unique_ptr topp{new Vtb{contextp.get()}}; + + m_trace->set_time_resolution("1ps"); + m_trace->set_time_unit("1ps"); + topp->trace (m_trace, 20); + m_trace->open("wave.fst"); + + +/* + uart_context_t uart_context; + int baud_rate = 0; + const char *arg = Verilated::commandArgsPlusMatch("uart_baudrate="); + if (arg[0]) { + baud_rate = atoi(arg+15); + if (baud_rate) { + uart_init(&uart_context, baud_rate); + } + } */ + + // signal(SIGINT, INThandler); + long long int t0 = 0; + while (!contextp->gotFinish()) { + topp->eval(); + m_trace->dump(contextp->time()); + + if (!topp->eventsPending()) break; + contextp->time(topp->nextTimeSlot()); + t0++; + } + + if (!contextp->gotFinish()) { + VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n");); + } + m_trace->close(); + topp->final(); + return 0; +} diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/tb/tb.sv b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/tb/tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..961724e541b0622ac96b27c4a28c93a8b44214d9 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/corescore/tb/tb.sv @@ -0,0 +1,40 @@ +`timescale 1ps/1ps +module tb #( + parameter int RUN_SIM_US = 50000 +)(); + +//-------------------------------------------------------------- +// Generate clock and run sim for the specified amount of time + localparam HALF_PERIOD_PS = 50_000; // 10MHz + logic clk_10, clk_100; + + logic rst_n; + initial begin + rst_n = 0; + clk_10 = 1; + fork + forever begin : clk_gen + #(HALF_PERIOD_PS * 1ps) clk_10 = ~clk_10; + end + + begin : run_sim + #(RUN_SIM_US * 1us); + $finish(); + end + + begin: reset + #100ns; + rst_n = 1; + end + join + + end + + logic uart_tx; + corescore_gatemate u_dut ( + .i_clk(clk_10), + .i_rstn(rst_n), + .o_uart_tx(uart_tx) + ); + +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/README.md b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/README.md new file mode 100644 index 0000000000000000000000000000000000000000..1a4ff0e8874aa3e7d891a941eec41edb94450501 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/README.md @@ -0,0 +1,47 @@ +FuseSoC standard core library +============================= + +This is the standard core library to be used with [FuseSoC](https://github.com/olofk/fusesoc) + +### Installation + +This library will be automatically cloned to `~/.local/share/fusesoc/fusesoc-cores` +and added to `fusesoc.conf` when you run `fusesoc init`. + +If you have a existing FuseSoC setup and the above does not work for you, +please consider this alternative installation method. Use git to clone +this repository and add it to your `fusesoc.conf`. For example in +`~/.config/fusesoc/fusesoc.conf`: + +``` +[main] +cores_root = + /home/joe/work/fusesoc-cores +cache_root = /home/joe/work/fuse-cache +build_root = /home/joe/work/fuse-builds +``` + +### Contributing + +Cores for FuseSoC should follow the following guidelines. + + - **No Code** Please do not store code in `fusesoc-cores`. Please store + your code in a separate repo or somewhere it can be fetched with the + `url` provider. + - If your core is really small please consider storing in the + [tiny-cores](http://github.com/fusesoc/tiny-cores) repo. + - **Stay Modern** Use the modern sections in your core file like `fileset` + and `parameter`, please no obsolete `verilog` sections. For details on + migrating old cores to the current standard please refer to the + [FuseSoC migration guide](https://github.com/olofk/fusesoc/blob/master/doc/migrations.adoc). + - **Versioning** Each core should be versioned with either + - **Versioned** For cores where the upstream provider provides a release + version, in git using tags is ideal, please use the corresponding + release version. + - **Pseudo-versioned** When an core's upstream provider is out of your + control and does not use versions please use version `0` and point to + a location which is unique for that revision (e.g. the sha for git + repos or revision for svn repos instead of pointing to master, which + might change over time). If you need to refer to a newer version of + the upstream repo, still without a proper version, step the revision + number (`0-r1`, `0-r2`..etc). diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_alu.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_alu.v new file mode 100644 index 0000000000000000000000000000000000000000..b5e1164c5358ca5878f08fed3991759c7a6215f0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_alu.v @@ -0,0 +1,106 @@ +`default_nettype none +module serv_alu + ( + input wire clk, + input wire i_rst, + input wire i_en, + input wire i_cnt0, + input wire i_rs1, + input wire i_rs2, + input wire i_imm, + input wire i_op_b_rs2, + input wire i_buf, + input wire i_init, + input wire i_cnt_done, + input wire i_sub, + input wire [1:0] i_bool_op, + input wire i_cmp_eq, + input wire i_cmp_uns, + output wire o_cmp, + input wire i_shamt_en, + input wire i_sh_right, + input wire i_sh_signed, + output wire o_sh_done, + input wire [3:0] i_rd_sel, + output wire o_rd); + + wire result_add; + wire result_eq; + wire result_lt; + wire result_sh; + + reg result_lt_r; + + reg [4:0] shamt; + reg shamt_msb; + + wire shamt_ser; + wire plus_1; + + wire add_cy; + reg add_cy_r; + + wire b_inv_plus_1; + wire b_inv_plus_1_cy; + reg b_inv_plus_1_cy_r; + + wire op_b = i_op_b_rs2 ? i_rs2 : i_imm; + assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1; + + serv_shift shift + ( + .i_clk (clk), + .i_load (i_init), + .i_shamt (shamt), + .i_shamt_msb (shamt_msb), + .i_signbit (i_sh_signed & i_rs1), + .i_right (i_sh_right), + .o_done (o_sh_done), + .i_d (i_buf), + .o_q (result_sh)); + + wire add_b = i_sub ? b_inv_plus_1 : op_b; + assign {add_cy,result_add} = i_rs1+add_b+add_cy_r; + assign {b_inv_plus_1_cy,b_inv_plus_1} = {1'b0,~op_b}+plus_1+b_inv_plus_1_cy_r; + + reg lt_r; + + reg eq_r; + + wire lt_sign = i_cnt_done & !i_cmp_uns; + + wire eq = (i_rs1 == op_b); + + assign result_eq = eq & eq_r; + assign result_lt = eq ? lt_r : op_b^lt_sign; + + assign plus_1 = i_cnt0; + assign o_cmp = i_cmp_eq ? result_eq : result_lt; + + localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor + wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}]; + + assign o_rd = (i_rd_sel[0] & result_add) | + (i_rd_sel[1] & result_sh) | + (i_rd_sel[2] & result_lt_r & plus_1) | + (i_rd_sel[3] & result_bool); + + + always @(posedge clk) begin + add_cy_r <= i_en & add_cy; + b_inv_plus_1_cy_r <= i_en & b_inv_plus_1_cy; + + lt_r <= result_lt & i_en; + + if (i_en) begin + result_lt_r <= result_lt; + end + eq_r <= result_eq | ~i_en; + + if (i_shamt_en) begin + shamt_msb <= b_inv_plus_1_cy; + shamt <= {shamt_ser,shamt[4:1]}; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_bufreg.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_bufreg.v new file mode 100644 index 0000000000000000000000000000000000000000..e7172a2a1a47d416569802a5c113b19e849caca5 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_bufreg.v @@ -0,0 +1,42 @@ +module serv_bufreg + ( + input wire i_clk, + input wire i_cnt0, + input wire i_cnt1, + input wire i_en, + input wire i_init, + input wire i_loop, + input wire i_rs1, + input wire i_rs1_en, + input wire i_imm, + input wire i_imm_en, + input wire i_clr_lsb, + output reg [1:0] o_lsb, + output wire [31:0] o_dbus_adr, + output wire o_q); + + wire c, q; + reg c_r; + (* ram_style = "distributed" *) reg [31:0] data; + + wire clr_lsb = i_cnt0 & i_clr_lsb; + + assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r; + + always @(posedge i_clk) begin + //Clear carry when not in INIT state + c_r <= c & i_init; + + if (i_en) + data <= {(i_loop & !i_init) ? o_q : q, data[31:1]}; + + if (i_cnt0 & i_init) + o_lsb[0] <= q; + if (i_cnt1 & i_init) + o_lsb[1] <= q; + end + + assign o_q = data[0]; + assign o_dbus_adr = {data[31:2], 2'b00}; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_csr.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_csr.v new file mode 100644 index 0000000000000000000000000000000000000000..897e2728f60784fe39e6819869554b10ee0aec76 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_csr.v @@ -0,0 +1,108 @@ +`default_nettype none +module serv_csr + ( + input wire i_clk, + input wire i_en, + input wire i_cnt0to3, + input wire i_cnt2, + input wire i_cnt3, + input wire i_cnt7, + input wire i_cnt_done, + input wire i_e_op, + input wire i_ebreak, + input wire i_mem_cmd, + input wire i_mem_misalign, + //From mpram + input wire i_rf_csr_out, + //to mpram + output wire o_csr_in, + //Stuff + input wire i_mtip, + output wire o_new_irq, + input wire i_pending_irq, + input wire i_trap_taken, + input wire i_mstatus_en, + input wire i_mie_en, + input wire i_mcause_en, + input wire [1:0] i_csr_source, + input wire i_mret, + input wire i_d, + output wire o_q); + +`include "serv_params.vh" + + reg mstatus; + reg mstatus_mie; + reg mstatus_mpie; + reg mie_mtie; + + reg mcause31; + reg [3:0] mcause3_0; + wire mcause; + + wire csr_in; + wire csr_out; + + reg timer_irq_r; + + assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? i_d : + (i_csr_source == CSR_SOURCE_SET) ? csr_out | i_d : + (i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~i_d : + (i_csr_source == CSR_SOURCE_CSR) ? csr_out : + 1'bx; + + assign csr_out = (i_mstatus_en & i_en & mstatus) | + i_rf_csr_out | + (i_mcause_en & i_en & mcause); + + assign o_q = csr_out; + + wire timer_irq = i_mtip & mstatus_mie & mie_mtie; + + assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0] + i_cnt_done ? mcause31 //[31] + : 1'b0; + + assign o_csr_in = csr_in; + + assign o_new_irq = !timer_irq_r & timer_irq; + + + always @(posedge i_clk) begin + /* + Note: To save resources mstatus_mpie (mstatus bit 7) is not + readable or writable from sw + */ + if (i_mstatus_en & i_cnt3) + mstatus_mie <= csr_in; + + if (i_mie_en & i_cnt7) + mie_mtie <= csr_in; + + mstatus <= i_cnt2 & mstatus_mie; + + timer_irq_r <= timer_irq; + + if (i_mret) begin + mstatus_mie <= mstatus_mpie; + end + + if (i_trap_taken) begin + mstatus_mpie <= mstatus_mie; + mstatus_mie <= 1'b0; + mcause31 <= i_pending_irq; + mcause3_0 <= i_pending_irq ? 4'd7 : + i_e_op ? {!i_ebreak, 3'b011} : + i_mem_misalign ? {2'b01, i_mem_cmd, 1'b0} : + 4'd0; + end + + if (i_mcause_en & i_en) begin + if (i_cnt0to3) + mcause3_0 <= {csr_in, mcause3_0[3:1]}; + if (i_cnt_done) + mcause31 <= csr_in; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_ctrl.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..f5899a58aa0df8db394b05decf6f46ecfd41df11 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_ctrl.v @@ -0,0 +1,87 @@ +`default_nettype none +module serv_ctrl + ( + input wire clk, + input wire i_rst, + //State + input wire i_pc_en, + input wire i_cnt12to31, + input wire i_cnt2, + input wire i_cnt_done, + //Control + input wire i_jump, + input wire i_jal_or_jalr, + input wire i_utype, + input wire i_pc_rel, + input wire i_trap, + //Data + input wire i_imm, + input wire i_buf, + input wire i_csr_pc, + output wire o_rd, + output wire o_bad_pc, + //External + output reg [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire i_ibus_ack); + + parameter RESET_PC = 32'd0; + parameter WITH_CSR = 1; + + reg en_pc_r; + + wire pc_plus_4; + wire pc_plus_4_cy; + reg pc_plus_4_cy_r; + wire pc_plus_offset; + wire pc_plus_offset_cy; + reg pc_plus_offset_cy_r; + wire pc_plus_offset_aligned; + wire plus_4; + + wire pc = o_ibus_adr[0]; + + wire new_pc; + + wire offset_a; + wire offset_b; + + assign plus_4 = i_cnt2; + + assign o_bad_pc = pc_plus_offset_aligned; + + assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r; + + generate + if (WITH_CSR) + assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4; + else + assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4; + endgenerate + assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr); + + assign offset_a = i_pc_rel & pc; + assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf; + assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r; + + assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r; + + assign o_ibus_cyc = en_pc_r & !i_pc_en; + + always @(posedge clk) begin + pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; + pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; + + if (i_pc_en) begin + en_pc_r <= 1'b1; + o_ibus_adr <= {new_pc, o_ibus_adr[31:1]}; + end else if (o_ibus_cyc & i_ibus_ack) + en_pc_r <= 1'b0; + + if (i_rst) begin + en_pc_r <= 1'b1; + o_ibus_adr <= RESET_PC; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_decode.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_decode.v new file mode 100644 index 0000000000000000000000000000000000000000..d66a1e046f47cafac6113e7d9c138c31fa82253c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_decode.v @@ -0,0 +1,239 @@ +`default_nettype none +module serv_decode + ( + input wire clk, + //Input + input wire i_cnt_en, + input wire i_cnt_done, + input wire [31:2] i_wb_rdt, + input wire i_wb_en, + input wire i_alu_cmp, + //To state + output wire o_take_branch, + output wire o_e_op, + output wire o_ebreak, + output wire o_branch_op, + output wire o_mem_op, + output wire o_shift_op, + output wire o_slt_op, + output wire o_rd_op, + //To bufreg + output wire o_bufreg_loop, + output wire o_bufreg_rs1_en, + output wire o_bufreg_imm_en, + output wire o_bufreg_clr_lsb, + //To ctrl + output wire o_ctrl_jal_or_jalr, + output wire o_ctrl_utype, + output wire o_ctrl_pc_rel, + output wire o_ctrl_mret, + //To alu + output wire o_alu_sub, + output wire [1:0] o_alu_bool_op, + output wire o_alu_cmp_eq, + output wire o_alu_cmp_uns, + output wire o_alu_sh_signed, + output wire o_alu_sh_right, + output wire [3:0] o_alu_rd_sel, + //To RF + output reg [4:0] o_rf_rd_addr, + output reg [4:0] o_rf_rs1_addr, + output reg [4:0] o_rf_rs2_addr, + //To mem IF + output wire o_mem_signed, + output wire o_mem_word, + output wire o_mem_half, + output wire o_mem_cmd, + //To CSR + output wire o_csr_en, + output wire [1:0] o_csr_addr, + output wire o_csr_mstatus_en, + output wire o_csr_mie_en, + output wire o_csr_mcause_en, + output wire [1:0] o_csr_source, + output wire o_csr_d_sel, + output wire o_csr_imm, + //To top + output wire o_imm, + output wire o_op_b_source, + output wire o_rd_csr_en, + output wire o_rd_alu_en); + +`include "serv_params.vh" + + reg [4:0] opcode; + reg [2:0] funct3; + reg op20; + reg op21; + reg op22; + reg op26; + + reg imm30; + + wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]); + + assign o_mem_op = !opcode[4] & !opcode[2] & !opcode[0]; + assign o_shift_op = op_or_opimm & (funct3[1:0] == 2'b01); + assign o_slt_op = op_or_opimm & (funct3[2:1] == 2'b01); + assign o_branch_op = opcode[4] & !opcode[2]; + + //Matches system opcodes except CSR accesses (funct3 == 0) + //No idea anymore why the !op21 condition is needed here + assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3); + + assign o_ebreak = op20; + + //jal,branch = imm + //jalr = rs1+imm + //mem = rs1+imm + //shift = rs1 + assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]); + assign o_bufreg_imm_en = !opcode[2]; + + //Loop bufreg contents for shift operations + assign o_bufreg_loop = op_or_opimm; + + //Clear LSB of immediate for BRANCH and JAL ops + //True for BRANCH and JAL + //False for JALR/LOAD/STORE/OP/OPIMM? + assign o_bufreg_clr_lsb = opcode[4] & ((opcode[1:0] == 2'b00) | (opcode[1:0] == 2'b11)); + + //Take branch for jump or branch instructions (opcode == 1x0xx) if + //a) It's an unconditional branch (opcode[0] == 1) + //b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true + //c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false + //Only valid during the last cycle of INIT, when the branch condition has + //been calculated. + assign o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^funct3[0])); + + assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0]; + assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0]; + + //True for jal, b* auipc + //False for jalr, lui + assign o_ctrl_pc_rel = (opcode[2:0] == 3'b000) | + (opcode[1:0] == 2'b11) | + (opcode[4:3] == 2'b00); + + assign o_ctrl_mret = (opcode[4] & opcode[2] & op21 & !(|funct3)); + + //Write to RD + //True for OP-IMM, AUIPC, OP, LUI, SYSTEM, JALR, JAL, LOAD + //False for STORE, BRANCH, MISC-MEM + assign o_rd_op = (opcode[2] | + (!opcode[2] & opcode[4] & opcode[0]) | + (!opcode[2] & !opcode[3] & !opcode[0])) & (|o_rf_rd_addr); + + assign o_alu_sub = opcode[3] & imm30/*alu_sub_r*/; + + /* + 300 0_000 mstatus RWSC + 304 0_100 mie SCWi + 305 0_101 mtvec RW + 340 1_000 mscratch + 341 1_001 mepc RW + 342 1_010 mcause R + 343 1_011 mtval + 344 1_100 mip CWi + */ + + //true for mtvec,mscratch,mepc and mtval + //false for mstatus, mie, mcause, mip + wire csr_valid = op20 | (op26 & !op22 & !op21); + + //Matches system ops except eceall/ebreak + wire csr_op = opcode[4] & opcode[2] & (|funct3); + assign o_rd_csr_en = csr_op; + + assign o_csr_en = csr_op & csr_valid; + assign o_csr_mstatus_en = csr_op & !op26 & !op22; + assign o_csr_mie_en = csr_op & !op26 & op22 & !op20; + assign o_csr_mcause_en = csr_op & op21 & !op20; + + assign o_csr_source = funct3[1:0]; + assign o_csr_d_sel = funct3[2]; + assign o_csr_imm = o_rf_rs1_addr[0]; + + assign o_csr_addr = (op26 & !op20) ? CSR_MSCRATCH : + (op26 & !op21) ? CSR_MEPC : + (op26) ? CSR_MTVAL : + CSR_MTVEC; + + assign o_alu_cmp_eq = funct3[2:1] == 2'b00; + + assign o_alu_cmp_uns = (funct3[0] & funct3[1]) | (funct3[1] & funct3[2]); + assign o_alu_sh_signed = imm30; + assign o_alu_sh_right = funct3[2]; + + assign o_mem_cmd = opcode[3]; + assign o_mem_signed = ~funct3[2]; + assign o_mem_word = funct3[1]; + assign o_mem_half = funct3[0]; + + assign o_alu_bool_op = funct3[1:0]; + + reg signbit; + + reg [8:0] imm19_12_20; + reg imm7; + reg [5:0] imm30_25; + reg [4:0] imm24_20; + reg [4:0] imm11_7; + + wire [1:0] m2; + //True for OP-IMM, LOAD, STORE, JALR + //False for LUI, AUIPC, JAL + assign m2[0] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00); + assign m2[1] = opcode[4] & !opcode[0]; + wire m3 = opcode[4]; + + assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub + assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift + assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT* + assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool + always @(posedge clk) begin + if (i_wb_en) begin + o_rf_rd_addr <= i_wb_rdt[11:7]; + o_rf_rs1_addr <= i_wb_rdt[19:15]; + o_rf_rs2_addr <= i_wb_rdt[24:20]; + funct3 <= i_wb_rdt[14:12]; + imm30 <= i_wb_rdt[30]; + opcode <= i_wb_rdt[6:2]; + op20 <= i_wb_rdt[20]; + op21 <= i_wb_rdt[21]; + op22 <= i_wb_rdt[22]; + op26 <= i_wb_rdt[26]; + + //Immediate decoder + signbit <= i_wb_rdt[31]; + imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]}; + imm7 <= i_wb_rdt[7]; + imm30_25 <= i_wb_rdt[30:25]; + imm24_20 <= i_wb_rdt[24:20]; + imm11_7 <= i_wb_rdt[11:7]; + end + if (i_cnt_en) begin + imm19_12_20 <= {m3 ? signbit : imm24_20[0], imm19_12_20[8:1]}; + imm7 <= signbit; + imm30_25 <= {m2[1] ? imm7 : m2[0] ? signbit : imm19_12_20[0], imm30_25[5:1]}; + imm24_20 <= {imm30_25[0], imm24_20[4:1]}; + imm11_7 <= {imm30_25[0], imm11_7[4:1]}; + if (csr_op & o_csr_d_sel) + o_rf_rs1_addr <= {1'b0,o_rf_rs1_addr[4:1]}; + end + end + + //True for S (STORE) or B (BRANCH) type instructions + //False for J type instructions + wire m1 = opcode[3:0] == 4'b1000; + + assign o_imm = i_cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]; + + //0 (OP_B_SOURCE_IMM) when OPIMM + //1 (OP_B_SOURCE_RS2) when BRANCH or OP + assign o_op_b_source = opcode[3]; + + assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4]; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_mem_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_mem_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b9ea5cb50b5b09c2119fad52b413e2dc880afdea --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_mem_if.v @@ -0,0 +1,68 @@ +`default_nettype none +module serv_mem_if + #(parameter WITH_CSR = 1) + ( + input wire i_clk, + input wire i_en, + input wire i_mem_op, + input wire i_signed, + input wire i_word, + input wire i_half, + input wire [1:0] i_bytecnt, + input wire i_rs2, + output wire o_rd, + input wire [1:0] i_lsb, + output wire o_misalign, + //External interface + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + reg signbit; + + wire [2:0] tmp = {1'b0,i_bytecnt}+{1'b0,i_lsb}; + + reg [31:0] dat; + + wire dat_en = i_en & !tmp[2]; + + wire dat_cur = + ((i_lsb == 2'd3) & dat[24]) | + ((i_lsb == 2'd2) & dat[16]) | + ((i_lsb == 2'd1) & dat[8]) | + ((i_lsb == 2'd0) & dat[0]); + + wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]); + + assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed); + + assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]); + assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word; + assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]); + assign o_wb_sel[0] = (i_lsb == 2'b00); + + assign o_wb_dat = dat; + + always @(posedge i_clk) begin + if (dat_en) + dat <= {i_rs2, dat[31:1]}; + + if (i_wb_ack) + dat <= i_wb_rdt; + + if (dat_valid) + signbit <= dat_cur; + end + generate + if (WITH_CSR) begin + reg misalign; + always @(posedge i_clk) + misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word); + assign o_misalign = misalign & i_mem_op; + end else begin + assign o_misalign = 1'b0; + end + endgenerate + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_params.vh b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_params.vh new file mode 100644 index 0000000000000000000000000000000000000000..0cf79d96ed485f0846d52efac5338c6a7d9d6552 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_params.vh @@ -0,0 +1,11 @@ +localparam [1:0] + CSR_SOURCE_CSR = 2'b00, + CSR_SOURCE_EXT = 2'b01, + CSR_SOURCE_SET = 2'b10, + CSR_SOURCE_CLR = 2'b11; + +localparam [1:0] + CSR_MSCRATCH = 2'b00, + CSR_MTVEC = 2'b01, + CSR_MEPC = 2'b10, + CSR_MTVAL = 2'b11; diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b26e75f1dba95334cfbf1eaa467facdc6833cb42 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_if.v @@ -0,0 +1,122 @@ +`default_nettype none +module serv_rf_if + #(parameter WITH_CSR = 1) + (//RF Interface + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + //Trap interface + input wire i_trap, + input wire i_mret, + input wire i_mepc, + input wire i_mem_misalign, + input wire i_bufreg_q, + input wire i_bad_pc, + output wire o_csr_pc, + //CSR interface + input wire i_csr_en, + input wire [1:0] i_csr_addr, + input wire i_csr, + output wire o_csr, + //RD write port + input wire i_rd_wen, + input wire [4:0] i_rd_waddr, + input wire i_ctrl_rd, + input wire i_alu_rd, + input wire i_rd_alu_en, + input wire i_csr_rd, + input wire i_rd_csr_en, + input wire i_mem_rd, + + //RS1 read port + input wire [4:0] i_rs1_raddr, + output wire o_rs1, + //RS2 read port + input wire [4:0] i_rs2_raddr, + output wire o_rs2); + + +`include "serv_params.vh" + + /* + ********** Write side *********** + */ + + generate + if (WITH_CSR) begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_csr_rd & i_rd_csr_en) | + (i_mem_rd); + + wire mtval = i_mem_misalign ? i_bufreg_q : i_bad_pc; + + assign o_wdata0 = i_trap ? mtval : rd; + assign o_wdata1 = i_trap ? i_mepc : i_csr; + + //port 0 rd mtval + //port 1 csr mepc + //mepc 100010 + //mtval 100011 + //csr 1000xx + //rd 0xxxxx + assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr}; + assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr}; + + assign o_wen0 = i_trap | i_rd_wen; + assign o_wen1 = i_trap | i_csr_en; + + /* + ********** Read side *********** + */ + + //0 : RS1 + //1 : RS2 / CSR + + + assign o_rreg0 = {1'b0, i_rs1_raddr}; + assign o_rreg1 = + i_trap ? {4'b1000, CSR_MTVEC} : + i_mret ? {4'b1000, CSR_MEPC} : + i_csr_en ? {4'b1000, i_csr_addr} : + {1'b0,i_rs2_raddr}; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + assign o_csr = i_rdata1 & i_csr_en; + assign o_csr_pc = i_rdata1; + + end else begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_mem_rd); + + assign o_wdata0 = rd; + assign o_wdata1 = 1'b0; + + assign o_wreg0 = i_rd_waddr; + assign o_wreg1 = 5'd0; + + assign o_wen0 =i_rd_wen; + assign o_wen1 = 1'b0; + + /* + ********** Read side *********** + */ + + assign o_rreg0 = i_rs1_raddr; + assign o_rreg1 = i_rs2_raddr; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + end // else: !if(WITH_CSR) + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..9bbc503d88e5f71471fc58603c0f87c1b127f092 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_ram.v @@ -0,0 +1,26 @@ +module serv_rf_ram + #(parameter width=0, + parameter csr_regs=4, + parameter depth=32*(32+csr_regs)/width) + (input wire i_clk, + input wire [$clog2(depth)-1:0] i_waddr, + input wire [width-1:0] i_wdata, + input wire i_wen, + input wire [$clog2(depth)-1:0] i_raddr, + output reg [width-1:0] o_rdata); + + reg [width-1:0] memory [0:depth-1]; + + always @(posedge i_clk) begin + if (i_wen) + memory[i_waddr] <= i_wdata; + o_rdata <= memory[i_raddr]; + end + +`ifdef SERV_CLEAR_RAM + integer i; + initial + for (i=0;i 2) + always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]}; + else + always @(posedge i_clk) wdata0_r <= i_wdata0; + endgenerate + + always @(posedge i_clk) begin + wen0_r <= i_wen0; + wen1_r <= i_wen1; + wreq_r <= i_wreq | rgnt; + + wdata1_r <= {i_wdata1,wdata1_r[width-1:1]}; + + if (wgo) + wcnt <= wcnt+5'd1; + + if (wreq_r) begin + wgo <= 1'b1; + end + + if (wcnt == 5'b11111) + wgo <= 1'b0; + + if (i_rst) begin + wcnt <= 5'd0; + end + end + + /* + ********** Read side *********** + */ + + reg [4:0] rcnt; + + wire rtrig0; + reg rtrig1; + + wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0; + generate if (width == 32) + assign o_raddr = rreg; + else + assign o_raddr = {rreg, rcnt[4:l2w]}; + endgenerate + + reg [width-1:0] rdata0; + reg [width-2:0] rdata1; + + assign o_rdata0 = rdata0[0]; + assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0]; + + assign rtrig0 = (rcnt[l2w-1:0] == 1); + + reg rreq_r; + + generate if (width>2) + always @(posedge i_clk) begin + rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize? + if (rtrig1) + rdata1[width-2:0] <= i_rdata[width-1:1]; + end + else + always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1]; + endgenerate + + always @(posedge i_clk) begin + rtrig1 <= rtrig0; + rcnt <= rcnt+5'd1; + if (i_rreq) + rcnt <= 5'd0; + + rreq_r <= i_rreq; + rgnt <= rreq_r; + + rdata0 <= {1'b0,rdata0[width-1:1]}; + if (rtrig0) + rdata0 <= i_rdata; + + if (i_rst) begin + rgnt <= 1'b0; + rreq_r <= 1'b0; + end + end + + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_top.v new file mode 100644 index 0000000000000000000000000000000000000000..ef0ae413261884b55b6fefb4cf18ed5e35a4905b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_rf_top.v @@ -0,0 +1,164 @@ +`default_nettype none + +module serv_rf_top + #(parameter RESET_PC = 32'd0, + parameter WITH_CSR = 1, + parameter RF_WIDTH = 2, + parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH)) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output wire rvfi_valid, + output wire [63:0] rvfi_order, + output wire [31:0] rvfi_insn, + output wire rvfi_trap, + output wire rvfi_halt, + output wire rvfi_intr, + output wire [1:0] rvfi_mode, + output wire [1:0] rvfi_ixl, + output wire [4:0] rvfi_rs1_addr, + output wire [4:0] rvfi_rs2_addr, + output wire [31:0] rvfi_rs1_rdata, + output wire [31:0] rvfi_rs2_rdata, + output wire [4:0] rvfi_rd_addr, + output wire [31:0] rvfi_rd_wdata, + output wire [31:0] rvfi_pc_rdata, + output wire [31:0] rvfi_pc_wdata, + output wire [31:0] rvfi_mem_addr, + output wire [3:0] rvfi_mem_rmask, + output wire [3:0] rvfi_mem_wmask, + output wire [31:0] rvfi_mem_rdata, + output wire [31:0] rvfi_mem_wdata, +`endif + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + localparam CSR_REGS = WITH_CSR*4; + + wire rf_wreq; + wire rf_rreq; + wire [4+WITH_CSR:0] wreg0; + wire [4+WITH_CSR:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [4+WITH_CSR:0] rreg0; + wire [4+WITH_CSR:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + wire [RF_L2D-1:0] waddr; + wire [RF_WIDTH-1:0] wdata; + wire wen; + wire [RF_L2D-1:0] raddr; + wire [RF_WIDTH-1:0] rdata; + + serv_rf_ram_if + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram_if + (.i_clk (clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_rf_ram + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram + (.i_clk (clk), + .i_waddr (waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (raddr), + .o_rdata (rdata)); + + serv_top + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_mode (rvfi_mode ), + .rvfi_ixl (rvfi_ixl ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata (rvfi_rs1_rdata), + .rvfi_rs2_rdata (rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask (rvfi_mem_rmask), + .rvfi_mem_wmask (rvfi_mem_wmask), + .rvfi_mem_rdata (rvfi_mem_rdata), + .rvfi_mem_wdata (rvfi_mem_wdata), +`endif + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_rdt (i_ibus_rdt), + .i_ibus_ack (i_ibus_ack), + + .o_dbus_adr (o_dbus_adr), + .o_dbus_dat (o_dbus_dat), + .o_dbus_sel (o_dbus_sel), + .o_dbus_we (o_dbus_we), + .o_dbus_cyc (o_dbus_cyc), + .i_dbus_rdt (i_dbus_rdt), + .i_dbus_ack (i_dbus_ack)); + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_shift.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_shift.v new file mode 100644 index 0000000000000000000000000000000000000000..70a80db813e0564f80df71c676ba266cf6055d90 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_shift.v @@ -0,0 +1,30 @@ +`default_nettype none +module serv_shift + ( + input wire i_clk, + input wire i_load, + input wire [4:0] i_shamt, + input wire i_shamt_msb, + input wire i_signbit, + input wire i_right, + output wire o_done, + input wire i_d, + output wire o_q); + + reg signbit; + reg [5:0] cnt; + reg wrapped; + + always @(posedge i_clk) begin + cnt <= cnt + 6'd1; + if (i_load) begin + cnt <= 6'd0; + signbit <= i_signbit & i_right; + end + wrapped <= cnt[5] | (i_shamt_msb & !i_right); + end + + assign o_done = (cnt[4:0] == i_shamt); + assign o_q = (i_right^wrapped) ? i_d : signbit; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_state.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_state.v new file mode 100644 index 0000000000000000000000000000000000000000..b919264f8899a6a4b9c93d9ad6bb43c149f6faa6 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_state.v @@ -0,0 +1,153 @@ +module serv_state + ( + input wire i_clk, + input wire i_rst, + input wire i_new_irq, + output wire o_trap_taken, + output reg o_pending_irq, + input wire i_dbus_ack, + input wire i_ibus_ack, + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire o_rf_rd_en, + input wire i_take_branch, + input wire i_branch_op, + input wire i_mem_op, + input wire i_shift_op, + input wire i_slt_op, + input wire i_e_op, + input wire i_rd_op, + output reg o_init, + output reg o_cnt_en, + output wire o_cnt0, + output wire o_cnt0to3, + output wire o_cnt12to31, + output wire o_cnt1, + output wire o_cnt2, + output wire o_cnt3, + output wire o_cnt7, + output wire o_ctrl_pc_en, + output reg o_ctrl_jump, + output wire o_ctrl_trap, + input wire i_ctrl_misalign, + output wire o_alu_shamt_en, + input wire i_alu_sh_done, + output wire o_dbus_cyc, + output wire [1:0] o_mem_bytecnt, + input wire i_mem_misalign, + output reg o_cnt_done, + output wire o_bufreg_hold); + + parameter WITH_CSR = 1; + + wire cnt4; + + reg stage_two_req; + + reg [4:2] o_cnt; + reg [3:0] o_cnt_r; + + //Update PC in RUN or TRAP states + assign o_ctrl_pc_en = o_cnt_en & !o_init; + + + assign o_mem_bytecnt = o_cnt[4:3]; + + assign o_cnt0to3 = (o_cnt[4:2] == 3'd0); + assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11)); + assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0]; + assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1]; + assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2]; + assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3]; + assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0]; + assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3]; + + assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init; + + + //slt*, branch/jump, shift, load/store + wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op; + + reg stage_two_pending; + + assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign; + + wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign); + + //Prepare RF for reads when a new instruction is fetched + // or when stage one caused an exception (rreq implies a write request too) + assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending); + + //Prepare RF for writes when everything is ready to enter stage two + assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending; + + assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init; + + //Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting + assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op); + + always @(posedge i_clk) begin + if (o_cnt_done) + o_ctrl_jump <= o_init & i_take_branch; + + if (o_cnt_en) + stage_two_pending <= o_init; + + o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2]; + + //Need a strobe for the first cycle in the IDLE state after INIT + stage_two_req <= o_cnt_done & o_init; + + if (i_rf_ready & !stage_two_pending) + o_init <= two_stage_op & !o_pending_irq; + + if (o_cnt_done) + o_init <= 1'b0; + + if (i_rf_ready) + o_cnt_en <= 1'b1; + + if (o_cnt_done) + o_cnt_en <= 1'b0; + + o_cnt <= o_cnt + {2'd0,o_cnt_r[3]}; + if (o_cnt_en) + o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]}; + + if (i_rst) begin + o_cnt <= 3'd0; + stage_two_pending <= 1'b0; + o_ctrl_jump <= 1'b0; + o_cnt_r <= 4'b0001; + end + end + + generate + if (WITH_CSR) begin + reg irq_sync; + reg misalign_trap_sync; + + assign o_ctrl_trap = i_e_op | o_pending_irq | misalign_trap_sync; + assign o_trap_taken = i_ibus_ack & o_ctrl_trap; + + always @(posedge i_clk) begin + if (i_ibus_ack) + irq_sync <= 1'b0; + if (i_new_irq) + irq_sync <= 1'b1; + + if (i_ibus_ack) + o_pending_irq <= irq_sync; + + if (stage_two_req) + misalign_trap_sync <= trap_pending; + if (i_ibus_ack) + misalign_trap_sync <= 1'b0; + end // always @ (posedge i_clk) + end else begin + always @(*) + o_pending_irq = 1'b0; + end + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_top.v new file mode 100644 index 0000000000000000000000000000000000000000..65b59b05bc9f9da4d8f99551ebb5fee73f9b5f26 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serv_1.0.2/rtl/serv_top.v @@ -0,0 +1,495 @@ +`default_nettype none + +module serv_top + #(parameter WITH_CSR = 1, + parameter RESET_PC = 32'd0) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output reg rvfi_valid = 1'b0, + output reg [63:0] rvfi_order = 64'd0, + output reg [31:0] rvfi_insn = 32'd0, + output reg rvfi_trap = 1'b0, + output reg rvfi_halt = 1'b0, + output reg rvfi_intr = 1'b0, + output reg [1:0] rvfi_mode = 2'b11, + output reg [1:0] rvfi_ixl = 2'b01, + output reg [4:0] rvfi_rs1_addr, + output reg [4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [3:0] rvfi_mem_rmask, + output reg [3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, +`endif + //RF Interface + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + wire [4:0] rd_addr; + wire [4:0] rs1_addr; + wire [4:0] rs2_addr; + + wire take_branch; + wire e_op; + wire ebreak; + wire branch_op; + wire mem_op; + wire shift_op; + wire slt_op; + wire rd_op; + + wire rd_alu_en; + wire rd_csr_en; + wire ctrl_rd; + wire alu_rd; + wire mem_rd; + wire csr_rd; + + wire ctrl_pc_en; + wire jump; + wire jal_or_jalr; + wire utype; + wire mret; + wire imm; + wire trap; + wire pc_rel; + + wire init; + wire cnt_en; + wire cnt0to3; + wire cnt12to31; + wire cnt0; + wire cnt1; + wire cnt2; + wire cnt3; + wire cnt7; + + wire cnt_done; + + wire bufreg_hold; + wire bufreg_rs1_en; + wire bufreg_imm_en; + wire bufreg_loop; + wire bufreg_q; + + wire alu_sub; + wire [1:0] alu_bool_op; + wire alu_cmp_eq; + wire alu_cmp_uns; + wire alu_cmp; + wire alu_shamt_en; + wire alu_sh_signed; + wire alu_sh_right; + wire alu_sh_done; + wire [3:0] alu_rd_sel; + + wire rs1; + wire rs2; + wire rd_en; + + wire op_b_source; + wire op_b; + + wire mem_signed; + wire mem_word; + wire mem_half; + wire [1:0] mem_bytecnt; + + wire mem_misalign; + + wire bad_pc; + + wire csr_mstatus_en; + wire csr_mie_en; + wire csr_mcause_en; + wire [1:0] csr_source; + wire csr_imm; + wire csr_d_sel; + wire csr_en; + wire [1:0] csr_addr; + wire csr_pc; + + + wire new_irq; + wire trap_taken; + wire pending_irq; + + wire [1:0] lsb; + + serv_state + #(.WITH_CSR (WITH_CSR)) + state + ( + .i_clk (clk), + .i_rst (i_rst), + .i_new_irq (new_irq), + .o_trap_taken (trap_taken), + .o_pending_irq (pending_irq), + .i_dbus_ack (i_dbus_ack), + .i_ibus_ack (i_ibus_ack), + .o_rf_rreq (o_rf_rreq), + .o_rf_wreq (o_rf_wreq), + .i_rf_ready (i_rf_ready), + .o_rf_rd_en (rd_en), + .i_take_branch (take_branch), + .i_branch_op (branch_op), + .i_mem_op (mem_op), + .i_shift_op (shift_op), + .i_slt_op (slt_op), + .i_e_op (e_op), + .i_rd_op (rd_op), + .o_init (init), + .o_cnt_en (cnt_en), + .o_cnt0to3 (cnt0to3), + .o_cnt12to31 (cnt12to31), + .o_cnt0 (cnt0), + .o_cnt1 (cnt1), + .o_cnt2 (cnt2), + .o_cnt3 (cnt3), + .o_cnt7 (cnt7), + .o_cnt_done (cnt_done), + .o_bufreg_hold (bufreg_hold), + .o_ctrl_pc_en (ctrl_pc_en), + .o_ctrl_jump (jump), + .o_ctrl_trap (trap), + .i_ctrl_misalign(lsb[1]), + .o_alu_shamt_en (alu_shamt_en), + .i_alu_sh_done (alu_sh_done), + .o_dbus_cyc (o_dbus_cyc), + .o_mem_bytecnt (mem_bytecnt), + .i_mem_misalign (mem_misalign)); + + wire bufreg_clr_lsb; + + serv_decode decode + ( + .clk (clk), + //Input + .i_cnt_en (cnt_en), + .i_cnt_done (cnt_done), + .i_wb_rdt (i_ibus_rdt[31:2]), + .i_wb_en (o_ibus_cyc & i_ibus_ack), + .i_alu_cmp (alu_cmp), + //To state + .o_take_branch (take_branch), + .o_e_op (e_op), + .o_ebreak (ebreak), + .o_branch_op (branch_op), + .o_mem_op (mem_op), + .o_shift_op (shift_op), + .o_slt_op (slt_op), + .o_rd_op (rd_op), + //To bufreg + .o_bufreg_loop (bufreg_loop), + .o_bufreg_rs1_en (bufreg_rs1_en), + .o_bufreg_imm_en (bufreg_imm_en), + .o_bufreg_clr_lsb (bufreg_clr_lsb), + //To ctrl + .o_ctrl_jal_or_jalr (jal_or_jalr), + .o_ctrl_utype (utype), + .o_ctrl_pc_rel (pc_rel), + .o_ctrl_mret (mret), + //To alu + .o_op_b_source (op_b_source), + .o_alu_sub (alu_sub), + .o_alu_bool_op (alu_bool_op), + .o_alu_cmp_eq (alu_cmp_eq), + .o_alu_cmp_uns (alu_cmp_uns), + .o_alu_sh_signed (alu_sh_signed), + .o_alu_sh_right (alu_sh_right), + .o_alu_rd_sel (alu_rd_sel), + //To RF + .o_rf_rd_addr (rd_addr), + .o_rf_rs1_addr (rs1_addr), + .o_rf_rs2_addr (rs2_addr), + //To mem IF + .o_mem_cmd (o_dbus_we), + .o_mem_signed (mem_signed), + .o_mem_word (mem_word), + .o_mem_half (mem_half), + //To CSR + .o_csr_en (csr_en), + .o_csr_addr (csr_addr), + .o_csr_mstatus_en (csr_mstatus_en), + .o_csr_mie_en (csr_mie_en), + .o_csr_mcause_en (csr_mcause_en), + .o_csr_source (csr_source), + .o_csr_d_sel (csr_d_sel), + .o_csr_imm (csr_imm), + //To top + .o_imm (imm), + .o_rd_csr_en (rd_csr_en), + .o_rd_alu_en (rd_alu_en)); + + serv_bufreg bufreg + ( + .i_clk (clk), + .i_cnt0 (cnt0), + .i_cnt1 (cnt1), + .i_en (!bufreg_hold), + .i_init (init), + .i_loop (bufreg_loop), + .i_rs1 (rs1), + .i_rs1_en (bufreg_rs1_en), + .i_imm (imm), + .i_imm_en (bufreg_imm_en), + .i_clr_lsb (bufreg_clr_lsb), + .o_lsb (lsb), + .o_dbus_adr (o_dbus_adr), + .o_q (bufreg_q)); + + serv_ctrl + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + ctrl + ( + .clk (clk), + .i_rst (i_rst), + //State + .i_pc_en (ctrl_pc_en), + .i_cnt12to31 (cnt12to31), + .i_cnt2 (cnt2), + .i_cnt_done (cnt_done), + //Control + .i_jump (jump), + .i_jal_or_jalr (jal_or_jalr), + .i_utype (utype), + .i_pc_rel (pc_rel), + .i_trap (trap | mret), + //Data + .i_imm (imm), + .i_buf (bufreg_q), + .i_csr_pc (csr_pc), + .o_rd (ctrl_rd), + .o_bad_pc (bad_pc), + //External + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_ack (i_ibus_ack)); + + + serv_alu alu + ( + .clk (clk), + .i_rst (i_rst), + .i_en (cnt_en), + .i_cnt0 (cnt0), + .i_rs1 (rs1), + .i_rs2 (rs2), + .i_imm (imm), + .i_op_b_rs2 (op_b_source), + .i_buf (bufreg_q), + .i_init (init), + .i_cnt_done (cnt_done), + .i_sub (alu_sub), + .i_bool_op (alu_bool_op), + .i_cmp_eq (alu_cmp_eq), + .i_cmp_uns (alu_cmp_uns), + .o_cmp (alu_cmp), + .i_shamt_en (alu_shamt_en), + .i_sh_right (alu_sh_right), + .i_sh_signed (alu_sh_signed), + .o_sh_done (alu_sh_done), + .i_rd_sel (alu_rd_sel), + .o_rd (alu_rd)); + + wire csr_in; + wire rf_csr_out; + + serv_rf_if + #(.WITH_CSR (WITH_CSR)) + rf_if + (//RF interface + .o_wreg0 (o_wreg0), + .o_wreg1 (o_wreg1), + .o_wen0 (o_wen0), + .o_wen1 (o_wen1), + .o_wdata0 (o_wdata0), + .o_wdata1 (o_wdata1), + .o_rreg0 (o_rreg0), + .o_rreg1 (o_rreg1), + .i_rdata0 (i_rdata0), + .i_rdata1 (i_rdata1), + + //Trap interface + .i_trap (trap), + .i_mret (mret), + .i_mepc (o_ibus_adr[0]), + .i_mem_misalign (mem_misalign), + .i_bufreg_q (bufreg_q), + .i_bad_pc (bad_pc), + .o_csr_pc (csr_pc), + //CSR write port + .i_csr_en (csr_en), + .i_csr_addr (csr_addr), + .i_csr (csr_in), + //RD write port + .i_rd_wen (rd_en), + .i_rd_waddr (rd_addr), + .i_ctrl_rd (ctrl_rd), + .i_alu_rd (alu_rd), + .i_rd_alu_en (rd_alu_en), + .i_csr_rd (csr_rd), + .i_rd_csr_en (rd_csr_en), + .i_mem_rd (mem_rd), + + //RS1 read port + .i_rs1_raddr (rs1_addr), + .o_rs1 (rs1), + //RS2 read port + .i_rs2_raddr (rs2_addr), + .o_rs2 (rs2), + + //CSR read port + .o_csr (rf_csr_out)); + + serv_mem_if + #(.WITH_CSR (WITH_CSR)) + mem_if + ( + .i_clk (clk), + .i_en (cnt_en), + .i_mem_op (mem_op), + .i_signed (mem_signed), + .i_word (mem_word), + .i_half (mem_half), + .i_bytecnt (mem_bytecnt), + .i_rs2 (rs2), + .o_rd (mem_rd), + .i_lsb (lsb), + .o_misalign (mem_misalign), + //External interface + .o_wb_dat (o_dbus_dat), + .o_wb_sel (o_dbus_sel), + .i_wb_rdt (i_dbus_rdt), + .i_wb_ack (i_dbus_ack)); + + generate + if (WITH_CSR) begin + serv_csr csr + ( + .i_clk (clk), + .i_en (cnt_en), + .i_cnt0to3 (cnt0to3), + .i_cnt2 (cnt2), + .i_cnt3 (cnt3), + .i_cnt7 (cnt7), + .i_cnt_done (cnt_done), + .i_e_op (e_op), + .i_ebreak (ebreak), + .i_mem_cmd (o_dbus_we), + .i_mem_misalign (mem_misalign), + .i_rf_csr_out (rf_csr_out), + .o_csr_in (csr_in), + .i_mtip (i_timer_irq), + .o_new_irq (new_irq), + .i_trap_taken (trap_taken), + .i_pending_irq (pending_irq), + .i_mstatus_en (csr_mstatus_en), + .i_mie_en (csr_mie_en ), + .i_mcause_en (csr_mcause_en ), + .i_csr_source (csr_source), + .i_mret (mret), + .i_d (csr_d_sel ? csr_imm : rs1), + .o_q (csr_rd)); + end else begin + assign csr_in = 1'b0; + assign csr_rd = 1'b0; + assign new_irq = 1'b0; + end + endgenerate + + +`ifdef RISCV_FORMAL + reg [31:0] pc = RESET_PC; + + wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en; + + always @(posedge clk) begin + rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst; + rvfi_order <= rvfi_order + {63'd0,rvfi_valid}; + if (o_ibus_cyc & i_ibus_ack) + rvfi_insn <= i_ibus_rdt; + if (o_wen0) + rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]}; + if (cnt_done & ctrl_pc_en) begin + rvfi_pc_rdata <= pc; + if (!rd_en) + rvfi_rd_addr <= 5'd0; + if (!rd_en | !(|rd_addr)) + rvfi_rd_wdata <= 32'd0; + end + rvfi_trap <= trap; + if (rvfi_valid) begin + rvfi_trap <= 1'b0; + pc <= rvfi_pc_wdata; + end + + rvfi_halt <= 1'b0; + rvfi_intr <= 1'b0; + rvfi_mode <= 2'd3; + rvfi_ixl = 2'd1; + if (i_rf_ready) begin + rvfi_rs1_addr <= rs1_addr; + rvfi_rs2_addr <= rs2_addr; + rvfi_rd_addr <= rd_addr; + end + if (rs_en) begin + rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]}; + rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]}; + end + + if (i_dbus_ack) begin + rvfi_mem_addr <= o_dbus_adr; + rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel; + rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000; + rvfi_mem_rdata <= i_dbus_rdt; + rvfi_mem_wdata <= o_dbus_dat; + end + if (i_ibus_ack) begin + rvfi_mem_rmask <= 4'b0000; + rvfi_mem_wmask <= 4'b0000; + end + end + /* verilator lint_off COMBDLY */ + always @(o_ibus_adr) + rvfi_pc_wdata <= o_ibus_adr; + /* verilator lint_on COMBDLY */ + + +`endif + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving.v new file mode 100644 index 0000000000000000000000000000000000000000..374bab40a12ffd914db04336c0c9a3516b30b556 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving.v @@ -0,0 +1,232 @@ +/* serving.v : Top-level for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving + ( + input wire i_clk, + input wire i_rst, + input wire i_timer_irq, + + output wire [31:0] o_wb_adr, + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + output wire o_wb_we , + output wire o_wb_stb, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + parameter memfile = ""; + parameter memsize = 8192; + parameter WITH_CSR = 1; + localparam regs = 32+WITH_CSR*4; + + localparam rf_width = 8; + + localparam aw = $clog2(memsize); + + wire [31:0] wb_ibus_adr; + wire wb_ibus_stb; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_ack; + + wire [31:0] wb_dbus_adr; + wire [31:0] wb_dbus_dat; + wire [3:0] wb_dbus_sel; + wire wb_dbus_we; + wire wb_dbus_stb; + wire [31:0] wb_dbus_rdt; + wire wb_dbus_ack; + + wire [31:0] wb_dmem_adr; + wire [31:0] wb_dmem_dat; + wire [3:0] wb_dmem_sel; + wire wb_dmem_we; + wire wb_dmem_stb; + wire [31:0] wb_dmem_rdt; + wire wb_dmem_ack; + + wire [31:0] wb_mem_adr; + wire [31:0] wb_mem_dat; + wire [3:0] wb_mem_sel; + wire wb_mem_we; + wire wb_mem_stb; + wire [31:0] wb_mem_rdt; + wire wb_mem_ack; + + wire [6+WITH_CSR:0] waddr; + wire [rf_width-1:0] wdata; + wire wen; + wire [6+WITH_CSR:0] raddr; + wire [rf_width-1:0] rdata; + + + wire [aw-1:0] rf_waddr = ~{{aw-2-5-WITH_CSR{1'b0}},waddr}; + wire [aw-1:0] rf_raddr = ~{{aw-2-5-WITH_CSR{1'b0}},raddr}; + + serving_arbiter arbiter + (.i_wb_cpu_dbus_adr (wb_dmem_adr), + .i_wb_cpu_dbus_dat (wb_dmem_dat), + .i_wb_cpu_dbus_sel (wb_dmem_sel), + .i_wb_cpu_dbus_we (wb_dmem_we ), + .i_wb_cpu_dbus_stb (wb_dmem_stb), + .o_wb_cpu_dbus_rdt (wb_dmem_rdt), + .o_wb_cpu_dbus_ack (wb_dmem_ack), + + .i_wb_cpu_ibus_adr (wb_ibus_adr), + .i_wb_cpu_ibus_stb (wb_ibus_stb), + .o_wb_cpu_ibus_rdt (wb_ibus_rdt), + .o_wb_cpu_ibus_ack (wb_ibus_ack), + + .o_wb_mem_adr (wb_mem_adr), + .o_wb_mem_dat (wb_mem_dat), + .o_wb_mem_sel (wb_mem_sel), + .o_wb_mem_we (wb_mem_we ), + .o_wb_mem_stb (wb_mem_stb), + .i_wb_mem_rdt (wb_mem_rdt), + .i_wb_mem_ack (wb_mem_ack)); + + serving_mux mux + (.i_clk (i_clk), + .i_rst (i_rst), + + .i_wb_cpu_adr (wb_dbus_adr), + .i_wb_cpu_dat (wb_dbus_dat), + .i_wb_cpu_sel (wb_dbus_sel), + .i_wb_cpu_we (wb_dbus_we), + .i_wb_cpu_stb (wb_dbus_stb), + .o_wb_cpu_rdt (wb_dbus_rdt), + .o_wb_cpu_ack (wb_dbus_ack), + + .o_wb_mem_adr (wb_dmem_adr), + .o_wb_mem_dat (wb_dmem_dat), + .o_wb_mem_sel (wb_dmem_sel), + .o_wb_mem_we (wb_dmem_we), + .o_wb_mem_stb (wb_dmem_stb), + .i_wb_mem_rdt (wb_dmem_rdt), + .i_wb_mem_ack (wb_dmem_ack), + + .o_wb_ext_adr (o_wb_adr), + .o_wb_ext_dat (o_wb_dat), + .o_wb_ext_sel (o_wb_sel), + .o_wb_ext_we (o_wb_we), + .o_wb_ext_stb (o_wb_stb), + .i_wb_ext_rdt (i_wb_rdt), + .i_wb_ext_ack (i_wb_ack)); + + serving_ram + #(.memfile (memfile), + .depth (memsize)) + ram + (// Wishbone interface + .i_clk (i_clk), + .i_waddr (rf_waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (rf_raddr), + .o_rdata (rdata), + .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), + .i_wb_stb (wb_mem_stb), + .i_wb_we (wb_mem_we) , + .i_wb_sel (wb_mem_sel), + .i_wb_dat (wb_mem_dat), + .o_wb_rdt (wb_mem_rdt), + .o_wb_ack (wb_mem_ack)); + + localparam RF_L2W = $clog2(rf_width); + + wire rf_wreq; + wire rf_rreq; + wire [$clog2(regs)-1:0] wreg0; + wire [$clog2(regs)-1:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [$clog2(regs)-1:0] rreg0; + wire [$clog2(regs)-1:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + + serv_rf_ram_if + #(.width (rf_width), + .csr_regs (WITH_CSR*4)) + rf_ram_if + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_top + #(.RESET_PC (32'h0000_0000), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), + //RF IF + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + //Instruction bus + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_stb), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + //Data bus + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_stb), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_arbiter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..9d537d4a46297b5f8902f134ada0dcba4a8cae2d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_arbiter.v @@ -0,0 +1,57 @@ +/* serving_arbiter.v : I/D arbiter for the serving SoC + * Relies on the fact that not both masters are active at the same time + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_arbiter + ( + input wire [31:0] i_wb_cpu_dbus_adr, + input wire [31:0] i_wb_cpu_dbus_dat, + input wire [3:0] i_wb_cpu_dbus_sel, + input wire i_wb_cpu_dbus_we, + input wire i_wb_cpu_dbus_stb, + output wire [31:0] o_wb_cpu_dbus_rdt, + output wire o_wb_cpu_dbus_ack, + + input wire [31:0] i_wb_cpu_ibus_adr, + input wire i_wb_cpu_ibus_stb, + output wire [31:0] o_wb_cpu_ibus_rdt, + output wire o_wb_cpu_ibus_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack); + + assign o_wb_cpu_dbus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_dbus_ack = i_wb_mem_ack & !i_wb_cpu_ibus_stb; + + assign o_wb_cpu_ibus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_ibus_ack = i_wb_mem_ack & i_wb_cpu_ibus_stb; + + assign o_wb_mem_adr = i_wb_cpu_ibus_stb ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr; + assign o_wb_mem_dat = i_wb_cpu_dbus_dat; + assign o_wb_mem_sel = i_wb_cpu_dbus_sel; + assign o_wb_mem_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_stb; + assign o_wb_mem_stb = i_wb_cpu_ibus_stb | i_wb_cpu_dbus_stb; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..daa1be8e3a714496eb611905cd1070f3f4610548 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_mux.v @@ -0,0 +1,66 @@ +/* serving_mux.v : Simple Wishbone mux for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_mux + ( + input wire i_clk, + input wire i_rst, + + input wire [31:0] i_wb_cpu_adr, + input wire [31:0] i_wb_cpu_dat, + input wire [3:0] i_wb_cpu_sel, + input wire i_wb_cpu_we, + input wire i_wb_cpu_stb, + output wire [31:0] o_wb_cpu_rdt, + output wire o_wb_cpu_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack, + + output wire [31:0] o_wb_ext_adr, + output wire [31:0] o_wb_ext_dat, + output wire [3:0] o_wb_ext_sel, + output wire o_wb_ext_we, + output wire o_wb_ext_stb, + input wire [31:0] i_wb_ext_rdt, + input wire i_wb_ext_ack); + + wire ext = (i_wb_cpu_adr[31:30] != 2'b00); + + assign o_wb_cpu_rdt = ext ? i_wb_ext_rdt : i_wb_mem_rdt; + assign o_wb_cpu_ack = ext ? i_wb_ext_ack : i_wb_mem_ack; + + assign o_wb_mem_adr = i_wb_cpu_adr; + assign o_wb_mem_dat = i_wb_cpu_dat; + assign o_wb_mem_sel = i_wb_cpu_sel; + assign o_wb_mem_we = i_wb_cpu_we; + assign o_wb_mem_stb = i_wb_cpu_stb & !ext; + + assign o_wb_ext_adr = i_wb_cpu_adr; + assign o_wb_ext_dat = i_wb_cpu_dat; + assign o_wb_ext_sel = i_wb_cpu_sel; + assign o_wb_ext_we = i_wb_cpu_we; + assign o_wb_ext_stb = i_wb_cpu_stb & ext; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..b58c22458ee44e8055be281376ce33697b624b79 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/fusesoc_libraries/fusesoc-cores/serv/serving/serving_ram.v @@ -0,0 +1,83 @@ +/* serving_ram.v : Shared RF I/D SRAM for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving_ram + #(//Memory parameters + parameter depth = 256, + parameter aw = $clog2(depth), + parameter memfile = "") + (input wire i_clk, + input wire [aw-1:0] i_waddr, + input wire [7:0] i_wdata, + input wire i_wen, + input wire [aw-1:0] i_raddr, + output wire [7:0] o_rdata, + + input wire [aw-1:2] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire [3:0] i_wb_sel, + input wire i_wb_we, + input wire i_wb_stb, + output wire [31:0] o_wb_rdt, + output reg o_wb_ack); + + wire wb_en = i_wb_stb & !i_wen & !o_wb_ack; + + wire wb_we = i_wb_we & i_wb_sel[bsel]; + + wire we = wb_en ? wb_we : i_wen; + + reg [7:0] mem [0:depth-1] /* verilator public */; + + wire [aw-1:0] waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_waddr; + wire [7:0] wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata; + wire [aw-1:0] raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr; + + reg [2:0] wb_en_r; + + reg [1:0] bsel; + + reg [23:0] wb_rdt; + assign o_wb_rdt = {rdata, wb_rdt}; + + always @(posedge i_clk) begin + if (wb_en) bsel <= bsel + 2'd1; + wb_en_r <= {wb_en_r[1:0], wb_en}; + o_wb_ack <= wb_en & &bsel; + if (bsel == 2'b01) wb_rdt[7:0] <= rdata; + if (bsel == 2'b10) wb_rdt[15:8] <= rdata; + if (bsel == 2'b11) wb_rdt[23:16] <= rdata; + end + + reg [7:0] rdata; + + always @(posedge i_clk) begin + if (we) mem[waddr] <= wdata; + rdata <= mem[raddr]; + end + + initial + if(|memfile) begin + $display("Preloading %m from %s", memfile); + $readmemh(memfile, mem); + end + + assign o_rdata = rdata; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin.tcl b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin.tcl new file mode 100644 index 0000000000000000000000000000000000000000..4583e8fa4dec16eb8a342086faba45733e175a75 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin.tcl @@ -0,0 +1,15 @@ +create_project -name gowin_corescore ./ -pn GW2AR-LV18QN88C8/I7 -device_version C -force +open_project ./gowin_corescore.gprj + +set_option -verilog_std sysv2017 -top_module corescore_gowin_yosys +set_option -place_option 1 +set_option -route_option 0 + +add_file ./src/constraints.cst +add_file ./src/corescore_0/rtl/base.v ./src/corescore_0/rtl/corescore_gowin_yosys.v ./src/corescore_0/rtl/emitter_uart.v ./src/corescore_0/rtl/gw2a18_clk_gen.v ./src/corescore_0/rtl/wb2axis.v +add_file ./src/corescore-corescorecore_0/corescorecore.v +add_file ./src/serv_1.0.2/rtl/serv_alu.v ./src/serv_1.0.2/rtl/serv_bufreg.v ./src/serv_1.0.2/rtl/serv_csr.v ./src/serv_1.0.2/rtl/serv_ctrl.v ./src/serv_1.0.2/rtl/serv_decode.v ./src/serv_1.0.2/rtl/serv_mem_if.v ./src/serv_1.0.2/rtl/serv_rf_if.v ./src/serv_1.0.2/rtl/serv_rf_ram_if.v ./src/serv_1.0.2/rtl/serv_rf_ram.v ./src/serv_1.0.2/rtl/serv_rf_top.v ./src/serv_1.0.2/rtl/serv_shift.v ./src/serv_1.0.2/rtl/serv_state.v ./src/serv_1.0.2/rtl/serv_top.v +add_file ./src/serving_1.0.2/serving/serving_arbiter.v ./src/serving_1.0.2/serving/serving_mux.v ./src/serving_1.0.2/serving/serving_ram.v ./src/serving_1.0.2/serving/serving.v +add_file ./src/verilog-axis_0-r3/rtl/arbiter.v ./src/verilog-axis_0-r3/rtl/axis_arb_mux.v ./src/verilog-axis_0-r3/rtl/axis_async_fifo.v ./src/verilog-axis_0-r3/rtl/priority_encoder.v + +run all \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/impl/gowin_corescore_process_config.json b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/impl/gowin_corescore_process_config.json new file mode 100644 index 0000000000000000000000000000000000000000..f5e5512a384232145ed17ce2278517914af004e5 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/impl/gowin_corescore_process_config.json @@ -0,0 +1,92 @@ +{ + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CPU" : false, + "CRC_CHECK" : true, + "Clock_Route_Order" : 0, + "Convert_SDP32_36_to_SDP16_18" : true, + "Correct_Hold_Violation" : true, + "DONE" : false, + "DOWNLOAD_SPEED" : "default", + "Disable_Insert_Pad" : false, + "ENABLE_CTP" : false, + "ENABLE_MERGE_MODE" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "ERROR_DECTION_AND_CORRECTION" : false, + "ERROR_DECTION_ONLY" : false, + "ERROR_INJECTION" : false, + "EXTERNAL_MASTER_CONFIG_CLOCK" : false, + "Enable_DSRM" : false, + "FORMAT" : "binary", + "FREQUENCY_DIVIDER" : "1", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "Global_Freq" : "default", + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "INCREMENTAL_PLACE_AND_ROUTING" : "0", + "INCREMENTAL_PLACE_ONLY" : "0", + "IncludePath" : [ + + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "MSPI_JUMP" : false, + "MULTIBOOT_ADDRESS_WIDTH" : "24", + "MULTIBOOT_MODE" : "Single", + "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", + "MULTIJUMP_ADDRESS_WIDTH" : "24", + "MULTIJUMP_MODE" : "Single", + "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", + "Multi_Boot" : true, + "OUTPUT_BASE_NAME" : "gowin_corescore", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "1", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "READY" : false, + "RECONFIG_N" : false, + "Ram_RW_Check" : false, + "Replicate_Resources" : false, + "Report_Auto-Placed_Io_Information" : false, + "Route_Maxfan" : "23", + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SEU_HANDLER" : false, + "SEU_HANDLER_CHECKSUM" : false, + "SEU_HANDLER_MODE" : "auto", + "SSPI" : false, + "STOP_SEU_HANDLER" : false, + "Show_All_Warnings" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "corescore_gowin_yosys", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "VCC" : "1.0", + "VCCAUX" : "3.3", + "VCCX" : "3.3", + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "show_all_warnings" : false, + "turn_off_bg" : false +} \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore-corescorecore_0/corescorecore.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore-corescorecore_0/corescorecore.v new file mode 100644 index 0000000000000000000000000000000000000000..3016cd08642a4a43d348d9847b4e5f6d974ef28f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore-corescorecore_0/corescorecore.v @@ -0,0 +1,600 @@ +// THIS FILE IS AUTOGENERATED BY corescorecore_gen +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module corescorecore + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + +wire [399:0] tdata; +wire [49:0] tlast; +wire [49:0] tvalid; +wire [49:0] tready; + +base + #(.memfile ("core_0.hex"), + .memsize (256)) + core_0 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[7:0]), + .o_tlast (tlast[0]), + .o_tvalid (tvalid[0]), + .i_tready (tready[0])); + +base + #(.memfile ("core_1.hex"), + .memsize (256)) + core_1 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[15:8]), + .o_tlast (tlast[1]), + .o_tvalid (tvalid[1]), + .i_tready (tready[1])); + +base + #(.memfile ("core_2.hex"), + .memsize (256)) + core_2 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[23:16]), + .o_tlast (tlast[2]), + .o_tvalid (tvalid[2]), + .i_tready (tready[2])); + +base + #(.memfile ("core_3.hex"), + .memsize (256)) + core_3 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[31:24]), + .o_tlast (tlast[3]), + .o_tvalid (tvalid[3]), + .i_tready (tready[3])); + +base + #(.memfile ("core_4.hex"), + .memsize (256)) + core_4 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[39:32]), + .o_tlast (tlast[4]), + .o_tvalid (tvalid[4]), + .i_tready (tready[4])); + +base + #(.memfile ("core_5.hex"), + .memsize (256)) + core_5 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[47:40]), + .o_tlast (tlast[5]), + .o_tvalid (tvalid[5]), + .i_tready (tready[5])); + +base + #(.memfile ("core_6.hex"), + .memsize (256)) + core_6 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[55:48]), + .o_tlast (tlast[6]), + .o_tvalid (tvalid[6]), + .i_tready (tready[6])); + +base + #(.memfile ("core_7.hex"), + .memsize (256)) + core_7 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[63:56]), + .o_tlast (tlast[7]), + .o_tvalid (tvalid[7]), + .i_tready (tready[7])); + +base + #(.memfile ("core_8.hex"), + .memsize (256)) + core_8 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[71:64]), + .o_tlast (tlast[8]), + .o_tvalid (tvalid[8]), + .i_tready (tready[8])); + +base + #(.memfile ("core_9.hex"), + .memsize (256)) + core_9 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[79:72]), + .o_tlast (tlast[9]), + .o_tvalid (tvalid[9]), + .i_tready (tready[9])); + +base + #(.memfile ("core_10.hex"), + .memsize (256)) + core_10 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[87:80]), + .o_tlast (tlast[10]), + .o_tvalid (tvalid[10]), + .i_tready (tready[10])); + +base + #(.memfile ("core_11.hex"), + .memsize (256)) + core_11 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[95:88]), + .o_tlast (tlast[11]), + .o_tvalid (tvalid[11]), + .i_tready (tready[11])); + +base + #(.memfile ("core_12.hex"), + .memsize (256)) + core_12 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[103:96]), + .o_tlast (tlast[12]), + .o_tvalid (tvalid[12]), + .i_tready (tready[12])); + +base + #(.memfile ("core_13.hex"), + .memsize (256)) + core_13 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[111:104]), + .o_tlast (tlast[13]), + .o_tvalid (tvalid[13]), + .i_tready (tready[13])); + +base + #(.memfile ("core_14.hex"), + .memsize (256)) + core_14 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[119:112]), + .o_tlast (tlast[14]), + .o_tvalid (tvalid[14]), + .i_tready (tready[14])); + +base + #(.memfile ("core_15.hex"), + .memsize (256)) + core_15 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[127:120]), + .o_tlast (tlast[15]), + .o_tvalid (tvalid[15]), + .i_tready (tready[15])); + +base + #(.memfile ("core_16.hex"), + .memsize (256)) + core_16 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[135:128]), + .o_tlast (tlast[16]), + .o_tvalid (tvalid[16]), + .i_tready (tready[16])); + +base + #(.memfile ("core_17.hex"), + .memsize (256)) + core_17 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[143:136]), + .o_tlast (tlast[17]), + .o_tvalid (tvalid[17]), + .i_tready (tready[17])); + +base + #(.memfile ("core_18.hex"), + .memsize (256)) + core_18 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[151:144]), + .o_tlast (tlast[18]), + .o_tvalid (tvalid[18]), + .i_tready (tready[18])); + +base + #(.memfile ("core_19.hex"), + .memsize (256)) + core_19 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[159:152]), + .o_tlast (tlast[19]), + .o_tvalid (tvalid[19]), + .i_tready (tready[19])); + +base + #(.memfile ("core_20.hex"), + .memsize (256)) + core_20 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[167:160]), + .o_tlast (tlast[20]), + .o_tvalid (tvalid[20]), + .i_tready (tready[20])); + +base + #(.memfile ("core_21.hex"), + .memsize (256)) + core_21 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[175:168]), + .o_tlast (tlast[21]), + .o_tvalid (tvalid[21]), + .i_tready (tready[21])); + +base + #(.memfile ("core_22.hex"), + .memsize (256)) + core_22 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[183:176]), + .o_tlast (tlast[22]), + .o_tvalid (tvalid[22]), + .i_tready (tready[22])); + +base + #(.memfile ("core_23.hex"), + .memsize (256)) + core_23 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[191:184]), + .o_tlast (tlast[23]), + .o_tvalid (tvalid[23]), + .i_tready (tready[23])); + +base + #(.memfile ("core_24.hex"), + .memsize (256)) + core_24 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[199:192]), + .o_tlast (tlast[24]), + .o_tvalid (tvalid[24]), + .i_tready (tready[24])); + +base + #(.memfile ("core_25.hex"), + .memsize (256)) + core_25 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[207:200]), + .o_tlast (tlast[25]), + .o_tvalid (tvalid[25]), + .i_tready (tready[25])); + +base + #(.memfile ("core_26.hex"), + .memsize (256)) + core_26 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[215:208]), + .o_tlast (tlast[26]), + .o_tvalid (tvalid[26]), + .i_tready (tready[26])); + +base + #(.memfile ("core_27.hex"), + .memsize (256)) + core_27 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[223:216]), + .o_tlast (tlast[27]), + .o_tvalid (tvalid[27]), + .i_tready (tready[27])); + +base + #(.memfile ("core_28.hex"), + .memsize (256)) + core_28 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[231:224]), + .o_tlast (tlast[28]), + .o_tvalid (tvalid[28]), + .i_tready (tready[28])); + +base + #(.memfile ("core_29.hex"), + .memsize (256)) + core_29 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[239:232]), + .o_tlast (tlast[29]), + .o_tvalid (tvalid[29]), + .i_tready (tready[29])); + +base + #(.memfile ("core_30.hex"), + .memsize (256)) + core_30 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[247:240]), + .o_tlast (tlast[30]), + .o_tvalid (tvalid[30]), + .i_tready (tready[30])); + +base + #(.memfile ("core_31.hex"), + .memsize (256)) + core_31 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[255:248]), + .o_tlast (tlast[31]), + .o_tvalid (tvalid[31]), + .i_tready (tready[31])); + +base + #(.memfile ("core_32.hex"), + .memsize (256)) + core_32 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[263:256]), + .o_tlast (tlast[32]), + .o_tvalid (tvalid[32]), + .i_tready (tready[32])); + +base + #(.memfile ("core_33.hex"), + .memsize (256)) + core_33 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[271:264]), + .o_tlast (tlast[33]), + .o_tvalid (tvalid[33]), + .i_tready (tready[33])); + +base + #(.memfile ("core_34.hex"), + .memsize (256)) + core_34 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[279:272]), + .o_tlast (tlast[34]), + .o_tvalid (tvalid[34]), + .i_tready (tready[34])); + +base + #(.memfile ("core_35.hex"), + .memsize (256)) + core_35 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[287:280]), + .o_tlast (tlast[35]), + .o_tvalid (tvalid[35]), + .i_tready (tready[35])); + +base + #(.memfile ("core_36.hex"), + .memsize (256)) + core_36 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[295:288]), + .o_tlast (tlast[36]), + .o_tvalid (tvalid[36]), + .i_tready (tready[36])); + +base + #(.memfile ("core_37.hex"), + .memsize (256)) + core_37 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[303:296]), + .o_tlast (tlast[37]), + .o_tvalid (tvalid[37]), + .i_tready (tready[37])); + +base + #(.memfile ("core_38.hex"), + .memsize (256)) + core_38 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[311:304]), + .o_tlast (tlast[38]), + .o_tvalid (tvalid[38]), + .i_tready (tready[38])); + +base + #(.memfile ("core_39.hex"), + .memsize (256)) + core_39 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[319:312]), + .o_tlast (tlast[39]), + .o_tvalid (tvalid[39]), + .i_tready (tready[39])); + +base + #(.memfile ("core_40.hex"), + .memsize (256)) + core_40 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[327:320]), + .o_tlast (tlast[40]), + .o_tvalid (tvalid[40]), + .i_tready (tready[40])); + +base + #(.memfile ("core_41.hex"), + .memsize (256)) + core_41 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[335:328]), + .o_tlast (tlast[41]), + .o_tvalid (tvalid[41]), + .i_tready (tready[41])); + +base + #(.memfile ("core_42.hex"), + .memsize (256)) + core_42 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[343:336]), + .o_tlast (tlast[42]), + .o_tvalid (tvalid[42]), + .i_tready (tready[42])); + +base + #(.memfile ("core_43.hex"), + .memsize (256)) + core_43 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[351:344]), + .o_tlast (tlast[43]), + .o_tvalid (tvalid[43]), + .i_tready (tready[43])); + +base + #(.memfile ("core_44.hex"), + .memsize (256)) + core_44 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[359:352]), + .o_tlast (tlast[44]), + .o_tvalid (tvalid[44]), + .i_tready (tready[44])); + +base + #(.memfile ("core_45.hex"), + .memsize (256)) + core_45 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[367:360]), + .o_tlast (tlast[45]), + .o_tvalid (tvalid[45]), + .i_tready (tready[45])); + +base + #(.memfile ("core_46.hex"), + .memsize (256)) + core_46 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[375:368]), + .o_tlast (tlast[46]), + .o_tvalid (tvalid[46]), + .i_tready (tready[46])); + +base + #(.memfile ("core_47.hex"), + .memsize (256)) + core_47 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[383:376]), + .o_tlast (tlast[47]), + .o_tvalid (tvalid[47]), + .i_tready (tready[47])); + +base + #(.memfile ("core_48.hex"), + .memsize (256)) + core_48 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[391:384]), + .o_tlast (tlast[48]), + .o_tvalid (tvalid[48]), + .i_tready (tready[48])); + +base + #(.memfile ("core_49.hex"), + .memsize (256)) + core_49 + (.i_clk (i_clk), + .i_rst (i_rst), + .o_tdata (tdata[399:392]), + .o_tlast (tlast[49]), + .o_tvalid (tvalid[49]), + .i_tready (tready[49])); + +axis_arb_mux + #(.S_COUNT (50), + .DATA_WIDTH (8), + .KEEP_ENABLE (0), + .KEEP_WIDTH (1), + .ID_ENABLE (0), + .ID_WIDTH (8), + .DEST_ENABLE (0), + .DEST_WIDTH (8), + .USER_ENABLE (0), + .USER_WIDTH (1), + .ARB_TYPE ("ROUND_ROBIN"), + .LSB_PRIORITY ("HIGH")) + axis_mux + (.clk (i_clk), + .rst (i_rst), + .s_axis_tdata (tdata), + .s_axis_tkeep (50'd0), + .s_axis_tvalid (tvalid), + .s_axis_tready (tready), + .s_axis_tlast (tlast), + .s_axis_tid (400'd0), + .s_axis_tdest (400'd0), + .s_axis_tuser (50'd0), + .m_axis_tdata (o_tdata), + .m_axis_tkeep (), + .m_axis_tvalid (o_tvalid), + .m_axis_tready (i_tready), + .m_axis_tlast (o_tlast), + .m_axis_tid (), + .m_axis_tdest (), + .m_axis_tuser ()); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/base.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/base.v new file mode 100644 index 0000000000000000000000000000000000000000..ba75ad9dc0c15e734cf479e693d9c6c449bf5ed7 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/base.v @@ -0,0 +1,46 @@ +module base + (input wire i_clk, + input wire i_rst, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + parameter memfile = ""; + parameter memsize = 8192; + + wire [31:0] wb_dat; + wire wb_we; + wire wb_stb; + wire wb_ack; + + wb2axis w2s + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wb_dat (wb_dat[8:0]), + .i_wb_we (wb_we), + .i_wb_stb (wb_stb), + .o_wb_ack (wb_ack), + .o_tdata (o_tdata), + .o_tlast (o_tlast), + .o_tvalid (o_tvalid), + .i_tready (i_tready)); + + serving + #(.memfile (memfile), + .memsize (memsize), + .WITH_CSR (0)) + serving + (.i_clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (1'b0), + + .o_wb_adr (), + .o_wb_dat (wb_dat), + .o_wb_sel (), + .o_wb_we (wb_we), + .o_wb_stb (wb_stb), + .i_wb_rdt (32'd0), + .i_wb_ack (wb_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/corescore_gowin_yosys.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/corescore_gowin_yosys.v new file mode 100644 index 0000000000000000000000000000000000000000..c11e8ad8b39b81ea46821361bedfcfdb10c1ef13 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/corescore_gowin_yosys.v @@ -0,0 +1,39 @@ +(* keep = 1 *) +module corescore_gowin_yosys + ( + input i_clk, + input i_rstn, + output wire o_uart_tx); + + wire clk; + wire o_rst; + + //Create a 16MHz clock from 10MHz using PLL + clkgen clkgen + (.i_clk (i_clk), + .i_rstn (i_rstn), + .o_clk_core(clk), + .o_rst_core(o_rst)); + + wire [7:0] tdata; + wire tlast; + wire tvalid; + wire tready; + + corescorecore corescorecore + (.i_clk (clk), + .i_rst (o_rst), + .o_tdata (tdata), + .o_tlast (tlast), + .o_tvalid (tvalid), + .i_tready (tready)); + + emitter_uart emitter + (.i_clk (clk), + .i_rst (o_rst), + .i_tdata (tdata), + .i_tvalid (tvalid), + .o_tready (tready), + .o_uart_tx (o_uart_tx)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/emitter_uart.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/emitter_uart.v new file mode 100644 index 0000000000000000000000000000000000000000..87146563eb9490b4a236e25e4bc0b1438d0aa2c0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/emitter_uart.v @@ -0,0 +1,45 @@ +/* + * emitter_uart.v : Simple UA(R)T used as emitter in CoreScore + * + * SPDX-FileCopyrightText: 2023 Olof Kindgren + * SPDX-License-Identifier: Apache-2.0 + */ + +module emitter_uart + #(parameter clk_freq_hz = 16_000_000, + parameter baud_rate = 57600) + (input wire i_clk, + input wire i_rst, + input wire [7:0] i_tdata, + input wire i_tvalid, + output reg o_tready, + output wire o_uart_tx); + + localparam START_VALUE = clk_freq_hz/baud_rate; + + localparam WIDTH = $clog2(START_VALUE); + + reg [WIDTH:0] cnt; + + reg [9:0] data; + + assign o_uart_tx = data[0] | !(|data); + + always @(posedge i_clk) begin + if (cnt[WIDTH] & !(|data)) + o_tready <= 1'b1; + else if (i_tvalid & o_tready) + o_tready <= 1'b0; + + if (o_tready | cnt[WIDTH]) + cnt <= {1'b0,START_VALUE[WIDTH-1:0]}; + else + cnt <= cnt-1; + + if (cnt[WIDTH]) + data <= {1'b0, data[9:1]}; + else if (i_tvalid & o_tready) + data <= {1'b1, i_tdata, 1'b0}; + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/gw2a18_clk_gen.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/gw2a18_clk_gen.v new file mode 100644 index 0000000000000000000000000000000000000000..4f0f0c5038ddf200a14a3d3703bdd0d9de31f057 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/gw2a18_clk_gen.v @@ -0,0 +1,75 @@ +module clkgen ( + input wire i_clk, + input wire i_rstn, + output wire o_clk_core, + output wire o_rst_core +); + +wire pll_lock; + + rPLL #( + //.DEVICE ("GW1NR-9C"), + //.DEVICE ("GW2AR-18C"), + .DEVICE ("GW2AR-18C"), + .FCLKIN ("27"), + .DYN_IDIV_SEL ("false"), + .IDIV_SEL (4), + .DYN_FBDIV_SEL ("false"), + .FBDIV_SEL (2), + .DYN_ODIV_SEL ("false"), + .ODIV_SEL (32), + .PSDA_SEL ("0000"), + .DYN_DA_EN ("true"), + .DUTYDA_SEL ("1000"), + .CLKOUT_FT_DIR (1'b1), + .CLKOUTP_FT_DIR (1'b1), + .CLKOUT_DLY_STEP (0), + .CLKOUTP_DLY_STEP (0), + .CLKFB_SEL ("internal"), + .CLKOUT_BYPASS ("false"), + .CLKOUTP_BYPASS ("false"), + .CLKOUTD_BYPASS ("false"), + .DYN_SDIV_SEL (2), + .CLKOUTD_SRC ("CLKOUT"), + .CLKOUTD3_SRC ("CLKOUT") + ) + u_pll ( + .CLKOUT (o_clk_core), + .LOCK (pll_lock), + .CLKOUTP (), + .CLKOUTD (), + .CLKOUTD3 (), + + .RESET (1'b0), + .RESET_P (1'b0), + .CLKIN (i_clk), + .CLKFB (1'b0), + .FBDSEL ('0), + .IDSEL ('0), + .ODSEL ('0), + .PSDA ('0), + .DUTYDA ('0), + .FDLY ('0) + ); + +//-------------------------------------------------- +// Reset synchronizer +//-------------------------------------------------- + reg srst_n_pipe; + wire final_rst; + assign final_rst = ~i_rstn | ~pll_lock; + reg srst_n; + + always @(posedge final_rst or posedge o_clk_core) begin + if (final_rst == 1'b1) begin + srst_n_pipe <= 1'b0; + srst_n <= 1'b0; + end + else begin + srst_n_pipe <= 1'b1; + srst_n <= srst_n_pipe; + end + end + + assign o_rst_core = ~srst_n; +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/wb2axis.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/wb2axis.v new file mode 100644 index 0000000000000000000000000000000000000000..10d983e13c230ac1367215aa64b7511b490590db --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/corescore_0/rtl/wb2axis.v @@ -0,0 +1,25 @@ +`default_nettype none +module wb2axis + ( + input wire i_clk, + input wire i_rst, + input wire [8:0] i_wb_dat, + input wire i_wb_we, + input wire i_wb_stb, + output reg o_wb_ack, + output wire [7:0] o_tdata, + output wire o_tlast, + output wire o_tvalid, + input wire i_tready); + + always @(posedge i_clk) begin + o_wb_ack <= i_wb_stb & i_tready & !o_wb_ack; + if (i_rst) + o_wb_ack <= 1'b0; + end + + assign o_tvalid = i_wb_stb & i_wb_we & !o_wb_ack; + assign o_tdata = i_wb_dat[7:0]; + assign o_tlast = i_wb_dat[8]; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_alu.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_alu.v new file mode 100644 index 0000000000000000000000000000000000000000..b5e1164c5358ca5878f08fed3991759c7a6215f0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_alu.v @@ -0,0 +1,106 @@ +`default_nettype none +module serv_alu + ( + input wire clk, + input wire i_rst, + input wire i_en, + input wire i_cnt0, + input wire i_rs1, + input wire i_rs2, + input wire i_imm, + input wire i_op_b_rs2, + input wire i_buf, + input wire i_init, + input wire i_cnt_done, + input wire i_sub, + input wire [1:0] i_bool_op, + input wire i_cmp_eq, + input wire i_cmp_uns, + output wire o_cmp, + input wire i_shamt_en, + input wire i_sh_right, + input wire i_sh_signed, + output wire o_sh_done, + input wire [3:0] i_rd_sel, + output wire o_rd); + + wire result_add; + wire result_eq; + wire result_lt; + wire result_sh; + + reg result_lt_r; + + reg [4:0] shamt; + reg shamt_msb; + + wire shamt_ser; + wire plus_1; + + wire add_cy; + reg add_cy_r; + + wire b_inv_plus_1; + wire b_inv_plus_1_cy; + reg b_inv_plus_1_cy_r; + + wire op_b = i_op_b_rs2 ? i_rs2 : i_imm; + assign shamt_ser = i_sh_right ? op_b : b_inv_plus_1; + + serv_shift shift + ( + .i_clk (clk), + .i_load (i_init), + .i_shamt (shamt), + .i_shamt_msb (shamt_msb), + .i_signbit (i_sh_signed & i_rs1), + .i_right (i_sh_right), + .o_done (o_sh_done), + .i_d (i_buf), + .o_q (result_sh)); + + wire add_b = i_sub ? b_inv_plus_1 : op_b; + assign {add_cy,result_add} = i_rs1+add_b+add_cy_r; + assign {b_inv_plus_1_cy,b_inv_plus_1} = {1'b0,~op_b}+plus_1+b_inv_plus_1_cy_r; + + reg lt_r; + + reg eq_r; + + wire lt_sign = i_cnt_done & !i_cmp_uns; + + wire eq = (i_rs1 == op_b); + + assign result_eq = eq & eq_r; + assign result_lt = eq ? lt_r : op_b^lt_sign; + + assign plus_1 = i_cnt0; + assign o_cmp = i_cmp_eq ? result_eq : result_lt; + + localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor + wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}]; + + assign o_rd = (i_rd_sel[0] & result_add) | + (i_rd_sel[1] & result_sh) | + (i_rd_sel[2] & result_lt_r & plus_1) | + (i_rd_sel[3] & result_bool); + + + always @(posedge clk) begin + add_cy_r <= i_en & add_cy; + b_inv_plus_1_cy_r <= i_en & b_inv_plus_1_cy; + + lt_r <= result_lt & i_en; + + if (i_en) begin + result_lt_r <= result_lt; + end + eq_r <= result_eq | ~i_en; + + if (i_shamt_en) begin + shamt_msb <= b_inv_plus_1_cy; + shamt <= {shamt_ser,shamt[4:1]}; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_bufreg.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_bufreg.v new file mode 100644 index 0000000000000000000000000000000000000000..e7172a2a1a47d416569802a5c113b19e849caca5 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_bufreg.v @@ -0,0 +1,42 @@ +module serv_bufreg + ( + input wire i_clk, + input wire i_cnt0, + input wire i_cnt1, + input wire i_en, + input wire i_init, + input wire i_loop, + input wire i_rs1, + input wire i_rs1_en, + input wire i_imm, + input wire i_imm_en, + input wire i_clr_lsb, + output reg [1:0] o_lsb, + output wire [31:0] o_dbus_adr, + output wire o_q); + + wire c, q; + reg c_r; + (* ram_style = "distributed" *) reg [31:0] data; + + wire clr_lsb = i_cnt0 & i_clr_lsb; + + assign {c,q} = {1'b0,(i_rs1 & i_rs1_en)} + {1'b0,(i_imm & i_imm_en & !clr_lsb)} + c_r; + + always @(posedge i_clk) begin + //Clear carry when not in INIT state + c_r <= c & i_init; + + if (i_en) + data <= {(i_loop & !i_init) ? o_q : q, data[31:1]}; + + if (i_cnt0 & i_init) + o_lsb[0] <= q; + if (i_cnt1 & i_init) + o_lsb[1] <= q; + end + + assign o_q = data[0]; + assign o_dbus_adr = {data[31:2], 2'b00}; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_csr.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_csr.v new file mode 100644 index 0000000000000000000000000000000000000000..897e2728f60784fe39e6819869554b10ee0aec76 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_csr.v @@ -0,0 +1,108 @@ +`default_nettype none +module serv_csr + ( + input wire i_clk, + input wire i_en, + input wire i_cnt0to3, + input wire i_cnt2, + input wire i_cnt3, + input wire i_cnt7, + input wire i_cnt_done, + input wire i_e_op, + input wire i_ebreak, + input wire i_mem_cmd, + input wire i_mem_misalign, + //From mpram + input wire i_rf_csr_out, + //to mpram + output wire o_csr_in, + //Stuff + input wire i_mtip, + output wire o_new_irq, + input wire i_pending_irq, + input wire i_trap_taken, + input wire i_mstatus_en, + input wire i_mie_en, + input wire i_mcause_en, + input wire [1:0] i_csr_source, + input wire i_mret, + input wire i_d, + output wire o_q); + +`include "serv_params.vh" + + reg mstatus; + reg mstatus_mie; + reg mstatus_mpie; + reg mie_mtie; + + reg mcause31; + reg [3:0] mcause3_0; + wire mcause; + + wire csr_in; + wire csr_out; + + reg timer_irq_r; + + assign csr_in = (i_csr_source == CSR_SOURCE_EXT) ? i_d : + (i_csr_source == CSR_SOURCE_SET) ? csr_out | i_d : + (i_csr_source == CSR_SOURCE_CLR) ? csr_out & ~i_d : + (i_csr_source == CSR_SOURCE_CSR) ? csr_out : + 1'bx; + + assign csr_out = (i_mstatus_en & i_en & mstatus) | + i_rf_csr_out | + (i_mcause_en & i_en & mcause); + + assign o_q = csr_out; + + wire timer_irq = i_mtip & mstatus_mie & mie_mtie; + + assign mcause = i_cnt0to3 ? mcause3_0[0] : //[3:0] + i_cnt_done ? mcause31 //[31] + : 1'b0; + + assign o_csr_in = csr_in; + + assign o_new_irq = !timer_irq_r & timer_irq; + + + always @(posedge i_clk) begin + /* + Note: To save resources mstatus_mpie (mstatus bit 7) is not + readable or writable from sw + */ + if (i_mstatus_en & i_cnt3) + mstatus_mie <= csr_in; + + if (i_mie_en & i_cnt7) + mie_mtie <= csr_in; + + mstatus <= i_cnt2 & mstatus_mie; + + timer_irq_r <= timer_irq; + + if (i_mret) begin + mstatus_mie <= mstatus_mpie; + end + + if (i_trap_taken) begin + mstatus_mpie <= mstatus_mie; + mstatus_mie <= 1'b0; + mcause31 <= i_pending_irq; + mcause3_0 <= i_pending_irq ? 4'd7 : + i_e_op ? {!i_ebreak, 3'b011} : + i_mem_misalign ? {2'b01, i_mem_cmd, 1'b0} : + 4'd0; + end + + if (i_mcause_en & i_en) begin + if (i_cnt0to3) + mcause3_0 <= {csr_in, mcause3_0[3:1]}; + if (i_cnt_done) + mcause31 <= csr_in; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_ctrl.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_ctrl.v new file mode 100644 index 0000000000000000000000000000000000000000..f5899a58aa0df8db394b05decf6f46ecfd41df11 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_ctrl.v @@ -0,0 +1,87 @@ +`default_nettype none +module serv_ctrl + ( + input wire clk, + input wire i_rst, + //State + input wire i_pc_en, + input wire i_cnt12to31, + input wire i_cnt2, + input wire i_cnt_done, + //Control + input wire i_jump, + input wire i_jal_or_jalr, + input wire i_utype, + input wire i_pc_rel, + input wire i_trap, + //Data + input wire i_imm, + input wire i_buf, + input wire i_csr_pc, + output wire o_rd, + output wire o_bad_pc, + //External + output reg [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire i_ibus_ack); + + parameter RESET_PC = 32'd0; + parameter WITH_CSR = 1; + + reg en_pc_r; + + wire pc_plus_4; + wire pc_plus_4_cy; + reg pc_plus_4_cy_r; + wire pc_plus_offset; + wire pc_plus_offset_cy; + reg pc_plus_offset_cy_r; + wire pc_plus_offset_aligned; + wire plus_4; + + wire pc = o_ibus_adr[0]; + + wire new_pc; + + wire offset_a; + wire offset_b; + + assign plus_4 = i_cnt2; + + assign o_bad_pc = pc_plus_offset_aligned; + + assign {pc_plus_4_cy,pc_plus_4} = pc+plus_4+pc_plus_4_cy_r; + + generate + if (WITH_CSR) + assign new_pc = i_trap ? (i_csr_pc & en_pc_r) : i_jump ? pc_plus_offset_aligned : pc_plus_4; + else + assign new_pc = i_jump ? pc_plus_offset_aligned : pc_plus_4; + endgenerate + assign o_rd = (i_utype & pc_plus_offset_aligned) | (pc_plus_4 & i_jal_or_jalr); + + assign offset_a = i_pc_rel & pc; + assign offset_b = i_utype ? (i_imm & i_cnt12to31): i_buf; + assign {pc_plus_offset_cy,pc_plus_offset} = offset_a+offset_b+pc_plus_offset_cy_r; + + assign pc_plus_offset_aligned = pc_plus_offset & en_pc_r; + + assign o_ibus_cyc = en_pc_r & !i_pc_en; + + always @(posedge clk) begin + pc_plus_4_cy_r <= i_pc_en & pc_plus_4_cy; + pc_plus_offset_cy_r <= i_pc_en & pc_plus_offset_cy; + + if (i_pc_en) begin + en_pc_r <= 1'b1; + o_ibus_adr <= {new_pc, o_ibus_adr[31:1]}; + end else if (o_ibus_cyc & i_ibus_ack) + en_pc_r <= 1'b0; + + if (i_rst) begin + en_pc_r <= 1'b1; + o_ibus_adr <= RESET_PC; + end + end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_decode.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_decode.v new file mode 100644 index 0000000000000000000000000000000000000000..d66a1e046f47cafac6113e7d9c138c31fa82253c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_decode.v @@ -0,0 +1,239 @@ +`default_nettype none +module serv_decode + ( + input wire clk, + //Input + input wire i_cnt_en, + input wire i_cnt_done, + input wire [31:2] i_wb_rdt, + input wire i_wb_en, + input wire i_alu_cmp, + //To state + output wire o_take_branch, + output wire o_e_op, + output wire o_ebreak, + output wire o_branch_op, + output wire o_mem_op, + output wire o_shift_op, + output wire o_slt_op, + output wire o_rd_op, + //To bufreg + output wire o_bufreg_loop, + output wire o_bufreg_rs1_en, + output wire o_bufreg_imm_en, + output wire o_bufreg_clr_lsb, + //To ctrl + output wire o_ctrl_jal_or_jalr, + output wire o_ctrl_utype, + output wire o_ctrl_pc_rel, + output wire o_ctrl_mret, + //To alu + output wire o_alu_sub, + output wire [1:0] o_alu_bool_op, + output wire o_alu_cmp_eq, + output wire o_alu_cmp_uns, + output wire o_alu_sh_signed, + output wire o_alu_sh_right, + output wire [3:0] o_alu_rd_sel, + //To RF + output reg [4:0] o_rf_rd_addr, + output reg [4:0] o_rf_rs1_addr, + output reg [4:0] o_rf_rs2_addr, + //To mem IF + output wire o_mem_signed, + output wire o_mem_word, + output wire o_mem_half, + output wire o_mem_cmd, + //To CSR + output wire o_csr_en, + output wire [1:0] o_csr_addr, + output wire o_csr_mstatus_en, + output wire o_csr_mie_en, + output wire o_csr_mcause_en, + output wire [1:0] o_csr_source, + output wire o_csr_d_sel, + output wire o_csr_imm, + //To top + output wire o_imm, + output wire o_op_b_source, + output wire o_rd_csr_en, + output wire o_rd_alu_en); + +`include "serv_params.vh" + + reg [4:0] opcode; + reg [2:0] funct3; + reg op20; + reg op21; + reg op22; + reg op26; + + reg imm30; + + wire op_or_opimm = (!opcode[4] & opcode[2] & !opcode[0]); + + assign o_mem_op = !opcode[4] & !opcode[2] & !opcode[0]; + assign o_shift_op = op_or_opimm & (funct3[1:0] == 2'b01); + assign o_slt_op = op_or_opimm & (funct3[2:1] == 2'b01); + assign o_branch_op = opcode[4] & !opcode[2]; + + //Matches system opcodes except CSR accesses (funct3 == 0) + //No idea anymore why the !op21 condition is needed here + assign o_e_op = opcode[4] & opcode[2] & !op21 & !(|funct3); + + assign o_ebreak = op20; + + //jal,branch = imm + //jalr = rs1+imm + //mem = rs1+imm + //shift = rs1 + assign o_bufreg_rs1_en = !opcode[4] | (!opcode[1] & opcode[0]); + assign o_bufreg_imm_en = !opcode[2]; + + //Loop bufreg contents for shift operations + assign o_bufreg_loop = op_or_opimm; + + //Clear LSB of immediate for BRANCH and JAL ops + //True for BRANCH and JAL + //False for JALR/LOAD/STORE/OP/OPIMM? + assign o_bufreg_clr_lsb = opcode[4] & ((opcode[1:0] == 2'b00) | (opcode[1:0] == 2'b11)); + + //Take branch for jump or branch instructions (opcode == 1x0xx) if + //a) It's an unconditional branch (opcode[0] == 1) + //b) It's a conditional branch (opcode[0] == 0) of type beq,blt,bltu (funct3[0] == 0) and ALU compare is true + //c) It's a conditional branch (opcode[0] == 0) of type bne,bge,bgeu (funct3[0] == 1) and ALU compare is false + //Only valid during the last cycle of INIT, when the branch condition has + //been calculated. + assign o_take_branch = opcode[4] & !opcode[2] & (opcode[0] | (i_alu_cmp^funct3[0])); + + assign o_ctrl_utype = !opcode[4] & opcode[2] & opcode[0]; + assign o_ctrl_jal_or_jalr = opcode[4] & opcode[0]; + + //True for jal, b* auipc + //False for jalr, lui + assign o_ctrl_pc_rel = (opcode[2:0] == 3'b000) | + (opcode[1:0] == 2'b11) | + (opcode[4:3] == 2'b00); + + assign o_ctrl_mret = (opcode[4] & opcode[2] & op21 & !(|funct3)); + + //Write to RD + //True for OP-IMM, AUIPC, OP, LUI, SYSTEM, JALR, JAL, LOAD + //False for STORE, BRANCH, MISC-MEM + assign o_rd_op = (opcode[2] | + (!opcode[2] & opcode[4] & opcode[0]) | + (!opcode[2] & !opcode[3] & !opcode[0])) & (|o_rf_rd_addr); + + assign o_alu_sub = opcode[3] & imm30/*alu_sub_r*/; + + /* + 300 0_000 mstatus RWSC + 304 0_100 mie SCWi + 305 0_101 mtvec RW + 340 1_000 mscratch + 341 1_001 mepc RW + 342 1_010 mcause R + 343 1_011 mtval + 344 1_100 mip CWi + */ + + //true for mtvec,mscratch,mepc and mtval + //false for mstatus, mie, mcause, mip + wire csr_valid = op20 | (op26 & !op22 & !op21); + + //Matches system ops except eceall/ebreak + wire csr_op = opcode[4] & opcode[2] & (|funct3); + assign o_rd_csr_en = csr_op; + + assign o_csr_en = csr_op & csr_valid; + assign o_csr_mstatus_en = csr_op & !op26 & !op22; + assign o_csr_mie_en = csr_op & !op26 & op22 & !op20; + assign o_csr_mcause_en = csr_op & op21 & !op20; + + assign o_csr_source = funct3[1:0]; + assign o_csr_d_sel = funct3[2]; + assign o_csr_imm = o_rf_rs1_addr[0]; + + assign o_csr_addr = (op26 & !op20) ? CSR_MSCRATCH : + (op26 & !op21) ? CSR_MEPC : + (op26) ? CSR_MTVAL : + CSR_MTVEC; + + assign o_alu_cmp_eq = funct3[2:1] == 2'b00; + + assign o_alu_cmp_uns = (funct3[0] & funct3[1]) | (funct3[1] & funct3[2]); + assign o_alu_sh_signed = imm30; + assign o_alu_sh_right = funct3[2]; + + assign o_mem_cmd = opcode[3]; + assign o_mem_signed = ~funct3[2]; + assign o_mem_word = funct3[1]; + assign o_mem_half = funct3[0]; + + assign o_alu_bool_op = funct3[1:0]; + + reg signbit; + + reg [8:0] imm19_12_20; + reg imm7; + reg [5:0] imm30_25; + reg [4:0] imm24_20; + reg [4:0] imm11_7; + + wire [1:0] m2; + //True for OP-IMM, LOAD, STORE, JALR + //False for LUI, AUIPC, JAL + assign m2[0] = (opcode[1:0] == 2'b00) | (opcode[2:1] == 2'b00); + assign m2[1] = opcode[4] & !opcode[0]; + wire m3 = opcode[4]; + + assign o_alu_rd_sel[0] = (funct3 == 3'b000); // Add/sub + assign o_alu_rd_sel[1] = (funct3[1:0] == 2'b01); //Shift + assign o_alu_rd_sel[2] = (funct3[2:1] == 2'b01); //SLT* + assign o_alu_rd_sel[3] = (funct3[2] & !(funct3[1:0] == 2'b01)); //Bool + always @(posedge clk) begin + if (i_wb_en) begin + o_rf_rd_addr <= i_wb_rdt[11:7]; + o_rf_rs1_addr <= i_wb_rdt[19:15]; + o_rf_rs2_addr <= i_wb_rdt[24:20]; + funct3 <= i_wb_rdt[14:12]; + imm30 <= i_wb_rdt[30]; + opcode <= i_wb_rdt[6:2]; + op20 <= i_wb_rdt[20]; + op21 <= i_wb_rdt[21]; + op22 <= i_wb_rdt[22]; + op26 <= i_wb_rdt[26]; + + //Immediate decoder + signbit <= i_wb_rdt[31]; + imm19_12_20 <= {i_wb_rdt[19:12],i_wb_rdt[20]}; + imm7 <= i_wb_rdt[7]; + imm30_25 <= i_wb_rdt[30:25]; + imm24_20 <= i_wb_rdt[24:20]; + imm11_7 <= i_wb_rdt[11:7]; + end + if (i_cnt_en) begin + imm19_12_20 <= {m3 ? signbit : imm24_20[0], imm19_12_20[8:1]}; + imm7 <= signbit; + imm30_25 <= {m2[1] ? imm7 : m2[0] ? signbit : imm19_12_20[0], imm30_25[5:1]}; + imm24_20 <= {imm30_25[0], imm24_20[4:1]}; + imm11_7 <= {imm30_25[0], imm11_7[4:1]}; + if (csr_op & o_csr_d_sel) + o_rf_rs1_addr <= {1'b0,o_rf_rs1_addr[4:1]}; + end + end + + //True for S (STORE) or B (BRANCH) type instructions + //False for J type instructions + wire m1 = opcode[3:0] == 4'b1000; + + assign o_imm = i_cnt_done ? signbit : m1 ? imm11_7[0] : imm24_20[0]; + + //0 (OP_B_SOURCE_IMM) when OPIMM + //1 (OP_B_SOURCE_RS2) when BRANCH or OP + assign o_op_b_source = opcode[3]; + + assign o_rd_alu_en = !opcode[0] & opcode[2] & !opcode[4]; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_mem_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_mem_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b9ea5cb50b5b09c2119fad52b413e2dc880afdea --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_mem_if.v @@ -0,0 +1,68 @@ +`default_nettype none +module serv_mem_if + #(parameter WITH_CSR = 1) + ( + input wire i_clk, + input wire i_en, + input wire i_mem_op, + input wire i_signed, + input wire i_word, + input wire i_half, + input wire [1:0] i_bytecnt, + input wire i_rs2, + output wire o_rd, + input wire [1:0] i_lsb, + output wire o_misalign, + //External interface + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + reg signbit; + + wire [2:0] tmp = {1'b0,i_bytecnt}+{1'b0,i_lsb}; + + reg [31:0] dat; + + wire dat_en = i_en & !tmp[2]; + + wire dat_cur = + ((i_lsb == 2'd3) & dat[24]) | + ((i_lsb == 2'd2) & dat[16]) | + ((i_lsb == 2'd1) & dat[8]) | + ((i_lsb == 2'd0) & dat[0]); + + wire dat_valid = i_word | (i_bytecnt == 2'b00) | (i_half & !i_bytecnt[1]); + + assign o_rd = i_mem_op & (dat_valid ? dat_cur : signbit & i_signed); + + assign o_wb_sel[3] = (i_lsb == 2'b11) | i_word | (i_half & i_lsb[1]); + assign o_wb_sel[2] = (i_lsb == 2'b10) | i_word; + assign o_wb_sel[1] = (i_lsb == 2'b01) | i_word | (i_half & !i_lsb[1]); + assign o_wb_sel[0] = (i_lsb == 2'b00); + + assign o_wb_dat = dat; + + always @(posedge i_clk) begin + if (dat_en) + dat <= {i_rs2, dat[31:1]}; + + if (i_wb_ack) + dat <= i_wb_rdt; + + if (dat_valid) + signbit <= dat_cur; + end + generate + if (WITH_CSR) begin + reg misalign; + always @(posedge i_clk) + misalign <= (i_lsb[0] & (i_word | i_half)) | (i_lsb[1] & i_word); + assign o_misalign = misalign & i_mem_op; + end else begin + assign o_misalign = 1'b0; + end + endgenerate + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_params.vh b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_params.vh new file mode 100644 index 0000000000000000000000000000000000000000..0cf79d96ed485f0846d52efac5338c6a7d9d6552 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_params.vh @@ -0,0 +1,11 @@ +localparam [1:0] + CSR_SOURCE_CSR = 2'b00, + CSR_SOURCE_EXT = 2'b01, + CSR_SOURCE_SET = 2'b10, + CSR_SOURCE_CLR = 2'b11; + +localparam [1:0] + CSR_MSCRATCH = 2'b00, + CSR_MTVEC = 2'b01, + CSR_MEPC = 2'b10, + CSR_MTVAL = 2'b11; diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_if.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_if.v new file mode 100644 index 0000000000000000000000000000000000000000..b26e75f1dba95334cfbf1eaa467facdc6833cb42 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_if.v @@ -0,0 +1,122 @@ +`default_nettype none +module serv_rf_if + #(parameter WITH_CSR = 1) + (//RF Interface + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + //Trap interface + input wire i_trap, + input wire i_mret, + input wire i_mepc, + input wire i_mem_misalign, + input wire i_bufreg_q, + input wire i_bad_pc, + output wire o_csr_pc, + //CSR interface + input wire i_csr_en, + input wire [1:0] i_csr_addr, + input wire i_csr, + output wire o_csr, + //RD write port + input wire i_rd_wen, + input wire [4:0] i_rd_waddr, + input wire i_ctrl_rd, + input wire i_alu_rd, + input wire i_rd_alu_en, + input wire i_csr_rd, + input wire i_rd_csr_en, + input wire i_mem_rd, + + //RS1 read port + input wire [4:0] i_rs1_raddr, + output wire o_rs1, + //RS2 read port + input wire [4:0] i_rs2_raddr, + output wire o_rs2); + + +`include "serv_params.vh" + + /* + ********** Write side *********** + */ + + generate + if (WITH_CSR) begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_csr_rd & i_rd_csr_en) | + (i_mem_rd); + + wire mtval = i_mem_misalign ? i_bufreg_q : i_bad_pc; + + assign o_wdata0 = i_trap ? mtval : rd; + assign o_wdata1 = i_trap ? i_mepc : i_csr; + + //port 0 rd mtval + //port 1 csr mepc + //mepc 100010 + //mtval 100011 + //csr 1000xx + //rd 0xxxxx + assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr}; + assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr}; + + assign o_wen0 = i_trap | i_rd_wen; + assign o_wen1 = i_trap | i_csr_en; + + /* + ********** Read side *********** + */ + + //0 : RS1 + //1 : RS2 / CSR + + + assign o_rreg0 = {1'b0, i_rs1_raddr}; + assign o_rreg1 = + i_trap ? {4'b1000, CSR_MTVEC} : + i_mret ? {4'b1000, CSR_MEPC} : + i_csr_en ? {4'b1000, i_csr_addr} : + {1'b0,i_rs2_raddr}; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + assign o_csr = i_rdata1 & i_csr_en; + assign o_csr_pc = i_rdata1; + + end else begin + wire rd = (i_ctrl_rd ) | + (i_alu_rd & i_rd_alu_en) | + (i_mem_rd); + + assign o_wdata0 = rd; + assign o_wdata1 = 1'b0; + + assign o_wreg0 = i_rd_waddr; + assign o_wreg1 = 5'd0; + + assign o_wen0 =i_rd_wen; + assign o_wen1 = 1'b0; + + /* + ********** Read side *********** + */ + + assign o_rreg0 = i_rs1_raddr; + assign o_rreg1 = i_rs2_raddr; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + end // else: !if(WITH_CSR) + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..9bbc503d88e5f71471fc58603c0f87c1b127f092 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_ram.v @@ -0,0 +1,26 @@ +module serv_rf_ram + #(parameter width=0, + parameter csr_regs=4, + parameter depth=32*(32+csr_regs)/width) + (input wire i_clk, + input wire [$clog2(depth)-1:0] i_waddr, + input wire [width-1:0] i_wdata, + input wire i_wen, + input wire [$clog2(depth)-1:0] i_raddr, + output reg [width-1:0] o_rdata); + + reg [width-1:0] memory [0:depth-1]; + + always @(posedge i_clk) begin + if (i_wen) + memory[i_waddr] <= i_wdata; + o_rdata <= memory[i_raddr]; + end + +`ifdef SERV_CLEAR_RAM + integer i; + initial + for (i=0;i 2) + always @(posedge i_clk) wdata0_r <= {i_wdata0, wdata0_r[width-2:1]}; + else + always @(posedge i_clk) wdata0_r <= i_wdata0; + endgenerate + + always @(posedge i_clk) begin + wen0_r <= i_wen0; + wen1_r <= i_wen1; + wreq_r <= i_wreq | rgnt; + + wdata1_r <= {i_wdata1,wdata1_r[width-1:1]}; + + if (wgo) + wcnt <= wcnt+5'd1; + + if (wreq_r) begin + wgo <= 1'b1; + end + + if (wcnt == 5'b11111) + wgo <= 1'b0; + + if (i_rst) begin + wcnt <= 5'd0; + end + end + + /* + ********** Read side *********** + */ + + reg [4:0] rcnt; + + wire rtrig0; + reg rtrig1; + + wire [$clog2(32+csr_regs)-1:0] rreg = rtrig0 ? i_rreg1 : i_rreg0; + generate if (width == 32) + assign o_raddr = rreg; + else + assign o_raddr = {rreg, rcnt[4:l2w]}; + endgenerate + + reg [width-1:0] rdata0; + reg [width-2:0] rdata1; + + assign o_rdata0 = rdata0[0]; + assign o_rdata1 = rtrig1 ? i_rdata[0] : rdata1[0]; + + assign rtrig0 = (rcnt[l2w-1:0] == 1); + + reg rreq_r; + + generate if (width>2) + always @(posedge i_clk) begin + rdata1 <= {1'b0,rdata1[width-2:1]}; //Optimize? + if (rtrig1) + rdata1[width-2:0] <= i_rdata[width-1:1]; + end + else + always @(posedge i_clk) if (rtrig1) rdata1 <= i_rdata[1]; + endgenerate + + always @(posedge i_clk) begin + rtrig1 <= rtrig0; + rcnt <= rcnt+5'd1; + if (i_rreq) + rcnt <= 5'd0; + + rreq_r <= i_rreq; + rgnt <= rreq_r; + + rdata0 <= {1'b0,rdata0[width-1:1]}; + if (rtrig0) + rdata0 <= i_rdata; + + if (i_rst) begin + rgnt <= 1'b0; + rreq_r <= 1'b0; + end + end + + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_top.v new file mode 100644 index 0000000000000000000000000000000000000000..ef0ae413261884b55b6fefb4cf18ed5e35a4905b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_rf_top.v @@ -0,0 +1,164 @@ +`default_nettype none + +module serv_rf_top + #(parameter RESET_PC = 32'd0, + parameter WITH_CSR = 1, + parameter RF_WIDTH = 2, + parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH)) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output wire rvfi_valid, + output wire [63:0] rvfi_order, + output wire [31:0] rvfi_insn, + output wire rvfi_trap, + output wire rvfi_halt, + output wire rvfi_intr, + output wire [1:0] rvfi_mode, + output wire [1:0] rvfi_ixl, + output wire [4:0] rvfi_rs1_addr, + output wire [4:0] rvfi_rs2_addr, + output wire [31:0] rvfi_rs1_rdata, + output wire [31:0] rvfi_rs2_rdata, + output wire [4:0] rvfi_rd_addr, + output wire [31:0] rvfi_rd_wdata, + output wire [31:0] rvfi_pc_rdata, + output wire [31:0] rvfi_pc_wdata, + output wire [31:0] rvfi_mem_addr, + output wire [3:0] rvfi_mem_rmask, + output wire [3:0] rvfi_mem_wmask, + output wire [31:0] rvfi_mem_rdata, + output wire [31:0] rvfi_mem_wdata, +`endif + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + localparam CSR_REGS = WITH_CSR*4; + + wire rf_wreq; + wire rf_rreq; + wire [4+WITH_CSR:0] wreg0; + wire [4+WITH_CSR:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [4+WITH_CSR:0] rreg0; + wire [4+WITH_CSR:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + wire [RF_L2D-1:0] waddr; + wire [RF_WIDTH-1:0] wdata; + wire wen; + wire [RF_L2D-1:0] raddr; + wire [RF_WIDTH-1:0] rdata; + + serv_rf_ram_if + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram_if + (.i_clk (clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_rf_ram + #(.width (RF_WIDTH), + .csr_regs (CSR_REGS)) + rf_ram + (.i_clk (clk), + .i_waddr (waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (raddr), + .o_rdata (rdata)); + + serv_top + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_mode (rvfi_mode ), + .rvfi_ixl (rvfi_ixl ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata (rvfi_rs1_rdata), + .rvfi_rs2_rdata (rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask (rvfi_mem_rmask), + .rvfi_mem_wmask (rvfi_mem_wmask), + .rvfi_mem_rdata (rvfi_mem_rdata), + .rvfi_mem_wdata (rvfi_mem_wdata), +`endif + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_rdt (i_ibus_rdt), + .i_ibus_ack (i_ibus_ack), + + .o_dbus_adr (o_dbus_adr), + .o_dbus_dat (o_dbus_dat), + .o_dbus_sel (o_dbus_sel), + .o_dbus_we (o_dbus_we), + .o_dbus_cyc (o_dbus_cyc), + .i_dbus_rdt (i_dbus_rdt), + .i_dbus_ack (i_dbus_ack)); + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_shift.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_shift.v new file mode 100644 index 0000000000000000000000000000000000000000..70a80db813e0564f80df71c676ba266cf6055d90 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_shift.v @@ -0,0 +1,30 @@ +`default_nettype none +module serv_shift + ( + input wire i_clk, + input wire i_load, + input wire [4:0] i_shamt, + input wire i_shamt_msb, + input wire i_signbit, + input wire i_right, + output wire o_done, + input wire i_d, + output wire o_q); + + reg signbit; + reg [5:0] cnt; + reg wrapped; + + always @(posedge i_clk) begin + cnt <= cnt + 6'd1; + if (i_load) begin + cnt <= 6'd0; + signbit <= i_signbit & i_right; + end + wrapped <= cnt[5] | (i_shamt_msb & !i_right); + end + + assign o_done = (cnt[4:0] == i_shamt); + assign o_q = (i_right^wrapped) ? i_d : signbit; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_state.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_state.v new file mode 100644 index 0000000000000000000000000000000000000000..b919264f8899a6a4b9c93d9ad6bb43c149f6faa6 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_state.v @@ -0,0 +1,153 @@ +module serv_state + ( + input wire i_clk, + input wire i_rst, + input wire i_new_irq, + output wire o_trap_taken, + output reg o_pending_irq, + input wire i_dbus_ack, + input wire i_ibus_ack, + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire o_rf_rd_en, + input wire i_take_branch, + input wire i_branch_op, + input wire i_mem_op, + input wire i_shift_op, + input wire i_slt_op, + input wire i_e_op, + input wire i_rd_op, + output reg o_init, + output reg o_cnt_en, + output wire o_cnt0, + output wire o_cnt0to3, + output wire o_cnt12to31, + output wire o_cnt1, + output wire o_cnt2, + output wire o_cnt3, + output wire o_cnt7, + output wire o_ctrl_pc_en, + output reg o_ctrl_jump, + output wire o_ctrl_trap, + input wire i_ctrl_misalign, + output wire o_alu_shamt_en, + input wire i_alu_sh_done, + output wire o_dbus_cyc, + output wire [1:0] o_mem_bytecnt, + input wire i_mem_misalign, + output reg o_cnt_done, + output wire o_bufreg_hold); + + parameter WITH_CSR = 1; + + wire cnt4; + + reg stage_two_req; + + reg [4:2] o_cnt; + reg [3:0] o_cnt_r; + + //Update PC in RUN or TRAP states + assign o_ctrl_pc_en = o_cnt_en & !o_init; + + + assign o_mem_bytecnt = o_cnt[4:3]; + + assign o_cnt0to3 = (o_cnt[4:2] == 3'd0); + assign o_cnt12to31 = (o_cnt[4] | (o_cnt[3:2] == 2'b11)); + assign o_cnt0 = (o_cnt[4:2] == 3'd0) & o_cnt_r[0]; + assign o_cnt1 = (o_cnt[4:2] == 3'd0) & o_cnt_r[1]; + assign o_cnt2 = (o_cnt[4:2] == 3'd0) & o_cnt_r[2]; + assign o_cnt3 = (o_cnt[4:2] == 3'd0) & o_cnt_r[3]; + assign cnt4 = (o_cnt[4:2] == 3'd1) & o_cnt_r[0]; + assign o_cnt7 = (o_cnt[4:2] == 3'd1) & o_cnt_r[3]; + + assign o_alu_shamt_en = (o_cnt0to3 | cnt4) & o_init; + + + //slt*, branch/jump, shift, load/store + wire two_stage_op = i_slt_op | i_mem_op | i_branch_op | i_shift_op; + + reg stage_two_pending; + + assign o_dbus_cyc = !o_cnt_en & stage_two_pending & i_mem_op & !i_mem_misalign; + + wire trap_pending = WITH_CSR & ((o_ctrl_jump & i_ctrl_misalign) | i_mem_misalign); + + //Prepare RF for reads when a new instruction is fetched + // or when stage one caused an exception (rreq implies a write request too) + assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending); + + //Prepare RF for writes when everything is ready to enter stage two + assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending; + + assign o_rf_rd_en = i_rd_op & o_cnt_en & !o_init; + + //Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting + assign o_bufreg_hold = !o_cnt_en & (stage_two_req | ~i_shift_op); + + always @(posedge i_clk) begin + if (o_cnt_done) + o_ctrl_jump <= o_init & i_take_branch; + + if (o_cnt_en) + stage_two_pending <= o_init; + + o_cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2]; + + //Need a strobe for the first cycle in the IDLE state after INIT + stage_two_req <= o_cnt_done & o_init; + + if (i_rf_ready & !stage_two_pending) + o_init <= two_stage_op & !o_pending_irq; + + if (o_cnt_done) + o_init <= 1'b0; + + if (i_rf_ready) + o_cnt_en <= 1'b1; + + if (o_cnt_done) + o_cnt_en <= 1'b0; + + o_cnt <= o_cnt + {2'd0,o_cnt_r[3]}; + if (o_cnt_en) + o_cnt_r <= {o_cnt_r[2:0],o_cnt_r[3]}; + + if (i_rst) begin + o_cnt <= 3'd0; + stage_two_pending <= 1'b0; + o_ctrl_jump <= 1'b0; + o_cnt_r <= 4'b0001; + end + end + + generate + if (WITH_CSR) begin + reg irq_sync; + reg misalign_trap_sync; + + assign o_ctrl_trap = i_e_op | o_pending_irq | misalign_trap_sync; + assign o_trap_taken = i_ibus_ack & o_ctrl_trap; + + always @(posedge i_clk) begin + if (i_ibus_ack) + irq_sync <= 1'b0; + if (i_new_irq) + irq_sync <= 1'b1; + + if (i_ibus_ack) + o_pending_irq <= irq_sync; + + if (stage_two_req) + misalign_trap_sync <= trap_pending; + if (i_ibus_ack) + misalign_trap_sync <= 1'b0; + end // always @ (posedge i_clk) + end else begin + always @(*) + o_pending_irq = 1'b0; + end + endgenerate +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_top.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_top.v new file mode 100644 index 0000000000000000000000000000000000000000..65b59b05bc9f9da4d8f99551ebb5fee73f9b5f26 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serv_1.0.2/rtl/serv_top.v @@ -0,0 +1,495 @@ +`default_nettype none + +module serv_top + #(parameter WITH_CSR = 1, + parameter RESET_PC = 32'd0) + ( + input wire clk, + input wire i_rst, + input wire i_timer_irq, +`ifdef RISCV_FORMAL + output reg rvfi_valid = 1'b0, + output reg [63:0] rvfi_order = 64'd0, + output reg [31:0] rvfi_insn = 32'd0, + output reg rvfi_trap = 1'b0, + output reg rvfi_halt = 1'b0, + output reg rvfi_intr = 1'b0, + output reg [1:0] rvfi_mode = 2'b11, + output reg [1:0] rvfi_ixl = 2'b01, + output reg [4:0] rvfi_rs1_addr, + output reg [4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [3:0] rvfi_mem_rmask, + output reg [3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, +`endif + //RF Interface + output wire o_rf_rreq, + output wire o_rf_wreq, + input wire i_rf_ready, + output wire [4+WITH_CSR:0] o_wreg0, + output wire [4+WITH_CSR:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [4+WITH_CSR:0] o_rreg0, + output wire [4+WITH_CSR:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + output wire [31:0] o_ibus_adr, + output wire o_ibus_cyc, + input wire [31:0] i_ibus_rdt, + input wire i_ibus_ack, + output wire [31:0] o_dbus_adr, + output wire [31:0] o_dbus_dat, + output wire [3:0] o_dbus_sel, + output wire o_dbus_we , + output wire o_dbus_cyc, + input wire [31:0] i_dbus_rdt, + input wire i_dbus_ack); + + wire [4:0] rd_addr; + wire [4:0] rs1_addr; + wire [4:0] rs2_addr; + + wire take_branch; + wire e_op; + wire ebreak; + wire branch_op; + wire mem_op; + wire shift_op; + wire slt_op; + wire rd_op; + + wire rd_alu_en; + wire rd_csr_en; + wire ctrl_rd; + wire alu_rd; + wire mem_rd; + wire csr_rd; + + wire ctrl_pc_en; + wire jump; + wire jal_or_jalr; + wire utype; + wire mret; + wire imm; + wire trap; + wire pc_rel; + + wire init; + wire cnt_en; + wire cnt0to3; + wire cnt12to31; + wire cnt0; + wire cnt1; + wire cnt2; + wire cnt3; + wire cnt7; + + wire cnt_done; + + wire bufreg_hold; + wire bufreg_rs1_en; + wire bufreg_imm_en; + wire bufreg_loop; + wire bufreg_q; + + wire alu_sub; + wire [1:0] alu_bool_op; + wire alu_cmp_eq; + wire alu_cmp_uns; + wire alu_cmp; + wire alu_shamt_en; + wire alu_sh_signed; + wire alu_sh_right; + wire alu_sh_done; + wire [3:0] alu_rd_sel; + + wire rs1; + wire rs2; + wire rd_en; + + wire op_b_source; + wire op_b; + + wire mem_signed; + wire mem_word; + wire mem_half; + wire [1:0] mem_bytecnt; + + wire mem_misalign; + + wire bad_pc; + + wire csr_mstatus_en; + wire csr_mie_en; + wire csr_mcause_en; + wire [1:0] csr_source; + wire csr_imm; + wire csr_d_sel; + wire csr_en; + wire [1:0] csr_addr; + wire csr_pc; + + + wire new_irq; + wire trap_taken; + wire pending_irq; + + wire [1:0] lsb; + + serv_state + #(.WITH_CSR (WITH_CSR)) + state + ( + .i_clk (clk), + .i_rst (i_rst), + .i_new_irq (new_irq), + .o_trap_taken (trap_taken), + .o_pending_irq (pending_irq), + .i_dbus_ack (i_dbus_ack), + .i_ibus_ack (i_ibus_ack), + .o_rf_rreq (o_rf_rreq), + .o_rf_wreq (o_rf_wreq), + .i_rf_ready (i_rf_ready), + .o_rf_rd_en (rd_en), + .i_take_branch (take_branch), + .i_branch_op (branch_op), + .i_mem_op (mem_op), + .i_shift_op (shift_op), + .i_slt_op (slt_op), + .i_e_op (e_op), + .i_rd_op (rd_op), + .o_init (init), + .o_cnt_en (cnt_en), + .o_cnt0to3 (cnt0to3), + .o_cnt12to31 (cnt12to31), + .o_cnt0 (cnt0), + .o_cnt1 (cnt1), + .o_cnt2 (cnt2), + .o_cnt3 (cnt3), + .o_cnt7 (cnt7), + .o_cnt_done (cnt_done), + .o_bufreg_hold (bufreg_hold), + .o_ctrl_pc_en (ctrl_pc_en), + .o_ctrl_jump (jump), + .o_ctrl_trap (trap), + .i_ctrl_misalign(lsb[1]), + .o_alu_shamt_en (alu_shamt_en), + .i_alu_sh_done (alu_sh_done), + .o_dbus_cyc (o_dbus_cyc), + .o_mem_bytecnt (mem_bytecnt), + .i_mem_misalign (mem_misalign)); + + wire bufreg_clr_lsb; + + serv_decode decode + ( + .clk (clk), + //Input + .i_cnt_en (cnt_en), + .i_cnt_done (cnt_done), + .i_wb_rdt (i_ibus_rdt[31:2]), + .i_wb_en (o_ibus_cyc & i_ibus_ack), + .i_alu_cmp (alu_cmp), + //To state + .o_take_branch (take_branch), + .o_e_op (e_op), + .o_ebreak (ebreak), + .o_branch_op (branch_op), + .o_mem_op (mem_op), + .o_shift_op (shift_op), + .o_slt_op (slt_op), + .o_rd_op (rd_op), + //To bufreg + .o_bufreg_loop (bufreg_loop), + .o_bufreg_rs1_en (bufreg_rs1_en), + .o_bufreg_imm_en (bufreg_imm_en), + .o_bufreg_clr_lsb (bufreg_clr_lsb), + //To ctrl + .o_ctrl_jal_or_jalr (jal_or_jalr), + .o_ctrl_utype (utype), + .o_ctrl_pc_rel (pc_rel), + .o_ctrl_mret (mret), + //To alu + .o_op_b_source (op_b_source), + .o_alu_sub (alu_sub), + .o_alu_bool_op (alu_bool_op), + .o_alu_cmp_eq (alu_cmp_eq), + .o_alu_cmp_uns (alu_cmp_uns), + .o_alu_sh_signed (alu_sh_signed), + .o_alu_sh_right (alu_sh_right), + .o_alu_rd_sel (alu_rd_sel), + //To RF + .o_rf_rd_addr (rd_addr), + .o_rf_rs1_addr (rs1_addr), + .o_rf_rs2_addr (rs2_addr), + //To mem IF + .o_mem_cmd (o_dbus_we), + .o_mem_signed (mem_signed), + .o_mem_word (mem_word), + .o_mem_half (mem_half), + //To CSR + .o_csr_en (csr_en), + .o_csr_addr (csr_addr), + .o_csr_mstatus_en (csr_mstatus_en), + .o_csr_mie_en (csr_mie_en), + .o_csr_mcause_en (csr_mcause_en), + .o_csr_source (csr_source), + .o_csr_d_sel (csr_d_sel), + .o_csr_imm (csr_imm), + //To top + .o_imm (imm), + .o_rd_csr_en (rd_csr_en), + .o_rd_alu_en (rd_alu_en)); + + serv_bufreg bufreg + ( + .i_clk (clk), + .i_cnt0 (cnt0), + .i_cnt1 (cnt1), + .i_en (!bufreg_hold), + .i_init (init), + .i_loop (bufreg_loop), + .i_rs1 (rs1), + .i_rs1_en (bufreg_rs1_en), + .i_imm (imm), + .i_imm_en (bufreg_imm_en), + .i_clr_lsb (bufreg_clr_lsb), + .o_lsb (lsb), + .o_dbus_adr (o_dbus_adr), + .o_q (bufreg_q)); + + serv_ctrl + #(.RESET_PC (RESET_PC), + .WITH_CSR (WITH_CSR)) + ctrl + ( + .clk (clk), + .i_rst (i_rst), + //State + .i_pc_en (ctrl_pc_en), + .i_cnt12to31 (cnt12to31), + .i_cnt2 (cnt2), + .i_cnt_done (cnt_done), + //Control + .i_jump (jump), + .i_jal_or_jalr (jal_or_jalr), + .i_utype (utype), + .i_pc_rel (pc_rel), + .i_trap (trap | mret), + //Data + .i_imm (imm), + .i_buf (bufreg_q), + .i_csr_pc (csr_pc), + .o_rd (ctrl_rd), + .o_bad_pc (bad_pc), + //External + .o_ibus_adr (o_ibus_adr), + .o_ibus_cyc (o_ibus_cyc), + .i_ibus_ack (i_ibus_ack)); + + + serv_alu alu + ( + .clk (clk), + .i_rst (i_rst), + .i_en (cnt_en), + .i_cnt0 (cnt0), + .i_rs1 (rs1), + .i_rs2 (rs2), + .i_imm (imm), + .i_op_b_rs2 (op_b_source), + .i_buf (bufreg_q), + .i_init (init), + .i_cnt_done (cnt_done), + .i_sub (alu_sub), + .i_bool_op (alu_bool_op), + .i_cmp_eq (alu_cmp_eq), + .i_cmp_uns (alu_cmp_uns), + .o_cmp (alu_cmp), + .i_shamt_en (alu_shamt_en), + .i_sh_right (alu_sh_right), + .i_sh_signed (alu_sh_signed), + .o_sh_done (alu_sh_done), + .i_rd_sel (alu_rd_sel), + .o_rd (alu_rd)); + + wire csr_in; + wire rf_csr_out; + + serv_rf_if + #(.WITH_CSR (WITH_CSR)) + rf_if + (//RF interface + .o_wreg0 (o_wreg0), + .o_wreg1 (o_wreg1), + .o_wen0 (o_wen0), + .o_wen1 (o_wen1), + .o_wdata0 (o_wdata0), + .o_wdata1 (o_wdata1), + .o_rreg0 (o_rreg0), + .o_rreg1 (o_rreg1), + .i_rdata0 (i_rdata0), + .i_rdata1 (i_rdata1), + + //Trap interface + .i_trap (trap), + .i_mret (mret), + .i_mepc (o_ibus_adr[0]), + .i_mem_misalign (mem_misalign), + .i_bufreg_q (bufreg_q), + .i_bad_pc (bad_pc), + .o_csr_pc (csr_pc), + //CSR write port + .i_csr_en (csr_en), + .i_csr_addr (csr_addr), + .i_csr (csr_in), + //RD write port + .i_rd_wen (rd_en), + .i_rd_waddr (rd_addr), + .i_ctrl_rd (ctrl_rd), + .i_alu_rd (alu_rd), + .i_rd_alu_en (rd_alu_en), + .i_csr_rd (csr_rd), + .i_rd_csr_en (rd_csr_en), + .i_mem_rd (mem_rd), + + //RS1 read port + .i_rs1_raddr (rs1_addr), + .o_rs1 (rs1), + //RS2 read port + .i_rs2_raddr (rs2_addr), + .o_rs2 (rs2), + + //CSR read port + .o_csr (rf_csr_out)); + + serv_mem_if + #(.WITH_CSR (WITH_CSR)) + mem_if + ( + .i_clk (clk), + .i_en (cnt_en), + .i_mem_op (mem_op), + .i_signed (mem_signed), + .i_word (mem_word), + .i_half (mem_half), + .i_bytecnt (mem_bytecnt), + .i_rs2 (rs2), + .o_rd (mem_rd), + .i_lsb (lsb), + .o_misalign (mem_misalign), + //External interface + .o_wb_dat (o_dbus_dat), + .o_wb_sel (o_dbus_sel), + .i_wb_rdt (i_dbus_rdt), + .i_wb_ack (i_dbus_ack)); + + generate + if (WITH_CSR) begin + serv_csr csr + ( + .i_clk (clk), + .i_en (cnt_en), + .i_cnt0to3 (cnt0to3), + .i_cnt2 (cnt2), + .i_cnt3 (cnt3), + .i_cnt7 (cnt7), + .i_cnt_done (cnt_done), + .i_e_op (e_op), + .i_ebreak (ebreak), + .i_mem_cmd (o_dbus_we), + .i_mem_misalign (mem_misalign), + .i_rf_csr_out (rf_csr_out), + .o_csr_in (csr_in), + .i_mtip (i_timer_irq), + .o_new_irq (new_irq), + .i_trap_taken (trap_taken), + .i_pending_irq (pending_irq), + .i_mstatus_en (csr_mstatus_en), + .i_mie_en (csr_mie_en ), + .i_mcause_en (csr_mcause_en ), + .i_csr_source (csr_source), + .i_mret (mret), + .i_d (csr_d_sel ? csr_imm : rs1), + .o_q (csr_rd)); + end else begin + assign csr_in = 1'b0; + assign csr_rd = 1'b0; + assign new_irq = 1'b0; + end + endgenerate + + +`ifdef RISCV_FORMAL + reg [31:0] pc = RESET_PC; + + wire rs_en = (branch_op|mem_op|shift_op|slt_op) ? init : ctrl_pc_en; + + always @(posedge clk) begin + rvfi_valid <= cnt_done & ctrl_pc_en & !i_rst; + rvfi_order <= rvfi_order + {63'd0,rvfi_valid}; + if (o_ibus_cyc & i_ibus_ack) + rvfi_insn <= i_ibus_rdt; + if (o_wen0) + rvfi_rd_wdata <= {o_wdata0,rvfi_rd_wdata[31:1]}; + if (cnt_done & ctrl_pc_en) begin + rvfi_pc_rdata <= pc; + if (!rd_en) + rvfi_rd_addr <= 5'd0; + if (!rd_en | !(|rd_addr)) + rvfi_rd_wdata <= 32'd0; + end + rvfi_trap <= trap; + if (rvfi_valid) begin + rvfi_trap <= 1'b0; + pc <= rvfi_pc_wdata; + end + + rvfi_halt <= 1'b0; + rvfi_intr <= 1'b0; + rvfi_mode <= 2'd3; + rvfi_ixl = 2'd1; + if (i_rf_ready) begin + rvfi_rs1_addr <= rs1_addr; + rvfi_rs2_addr <= rs2_addr; + rvfi_rd_addr <= rd_addr; + end + if (rs_en) begin + rvfi_rs1_rdata <= {rs1,rvfi_rs1_rdata[31:1]}; + rvfi_rs2_rdata <= {rs2,rvfi_rs2_rdata[31:1]}; + end + + if (i_dbus_ack) begin + rvfi_mem_addr <= o_dbus_adr; + rvfi_mem_rmask <= o_dbus_we ? 4'b0000 : o_dbus_sel; + rvfi_mem_wmask <= o_dbus_we ? o_dbus_sel : 4'b0000; + rvfi_mem_rdata <= i_dbus_rdt; + rvfi_mem_wdata <= o_dbus_dat; + end + if (i_ibus_ack) begin + rvfi_mem_rmask <= 4'b0000; + rvfi_mem_wmask <= 4'b0000; + end + end + /* verilator lint_off COMBDLY */ + always @(o_ibus_adr) + rvfi_pc_wdata <= o_ibus_adr; + /* verilator lint_on COMBDLY */ + + +`endif + +endmodule +`default_nettype wire diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving.v new file mode 100644 index 0000000000000000000000000000000000000000..374bab40a12ffd914db04336c0c9a3516b30b556 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving.v @@ -0,0 +1,232 @@ +/* serving.v : Top-level for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving + ( + input wire i_clk, + input wire i_rst, + input wire i_timer_irq, + + output wire [31:0] o_wb_adr, + output wire [31:0] o_wb_dat, + output wire [3:0] o_wb_sel, + output wire o_wb_we , + output wire o_wb_stb, + input wire [31:0] i_wb_rdt, + input wire i_wb_ack); + + parameter memfile = ""; + parameter memsize = 8192; + parameter WITH_CSR = 1; + localparam regs = 32+WITH_CSR*4; + + localparam rf_width = 8; + + localparam aw = $clog2(memsize); + + wire [31:0] wb_ibus_adr; + wire wb_ibus_stb; + wire [31:0] wb_ibus_rdt; + wire wb_ibus_ack; + + wire [31:0] wb_dbus_adr; + wire [31:0] wb_dbus_dat; + wire [3:0] wb_dbus_sel; + wire wb_dbus_we; + wire wb_dbus_stb; + wire [31:0] wb_dbus_rdt; + wire wb_dbus_ack; + + wire [31:0] wb_dmem_adr; + wire [31:0] wb_dmem_dat; + wire [3:0] wb_dmem_sel; + wire wb_dmem_we; + wire wb_dmem_stb; + wire [31:0] wb_dmem_rdt; + wire wb_dmem_ack; + + wire [31:0] wb_mem_adr; + wire [31:0] wb_mem_dat; + wire [3:0] wb_mem_sel; + wire wb_mem_we; + wire wb_mem_stb; + wire [31:0] wb_mem_rdt; + wire wb_mem_ack; + + wire [6+WITH_CSR:0] waddr; + wire [rf_width-1:0] wdata; + wire wen; + wire [6+WITH_CSR:0] raddr; + wire [rf_width-1:0] rdata; + + + wire [aw-1:0] rf_waddr = ~{{aw-2-5-WITH_CSR{1'b0}},waddr}; + wire [aw-1:0] rf_raddr = ~{{aw-2-5-WITH_CSR{1'b0}},raddr}; + + serving_arbiter arbiter + (.i_wb_cpu_dbus_adr (wb_dmem_adr), + .i_wb_cpu_dbus_dat (wb_dmem_dat), + .i_wb_cpu_dbus_sel (wb_dmem_sel), + .i_wb_cpu_dbus_we (wb_dmem_we ), + .i_wb_cpu_dbus_stb (wb_dmem_stb), + .o_wb_cpu_dbus_rdt (wb_dmem_rdt), + .o_wb_cpu_dbus_ack (wb_dmem_ack), + + .i_wb_cpu_ibus_adr (wb_ibus_adr), + .i_wb_cpu_ibus_stb (wb_ibus_stb), + .o_wb_cpu_ibus_rdt (wb_ibus_rdt), + .o_wb_cpu_ibus_ack (wb_ibus_ack), + + .o_wb_mem_adr (wb_mem_adr), + .o_wb_mem_dat (wb_mem_dat), + .o_wb_mem_sel (wb_mem_sel), + .o_wb_mem_we (wb_mem_we ), + .o_wb_mem_stb (wb_mem_stb), + .i_wb_mem_rdt (wb_mem_rdt), + .i_wb_mem_ack (wb_mem_ack)); + + serving_mux mux + (.i_clk (i_clk), + .i_rst (i_rst), + + .i_wb_cpu_adr (wb_dbus_adr), + .i_wb_cpu_dat (wb_dbus_dat), + .i_wb_cpu_sel (wb_dbus_sel), + .i_wb_cpu_we (wb_dbus_we), + .i_wb_cpu_stb (wb_dbus_stb), + .o_wb_cpu_rdt (wb_dbus_rdt), + .o_wb_cpu_ack (wb_dbus_ack), + + .o_wb_mem_adr (wb_dmem_adr), + .o_wb_mem_dat (wb_dmem_dat), + .o_wb_mem_sel (wb_dmem_sel), + .o_wb_mem_we (wb_dmem_we), + .o_wb_mem_stb (wb_dmem_stb), + .i_wb_mem_rdt (wb_dmem_rdt), + .i_wb_mem_ack (wb_dmem_ack), + + .o_wb_ext_adr (o_wb_adr), + .o_wb_ext_dat (o_wb_dat), + .o_wb_ext_sel (o_wb_sel), + .o_wb_ext_we (o_wb_we), + .o_wb_ext_stb (o_wb_stb), + .i_wb_ext_rdt (i_wb_rdt), + .i_wb_ext_ack (i_wb_ack)); + + serving_ram + #(.memfile (memfile), + .depth (memsize)) + ram + (// Wishbone interface + .i_clk (i_clk), + .i_waddr (rf_waddr), + .i_wdata (wdata), + .i_wen (wen), + .i_raddr (rf_raddr), + .o_rdata (rdata), + .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]), + .i_wb_stb (wb_mem_stb), + .i_wb_we (wb_mem_we) , + .i_wb_sel (wb_mem_sel), + .i_wb_dat (wb_mem_dat), + .o_wb_rdt (wb_mem_rdt), + .o_wb_ack (wb_mem_ack)); + + localparam RF_L2W = $clog2(rf_width); + + wire rf_wreq; + wire rf_rreq; + wire [$clog2(regs)-1:0] wreg0; + wire [$clog2(regs)-1:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [$clog2(regs)-1:0] rreg0; + wire [$clog2(regs)-1:0] rreg1; + wire rf_ready; + wire rdata0; + wire rdata1; + + + serv_rf_ram_if + #(.width (rf_width), + .csr_regs (WITH_CSR*4)) + rf_ram_if + (.i_clk (i_clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_ready (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1), + .o_waddr (waddr), + .o_wdata (wdata), + .o_wen (wen), + .o_raddr (raddr), + .i_rdata (rdata)); + + serv_top + #(.RESET_PC (32'h0000_0000), + .WITH_CSR (WITH_CSR)) + cpu + ( + .clk (i_clk), + .i_rst (i_rst), + .i_timer_irq (i_timer_irq), + //RF IF + .o_rf_rreq (rf_rreq), + .o_rf_wreq (rf_wreq), + .i_rf_ready (rf_ready), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + + //Instruction bus + .o_ibus_adr (wb_ibus_adr), + .o_ibus_cyc (wb_ibus_stb), + .i_ibus_rdt (wb_ibus_rdt), + .i_ibus_ack (wb_ibus_ack), + + //Data bus + .o_dbus_adr (wb_dbus_adr), + .o_dbus_dat (wb_dbus_dat), + .o_dbus_sel (wb_dbus_sel), + .o_dbus_we (wb_dbus_we), + .o_dbus_cyc (wb_dbus_stb), + .i_dbus_rdt (wb_dbus_rdt), + .i_dbus_ack (wb_dbus_ack)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_arbiter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..9d537d4a46297b5f8902f134ada0dcba4a8cae2d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_arbiter.v @@ -0,0 +1,57 @@ +/* serving_arbiter.v : I/D arbiter for the serving SoC + * Relies on the fact that not both masters are active at the same time + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_arbiter + ( + input wire [31:0] i_wb_cpu_dbus_adr, + input wire [31:0] i_wb_cpu_dbus_dat, + input wire [3:0] i_wb_cpu_dbus_sel, + input wire i_wb_cpu_dbus_we, + input wire i_wb_cpu_dbus_stb, + output wire [31:0] o_wb_cpu_dbus_rdt, + output wire o_wb_cpu_dbus_ack, + + input wire [31:0] i_wb_cpu_ibus_adr, + input wire i_wb_cpu_ibus_stb, + output wire [31:0] o_wb_cpu_ibus_rdt, + output wire o_wb_cpu_ibus_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack); + + assign o_wb_cpu_dbus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_dbus_ack = i_wb_mem_ack & !i_wb_cpu_ibus_stb; + + assign o_wb_cpu_ibus_rdt = i_wb_mem_rdt; + assign o_wb_cpu_ibus_ack = i_wb_mem_ack & i_wb_cpu_ibus_stb; + + assign o_wb_mem_adr = i_wb_cpu_ibus_stb ? i_wb_cpu_ibus_adr : i_wb_cpu_dbus_adr; + assign o_wb_mem_dat = i_wb_cpu_dbus_dat; + assign o_wb_mem_sel = i_wb_cpu_dbus_sel; + assign o_wb_mem_we = i_wb_cpu_dbus_we & !i_wb_cpu_ibus_stb; + assign o_wb_mem_stb = i_wb_cpu_ibus_stb | i_wb_cpu_dbus_stb; + + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..daa1be8e3a714496eb611905cd1070f3f4610548 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_mux.v @@ -0,0 +1,66 @@ +/* serving_mux.v : Simple Wishbone mux for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +module serving_mux + ( + input wire i_clk, + input wire i_rst, + + input wire [31:0] i_wb_cpu_adr, + input wire [31:0] i_wb_cpu_dat, + input wire [3:0] i_wb_cpu_sel, + input wire i_wb_cpu_we, + input wire i_wb_cpu_stb, + output wire [31:0] o_wb_cpu_rdt, + output wire o_wb_cpu_ack, + + output wire [31:0] o_wb_mem_adr, + output wire [31:0] o_wb_mem_dat, + output wire [3:0] o_wb_mem_sel, + output wire o_wb_mem_we, + output wire o_wb_mem_stb, + input wire [31:0] i_wb_mem_rdt, + input wire i_wb_mem_ack, + + output wire [31:0] o_wb_ext_adr, + output wire [31:0] o_wb_ext_dat, + output wire [3:0] o_wb_ext_sel, + output wire o_wb_ext_we, + output wire o_wb_ext_stb, + input wire [31:0] i_wb_ext_rdt, + input wire i_wb_ext_ack); + + wire ext = (i_wb_cpu_adr[31:30] != 2'b00); + + assign o_wb_cpu_rdt = ext ? i_wb_ext_rdt : i_wb_mem_rdt; + assign o_wb_cpu_ack = ext ? i_wb_ext_ack : i_wb_mem_ack; + + assign o_wb_mem_adr = i_wb_cpu_adr; + assign o_wb_mem_dat = i_wb_cpu_dat; + assign o_wb_mem_sel = i_wb_cpu_sel; + assign o_wb_mem_we = i_wb_cpu_we; + assign o_wb_mem_stb = i_wb_cpu_stb & !ext; + + assign o_wb_ext_adr = i_wb_cpu_adr; + assign o_wb_ext_dat = i_wb_cpu_dat; + assign o_wb_ext_sel = i_wb_cpu_sel; + assign o_wb_ext_we = i_wb_cpu_we; + assign o_wb_ext_stb = i_wb_cpu_stb & ext; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_ram.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_ram.v new file mode 100644 index 0000000000000000000000000000000000000000..38585fdcf09c927663897005d59757a246bbb9c9 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/serving_1.0.2/serving/serving_ram.v @@ -0,0 +1,83 @@ +/* serving_ram.v : Shared RF I/D SRAM for the serving SoC + * + * ISC License + * + * Copyright (C) 2020 Olof Kindgren + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +`default_nettype none +module serving_ram + #(//Memory parameters + parameter depth = 256, + parameter aw = $clog2(depth), + parameter memfile = "") + (input wire i_clk, + input wire [aw-1:0] i_waddr, + input wire [7:0] i_wdata, + input wire i_wen, + input wire [aw-1:0] i_raddr, + output wire [7:0] o_rdata, + + input wire [aw-1:2] i_wb_adr, + input wire [31:0] i_wb_dat, + input wire [3:0] i_wb_sel, + input wire i_wb_we, + input wire i_wb_stb, + output wire [31:0] o_wb_rdt, + output reg o_wb_ack); + + wire wb_en = i_wb_stb & !i_wen & !o_wb_ack; + + wire wb_we = i_wb_we & i_wb_sel[bsel]; + + wire we = wb_en ? wb_we : i_wen; + + reg [7:0] mem [0:depth-1] /* verilator public */; + + wire [aw-1:0] waddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_waddr; + wire [7:0] wdata = wb_en ? i_wb_dat[bsel*8+:8] : i_wdata; + wire [aw-1:0] raddr = wb_en ? {i_wb_adr[aw-1:2],bsel} : i_raddr; + + reg [2:0] wb_en_r; + + reg [1:0] bsel; + + reg [23:0] wb_rdt; + assign o_wb_rdt = {rdata, wb_rdt}; + + always @(posedge i_clk) begin + if (wb_en) bsel <= bsel + 2'd1; + wb_en_r <= {wb_en_r[1:0], wb_en}; + o_wb_ack <= wb_en & &bsel; + if (bsel == 2'b01) wb_rdt[7:0] <= rdata; + if (bsel == 2'b10) wb_rdt[15:8] <= rdata; + if (bsel == 2'b11) wb_rdt[23:16] <= rdata; + end + + reg [7:0] rdata; + + always @(posedge i_clk) begin + if (we) mem[waddr] <= wdata; + rdata <= mem[raddr]; + end + + initial + if(|memfile) begin + //$display("Preloading %m from %s", memfile); + $readmemh(memfile, mem); + end + + assign o_rdata = rdata; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/arbiter.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..3612fc45948a4e436e9d4333f8edc8ab4af79c75 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/arbiter.v @@ -0,0 +1,153 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Arbiter module + */ +module arbiter # +( + parameter PORTS = 4, + // arbitration type: "PRIORITY" or "ROUND_ROBIN" + parameter TYPE = "PRIORITY", + // block type: "NONE", "REQUEST", "ACKNOWLEDGE" + parameter BLOCK = "NONE", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" +) +( + input wire clk, + input wire rst, + + input wire [PORTS-1:0] request, + input wire [PORTS-1:0] acknowledge, + + output wire [PORTS-1:0] grant, + output wire grant_valid, + output wire [$clog2(PORTS)-1:0] grant_encoded +); + +reg [PORTS-1:0] grant_reg = 0, grant_next; +reg grant_valid_reg = 0, grant_valid_next; +reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next; + +assign grant_valid = grant_valid_reg; +assign grant = grant_reg; +assign grant_encoded = grant_encoded_reg; + +wire request_valid; +wire [$clog2(PORTS)-1:0] request_index; +wire [PORTS-1:0] request_mask; + +priority_encoder #( + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) +) +priority_encoder_inst ( + .input_unencoded(request), + .output_valid(request_valid), + .output_encoded(request_index), + .output_unencoded(request_mask) +); + +reg [PORTS-1:0] mask_reg = 0, mask_next; + +wire masked_request_valid; +wire [$clog2(PORTS)-1:0] masked_request_index; +wire [PORTS-1:0] masked_request_mask; + +priority_encoder #( + .WIDTH(PORTS), + .LSB_PRIORITY(LSB_PRIORITY) +) +priority_encoder_masked ( + .input_unencoded(request & mask_reg), + .output_valid(masked_request_valid), + .output_encoded(masked_request_index), + .output_unencoded(masked_request_mask) +); + +always @* begin + grant_next = 0; + grant_valid_next = 0; + grant_encoded_next = 0; + mask_next = mask_reg; + + if (BLOCK == "REQUEST" && |(grant_reg & request)) begin + // granted request still asserted; hold it + grant_valid_next = grant_valid_reg; + grant_next = grant_reg; + grant_encoded_next = grant_encoded_reg; + end else if (BLOCK == "ACKNOWLEDGE" && grant_valid && !(|(grant_reg & acknowledge))) begin + // granted request not yet acknowledged; hold it + grant_valid_next = grant_valid_reg; + grant_next = grant_reg; + grant_encoded_next = grant_encoded_reg; + end else if (request_valid) begin + if (TYPE == "PRIORITY") begin + grant_valid_next = 1; + grant_next = request_mask; + grant_encoded_next = request_index; + end else if (TYPE == "ROUND_ROBIN") begin + if (masked_request_valid) begin + grant_valid_next = 1; + grant_next = masked_request_mask; + grant_encoded_next = masked_request_index; + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index); + end else begin + mask_next = {PORTS{1'b1}} << (masked_request_index + 1); + end + end else begin + grant_valid_next = 1; + grant_next = request_mask; + grant_encoded_next = request_index; + if (LSB_PRIORITY == "LOW") begin + mask_next = {PORTS{1'b1}} >> (PORTS - request_index); + end else begin + mask_next = {PORTS{1'b1}} << (request_index + 1); + end + end + end + end +end + +always @(posedge clk) begin + if (rst) begin + grant_reg <= 0; + grant_valid_reg <= 0; + grant_encoded_reg <= 0; + mask_reg <= 0; + end else begin + grant_reg <= grant_next; + grant_valid_reg <= grant_valid_next; + grant_encoded_reg <= grant_encoded_next; + mask_reg <= mask_next; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/axis_arb_mux.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/axis_arb_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..56b9cc8d8eabb5cad59561fb27a24586f347bbc8 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/axis_arb_mux.v @@ -0,0 +1,249 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * AXI4-Stream arbitrated multiplexer + */ +module axis_arb_mux # +( + // Number of AXI stream inputs + parameter S_COUNT = 4, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = (DATA_WIDTH/8), + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // arbitration type: "PRIORITY" or "ROUND_ROBIN" + parameter ARB_TYPE = "PRIORITY", + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "HIGH" +) +( + input wire clk, + input wire rst, + + /* + * AXI Stream inputs + */ + input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata, + input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep, + input wire [S_COUNT-1:0] s_axis_tvalid, + output wire [S_COUNT-1:0] s_axis_tready, + input wire [S_COUNT-1:0] s_axis_tlast, + input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid, + input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest, + input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI Stream output + */ + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser +); + +parameter CL_S_COUNT = $clog2(S_COUNT); + +wire [S_COUNT-1:0] request; +wire [S_COUNT-1:0] acknowledge; +wire [S_COUNT-1:0] grant; +wire grant_valid; +wire [CL_S_COUNT-1:0] grant_encoded; + +// internal datapath +reg [DATA_WIDTH-1:0] m_axis_tdata_int; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_int; +reg m_axis_tvalid_int; +reg m_axis_tready_int_reg = 1'b0; +reg m_axis_tlast_int; +reg [ID_WIDTH-1:0] m_axis_tid_int; +reg [DEST_WIDTH-1:0] m_axis_tdest_int; +reg [USER_WIDTH-1:0] m_axis_tuser_int; +wire m_axis_tready_int_early; + +assign s_axis_tready = {{S_COUNT-1{1'b0}},(m_axis_tready_int_reg && grant_valid)} << grant_encoded; + +// mux for incoming packet +wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH]; +wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH]; +wire current_s_tvalid = s_axis_tvalid[grant_encoded]; +wire current_s_tready = s_axis_tready[grant_encoded]; +wire current_s_tlast = s_axis_tlast[grant_encoded]; +wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH]; +wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; +wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH]; + +// arbiter instance +arbiter #( + .PORTS(S_COUNT), + .TYPE(ARB_TYPE), + .BLOCK("ACKNOWLEDGE"), + .LSB_PRIORITY(LSB_PRIORITY) +) +arb_inst ( + .clk(clk), + .rst(rst), + .request(request), + .acknowledge(acknowledge), + .grant(grant), + .grant_valid(grant_valid), + .grant_encoded(grant_encoded) +); + +assign request = s_axis_tvalid & ~grant; +assign acknowledge = grant & s_axis_tvalid & s_axis_tready & s_axis_tlast; + +always @* begin + // pass through selected packet data + m_axis_tdata_int = current_s_tdata; + m_axis_tkeep_int = current_s_tkeep; + m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid; + m_axis_tlast_int = current_s_tlast; + m_axis_tid_int = current_s_tid; + m_axis_tdest_int = current_s_tdest; + m_axis_tuser_int = current_s_tuser; +end + +// output datapath logic +reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; +reg m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}}; +reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}; +reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next; +reg temp_m_axis_tlast_reg = 1'b0; +reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}}; +reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}}; + +// datapath control +reg store_axis_int_to_output; +reg store_axis_int_to_temp; +reg store_axis_temp_to_output; + +assign m_axis_tdata = m_axis_tdata_reg; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}}; +assign m_axis_tvalid = m_axis_tvalid_reg; +assign m_axis_tlast = m_axis_tlast_reg; +assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}}; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int)); + +always @* begin + // transfer sink ready state to source + m_axis_tvalid_next = m_axis_tvalid_reg; + temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_axis_temp_to_output = 1'b0; + + if (m_axis_tready_int_reg) begin + // input is ready + if (m_axis_tready || !m_axis_tvalid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axis_tvalid_next = m_axis_tvalid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_axis_tready) begin + // input is not ready, but output is ready + m_axis_tvalid_next = temp_m_axis_tvalid_reg; + temp_m_axis_tvalid_next = 1'b0; + store_axis_temp_to_output = 1'b1; + end +end + +always @(posedge clk) begin + if (rst) begin + m_axis_tvalid_reg <= 1'b0; + m_axis_tready_int_reg <= 1'b0; + temp_m_axis_tvalid_reg <= 1'b0; + end else begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + m_axis_tready_int_reg <= m_axis_tready_int_early; + temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next; + end + + // datapath + if (store_axis_int_to_output) begin + m_axis_tdata_reg <= m_axis_tdata_int; + m_axis_tkeep_reg <= m_axis_tkeep_int; + m_axis_tlast_reg <= m_axis_tlast_int; + m_axis_tid_reg <= m_axis_tid_int; + m_axis_tdest_reg <= m_axis_tdest_int; + m_axis_tuser_reg <= m_axis_tuser_int; + end else if (store_axis_temp_to_output) begin + m_axis_tdata_reg <= temp_m_axis_tdata_reg; + m_axis_tkeep_reg <= temp_m_axis_tkeep_reg; + m_axis_tlast_reg <= temp_m_axis_tlast_reg; + m_axis_tid_reg <= temp_m_axis_tid_reg; + m_axis_tdest_reg <= temp_m_axis_tdest_reg; + m_axis_tuser_reg <= temp_m_axis_tuser_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_axis_tdata_reg <= m_axis_tdata_int; + temp_m_axis_tkeep_reg <= m_axis_tkeep_int; + temp_m_axis_tlast_reg <= m_axis_tlast_int; + temp_m_axis_tid_reg <= m_axis_tid_int; + temp_m_axis_tdest_reg <= m_axis_tdest_int; + temp_m_axis_tuser_reg <= m_axis_tuser_int; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/axis_async_fifo.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/axis_async_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..39ac3498d5b4ac6b5a395831d85d82f0441798ff --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/axis_async_fifo.v @@ -0,0 +1,538 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * AXI4-Stream asynchronous FIFO + */ +module axis_async_fifo # +( + // FIFO depth in words + // KEEP_WIDTH words per cycle if KEEP_ENABLE set + // Rounded up to nearest power of 2 cycles + parameter DEPTH = 4096, + // Width of AXI stream interfaces in bits + parameter DATA_WIDTH = 8, + // Propagate tkeep signal + // If disabled, tkeep assumed to be 1'b1 + parameter KEEP_ENABLE = (DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter KEEP_WIDTH = (DATA_WIDTH/8), + // Propagate tlast signal + parameter LAST_ENABLE = 1, + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // Frame FIFO mode - operate on frames instead of cycles + // When set, m_axis_tvalid will not be deasserted within a frame + // Requires LAST_ENABLE set + parameter FRAME_FIFO = 0, + // tuser value for bad frame marker + parameter USER_BAD_FRAME_VALUE = 1'b1, + // tuser mask for bad frame marker + parameter USER_BAD_FRAME_MASK = 1'b1, + // Drop frames marked bad + // Requires FRAME_FIFO set + parameter DROP_BAD_FRAME = 0, + // Drop incoming frames when full + // When set, s_axis_tready is always asserted + // Requires FRAME_FIFO set + parameter DROP_WHEN_FULL = 0 +) +( + /* + * Common asynchronous reset + */ + input wire async_rst, + + /* + * AXI input + */ + input wire s_clk, + input wire [DATA_WIDTH-1:0] s_axis_tdata, + input wire [KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI output + */ + input wire m_clk, + output wire [DATA_WIDTH-1:0] m_axis_tdata, + output wire [KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser, + + /* + * Status + */ + output wire s_status_overflow, + output wire s_status_bad_frame, + output wire s_status_good_frame, + output wire m_status_overflow, + output wire m_status_bad_frame, + output wire m_status_good_frame +); + +parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH); + +// check configuration +initial begin + if (FRAME_FIFO && !LAST_ENABLE) begin + $error("Error: FRAME_FIFO set requires LAST_ENABLE set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && !FRAME_FIFO) begin + $error("Error: DROP_BAD_FRAME set requires FRAME_FIFO set (instance %m)"); + $finish; + end + + if (DROP_WHEN_FULL && !FRAME_FIFO) begin + $error("Error: DROP_WHEN_FULL set requires FRAME_FIFO set (instance %m)"); + $finish; + end + + if (DROP_BAD_FRAME && (USER_BAD_FRAME_MASK & {USER_WIDTH{1'b1}}) == 0) begin + $error("Error: Invalid USER_BAD_FRAME_MASK value (instance %m)"); + $finish; + end +end + +localparam KEEP_OFFSET = DATA_WIDTH; +localparam LAST_OFFSET = KEEP_OFFSET + (KEEP_ENABLE ? KEEP_WIDTH : 0); +localparam ID_OFFSET = LAST_OFFSET + (LAST_ENABLE ? 1 : 0); +localparam DEST_OFFSET = ID_OFFSET + (ID_ENABLE ? ID_WIDTH : 0); +localparam USER_OFFSET = DEST_OFFSET + (DEST_ENABLE ? DEST_WIDTH : 0); +localparam WIDTH = USER_OFFSET + (USER_ENABLE ? USER_WIDTH : 0); + +reg [ADDR_WIDTH:0] wr_ptr_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_next; +reg [ADDR_WIDTH:0] wr_ptr_cur_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_next; +reg [ADDR_WIDTH:0] wr_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_gray_next; +reg [ADDR_WIDTH:0] wr_ptr_sync_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_sync_gray_next; +reg [ADDR_WIDTH:0] wr_ptr_cur_gray_reg = {ADDR_WIDTH+1{1'b0}}, wr_ptr_cur_gray_next; +reg [ADDR_WIDTH:0] wr_addr_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_next; +reg [ADDR_WIDTH:0] rd_ptr_gray_reg = {ADDR_WIDTH+1{1'b0}}, rd_ptr_gray_next; +reg [ADDR_WIDTH:0] rd_addr_reg = {ADDR_WIDTH+1{1'b0}}; + +reg [ADDR_WIDTH:0] wr_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] wr_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_gray_sync1_reg = {ADDR_WIDTH+1{1'b0}}; +reg [ADDR_WIDTH:0] rd_ptr_gray_sync2_reg = {ADDR_WIDTH+1{1'b0}}; + +reg wr_ptr_update_valid_reg = 1'b0, wr_ptr_update_valid_next; +reg wr_ptr_update_reg = 1'b0, wr_ptr_update_next; +reg wr_ptr_update_sync1_reg = 1'b0; +reg wr_ptr_update_sync2_reg = 1'b0; +reg wr_ptr_update_sync3_reg = 1'b0; +reg wr_ptr_update_ack_sync1_reg = 1'b0; +reg wr_ptr_update_ack_sync2_reg = 1'b0; + +reg s_rst_sync1_reg = 1'b1; +reg s_rst_sync2_reg = 1'b1; +reg s_rst_sync3_reg = 1'b1; +reg m_rst_sync1_reg = 1'b1; +reg m_rst_sync2_reg = 1'b1; +reg m_rst_sync3_reg = 1'b1; + +reg [WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0]; +reg [WIDTH-1:0] mem_read_data_reg; +reg mem_read_data_valid_reg = 1'b0, mem_read_data_valid_next; + +wire [WIDTH-1:0] s_axis; + +reg [WIDTH-1:0] m_axis_reg; +reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; + +// full when first TWO MSBs do NOT match, but rest matches +// (gray code equivalent of first MSB different but rest same) +wire full = ((wr_ptr_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && + (wr_ptr_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && + (wr_ptr_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); +wire full_cur = ((wr_ptr_cur_gray_reg[ADDR_WIDTH] != rd_ptr_gray_sync2_reg[ADDR_WIDTH]) && + (wr_ptr_cur_gray_reg[ADDR_WIDTH-1] != rd_ptr_gray_sync2_reg[ADDR_WIDTH-1]) && + (wr_ptr_cur_gray_reg[ADDR_WIDTH-2:0] == rd_ptr_gray_sync2_reg[ADDR_WIDTH-2:0])); +// empty when pointers match exactly +wire empty = rd_ptr_gray_reg == (FRAME_FIFO ? wr_ptr_gray_sync1_reg : wr_ptr_gray_sync2_reg); +// overflow within packet +wire full_wr = ((wr_ptr_reg[ADDR_WIDTH] != wr_ptr_cur_reg[ADDR_WIDTH]) && + (wr_ptr_reg[ADDR_WIDTH-1:0] == wr_ptr_cur_reg[ADDR_WIDTH-1:0])); + +// control signals +reg write; +reg read; +reg store_output; + +reg drop_frame_reg = 1'b0, drop_frame_next; +reg overflow_reg = 1'b0, overflow_next; +reg bad_frame_reg = 1'b0, bad_frame_next; +reg good_frame_reg = 1'b0, good_frame_next; + +reg overflow_sync1_reg = 1'b0; +reg overflow_sync2_reg = 1'b0; +reg overflow_sync3_reg = 1'b0; +reg overflow_sync4_reg = 1'b0; +reg bad_frame_sync1_reg = 1'b0; +reg bad_frame_sync2_reg = 1'b0; +reg bad_frame_sync3_reg = 1'b0; +reg bad_frame_sync4_reg = 1'b0; +reg good_frame_sync1_reg = 1'b0; +reg good_frame_sync2_reg = 1'b0; +reg good_frame_sync3_reg = 1'b0; +reg good_frame_sync4_reg = 1'b0; + +assign s_axis_tready = (FRAME_FIFO ? (!full_cur || full_wr || DROP_WHEN_FULL) : !full) && !s_rst_sync3_reg; + +generate + assign s_axis[DATA_WIDTH-1:0] = s_axis_tdata; + if (KEEP_ENABLE) assign s_axis[KEEP_OFFSET +: KEEP_WIDTH] = s_axis_tkeep; + if (LAST_ENABLE) assign s_axis[LAST_OFFSET] = s_axis_tlast; + if (ID_ENABLE) assign s_axis[ID_OFFSET +: ID_WIDTH] = s_axis_tid; + if (DEST_ENABLE) assign s_axis[DEST_OFFSET +: DEST_WIDTH] = s_axis_tdest; + if (USER_ENABLE) assign s_axis[USER_OFFSET +: USER_WIDTH] = s_axis_tuser; +endgenerate + +assign m_axis_tvalid = m_axis_tvalid_reg; + +assign m_axis_tdata = m_axis_reg[DATA_WIDTH-1:0]; +assign m_axis_tkeep = KEEP_ENABLE ? m_axis_reg[KEEP_OFFSET +: KEEP_WIDTH] : {KEEP_WIDTH{1'b1}}; +assign m_axis_tlast = LAST_ENABLE ? m_axis_reg[LAST_OFFSET] : 1'b1; +assign m_axis_tid = ID_ENABLE ? m_axis_reg[ID_OFFSET +: ID_WIDTH] : {ID_WIDTH{1'b0}}; +assign m_axis_tdest = DEST_ENABLE ? m_axis_reg[DEST_OFFSET +: DEST_WIDTH] : {DEST_WIDTH{1'b0}}; +assign m_axis_tuser = USER_ENABLE ? m_axis_reg[USER_OFFSET +: USER_WIDTH] : {USER_WIDTH{1'b0}}; + +assign s_status_overflow = overflow_reg; +assign s_status_bad_frame = bad_frame_reg; +assign s_status_good_frame = good_frame_reg; + +assign m_status_overflow = overflow_sync3_reg ^ overflow_sync4_reg; +assign m_status_bad_frame = bad_frame_sync3_reg ^ bad_frame_sync4_reg; +assign m_status_good_frame = good_frame_sync3_reg ^ good_frame_sync4_reg; + +// reset synchronization +always @(posedge s_clk or posedge async_rst) begin + if (async_rst) begin + s_rst_sync1_reg <= 1'b1; + s_rst_sync2_reg <= 1'b1; + s_rst_sync3_reg <= 1'b1; + end else begin + s_rst_sync1_reg <= 1'b0; + s_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg; + s_rst_sync3_reg <= s_rst_sync2_reg; + end +end + +always @(posedge m_clk or posedge async_rst) begin + if (async_rst) begin + m_rst_sync1_reg <= 1'b1; + m_rst_sync2_reg <= 1'b1; + m_rst_sync3_reg <= 1'b1; + end else begin + m_rst_sync1_reg <= 1'b0; + m_rst_sync2_reg <= s_rst_sync1_reg || m_rst_sync1_reg; + m_rst_sync3_reg <= m_rst_sync2_reg; + end +end + +// Write logic +always @* begin + write = 1'b0; + + drop_frame_next = drop_frame_reg; + overflow_next = 1'b0; + bad_frame_next = 1'b0; + good_frame_next = 1'b0; + + wr_ptr_next = wr_ptr_reg; + wr_ptr_cur_next = wr_ptr_cur_reg; + wr_ptr_gray_next = wr_ptr_gray_reg; + wr_ptr_sync_gray_next = wr_ptr_sync_gray_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_gray_reg; + + wr_ptr_update_valid_next = wr_ptr_update_valid_reg; + wr_ptr_update_next = wr_ptr_update_reg; + + if (FRAME_FIFO && wr_ptr_update_valid_reg) begin + // have updated pointer to sync + if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_next = 1'b0; + wr_ptr_sync_gray_next = wr_ptr_gray_reg; + wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg; + end + end + + if (s_axis_tready && s_axis_tvalid) begin + // transfer in + if (!FRAME_FIFO) begin + // normal FIFO mode + write = 1'b1; + wr_ptr_next = wr_ptr_reg + 1; + wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); + end else if (full_cur || full_wr || drop_frame_reg) begin + // full, packet overflow, or currently dropping frame + // drop frame + drop_frame_next = 1'b1; + if (s_axis_tlast) begin + // end of frame, reset write pointer + wr_ptr_cur_next = wr_ptr_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + drop_frame_next = 1'b0; + overflow_next = 1'b1; + end + end else begin + write = 1'b1; + wr_ptr_cur_next = wr_ptr_cur_reg + 1; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + if (s_axis_tlast) begin + // end of frame + if (DROP_BAD_FRAME && USER_BAD_FRAME_MASK & ~(s_axis_tuser ^ USER_BAD_FRAME_VALUE)) begin + // bad packet, reset write pointer + wr_ptr_cur_next = wr_ptr_reg; + wr_ptr_cur_gray_next = wr_ptr_cur_next ^ (wr_ptr_cur_next >> 1); + bad_frame_next = 1'b1; + end else begin + // good packet, update write pointer + wr_ptr_next = wr_ptr_cur_reg + 1; + wr_ptr_gray_next = wr_ptr_next ^ (wr_ptr_next >> 1); + + if (wr_ptr_update_next == wr_ptr_update_ack_sync2_reg) begin + // no sync in progress; sync update + wr_ptr_update_valid_next = 1'b0; + wr_ptr_sync_gray_next = wr_ptr_gray_next; + wr_ptr_update_next = !wr_ptr_update_ack_sync2_reg; + end else begin + // sync in progress; flag it for later + wr_ptr_update_valid_next = 1'b1; + end + + good_frame_next = 1'b1; + end + end + end + end +end + +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_cur_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_sync_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_cur_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + + wr_ptr_update_valid_reg <= 1'b0; + wr_ptr_update_reg <= 1'b0; + + drop_frame_reg <= 1'b0; + overflow_reg <= 1'b0; + bad_frame_reg <= 1'b0; + good_frame_reg <= 1'b0; + end else begin + wr_ptr_reg <= wr_ptr_next; + wr_ptr_cur_reg <= wr_ptr_cur_next; + wr_ptr_gray_reg <= wr_ptr_gray_next; + wr_ptr_sync_gray_reg <= wr_ptr_sync_gray_next; + wr_ptr_cur_gray_reg <= wr_ptr_cur_gray_next; + + wr_ptr_update_valid_reg <= wr_ptr_update_valid_next; + wr_ptr_update_reg <= wr_ptr_update_next; + + drop_frame_reg <= drop_frame_next; + overflow_reg <= overflow_next; + bad_frame_reg <= bad_frame_next; + good_frame_reg <= good_frame_next; + end + + if (FRAME_FIFO) begin + wr_addr_reg <= wr_ptr_cur_next; + end else begin + wr_addr_reg <= wr_ptr_next; + end + + if (write) begin + mem[wr_addr_reg[ADDR_WIDTH-1:0]] <= s_axis; + end +end + +// pointer synchronization +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + rd_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}}; + rd_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_update_ack_sync1_reg <= 1'b0; + wr_ptr_update_ack_sync2_reg <= 1'b0; + end else begin + rd_ptr_gray_sync1_reg <= rd_ptr_gray_reg; + rd_ptr_gray_sync2_reg <= rd_ptr_gray_sync1_reg; + wr_ptr_update_ack_sync1_reg <= wr_ptr_update_sync3_reg; + wr_ptr_update_ack_sync2_reg <= wr_ptr_update_ack_sync1_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + wr_ptr_gray_sync1_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_gray_sync2_reg <= {ADDR_WIDTH+1{1'b0}}; + wr_ptr_update_sync1_reg <= 1'b0; + wr_ptr_update_sync2_reg <= 1'b0; + wr_ptr_update_sync3_reg <= 1'b0; + end else begin + if (!FRAME_FIFO) begin + wr_ptr_gray_sync1_reg <= wr_ptr_gray_reg; + end else if (wr_ptr_update_sync2_reg ^ wr_ptr_update_sync3_reg) begin + wr_ptr_gray_sync1_reg <= wr_ptr_sync_gray_reg; + end + wr_ptr_gray_sync2_reg <= wr_ptr_gray_sync1_reg; + wr_ptr_update_sync1_reg <= wr_ptr_update_reg; + wr_ptr_update_sync2_reg <= wr_ptr_update_sync1_reg; + wr_ptr_update_sync3_reg <= wr_ptr_update_sync2_reg; + end +end + +// status synchronization +always @(posedge s_clk) begin + if (s_rst_sync3_reg) begin + overflow_sync1_reg <= 1'b0; + bad_frame_sync1_reg <= 1'b0; + good_frame_sync1_reg <= 1'b0; + end else begin + overflow_sync1_reg <= overflow_sync1_reg ^ overflow_reg; + bad_frame_sync1_reg <= bad_frame_sync1_reg ^ bad_frame_reg; + good_frame_sync1_reg <= good_frame_sync1_reg ^ good_frame_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + overflow_sync2_reg <= 1'b0; + overflow_sync3_reg <= 1'b0; + overflow_sync4_reg <= 1'b0; + bad_frame_sync2_reg <= 1'b0; + bad_frame_sync3_reg <= 1'b0; + bad_frame_sync4_reg <= 1'b0; + good_frame_sync2_reg <= 1'b0; + good_frame_sync3_reg <= 1'b0; + good_frame_sync4_reg <= 1'b0; + end else begin + overflow_sync2_reg <= overflow_sync1_reg; + overflow_sync3_reg <= overflow_sync2_reg; + overflow_sync4_reg <= overflow_sync3_reg; + bad_frame_sync2_reg <= bad_frame_sync1_reg; + bad_frame_sync3_reg <= bad_frame_sync2_reg; + bad_frame_sync4_reg <= bad_frame_sync3_reg; + good_frame_sync2_reg <= good_frame_sync1_reg; + good_frame_sync3_reg <= good_frame_sync2_reg; + good_frame_sync4_reg <= good_frame_sync3_reg; + end +end + +// Read logic +always @* begin + read = 1'b0; + + rd_ptr_next = rd_ptr_reg; + rd_ptr_gray_next = rd_ptr_gray_reg; + + mem_read_data_valid_next = mem_read_data_valid_reg; + + if (store_output || !mem_read_data_valid_reg) begin + // output data not valid OR currently being transferred + if (!empty) begin + // not empty, perform read + read = 1'b1; + mem_read_data_valid_next = 1'b1; + rd_ptr_next = rd_ptr_reg + 1; + rd_ptr_gray_next = rd_ptr_next ^ (rd_ptr_next >> 1); + end else begin + // empty, invalidate + mem_read_data_valid_next = 1'b0; + end + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + rd_ptr_reg <= {ADDR_WIDTH+1{1'b0}}; + rd_ptr_gray_reg <= {ADDR_WIDTH+1{1'b0}}; + mem_read_data_valid_reg <= 1'b0; + end else begin + rd_ptr_reg <= rd_ptr_next; + rd_ptr_gray_reg <= rd_ptr_gray_next; + mem_read_data_valid_reg <= mem_read_data_valid_next; + end + + rd_addr_reg <= rd_ptr_next; + + if (read) begin + mem_read_data_reg <= mem[rd_addr_reg[ADDR_WIDTH-1:0]]; + end +end + +// Output register +always @* begin + store_output = 1'b0; + + m_axis_tvalid_next = m_axis_tvalid_reg; + + if (m_axis_tready || !m_axis_tvalid) begin + store_output = 1'b1; + m_axis_tvalid_next = mem_read_data_valid_reg; + end +end + +always @(posedge m_clk) begin + if (m_rst_sync3_reg) begin + m_axis_tvalid_reg <= 1'b0; + end else begin + m_axis_tvalid_reg <= m_axis_tvalid_next; + end + + if (store_output) begin + m_axis_reg <= mem_read_data_reg; + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/priority_encoder.v b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/priority_encoder.v new file mode 100644 index 0000000000000000000000000000000000000000..6d7f31b5ec28e0db6ab77f2179bedd69d547003d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/gowin/gowin_corescore/src/verilog-axis_0-r3/rtl/priority_encoder.v @@ -0,0 +1,100 @@ +/* + +Copyright (c) 2014-2018 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`timescale 1ns / 1ps + +/* + * Priority encoder module + */ +module priority_encoder # +( + parameter WIDTH = 4, + // LSB priority: "LOW", "HIGH" + parameter LSB_PRIORITY = "LOW" +) +( + input wire [WIDTH-1:0] input_unencoded, + output wire output_valid, + output wire [$clog2(WIDTH)-1:0] output_encoded, + output wire [WIDTH-1:0] output_unencoded +); + +// power-of-two width +parameter W1 = 2**$clog2(WIDTH); +parameter W2 = W1/2; + +generate + if (WIDTH == 1) begin + // one input + assign output_valid = input_unencoded; + assign output_encoded = 0; + end else if (WIDTH == 2) begin + // two inputs - just an OR gate + assign output_valid = |input_unencoded; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = input_unencoded[1]; + end else begin + assign output_encoded = ~input_unencoded[0]; + end + end else begin + // more than two inputs - split into two parts and recurse + // also pad input to correct power-of-two width + wire [$clog2(W2)-1:0] out1, out2; + wire valid1, valid2; + priority_encoder #( + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) + ) + priority_encoder_inst1 ( + .input_unencoded(input_unencoded[W2-1:0]), + .output_valid(valid1), + .output_unencoded(), + .output_encoded(out1) + ); + priority_encoder #( + .WIDTH(W2), + .LSB_PRIORITY(LSB_PRIORITY) + ) + priority_encoder_inst2 ( + .input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}), + .output_valid(valid2), + .output_unencoded(), + .output_encoded(out2) + ); + // multiplexer to select part + assign output_valid = valid1 | valid2; + if (LSB_PRIORITY == "LOW") begin + assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1}; + end else begin + assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2}; + end + end +endgenerate + +// unencoded output +assign output_unencoded = 1 << output_encoded; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/plot.py b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/plot.py new file mode 100644 index 0000000000000000000000000000000000000000..7be739eb1132895d0350f3d4ae8a114dcb1b36bf --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/plot.py @@ -0,0 +1,128 @@ +import os +import re +import matplotlib.pyplot as plt +import numpy as np + + +# Directory containing the reports +gowin_rpt_dir = "./gowin_rpt" +# Directory containing the Yosys logs +yosys_log_dir = "./yosys_logs" + +# Data storage for Yosys extracted values +yosys_counts = [] +yosys_lut_counts = [] +yosys_dff_counts = [] + +# Data storage +counts = [] +lut_counts = [] +dff_counts = [] +bsram_counts = [] + +# Regular expressions to extract required numbers +lut_pattern = re.compile(r"Logic<\/td>\s*(\d+)\(") +dff_pattern = re.compile(r"  --Register as FF<\/td>\s*(\d+) /") +bsram_pattern = re.compile(r"BSRAM<\/td>\s*(\d+) /") + + + +# Regular expressions to extract LUT and DFF values from Yosys logs +lut_pattern_yosys = re.compile(r"^\s+LUT1\s+(\d+)", re.MULTILINE) +lut2_pattern_yosys = re.compile(r"^\s+LUT2\s+(\d+)", re.MULTILINE) +lut3_pattern_yosys = re.compile(r"^\s+LUT3\s+(\d+)", re.MULTILINE) +lut4_pattern_yosys = re.compile(r"^\s+LUT4\s+(\d+)", re.MULTILINE) +dff_pattern_yosys = re.compile(r"^\s+DFF\s+(\d+)", re.MULTILINE) +dffc_pattern_yosys = re.compile(r"^\s+DFFC\s+(\d+)", re.MULTILINE) +dffe_pattern_yosys = re.compile(r"^\s+DFFE\s+(\d+)", re.MULTILINE) +dffr_pattern_yosys = re.compile(r"^\s+DFFR\s+(\d+)", re.MULTILINE) +dffre_pattern_yosys = re.compile(r"^\s+DFFRE\s+(\d+)", re.MULTILINE) +dffs_pattern_yosys = re.compile(r"^\s+DFFS\s+(\d+)", re.MULTILINE) +dffse_pattern_yosys = re.compile(r"^\s+DFFSE\s+(\d+)", re.MULTILINE) + +# Process each Yosys log file +for count in range(1, 51): + file_path = os.path.join(yosys_log_dir, f"log_{count}") + + if os.path.exists(file_path): + with open(file_path, "r", encoding="utf-8") as file: + content = file.read() + + # Extract LUT and DFF counts + lut1_match = lut_pattern_yosys.search(content) + lut2_match = lut2_pattern_yosys.search(content) + lut3_match = lut3_pattern_yosys.search(content) + lut4_match = lut4_pattern_yosys.search(content) + dff_match = dff_pattern_yosys.search(content) + dffc_match = dffc_pattern_yosys.search(content) + dffe_match = dffe_pattern_yosys.search(content) + dffr_match = dffr_pattern_yosys.search(content) + dffre_match = dffre_pattern_yosys.search(content) + dffs_match = dffs_pattern_yosys.search(content) + dffse_match = dffse_pattern_yosys.search(content) + + if all([lut1_match, lut2_match, lut3_match, lut4_match, dff_match, dffc_match, dffe_match, dffr_match, dffre_match, dffs_match, dffse_match]): + yosys_counts.append(count) + lut_total = sum(int(m.group(1)) for m in [lut1_match, lut2_match, lut3_match, lut4_match]) + dff_total = sum(int(m.group(1)) for m in [dff_match, dffc_match, dffe_match, dffr_match, dffre_match, dffs_match, dffse_match]) + + yosys_lut_counts.append(lut_total) + yosys_dff_counts.append(dff_total) +# Process each file +for count in range(1, 51): + file_path = os.path.join(gowin_rpt_dir, f"gowin_corescore_syn_rpt_{count}.html") + + if os.path.exists(file_path): + with open(file_path, "r", encoding="utf-8") as file: + content = file.read() + + lut_match = lut_pattern.search(content) + dff_match = dff_pattern.search(content) + bsram_match = bsram_pattern.search(content) + + if lut_match and dff_match and bsram_match: + counts.append(count) + lut_counts.append(int(lut_match.group(1))) + dff_counts.append(int(dff_match.group(1))) + bsram_counts.append(int(bsram_match.group(1))) + +# Compute relative differences (percentage difference) +lut_percentage_diff = [(y - p) / p * 100 for p, y in zip(lut_counts, yosys_lut_counts)] +dff_percentage_diff = [(y - p) / p * 100 for p, y in zip(dff_counts, yosys_dff_counts)] + + +mean_lut_percentage_diff = np.mean(lut_percentage_diff) +print(f"Mean LUT Percentage Difference: {mean_lut_percentage_diff:.2f}%") +# Plot results comparing proprietary and Yosys synthesis +plt.figure(figsize=(10, 6)) +plt.plot(counts, lut_counts, marker='o', linestyle='-', label="LUT Count (Proprietary)") +plt.plot(yosys_counts, yosys_lut_counts, marker='o', linestyle='--', label="LUT Count (Yosys)") +plt.plot(counts, dff_counts, marker='s', linestyle='-', label="DFF Count (Proprietary)") +plt.plot(yosys_counts, yosys_dff_counts, marker='s', linestyle='--', label="DFF Count (Yosys)") + +plt.xlabel("Number of Cores") +plt.ylabel("Count") +plt.legend() +plt.grid(True) + +# Show the updated plot +plt.show() + + + + + + +# Plot relative differences +plt.figure(figsize=(10, 6)) +plt.plot(counts, lut_percentage_diff, marker='o', linestyle='-', label="LUT Count Difference (%)") +plt.plot(counts, dff_percentage_diff, marker='s', linestyle='-', label="DFF Count Difference (%)") + +plt.xlabel("Number of Cores") +plt.ylabel("Percentage Difference (%)") +plt.legend() +plt.axhline(0, color='black', linestyle='--', linewidth=0.8) # Add horizontal line at 0% +plt.grid(True) + +# Show the percentage difference plot +plt.show() diff --git a/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/yosys_gowin.py b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/yosys_gowin.py new file mode 100644 index 0000000000000000000000000000000000000000..59e8de2da2a2d87d15d41990a057bd7c73d4466e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/1.corescore_cc/yosys_gowin.py @@ -0,0 +1,70 @@ +#-------------------------------------------------------------- +#python script to run yosys vs gowin synth testing on corescore +#-------------------------------------------------------------- + +import yaml +import subprocess +import shutil +import os + +# Load the YAML file +input_file = "./fusesoc_libraries/corescore/corescore.core" +yosys_log_dir = "./yosys_logs" +gowin_src_dir = "./gowin/gowin_corescore/src/" +gowin_rpt_dir = "./gowin_rpt" +os.makedirs(yosys_log_dir, exist_ok=True) +os.makedirs(gowin_rpt_dir, exist_ok=True) + +with open(input_file, "r") as f: + data = yaml.safe_load(f) + +# Ensure the structure exists +if "targets" in data and "gowin_yosys" in data["targets"]: + for count in range(1, 50): + data["targets"]["gowin_yosys"]["generate"] = [{"corescorecore": {"count": count}}] + + # Save modifications back to the same file + with open(input_file, "w") as f: + yaml.dump(data, f, default_flow_style=False) + print(f"Updated count to {count}") + + # Run fusesoc command + subprocess.run(["fusesoc", "run", "--target=gowin_yosys", "corescore"], check=True) + + # Copy yosys log file + source_log = "./build/corescore_0/gowin_yosys-yosys/yosys.log" + destination_log = os.path.join(yosys_log_dir, f"log_{count}") + if os.path.exists(source_log): + shutil.copy(source_log, destination_log) + print(f"Copied {source_log} to {destination_log}") + else: + print(f"Warning: {source_log} not found, skipping copy.") + + # # Copy corecore-corecorecore_0 folder + # source_folder = "./build/corescore_0/gowin_yosys-yosys/src/corescore-corescorecore_0" + # destination_folder = os.path.join(gowin_src_dir, "corescore-corescorecore_0") + # if os.path.exists(source_folder): + # if os.path.exists(destination_folder): + # shutil.rmtree(destination_folder) + # shutil.copytree(source_folder, destination_folder) + # print(f"Copied {source_folder} to {destination_folder}") + # else: + # print(f"Warning: {source_folder} not found, skipping copy.") + + # # Run Gowin script + # os.chdir("gowin") + # subprocess.run(["gw_sh", "gowin.tcl"], check=True) + # os.chdir("..") + + # # Copy Gowin synthesis report + # source_rpt = "./gowin/gowin_corescore/impl/gwsynthesis/gowin_corescore_syn.rpt.html" + # destination_rpt = os.path.join(gowin_rpt_dir, f"gowin_corescore_syn_rpt_{count}.html") + # if os.path.exists(source_rpt): + # shutil.copy(source_rpt, destination_rpt) + # print(f"Copied {source_rpt} to {destination_rpt}") + # else: + # print(f"Warning: {source_rpt} not found, skipping copy.") +else: + print("Error: Required target structure not found in YAML file.") + + diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/1.hw/femtorv32_quark_bicycle.v b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/1.hw/femtorv32_quark_bicycle.v new file mode 100644 index 0000000000000000000000000000000000000000..e8890100f799f4e4bb87431a0af6d380aa428979 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/1.hw/femtorv32_quark_bicycle.v @@ -0,0 +1,409 @@ +/*******************************************************************/ +// FemtoRV32, a collection of minimalistic RISC-V RV32 cores. +// This version: The "Quark", the most elementary version of FemtoRV32. +// A single VERILOG file, compact & understandable code. +// (200 lines of code, 400 lines counting comments) +// +// Instruction set: RV32I + RDCYCLES +// +// Parameters: +// Reset address can be defined using RESET_ADDR (default is 0). +// +// The ADDR_WIDTH parameter lets you define the width of the internal +// address bus (and address computation logic). +// +// Macros: +// optionally one may define NRV_IS_IO_ADDR(addr), that is supposed to: +// evaluate to 1 if addr is in mapped IO space, +// evaluate to 0 otherwise +// (additional wait states are used when in IO space). +// If left undefined, wait states are always used. +// +// NRV_COUNTER_WIDTH may be defined to reduce the number of bits used +// by the ticks counter. If not defined, a 32-bits counter is generated. +// (reducing its width may be useful for space-constrained designs). +// +// Bruno Levy, Matthias Koch, 2020-2021 +/*******************************************************************/ + +// Firmware generation flags for this processor +`define NRV_ARCH "rv32i" +`define NRV_ABI "ilp32" +`define NRV_OPTIMIZE "-Os" + +module FemtoRV32( + input clk, + + output [31:0] mem_addr, // address bus + output [31:0] mem_wdata, // data to be written + output [3:0] mem_wmask, // write mask for the 4 bytes of each word + input [31:0] mem_rdata, // input lines for both data and instr + output mem_rstrb, // active to initiate memory read (used by IO) + input mem_rbusy, // asserted if memory is busy reading value + input mem_wbusy, // asserted if memory is busy writing value + + input reset // set to 0 to reset the processor +); + + parameter RESET_ADDR = 32'h00000000; + parameter ADDR_WIDTH = 24; + + /***************************************************************************/ + // Instruction decoding. + /***************************************************************************/ + + // Extracts rd,rs1,rs2,funct3,imm and opcode from instruction. + // Reference: Table page 104 of: + // https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf + + // The destination register + wire [4:0] rdId = instr[11:7]; + + // The ALU function, decoded in 1-hot form (doing so reduces LUT count) + // It is used as follows: funct3Is[val] <=> funct3 == val + (* onehot *) + wire [7:0] funct3Is = 8'b00000001 << instr[14:12]; + + // The five immediate formats, see RiscV reference (link above), Fig. 2.4 p. 12 + wire [31:0] Uimm = { instr[31], instr[30:12], {12{1'b0}}}; + wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]}; + /* verilator lint_off UNUSED */ // MSBs of SBJimms are not used by addr adder. + wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]}; + wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0}; + wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0}; + /* verilator lint_on UNUSED */ + + // Base RISC-V (RV32I) has only 10 different instructions ! + wire isLoad = (instr[6:2] == 5'b00000); // rd <- mem[rs1+Iimm] + wire isALUimm = (instr[6:2] == 5'b00100); // rd <- rs1 OP Iimm + wire isAUIPC = (instr[6:2] == 5'b00101); // rd <- PC + Uimm + wire isStore = (instr[6:2] == 5'b01000); // mem[rs1+Simm] <- rs2 + wire isALUreg = (instr[6:2] == 5'b01100); // rd <- rs1 OP rs2 + wire isLUI = (instr[6:2] == 5'b01101); // rd <- Uimm + wire isBranch = (instr[6:2] == 5'b11000); // if(rs1 OP rs2) PC<-PC+Bimm + wire isJALR = (instr[6:2] == 5'b11001); // rd <- PC+4; PC<-rs1+Iimm + wire isJAL = (instr[6:2] == 5'b11011); // rd <- PC+4; PC<-PC+Jimm + wire isSYSTEM = (instr[6:2] == 5'b11100); // rd <- cycles + + wire isALU = isALUimm | isALUreg; + + /***************************************************************************/ + // The register file. + /***************************************************************************/ + + reg [31:0] rs1; + reg [31:0] rs2; + reg [31:0] registerFile [31:0]; + + always @(posedge clk) begin + if (writeBack) + if (rdId != 0) + registerFile[rdId] <= writeBackData; + end + + /***************************************************************************/ + // The ALU. Does operations and tests combinatorially, except shifts. + /***************************************************************************/ + + // First ALU source, always rs1 + wire [31:0] aluIn1 = rs1; + + // Second ALU source, depends on opcode: + // ALUreg, Branch: rs2 + // ALUimm, Load, JALR: Iimm + wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm; + + // The adder is used by both arithmetic instructions and JALR. + wire [31:0] aluPlus = aluIn1 + aluIn2; + + // Use a single 33 bits subtract to do subtraction and all comparisons + // (trick borrowed from swapforth/J1) + wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1; + wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32]; + wire LTU = aluMinus[32]; + wire EQ = (aluMinus[31:0] == 0); + + /***************************************************************************/ + + // Use the same shifter both for left and right shifts by + // applying bit reversal + + wire [31:0] shifter_in = funct3Is[1] ? + {aluIn1[ 0], aluIn1[ 1], aluIn1[ 2], aluIn1[ 3], aluIn1[ 4], aluIn1[ 5], + aluIn1[ 6], aluIn1[ 7], aluIn1[ 8], aluIn1[ 9], aluIn1[10], aluIn1[11], + aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], + aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], + aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], + aluIn1[30], aluIn1[31]} : aluIn1; + + /* verilator lint_off WIDTH */ + wire [31:0] shifter = + $signed({instr[30] & aluIn1[31], shifter_in}) >>> aluIn2[4:0]; + /* verilator lint_on WIDTH */ + + wire [31:0] leftshift = { + shifter[ 0], shifter[ 1], shifter[ 2], shifter[ 3], shifter[ 4], + shifter[ 5], shifter[ 6], shifter[ 7], shifter[ 8], shifter[ 9], + shifter[10], shifter[11], shifter[12], shifter[13], shifter[14], + shifter[15], shifter[16], shifter[17], shifter[18], shifter[19], + shifter[20], shifter[21], shifter[22], shifter[23], shifter[24], + shifter[25], shifter[26], shifter[27], shifter[28], shifter[29], + shifter[30], shifter[31]}; + + /***************************************************************************/ + + // Notes: + // - instr[30] is 1 for SUB and 0 for ADD + // - for SUB, need to test also instr[5] to discriminate ADDI: + // (1 for ADD/SUB, 0 for ADDI, and Iimm used by ADDI overlaps bit 30 !) + // - instr[30] is 1 for SRA (do sign extension) and 0 for SRL + + wire [31:0] aluOut = + (funct3Is[0] ? instr[30] & instr[5] ? aluMinus[31:0] : aluPlus : 32'b0) | + (funct3Is[1] ? leftshift : 32'b0) | + (funct3Is[2] ? {31'b0, LT} : 32'b0) | + (funct3Is[3] ? {31'b0, LTU} : 32'b0) | + (funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b0) | + (funct3Is[5] ? shifter : 32'b0) | + (funct3Is[6] ? aluIn1 | aluIn2 : 32'b0) | + (funct3Is[7] ? aluIn1 & aluIn2 : 32'b0) ; + + /***************************************************************************/ + // The predicate for conditional branches. + /***************************************************************************/ + + wire predicate = + funct3Is[0] & EQ | // BEQ + funct3Is[1] & !EQ | // BNE + funct3Is[4] & LT | // BLT + funct3Is[5] & !LT | // BGE + funct3Is[6] & LTU | // BLTU + funct3Is[7] & !LTU ; // BGEU + + /***************************************************************************/ + // Program counter and branch target computation. + /***************************************************************************/ + + reg [ADDR_WIDTH-1:0] PC; // The program counter. + reg [31:2] instr; // Latched instruction. Note that bits 0 and 1 are + // ignored (not used in RV32I base instr set). + + wire [ADDR_WIDTH-1:0] PCplus4 = PC + 4; + + // An adder used to compute branch address, JAL address and AUIPC. + // branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm + // Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm) + wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] : + instr[4] ? Uimm[ADDR_WIDTH-1:0] : + Bimm[ADDR_WIDTH-1:0] ); + + // A separate adder to compute the destination of load/store. + // testing instr[5] is equivalent to testing isStore in this context. + wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] + + (instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]); + + /* verilator lint_off WIDTH */ + // internal address registers and cycles counter may have less than + // 32 bits, so we deactivate width test for mem_addr and writeBackData + + wire [ADDR_WIDTH-1:0] PC_new = + isJALR ? {aluPlus[ADDR_WIDTH-1:1],1'b0} : + jumpToPCplusImm ? PCplusImm : + PCplus4; + + assign mem_addr = state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ? PC : + state[EXECUTE_bit] & ~isLoad & ~isStore ? PC_new : + loadstore_addr ; + + /***************************************************************************/ + // The value written back to the register file. + /***************************************************************************/ + + wire [31:0] writeBackData = + (isSYSTEM ? cycles : 32'b0) | // SYSTEM + (isLUI ? Uimm : 32'b0) | // LUI + (isALU ? aluOut : 32'b0) | // ALUreg, ALUimm + (isAUIPC ? PCplusImm : 32'b0) | // AUIPC + (isJALR | isJAL ? PCplus4 : 32'b0) | // JAL, JALR + (isLoad ? LOAD_data : 32'b0) ; // Load + + /* verilator lint_on WIDTH */ + + + /***************************************************************************/ + // LOAD/STORE + /***************************************************************************/ + + // All memory accesses are aligned on 32 bits boundary. For this + // reason, we need some circuitry that does unaligned halfword + // and byte load/store, based on: + // - funct3[1:0]: 00->byte 01->halfword 10->word + // - mem_addr[1:0]: indicates which byte/halfword is accessed + + wire mem_byteAccess = instr[13:12] == 2'b00; // funct3[1:0] == 2'b00; + wire mem_halfwordAccess = instr[13:12] == 2'b01; // funct3[1:0] == 2'b01; + + // LOAD, in addition to funct3[1:0], LOAD depends on: + // - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion + + wire LOAD_sign = + !instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]); + + wire [31:0] LOAD_data = + mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} : + mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} : + mem_rdata ; + + wire [15:0] LOAD_halfword = + loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0]; + + wire [7:0] LOAD_byte = + loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0]; + + // STORE + + assign mem_wdata[ 7: 0] = rs2[7:0]; + assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8]; + assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16]; + assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] : + loadstore_addr[1] ? rs2[15:8] : rs2[31:24]; + + // The memory write mask: + // 1111 if writing a word + // 0011 or 1100 if writing a halfword + // (depending on loadstore_addr[1]) + // 0001, 0010, 0100 or 1000 if writing a byte + // (depending on loadstore_addr[1:0]) + + wire [3:0] STORE_wmask = + mem_byteAccess ? + (loadstore_addr[1] ? + (loadstore_addr[0] ? 4'b1000 : 4'b0100) : + (loadstore_addr[0] ? 4'b0010 : 4'b0001) + ) : + mem_halfwordAccess ? + (loadstore_addr[1] ? 4'b1100 : 4'b0011) : + 4'b1111; + + /*************************************************************************/ + // And, last but not least, the state machine. + /*************************************************************************/ + + localparam FETCH_INSTR_bit = 0; + localparam WAIT_INSTR_bit = 1; + localparam EXECUTE_bit = 2; + localparam WAIT_ALU_OR_MEM_bit = 3; + localparam NB_STATES = 4; + + localparam FETCH_INSTR = 1 << FETCH_INSTR_bit; + localparam WAIT_INSTR = 1 << WAIT_INSTR_bit; + localparam EXECUTE = 1 << EXECUTE_bit; + localparam WAIT_ALU_OR_MEM = 1 << WAIT_ALU_OR_MEM_bit; + + (* onehot *) + reg [NB_STATES-1:0] state; + + // The signals (internal and external) that are determined + // combinatorially from state and other signals. + + // register write-back enable. + wire writeBack = ~(isBranch | isStore ) & + (state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]); + + // The memory-read signal. + assign mem_rstrb = state[EXECUTE_bit] & ~isStore | state[FETCH_INSTR_bit]; + + // The mask for memory-write. + assign mem_wmask = {4{state[EXECUTE_bit] & isStore}} & STORE_wmask; + + wire jumpToPCplusImm = isJAL | (isBranch & predicate); +`ifdef NRV_IS_IO_ADDR + wire needToWait = isLoad | + isStore & `NRV_IS_IO_ADDR(mem_addr) ; +`else + wire needToWait = isLoad | isStore ; +`endif + + always @(posedge clk) begin + if(!reset) begin + state <= WAIT_ALU_OR_MEM; // Just waiting for !mem_wbusy + PC <= RESET_ADDR[ADDR_WIDTH-1:0]; + end else + + // See note [1] at the end of this file. + (* parallel_case *) + case(1'b1) + + state[WAIT_INSTR_bit]: begin + if(!mem_rbusy) begin // may be high when executing from SPI flash + rs1 <= registerFile[mem_rdata[19:15]]; + rs2 <= registerFile[mem_rdata[24:20]]; + instr <= mem_rdata[31:2]; // Bits 0 and 1 are ignored (see + state <= EXECUTE; // also the declaration of instr). + end + end + + state[EXECUTE_bit]: begin + PC <= PC_new; + state <= needToWait ? WAIT_ALU_OR_MEM : WAIT_INSTR; + end + + state[WAIT_ALU_OR_MEM_bit]: begin + if(!mem_rbusy & !mem_wbusy) state <= FETCH_INSTR; + end + + default: begin // FETCH_INSTR + state <= WAIT_INSTR; + end + + endcase + end + + /***************************************************************************/ + // Cycle counter + /***************************************************************************/ + +`ifdef NRV_COUNTER_WIDTH + reg [`NRV_COUNTER_WIDTH-1:0] cycles; +`else + reg [31:0] cycles; +`endif + always @(posedge clk) cycles <= cycles + 1; + +`ifdef BENCH + initial begin + cycles = 0; + registerFile[0] = 0; + end +`endif + +endmodule + +/*****************************************************************************/ +// Notes: +// +// [1] About the "reverse case" statement, also used in Claire Wolf's picorv32: +// It is just a cleaner way of writing a series of cascaded if() statements, +// To understand it, think about the case statement *in general* as follows: +// case (expr) +// val_1: statement_1 +// val_2: statement_2 +// ... val_n: statement_n +// endcase +// The first statement_i such that expr == val_i is executed. +// Now if expr is 1'b1: +// case (1'b1) +// cond_1: statement_1 +// cond_2: statement_2 +// ... cond_n: statement_n +// endcase +// It is *exactly the same thing*, the first statement_i such that +// expr == cond_i is executed (that is, such that 1'b1 == cond_i, +// in other words, such that cond_i is true) +// More on this: +// https://stackoverflow.com/questions/15418636/case-statement-in-verilog +// +// [2] state uses 1-hot encoding (at any time, state has only one bit set to 1). +// It uses a larger number of bits (one bit per state), but often results in +// a both more compact (fewer LUTs) and faster state machine. + diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/FemtoRV32.v b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/FemtoRV32.v new file mode 100644 index 0000000000000000000000000000000000000000..4f4e616e91f824fa0d8f550a7f0ba830d967fdf6 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/FemtoRV32.v @@ -0,0 +1,121 @@ +module FemtoRV32 ( + clk, + mem_addr, + mem_wdata, + mem_wmask, + mem_rdata, + mem_rstrb, + mem_rbusy, + mem_wbusy, + reset +); + input clk; + output wire [31:0] mem_addr; + output wire [31:0] mem_wdata; + output wire [3:0] mem_wmask; + input [31:0] mem_rdata; + output wire mem_rstrb; + input mem_rbusy; + input mem_wbusy; + input reset; + parameter RESET_ADDR = 32'h00000000; + parameter ADDR_WIDTH = 24; + reg [31:2] instr; + wire [4:0] rdId = instr[11:7]; + (* onehot *) wire [7:0] funct3Is = 8'b00000001 << instr[14:12]; + wire [31:0] Uimm = {instr[31], instr[30:12], {12 {1'b0}}}; + wire [31:0] Iimm = {{21 {instr[31]}}, instr[30:20]}; + wire [31:0] Simm = {{21 {instr[31]}}, instr[30:25], instr[11:7]}; + wire [31:0] Bimm = {{20 {instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; + wire [31:0] Jimm = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; + wire isLoad = instr[6:2] == 5'b00000; + wire isALUimm = instr[6:2] == 5'b00100; + wire isAUIPC = instr[6:2] == 5'b00101; + wire isStore = instr[6:2] == 5'b01000; + wire isALUreg = instr[6:2] == 5'b01100; + wire isLUI = instr[6:2] == 5'b01101; + wire isBranch = instr[6:2] == 5'b11000; + wire isJALR = instr[6:2] == 5'b11001; + wire isJAL = instr[6:2] == 5'b11011; + wire isSYSTEM = instr[6:2] == 5'b11100; + wire isALU = isALUimm | isALUreg; + reg [31:0] rs1; + reg [31:0] rs2; + reg [31:0] registerFile [31:0]; + localparam EXECUTE_bit = 2; + localparam WAIT_ALU_OR_MEM_bit = 3; + wire writeBack = ~(isBranch | isStore) & (state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]); + wire [ADDR_WIDTH - 1:0] loadstore_addr = rs1[ADDR_WIDTH - 1:0] + (instr[5] ? Simm[ADDR_WIDTH - 1:0] : Iimm[ADDR_WIDTH - 1:0]); + wire [15:0] LOAD_halfword = (loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0]); + wire [7:0] LOAD_byte = (loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0]); + wire mem_byteAccess = instr[13:12] == 2'b00; + wire LOAD_sign = !instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]); + wire mem_halfwordAccess = instr[13:12] == 2'b01; + wire [31:0] LOAD_data = (mem_byteAccess ? {{24 {LOAD_sign}}, LOAD_byte} : (mem_halfwordAccess ? {{16 {LOAD_sign}}, LOAD_halfword} : mem_rdata)); + reg [ADDR_WIDTH - 1:0] PC; + wire [ADDR_WIDTH - 1:0] PCplus4 = PC + 4; + wire [ADDR_WIDTH - 1:0] PCplusImm = PC + (instr[3] ? Jimm[ADDR_WIDTH - 1:0] : (instr[4] ? Uimm[ADDR_WIDTH - 1:0] : Bimm[ADDR_WIDTH - 1:0])); + wire [31:0] aluIn1 = rs1; + wire [31:0] aluIn2 = (isALUreg | isBranch ? rs2 : Iimm); + wire [32:0] aluMinus = ({1'b1, ~aluIn2} + {1'b0, aluIn1}) + 33'b000000000000000000000000000000001; + wire LT = (aluIn1[31] ^ aluIn2[31] ? aluIn1[31] : aluMinus[32]); + wire LTU = aluMinus[32]; + wire [31:0] aluPlus = aluIn1 + aluIn2; + wire [31:0] shifter_in = (funct3Is[1] ? {aluIn1[0], aluIn1[1], aluIn1[2], aluIn1[3], aluIn1[4], aluIn1[5], aluIn1[6], aluIn1[7], aluIn1[8], aluIn1[9], aluIn1[10], aluIn1[11], aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], aluIn1[30], aluIn1[31]} : aluIn1); + wire [31:0] shifter = $signed({instr[30] & aluIn1[31], shifter_in}) >>> aluIn2[4:0]; + wire [31:0] leftshift = {shifter[0], shifter[1], shifter[2], shifter[3], shifter[4], shifter[5], shifter[6], shifter[7], shifter[8], shifter[9], shifter[10], shifter[11], shifter[12], shifter[13], shifter[14], shifter[15], shifter[16], shifter[17], shifter[18], shifter[19], shifter[20], shifter[21], shifter[22], shifter[23], shifter[24], shifter[25], shifter[26], shifter[27], shifter[28], shifter[29], shifter[30], shifter[31]}; + wire [31:0] aluOut = (((((((funct3Is[0] ? (instr[30] & instr[5] ? aluMinus[31:0] : aluPlus) : 32'b00000000000000000000000000000000) | (funct3Is[1] ? leftshift : 32'b00000000000000000000000000000000)) | (funct3Is[2] ? {31'b0000000000000000000000000000000, LT} : 32'b00000000000000000000000000000000)) | (funct3Is[3] ? {31'b0000000000000000000000000000000, LTU} : 32'b00000000000000000000000000000000)) | (funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b00000000000000000000000000000000)) | (funct3Is[5] ? shifter : 32'b00000000000000000000000000000000)) | (funct3Is[6] ? aluIn1 | aluIn2 : 32'b00000000000000000000000000000000)) | (funct3Is[7] ? aluIn1 & aluIn2 : 32'b00000000000000000000000000000000); + reg [31:0] cycles; + wire [31:0] writeBackData = (((((isSYSTEM ? cycles : 32'b00000000000000000000000000000000) | (isLUI ? Uimm : 32'b00000000000000000000000000000000)) | (isALU ? aluOut : 32'b00000000000000000000000000000000)) | (isAUIPC ? PCplusImm : 32'b00000000000000000000000000000000)) | (isJALR | isJAL ? PCplus4 : 32'b00000000000000000000000000000000)) | (isLoad ? LOAD_data : 32'b00000000000000000000000000000000); + always @(posedge clk) + if (writeBack) begin + if (rdId != 0) + registerFile[rdId] <= writeBackData; + end + wire EQ = aluMinus[31:0] == 0; + wire predicate = (((((funct3Is[0] & EQ) | (funct3Is[1] & !EQ)) | (funct3Is[4] & LT)) | (funct3Is[5] & !LT)) | (funct3Is[6] & LTU)) | (funct3Is[7] & !LTU); + wire jumpToPCplusImm = isJAL | (isBranch & predicate); + wire [ADDR_WIDTH - 1:0] PC_new = (isJALR ? {aluPlus[ADDR_WIDTH - 1:1], 1'b0} : (jumpToPCplusImm ? PCplusImm : PCplus4)); + localparam FETCH_INSTR_bit = 0; + localparam WAIT_INSTR_bit = 1; + assign mem_addr = (state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ? PC : ((state[EXECUTE_bit] & ~isLoad) & ~isStore ? PC_new : loadstore_addr)); + assign mem_wdata[7:0] = rs2[7:0]; + assign mem_wdata[15:8] = (loadstore_addr[0] ? rs2[7:0] : rs2[15:8]); + assign mem_wdata[23:16] = (loadstore_addr[1] ? rs2[7:0] : rs2[23:16]); + assign mem_wdata[31:24] = (loadstore_addr[0] ? rs2[7:0] : (loadstore_addr[1] ? rs2[15:8] : rs2[31:24])); + wire [3:0] STORE_wmask = (mem_byteAccess ? (loadstore_addr[1] ? (loadstore_addr[0] ? 4'b1000 : 4'b0100) : (loadstore_addr[0] ? 4'b0010 : 4'b0001)) : (mem_halfwordAccess ? (loadstore_addr[1] ? 4'b1100 : 4'b0011) : 4'b1111)); + localparam NB_STATES = 4; + localparam FETCH_INSTR = 1; + localparam WAIT_INSTR = 2; + localparam EXECUTE = 4; + localparam WAIT_ALU_OR_MEM = 8; + (* onehot *) reg [3:0] state; + assign mem_rstrb = (state[EXECUTE_bit] & ~isStore) | state[FETCH_INSTR_bit]; + assign mem_wmask = {4 {state[EXECUTE_bit] & isStore}} & STORE_wmask; + wire needToWait = isLoad | isStore; + always @(posedge clk) + if (!reset) begin + state <= WAIT_ALU_OR_MEM; + PC <= RESET_ADDR[ADDR_WIDTH - 1:0]; + end + else + (* parallel_case *) + case (1'b1) + state[WAIT_INSTR_bit]: + if (!mem_rbusy) begin + rs1 <= registerFile[mem_rdata[19:15]]; + rs2 <= registerFile[mem_rdata[24:20]]; + instr <= mem_rdata[31:2]; + state <= EXECUTE; + end + state[EXECUTE_bit]: begin + PC <= PC_new; + state <= (needToWait ? WAIT_ALU_OR_MEM : WAIT_INSTR); + end + state[WAIT_ALU_OR_MEM_bit]: + if (!mem_rbusy & !mem_wbusy) + state <= FETCH_INSTR; + default: state <= WAIT_INSTR; + endcase + always @(posedge clk) cycles <= cycles + 1; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/FemtoRV32_00.v b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/FemtoRV32_00.v new file mode 100644 index 0000000000000000000000000000000000000000..6be1721d6f9dc525e3ece038f295aba05e54cd8a --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/FemtoRV32_00.v @@ -0,0 +1,9517 @@ +// (c) Cologne Chip AG +// FPGA Verilog netlist writer Version: Version 4.2 (1 January 2025) +// Compile Time: 2025-02-04 05:47:38 +// Program Run: 2025-03-16 11:26:34 +// Program Call: /home/tibrahimovic/0.git-repo/cc-toolchain-linux/bin/p_r/p_r -i net/FemtoRV32_synth.v -o FemtoRV32 -ccf /home/tibrahimovic/projects/femtorv32-quark-bicycle/3.build/../1.hw/constraints/constraints.ccf -cCP --verbose +// File Type: Verilog + +// Gatecount: 1516 +module FemtoRV32 (clk , mem_rbusy , mem_rdata , mem_wbusy , reset , + mem_addr , mem_rstrb , mem_wdata , mem_wmask + ) ; + +input clk; +input mem_rbusy; +input [31:0]mem_rdata; +input mem_wbusy; +input reset; + +output [31:0]mem_addr; +output mem_rstrb; +output [31:0]mem_wdata; +output [3:0]mem_wmask; + + + +wire [31:0]mem_rdata; +wire [31:0]mem_addr; +wire [31:0]mem_wdata; +wire [3:0]mem_wmask; +wire clk; +wire na1_2; +wire na2_1; +wire na3_2; +wire na4_1; +wire na5_1; +wire na5_2; +wire na6_1; +wire na7_1; +wire na8_1; +wire na9_2; +wire reset; +wire na10_1; +wire na11_1; +wire na12_1; +wire na13_1; +wire na14_1; +wire na15_1; +wire na16_1; +wire na17_1; +wire na18_1; +wire na19_1; +wire na20_1; +wire na21_1; +wire na22_1; +wire na23_1; +wire na24_1; +wire na25_1; +wire na26_1; +wire na27_1; +wire na28_1; +wire na29_1; +wire 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na1834_2; +wire na1835_2; +wire na1836_2; +wire na1837_2; +wire na1838_2; +wire na1839_2; +wire na1840_2; +wire na1841_2; +wire na1842_2; +wire na1843_2; +wire na1844_2; +wire na1845_2; +wire na1846_2; +wire na1847_2; +wire na1848_2; +wire na1849_2; +wire na1850_2; +wire na1851_2; +wire na1852_2; +wire na1853_2; +wire na1854_2; +wire na1855_2; +wire na1856_2; +wire na1857_2; +wire na1858_2; +wire na1859_2; +wire na1860_2; +wire na1861_2; +wire na1862_2; +wire na1863_2; +wire na1864_2; +wire na1865_2; +wire na1866_2; +wire na1867_2; +wire na1868_2; +wire na1869_2; +wire na1870_2; +wire na1871_2; +wire na1872_2; +wire na1873_2; +wire na1874_2; +wire na1875_2; +wire na1876_2; +wire na1877_2; +wire na1878_2; +wire na1879_2; +wire na1880_2; +wire na1881_2; +wire na1882_2; +wire na1883_2; +wire na1884_2; +wire na1885_2; +wire na1886_2; +wire na1887_2; +wire na1888_2; +wire na1889_2; +wire na1890_2; +wire na1891_2; +wire na1892_2; +wire na1893_2; +wire na1894_2; +wire na1895_2; +wire na1896_2; +wire na1897_2; +wire na1898_2; +wire na1899_2; +wire na1900_2; +wire na1901_2; +wire na1902_2; +wire na1903_2; +wire na1904_2; +wire na1905_2; +wire na1906_2; +wire na1907_2; +wire na1908_2; +wire na1909_2; +wire na1910_2; +wire na1911_2; +wire na1912_2; +wire na1913_2; +wire na1914_2; +wire na1915_2; +wire na1916_2; +wire na1917_2; +wire na1918_2; +wire na1919_2; +wire na1920_2; +wire na1921_2; +wire na1922_2; +wire na1923_2; +wire na1924_2; +wire na1925_2; +wire na1926_2; +wire na1927_2; +wire na1928_2; +wire na1929_2; +wire na1930_2; +wire na1931_2; +wire na1932_2; +wire na1933_2; +wire na1934_2; +wire na1935_2; +wire na1936_2; +wire na1937_2; +wire na1938_2; +wire na1939_2; +wire na1940_2; +wire na1941_2; +wire na1942_2; +wire na1943_2; +wire na1944_2; +wire na1945_2; +wire na1946_2; +wire na1947_2; +wire na1948_2; +wire na1949_2; +wire na1950_2; +wire na1951_2; +wire na1952_2; +wire na1953_2; +wire na1954_2; +wire na1955_2; +wire na1956_2; +wire na1957_2; +wire na1958_2; +wire na1959_2; +wire na1960_2; +wire na1961_2; +wire na1962_2; +wire na1963_2; +wire na1964_2; +wire na1965_2; +wire na1966_2; +wire na1967_2; +wire na1968_2; +wire na1969_2; +wire na1970_2; +wire na1971_2; +wire na1972_2; +wire na1973_2; +wire na1974_2; +wire na1975_2; +wire na1976_2; +wire na1977_2; +wire na1978_2; +wire na1979_2; +wire na1980_2; +wire na1981_2; +wire na1982_2; +wire na1983_2; +wire na1984_2; +wire na1985_2; +wire na1986_2; +wire na1987_2; +wire na1988_2; +wire na1989_2; +wire na1990_2; +wire na1991_2; +wire na1992_2; +wire na1993_2; +wire na1994_2; +wire na1995_2; +wire na1996_2; +wire na1997_2; +wire na1998_2; +wire na1999_2; +wire na2000_2; +wire na2001_2; +wire na2002_2; +wire na2003_2; +wire na2004_2; +wire na2005_2; +wire na2006_2; +wire na2007_2; +wire na2008_2; +wire na2009_2; +wire na2010_2; +wire na2011_2; +wire na2012_2; +wire na2013_2; +wire na2014_2; +wire na2015_2; +wire na2016_2; +wire na2017_2; +wire na2018_2; +wire na2019_2; +wire na2020_2; +wire na2021_2; +wire na2022_2; +wire na2023_2; +wire na2024_2; +wire na2025_2; +wire na2026_2; +wire na2027_2; +wire na2028_2; +wire na2029_2; +wire na2030_2; +wire na2031_2; +wire na2032_2; +wire na2033_2; +wire na2034_2; +wire na2035_2; +wire na2036_2; +wire na2037_2; +wire na2038_2; +wire na2039_2; +wire na2040_2; +wire na2041_2; +wire na2042_2; +wire na2043_2; +wire na2044_2; +wire na2045_2; +wire na2046_2; +wire na2047_2; +wire na2048_2; +wire na2049_2; +wire na2050_2; +wire na2051_2; +wire na2052_2; +wire na2053_2; +wire na2054_2; +wire na2055_2; +wire na2056_2; +wire na2057_2; +wire na2058_2; +wire na2059_2; +wire na2060_2; +wire na2061_2; +wire na2062_2; +wire na2063_2; +wire na2064_2; +wire na2065_2; +wire na2066_2; +wire na2067_2; +wire na2068_2; +wire na2069_2; +wire na2070_2; +wire na2071_2; +wire na2072_2; +wire na2073_2; +wire na2074_2; +wire na2075_2; +wire na2076_2; +wire na2077_2; +wire na2078_2; +wire na2079_2; +wire na2080_2; +wire na2081_2; +wire na2082_2; +wire na2083_2; +wire na2084_2; +wire na2085_2; +wire na2086_2; +wire na2087_2; +wire na2088_2; +wire na2089_2; +wire na2090_2; +wire na2091_2; +wire na2092_2; +wire na2093_2; +wire na2094_2; +wire na2095_2; +wire na2096_2; +wire na2097_2; +wire na2098_2; +wire na2099_2; +wire na2100_2; +wire na2101_2; +wire na2102_2; +wire na2103_2; +wire na2104_2; +wire na2105_2; +wire na2106_2; +wire na2107_2; +wire na2108_2; +wire na2109_2; +wire na2110_2; +wire na2111_2; +wire na2112_2; +wire na2113_2; +wire na2114_2; +wire na2115_2; +wire na2116_2; +wire mem_rbusy; +wire mem_rstrb; +wire mem_wbusy; +wire na1213_10; +wire na1213_11; +wire na1213_12; +wire na1213_13; +wire na1213_14; +wire na1213_15; +wire na1213_16; +wire na1213_17; +wire na1213_18; +wire na1213_19; +wire na1213_20; +wire na1213_89; +wire na1213_90; +wire na1213_91; +wire na1213_92; +wire na1213_93; +wire na1213_94; +wire na1213_95; +wire na1213_96; +wire na1213_97; +wire na1213_98; +wire na1213_99; +wire na1214_21; +wire na1214_22; +wire na1214_23; +wire na1214_24; +wire na1214_25; +wire na1214_26; +wire na1214_27; +wire na1214_28; +wire na1214_29; +wire na1214_30; +wire na1214_31; +wire na1214_32; +wire na1214_33; +wire na1214_34; +wire na1214_35; +wire na1214_36; +wire na1214_37; +wire na1214_38; +wire na1214_39; +wire na1214_40; +wire na1217_10; +wire na1219_10; +wire na1230_10; +wire na1237_10; +wire na1241_10; +wire na1245_10; +wire na1247_10; +wire na1250_10; +wire na1253_10; +wire na1255_10; +wire na1258_10; +wire na1261_10; +wire na1263_10; +wire na1266_10; +wire na1269_10; +wire na1271_10; +wire na1274_10; +wire na1277_10; +wire na1279_10; +wire na1282_10; +wire na1285_10; +wire na1287_10; +wire na1290_10; +wire na1293_10; +wire na1295_10; +wire na1298_10; +wire na1301_10; +wire na1303_10; +wire na1306_10; +wire na1309_10; +wire na1311_10; +wire na1314_10; +wire na1317_10; +wire na1319_10; +wire na1322_10; +wire na1324_10; +wire na1328_10; +wire na1335_10; +wire na1338_10; +wire na1340_10; +wire na1344_10; +wire na1354_10; +wire na1360_10; +wire na1367_10; +wire na1369_10; +wire na1373_10; +wire na1380_10; +wire na1385_10; +wire na1388_10; +wire na1398_10; +wire na1404_10; +wire na1406_10; +wire na1416_10; +wire na1423_10; +wire na1430_10; +wire na1436_10; +wire na1447_10; +wire na1454_10; +wire na1459_10; +wire na1468_10; +wire na1475_10; +wire na1480_10; +wire na1491_10; +wire na1493_10; +wire na1497_10; +wire na1504_10; +wire na1510_10; +wire na1516_10; +wire na1518_10; +wire na1520_10; +wire na1526_10; +wire na1533_10; +wire na1535_10; +wire na1540_10; +wire na1797_10; +wire na1798_10; +wire na1799_10; +wire na1800_10; +wire na1801_10; +wire na1802_10; +wire na1803_10; +wire na1804_10; +wire na1805_10; +wire na1806_10; +wire na1807_10; +wire na1808_10; +wire na1809_10; +wire na1810_10; +wire na1811_10; +wire na1812_10; +wire na1813_10; +wire na1814_10; +wire na1815_10; +wire na1816_10; +wire na1817_10; +wire na1818_10; +wire na1819_10; +wire na1820_10; +wire na1821_10; +wire na1822_10; +wire na1823_10; +wire na1824_10; +wire na1825_10; +wire na1826_10; +wire na1827_10; +wire na1828_10; +wire na1829_10; +wire na1830_10; +wire na1831_10; +wire na1832_10; +wire na1833_10; +wire na1834_10; +wire na1835_10; +wire na1836_10; +wire na1837_10; +wire na1838_10; +wire na1839_10; +wire na1840_10; +wire na1841_10; +wire na1842_10; +wire na1843_10; +wire na1844_10; +wire na1845_10; +wire na1846_10; +wire na1847_10; +wire na1848_10; +wire na1849_10; +wire na1850_10; +wire na1851_10; +wire na1852_10; +wire na1853_10; +wire na1854_10; +wire na1855_10; +wire na1856_10; +wire na1857_10; +wire na1858_10; +wire na1859_10; +wire na1860_10; +wire na1861_10; +wire na1862_10; +wire na1863_10; +wire na1864_10; +wire na1865_10; +wire na1213_100; +wire na1214_109; +wire na1214_110; +wire na1214_111; +wire na1214_112; +wire na1214_113; +wire na1214_114; +wire na1214_115; +wire na1214_116; +wire na1214_117; +wire na1214_118; +wire na1214_119; +wire na1214_120; + +// C_///AND/ x94y67 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1_4 ( .OUT(na1_2), .IN1(1'b1), .IN2(na1212_1), .IN3(~na240_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y63 80'h00_0018_00_0000_0C88_ECFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a2_1 ( .OUT(na2_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na1212_1), .IN7(na1866_2), .IN8(na1216_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x85y71 80'h00_0060_00_0000_0C08_FFCE +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a3_4 ( .OUT(na3_2), .IN1(na1141_1), .IN2(na1175_1), .IN3(1'b0), .IN4(na241_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y72 80'h00_0018_00_0040_0A55_0080 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a4_1 ( .OUT(na4_1), .IN1(1'b0), .IN2(1'b0), .IN3(na6_1), .IN4(na5_1), .IN5(~na1058_2), .IN6(1'b0), .IN7(~na1302_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x86y68 80'h00_0078_00_0000_0C88_C1A3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a5_1 ( .OUT(na5_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1053_2), .IN6(~na1054_1), .IN7(1'b1), .IN8(na1056_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a5_4 ( .OUT(na5_2), .IN1(1'b1), .IN2(~na1054_1), .IN3(na1055_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_XOR//// x82y67 80'h00_0018_00_0000_0C66_AA00 +C_XOR #(.CPE_CFG (9'b0_0000_0000)) + _a6_1 ( .OUT(na6_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2019_2), .IN6(1'b0), .IN7(na1055_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y68 80'h00_0018_00_0040_0A55_0080 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a7_1 ( .OUT(na7_1), .IN1(1'b0), .IN2(1'b0), .IN3(na6_1), .IN4(na5_1), .IN5(~na1059_2), .IN6(1'b0), .IN7(~na1301_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y68 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a8_1 ( .OUT(na8_1), .IN1(1'b1), .IN2(na9_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1060_2), .IN8(~na1299_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x71y62 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a9_4 ( .OUT(na9_2), .IN1(1'b1), .IN2(1'b1), .IN3(na6_1), .IN4(na5_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), .CINX(1'b0), + .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y67 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a10_1 ( .OUT(na10_1), .IN1(1'b1), .IN2(na9_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na2027_2), .IN8(~na1298_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y64 80'h00_0018_00_0040_0A55_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a11_1 ( .OUT(na11_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1874_2), .IN5(~na1062_2), .IN6(1'b0), .IN7(~na1297_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x75y58 80'h00_0018_00_0040_0CCC_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a12_1 ( .OUT(na12_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na1295_2), .IN4(~na2041_2), .IN5(1'b1), .IN6(~na9_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y64 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a13_1 ( .OUT(na13_1), .IN1(1'b1), .IN2(na9_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na2039_2), .IN8(~na1294_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x75y59 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a14_1 ( .OUT(na14_1), .IN1(1'b1), .IN2(na9_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na2043_2), .IN8(~na1293_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y66 80'h00_0018_00_0040_0A55_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a15_1 ( .OUT(na15_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1874_2), .IN5(~na1079_1), .IN6(1'b0), .IN7(~na1291_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y66 80'h00_0018_00_0040_0A55_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a16_1 ( .OUT(na16_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1874_2), .IN5(~na1081_2), .IN6(1'b0), .IN7(~na1290_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x71y66 80'h00_0018_00_0040_0CCC_FC00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a17_1 ( .OUT(na17_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na2044_2), .IN4(~na1289_1), .IN5(1'b1), .IN6(na9_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y62 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a18_1 ( .OUT(na18_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1287_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x77y71 80'h00_0018_00_0040_0C33_0300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a19_1 ( .OUT(na19_1), .IN1(~na2056_2), .IN2(~na1063_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na9_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y68 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a20_1 ( .OUT(na20_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na2055_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y67 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a21_1 ( .OUT(na21_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1283_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y67 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a22_1 ( .OUT(na22_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1282_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y61 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a23_1 ( .OUT(na23_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na2051_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x68y64 80'h00_0018_00_0040_0C33_0300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a24_1 ( .OUT(na24_1), .IN1(~na2050_2), .IN2(~na1063_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na9_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y70 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a25_1 ( .OUT(na25_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1278_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x73y70 80'h00_0018_00_0040_0C33_0300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a26_1 ( .OUT(na26_1), .IN1(~na2047_2), .IN2(~na1063_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na9_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y67 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a27_1 ( .OUT(na27_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na2072_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x68y66 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a28_1 ( .OUT(na28_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na2070_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x63y65 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a29_1 ( .OUT(na29_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1315_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x63y66 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a30_1 ( .OUT(na30_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1314_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x74y70 80'h00_0018_00_0040_0C33_0300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a31_1 ( .OUT(na31_1), .IN1(~na2066_2), .IN2(~na1063_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na9_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x63y67 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a32_1 ( .OUT(na32_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na2065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x63y68 80'h00_0018_00_0040_0C33_0300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a33_1 ( .OUT(na33_1), .IN1(~na2064_2), .IN2(~na1063_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na9_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x69y73 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a34_1 ( .OUT(na34_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1309_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y73 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a35_1 ( .OUT(na35_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na2063_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y72 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a36_1 ( .OUT(na36_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na2062_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y70 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a37_1 ( .OUT(na37_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1874_2), .IN5(1'b0), .IN6(~na1063_2), .IN7(1'b0), .IN8(~na1305_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x79y71 80'h00_0018_00_0040_0CAA_8F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a38_1 ( .OUT(na38_1), .IN1(1'b0), .IN2(~na1063_2), .IN3(1'b0), .IN4(~na1303_2), .IN5(1'b1), .IN6(1'b1), .IN7(na6_1), .IN8(na5_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x77y62 80'h00_0018_00_0000_0888_BFE5 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a39_1 ( .OUT(na39_1), .IN1(~na1220_1), .IN2(1'b0), .IN3(na240_2), .IN4(na241_1), .IN5(1'b1), .IN6(1'b1), .IN7(na1055_1), + .IN8(~na5_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +CLKIN #(.CLKIN_CFG (32'h0000_0000)) + _a40 ( .PCLK0(na40_1), .PCLK1(_d0), .PCLK2(_d1), .PCLK3(_d2), .CLK0(na1108_1), .CLK1(1'b0), .CLK2(1'b0), .CLK3(1'b0), .SER_CLK(1'b0), + .SPI_CLK(1'b0), .JTAG_CLK(1'b0) ); +// C_ORAND/D/// x92y69 80'h00_FE00_00_0000_0C88_CDFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a42_1 ( .OUT(na42_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na46_1), .IN6(na1228_2), .IN7(1'b0), .IN8(na1212_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a42_2 ( .OUT(na42_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na42_1_i) ); +// C_AND///AND/ x84y70 80'h00_0078_00_0000_0C88_54C3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a44_1 ( .OUT(na44_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1053_2), .IN6(na1902_2), .IN7(~na1055_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a44_4 ( .OUT(na44_2), .IN1(1'b1), .IN2(~na1054_1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x87y67 80'h00_0018_00_0000_0C88_53FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a45_1 ( .OUT(na45_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1054_1), .IN7(~na1055_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y61 80'h00_0018_00_0040_0A55_0050 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a46_1 ( .OUT(na46_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na42_1), .IN4(1'b1), .IN5(~na1141_1), .IN6(1'b0), .IN7(~na1218_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/D x77y69 80'h00_F600_80_0000_0C08_FF38 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a47_4 ( .OUT(na47_2_i), .IN1(na47_2), .IN2(na1212_1), .IN3(1'b1), .IN4(~na44_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a47_5 ( .OUT(na47_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na47_2_i) ); +// C_AND///AND/ x86y64 80'h00_0078_00_0000_0C88_8285 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a49_1 ( .OUT(na49_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1053_2), .IN6(~na2020_2), .IN7(na1055_2), .IN8(na1056_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a49_4 ( .OUT(na49_2), .IN1(~na2019_2), .IN2(1'b1), .IN3(na1055_2), .IN4(na5_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/D/// x88y72 80'h00_F600_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a50_1 ( .OUT(na50_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1212_1), .IN7(1'b1), .IN8(na241_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a50_2 ( .OUT(na50_1), .CLK(na1018_1), .EN(~na2_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na50_1_i) ); +// C_MX2a//// x82y79 80'h00_0018_00_0040_0C45_1000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a75_1 ( .OUT(na75_1), .IN1(na47_2), .IN2(1'b0), .IN3(~na76_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na42_1), .IN8(~na50_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x82y75 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a76_1 ( .OUT(na76_1), .IN1(1'b1), .IN2(na1228_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na883_1), .IN8(~na2046_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x84y81 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a77_1 ( .OUT(na77_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na1913_2), .IN7(~na1229_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x81y69 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a78_1 ( .OUT(na78_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na44_2), .IN5(1'b0), .IN6(~na952_2), .IN7(1'b0), .IN8(~na79_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x88y64 80'h00_0018_00_0040_0A30_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a79_1 ( .OUT(na79_1), .IN1(~na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na1912_2), .IN6(na929_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x91y67 80'h00_0018_00_0040_0C8A_3F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a80_1 ( .OUT(na80_1), .IN1(1'b0), .IN2(na1231_1), .IN3(1'b0), .IN4(~na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(~na49_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x92y82 80'h00_0018_00_0040_0A55_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a81_1 ( .OUT(na81_1), .IN1(na84_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1243_1), .IN5(~na85_1), .IN6(1'b0), .IN7(~na1905_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x80y69 80'h00_0060_00_0000_0C08_FFC1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a83_4 ( .OUT(na83_2), .IN1(~na1064_1), .IN2(~na1063_1), .IN3(1'b1), .IN4(na1065_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x73y63 80'h00_0078_00_0000_0C88_C8A3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a84_1 ( .OUT(na84_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1064_1), .IN6(na1063_1), .IN7(1'b1), .IN8(na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a84_4 ( .OUT(na84_2), .IN1(1'b1), .IN2(~na349_1), .IN3(na83_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x71y61 80'h00_0018_00_0000_0C88_C2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a85_1 ( .OUT(na85_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(1'b1), .IN8(na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x91y62 80'h00_0018_00_0040_0AAA_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a86_1 ( .OUT(na86_1), .IN1(1'b1), .IN2(~na101_2), .IN3(na90_1), .IN4(1'b1), .IN5(1'b0), .IN6(~na101_1), .IN7(1'b0), .IN8(~na102_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x79y64 80'h00_0018_00_0000_0C88_F4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a89_1 ( .OUT(na89_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(na1063_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x68y63 80'h00_0018_00_0000_0888_8888 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a90_1 ( .OUT(na90_1), .IN1(na99_1), .IN2(na92_1), .IN3(na97_1), .IN4(na100_1), .IN5(na99_2), .IN6(na92_2), .IN7(na97_2), + .IN8(na100_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x67y62 80'h00_0078_00_0000_0C88_1111 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a92_1 ( .OUT(na92_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2008_2), .IN6(~na2009_2), .IN7(~na998_2), + .IN8(~na996_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a92_4 ( .OUT(na92_2), .IN1(~na2006_2), .IN2(~na2007_2), .IN3(~na993_2), .IN4(~na991_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x72y61 80'h00_0078_00_0000_0C88_1111 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a97_1 ( .OUT(na97_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2015_2), .IN6(~na2016_2), .IN7(~na1013_2), + .IN8(~na1011_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a97_4 ( .OUT(na97_2), .IN1(~na2012_2), .IN2(~na2014_2), .IN3(~na1007_2), .IN4(~na1004_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x67y65 80'h00_0078_00_0000_0C88_1111 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a99_1 ( .OUT(na99_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2004_2), .IN6(~na2005_2), .IN7(~na989_2), + .IN8(~na987_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a99_4 ( .OUT(na99_2), .IN1(~na2010_2), .IN2(~na2011_2), .IN3(~na1002_2), .IN4(~na1000_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x72y60 80'h00_0078_00_0000_0C88_1111 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a100_1 ( .OUT(na100_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2017_2), .IN6(~na2003_2), .IN7(~na985_2), + .IN8(~na1015_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a100_4 ( .OUT(na100_2), .IN1(~na2002_2), .IN2(~na2013_2), .IN3(~na1006_2), .IN4(~na984_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x79y66 80'h00_0078_00_0000_0C88_34CC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a101_1 ( .OUT(na101_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(na1063_1), .IN7(1'b1), .IN8(~na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a101_4 ( .OUT(na101_2), .IN1(1'b1), .IN2(na349_1), .IN3(1'b1), .IN4(na102_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x80y70 80'h00_0078_00_0000_0C88_31CC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a102_1 ( .OUT(na102_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(~na1063_1), .IN7(1'b1), .IN8(~na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a102_4 ( .OUT(na102_2), .IN1(1'b1), .IN2(na89_1), .IN3(1'b1), .IN4(na1065_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x94y82 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a106_1 ( .OUT(na106_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na1916_2), .IN7(1'b0), .IN8(~na1236_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x87y71 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a107_1 ( .OUT(na107_1), .IN1(1'b1), .IN2(~na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na974_1), .IN6(~na108_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x95y60 80'h00_0018_00_0040_0A32_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a108_1 ( .OUT(na108_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na940_1), .IN6(~na1916_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x100y81 80'h00_0060_00_0000_0C08_FF3B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a111_4 ( .OUT(na111_2), .IN1(na1235_2), .IN2(~na249_1), .IN3(1'b0), .IN4(~na1240_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x89y65 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a112_1 ( .OUT(na112_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na44_2), .IN5(~na974_2), .IN6(1'b0), .IN7(~na113_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x92y63 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a113_1 ( .OUT(na113_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na2001_2), .IN6(na918_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x100y55 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a116_1 ( .OUT(na116_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na1915_2), .IN7(1'b0), .IN8(~na1244_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x87y63 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a117_1 ( .OUT(na117_1), .IN1(1'b1), .IN2(na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na118_1), .IN6(~na978_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x95y57 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a118_1 ( .OUT(na118_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na945_1), .IN6(na918_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x100y59 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a121_4 ( .OUT(na121_2), .IN1(na1235_2), .IN2(~na252_2), .IN3(~na1248_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x85y61 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a122_1 ( .OUT(na122_1), .IN1(1'b1), .IN2(na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na123_1), .IN6(~na978_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x89y69 80'h00_0018_00_0040_0A30_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a123_1 ( .OUT(na123_1), .IN1(~na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na922_1), .IN6(na946_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x100y57 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a126_1 ( .OUT(na126_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na252_1), .IN7(~na1252_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x85y59 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a127_1 ( .OUT(na127_1), .IN1(1'b1), .IN2(~na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na980_1), .IN6(~na128_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x97y68 80'h00_0018_00_0040_0A30_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a128_1 ( .OUT(na128_1), .IN1(~na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na922_2), .IN6(na946_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x98y59 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a131_4 ( .OUT(na131_2), .IN1(na1235_2), .IN2(~na254_2), .IN3(~na1256_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y69 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a132_1 ( .OUT(na132_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na44_2), .IN5(~na980_2), .IN6(1'b0), .IN7(~na133_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x96y67 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a133_1 ( .OUT(na133_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na948_1), .IN6(na924_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x100y59 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a136_1 ( .OUT(na136_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na254_1), .IN7(1'b0), .IN8(~na1260_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x91y73 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a137_1 ( .OUT(na137_1), .IN1(1'b1), .IN2(na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na138_1), .IN6(~na982_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x97y65 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a138_1 ( .OUT(na138_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na948_2), .IN6(na924_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x100y63 80'h00_0060_00_0000_0C08_FF3B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a141_4 ( .OUT(na141_2), .IN1(na1235_2), .IN2(~na256_2), .IN3(1'b0), .IN4(~na1264_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x89y73 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a142_1 ( .OUT(na142_1), .IN1(1'b1), .IN2(na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na143_1), .IN6(~na982_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x97y69 80'h00_0018_00_0040_0A30_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a143_1 ( .OUT(na143_1), .IN1(~na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na926_1), .IN6(na950_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y76 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a146_1 ( .OUT(na146_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na256_1), .IN7(1'b0), .IN8(~na1268_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x87y69 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a147_1 ( .OUT(na147_1), .IN1(1'b1), .IN2(~na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na953_1), .IN6(~na148_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x95y58 80'h00_0018_00_0040_0A30_0005 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a148_1 ( .OUT(na148_1), .IN1(~na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na926_2), .IN6(na950_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x84y81 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a151_4 ( .OUT(na151_2), .IN1(na1235_2), .IN2(~na258_2), .IN3(~na1272_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y67 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a152_1 ( .OUT(na152_1), .IN1(1'b1), .IN2(~na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na953_2), .IN6(~na153_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x97y66 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a153_1 ( .OUT(na153_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na930_1), .IN6(na928_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x90y82 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a156_1 ( .OUT(na156_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na258_1), .IN7(~na1276_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y73 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a157_1 ( .OUT(na157_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na44_2), .IN5(1'b0), .IN6(~na955_1), .IN7(1'b0), .IN8(~na158_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x90y70 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a158_1 ( .OUT(na158_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na1998_2), .IN6(na928_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x86y81 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a161_4 ( .OUT(na161_2), .IN1(na1235_2), .IN2(~na1920_2), .IN3(~na1280_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x81y75 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a162_1 ( .OUT(na162_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na44_2), .IN5(1'b0), .IN6(~na955_2), .IN7(1'b0), .IN8(~na163_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x92y70 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a163_1 ( .OUT(na163_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na932_1), .IN6(na1995_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x75y54 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a166_1 ( .OUT(na166_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na1919_2), .IN7(~na1284_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x83y77 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a167_1 ( .OUT(na167_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na44_2), .IN5(~na957_1), .IN6(1'b0), .IN7(~na168_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x86y69 80'h00_0018_00_0040_0C03_0500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a168_1 ( .OUT(na168_1), .IN1(na909_2), .IN2(na933_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na80_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x93y80 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a171_1 ( .OUT(na171_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na262_2), .IN7(~na1288_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x83y75 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a172_1 ( .OUT(na172_1), .IN1(1'b1), .IN2(~na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na957_2), .IN6(~na173_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x91y72 80'h00_0018_00_0040_0C03_0A00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a173_1 ( .OUT(na173_1), .IN1(na934_1), .IN2(na911_1), .IN3(1'b0), .IN4(1'b0), .IN5(na80_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y81 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a176_1 ( .OUT(na176_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na262_1), .IN7(1'b0), .IN8(~na1292_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y77 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a177_1 ( .OUT(na177_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na44_2), .IN5(1'b0), .IN6(~na959_1), .IN7(1'b0), .IN8(~na178_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x94y70 80'h00_0018_00_0040_0C03_0A00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a178_1 ( .OUT(na178_1), .IN1(na1999_2), .IN2(na911_2), .IN3(1'b0), .IN4(1'b0), .IN5(na80_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x87y82 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a181_4 ( .OUT(na181_2), .IN1(na1235_2), .IN2(~na264_2), .IN3(~na1296_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x89y75 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a182_1 ( .OUT(na182_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na44_2), .IN5(1'b0), .IN6(~na959_2), .IN7(1'b0), .IN8(~na183_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x92y72 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a183_1 ( .OUT(na183_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na936_1), .IN6(na1996_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y82 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a186_1 ( .OUT(na186_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na264_1), .IN7(1'b0), .IN8(~na1300_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x91y75 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a187_1 ( .OUT(na187_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na44_2), .IN5(~na961_1), .IN6(1'b0), .IN7(~na188_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x94y71 80'h00_0018_00_0040_0C03_0500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a188_1 ( .OUT(na188_1), .IN1(na913_2), .IN2(na937_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na80_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x89y81 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a191_4 ( .OUT(na191_2), .IN1(na1235_2), .IN2(~na266_2), .IN3(~na1304_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x91y77 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a192_1 ( .OUT(na192_1), .IN1(1'b1), .IN2(~na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na961_2), .IN6(~na193_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x91y74 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a193_1 ( .OUT(na193_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na938_1), .IN6(na915_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x99y81 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a196_1 ( .OUT(na196_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na266_1), .IN7(~na1308_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x87y79 80'h00_0018_00_0040_0AAA_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a197_1 ( .OUT(na197_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na44_2), .IN5(1'b0), .IN6(~na964_1), .IN7(1'b0), .IN8(~na198_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x94y72 80'h00_0018_00_0040_0C03_0A00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a198_1 ( .OUT(na198_1), .IN1(na2000_2), .IN2(na915_2), .IN3(1'b0), .IN4(1'b0), .IN5(na80_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x98y81 80'h00_0060_00_0000_0C08_FF5B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a201_4 ( .OUT(na201_2), .IN1(na1235_2), .IN2(~na268_2), .IN3(~na1312_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x93y77 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a202_1 ( .OUT(na202_1), .IN1(1'b1), .IN2(na1899_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na203_1), .IN6(~na964_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x95y75 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a203_1 ( .OUT(na203_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na941_1), .IN6(na1997_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x100y81 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a206_1 ( .OUT(na206_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1235_2), .IN6(~na268_1), .IN7(1'b0), .IN8(~na1316_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x85y79 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a207_1 ( .OUT(na207_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na44_2), .IN5(~na966_1), .IN6(1'b0), .IN7(~na208_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x96y75 80'h00_0018_00_0040_0C03_0500 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a208_1 ( .OUT(na208_1), .IN1(na917_2), .IN2(na942_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na80_1), .IN6(1'b1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x99y81 80'h00_0060_00_0000_0C08_FF3B +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a211_4 ( .OUT(na211_2), .IN1(na1235_2), .IN2(~na269_2), .IN3(1'b0), .IN4(~na1320_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x89y77 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a212_1 ( .OUT(na212_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na44_2), .IN5(~na966_2), .IN6(1'b0), .IN7(~na213_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x96y71 80'h00_0018_00_0040_0A30_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a213_1 ( .OUT(na213_1), .IN1(na80_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(na943_1), .IN6(na920_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y61 80'h00_0018_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a216_1 ( .OUT(na216_1), .IN1(1'b1), .IN2(~na1970_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1302_1), .IN8(na2061_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x63y63 80'h00_0018_00_0040_0C05_A000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a217_1 ( .OUT(na217_1), .IN1(na2060_2), .IN2(1'b0), .IN3(na1301_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na883_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x75y46 80'h00_0018_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a218_1 ( .OUT(na218_1), .IN1(1'b1), .IN2(na1970_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na2059_2), .IN8(na1299_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x77y46 80'h00_0018_00_0040_0C0A_AF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a219_1 ( .OUT(na219_1), .IN1(1'b0), .IN2(na2058_2), .IN3(1'b0), .IN4(na1298_2), .IN5(1'b1), .IN6(1'b1), .IN7(na883_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y47 80'h00_0018_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a220_1 ( .OUT(na220_1), .IN1(1'b1), .IN2(~na1970_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1297_1), .IN8(na2057_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x79y45 80'h00_0018_00_0040_0C05_A000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a221_1 ( .OUT(na221_1), .IN1(na2054_2), .IN2(1'b0), .IN3(na1295_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na883_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y46 80'h00_0018_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a222_1 ( .OUT(na222_1), .IN1(1'b1), .IN2(na1970_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na2053_2), .IN8(na1294_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x79y48 80'h00_0018_00_0040_0C0A_AF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a223_1 ( .OUT(na223_1), .IN1(1'b0), .IN2(na2052_2), .IN3(1'b0), .IN4(na1293_2), .IN5(1'b1), .IN6(1'b1), .IN7(na883_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x83y46 80'h00_0018_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a224_1 ( .OUT(na224_1), .IN1(1'b1), .IN2(~na1982_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1302_1), .IN8(na2051_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x86y46 80'h00_0018_00_0040_0C05_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a225_1 ( .OUT(na225_1), .IN1(na2050_2), .IN2(1'b0), .IN3(na1301_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x84y45 80'h00_0018_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a226_1 ( .OUT(na226_1), .IN1(1'b1), .IN2(na1982_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na2049_2), .IN8(na1299_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x66y51 80'h00_0018_00_0040_0C0A_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a227_1 ( .OUT(na227_1), .IN1(1'b0), .IN2(na2048_2), .IN3(1'b0), .IN4(na1298_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x66y47 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a228_1 ( .OUT(na228_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na894_1), .IN5(na2071_2), .IN6(1'b0), .IN7(na1297_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x66y52 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a229_1 ( .OUT(na229_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na894_1), .IN5(na2069_2), .IN6(1'b0), .IN7(na1295_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x68y53 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a230_1 ( .OUT(na230_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na894_1), .IN5(1'b0), .IN6(na2068_2), .IN7(1'b0), .IN8(na1294_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x66y54 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a231_1 ( .OUT(na231_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na894_1), .IN5(1'b0), .IN6(na2067_2), .IN7(1'b0), .IN8(na1293_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x67y55 80'h00_0018_00_0040_0C05_1000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a232_1 ( .OUT(na232_1), .IN1(na216_1), .IN2(1'b0), .IN3(na1313_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x66y56 80'h00_0018_00_0040_0C05_1000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a233_1 ( .OUT(na233_1), .IN1(na217_1), .IN2(1'b0), .IN3(na1311_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x67y54 80'h00_0018_00_0040_0C0A_1F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a234_1 ( .OUT(na234_1), .IN1(1'b0), .IN2(na218_1), .IN3(1'b0), .IN4(na1310_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x65y53 80'h00_0018_00_0040_0C0A_1F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a235_1 ( .OUT(na235_1), .IN1(1'b0), .IN2(na219_1), .IN3(1'b0), .IN4(na1309_2), .IN5(1'b1), .IN6(1'b1), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x66y53 80'h00_0018_00_0040_0C05_1000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a236_1 ( .OUT(na236_1), .IN1(na220_1), .IN2(1'b0), .IN3(na1307_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x65y55 80'h00_0018_00_0040_0C05_1000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a237_1 ( .OUT(na237_1), .IN1(na221_1), .IN2(1'b0), .IN3(na1306_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x65y59 80'h00_0018_00_0040_0C0A_1F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a238_1 ( .OUT(na238_1), .IN1(1'b0), .IN2(na222_1), .IN3(1'b0), .IN4(na1305_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x65y58 80'h00_0018_00_0040_0C0A_1F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a239_1 ( .OUT(na239_1), .IN1(1'b0), .IN2(na223_1), .IN3(1'b0), .IN4(na1303_2), .IN5(1'b1), .IN6(1'b1), .IN7(~na883_1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND////D x82y65 80'h00_FE18_00_0000_0888_AFF4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a240_1 ( .OUT(na240_1), .IN1(~na1141_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na42_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a240_5 ( .OUT(na240_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na240_1) ); +// C_ORAND*/D/// x82y68 80'h00_FE00_00_0000_0788_FC75 +C_ORAND #(.CPE_CFG (9'b1_0000_0000)) + _a241_1 ( .OUT(na241_1_i), .IN1(~na3_2), .IN2(1'b0), .IN3(~na240_2), .IN4(~na44_1), .IN5(1'b0), .IN6(na1212_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b1_0000_0000)) + _a241_2 ( .OUT(na241_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na241_1_i) ); +// C_///AND/D x88y65 80'h00_F600_80_0000_0C08_FFF4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a247_4 ( .OUT(na247_2_i), .IN1(~na78_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a247_5 ( .OUT(na247_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na247_2_i) ); +// C_AND/D/// x97y70 80'h00_F600_00_0000_0C88_F4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a249_1 ( .OUT(na249_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na112_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a249_2 ( .OUT(na249_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na249_1_i) ); +// C_AND/D//AND/D x90y64 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a250_1 ( .OUT(na250_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na117_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a250_2 ( .OUT(na250_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na250_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a250_4 ( .OUT(na250_2_i), .IN1(~na107_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a250_5 ( .OUT(na250_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na250_2_i) ); +// C_AND/D//AND/D x97y62 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a252_1 ( .OUT(na252_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na127_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a252_2 ( .OUT(na252_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na252_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a252_4 ( .OUT(na252_2_i), .IN1(~na122_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a252_5 ( .OUT(na252_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na252_2_i) ); +// C_AND/D//AND/D x97y64 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a254_1 ( .OUT(na254_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na137_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a254_2 ( .OUT(na254_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na254_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a254_4 ( .OUT(na254_2_i), .IN1(~na132_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a254_5 ( .OUT(na254_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na254_2_i) ); +// C_AND/D//AND/D x91y70 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a256_1 ( .OUT(na256_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na147_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a256_2 ( .OUT(na256_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na256_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a256_4 ( .OUT(na256_2_i), .IN1(~na142_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a256_5 ( .OUT(na256_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na256_2_i) ); +// C_AND/D//AND/D x89y76 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a258_1 ( .OUT(na258_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na157_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a258_2 ( .OUT(na258_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na258_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a258_4 ( .OUT(na258_2_i), .IN1(~na152_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a258_5 ( .OUT(na258_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na258_2_i) ); +// C_AND/D//AND/D x90y76 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a260_1 ( .OUT(na260_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na167_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a260_2 ( .OUT(na260_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na260_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a260_4 ( .OUT(na260_2_i), .IN1(~na162_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a260_5 ( .OUT(na260_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na260_2_i) ); +// C_AND/D//AND/D x93y76 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a262_1 ( .OUT(na262_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na177_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a262_2 ( .OUT(na262_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na262_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a262_4 ( .OUT(na262_2_i), .IN1(~na172_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a262_5 ( .OUT(na262_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na262_2_i) ); +// C_AND/D//AND/D x89y78 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a264_1 ( .OUT(na264_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na187_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a264_2 ( .OUT(na264_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na264_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a264_4 ( .OUT(na264_2_i), .IN1(~na182_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a264_5 ( .OUT(na264_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na264_2_i) ); +// C_AND/D//AND/D x91y78 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a266_1 ( .OUT(na266_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na197_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a266_2 ( .OUT(na266_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na266_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a266_4 ( .OUT(na266_2_i), .IN1(~na192_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a266_5 ( .OUT(na266_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na266_2_i) ); +// C_AND/D//AND/D x93y78 80'h00_F600_80_0000_0C88_F4F4 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a268_1 ( .OUT(na268_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na207_1), .IN6(na1212_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a268_2 ( .OUT(na268_1), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na268_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a268_4 ( .OUT(na268_2_i), .IN1(~na202_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a268_5 ( .OUT(na268_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na268_2_i) ); +// C_///AND/D x95y78 80'h00_F600_80_0000_0C08_FFF4 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a269_4 ( .OUT(na269_2_i), .IN1(~na212_1), .IN2(na1212_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a269_5 ( .OUT(na269_2), .CLK(na1018_1), .EN(~na1_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na269_2_i) ); +// C_ORAND//// x79y63 80'h00_0018_00_0000_0888_7DBD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a270_1 ( .OUT(na270_1), .IN1(~na47_2), .IN2(na2075_2), .IN3(na1326_1), .IN4(~na350_1), .IN5(~na1341_2), .IN6(na1342_1), .IN7(~na2018_2), + .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x68y67 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a272_1 ( .OUT(na272_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1496_1), .IN8(~na1497_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x63y69 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a273_1 ( .OUT(na273_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1493_2), .IN8(~na1503_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y69 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a274_1 ( .OUT(na274_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1504_2), .IN8(~na1492_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y70 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a275_1 ( .OUT(na275_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1509_1), .IN8(~na1491_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y74 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a276_1 ( .OUT(na276_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na277_1), .IN6(na280_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y65 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a277_1 ( .OUT(na277_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na278_1), .IN6(na279_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x61y69 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a278_1 ( .OUT(na278_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1484_1), .IN8(~na1510_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y74 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a279_1 ( .OUT(na279_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1480_2), .IN8(~na1514_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y68 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a280_1 ( .OUT(na280_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na281_1), .IN6(na282_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y65 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a281_1 ( .OUT(na281_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1516_2), .IN8(~na1478_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x63y72 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a282_1 ( .OUT(na282_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1517_1), .IN8(~na1475_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y72 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a283_1 ( .OUT(na283_1), .IN1(1'b1), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(na291_1), .IN6(na1931_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x81y65 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a284_1 ( .OUT(na284_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na285_1), .IN6(na288_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y71 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a285_1 ( .OUT(na285_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na286_1), .IN6(na287_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x63y61 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a286_1 ( .OUT(na286_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1474_1), .IN8(~na1518_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y66 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a287_1 ( .OUT(na287_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1468_2), .IN8(~na1519_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x69y74 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a288_1 ( .OUT(na288_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na289_1), .IN6(na290_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y67 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a289_1 ( .OUT(na289_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1520_2), .IN8(~na1463_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y68 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a290_1 ( .OUT(na290_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1525_1), .IN8(~na1459_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y65 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a291_1 ( .OUT(na291_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na292_1), .IN6(na295_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y73 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a292_1 ( .OUT(na292_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na293_1), .IN6(na294_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y69 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a293_1 ( .OUT(na293_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1455_1), .IN8(~na1430_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y70 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a294_1 ( .OUT(na294_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1454_2), .IN8(~na1433_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y76 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a295_1 ( .OUT(na295_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na296_1), .IN6(na297_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y73 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a296_1 ( .OUT(na296_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1436_2), .IN8(~na1452_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y74 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a297_1 ( .OUT(na297_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1442_1), .IN8(~na1447_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y72 80'h00_0018_00_0000_0C88_3EFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a298_1 ( .OUT(na298_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na314_2), .IN6(na299_2), .IN7(1'b0), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x81y66 80'h00_0060_00_0000_0C08_FF2F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a299_4 ( .OUT(na299_2), .IN1(1'b1), .IN2(1'b1), .IN3(na10_1), .IN4(~na516_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y76 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a300_1 ( .OUT(na300_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na7_1), .IN5(1'b0), .IN6(na304_1), .IN7(1'b0), .IN8(na301_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x68y72 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a301_1 ( .OUT(na301_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na302_1), .IN6(na1933_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y73 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a302_1 ( .OUT(na302_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1442_1), .IN8(~na1447_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y76 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a303_1 ( .OUT(na303_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1436_2), .IN8(~na1452_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y76 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a304_1 ( .OUT(na304_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1868_2), .IN5(na306_1), .IN6(1'b0), .IN7(na305_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x64y73 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a305_1 ( .OUT(na305_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1454_2), .IN8(~na1433_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x63y73 80'h00_0018_00_0040_0CCC_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a306_1 ( .OUT(na306_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na1455_1), .IN4(~na1430_2), .IN5(1'b1), .IN6(~na101_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y74 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a307_1 ( .OUT(na307_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na308_1), .IN6(na1935_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x77y73 80'h00_0018_00_0040_0C03_0C00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a308_1 ( .OUT(na308_1), .IN1(na310_1), .IN2(na309_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na4_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x65y62 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a309_1 ( .OUT(na309_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1525_1), .IN8(~na1459_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y77 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a310_1 ( .OUT(na310_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1520_2), .IN8(~na1463_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y75 80'h00_0018_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a311_1 ( .OUT(na311_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1868_2), .IN5(1'b0), .IN6(na312_1), .IN7(1'b0), .IN8(na313_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x69y78 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a312_1 ( .OUT(na312_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1468_2), .IN8(~na1519_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x70y76 80'h00_0018_00_0040_0CCC_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a313_1 ( .OUT(na313_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na1474_1), .IN4(~na1518_2), .IN5(1'b1), .IN6(~na101_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x87y67 80'h00_0060_00_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a314_4 ( .OUT(na314_2), .IN1(na315_2), .IN2(na322_1), .IN3(~na10_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x77y67 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a315_4 ( .OUT(na315_2), .IN1(1'b1), .IN2(na8_1), .IN3(na1332_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y73 80'h00_0018_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a316_1 ( .OUT(na316_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na317_1), .IN8(na318_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x70y77 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a317_1 ( .OUT(na317_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1517_1), .IN8(~na1475_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x70y78 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a318_1 ( .OUT(na318_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1516_2), .IN8(~na1478_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x72y76 80'h00_0018_00_0040_0C0C_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a319_1 ( .OUT(na319_1), .IN1(1'b0), .IN2(1'b0), .IN3(na320_1), .IN4(na321_1), .IN5(1'b1), .IN6(~na4_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x70y75 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a320_1 ( .OUT(na320_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1480_2), .IN8(~na1514_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y78 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a321_1 ( .OUT(na321_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1484_1), .IN8(~na1510_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x79y62 80'h00_0018_00_0000_0C88_E3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a322_1 ( .OUT(na322_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na8_1), .IN7(na326_1), .IN8(na323_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x78y78 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a323_1 ( .OUT(na323_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na406_1), .IN8(na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y75 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a324_1 ( .OUT(na324_1), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1509_1), .IN8(~na1491_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x70y74 80'h00_0018_00_0040_0CCC_FC00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a325_1 ( .OUT(na325_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na1504_2), .IN4(~na1492_1), .IN5(1'b1), .IN6(na101_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x80y61 80'h00_0018_00_0040_0ACC_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a326_1 ( .OUT(na326_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b1), .IN4(~na7_1), .IN5(1'b0), .IN6(1'b0), .IN7(~na328_1), .IN8(~na1939_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y67 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a327_1 ( .OUT(na327_1), .IN1(1'b1), .IN2(~na101_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na1496_1), .IN8(~na1497_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x72y65 80'h00_0018_00_0040_0CCC_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a328_1 ( .OUT(na328_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na1493_2), .IN4(~na1503_1), .IN5(1'b1), .IN6(~na101_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x82y70 80'h00_0018_00_0040_0A51_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a330_1 ( .OUT(na330_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na11_1), .IN5(~na333_2), .IN6(1'b0), .IN7(na331_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x86y65 80'h00_0018_00_0040_0C15_8000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a331_1 ( .OUT(na331_1), .IN1(~na333_2), .IN2(1'b0), .IN3(na332_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na10_1), .IN8(na1873_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x80y71 80'h00_0018_00_0040_0C15_8000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a332_1 ( .OUT(na332_1), .IN1(~na333_2), .IN2(1'b0), .IN3(na327_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1867_2), .IN8(na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x85y73 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a333_4 ( .OUT(na333_2), .IN1(na1081_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1497_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x79y61 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a334_1 ( .OUT(na334_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1336_1), .IN7(1'b1), .IN8(na102_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x74y62 80'h00_0018_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a335_1 ( .OUT(na335_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1081_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1056_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x74y61 80'h00_0018_00_0040_0A76_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a336_1 ( .OUT(na336_1), .IN1(1'b1), .IN2(~na2106_2), .IN3(1'b1), .IN4(na1868_2), .IN5(na85_1), .IN6(~na2074_2), .IN7(~na1337_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x81y58 80'h00_0018_00_0040_0AC0_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a342_1 ( .OUT(na342_1), .IN1(1'b1), .IN2(na1982_2), .IN3(1'b1), .IN4(na343_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1142_1), .IN8(na1150_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x80y62 80'h00_0018_00_0000_0C88_D5FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a343_1 ( .OUT(na343_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(1'b0), .IN7(~na883_1), .IN8(na2030_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x76y60 80'h00_0018_00_0040_0C55_3000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a344_1 ( .OUT(na344_1), .IN1(~na1159_1), .IN2(1'b0), .IN3(~na1172_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x84y61 80'h00_0018_00_0000_0C88_18FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a346_1 ( .OUT(na346_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1053_2), .IN6(na1870_2), .IN7(~na1055_2), + .IN8(~na1056_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x84y58 80'h00_0078_00_0000_0C88_123C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a348_1 ( .OUT(na348_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1064_1), .IN6(~na349_1), .IN7(~na2029_2), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a348_4 ( .OUT(na348_2), .IN1(1'b1), .IN2(na101_1), .IN3(1'b1), .IN4(~na330_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x63y74 80'h00_0018_00_0040_0CB9_3500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a349_1 ( .OUT(na349_1), .IN1(~na2107_2), .IN2(1'b1), .IN3(1'b0), .IN4(~na1497_2), .IN5(~na38_1), .IN6(1'b1), .IN7(1'b1), + .IN8(~na1243_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x82y62 80'h00_0078_00_0000_0C88_458A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a350_1 ( .OUT(na350_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1053_2), .IN6(1'b1), .IN7(~na1055_2), .IN8(na5_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a350_4 ( .OUT(na350_2), .IN1(na2019_2), .IN2(1'b1), .IN3(na1055_2), .IN4(na5_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x74y59 80'h00_0018_00_0000_0EEE_5CDA +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a351_1 ( .OUT(na351_1), .IN1(na1357_2), .IN2(1'b0), .IN3(~na1356_1), .IN4(na1361_2), .IN5(1'b0), .IN6(na1346_2), .IN7(~na1356_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y70 80'h00_0018_00_0000_0888_CFB5 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a352_1 ( .OUT(na352_1), .IN1(~na364_1), .IN2(1'b0), .IN3(na1734_2), .IN4(~na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y68 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a353_1 ( .OUT(na353_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na281_1), .IN6(na279_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y72 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a354_1 ( .OUT(na354_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na286_1), .IN6(na282_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x69y75 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a355_1 ( .OUT(na355_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na274_1), .IN6(~na1930_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y68 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a356_1 ( .OUT(na356_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na278_1), .IN6(na275_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x83y80 80'h00_0018_00_0040_0AC0_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a357_1 ( .OUT(na357_1), .IN1(1'b1), .IN2(na8_1), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na361_1), .IN8(na358_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y80 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a358_1 ( .OUT(na358_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na359_1), .IN6(na360_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y71 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a359_1 ( .OUT(na359_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na289_1), .IN6(na287_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y72 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a360_1 ( .OUT(na360_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na293_1), .IN6(na290_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y81 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a361_1 ( .OUT(na361_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na362_1), .IN6(na363_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x71y77 80'h00_0018_00_0040_0C03_0C00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a362_1 ( .OUT(na362_1), .IN1(na296_1), .IN2(na294_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na4_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y80 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a363_1 ( .OUT(na363_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na302_1), .IN6(na297_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x91y79 80'h00_0018_00_0000_0888_3FDE +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a364_1 ( .OUT(na364_1), .IN1(na1875_2), .IN2(na1350_1), .IN3(~na10_1), .IN4(na1348_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), + .IN8(~na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y80 80'h00_0018_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a367_1 ( .OUT(na367_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na305_1), .IN8(na303_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y79 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a368_1 ( .OUT(na368_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na306_1), .IN6(na309_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x76y81 80'h00_0018_00_0040_0ACC_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a369_1 ( .OUT(na369_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b1), .IN4(~na1873_2), .IN5(1'b0), .IN6(1'b0), .IN7(~na371_1), + .IN8(~na1948_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y72 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a370_1 ( .OUT(na370_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na310_1), .IN6(na312_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x74y71 80'h00_0018_00_0040_0C0C_FC00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a371_1 ( .OUT(na371_1), .IN1(1'b0), .IN2(1'b0), .IN3(na317_1), .IN4(na313_1), .IN5(1'b1), .IN6(na4_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y74 80'h00_0018_00_0040_0AC0_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a374_1 ( .OUT(na374_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na320_1), .IN8(na318_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x76y73 80'h00_0018_00_0040_0C0C_FC00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a375_1 ( .OUT(na375_1), .IN1(1'b0), .IN2(1'b0), .IN3(na324_1), .IN4(na321_1), .IN5(1'b1), .IN6(na4_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x72y69 80'h00_0060_00_0000_0C08_FFE3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a376_4 ( .OUT(na376_2), .IN1(1'b0), .IN2(~na8_1), .IN3(na1949_2), .IN4(na377_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x80y64 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a377_4 ( .OUT(na377_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1353_1), .IN4(na7_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x83y63 80'h00_0018_00_0040_0A32_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a378_1 ( .OUT(na378_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b1), .IN4(na7_1), .IN5(na333_2), .IN6(~na1938_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x83y69 80'h00_0018_00_0040_0C15_8000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a380_1 ( .OUT(na380_1), .IN1(~na333_2), .IN2(1'b0), .IN3(na381_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na10_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x88y73 80'h00_0018_00_0040_0C15_8000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a381_1 ( .OUT(na381_1), .IN1(~na333_2), .IN2(1'b0), .IN3(na382_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1872_2), .IN8(na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y65 80'h00_0018_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a382_1 ( .OUT(na382_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na328_1), .IN8(na1939_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x81y60 80'h00_0018_00_0000_0888_F773 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a386_1 ( .OUT(na386_1), .IN1(1'b0), .IN2(~na388_1), .IN3(~na510_2), .IN4(~na1359_1), .IN5(~na1064_1), .IN6(~na1143_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x79y58 80'h00_0018_00_0040_0AC0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a388_1 ( .OUT(na388_1), .IN1(na1981_2), .IN2(1'b1), .IN3(1'b1), .IN4(na343_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1143_1), .IN8(na1151_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y70 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a390_1 ( .OUT(na390_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na399_1), .IN6(na391_2), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x83y70 80'h00_0060_00_0000_0C08_FFCE +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a391_4 ( .OUT(na391_2), .IN1(na392_1), .IN2(na1364_1), .IN3(1'b0), .IN4(na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y81 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a392_1 ( .OUT(na392_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na10_1), .IN8(na1365_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y71 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a393_1 ( .OUT(na393_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na7_1), .IN5(na277_1), .IN6(1'b0), .IN7(na394_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x68y65 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a394_1 ( .OUT(na394_1), .IN1(1'b1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(na274_1), .IN6(na275_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y75 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a395_1 ( .OUT(na395_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na285_1), .IN6(na280_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x84y76 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a396_1 ( .OUT(na396_1), .IN1(1'b1), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(na398_1), .IN6(na397_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y76 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a397_1 ( .OUT(na397_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na292_1), .IN6(na288_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y81 80'h00_0018_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a398_1 ( .OUT(na398_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na7_1), .IN5(1'b0), .IN6(na295_1), .IN7(1'b0), .IN8(na301_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x95y79 80'h00_0018_00_0000_0C88_3EFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a399_1 ( .OUT(na399_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na400_1), .IN6(na403_1), .IN7(1'b0), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x91y81 80'h00_0018_00_0000_0C88_2FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a400_1 ( .OUT(na400_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na10_1), .IN8(~na538_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x75y82 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a401_1 ( .OUT(na401_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na308_1), .IN6(na304_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x78y82 80'h00_0018_00_0040_0C05_3000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a402_1 ( .OUT(na402_1), .IN1(na311_1), .IN2(1'b0), .IN3(na316_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(~na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x91y80 80'h00_0018_00_0000_0C88_53FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a403_1 ( .OUT(na403_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1876_2), .IN7(~na470_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y77 80'h00_0018_00_0040_0A51_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a404_1 ( .OUT(na404_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na7_1), .IN5(~na333_2), .IN6(1'b0), .IN7(na382_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x78y73 80'h00_0018_00_0040_0C0C_F300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a406_1 ( .OUT(na406_1), .IN1(1'b0), .IN2(1'b0), .IN3(na324_1), .IN4(na325_1), .IN5(1'b1), .IN6(~na4_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x68y61 80'h00_0060_00_0000_0C08_FFEC +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a407_4 ( .OUT(na407_2), .IN1(1'b0), .IN2(na101_1), .IN3(na1372_1), .IN4(na410_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x89y72 80'h00_0018_00_0040_0A51_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a408_1 ( .OUT(na408_1), .IN1(1'b0), .IN2(1'b0), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na409_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x94y79 80'h00_0018_00_0040_0A51_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a409_1 ( .OUT(na409_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1873_2), .IN5(~na333_2), .IN6(1'b0), .IN7(na1352_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x82y76 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a410_4 ( .OUT(na410_2), .IN1(na333_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x74y56 80'h00_0018_00_0040_0AC0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a415_1 ( .OUT(na415_1), .IN1(na1981_2), .IN2(1'b1), .IN3(1'b1), .IN4(na343_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1154_1), .IN8(na1152_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y58 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a417_1 ( .OUT(na417_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na894_1), .IN5(~na1161_1), .IN6(1'b0), .IN7(~na1144_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x90y72 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a418_1 ( .OUT(na418_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na11_1), .IN5(1'b0), .IN6(na425_1), .IN7(1'b0), .IN8(na1382_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x81y80 80'h00_0018_00_0040_0A33_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a419_1 ( .OUT(na419_1), .IN1(1'b1), .IN2(~na8_1), .IN3(na10_1), .IN4(1'b1), .IN5(~na420_1), .IN6(~na421_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y81 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a420_1 ( .OUT(na420_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na362_1), .IN6(na360_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y82 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a421_1 ( .OUT(na421_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1947_2), .IN6(na367_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x82y66 80'h00_0018_00_0040_0C0A_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a423_1 ( .OUT(na423_1), .IN1(1'b0), .IN2(na353_1), .IN3(1'b0), .IN4(na1944_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x71y78 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a424_1 ( .OUT(na424_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na7_1), .IN5(1'b0), .IN6(na1945_2), .IN7(1'b0), .IN8(na354_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x89y80 80'h00_0018_00_0040_0C05_5000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a425_1 ( .OUT(na425_1), .IN1(na1384_1), .IN2(1'b0), .IN3(na428_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x86y76 80'h00_0018_00_0040_0ACC_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a427_1 ( .OUT(na427_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b1), .IN4(~na1873_2), .IN5(1'b0), .IN6(1'b0), .IN7(~na371_1), + .IN8(~na374_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x88y83 80'h00_0018_00_0040_0A50_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a428_1 ( .OUT(na428_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na1873_2), .IN5(na1386_1), .IN6(1'b0), .IN7(na332_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x66y75 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a429_4 ( .OUT(na429_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na375_1), .IN4(na7_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x81y72 80'h00_0018_00_0040_0ACC_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a430_1 ( .OUT(na430_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b1), .IN4(~na7_1), .IN5(1'b0), .IN6(1'b0), .IN7(~na328_1), .IN8(~na325_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x85y67 80'h00_0018_00_0040_0C15_8000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a431_1 ( .OUT(na431_1), .IN1(~na333_2), .IN2(1'b0), .IN3(na432_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na10_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x90y75 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a432_1 ( .OUT(na432_1), .IN1(1'b1), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na333_2), .IN6(na1333_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x74y58 80'h00_0018_00_0000_0888_F773 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a436_1 ( .OUT(na436_1), .IN1(1'b0), .IN2(~na438_1), .IN3(~na510_2), .IN4(~na1393_1), .IN5(~na1064_1), .IN6(~na1165_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x85y60 80'h00_0018_00_0040_0AC0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a438_1 ( .OUT(na438_1), .IN1(na1981_2), .IN2(1'b1), .IN3(1'b1), .IN4(na343_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1165_1), .IN8(na1153_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x82y61 80'h00_0018_00_0000_0EEE_3EAA +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a440_1 ( .OUT(na440_1), .IN1(na1412_1), .IN2(1'b0), .IN3(na1407_2), .IN4(1'b0), .IN5(na1408_2), .IN6(na1396_1), .IN7(1'b0), + .IN8(~na1411_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x71y55 80'h00_0018_00_0000_0888_1F51 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a441_1 ( .OUT(na441_1), .IN1(~na452_1), .IN2(~na451_1), .IN3(~na1397_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1397_2), + .IN8(~na442_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x80y68 80'h00_0018_00_0000_0C88_ECFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a442_1 ( .OUT(na442_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na101_1), .IN7(na1399_1), .IN8(na410_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y81 80'h00_0018_00_0040_0A51_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a443_1 ( .OUT(na443_1), .IN1(1'b0), .IN2(1'b0), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na428_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x85y69 80'h00_0018_00_0040_0AC0_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a444_1 ( .OUT(na444_1), .IN1(1'b1), .IN2(~na1877_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na1400_1), .IN8(na447_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x79y84 80'h00_0018_00_0040_0A33_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a446_1 ( .OUT(na446_1), .IN1(1'b1), .IN2(~na8_1), .IN3(na10_1), .IN4(1'b1), .IN5(~na291_1), .IN6(~na300_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x88y74 80'h00_0018_00_0040_0A50_0050 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a447_1 ( .OUT(na447_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na10_1), .IN4(1'b1), .IN5(na1402_1), .IN6(1'b0), .IN7(na432_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x76y78 80'h00_0018_00_0040_0ACC_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a449_1 ( .OUT(na449_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b1), .IN4(~na1873_2), .IN5(1'b0), .IN6(1'b0), .IN7(~na316_1), + .IN8(~na319_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x73y52 80'h00_0018_00_0040_0A76_005C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a451_1 ( .OUT(na451_1), .IN1(1'b1), .IN2(na1877_2), .IN3(~na1484_1), .IN4(1'b1), .IN5(na85_1), .IN6(~na2074_2), .IN7(~na1337_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x81y63 80'h00_0018_00_0000_0C88_2AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a452_1 ( .OUT(na452_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na84_1), .IN6(1'b1), .IN7(na1484_1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x71y60 80'h00_0018_00_0040_0CAA_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a453_1 ( .OUT(na453_1), .IN1(1'b0), .IN2(~na978_1), .IN3(1'b0), .IN4(~na1011_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na335_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x84y64 80'h00_0018_00_0000_0888_F773 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a456_1 ( .OUT(na456_1), .IN1(1'b0), .IN2(~na458_1), .IN3(~na510_2), .IN4(~na1410_1), .IN5(~na1064_1), .IN6(~na1168_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x79y56 80'h00_0018_00_0040_0AC0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a458_1 ( .OUT(na458_1), .IN1(na1981_2), .IN2(1'b1), .IN3(1'b1), .IN4(na343_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1168_1), .IN8(na1155_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x90y69 80'h00_0018_00_0040_0C55_3000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a460_1 ( .OUT(na460_1), .IN1(~na1413_1), .IN2(1'b0), .IN3(~na466_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x76y69 80'h00_0018_00_0040_0C0A_3F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a462_1 ( .OUT(na462_1), .IN1(1'b0), .IN2(na353_1), .IN3(1'b0), .IN4(na354_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(~na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x85y78 80'h00_0060_00_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a463_4 ( .OUT(na463_2), .IN1(na464_2), .IN2(na465_1), .IN3(~na10_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x83y79 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a464_4 ( .OUT(na464_2), .IN1(1'b1), .IN2(na8_1), .IN3(~na361_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x77y80 80'h00_0018_00_0040_0A33_00CC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a465_1 ( .OUT(na465_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b1), .IN4(na1873_2), .IN5(~na368_1), .IN6(~na367_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x88y75 80'h00_0018_00_0040_0A50_0050 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a466_1 ( .OUT(na466_1), .IN1(1'b0), .IN2(1'b0), .IN3(~na10_1), .IN4(1'b1), .IN5(na1417_1), .IN6(1'b0), .IN7(na409_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x85y77 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a467_4 ( .OUT(na467_2), .IN1(1'b1), .IN2(na8_1), .IN3(na1418_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x79y80 80'h00_0018_00_0040_0ACC_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a468_1 ( .OUT(na468_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b1), .IN4(~na1873_2), .IN5(1'b0), .IN6(1'b0), .IN7(~na375_1), + .IN8(~na374_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x81y71 80'h00_0018_00_0040_0C15_8000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a469_1 ( .OUT(na469_1), .IN1(~na333_2), .IN2(1'b0), .IN3(na470_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na10_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x84y77 80'h00_0018_00_0000_0C88_7EFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a470_1 ( .OUT(na470_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na404_1), .IN6(na8_1), .IN7(~na1370_1), .IN8(~na1873_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x71y56 80'h00_0018_00_0000_0888_F775 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a474_1 ( .OUT(na474_1), .IN1(~na476_1), .IN2(1'b0), .IN3(~na510_2), .IN4(~na1424_1), .IN5(~na1064_1), .IN6(~na1169_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x75y57 80'h00_0018_00_0040_0A30_0035 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a476_1 ( .OUT(na476_1), .IN1(~na1981_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na343_1), .IN5(na1156_1), .IN6(na1169_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x90y67 80'h00_0018_00_0040_0A55_0030 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a479_1 ( .OUT(na479_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na11_1), .IN5(~na1427_1), .IN6(1'b0), .IN7(~na482_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x81y79 80'h00_0018_00_0040_0A33_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a480_1 ( .OUT(na480_1), .IN1(1'b1), .IN2(~na8_1), .IN3(na10_1), .IN4(1'b1), .IN5(~na398_1), .IN6(~na401_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x90y73 80'h00_0018_00_0040_0C05_5000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a482_1 ( .OUT(na482_1), .IN1(na1429_1), .IN2(1'b0), .IN3(na381_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x76y79 80'h00_0018_00_0040_0ACC_003C +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a484_1 ( .OUT(na484_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b1), .IN4(~na1873_2), .IN5(1'b0), .IN6(1'b0), .IN7(~na406_1), + .IN8(~na319_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x89y64 80'h00_0018_00_0000_0C88_ECFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a485_1 ( .OUT(na485_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na101_1), .IN7(na1432_1), .IN8(na410_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x92y75 80'h00_0018_00_0040_0C15_A000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a486_1 ( .OUT(na486_1), .IN1(~na333_2), .IN2(1'b0), .IN3(na2077_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x73y58 80'h00_0018_00_0000_0888_F775 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a489_1 ( .OUT(na489_1), .IN1(~na491_1), .IN2(1'b0), .IN3(~na510_2), .IN4(~na1437_1), .IN5(~na1064_1), .IN6(~na1170_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x73y57 80'h00_0018_00_0040_0AC0_00CA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a491_1 ( .OUT(na491_1), .IN1(na1981_2), .IN2(1'b1), .IN3(1'b1), .IN4(na343_1), .IN5(1'b0), .IN6(1'b0), .IN7(na1170_1), .IN8(na1157_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x84y63 80'h00_0018_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a493_1 ( .OUT(na493_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na922_2), .IN6(1'b1), .IN7(1'b1), .IN8(na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x83y68 80'h00_0060_00_0000_0C08_FFEC +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a494_4 ( .OUT(na494_2), .IN1(1'b0), .IN2(na101_1), .IN3(na1441_1), .IN4(na410_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x94y75 80'h00_0018_00_0040_0A51_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a495_1 ( .OUT(na495_1), .IN1(1'b0), .IN2(1'b0), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na1331_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x83y67 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a496_1 ( .OUT(na496_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na11_1), .IN5(1'b0), .IN6(na500_1), .IN7(1'b0), .IN8(na1443_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x83y81 80'h00_0018_00_0040_0A33_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a498_1 ( .OUT(na498_1), .IN1(1'b1), .IN2(na8_1), .IN3(na10_1), .IN4(1'b1), .IN5(~na499_1), .IN6(~na421_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y79 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a499_1 ( .OUT(na499_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(na368_1), .IN6(na370_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x89y74 80'h00_0018_00_0040_0C0A_AF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a500_1 ( .OUT(na500_1), .IN1(1'b0), .IN2(na501_1), .IN3(1'b0), .IN4(na1445_1), .IN5(1'b1), .IN6(1'b1), .IN7(na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x85y82 80'h00_0018_00_0040_0A51_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a501_1 ( .OUT(na501_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1873_2), .IN5(~na333_2), .IN6(1'b0), .IN7(na332_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y80 80'h00_0018_00_0000_0C88_E3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a503_1 ( .OUT(na503_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na8_1), .IN7(na429_2), .IN8(na1953_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y49 80'h00_0018_00_0000_0C88_DDFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a508_1 ( .OUT(na508_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1960_2), .IN6(na509_1), .IN7(~na510_2), .IN8(na511_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x79y60 80'h00_0018_00_0040_0C55_3000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a509_1 ( .OUT(na509_1), .IN1(~na1158_1), .IN2(1'b0), .IN3(~na1171_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(~na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x68y59 80'h00_0078_00_0000_0C88_51A1 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a510_1 ( .OUT(na510_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(~na1063_1), .IN7(~na883_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a510_4 ( .OUT(na510_2), .IN1(~na1064_1), .IN2(~na1063_1), .IN3(na883_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x80y58 80'h00_0018_00_0040_0CAA_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a511_1 ( .OUT(na511_1), .IN1(1'b0), .IN2(~na1149_1), .IN3(1'b0), .IN4(~na1167_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na894_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x89y48 80'h00_0018_00_0040_0A33_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a512_1 ( .OUT(na512_1), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1456_2), .IN6(~na1171_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x85y53 80'h00_0018_00_0000_0EEE_0DEC +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a513_1 ( .OUT(na513_1), .IN1(1'b0), .IN2(na1461_1), .IN3(na1462_1), .IN4(na1465_2), .IN5(~na1464_1), .IN6(na1457_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y70 80'h00_0018_00_0000_0888_DF7C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a514_1 ( .OUT(na514_1), .IN1(1'b0), .IN2(na1911_2), .IN3(~na1460_1), .IN4(~na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na495_1), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x88y80 80'h00_0018_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a516_1 ( .OUT(na516_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1873_2), .IN5(1'b0), .IN6(na300_1), .IN7(1'b0), .IN8(na307_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x91y61 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a517_1 ( .OUT(na517_1), .IN1(1'b1), .IN2(na1877_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na333_2), .IN6(na500_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y55 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a518_1 ( .OUT(na518_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(~na982_1), .IN7(1'b0), .IN8(~na1015_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x98y45 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a521_1 ( .OUT(na521_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na508_1), .IN8(na102_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x92y48 80'h00_0018_00_0040_0A33_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a523_1 ( .OUT(na523_1), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1466_2), .IN6(~na1172_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x86y67 80'h00_0018_00_0040_0C05_3000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a525_1 ( .OUT(na525_1), .IN1(na1467_1), .IN2(1'b0), .IN3(na486_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x81y67 80'h00_0060_00_0000_0C08_FFEC +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a528_4 ( .OUT(na528_2), .IN1(1'b0), .IN2(na101_1), .IN3(na1471_1), .IN4(na410_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x96y47 80'h00_0018_00_0000_0888_F757 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a531_1 ( .OUT(na531_1), .IN1(~na2078_2), .IN2(~na89_1), .IN3(~na521_1), .IN4(1'b0), .IN5(~na1064_1), .IN6(~na1173_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x89y66 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a533_4 ( .OUT(na533_2), .IN1(1'b1), .IN2(na950_1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x90y71 80'h00_0018_00_0000_0888_DF7C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a535_1 ( .OUT(na535_1), .IN1(1'b0), .IN2(na1911_2), .IN3(~na1479_1), .IN4(~na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na536_1), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x92y73 80'h00_0018_00_0040_0A51_00A0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a536_1 ( .OUT(na536_1), .IN1(1'b0), .IN2(1'b0), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na470_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x84y80 80'h00_0018_00_0040_0AA0_003F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a538_1 ( .OUT(na538_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1873_2), .IN5(1'b0), .IN6(na401_1), .IN7(1'b0), .IN8(na402_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x81y67 80'h00_0018_00_0000_0C88_ECFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a539_1 ( .OUT(na539_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na101_1), .IN7(na2099_2), .IN8(na410_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x94y48 80'h00_0018_00_0040_0C33_0A00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a544_1 ( .OUT(na544_1), .IN1(~na1488_1), .IN2(~na1144_1), .IN3(1'b0), .IN4(1'b0), .IN5(na1064_1), .IN6(1'b1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x83y64 80'h00_0060_00_0000_0C08_FF43 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a545_4 ( .OUT(na545_2), .IN1(1'b1), .IN2(~na548_1), .IN3(~na1489_1), .IN4(na102_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x87y72 80'h00_0018_00_0040_0A51_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a548_1 ( .OUT(na548_1), .IN1(1'b1), .IN2(na1877_2), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na428_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y63 80'h00_0018_00_0000_0C88_ECFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a549_1 ( .OUT(na549_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na101_1), .IN7(na2105_2), .IN8(na410_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x96y45 80'h00_0018_00_0000_0888_F757 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a551_1 ( .OUT(na551_1), .IN1(~na2080_2), .IN2(~na89_1), .IN3(~na521_1), .IN4(1'b0), .IN5(~na1064_1), .IN6(~na1145_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x88y69 80'h00_0018_00_0040_0A31_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a556_1 ( .OUT(na556_1), .IN1(1'b1), .IN2(na1877_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na333_2), .IN6(na425_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x84y67 80'h00_0060_00_0000_0C08_FF43 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a557_4 ( .OUT(na557_2), .IN1(1'b1), .IN2(~na560_1), .IN3(~na1501_1), .IN4(na102_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x85y72 80'h00_0018_00_0040_0A51_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a560_1 ( .OUT(na560_1), .IN1(1'b1), .IN2(na1877_2), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na432_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x94y47 80'h00_0018_00_0000_0888_F757 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a564_1 ( .OUT(na564_1), .IN1(~na2082_2), .IN2(~na89_1), .IN3(~na521_1), .IN4(1'b0), .IN5(~na1064_1), .IN6(~na1146_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x85y62 80'h00_0018_00_0000_0C88_48FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a567_1 ( .OUT(na567_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1053_2), .IN6(na1870_2), .IN7(~na1055_2), + .IN8(na1056_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x87y55 80'h00_0018_00_0000_0EEE_E0DB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a568_1 ( .OUT(na568_1), .IN1(na1524_1), .IN2(~na1523_2), .IN3(~na1527_2), .IN4(na1528_2), .IN5(1'b0), .IN6(1'b0), .IN7(na1522_2), + .IN8(na1513_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y68 80'h00_0018_00_0000_0888_7B75 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a569_1 ( .OUT(na569_1), .IN1(~na570_1), .IN2(1'b0), .IN3(~na1521_1), .IN4(~na102_1), .IN5(na1965_2), .IN6(~na101_1), .IN7(~na813_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x91y69 80'h00_0018_00_0000_0C88_45FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a570_1 ( .OUT(na570_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1515_1), .IN6(1'b1), .IN7(~na572_1), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x83y76 80'h00_0060_00_0000_0C08_FF5E +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a571_4 ( .OUT(na571_2), .IN1(na467_2), .IN2(na468_1), .IN3(~na10_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x88y71 80'h00_0018_00_0040_0A51_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a572_1 ( .OUT(na572_1), .IN1(1'b1), .IN2(na1877_2), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na409_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x90y65 80'h00_0018_00_0000_0C88_B3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a574_1 ( .OUT(na574_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na1952_2), .IN7(na1366_1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x95y48 80'h00_0018_00_0000_0888_F757 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a578_1 ( .OUT(na578_1), .IN1(~na2084_2), .IN2(~na89_1), .IN3(~na521_1), .IN4(1'b0), .IN5(~na1064_1), .IN6(~na1147_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x90y61 80'h00_0018_00_0000_0EEE_CBAB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a581_1 ( .OUT(na581_1), .IN1(na1542_2), .IN2(~na1543_1), .IN3(na1544_1), .IN4(1'b0), .IN5(na1538_1), .IN6(~na1541_1), .IN7(1'b0), + .IN8(na1529_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y66 80'h00_0018_00_0000_0888_7B73 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a582_1 ( .OUT(na582_1), .IN1(1'b0), .IN2(~na583_2), .IN3(~na1537_1), .IN4(~na102_1), .IN5(na587_1), .IN6(~na101_1), .IN7(~na815_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x83y72 80'h00_0060_00_0000_0C08_FF34 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a583_4 ( .OUT(na583_2), .IN1(~na1531_1), .IN2(na1911_2), .IN3(1'b1), .IN4(~na586_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x84y72 80'h00_0018_00_0040_0A51_00AC +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a586_1 ( .OUT(na586_1), .IN1(1'b1), .IN2(na1877_2), .IN3(na10_1), .IN4(1'b1), .IN5(~na333_2), .IN6(1'b0), .IN7(na381_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x89y71 80'h00_0018_00_0000_0C88_B3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a587_1 ( .OUT(na587_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na1952_2), .IN7(na1536_1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x93y47 80'h00_0018_00_0000_0888_F757 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a590_1 ( .OUT(na590_1), .IN1(~na2088_2), .IN2(~na89_1), .IN3(~na521_1), .IN4(1'b0), .IN5(~na1064_1), .IN6(~na1148_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x89y56 80'h00_0018_00_0000_0EEE_EB0D +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a594_1 ( .OUT(na594_1), .IN1(~na1558_2), .IN2(na603_1), .IN3(1'b0), .IN4(1'b0), .IN5(na1557_1), .IN6(~na1556_2), .IN7(na1559_2), + .IN8(na1545_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x75y53 80'h00_0018_00_0000_0888_7B73 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a595_1 ( .OUT(na595_1), .IN1(1'b0), .IN2(~na596_1), .IN3(~na1553_1), .IN4(~na102_1), .IN5(na1966_2), .IN6(~na101_1), .IN7(~na817_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x89y70 80'h00_0018_00_0000_0888_F5DC +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a596_1 ( .OUT(na596_1), .IN1(1'b0), .IN2(na1911_2), .IN3(~na331_1), .IN4(na11_1), .IN5(~na1547_1), .IN6(1'b0), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x82y67 80'h00_0060_00_0000_0C08_FFB3 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a600_4 ( .OUT(na600_2), .IN1(1'b0), .IN2(~na1952_2), .IN3(na1329_1), .IN4(~na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y60 80'h00_0018_00_0000_0C88_BAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a603_1 ( .OUT(na603_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na521_1), .IN8(~na604_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x88y50 80'h00_0018_00_0040_0A33_000A +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a604_1 ( .OUT(na604_1), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1555_2), .IN6(~na1149_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y74 80'h00_0018_00_0000_0888_F5DC +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a608_1 ( .OUT(na608_1), .IN1(1'b0), .IN2(na101_1), .IN3(~na331_1), .IN4(na11_1), .IN5(~na1547_1), .IN6(1'b0), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x98y47 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a611_1 ( .OUT(na611_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1563_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x100y47 80'h00_0018_00_0000_0C88_15FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a612_1 ( .OUT(na612_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na613_1), .IN6(1'b1), .IN7(~na2031_2), .IN8(~na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x87y47 80'h00_0018_00_0040_0AA0_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a613_1 ( .OUT(na613_1), .IN1(1'b1), .IN2(1'b1), .IN3(~na510_1), .IN4(1'b1), .IN5(1'b0), .IN6(na509_1), .IN7(1'b0), .IN8(na511_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x87y60 80'h00_0018_00_0000_0EEE_CDCE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a616_1 ( .OUT(na616_1), .IN1(na1577_1), .IN2(na625_1), .IN3(1'b0), .IN4(na2115_2), .IN5(~na1581_1), .IN6(na1568_1), .IN7(1'b0), + .IN8(na1582_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x84y68 80'h00_0078_00_0000_0C88_C58F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a617_1 ( .OUT(na617_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na587_1), .IN6(1'b1), .IN7(1'b1), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a617_4 ( .OUT(na617_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1576_1), .IN4(na102_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x72y51 80'h00_0018_00_0040_0A76_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a620_1 ( .OUT(na620_1), .IN1(1'b1), .IN2(~na2087_2), .IN3(1'b1), .IN4(na24_1), .IN5(na85_1), .IN6(~na2074_2), .IN7(~na1337_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x91y52 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a625_1 ( .OUT(na625_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1580_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x83y68 80'h00_0018_00_0000_0C88_54FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a628_1 ( .OUT(na628_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1515_1), .IN6(na101_1), .IN7(~na572_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x95y51 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a632_1 ( .OUT(na632_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1588_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x85y73 80'h00_0018_00_0000_0C88_43FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a635_1 ( .OUT(na635_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na560_1), .IN7(~na1501_1), .IN8(na1907_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x94y52 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a639_1 ( .OUT(na639_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1596_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x88y53 80'h00_0018_00_0000_0EEE_AAEB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a641_1 ( .OUT(na641_1), .IN1(na830_1), .IN2(~na1607_1), .IN3(na1599_2), .IN4(na646_1), .IN5(na1608_1), .IN6(1'b0), .IN7(na1599_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x83y64 80'h00_0018_00_0000_0C88_43FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a642_1 ( .OUT(na642_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na548_1), .IN7(~na1489_1), .IN8(na1907_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x91y63 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a643_1 ( .OUT(na643_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1494_1), .IN6(na1952_2), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x92y50 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a646_1 ( .OUT(na646_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1606_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y73 80'h00_0018_00_0000_0888_DF7C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a648_1 ( .OUT(na648_1), .IN1(1'b0), .IN2(na101_1), .IN3(~na1479_1), .IN4(~na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na536_1), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x94y67 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a649_1 ( .OUT(na649_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1481_1), .IN6(na1952_2), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y71 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a652_1 ( .OUT(na652_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1614_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x88y56 80'h00_0018_00_0000_0EEE_AAEE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a655_1 ( .OUT(na655_1), .IN1(na662_2), .IN2(na1624_1), .IN3(na1619_1), .IN4(na660_1), .IN5(na662_1), .IN6(1'b0), .IN7(na1619_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y59 80'h00_0018_00_0000_0888_7B7D +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a656_1 ( .OUT(na656_1), .IN1(~na1910_2), .IN2(na1470_1), .IN3(~na1623_1), .IN4(~na102_1), .IN5(na1961_2), .IN6(~na101_1), + .IN7(~na834_1), .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x92y52 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a660_1 ( .OUT(na660_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1626_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x89y67 80'h00_0078_00_0000_0C88_ACCA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a662_1 ( .OUT(na662_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na942_1), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a662_4 ( .OUT(na662_2), .IN1(na917_2), .IN2(1'b1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y74 80'h00_0018_00_0000_0888_DF7C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a664_1 ( .OUT(na664_1), .IN1(1'b0), .IN2(na101_1), .IN3(~na1460_1), .IN4(~na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na495_1), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x96y69 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a665_1 ( .OUT(na665_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1630_2), .IN6(na1952_2), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x95y50 80'h00_0018_00_0000_0C88_EAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a669_1 ( .OUT(na669_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na612_1), .IN8(na1635_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x84y54 80'h00_0018_00_0000_0888_77BD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a671_1 ( .OUT(na671_1), .IN1(~na1341_2), .IN2(na1643_2), .IN3(na672_1), .IN4(~na350_1), .IN5(~na1062_2), .IN6(~na567_1), + .IN7(~na1045_2), .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x90y63 80'h00_0018_00_0000_0888_7B7B +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a672_1 ( .OUT(na672_1), .IN1(na1440_1), .IN2(~na1911_2), .IN3(~na1642_1), .IN4(~na102_1), .IN5(na496_1), .IN6(~na101_1), + .IN7(~na839_1), .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y54 80'h00_0018_00_0000_0888_77BD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a677_1 ( .OUT(na677_1), .IN1(~na1341_2), .IN2(na1652_1), .IN3(na678_1), .IN4(~na350_1), .IN5(~na1077_2), .IN6(~na567_1), + .IN7(~na868_1), .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x80y63 80'h00_0018_00_0000_0888_777B +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a678_1 ( .OUT(na678_1), .IN1(na1431_1), .IN2(~na1911_2), .IN3(~na1651_1), .IN4(~na102_1), .IN5(~na1957_2), .IN6(~na101_1), + .IN7(~na841_1), .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y54 80'h00_0018_00_0000_0888_77BD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a683_1 ( .OUT(na683_1), .IN1(~na1341_2), .IN2(na1662_1), .IN3(na1657_1), .IN4(~na350_1), .IN5(~na1077_1), .IN6(~na567_1), + .IN7(~na1047_2), .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x84y65 80'h00_0078_00_0000_0C88_AC3C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a684_1 ( .OUT(na684_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na101_1), .IN7(na460_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a684_4 ( .OUT(na684_2), .IN1(1'b1), .IN2(na1909_2), .IN3(1'b1), .IN4(~na688_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x72y50 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a687_1 ( .OUT(na687_1), .IN1(~na2111_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1894_2), .IN5(na85_1), .IN6(~na2074_2), .IN7(~na1337_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x68y76 80'h00_0018_00_0040_0C55_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a688_1 ( .OUT(na688_1), .IN1(~na970_1), .IN2(1'b0), .IN3(~na1002_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na335_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x71y63 80'h00_0018_00_0000_0C88_C2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a689_1 ( .OUT(na689_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na84_1), .IN6(~na33_1), .IN7(1'b1), .IN8(na1514_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y56 80'h00_0018_00_0000_0888_77BD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a693_1 ( .OUT(na693_1), .IN1(~na1341_2), .IN2(na1676_2), .IN3(na1667_1), .IN4(~na350_1), .IN5(~na1079_2), .IN6(~na567_1), + .IN7(~na1968_2), .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x74y47 80'h00_0018_00_0040_0A76_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a695_1 ( .OUT(na695_1), .IN1(na34_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1510_2), .IN5(na85_1), .IN6(~na2074_2), .IN7(~na1337_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y62 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a698_1 ( .OUT(na698_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2081_2), .IN6(na1952_2), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y55 80'h00_0018_00_0000_0888_7D77 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a702_1 ( .OUT(na702_1), .IN1(~na1079_1), .IN2(~na567_1), .IN3(~na1681_1), .IN4(~na350_1), .IN5(~na1341_2), .IN6(na1687_2), + .IN7(~na1049_2), .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x72y49 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a706_1 ( .OUT(na706_1), .IN1(~na2110_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1895_2), .IN5(na85_1), .IN6(~na2074_2), .IN7(~na1337_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x80y77 80'h00_0018_00_0040_0CAA_CF00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a707_1 ( .OUT(na707_1), .IN1(1'b0), .IN2(~na972_1), .IN3(1'b0), .IN4(~na1004_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na335_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x76y62 80'h00_0018_00_0000_0C88_A4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a708_1 ( .OUT(na708_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na35_1), .IN6(na1906_2), .IN7(na1509_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x77y65 80'h00_0018_00_0000_0888_77BD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a711_1 ( .OUT(na711_1), .IN1(~na1341_2), .IN2(na1698_1), .IN3(na1692_1), .IN4(~na350_1), .IN5(~na1081_2), .IN6(~na567_1), + .IN7(~na872_1), .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x88y65 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a714_1 ( .OUT(na714_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2079_2), .IN6(na1952_2), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y56 80'h00_0018_00_0000_0888_7DB5 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a718_1 ( .OUT(na718_1), .IN1(~na726_1), .IN2(1'b0), .IN3(na719_1), .IN4(~na350_1), .IN5(~na1341_2), .IN6(na1712_1), .IN7(~na1051_1), + .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x84y57 80'h00_0018_00_0000_0888_4F1C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a719_1 ( .OUT(na719_1), .IN1(1'b1), .IN2(na1708_1), .IN3(~na1705_1), .IN4(~na721_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na1705_2), + .IN8(na1703_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x72y52 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a721_1 ( .OUT(na721_1), .IN1(~na2108_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1897_2), .IN5(na85_1), .IN6(~na2074_2), .IN7(~na1337_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x79y57 80'h00_0018_00_0000_0C88_48FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a726_1 ( .OUT(na726_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1053_2), .IN6(na1940_2), .IN7(~na1055_2), + .IN8(na5_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y57 80'h00_0018_00_0000_0888_77BD +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a727_1 ( .OUT(na727_1), .IN1(~na1341_2), .IN2(na1721_2), .IN3(na1715_1), .IN4(~na350_1), .IN5(~na1964_2), .IN6(~na1063_2), + .IN7(~na1969_2), .IN8(~na350_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x84y75 80'h00_0018_00_0000_0C88_ECFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a728_1 ( .OUT(na728_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(na101_1), .IN7(na1967_2), .IN8(na298_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x77y56 80'h00_0018_00_0040_0A7F_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a731_1 ( .OUT(na731_1), .IN1(na38_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1497_2), .IN5(~na84_1), .IN6(~na1904_2), .IN7(~na83_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x71y63 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a732_4 ( .OUT(na732_2), .IN1(na1720_1), .IN2(1'b1), .IN3(1'b1), .IN4(na102_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y54 80'h00_0018_00_0000_0888_3FD3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a736_1 ( .OUT(na736_1), .IN1(1'b0), .IN2(~na1228_2), .IN3(~na240_2), .IN4(na1056_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x61y65 80'h00_0018_00_0000_0888_FB5C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a737_1 ( .OUT(na737_1), .IN1(1'b0), .IN2(na738_1), .IN3(~na510_2), .IN4(1'b0), .IN5(na1064_1), .IN6(~na1982_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x67y50 80'h00_0018_00_0000_0C88_8CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a738_1 ( .OUT(na738_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2021_2), .IN7(na240_2), .IN8(na44_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x61y67 80'h00_0018_00_0000_0888_FB5C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a739_1 ( .OUT(na739_1), .IN1(1'b0), .IN2(na738_1), .IN3(~na510_1), .IN4(1'b0), .IN5(na1064_1), .IN6(~na1982_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x61y68 80'h00_0018_00_0000_0888_FE5C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a740_1 ( .OUT(na740_1), .IN1(1'b0), .IN2(na738_1), .IN3(~na510_2), .IN4(1'b0), .IN5(na1064_1), .IN6(na1982_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x61y71 80'h00_0018_00_0000_0888_FE5C +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a741_1 ( .OUT(na741_1), .IN1(1'b0), .IN2(na738_1), .IN3(~na510_1), .IN4(1'b0), .IN5(na1064_1), .IN6(na1982_2), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x73y69 80'h00_0018_00_0040_0C85_C300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a774_1 ( .OUT(na774_1), .IN1(na274_1), .IN2(1'b0), .IN3(na272_1), .IN4(1'b1), .IN5(1'b1), .IN6(~na4_1), .IN7(1'b1), .IN8(na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x79y59 80'h00_0018_00_0040_0A3B_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a775_1 ( .OUT(na775_1), .IN1(~na774_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1868_2), .IN5(~na273_1), .IN6(~na275_1), .IN7(1'b0), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x80y72 80'h00_0018_00_0040_0C23_0300 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a776_1 ( .OUT(na776_1), .IN1(na775_1), .IN2(~na276_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na8_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x85y75 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a777_1 ( .OUT(na777_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1730_1), .IN7(1'b1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x73y56 80'h00_0018_00_0040_0C8A_3F00 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a778_1 ( .OUT(na778_1), .IN1(1'b0), .IN2(na1731_1), .IN3(1'b0), .IN4(~na1243_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(~na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x78y74 80'h00_0018_00_0040_0C53_3300 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a780_1 ( .OUT(na780_1), .IN1(~na355_1), .IN2(na353_1), .IN3(1'b1), .IN4(1'b0), .IN5(1'b1), .IN6(~na8_1), .IN7(1'b1), .IN8(~na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x78y72 80'h00_0018_00_0040_0AA1_0033 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a781_1 ( .OUT(na781_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b1), .IN4(~na780_1), .IN5(1'b1), .IN6(na356_1), .IN7(1'b0), .IN8(na354_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y81 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a782_1 ( .OUT(na782_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1735_2), .IN6(na357_1), .IN7(1'b0), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x80y55 80'h00_0018_00_0040_0A76_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a783_1 ( .OUT(na783_1), .IN1(1'b1), .IN2(~na2104_2), .IN3(1'b1), .IN4(na7_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x77y61 80'h00_0018_00_0040_0A76_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a785_1 ( .OUT(na785_1), .IN1(1'b1), .IN2(~na2102_2), .IN3(1'b1), .IN4(na1873_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x72y57 80'h00_0018_00_0000_0EEE_ADC5 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a787_1 ( .OUT(na787_1), .IN1(~na1376_1), .IN2(1'b0), .IN3(1'b0), .IN4(na1379_2), .IN5(~na1376_2), .IN6(na1738_2), .IN7(na1375_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x77y57 80'h00_0018_00_0040_0A76_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a788_1 ( .OUT(na788_1), .IN1(1'b1), .IN2(~na2101_2), .IN3(na10_1), .IN4(1'b1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x67y59 80'h00_0018_00_0040_0A76_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a789_1 ( .OUT(na789_1), .IN1(1'b1), .IN2(~na2098_2), .IN3(1'b1), .IN4(na1878_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x77y49 80'h00_0018_00_0040_0A76_00C3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a790_1 ( .OUT(na790_1), .IN1(1'b1), .IN2(~na2097_2), .IN3(1'b1), .IN4(na1879_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x82y53 80'h00_0018_00_0000_0EEE_5AAE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a792_1 ( .OUT(na792_1), .IN1(na1439_2), .IN2(na1435_1), .IN3(na493_1), .IN4(1'b0), .IN5(na1741_2), .IN6(1'b0), .IN7(~na1438_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x78y48 80'h00_0018_00_0040_0A76_00A3 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a793_1 ( .OUT(na793_1), .IN1(1'b1), .IN2(~na2096_2), .IN3(na1880_2), .IN4(1'b1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x82y55 80'h00_0018_00_0000_0EEE_A3CB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a794_1 ( .OUT(na794_1), .IN1(na1453_2), .IN2(~na1450_1), .IN3(1'b0), .IN4(na1449_1), .IN5(1'b0), .IN6(~na1450_2), .IN7(na1743_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x90y56 80'h00_0018_00_0000_0888_BF73 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a795_1 ( .OUT(na795_1), .IN1(1'b0), .IN2(~na494_2), .IN3(~na1448_1), .IN4(~na102_1), .IN5(1'b1), .IN6(1'b1), .IN7(na1958_2), + .IN8(~na102_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2a//// x68y60 80'h00_0018_00_0040_0C15_C000 +C_MX2a #(.CPE_CFG (9'b0_0000_0000)) + _a796_1 ( .OUT(na796_1), .IN1(~na1745_1), .IN2(1'b0), .IN3(na794_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na795_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x76y51 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a797_1 ( .OUT(na797_1), .IN1(~na2095_2), .IN2(1'b1), .IN3(1'b1), .IN4(na15_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x77y51 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a800_1 ( .OUT(na800_1), .IN1(~na2094_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1882_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x84y55 80'h00_0018_00_0000_0EEE_D0CE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a802_1 ( .OUT(na802_1), .IN1(na1477_1), .IN2(na533_2), .IN3(1'b0), .IN4(na1473_2), .IN5(1'b0), .IN6(1'b0), .IN7(~na1476_1), + .IN8(na1750_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x79y54 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a803_1 ( .OUT(na803_1), .IN1(~na2093_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1883_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x85y54 80'h00_0018_00_0000_0EEE_5AAE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a805_1 ( .OUT(na805_1), .IN1(na1753_2), .IN2(na1485_1), .IN3(na1487_2), .IN4(1'b0), .IN5(na1483_1), .IN6(1'b0), .IN7(~na1486_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x79y53 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a806_1 ( .OUT(na806_1), .IN1(~na2092_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1884_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x85y55 80'h00_0018_00_0000_0EEE_AD0E +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a809_1 ( .OUT(na809_1), .IN1(na1757_1), .IN2(na1756_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na1499_1), .IN6(na1500_2), .IN7(na1498_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x70y49 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a810_1 ( .OUT(na810_1), .IN1(~na2091_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1885_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x87y58 80'h00_0018_00_0000_0EEE_E5AB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a812_1 ( .OUT(na812_1), .IN1(na1512_2), .IN2(~na1507_1), .IN3(na1760_1), .IN4(1'b0), .IN5(~na1511_1), .IN6(1'b0), .IN7(na1506_2), + .IN8(na1508_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x78y53 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a813_1 ( .OUT(na813_1), .IN1(~na2090_2), .IN2(1'b1), .IN3(1'b1), .IN4(na20_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x72y63 80'h00_0018_00_0040_0A76_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a815_1 ( .OUT(na815_1), .IN1(na21_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1452_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x78y55 80'h00_0018_00_0040_0A76_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a817_1 ( .OUT(na817_1), .IN1(na22_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1447_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x75y55 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a819_1 ( .OUT(na819_1), .IN1(~na2089_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1887_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x87y59 80'h00_0018_00_0000_0EEE_E3E5 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a821_1 ( .OUT(na821_1), .IN1(~na1564_1), .IN2(1'b0), .IN3(na1565_2), .IN4(na1766_2), .IN5(1'b0), .IN6(~na1566_1), .IN7(na611_1), + .IN8(na1567_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x71y53 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a822_1 ( .OUT(na822_1), .IN1(~na2086_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1889_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x88y62 80'h00_0018_00_0000_0EEE_DEE0 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a824_1 ( .OUT(na824_1), .IN1(1'b0), .IN2(1'b0), .IN3(na1585_2), .IN4(na1769_2), .IN5(na632_1), .IN6(na1590_2), .IN7(~na1589_1), + .IN8(na1769_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x72y55 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a825_1 ( .OUT(na825_1), .IN1(~na2085_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1890_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x87y61 80'h00_0018_00_0000_0EEE_EB0E +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a827_1 ( .OUT(na827_1), .IN1(na1772_1), .IN2(na1593_1), .IN3(1'b0), .IN4(1'b0), .IN5(na1772_2), .IN6(~na1597_1), .IN7(na1598_2), + .IN8(na639_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x80y49 80'h00_0018_00_0040_0A76_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a828_1 ( .OUT(na828_1), .IN1(na27_1), .IN2(1'b1), .IN3(~na1525_1), .IN4(1'b1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y55 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a830_1 ( .OUT(na830_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1775_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x81y49 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a831_1 ( .OUT(na831_1), .IN1(~na2114_2), .IN2(1'b1), .IN3(1'b1), .IN4(na28_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x87y53 80'h00_0018_00_0000_0EEE_BACB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a833_1 ( .OUT(na833_1), .IN1(na1616_1), .IN2(~na1615_2), .IN3(1'b0), .IN4(na1778_2), .IN5(na1618_1), .IN6(1'b0), .IN7(na652_1), + .IN8(~na1617_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x80y51 80'h00_0018_00_0040_0A76_003A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a834_1 ( .OUT(na834_1), .IN1(na29_1), .IN2(1'b1), .IN3(1'b1), .IN4(~na1519_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x81y51 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a836_1 ( .OUT(na836_1), .IN1(~na2113_2), .IN2(1'b1), .IN3(1'b1), .IN4(na1892_2), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x88y59 80'h00_0018_00_0000_0EEE_BCEC +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a838_1 ( .OUT(na838_1), .IN1(1'b0), .IN2(na2116_2), .IN3(na1782_2), .IN4(na1632_2), .IN5(1'b0), .IN6(na669_1), .IN7(na1637_1), + .IN8(~na1636_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x78y49 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a839_1 ( .OUT(na839_1), .IN1(~na2112_2), .IN2(1'b1), .IN3(1'b1), .IN4(na31_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x80y53 80'h00_0018_00_0040_0A76_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a841_1 ( .OUT(na841_1), .IN1(na32_1), .IN2(1'b1), .IN3(~na1516_2), .IN4(1'b1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x86y63 80'h00_0018_00_0040_0A76_00C5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a843_1 ( .OUT(na843_1), .IN1(~na2109_2), .IN2(1'b1), .IN3(1'b1), .IN4(na36_1), .IN5(na1064_1), .IN6(~na1063_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y62 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a845_1 ( .OUT(na845_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na788_1), .IN6(na1788_2), .IN7(1'b0), .IN8(na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x86y51 80'h00_0018_00_0000_0EEE_AAE3 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a847_1 ( .OUT(na847_1), .IN1(1'b0), .IN2(~na1394_2), .IN3(na1790_2), .IN4(na1390_1), .IN5(na1391_2), .IN6(1'b0), .IN7(na1395_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x89y59 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a848_1 ( .OUT(na848_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na789_1), .IN6(na1793_1), .IN7(1'b0), .IN8(na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x83y51 80'h00_0018_00_0000_0EEE_0BAB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a850_1 ( .OUT(na850_1), .IN1(na1426_2), .IN2(~na1421_2), .IN3(na1795_1), .IN4(1'b0), .IN5(na1422_2), .IN6(~na1421_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y56 80'h00_FE60_00_0020_0C66_C00A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a853_1 ( .OUT(na853_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na853_1), + .CINX(1'b0), .CINY1(na882_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a853_2 ( .OUT(na853_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na853_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a853_4 ( .OUT(na853_2), .COUTY1(na853_4), .IN1(na1033_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na853_1), .CINX(1'b0), .CINY1(na882_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y57 80'h00_FE60_00_0020_0C66_A00C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a855_1 ( .OUT(na855_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na855_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na853_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a855_2 ( .OUT(na855_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na855_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a855_4 ( .OUT(na855_2), .COUTY1(na855_4), .IN1(1'b1), .IN2(na1035_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na855_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na853_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y58 80'h00_FE60_00_0020_0C66_C00A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a857_1 ( .OUT(na857_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na857_1), + .CINX(1'b0), .CINY1(na855_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a857_2 ( .OUT(na857_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na857_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a857_4 ( .OUT(na857_2), .COUTY1(na857_4), .IN1(na1037_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na857_1), .CINX(1'b0), .CINY1(na855_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y59 80'h00_FE60_00_0020_0C66_A0A0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a859_1 ( .OUT(na859_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na859_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na857_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a859_2 ( .OUT(na859_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na859_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a859_4 ( .OUT(na859_2), .COUTY1(na859_4), .IN1(1'b0), .IN2(1'b0), .IN3(na1039_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na859_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na857_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y60 80'h00_FE60_00_0020_0C66_C00A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a861_1 ( .OUT(na861_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na861_1), + .CINX(1'b0), .CINY1(na859_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a861_2 ( .OUT(na861_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na861_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a861_4 ( .OUT(na861_2), .COUTY1(na861_4), .IN1(na1041_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na861_1), .CINX(1'b0), .CINY1(na859_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y51 80'h00_FE60_00_0020_0C66_AC0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a862_1 ( .OUT(na862_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1023_2), .IN7(na862_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na907_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a862_2 ( .OUT(na862_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na862_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a862_4 ( .OUT(na862_2), .COUTY1(na862_4), .IN1(1'b1), .IN2(na1023_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1023_2), + .IN7(na862_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na907_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y61 80'h00_FE60_00_0020_0C66_A0C0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a864_1 ( .OUT(na864_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na864_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na861_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a864_2 ( .OUT(na864_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na864_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a864_4 ( .OUT(na864_2), .COUTY1(na864_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1043_1), .IN5(1'b0), .IN6(1'b0), .IN7(na864_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na861_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y62 80'h00_FE60_00_0020_0C66_C0A0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a866_1 ( .OUT(na866_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na866_1), + .CINX(1'b0), .CINY1(na864_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a866_2 ( .OUT(na866_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na866_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a866_4 ( .OUT(na866_2), .COUTY1(na866_4), .IN1(1'b0), .IN2(1'b0), .IN3(na1045_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na866_1), .CINX(1'b0), .CINY1(na864_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y63 80'h00_FE60_00_0020_0C66_A0A0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a868_1 ( .OUT(na868_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na868_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na866_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a868_2 ( .OUT(na868_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na868_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a868_4 ( .OUT(na868_2), .COUTY1(na868_4), .IN1(1'b0), .IN2(1'b0), .IN3(na1047_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na868_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na866_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y64 80'h00_FE60_00_0020_0C66_C0A0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a870_1 ( .OUT(na870_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na870_1), + .CINX(1'b0), .CINY1(na868_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a870_2 ( .OUT(na870_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na870_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a870_4 ( .OUT(na870_2), .COUTY1(na870_4), .IN1(1'b0), .IN2(1'b0), .IN3(na1049_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na870_1), .CINX(1'b0), .CINY1(na868_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y65 80'h00_FE60_00_0020_0C66_A0A0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a872_1 ( .OUT(na872_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na872_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na870_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a872_2 ( .OUT(na872_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na872_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a872_4 ( .OUT(na872_2), .COUTY1(na872_4), .IN1(1'b0), .IN2(1'b0), .IN3(na1051_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(na872_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na870_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF/D/// x96y66 80'h00_FE00_00_0010_0666_00C0 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a875_1 ( .OUT(na875_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na875_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na872_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a875_2 ( .OUT(na875_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na875_1_i) ); +// C_ADDF2/D//ADDF2/ x96y52 80'h00_FE60_00_0020_0C66_C00C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a876_1 ( .OUT(na876_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na876_1), + .CINX(1'b0), .CINY1(na862_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a876_2 ( .OUT(na876_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na876_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a876_4 ( .OUT(na876_2), .COUTY1(na876_4), .IN1(1'b1), .IN2(na1025_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na876_1), .CINX(1'b0), .CINY1(na862_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y53 80'h00_FE60_00_0020_0C66_A0C0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a878_1 ( .OUT(na878_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na878_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na876_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a878_2 ( .OUT(na878_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na878_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a878_4 ( .OUT(na878_2), .COUTY1(na878_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1027_2), .IN5(1'b0), .IN6(1'b0), .IN7(na878_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na876_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y54 80'h00_FE60_00_0020_0C66_C00A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a880_1 ( .OUT(na880_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na880_1), + .CINX(1'b0), .CINY1(na878_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a880_2 ( .OUT(na880_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na880_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a880_4 ( .OUT(na880_2), .COUTY1(na880_4), .IN1(na1029_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na880_1), .CINX(1'b0), .CINY1(na878_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2/D//ADDF2/ x96y55 80'h00_FE60_00_0020_0C66_A00A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a882_1 ( .OUT(na882_1_i), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na882_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na880_4), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a882_2 ( .OUT(na882_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na882_1_i) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a882_4 ( .OUT(na882_2), .COUTY1(na882_4), .IN1(na1031_2), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na882_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na880_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x78y57 80'h00_0018_00_0010_0666_20A8 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a883_1 ( .OUT(na883_1), .COUTY1(na883_4), .IN1(na1058_1), .IN2(na2021_2), .IN3(na1496_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), + .IN7(na2023_2), .IN8(~na1056_1), .CINX(1'b0), .CINY1(na1009_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y65 80'h00_0078_00_0020_0C66_CCAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a885_1 ( .OUT(na885_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1063_2), .IN7(1'b1), .IN8(na1459_2), + .CINX(1'b0), .CINY1(na906_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a885_4 ( .OUT(na885_2), .COUTY1(na885_4), .IN1(1'b1), .IN2(na1063_2), .IN3(na1455_1), .IN4(1'b1), .IN5(1'b1), .IN6(na1063_2), + .IN7(1'b1), .IN8(na1459_2), .CINX(1'b0), .CINY1(na906_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y66 80'h00_0078_00_0020_0C66_ACCC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a887_1 ( .OUT(na887_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1063_2), .IN7(na1454_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na885_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a887_4 ( .OUT(na887_2), .COUTY1(na887_4), .IN1(1'b1), .IN2(na1063_2), .IN3(1'b1), .IN4(na1452_1), .IN5(1'b1), .IN6(na1063_2), + .IN7(na1454_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na885_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y67 80'h00_0078_00_0020_0C66_CCAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a889_1 ( .OUT(na889_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1063_2), .IN7(1'b1), .IN8(na1447_2), + .CINX(1'b0), .CINY1(na887_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a889_4 ( .OUT(na889_2), .COUTY1(na889_4), .IN1(1'b1), .IN2(na1063_2), .IN3(na1442_1), .IN4(1'b1), .IN5(1'b1), .IN6(na1063_2), + .IN7(1'b1), .IN8(na1447_2), .CINX(1'b0), .CINY1(na887_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y68 80'h00_0078_00_0020_0C66_ACCC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a891_1 ( .OUT(na891_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1063_2), .IN7(na1436_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na889_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a891_4 ( .OUT(na891_2), .COUTY1(na891_4), .IN1(1'b1), .IN2(na1063_2), .IN3(1'b1), .IN4(na1433_1), .IN5(1'b1), .IN6(na1063_2), + .IN7(na1436_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na889_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y69 80'h00_0078_00_0020_0C66_CCAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a893_1 ( .OUT(na893_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1063_2), .IN7(1'b1), .IN8(na1430_2), + .CINX(1'b0), .CINY1(na891_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a893_4 ( .OUT(na893_2), .COUTY1(na893_4), .IN1(1'b1), .IN2(na1063_2), .IN3(na1525_1), .IN4(1'b1), .IN5(1'b1), .IN6(na1063_2), + .IN7(1'b1), .IN8(na1430_2), .CINX(1'b0), .CINY1(na891_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x78y58 80'h00_0018_00_0010_0666_20A8 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a894_1 ( .OUT(na894_1), .COUTY1(na894_4), .IN1(na1059_1), .IN2(na2021_2), .IN3(na1493_2), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), + .IN7(na2024_2), .IN8(~na1056_1), .CINX(1'b0), .CINY1(na883_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y70 80'h00_0078_00_0020_0C66_ACCC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a896_1 ( .OUT(na896_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1063_2), .IN7(na1520_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na893_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a896_4 ( .OUT(na896_2), .COUTY1(na896_4), .IN1(1'b1), .IN2(na1063_2), .IN3(1'b1), .IN4(na1519_1), .IN5(1'b1), .IN6(na1063_2), + .IN7(na1520_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na893_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x78y71 80'h00_0018_00_0010_0666_00CC +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a898_1 ( .OUT(na898_1), .IN1(1'b1), .IN2(na1063_2), .IN3(1'b1), .IN4(na1518_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na896_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x78y59 80'h00_0018_00_0010_0666_208C +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a899_1 ( .OUT(na899_1), .COUTY1(na899_4), .IN1(1'b1), .IN2(na2102_2), .IN3(na1060_1), .IN4(na1056_1), .IN5(1'b0), .IN6(1'b0), + .IN7(na1060_2), .IN8(~na1056_1), .CINX(1'b0), .CINY1(na894_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x78y60 80'h00_0018_00_0010_0666_20C8 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a900_1 ( .OUT(na900_1), .COUTY1(na900_4), .IN1(na1061_1), .IN2(na2021_2), .IN3(1'b1), .IN4(na1491_2), .IN5(1'b0), .IN6(1'b0), + .IN7(na2027_2), .IN8(~na1056_1), .CINX(1'b0), .CINY1(na899_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x78y61 80'h00_0018_00_0010_0666_20A8 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a901_1 ( .OUT(na901_1), .COUTY1(na901_4), .IN1(na1062_1), .IN2(na2021_2), .IN3(na1484_1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), + .IN7(na2028_2), .IN8(~na1056_1), .CINX(1'b0), .CINY1(na900_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y62 80'h00_0078_00_0020_0C66_AACA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a902_1 ( .OUT(na902_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1077_2), .IN6(1'b1), .IN7(na1480_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na901_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a902_4 ( .OUT(na902_2), .COUTY1(na902_4), .IN1(na1077_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1478_1), .IN5(na1077_2), .IN6(1'b1), + .IN7(na1480_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na901_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y63 80'h00_0078_00_0020_0C66_CAAA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a904_1 ( .OUT(na904_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1079_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1475_2), + .CINX(1'b0), .CINY1(na902_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a904_4 ( .OUT(na904_2), .COUTY1(na904_4), .IN1(na1079_1), .IN2(1'b1), .IN3(na1474_1), .IN4(1'b1), .IN5(na1079_2), .IN6(1'b1), + .IN7(1'b1), .IN8(na1475_2), .CINX(1'b0), .CINY1(na902_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x78y64 80'h00_0078_00_0020_0C66_AACA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a906_1 ( .OUT(na906_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1081_2), .IN6(1'b1), .IN7(na1468_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(na904_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a906_4 ( .OUT(na906_2), .COUTY1(na906_4), .IN1(na1081_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1463_1), .IN5(na1081_2), .IN6(1'b1), + .IN7(na1468_2), .IN8(1'b1), .CINX(1'b0), .CINY1(na904_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x96y50 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a907_2 ( .OUT(na907_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a907_6 ( .COUTY1(na907_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na907_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x95y67 80'h00_0078_00_0020_0C66_C0C0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a909_1 ( .OUT(na909_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), .IN8(na260_2), + .CINX(1'b0), .CINY1(na928_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a909_4 ( .OUT(na909_2), .COUTY1(na909_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na260_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b1), + .IN8(na260_2), .CINX(1'b0), .CINY1(na928_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y68 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a911_1 ( .OUT(na911_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na262_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na909_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a911_4 ( .OUT(na911_2), .COUTY1(na911_4), .IN1(1'b1), .IN2(na262_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na262_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na909_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y69 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a913_1 ( .OUT(na913_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na264_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na911_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a913_4 ( .OUT(na913_2), .COUTY1(na913_4), .IN1(1'b1), .IN2(na264_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na264_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na911_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y70 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a915_1 ( .OUT(na915_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na266_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na913_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a915_4 ( .OUT(na915_2), .COUTY1(na915_4), .IN1(1'b1), .IN2(na266_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na266_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na913_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y71 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a917_1 ( .OUT(na917_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na268_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na915_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a917_4 ( .OUT(na917_2), .COUTY1(na917_4), .IN1(1'b1), .IN2(na268_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na268_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na915_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y62 80'h00_0078_00_0020_0C66_CCC0 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a918_1 ( .OUT(na918_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na249_1), .IN7(1'b1), .IN8(na250_2), + .CINX(1'b0), .CINY1(na1222_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a918_4 ( .OUT(na918_2), .COUTY1(na918_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na250_1), .IN5(1'b1), .IN6(na249_1), .IN7(1'b1), + .IN8(na250_2), .CINX(1'b0), .CINY1(na1222_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x95y72 80'h00_0018_00_0010_0666_000C +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a920_1 ( .OUT(na920_1), .IN1(1'b1), .IN2(na269_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na917_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y63 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a922_1 ( .OUT(na922_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na252_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na918_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a922_4 ( .OUT(na922_2), .COUTY1(na922_4), .IN1(1'b1), .IN2(na252_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na252_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na918_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y64 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a924_1 ( .OUT(na924_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na254_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na922_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a924_4 ( .OUT(na924_2), .COUTY1(na924_4), .IN1(1'b1), .IN2(na254_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na254_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na922_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y65 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a926_1 ( .OUT(na926_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na256_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na924_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a926_4 ( .OUT(na926_2), .COUTY1(na926_4), .IN1(1'b1), .IN2(na256_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na256_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na924_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x95y66 80'h00_0078_00_0020_0C66_0C0C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a928_1 ( .OUT(na928_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na258_2), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na926_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a928_4 ( .OUT(na928_2), .COUTY1(na928_4), .IN1(1'b1), .IN2(na258_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na258_2), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na926_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y56 80'h00_0018_00_0010_0666_08A2 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a929_1 ( .OUT(na929_1), .COUTY1(na929_4), .IN1(na1223_2), .IN2(~na1054_1), .IN3(na247_2), .IN4(1'b1), .IN5(na1059_2), .IN6(na1054_1), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na1232_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y63 80'h00_0018_00_0010_0666_08C2 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a930_1 ( .OUT(na930_1), .COUTY1(na930_4), .IN1(na1227_2), .IN2(~na1054_1), .IN3(1'b1), .IN4(na1918_2), .IN5(na1058_2), .IN6(na1054_1), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na950_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y64 80'h00_0018_00_0010_0666_08C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a931_1 ( .OUT(na931_1), .COUTY1(na931_4), .IN1(~na45_1), .IN2(na1063_1), .IN3(1'b1), .IN4(na1917_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na930_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y65 80'h00_0018_00_0010_0666_08C2 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a932_1 ( .OUT(na932_1), .COUTY1(na932_4), .IN1(na1064_1), .IN2(~na1900_2), .IN3(1'b1), .IN4(na260_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na931_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y66 80'h00_0018_00_0010_0666_084C +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a933_1 ( .OUT(na933_1), .COUTY1(na933_4), .IN1(1'b1), .IN2(na1919_2), .IN3(~na1901_2), .IN4(na1065_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na932_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y67 80'h00_0018_00_0010_0666_08C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a934_1 ( .OUT(na934_1), .COUTY1(na934_4), .IN1(~na45_1), .IN2(na2034_2), .IN3(1'b1), .IN4(na1922_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na933_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y68 80'h00_0018_00_0010_0666_08C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a935_1 ( .OUT(na935_1), .COUTY1(na935_4), .IN1(~na45_1), .IN2(na2035_2), .IN3(1'b1), .IN4(na1921_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na934_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y69 80'h00_0018_00_0010_0666_08C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a936_1 ( .OUT(na936_1), .COUTY1(na936_4), .IN1(~na45_1), .IN2(na2036_2), .IN3(1'b1), .IN4(na1924_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na935_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y70 80'h00_0018_00_0010_0666_08C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a937_1 ( .OUT(na937_1), .COUTY1(na937_4), .IN1(~na45_1), .IN2(na2037_2), .IN3(1'b1), .IN4(na1923_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na936_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y71 80'h00_0018_00_0010_0666_08C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a938_1 ( .OUT(na938_1), .COUTY1(na938_4), .IN1(~na45_1), .IN2(na2038_2), .IN3(1'b1), .IN4(na1926_2), .IN5(na45_1), .IN6(na1063_2), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na937_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y72 80'h00_0018_00_0010_0666_80C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a939_1 ( .OUT(na939_1), .COUTY1(na939_4), .IN1(~na1869_2), .IN2(na1063_2), .IN3(1'b1), .IN4(na1925_2), .IN5(1'b0), .IN6(1'b0), + .IN7(na2023_2), .IN8(na5_2), .CINX(1'b0), .CINY1(na938_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y57 80'h00_0018_00_0010_0666_08C2 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a940_1 ( .OUT(na940_1), .COUTY1(na940_4), .IN1(na1224_1), .IN2(~na1054_1), .IN3(1'b1), .IN4(na250_2), .IN5(na2025_2), .IN6(na1054_1), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na929_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y73 80'h00_0018_00_0010_0666_80C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a941_1 ( .OUT(na941_1), .COUTY1(na941_4), .IN1(~na1869_2), .IN2(na1063_2), .IN3(1'b1), .IN4(na1928_2), .IN5(1'b0), .IN6(1'b0), + .IN7(na2024_2), .IN8(na5_2), .CINX(1'b0), .CINY1(na939_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y74 80'h00_0018_00_0010_0666_80C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a942_1 ( .OUT(na942_1), .COUTY1(na942_4), .IN1(~na1869_2), .IN2(na1063_2), .IN3(1'b1), .IN4(na1927_2), .IN5(1'b0), .IN6(1'b0), + .IN7(na1060_2), .IN8(na5_2), .CINX(1'b0), .CINY1(na941_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y75 80'h00_0018_00_0010_0666_80C4 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a943_1 ( .OUT(na943_1), .IN1(~na1869_2), .IN2(na1063_2), .IN3(1'b1), .IN4(na1929_2), .IN5(1'b0), .IN6(1'b0), .IN7(na2027_2), + .IN8(na5_2), .CINX(1'b0), .CINY1(na942_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y58 80'h00_0018_00_0010_0666_08A2 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a944_1 ( .OUT(na944_1), .COUTY1(na944_4), .IN1(na1225_1), .IN2(~na1054_1), .IN3(na1914_2), .IN4(1'b1), .IN5(na1061_2), .IN6(na1054_1), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na940_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x93y59 80'h00_0018_00_0010_0666_08C2 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a945_1 ( .OUT(na945_1), .COUTY1(na945_4), .IN1(na1226_2), .IN2(~na1054_1), .IN3(1'b1), .IN4(na250_1), .IN5(na1062_2), .IN6(na1054_1), + .IN7(1'b0), .IN8(1'b0), .CINX(1'b0), .CINY1(na944_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x93y60 80'h00_0078_00_0020_0C66_2C2C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a946_1 ( .OUT(na946_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na252_2), .IN7(na2040_2), .IN8(~na5_2), + .CINX(1'b0), .CINY1(na945_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a946_4 ( .OUT(na946_2), .COUTY1(na946_4), .IN1(1'b1), .IN2(na252_1), .IN3(na2039_2), .IN4(~na5_2), .IN5(1'b1), .IN6(na252_2), + .IN7(na2040_2), .IN8(~na5_2), .CINX(1'b0), .CINY1(na945_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x93y61 80'h00_0078_00_0020_0C66_2C2C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a948_1 ( .OUT(na948_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na254_2), .IN7(na2043_2), .IN8(~na5_2), + .CINX(1'b0), .CINY1(na946_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a948_4 ( .OUT(na948_2), .COUTY1(na948_4), .IN1(1'b1), .IN2(na254_1), .IN3(na2042_2), .IN4(~na5_2), .IN5(1'b1), .IN6(na254_2), + .IN7(na2043_2), .IN8(~na5_2), .CINX(1'b0), .CINY1(na946_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x93y62 80'h00_0078_00_0020_0C66_2C2C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a950_1 ( .OUT(na950_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na256_2), .IN7(na2045_2), .IN8(~na5_2), + .CINX(1'b0), .CINY1(na948_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a950_4 ( .OUT(na950_2), .COUTY1(na950_4), .IN1(1'b1), .IN2(na256_1), .IN3(na2044_2), .IN4(~na5_2), .IN5(1'b1), .IN6(na256_2), + .IN7(na2045_2), .IN8(~na5_2), .CINX(1'b0), .CINY1(na948_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y62 80'h00_0078_00_0020_0C66_A33A +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a952_1 ( .OUT(na952_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na4_1), .IN7(na1496_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1233_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a952_4 ( .OUT(na952_2), .COUTY1(na952_4), .IN1(na2103_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na7_1), .IN5(1'b1), .IN6(~na4_1), + .IN7(na1496_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na1233_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y67 80'h00_0078_00_0020_0C66_C3C3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a953_1 ( .OUT(na953_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na17_1), .IN7(1'b1), .IN8(na1463_1), + .CINX(1'b0), .CINY1(na982_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a953_4 ( .OUT(na953_2), .COUTY1(na953_4), .IN1(1'b1), .IN2(~na18_1), .IN3(1'b1), .IN4(na1459_2), .IN5(1'b1), .IN6(~na17_1), + .IN7(1'b1), .IN8(na1463_1), .CINX(1'b0), .CINY1(na982_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y68 80'h00_0078_00_0020_0C66_A5A3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a955_1 ( .OUT(na955_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na19_1), .IN6(1'b1), .IN7(na1455_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na953_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a955_4 ( .OUT(na955_2), .COUTY1(na955_4), .IN1(1'b1), .IN2(~na1886_2), .IN3(na1454_2), .IN4(1'b1), .IN5(~na19_1), .IN6(1'b1), + .IN7(na1455_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na953_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y69 80'h00_0078_00_0020_0C66_C5C5 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a957_1 ( .OUT(na957_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na21_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1452_1), + .CINX(1'b0), .CINY1(na955_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a957_4 ( .OUT(na957_2), .COUTY1(na957_4), .IN1(~na22_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1447_2), .IN5(~na21_1), .IN6(1'b1), + .IN7(1'b1), .IN8(na1452_1), .CINX(1'b0), .CINY1(na955_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y70 80'h00_0078_00_0020_0C66_A5A3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a959_1 ( .OUT(na959_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na23_1), .IN6(1'b1), .IN7(na1442_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na957_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a959_4 ( .OUT(na959_2), .COUTY1(na959_4), .IN1(1'b1), .IN2(~na1888_2), .IN3(na1436_2), .IN4(1'b1), .IN5(~na23_1), .IN6(1'b1), + .IN7(na1442_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na957_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y71 80'h00_0078_00_0020_0C66_C3C3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a961_1 ( .OUT(na961_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na25_1), .IN7(1'b1), .IN8(na1433_1), + .CINX(1'b0), .CINY1(na959_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a961_4 ( .OUT(na961_2), .COUTY1(na961_4), .IN1(1'b1), .IN2(~na26_1), .IN3(1'b1), .IN4(na1430_2), .IN5(1'b1), .IN6(~na25_1), + .IN7(1'b1), .IN8(na1433_1), .CINX(1'b0), .CINY1(na959_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y72 80'h00_0078_00_0020_0C66_A5A3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a964_1 ( .OUT(na964_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na27_1), .IN6(1'b1), .IN7(na1525_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na961_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a964_4 ( .OUT(na964_2), .COUTY1(na964_4), .IN1(1'b1), .IN2(~na1891_2), .IN3(na1520_2), .IN4(1'b1), .IN5(~na27_1), .IN6(1'b1), + .IN7(na1525_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na961_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y73 80'h00_0078_00_0020_0C66_C5C3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a966_1 ( .OUT(na966_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na29_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1519_1), + .CINX(1'b0), .CINY1(na964_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a966_4 ( .OUT(na966_2), .COUTY1(na966_4), .IN1(1'b1), .IN2(~na30_1), .IN3(1'b1), .IN4(na1518_2), .IN5(~na29_1), .IN6(1'b1), + .IN7(1'b1), .IN8(na1519_1), .CINX(1'b0), .CINY1(na964_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y74 80'h00_0078_00_0020_0C66_A3A5 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a968_1 ( .OUT(na968_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na1893_2), .IN7(na1517_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na966_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a968_4 ( .OUT(na968_2), .COUTY1(na968_4), .IN1(~na32_1), .IN2(1'b1), .IN3(na1516_2), .IN4(1'b1), .IN5(1'b1), .IN6(~na1893_2), + .IN7(na1517_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na966_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y75 80'h00_0078_00_0020_0C66_C3C5 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a970_1 ( .OUT(na970_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na33_1), .IN7(1'b1), .IN8(na1514_1), + .CINX(1'b0), .CINY1(na968_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a970_4 ( .OUT(na970_2), .COUTY1(na970_4), .IN1(~na34_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1510_2), .IN5(1'b1), .IN6(~na33_1), + .IN7(1'b1), .IN8(na1514_1), .CINX(1'b0), .CINY1(na968_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y76 80'h00_0078_00_0020_0C66_A5A3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a972_1 ( .OUT(na972_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na35_1), .IN6(1'b1), .IN7(na1509_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na970_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a972_4 ( .OUT(na972_2), .COUTY1(na972_4), .IN1(1'b1), .IN2(~na1896_2), .IN3(na1504_2), .IN4(1'b1), .IN5(~na35_1), .IN6(1'b1), + .IN7(na1509_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na970_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y63 80'h00_0078_00_0020_0C66_C35C +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a974_1 ( .OUT(na974_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na8_1), .IN7(1'b1), .IN8(na1492_1), + .CINX(1'b0), .CINY1(na952_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a974_4 ( .OUT(na974_2), .COUTY1(na974_4), .IN1(1'b1), .IN2(na2101_2), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b1), .IN6(~na8_1), + .IN7(1'b1), .IN8(na1492_1), .CINX(1'b0), .CINY1(na952_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y77 80'h00_0078_00_0020_0C66_C3C5 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a975_1 ( .OUT(na975_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na37_1), .IN7(1'b1), .IN8(na1503_1), + .CINX(1'b0), .CINY1(na972_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a975_4 ( .OUT(na975_2), .IN1(~na38_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1497_2), .IN5(1'b1), .IN6(~na37_1), .IN7(1'b1), .IN8(na1503_1), + .CINX(1'b0), .CINY1(na972_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y64 80'h00_0078_00_0020_0C66_3AA3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a978_1 ( .OUT(na978_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2100_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(na974_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a978_4 ( .OUT(na978_2), .COUTY1(na978_4), .IN1(1'b1), .IN2(~na12_1), .IN3(na1480_2), .IN4(1'b1), .IN5(na2100_2), .IN6(1'b1), + .IN7(1'b1), .IN8(~na11_1), .CINX(1'b0), .CINY1(na974_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y65 80'h00_0078_00_0020_0C66_C3C5 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a980_1 ( .OUT(na980_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na13_1), .IN7(1'b1), .IN8(na1478_1), + .CINX(1'b0), .CINY1(na978_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a980_4 ( .OUT(na980_2), .COUTY1(na980_4), .IN1(~na14_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1475_2), .IN5(1'b1), .IN6(~na13_1), + .IN7(1'b1), .IN8(na1478_1), .CINX(1'b0), .CINY1(na978_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x75y66 80'h00_0078_00_0020_0C66_A5A3 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a982_1 ( .OUT(na982_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1881_2), .IN6(1'b1), .IN7(na1474_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na980_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a982_4 ( .OUT(na982_2), .COUTY1(na982_4), .IN1(1'b1), .IN2(~na16_1), .IN3(na1468_2), .IN4(1'b1), .IN5(~na1881_2), .IN6(1'b1), + .IN7(na1474_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na980_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y56 80'h00_0078_00_0020_0C66_ACCA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a984_1 ( .OUT(na984_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na4_1), .IN7(na1496_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1239_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a984_4 ( .OUT(na984_2), .COUTY1(na984_4), .IN1(na2103_2), .IN2(1'b1), .IN3(1'b1), .IN4(na7_1), .IN5(1'b1), .IN6(na4_1), .IN7(na1496_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(na1239_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y61 80'h00_0078_00_0020_0C66_CCCC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a985_1 ( .OUT(na985_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na17_1), .IN7(1'b1), .IN8(na1463_1), + .CINX(1'b0), .CINY1(na1015_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a985_4 ( .OUT(na985_2), .COUTY1(na985_4), .IN1(1'b1), .IN2(na18_1), .IN3(1'b1), .IN4(na1459_2), .IN5(1'b1), .IN6(na17_1), + .IN7(1'b1), .IN8(na1463_1), .CINX(1'b0), .CINY1(na1015_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y62 80'h00_0078_00_0020_0C66_AAAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a987_1 ( .OUT(na987_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na19_1), .IN6(1'b1), .IN7(na1455_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na985_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a987_4 ( .OUT(na987_2), .COUTY1(na987_4), .IN1(1'b1), .IN2(na1886_2), .IN3(na1454_2), .IN4(1'b1), .IN5(na19_1), .IN6(1'b1), + .IN7(na1455_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na985_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y63 80'h00_0078_00_0020_0C66_CACA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a989_1 ( .OUT(na989_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na21_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1452_1), + .CINX(1'b0), .CINY1(na987_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a989_4 ( .OUT(na989_2), .COUTY1(na989_4), .IN1(na22_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1447_2), .IN5(na21_1), .IN6(1'b1), + .IN7(1'b1), .IN8(na1452_1), .CINX(1'b0), .CINY1(na987_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y64 80'h00_0078_00_0020_0C66_AAAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a991_1 ( .OUT(na991_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na23_1), .IN6(1'b1), .IN7(na1442_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na989_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a991_4 ( .OUT(na991_2), .COUTY1(na991_4), .IN1(1'b1), .IN2(na1888_2), .IN3(na1436_2), .IN4(1'b1), .IN5(na23_1), .IN6(1'b1), + .IN7(na1442_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na989_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y65 80'h00_0078_00_0020_0C66_CCCC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a993_1 ( .OUT(na993_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na25_1), .IN7(1'b1), .IN8(na1433_1), + .CINX(1'b0), .CINY1(na991_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a993_4 ( .OUT(na993_2), .COUTY1(na993_4), .IN1(1'b1), .IN2(na26_1), .IN3(1'b1), .IN4(na1430_2), .IN5(1'b1), .IN6(na25_1), + .IN7(1'b1), .IN8(na1433_1), .CINX(1'b0), .CINY1(na991_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y66 80'h00_0078_00_0020_0C66_AAAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a996_1 ( .OUT(na996_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na27_1), .IN6(1'b1), .IN7(na1525_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na993_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a996_4 ( .OUT(na996_2), .COUTY1(na996_4), .IN1(1'b1), .IN2(na1891_2), .IN3(na1520_2), .IN4(1'b1), .IN5(na27_1), .IN6(1'b1), + .IN7(na1525_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na993_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y67 80'h00_0078_00_0020_0C66_CACC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a998_1 ( .OUT(na998_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na29_1), .IN6(1'b1), .IN7(1'b1), .IN8(na1519_1), + .CINX(1'b0), .CINY1(na996_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a998_4 ( .OUT(na998_2), .COUTY1(na998_4), .IN1(1'b1), .IN2(na30_1), .IN3(1'b1), .IN4(na1518_2), .IN5(na29_1), .IN6(1'b1), + .IN7(1'b1), .IN8(na1519_1), .CINX(1'b0), .CINY1(na996_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y68 80'h00_0078_00_0020_0C66_ACAA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1000_1 ( .OUT(na1000_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na1893_2), .IN7(na1517_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na998_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1000_4 ( .OUT(na1000_2), .COUTY1(na1000_4), .IN1(na32_1), .IN2(1'b1), .IN3(na1516_2), .IN4(1'b1), .IN5(1'b1), .IN6(na1893_2), + .IN7(na1517_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na998_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y69 80'h00_0078_00_0020_0C66_CCCA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1002_1 ( .OUT(na1002_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na33_1), .IN7(1'b1), .IN8(na1514_1), + .CINX(1'b0), .CINY1(na1000_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1002_4 ( .OUT(na1002_2), .COUTY1(na1002_4), .IN1(na34_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1510_2), .IN5(1'b1), .IN6(na33_1), + .IN7(1'b1), .IN8(na1514_1), .CINX(1'b0), .CINY1(na1000_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y70 80'h00_0078_00_0020_0C66_AAAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1004_1 ( .OUT(na1004_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na35_1), .IN6(1'b1), .IN7(na1509_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1002_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1004_4 ( .OUT(na1004_2), .COUTY1(na1004_4), .IN1(1'b1), .IN2(na1896_2), .IN3(na1504_2), .IN4(1'b1), .IN5(na35_1), .IN6(1'b1), + .IN7(na1509_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na1002_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y57 80'h00_0078_00_0020_0C66_CCAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1006_1 ( .OUT(na1006_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na8_1), .IN7(1'b1), .IN8(na1492_1), + .CINX(1'b0), .CINY1(na984_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1006_4 ( .OUT(na1006_2), .COUTY1(na1006_4), .IN1(1'b1), .IN2(na2101_2), .IN3(na10_1), .IN4(1'b1), .IN5(1'b1), .IN6(na8_1), + .IN7(1'b1), .IN8(na1492_1), .CINX(1'b0), .CINY1(na984_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y71 80'h00_0078_00_0020_0C66_CCCA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1007_1 ( .OUT(na1007_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na37_1), .IN7(1'b1), .IN8(na1503_1), + .CINX(1'b0), .CINY1(na1004_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1007_4 ( .OUT(na1007_2), .COUTY1(na1007_4), .IN1(na38_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1497_2), .IN5(1'b1), .IN6(na37_1), + .IN7(1'b1), .IN8(na1503_1), .CINX(1'b0), .CINY1(na1004_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x78y56 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1009_2 ( .OUT(na1009_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1009_6 ( .COUTY1(na1009_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1009_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ADDF2///ADDF2/ x70y58 80'h00_0078_00_0020_0C66_CAAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1011_1 ( .OUT(na1011_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na2100_2), .IN6(1'b1), .IN7(1'b1), .IN8(na11_1), + .CINX(1'b0), .CINY1(na1006_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1011_4 ( .OUT(na1011_2), .COUTY1(na1011_4), .IN1(1'b1), .IN2(na12_1), .IN3(na1480_2), .IN4(1'b1), .IN5(na2100_2), .IN6(1'b1), + .IN7(1'b1), .IN8(na11_1), .CINX(1'b0), .CINY1(na1006_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y59 80'h00_0078_00_0020_0C66_CCCA +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1013_1 ( .OUT(na1013_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(na13_1), .IN7(1'b1), .IN8(na1478_1), + .CINX(1'b0), .CINY1(na1011_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1013_4 ( .OUT(na1013_2), .COUTY1(na1013_4), .IN1(na14_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1475_2), .IN5(1'b1), .IN6(na13_1), + .IN7(1'b1), .IN8(na1478_1), .CINX(1'b0), .CINY1(na1011_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x70y60 80'h00_0078_00_0020_0C66_AAAC +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a1015_1 ( .OUT(na1015_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1881_2), .IN6(1'b1), .IN7(na1474_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na1013_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a1015_4 ( .OUT(na1015_2), .COUTY1(na1015_4), .IN1(1'b1), .IN2(na16_1), .IN3(na1468_2), .IN4(1'b1), .IN5(na1881_2), .IN6(1'b1), + .IN7(na1474_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na1013_4), .PINX(1'b0), .PINY1(1'b0) ); +GLBOUT #(.GLBOUT_CFG (64'h0000_0000_0000_0010)) + _a1018 ( .GLB0(na1018_1), .GLB1(_d3), .GLB2(_d4), .GLB3(_d5), .CLK_FB0(_d6), .CLK_FB1(_d7), .CLK_FB2(_d8), .CLK_FB3(_d9), + .CLK0_0(1'b0), .CLK0_90(1'b0), .CLK0_180(1'b0), .CLK0_270(1'b0), .CLK0_BYP(na40_1), .CLK1_0(1'b0), .CLK1_90(1'b0), + .CLK1_180(1'b0), .CLK1_270(1'b0), .CLK1_BYP(1'b0), .CLK2_0(1'b0), .CLK2_90(1'b0), .CLK2_180(1'b0), .CLK2_270(1'b0), + .CLK2_BYP(1'b0), .CLK3_0(1'b0), .CLK3_90(1'b0), .CLK3_180(1'b0), .CLK3_270(1'b0), .CLK3_BYP(1'b0), .USR_GLB0(1'b0), + .USR_GLB1(1'b0), .USR_GLB2(1'b0), .USR_GLB3(1'b0), .USR_FB0(1'b0), .USR_FB1(1'b0), .USR_FB2(1'b0), .USR_FB3(1'b0) ); +// C_AND/D//AND/D x87y56 80'h00_FE00_80_0000_0C88_AFF3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1023_1 ( .OUT(na1023_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na862_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1023_2 ( .OUT(na1023_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1023_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1023_4 ( .OUT(na1023_2_i), .IN1(1'b1), .IN2(~na1023_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1023_5 ( .OUT(na1023_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1023_2_i) ); +// C_AND/D/// x93y54 80'h00_FE00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1025_1 ( .OUT(na1025_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na876_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1025_2 ( .OUT(na1025_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1025_1_i) ); +// C_///AND/D x92y56 80'h00_FE00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1027_4 ( .OUT(na1027_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na878_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1027_5 ( .OUT(na1027_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1027_2_i) ); +// C_AND/D/// x91y55 80'h00_FE00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1029_1 ( .OUT(na1029_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na880_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1029_2 ( .OUT(na1029_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1029_1_i) ); +// C_///AND/D x91y57 80'h00_FE00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1031_4 ( .OUT(na1031_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na882_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1031_5 ( .OUT(na1031_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1031_2_i) ); +// C_///AND/D x89y59 80'h00_FE00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1033_4 ( .OUT(na1033_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na853_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1033_5 ( .OUT(na1033_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1033_2_i) ); +// C_AND/D/// x91y58 80'h00_FE00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1035_1 ( .OUT(na1035_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na855_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1035_2 ( .OUT(na1035_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1035_1_i) ); +// C_AND/D/// x91y59 80'h00_FE00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1037_1 ( .OUT(na1037_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na857_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1037_2 ( .OUT(na1037_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1037_1_i) ); +// C_AND/D/// x94y61 80'h00_FE00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1039_1 ( .OUT(na1039_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na859_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1039_2 ( .OUT(na1039_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1039_1_i) ); +// C_///AND/D x91y59 80'h00_FE00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1041_4 ( .OUT(na1041_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na861_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1041_5 ( .OUT(na1041_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1041_2_i) ); +// C_AND/D/// x94y60 80'h00_FE00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1043_1 ( .OUT(na1043_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na864_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1043_2 ( .OUT(na1043_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1043_1_i) ); +// C_///AND/D x88y61 80'h00_FE00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1045_4 ( .OUT(na1045_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na866_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1045_5 ( .OUT(na1045_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1045_2_i) ); +// C_///AND/D x88y63 80'h00_FE00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1047_4 ( .OUT(na1047_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na868_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1047_5 ( .OUT(na1047_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1047_2_i) ); +// C_///AND/D x94y65 80'h00_FE00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1049_4 ( .OUT(na1049_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na870_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1049_5 ( .OUT(na1049_2), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1049_2_i) ); +// C_AND/D/// x88y61 80'h00_FE00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1051_1 ( .OUT(na1051_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na872_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1051_2 ( .OUT(na1051_1), .CLK(na1018_1), .EN(1'b1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na1051_1_i) ); +// C_///AND/D x85y63 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1053_4 ( .OUT(na1053_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na1154_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1053_5 ( .OUT(na1053_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1053_2_i) ); +// C_AND/D/// x89y58 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1054_1 ( .OUT(na1054_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1165_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1054_2 ( .OUT(na1054_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1054_1_i) ); +// C_AND/D//AND/D x86y61 80'h00_FA00_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1055_1 ( .OUT(na1055_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1168_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1055_2 ( .OUT(na1055_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1055_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1055_4 ( .OUT(na1055_2_i), .IN1(na1170_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1055_5 ( .OUT(na1055_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1055_2_i) ); +// C_AND/D/// x82y58 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1056_1 ( .OUT(na1056_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1169_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1056_2 ( .OUT(na1056_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1056_1_i) ); +// C_AND/D//AND/D x81y53 80'h00_FA00_80_0000_0C88_FCCF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1058_1 ( .OUT(na1058_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1171_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1058_2 ( .OUT(na1058_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1058_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1058_4 ( .OUT(na1058_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1155_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1058_5 ( .OUT(na1058_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1058_2_i) ); +// C_AND/D//AND/D x77y53 80'h00_FA00_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1059_1 ( .OUT(na1059_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1172_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1059_2 ( .OUT(na1059_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1059_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1059_4 ( .OUT(na1059_2_i), .IN1(na1156_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1059_5 ( .OUT(na1059_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1059_2_i) ); +// C_AND/D//AND/D x80y57 80'h00_FA00_80_0000_0C88_FACF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1060_1 ( .OUT(na1060_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1173_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1060_2 ( .OUT(na1060_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1060_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1060_4 ( .OUT(na1060_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1157_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1060_5 ( .OUT(na1060_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1060_2_i) ); +// C_AND/D//AND/D x81y59 80'h00_FA00_80_0000_0C88_FCFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1061_1 ( .OUT(na1061_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1144_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1061_2 ( .OUT(na1061_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1061_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1061_4 ( .OUT(na1061_2_i), .IN1(na1158_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1061_5 ( .OUT(na1061_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1061_2_i) ); +// C_AND/D//AND/D x79y55 80'h00_FA00_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1062_1 ( .OUT(na1062_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1145_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1062_2 ( .OUT(na1062_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1062_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1062_4 ( .OUT(na1062_2_i), .IN1(na1159_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1062_5 ( .OUT(na1062_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1062_2_i) ); +// C_AND/D//AND/D x77y58 80'h00_FA00_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1063_1 ( .OUT(na1063_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1146_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1063_2 ( .OUT(na1063_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1063_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1063_4 ( .OUT(na1063_2_i), .IN1(na1167_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1063_5 ( .OUT(na1063_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1063_2_i) ); +// C_AND/D/// x81y57 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1064_1 ( .OUT(na1064_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1147_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1064_2 ( .OUT(na1064_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1064_1_i) ); +// C_///AND/D x82y60 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1065_4 ( .OUT(na1065_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1148_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1065_5 ( .OUT(na1065_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1065_2_i) ); +// C_AND/D/// x90y66 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1066_1 ( .OUT(na1066_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1149_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1066_2 ( .OUT(na1066_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1066_1_i) ); +// C_///AND/D x90y66 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1067_4 ( .OUT(na1067_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1150_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1067_5 ( .OUT(na1067_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1067_2_i) ); +// C_///AND/D x92y66 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1068_4 ( .OUT(na1068_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1151_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1068_5 ( .OUT(na1068_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1068_2_i) ); +// C_///AND/D x90y68 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1069_4 ( .OUT(na1069_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1152_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1069_5 ( .OUT(na1069_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1069_2_i) ); +// C_AND/D/// x92y68 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1070_1 ( .OUT(na1070_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1153_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1070_2 ( .OUT(na1070_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1070_1_i) ); +// C_AND/D//AND/D x81y55 80'h00_FA00_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1077_1 ( .OUT(na1077_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1161_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1077_2 ( .OUT(na1077_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1077_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1077_4 ( .OUT(na1077_2_i), .IN1(na1160_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1077_5 ( .OUT(na1077_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1077_2_i) ); +// C_AND/D//AND/D x83y59 80'h00_FA00_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1079_1 ( .OUT(na1079_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1163_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1079_2 ( .OUT(na1079_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1079_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1079_4 ( .OUT(na1079_2_i), .IN1(na1162_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1079_5 ( .OUT(na1079_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1079_2_i) ); +// C_AND/D//AND/D x83y53 80'h00_FA00_80_0000_0C88_FAFA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1081_1 ( .OUT(na1081_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1166_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0000)) + _a1081_2 ( .OUT(na1081_1), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1081_1_i) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1081_4 ( .OUT(na1081_2_i), .IN1(na1164_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'b0_0000_0100)) + _a1081_5 ( .OUT(na1081_2), .CLK(na1018_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1081_2_i) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000090)) + _a1108 ( .Y(na1108_1), .I(clk) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1109 ( .O(mem_addr[0]), .A(na1797_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1110 ( .O(mem_addr[1]), .A(na1798_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1111 ( .O(mem_addr[10]), .A(na1799_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1112 ( .O(mem_addr[11]), .A(na1800_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1113 ( .O(mem_addr[12]), .A(na1801_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1114 ( .O(mem_addr[13]), .A(na1802_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1115 ( .O(mem_addr[14]), .A(na1803_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1116 ( .O(mem_addr[15]), .A(na1804_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1117 ( .O(mem_addr[16]), .A(na1805_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1118 ( .O(mem_addr[17]), .A(na1806_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1119 ( .O(mem_addr[18]), .A(na1807_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1120 ( .O(mem_addr[19]), .A(na1808_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1121 ( .O(mem_addr[2]), .A(na1809_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1122 ( .O(mem_addr[20]), .A(na1810_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1123 ( .O(mem_addr[21]), .A(na1811_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1124 ( .O(mem_addr[22]), .A(na1812_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1125 ( .O(mem_addr[23]), .A(na1813_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1126 ( .O(mem_addr[24]), .A(na1814_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1127 ( .O(mem_addr[25]), .A(na1815_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1128 ( .O(mem_addr[26]), .A(na1816_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1129 ( .O(mem_addr[27]), .A(na1817_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1130 ( .O(mem_addr[28]), .A(na1818_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1131 ( .O(mem_addr[29]), .A(na1819_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1132 ( .O(mem_addr[3]), .A(na1820_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1133 ( .O(mem_addr[30]), .A(na1821_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1134 ( .O(mem_addr[31]), .A(na1822_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1135 ( .O(mem_addr[4]), .A(na1823_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1136 ( .O(mem_addr[5]), .A(na1824_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1137 ( .O(mem_addr[6]), .A(na1825_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1138 ( .O(mem_addr[7]), .A(na1826_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1139 ( .O(mem_addr[8]), .A(na1827_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1140 ( .O(mem_addr[9]), .A(na1828_10) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1141 ( .Y(na1141_1), .I(mem_rbusy) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1142 ( .Y(na1142_1), .I(mem_rdata[0]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1143 ( .Y(na1143_1), .I(mem_rdata[1]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1144 ( .Y(na1144_1), .I(mem_rdata[10]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1145 ( .Y(na1145_1), .I(mem_rdata[11]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1146 ( .Y(na1146_1), .I(mem_rdata[12]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1147 ( .Y(na1147_1), .I(mem_rdata[13]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1148 ( .Y(na1148_1), .I(mem_rdata[14]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1149 ( .Y(na1149_1), .I(mem_rdata[15]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1150 ( .Y(na1150_1), .I(mem_rdata[16]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1151 ( .Y(na1151_1), .I(mem_rdata[17]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1152 ( .Y(na1152_1), .I(mem_rdata[18]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1153 ( .Y(na1153_1), .I(mem_rdata[19]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1154 ( .Y(na1154_1), .I(mem_rdata[2]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1155 ( .Y(na1155_1), .I(mem_rdata[20]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1156 ( .Y(na1156_1), .I(mem_rdata[21]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1157 ( .Y(na1157_1), .I(mem_rdata[22]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1158 ( .Y(na1158_1), .I(mem_rdata[23]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1159 ( .Y(na1159_1), .I(mem_rdata[24]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1160 ( .Y(na1160_1), .I(mem_rdata[25]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1161 ( .Y(na1161_1), .I(mem_rdata[26]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1162 ( .Y(na1162_1), .I(mem_rdata[27]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1163 ( .Y(na1163_1), .I(mem_rdata[28]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1164 ( .Y(na1164_1), .I(mem_rdata[29]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1165 ( .Y(na1165_1), .I(mem_rdata[3]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1166 ( .Y(na1166_1), .I(mem_rdata[30]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1167 ( .Y(na1167_1), .I(mem_rdata[31]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1168 ( .Y(na1168_1), .I(mem_rdata[4]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1169 ( .Y(na1169_1), .I(mem_rdata[5]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1170 ( .Y(na1170_1), .I(mem_rdata[6]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1171 ( .Y(na1171_1), .I(mem_rdata[7]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1172 ( .Y(na1172_1), .I(mem_rdata[8]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1173 ( .Y(na1173_1), .I(mem_rdata[9]) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1174 ( .O(mem_rstrb), .A(na1829_10) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a1175 ( .Y(na1175_1), .I(mem_wbusy) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1176 ( .O(mem_wdata[0]), .A(na1830_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1177 ( .O(mem_wdata[1]), .A(na1831_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1178 ( .O(mem_wdata[10]), .A(na1832_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1179 ( .O(mem_wdata[11]), .A(na1833_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1180 ( .O(mem_wdata[12]), .A(na1834_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1181 ( .O(mem_wdata[13]), .A(na1835_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1182 ( .O(mem_wdata[14]), .A(na1836_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1183 ( .O(mem_wdata[15]), .A(na1837_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1184 ( .O(mem_wdata[16]), .A(na1838_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1185 ( .O(mem_wdata[17]), .A(na1839_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1186 ( .O(mem_wdata[18]), .A(na1840_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1187 ( .O(mem_wdata[19]), .A(na1841_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1188 ( .O(mem_wdata[2]), .A(na1842_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1189 ( .O(mem_wdata[20]), .A(na1843_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1190 ( .O(mem_wdata[21]), .A(na1844_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1191 ( .O(mem_wdata[22]), .A(na1845_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1192 ( .O(mem_wdata[23]), .A(na1846_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1193 ( .O(mem_wdata[24]), .A(na1847_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1194 ( .O(mem_wdata[25]), .A(na1848_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1195 ( .O(mem_wdata[26]), .A(na1849_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1196 ( .O(mem_wdata[27]), .A(na1850_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1197 ( .O(mem_wdata[28]), .A(na1851_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1198 ( .O(mem_wdata[29]), .A(na1852_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1199 ( .O(mem_wdata[3]), .A(na1853_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1200 ( .O(mem_wdata[30]), .A(na1854_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1201 ( .O(mem_wdata[31]), .A(na1855_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1202 ( .O(mem_wdata[4]), .A(na1856_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1203 ( .O(mem_wdata[5]), .A(na1857_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1204 ( .O(mem_wdata[6]), .A(na1858_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1205 ( .O(mem_wdata[7]), .A(na1859_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1206 ( .O(mem_wdata[8]), .A(na1860_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1207 ( .O(mem_wdata[9]), .A(na1861_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1208 ( .O(mem_wmask[0]), .A(na1862_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1209 ( .O(mem_wmask[1]), .A(na1863_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1210 ( .O(mem_wmask[2]), .A(na1864_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a1211 ( .O(mem_wmask[3]), .A(na1865_10) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000050)) + _a1212 ( .Y(na1212_1), .I(reset) ); +FPGA_RAM #(.RAM_CFG (216'h00_05_00_00_00_00_00_00_00_06_00_00_C3_03_00_23_00_00_23_00_13_23_00_00_23_00_00), + .INIT_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000)) + _a1213 ( .DOA({na1213_1, na1213_2, na1213_3, na1213_4, na1213_5, na1213_6, na1213_7, na1213_8, na1213_9, na1213_10, na1213_11, + na1213_12, na1213_13, na1213_14, na1213_15, na1213_16, na1213_17, na1213_18, na1213_19, na1213_20, _d10, _d11, _d12, + _d13, _d14, _d15, _d16, _d17, _d18, _d19, _d20, _d21, _d22, _d23, _d24, _d25, _d26, _d27, _d28, _d29}), + .DOAX({_d30, _d31, _d32, _d33, _d34, _d35, _d36, _d37, _d38, _d39, _d40, _d41, _d42, _d43, _d44, _d45, _d46, _d47, + _d48, _d49, _d50, _d51, _d52, _d53, _d54, _d55, _d56, _d57, _d58, _d59, _d60, _d61, _d62, _d63, _d64, _d65, _d66, + _d67, _d68, _d69}), + .DOB({_d70, _d71, _d72, _d73, _d74, _d75, _d76, _d77, na1213_89, na1213_90, na1213_91, na1213_92, na1213_93, na1213_94, + na1213_95, na1213_96, na1213_97, na1213_98, na1213_99, na1213_100, _d78, _d79, _d80, _d81, _d82, _d83, _d84, _d85, + _d86, _d87, _d88, _d89, _d90, _d91, _d92, _d93, _d94, _d95, _d96, _d97}), + .DOBX({_d98, _d99, _d100, _d101, _d102, _d103, _d104, _d105, _d106, _d107, _d108, _d109, _d110, _d111, _d112, _d113, + _d114, _d115, _d116, _d117, _d118, _d119, _d120, _d121, _d122, _d123, _d124, _d125, _d126, _d127, _d128, _d129, _d130, + _d131, _d132, _d133, _d134, _d135, _d136, _d137}), + .ECC1B_ERRA({_d138, _d139, _d140, _d141}), + .ECC1B_ERRB({_d142, _d143, _d144, _d145}), + .ECC2B_ERRA({_d146, _d147, _d148, _d149}), + .ECC2B_ERRB({_d150, _d151, _d152, _d153}), + .FORW_CAS_WRAO(_d154), .FORW_CAS_WRBO(_d155), .FORW_CAS_BMAO(_d156), .FORW_CAS_BMBO(_d157), .FORW_CAS_RDAO(_d158), + .FORW_CAS_RDBO(_d159), .FORW_UADDRAO({_d160, _d161, _d162, _d163, _d164, _d165, _d166, _d167, _d168, _d169, _d170, + _d171, _d172, _d173, _d174, _d175}), + .FORW_LADDRAO({_d176, _d177, _d178, _d179, _d180, _d181, _d182, _d183, _d184, _d185, _d186, _d187, _d188, _d189, + _d190, _d191}), + .FORW_UADDRBO({_d192, _d193, _d194, _d195, _d196, _d197, _d198, _d199, _d200, _d201, _d202, _d203, _d204, _d205, + _d206, _d207}), + .FORW_LADDRBO({_d208, _d209, _d210, _d211, _d212, _d213, _d214, _d215, _d216, _d217, _d218, _d219, _d220, _d221, + _d222, _d223}), + .FORW_UA0CLKO(_d224), .FORW_UA0ENO(_d225), .FORW_UA0WEO(_d226), .FORW_LA0CLKO(_d227), .FORW_LA0ENO(_d228), .FORW_LA0WEO(_d229), + .FORW_UA1CLKO(_d230), .FORW_UA1ENO(_d231), .FORW_UA1WEO(_d232), .FORW_LA1CLKO(_d233), .FORW_LA1ENO(_d234), .FORW_LA1WEO(_d235), + .FORW_UB0CLKO(_d236), .FORW_UB0ENO(_d237), .FORW_UB0WEO(_d238), .FORW_LB0CLKO(_d239), .FORW_LB0ENO(_d240), .FORW_LB0WEO(_d241), + .FORW_UB1CLKO(_d242), .FORW_UB1ENO(_d243), .FORW_UB1WEO(_d244), .FORW_LB1CLKO(_d245), .FORW_LB1ENO(_d246), .FORW_LB1WEO(_d247), + .CLOCKA({_d248, _d249, _d250, _d251}), + .CLOCKB({_d252, _d253, _d254, _d255}), + .CLKA({1'b1, 1'b1, 1'b1, 1'b1}), + .CLKB({1'b1, 1'b1, 1'b1, 1'b1}), + .ENA({1'b1, 1'b1, 1'b1, 1'b1}), + .ENB({1'b1, na1215_9, 1'b1, 1'b1}), + .GLWEA({1'b1, na1217_10, 1'b1, 1'b1}), + .GLWEB({1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA0({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA1({na1219_10, na1221_9, na1230_10, na1234_9, na1237_10, na1238_9, na1241_10, na1242_9, na1245_10, na1246_9, + na1247_10, na1249_9, na1250_10, na1251_9, na1253_10, na1254_9}), + .ADDRA0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB0({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB1({na1255_10, na1257_9, na1258_10, na1259_9, na1261_10, na1262_9, na1263_10, na1265_9, na1266_10, na1267_9, + na1269_10, na1270_9, na1271_10, na1273_9, na1274_10, na1275_9}), + .ADDRB1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .DIA({na1277_10, na1278_9, na1279_10, na1281_9, na1282_10, na1283_9, na1285_10, na1286_9, na1287_10, na1289_9, na1290_10, + na1291_9, na1293_10, na1294_9, na1295_10, na1297_9, na1298_10, na1299_9, na1301_10, na1302_9, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .DIB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, na1303_10, na1305_9, na1306_10, na1307_9, na1309_10, na1310_9, + na1311_10, na1313_9, na1314_10, na1315_9, na1317_10, na1318_9, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .WEA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .WEB({na1319_10, na1321_9, na1322_10, na1323_9, na1324_10, na1325_9, na1328_10, na1330_9, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .CLOCK1(na1018_1), .CLOCK2(1'b1), .CLOCK3(1'b1), .CLOCK4(1'b1), .FORW_CAS_WRAI(1'b1), .FORW_CAS_WRBI(1'b1), .FORW_CAS_BMAI(1'b1), + .FORW_CAS_BMBI(1'b1), .FORW_CAS_RDAI(1'b1), .FORW_CAS_RDBI(1'b1), .FORW_LADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LA0CLKI(1'b1), .FORW_LA0ENI(1'b1), .FORW_LA0WEI(1'b1), .FORW_UA0CLKI(1'b1), .FORW_UA0ENI(1'b1), .FORW_UA0WEI(1'b1), + .FORW_LA1CLKI(1'b1), .FORW_LA1ENI(1'b1), .FORW_LA1WEI(1'b1), .FORW_UA1CLKI(1'b1), .FORW_UA1ENI(1'b1), .FORW_UA1WEI(1'b1), + .FORW_LB0CLKI(1'b1), .FORW_LB0ENI(1'b1), .FORW_LB0WEI(1'b1), .FORW_UB0CLKI(1'b1), .FORW_UB0ENI(1'b1), .FORW_UB0WEI(1'b1), + .FORW_LB1CLKI(1'b1), .FORW_LB1ENI(1'b1), .FORW_LB1WEI(1'b1), .FORW_UB1CLKI(1'b1), .FORW_UB1ENI(1'b1), .FORW_UB1WEI(1'b1) ); +FPGA_RAM #(.RAM_CFG (216'h00_05_00_00_00_00_00_00_00_00_C0_00_1B_00_00_23_03_00_23_00_00_23_00_13_23_00_00), + .INIT_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_40(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_41(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_42(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_43(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_44(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_45(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_46(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_47(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_48(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_49(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_4F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_50(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_51(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_52(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_53(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_54(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_55(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_56(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_57(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_58(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_59(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_5F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_60(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_61(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_62(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_63(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_64(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_65(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_66(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_67(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_68(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_69(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_6F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_70(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_71(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_72(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_73(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_74(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_75(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_76(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_77(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_78(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_79(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_7F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000)) + _a1214 ( .DOA({_d256, _d257, _d258, _d259, _d260, _d261, _d262, _d263, _d264, _d265, _d266, _d267, _d268, _d269, _d270, _d271, + _d272, _d273, _d274, _d275, na1214_21, na1214_22, na1214_23, na1214_24, na1214_25, na1214_26, na1214_27, na1214_28, + na1214_29, na1214_30, na1214_31, na1214_32, na1214_33, na1214_34, na1214_35, na1214_36, na1214_37, na1214_38, na1214_39, + na1214_40}), + .DOAX({_d276, _d277, _d278, _d279, _d280, _d281, _d282, _d283, _d284, _d285, _d286, _d287, _d288, _d289, _d290, + _d291, _d292, _d293, _d294, _d295, _d296, _d297, _d298, _d299, _d300, _d301, _d302, _d303, _d304, _d305, _d306, _d307, + _d308, _d309, _d310, _d311, _d312, _d313, _d314, _d315}), + .DOB({_d316, _d317, _d318, _d319, _d320, _d321, _d322, _d323, _d324, _d325, _d326, _d327, _d328, _d329, _d330, _d331, + _d332, _d333, _d334, _d335, _d336, _d337, _d338, _d339, _d340, _d341, _d342, _d343, na1214_109, na1214_110, na1214_111, + na1214_112, na1214_113, na1214_114, na1214_115, na1214_116, na1214_117, na1214_118, na1214_119, na1214_120}), + .DOBX({_d344, _d345, _d346, _d347, _d348, _d349, _d350, _d351, _d352, _d353, _d354, _d355, _d356, _d357, _d358, + _d359, _d360, _d361, _d362, _d363, _d364, _d365, _d366, _d367, _d368, _d369, _d370, _d371, _d372, _d373, _d374, _d375, + _d376, _d377, _d378, _d379, _d380, _d381, _d382, _d383}), + .ECC1B_ERRA({_d384, _d385, _d386, _d387}), + .ECC1B_ERRB({_d388, _d389, _d390, _d391}), + .ECC2B_ERRA({_d392, _d393, _d394, _d395}), + .ECC2B_ERRB({_d396, _d397, _d398, _d399}), + .FORW_CAS_WRAO(_d400), .FORW_CAS_WRBO(_d401), .FORW_CAS_BMAO(_d402), .FORW_CAS_BMBO(_d403), .FORW_CAS_RDAO(_d404), + .FORW_CAS_RDBO(_d405), .FORW_UADDRAO({_d406, _d407, _d408, _d409, _d410, _d411, _d412, _d413, _d414, _d415, _d416, + _d417, _d418, _d419, _d420, _d421}), + .FORW_LADDRAO({_d422, _d423, _d424, _d425, _d426, _d427, _d428, _d429, _d430, _d431, _d432, _d433, _d434, _d435, + _d436, _d437}), + .FORW_UADDRBO({_d438, _d439, _d440, _d441, _d442, _d443, _d444, _d445, _d446, _d447, _d448, _d449, _d450, _d451, + _d452, _d453}), + .FORW_LADDRBO({_d454, _d455, _d456, _d457, _d458, _d459, _d460, _d461, _d462, _d463, _d464, _d465, _d466, _d467, + _d468, _d469}), + .FORW_UA0CLKO(_d470), .FORW_UA0ENO(_d471), .FORW_UA0WEO(_d472), .FORW_LA0CLKO(_d473), .FORW_LA0ENO(_d474), .FORW_LA0WEO(_d475), + .FORW_UA1CLKO(_d476), .FORW_UA1ENO(_d477), .FORW_UA1WEO(_d478), .FORW_LA1CLKO(_d479), .FORW_LA1ENO(_d480), .FORW_LA1WEO(_d481), + .FORW_UB0CLKO(_d482), .FORW_UB0ENO(_d483), .FORW_UB0WEO(_d484), .FORW_LB0CLKO(_d485), .FORW_LB0ENO(_d486), .FORW_LB0WEO(_d487), + .FORW_UB1CLKO(_d488), .FORW_UB1ENO(_d489), .FORW_UB1WEO(_d490), .FORW_LB1CLKO(_d491), .FORW_LB1ENO(_d492), .FORW_LB1WEO(_d493), + .CLOCKA({_d494, _d495, _d496, _d497}), + .CLOCKB({_d498, _d499, _d500, _d501}), + .CLKA({1'b1, 1'b1, 1'b1, 1'b1}), + .CLKB({1'b1, 1'b1, 1'b1, 1'b1}), + .ENA({1'b1, 1'b1, 1'b1, 1'b1}), + .ENB({1'b1, 1'b1, 1'b1, na1334_9}), + .GLWEA({1'b1, 1'b1, 1'b1, na1335_10}), + .GLWEB({1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA0({na1338_10, na1339_9, na1340_10, na1343_9, na1344_10, na1345_9, na1354_10, na1358_9, na1360_10, na1363_9, + na1367_10, na1368_9, na1369_10, na1371_9, na1373_10, na1378_9}), + .ADDRA1({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRA1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB0({na1380_10, na1381_9, na1385_10, na1387_9, na1388_10, na1392_9, na1398_10, na1403_9, na1404_10, na1405_9, + na1406_10, na1409_9, na1416_10, na1419_9, na1423_10, na1425_9}), + .ADDRB0X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB1({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .ADDRB1X({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .C_ADDRB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .DIA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, na1430_10, na1433_9, na1436_10, na1442_9, na1447_10, na1452_9, na1454_10, na1455_9, na1459_10, na1463_9, + na1468_10, na1474_9, na1475_10, na1478_9, na1480_10, na1484_9, na1491_10, na1492_9, na1493_10, na1496_9}), + .DIB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, na1497_10, na1503_9, na1504_10, na1509_9, na1510_10, + na1514_9, na1516_10, na1517_9, na1518_10, na1519_9, na1520_10, na1525_9}), + .WEA({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1}), + .WEB({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, na1526_10, na1530_9, na1533_10, na1534_9, na1535_10, na1539_9, na1540_10, na1546_9, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .CLOCK1(na1018_1), .CLOCK2(1'b1), .CLOCK3(1'b1), .CLOCK4(1'b1), .FORW_CAS_WRAI(1'b1), .FORW_CAS_WRBI(1'b1), .FORW_CAS_BMAI(1'b1), + .FORW_CAS_BMBI(1'b1), .FORW_CAS_RDAI(1'b1), .FORW_CAS_RDBI(1'b1), .FORW_LADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, + 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRAI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_UADDRBI({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), + .FORW_LA0CLKI(1'b1), .FORW_LA0ENI(1'b1), .FORW_LA0WEI(1'b1), .FORW_UA0CLKI(1'b1), .FORW_UA0ENI(1'b1), .FORW_UA0WEI(1'b1), + .FORW_LA1CLKI(1'b1), .FORW_LA1ENI(1'b1), .FORW_LA1WEI(1'b1), .FORW_UA1CLKI(1'b1), .FORW_UA1ENI(1'b1), .FORW_UA1WEI(1'b1), + .FORW_LB0CLKI(1'b1), .FORW_LB0ENI(1'b1), .FORW_LB0WEI(1'b1), .FORW_UB0CLKI(1'b1), .FORW_UB0ENI(1'b1), .FORW_UB0WEI(1'b1), + .FORW_LB1CLKI(1'b1), .FORW_LB1ENI(1'b1), .FORW_LB1WEI(1'b1), .FORW_UB1CLKI(1'b1), .FORW_UB1ENI(1'b1), .FORW_UB1WEI(1'b1) ); +// C_AND//// x67y58 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1215_1 ( .OUT(na1215_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na240_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1215_6 ( .RAM_O1(na1215_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1215_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x88y72 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1216_4 ( .OUT(na1216_2), .IN1(na1141_1), .IN2(1'b1), .IN3(na42_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x59y57 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1217_4 ( .OUT(na1217_2), .IN1(1'b1), .IN2(na39_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1217_6 ( .RAM_O2(na1217_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1217_2), .COMP_OUT(1'b0) ); +// C_///AND/ x86y71 80'h00_0060_00_0000_0C08_FF1F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1218_4 ( .OUT(na1218_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na240_2), .IN4(~na241_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y64 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1219_4 ( .OUT(na1219_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1219_6 ( .RAM_O2(na1219_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1219_2), .COMP_OUT(1'b0) ); +// C_AND//// x79y51 80'h00_0018_00_0000_0888_F151 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1220_1 ( .OUT(na1220_1), .IN1(~na1059_1), .IN2(~na2022_2), .IN3(~na1060_1), .IN4(1'b1), .IN5(~na1062_1), .IN6(~na2026_2), + .IN7(1'b1), .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y64 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1221_1 ( .OUT(na1221_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1221_6 ( .RAM_O1(na1221_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1221_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x95y61 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1222_2 ( .OUT(na1222_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1222_6 ( .COUTY1(na1222_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1222_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x83y61 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1223_4 ( .OUT(na1223_2), .IN1(na1059_1), .IN2(1'b1), .IN3(~na1055_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x83y57 80'h00_0018_00_0000_0C88_A5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1224_1 ( .OUT(na1224_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2019_2), .IN6(1'b1), .IN7(na1060_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x95y53 80'h00_0018_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1225_1 ( .OUT(na1225_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1061_1), .IN6(1'b1), .IN7(~na1055_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x81y61 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1226_4 ( .OUT(na1226_2), .IN1(na1062_1), .IN2(1'b1), .IN3(~na1055_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x81y63 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1227_4 ( .OUT(na1227_2), .IN1(na1058_1), .IN2(1'b1), .IN3(~na1055_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x87y76 80'h00_0078_00_0000_0C88_3A2F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1228_1 ( .OUT(na1228_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na47_2), .IN6(1'b1), .IN7(1'b1), .IN8(~na44_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1228_4 ( .OUT(na1228_2), .IN1(1'b1), .IN2(1'b1), .IN3(na240_2), .IN4(~na44_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x80y75 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1229_1 ( .OUT(na1229_1), .IN1(~na78_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1981_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y63 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1230_4 ( .OUT(na1230_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1230_6 ( .RAM_O2(na1230_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1230_2), .COMP_OUT(1'b0) ); +// C_AND//// x89y68 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1231_1 ( .OUT(na1231_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na86_1), .IN7(1'b1), .IN8(na81_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x93y55 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1232_2 ( .OUT(na1232_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1232_6 ( .COUTY1(na1232_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1232_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x75y61 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1233_2 ( .OUT(na1233_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1233_6 ( .COUTY1(na1233_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1233_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x60y63 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1234_1 ( .OUT(na1234_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1234_6 ( .RAM_O1(na1234_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1234_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x93y81 80'h00_0060_00_0000_0C08_FF1F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1235_4 ( .OUT(na1235_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na42_1), .IN4(~na50_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y78 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1236_1 ( .OUT(na1236_1), .IN1(~na107_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1986_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y62 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1237_4 ( .OUT(na1237_2), .IN1(na1062_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1237_6 ( .RAM_O2(na1237_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1237_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y62 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1238_1 ( .OUT(na1238_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1061_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1238_6 ( .RAM_O1(na1238_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1238_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_/C_0_1/// x70y55 80'h00_3F00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a1239_2 ( .OUT(na1239_1), .CLK(1'b1), .EN(1'b0), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a1239_6 ( .COUTY1(na1239_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1239_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x94y74 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1240_1 ( .OUT(na1240_1), .IN1(~na112_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1987_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y61 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1241_4 ( .OUT(na1241_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1060_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1241_6 ( .RAM_O2(na1241_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1241_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y61 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1242_1 ( .OUT(na1242_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1059_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1242_6 ( .RAM_O1(na1242_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1242_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_Route1//// x70y72 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a1243_1 ( .OUT(na1243_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na1007_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x96y72 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1244_1 ( .OUT(na1244_1), .IN1(~na117_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1988_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y60 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1245_4 ( .OUT(na1245_2), .IN1(na1058_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1245_6 ( .RAM_O2(na1245_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1245_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y60 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1246_1 ( .OUT(na1246_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1246_6 ( .RAM_O1(na1246_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1246_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x60y59 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1247_4 ( .OUT(na1247_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1247_6 ( .RAM_O2(na1247_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1247_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x98y75 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1248_1 ( .OUT(na1248_1), .IN1(~na122_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1989_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y59 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1249_1 ( .OUT(na1249_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1249_6 ( .RAM_O1(na1249_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1249_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x60y58 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1250_4 ( .OUT(na1250_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1250_6 ( .RAM_O2(na1250_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1250_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y58 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1251_1 ( .OUT(na1251_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1251_6 ( .RAM_O1(na1251_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1251_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x100y71 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1252_1 ( .OUT(na1252_1), .IN1(~na127_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1990_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y57 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1253_4 ( .OUT(na1253_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1253_6 ( .RAM_O2(na1253_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1253_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y57 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1254_1 ( .OUT(na1254_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1254_6 ( .RAM_O1(na1254_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1254_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y64 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1255_4 ( .OUT(na1255_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1255_6 ( .RAM_O2(na1255_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1255_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x100y73 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1256_1 ( .OUT(na1256_1), .IN1(~na132_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1991_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y64 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1257_1 ( .OUT(na1257_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1257_6 ( .RAM_O1(na1257_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1257_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y63 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1258_4 ( .OUT(na1258_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1258_6 ( .RAM_O2(na1258_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1258_2), .COMP_OUT(1'b0) ); +// C_AND//// x69y63 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1259_1 ( .OUT(na1259_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1259_6 ( .RAM_O1(na1259_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1259_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x100y74 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1260_1 ( .OUT(na1260_1), .IN1(~na137_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1992_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y62 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1261_4 ( .OUT(na1261_2), .IN1(na1159_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1261_6 ( .RAM_O2(na1261_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1261_2), .COMP_OUT(1'b0) ); +// C_AND//// x69y62 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1262_1 ( .OUT(na1262_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1158_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1262_6 ( .RAM_O1(na1262_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1262_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y61 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1263_4 ( .OUT(na1263_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1157_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1263_6 ( .RAM_O2(na1263_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1263_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x96y74 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1264_1 ( .OUT(na1264_1), .IN1(~na142_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1993_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y61 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1265_1 ( .OUT(na1265_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1156_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1265_6 ( .RAM_O1(na1265_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1265_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y60 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1266_4 ( .OUT(na1266_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1155_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1266_6 ( .RAM_O2(na1266_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1266_2), .COMP_OUT(1'b0) ); +// C_AND//// x69y60 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1267_1 ( .OUT(na1267_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1267_6 ( .RAM_O1(na1267_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1267_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x92y76 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1268_1 ( .OUT(na1268_1), .IN1(~na147_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1994_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y59 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1269_4 ( .OUT(na1269_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1269_6 ( .RAM_O2(na1269_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1269_2), .COMP_OUT(1'b0) ); +// C_AND//// x69y59 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1270_1 ( .OUT(na1270_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1270_6 ( .RAM_O1(na1270_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1270_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y58 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1271_4 ( .OUT(na1271_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1271_6 ( .RAM_O2(na1271_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1271_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x80y79 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1272_1 ( .OUT(na1272_1), .IN1(~na152_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1971_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y58 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1273_1 ( .OUT(na1273_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1273_6 ( .RAM_O1(na1273_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1273_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y57 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1274_4 ( .OUT(na1274_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1274_6 ( .RAM_O2(na1274_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1274_2), .COMP_OUT(1'b0) ); +// C_AND//// x69y57 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1275_1 ( .OUT(na1275_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1275_6 ( .RAM_O1(na1275_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1275_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x84y79 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1276_1 ( .OUT(na1276_1), .IN1(~na157_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1972_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x62y64 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1277_4 ( .OUT(na1277_2_i), .IN1(na827_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1277_5 ( .OUT(na1277_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_1), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1277_6 ( .RAM_O2(na1277_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1277_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x62y64 80'h05_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1278_1 ( .OUT(na1278_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na824_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1278_2 ( .OUT(na1278_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_2), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1278_6 ( .RAM_O1(na1278_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1278_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x62y63 80'h0A_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1279_4 ( .OUT(na1279_2_i), .IN1(1'b1), .IN2(na616_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1279_5 ( .OUT(na1279_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_3), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1279_6 ( .RAM_O2(na1279_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1279_2_i), .COMP_OUT(1'b0) ); +// C_ORAND//// x86y77 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1280_1 ( .OUT(na1280_1), .IN1(~na162_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1973_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x62y63 80'h05_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1281_1 ( .OUT(na1281_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na821_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1281_2 ( .OUT(na1281_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_4), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1281_6 ( .RAM_O1(na1281_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1281_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x64y64 80'h0A_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1282_4 ( .OUT(na1282_2_i), .IN1(1'b1), .IN2(na594_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1282_5 ( .OUT(na1282_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_5), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1282_6 ( .RAM_O2(na1282_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1282_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y64 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1283_1 ( .OUT(na1283_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na581_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1283_2 ( .OUT(na1283_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_6), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1283_6 ( .RAM_O1(na1283_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1283_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x90y77 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1284_1 ( .OUT(na1284_1), .IN1(~na167_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1974_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y63 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1285_4 ( .OUT(na1285_2_i), .IN1(na568_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1285_5 ( .OUT(na1285_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_7), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1285_6 ( .RAM_O2(na1285_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1285_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y63 80'h05_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1286_1 ( .OUT(na1286_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na812_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1286_2 ( .OUT(na1286_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_8), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1286_6 ( .RAM_O1(na1286_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1286_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x64y62 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1287_4 ( .OUT(na1287_2_i), .IN1(na809_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1287_5 ( .OUT(na1287_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_9), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1287_6 ( .RAM_O2(na1287_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1287_2_i), .COMP_OUT(1'b0) ); +// C_ORAND//// x90y83 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1288_1 ( .OUT(na1288_1), .IN1(~na172_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1975_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y62 80'h05_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1289_1 ( .OUT(na1289_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na805_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1289_2 ( .OUT(na1289_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_10), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1289_6 ( .RAM_O1(na1289_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1289_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x64y61 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1290_4 ( .OUT(na1290_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na802_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1290_5 ( .OUT(na1290_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_11), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1290_6 ( .RAM_O2(na1290_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1290_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y61 80'h05_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1291_1 ( .OUT(na1291_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na513_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1291_2 ( .OUT(na1291_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_12), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1291_6 ( .RAM_O1(na1291_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1291_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x88y76 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1292_1 ( .OUT(na1292_1), .IN1(~na177_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1976_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y60 80'h0A_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1293_4 ( .OUT(na1293_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na796_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1293_5 ( .OUT(na1293_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_13), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1293_6 ( .RAM_O2(na1293_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1293_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y60 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1294_1 ( .OUT(na1294_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na792_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1294_2 ( .OUT(na1294_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_14), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1294_6 ( .RAM_O1(na1294_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1294_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x64y59 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1295_4 ( .OUT(na1295_2_i), .IN1(na850_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1295_5 ( .OUT(na1295_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_15), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1295_6 ( .RAM_O2(na1295_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1295_2_i), .COMP_OUT(1'b0) ); +// C_ORAND//// x90y79 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1296_1 ( .OUT(na1296_1), .IN1(~na182_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1977_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y59 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1297_1 ( .OUT(na1297_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na440_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1297_2 ( .OUT(na1297_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_16), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1297_6 ( .RAM_O1(na1297_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1297_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x64y58 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1298_4 ( .OUT(na1298_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na847_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1298_5 ( .OUT(na1298_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_17), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1298_6 ( .RAM_O2(na1298_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1298_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y58 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1299_1 ( .OUT(na1299_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na787_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1299_2 ( .OUT(na1299_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_18), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1299_6 ( .RAM_O1(na1299_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1299_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x90y78 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1300_1 ( .OUT(na1300_1), .IN1(~na187_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1978_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y57 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1301_4 ( .OUT(na1301_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na351_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1301_5 ( .OUT(na1301_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_19), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1301_6 ( .RAM_O2(na1301_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1301_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y57 80'h05_0018_00_0000_0C88_F5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1302_1 ( .OUT(na1302_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na270_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1302_2 ( .OUT(na1302_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_20), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1302_6 ( .RAM_O1(na1302_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1302_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y62 80'h0A_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1303_4 ( .OUT(na1303_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na727_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1303_5 ( .OUT(na1303_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_89), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1303_6 ( .RAM_O2(na1303_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1303_2_i), .COMP_OUT(1'b0) ); +// C_ORAND//// x82y81 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1304_1 ( .OUT(na1304_1), .IN1(~na192_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1979_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x66y62 80'h05_0018_00_0000_0C88_F3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1305_1 ( .OUT(na1305_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na718_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1305_2 ( .OUT(na1305_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_90), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1305_6 ( .RAM_O1(na1305_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1305_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y61 80'h0A_0060_00_0000_0C08_FFF5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1306_4 ( .OUT(na1306_2_i), .IN1(~na711_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1306_5 ( .OUT(na1306_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_91), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1306_6 ( .RAM_O2(na1306_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1306_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x66y61 80'h05_0018_00_0000_0C88_F5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1307_1 ( .OUT(na1307_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na702_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1307_2 ( .OUT(na1307_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_92), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1307_6 ( .RAM_O1(na1307_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1307_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x86y83 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1308_1 ( .OUT(na1308_1), .IN1(~na197_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1980_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x66y60 80'h0A_0060_00_0000_0C08_FF3F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1309_4 ( .OUT(na1309_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na693_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1309_5 ( .OUT(na1309_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_93), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1309_6 ( .RAM_O2(na1309_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1309_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x66y60 80'h05_0018_00_0000_0C88_F3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1310_1 ( .OUT(na1310_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na683_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1310_2 ( .OUT(na1310_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_94), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1310_6 ( .RAM_O1(na1310_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1310_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y59 80'h0A_0060_00_0000_0C08_FF3F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1311_4 ( .OUT(na1311_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na677_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1311_5 ( .OUT(na1311_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_95), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1311_6 ( .RAM_O2(na1311_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1311_2_i), .COMP_OUT(1'b0) ); +// C_ORAND//// x92y79 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1312_1 ( .OUT(na1312_1), .IN1(~na202_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1983_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x66y59 80'h05_0018_00_0000_0C88_3FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1313_1 ( .OUT(na1313_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(~na671_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1313_2 ( .OUT(na1313_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_96), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1313_6 ( .RAM_O1(na1313_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1313_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y58 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1314_4 ( .OUT(na1314_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na838_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1314_5 ( .OUT(na1314_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_97), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1314_6 ( .RAM_O2(na1314_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1314_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x66y58 80'h05_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1315_1 ( .OUT(na1315_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na655_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1315_2 ( .OUT(na1315_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_98), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1315_6 ( .RAM_O1(na1315_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1315_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x94y80 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1316_1 ( .OUT(na1316_1), .IN1(~na207_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1984_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x66y57 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1317_4 ( .OUT(na1317_2_i), .IN1(na833_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1317_5 ( .OUT(na1317_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_99), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1317_6 ( .RAM_O2(na1317_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1317_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x66y57 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1318_1 ( .OUT(na1318_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na641_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1318_2 ( .OUT(na1318_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1213_100), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1318_6 ( .RAM_O1(na1318_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1318_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x67y64 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1319_4 ( .OUT(na1319_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1319_6 ( .RAM_O2(na1319_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1319_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x92y80 80'h00_0018_00_0000_0888_3E57 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1320_1 ( .OUT(na1320_1), .IN1(~na212_1), .IN2(~na1228_2), .IN3(~na42_1), .IN4(1'b0), .IN5(na1985_2), .IN6(na1228_2), .IN7(1'b0), + .IN8(~na50_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x67y64 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1321_1 ( .OUT(na1321_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1321_6 ( .RAM_O1(na1321_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1321_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x67y63 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1322_4 ( .OUT(na1322_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1322_6 ( .RAM_O2(na1322_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1322_2), .COMP_OUT(1'b0) ); +// C_AND//// x67y63 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1323_1 ( .OUT(na1323_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1323_6 ( .RAM_O1(na1323_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1323_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x65y64 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1324_4 ( .OUT(na1324_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1324_6 ( .RAM_O2(na1324_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1324_2), .COMP_OUT(1'b0) ); +// C_AND//// x65y64 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1325_1 ( .OUT(na1325_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1325_6 ( .RAM_O1(na1325_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1325_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x84y53 80'h00_0018_00_0000_0888_1532 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1326_1 ( .OUT(na1326_1), .IN1(na1732_1), .IN2(~na1327_1), .IN3(1'b1), .IN4(~na348_2), .IN5(~na334_1), .IN6(1'b1), .IN7(~na336_1), + .IN8(~na348_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y66 80'h00_0018_00_0000_0C88_CEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1327_1 ( .OUT(na1327_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na777_1), .IN6(na1932_2), .IN7(1'b0), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x65y63 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1328_4 ( .OUT(na1328_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1328_6 ( .RAM_O2(na1328_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1328_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x88y79 80'h00_0018_00_0000_0C88_D5FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1329_1 ( .OUT(na1329_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na314_2), .IN6(1'b0), .IN7(~na10_1), .IN8(na516_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x65y63 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1330_1 ( .OUT(na1330_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1330_6 ( .RAM_O1(na1330_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1330_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x82y77 80'h00_0018_00_0000_0C88_37FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1331_1 ( .OUT(na1331_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2073_2), .IN6(~na8_1), .IN7(1'b0), .IN8(~na1936_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y75 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1332_1 ( .OUT(na1332_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na316_1), .IN8(~na319_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x77y70 80'h00_0018_00_0000_0C88_B5FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1333_1 ( .OUT(na1333_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1937_2), .IN6(1'b0), .IN7(na406_1), .IN8(~na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x67y66 80'h04_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1334_1 ( .OUT(na1334_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na240_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1334_6 ( .RAM_O1(na1334_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1334_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x59y65 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1335_4 ( .OUT(na1335_2), .IN1(1'b1), .IN2(na39_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1335_6 ( .RAM_O2(na1335_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1335_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x71y58 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1336_1 ( .OUT(na1336_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na952_1), .IN7(1'b0), .IN8(na984_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x76y47 80'h00_0018_00_0000_0C88_55FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1337_1 ( .OUT(na1337_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na85_1), .IN6(1'b1), .IN7(~na83_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y72 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1338_4 ( .OUT(na1338_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1338_6 ( .RAM_O2(na1338_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1338_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y72 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1339_1 ( .OUT(na1339_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1339_6 ( .RAM_O1(na1339_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1339_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x60y71 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1340_4 ( .OUT(na1340_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1340_6 ( .RAM_O2(na1340_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1340_2), .COMP_OUT(1'b0) ); +// C_AND///AND/ x93y49 80'h00_0078_00_0000_0C88_1FC3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1341_1 ( .OUT(na1341_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na346_1), .IN8(~na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1341_4 ( .OUT(na1341_2), .IN1(1'b1), .IN2(~na2021_2), .IN3(1'b1), .IN4(na44_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x81y52 80'h00_0018_00_0000_0888_F7D3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1342_1 ( .OUT(na1342_1), .IN1(1'b0), .IN2(~na342_1), .IN3(~na510_2), .IN4(na344_1), .IN5(~na1064_1), .IN6(~na1142_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y71 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1343_1 ( .OUT(na1343_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1343_6 ( .RAM_O1(na1343_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1343_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x60y70 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1344_4 ( .OUT(na1344_2), .IN1(na1062_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1344_6 ( .RAM_O2(na1344_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1344_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y70 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1345_1 ( .OUT(na1345_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1061_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1345_6 ( .RAM_O1(na1345_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1345_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x75y60 80'h00_0060_00_0000_0C08_FFC5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1346_4 ( .OUT(na1346_2), .IN1(~na1347_1), .IN2(1'b1), .IN3(1'b1), .IN4(na350_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x77y63 80'h00_0018_00_0000_0888_7B73 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1347_1 ( .OUT(na1347_1), .IN1(1'b0), .IN2(~na352_1), .IN3(~na1355_1), .IN4(~na102_1), .IN5(na380_1), .IN6(~na101_1), .IN7(~na783_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x82y80 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1348_1 ( .OUT(na1348_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1349_1), .IN6(~na8_1), .IN7(~na369_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y77 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1349_1 ( .OUT(na1349_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b0), .IN4(1'b0), .IN5(~na368_1), .IN6(~na367_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y76 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1350_1 ( .OUT(na1350_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1351_1), .IN6(~na8_1), .IN7(~na376_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x75y79 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1351_1 ( .OUT(na1351_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na375_1), .IN8(~na374_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x80y69 80'h00_0018_00_0000_0C88_75FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1352_1 ( .OUT(na1352_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na378_1), .IN6(1'b0), .IN7(~na1353_1), .IN8(~na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y69 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1353_1 ( .OUT(na1353_1), .IN1(1'b1), .IN2(na4_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na328_1), .IN8(~na325_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y69 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1354_4 ( .OUT(na1354_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1060_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1354_6 ( .RAM_O2(na1354_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1354_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x74y49 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1355_1 ( .OUT(na1355_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na952_2), .IN7(1'b0), .IN8(na984_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x86y59 80'h00_0078_00_0000_0CEE_0D70 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1356_1 ( .OUT(na1356_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1341_2), .IN6(na386_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1356_4 ( .OUT(na1356_2), .IN1(1'b0), .IN2(1'b0), .IN3(~na862_1), .IN4(~na350_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x81y57 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1357_4 ( .OUT(na1357_2), .IN1(1'b1), .IN2(na929_1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y69 80'h04_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1358_1 ( .OUT(na1358_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1059_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1358_6 ( .RAM_O1(na1358_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1358_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x82y56 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1359_1 ( .OUT(na1359_1), .IN1(1'b1), .IN2(na1982_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1173_1), .IN6(na1160_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y68 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1360_4 ( .OUT(na1360_2), .IN1(na1058_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1360_6 ( .RAM_O2(na1360_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1360_2), .COMP_OUT(1'b0) ); +// C_///AND/ x86y70 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1361_4 ( .OUT(na1361_2), .IN1(1'b1), .IN2(1'b1), .IN3(na247_2), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x89y79 80'h00_0060_00_0000_0C08_FFF1 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1362_4 ( .OUT(na1362_2), .IN1(~na399_1), .IN2(~na391_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y68 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1363_1 ( .OUT(na1363_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1363_6 ( .RAM_O1(na1363_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1363_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x87y80 80'h00_0018_00_0000_0C88_1FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1364_1 ( .OUT(na1364_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na10_1), .IN8(~na396_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y76 80'h00_0018_00_0040_0A55_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1365_1 ( .OUT(na1365_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na1873_2), .IN5(~na395_1), .IN6(1'b0), .IN7(~na393_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x92y77 80'h00_0018_00_0000_0C88_EDFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1366_1 ( .OUT(na1366_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1875_2), .IN6(na1962_2), .IN7(na10_1), .IN8(na1956_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y67 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1367_4 ( .OUT(na1367_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1367_6 ( .RAM_O2(na1367_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1367_2), .COMP_OUT(1'b0) ); +// C_AND//// x60y67 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1368_1 ( .OUT(na1368_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1368_6 ( .RAM_O1(na1368_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1368_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x60y66 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1369_4 ( .OUT(na1369_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1369_6 ( .RAM_O2(na1369_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1369_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x74y77 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1370_1 ( .OUT(na1370_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na406_1), .IN8(~na319_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y66 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1371_1 ( .OUT(na1371_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1371_6 ( .RAM_O1(na1371_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1371_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x92y71 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1372_1 ( .OUT(na1372_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na408_1), .IN7(1'b1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x60y65 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1373_4 ( .OUT(na1373_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1373_6 ( .RAM_O2(na1373_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1373_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x76y49 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1374_1 ( .OUT(na1374_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na974_1), .IN6(1'b0), .IN7(na1006_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x84y61 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1375_4 ( .OUT(na1375_2), .IN1(na940_1), .IN2(1'b1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x91y49 80'h00_0078_00_0000_0CEE_A533 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1376_1 ( .OUT(na1376_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1341_2), .IN6(1'b0), .IN7(na1377_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1376_4 ( .OUT(na1376_2), .IN1(1'b0), .IN2(~na1023_1), .IN3(1'b0), .IN4(~na350_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x84y51 80'h00_0018_00_0000_0888_DF37 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1377_1 ( .OUT(na1377_1), .IN1(~na1064_1), .IN2(~na1154_1), .IN3(1'b0), .IN4(~na415_1), .IN5(1'b1), .IN6(1'b1), .IN7(~na510_2), + .IN8(na417_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x60y65 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1378_1 ( .OUT(na1378_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1378_6 ( .RAM_O1(na1378_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1378_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x88y66 80'h00_0060_00_0000_0C08_FF2F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1379_4 ( .OUT(na1379_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1903_2), .IN4(~na250_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y72 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1380_4 ( .OUT(na1380_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1380_6 ( .RAM_O2(na1380_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1380_2), .COMP_OUT(1'b0) ); +// C_AND//// x69y72 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1381_1 ( .OUT(na1381_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1381_6 ( .RAM_O1(na1381_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1381_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x82y76 80'h00_0018_00_0000_0C88_73FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1382_1 ( .OUT(na1382_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na419_1), .IN7(~na10_1), .IN8(~na1383_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y74 80'h00_0018_00_0040_0AAA_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1383_1 ( .OUT(na1383_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1873_2), .IN5(1'b0), .IN6(~na424_1), .IN7(1'b0), .IN8(~na423_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y77 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1384_1 ( .OUT(na1384_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na499_1), .IN6(~na8_1), .IN7(1'b0), .IN8(~na427_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y71 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1385_4 ( .OUT(na1385_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1385_6 ( .RAM_O2(na1385_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1385_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x77y69 80'h00_0018_00_0000_0C88_B3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1386_1 ( .OUT(na1386_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na430_1), .IN7(na375_1), .IN8(~na7_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y71 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1387_1 ( .OUT(na1387_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1387_6 ( .RAM_O1(na1387_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1387_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y70 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1388_4 ( .OUT(na1388_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1153_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1388_6 ( .RAM_O2(na1388_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1388_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x78y51 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1389_1 ( .OUT(na1389_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na974_2), .IN6(1'b0), .IN7(na1006_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x90y54 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1390_1 ( .OUT(na1390_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na944_1), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x73y59 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1391_4 ( .OUT(na1391_2), .IN1(na1341_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na436_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y70 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1392_1 ( .OUT(na1392_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1152_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1392_6 ( .RAM_O1(na1392_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1392_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x84y56 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1393_1 ( .OUT(na1393_1), .IN1(1'b1), .IN2(na1982_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1145_1), .IN6(na1162_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x81y56 80'h00_0060_00_0000_0C0E_FF33 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1394_4 ( .OUT(na1394_2), .IN1(1'b0), .IN2(~na1943_2), .IN3(1'b0), .IN4(~na876_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x90y65 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1395_4 ( .OUT(na1395_2), .IN1(1'b1), .IN2(na918_1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y54 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1396_1 ( .OUT(na1396_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na441_1), .IN6(1'b1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x80y59 80'h00_0078_00_0000_0C88_C5C3 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1397_1 ( .OUT(na1397_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na444_1), .IN6(1'b1), .IN7(1'b1), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1397_4 ( .OUT(na1397_2), .IN1(1'b1), .IN2(~na453_1), .IN3(1'b1), .IN4(na102_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y69 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1398_4 ( .OUT(na1398_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1151_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1398_6 ( .RAM_O2(na1398_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1398_2), .COMP_OUT(1'b0) ); +// C_AND//// x88y63 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1399_1 ( .OUT(na1399_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na443_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x78y77 80'h00_0018_00_0000_0C88_73FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1400_1 ( .OUT(na1400_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na446_1), .IN7(~na10_1), .IN8(~na1401_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x78y76 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1401_1 ( .OUT(na1401_1), .IN1(1'b1), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na284_1), .IN6(~na276_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x79y75 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1402_1 ( .OUT(na1402_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1934_2), .IN6(~na8_1), .IN7(1'b0), .IN8(~na449_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y69 80'h04_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1403_1 ( .OUT(na1403_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na1150_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1403_6 ( .RAM_O1(na1403_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1403_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y68 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1404_4 ( .OUT(na1404_2), .IN1(1'b1), .IN2(na1149_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1404_6 ( .RAM_O2(na1404_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1404_2), .COMP_OUT(1'b0) ); +// C_AND//// x69y68 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1405_1 ( .OUT(na1405_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1405_6 ( .RAM_O1(na1405_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1405_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x69y67 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1406_4 ( .OUT(na1406_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1406_6 ( .RAM_O2(na1406_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1406_2), .COMP_OUT(1'b0) ); +// C_///AND/ x90y59 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1407_4 ( .OUT(na1407_2), .IN1(na945_1), .IN2(1'b1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x79y57 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1408_4 ( .OUT(na1408_2), .IN1(na1341_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na456_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y67 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1409_1 ( .OUT(na1409_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1409_6 ( .RAM_O1(na1409_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1409_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x80y56 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1410_1 ( .OUT(na1410_1), .IN1(1'b1), .IN2(na1982_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1146_1), .IN6(na1163_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x86y58 80'h00_0060_00_0000_0C0E_FF33 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1411_4 ( .OUT(na1411_2), .IN1(1'b0), .IN2(~na1025_1), .IN3(1'b0), .IN4(~na350_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y61 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1412_1 ( .OUT(na1412_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na918_2), .IN7(1'b1), .IN8(na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x81y77 80'h00_0018_00_0000_0C88_73FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1413_1 ( .OUT(na1413_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na463_2), .IN7(~na10_1), .IN8(~na1414_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y76 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1414_1 ( .OUT(na1414_1), .IN1(1'b1), .IN2(~na8_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na462_1), .IN8(~na358_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x78y80 80'h00_0018_00_0000_0C88_3BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1415_1 ( .OUT(na1415_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1946_2), .IN6(~na8_1), .IN7(1'b0), .IN8(~na1954_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y66 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1416_4 ( .OUT(na1416_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1416_6 ( .RAM_O2(na1416_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1416_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x77y75 80'h00_0018_00_0000_0C88_37FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1417_1 ( .OUT(na1417_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2083_2), .IN6(~na8_1), .IN7(1'b0), .IN8(~na1955_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y75 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1418_1 ( .OUT(na1418_1), .IN1(1'b1), .IN2(na1871_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na371_1), .IN8(~na1948_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y66 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1419_1 ( .OUT(na1419_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1419_6 ( .RAM_O1(na1419_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1419_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x76y53 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1420_1 ( .OUT(na1420_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na978_2), .IN7(1'b0), .IN8(na1011_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x83y58 80'h00_0078_00_0000_0CEE_0D70 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1421_1 ( .OUT(na1421_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1341_2), .IN6(na474_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1421_4 ( .OUT(na1421_2), .IN1(1'b0), .IN2(1'b0), .IN3(~na878_1), .IN4(~na350_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x87y57 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1422_4 ( .OUT(na1422_2), .IN1(1'b1), .IN2(na946_1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x69y65 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1423_4 ( .OUT(na1423_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1423_6 ( .RAM_O2(na1423_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1423_2), .COMP_OUT(1'b0) ); +// C_MX2b//// x76y56 80'h00_0018_00_0040_0A30_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1424_1 ( .OUT(na1424_1), .IN1(1'b1), .IN2(na1982_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1147_1), .IN6(na1164_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x69y65 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1425_1 ( .OUT(na1425_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1425_6 ( .RAM_O1(na1425_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1425_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x87y65 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1426_4 ( .OUT(na1426_2), .IN1(na922_1), .IN2(1'b1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x81y73 80'h00_0018_00_0000_0C88_75FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1427_1 ( .OUT(na1427_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na480_1), .IN6(1'b0), .IN7(~na10_1), .IN8(~na1428_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x82y74 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1428_1 ( .OUT(na1428_1), .IN1(1'b1), .IN2(~na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na395_1), .IN6(~na397_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y77 80'h00_0018_00_0000_0C88_5BFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1429_1 ( .OUT(na1429_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1951_2), .IN6(~na8_1), .IN7(~na484_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x62y72 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1430_4 ( .OUT(na1430_2_i), .IN1(na827_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1430_5 ( .OUT(na1430_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_21), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1430_6 ( .RAM_O2(na1430_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1430_2_i), .COMP_OUT(1'b0) ); +// C_ORAND//// x91y71 80'h00_0018_00_0000_0C88_B3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1431_1 ( .OUT(na1431_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na1952_2), .IN7(na486_1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x96y73 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1432_1 ( .OUT(na1432_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na486_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x62y72 80'h05_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1433_1 ( .OUT(na1433_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na824_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1433_2 ( .OUT(na1433_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_22), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1433_6 ( .RAM_O1(na1433_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1433_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x72y53 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1434_1 ( .OUT(na1434_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na980_1), .IN6(1'b0), .IN7(na1013_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x87y50 80'h00_0018_00_0000_0C88_F2FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1435_1 ( .OUT(na1435_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(~na489_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x62y71 80'h0A_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1436_4 ( .OUT(na1436_2_i), .IN1(1'b1), .IN2(na616_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1436_5 ( .OUT(na1436_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_23), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1436_6 ( .RAM_O2(na1436_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1436_2_i), .COMP_OUT(1'b0) ); +// C_MX2b//// x72y56 80'h00_0018_00_0040_0A30_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1437_1 ( .OUT(na1437_1), .IN1(1'b1), .IN2(~na1982_2), .IN3(1'b0), .IN4(1'b0), .IN5(na1166_1), .IN6(na1148_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x92y57 80'h00_0060_00_0000_0C0E_FF53 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1438_4 ( .OUT(na1438_2), .IN1(1'b0), .IN2(~na946_2), .IN3(~na346_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x89y57 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1439_4 ( .OUT(na1439_2), .IN1(1'b1), .IN2(na1943_2), .IN3(1'b1), .IN4(na1027_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x91y65 80'h00_0018_00_0000_0C88_B3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1440_1 ( .OUT(na1440_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na1952_2), .IN7(na495_1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x92y67 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1441_1 ( .OUT(na1441_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na495_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x62y71 80'h05_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1442_1 ( .OUT(na1442_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na821_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1442_2 ( .OUT(na1442_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_24), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1442_6 ( .RAM_O1(na1442_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1442_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x84y78 80'h00_0018_00_0000_0C88_75FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1443_1 ( .OUT(na1443_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na498_1), .IN6(1'b0), .IN7(~na10_1), .IN8(~na1444_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x84y74 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1444_1 ( .OUT(na1444_1), .IN1(1'b1), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na420_1), .IN6(~na424_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y78 80'h00_0018_00_0000_0C88_37FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1445_1 ( .OUT(na1445_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1446_1), .IN6(~na8_1), .IN7(1'b0), .IN8(~na503_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x69y77 80'h00_0018_00_0040_0ACC_00F3 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1446_1 ( .OUT(na1446_1), .IN1(1'b1), .IN2(~na1871_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na371_1), .IN8(~na374_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y72 80'h0A_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1447_4 ( .OUT(na1447_2_i), .IN1(1'b1), .IN2(na594_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1447_5 ( .OUT(na1447_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_25), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1447_6 ( .RAM_O2(na1447_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1447_2_i), .COMP_OUT(1'b0) ); +// C_MX2b//// x70y51 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1448_1 ( .OUT(na1448_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na980_2), .IN6(1'b0), .IN7(na1013_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x86y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1449_1 ( .OUT(na1449_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na948_1), .IN6(1'b1), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR///OR/ x97y48 80'h00_0078_00_0000_0CEE_0D33 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1450_1 ( .OUT(na1450_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1341_2), .IN6(na1451_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1450_4 ( .OUT(na1450_2), .IN1(1'b0), .IN2(~na1943_2), .IN3(1'b0), .IN4(~na880_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x87y48 80'h00_0018_00_0000_0888_DFDC +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1451_1 ( .OUT(na1451_1), .IN1(1'b0), .IN2(na512_1), .IN3(~na510_1), .IN4(na1959_2), .IN5(1'b1), .IN6(1'b1), .IN7(~na510_2), + .IN8(na511_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y72 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1452_1 ( .OUT(na1452_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na581_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1452_2 ( .OUT(na1452_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_26), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1452_6 ( .RAM_O1(na1452_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1452_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x85y65 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1453_4 ( .OUT(na1453_2), .IN1(1'b1), .IN2(na924_1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y71 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1454_4 ( .OUT(na1454_2_i), .IN1(na568_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1454_5 ( .OUT(na1454_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_27), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1454_6 ( .RAM_O2(na1454_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1454_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y71 80'h05_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1455_1 ( .OUT(na1455_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na812_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1455_2 ( .OUT(na1455_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_28), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1455_6 ( .RAM_O1(na1455_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1455_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x71y59 80'h00_0060_00_0000_0C08_FFA3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1456_4 ( .OUT(na1456_2), .IN1(1'b1), .IN2(~na509_1), .IN3(na2029_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x91y56 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1457_4 ( .OUT(na1457_2), .IN1(na1942_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1458_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y66 80'h00_0018_00_0000_0888_7BB3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1458_1 ( .OUT(na1458_1), .IN1(1'b0), .IN2(~na514_1), .IN3(na518_1), .IN4(~na102_1), .IN5(na517_1), .IN6(~na101_1), .IN7(~na797_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y70 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1459_4 ( .OUT(na1459_2_i), .IN1(na809_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1459_5 ( .OUT(na1459_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_29), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1459_6 ( .RAM_O2(na1459_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1459_2_i), .COMP_OUT(1'b0) ); +// C_MX2b//// x82y73 80'h00_0018_00_0040_0AA0_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1460_1 ( .OUT(na1460_1), .IN1(1'b1), .IN2(1'b1), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b0), .IN6(na283_1), .IN7(1'b0), .IN8(na516_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x97y54 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1461_1 ( .OUT(na1461_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na948_2), .IN6(1'b1), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x90y49 80'h00_0018_00_0000_0C88_BAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1462_1 ( .OUT(na1462_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na521_1), .IN8(~na523_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y70 80'h05_0018_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1463_1 ( .OUT(na1463_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na805_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1463_2 ( .OUT(na1463_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_30), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1463_6 ( .RAM_O1(na1463_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1463_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_OR//// x87y57 80'h00_0018_00_0000_0CEE_3500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1464_1 ( .OUT(na1464_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1029_1), .IN6(1'b0), .IN7(1'b0), .IN8(~na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x90y62 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1465_4 ( .OUT(na1465_2), .IN1(1'b1), .IN2(na924_2), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x89y55 80'h00_0060_00_0000_0C08_FF3C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1466_4 ( .OUT(na1466_2), .IN1(1'b1), .IN2(na1063_1), .IN3(1'b1), .IN4(~na344_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x89y79 80'h00_0018_00_0000_0C88_E7FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1467_1 ( .OUT(na1467_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1875_2), .IN6(~na1469_1), .IN7(na10_1), + .IN8(na1348_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y69 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1468_4 ( .OUT(na1468_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na802_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1468_5 ( .OUT(na1468_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_31), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1468_6 ( .RAM_O2(na1468_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1468_2_i), .COMP_OUT(1'b0) ); +// C_MX2b//// x79y82 80'h00_0018_00_0040_0ACC_00FC +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1469_1 ( .OUT(na1469_1), .IN1(1'b1), .IN2(na8_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b0), .IN7(~na361_1), .IN8(~na358_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x91y68 80'h00_0018_00_0000_0C88_B3FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1470_1 ( .OUT(na1470_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(~na1952_2), .IN7(na482_1), .IN8(~na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x94y73 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1471_1 ( .OUT(na1471_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na482_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y53 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1472_1 ( .OUT(na1472_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na982_2), .IN7(1'b0), .IN8(na1015_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y52 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1473_4 ( .OUT(na1473_2), .IN1(na1341_2), .IN2(1'b1), .IN3(~na531_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y69 80'h05_0018_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1474_1 ( .OUT(na1474_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na513_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1474_2 ( .OUT(na1474_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_32), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1474_6 ( .RAM_O1(na1474_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1474_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x64y68 80'h0A_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1475_4 ( .OUT(na1475_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na796_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1475_5 ( .OUT(na1475_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_33), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1475_6 ( .RAM_O2(na1475_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1475_2_i), .COMP_OUT(1'b0) ); +// C_OR//// x88y57 80'h00_0018_00_0000_0CEE_7000 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1476_1 ( .OUT(na1476_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na882_1), .IN8(~na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x97y59 80'h00_0018_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1477_1 ( .OUT(na1477_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na926_1), .IN6(1'b1), .IN7(1'b1), .IN8(na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y68 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1478_1 ( .OUT(na1478_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na792_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1478_2 ( .OUT(na1478_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_34), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1478_6 ( .RAM_O1(na1478_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1478_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_MX2b//// x86y79 80'h00_0018_00_0040_0AA0_005F +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1479_1 ( .OUT(na1479_1), .IN1(1'b1), .IN2(1'b1), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b0), .IN6(na1950_2), .IN7(1'b0), .IN8(na538_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y67 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1480_4 ( .OUT(na1480_2_i), .IN1(na850_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1480_5 ( .OUT(na1480_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_35), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1480_6 ( .RAM_O2(na1480_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1480_2_i), .COMP_OUT(1'b0) ); +// C_AND//// x87y65 80'h00_0018_00_0000_0C88_4FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1481_1 ( .OUT(na1481_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na466_1), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y61 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1482_1 ( .OUT(na1482_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na953_1), .IN6(1'b0), .IN7(na985_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x89y49 80'h00_0018_00_0000_0C88_BAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1483_1 ( .OUT(na1483_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b0), .IN7(na521_1), .IN8(~na544_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y67 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1484_1 ( .OUT(na1484_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na440_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1484_2 ( .OUT(na1484_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_36), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1484_6 ( .RAM_O1(na1484_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1484_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_AND//// x97y56 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1485_1 ( .OUT(na1485_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na950_2), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x98y53 80'h00_0018_00_0000_0CEE_3500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1486_1 ( .OUT(na1486_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1031_2), .IN6(1'b0), .IN7(1'b0), .IN8(~na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x88y67 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1487_4 ( .OUT(na1487_2), .IN1(na926_2), .IN2(1'b1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x79y49 80'h00_0018_00_0000_0C88_3CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1488_1 ( .OUT(na1488_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1063_1), .IN7(1'b1), .IN8(~na417_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y73 80'h00_0018_00_0000_0888_CF7E +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1489_1 ( .OUT(na1489_1), .IN1(na1384_1), .IN2(na1876_2), .IN3(~na10_1), .IN4(~na1490_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y78 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1490_1 ( .OUT(na1490_1), .IN1(1'b1), .IN2(~na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na420_1), .IN6(~na421_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x64y66 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1491_4 ( .OUT(na1491_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na847_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1491_5 ( .OUT(na1491_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_37), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1491_6 ( .RAM_O2(na1491_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1491_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x64y66 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1492_1 ( .OUT(na1492_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na787_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1492_2 ( .OUT(na1492_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_38), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1492_6 ( .RAM_O1(na1492_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1492_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x64y65 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1493_4 ( .OUT(na1493_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na351_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1493_5 ( .OUT(na1493_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_39), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1493_6 ( .RAM_O2(na1493_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1493_2_i), .COMP_OUT(1'b0) ); +// C_AND//// x85y65 80'h00_0018_00_0000_0C88_3CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1494_1 ( .OUT(na1494_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1877_2), .IN7(1'b1), .IN8(~na447_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x70y53 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1495_1 ( .OUT(na1495_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na953_2), .IN6(1'b0), .IN7(na985_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x64y65 80'h05_0018_00_0000_0C88_F5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1496_1 ( .OUT(na1496_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na270_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1496_2 ( .OUT(na1496_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_40), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1496_6 ( .RAM_O1(na1496_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1496_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y70 80'h0A_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1497_4 ( .OUT(na1497_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(~na727_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1497_5 ( .OUT(na1497_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_109), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1497_6 ( .RAM_O2(na1497_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1497_2_i), .COMP_OUT(1'b0) ); +// C_AND//// x98y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1498_1 ( .OUT(na1498_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na930_1), .IN6(1'b1), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x89y53 80'h00_0018_00_0000_0CEE_3300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1499_1 ( .OUT(na1499_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na1943_2), .IN7(1'b0), .IN8(~na853_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x89y62 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1500_4 ( .OUT(na1500_2), .IN1(1'b1), .IN2(na928_1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y75 80'h00_0018_00_0000_0888_CF7E +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1501_1 ( .OUT(na1501_1), .IN1(na1402_1), .IN2(na1876_2), .IN3(~na10_1), .IN4(~na1502_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y80 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1502_1 ( .OUT(na1502_1), .IN1(1'b1), .IN2(~na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na291_1), .IN6(~na300_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x66y70 80'h05_0018_00_0000_0C88_F3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1503_1 ( .OUT(na1503_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na718_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1503_2 ( .OUT(na1503_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_110), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1503_6 ( .RAM_O1(na1503_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1503_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y69 80'h0A_0060_00_0000_0C08_FFF5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1504_4 ( .OUT(na1504_2_i), .IN1(~na711_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1504_5 ( .OUT(na1504_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_111), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1504_6 ( .RAM_O2(na1504_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1504_2_i), .COMP_OUT(1'b0) ); +// C_MX2b//// x77y60 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1505_1 ( .OUT(na1505_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na955_1), .IN7(1'b0), .IN8(na987_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y59 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1506_4 ( .OUT(na1506_2), .IN1(1'b1), .IN2(na567_1), .IN3(na2029_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x89y52 80'h00_0018_00_0000_0CEE_A500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1507_1 ( .OUT(na1507_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1341_2), .IN6(1'b0), .IN7(na564_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x98y58 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1508_1 ( .OUT(na1508_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na931_1), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x66y69 80'h05_0018_00_0000_0C88_F5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1509_1 ( .OUT(na1509_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na702_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1509_2 ( .OUT(na1509_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_112), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1509_6 ( .RAM_O1(na1509_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1509_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y68 80'h0A_0060_00_0000_0C08_FF3F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1510_4 ( .OUT(na1510_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na693_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1510_5 ( .OUT(na1510_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_113), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1510_6 ( .RAM_O2(na1510_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1510_2_i), .COMP_OUT(1'b0) ); +// C_OR//// x93y53 80'h00_0018_00_0000_0CEE_3500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1511_1 ( .OUT(na1511_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1033_2), .IN6(1'b0), .IN7(1'b0), .IN8(~na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x89y71 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1512_4 ( .OUT(na1512_2), .IN1(1'b1), .IN2(na928_2), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x88y54 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1513_1 ( .OUT(na1513_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na569_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x66y68 80'h05_0018_00_0000_0C88_F3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1514_1 ( .OUT(na1514_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na683_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1514_2 ( .OUT(na1514_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_114), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1514_6 ( .RAM_O1(na1514_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1514_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x83y71 80'h00_0018_00_0000_0888_CFD3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1515_1 ( .OUT(na1515_1), .IN1(1'b0), .IN2(~na571_2), .IN3(~na10_1), .IN4(na1415_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), .IN8(na11_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/RAM_I2 x66y67 80'h0A_0060_00_0000_0C08_FF3F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1516_4 ( .OUT(na1516_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na677_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1516_5 ( .OUT(na1516_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_115), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1516_6 ( .RAM_O2(na1516_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1516_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x66y67 80'h05_0018_00_0000_0C88_3FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1517_1 ( .OUT(na1517_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(~na671_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1517_2 ( .OUT(na1517_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_116), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1517_6 ( .RAM_O1(na1517_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1517_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y66 80'h0A_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1518_4 ( .OUT(na1518_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na838_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1518_5 ( .OUT(na1518_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_117), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1518_6 ( .RAM_O2(na1518_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1518_2_i), .COMP_OUT(1'b0) ); +// C_AND/RAM_I1/// x66y66 80'h05_0018_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1519_1 ( .OUT(na1519_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na655_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1519_2 ( .OUT(na1519_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_118), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1519_6 ( .RAM_O1(na1519_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1519_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/RAM_I2 x66y65 80'h0A_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1520_4 ( .OUT(na1520_2_i), .IN1(na833_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I2 #(.CPE_CFG (9'bX_1000_0011)) + _a1520_5 ( .OUT(na1520_2), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_119), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1520_6 ( .RAM_O2(na1520_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1520_2_i), .COMP_OUT(1'b0) ); +// C_MX2b//// x74y55 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1521_1 ( .OUT(na1521_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na955_2), .IN7(1'b0), .IN8(na987_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x88y57 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1522_4 ( .OUT(na1522_2), .IN1(1'b1), .IN2(1'b1), .IN3(na855_1), .IN4(na350_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x95y52 80'h00_0060_00_0000_0C0E_FF0D +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1523_4 ( .OUT(na1523_2), .IN1(~na1341_2), .IN2(na578_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x95y59 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1524_1 ( .OUT(na1524_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na932_1), .IN6(1'b1), .IN7(na346_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND/RAM_I1/// x66y65 80'h05_0018_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1525_1 ( .OUT(na1525_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na641_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_RAM_I1 #(.CPE_CFG (9'bX_1000_0011)) + _a1525_2 ( .OUT(na1525_1), .CLK(1'b0), .EN(1'b0), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(na1214_120), .CP_O(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1525_6 ( .RAM_O1(na1525_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1525_1_i), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x67y72 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1526_4 ( .OUT(na1526_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1526_6 ( .RAM_O2(na1526_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1526_2), .COMP_OUT(1'b0) ); +// C_///OR/ x90y55 80'h00_0060_00_0000_0C0E_FF07 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1527_4 ( .OUT(na1527_2), .IN1(~na1064_1), .IN2(~na567_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x82y72 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1528_4 ( .OUT(na1528_2), .IN1(na909_1), .IN2(1'b1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x94y62 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1529_1 ( .OUT(na1529_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na582_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x67y72 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1530_1 ( .OUT(na1530_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1530_6 ( .RAM_O1(na1530_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1530_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x87y75 80'h00_0018_00_0000_0888_CF7E +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1531_1 ( .OUT(na1531_1), .IN1(na1429_1), .IN2(na1876_2), .IN3(~na10_1), .IN4(~na1532_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x80y82 80'h00_0018_00_0040_0A33_0003 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1532_1 ( .OUT(na1532_1), .IN1(1'b1), .IN2(~na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na398_1), .IN6(~na401_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x67y71 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1533_4 ( .OUT(na1533_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1533_6 ( .RAM_O2(na1533_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1533_2), .COMP_OUT(1'b0) ); +// C_AND//// x67y71 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1534_1 ( .OUT(na1534_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1534_6 ( .RAM_O1(na1534_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1534_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x65y72 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1535_4 ( .OUT(na1535_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1535_6 ( .RAM_O2(na1535_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1535_2), .COMP_OUT(1'b0) ); +// C_ORAND//// x90y81 80'h00_0018_00_0000_0C88_DEFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1536_1 ( .OUT(na1536_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1875_2), .IN6(na1350_1), .IN7(~na10_1), .IN8(na1348_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y59 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1537_1 ( .OUT(na1537_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na957_1), .IN6(1'b0), .IN7(na989_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y51 80'h00_0018_00_0000_0C88_F4FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1538_1 ( .OUT(na1538_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na590_1), .IN6(na2076_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x65y72 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1539_1 ( .OUT(na1539_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1539_6 ( .RAM_O1(na1539_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1539_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/ x65y71 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1540_4 ( .OUT(na1540_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1540_6 ( .RAM_O2(na1540_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1540_2), .COMP_OUT(1'b0) ); +// C_OR//// x89y62 80'h00_0018_00_0000_0CEE_3300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1541_1 ( .OUT(na1541_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na567_1), .IN7(1'b0), .IN8(~na1065_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x91y71 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1542_4 ( .OUT(na1542_2), .IN1(na909_2), .IN2(1'b1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x97y60 80'h00_0018_00_0000_0CEE_5300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1543_1 ( .OUT(na1543_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na933_1), .IN7(~na346_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x94y53 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1544_1 ( .OUT(na1544_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1035_1), .IN7(1'b1), .IN8(na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x90y58 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1545_1 ( .OUT(na1545_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na595_1), .IN6(1'b1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x65y71 80'h04_0018_00_0000_0C88_F0FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1546_1 ( .OUT(na1546_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b0), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1546_6 ( .RAM_O1(na1546_9), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na1546_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_ORAND//// x87y73 80'h00_0018_00_0000_0888_CFE7 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1547_1 ( .OUT(na1547_1), .IN1(~na1875_2), .IN2(~na1548_1), .IN3(na10_1), .IN4(na1445_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b0), + .IN8(na11_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x79y78 80'h00_0018_00_0040_0A33_000C +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1548_1 ( .OUT(na1548_1), .IN1(1'b1), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(~na499_1), .IN6(~na421_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y59 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1553_1 ( .OUT(na1553_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na957_2), .IN6(1'b0), .IN7(na989_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x67y57 80'h00_0060_00_0000_0C08_FF3C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1555_4 ( .OUT(na1555_2), .IN1(1'b1), .IN2(na1063_1), .IN3(1'b1), .IN4(~na511_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x91y60 80'h00_0060_00_0000_0C0E_FF33 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1556_4 ( .OUT(na1556_2), .IN1(1'b0), .IN2(~na1943_2), .IN3(1'b0), .IN4(~na857_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x97y57 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1557_1 ( .OUT(na1557_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na911_1), .IN7(1'b1), .IN8(na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x95y73 80'h00_0060_00_0000_0C0E_FF55 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1558_4 ( .OUT(na1558_2), .IN1(~na934_1), .IN2(1'b0), .IN3(~na346_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x98y55 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1559_4 ( .OUT(na1559_2), .IN1(1'b1), .IN2(na567_1), .IN3(1'b1), .IN4(na1066_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y57 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1561_1 ( .OUT(na1561_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na959_1), .IN7(1'b0), .IN8(na991_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x94y50 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1563_4 ( .OUT(na1563_2), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1150_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x95y55 80'h00_0018_00_0000_0CEE_3500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1564_1 ( .OUT(na1564_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1037_1), .IN6(1'b0), .IN7(1'b0), .IN8(~na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y71 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1565_4 ( .OUT(na1565_2), .IN1(1'b1), .IN2(na911_2), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x91y66 80'h00_0018_00_0000_0CEE_5300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1566_1 ( .OUT(na1566_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na935_1), .IN7(~na346_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x92y58 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1567_1 ( .OUT(na1567_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na567_1), .IN7(1'b1), .IN8(na1067_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x97y58 80'h00_0078_00_0000_0C88_C3AA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1568_1 ( .OUT(na1568_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1569_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1568_4 ( .OUT(na1568_2), .IN1(na936_1), .IN2(1'b1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x81y62 80'h00_0018_00_0000_0888_3F14 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1569_1 ( .OUT(na1569_1), .IN1(~na1570_1), .IN2(na1574_2), .IN3(~na620_1), .IN4(~na617_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(~na617_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x85y71 80'h00_0018_00_0000_0C88_34FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1570_1 ( .OUT(na1570_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1531_1), .IN6(na101_1), .IN7(1'b1), .IN8(~na586_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x67y66 80'h00_0060_00_0000_0C0E_FFD5 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1574_4 ( .OUT(na1574_2), .IN1(~na84_1), .IN2(1'b0), .IN3(~na1436_2), .IN4(na24_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y63 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1576_1 ( .OUT(na1576_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na959_2), .IN7(1'b0), .IN8(na991_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x97y51 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1577_1 ( .OUT(na1577_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na859_1), .IN8(na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x86y52 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1580_4 ( .OUT(na1580_2), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1151_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x91y57 80'h00_0018_00_0000_0CEE_3300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1581_1 ( .OUT(na1581_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na567_1), .IN7(1'b0), .IN8(~na1068_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y68 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1582_4 ( .OUT(na1582_2), .IN1(na913_1), .IN2(1'b1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x84y69 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1584_1 ( .OUT(na1584_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na961_1), .IN6(1'b0), .IN7(na993_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x84y63 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1585_4 ( .OUT(na1585_2), .IN1(1'b1), .IN2(na937_1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x90y52 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1588_4 ( .OUT(na1588_2), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1152_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x94y55 80'h00_0018_00_0000_0CEE_7000 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1589_1 ( .OUT(na1589_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na1039_1), .IN8(~na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x77y64 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1590_4 ( .OUT(na1590_2), .IN1(1'b1), .IN2(na567_1), .IN3(1'b1), .IN4(na1069_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x73y65 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1592_1 ( .OUT(na1592_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na961_2), .IN6(1'b0), .IN7(na993_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x99y54 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1593_1 ( .OUT(na1593_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1943_2), .IN7(1'b1), .IN8(na861_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x88y52 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1596_4 ( .OUT(na1596_2), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1153_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x91y64 80'h00_0018_00_0000_0CEE_5500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1597_1 ( .OUT(na1597_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na938_1), .IN6(1'b0), .IN7(~na346_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y67 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1598_4 ( .OUT(na1598_2), .IN1(1'b1), .IN2(na915_1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x92y65 80'h00_0078_00_0000_0C88_CCAC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1599_1 ( .OUT(na1599_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na915_2), .IN7(1'b1), .IN8(na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1599_4 ( .OUT(na1599_2), .IN1(1'b1), .IN2(na939_1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y67 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1603_1 ( .OUT(na1603_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na964_1), .IN7(1'b0), .IN8(na996_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x90y50 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1606_4 ( .OUT(na1606_2), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1155_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x95y54 80'h00_0018_00_0000_0CEE_3500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1607_1 ( .OUT(na1607_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1041_2), .IN6(1'b0), .IN7(1'b0), .IN8(~na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y57 80'h00_0018_00_0000_0C88_F8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1608_1 ( .OUT(na1608_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1058_2), .IN6(na567_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y67 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1612_1 ( .OUT(na1612_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na964_2), .IN7(1'b0), .IN8(na996_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y50 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1614_4 ( .OUT(na1614_2), .IN1(na1156_1), .IN2(1'b1), .IN3(na2031_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x89y58 80'h00_0060_00_0000_0C0E_FF07 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1615_4 ( .OUT(na1615_2), .IN1(~na1059_2), .IN2(~na567_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x97y61 80'h00_0018_00_0000_0C88_CAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1616_1 ( .OUT(na1616_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na917_1), .IN6(1'b1), .IN7(1'b1), .IN8(na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x94y66 80'h00_0018_00_0000_0CEE_5500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1617_1 ( .OUT(na1617_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na941_1), .IN6(1'b0), .IN7(~na346_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x99y51 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1618_1 ( .OUT(na1618_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na864_1), .IN8(na350_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x90y57 80'h00_0078_00_0000_0C88_4FAC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1619_1 ( .OUT(na1619_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(~na656_1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1619_4 ( .OUT(na1619_2), .IN1(1'b1), .IN2(na567_1), .IN3(na1060_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x74y65 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1623_1 ( .OUT(na1623_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na966_1), .IN6(1'b0), .IN7(na998_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x95y56 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1624_1 ( .OUT(na1624_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1943_2), .IN7(1'b1), .IN8(na1043_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x88y54 80'h00_0060_00_0000_0C08_FFCA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1626_4 ( .OUT(na1626_2), .IN1(na1064_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1157_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x87y77 80'h00_0060_00_0000_0C08_FFC3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1630_4 ( .OUT(na1630_2), .IN1(1'b1), .IN2(~na500_1), .IN3(1'b1), .IN4(na11_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y63 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1631_1 ( .OUT(na1631_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na966_2), .IN6(1'b0), .IN7(na998_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y58 80'h00_0060_00_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1632_4 ( .OUT(na1632_2), .IN1(na1061_2), .IN2(na567_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x88y52 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1635_1 ( .OUT(na1635_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1158_1), .IN6(1'b1), .IN7(na2031_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x88y60 80'h00_0060_00_0000_0C0E_FF33 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1636_4 ( .OUT(na1636_2), .IN1(1'b0), .IN2(~na1943_2), .IN3(1'b0), .IN4(~na866_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x98y63 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1637_1 ( .OUT(na1637_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na920_1), .IN7(1'b1), .IN8(na49_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x68y73 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1642_1 ( .OUT(na1642_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na968_1), .IN7(1'b0), .IN8(na1000_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x71y64 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1643_4 ( .OUT(na1643_2), .IN1(~na1064_1), .IN2(~na1159_1), .IN3(~na612_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x72y73 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1651_1 ( .OUT(na1651_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na968_2), .IN7(1'b0), .IN8(na1000_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x75y60 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1652_1 ( .OUT(na1652_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(~na1160_1), .IN7(~na612_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x74y57 80'h00_0018_00_0000_0888_5515 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1657_1 ( .OUT(na1657_1), .IN1(~na689_1), .IN2(1'b1), .IN3(~na684_1), .IN4(~na687_1), .IN5(~na1658_2), .IN6(1'b1), .IN7(~na684_2), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x75y61 80'h00_0060_00_0000_0C08_FFC5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1658_4 ( .OUT(na1658_2), .IN1(~na469_1), .IN2(1'b1), .IN3(1'b1), .IN4(na102_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x73y60 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1662_1 ( .OUT(na1662_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(~na1161_1), .IN7(~na612_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x74y51 80'h00_0018_00_0000_0888_331A +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1667_1 ( .OUT(na1667_1), .IN1(na1671_1), .IN2(1'b1), .IN3(~na695_1), .IN4(~na1668_1), .IN5(1'b1), .IN6(~na698_1), .IN7(1'b1), + .IN8(~na1668_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x80y66 80'h00_0078_00_0000_0C88_F4CC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1668_1 ( .OUT(na1668_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na444_1), .IN6(na101_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1668_4 ( .OUT(na1668_2), .IN1(1'b1), .IN2(na1909_2), .IN3(1'b1), .IN4(na1673_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x71y59 80'h00_0018_00_0000_0CEE_7A00 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1671_1 ( .OUT(na1671_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na34_1), .IN6(1'b0), .IN7(~na1905_2), .IN8(~na1510_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x76y64 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1673_1 ( .OUT(na1673_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na970_2), .IN6(1'b0), .IN7(na1002_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x91y54 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1676_4 ( .OUT(na1676_2), .IN1(~na1064_1), .IN2(~na1162_1), .IN3(~na612_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x84y59 80'h00_0018_00_0000_0EEE_0EEC +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1681_1 ( .OUT(na1681_1), .IN1(1'b0), .IN2(na1682_2), .IN3(na706_1), .IN4(na708_1), .IN5(na1683_1), .IN6(na1682_1), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x81y70 80'h00_0078_00_0000_0C88_3C4F +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1682_1 ( .OUT(na1682_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na101_1), .IN7(1'b1), .IN8(~na418_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1682_4 ( .OUT(na1682_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na707_1), .IN4(na102_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x83y61 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1683_1 ( .OUT(na1683_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na431_1), .IN6(1'b1), .IN7(1'b1), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x89y54 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1687_4 ( .OUT(na1687_2), .IN1(~na1064_1), .IN2(~na1163_1), .IN3(~na612_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x76y65 80'h00_0018_00_0000_0888_775B +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1692_1 ( .OUT(na1692_1), .IN1(na1362_2), .IN2(~na101_1), .IN3(~na714_1), .IN4(1'b0), .IN5(~na1695_1), .IN6(~na1909_2), .IN7(~na843_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x67y75 80'h00_0018_00_0040_0AA0_00CF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1695_1 ( .OUT(na1695_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na335_1), .IN5(1'b0), .IN6(na972_2), .IN7(1'b0), .IN8(na1004_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x81y66 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1698_1 ( .OUT(na1698_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(~na1164_1), .IN7(~na612_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x82y64 80'h00_0060_00_0000_0C0E_FFAB +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a1703_4 ( .OUT(na1703_2), .IN1(na364_1), .IN2(~na101_1), .IN3(na782_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x84y71 80'h00_0078_00_0000_0C88_C5CC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1705_1 ( .OUT(na1705_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na380_1), .IN6(1'b1), .IN7(1'b1), .IN8(na102_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1705_4 ( .OUT(na1705_2), .IN1(1'b1), .IN2(na1710_1), .IN3(1'b1), .IN4(na102_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x67y60 80'h00_0018_00_0000_0CEE_3D00 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1708_1 ( .OUT(na1708_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na84_1), .IN6(na37_1), .IN7(1'b0), .IN8(~na1503_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x77y68 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1710_1 ( .OUT(na1710_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na975_1), .IN6(1'b0), .IN7(na1007_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y52 80'h00_0018_00_0000_0C88_57FF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1712_1 ( .OUT(na1712_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1064_1), .IN6(~na1166_1), .IN7(~na612_1), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x82y57 80'h00_0018_00_0000_0888_5435 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1715_1 ( .OUT(na1715_1), .IN1(~na732_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1717_1), .IN5(~na1718_1), .IN6(na731_1), .IN7(~na728_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x88y66 80'h00_0018_00_0000_0C88_3CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1717_1 ( .OUT(na1717_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na1911_2), .IN7(1'b1), .IN8(~na330_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x73y59 80'h00_0018_00_0000_0C88_DAFF +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1718_1 ( .OUT(na1718_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na85_1), .IN6(1'b0), .IN7(~na1898_2), .IN8(na1497_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x69y79 80'h00_0018_00_0040_0A50_00C0 +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1720_1 ( .OUT(na1720_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(na335_1), .IN5(na975_2), .IN6(1'b0), .IN7(na1007_2), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x77y70 80'h00_0060_00_0000_0C08_FF57 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1721_4 ( .OUT(na1721_2), .IN1(~na1064_1), .IN2(~na1167_1), .IN3(~na612_1), .IN4(1'b0), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX2b//// x83y74 80'h00_0018_00_0040_0AA2_00AF +C_MX2b #(.CPE_CFG (9'b0_0000_0000)) + _a1730_1 ( .OUT(na1730_1), .IN1(1'b1), .IN2(1'b1), .IN3(na10_1), .IN4(1'b1), .IN5(1'b0), .IN6(~na283_1), .IN7(1'b0), .IN8(na776_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x67y56 80'h00_0018_00_0000_0C88_A3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1731_1 ( .OUT(na1731_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na4_1), .IN7(na1496_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x77y67 80'h00_0018_00_0000_0CEE_5700 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1732_1 ( .OUT(na1732_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na1064_1), .IN6(~na778_1), .IN7(~na2029_2), + .IN8(1'b0), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///ORAND/ x82y71 80'h00_0060_00_0000_0C08_FF73 +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a1734_4 ( .OUT(na1734_2), .IN1(1'b0), .IN2(~na357_1), .IN3(~na10_1), .IN4(~na781_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x81y73 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1735_4 ( .OUT(na1735_2), .IN1(1'b1), .IN2(1'b1), .IN3(na10_1), .IN4(na781_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x93y52 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1738_4 ( .OUT(na1738_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na1739_1), .IN4(na350_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y53 80'h00_0018_00_0000_0888_7753 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1739_1 ( .OUT(na1739_1), .IN1(1'b0), .IN2(~na390_1), .IN3(~na407_2), .IN4(1'b0), .IN5(~na785_1), .IN6(~na2033_2), .IN7(~na1374_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x91y51 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1741_4 ( .OUT(na1741_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na1742_1), .IN4(na350_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x88y55 80'h00_0018_00_0000_0888_7773 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1742_1 ( .OUT(na1742_1), .IN1(1'b0), .IN2(~na485_1), .IN3(~na479_1), .IN4(~na102_2), .IN5(~na790_1), .IN6(~na2033_2), .IN7(~na1434_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x90y55 80'h00_0018_00_0000_0C88_C8FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1743_1 ( .OUT(na1743_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1941_2), .IN6(na2033_2), .IN7(1'b1), .IN8(na793_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x91y53 80'h00_0018_00_0000_0888_3C34 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1745_1 ( .OUT(na1745_1), .IN1(~na1453_2), .IN2(na1450_1), .IN3(1'b1), .IN4(~na1449_1), .IN5(1'b1), .IN6(na1450_2), .IN7(1'b1), + .IN8(~na350_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x92y56 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1750_1 ( .OUT(na1750_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1751_1), .IN6(1'b1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y57 80'h00_0018_00_0000_0888_77B5 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1751_1 ( .OUT(na1751_1), .IN1(~na528_2), .IN2(1'b0), .IN3(na525_1), .IN4(~na102_2), .IN5(~na800_1), .IN6(~na2033_2), .IN7(~na1472_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x93y53 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1753_4 ( .OUT(na1753_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na1754_1), .IN4(na350_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y55 80'h00_0018_00_0000_0888_7755 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1754_1 ( .OUT(na1754_1), .IN1(~na539_1), .IN2(1'b0), .IN3(~na535_1), .IN4(1'b0), .IN5(~na2032_2), .IN6(~na803_1), .IN7(~na1482_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y50 80'h00_0018_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1756_1 ( .OUT(na1756_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na1341_2), .IN6(1'b1), .IN7(~na551_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x87y51 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1757_1 ( .OUT(na1757_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1758_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y56 80'h00_0018_00_0000_0888_7753 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1758_1 ( .OUT(na1758_1), .IN1(1'b0), .IN2(~na545_2), .IN3(~na549_1), .IN4(1'b0), .IN5(~na806_1), .IN6(~na2033_2), .IN7(~na1495_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x92y59 80'h00_0018_00_0000_0C88_C3FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1760_1 ( .OUT(na1760_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1761_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x81y64 80'h00_0018_00_0000_0888_775B +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1761_1 ( .OUT(na1761_1), .IN1(na1963_2), .IN2(~na101_1), .IN3(~na557_2), .IN4(1'b0), .IN5(~na1908_2), .IN6(~na1505_1), .IN7(~na810_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x94y56 80'h00_0060_00_0000_0C08_FF4F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1766_4 ( .OUT(na1766_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na1767_1), .IN4(na350_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x94y69 80'h00_0018_00_0000_0888_77B3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1767_1 ( .OUT(na1767_1), .IN1(1'b0), .IN2(~na608_1), .IN3(na600_2), .IN4(~na102_2), .IN5(~na819_1), .IN6(~na2033_2), .IN7(~na1561_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x90y60 80'h00_0078_00_0000_0C88_C3CA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1769_1 ( .OUT(na1769_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1770_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1769_4 ( .OUT(na1769_2), .IN1(na913_2), .IN2(1'b1), .IN3(1'b1), .IN4(na49_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x77y74 80'h00_0018_00_0000_0888_77B3 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1770_1 ( .OUT(na1770_1), .IN1(1'b0), .IN2(~na628_1), .IN3(na574_1), .IN4(~na102_2), .IN5(~na822_1), .IN6(~na2033_2), .IN7(~na1584_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x89y63 80'h00_0078_00_0000_0C88_C3CC +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1772_1 ( .OUT(na1772_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1773_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1772_4 ( .OUT(na1772_2), .IN1(1'b1), .IN2(na567_1), .IN3(1'b1), .IN4(na1070_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y66 80'h00_0018_00_0000_0888_77B5 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1773_1 ( .OUT(na1773_1), .IN1(~na635_1), .IN2(1'b0), .IN3(na556_1), .IN4(~na102_2), .IN5(~na1592_1), .IN6(~na1909_2), .IN7(~na825_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x85y64 80'h00_0018_00_0000_0888_7573 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1775_1 ( .OUT(na1775_1), .IN1(1'b0), .IN2(~na642_1), .IN3(~na1603_1), .IN4(~na102_1), .IN5(~na643_1), .IN6(1'b0), .IN7(~na828_1), + .IN8(~na1065_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x94y54 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1778_4 ( .OUT(na1778_2), .IN1(na1942_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1779_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x86y62 80'h00_0018_00_0000_0888_7755 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1779_1 ( .OUT(na1779_1), .IN1(~na648_1), .IN2(1'b0), .IN3(~na649_1), .IN4(1'b0), .IN5(~na831_1), .IN6(~na2033_2), .IN7(~na1612_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x92y61 80'h00_0078_00_0000_0C88_C3AA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1782_1 ( .OUT(na1782_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na1783_1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1782_4 ( .OUT(na1782_2), .IN1(na943_1), .IN2(1'b1), .IN3(na346_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x77y54 80'h00_0018_00_0000_0888_7753 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1783_1 ( .OUT(na1783_1), .IN1(1'b0), .IN2(~na664_1), .IN3(~na665_1), .IN4(1'b0), .IN5(~na836_1), .IN6(~na2033_2), .IN7(~na1631_1), + .IN8(~na102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x91y64 80'h00_0060_00_0000_0C08_FF3C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1788_4 ( .OUT(na1788_2), .IN1(1'b1), .IN2(na89_1), .IN3(1'b1), .IN4(~na418_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x92y55 80'h00_0060_00_0000_0C08_FF3A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1790_4 ( .OUT(na1790_2), .IN1(na1942_2), .IN2(1'b1), .IN3(1'b1), .IN4(~na1791_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x80y60 80'h00_0018_00_0000_0888_FB73 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1791_1 ( .OUT(na1791_1), .IN1(1'b0), .IN2(~na845_1), .IN3(~na1389_1), .IN4(~na102_1), .IN5(na431_1), .IN6(~na101_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x89y60 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1793_1 ( .OUT(na1793_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na89_1), .IN7(na460_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x90y53 80'h00_0018_00_0000_0C88_C5FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1795_1 ( .OUT(na1795_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na1796_1), .IN6(1'b1), .IN7(1'b1), .IN8(na350_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND//// x83y65 80'h00_0018_00_0000_0888_FB75 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a1796_1 ( .OUT(na1796_1), .IN1(~na848_1), .IN2(1'b0), .IN3(~na1420_1), .IN4(~na102_1), .IN5(na469_1), .IN6(~na101_1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x59y128 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1797_4 ( .OUT(na1797_2), .IN1(1'b1), .IN2(1'b1), .IN3(na75_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1797_6 ( .RAM_O2(na1797_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1797_2), .COMP_OUT(1'b0) ); +// C_///AND/ x61y128 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1798_4 ( .OUT(na1798_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na77_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1798_6 ( .RAM_O2(na1798_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1798_2), .COMP_OUT(1'b0) ); +// C_///AND/ x65y128 80'h08_0060_00_0000_0C08_FFF3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1799_4 ( .OUT(na1799_2), .IN1(1'b1), .IN2(~na146_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1799_6 ( .RAM_O2(na1799_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1799_2), .COMP_OUT(1'b0) ); +// C_///AND/ x67y128 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1800_4 ( .OUT(na1800_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na151_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1800_6 ( .RAM_O2(na1800_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1800_2), .COMP_OUT(1'b0) ); +// C_///AND/ x69y128 80'h08_0060_00_0000_0C08_FF3F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1801_4 ( .OUT(na1801_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na156_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1801_6 ( .RAM_O2(na1801_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1801_2), .COMP_OUT(1'b0) ); +// C_///AND/ x73y128 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1802_4 ( .OUT(na1802_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na161_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1802_6 ( .RAM_O2(na1802_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1802_2), .COMP_OUT(1'b0) ); +// C_///AND/ x75y128 80'h08_0060_00_0000_0C08_FFF3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1803_4 ( .OUT(na1803_2), .IN1(1'b1), .IN2(~na166_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1803_6 ( .RAM_O2(na1803_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1803_2), .COMP_OUT(1'b0) ); +// C_///AND/ x77y128 80'h08_0060_00_0000_0C08_FFF3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1804_4 ( .OUT(na1804_2), .IN1(1'b1), .IN2(~na171_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1804_6 ( .RAM_O2(na1804_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1804_2), .COMP_OUT(1'b0) ); +// C_///AND/ x81y128 80'h08_0060_00_0000_0C08_FFF5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1805_4 ( .OUT(na1805_2), .IN1(~na176_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1805_6 ( .RAM_O2(na1805_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1805_2), .COMP_OUT(1'b0) ); +// C_///AND/ x83y128 80'h08_0060_00_0000_0C08_FFF3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1806_4 ( .OUT(na1806_2), .IN1(1'b1), .IN2(~na181_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1806_6 ( .RAM_O2(na1806_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1806_2), .COMP_OUT(1'b0) ); +// C_///AND/ x87y128 80'h08_0060_00_0000_0C08_FF3F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1807_4 ( .OUT(na1807_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na186_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1807_6 ( .RAM_O2(na1807_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1807_2), .COMP_OUT(1'b0) ); +// C_///AND/ x89y128 80'h08_0060_00_0000_0C08_FFF5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1808_4 ( .OUT(na1808_2), .IN1(~na191_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1808_6 ( .RAM_O2(na1808_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1808_2), .COMP_OUT(1'b0) ); +// C_///AND/ x91y128 80'h08_0060_00_0000_0C08_FF3F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1809_4 ( .OUT(na1809_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(~na106_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1809_6 ( .RAM_O2(na1809_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1809_2), .COMP_OUT(1'b0) ); +// C_///AND/ x103y128 80'h08_0060_00_0000_0C08_FFF5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1810_4 ( .OUT(na1810_2), .IN1(~na196_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1810_6 ( .RAM_O2(na1810_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1810_2), .COMP_OUT(1'b0) ); +// C_///AND/ x105y128 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1811_4 ( .OUT(na1811_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na201_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1811_6 ( .RAM_O2(na1811_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1811_2), .COMP_OUT(1'b0) ); +// C_///AND/ x107y128 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1812_4 ( .OUT(na1812_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na206_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1812_6 ( .RAM_O2(na1812_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1812_2), .COMP_OUT(1'b0) ); +// C_///AND/ x111y128 80'h08_0060_00_0000_0C08_FFF5 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1813_4 ( .OUT(na1813_2), .IN1(~na211_2), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1813_6 ( .RAM_O2(na1813_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1813_2), .COMP_OUT(1'b0) ); +// C_///AND/ x113y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1814_4 ( .OUT(na1814_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1814_6 ( .RAM_O2(na1814_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1814_2), .COMP_OUT(1'b0) ); +// C_///AND/ x117y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1815_4 ( .OUT(na1815_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1815_6 ( .RAM_O2(na1815_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1815_2), .COMP_OUT(1'b0) ); +// C_///AND/ x119y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1816_4 ( .OUT(na1816_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1816_6 ( .RAM_O2(na1816_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1816_2), .COMP_OUT(1'b0) ); +// C_///AND/ x121y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1817_4 ( .OUT(na1817_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1817_6 ( .RAM_O2(na1817_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1817_2), .COMP_OUT(1'b0) ); +// C_///AND/ x125y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1818_4 ( .OUT(na1818_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1818_6 ( .RAM_O2(na1818_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1818_2), .COMP_OUT(1'b0) ); +// C_///AND/ x127y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1819_4 ( .OUT(na1819_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1819_6 ( .RAM_O2(na1819_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1819_2), .COMP_OUT(1'b0) ); +// C_///AND/ x129y128 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1820_4 ( .OUT(na1820_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na111_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1820_6 ( .RAM_O2(na1820_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1820_2), .COMP_OUT(1'b0) ); +// C_///AND/ x133y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1821_4 ( .OUT(na1821_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1821_6 ( .RAM_O2(na1821_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1821_2), .COMP_OUT(1'b0) ); +// C_///AND/ x135y128 80'h08_0060_00_0000_0C08_FFF0 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1822_4 ( .OUT(na1822_2), .IN1(1'b0), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1822_6 ( .RAM_O2(na1822_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1822_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y27 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1823_4 ( .OUT(na1823_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na116_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1823_6 ( .RAM_O2(na1823_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1823_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y29 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1824_4 ( .OUT(na1824_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na121_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1824_6 ( .RAM_O2(na1824_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1824_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y31 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1825_4 ( .OUT(na1825_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na126_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1825_6 ( .RAM_O2(na1825_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1825_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y35 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1826_4 ( .OUT(na1826_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na131_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1826_6 ( .RAM_O2(na1826_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1826_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y37 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1827_4 ( .OUT(na1827_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na136_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1827_6 ( .RAM_O2(na1827_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1827_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y39 80'h08_0060_00_0000_0C08_FF5F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1828_4 ( .OUT(na1828_2), .IN1(1'b1), .IN2(1'b1), .IN3(~na141_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1828_6 ( .RAM_O2(na1828_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1828_2), .COMP_OUT(1'b0) ); +// C_///AND/ x101y1 80'h08_0060_00_0000_0C08_FFF3 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1829_4 ( .OUT(na1829_2), .IN1(1'b1), .IN2(~na736_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1829_6 ( .RAM_O2(na1829_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1829_2), .COMP_OUT(1'b0) ); +// C_///AND/ x107y1 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1830_4 ( .OUT(na1830_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1302_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1830_6 ( .RAM_O2(na1830_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1830_2), .COMP_OUT(1'b0) ); +// C_///AND/ x109y1 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1831_4 ( .OUT(na1831_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1301_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1831_6 ( .RAM_O2(na1831_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1831_2), .COMP_OUT(1'b0) ); +// C_///AND/ x113y1 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1832_4 ( .OUT(na1832_2), .IN1(1'b1), .IN2(na218_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1832_6 ( .RAM_O2(na1832_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1832_2), .COMP_OUT(1'b0) ); +// C_///AND/ x115y1 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1833_4 ( .OUT(na1833_2), .IN1(1'b1), .IN2(na219_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1833_6 ( .RAM_O2(na1833_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1833_2), .COMP_OUT(1'b0) ); +// C_///AND/ x117y1 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1834_4 ( .OUT(na1834_2), .IN1(na220_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1834_6 ( .RAM_O2(na1834_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1834_2), .COMP_OUT(1'b0) ); +// C_///AND/ x121y1 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1835_4 ( .OUT(na1835_2), .IN1(na221_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1835_6 ( .RAM_O2(na1835_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1835_2), .COMP_OUT(1'b0) ); +// C_///AND/ x123y1 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1836_4 ( .OUT(na1836_2), .IN1(1'b1), .IN2(na222_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1836_6 ( .RAM_O2(na1836_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1836_2), .COMP_OUT(1'b0) ); +// C_///AND/ x125y1 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1837_4 ( .OUT(na1837_2), .IN1(1'b1), .IN2(na223_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1837_6 ( .RAM_O2(na1837_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1837_2), .COMP_OUT(1'b0) ); +// C_///AND/ x129y1 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1838_4 ( .OUT(na1838_2), .IN1(1'b1), .IN2(na224_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1838_6 ( .RAM_O2(na1838_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1838_2), .COMP_OUT(1'b0) ); +// C_///AND/ x131y1 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1839_4 ( .OUT(na1839_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na225_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1839_6 ( .RAM_O2(na1839_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1839_2), .COMP_OUT(1'b0) ); +// C_///AND/ x133y1 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1840_4 ( .OUT(na1840_2), .IN1(1'b1), .IN2(1'b1), .IN3(na226_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1840_6 ( .RAM_O2(na1840_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1840_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y25 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1841_4 ( .OUT(na1841_2), .IN1(1'b1), .IN2(1'b1), .IN3(na227_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1841_6 ( .RAM_O2(na1841_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1841_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y27 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1842_4 ( .OUT(na1842_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1299_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1842_6 ( .RAM_O2(na1842_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1842_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y31 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1843_4 ( .OUT(na1843_2), .IN1(1'b1), .IN2(1'b1), .IN3(na228_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1843_6 ( .RAM_O2(na1843_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1843_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y33 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1844_4 ( .OUT(na1844_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na229_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1844_6 ( .RAM_O2(na1844_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1844_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y35 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1845_4 ( .OUT(na1845_2), .IN1(1'b1), .IN2(1'b1), .IN3(na230_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1845_6 ( .RAM_O2(na1845_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1845_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y39 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1846_4 ( .OUT(na1846_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na231_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1846_6 ( .RAM_O2(na1846_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1846_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y41 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1847_4 ( .OUT(na1847_2), .IN1(na232_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1847_6 ( .RAM_O2(na1847_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1847_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y43 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1848_4 ( .OUT(na1848_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na233_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1848_6 ( .RAM_O2(na1848_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1848_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y47 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1849_4 ( .OUT(na1849_2), .IN1(1'b1), .IN2(na234_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1849_6 ( .RAM_O2(na1849_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1849_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y49 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1850_4 ( .OUT(na1850_2), .IN1(na235_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1850_6 ( .RAM_O2(na1850_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1850_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y53 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1851_4 ( .OUT(na1851_2), .IN1(1'b1), .IN2(1'b1), .IN3(na236_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1851_6 ( .RAM_O2(na1851_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1851_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y55 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1852_4 ( .OUT(na1852_2), .IN1(na237_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1852_6 ( .RAM_O2(na1852_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1852_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y57 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1853_4 ( .OUT(na1853_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1298_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1853_6 ( .RAM_O2(na1853_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1853_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y69 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1854_4 ( .OUT(na1854_2), .IN1(na238_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1854_6 ( .RAM_O2(na1854_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1854_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y71 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1855_4 ( .OUT(na1855_2), .IN1(1'b1), .IN2(na239_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1855_6 ( .RAM_O2(na1855_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1855_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y73 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1856_4 ( .OUT(na1856_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1297_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1856_6 ( .RAM_O2(na1856_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1856_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y77 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1857_4 ( .OUT(na1857_2), .IN1(1'b1), .IN2(1'b1), .IN3(na1295_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1857_6 ( .RAM_O2(na1857_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1857_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y79 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1858_4 ( .OUT(na1858_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1294_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1858_6 ( .RAM_O2(na1858_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1858_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y83 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1859_4 ( .OUT(na1859_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1293_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1859_6 ( .RAM_O2(na1859_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1859_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y85 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1860_4 ( .OUT(na1860_2), .IN1(na216_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1860_6 ( .RAM_O2(na1860_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1860_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y87 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1861_4 ( .OUT(na1861_2), .IN1(na217_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1861_6 ( .RAM_O2(na1861_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1861_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y91 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1862_4 ( .OUT(na1862_2), .IN1(na737_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1862_6 ( .RAM_O2(na1862_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1862_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y93 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1863_4 ( .OUT(na1863_2), .IN1(na739_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1863_6 ( .RAM_O2(na1863_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1863_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y95 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1864_4 ( .OUT(na1864_2), .IN1(1'b1), .IN2(na740_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1864_6 ( .RAM_O2(na1864_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1864_2), .COMP_OUT(1'b0) ); +// C_///AND/ x1y89 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1865_4 ( .OUT(na1865_2), .IN1(na741_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a1865_6 ( .RAM_O2(na1865_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na1865_2), .COMP_OUT(1'b0) ); +// C_////Bridge x92y69 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1866_5 ( .OUT(na1866_2), .IN1(na3_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x82y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1867_5 ( .OUT(na1867_2), .IN1(1'b0), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x76y66 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1868_5 ( .OUT(na1868_2), .IN1(1'b0), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x95y75 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1869_5 ( .OUT(na1869_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na5_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x83y60 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1870_5 ( .OUT(na1870_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na5_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x77y76 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1871_5 ( .OUT(na1871_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na7_1) ); +// C_////Bridge x90y73 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1872_5 ( .OUT(na1872_2), .IN1(1'b0), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x84y78 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1873_5 ( .OUT(na1873_2), .IN1(1'b0), .IN2(na8_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y66 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1874_5 ( .OUT(na1874_2), .IN1(1'b0), .IN2(na9_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y75 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1875_5 ( .OUT(na1875_2), .IN1(1'b0), .IN2(1'b0), .IN3(na10_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y74 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1876_5 ( .OUT(na1876_2), .IN1(1'b0), .IN2(1'b0), .IN3(na10_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y66 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1877_5 ( .OUT(na1877_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na11_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y58 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1878_5 ( .OUT(na1878_2), .IN1(1'b0), .IN2(na12_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y50 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1879_5 ( .OUT(na1879_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na13_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y47 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1880_5 ( .OUT(na1880_2), .IN1(na14_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y61 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1881_5 ( .OUT(na1881_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na15_1) ); +// C_////Bridge x80y52 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1882_5 ( .OUT(na1882_2), .IN1(1'b0), .IN2(na16_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x82y52 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1883_5 ( .OUT(na1883_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na17_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x82y54 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1884_5 ( .OUT(na1884_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na18_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x72y48 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1885_5 ( .OUT(na1885_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na19_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y64 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1886_5 ( .OUT(na1886_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na20_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x78y54 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1887_5 ( .OUT(na1887_2), .IN1(na23_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y68 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1888_5 ( .OUT(na1888_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na24_1) ); +// C_////Bridge x74y54 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1889_5 ( .OUT(na1889_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na25_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y56 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1890_5 ( .OUT(na1890_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na26_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y70 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1891_5 ( .OUT(na1891_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na28_1) ); +// C_////Bridge x84y52 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1892_5 ( .OUT(na1892_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na30_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y72 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1893_5 ( .OUT(na1893_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na31_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y50 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1894_5 ( .OUT(na1894_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na33_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y48 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1895_5 ( .OUT(na1895_2), .IN1(na35_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y74 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1896_5 ( .OUT(na1896_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na36_1) ); +// C_////Bridge x74y52 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1897_5 ( .OUT(na1897_2), .IN1(1'b0), .IN2(na37_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x76y59 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1898_5 ( .OUT(na1898_2), .IN1(na38_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y70 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1899_5 ( .OUT(na1899_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na44_2) ); +// C_////Bridge x91y62 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1900_5 ( .OUT(na1900_2), .IN1(na45_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x98y67 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1901_5 ( .OUT(na1901_2), .IN1(na45_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y68 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1902_5 ( .OUT(na1902_2), .IN1(na45_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x86y63 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1903_5 ( .OUT(na1903_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na49_1) ); +// C_////Bridge x81y52 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1904_5 ( .OUT(na1904_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na83_2), .IN8(1'b0) ); +// C_////Bridge x84y69 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1905_5 ( .OUT(na1905_2), .IN1(na84_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x77y60 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1906_5 ( .OUT(na1906_2), .IN1(na84_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x82y66 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1907_5 ( .OUT(na1907_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na101_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y65 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1908_5 ( .OUT(na1908_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na102_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x81y64 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1909_5 ( .OUT(na1909_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na102_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y61 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1910_5 ( .OUT(na1910_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na102_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y68 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1911_5 ( .OUT(na1911_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na102_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x87y61 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1912_5 ( .OUT(na1912_2), .IN1(1'b0), .IN2(1'b0), .IN3(na247_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y82 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1913_5 ( .OUT(na1913_2), .IN1(1'b0), .IN2(1'b0), .IN3(na247_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y55 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1914_5 ( .OUT(na1914_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na249_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x101y56 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1915_5 ( .OUT(na1915_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na250_1) ); +// C_////Bridge x95y72 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1916_5 ( .OUT(na1916_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na250_2) ); +// C_////Bridge x92y64 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1917_5 ( .OUT(na1917_2), .IN1(1'b0), .IN2(na258_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x92y62 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1918_5 ( .OUT(na1918_2), .IN1(1'b0), .IN2(na258_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y58 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1919_5 ( .OUT(na1919_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na260_1) ); +// C_////Bridge x85y80 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1920_5 ( .OUT(na1920_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na260_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x96y68 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1921_5 ( .OUT(na1921_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na262_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x96y66 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1922_5 ( .OUT(na1922_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na262_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x96y70 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1923_5 ( .OUT(na1923_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na264_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y68 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1924_5 ( .OUT(na1924_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na264_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y70 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1925_5 ( .OUT(na1925_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na266_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x92y74 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1926_5 ( .OUT(na1926_2), .IN1(1'b0), .IN2(na266_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y76 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1927_5 ( .OUT(na1927_2), .IN1(1'b0), .IN2(na268_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y72 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1928_5 ( .OUT(na1928_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na268_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x96y76 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1929_5 ( .OUT(na1929_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na269_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y76 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1930_5 ( .OUT(na1930_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na273_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x81y72 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1931_5 ( .OUT(na1931_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na284_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x87y64 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1932_5 ( .OUT(na1932_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na298_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y70 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1933_5 ( .OUT(na1933_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na303_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x77y73 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1934_5 ( .OUT(na1934_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na307_1) ); +// C_////Bridge x77y74 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1935_5 ( .OUT(na1935_2), .IN1(na311_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x82y80 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1936_5 ( .OUT(na1936_2), .IN1(1'b0), .IN2(na322_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y69 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1937_5 ( .OUT(na1937_2), .IN1(1'b0), .IN2(1'b0), .IN3(na326_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y62 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1938_5 ( .OUT(na1938_2), .IN1(1'b0), .IN2(1'b0), .IN3(na327_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y62 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1939_5 ( .OUT(na1939_2), .IN1(1'b0), .IN2(1'b0), .IN3(na327_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y60 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1940_5 ( .OUT(na1940_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na335_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y55 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1941_5 ( .OUT(na1941_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na350_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y55 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1942_5 ( .OUT(na1942_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na350_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y56 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1943_5 ( .OUT(na1943_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na350_2) ); +// C_////Bridge x84y66 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1944_5 ( .OUT(na1944_2), .IN1(1'b0), .IN2(na356_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y78 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1945_5 ( .OUT(na1945_2), .IN1(na359_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y79 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1946_5 ( .OUT(na1946_2), .IN1(1'b0), .IN2(1'b0), .IN3(na361_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y81 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1947_5 ( .OUT(na1947_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na363_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x78y78 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1948_5 ( .OUT(na1948_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na370_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y69 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1949_5 ( .OUT(na1949_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na378_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x87y80 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1950_5 ( .OUT(na1950_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na396_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y75 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1951_5 ( .OUT(na1951_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na402_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y66 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1952_5 ( .OUT(na1952_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na410_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x88y78 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1953_5 ( .OUT(na1953_2), .IN1(1'b0), .IN2(na430_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x76y78 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1954_5 ( .OUT(na1954_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na465_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x76y76 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1955_5 ( .OUT(na1955_2), .IN1(1'b0), .IN2(na468_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y78 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1956_5 ( .OUT(na1956_2), .IN1(1'b0), .IN2(1'b0), .IN3(na470_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x77y61 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1957_5 ( .OUT(na1957_2), .IN1(1'b0), .IN2(1'b0), .IN3(na479_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x92y53 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1958_5 ( .OUT(na1958_2), .IN1(na496_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x90y48 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1959_5 ( .OUT(na1959_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na509_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x83y49 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1960_5 ( .OUT(na1960_2), .IN1(1'b0), .IN2(1'b0), .IN3(na510_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y59 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1961_5 ( .OUT(na1961_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na525_1), .IN8(1'b0) ); +// C_////Bridge x91y76 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1962_5 ( .OUT(na1962_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na538_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x83y63 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1963_5 ( .OUT(na1963_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na556_1), .IN8(1'b0) ); +// C_////Bridge x83y57 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1964_5 ( .OUT(na1964_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na567_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y69 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1965_5 ( .OUT(na1965_2), .IN1(1'b0), .IN2(1'b0), .IN3(na574_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x77y51 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1966_5 ( .OUT(na1966_2), .IN1(1'b0), .IN2(1'b0), .IN3(na600_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x86y75 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1967_5 ( .OUT(na1967_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na777_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x86y53 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1968_5 ( .OUT(na1968_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na870_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x88y53 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1969_5 ( .OUT(na1969_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na875_1) ); +// C_////Bridge x75y50 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1970_5 ( .OUT(na1970_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na883_1), .IN8(1'b0) ); +// C_////Bridge x81y77 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1971_5 ( .OUT(na1971_2), .IN1(1'b0), .IN2(1'b0), .IN3(na885_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x81y79 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1972_5 ( .OUT(na1972_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na885_2), .IN8(1'b0) ); +// C_////Bridge x83y75 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1973_5 ( .OUT(na1973_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na887_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y77 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1974_5 ( .OUT(na1974_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na887_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y83 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1975_5 ( .OUT(na1975_2), .IN1(1'b0), .IN2(1'b0), .IN3(na889_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y75 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1976_5 ( .OUT(na1976_2), .IN1(1'b0), .IN2(1'b0), .IN3(na889_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x87y81 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1977_5 ( .OUT(na1977_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na891_1) ); +// C_////Bridge x93y79 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1978_5 ( .OUT(na1978_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na891_2) ); +// C_////Bridge x79y83 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1979_5 ( .OUT(na1979_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na893_1), .IN8(1'b0) ); +// C_////Bridge x87y83 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1980_5 ( .OUT(na1980_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na893_2), .IN8(1'b0) ); +// C_////Bridge x77y57 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1981_5 ( .OUT(na1981_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na894_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x75y56 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1982_5 ( .OUT(na1982_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na894_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y77 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1983_5 ( .OUT(na1983_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na896_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x95y77 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1984_5 ( .OUT(na1984_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na896_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y77 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1985_5 ( .OUT(na1985_2), .IN1(1'b0), .IN2(1'b0), .IN3(na898_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x81y75 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1986_5 ( .OUT(na1986_2), .IN1(1'b0), .IN2(1'b0), .IN3(na899_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y71 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1987_5 ( .OUT(na1987_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na900_1) ); +// C_////Bridge x97y71 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1988_5 ( .OUT(na1988_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na901_1), .IN8(1'b0) ); +// C_////Bridge x99y75 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1989_5 ( .OUT(na1989_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na902_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x101y71 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1990_5 ( .OUT(na1990_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na902_2) ); +// C_////Bridge x99y71 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1991_5 ( .OUT(na1991_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na904_1), .IN8(1'b0) ); +// C_////Bridge x101y73 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1992_5 ( .OUT(na1992_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na904_2), .IN8(1'b0) ); +// C_////Bridge x97y73 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1993_5 ( .OUT(na1993_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na906_1) ); +// C_////Bridge x91y73 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1994_5 ( .OUT(na1994_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na906_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y72 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1995_5 ( .OUT(na1995_2), .IN1(na909_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y72 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1996_5 ( .OUT(na1996_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na913_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x97y76 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1997_5 ( .OUT(na1997_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na917_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1998_5 ( .OUT(na1998_2), .IN1(1'b0), .IN2(na931_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y67 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a1999_5 ( .OUT(na1999_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na935_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y73 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2000_5 ( .OUT(na2000_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na939_1), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y61 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2001_5 ( .OUT(na2001_2), .IN1(1'b0), .IN2(na944_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y61 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2002_5 ( .OUT(na2002_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na984_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y56 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2003_5 ( .OUT(na2003_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na985_1), .IN8(1'b0) ); +// C_////Bridge x65y67 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2004_5 ( .OUT(na2004_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na987_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y68 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2005_5 ( .OUT(na2005_2), .IN1(1'b0), .IN2(1'b0), .IN3(na989_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y57 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2006_5 ( .OUT(na2006_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na991_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y60 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2007_5 ( .OUT(na2007_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na993_1), .IN8(1'b0) ); +// C_////Bridge x65y61 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2008_5 ( .OUT(na2008_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na996_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x65y60 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2009_5 ( .OUT(na2009_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na998_1), .IN8(1'b0) ); +// C_////Bridge x65y65 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2010_5 ( .OUT(na2010_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1000_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y68 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2011_5 ( .OUT(na2011_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1002_1), .IN8(1'b0) ); +// C_////Bridge x71y57 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2012_5 ( .OUT(na2012_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1004_1) ); +// C_////Bridge x73y56 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2013_5 ( .OUT(na2013_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1006_1), .IN8(1'b0) ); +// C_////Bridge x71y58 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2014_5 ( .OUT(na2014_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1007_1), .IN8(1'b0) ); +// C_////Bridge x75y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2015_5 ( .OUT(na2015_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1011_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y62 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2016_5 ( .OUT(na2016_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1013_1), .IN8(1'b0) ); +// C_////Bridge x71y55 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2017_5 ( .OUT(na2017_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1015_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y61 80'h00_00A5_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2018_5 ( .OUT(na2018_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(na1023_2), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x85y59 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2019_5 ( .OUT(na2019_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1055_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x87y62 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2020_5 ( .OUT(na2020_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1055_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y54 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2021_5 ( .OUT(na2021_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1056_1) ); +// C_////Bridge x79y52 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2022_5 ( .OUT(na2022_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1058_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x88y59 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2023_5 ( .OUT(na2023_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1058_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x90y67 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2024_5 ( .OUT(na2024_2), .IN1(na1059_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x95y57 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2025_5 ( .OUT(na2025_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1060_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x81y50 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2026_5 ( .OUT(na2026_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1061_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x88y69 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2027_5 ( .OUT(na2027_2), .IN1(na1061_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x78y59 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2028_5 ( .OUT(na2028_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1062_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x78y51 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2029_5 ( .OUT(na2029_2), .IN1(1'b0), .IN2(na1063_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x84y62 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2030_5 ( .OUT(na2030_2), .IN1(1'b0), .IN2(na1063_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y49 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2031_5 ( .OUT(na2031_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1064_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y53 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2032_5 ( .OUT(na2032_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1065_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x87y58 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2033_5 ( .OUT(na2033_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1065_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y66 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2034_5 ( .OUT(na2034_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1066_1) ); +// C_////Bridge x91y68 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2035_5 ( .OUT(na2035_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1067_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x93y68 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2036_5 ( .OUT(na2036_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1068_2) ); +// C_////Bridge x91y72 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2037_5 ( .OUT(na2037_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1069_2) ); +// C_////Bridge x93y70 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2038_5 ( .OUT(na2038_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1070_1) ); +// C_////Bridge x82y63 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2039_5 ( .OUT(na2039_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1077_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y57 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2040_5 ( .OUT(na2040_2), .IN1(na1077_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x78y56 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2041_5 ( .OUT(na2041_2), .IN1(na1077_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y63 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2042_5 ( .OUT(na2042_2), .IN1(na1079_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x84y57 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2043_5 ( .OUT(na2043_2), .IN1(na1079_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x84y59 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2044_5 ( .OUT(na2044_2), .IN1(na1081_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y59 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2045_5 ( .OUT(na2045_2), .IN1(na1081_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y74 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2046_5 ( .OUT(na2046_2), .IN1(1'b0), .IN2(na1228_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y69 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2047_5 ( .OUT(na2047_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1277_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y50 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2048_5 ( .OUT(na2048_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1277_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x86y45 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2049_5 ( .OUT(na2049_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1278_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x75y51 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2050_5 ( .OUT(na2050_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1279_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x78y52 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2051_5 ( .OUT(na2051_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1281_1), .IN8(1'b0) ); +// C_////Bridge x81y48 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2052_5 ( .OUT(na2052_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1282_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x82y45 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2053_5 ( .OUT(na2053_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1283_1) ); +// C_////Bridge x81y45 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2054_5 ( .OUT(na2054_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1285_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y66 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2055_5 ( .OUT(na2055_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1285_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y71 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2056_5 ( .OUT(na2056_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1286_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y48 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2057_5 ( .OUT(na2057_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1286_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y44 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2058_5 ( .OUT(na2058_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1287_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x78y45 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2059_5 ( .OUT(na2059_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1289_1) ); +// C_////Bridge x61y61 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2060_5 ( .OUT(na2060_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1290_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y62 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2061_5 ( .OUT(na2061_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1291_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x74y72 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2062_5 ( .OUT(na2062_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1306_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x76y74 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2063_5 ( .OUT(na2063_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1307_1), .IN8(1'b0) ); +// C_////Bridge x61y65 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2064_5 ( .OUT(na2064_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1310_1) ); +// C_////Bridge x62y66 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2065_5 ( .OUT(na2065_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1311_2), .IN8(1'b0) ); +// C_////Bridge x73y67 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2066_5 ( .OUT(na2066_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1313_1), .IN8(1'b0) ); +// C_////Bridge x67y52 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2067_5 ( .OUT(na2067_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1314_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x69y54 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2068_5 ( .OUT(na2068_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1315_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y51 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2069_5 ( .OUT(na2069_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1317_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y64 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2070_5 ( .OUT(na2070_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1317_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y47 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2071_5 ( .OUT(na2071_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1318_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x68y66 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2072_5 ( .OUT(na2072_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1318_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x83y77 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2073_5 ( .OUT(na2073_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1332_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y50 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2074_5 ( .OUT(na2074_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1337_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y62 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2075_5 ( .OUT(na2075_2), .IN1(na1341_1), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x91y50 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2076_5 ( .OUT(na2076_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1341_2), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x94y75 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2077_5 ( .OUT(na2077_2), .IN1(1'b0), .IN2(na1350_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x97y47 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2078_5 ( .OUT(na2078_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1359_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y65 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2079_5 ( .OUT(na2079_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1372_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x97y43 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2080_5 ( .OUT(na2080_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1393_1) ); +// C_////Bridge x85y61 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2081_5 ( .OUT(na2081_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1399_1), .IN8(1'b0) ); +// C_////Bridge x95y47 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2082_5 ( .OUT(na2082_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1410_1) ); +// C_////Bridge x79y75 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2083_5 ( .OUT(na2083_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1418_1), .IN8(1'b0) ); +// C_////Bridge x97y45 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2084_5 ( .OUT(na2084_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1424_1) ); +// C_////Bridge x73y55 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2085_5 ( .OUT(na2085_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1430_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y53 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2086_5 ( .OUT(na2086_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1433_1) ); +// C_////Bridge x73y50 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2087_5 ( .OUT(na2087_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1436_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x95y45 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2088_5 ( .OUT(na2088_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1437_1) ); +// C_////Bridge x71y51 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2089_5 ( .OUT(na2089_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1442_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y49 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2090_5 ( .OUT(na2090_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1454_2), .IN8(1'b0) ); +// C_////Bridge x71y49 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2091_5 ( .OUT(na2091_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1455_1), .IN8(1'b0) ); +// C_////Bridge x77y55 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2092_5 ( .OUT(na2092_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1459_2) ); +// C_////Bridge x81y51 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2093_5 ( .OUT(na2093_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1463_1) ); +// C_////Bridge x77y49 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2094_5 ( .OUT(na2094_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1468_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x75y49 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2095_5 ( .OUT(na2095_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1474_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x79y48 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2096_5 ( .OUT(na2096_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1475_2) ); +// C_////Bridge x79y50 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2097_5 ( .OUT(na2097_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1478_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x67y58 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2098_5 ( .OUT(na2098_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1480_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y67 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2099_5 ( .OUT(na2099_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1481_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x75y57 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2100_5 ( .OUT(na2100_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1484_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y58 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2101_5 ( .OUT(na2101_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1491_2) ); +// C_////Bridge x75y58 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2102_5 ( .OUT(na2102_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1492_1) ); +// C_////Bridge x73y57 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2103_5 ( .OUT(na2103_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1493_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x81y54 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2104_5 ( .OUT(na2104_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1493_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x80y65 80'h00_00A4_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2105_5 ( .OUT(na2105_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(na1494_1), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x71y60 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2106_5 ( .OUT(na2106_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1496_1), .IN8(1'b0) ); +// C_////Bridge x63y71 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2107_5 ( .OUT(na2107_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1497_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y51 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2108_5 ( .OUT(na2108_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1503_1) ); +// C_////Bridge x87y63 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2109_5 ( .OUT(na2109_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na1504_2), .IN8(1'b0) ); +// C_////Bridge x73y47 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2110_5 ( .OUT(na2110_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1509_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x73y49 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2111_5 ( .OUT(na2111_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na1514_1) ); +// C_////Bridge x79y47 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2112_5 ( .OUT(na2112_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1517_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x83y51 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2113_5 ( .OUT(na2113_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na1518_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x83y47 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2114_5 ( .OUT(na2114_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1520_2), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x90y58 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2115_5 ( .OUT(na2115_2), .IN1(1'b0), .IN2(na1568_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x89y60 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2116_5 ( .OUT(na2116_2), .IN1(1'b0), .IN2(1'b0), .IN3(na1782_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut3.txt b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut3.txt new file mode 100644 index 0000000000000000000000000000000000000000..48d719af82156c2e12b49d4a1490897d2e44ea41 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut3.txt @@ -0,0 +1,22 @@ +0001 4 abc +0007 11 c/AB\ +000B 2 c/aB\ +000D 2 c/Ab\ +000E 11 c/ab\ +0010 7 abC +0017 1 AB?1:c:c:0 +0035 70 c?b:a +0040 10 aBC +004F 5 (aB)+c +0053 23 C?b:a +0070 12 C/AB\ +0080 3 ABC +00AC 6 c?A:B +00B0 4 C/aB\ +00C5 9 C?a:B +00CA 102 C?A:B +00D0 3 C/Ab\ +00E0 28 C/ab\ +00EF 1 /ab\+c +00F4 2 (aB)+C + Gesamt: 316 DS4: 1 diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut4.txt b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut4.txt new file mode 100644 index 0000000000000000000000000000000000000000..625598dd33fdd6018806c402d8c953cdcedfca9f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut4.txt @@ -0,0 +1,74 @@ +0001 9 abcd +0007 23 cd/AB\ +000B 1 cd/aB\ +000D 1 cd/Ab\ +000E 23 cd/ab\ +001F 4 ((ab)+c)d +007F 1 ((/AB\)+c)d +00BF 3 ((/aB\)+c)d +00F1 1 ((ab)+C)d +0100 1 abcD +0305 13 DC?a:b:0:0 +030A 1 DC?A:b:0:0 +0503 1 DC?b:a:0:0 +05F3 1 DC?b:a:1:0 +0700 6 cD/AB\ +0777 33 /AB\(d+c) +07FF 2 (c/AB\)+d +0A0C 1 DC?B:A:0:0 +0B00 7 cD/aB\ +0BBB 1 /aB\(d+c) +0BFF 1 (c/aB\)+d +0C05 4 DC?a:B:0:0 +0C0A 7 DC?A:B:0:0 +0D00 23 cD/Ab\ +0E00 2 cD/ab\ +0FBB 4 D?/aB\:c +0FEE 1 D?/ab\:c +1000 1 abCD +110F 4 D?c:ab +11F0 10 D?C:ab +1700 1 D(AB?1:c:c:0) +1F00 3 ((ab)+c)D +2FFF 1 (Ab)+c+d +3500 25 D(c?b:a) +35F3 1 DC?b:a:1:b +3A03 24 DC?b:A:0:b +3FA0 1 DC?0:1:A:b +4000 3 aBCD +44F0 1 D?C:aB +4F00 6 ((aB)+c)D +5300 1 D(C?b:a) +5333 3 DC?b:b:b:a +7000 2 CD/AB\ +7077 5 /AB\(d+C) +70FF 2 (C/AB\)+d +8000 2 ABCD +80FF 1 (ABC)+d +880F 1 D?c:AB +8F00 1 ((AB)+c)D +A333 6 DC?b:b:b:A +B0BB 2 /aB\(d+C) +B0FF 19 (C/aB\)+d +BB0F 1 D?c:/aB\ +C500 1 D(C?a:B) +CA00 40 D(C?A:B) +CCC5 1 DC?a:B:B:B +CCCA 8 DC?A:B:B:B +CFA0 1 DC?0:1:A:B +D000 1 CD/Ab\ +E800 1 D(AB?0:C:C:1) +EC0E 7 DC?/ab\:B:0:/ab\ +EE0F 2 D?c:/ab\ +EF00 2 ((/ab\)+c)D +F044 5 D?aB:C +F0BB 1 D?/aB\:C +F100 5 ((ab)+C)D +F2FF 2 (Ab)+C+d +F400 15 ((aB)+C)D +F800 17 ((AB)+C)D +F8FF 2 (AB)+C+d +FC0A 1 DC?A:B:0:1 +FF70 23 (C/AB\)+D +FFF4 1 (aB)+C+D + Gesamt: 438 DS4: 17 diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut_report.txt b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut_report.txt new file mode 100644 index 0000000000000000000000000000000000000000..a72b00326c849f0b7ebf6b17a01e5f248df2db6a --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/lut_report.txt @@ -0,0 +1,850 @@ + 1 LUT2 B /aB\ + 2 LUT4 07FF (c/AB\)+d + 3 LUT3 E0 C/ab\ + 4 LUT4 5333 DC?b:b:b:a + 5 LUT3 10 abC + 6 LUT2 6 A^B + 7 LUT4 5333 DC?b:b:b:a + 8 LUT3 35 c?b:a + 9 LUT2 8 AB + 10 LUT3 35 c?b:a + 11 LUT3 35 c?b:a + 12 LUT3 35 c?b:a + 13 LUT3 35 c?b:a + 14 LUT3 35 c?b:a + 15 LUT3 35 c?b:a + 16 LUT3 35 c?b:a + 17 LUT3 35 c?b:a + 18 LUT3 35 c?b:a + 19 LUT3 35 c?b:a + 20 LUT3 35 c?b:a + 21 LUT3 35 c?b:a + 22 LUT3 35 c?b:a + 23 LUT3 35 c?b:a + 24 LUT3 35 c?b:a + 25 LUT3 35 c?b:a + 26 LUT3 35 c?b:a + 27 LUT3 35 c?b:a + 28 LUT3 35 c?b:a + 29 LUT3 35 c?b:a + 30 LUT3 35 c?b:a + 31 LUT3 35 c?b:a + 32 LUT3 35 c?b:a + 33 LUT3 35 c?b:a + 34 LUT3 35 c?b:a + 35 LUT3 35 c?b:a + 36 LUT3 35 c?b:a + 37 LUT3 35 c?b:a + 38 LUT4 5333 DC?b:b:b:a + 39 LUT3 E0 C/ab\ + 40 LUT4 B0BB /aB\(d+C) + 41 LUT4 0001 abcd + 42 LUT3 D0 C/Ab\ + 43 LUT2 4 aB + 44 LUT3 10 abC + 45 LUT2 1 ab + 46 LUT4 0FEE D?/ab\:c + 47 LUT3 40 aBC + 48 LUT2 4 aB + 49 LUT4 4000 aBCD + 50 LUT2 8 AB + 51 LUT4 F044 D?aB:C + 52 LUT4 F044 D?aB:C + 53 LUT4 F044 D?aB:C + 54 LUT4 F044 D?aB:C + 55 LUT2 4 aB + 56 LUT2 4 aB + 57 LUT2 4 aB + 58 LUT2 4 aB + 59 LUT2 4 aB + 60 LUT2 4 aB + 61 LUT2 4 aB + 62 LUT4 F044 D?aB:C + 63 LUT3 CA C?A:B + 64 LUT3 CA C?A:B + 65 LUT3 CA C?A:B + 66 LUT3 CA C?A:B + 67 LUT3 CA C?A:B + 68 LUT3 CA C?A:B + 69 LUT3 CA C?A:B + 70 LUT3 CA C?A:B + 71 LUT3 CA C?A:B + 72 LUT3 CA C?A:B + 73 LUT3 CA C?A:B + 74 LUT3 CA C?A:B + 75 LUT4 CCC5 DC?a:B:B:B + 76 LUT4 BB0F D?c:/aB\ + 77 LUT4 FF70 (C/AB\)+D + 78 LUT3 53 C?b:a + 79 LUT3 CA C?A:B + 80 LUT4 880F D?c:AB + 81 LUT4 0503 DC?b:a:0:0 + 82 LUT4 E800 D(AB?0:C:C:1) + 83 LUT3 10 abC + 84 LUT3 80 ABC + 85 LUT3 40 aBC + 86 LUT4 0305 DC?a:b:0:0 + 87 LUT4 1700 D(AB?1:c:c:0) + 88 LUT2 8 AB + 89 LUT2 4 aB + 90 LUT4 8000 ABCD + 91 LUT4 8000 ABCD + 92 LUT4 0001 abcd + 93 LUT4 0001 abcd + 94 LUT4 0001 abcd + 95 LUT4 0001 abcd + 96 LUT2 8 AB + 97 LUT4 0001 abcd + 98 LUT4 0001 abcd + 99 LUT4 0001 abcd + 100 LUT4 0001 abcd + 101 LUT3 10 abC + 102 LUT3 01 abc + 103 LUT3 40 aBC + 104 LUT4 000E cd/ab\ + 105 LUT3 E0 C/ab\ + 106 LUT4 FF70 (C/AB\)+D + 107 LUT3 53 C?b:a + 108 LUT3 CA C?A:B + 109 LUT4 000E cd/ab\ + 110 LUT3 E0 C/ab\ + 111 LUT4 FF70 (C/AB\)+D + 112 LUT3 53 C?b:a + 113 LUT3 CA C?A:B + 114 LUT4 000E cd/ab\ + 115 LUT3 E0 C/ab\ + 116 LUT4 FF70 (C/AB\)+D + 117 LUT3 53 C?b:a + 118 LUT3 CA C?A:B + 119 LUT4 000E cd/ab\ + 120 LUT3 E0 C/ab\ + 121 LUT4 FF70 (C/AB\)+D + 122 LUT3 53 C?b:a + 123 LUT3 CA C?A:B + 124 LUT4 000E cd/ab\ + 125 LUT3 E0 C/ab\ + 126 LUT4 FF70 (C/AB\)+D + 127 LUT3 53 C?b:a + 128 LUT3 CA C?A:B + 129 LUT4 000E cd/ab\ + 130 LUT3 E0 C/ab\ + 131 LUT4 FF70 (C/AB\)+D + 132 LUT3 53 C?b:a + 133 LUT3 CA C?A:B + 134 LUT4 000E cd/ab\ + 135 LUT3 E0 C/ab\ + 136 LUT4 FF70 (C/AB\)+D + 137 LUT3 53 C?b:a + 138 LUT3 CA C?A:B + 139 LUT4 000E cd/ab\ + 140 LUT3 E0 C/ab\ + 141 LUT4 FF70 (C/AB\)+D + 142 LUT3 53 C?b:a + 143 LUT3 CA C?A:B + 144 LUT4 000E cd/ab\ + 145 LUT3 E0 C/ab\ + 146 LUT4 FF70 (C/AB\)+D + 147 LUT3 53 C?b:a + 148 LUT3 CA C?A:B + 149 LUT4 000E cd/ab\ + 150 LUT3 E0 C/ab\ + 151 LUT4 FF70 (C/AB\)+D + 152 LUT3 53 C?b:a + 153 LUT3 CA C?A:B + 154 LUT4 000E cd/ab\ + 155 LUT3 E0 C/ab\ + 156 LUT4 FF70 (C/AB\)+D + 157 LUT3 53 C?b:a + 158 LUT3 CA C?A:B + 159 LUT4 000E cd/ab\ + 160 LUT3 E0 C/ab\ + 161 LUT4 FF70 (C/AB\)+D + 162 LUT3 53 C?b:a + 163 LUT3 CA C?A:B + 164 LUT4 000E cd/ab\ + 165 LUT3 E0 C/ab\ + 166 LUT4 FF70 (C/AB\)+D + 167 LUT3 53 C?b:a + 168 LUT3 CA C?A:B + 169 LUT4 000E cd/ab\ + 170 LUT3 E0 C/ab\ + 171 LUT4 FF70 (C/AB\)+D + 172 LUT3 53 C?b:a + 173 LUT3 CA C?A:B + 174 LUT4 000E cd/ab\ + 175 LUT3 E0 C/ab\ + 176 LUT4 FF70 (C/AB\)+D + 177 LUT3 53 C?b:a + 178 LUT3 CA C?A:B + 179 LUT4 000E cd/ab\ + 180 LUT3 E0 C/ab\ + 181 LUT4 FF70 (C/AB\)+D + 182 LUT3 53 C?b:a + 183 LUT3 CA C?A:B + 184 LUT4 000E cd/ab\ + 185 LUT3 E0 C/ab\ + 186 LUT4 FF70 (C/AB\)+D + 187 LUT3 53 C?b:a + 188 LUT3 CA C?A:B + 189 LUT4 000E cd/ab\ + 190 LUT3 E0 C/ab\ + 191 LUT4 FF70 (C/AB\)+D + 192 LUT3 53 C?b:a + 193 LUT3 CA C?A:B + 194 LUT4 000E cd/ab\ + 195 LUT3 E0 C/ab\ + 196 LUT4 FF70 (C/AB\)+D + 197 LUT3 53 C?b:a + 198 LUT3 CA C?A:B + 199 LUT4 000E cd/ab\ + 200 LUT3 E0 C/ab\ + 201 LUT4 FF70 (C/AB\)+D + 202 LUT3 53 C?b:a + 203 LUT3 CA C?A:B + 204 LUT4 000E cd/ab\ + 205 LUT3 E0 C/ab\ + 206 LUT4 FF70 (C/AB\)+D + 207 LUT3 53 C?b:a + 208 LUT3 CA C?A:B + 209 LUT4 000E cd/ab\ + 210 LUT3 E0 C/ab\ + 211 LUT4 FF70 (C/AB\)+D + 212 LUT3 53 C?b:a + 213 LUT3 CA C?A:B + 214 LUT4 000E cd/ab\ + 215 LUT3 E0 C/ab\ + 216 LUT3 CA C?A:B + 217 LUT3 CA C?A:B + 218 LUT3 CA C?A:B + 219 LUT3 CA C?A:B + 220 LUT3 CA C?A:B + 221 LUT3 CA C?A:B + 222 LUT3 CA C?A:B + 223 LUT3 CA C?A:B + 224 LUT3 CA C?A:B + 225 LUT3 CA C?A:B + 226 LUT3 CA C?A:B + 227 LUT3 CA C?A:B + 228 LUT3 CA C?A:B + 229 LUT3 CA C?A:B + 230 LUT3 CA C?A:B + 231 LUT3 CA C?A:B + 232 LUT4 CCCA DC?A:B:B:B + 233 LUT4 CCCA DC?A:B:B:B + 234 LUT4 CCCA DC?A:B:B:B + 235 LUT4 CCCA DC?A:B:B:B + 236 LUT4 CCCA DC?A:B:B:B + 237 LUT4 CCCA DC?A:B:B:B + 238 LUT4 CCCA DC?A:B:B:B + 239 LUT4 CCCA DC?A:B:B:B + 240 LUT3 40 aBC + 241 LUT4 F8FF (AB)+C+d + 242 LUT3 AC c?A:B + 243 LUT3 AC c?A:B + 244 LUT3 AC c?A:B + 245 LUT3 AC c?A:B + 246 LUT3 AC c?A:B + 247 LUT2 4 aB + 248 LUT2 4 aB + 249 LUT2 4 aB + 250 LUT2 4 aB + 251 LUT2 4 aB + 252 LUT2 4 aB + 253 LUT2 4 aB + 254 LUT2 4 aB + 255 LUT2 4 aB + 256 LUT2 4 aB + 257 LUT2 4 aB + 258 LUT2 4 aB + 259 LUT2 4 aB + 260 LUT2 4 aB + 261 LUT2 4 aB + 262 LUT2 4 aB + 263 LUT2 4 aB + 264 LUT2 4 aB + 265 LUT2 4 aB + 266 LUT2 4 aB + 267 LUT2 4 aB + 268 LUT2 4 aB + 269 LUT2 4 aB + 270 LUT4 B0FF (C/aB\)+d + 271 LUT4 1F00 ((ab)+c)D + 272 LUT3 35 c?b:a + 273 LUT3 35 c?b:a + 274 LUT3 35 c?b:a + 275 LUT3 35 c?b:a + 276 LUT3 CA C?A:B + 277 LUT3 CA C?A:B + 278 LUT3 35 c?b:a + 279 LUT3 35 c?b:a + 280 LUT3 CA C?A:B + 281 LUT3 35 c?b:a + 282 LUT3 35 c?b:a + 283 LUT3 CA C?A:B + 284 LUT3 CA C?A:B + 285 LUT3 CA C?A:B + 286 LUT3 35 c?b:a + 287 LUT3 35 c?b:a + 288 LUT3 CA C?A:B + 289 LUT3 35 c?b:a + 290 LUT3 35 c?b:a + 291 LUT3 CA C?A:B + 292 LUT3 CA C?A:B + 293 LUT3 35 c?b:a + 294 LUT3 35 c?b:a + 295 LUT3 CA C?A:B + 296 LUT3 35 c?b:a + 297 LUT3 35 c?b:a + 298 LUT3 0E c/ab\ + 299 LUT4 3500 D(c?b:a) + 300 LUT3 CA C?A:B + 301 LUT3 CA C?A:B + 302 LUT3 35 c?b:a + 303 LUT3 35 c?b:a + 304 LUT3 CA C?A:B + 305 LUT3 35 c?b:a + 306 LUT3 35 c?b:a + 307 LUT3 CA C?A:B + 308 LUT3 CA C?A:B + 309 LUT3 35 c?b:a + 310 LUT3 35 c?b:a + 311 LUT3 CA C?A:B + 312 LUT3 35 c?b:a + 313 LUT3 35 c?b:a + 314 LUT3 0E c/ab\ + 315 LUT4 3500 D(c?b:a) + 316 LUT3 CA C?A:B + 317 LUT3 35 c?b:a + 318 LUT3 35 c?b:a + 319 LUT3 CA C?A:B + 320 LUT3 35 c?b:a + 321 LUT3 35 c?b:a + 322 LUT3 0E c/ab\ + 323 LUT4 3500 D(c?b:a) + 324 LUT3 35 c?b:a + 325 LUT3 35 c?b:a + 326 LUT4 0305 DC?a:b:0:0 + 327 LUT3 35 c?b:a + 328 LUT3 35 c?b:a + 329 LUT4 0D00 cD/Ab\ + 330 LUT3 C5 C?a:B + 331 LUT4 A333 DC?b:b:b:A + 332 LUT4 A333 DC?b:b:b:A + 333 LUT2 8 AB + 334 LUT4 CA00 D(C?A:B) + 335 LUT2 8 AB + 336 LUT4 EC0E DC?/ab\:B:0:/ab\ + 337 LUT3 70 C/AB\ + 338 LUT4 001F ((ab)+c)d + 339 LUT4 4F00 ((aB)+c)D + 340 LUT2 4 aB + 341 LUT3 07 c/AB\ + 342 LUT4 0A0C DC?B:A:0:0 + 343 LUT3 F4 (aB)+C + 344 LUT3 35 c?b:a + 345 LUT3 10 abC + 346 LUT4 1000 abCD + 347 LUT3 80 ABC + 348 LUT4 0100 abcD + 349 LUT3 17 AB?1:c:c:0 + 350 LUT3 10 abC + 351 LUT4 B0FF (C/aB\)+d + 352 LUT3 10 abC + 353 LUT3 CA C?A:B + 354 LUT3 CA C?A:B + 355 LUT3 35 c?b:a + 356 LUT3 CA C?A:B + 357 LUT4 0C0A DC?A:B:0:0 + 358 LUT3 CA C?A:B + 359 LUT3 CA C?A:B + 360 LUT3 CA C?A:B + 361 LUT3 CA C?A:B + 362 LUT3 CA C?A:B + 363 LUT3 CA C?A:B + 364 LUT3 01 abc + 365 LUT3 E0 C/ab\ + 366 LUT4 3500 D(c?b:a) + 367 LUT3 CA C?A:B + 368 LUT3 CA C?A:B + 369 LUT4 0305 DC?a:b:0:0 + 370 LUT3 CA C?A:B + 371 LUT3 CA C?A:B + 372 LUT3 0E c/ab\ + 373 LUT4 3500 D(c?b:a) + 374 LUT3 CA C?A:B + 375 LUT3 CA C?A:B + 376 LUT3 0E c/ab\ + 377 LUT4 3500 D(c?b:a) + 378 LUT4 030A DC?A:b:0:0 + 379 LUT3 D0 C/Ab\ + 380 LUT4 A333 DC?b:b:b:A + 381 LUT4 A333 DC?b:b:b:A + 382 LUT3 CA C?A:B + 383 LUT4 CA00 D(C?A:B) + 384 LUT2 8 AB + 385 LUT4 7077 /AB\(d+C) + 386 LUT4 0007 cd/AB\ + 387 LUT4 CA00 D(C?A:B) + 388 LUT4 0C0A DC?A:B:0:0 + 389 LUT4 0777 /AB\(d+c) + 390 LUT3 E0 C/ab\ + 391 LUT4 F100 ((ab)+C)D + 392 LUT4 3500 D(c?b:a) + 393 LUT3 CA C?A:B + 394 LUT3 CA C?A:B + 395 LUT3 CA C?A:B + 396 LUT3 CA C?A:B + 397 LUT3 CA C?A:B + 398 LUT3 CA C?A:B + 399 LUT3 0E c/ab\ + 400 LUT4 3500 D(c?b:a) + 401 LUT3 CA C?A:B + 402 LUT3 CA C?A:B + 403 LUT4 00F1 ((ab)+C)d + 404 LUT3 C5 C?a:B + 405 LUT4 3500 D(c?b:a) + 406 LUT3 CA C?A:B + 407 LUT4 F400 ((aB)+C)D + 408 LUT3 C5 C?a:B + 409 LUT4 110F D?c:ab + 410 LUT2 4 aB + 411 LUT4 CA00 D(C?A:B) + 412 LUT3 70 C/AB\ + 413 LUT4 4F00 ((aB)+c)D + 414 LUT4 0777 /AB\(d+c) + 415 LUT4 0C0A DC?A:B:0:0 + 416 LUT4 7077 /AB\(d+C) + 417 LUT3 35 c?b:a + 418 LUT4 11F0 D?C:ab + 419 LUT4 0305 DC?a:b:0:0 + 420 LUT3 CA C?A:B + 421 LUT3 CA C?A:B + 422 LUT4 3500 D(c?b:a) + 423 LUT3 AC c?A:B + 424 LUT3 CA C?A:B + 425 LUT4 11F0 D?C:ab + 426 LUT4 3500 D(c?b:a) + 427 LUT4 0305 DC?a:b:0:0 + 428 LUT4 11F0 D?C:ab + 429 LUT4 3500 D(c?b:a) + 430 LUT4 0305 DC?a:b:0:0 + 431 LUT4 A333 DC?b:b:b:A + 432 LUT4 110F D?c:ab + 433 LUT4 CA00 D(C?A:B) + 434 LUT3 70 C/AB\ + 435 LUT3 B0 C/aB\ + 436 LUT4 0007 cd/AB\ + 437 LUT4 CA00 D(C?A:B) + 438 LUT4 0C0A DC?A:B:0:0 + 439 LUT4 0777 /AB\(d+c) + 440 LUT3 4F (aB)+c + 441 LUT4 0D00 cD/Ab\ + 442 LUT4 F400 ((aB)+C)D + 443 LUT3 C5 C?a:B + 444 LUT4 11F0 D?C:ab + 445 LUT4 3500 D(c?b:a) + 446 LUT4 0305 DC?a:b:0:0 + 447 LUT4 11F0 D?C:ab + 448 LUT4 3500 D(c?b:a) + 449 LUT4 0305 DC?a:b:0:0 + 450 LUT4 000D cd/Ab\ + 451 LUT4 EC0E DC?/ab\:B:0:/ab\ + 452 LUT3 40 aBC + 453 LUT3 35 c?b:a + 454 LUT3 70 C/AB\ + 455 LUT3 B0 C/aB\ + 456 LUT4 0007 cd/AB\ + 457 LUT4 CA00 D(C?A:B) + 458 LUT4 0C0A DC?A:B:0:0 + 459 LUT4 0777 /AB\(d+c) + 460 LUT4 EE0F D?c:/ab\ + 461 LUT4 3500 D(c?b:a) + 462 LUT3 CA C?A:B + 463 LUT3 0E c/ab\ + 464 LUT4 3500 D(c?b:a) + 465 LUT4 0305 DC?a:b:0:0 + 466 LUT4 11F0 D?C:ab + 467 LUT4 3500 D(c?b:a) + 468 LUT4 0305 DC?a:b:0:0 + 469 LUT4 A333 DC?b:b:b:A + 470 LUT3 0E c/ab\ + 471 LUT4 CA00 D(C?A:B) + 472 LUT2 8 AB + 473 LUT4 7077 /AB\(d+C) + 474 LUT4 0007 cd/AB\ + 475 LUT4 CA00 D(C?A:B) + 476 LUT4 0C0A DC?A:B:0:0 + 477 LUT4 0777 /AB\(d+c) + 478 LUT2 8 AB + 479 LUT4 EE0F D?c:/ab\ + 480 LUT4 0305 DC?a:b:0:0 + 481 LUT4 3500 D(c?b:a) + 482 LUT4 11F0 D?C:ab + 483 LUT4 3500 D(c?b:a) + 484 LUT4 0305 DC?a:b:0:0 + 485 LUT4 F400 ((aB)+C)D + 486 LUT4 110F D?c:ab + 487 LUT4 CA00 D(C?A:B) + 488 LUT4 0B00 cD/aB\ + 489 LUT4 0007 cd/AB\ + 490 LUT4 CA00 D(C?A:B) + 491 LUT4 0C0A DC?A:B:0:0 + 492 LUT4 0777 /AB\(d+c) + 493 LUT2 8 AB + 494 LUT4 F400 ((aB)+C)D + 495 LUT4 110F D?c:ab + 496 LUT4 11F0 D?C:ab + 497 LUT4 5300 D(C?b:a) + 498 LUT4 0305 DC?a:b:0:0 + 499 LUT3 CA C?A:B + 500 LUT4 11F0 D?C:ab + 501 LUT3 C5 C?a:B + 502 LUT4 3500 D(c?b:a) + 503 LUT3 0E c/ab\ + 504 LUT4 CA00 D(C?A:B) + 505 LUT3 70 C/AB\ + 506 LUT4 8F00 ((AB)+c)D + 507 LUT4 0777 /AB\(d+c) + 508 LUT4 B0BB /aB\(d+C) + 509 LUT3 35 c?b:a + 510 LUT3 01 abc + 511 LUT3 35 c?b:a + 512 LUT4 0FBB D?/aB\:c + 513 LUT4 B0FF (C/aB\)+d + 514 LUT4 0B00 cD/aB\ + 515 LUT4 CA00 D(C?A:B) + 516 LUT3 CA C?A:B + 517 LUT3 C5 C?a:B + 518 LUT3 35 c?b:a + 519 LUT3 70 C/AB\ + 520 LUT4 4F00 ((aB)+c)D + 521 LUT2 4 aB + 522 LUT4 0777 /AB\(d+c) + 523 LUT4 0FBB D?/aB\:c + 524 LUT2 4 aB + 525 LUT4 11F0 D?C:ab + 526 LUT3 0E c/ab\ + 527 LUT4 3500 D(c?b:a) + 528 LUT4 F400 ((aB)+C)D + 529 LUT4 CA00 D(C?A:B) + 530 LUT4 0D00 cD/Ab\ + 531 LUT4 0007 cd/AB\ + 532 LUT4 CA00 D(C?A:B) + 533 LUT2 8 AB + 534 LUT4 0777 /AB\(d+c) + 535 LUT4 0B00 cD/aB\ + 536 LUT3 C5 C?a:B + 537 LUT4 CA00 D(C?A:B) + 538 LUT3 CA C?A:B + 539 LUT4 F400 ((aB)+C)D + 540 LUT4 CA00 D(C?A:B) + 541 LUT4 4F00 ((aB)+c)D + 542 LUT3 70 C/AB\ + 543 LUT4 0777 /AB\(d+c) + 544 LUT4 0FBB D?/aB\:c + 545 LUT4 0D00 cD/Ab\ + 546 LUT4 3500 D(c?b:a) + 547 LUT4 F100 ((ab)+C)D + 548 LUT4 0C05 DC?a:B:0:0 + 549 LUT4 F400 ((aB)+C)D + 550 LUT4 CA00 D(C?A:B) + 551 LUT4 0007 cd/AB\ + 552 LUT4 CA00 D(C?A:B) + 553 LUT3 70 C/AB\ + 554 LUT4 0777 /AB\(d+c) + 555 LUT2 4 aB + 556 LUT3 C5 C?a:B + 557 LUT4 0D00 cD/Ab\ + 558 LUT4 3500 D(c?b:a) + 559 LUT4 F100 ((ab)+C)D + 560 LUT4 0C05 DC?a:B:0:0 + 561 LUT4 CA00 D(C?A:B) + 562 LUT4 7000 CD/AB\ + 563 LUT4 7077 /AB\(d+C) + 564 LUT4 0007 cd/AB\ + 565 LUT4 CA00 D(C?A:B) + 566 LUT4 0777 /AB\(d+c) + 567 LUT4 4000 aBCD + 568 LUT3 4F (aB)+c + 569 LUT4 0D00 cD/Ab\ + 570 LUT4 0D00 cD/Ab\ + 571 LUT3 0E c/ab\ + 572 LUT4 0C05 DC?a:B:0:0 + 573 LUT4 1F00 ((ab)+c)D + 574 LUT4 001F ((ab)+c)d + 575 LUT4 CA00 D(C?A:B) + 576 LUT4 7000 CD/AB\ + 577 LUT4 7077 /AB\(d+C) + 578 LUT4 0007 cd/AB\ + 579 LUT4 CA00 D(C?A:B) + 580 LUT4 0777 /AB\(d+c) + 581 LUT3 4F (aB)+c + 582 LUT4 0D00 cD/Ab\ + 583 LUT4 0D00 cD/Ab\ + 584 LUT4 3500 D(c?b:a) + 585 LUT4 F100 ((ab)+C)D + 586 LUT4 0C05 DC?a:B:0:0 + 587 LUT4 001F ((ab)+c)d + 588 LUT4 CA00 D(C?A:B) + 589 LUT4 D000 CD/Ab\ + 590 LUT4 0007 cd/AB\ + 591 LUT4 CA00 D(C?A:B) + 592 LUT4 0777 /AB\(d+c) + 593 LUT4 0777 /AB\(d+c) + 594 LUT3 4F (aB)+c + 595 LUT4 0D00 cD/Ab\ + 596 LUT4 0D00 cD/Ab\ + 597 LUT4 3500 D(c?b:a) + 598 LUT4 F100 ((ab)+C)D + 599 LUT2 4 aB + 600 LUT4 001F ((ab)+c)d + 601 LUT4 CA00 D(C?A:B) + 602 LUT3 40 aBC + 603 LUT3 D0 C/Ab\ + 604 LUT4 0FBB D?/aB\:c + 605 LUT4 0777 /AB\(d+c) + 606 LUT4 0777 /AB\(d+c) + 607 LUT2 4 aB + 608 LUT4 0D00 cD/Ab\ + 609 LUT4 CA00 D(C?A:B) + 610 LUT3 40 aBC + 611 LUT4 F800 ((AB)+C)D + 612 LUT3 01 abc + 613 LUT3 CA C?A:B + 614 LUT4 0777 /AB\(d+c) + 615 LUT4 0777 /AB\(d+c) + 616 LUT4 B0FF (C/aB\)+d + 617 LUT2 4 aB + 618 LUT4 0D00 cD/Ab\ + 619 LUT3 F4 (aB)+C + 620 LUT4 EC0E DC?/ab\:B:0:/ab\ + 621 LUT4 00BF ((/aB\)+c)d + 622 LUT4 CA00 D(C?A:B) + 623 LUT3 70 C/AB\ + 624 LUT4 0700 cD/AB\ + 625 LUT4 F800 ((AB)+C)D + 626 LUT4 0777 /AB\(d+c) + 627 LUT2 4 aB + 628 LUT4 0D00 cD/Ab\ + 629 LUT4 CA00 D(C?A:B) + 630 LUT3 70 C/AB\ + 631 LUT4 0700 cD/AB\ + 632 LUT4 F800 ((AB)+C)D + 633 LUT4 0777 /AB\(d+c) + 634 LUT2 4 aB + 635 LUT4 0D00 cD/Ab\ + 636 LUT4 CA00 D(C?A:B) + 637 LUT3 70 C/AB\ + 638 LUT4 0700 cD/AB\ + 639 LUT4 F800 ((AB)+C)D + 640 LUT4 0777 /AB\(d+c) + 641 LUT4 F8FF (AB)+C+d + 642 LUT4 0D00 cD/Ab\ + 643 LUT4 F400 ((aB)+C)D + 644 LUT4 CA00 D(C?A:B) + 645 LUT4 0700 cD/AB\ + 646 LUT4 F800 ((AB)+C)D + 647 LUT4 0777 /AB\(d+c) + 648 LUT4 0B00 cD/aB\ + 649 LUT4 F400 ((aB)+C)D + 650 LUT4 CA00 D(C?A:B) + 651 LUT3 40 aBC + 652 LUT4 F800 ((AB)+C)D + 653 LUT4 0777 /AB\(d+c) + 654 LUT4 0777 /AB\(d+c) + 655 LUT4 2FFF (Ab)+c+d + 656 LUT4 0D00 cD/Ab\ + 657 LUT4 F400 ((aB)+C)D + 658 LUT4 CA00 D(C?A:B) + 659 LUT3 07 c/AB\ + 660 LUT4 F800 ((AB)+C)D + 661 LUT4 0007 cd/AB\ + 662 LUT2 8 AB + 663 LUT2 8 AB + 664 LUT4 0B00 cD/aB\ + 665 LUT4 F400 ((aB)+C)D + 666 LUT4 CA00 D(C?A:B) + 667 LUT3 70 C/AB\ + 668 LUT4 0700 cD/AB\ + 669 LUT4 F800 ((AB)+C)D + 670 LUT4 0777 /AB\(d+c) + 671 LUT4 F2FF (Ab)+C+d + 672 LUT4 0D00 cD/Ab\ + 673 LUT4 F400 ((aB)+C)D + 674 LUT4 CA00 D(C?A:B) + 675 LUT4 F800 ((AB)+C)D + 676 LUT4 0777 /AB\(d+c) + 677 LUT4 F2FF (Ab)+C+d + 678 LUT4 0700 cD/AB\ + 679 LUT4 F400 ((aB)+C)D + 680 LUT4 CA00 D(C?A:B) + 681 LUT4 F800 ((AB)+C)D + 682 LUT4 0777 /AB\(d+c) + 683 LUT4 B0FF (C/aB\)+d + 684 LUT2 8 AB + 685 LUT4 0D00 cD/Ab\ + 686 LUT3 0D c/Ab\ + 687 LUT4 EC0E DC?/ab\:B:0:/ab\ + 688 LUT3 35 c?b:a + 689 LUT3 40 aBC + 690 LUT2 4 aB + 691 LUT4 F800 ((AB)+C)D + 692 LUT4 0777 /AB\(d+c) + 693 LUT4 B0FF (C/aB\)+d + 694 LUT4 0D00 cD/Ab\ + 695 LUT4 EC0E DC?/ab\:B:0:/ab\ + 696 LUT4 00BF ((/aB\)+c)d + 697 LUT4 CA00 D(C?A:B) + 698 LUT4 F400 ((aB)+C)D + 699 LUT2 4 aB + 700 LUT4 F800 ((AB)+C)D + 701 LUT4 0777 /AB\(d+c) + 702 LUT3 EF /ab\+c + 703 LUT4 4F00 ((aB)+c)D + 704 LUT4 0D00 cD/Ab\ + 705 LUT3 0D c/Ab\ + 706 LUT4 EC0E DC?/ab\:B:0:/ab\ + 707 LUT3 35 c?b:a + 708 LUT3 40 aBC + 709 LUT4 F800 ((AB)+C)D + 710 LUT4 0777 /AB\(d+c) + 711 LUT4 B0FF (C/aB\)+d + 712 LUT4 1F00 ((ab)+c)D + 713 LUT4 CA00 D(C?A:B) + 714 LUT4 F400 ((aB)+C)D + 715 LUT2 4 aB + 716 LUT4 F800 ((AB)+C)D + 717 LUT4 0777 /AB\(d+c) + 718 LUT3 4F (aB)+c + 719 LUT4 EF00 ((/ab\)+c)D + 720 LUT4 0D00 cD/Ab\ + 721 LUT4 EC0E DC?/ab\:B:0:/ab\ + 722 LUT4 00BF ((/aB\)+c)d + 723 LUT4 CA00 D(C?A:B) + 724 LUT4 0007 cd/AB\ + 725 LUT4 F800 ((AB)+C)D + 726 LUT4 4000 aBCD + 727 LUT4 B0FF (C/aB\)+d + 728 LUT3 E0 C/ab\ + 729 LUT4 0D00 cD/Ab\ + 730 LUT4 4F00 ((aB)+c)D + 731 LUT4 35F3 DC?b:a:1:b + 732 LUT4 CA00 D(C?A:B) + 733 LUT2 4 aB + 734 LUT4 F800 ((AB)+C)D + 735 LUT4 0777 /AB\(d+c) + 736 LUT4 FFF4 (aB)+C+D + 737 LUT4 0B00 cD/aB\ + 738 LUT3 80 ABC + 739 LUT4 0B00 cD/aB\ + 740 LUT4 0E00 cD/ab\ + 741 LUT4 0E00 cD/ab\ + 742 LUT1 1 a deleted + 743 LUT1 1 a deleted + 744 LUT1 1 a deleted + 745 LUT1 1 a deleted + 746 LUT1 1 a deleted + 747 LUT1 1 a deleted + 748 LUT1 1 a deleted + 749 LUT1 1 a deleted + 750 LUT1 1 a deleted + 751 LUT1 1 a deleted + 752 LUT1 1 a deleted + 753 LUT1 1 a deleted + 754 LUT1 1 a deleted + 755 LUT1 1 a deleted + 756 LUT1 1 a deleted + 757 LUT1 1 a deleted + 758 LUT1 1 a deleted + 759 LUT1 1 a deleted + 760 LUT1 1 a deleted + 761 LUT1 1 a deleted + 762 LUT1 1 a deleted + 763 LUT1 1 a deleted + 764 LUT1 1 a deleted + 765 LUT1 1 a deleted + 766 LUT1 1 a deleted + 767 LUT1 1 a deleted + 768 LUT1 1 a deleted + 769 LUT1 1 a deleted + 770 LUT1 1 a deleted + 771 LUT1 1 a deleted + 772 LUT1 1 a deleted + 773 LUT1 1 a deleted + 774 LUT4 CFA0 DC?0:1:A:B + 775 LUT4 05F3 DC?b:a:1:0 + 776 LUT3 C5 C?a:B + 777 LUT4 C500 D(C?a:B) + 778 LUT4 44F0 D?C:aB + 779 LUT4 007F ((/AB\)+c)d + 780 LUT4 3FA0 DC?0:1:A:b + 781 LUT4 FC0A DC?A:B:0:1 + 782 LUT4 F800 ((AB)+C)D + 783 LUT4 3A03 DC?b:A:0:b + 784 LUT3 07 c/AB\ + 785 LUT4 3A03 DC?b:A:0:b + 786 LUT4 0007 cd/AB\ + 787 LUT4 B0FF (C/aB\)+d + 788 LUT4 3A03 DC?b:A:0:b + 789 LUT4 3A03 DC?b:A:0:b + 790 LUT4 3A03 DC?b:A:0:b + 791 LUT4 0007 cd/AB\ + 792 LUT4 B0FF (C/aB\)+d + 793 LUT4 3A03 DC?b:A:0:b + 794 LUT4 80FF (ABC)+d + 795 LUT4 000B cd/aB\ + 796 LUT4 F0BB D?/aB\:C + 797 LUT4 3A03 DC?b:A:0:b + 798 LUT4 0BBB /aB\(d+c) + 799 LUT3 B0 C/aB\ + 800 LUT4 3A03 DC?b:A:0:b + 801 LUT4 0007 cd/AB\ + 802 LUT4 B0FF (C/aB\)+d + 803 LUT4 3A03 DC?b:A:0:b + 804 LUT4 0007 cd/AB\ + 805 LUT4 B0FF (C/aB\)+d + 806 LUT4 3A03 DC?b:A:0:b + 807 LUT4 0007 cd/AB\ + 808 LUT3 B0 C/aB\ + 809 LUT4 B0FF (C/aB\)+d + 810 LUT4 3A03 DC?b:A:0:b + 811 LUT4 0007 cd/AB\ + 812 LUT4 B0FF (C/aB\)+d + 813 LUT4 3A03 DC?b:A:0:b + 814 LUT3 07 c/AB\ + 815 LUT4 3A03 DC?b:A:0:b + 816 LUT3 07 c/AB\ + 817 LUT4 3A03 DC?b:A:0:b + 818 LUT3 07 c/AB\ + 819 LUT4 3A03 DC?b:A:0:b + 820 LUT4 0007 cd/AB\ + 821 LUT4 B0FF (C/aB\)+d + 822 LUT4 3A03 DC?b:A:0:b + 823 LUT4 0007 cd/AB\ + 824 LUT4 B0FF (C/aB\)+d + 825 LUT4 3A03 DC?b:A:0:b + 826 LUT4 0007 cd/AB\ + 827 LUT4 B0FF (C/aB\)+d + 828 LUT4 3A03 DC?b:A:0:b + 829 LUT3 07 c/AB\ + 830 LUT4 EF00 ((/ab\)+c)D + 831 LUT4 3A03 DC?b:A:0:b + 832 LUT4 0007 cd/AB\ + 833 LUT4 B0FF (C/aB\)+d + 834 LUT4 3A03 DC?b:A:0:b + 835 LUT3 07 c/AB\ + 836 LUT4 3A03 DC?b:A:0:b + 837 LUT4 0007 cd/AB\ + 838 LUT4 B0FF (C/aB\)+d + 839 LUT4 3A03 DC?b:A:0:b + 840 LUT3 07 c/AB\ + 841 LUT4 3A03 DC?b:A:0:b + 842 LUT3 07 c/AB\ + 843 LUT4 3A03 DC?b:A:0:b + 844 LUT3 07 c/AB\ + 845 LUT4 0BFF (c/aB\)+d + 846 LUT3 0B c/aB\ + 847 LUT4 70FF (C/AB\)+d + 848 LUT4 07FF (c/AB\)+d + 849 LUT3 0B c/aB\ + 850 LUT4 70FF (C/AB\)+d diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/net/FemtoRV32_synth.v b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/net/FemtoRV32_synth.v new file mode 100644 index 0000000000000000000000000000000000000000..33dc6e49fc73cb9751eda7cfc4ed535231b0cbe5 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/2.build/net/FemtoRV32_synth.v @@ -0,0 +1,10939 @@ +/* Generated by Yosys 0.42+15 (git sha1 dd9624444, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module FemtoRV32(clk, mem_addr, mem_wdata, mem_wmask, mem_rdata, mem_rstrb, mem_rbusy, mem_wbusy, reset); + wire [31:0] _0000_; + wire _0001_; + wire _0002_; + wire _0003_; + wire _0004_; + wire _0005_; + wire _0006_; + wire _0007_; + wire _0008_; + wire _0009_; + wire _0010_; + wire _0011_; + wire _0012_; + wire _0013_; + wire _0014_; + wire _0015_; + wire _0016_; + wire _0017_; + wire _0018_; + wire _0019_; + wire _0020_; + wire _0021_; + wire _0022_; + wire _0023_; + wire _0024_; + wire _0025_; + wire _0026_; + wire _0027_; + wire _0028_; + wire _0029_; + wire _0030_; + wire _0031_; + wire _0032_; + wire _0033_; + wire _0034_; + wire _0035_; + wire _0036_; + wire _0037_; + wire _0038_; + wire _0039_; + wire _0040_; + wire _0041_; + wire _0042_; + wire _0043_; + wire _0044_; + wire _0045_; + wire _0046_; + wire _0047_; + wire _0048_; + wire _0049_; + wire _0050_; + wire _0051_; + wire _0052_; + wire _0053_; + wire _0054_; + wire _0055_; + wire _0056_; + wire _0057_; + wire _0058_; + wire _0059_; + wire _0060_; + wire _0061_; + wire _0062_; + wire _0063_; + wire _0064_; + wire _0065_; + wire _0066_; + wire _0067_; + wire _0068_; + wire _0069_; + wire _0070_; + wire _0071_; + wire _0072_; + wire _0073_; + wire _0074_; + wire _0075_; + wire [31:0] _0076_; + wire [31:0] _0077_; + wire [31:0] _0078_; + wire [23:0] _0079_; + wire [23:0] _0080_; + wire [23:0] _0081_; + wire [21:0] _0082_; + wire [21:0] _0083_; + wire [22:0] _0084_; + wire [22:0] _0085_; + wire [22:0] _0086_; + wire [31:0] _0087_; + wire [31:0] _0088_; + wire [32:0] _0089_; + wire [32:0] _0090_; + wire [32:0] _0091_; + wire _0092_; + wire [39:0] _0093_; + wire [39:0] _0094_; + wire _0095_; + wire [11:0] _0096_; + wire [3:0] _0097_; + wire [2:0] _0098_; + wire [3:0] _0099_; + wire [2:0] _0100_; + wire [2:0] _0101_; + wire [2:0] _0102_; + wire [3:0] _0103_; + wire [2:0] _0104_; + wire [2:0] _0105_; + wire [2:0] _0106_; + wire [3:0] _0107_; + wire [2:0] _0108_; + wire [3:0] _0109_; + wire [3:0] _0110_; + wire [2:0] _0111_; + wire [2:0] _0112_; + wire [3:0] _0113_; + wire [2:0] _0114_; + wire [2:0] _0115_; + wire [3:0] _0116_; + wire [3:0] _0117_; + wire [3:0] _0118_; + wire [2:0] _0119_; + wire [2:0] _0120_; + wire [3:0] _0121_; + wire [2:0] _0122_; + wire [2:0] _0123_; + wire [3:0] _0124_; + wire [2:0] _0125_; + wire [2:0] _0126_; + wire [2:0] _0127_; + wire [2:0] _0128_; + wire [2:0] _0129_; + wire [2:0] _0130_; + wire [2:0] _0131_; + wire [3:0] _0132_; + wire [3:0] _0133_; + wire [3:0] _0134_; + wire [3:0] _0135_; + wire [3:0] _0136_; + wire [2:0] _0137_; + wire [2:0] _0138_; + wire [3:0] _0139_; + wire [3:0] _0140_; + wire [3:0] _0141_; + wire [3:0] _0142_; + wire [3:0] _0143_; + wire [3:0] _0144_; + wire [3:0] _0145_; + wire [3:0] _0146_; + wire [2:0] _0147_; + wire [1:0] _0148_; + wire [2:0] _0149_; + wire [3:0] _0150_; + wire [2:0] _0151_; + wire [3:0] _0152_; + wire [3:0] _0153_; + wire [3:0] _0154_; + wire [3:0] _0155_; + wire [3:0] _0156_; + wire [1:0] _0157_; + wire [3:0] _0158_; + wire [2:0] _0159_; + wire [2:0] _0160_; + wire [2:0] _0161_; + wire [3:0] _0162_; + wire [3:0] _0163_; + wire [3:0] _0164_; + wire [2:0] _0165_; + wire [2:0] _0166_; + wire [2:0] _0167_; + wire [2:0] _0168_; + wire [3:0] _0169_; + wire [3:0] _0170_; + wire [2:0] _0171_; + wire [2:0] _0172_; + wire [2:0] _0173_; + wire [2:0] _0174_; + wire [2:0] _0175_; + wire [2:0] _0176_; + wire [2:0] _0177_; + wire [3:0] _0178_; + wire [3:0] _0179_; + wire [3:0] _0180_; + wire [3:0] _0181_; + wire [3:0] _0182_; + wire [2:0] _0183_; + wire [3:0] _0184_; + wire [2:0] _0185_; + wire [2:0] _0186_; + wire [2:0] _0187_; + wire [3:0] _0188_; + wire [3:0] _0189_; + wire [3:0] _0190_; + wire [2:0] _0191_; + wire [3:0] _0192_; + wire [3:0] _0193_; + wire [3:0] _0194_; + wire [3:0] _0195_; + wire [3:0] _0196_; + wire [3:0] _0197_; + wire [3:0] _0198_; + wire [2:0] _0199_; + wire [1:0] _0200_; + wire [3:0] _0201_; + wire [3:0] _0202_; + wire [3:0] _0203_; + wire [3:0] _0204_; + wire [3:0] _0205_; + wire [2:0] _0206_; + wire [3:0] _0207_; + wire [1:0] _0208_; + wire [3:0] _0209_; + wire [1:0] _0210_; + wire [3:0] _0211_; + wire [3:0] _0212_; + wire [3:0] _0213_; + wire [3:0] _0214_; + wire [2:0] _0215_; + wire [3:0] _0216_; + wire [1:0] _0217_; + wire [3:0] _0218_; + wire [2:0] _0219_; + wire [2:0] _0220_; + wire [2:0] _0221_; + wire [3:0] _0222_; + wire [3:0] _0223_; + wire [1:0] _0224_; + wire [3:0] _0225_; + wire [3:0] _0226_; + wire [3:0] _0227_; + wire [3:0] _0228_; + wire [2:0] _0229_; + wire [3:0] _0230_; + wire [2:0] _0231_; + wire [3:0] _0232_; + wire [3:0] _0233_; + wire [3:0] _0234_; + wire [2:0] _0235_; + wire [3:0] _0236_; + wire [2:0] _0237_; + wire [3:0] _0238_; + wire [3:0] _0239_; + wire [3:0] _0240_; + wire [3:0] _0241_; + wire [3:0] _0242_; + wire [3:0] _0243_; + wire [3:0] _0244_; + wire [3:0] _0245_; + wire [3:0] _0246_; + wire [2:0] _0247_; + wire [3:0] _0248_; + wire [3:0] _0249_; + wire [1:0] _0250_; + wire [3:0] _0251_; + wire [3:0] _0252_; + wire [2:0] _0253_; + wire [3:0] _0254_; + wire [3:0] _0255_; + wire [3:0] _0256_; + wire [2:0] _0257_; + wire [3:0] _0258_; + wire [3:0] _0259_; + wire [3:0] _0260_; + wire [3:0] _0261_; + wire [3:0] _0262_; + wire [3:0] _0263_; + wire [3:0] _0264_; + wire [2:0] _0265_; + wire [3:0] _0266_; + wire [3:0] _0267_; + wire [1:0] _0268_; + wire [3:0] _0269_; + wire [3:0] _0270_; + wire [3:0] _0271_; + wire [3:0] _0272_; + wire [3:0] _0273_; + wire [2:0] _0274_; + wire [2:0] _0275_; + wire [2:0] _0276_; + wire [3:0] _0277_; + wire [3:0] _0278_; + wire [2:0] _0279_; + wire [3:0] _0280_; + wire [2:0] _0281_; + wire [2:0] _0282_; + wire [3:0] _0283_; + wire [3:0] _0284_; + wire [3:0] _0285_; + wire [3:0] _0286_; + wire [3:0] _0287_; + wire [3:0] _0288_; + wire [2:0] _0289_; + wire [3:0] _0290_; + wire [3:0] _0291_; + wire [3:0] _0292_; + wire [1:0] _0293_; + wire [3:0] _0294_; + wire [3:0] _0295_; + wire [3:0] _0296_; + wire [2:0] _0297_; + wire [3:0] _0298_; + wire [3:0] _0299_; + wire [3:0] _0300_; + wire [3:0] _0301_; + wire [2:0] _0302_; + wire [3:0] _0303_; + wire [2:0] _0304_; + wire [1:0] _0305_; + wire [3:0] _0306_; + wire [3:0] _0307_; + wire [2:0] _0308_; + wire [3:0] _0309_; + wire [3:0] _0310_; + wire [2:0] _0311_; + wire [1:0] _0312_; + wire [3:0] _0313_; + wire [3:0] _0314_; + wire [3:0] _0315_; + wire [3:0] _0316_; + wire [3:0] _0317_; + wire [1:0] _0318_; + wire [2:0] _0319_; + wire [3:0] _0320_; + wire [3:0] _0321_; + wire [3:0] _0322_; + wire [3:0] _0323_; + wire [3:0] _0324_; + wire [3:0] _0325_; + wire [3:0] _0326_; + wire [3:0] _0327_; + wire [2:0] _0328_; + wire [3:0] _0329_; + wire [3:0] _0330_; + wire [3:0] _0331_; + wire [3:0] _0332_; + wire [3:0] _0333_; + wire [3:0] _0334_; + wire [3:0] _0335_; + wire [2:0] _0336_; + wire [3:0] _0337_; + wire [2:0] _0338_; + wire [3:0] _0339_; + wire [1:0] _0340_; + wire [3:0] _0341_; + wire [2:0] _0342_; + wire [2:0] _0343_; + wire [3:0] _0344_; + wire [2:0] _0345_; + wire [3:0] _0346_; + wire [3:0] _0347_; + wire [3:0] _0348_; + wire [2:0] _0349_; + wire [3:0] _0350_; + wire [3:0] _0351_; + wire [3:0] _0352_; + wire [3:0] _0353_; + wire [2:0] _0354_; + wire [2:0] _0355_; + wire [3:0] _0356_; + wire [3:0] _0357_; + wire [2:0] _0358_; + wire [3:0] _0359_; + wire [3:0] _0360_; + wire [3:0] _0361_; + wire [2:0] _0362_; + wire [2:0] _0363_; + wire [3:0] _0364_; + wire [3:0] _0365_; + wire [2:0] _0366_; + wire [3:0] _0367_; + wire [3:0] _0368_; + wire [3:0] _0369_; + wire [1:0] _0370_; + wire [2:0] _0371_; + wire [3:0] _0372_; + wire [3:0] _0373_; + wire [3:0] _0374_; + wire [2:0] _0375_; + wire [3:0] _0376_; + wire [3:0] _0377_; + wire [2:0] _0378_; + wire [3:0] _0379_; + wire [3:0] _0380_; + wire [3:0] _0381_; + wire [1:0] _0382_; + wire [3:0] _0383_; + wire [3:0] _0384_; + wire [3:0] _0385_; + wire [3:0] _0386_; + wire [3:0] _0387_; + wire [2:0] _0388_; + wire [2:0] _0389_; + wire [1:0] _0390_; + wire [2:0] _0391_; + wire [1:0] _0392_; + wire [2:0] _0393_; + wire [1:0] _0394_; + wire [2:0] _0395_; + wire [1:0] _0396_; + wire [2:0] _0397_; + wire [1:0] _0398_; + wire [2:0] _0399_; + wire [1:0] _0400_; + wire [2:0] _0401_; + wire [1:0] _0402_; + wire [2:0] _0403_; + wire [1:0] _0404_; + wire [2:0] _0405_; + wire [1:0] _0406_; + wire [2:0] _0407_; + wire [1:0] _0408_; + wire [2:0] _0409_; + wire [1:0] _0410_; + wire [2:0] _0411_; + wire [1:0] _0412_; + wire [2:0] _0413_; + wire [1:0] _0414_; + wire [2:0] _0415_; + wire [1:0] _0416_; + wire [2:0] _0417_; + wire [1:0] _0418_; + wire [2:0] _0419_; + wire [1:0] _0420_; + wire [2:0] _0421_; + wire [1:0] _0422_; + wire [2:0] _0423_; + wire [1:0] _0424_; + wire [2:0] _0425_; + wire [1:0] _0426_; + wire [2:0] _0427_; + wire [1:0] _0428_; + wire [2:0] _0429_; + wire [1:0] _0430_; + wire [2:0] _0431_; + wire [1:0] _0432_; + wire [2:0] _0433_; + wire [1:0] _0434_; + wire [2:0] _0435_; + wire [3:0] _0436_; + wire [3:0] _0437_; + wire [3:0] _0438_; + wire [3:0] _0439_; + wire [3:0] _0440_; + wire [3:0] _0441_; + wire [3:0] _0442_; + wire [3:0] _0443_; + wire [3:0] _0444_; + wire [3:0] _0445_; + wire [3:0] _0446_; + wire [3:0] _0447_; + wire [3:0] _0448_; + wire [3:0] _0449_; + wire [3:0] _0450_; + wire [3:0] _0451_; + wire [3:0] _0452_; + wire [3:0] _0453_; + wire [3:0] _0454_; + wire [3:0] _0455_; + wire [3:0] _0456_; + wire [3:0] _0457_; + wire [3:0] _0458_; + wire [3:0] _0459_; + wire [3:0] _0460_; + wire [3:0] _0461_; + wire [3:0] _0462_; + wire [3:0] _0463_; + wire [3:0] _0464_; + wire [3:0] _0465_; + wire [3:0] _0466_; + wire [3:0] _0467_; + wire [3:0] _0468_; + wire [2:0] _0469_; + wire [3:0] _0470_; + wire [2:0] _0471_; + wire [31:0] Bimm; + wire [31:0] Iimm; + wire [31:0] Jimm; + wire LTU; + wire [23:0] PC; + wire [23:0] PCplus4; + wire [23:0] PCplusImm; + wire [31:0] aluIn1; + wire [31:0] aluIn2; + wire [32:0] aluMinus; + wire [31:0] aluPlus; + input clk; + wire clk; + wire [31:0] cycles; + wire [31:2] instr; + wire [23:0] loadstore_addr; + output [31:0] mem_addr; + wire [31:0] mem_addr; + input mem_rbusy; + wire mem_rbusy; + input [31:0] mem_rdata; + wire [31:0] mem_rdata; + output mem_rstrb; + wire mem_rstrb; + input mem_wbusy; + wire mem_wbusy; + output [31:0] mem_wdata; + wire [31:0] mem_wdata; + output [3:0] mem_wmask; + wire [3:0] mem_wmask; + input reset; + wire reset; + wire [31:0] rs2; + wire [3:0] state; + wire [31:0] writeBackData; + CC_LUT2 #( + .INIT(4'hb) + ) _0472_ ( + .I0(state[2]), + .I1(_0390_[1]), + .O(_0002_) + ); + CC_LUT4 #( + .INIT(16'h07ff) + ) _0473_ ( + .I0(state[1]), + .I1(_0096_[9]), + .I2(_0436_[2]), + .I3(_0390_[1]), + .O(_0003_) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0474_ ( + .I0(_0435_[0]), + .I1(_0096_[9]), + .I2(state[3]), + .O(_0436_[2]) + ); + CC_LUT4 #( + .INIT(16'h5333) + ) _0475_ ( + .I0(rs2[0]), + .I1(Iimm[0]), + .I2(_0099_[2]), + .I3(_0099_[3]), + .O(_0089_[0]) + ); + CC_LUT3 #( + .INIT(8'h10) + ) _0476_ ( + .I0(instr[3]), + .I1(instr[2]), + .I2(instr[5]), + .O(_0099_[2]) + ); + CC_LUT2 #( + .INIT(4'h6) + ) _0477_ ( + .I0(instr[4]), + .I1(instr[6]), + .O(_0099_[3]) + ); + CC_LUT4 #( + .INIT(16'h5333) + ) _0478_ ( + .I0(rs2[1]), + .I1(Iimm[1]), + .I2(_0099_[2]), + .I3(_0099_[3]), + .O(_0089_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0479_ ( + .I0(Iimm[2]), + .I1(rs2[2]), + .I2(_0102_[2]), + .O(_0089_[2]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0480_ ( + .I0(_0099_[2]), + .I1(_0099_[3]), + .O(_0102_[2]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0481_ ( + .I0(Iimm[3]), + .I1(rs2[3]), + .I2(_0102_[2]), + .O(_0089_[3]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0482_ ( + .I0(Iimm[4]), + .I1(rs2[4]), + .I2(_0102_[2]), + .O(_0089_[4]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0483_ ( + .I0(Bimm[5]), + .I1(rs2[5]), + .I2(_0102_[2]), + .O(_0089_[5]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0484_ ( + .I0(Bimm[6]), + .I1(rs2[6]), + .I2(_0102_[2]), + .O(_0089_[6]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0485_ ( + .I0(Bimm[7]), + .I1(rs2[7]), + .I2(_0102_[2]), + .O(_0089_[7]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0486_ ( + .I0(Bimm[8]), + .I1(rs2[8]), + .I2(_0102_[2]), + .O(_0089_[8]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0487_ ( + .I0(Bimm[9]), + .I1(rs2[9]), + .I2(_0102_[2]), + .O(_0089_[9]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0488_ ( + .I0(Bimm[10]), + .I1(rs2[10]), + .I2(_0102_[2]), + .O(_0089_[10]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0489_ ( + .I0(Bimm[31]), + .I1(rs2[11]), + .I2(_0102_[2]), + .O(_0089_[11]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0490_ ( + .I0(Bimm[31]), + .I1(rs2[12]), + .I2(_0102_[2]), + .O(_0089_[12]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0491_ ( + .I0(Bimm[31]), + .I1(rs2[13]), + .I2(_0102_[2]), + .O(_0089_[13]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0492_ ( + .I0(Bimm[31]), + .I1(rs2[14]), + .I2(_0102_[2]), + .O(_0089_[14]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0493_ ( + .I0(Bimm[31]), + .I1(rs2[15]), + .I2(_0102_[2]), + .O(_0089_[15]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0494_ ( + .I0(Bimm[31]), + .I1(rs2[16]), + .I2(_0102_[2]), + .O(_0089_[16]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0495_ ( + .I0(Bimm[31]), + .I1(rs2[17]), + .I2(_0102_[2]), + .O(_0089_[17]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0496_ ( + .I0(Bimm[31]), + .I1(rs2[18]), + .I2(_0102_[2]), + .O(_0089_[18]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0497_ ( + .I0(Bimm[31]), + .I1(rs2[19]), + .I2(_0102_[2]), + .O(_0089_[19]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0498_ ( + .I0(Bimm[31]), + .I1(rs2[20]), + .I2(_0102_[2]), + .O(_0089_[20]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0499_ ( + .I0(Bimm[31]), + .I1(rs2[21]), + .I2(_0102_[2]), + .O(_0089_[21]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0500_ ( + .I0(Bimm[31]), + .I1(rs2[22]), + .I2(_0102_[2]), + .O(_0089_[22]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0501_ ( + .I0(Bimm[31]), + .I1(rs2[23]), + .I2(_0102_[2]), + .O(_0089_[23]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0502_ ( + .I0(Bimm[31]), + .I1(rs2[24]), + .I2(_0102_[2]), + .O(_0089_[24]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0503_ ( + .I0(Bimm[31]), + .I1(rs2[25]), + .I2(_0102_[2]), + .O(_0089_[25]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0504_ ( + .I0(Bimm[31]), + .I1(rs2[26]), + .I2(_0102_[2]), + .O(_0089_[26]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0505_ ( + .I0(Bimm[31]), + .I1(rs2[27]), + .I2(_0102_[2]), + .O(_0089_[27]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0506_ ( + .I0(Bimm[31]), + .I1(rs2[28]), + .I2(_0102_[2]), + .O(_0089_[28]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0507_ ( + .I0(Bimm[31]), + .I1(rs2[29]), + .I2(_0102_[2]), + .O(_0089_[29]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0508_ ( + .I0(Bimm[31]), + .I1(rs2[30]), + .I2(_0102_[2]), + .O(_0089_[30]) + ); + CC_LUT4 #( + .INIT(16'h5333) + ) _0509_ ( + .I0(rs2[31]), + .I1(Bimm[31]), + .I2(_0099_[2]), + .I3(_0099_[3]), + .O(_0089_[31]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0510_ ( + .I0(state[3]), + .I1(state[2]), + .I2(_0471_[2]), + .O(_0000_[31]) + ); + CC_LUT4 #( + .INIT(16'hb0bb) + ) _0511_ ( + .I0(Bimm[4]), + .I1(_0470_[1]), + .I2(instr[4]), + .I3(_0099_[2]), + .O(_0471_[2]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0512_ ( + .I0(Bimm[1]), + .I1(Bimm[2]), + .I2(Bimm[3]), + .I3(Bimm[11]), + .O(_0470_[1]) + ); + CC_LUT3 #( + .INIT(8'hd0) + ) _0513_ ( + .I0(_0469_[0]), + .I1(_0292_[2]), + .I2(_0390_[1]), + .O(_0049_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0514_ ( + .I0(_0148_[1]), + .I1(state[2]), + .O(_0292_[2]) + ); + CC_LUT3 #( + .INIT(8'h10) + ) _0515_ ( + .I0(instr[6]), + .I1(instr[2]), + .I2(_0147_[2]), + .O(_0148_[1]) + ); + CC_LUT2 #( + .INIT(4'h1) + ) _0516_ ( + .I0(instr[4]), + .I1(instr[3]), + .O(_0147_[2]) + ); + CC_LUT4 #( + .INIT(16'h0fee) + ) _0517_ ( + .I0(state[3]), + .I1(state[2]), + .I2(_0096_[9]), + .I3(state[1]), + .O(_0469_[0]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0518_ ( + .I0(_0389_[2]), + .I1(_0390_[1]), + .I2(PC[0]), + .O(_0050_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0519_ ( + .I0(instr[3]), + .I1(_0143_[1]), + .O(_0389_[2]) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0520_ ( + .I0(instr[4]), + .I1(instr[5]), + .I2(instr[6]), + .I3(instr[2]), + .O(_0143_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0521_ ( + .I0(_0390_[1]), + .I1(state[3]), + .O(_0051_) + ); + CC_LUT4 #( + .INIT(16'hf044) + ) _0522_ ( + .I0(instr[4]), + .I1(Bimm[1]), + .I2(Iimm[1]), + .I3(instr[3]), + .O(_0084_[0]) + ); + CC_LUT4 #( + .INIT(16'hf044) + ) _0523_ ( + .I0(instr[4]), + .I1(Bimm[2]), + .I2(Iimm[2]), + .I3(instr[3]), + .O(_0084_[1]) + ); + CC_LUT4 #( + .INIT(16'hf044) + ) _0524_ ( + .I0(instr[4]), + .I1(Bimm[3]), + .I2(Iimm[3]), + .I3(instr[3]), + .O(_0084_[2]) + ); + CC_LUT4 #( + .INIT(16'hf044) + ) _0525_ ( + .I0(instr[4]), + .I1(Bimm[4]), + .I2(Iimm[4]), + .I3(instr[3]), + .O(_0084_[3]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0526_ ( + .I0(_0150_[2]), + .I1(Bimm[5]), + .O(_0084_[4]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0527_ ( + .I0(instr[3]), + .I1(instr[4]), + .O(_0150_[2]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0528_ ( + .I0(_0150_[2]), + .I1(Bimm[6]), + .O(_0084_[5]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0529_ ( + .I0(_0150_[2]), + .I1(Bimm[7]), + .O(_0084_[6]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0530_ ( + .I0(_0150_[2]), + .I1(Bimm[8]), + .O(_0084_[7]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0531_ ( + .I0(_0150_[2]), + .I1(Bimm[9]), + .O(_0084_[8]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0532_ ( + .I0(_0150_[2]), + .I1(Bimm[10]), + .O(_0084_[9]) + ); + CC_LUT4 #( + .INIT(16'hf044) + ) _0533_ ( + .I0(instr[4]), + .I1(Bimm[11]), + .I2(Iimm[0]), + .I3(instr[3]), + .O(_0084_[10]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0534_ ( + .I0(Jimm[12]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[11]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0535_ ( + .I0(Jimm[13]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[12]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0536_ ( + .I0(Jimm[14]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[13]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0537_ ( + .I0(Jimm[15]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[14]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0538_ ( + .I0(Jimm[16]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[15]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0539_ ( + .I0(Jimm[17]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[16]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0540_ ( + .I0(Jimm[18]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[17]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0541_ ( + .I0(Jimm[19]), + .I1(Bimm[31]), + .I2(_0147_[2]), + .O(_0084_[18]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0542_ ( + .I0(Bimm[31]), + .I1(Iimm[0]), + .I2(_0150_[2]), + .O(_0084_[19]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0543_ ( + .I0(Bimm[31]), + .I1(Iimm[1]), + .I2(_0150_[2]), + .O(_0084_[20]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0544_ ( + .I0(Bimm[31]), + .I1(Iimm[2]), + .I2(_0150_[2]), + .O(_0084_[21]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0545_ ( + .I0(Bimm[31]), + .I1(Iimm[3]), + .I2(_0150_[2]), + .O(_0084_[22]) + ); + CC_LUT4 #( + .INIT(16'hccc5) + ) _0546_ ( + .I0(_0468_[0]), + .I1(PC[0]), + .I2(state[1]), + .I3(state[0]), + .O(_0004_) + ); + CC_LUT4 #( + .INIT(16'hbb0f) + ) _0547_ ( + .I0(_0389_[2]), + .I1(PC[0]), + .I2(loadstore_addr[0]), + .I3(_0292_[2]), + .O(_0468_[0]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0548_ ( + .I0(_0434_[0]), + .I1(_0292_[2]), + .I2(_0467_[2]), + .I3(_0467_[3]), + .O(_0015_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0549_ ( + .I0(aluPlus[1]), + .I1(_0433_[1]), + .I2(_0389_[2]), + .O(_0434_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0550_ ( + .I0(PCplusImm[1]), + .I1(PC[1]), + .I2(_0388_[2]), + .O(_0433_[1]) + ); + CC_LUT4 #( + .INIT(16'h880f) + ) _0551_ ( + .I0(_0387_[0]), + .I1(_0387_[1]), + .I2(_0143_[1]), + .I3(_0387_[3]), + .O(_0388_[2]) + ); + CC_LUT4 #( + .INIT(16'h0503) + ) _0552_ ( + .I0(_0295_[2]), + .I1(_0294_[0]), + .I2(_0386_[2]), + .I3(LTU), + .O(_0387_[1]) + ); + CC_LUT4 #( + .INIT(16'he800) + ) _0553_ ( + .I0(_0089_[31]), + .I1(LTU), + .I2(aluIn1[31]), + .I3(_0294_[1]), + .O(_0386_[2]) + ); + CC_LUT3 #( + .INIT(8'h10) + ) _0554_ ( + .I0(Jimm[12]), + .I1(Jimm[13]), + .I2(Jimm[14]), + .O(_0294_[1]) + ); + CC_LUT3 #( + .INIT(8'h80) + ) _0555_ ( + .I0(Jimm[14]), + .I1(Jimm[12]), + .I2(Jimm[13]), + .O(_0294_[0]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0556_ ( + .I0(Jimm[12]), + .I1(Jimm[14]), + .I2(Jimm[13]), + .O(_0295_[2]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0557_ ( + .I0(_0098_[2]), + .I1(_0097_[3]), + .I2(_0385_[2]), + .I3(_0385_[3]), + .O(_0387_[0]) + ); + CC_LUT4 #( + .INIT(16'h1700) + ) _0558_ ( + .I0(_0089_[31]), + .I1(LTU), + .I2(aluIn1[31]), + .I3(_0163_[3]), + .O(_0385_[2]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0559_ ( + .I0(_0134_[0]), + .I1(Jimm[14]), + .O(_0163_[3]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0560_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .O(_0134_[0]) + ); + CC_LUT4 #( + .INIT(16'h8000) + ) _0561_ ( + .I0(_0384_[0]), + .I1(_0384_[1]), + .I2(_0384_[2]), + .I3(_0384_[3]), + .O(_0385_[3]) + ); + CC_LUT4 #( + .INIT(16'h8000) + ) _0562_ ( + .I0(_0383_[0]), + .I1(_0383_[1]), + .I2(_0383_[2]), + .I3(_0383_[3]), + .O(_0384_[0]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0563_ ( + .I0(aluMinus[20]), + .I1(aluMinus[21]), + .I2(aluMinus[22]), + .I3(aluMinus[23]), + .O(_0383_[0]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0564_ ( + .I0(aluMinus[16]), + .I1(aluMinus[17]), + .I2(aluMinus[18]), + .I3(aluMinus[19]), + .O(_0383_[1]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0565_ ( + .I0(aluMinus[28]), + .I1(aluMinus[29]), + .I2(aluMinus[30]), + .I3(aluMinus[31]), + .O(_0383_[2]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0566_ ( + .I0(aluMinus[24]), + .I1(aluMinus[25]), + .I2(aluMinus[26]), + .I3(aluMinus[27]), + .O(_0383_[3]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0567_ ( + .I0(_0382_[0]), + .I1(_0382_[1]), + .O(_0384_[1]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0568_ ( + .I0(aluMinus[4]), + .I1(aluMinus[5]), + .I2(aluMinus[6]), + .I3(aluMinus[7]), + .O(_0382_[0]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0569_ ( + .I0(aluMinus[0]), + .I1(aluMinus[1]), + .I2(aluMinus[2]), + .I3(aluMinus[3]), + .O(_0382_[1]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0570_ ( + .I0(aluMinus[12]), + .I1(aluMinus[13]), + .I2(aluMinus[14]), + .I3(aluMinus[15]), + .O(_0384_[2]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0571_ ( + .I0(aluMinus[8]), + .I1(aluMinus[9]), + .I2(aluMinus[10]), + .I3(aluMinus[11]), + .O(_0384_[3]) + ); + CC_LUT3 #( + .INIT(8'h10) + ) _0572_ ( + .I0(Jimm[14]), + .I1(Jimm[13]), + .I2(Jimm[12]), + .O(_0098_[2]) + ); + CC_LUT3 #( + .INIT(8'h01) + ) _0573_ ( + .I0(Jimm[14]), + .I1(Jimm[12]), + .I2(Jimm[13]), + .O(_0097_[3]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0574_ ( + .I0(instr[4]), + .I1(_0099_[2]), + .I2(instr[6]), + .O(_0387_[3]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0575_ ( + .I0(loadstore_addr[1]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0467_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0576_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[1]), + .O(_0467_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0577_ ( + .I0(_0432_[0]), + .I1(_0292_[2]), + .I2(_0466_[2]), + .I3(_0466_[3]), + .O(_0020_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0578_ ( + .I0(aluPlus[2]), + .I1(_0431_[1]), + .I2(_0389_[2]), + .O(_0432_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0579_ ( + .I0(PCplusImm[2]), + .I1(PCplus4[2]), + .I2(_0388_[2]), + .O(_0431_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0580_ ( + .I0(loadstore_addr[2]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0466_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0581_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[2]), + .O(_0466_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0582_ ( + .I0(_0430_[0]), + .I1(_0292_[2]), + .I2(_0465_[2]), + .I3(_0465_[3]), + .O(_0021_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0583_ ( + .I0(aluPlus[3]), + .I1(_0429_[1]), + .I2(_0389_[2]), + .O(_0430_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0584_ ( + .I0(PCplusImm[3]), + .I1(PCplus4[3]), + .I2(_0388_[2]), + .O(_0429_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0585_ ( + .I0(loadstore_addr[3]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0465_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0586_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[3]), + .O(_0465_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0587_ ( + .I0(_0428_[0]), + .I1(_0292_[2]), + .I2(_0464_[2]), + .I3(_0464_[3]), + .O(_0022_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0588_ ( + .I0(aluPlus[4]), + .I1(_0427_[1]), + .I2(_0389_[2]), + .O(_0428_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0589_ ( + .I0(PCplusImm[4]), + .I1(PCplus4[4]), + .I2(_0388_[2]), + .O(_0427_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0590_ ( + .I0(loadstore_addr[4]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0464_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0591_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[4]), + .O(_0464_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0592_ ( + .I0(_0426_[0]), + .I1(_0292_[2]), + .I2(_0463_[2]), + .I3(_0463_[3]), + .O(_0023_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0593_ ( + .I0(aluPlus[5]), + .I1(_0425_[1]), + .I2(_0389_[2]), + .O(_0426_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0594_ ( + .I0(PCplusImm[5]), + .I1(PCplus4[5]), + .I2(_0388_[2]), + .O(_0425_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0595_ ( + .I0(loadstore_addr[5]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0463_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0596_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[5]), + .O(_0463_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0597_ ( + .I0(_0424_[0]), + .I1(_0292_[2]), + .I2(_0462_[2]), + .I3(_0462_[3]), + .O(_0024_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0598_ ( + .I0(aluPlus[6]), + .I1(_0423_[1]), + .I2(_0389_[2]), + .O(_0424_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0599_ ( + .I0(PCplusImm[6]), + .I1(PCplus4[6]), + .I2(_0388_[2]), + .O(_0423_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0600_ ( + .I0(loadstore_addr[6]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0462_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0601_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[6]), + .O(_0462_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0602_ ( + .I0(_0422_[0]), + .I1(_0292_[2]), + .I2(_0461_[2]), + .I3(_0461_[3]), + .O(_0025_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0603_ ( + .I0(aluPlus[7]), + .I1(_0421_[1]), + .I2(_0389_[2]), + .O(_0422_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0604_ ( + .I0(PCplusImm[7]), + .I1(PCplus4[7]), + .I2(_0388_[2]), + .O(_0421_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0605_ ( + .I0(loadstore_addr[7]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0461_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0606_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[7]), + .O(_0461_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0607_ ( + .I0(_0420_[0]), + .I1(_0292_[2]), + .I2(_0460_[2]), + .I3(_0460_[3]), + .O(_0026_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0608_ ( + .I0(aluPlus[8]), + .I1(_0419_[1]), + .I2(_0389_[2]), + .O(_0420_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0609_ ( + .I0(PCplusImm[8]), + .I1(PCplus4[8]), + .I2(_0388_[2]), + .O(_0419_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0610_ ( + .I0(loadstore_addr[8]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0460_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0611_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[8]), + .O(_0460_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0612_ ( + .I0(_0418_[0]), + .I1(_0292_[2]), + .I2(_0459_[2]), + .I3(_0459_[3]), + .O(_0027_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0613_ ( + .I0(aluPlus[9]), + .I1(_0417_[1]), + .I2(_0389_[2]), + .O(_0418_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0614_ ( + .I0(PCplusImm[9]), + .I1(PCplus4[9]), + .I2(_0388_[2]), + .O(_0417_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0615_ ( + .I0(loadstore_addr[9]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0459_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0616_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[9]), + .O(_0459_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0617_ ( + .I0(_0416_[0]), + .I1(_0292_[2]), + .I2(_0458_[2]), + .I3(_0458_[3]), + .O(_0005_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0618_ ( + .I0(aluPlus[10]), + .I1(_0415_[1]), + .I2(_0389_[2]), + .O(_0416_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0619_ ( + .I0(PCplusImm[10]), + .I1(PCplus4[10]), + .I2(_0388_[2]), + .O(_0415_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0620_ ( + .I0(loadstore_addr[10]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0458_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0621_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[10]), + .O(_0458_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0622_ ( + .I0(_0414_[0]), + .I1(_0292_[2]), + .I2(_0457_[2]), + .I3(_0457_[3]), + .O(_0006_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0623_ ( + .I0(aluPlus[11]), + .I1(_0413_[1]), + .I2(_0389_[2]), + .O(_0414_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0624_ ( + .I0(PCplusImm[11]), + .I1(PCplus4[11]), + .I2(_0388_[2]), + .O(_0413_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0625_ ( + .I0(loadstore_addr[11]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0457_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0626_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[11]), + .O(_0457_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0627_ ( + .I0(_0412_[0]), + .I1(_0292_[2]), + .I2(_0456_[2]), + .I3(_0456_[3]), + .O(_0007_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0628_ ( + .I0(aluPlus[12]), + .I1(_0411_[1]), + .I2(_0389_[2]), + .O(_0412_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0629_ ( + .I0(PCplusImm[12]), + .I1(PCplus4[12]), + .I2(_0388_[2]), + .O(_0411_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0630_ ( + .I0(loadstore_addr[12]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0456_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0631_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[12]), + .O(_0456_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0632_ ( + .I0(_0410_[0]), + .I1(_0292_[2]), + .I2(_0455_[2]), + .I3(_0455_[3]), + .O(_0008_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0633_ ( + .I0(aluPlus[13]), + .I1(_0409_[1]), + .I2(_0389_[2]), + .O(_0410_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0634_ ( + .I0(PCplusImm[13]), + .I1(PCplus4[13]), + .I2(_0388_[2]), + .O(_0409_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0635_ ( + .I0(loadstore_addr[13]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0455_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0636_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[13]), + .O(_0455_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0637_ ( + .I0(_0408_[0]), + .I1(_0292_[2]), + .I2(_0454_[2]), + .I3(_0454_[3]), + .O(_0009_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0638_ ( + .I0(aluPlus[14]), + .I1(_0407_[1]), + .I2(_0389_[2]), + .O(_0408_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0639_ ( + .I0(PCplusImm[14]), + .I1(PCplus4[14]), + .I2(_0388_[2]), + .O(_0407_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0640_ ( + .I0(loadstore_addr[14]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0454_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0641_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[14]), + .O(_0454_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0642_ ( + .I0(_0406_[0]), + .I1(_0292_[2]), + .I2(_0453_[2]), + .I3(_0453_[3]), + .O(_0010_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0643_ ( + .I0(aluPlus[15]), + .I1(_0405_[1]), + .I2(_0389_[2]), + .O(_0406_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0644_ ( + .I0(PCplusImm[15]), + .I1(PCplus4[15]), + .I2(_0388_[2]), + .O(_0405_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0645_ ( + .I0(loadstore_addr[15]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0453_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0646_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[15]), + .O(_0453_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0647_ ( + .I0(_0404_[0]), + .I1(_0292_[2]), + .I2(_0452_[2]), + .I3(_0452_[3]), + .O(_0011_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0648_ ( + .I0(aluPlus[16]), + .I1(_0403_[1]), + .I2(_0389_[2]), + .O(_0404_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0649_ ( + .I0(PCplusImm[16]), + .I1(PCplus4[16]), + .I2(_0388_[2]), + .O(_0403_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0650_ ( + .I0(loadstore_addr[16]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0452_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0651_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[16]), + .O(_0452_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0652_ ( + .I0(_0402_[0]), + .I1(_0292_[2]), + .I2(_0451_[2]), + .I3(_0451_[3]), + .O(_0012_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0653_ ( + .I0(aluPlus[17]), + .I1(_0401_[1]), + .I2(_0389_[2]), + .O(_0402_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0654_ ( + .I0(PCplusImm[17]), + .I1(PCplus4[17]), + .I2(_0388_[2]), + .O(_0401_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0655_ ( + .I0(loadstore_addr[17]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0451_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0656_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[17]), + .O(_0451_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0657_ ( + .I0(_0400_[0]), + .I1(_0292_[2]), + .I2(_0450_[2]), + .I3(_0450_[3]), + .O(_0013_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0658_ ( + .I0(aluPlus[18]), + .I1(_0399_[1]), + .I2(_0389_[2]), + .O(_0400_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0659_ ( + .I0(PCplusImm[18]), + .I1(PCplus4[18]), + .I2(_0388_[2]), + .O(_0399_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0660_ ( + .I0(loadstore_addr[18]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0450_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0661_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[18]), + .O(_0450_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0662_ ( + .I0(_0398_[0]), + .I1(_0292_[2]), + .I2(_0449_[2]), + .I3(_0449_[3]), + .O(_0014_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0663_ ( + .I0(aluPlus[19]), + .I1(_0397_[1]), + .I2(_0389_[2]), + .O(_0398_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0664_ ( + .I0(PCplusImm[19]), + .I1(PCplus4[19]), + .I2(_0388_[2]), + .O(_0397_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0665_ ( + .I0(loadstore_addr[19]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0449_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0666_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[19]), + .O(_0449_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0667_ ( + .I0(_0396_[0]), + .I1(_0292_[2]), + .I2(_0448_[2]), + .I3(_0448_[3]), + .O(_0016_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0668_ ( + .I0(aluPlus[20]), + .I1(_0395_[1]), + .I2(_0389_[2]), + .O(_0396_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0669_ ( + .I0(PCplusImm[20]), + .I1(PCplus4[20]), + .I2(_0388_[2]), + .O(_0395_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0670_ ( + .I0(loadstore_addr[20]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0448_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0671_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[20]), + .O(_0448_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0672_ ( + .I0(_0394_[0]), + .I1(_0292_[2]), + .I2(_0447_[2]), + .I3(_0447_[3]), + .O(_0017_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0673_ ( + .I0(aluPlus[21]), + .I1(_0393_[1]), + .I2(_0389_[2]), + .O(_0394_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0674_ ( + .I0(PCplusImm[21]), + .I1(PCplus4[21]), + .I2(_0388_[2]), + .O(_0393_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0675_ ( + .I0(loadstore_addr[21]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0447_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0676_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[21]), + .O(_0447_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0677_ ( + .I0(_0392_[0]), + .I1(_0292_[2]), + .I2(_0446_[2]), + .I3(_0446_[3]), + .O(_0018_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0678_ ( + .I0(aluPlus[22]), + .I1(_0391_[1]), + .I2(_0389_[2]), + .O(_0392_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0679_ ( + .I0(PCplusImm[22]), + .I1(PCplus4[22]), + .I2(_0388_[2]), + .O(_0391_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0680_ ( + .I0(loadstore_addr[22]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0446_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0681_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[22]), + .O(_0446_[3]) + ); + CC_LUT4 #( + .INIT(16'hff70) + ) _0682_ ( + .I0(_0390_[0]), + .I1(_0292_[2]), + .I2(_0445_[2]), + .I3(_0445_[3]), + .O(_0019_) + ); + CC_LUT3 #( + .INIT(8'h53) + ) _0683_ ( + .I0(aluPlus[23]), + .I1(_0389_[1]), + .I2(_0389_[2]), + .O(_0390_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0684_ ( + .I0(PCplusImm[23]), + .I1(PCplus4[23]), + .I2(_0388_[2]), + .O(_0389_[1]) + ); + CC_LUT4 #( + .INIT(16'h000e) + ) _0685_ ( + .I0(loadstore_addr[23]), + .I1(_0292_[2]), + .I2(state[1]), + .I3(state[0]), + .O(_0445_[2]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0686_ ( + .I0(state[0]), + .I1(state[1]), + .I2(PC[23]), + .O(_0445_[3]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0687_ ( + .I0(rs2[8]), + .I1(rs2[0]), + .I2(loadstore_addr[0]), + .O(_0444_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0688_ ( + .I0(rs2[9]), + .I1(rs2[1]), + .I2(loadstore_addr[0]), + .O(_0443_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0689_ ( + .I0(rs2[10]), + .I1(rs2[2]), + .I2(loadstore_addr[0]), + .O(_0442_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0690_ ( + .I0(rs2[11]), + .I1(rs2[3]), + .I2(loadstore_addr[0]), + .O(_0441_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0691_ ( + .I0(rs2[12]), + .I1(rs2[4]), + .I2(loadstore_addr[0]), + .O(_0440_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0692_ ( + .I0(rs2[13]), + .I1(rs2[5]), + .I2(loadstore_addr[0]), + .O(_0439_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0693_ ( + .I0(rs2[14]), + .I1(rs2[6]), + .I2(loadstore_addr[0]), + .O(_0438_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0694_ ( + .I0(rs2[15]), + .I1(rs2[7]), + .I2(loadstore_addr[0]), + .O(_0437_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0695_ ( + .I0(rs2[16]), + .I1(rs2[0]), + .I2(loadstore_addr[1]), + .O(_0029_) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0696_ ( + .I0(rs2[17]), + .I1(rs2[1]), + .I2(loadstore_addr[1]), + .O(_0030_) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0697_ ( + .I0(rs2[18]), + .I1(rs2[2]), + .I2(loadstore_addr[1]), + .O(_0031_) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0698_ ( + .I0(rs2[19]), + .I1(rs2[3]), + .I2(loadstore_addr[1]), + .O(_0032_) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0699_ ( + .I0(rs2[20]), + .I1(rs2[4]), + .I2(loadstore_addr[1]), + .O(_0033_) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0700_ ( + .I0(rs2[21]), + .I1(rs2[5]), + .I2(loadstore_addr[1]), + .O(_0034_) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0701_ ( + .I0(rs2[22]), + .I1(rs2[6]), + .I2(loadstore_addr[1]), + .O(_0035_) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0702_ ( + .I0(rs2[23]), + .I1(rs2[7]), + .I2(loadstore_addr[1]), + .O(_0036_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0703_ ( + .I0(rs2[24]), + .I1(_0444_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0037_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0704_ ( + .I0(rs2[25]), + .I1(_0443_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0038_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0705_ ( + .I0(rs2[26]), + .I1(_0442_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0039_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0706_ ( + .I0(rs2[27]), + .I1(_0441_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0040_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0707_ ( + .I0(rs2[28]), + .I1(_0440_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0041_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0708_ ( + .I0(rs2[29]), + .I1(_0439_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0042_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0709_ ( + .I0(rs2[30]), + .I1(_0438_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0043_) + ); + CC_LUT4 #( + .INIT(16'hccca) + ) _0710_ ( + .I0(rs2[31]), + .I1(_0437_[1]), + .I2(loadstore_addr[1]), + .I3(loadstore_addr[0]), + .O(_0044_) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0711_ ( + .I0(_0096_[9]), + .I1(state[1]), + .I2(_0390_[1]), + .O(_0001_) + ); + CC_LUT4 #( + .INIT(16'hf8ff) + ) _0712_ ( + .I0(state[2]), + .I1(_0148_[1]), + .I2(_0436_[2]), + .I3(_0390_[1]), + .O(_0052_) + ); + CC_LUT3 #( + .INIT(8'hac) + ) _0713_ ( + .I0(Bimm[11]), + .I1(Iimm[0]), + .I2(instr[5]), + .O(_0079_[0]) + ); + CC_LUT3 #( + .INIT(8'hac) + ) _0714_ ( + .I0(Bimm[1]), + .I1(Iimm[1]), + .I2(instr[5]), + .O(_0079_[1]) + ); + CC_LUT3 #( + .INIT(8'hac) + ) _0715_ ( + .I0(Bimm[2]), + .I1(Iimm[2]), + .I2(instr[5]), + .O(_0079_[2]) + ); + CC_LUT3 #( + .INIT(8'hac) + ) _0716_ ( + .I0(Bimm[3]), + .I1(Iimm[3]), + .I2(instr[5]), + .O(_0079_[3]) + ); + CC_LUT3 #( + .INIT(8'hac) + ) _0717_ ( + .I0(Bimm[4]), + .I1(Iimm[4]), + .I2(instr[5]), + .O(_0079_[4]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0718_ ( + .I0(_0434_[0]), + .I1(_0390_[1]), + .O(_0053_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0719_ ( + .I0(_0432_[0]), + .I1(_0390_[1]), + .O(_0054_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0720_ ( + .I0(_0430_[0]), + .I1(_0390_[1]), + .O(_0055_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0721_ ( + .I0(_0428_[0]), + .I1(_0390_[1]), + .O(_0056_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0722_ ( + .I0(_0426_[0]), + .I1(_0390_[1]), + .O(_0057_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0723_ ( + .I0(_0424_[0]), + .I1(_0390_[1]), + .O(_0058_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0724_ ( + .I0(_0422_[0]), + .I1(_0390_[1]), + .O(_0059_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0725_ ( + .I0(_0420_[0]), + .I1(_0390_[1]), + .O(_0060_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0726_ ( + .I0(_0418_[0]), + .I1(_0390_[1]), + .O(_0061_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0727_ ( + .I0(_0416_[0]), + .I1(_0390_[1]), + .O(_0062_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0728_ ( + .I0(_0414_[0]), + .I1(_0390_[1]), + .O(_0063_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0729_ ( + .I0(_0412_[0]), + .I1(_0390_[1]), + .O(_0064_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0730_ ( + .I0(_0410_[0]), + .I1(_0390_[1]), + .O(_0065_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0731_ ( + .I0(_0408_[0]), + .I1(_0390_[1]), + .O(_0066_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0732_ ( + .I0(_0406_[0]), + .I1(_0390_[1]), + .O(_0067_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0733_ ( + .I0(_0404_[0]), + .I1(_0390_[1]), + .O(_0068_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0734_ ( + .I0(_0402_[0]), + .I1(_0390_[1]), + .O(_0069_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0735_ ( + .I0(_0400_[0]), + .I1(_0390_[1]), + .O(_0070_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0736_ ( + .I0(_0398_[0]), + .I1(_0390_[1]), + .O(_0071_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0737_ ( + .I0(_0396_[0]), + .I1(_0390_[1]), + .O(_0072_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0738_ ( + .I0(_0394_[0]), + .I1(_0390_[1]), + .O(_0073_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0739_ ( + .I0(_0392_[0]), + .I1(_0390_[1]), + .O(_0074_) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0740_ ( + .I0(_0390_[0]), + .I1(_0390_[1]), + .O(_0075_) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _0741_ ( + .I0(_0381_[0]), + .I1(_0381_[1]), + .I2(_0152_[2]), + .I3(_0381_[3]), + .O(writeBackData[0]) + ); + CC_LUT4 #( + .INIT(16'h1f00) + ) _0742_ ( + .I0(_0297_[0]), + .I1(_0297_[1]), + .I2(_0163_[3]), + .I3(_0380_[3]), + .O(_0381_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0743_ ( + .I0(aluIn1[0]), + .I1(aluIn1[31]), + .I2(_0098_[2]), + .O(_0287_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0744_ ( + .I0(aluIn1[1]), + .I1(aluIn1[30]), + .I2(_0098_[2]), + .O(_0282_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0745_ ( + .I0(aluIn1[2]), + .I1(aluIn1[29]), + .I2(_0098_[2]), + .O(_0275_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0746_ ( + .I0(aluIn1[3]), + .I1(aluIn1[28]), + .I2(_0098_[2]), + .O(_0137_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0747_ ( + .I0(_0265_[1]), + .I1(_0276_[0]), + .I2(_0089_[1]), + .O(_0289_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0748_ ( + .I0(_0127_[1]), + .I1(_0137_[0]), + .I2(_0089_[0]), + .O(_0276_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0749_ ( + .I0(aluIn1[4]), + .I1(aluIn1[27]), + .I2(_0098_[2]), + .O(_0137_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0750_ ( + .I0(aluIn1[5]), + .I1(aluIn1[26]), + .I2(_0098_[2]), + .O(_0127_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0751_ ( + .I0(_0126_[1]), + .I1(_0127_[0]), + .I2(_0089_[0]), + .O(_0265_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0752_ ( + .I0(aluIn1[6]), + .I1(aluIn1[25]), + .I2(_0098_[2]), + .O(_0127_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0753_ ( + .I0(aluIn1[7]), + .I1(aluIn1[24]), + .I2(_0098_[2]), + .O(_0126_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0754_ ( + .I0(_0177_[0]), + .I1(_0177_[1]), + .I2(_0089_[2]), + .O(_0178_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0755_ ( + .I0(_0176_[0]), + .I1(_0176_[1]), + .I2(_0089_[1]), + .O(_0177_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0756_ ( + .I0(_0130_[1]), + .I1(_0126_[0]), + .I2(_0089_[0]), + .O(_0176_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0757_ ( + .I0(aluIn1[8]), + .I1(aluIn1[23]), + .I2(_0098_[2]), + .O(_0126_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0758_ ( + .I0(aluIn1[9]), + .I1(aluIn1[22]), + .I2(_0098_[2]), + .O(_0130_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0759_ ( + .I0(_0129_[1]), + .I1(_0130_[0]), + .I2(_0089_[0]), + .O(_0176_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0760_ ( + .I0(aluIn1[10]), + .I1(aluIn1[21]), + .I2(_0098_[2]), + .O(_0130_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0761_ ( + .I0(aluIn1[11]), + .I1(aluIn1[20]), + .I2(_0098_[2]), + .O(_0129_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0762_ ( + .I0(_0175_[0]), + .I1(_0175_[1]), + .I2(_0089_[1]), + .O(_0177_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0763_ ( + .I0(_0123_[1]), + .I1(_0129_[0]), + .I2(_0089_[0]), + .O(_0175_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0764_ ( + .I0(aluIn1[12]), + .I1(aluIn1[19]), + .I2(_0098_[2]), + .O(_0129_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0765_ ( + .I0(aluIn1[13]), + .I1(aluIn1[18]), + .I2(_0098_[2]), + .O(_0123_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0766_ ( + .I0(_0122_[1]), + .I1(_0123_[0]), + .I2(_0089_[0]), + .O(_0175_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0767_ ( + .I0(aluIn1[14]), + .I1(aluIn1[17]), + .I2(_0098_[2]), + .O(_0123_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0768_ ( + .I0(aluIn1[15]), + .I1(aluIn1[16]), + .I2(_0098_[2]), + .O(_0122_[1]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0769_ ( + .I0(_0216_[0]), + .I1(_0216_[1]), + .I2(_0089_[4]), + .O(_0297_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0770_ ( + .I0(_0174_[0]), + .I1(_0174_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0216_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0771_ ( + .I0(_0173_[0]), + .I1(_0173_[1]), + .I2(_0089_[1]), + .O(_0174_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0772_ ( + .I0(_0120_[1]), + .I1(_0122_[0]), + .I2(_0089_[0]), + .O(_0173_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0773_ ( + .I0(aluIn1[16]), + .I1(aluIn1[15]), + .I2(_0098_[2]), + .O(_0122_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0774_ ( + .I0(aluIn1[17]), + .I1(aluIn1[14]), + .I2(_0098_[2]), + .O(_0120_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0775_ ( + .I0(_0119_[1]), + .I1(_0120_[0]), + .I2(_0089_[0]), + .O(_0173_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0776_ ( + .I0(aluIn1[18]), + .I1(aluIn1[13]), + .I2(_0098_[2]), + .O(_0120_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0777_ ( + .I0(aluIn1[19]), + .I1(aluIn1[12]), + .I2(_0098_[2]), + .O(_0119_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0778_ ( + .I0(_0172_[0]), + .I1(_0172_[1]), + .I2(_0089_[1]), + .O(_0174_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0779_ ( + .I0(_0115_[1]), + .I1(_0119_[0]), + .I2(_0089_[0]), + .O(_0172_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0780_ ( + .I0(aluIn1[20]), + .I1(aluIn1[11]), + .I2(_0098_[2]), + .O(_0119_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0781_ ( + .I0(aluIn1[21]), + .I1(aluIn1[10]), + .I2(_0098_[2]), + .O(_0115_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0782_ ( + .I0(_0114_[1]), + .I1(_0115_[0]), + .I2(_0089_[0]), + .O(_0172_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0783_ ( + .I0(aluIn1[22]), + .I1(aluIn1[9]), + .I2(_0098_[2]), + .O(_0115_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0784_ ( + .I0(aluIn1[23]), + .I1(aluIn1[8]), + .I2(_0098_[2]), + .O(_0114_[1]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0785_ ( + .I0(_0180_[0]), + .I1(_0180_[1]), + .I2(_0089_[3]), + .O(_0216_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0786_ ( + .I0(_0103_[1]), + .I1(_0179_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0180_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0787_ ( + .I0(_0112_[1]), + .I1(_0114_[0]), + .I2(_0089_[0]), + .O(_0179_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0788_ ( + .I0(aluIn1[24]), + .I1(aluIn1[7]), + .I2(_0098_[2]), + .O(_0114_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0789_ ( + .I0(aluIn1[25]), + .I1(aluIn1[6]), + .I2(_0098_[2]), + .O(_0112_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0790_ ( + .I0(_0101_[0]), + .I1(_0101_[1]), + .I2(_0089_[0]), + .O(_0103_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0791_ ( + .I0(aluIn1[26]), + .I1(aluIn1[5]), + .I2(_0098_[2]), + .O(_0101_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0792_ ( + .I0(aluIn1[27]), + .I1(aluIn1[4]), + .I2(_0098_[2]), + .O(_0101_[0]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0793_ ( + .I0(_0109_[1]), + .I1(_0109_[0]), + .I2(_0089_[2]), + .O(_0180_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0794_ ( + .I0(_0100_[0]), + .I1(_0100_[1]), + .I2(_0089_[0]), + .I3(_0089_[1]), + .O(_0109_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0795_ ( + .I0(aluIn1[28]), + .I1(aluIn1[3]), + .I2(_0098_[2]), + .O(_0100_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0796_ ( + .I0(aluIn1[29]), + .I1(aluIn1[2]), + .I2(_0098_[2]), + .O(_0100_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0797_ ( + .I0(_0104_[0]), + .I1(_0104_[1]), + .I2(_0089_[1]), + .I3(_0089_[0]), + .O(_0109_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0798_ ( + .I0(aluIn1[31]), + .I1(aluIn1[0]), + .I2(_0098_[2]), + .O(_0104_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0799_ ( + .I0(aluIn1[30]), + .I1(aluIn1[1]), + .I2(_0098_[2]), + .O(_0104_[1]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _0800_ ( + .I0(_0098_[2]), + .I1(_0296_[1]), + .I2(_0379_[2]), + .I3(_0379_[3]), + .O(_0380_[3]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _0801_ ( + .I0(_0105_[0]), + .I1(_0210_[1]), + .I2(_0089_[4]), + .O(_0296_[1]) + ); + CC_LUT4 #( + .INIT(16'ha333) + ) _0802_ ( + .I0(_0135_[2]), + .I1(_0105_[0]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0210_[1]) + ); + CC_LUT4 #( + .INIT(16'ha333) + ) _0803_ ( + .I0(_0104_[0]), + .I1(_0105_[0]), + .I2(_0089_[0]), + .I3(_0089_[1]), + .O(_0135_[2]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0804_ ( + .I0(Bimm[10]), + .I1(aluIn1[31]), + .O(_0105_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0805_ ( + .I0(aluPlus[0]), + .I1(aluMinus[0]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0286_[3]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0806_ ( + .I0(Bimm[10]), + .I1(instr[5]), + .O(_0097_[2]) + ); + CC_LUT4 #( + .INIT(16'hec0e) + ) _0807_ ( + .I0(_0294_[1]), + .I1(_0295_[2]), + .I2(_0089_[0]), + .I3(aluIn1[0]), + .O(_0379_[2]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _0808_ ( + .I0(cycles[0]), + .I1(_0143_[2]), + .I2(_0378_[2]), + .O(_0381_[3]) + ); + CC_LUT4 #( + .INIT(16'h001f) + ) _0809_ ( + .I0(_0151_[1]), + .I1(_0143_[1]), + .I2(PC[0]), + .I3(_0377_[3]), + .O(_0378_[2]) + ); + CC_LUT4 #( + .INIT(16'h4f00) + ) _0810_ ( + .I0(_0356_[0]), + .I1(_0145_[3]), + .I2(_0376_[2]), + .I3(_0149_[1]), + .O(_0377_[3]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0811_ ( + .I0(instr[5]), + .I1(_0148_[1]), + .O(_0149_[1]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _0812_ ( + .I0(Jimm[13]), + .I1(_0374_[1]), + .I2(_0375_[2]), + .O(_0376_[2]) + ); + CC_LUT4 #( + .INIT(16'h0a0c) + ) _0813_ ( + .I0(_0214_[0]), + .I1(_0374_[1]), + .I2(_0144_[2]), + .I3(loadstore_addr[1]), + .O(_0375_[2]) + ); + CC_LUT3 #( + .INIT(8'hf4) + ) _0814_ ( + .I0(Jimm[12]), + .I1(loadstore_addr[0]), + .I2(Jimm[13]), + .O(_0144_[2]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0815_ ( + .I0(_0355_[0]), + .I1(_0324_[0]), + .I2(loadstore_addr[1]), + .O(_0356_[0]) + ); + CC_LUT3 #( + .INIT(8'h10) + ) _0816_ ( + .I0(Jimm[12]), + .I1(Jimm[13]), + .I2(loadstore_addr[0]), + .O(_0145_[3]) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0817_ ( + .I0(instr[5]), + .I1(instr[6]), + .I2(_0150_[2]), + .I3(instr[2]), + .O(_0151_[1]) + ); + CC_LUT3 #( + .INIT(8'h80) + ) _0818_ ( + .I0(_0099_[2]), + .I1(instr[4]), + .I2(instr[6]), + .O(_0143_[2]) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0819_ ( + .I0(_0373_[0]), + .I1(Jimm[14]), + .I2(Jimm[12]), + .I3(Jimm[13]), + .O(_0381_[0]) + ); + CC_LUT3 #( + .INIT(8'h17) + ) _0820_ ( + .I0(_0089_[31]), + .I1(LTU), + .I2(aluIn1[31]), + .O(_0373_[0]) + ); + CC_LUT3 #( + .INIT(8'h10) + ) _0821_ ( + .I0(instr[6]), + .I1(instr[2]), + .I2(_0150_[2]), + .O(_0152_[2]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _0822_ ( + .I0(_0372_[0]), + .I1(_0372_[1]), + .I2(_0152_[2]), + .I3(_0372_[3]), + .O(writeBackData[1]) + ); + CC_LUT3 #( + .INIT(8'h10) + ) _0823_ ( + .I0(_0303_[1]), + .I1(_0303_[0]), + .I2(_0163_[3]), + .O(_0372_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0824_ ( + .I0(_0127_[0]), + .I1(_0127_[1]), + .I2(_0089_[0]), + .O(_0128_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0825_ ( + .I0(_0126_[0]), + .I1(_0126_[1]), + .I2(_0089_[0]), + .O(_0128_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0826_ ( + .I0(_0275_[1]), + .I1(_0282_[1]), + .I2(_0089_[0]), + .O(_0283_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0827_ ( + .I0(_0137_[0]), + .I1(_0137_[1]), + .I2(_0089_[0]), + .O(_0138_[0]) + ); + CC_LUT4 #( + .INIT(16'h0c0a) + ) _0828_ ( + .I0(_0246_[0]), + .I1(_0132_[0]), + .I2(_0089_[3]), + .I3(_0089_[2]), + .O(_0285_[2]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0829_ ( + .I0(_0131_[0]), + .I1(_0131_[1]), + .I2(_0089_[1]), + .O(_0132_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0830_ ( + .I0(_0130_[0]), + .I1(_0130_[1]), + .I2(_0089_[0]), + .O(_0131_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0831_ ( + .I0(_0129_[0]), + .I1(_0129_[1]), + .I2(_0089_[0]), + .O(_0131_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0832_ ( + .I0(_0124_[0]), + .I1(_0124_[1]), + .I2(_0089_[1]), + .O(_0246_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0833_ ( + .I0(_0123_[0]), + .I1(_0123_[1]), + .I2(_0089_[0]), + .O(_0124_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0834_ ( + .I0(_0122_[0]), + .I1(_0122_[1]), + .I2(_0089_[0]), + .O(_0124_[0]) + ); + CC_LUT3 #( + .INIT(8'h01) + ) _0835_ ( + .I0(_0302_[0]), + .I1(_0302_[1]), + .I2(_0089_[4]), + .O(_0303_[0]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0836_ ( + .I0(_0247_[0]), + .I1(_0247_[1]), + .I2(_0089_[3]), + .O(_0302_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0837_ ( + .I0(_0121_[0]), + .I1(_0121_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0247_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0838_ ( + .I0(_0120_[0]), + .I1(_0120_[1]), + .I2(_0089_[0]), + .O(_0121_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0839_ ( + .I0(_0119_[0]), + .I1(_0119_[1]), + .I2(_0089_[0]), + .O(_0121_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0840_ ( + .I0(_0116_[0]), + .I1(_0116_[1]), + .I2(_0089_[2]), + .I3(_0089_[1]), + .O(_0247_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0841_ ( + .I0(_0115_[0]), + .I1(_0115_[1]), + .I2(_0089_[0]), + .O(_0116_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0842_ ( + .I0(_0114_[0]), + .I1(_0114_[1]), + .I2(_0089_[0]), + .O(_0116_[0]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0843_ ( + .I0(_0248_[0]), + .I1(_0248_[1]), + .I2(_0089_[3]), + .O(_0302_[1]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0844_ ( + .I0(_0113_[0]), + .I1(_0113_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0248_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0845_ ( + .I0(_0101_[1]), + .I1(_0112_[1]), + .I2(_0089_[0]), + .O(_0113_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0846_ ( + .I0(_0100_[1]), + .I1(_0101_[0]), + .I2(_0089_[0]), + .O(_0113_[0]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0847_ ( + .I0(_0117_[1]), + .I1(_0117_[0]), + .I2(_0089_[2]), + .O(_0248_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0848_ ( + .I0(_0104_[1]), + .I1(_0100_[0]), + .I2(_0089_[0]), + .I3(_0089_[1]), + .O(_0117_[0]) + ); + CC_LUT4 #( + .INIT(16'h030a) + ) _0849_ ( + .I0(_0105_[0]), + .I1(_0104_[0]), + .I2(_0089_[1]), + .I3(_0089_[0]), + .O(_0117_[1]) + ); + CC_LUT3 #( + .INIT(8'hd0) + ) _0850_ ( + .I0(_0098_[2]), + .I1(_0301_[1]), + .I2(_0371_[2]), + .O(_0372_[1]) + ); + CC_LUT4 #( + .INIT(16'ha333) + ) _0851_ ( + .I0(_0240_[2]), + .I1(_0105_[0]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0301_[1]) + ); + CC_LUT4 #( + .INIT(16'ha333) + ) _0852_ ( + .I0(_0105_[1]), + .I1(_0105_[0]), + .I2(_0089_[2]), + .I3(_0089_[1]), + .O(_0240_[2]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0853_ ( + .I0(_0104_[0]), + .I1(_0104_[1]), + .I2(_0089_[0]), + .O(_0105_[1]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0854_ ( + .I0(aluPlus[1]), + .I1(aluMinus[1]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0281_[2]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0855_ ( + .I0(_0370_[0]), + .I1(_0370_[1]), + .O(_0372_[3]) + ); + CC_LUT4 #( + .INIT(16'h7077) + ) _0856_ ( + .I0(_0151_[1]), + .I1(PCplusImm[1]), + .I2(_0369_[2]), + .I3(_0149_[1]), + .O(_0370_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _0857_ ( + .I0(Jimm[13]), + .I1(_0367_[0]), + .I2(_0368_[2]), + .I3(_0368_[3]), + .O(_0369_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0858_ ( + .I0(_0243_[0]), + .I1(_0243_[1]), + .I2(loadstore_addr[1]), + .I3(_0145_[3]), + .O(_0368_[2]) + ); + CC_LUT4 #( + .INIT(16'h0c0a) + ) _0859_ ( + .I0(_0367_[0]), + .I1(_0334_[0]), + .I2(_0144_[2]), + .I3(loadstore_addr[1]), + .O(_0368_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0860_ ( + .I0(PC[1]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[1]), + .O(_0370_[1]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _0861_ ( + .I0(_0279_[0]), + .I1(_0279_[1]), + .I2(_0163_[3]), + .O(_0280_[0]) + ); + CC_LUT4 #( + .INIT(16'hf100) + ) _0862_ ( + .I0(_0188_[1]), + .I1(_0089_[3]), + .I2(_0278_[2]), + .I3(_0089_[4]), + .O(_0279_[1]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0863_ ( + .I0(_0266_[1]), + .I1(_0277_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0278_[2]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0864_ ( + .I0(_0276_[0]), + .I1(_0276_[1]), + .I2(_0089_[1]), + .O(_0277_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0865_ ( + .I0(_0137_[1]), + .I1(_0275_[1]), + .I2(_0089_[0]), + .O(_0276_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0866_ ( + .I0(_0176_[1]), + .I1(_0265_[1]), + .I2(_0089_[1]), + .O(_0266_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0867_ ( + .I0(_0187_[0]), + .I1(_0187_[1]), + .I2(_0089_[2]), + .O(_0188_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0868_ ( + .I0(_0175_[1]), + .I1(_0176_[0]), + .I2(_0089_[1]), + .O(_0187_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0869_ ( + .I0(_0173_[1]), + .I1(_0175_[0]), + .I2(_0089_[1]), + .O(_0187_[0]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0870_ ( + .I0(_0207_[0]), + .I1(_0207_[1]), + .I2(_0089_[4]), + .O(_0279_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0871_ ( + .I0(_0186_[0]), + .I1(_0186_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0207_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0872_ ( + .I0(_0172_[1]), + .I1(_0173_[0]), + .I2(_0089_[1]), + .O(_0186_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0873_ ( + .I0(_0179_[1]), + .I1(_0172_[0]), + .I2(_0089_[1]), + .O(_0186_[0]) + ); + CC_LUT4 #( + .INIT(16'h00f1) + ) _0874_ ( + .I0(_0106_[1]), + .I1(_0089_[2]), + .I2(_0106_[2]), + .I3(_0089_[3]), + .O(_0207_[0]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _0875_ ( + .I0(_0105_[0]), + .I1(_0105_[1]), + .I2(_0089_[1]), + .O(_0106_[1]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0876_ ( + .I0(_0103_[0]), + .I1(_0103_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0106_[2]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0877_ ( + .I0(_0100_[0]), + .I1(_0100_[1]), + .I2(_0089_[0]), + .O(_0103_[0]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _0878_ ( + .I0(_0270_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0098_[2]), + .O(_0271_[2]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _0879_ ( + .I0(_0105_[0]), + .I1(_0118_[2]), + .I2(_0089_[3]), + .O(_0270_[0]) + ); + CC_LUT4 #( + .INIT(16'h110f) + ) _0880_ ( + .I0(_0117_[0]), + .I1(_0117_[1]), + .I2(_0105_[0]), + .I3(_0089_[2]), + .O(_0118_[2]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0881_ ( + .I0(_0089_[4]), + .I1(_0105_[0]), + .O(_0163_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0882_ ( + .I0(aluPlus[2]), + .I1(aluMinus[2]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0271_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _0883_ ( + .I0(PCplusImm[2]), + .I1(_0151_[1]), + .I2(_0274_[2]), + .O(_0280_[3]) + ); + CC_LUT4 #( + .INIT(16'h4f00) + ) _0884_ ( + .I0(_0273_[0]), + .I1(_0273_[1]), + .I2(_0149_[1]), + .I3(_0273_[3]), + .O(_0274_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0885_ ( + .I0(PCplus4[2]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[2]), + .O(_0273_[3]) + ); + CC_LUT4 #( + .INIT(16'h0c0a) + ) _0886_ ( + .I0(_0272_[0]), + .I1(_0204_[0]), + .I2(_0144_[2]), + .I3(loadstore_addr[1]), + .O(_0273_[0]) + ); + CC_LUT4 #( + .INIT(16'h7077) + ) _0887_ ( + .I0(_0272_[0]), + .I1(Jimm[13]), + .I2(_0236_[0]), + .I3(_0145_[3]), + .O(_0273_[1]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0888_ ( + .I0(_0235_[0]), + .I1(_0235_[1]), + .I2(loadstore_addr[1]), + .O(_0236_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0889_ ( + .I0(_0141_[0]), + .I1(_0141_[1]), + .I2(_0141_[2]), + .I3(_0089_[4]), + .O(_0142_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0890_ ( + .I0(_0140_[0]), + .I1(_0140_[1]), + .I2(_0089_[3]), + .I3(_0089_[2]), + .O(_0141_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0891_ ( + .I0(_0124_[1]), + .I1(_0131_[0]), + .I2(_0089_[1]), + .O(_0140_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0892_ ( + .I0(_0121_[1]), + .I1(_0124_[0]), + .I2(_0089_[1]), + .O(_0140_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0893_ ( + .I0(_0139_[0]), + .I1(_0139_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0141_[0]) + ); + CC_LUT3 #( + .INIT(8'hac) + ) _0894_ ( + .I0(_0138_[0]), + .I1(_0128_[1]), + .I2(_0089_[1]), + .O(_0139_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0895_ ( + .I0(_0131_[1]), + .I1(_0128_[0]), + .I2(_0089_[1]), + .O(_0139_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0896_ ( + .I0(_0136_[0]), + .I1(_0136_[1]), + .I2(_0136_[2]), + .I3(_0089_[3]), + .O(_0141_[2]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0897_ ( + .I0(_0116_[1]), + .I1(_0121_[0]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0136_[1]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0898_ ( + .I0(_0113_[1]), + .I1(_0116_[0]), + .I2(_0089_[2]), + .I3(_0089_[1]), + .O(_0136_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0899_ ( + .I0(_0135_[0]), + .I1(_0135_[1]), + .I2(_0135_[2]), + .I3(_0089_[2]), + .O(_0136_[2]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0900_ ( + .I0(_0100_[1]), + .I1(_0101_[0]), + .I2(_0089_[0]), + .I3(_0089_[1]), + .O(_0135_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0901_ ( + .I0(_0104_[1]), + .I1(_0100_[0]), + .I2(_0089_[1]), + .I3(_0089_[0]), + .O(_0135_[1]) + ); + CC_LUT4 #( + .INIT(16'ha333) + ) _0902_ ( + .I0(_0110_[0]), + .I1(_0105_[0]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0111_[0]) + ); + CC_LUT4 #( + .INIT(16'h110f) + ) _0903_ ( + .I0(_0109_[0]), + .I1(_0109_[1]), + .I2(_0105_[0]), + .I3(_0089_[2]), + .O(_0110_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0904_ ( + .I0(aluPlus[3]), + .I1(aluMinus[3]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0111_[2]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _0905_ ( + .I0(PCplusImm[3]), + .I1(_0151_[1]), + .I2(_0151_[2]), + .O(_0152_[3]) + ); + CC_LUT3 #( + .INIT(8'hb0) + ) _0906_ ( + .I0(_0149_[0]), + .I1(_0149_[1]), + .I2(_0149_[2]), + .O(_0151_[2]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _0907_ ( + .I0(Jimm[13]), + .I1(_0144_[0]), + .I2(_0146_[2]), + .I3(_0146_[3]), + .O(_0149_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0908_ ( + .I0(_0145_[0]), + .I1(_0145_[1]), + .I2(loadstore_addr[1]), + .I3(_0145_[3]), + .O(_0146_[2]) + ); + CC_LUT4 #( + .INIT(16'h0c0a) + ) _0909_ ( + .I0(_0144_[0]), + .I1(_0144_[1]), + .I2(_0144_[2]), + .I3(loadstore_addr[1]), + .O(_0146_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0910_ ( + .I0(PCplus4[3]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[3]), + .O(_0149_[2]) + ); + CC_LUT3 #( + .INIT(8'h4f) + ) _0911_ ( + .I0(_0366_[0]), + .I1(_0152_[2]), + .I2(_0366_[2]), + .O(writeBackData[4]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _0912_ ( + .I0(_0163_[3]), + .I1(_0316_[1]), + .I2(_0365_[2]), + .I3(_0365_[3]), + .O(_0366_[0]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _0913_ ( + .I0(_0313_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0098_[2]), + .O(_0365_[2]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _0914_ ( + .I0(_0105_[0]), + .I1(_0136_[2]), + .I2(_0089_[3]), + .O(_0313_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0915_ ( + .I0(_0315_[0]), + .I1(_0315_[1]), + .I2(_0193_[0]), + .I3(_0089_[4]), + .O(_0316_[1]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0916_ ( + .I0(_0177_[1]), + .I1(_0289_[0]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0315_[1]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0917_ ( + .I0(_0174_[1]), + .I1(_0177_[0]), + .I2(_0089_[3]), + .I3(_0089_[2]), + .O(_0315_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0918_ ( + .I0(_0192_[0]), + .I1(_0192_[1]), + .I2(_0110_[0]), + .I3(_0089_[3]), + .O(_0193_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0919_ ( + .I0(_0172_[0]), + .I1(_0172_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0192_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0920_ ( + .I0(_0103_[1]), + .I1(_0179_[1]), + .I2(_0089_[2]), + .I3(_0089_[1]), + .O(_0192_[1]) + ); + CC_LUT4 #( + .INIT(16'h000d) + ) _0921_ ( + .I0(_0097_[3]), + .I1(_0364_[1]), + .I2(_0364_[2]), + .I3(_0364_[3]), + .O(_0365_[3]) + ); + CC_LUT4 #( + .INIT(16'hec0e) + ) _0922_ ( + .I0(_0294_[1]), + .I1(_0295_[2]), + .I2(_0089_[4]), + .I3(aluIn1[4]), + .O(_0364_[2]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0923_ ( + .I0(_0089_[4]), + .I1(_0294_[0]), + .I2(aluIn1[4]), + .O(_0364_[3]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0924_ ( + .I0(aluPlus[4]), + .I1(aluMinus[4]), + .I2(_0097_[2]), + .O(_0364_[1]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _0925_ ( + .I0(PCplusImm[4]), + .I1(_0151_[1]), + .I2(_0363_[2]), + .O(_0366_[2]) + ); + CC_LUT3 #( + .INIT(8'hb0) + ) _0926_ ( + .I0(_0362_[0]), + .I1(_0149_[1]), + .I2(_0362_[2]), + .O(_0363_[2]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _0927_ ( + .I0(Jimm[13]), + .I1(_0360_[0]), + .I2(_0361_[2]), + .I3(_0361_[3]), + .O(_0362_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0928_ ( + .I0(_0223_[0]), + .I1(_0223_[1]), + .I2(loadstore_addr[1]), + .I3(_0145_[3]), + .O(_0361_[2]) + ); + CC_LUT4 #( + .INIT(16'h0c0a) + ) _0929_ ( + .I0(_0360_[0]), + .I1(_0331_[0]), + .I2(_0144_[2]), + .I3(loadstore_addr[1]), + .O(_0361_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0930_ ( + .I0(PCplus4[4]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[4]), + .O(_0362_[2]) + ); + CC_LUT4 #( + .INIT(16'hee0f) + ) _0931_ ( + .I0(_0133_[0]), + .I1(_0133_[1]), + .I2(_0133_[2]), + .I3(_0089_[4]), + .O(_0134_[1]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0932_ ( + .I0(_0132_[0]), + .I1(_0132_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0133_[1]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0933_ ( + .I0(_0128_[0]), + .I1(_0128_[1]), + .I2(_0089_[1]), + .O(_0132_[1]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0934_ ( + .I0(_0125_[0]), + .I1(_0125_[1]), + .I2(_0089_[3]), + .O(_0133_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0935_ ( + .I0(_0124_[0]), + .I1(_0124_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0125_[1]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0936_ ( + .I0(_0121_[0]), + .I1(_0121_[1]), + .I2(_0089_[2]), + .I3(_0089_[1]), + .O(_0125_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0937_ ( + .I0(_0118_[0]), + .I1(_0118_[1]), + .I2(_0118_[2]), + .I3(_0089_[3]), + .O(_0133_[2]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0938_ ( + .I0(_0116_[0]), + .I1(_0116_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0118_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0939_ ( + .I0(_0113_[0]), + .I1(_0113_[1]), + .I2(_0089_[2]), + .I3(_0089_[1]), + .O(_0118_[1]) + ); + CC_LUT4 #( + .INIT(16'ha333) + ) _0940_ ( + .I0(_0107_[0]), + .I1(_0105_[0]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0108_[0]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0941_ ( + .I0(_0089_[2]), + .I1(_0106_[1]), + .I2(_0106_[2]), + .O(_0107_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0942_ ( + .I0(aluPlus[5]), + .I1(aluMinus[5]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0108_[2]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0943_ ( + .I0(_0157_[0]), + .I1(_0157_[1]), + .O(_0158_[3]) + ); + CC_LUT4 #( + .INIT(16'h7077) + ) _0944_ ( + .I0(_0151_[1]), + .I1(PCplusImm[5]), + .I2(_0156_[2]), + .I3(_0149_[1]), + .O(_0157_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _0945_ ( + .I0(Jimm[13]), + .I1(_0153_[0]), + .I2(_0155_[2]), + .I3(_0155_[3]), + .O(_0156_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0946_ ( + .I0(_0154_[0]), + .I1(_0154_[1]), + .I2(loadstore_addr[1]), + .I3(_0145_[3]), + .O(_0155_[2]) + ); + CC_LUT4 #( + .INIT(16'h0c0a) + ) _0947_ ( + .I0(_0153_[0]), + .I1(_0153_[1]), + .I2(_0144_[2]), + .I3(loadstore_addr[1]), + .O(_0155_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0948_ ( + .I0(PCplus4[5]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[5]), + .O(_0157_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0949_ ( + .I0(_0268_[0]), + .I1(_0163_[3]), + .O(_0269_[0]) + ); + CC_LUT4 #( + .INIT(16'hee0f) + ) _0950_ ( + .I0(_0267_[0]), + .I1(_0267_[1]), + .I2(_0241_[0]), + .I3(_0089_[4]), + .O(_0268_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0951_ ( + .I0(_0186_[1]), + .I1(_0187_[0]), + .I2(_0089_[3]), + .I3(_0089_[2]), + .O(_0267_[1]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0952_ ( + .I0(_0187_[1]), + .I1(_0266_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0267_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0953_ ( + .I0(_0240_[0]), + .I1(_0240_[1]), + .I2(_0240_[2]), + .I3(_0089_[3]), + .O(_0241_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0954_ ( + .I0(_0179_[1]), + .I1(_0172_[0]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0240_[0]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0955_ ( + .I0(_0103_[0]), + .I1(_0103_[1]), + .I2(_0089_[2]), + .I3(_0089_[1]), + .O(_0240_[1]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _0956_ ( + .I0(_0249_[2]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0098_[2]), + .O(_0260_[2]) + ); + CC_LUT4 #( + .INIT(16'h110f) + ) _0957_ ( + .I0(_0248_[0]), + .I1(_0248_[1]), + .I2(_0105_[0]), + .I3(_0089_[3]), + .O(_0249_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0958_ ( + .I0(aluPlus[6]), + .I1(aluMinus[6]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0260_[3]) + ); + CC_LUT4 #( + .INIT(16'h0b00) + ) _0959_ ( + .I0(_0264_[0]), + .I1(_0149_[1]), + .I2(_0264_[2]), + .I3(_0264_[3]), + .O(_0269_[3]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _0960_ ( + .I0(Jimm[13]), + .I1(_0261_[0]), + .I2(_0263_[2]), + .I3(_0263_[3]), + .O(_0264_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0961_ ( + .I0(_0262_[0]), + .I1(_0262_[1]), + .I2(loadstore_addr[1]), + .I3(_0145_[3]), + .O(_0263_[2]) + ); + CC_LUT4 #( + .INIT(16'h0c0a) + ) _0962_ ( + .I0(_0261_[0]), + .I1(_0261_[1]), + .I2(_0144_[2]), + .I3(loadstore_addr[1]), + .O(_0263_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0963_ ( + .I0(_0143_[2]), + .I1(cycles[6]), + .I2(_0151_[1]), + .I3(PCplusImm[6]), + .O(_0264_[3]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0964_ ( + .I0(_0143_[1]), + .I1(PCplus4[6]), + .O(_0264_[2]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _0965_ ( + .I0(_0181_[1]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0098_[2]), + .O(_0255_[2]) + ); + CC_LUT4 #( + .INIT(16'h110f) + ) _0966_ ( + .I0(_0180_[0]), + .I1(_0180_[1]), + .I2(_0105_[0]), + .I3(_0089_[3]), + .O(_0181_[1]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0967_ ( + .I0(_0254_[0]), + .I1(_0254_[1]), + .I2(_0163_[0]), + .I3(_0089_[4]), + .O(_0255_[0]) + ); + CC_LUT4 #( + .INIT(16'h5300) + ) _0968_ ( + .I0(_0139_[0]), + .I1(_0140_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0254_[1]) + ); + CC_LUT4 #( + .INIT(16'h0305) + ) _0969_ ( + .I0(_0211_[0]), + .I1(_0140_[0]), + .I2(_0089_[3]), + .I3(_0089_[2]), + .O(_0254_[0]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0970_ ( + .I0(_0116_[1]), + .I1(_0121_[0]), + .I2(_0089_[1]), + .O(_0211_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0971_ ( + .I0(_0162_[0]), + .I1(_0162_[1]), + .I2(_0162_[2]), + .I3(_0089_[3]), + .O(_0163_[0]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _0972_ ( + .I0(_0105_[0]), + .I1(_0135_[2]), + .I2(_0089_[2]), + .O(_0162_[2]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0973_ ( + .I0(_0113_[1]), + .I1(_0116_[0]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0162_[0]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0974_ ( + .I0(_0135_[1]), + .I1(_0135_[0]), + .I2(_0089_[2]), + .O(_0162_[1]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0975_ ( + .I0(aluPlus[7]), + .I1(aluMinus[7]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0255_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _0976_ ( + .I0(PCplusImm[7]), + .I1(_0151_[1]), + .I2(_0257_[2]), + .O(_0258_[3]) + ); + CC_LUT4 #( + .INIT(16'h8f00) + ) _0977_ ( + .I0(_0224_[0]), + .I1(_0256_[1]), + .I2(_0149_[1]), + .I3(_0256_[3]), + .O(_0257_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0978_ ( + .I0(PCplus4[7]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[7]), + .O(_0256_[3]) + ); + CC_LUT4 #( + .INIT(16'hb0bb) + ) _0979_ ( + .I0(_0167_[1]), + .I1(_0167_[2]), + .I2(_0167_[0]), + .I3(_0145_[3]), + .O(_0224_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0980_ ( + .I0(_0166_[0]), + .I1(_0166_[1]), + .I2(loadstore_addr[1]), + .O(_0167_[1]) + ); + CC_LUT3 #( + .INIT(8'h01) + ) _0981_ ( + .I0(loadstore_addr[0]), + .I1(Jimm[12]), + .I2(Jimm[13]), + .O(_0167_[2]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0982_ ( + .I0(_0165_[0]), + .I1(_0165_[1]), + .I2(loadstore_addr[1]), + .O(_0167_[0]) + ); + CC_LUT4 #( + .INIT(16'h0fbb) + ) _0983_ ( + .I0(_0167_[1]), + .I1(Jimm[12]), + .I2(_0166_[0]), + .I3(Jimm[13]), + .O(_0256_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _0984_ ( + .I0(_0359_[0]), + .I1(_0359_[1]), + .I2(_0152_[2]), + .I3(_0359_[3]), + .O(writeBackData[8]) + ); + CC_LUT4 #( + .INIT(16'h0b00) + ) _0985_ ( + .I0(_0089_[4]), + .I1(_0181_[1]), + .I2(_0181_[2]), + .I3(_0163_[3]), + .O(_0359_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _0986_ ( + .I0(_0178_[0]), + .I1(_0178_[1]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0181_[2]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _0987_ ( + .I0(_0174_[0]), + .I1(_0174_[1]), + .I2(_0089_[2]), + .O(_0178_[0]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _0988_ ( + .I0(_0105_[0]), + .I1(_0163_[0]), + .I2(_0089_[4]), + .O(_0253_[0]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _0989_ ( + .I0(aluPlus[8]), + .I1(aluMinus[8]), + .I2(_0097_[2]), + .O(_0252_[0]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _0990_ ( + .I0(PCplusImm[8]), + .I1(_0151_[1]), + .I2(_0358_[2]), + .O(_0359_[3]) + ); + CC_LUT4 #( + .INIT(16'h4f00) + ) _0991_ ( + .I0(_0225_[2]), + .I1(_0357_[1]), + .I2(_0149_[1]), + .I3(_0357_[3]), + .O(_0358_[2]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0992_ ( + .I0(_0224_[0]), + .I1(_0097_[3]), + .O(_0225_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0993_ ( + .I0(PCplus4[8]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[8]), + .O(_0357_[3]) + ); + CC_LUT4 #( + .INIT(16'h0fbb) + ) _0994_ ( + .I0(_0356_[0]), + .I1(Jimm[12]), + .I2(_0355_[0]), + .I3(Jimm[13]), + .O(_0357_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0995_ ( + .I0(_0250_[0]), + .I1(_0163_[3]), + .O(_0251_[0]) + ); + CC_LUT4 #( + .INIT(16'h11f0) + ) _0996_ ( + .I0(_0249_[0]), + .I1(_0249_[1]), + .I2(_0249_[2]), + .I3(_0089_[4]), + .O(_0250_[0]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _0997_ ( + .I0(_0247_[0]), + .I1(_0247_[1]), + .I2(_0089_[3]), + .O(_0249_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _0998_ ( + .I0(_0246_[0]), + .I1(_0132_[0]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0249_[1]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _0999_ ( + .I0(_0241_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0098_[2]), + .O(_0242_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1000_ ( + .I0(aluPlus[9]), + .I1(aluMinus[9]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0242_[3]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1001_ ( + .I0(_0149_[1]), + .I1(_0245_[1]), + .I2(_0245_[2]), + .I3(_0245_[3]), + .O(_0251_[3]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1002_ ( + .I0(Jimm[13]), + .I1(_0243_[0]), + .I2(_0225_[2]), + .I3(_0244_[3]), + .O(_0245_[1]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1003_ ( + .I0(_0243_[0]), + .I1(_0243_[1]), + .I2(loadstore_addr[1]), + .I3(_0134_[0]), + .O(_0244_[3]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _1004_ ( + .I0(_0151_[1]), + .I1(PCplusImm[9]), + .O(_0245_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1005_ ( + .I0(PCplus4[9]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[9]), + .O(_0245_[3]) + ); + CC_LUT4 #( + .INIT(16'h0b00) + ) _1006_ ( + .I0(_0089_[4]), + .I1(_0189_[1]), + .I2(_0189_[2]), + .I3(_0163_[3]), + .O(_0239_[0]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _1007_ ( + .I0(_0105_[0]), + .I1(_0107_[0]), + .I2(_0089_[3]), + .O(_0189_[1]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1008_ ( + .I0(_0188_[0]), + .I1(_0188_[1]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0189_[2]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _1009_ ( + .I0(_0186_[0]), + .I1(_0186_[1]), + .I2(_0089_[2]), + .O(_0188_[0]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1010_ ( + .I0(_0133_[2]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0098_[2]), + .O(_0234_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1011_ ( + .I0(aluPlus[10]), + .I1(aluMinus[10]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0234_[3]) + ); + CC_LUT4 #( + .INIT(16'h4f00) + ) _1012_ ( + .I0(_0225_[2]), + .I1(_0238_[1]), + .I2(_0149_[1]), + .I3(_0238_[3]), + .O(_0239_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _1013_ ( + .I0(PCplusImm[10]), + .I1(_0151_[1]), + .I2(_0237_[2]), + .O(_0238_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1014_ ( + .I0(PCplus4[10]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[10]), + .O(_0237_[2]) + ); + CC_LUT4 #( + .INIT(16'h0fbb) + ) _1015_ ( + .I0(_0236_[0]), + .I1(Jimm[12]), + .I2(_0235_[0]), + .I3(Jimm[13]), + .O(_0238_[1]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1016_ ( + .I0(_0194_[0]), + .I1(_0194_[1]), + .I2(_0194_[2]), + .I3(_0163_[3]), + .O(_0233_[0]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _1017_ ( + .I0(_0140_[0]), + .I1(_0140_[1]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0194_[1]) + ); + CC_LUT4 #( + .INIT(16'hf100) + ) _1018_ ( + .I0(_0136_[0]), + .I1(_0136_[1]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0194_[0]) + ); + CC_LUT4 #( + .INIT(16'h0c05) + ) _1019_ ( + .I0(_0105_[0]), + .I1(_0136_[2]), + .I2(_0089_[4]), + .I3(_0089_[3]), + .O(_0194_[2]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1020_ ( + .I0(_0193_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0098_[2]), + .O(_0232_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1021_ ( + .I0(aluPlus[11]), + .I1(aluMinus[11]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0232_[3]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1022_ ( + .I0(Jimm[13]), + .I1(_0145_[0]), + .I2(_0225_[2]), + .I3(_0230_[3]), + .O(_0231_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1023_ ( + .I0(_0145_[0]), + .I1(_0145_[1]), + .I2(loadstore_addr[1]), + .I3(_0134_[0]), + .O(_0230_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _1024_ ( + .I0(PCplusImm[11]), + .I1(_0151_[1]), + .I2(_0229_[2]), + .O(_0231_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1025_ ( + .I0(PCplus4[11]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[11]), + .O(_0229_[2]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1026_ ( + .I0(_0200_[0]), + .I1(_0098_[2]), + .O(_0228_[0]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _1027_ ( + .I0(_0105_[0]), + .I1(_0141_[2]), + .I2(_0089_[4]), + .O(_0200_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1028_ ( + .I0(_0196_[0]), + .I1(_0196_[1]), + .I2(_0196_[2]), + .I3(_0163_[3]), + .O(_0222_[2]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _1029_ ( + .I0(_0174_[1]), + .I1(_0177_[0]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0196_[1]) + ); + CC_LUT4 #( + .INIT(16'hf100) + ) _1030_ ( + .I0(_0192_[1]), + .I1(_0192_[0]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0196_[0]) + ); + CC_LUT4 #( + .INIT(16'h0c05) + ) _1031_ ( + .I0(_0105_[0]), + .I1(_0110_[0]), + .I2(_0089_[4]), + .I3(_0089_[3]), + .O(_0196_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1032_ ( + .I0(aluPlus[12]), + .I1(aluMinus[12]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0222_[3]) + ); + CC_LUT4 #( + .INIT(16'h7000) + ) _1033_ ( + .I0(Jimm[12]), + .I1(_0171_[1]), + .I2(_0227_[2]), + .I3(_0227_[3]), + .O(_0228_[3]) + ); + CC_LUT4 #( + .INIT(16'h7077) + ) _1034_ ( + .I0(_0151_[1]), + .I1(PCplusImm[12]), + .I2(_0226_[2]), + .I3(_0149_[1]), + .O(_0227_[2]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1035_ ( + .I0(Jimm[13]), + .I1(_0223_[0]), + .I2(_0225_[2]), + .I3(_0225_[3]), + .O(_0226_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1036_ ( + .I0(_0223_[0]), + .I1(_0223_[1]), + .I2(loadstore_addr[1]), + .I3(_0134_[0]), + .O(_0225_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1037_ ( + .I0(PCplus4[12]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[12]), + .O(_0227_[3]) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _1038_ ( + .I0(instr[6]), + .I1(instr[5]), + .I2(_0150_[2]), + .I3(instr[2]), + .O(_0171_[1]) + ); + CC_LUT3 #( + .INIT(8'h4f) + ) _1039_ ( + .I0(_0354_[0]), + .I1(_0152_[2]), + .I2(_0354_[2]), + .O(writeBackData[13]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1040_ ( + .I0(_0098_[2]), + .I1(_0208_[0]), + .I2(_0353_[2]), + .I3(_0353_[3]), + .O(_0354_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1041_ ( + .I0(_0202_[0]), + .I1(_0202_[1]), + .I2(_0202_[2]), + .I3(_0163_[3]), + .O(_0353_[2]) + ); + CC_LUT3 #( + .INIT(8'h0e) + ) _1042_ ( + .I0(_0118_[1]), + .I1(_0118_[0]), + .I2(_0089_[3]), + .O(_0202_[1]) + ); + CC_LUT4 #( + .INIT(16'h0c05) + ) _1043_ ( + .I0(_0105_[0]), + .I1(_0118_[2]), + .I2(_0089_[4]), + .I3(_0089_[3]), + .O(_0202_[2]) + ); + CC_LUT4 #( + .INIT(16'h1f00) + ) _1044_ ( + .I0(_0125_[0]), + .I1(_0125_[1]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0202_[0]) + ); + CC_LUT4 #( + .INIT(16'h001f) + ) _1045_ ( + .I0(_0207_[0]), + .I1(_0207_[1]), + .I2(_0089_[4]), + .I3(_0163_[2]), + .O(_0208_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1046_ ( + .I0(aluPlus[13]), + .I1(aluMinus[13]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0221_[2]) + ); + CC_LUT4 #( + .INIT(16'h7000) + ) _1047_ ( + .I0(cycles[13]), + .I1(_0143_[2]), + .I2(_0352_[2]), + .I3(_0352_[3]), + .O(_0354_[2]) + ); + CC_LUT4 #( + .INIT(16'h7077) + ) _1048_ ( + .I0(_0151_[1]), + .I1(PCplusImm[13]), + .I2(_0351_[2]), + .I3(_0149_[1]), + .O(_0352_[2]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1049_ ( + .I0(Jimm[13]), + .I1(_0154_[0]), + .I2(_0225_[2]), + .I3(_0350_[3]), + .O(_0351_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1050_ ( + .I0(_0154_[0]), + .I1(_0154_[1]), + .I2(loadstore_addr[1]), + .I3(_0134_[0]), + .O(_0350_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1051_ ( + .I0(PCplus4[13]), + .I1(_0143_[1]), + .I2(_0171_[1]), + .I3(Jimm[13]), + .O(_0352_[3]) + ); + CC_LUT3 #( + .INIT(8'h4f) + ) _1052_ ( + .I0(_0349_[0]), + .I1(_0152_[2]), + .I2(_0349_[2]), + .O(writeBackData[14]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1053_ ( + .I0(_0098_[2]), + .I1(_0340_[0]), + .I2(_0348_[2]), + .I3(_0348_[3]), + .O(_0349_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1054_ ( + .I0(_0338_[1]), + .I1(_0338_[0]), + .I2(_0338_[2]), + .I3(_0163_[3]), + .O(_0348_[2]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _1055_ ( + .I0(_0186_[1]), + .I1(_0187_[0]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0338_[0]) + ); + CC_LUT4 #( + .INIT(16'hf100) + ) _1056_ ( + .I0(_0240_[1]), + .I1(_0240_[0]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0338_[1]) + ); + CC_LUT4 #( + .INIT(16'h0c05) + ) _1057_ ( + .I0(_0105_[0]), + .I1(_0240_[2]), + .I2(_0089_[4]), + .I3(_0089_[3]), + .O(_0338_[2]) + ); + CC_LUT4 #( + .INIT(16'h001f) + ) _1058_ ( + .I0(_0302_[1]), + .I1(_0302_[0]), + .I2(_0089_[4]), + .I3(_0163_[2]), + .O(_0340_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1059_ ( + .I0(aluPlus[14]), + .I1(aluMinus[14]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0220_[2]) + ); + CC_LUT4 #( + .INIT(16'hd000) + ) _1060_ ( + .I0(_0149_[1]), + .I1(_0347_[1]), + .I2(_0347_[2]), + .I3(_0347_[3]), + .O(_0349_[2]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1061_ ( + .I0(Jimm[13]), + .I1(_0262_[0]), + .I2(_0225_[2]), + .I3(_0346_[3]), + .O(_0347_[1]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1062_ ( + .I0(_0262_[0]), + .I1(_0262_[1]), + .I2(loadstore_addr[1]), + .I3(_0134_[0]), + .O(_0346_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1063_ ( + .I0(_0143_[1]), + .I1(PCplus4[14]), + .I2(_0171_[1]), + .I3(Jimm[14]), + .O(_0347_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1064_ ( + .I0(_0143_[2]), + .I1(cycles[14]), + .I2(_0151_[1]), + .I3(PCplusImm[14]), + .O(_0347_[3]) + ); + CC_LUT3 #( + .INIT(8'h4f) + ) _1065_ ( + .I0(_0345_[0]), + .I1(_0152_[2]), + .I2(_0345_[2]), + .O(writeBackData[15]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1066_ ( + .I0(_0098_[2]), + .I1(_0217_[0]), + .I2(_0344_[2]), + .I3(_0344_[3]), + .O(_0345_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1067_ ( + .I0(_0212_[0]), + .I1(_0212_[1]), + .I2(_0212_[2]), + .I3(_0163_[3]), + .O(_0344_[2]) + ); + CC_LUT4 #( + .INIT(16'h3500) + ) _1068_ ( + .I0(_0211_[0]), + .I1(_0140_[0]), + .I2(_0089_[2]), + .I3(_0089_[3]), + .O(_0212_[1]) + ); + CC_LUT4 #( + .INIT(16'hf100) + ) _1069_ ( + .I0(_0162_[1]), + .I1(_0162_[0]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0212_[0]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1070_ ( + .I0(_0089_[4]), + .I1(_0210_[1]), + .O(_0212_[2]) + ); + CC_LUT4 #( + .INIT(16'h001f) + ) _1071_ ( + .I0(_0216_[0]), + .I1(_0216_[1]), + .I2(_0089_[4]), + .I3(_0163_[2]), + .O(_0217_[0]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1072_ ( + .I0(aluPlus[15]), + .I1(aluMinus[15]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0219_[2]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _1073_ ( + .I0(_0343_[0]), + .I1(_0343_[1]), + .I2(_0343_[2]), + .O(_0345_[2]) + ); + CC_LUT3 #( + .INIT(8'hd0) + ) _1074_ ( + .I0(_0342_[0]), + .I1(_0225_[2]), + .I2(_0149_[1]), + .O(_0343_[0]) + ); + CC_LUT4 #( + .INIT(16'h0fbb) + ) _1075_ ( + .I0(_0167_[0]), + .I1(Jimm[12]), + .I2(_0165_[0]), + .I3(Jimm[13]), + .O(_0342_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1076_ ( + .I0(PCplus4[15]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[15]), + .O(_0343_[1]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1077_ ( + .I0(_0171_[1]), + .I1(Jimm[15]), + .I2(_0151_[1]), + .I3(PCplusImm[15]), + .O(_0343_[2]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1078_ ( + .I0(_0217_[0]), + .I1(_0163_[3]), + .O(_0218_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1079_ ( + .I0(_0212_[0]), + .I1(_0212_[1]), + .I2(_0212_[2]), + .I3(_0098_[2]), + .O(_0213_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1080_ ( + .I0(aluPlus[16]), + .I1(aluMinus[16]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0213_[3]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _1081_ ( + .I0(_0215_[0]), + .I1(_0215_[1]), + .I2(_0215_[2]), + .O(_0218_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1082_ ( + .I0(_0214_[0]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0215_[0]) + ); + CC_LUT3 #( + .INIT(8'h01) + ) _1083_ ( + .I0(_0168_[0]), + .I1(Jimm[14]), + .I2(Jimm[13]), + .O(_0169_[2]) + ); + CC_LUT3 #( + .INIT(8'hca) + ) _1084_ ( + .I0(_0167_[0]), + .I1(_0167_[1]), + .I2(_0167_[2]), + .O(_0168_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1085_ ( + .I0(PCplus4[16]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[16]), + .O(_0215_[1]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1086_ ( + .I0(_0171_[1]), + .I1(Jimm[16]), + .I2(_0151_[1]), + .I3(PCplusImm[16]), + .O(_0215_[2]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1087_ ( + .I0(_0341_[0]), + .I1(_0341_[1]), + .I2(_0152_[2]), + .I3(_0341_[3]), + .O(writeBackData[17]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1088_ ( + .I0(_0340_[0]), + .I1(_0163_[3]), + .O(_0341_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1089_ ( + .I0(_0098_[2]), + .I1(_0339_[1]), + .I2(_0339_[2]), + .I3(_0339_[3]), + .O(_0341_[1]) + ); + CC_LUT3 #( + .INIT(8'hf4) + ) _1090_ ( + .I0(_0338_[0]), + .I1(_0338_[1]), + .I2(_0338_[2]), + .O(_0339_[1]) + ); + CC_LUT4 #( + .INIT(16'hec0e) + ) _1091_ ( + .I0(_0294_[1]), + .I1(_0295_[2]), + .I2(_0089_[17]), + .I3(aluIn1[17]), + .O(_0339_[2]) + ); + CC_LUT4 #( + .INIT(16'h00bf) + ) _1092_ ( + .I0(_0089_[17]), + .I1(_0294_[0]), + .I2(aluIn1[17]), + .I3(_0337_[3]), + .O(_0339_[3]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1093_ ( + .I0(aluPlus[17]), + .I1(aluMinus[17]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0337_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _1094_ ( + .I0(cycles[17]), + .I1(_0143_[2]), + .I2(_0336_[2]), + .O(_0341_[3]) + ); + CC_LUT4 #( + .INIT(16'h0700) + ) _1095_ ( + .I0(PCplusImm[17]), + .I1(_0151_[1]), + .I2(_0335_[2]), + .I3(_0335_[3]), + .O(_0336_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1096_ ( + .I0(_0334_[0]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0335_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1097_ ( + .I0(PCplus4[17]), + .I1(_0143_[1]), + .I2(_0171_[1]), + .I3(Jimm[17]), + .O(_0335_[3]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1098_ ( + .I0(_0208_[0]), + .I1(_0163_[3]), + .O(_0209_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1099_ ( + .I0(_0202_[0]), + .I1(_0202_[1]), + .I2(_0202_[2]), + .I3(_0098_[2]), + .O(_0203_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1100_ ( + .I0(aluPlus[18]), + .I1(aluMinus[18]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0203_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _1101_ ( + .I0(PCplusImm[18]), + .I1(_0151_[1]), + .I2(_0206_[2]), + .O(_0209_[3]) + ); + CC_LUT4 #( + .INIT(16'h0700) + ) _1102_ ( + .I0(PCplus4[18]), + .I1(_0143_[1]), + .I2(_0205_[2]), + .I3(_0205_[3]), + .O(_0206_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1103_ ( + .I0(_0204_[0]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0205_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1104_ ( + .I0(_0171_[1]), + .I1(Jimm[18]), + .I2(_0143_[2]), + .I3(cycles[18]), + .O(_0205_[3]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1105_ ( + .I0(_0200_[0]), + .I1(_0163_[3]), + .O(_0201_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1106_ ( + .I0(_0196_[0]), + .I1(_0196_[1]), + .I2(_0196_[2]), + .I3(_0098_[2]), + .O(_0197_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1107_ ( + .I0(aluPlus[19]), + .I1(aluMinus[19]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0197_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _1108_ ( + .I0(cycles[19]), + .I1(_0143_[2]), + .I2(_0199_[2]), + .O(_0201_[3]) + ); + CC_LUT4 #( + .INIT(16'h0700) + ) _1109_ ( + .I0(Jimm[19]), + .I1(_0171_[1]), + .I2(_0198_[2]), + .I3(_0198_[3]), + .O(_0199_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1110_ ( + .I0(_0144_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0198_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1111_ ( + .I0(PCplus4[19]), + .I1(_0143_[1]), + .I2(_0151_[1]), + .I3(PCplusImm[19]), + .O(_0198_[3]) + ); + CC_LUT4 #( + .INIT(16'hf8ff) + ) _1112_ ( + .I0(PCplus4[20]), + .I1(_0143_[1]), + .I2(_0333_[2]), + .I3(_0333_[3]), + .O(writeBackData[20]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1113_ ( + .I0(_0194_[0]), + .I1(_0194_[1]), + .I2(_0194_[2]), + .I3(_0098_[2]), + .O(_0195_[0]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1114_ ( + .I0(_0193_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0195_[1]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1115_ ( + .I0(aluPlus[20]), + .I1(aluMinus[20]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0191_[2]) + ); + CC_LUT4 #( + .INIT(16'h0700) + ) _1116_ ( + .I0(PCplusImm[20]), + .I1(_0151_[1]), + .I2(_0332_[2]), + .I3(_0332_[3]), + .O(_0333_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1117_ ( + .I0(_0331_[0]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0332_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1118_ ( + .I0(Iimm[0]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[20]), + .O(_0332_[3]) + ); + CC_LUT4 #( + .INIT(16'h0b00) + ) _1119_ ( + .I0(_0089_[4]), + .I1(_0189_[1]), + .I2(_0189_[2]), + .I3(_0098_[2]), + .O(_0190_[0]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1120_ ( + .I0(_0133_[2]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0184_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1121_ ( + .I0(aluPlus[21]), + .I1(aluMinus[21]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0184_[3]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _1122_ ( + .I0(_0185_[0]), + .I1(_0185_[1]), + .I2(_0185_[2]), + .O(_0190_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1123_ ( + .I0(_0153_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0185_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1124_ ( + .I0(_0143_[1]), + .I1(PCplus4[21]), + .I2(_0171_[1]), + .I3(Iimm[1]), + .O(_0185_[1]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1125_ ( + .I0(_0143_[2]), + .I1(cycles[21]), + .I2(_0151_[1]), + .I3(PCplusImm[21]), + .O(_0185_[2]) + ); + CC_LUT4 #( + .INIT(16'h2fff) + ) _1126_ ( + .I0(_0152_[2]), + .I1(_0330_[1]), + .I2(_0330_[2]), + .I3(_0330_[3]), + .O(writeBackData[22]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1127_ ( + .I0(_0098_[2]), + .I1(_0250_[0]), + .I2(_0329_[2]), + .I3(_0329_[3]), + .O(_0330_[1]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1128_ ( + .I0(_0241_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0329_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1129_ ( + .I0(aluPlus[22]), + .I1(aluMinus[22]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0183_[2]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1130_ ( + .I0(cycles[22]), + .I1(_0143_[2]), + .I2(_0328_[2]), + .O(_0330_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1131_ ( + .I0(_0261_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0328_[2]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1132_ ( + .I0(PCplus4[22]), + .I1(_0143_[1]), + .I2(_0327_[2]), + .I3(_0327_[3]), + .O(_0330_[2]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _1133_ ( + .I0(_0151_[1]), + .I1(PCplusImm[22]), + .O(_0327_[2]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _1134_ ( + .I0(_0171_[1]), + .I1(Iimm[2]), + .O(_0327_[3]) + ); + CC_LUT4 #( + .INIT(16'h0b00) + ) _1135_ ( + .I0(_0089_[4]), + .I1(_0181_[1]), + .I2(_0181_[2]), + .I3(_0098_[2]), + .O(_0182_[0]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1136_ ( + .I0(_0163_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0164_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1137_ ( + .I0(aluPlus[23]), + .I1(aluMinus[23]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0164_[3]) + ); + CC_LUT3 #( + .INIT(8'h70) + ) _1138_ ( + .I0(Iimm[3]), + .I1(_0171_[1]), + .I2(_0171_[2]), + .O(_0182_[3]) + ); + CC_LUT4 #( + .INIT(16'h0700) + ) _1139_ ( + .I0(PCplusImm[23]), + .I1(_0151_[1]), + .I2(_0170_[2]), + .I3(_0170_[3]), + .O(_0171_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1140_ ( + .I0(_0166_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0170_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1141_ ( + .I0(PCplus4[23]), + .I1(_0143_[1]), + .I2(_0143_[2]), + .I3(cycles[23]), + .O(_0170_[3]) + ); + CC_LUT4 #( + .INIT(16'hf2ff) + ) _1142_ ( + .I0(_0152_[2]), + .I1(_0326_[1]), + .I2(_0326_[2]), + .I3(_0326_[3]), + .O(writeBackData[24]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1143_ ( + .I0(_0098_[2]), + .I1(_0255_[0]), + .I2(_0325_[2]), + .I3(_0325_[3]), + .O(_0326_[1]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1144_ ( + .I0(_0181_[1]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0325_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1145_ ( + .I0(aluPlus[24]), + .I1(aluMinus[24]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0161_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1146_ ( + .I0(_0324_[0]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0326_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1147_ ( + .I0(Iimm[4]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[24]), + .O(_0326_[3]) + ); + CC_LUT4 #( + .INIT(16'hf2ff) + ) _1148_ ( + .I0(_0152_[2]), + .I1(_0323_[1]), + .I2(_0323_[2]), + .I3(_0323_[3]), + .O(writeBackData[25]) + ); + CC_LUT4 #( + .INIT(16'h0700) + ) _1149_ ( + .I0(_0098_[2]), + .I1(_0268_[0]), + .I2(_0322_[2]), + .I3(_0322_[3]), + .O(_0323_[1]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1150_ ( + .I0(_0249_[2]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0322_[2]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1151_ ( + .I0(aluPlus[25]), + .I1(aluMinus[25]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0159_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1152_ ( + .I0(_0243_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0323_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1153_ ( + .I0(Bimm[5]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[25]), + .O(_0323_[3]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1154_ ( + .I0(_0321_[0]), + .I1(_0321_[1]), + .I2(_0152_[2]), + .I3(_0321_[3]), + .O(writeBackData[26]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _1155_ ( + .I0(_0134_[1]), + .I1(_0098_[2]), + .O(_0321_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1156_ ( + .I0(_0163_[3]), + .I1(_0108_[0]), + .I2(_0320_[2]), + .I3(_0320_[3]), + .O(_0321_[1]) + ); + CC_LUT3 #( + .INIT(8'h0d) + ) _1157_ ( + .I0(_0097_[3]), + .I1(_0319_[1]), + .I2(_0319_[2]), + .O(_0320_[3]) + ); + CC_LUT4 #( + .INIT(16'hec0e) + ) _1158_ ( + .I0(_0294_[1]), + .I1(_0295_[2]), + .I2(_0089_[26]), + .I3(aluIn1[26]), + .O(_0319_[2]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _1159_ ( + .I0(aluPlus[26]), + .I1(aluMinus[26]), + .I2(_0097_[2]), + .O(_0319_[1]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _1160_ ( + .I0(_0089_[26]), + .I1(_0294_[0]), + .I2(aluIn1[26]), + .O(_0320_[2]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1161_ ( + .I0(_0318_[0]), + .I1(_0318_[1]), + .O(_0321_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1162_ ( + .I0(_0235_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0318_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1163_ ( + .I0(Bimm[6]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[26]), + .O(_0318_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1164_ ( + .I0(_0317_[0]), + .I1(_0317_[1]), + .I2(_0152_[2]), + .I3(_0317_[3]), + .O(writeBackData[27]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1165_ ( + .I0(_0098_[2]), + .I1(_0316_[1]), + .I2(_0316_[2]), + .I3(_0316_[3]), + .O(_0317_[1]) + ); + CC_LUT4 #( + .INIT(16'hec0e) + ) _1166_ ( + .I0(_0294_[1]), + .I1(_0295_[2]), + .I2(_0089_[27]), + .I3(aluIn1[27]), + .O(_0316_[2]) + ); + CC_LUT4 #( + .INIT(16'h00bf) + ) _1167_ ( + .I0(_0089_[27]), + .I1(_0294_[0]), + .I2(aluIn1[27]), + .I3(_0314_[3]), + .O(_0316_[3]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1168_ ( + .I0(aluPlus[27]), + .I1(aluMinus[27]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0314_[3]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1169_ ( + .I0(_0313_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0317_[0]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1170_ ( + .I0(_0312_[0]), + .I1(_0312_[1]), + .O(_0317_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1171_ ( + .I0(_0145_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0312_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1172_ ( + .I0(Bimm[7]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[27]), + .O(_0312_[1]) + ); + CC_LUT3 #( + .INIT(8'hef) + ) _1173_ ( + .I0(_0311_[0]), + .I1(_0311_[1]), + .I2(_0311_[2]), + .O(writeBackData[28]) + ); + CC_LUT4 #( + .INIT(16'h4f00) + ) _1174_ ( + .I0(_0142_[0]), + .I1(_0098_[2]), + .I2(_0310_[2]), + .I3(_0152_[2]), + .O(_0311_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1175_ ( + .I0(_0163_[3]), + .I1(_0111_[0]), + .I2(_0309_[2]), + .I3(_0309_[3]), + .O(_0310_[2]) + ); + CC_LUT3 #( + .INIT(8'h0d) + ) _1176_ ( + .I0(_0097_[3]), + .I1(_0308_[1]), + .I2(_0308_[2]), + .O(_0309_[3]) + ); + CC_LUT4 #( + .INIT(16'hec0e) + ) _1177_ ( + .I0(_0294_[1]), + .I1(_0295_[2]), + .I2(_0089_[28]), + .I3(aluIn1[28]), + .O(_0308_[2]) + ); + CC_LUT3 #( + .INIT(8'h35) + ) _1178_ ( + .I0(aluPlus[28]), + .I1(aluMinus[28]), + .I2(_0097_[2]), + .O(_0308_[1]) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _1179_ ( + .I0(_0089_[28]), + .I1(_0294_[0]), + .I2(aluIn1[28]), + .O(_0309_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1180_ ( + .I0(_0223_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0311_[1]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1181_ ( + .I0(Bimm[8]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[28]), + .O(_0311_[2]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1182_ ( + .I0(_0307_[0]), + .I1(_0307_[1]), + .I2(_0152_[2]), + .I3(_0307_[3]), + .O(writeBackData[29]) + ); + CC_LUT4 #( + .INIT(16'h1f00) + ) _1183_ ( + .I0(_0279_[0]), + .I1(_0279_[1]), + .I2(_0098_[2]), + .I3(_0306_[3]), + .O(_0307_[1]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1184_ ( + .I0(aluPlus[29]), + .I1(aluMinus[29]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0160_[2]) + ); + CC_LUT4 #( + .INIT(16'hf400) + ) _1185_ ( + .I0(_0270_[0]), + .I1(_0089_[4]), + .I2(_0163_[2]), + .I3(_0163_[3]), + .O(_0307_[0]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1186_ ( + .I0(_0305_[0]), + .I1(_0305_[1]), + .O(_0307_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1187_ ( + .I0(_0154_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0305_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1188_ ( + .I0(Bimm[9]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[29]), + .O(_0305_[1]) + ); + CC_LUT3 #( + .INIT(8'h4f) + ) _1189_ ( + .I0(_0304_[0]), + .I1(_0152_[2]), + .I2(_0304_[2]), + .O(writeBackData[30]) + ); + CC_LUT4 #( + .INIT(16'hef00) + ) _1190_ ( + .I0(_0303_[0]), + .I1(_0303_[1]), + .I2(_0098_[2]), + .I3(_0303_[3]), + .O(_0304_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1191_ ( + .I0(_0163_[3]), + .I1(_0301_[1]), + .I2(_0301_[2]), + .I3(_0301_[3]), + .O(_0303_[3]) + ); + CC_LUT4 #( + .INIT(16'hec0e) + ) _1192_ ( + .I0(_0294_[1]), + .I1(_0295_[2]), + .I2(_0089_[30]), + .I3(aluIn1[30]), + .O(_0301_[2]) + ); + CC_LUT4 #( + .INIT(16'h00bf) + ) _1193_ ( + .I0(_0089_[30]), + .I1(_0294_[0]), + .I2(aluIn1[30]), + .I3(_0300_[3]), + .O(_0301_[3]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1194_ ( + .I0(aluPlus[30]), + .I1(aluMinus[30]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0300_[3]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1195_ ( + .I0(cycles[30]), + .I1(_0143_[2]), + .I2(_0299_[2]), + .I3(_0299_[3]), + .O(_0304_[2]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1196_ ( + .I0(_0262_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0299_[3]) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _1197_ ( + .I0(instr[6]), + .I1(_0097_[2]), + .I2(_0150_[2]), + .I3(instr[2]), + .O(_0299_[2]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1198_ ( + .I0(_0298_[0]), + .I1(_0298_[1]), + .I2(_0152_[2]), + .I3(_0298_[3]), + .O(writeBackData[31]) + ); + CC_LUT3 #( + .INIT(8'he0) + ) _1199_ ( + .I0(_0297_[0]), + .I1(_0297_[1]), + .I2(_0098_[2]), + .O(_0298_[0]) + ); + CC_LUT4 #( + .INIT(16'h0d00) + ) _1200_ ( + .I0(_0163_[3]), + .I1(_0296_[1]), + .I2(_0296_[2]), + .I3(_0296_[3]), + .O(_0298_[1]) + ); + CC_LUT4 #( + .INIT(16'h4f00) + ) _1201_ ( + .I0(aluIn1[31]), + .I1(_0089_[31]), + .I2(_0295_[2]), + .I3(_0295_[3]), + .O(_0296_[3]) + ); + CC_LUT4 #( + .INIT(16'h35f3) + ) _1202_ ( + .I0(_0294_[0]), + .I1(_0294_[1]), + .I2(_0089_[31]), + .I3(aluIn1[31]), + .O(_0295_[3]) + ); + CC_LUT4 #( + .INIT(16'hca00) + ) _1203_ ( + .I0(aluPlus[31]), + .I1(aluMinus[31]), + .I2(_0097_[2]), + .I3(_0097_[3]), + .O(_0296_[2]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _1204_ ( + .I0(_0293_[0]), + .I1(_0293_[1]), + .O(_0298_[3]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1205_ ( + .I0(_0165_[1]), + .I1(Jimm[13]), + .I2(_0169_[2]), + .I3(_0149_[1]), + .O(_0293_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _1206_ ( + .I0(Bimm[31]), + .I1(_0171_[1]), + .I2(_0143_[2]), + .I3(cycles[31]), + .O(_0293_[1]) + ); + CC_LUT4 #( + .INIT(16'hfff4) + ) _1207_ ( + .I0(instr[5]), + .I1(state[2]), + .I2(_0292_[2]), + .I3(state[0]), + .O(_0028_) + ); + CC_LUT4 #( + .INIT(16'h0b00) + ) _1208_ ( + .I0(Jimm[13]), + .I1(loadstore_addr[1]), + .I2(_0145_[3]), + .I3(_0291_[3]), + .O(_0045_) + ); + CC_LUT3 #( + .INIT(8'h80) + ) _1209_ ( + .I0(_0148_[1]), + .I1(state[2]), + .I2(instr[5]), + .O(_0291_[3]) + ); + CC_LUT4 #( + .INIT(16'h0b00) + ) _1210_ ( + .I0(Jimm[13]), + .I1(loadstore_addr[1]), + .I2(_0167_[2]), + .I3(_0291_[3]), + .O(_0046_) + ); + CC_LUT4 #( + .INIT(16'h0e00) + ) _1211_ ( + .I0(Jimm[13]), + .I1(loadstore_addr[1]), + .I2(_0145_[3]), + .I3(_0291_[3]), + .O(_0047_) + ); + CC_LUT4 #( + .INIT(16'h0e00) + ) _1212_ ( + .I0(Jimm[13]), + .I1(loadstore_addr[1]), + .I2(_0167_[2]), + .I3(_0291_[3]), + .O(_0048_) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1213_ ( + .I0(_0089_[0]), + .O(aluIn2[0]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1214_ ( + .I0(_0089_[1]), + .O(aluIn2[1]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1215_ ( + .I0(_0089_[2]), + .O(aluIn2[2]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1216_ ( + .I0(_0089_[3]), + .O(aluIn2[3]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1217_ ( + .I0(_0089_[4]), + .O(aluIn2[4]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1218_ ( + .I0(_0089_[5]), + .O(aluIn2[5]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1219_ ( + .I0(_0089_[6]), + .O(aluIn2[6]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1220_ ( + .I0(_0089_[7]), + .O(aluIn2[7]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1221_ ( + .I0(_0089_[8]), + .O(aluIn2[8]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1222_ ( + .I0(_0089_[9]), + .O(aluIn2[9]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1223_ ( + .I0(_0089_[10]), + .O(aluIn2[10]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1224_ ( + .I0(_0089_[11]), + .O(aluIn2[11]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1225_ ( + .I0(_0089_[12]), + .O(aluIn2[12]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1226_ ( + .I0(_0089_[13]), + .O(aluIn2[13]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1227_ ( + .I0(_0089_[14]), + .O(aluIn2[14]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1228_ ( + .I0(_0089_[15]), + .O(aluIn2[15]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1229_ ( + .I0(_0089_[16]), + .O(aluIn2[16]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1230_ ( + .I0(_0089_[17]), + .O(aluIn2[17]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1231_ ( + .I0(_0089_[18]), + .O(aluIn2[18]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1232_ ( + .I0(_0089_[19]), + .O(aluIn2[19]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1233_ ( + .I0(_0089_[20]), + .O(aluIn2[20]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1234_ ( + .I0(_0089_[21]), + .O(aluIn2[21]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1235_ ( + .I0(_0089_[22]), + .O(aluIn2[22]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1236_ ( + .I0(_0089_[23]), + .O(aluIn2[23]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1237_ ( + .I0(_0089_[24]), + .O(aluIn2[24]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1238_ ( + .I0(_0089_[25]), + .O(aluIn2[25]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1239_ ( + .I0(_0089_[26]), + .O(aluIn2[26]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1240_ ( + .I0(_0089_[27]), + .O(aluIn2[27]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1241_ ( + .I0(_0089_[28]), + .O(aluIn2[28]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1242_ ( + .I0(_0089_[29]), + .O(aluIn2[29]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1243_ ( + .I0(_0089_[30]), + .O(aluIn2[30]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _1244_ ( + .I0(_0089_[31]), + .O(aluIn2[31]) + ); + CC_LUT4 #( + .INIT(16'hcfa0) + ) _1245_ ( + .I0(_0275_[1]), + .I1(_0287_[1]), + .I2(_0089_[0]), + .I3(_0089_[1]), + .O(_0288_[3]) + ); + CC_LUT4 #( + .INIT(16'h05f3) + ) _1246_ ( + .I0(_0282_[1]), + .I1(_0137_[1]), + .I2(_0089_[0]), + .I3(_0288_[3]), + .O(_0289_[1]) + ); + CC_LUT3 #( + .INIT(8'hc5) + ) _1247_ ( + .I0(_0289_[0]), + .I1(_0289_[1]), + .I2(_0089_[2]), + .O(_0290_[1]) + ); + CC_LUT4 #( + .INIT(16'hc500) + ) _1248_ ( + .I0(_0178_[1]), + .I1(_0290_[1]), + .I2(_0089_[3]), + .I3(_0089_[4]), + .O(_0297_[1]) + ); + CC_LUT4 #( + .INIT(16'h44f0) + ) _1249_ ( + .I0(_0089_[0]), + .I1(aluIn1[0]), + .I2(LTU), + .I3(Jimm[14]), + .O(_0286_[2]) + ); + CC_LUT4 #( + .INIT(16'h007f) + ) _1250_ ( + .I0(Jimm[12]), + .I1(Jimm[13]), + .I2(_0286_[2]), + .I3(_0286_[3]), + .O(_0379_[3]) + ); + CC_LUT4 #( + .INIT(16'h3fa0) + ) _1251_ ( + .I0(_0128_[1]), + .I1(_0283_[1]), + .I2(_0089_[1]), + .I3(_0089_[2]), + .O(_0284_[3]) + ); + CC_LUT4 #( + .INIT(16'hfc0a) + ) _1252_ ( + .I0(_0128_[0]), + .I1(_0138_[0]), + .I2(_0089_[1]), + .I3(_0284_[3]), + .O(_0285_[1]) + ); + CC_LUT4 #( + .INIT(16'hf800) + ) _1253_ ( + .I0(_0089_[3]), + .I1(_0285_[1]), + .I2(_0285_[2]), + .I3(_0089_[4]), + .O(_0303_[1]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1254_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[1]), + .I3(aluIn1[1]), + .O(_0281_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1255_ ( + .I0(_0281_[0]), + .I1(Jimm[14]), + .I2(_0281_[2]), + .O(_0371_[2]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1256_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[2]), + .I3(aluIn1[2]), + .O(_0271_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1257_ ( + .I0(_0271_[0]), + .I1(Jimm[14]), + .I2(_0271_[2]), + .I3(_0271_[3]), + .O(_0280_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1258_ ( + .I0(_0280_[0]), + .I1(_0280_[1]), + .I2(_0152_[2]), + .I3(_0280_[3]), + .O(writeBackData[2]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1259_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[3]), + .I3(aluIn1[3]), + .O(_0142_[2]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1260_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[5]), + .I3(aluIn1[5]), + .O(_0134_[2]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1261_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[6]), + .I3(aluIn1[6]), + .O(_0260_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1262_ ( + .I0(_0260_[0]), + .I1(Jimm[14]), + .I2(_0260_[2]), + .I3(_0260_[3]), + .O(_0269_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1263_ ( + .I0(_0269_[0]), + .I1(_0269_[1]), + .I2(_0152_[2]), + .I3(_0269_[3]), + .O(writeBackData[6]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1264_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[7]), + .I3(aluIn1[7]), + .O(_0258_[0]) + ); + CC_LUT4 #( + .INIT(16'h80ff) + ) _1265_ ( + .I0(_0258_[0]), + .I1(_0152_[2]), + .I2(Jimm[14]), + .I3(_0258_[3]), + .O(_0259_[2]) + ); + CC_LUT4 #( + .INIT(16'h000b) + ) _1266_ ( + .I0(_0255_[0]), + .I1(_0163_[3]), + .I2(_0255_[2]), + .I3(_0255_[3]), + .O(_0259_[3]) + ); + CC_LUT4 #( + .INIT(16'hf0bb) + ) _1267_ ( + .I0(_0152_[2]), + .I1(_0258_[3]), + .I2(_0259_[2]), + .I3(_0259_[3]), + .O(writeBackData[7]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1268_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[8]), + .I3(aluIn1[8]), + .O(_0252_[3]) + ); + CC_LUT4 #( + .INIT(16'h0bbb) + ) _1269_ ( + .I0(_0252_[0]), + .I1(_0097_[3]), + .I2(Jimm[14]), + .I3(_0252_[3]), + .O(_0253_[2]) + ); + CC_LUT3 #( + .INIT(8'hb0) + ) _1270_ ( + .I0(_0253_[0]), + .I1(_0098_[2]), + .I2(_0253_[2]), + .O(_0359_[1]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1271_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[9]), + .I3(aluIn1[9]), + .O(_0242_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1272_ ( + .I0(_0242_[0]), + .I1(Jimm[14]), + .I2(_0242_[2]), + .I3(_0242_[3]), + .O(_0251_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1273_ ( + .I0(_0251_[0]), + .I1(_0251_[1]), + .I2(_0152_[2]), + .I3(_0251_[3]), + .O(writeBackData[9]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1274_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[10]), + .I3(aluIn1[10]), + .O(_0234_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1275_ ( + .I0(_0234_[0]), + .I1(Jimm[14]), + .I2(_0234_[2]), + .I3(_0234_[3]), + .O(_0239_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1276_ ( + .I0(_0239_[0]), + .I1(_0239_[1]), + .I2(_0152_[2]), + .I3(_0239_[3]), + .O(writeBackData[10]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1277_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[11]), + .I3(aluIn1[11]), + .O(_0232_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1278_ ( + .I0(_0232_[0]), + .I1(Jimm[14]), + .I2(_0232_[2]), + .I3(_0232_[3]), + .O(_0233_[1]) + ); + CC_LUT3 #( + .INIT(8'hb0) + ) _1279_ ( + .I0(_0231_[0]), + .I1(_0149_[1]), + .I2(_0231_[2]), + .O(_0233_[3]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1280_ ( + .I0(_0233_[0]), + .I1(_0233_[1]), + .I2(_0152_[2]), + .I3(_0233_[3]), + .O(writeBackData[11]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1281_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[12]), + .I3(aluIn1[12]), + .O(_0222_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1282_ ( + .I0(_0222_[0]), + .I1(Jimm[14]), + .I2(_0222_[2]), + .I3(_0222_[3]), + .O(_0228_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1283_ ( + .I0(_0228_[0]), + .I1(_0228_[1]), + .I2(_0152_[2]), + .I3(_0228_[3]), + .O(writeBackData[12]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1284_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[13]), + .I3(aluIn1[13]), + .O(_0221_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1285_ ( + .I0(_0221_[0]), + .I1(Jimm[14]), + .I2(_0221_[2]), + .O(_0353_[3]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1286_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[14]), + .I3(aluIn1[14]), + .O(_0220_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1287_ ( + .I0(_0220_[0]), + .I1(Jimm[14]), + .I2(_0220_[2]), + .O(_0348_[3]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1288_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[15]), + .I3(aluIn1[15]), + .O(_0219_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1289_ ( + .I0(_0219_[0]), + .I1(Jimm[14]), + .I2(_0219_[2]), + .O(_0344_[3]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1290_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[16]), + .I3(aluIn1[16]), + .O(_0213_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1291_ ( + .I0(_0213_[0]), + .I1(Jimm[14]), + .I2(_0213_[2]), + .I3(_0213_[3]), + .O(_0218_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1292_ ( + .I0(_0218_[0]), + .I1(_0218_[1]), + .I2(_0152_[2]), + .I3(_0218_[3]), + .O(writeBackData[16]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1293_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[18]), + .I3(aluIn1[18]), + .O(_0203_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1294_ ( + .I0(_0203_[0]), + .I1(Jimm[14]), + .I2(_0203_[2]), + .I3(_0203_[3]), + .O(_0209_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1295_ ( + .I0(_0209_[0]), + .I1(_0209_[1]), + .I2(_0152_[2]), + .I3(_0209_[3]), + .O(writeBackData[18]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1296_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[19]), + .I3(aluIn1[19]), + .O(_0197_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1297_ ( + .I0(_0197_[0]), + .I1(Jimm[14]), + .I2(_0197_[2]), + .I3(_0197_[3]), + .O(_0201_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1298_ ( + .I0(_0201_[0]), + .I1(_0201_[1]), + .I2(_0152_[2]), + .I3(_0201_[3]), + .O(writeBackData[19]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1299_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[20]), + .I3(aluIn1[20]), + .O(_0191_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1300_ ( + .I0(_0191_[0]), + .I1(Jimm[14]), + .I2(_0191_[2]), + .O(_0195_[2]) + ); + CC_LUT4 #( + .INIT(16'hef00) + ) _1301_ ( + .I0(_0195_[0]), + .I1(_0195_[1]), + .I2(_0195_[2]), + .I3(_0152_[2]), + .O(_0333_[2]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1302_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[21]), + .I3(aluIn1[21]), + .O(_0184_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1303_ ( + .I0(_0184_[0]), + .I1(Jimm[14]), + .I2(_0184_[2]), + .I3(_0184_[3]), + .O(_0190_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1304_ ( + .I0(_0190_[0]), + .I1(_0190_[1]), + .I2(_0152_[2]), + .I3(_0190_[3]), + .O(writeBackData[21]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1305_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[22]), + .I3(aluIn1[22]), + .O(_0183_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1306_ ( + .I0(_0183_[0]), + .I1(Jimm[14]), + .I2(_0183_[2]), + .O(_0329_[3]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1307_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[23]), + .I3(aluIn1[23]), + .O(_0164_[0]) + ); + CC_LUT4 #( + .INIT(16'h0007) + ) _1308_ ( + .I0(_0164_[0]), + .I1(Jimm[14]), + .I2(_0164_[2]), + .I3(_0164_[3]), + .O(_0182_[1]) + ); + CC_LUT4 #( + .INIT(16'hb0ff) + ) _1309_ ( + .I0(_0182_[0]), + .I1(_0182_[1]), + .I2(_0152_[2]), + .I3(_0182_[3]), + .O(writeBackData[23]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1310_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[24]), + .I3(aluIn1[24]), + .O(_0161_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1311_ ( + .I0(_0161_[0]), + .I1(Jimm[14]), + .I2(_0161_[2]), + .O(_0325_[3]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1312_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[25]), + .I3(aluIn1[25]), + .O(_0159_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1313_ ( + .I0(_0159_[0]), + .I1(Jimm[14]), + .I2(_0159_[2]), + .O(_0322_[3]) + ); + CC_LUT4 #( + .INIT(16'h3a03) + ) _1314_ ( + .I0(Jimm[13]), + .I1(Jimm[12]), + .I2(_0089_[29]), + .I3(aluIn1[29]), + .O(_0160_[0]) + ); + CC_LUT3 #( + .INIT(8'h07) + ) _1315_ ( + .I0(_0160_[0]), + .I1(Jimm[14]), + .I2(_0160_[2]), + .O(_0306_[3]) + ); + CC_LUT4 #( + .INIT(16'h0bff) + ) _1316_ ( + .I0(_0142_[0]), + .I1(_0134_[0]), + .I2(_0142_[2]), + .I3(Jimm[14]), + .O(_0152_[1]) + ); + CC_LUT3 #( + .INIT(8'h0b) + ) _1317_ ( + .I0(_0111_[0]), + .I1(_0098_[2]), + .I2(_0111_[2]), + .O(_0152_[0]) + ); + CC_LUT4 #( + .INIT(16'h70ff) + ) _1318_ ( + .I0(_0152_[0]), + .I1(_0152_[1]), + .I2(_0152_[2]), + .I3(_0152_[3]), + .O(writeBackData[3]) + ); + CC_LUT4 #( + .INIT(16'h07ff) + ) _1319_ ( + .I0(_0134_[0]), + .I1(_0134_[1]), + .I2(_0134_[2]), + .I3(Jimm[14]), + .O(_0158_[1]) + ); + CC_LUT3 #( + .INIT(8'h0b) + ) _1320_ ( + .I0(_0108_[0]), + .I1(_0098_[2]), + .I2(_0108_[2]), + .O(_0158_[0]) + ); + CC_LUT4 #( + .INIT(16'h70ff) + ) _1321_ ( + .I0(_0158_[0]), + .I1(_0158_[1]), + .I2(_0152_[2]), + .I3(_0158_[3]), + .O(writeBackData[5]) + ); + CC_ADDF _1322_ ( + .A(1'h1), + .B(cycles[0]), + .CI(1'h0), + .CO(_0076_[1]), + .S(_0078_[0]) + ); + CC_ADDF _1323_ ( + .A(1'h0), + .B(cycles[10]), + .CI(_0076_[10]), + .CO(_0076_[11]), + .S(_0078_[10]) + ); + CC_ADDF _1324_ ( + .A(1'h0), + .B(cycles[11]), + .CI(_0076_[11]), + .CO(_0076_[12]), + .S(_0078_[11]) + ); + CC_ADDF _1325_ ( + .A(1'h0), + .B(cycles[12]), + .CI(_0076_[12]), + .CO(_0076_[13]), + .S(_0078_[12]) + ); + CC_ADDF _1326_ ( + .A(1'h0), + .B(cycles[13]), + .CI(_0076_[13]), + .CO(_0076_[14]), + .S(_0078_[13]) + ); + CC_ADDF _1327_ ( + .A(1'h0), + .B(cycles[14]), + .CI(_0076_[14]), + .CO(_0076_[15]), + .S(_0078_[14]) + ); + CC_ADDF _1328_ ( + .A(1'h0), + .B(cycles[15]), + .CI(_0076_[15]), + .CO(_0076_[16]), + .S(_0078_[15]) + ); + CC_ADDF _1329_ ( + .A(1'h0), + .B(cycles[16]), + .CI(_0076_[16]), + .CO(_0076_[17]), + .S(_0078_[16]) + ); + CC_ADDF _1330_ ( + .A(1'h0), + .B(cycles[17]), + .CI(_0076_[17]), + .CO(_0076_[18]), + .S(_0078_[17]) + ); + CC_ADDF _1331_ ( + .A(1'h0), + .B(cycles[18]), + .CI(_0076_[18]), + .CO(_0076_[19]), + .S(_0078_[18]) + ); + CC_ADDF _1332_ ( + .A(1'h0), + .B(cycles[19]), + .CI(_0076_[19]), + .CO(_0076_[20]), + .S(_0078_[19]) + ); + CC_ADDF _1333_ ( + .A(1'h0), + .B(cycles[1]), + .CI(_0076_[1]), + .CO(_0076_[2]), + .S(_0078_[1]) + ); + CC_ADDF _1334_ ( + .A(1'h0), + .B(cycles[20]), + .CI(_0076_[20]), + .CO(_0076_[21]), + .S(_0078_[20]) + ); + CC_ADDF _1335_ ( + .A(1'h0), + .B(cycles[21]), + .CI(_0076_[21]), + .CO(_0076_[22]), + .S(_0078_[21]) + ); + CC_ADDF _1336_ ( + .A(1'h0), + .B(cycles[22]), + .CI(_0076_[22]), + .CO(_0076_[23]), + .S(_0078_[22]) + ); + CC_ADDF _1337_ ( + .A(1'h0), + .B(cycles[23]), + .CI(_0076_[23]), + .CO(_0076_[24]), + .S(_0078_[23]) + ); + CC_ADDF _1338_ ( + .A(1'h0), + .B(cycles[24]), + .CI(_0076_[24]), + .CO(_0076_[25]), + .S(_0078_[24]) + ); + CC_ADDF _1339_ ( + .A(1'h0), + .B(cycles[25]), + .CI(_0076_[25]), + .CO(_0076_[26]), + .S(_0078_[25]) + ); + CC_ADDF _1340_ ( + .A(1'h0), + .B(cycles[26]), + .CI(_0076_[26]), + .CO(_0076_[27]), + .S(_0078_[26]) + ); + CC_ADDF _1341_ ( + .A(1'h0), + .B(cycles[27]), + .CI(_0076_[27]), + .CO(_0076_[28]), + .S(_0078_[27]) + ); + CC_ADDF _1342_ ( + .A(1'h0), + .B(cycles[28]), + .CI(_0076_[28]), + .CO(_0076_[29]), + .S(_0078_[28]) + ); + CC_ADDF _1343_ ( + .A(1'h0), + .B(cycles[29]), + .CI(_0076_[29]), + .CO(_0076_[30]), + .S(_0078_[29]) + ); + CC_ADDF _1344_ ( + .A(1'h0), + .B(cycles[2]), + .CI(_0076_[2]), + .CO(_0076_[3]), + .S(_0078_[2]) + ); + CC_ADDF _1345_ ( + .A(1'h0), + .B(cycles[30]), + .CI(_0076_[30]), + .CO(_0076_[31]), + .S(_0078_[30]) + ); + CC_ADDF _1346_ ( + .A(1'h0), + .B(cycles[31]), + .CI(_0076_[31]), + .CO(_0077_[31]), + .S(_0078_[31]) + ); + CC_ADDF _1347_ ( + .A(1'h0), + .B(cycles[3]), + .CI(_0076_[3]), + .CO(_0076_[4]), + .S(_0078_[3]) + ); + CC_ADDF _1348_ ( + .A(1'h0), + .B(cycles[4]), + .CI(_0076_[4]), + .CO(_0076_[5]), + .S(_0078_[4]) + ); + CC_ADDF _1349_ ( + .A(1'h0), + .B(cycles[5]), + .CI(_0076_[5]), + .CO(_0076_[6]), + .S(_0078_[5]) + ); + CC_ADDF _1350_ ( + .A(1'h0), + .B(cycles[6]), + .CI(_0076_[6]), + .CO(_0076_[7]), + .S(_0078_[6]) + ); + CC_ADDF _1351_ ( + .A(1'h0), + .B(cycles[7]), + .CI(_0076_[7]), + .CO(_0076_[8]), + .S(_0078_[7]) + ); + CC_ADDF _1352_ ( + .A(1'h0), + .B(cycles[8]), + .CI(_0076_[8]), + .CO(_0076_[9]), + .S(_0078_[8]) + ); + CC_ADDF _1353_ ( + .A(1'h0), + .B(cycles[9]), + .CI(_0076_[9]), + .CO(_0076_[10]), + .S(_0078_[9]) + ); + CC_ADDF _1354_ ( + .A(aluIn1[0]), + .B(_0079_[0]), + .CI(1'h0), + .CO(_0080_[1]), + .S(loadstore_addr[0]) + ); + CC_ADDF _1355_ ( + .A(aluIn1[10]), + .B(Bimm[10]), + .CI(_0080_[10]), + .CO(_0080_[11]), + .S(loadstore_addr[10]) + ); + CC_ADDF _1356_ ( + .A(aluIn1[11]), + .B(Bimm[31]), + .CI(_0080_[11]), + .CO(_0080_[12]), + .S(loadstore_addr[11]) + ); + CC_ADDF _1357_ ( + .A(aluIn1[12]), + .B(Bimm[31]), + .CI(_0080_[12]), + .CO(_0080_[13]), + .S(loadstore_addr[12]) + ); + CC_ADDF _1358_ ( + .A(aluIn1[13]), + .B(Bimm[31]), + .CI(_0080_[13]), + .CO(_0080_[14]), + .S(loadstore_addr[13]) + ); + CC_ADDF _1359_ ( + .A(aluIn1[14]), + .B(Bimm[31]), + .CI(_0080_[14]), + .CO(_0080_[15]), + .S(loadstore_addr[14]) + ); + CC_ADDF _1360_ ( + .A(aluIn1[15]), + .B(Bimm[31]), + .CI(_0080_[15]), + .CO(_0080_[16]), + .S(loadstore_addr[15]) + ); + CC_ADDF _1361_ ( + .A(aluIn1[16]), + .B(Bimm[31]), + .CI(_0080_[16]), + .CO(_0080_[17]), + .S(loadstore_addr[16]) + ); + CC_ADDF _1362_ ( + .A(aluIn1[17]), + .B(Bimm[31]), + .CI(_0080_[17]), + .CO(_0080_[18]), + .S(loadstore_addr[17]) + ); + CC_ADDF _1363_ ( + .A(aluIn1[18]), + .B(Bimm[31]), + .CI(_0080_[18]), + .CO(_0080_[19]), + .S(loadstore_addr[18]) + ); + CC_ADDF _1364_ ( + .A(aluIn1[19]), + .B(Bimm[31]), + .CI(_0080_[19]), + .CO(_0080_[20]), + .S(loadstore_addr[19]) + ); + CC_ADDF _1365_ ( + .A(aluIn1[1]), + .B(_0079_[1]), + .CI(_0080_[1]), + .CO(_0080_[2]), + .S(loadstore_addr[1]) + ); + CC_ADDF _1366_ ( + .A(aluIn1[20]), + .B(Bimm[31]), + .CI(_0080_[20]), + .CO(_0080_[21]), + .S(loadstore_addr[20]) + ); + CC_ADDF _1367_ ( + .A(aluIn1[21]), + .B(Bimm[31]), + .CI(_0080_[21]), + .CO(_0080_[22]), + .S(loadstore_addr[21]) + ); + CC_ADDF _1368_ ( + .A(aluIn1[22]), + .B(Bimm[31]), + .CI(_0080_[22]), + .CO(_0080_[23]), + .S(loadstore_addr[22]) + ); + CC_ADDF _1369_ ( + .A(aluIn1[23]), + .B(Bimm[31]), + .CI(_0080_[23]), + .CO(_0081_[23]), + .S(loadstore_addr[23]) + ); + CC_ADDF _1370_ ( + .A(aluIn1[2]), + .B(_0079_[2]), + .CI(_0080_[2]), + .CO(_0080_[3]), + .S(loadstore_addr[2]) + ); + CC_ADDF _1371_ ( + .A(aluIn1[3]), + .B(_0079_[3]), + .CI(_0080_[3]), + .CO(_0080_[4]), + .S(loadstore_addr[3]) + ); + CC_ADDF _1372_ ( + .A(aluIn1[4]), + .B(_0079_[4]), + .CI(_0080_[4]), + .CO(_0080_[5]), + .S(loadstore_addr[4]) + ); + CC_ADDF _1373_ ( + .A(aluIn1[5]), + .B(Bimm[5]), + .CI(_0080_[5]), + .CO(_0080_[6]), + .S(loadstore_addr[5]) + ); + CC_ADDF _1374_ ( + .A(aluIn1[6]), + .B(Bimm[6]), + .CI(_0080_[6]), + .CO(_0080_[7]), + .S(loadstore_addr[6]) + ); + CC_ADDF _1375_ ( + .A(aluIn1[7]), + .B(Bimm[7]), + .CI(_0080_[7]), + .CO(_0080_[8]), + .S(loadstore_addr[7]) + ); + CC_ADDF _1376_ ( + .A(aluIn1[8]), + .B(Bimm[8]), + .CI(_0080_[8]), + .CO(_0080_[9]), + .S(loadstore_addr[8]) + ); + CC_ADDF _1377_ ( + .A(aluIn1[9]), + .B(Bimm[9]), + .CI(_0080_[9]), + .CO(_0080_[10]), + .S(loadstore_addr[9]) + ); + CC_ADDF _1378_ ( + .A(1'h1), + .B(PC[2]), + .CI(1'h0), + .CO(_0082_[1]), + .S(PCplus4[2]) + ); + CC_ADDF _1379_ ( + .A(1'h0), + .B(PC[12]), + .CI(_0082_[10]), + .CO(_0082_[11]), + .S(PCplus4[12]) + ); + CC_ADDF _1380_ ( + .A(1'h0), + .B(PC[13]), + .CI(_0082_[11]), + .CO(_0082_[12]), + .S(PCplus4[13]) + ); + CC_ADDF _1381_ ( + .A(1'h0), + .B(PC[14]), + .CI(_0082_[12]), + .CO(_0082_[13]), + .S(PCplus4[14]) + ); + CC_ADDF _1382_ ( + .A(1'h0), + .B(PC[15]), + .CI(_0082_[13]), + .CO(_0082_[14]), + .S(PCplus4[15]) + ); + CC_ADDF _1383_ ( + .A(1'h0), + .B(PC[16]), + .CI(_0082_[14]), + .CO(_0082_[15]), + .S(PCplus4[16]) + ); + CC_ADDF _1384_ ( + .A(1'h0), + .B(PC[17]), + .CI(_0082_[15]), + .CO(_0082_[16]), + .S(PCplus4[17]) + ); + CC_ADDF _1385_ ( + .A(1'h0), + .B(PC[18]), + .CI(_0082_[16]), + .CO(_0082_[17]), + .S(PCplus4[18]) + ); + CC_ADDF _1386_ ( + .A(1'h0), + .B(PC[19]), + .CI(_0082_[17]), + .CO(_0082_[18]), + .S(PCplus4[19]) + ); + CC_ADDF _1387_ ( + .A(1'h0), + .B(PC[20]), + .CI(_0082_[18]), + .CO(_0082_[19]), + .S(PCplus4[20]) + ); + CC_ADDF _1388_ ( + .A(1'h0), + .B(PC[21]), + .CI(_0082_[19]), + .CO(_0082_[20]), + .S(PCplus4[21]) + ); + CC_ADDF _1389_ ( + .A(1'h0), + .B(PC[3]), + .CI(_0082_[1]), + .CO(_0082_[2]), + .S(PCplus4[3]) + ); + CC_ADDF _1390_ ( + .A(1'h0), + .B(PC[22]), + .CI(_0082_[20]), + .CO(_0082_[21]), + .S(PCplus4[22]) + ); + CC_ADDF _1391_ ( + .A(1'h0), + .B(PC[23]), + .CI(_0082_[21]), + .CO(_0083_[21]), + .S(PCplus4[23]) + ); + CC_ADDF _1392_ ( + .A(1'h0), + .B(PC[4]), + .CI(_0082_[2]), + .CO(_0082_[3]), + .S(PCplus4[4]) + ); + CC_ADDF _1393_ ( + .A(1'h0), + .B(PC[5]), + .CI(_0082_[3]), + .CO(_0082_[4]), + .S(PCplus4[5]) + ); + CC_ADDF _1394_ ( + .A(1'h0), + .B(PC[6]), + .CI(_0082_[4]), + .CO(_0082_[5]), + .S(PCplus4[6]) + ); + CC_ADDF _1395_ ( + .A(1'h0), + .B(PC[7]), + .CI(_0082_[5]), + .CO(_0082_[6]), + .S(PCplus4[7]) + ); + CC_ADDF _1396_ ( + .A(1'h0), + .B(PC[8]), + .CI(_0082_[6]), + .CO(_0082_[7]), + .S(PCplus4[8]) + ); + CC_ADDF _1397_ ( + .A(1'h0), + .B(PC[9]), + .CI(_0082_[7]), + .CO(_0082_[8]), + .S(PCplus4[9]) + ); + CC_ADDF _1398_ ( + .A(1'h0), + .B(PC[10]), + .CI(_0082_[8]), + .CO(_0082_[9]), + .S(PCplus4[10]) + ); + CC_ADDF _1399_ ( + .A(1'h0), + .B(PC[11]), + .CI(_0082_[9]), + .CO(_0082_[10]), + .S(PCplus4[11]) + ); + CC_ADDF _1400_ ( + .A(_0084_[0]), + .B(PC[1]), + .CI(1'h0), + .CO(_0085_[1]), + .S(PCplusImm[1]) + ); + CC_ADDF _1401_ ( + .A(_0084_[10]), + .B(PC[11]), + .CI(_0085_[10]), + .CO(_0085_[11]), + .S(PCplusImm[11]) + ); + CC_ADDF _1402_ ( + .A(_0084_[11]), + .B(PC[12]), + .CI(_0085_[11]), + .CO(_0085_[12]), + .S(PCplusImm[12]) + ); + CC_ADDF _1403_ ( + .A(_0084_[12]), + .B(PC[13]), + .CI(_0085_[12]), + .CO(_0085_[13]), + .S(PCplusImm[13]) + ); + CC_ADDF _1404_ ( + .A(_0084_[13]), + .B(PC[14]), + .CI(_0085_[13]), + .CO(_0085_[14]), + .S(PCplusImm[14]) + ); + CC_ADDF _1405_ ( + .A(_0084_[14]), + .B(PC[15]), + .CI(_0085_[14]), + .CO(_0085_[15]), + .S(PCplusImm[15]) + ); + CC_ADDF _1406_ ( + .A(_0084_[15]), + .B(PC[16]), + .CI(_0085_[15]), + .CO(_0085_[16]), + .S(PCplusImm[16]) + ); + CC_ADDF _1407_ ( + .A(_0084_[16]), + .B(PC[17]), + .CI(_0085_[16]), + .CO(_0085_[17]), + .S(PCplusImm[17]) + ); + CC_ADDF _1408_ ( + .A(_0084_[17]), + .B(PC[18]), + .CI(_0085_[17]), + .CO(_0085_[18]), + .S(PCplusImm[18]) + ); + CC_ADDF _1409_ ( + .A(_0084_[18]), + .B(PC[19]), + .CI(_0085_[18]), + .CO(_0085_[19]), + .S(PCplusImm[19]) + ); + CC_ADDF _1410_ ( + .A(_0084_[19]), + .B(PC[20]), + .CI(_0085_[19]), + .CO(_0085_[20]), + .S(PCplusImm[20]) + ); + CC_ADDF _1411_ ( + .A(_0084_[1]), + .B(PC[2]), + .CI(_0085_[1]), + .CO(_0085_[2]), + .S(PCplusImm[2]) + ); + CC_ADDF _1412_ ( + .A(_0084_[20]), + .B(PC[21]), + .CI(_0085_[20]), + .CO(_0085_[21]), + .S(PCplusImm[21]) + ); + CC_ADDF _1413_ ( + .A(_0084_[21]), + .B(PC[22]), + .CI(_0085_[21]), + .CO(_0085_[22]), + .S(PCplusImm[22]) + ); + CC_ADDF _1414_ ( + .A(_0084_[22]), + .B(PC[23]), + .CI(_0085_[22]), + .CO(_0086_[22]), + .S(PCplusImm[23]) + ); + CC_ADDF _1415_ ( + .A(_0084_[2]), + .B(PC[3]), + .CI(_0085_[2]), + .CO(_0085_[3]), + .S(PCplusImm[3]) + ); + CC_ADDF _1416_ ( + .A(_0084_[3]), + .B(PC[4]), + .CI(_0085_[3]), + .CO(_0085_[4]), + .S(PCplusImm[4]) + ); + CC_ADDF _1417_ ( + .A(_0084_[4]), + .B(PC[5]), + .CI(_0085_[4]), + .CO(_0085_[5]), + .S(PCplusImm[5]) + ); + CC_ADDF _1418_ ( + .A(_0084_[5]), + .B(PC[6]), + .CI(_0085_[5]), + .CO(_0085_[6]), + .S(PCplusImm[6]) + ); + CC_ADDF _1419_ ( + .A(_0084_[6]), + .B(PC[7]), + .CI(_0085_[6]), + .CO(_0085_[7]), + .S(PCplusImm[7]) + ); + CC_ADDF _1420_ ( + .A(_0084_[7]), + .B(PC[8]), + .CI(_0085_[7]), + .CO(_0085_[8]), + .S(PCplusImm[8]) + ); + CC_ADDF _1421_ ( + .A(_0084_[8]), + .B(PC[9]), + .CI(_0085_[8]), + .CO(_0085_[9]), + .S(PCplusImm[9]) + ); + CC_ADDF _1422_ ( + .A(_0084_[9]), + .B(PC[10]), + .CI(_0085_[9]), + .CO(_0085_[10]), + .S(PCplusImm[10]) + ); + CC_ADDF _1423_ ( + .A(aluIn1[0]), + .B(aluIn2[0]), + .CI(1'h0), + .CO(_0087_[1]), + .S(aluPlus[0]) + ); + CC_ADDF _1424_ ( + .A(aluIn1[10]), + .B(aluIn2[10]), + .CI(_0087_[10]), + .CO(_0087_[11]), + .S(aluPlus[10]) + ); + CC_ADDF _1425_ ( + .A(aluIn1[11]), + .B(aluIn2[11]), + .CI(_0087_[11]), + .CO(_0087_[12]), + .S(aluPlus[11]) + ); + CC_ADDF _1426_ ( + .A(aluIn1[12]), + .B(aluIn2[12]), + .CI(_0087_[12]), + .CO(_0087_[13]), + .S(aluPlus[12]) + ); + CC_ADDF _1427_ ( + .A(aluIn1[13]), + .B(aluIn2[13]), + .CI(_0087_[13]), + .CO(_0087_[14]), + .S(aluPlus[13]) + ); + CC_ADDF _1428_ ( + .A(aluIn1[14]), + .B(aluIn2[14]), + .CI(_0087_[14]), + .CO(_0087_[15]), + .S(aluPlus[14]) + ); + CC_ADDF _1429_ ( + .A(aluIn1[15]), + .B(aluIn2[15]), + .CI(_0087_[15]), + .CO(_0087_[16]), + .S(aluPlus[15]) + ); + CC_ADDF _1430_ ( + .A(aluIn1[16]), + .B(aluIn2[16]), + .CI(_0087_[16]), + .CO(_0087_[17]), + .S(aluPlus[16]) + ); + CC_ADDF _1431_ ( + .A(aluIn1[17]), + .B(aluIn2[17]), + .CI(_0087_[17]), + .CO(_0087_[18]), + .S(aluPlus[17]) + ); + CC_ADDF _1432_ ( + .A(aluIn1[18]), + .B(aluIn2[18]), + .CI(_0087_[18]), + .CO(_0087_[19]), + .S(aluPlus[18]) + ); + CC_ADDF _1433_ ( + .A(aluIn1[19]), + .B(aluIn2[19]), + .CI(_0087_[19]), + .CO(_0087_[20]), + .S(aluPlus[19]) + ); + CC_ADDF _1434_ ( + .A(aluIn1[1]), + .B(aluIn2[1]), + .CI(_0087_[1]), + .CO(_0087_[2]), + .S(aluPlus[1]) + ); + CC_ADDF _1435_ ( + .A(aluIn1[20]), + .B(aluIn2[20]), + .CI(_0087_[20]), + .CO(_0087_[21]), + .S(aluPlus[20]) + ); + CC_ADDF _1436_ ( + .A(aluIn1[21]), + .B(aluIn2[21]), + .CI(_0087_[21]), + .CO(_0087_[22]), + .S(aluPlus[21]) + ); + CC_ADDF _1437_ ( + .A(aluIn1[22]), + .B(aluIn2[22]), + .CI(_0087_[22]), + .CO(_0087_[23]), + .S(aluPlus[22]) + ); + CC_ADDF _1438_ ( + .A(aluIn1[23]), + .B(aluIn2[23]), + .CI(_0087_[23]), + .CO(_0087_[24]), + .S(aluPlus[23]) + ); + CC_ADDF _1439_ ( + .A(aluIn1[24]), + .B(aluIn2[24]), + .CI(_0087_[24]), + .CO(_0087_[25]), + .S(aluPlus[24]) + ); + CC_ADDF _1440_ ( + .A(aluIn1[25]), + .B(aluIn2[25]), + .CI(_0087_[25]), + .CO(_0087_[26]), + .S(aluPlus[25]) + ); + CC_ADDF _1441_ ( + .A(aluIn1[26]), + .B(aluIn2[26]), + .CI(_0087_[26]), + .CO(_0087_[27]), + .S(aluPlus[26]) + ); + CC_ADDF _1442_ ( + .A(aluIn1[27]), + .B(aluIn2[27]), + .CI(_0087_[27]), + .CO(_0087_[28]), + .S(aluPlus[27]) + ); + CC_ADDF _1443_ ( + .A(aluIn1[28]), + .B(aluIn2[28]), + .CI(_0087_[28]), + .CO(_0087_[29]), + .S(aluPlus[28]) + ); + CC_ADDF _1444_ ( + .A(aluIn1[29]), + .B(aluIn2[29]), + .CI(_0087_[29]), + .CO(_0087_[30]), + .S(aluPlus[29]) + ); + CC_ADDF _1445_ ( + .A(aluIn1[2]), + .B(aluIn2[2]), + .CI(_0087_[2]), + .CO(_0087_[3]), + .S(aluPlus[2]) + ); + CC_ADDF _1446_ ( + .A(aluIn1[30]), + .B(aluIn2[30]), + .CI(_0087_[30]), + .CO(_0087_[31]), + .S(aluPlus[30]) + ); + CC_ADDF _1447_ ( + .A(aluIn1[31]), + .B(aluIn2[31]), + .CI(_0087_[31]), + .CO(_0088_[31]), + .S(aluPlus[31]) + ); + CC_ADDF _1448_ ( + .A(aluIn1[3]), + .B(aluIn2[3]), + .CI(_0087_[3]), + .CO(_0087_[4]), + .S(aluPlus[3]) + ); + CC_ADDF _1449_ ( + .A(aluIn1[4]), + .B(aluIn2[4]), + .CI(_0087_[4]), + .CO(_0087_[5]), + .S(aluPlus[4]) + ); + CC_ADDF _1450_ ( + .A(aluIn1[5]), + .B(aluIn2[5]), + .CI(_0087_[5]), + .CO(_0087_[6]), + .S(aluPlus[5]) + ); + CC_ADDF _1451_ ( + .A(aluIn1[6]), + .B(aluIn2[6]), + .CI(_0087_[6]), + .CO(_0087_[7]), + .S(aluPlus[6]) + ); + CC_ADDF _1452_ ( + .A(aluIn1[7]), + .B(aluIn2[7]), + .CI(_0087_[7]), + .CO(_0087_[8]), + .S(aluPlus[7]) + ); + CC_ADDF _1453_ ( + .A(aluIn1[8]), + .B(aluIn2[8]), + .CI(_0087_[8]), + .CO(_0087_[9]), + .S(aluPlus[8]) + ); + CC_ADDF _1454_ ( + .A(aluIn1[9]), + .B(aluIn2[9]), + .CI(_0087_[9]), + .CO(_0087_[10]), + .S(aluPlus[9]) + ); + CC_ADDF _1455_ ( + .A(aluIn1[0]), + .B(_0089_[0]), + .CI(1'h1), + .CO(_0090_[1]), + .S(aluMinus[0]) + ); + CC_ADDF _1456_ ( + .A(aluIn1[10]), + .B(_0089_[10]), + .CI(_0090_[10]), + .CO(_0090_[11]), + .S(aluMinus[10]) + ); + CC_ADDF _1457_ ( + .A(aluIn1[11]), + .B(_0089_[11]), + .CI(_0090_[11]), + .CO(_0090_[12]), + .S(aluMinus[11]) + ); + CC_ADDF _1458_ ( + .A(aluIn1[12]), + .B(_0089_[12]), + .CI(_0090_[12]), + .CO(_0090_[13]), + .S(aluMinus[12]) + ); + CC_ADDF _1459_ ( + .A(aluIn1[13]), + .B(_0089_[13]), + .CI(_0090_[13]), + .CO(_0090_[14]), + .S(aluMinus[13]) + ); + CC_ADDF _1460_ ( + .A(aluIn1[14]), + .B(_0089_[14]), + .CI(_0090_[14]), + .CO(_0090_[15]), + .S(aluMinus[14]) + ); + CC_ADDF _1461_ ( + .A(aluIn1[15]), + .B(_0089_[15]), + .CI(_0090_[15]), + .CO(_0090_[16]), + .S(aluMinus[15]) + ); + CC_ADDF _1462_ ( + .A(aluIn1[16]), + .B(_0089_[16]), + .CI(_0090_[16]), + .CO(_0090_[17]), + .S(aluMinus[16]) + ); + CC_ADDF _1463_ ( + .A(aluIn1[17]), + .B(_0089_[17]), + .CI(_0090_[17]), + .CO(_0090_[18]), + .S(aluMinus[17]) + ); + CC_ADDF _1464_ ( + .A(aluIn1[18]), + .B(_0089_[18]), + .CI(_0090_[18]), + .CO(_0090_[19]), + .S(aluMinus[18]) + ); + CC_ADDF _1465_ ( + .A(aluIn1[19]), + .B(_0089_[19]), + .CI(_0090_[19]), + .CO(_0090_[20]), + .S(aluMinus[19]) + ); + CC_ADDF _1466_ ( + .A(aluIn1[1]), + .B(_0089_[1]), + .CI(_0090_[1]), + .CO(_0090_[2]), + .S(aluMinus[1]) + ); + CC_ADDF _1467_ ( + .A(aluIn1[20]), + .B(_0089_[20]), + .CI(_0090_[20]), + .CO(_0090_[21]), + .S(aluMinus[20]) + ); + CC_ADDF _1468_ ( + .A(aluIn1[21]), + .B(_0089_[21]), + .CI(_0090_[21]), + .CO(_0090_[22]), + .S(aluMinus[21]) + ); + CC_ADDF _1469_ ( + .A(aluIn1[22]), + .B(_0089_[22]), + .CI(_0090_[22]), + .CO(_0090_[23]), + .S(aluMinus[22]) + ); + CC_ADDF _1470_ ( + .A(aluIn1[23]), + .B(_0089_[23]), + .CI(_0090_[23]), + .CO(_0090_[24]), + .S(aluMinus[23]) + ); + CC_ADDF _1471_ ( + .A(aluIn1[24]), + .B(_0089_[24]), + .CI(_0090_[24]), + .CO(_0090_[25]), + .S(aluMinus[24]) + ); + CC_ADDF _1472_ ( + .A(aluIn1[25]), + .B(_0089_[25]), + .CI(_0090_[25]), + .CO(_0090_[26]), + .S(aluMinus[25]) + ); + CC_ADDF _1473_ ( + .A(aluIn1[26]), + .B(_0089_[26]), + .CI(_0090_[26]), + .CO(_0090_[27]), + .S(aluMinus[26]) + ); + CC_ADDF _1474_ ( + .A(aluIn1[27]), + .B(_0089_[27]), + .CI(_0090_[27]), + .CO(_0090_[28]), + .S(aluMinus[27]) + ); + CC_ADDF _1475_ ( + .A(aluIn1[28]), + .B(_0089_[28]), + .CI(_0090_[28]), + .CO(_0090_[29]), + .S(aluMinus[28]) + ); + CC_ADDF _1476_ ( + .A(aluIn1[29]), + .B(_0089_[29]), + .CI(_0090_[29]), + .CO(_0090_[30]), + .S(aluMinus[29]) + ); + CC_ADDF _1477_ ( + .A(aluIn1[2]), + .B(_0089_[2]), + .CI(_0090_[2]), + .CO(_0090_[3]), + .S(aluMinus[2]) + ); + CC_ADDF _1478_ ( + .A(aluIn1[30]), + .B(_0089_[30]), + .CI(_0090_[30]), + .CO(_0090_[31]), + .S(aluMinus[30]) + ); + CC_ADDF _1479_ ( + .A(aluIn1[31]), + .B(_0089_[31]), + .CI(_0090_[31]), + .CO(_0090_[32]), + .S(aluMinus[31]) + ); + CC_ADDF _1480_ ( + .A(1'h0), + .B(1'h1), + .CI(_0090_[32]), + .CO(_0091_[32]), + .S(LTU) + ); + CC_ADDF _1481_ ( + .A(aluIn1[3]), + .B(_0089_[3]), + .CI(_0090_[3]), + .CO(_0090_[4]), + .S(aluMinus[3]) + ); + CC_ADDF _1482_ ( + .A(aluIn1[4]), + .B(_0089_[4]), + .CI(_0090_[4]), + .CO(_0090_[5]), + .S(aluMinus[4]) + ); + CC_ADDF _1483_ ( + .A(aluIn1[5]), + .B(_0089_[5]), + .CI(_0090_[5]), + .CO(_0090_[6]), + .S(aluMinus[5]) + ); + CC_ADDF _1484_ ( + .A(aluIn1[6]), + .B(_0089_[6]), + .CI(_0090_[6]), + .CO(_0090_[7]), + .S(aluMinus[6]) + ); + CC_ADDF _1485_ ( + .A(aluIn1[7]), + .B(_0089_[7]), + .CI(_0090_[7]), + .CO(_0090_[8]), + .S(aluMinus[7]) + ); + CC_ADDF _1486_ ( + .A(aluIn1[8]), + .B(_0089_[8]), + .CI(_0090_[8]), + .CO(_0090_[9]), + .S(aluMinus[8]) + ); + CC_ADDF _1487_ ( + .A(aluIn1[9]), + .B(_0089_[9]), + .CI(_0090_[9]), + .CO(_0090_[10]), + .S(aluMinus[9]) + ); + CC_BUFG _1488_ ( + .I(_0092_), + .O(_0095_) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1489_ ( + .CLK(_0095_), + .D(_0049_), + .EN(1'h1), + .Q(state[1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1490_ ( + .CLK(_0095_), + .D(_0001_), + .EN(1'h1), + .Q(state[2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h1), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1491_ ( + .CLK(_0095_), + .D(_0052_), + .EN(1'h1), + .Q(state[3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1492_ ( + .CLK(_0095_), + .D(_0078_[0]), + .EN(1'h1), + .Q(cycles[0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1493_ ( + .CLK(_0095_), + .D(_0078_[1]), + .EN(1'h1), + .Q(cycles[1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1494_ ( + .CLK(_0095_), + .D(_0078_[2]), + .EN(1'h1), + .Q(cycles[2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1495_ ( + .CLK(_0095_), + .D(_0078_[3]), + .EN(1'h1), + .Q(cycles[3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1496_ ( + .CLK(_0095_), + .D(_0078_[4]), + .EN(1'h1), + .Q(cycles[4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1497_ ( + .CLK(_0095_), + .D(_0078_[5]), + .EN(1'h1), + .Q(cycles[5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1498_ ( + .CLK(_0095_), + .D(_0078_[6]), + .EN(1'h1), + .Q(cycles[6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1499_ ( + .CLK(_0095_), + .D(_0078_[7]), + .EN(1'h1), + .Q(cycles[7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1500_ ( + .CLK(_0095_), + .D(_0078_[8]), + .EN(1'h1), + .Q(cycles[8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1501_ ( + .CLK(_0095_), + .D(_0078_[9]), + .EN(1'h1), + .Q(cycles[9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1502_ ( + .CLK(_0095_), + .D(_0078_[10]), + .EN(1'h1), + .Q(cycles[10]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1503_ ( + .CLK(_0095_), + .D(_0078_[11]), + .EN(1'h1), + .Q(cycles[11]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1504_ ( + .CLK(_0095_), + .D(_0078_[12]), + .EN(1'h1), + .Q(cycles[12]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1505_ ( + .CLK(_0095_), + .D(_0078_[13]), + .EN(1'h1), + .Q(cycles[13]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1506_ ( + .CLK(_0095_), + .D(_0078_[14]), + .EN(1'h1), + .Q(cycles[14]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1507_ ( + .CLK(_0095_), + .D(_0078_[15]), + .EN(1'h1), + .Q(cycles[15]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1508_ ( + .CLK(_0095_), + .D(_0078_[16]), + .EN(1'h1), + .Q(cycles[16]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1509_ ( + .CLK(_0095_), + .D(_0078_[17]), + .EN(1'h1), + .Q(cycles[17]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1510_ ( + .CLK(_0095_), + .D(_0078_[18]), + .EN(1'h1), + .Q(cycles[18]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1511_ ( + .CLK(_0095_), + .D(_0078_[19]), + .EN(1'h1), + .Q(cycles[19]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1512_ ( + .CLK(_0095_), + .D(_0078_[20]), + .EN(1'h1), + .Q(cycles[20]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1513_ ( + .CLK(_0095_), + .D(_0078_[21]), + .EN(1'h1), + .Q(cycles[21]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1514_ ( + .CLK(_0095_), + .D(_0078_[22]), + .EN(1'h1), + .Q(cycles[22]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1515_ ( + .CLK(_0095_), + .D(_0078_[23]), + .EN(1'h1), + .Q(cycles[23]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1516_ ( + .CLK(_0095_), + .D(_0078_[24]), + .EN(1'h1), + .Q(cycles[24]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1517_ ( + .CLK(_0095_), + .D(_0078_[25]), + .EN(1'h1), + .Q(cycles[25]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1518_ ( + .CLK(_0095_), + .D(_0078_[26]), + .EN(1'h1), + .Q(cycles[26]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1519_ ( + .CLK(_0095_), + .D(_0078_[27]), + .EN(1'h1), + .Q(cycles[27]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1520_ ( + .CLK(_0095_), + .D(_0078_[28]), + .EN(1'h1), + .Q(cycles[28]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1521_ ( + .CLK(_0095_), + .D(_0078_[29]), + .EN(1'h1), + .Q(cycles[29]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1522_ ( + .CLK(_0095_), + .D(_0078_[30]), + .EN(1'h1), + .Q(cycles[30]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1523_ ( + .CLK(_0095_), + .D(_0078_[31]), + .EN(1'h1), + .Q(cycles[31]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1524_ ( + .CLK(_0095_), + .D(_0272_[0]), + .EN(_0001_), + .Q(instr[2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1525_ ( + .CLK(_0095_), + .D(_0144_[0]), + .EN(_0001_), + .Q(instr[3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1526_ ( + .CLK(_0095_), + .D(_0360_[0]), + .EN(_0001_), + .Q(instr[4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1527_ ( + .CLK(_0095_), + .D(_0153_[0]), + .EN(_0001_), + .Q(instr[5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1528_ ( + .CLK(_0095_), + .D(_0261_[0]), + .EN(_0001_), + .Q(instr[6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1529_ ( + .CLK(_0095_), + .D(_0166_[0]), + .EN(_0001_), + .Q(Bimm[11]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1530_ ( + .CLK(_0095_), + .D(_0355_[0]), + .EN(_0001_), + .Q(Bimm[1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1531_ ( + .CLK(_0095_), + .D(_0243_[0]), + .EN(_0001_), + .Q(Bimm[2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1532_ ( + .CLK(_0095_), + .D(_0235_[0]), + .EN(_0001_), + .Q(Bimm[3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1533_ ( + .CLK(_0095_), + .D(_0145_[0]), + .EN(_0001_), + .Q(Bimm[4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1534_ ( + .CLK(_0095_), + .D(_0223_[0]), + .EN(_0001_), + .Q(Jimm[12]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1535_ ( + .CLK(_0095_), + .D(_0154_[0]), + .EN(_0001_), + .Q(Jimm[13]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1536_ ( + .CLK(_0095_), + .D(_0262_[0]), + .EN(_0001_), + .Q(Jimm[14]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1537_ ( + .CLK(_0095_), + .D(_0165_[0]), + .EN(_0001_), + .Q(Jimm[15]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1538_ ( + .CLK(_0095_), + .D(_0214_[0]), + .EN(_0001_), + .Q(Jimm[16]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1539_ ( + .CLK(_0095_), + .D(_0334_[0]), + .EN(_0001_), + .Q(Jimm[17]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1540_ ( + .CLK(_0095_), + .D(_0204_[0]), + .EN(_0001_), + .Q(Jimm[18]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1541_ ( + .CLK(_0095_), + .D(_0144_[1]), + .EN(_0001_), + .Q(Jimm[19]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1542_ ( + .CLK(_0095_), + .D(_0331_[0]), + .EN(_0001_), + .Q(Iimm[0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1543_ ( + .CLK(_0095_), + .D(_0153_[1]), + .EN(_0001_), + .Q(Iimm[1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1544_ ( + .CLK(_0095_), + .D(_0261_[1]), + .EN(_0001_), + .Q(Iimm[2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1545_ ( + .CLK(_0095_), + .D(_0166_[1]), + .EN(_0001_), + .Q(Iimm[3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1546_ ( + .CLK(_0095_), + .D(_0324_[0]), + .EN(_0001_), + .Q(Iimm[4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1547_ ( + .CLK(_0095_), + .D(_0243_[1]), + .EN(_0001_), + .Q(Bimm[5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1548_ ( + .CLK(_0095_), + .D(_0235_[1]), + .EN(_0001_), + .Q(Bimm[6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1549_ ( + .CLK(_0095_), + .D(_0145_[1]), + .EN(_0001_), + .Q(Bimm[7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1550_ ( + .CLK(_0095_), + .D(_0223_[1]), + .EN(_0001_), + .Q(Bimm[8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1551_ ( + .CLK(_0095_), + .D(_0154_[1]), + .EN(_0001_), + .Q(Bimm[9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1552_ ( + .CLK(_0095_), + .D(_0262_[1]), + .EN(_0001_), + .Q(Bimm[10]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1553_ ( + .CLK(_0095_), + .D(_0165_[1]), + .EN(_0001_), + .Q(Bimm[31]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1554_ ( + .CLK(_0095_), + .D(_0050_), + .EN(_0002_), + .Q(PC[0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1555_ ( + .CLK(_0095_), + .D(_0053_), + .EN(_0002_), + .Q(PC[1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1556_ ( + .CLK(_0095_), + .D(_0054_), + .EN(_0002_), + .Q(PC[2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1557_ ( + .CLK(_0095_), + .D(_0055_), + .EN(_0002_), + .Q(PC[3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1558_ ( + .CLK(_0095_), + .D(_0056_), + .EN(_0002_), + .Q(PC[4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1559_ ( + .CLK(_0095_), + .D(_0057_), + .EN(_0002_), + .Q(PC[5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1560_ ( + .CLK(_0095_), + .D(_0058_), + .EN(_0002_), + .Q(PC[6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1561_ ( + .CLK(_0095_), + .D(_0059_), + .EN(_0002_), + .Q(PC[7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1562_ ( + .CLK(_0095_), + .D(_0060_), + .EN(_0002_), + .Q(PC[8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1563_ ( + .CLK(_0095_), + .D(_0061_), + .EN(_0002_), + .Q(PC[9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1564_ ( + .CLK(_0095_), + .D(_0062_), + .EN(_0002_), + .Q(PC[10]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1565_ ( + .CLK(_0095_), + .D(_0063_), + .EN(_0002_), + .Q(PC[11]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1566_ ( + .CLK(_0095_), + .D(_0064_), + .EN(_0002_), + .Q(PC[12]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1567_ ( + .CLK(_0095_), + .D(_0065_), + .EN(_0002_), + .Q(PC[13]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1568_ ( + .CLK(_0095_), + .D(_0066_), + .EN(_0002_), + .Q(PC[14]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1569_ ( + .CLK(_0095_), + .D(_0067_), + .EN(_0002_), + .Q(PC[15]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1570_ ( + .CLK(_0095_), + .D(_0068_), + .EN(_0002_), + .Q(PC[16]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1571_ ( + .CLK(_0095_), + .D(_0069_), + .EN(_0002_), + .Q(PC[17]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1572_ ( + .CLK(_0095_), + .D(_0070_), + .EN(_0002_), + .Q(PC[18]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1573_ ( + .CLK(_0095_), + .D(_0071_), + .EN(_0002_), + .Q(PC[19]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1574_ ( + .CLK(_0095_), + .D(_0072_), + .EN(_0002_), + .Q(PC[20]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1575_ ( + .CLK(_0095_), + .D(_0073_), + .EN(_0002_), + .Q(PC[21]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1576_ ( + .CLK(_0095_), + .D(_0074_), + .EN(_0002_), + .Q(PC[22]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1577_ ( + .CLK(_0095_), + .D(_0075_), + .EN(_0002_), + .Q(PC[23]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'h0), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1578_ ( + .CLK(_0095_), + .D(_0051_), + .EN(_0003_), + .Q(state[0]), + .SR(1'h0) + ); + CC_IBUF _1579_ ( + .I(clk), + .Y(_0092_) + ); + CC_OBUF _1580_ ( + .A(_0004_), + .O(mem_addr[0]) + ); + CC_OBUF _1581_ ( + .A(_0015_), + .O(mem_addr[1]) + ); + CC_OBUF _1582_ ( + .A(_0005_), + .O(mem_addr[10]) + ); + CC_OBUF _1583_ ( + .A(_0006_), + .O(mem_addr[11]) + ); + CC_OBUF _1584_ ( + .A(_0007_), + .O(mem_addr[12]) + ); + CC_OBUF _1585_ ( + .A(_0008_), + .O(mem_addr[13]) + ); + CC_OBUF _1586_ ( + .A(_0009_), + .O(mem_addr[14]) + ); + CC_OBUF _1587_ ( + .A(_0010_), + .O(mem_addr[15]) + ); + CC_OBUF _1588_ ( + .A(_0011_), + .O(mem_addr[16]) + ); + CC_OBUF _1589_ ( + .A(_0012_), + .O(mem_addr[17]) + ); + CC_OBUF _1590_ ( + .A(_0013_), + .O(mem_addr[18]) + ); + CC_OBUF _1591_ ( + .A(_0014_), + .O(mem_addr[19]) + ); + CC_OBUF _1592_ ( + .A(_0020_), + .O(mem_addr[2]) + ); + CC_OBUF _1593_ ( + .A(_0016_), + .O(mem_addr[20]) + ); + CC_OBUF _1594_ ( + .A(_0017_), + .O(mem_addr[21]) + ); + CC_OBUF _1595_ ( + .A(_0018_), + .O(mem_addr[22]) + ); + CC_OBUF _1596_ ( + .A(_0019_), + .O(mem_addr[23]) + ); + CC_OBUF _1597_ ( + .A(1'h0), + .O(mem_addr[24]) + ); + CC_OBUF _1598_ ( + .A(1'h0), + .O(mem_addr[25]) + ); + CC_OBUF _1599_ ( + .A(1'h0), + .O(mem_addr[26]) + ); + CC_OBUF _1600_ ( + .A(1'h0), + .O(mem_addr[27]) + ); + CC_OBUF _1601_ ( + .A(1'h0), + .O(mem_addr[28]) + ); + CC_OBUF _1602_ ( + .A(1'h0), + .O(mem_addr[29]) + ); + CC_OBUF _1603_ ( + .A(_0021_), + .O(mem_addr[3]) + ); + CC_OBUF _1604_ ( + .A(1'h0), + .O(mem_addr[30]) + ); + CC_OBUF _1605_ ( + .A(1'h0), + .O(mem_addr[31]) + ); + CC_OBUF _1606_ ( + .A(_0022_), + .O(mem_addr[4]) + ); + CC_OBUF _1607_ ( + .A(_0023_), + .O(mem_addr[5]) + ); + CC_OBUF _1608_ ( + .A(_0024_), + .O(mem_addr[6]) + ); + CC_OBUF _1609_ ( + .A(_0025_), + .O(mem_addr[7]) + ); + CC_OBUF _1610_ ( + .A(_0026_), + .O(mem_addr[8]) + ); + CC_OBUF _1611_ ( + .A(_0027_), + .O(mem_addr[9]) + ); + CC_IBUF _1612_ ( + .I(mem_rbusy), + .Y(_0096_[9]) + ); + CC_IBUF _1613_ ( + .I(mem_rdata[0]), + .Y(_0374_[1]) + ); + CC_IBUF _1614_ ( + .I(mem_rdata[1]), + .Y(_0367_[0]) + ); + CC_IBUF _1615_ ( + .I(mem_rdata[10]), + .Y(_0235_[0]) + ); + CC_IBUF _1616_ ( + .I(mem_rdata[11]), + .Y(_0145_[0]) + ); + CC_IBUF _1617_ ( + .I(mem_rdata[12]), + .Y(_0223_[0]) + ); + CC_IBUF _1618_ ( + .I(mem_rdata[13]), + .Y(_0154_[0]) + ); + CC_IBUF _1619_ ( + .I(mem_rdata[14]), + .Y(_0262_[0]) + ); + CC_IBUF _1620_ ( + .I(mem_rdata[15]), + .Y(_0165_[0]) + ); + CC_IBUF _1621_ ( + .I(mem_rdata[16]), + .Y(_0214_[0]) + ); + CC_IBUF _1622_ ( + .I(mem_rdata[17]), + .Y(_0334_[0]) + ); + CC_IBUF _1623_ ( + .I(mem_rdata[18]), + .Y(_0204_[0]) + ); + CC_IBUF _1624_ ( + .I(mem_rdata[19]), + .Y(_0144_[1]) + ); + CC_IBUF _1625_ ( + .I(mem_rdata[2]), + .Y(_0272_[0]) + ); + CC_IBUF _1626_ ( + .I(mem_rdata[20]), + .Y(_0331_[0]) + ); + CC_IBUF _1627_ ( + .I(mem_rdata[21]), + .Y(_0153_[1]) + ); + CC_IBUF _1628_ ( + .I(mem_rdata[22]), + .Y(_0261_[1]) + ); + CC_IBUF _1629_ ( + .I(mem_rdata[23]), + .Y(_0166_[1]) + ); + CC_IBUF _1630_ ( + .I(mem_rdata[24]), + .Y(_0324_[0]) + ); + CC_IBUF _1631_ ( + .I(mem_rdata[25]), + .Y(_0243_[1]) + ); + CC_IBUF _1632_ ( + .I(mem_rdata[26]), + .Y(_0235_[1]) + ); + CC_IBUF _1633_ ( + .I(mem_rdata[27]), + .Y(_0145_[1]) + ); + CC_IBUF _1634_ ( + .I(mem_rdata[28]), + .Y(_0223_[1]) + ); + CC_IBUF _1635_ ( + .I(mem_rdata[29]), + .Y(_0154_[1]) + ); + CC_IBUF _1636_ ( + .I(mem_rdata[3]), + .Y(_0144_[0]) + ); + CC_IBUF _1637_ ( + .I(mem_rdata[30]), + .Y(_0262_[1]) + ); + CC_IBUF _1638_ ( + .I(mem_rdata[31]), + .Y(_0165_[1]) + ); + CC_IBUF _1639_ ( + .I(mem_rdata[4]), + .Y(_0360_[0]) + ); + CC_IBUF _1640_ ( + .I(mem_rdata[5]), + .Y(_0153_[0]) + ); + CC_IBUF _1641_ ( + .I(mem_rdata[6]), + .Y(_0261_[0]) + ); + CC_IBUF _1642_ ( + .I(mem_rdata[7]), + .Y(_0166_[0]) + ); + CC_IBUF _1643_ ( + .I(mem_rdata[8]), + .Y(_0355_[0]) + ); + CC_IBUF _1644_ ( + .I(mem_rdata[9]), + .Y(_0243_[0]) + ); + CC_OBUF _1645_ ( + .A(_0028_), + .O(mem_rstrb) + ); + CC_IBUF _1646_ ( + .I(mem_wbusy), + .Y(_0435_[0]) + ); + CC_OBUF _1647_ ( + .A(rs2[0]), + .O(mem_wdata[0]) + ); + CC_OBUF _1648_ ( + .A(rs2[1]), + .O(mem_wdata[1]) + ); + CC_OBUF _1649_ ( + .A(_0442_[1]), + .O(mem_wdata[10]) + ); + CC_OBUF _1650_ ( + .A(_0441_[1]), + .O(mem_wdata[11]) + ); + CC_OBUF _1651_ ( + .A(_0440_[1]), + .O(mem_wdata[12]) + ); + CC_OBUF _1652_ ( + .A(_0439_[1]), + .O(mem_wdata[13]) + ); + CC_OBUF _1653_ ( + .A(_0438_[1]), + .O(mem_wdata[14]) + ); + CC_OBUF _1654_ ( + .A(_0437_[1]), + .O(mem_wdata[15]) + ); + CC_OBUF _1655_ ( + .A(_0029_), + .O(mem_wdata[16]) + ); + CC_OBUF _1656_ ( + .A(_0030_), + .O(mem_wdata[17]) + ); + CC_OBUF _1657_ ( + .A(_0031_), + .O(mem_wdata[18]) + ); + CC_OBUF _1658_ ( + .A(_0032_), + .O(mem_wdata[19]) + ); + CC_OBUF _1659_ ( + .A(rs2[2]), + .O(mem_wdata[2]) + ); + CC_OBUF _1660_ ( + .A(_0033_), + .O(mem_wdata[20]) + ); + CC_OBUF _1661_ ( + .A(_0034_), + .O(mem_wdata[21]) + ); + CC_OBUF _1662_ ( + .A(_0035_), + .O(mem_wdata[22]) + ); + CC_OBUF _1663_ ( + .A(_0036_), + .O(mem_wdata[23]) + ); + CC_OBUF _1664_ ( + .A(_0037_), + .O(mem_wdata[24]) + ); + CC_OBUF _1665_ ( + .A(_0038_), + .O(mem_wdata[25]) + ); + CC_OBUF _1666_ ( + .A(_0039_), + .O(mem_wdata[26]) + ); + CC_OBUF _1667_ ( + .A(_0040_), + .O(mem_wdata[27]) + ); + CC_OBUF _1668_ ( + .A(_0041_), + .O(mem_wdata[28]) + ); + CC_OBUF _1669_ ( + .A(_0042_), + .O(mem_wdata[29]) + ); + CC_OBUF _1670_ ( + .A(rs2[3]), + .O(mem_wdata[3]) + ); + CC_OBUF _1671_ ( + .A(_0043_), + .O(mem_wdata[30]) + ); + CC_OBUF _1672_ ( + .A(_0044_), + .O(mem_wdata[31]) + ); + CC_OBUF _1673_ ( + .A(rs2[4]), + .O(mem_wdata[4]) + ); + CC_OBUF _1674_ ( + .A(rs2[5]), + .O(mem_wdata[5]) + ); + CC_OBUF _1675_ ( + .A(rs2[6]), + .O(mem_wdata[6]) + ); + CC_OBUF _1676_ ( + .A(rs2[7]), + .O(mem_wdata[7]) + ); + CC_OBUF _1677_ ( + .A(_0444_[1]), + .O(mem_wdata[8]) + ); + CC_OBUF _1678_ ( + .A(_0443_[1]), + .O(mem_wdata[9]) + ); + CC_OBUF _1679_ ( + .A(_0045_), + .O(mem_wmask[0]) + ); + CC_OBUF _1680_ ( + .A(_0046_), + .O(mem_wmask[1]) + ); + CC_OBUF _1681_ ( + .A(_0047_), + .O(mem_wmask[2]) + ); + CC_OBUF _1682_ ( + .A(_0048_), + .O(mem_wmask[3]) + ); + CC_IBUF _1683_ ( + .I(reset), + .Y(_0390_[1]) + ); + CC_BRAM_20K #( + .A_CLK_INV(1'h0), + .A_RD_WIDTH(32'sd0), + .A_WR_MODE("NO_CHANGE"), + .A_WR_WIDTH(32'd40), + .B_CLK_INV(1'h0), + .B_RD_WIDTH(32'd40), + .B_WR_MODE("NO_CHANGE"), + .B_WR_WIDTH(32'sd0), + .INIT_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .RAM_MODE("SDP") + ) \registerFile.0.0 ( + .A_ADDR({ 4'h0, Bimm[4:1], Bimm[11], 7'h00 }), + .A_BM({ _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31] }), + .A_CLK(_0095_), + .A_DI(writeBackData[19:0]), + .A_DO(rs2[19:0]), + .A_EN(1'h1), + .A_WE(_0000_[31]), + .B_ADDR({ 4'h0, _0324_[0], _0166_[1], _0261_[1], _0153_[1], _0331_[0], 7'h00 }), + .B_BM({ 8'h00, _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31] }), + .B_CLK(_0095_), + .B_DI({ 8'hxx, writeBackData[31:20] }), + .B_DO({ _0093_[39:32], rs2[31:20] }), + .B_EN(_0001_), + .B_WE(1'h0) + ); + CC_BRAM_20K #( + .A_CLK_INV(1'h0), + .A_RD_WIDTH(32'sd0), + .A_WR_MODE("NO_CHANGE"), + .A_WR_WIDTH(32'd40), + .B_CLK_INV(1'h0), + .B_RD_WIDTH(32'd40), + .B_WR_MODE("NO_CHANGE"), + .B_WR_WIDTH(32'sd0), + .INIT_00(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_01(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_02(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_03(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_04(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_05(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_06(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_07(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_08(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_09(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_0F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_10(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_11(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_12(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_13(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_14(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_15(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_16(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_17(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_18(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_19(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_1F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_20(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_21(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_22(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_23(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_24(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_25(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_26(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_27(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_28(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_29(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_2F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_30(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_31(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_32(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_33(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_34(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_35(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_36(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_37(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_38(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_39(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3A(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3B(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3C(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3D(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3E(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .INIT_3F(320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000), + .RAM_MODE("SDP") + ) \registerFile.1.0 ( + .A_ADDR({ 4'h0, Bimm[4:1], Bimm[11], 7'h00 }), + .A_BM({ _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31] }), + .A_CLK(_0095_), + .A_DI(writeBackData[19:0]), + .A_DO(aluIn1[19:0]), + .A_EN(1'h1), + .A_WE(_0000_[31]), + .B_ADDR({ 4'h0, _0144_[1], _0204_[0], _0334_[0], _0214_[0], _0165_[0], 7'h00 }), + .B_BM({ 8'h00, _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31] }), + .B_CLK(_0095_), + .B_DI({ 8'hxx, writeBackData[31:20] }), + .B_DO({ _0094_[39:32], aluIn1[31:20] }), + .B_EN(_0001_), + .B_WE(1'h0) + ); + assign _0076_[0] = 1'h0; + assign _0077_[30:0] = _0076_[31:1]; + assign _0079_[23:5] = { Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[10:5] }; + assign _0080_[0] = 1'h0; + assign _0081_[22:0] = _0080_[23:1]; + assign _0082_[0] = 1'h0; + assign _0083_[20:0] = _0082_[21:1]; + assign _0085_[0] = 1'h0; + assign _0086_[21:0] = _0085_[22:1]; + assign _0087_[0] = 1'h0; + assign _0088_[30:0] = _0087_[31:1]; + assign _0089_[32] = 1'h1; + assign _0090_[0] = 1'h1; + assign _0091_[31:0] = _0090_[32:1]; + assign _0093_[31:0] = rs2; + assign _0094_[31:0] = aluIn1; + assign { _0096_[11], _0096_[8], _0096_[6], _0096_[4], _0096_[2:0] } = 7'h01; + assign _0097_[1:0] = { aluMinus[5], aluPlus[5] }; + assign _0098_[1:0] = { aluIn1[2], aluIn1[29] }; + assign _0099_[1:0] = { Iimm[0], rs2[0] }; + assign _0100_[2] = _0089_[0]; + assign _0101_[2] = _0089_[0]; + assign _0102_[1:0] = { rs2[2], Iimm[2] }; + assign _0103_[3:2] = _0089_[2:1]; + assign _0104_[2] = _0089_[0]; + assign _0105_[2] = _0089_[1]; + assign _0106_[0] = _0089_[2]; + assign _0107_[3:1] = { _0089_[4:3], _0105_[0] }; + assign _0108_[1] = _0098_[2]; + assign _0109_[3:2] = { _0089_[2], _0105_[0] }; + assign _0110_[3:1] = { _0089_[4:3], _0105_[0] }; + assign _0111_[1] = _0098_[2]; + assign { _0112_[2], _0112_[0] } = { _0089_[0], _0101_[1] }; + assign _0113_[3:2] = { _0089_[1], _0089_[2] }; + assign _0114_[2] = _0089_[0]; + assign _0115_[2] = _0089_[0]; + assign _0116_[3:2] = _0089_[2:1]; + assign _0117_[3:2] = { _0089_[2], _0105_[0] }; + assign _0118_[3] = _0089_[3]; + assign _0119_[2] = _0089_[0]; + assign _0120_[2] = _0089_[0]; + assign _0121_[3:2] = { _0089_[1], _0089_[2] }; + assign _0122_[2] = _0089_[0]; + assign _0123_[2] = _0089_[0]; + assign _0124_[3:2] = _0089_[2:1]; + assign _0125_[2] = _0089_[3]; + assign _0126_[2] = _0089_[0]; + assign _0127_[2] = _0089_[0]; + assign _0128_[2] = _0089_[1]; + assign _0129_[2] = _0089_[0]; + assign _0130_[2] = _0089_[0]; + assign _0131_[2] = _0089_[1]; + assign _0132_[3:2] = _0089_[3:2]; + assign _0133_[3] = _0089_[4]; + assign _0134_[3] = Jimm[14]; + assign _0135_[3] = _0089_[2]; + assign _0136_[3] = _0089_[3]; + assign _0137_[2] = _0089_[0]; + assign _0138_[2:1] = { _0089_[1], _0128_[1] }; + assign _0139_[3:2] = _0089_[3:2]; + assign _0140_[3:2] = { _0089_[2], _0089_[3] }; + assign _0141_[3] = _0089_[4]; + assign { _0142_[3], _0142_[1] } = { Jimm[14], _0134_[0] }; + assign { _0143_[3], _0143_[0] } = { cycles[3], PCplus4[3] }; + assign _0144_[3] = loadstore_addr[1]; + assign _0145_[2] = loadstore_addr[1]; + assign _0146_[1:0] = { _0144_[0], Jimm[13] }; + assign _0147_[1:0] = { instr[2], instr[6] }; + assign _0148_[0] = instr[5]; + assign { _0150_[3], _0150_[1:0] } = { instr[2], instr[6:5] }; + assign _0151_[0] = PCplusImm[3]; + assign _0153_[3:2] = { loadstore_addr[1], _0144_[2] }; + assign _0154_[3:2] = { _0145_[3], loadstore_addr[1] }; + assign _0155_[1:0] = { _0153_[0], Jimm[13] }; + assign { _0156_[3], _0156_[1:0] } = { _0149_[1], PCplusImm[5], _0151_[1] }; + assign _0158_[2] = _0152_[2]; + assign _0159_[1] = Jimm[14]; + assign _0160_[1] = Jimm[14]; + assign _0161_[1] = Jimm[14]; + assign _0162_[3] = _0089_[3]; + assign _0163_[1] = _0089_[4]; + assign _0164_[1] = Jimm[14]; + assign _0165_[2] = loadstore_addr[1]; + assign _0166_[2] = loadstore_addr[1]; + assign _0168_[2:1] = { Jimm[13], Jimm[14] }; + assign { _0169_[3], _0169_[1:0] } = { _0149_[1], Jimm[13], _0166_[1] }; + assign _0170_[1:0] = { _0151_[1], PCplusImm[23] }; + assign _0171_[0] = Iimm[3]; + assign _0172_[2] = _0089_[1]; + assign _0173_[2] = _0089_[1]; + assign _0174_[2] = _0089_[2]; + assign _0175_[2] = _0089_[1]; + assign _0176_[2] = _0089_[1]; + assign _0177_[2] = _0089_[2]; + assign _0178_[3:2] = _0089_[4:3]; + assign { _0179_[3:2], _0179_[0] } = { _0089_[2:1], _0103_[1] }; + assign _0180_[3:2] = { _0089_[3], _0105_[0] }; + assign { _0181_[3], _0181_[0] } = { _0098_[2], _0089_[4] }; + assign _0182_[2] = _0152_[2]; + assign _0183_[1] = Jimm[14]; + assign _0184_[1] = Jimm[14]; + assign _0186_[2] = _0089_[2]; + assign _0187_[2] = _0089_[2]; + assign _0188_[3:2] = _0089_[4:3]; + assign { _0189_[3], _0189_[0] } = { _0098_[2], _0089_[4] }; + assign _0190_[2] = _0152_[2]; + assign _0191_[1] = Jimm[14]; + assign _0192_[3:2] = { _0089_[3], _0110_[0] }; + assign _0193_[3:1] = { _0163_[3:2], _0089_[4] }; + assign _0194_[3] = _0098_[2]; + assign _0195_[3] = _0152_[2]; + assign _0196_[3] = _0098_[2]; + assign _0197_[1] = Jimm[14]; + assign _0198_[1:0] = { _0171_[1], Jimm[19] }; + assign _0199_[1:0] = { _0143_[2], cycles[19] }; + assign _0200_[1] = _0163_[3]; + assign _0201_[2] = _0152_[2]; + assign _0202_[3] = _0098_[2]; + assign _0203_[1] = Jimm[14]; + assign _0204_[3:1] = { _0149_[1], _0169_[2], Jimm[13] }; + assign _0205_[1:0] = { _0143_[1], PCplus4[18] }; + assign _0206_[1:0] = { _0151_[1], PCplusImm[18] }; + assign _0207_[3:2] = { _0163_[2], _0089_[4] }; + assign _0208_[1] = _0163_[3]; + assign _0209_[2] = _0152_[2]; + assign _0210_[0] = _0089_[4]; + assign _0211_[3:1] = { _0089_[3:2], _0140_[0] }; + assign _0212_[3] = _0098_[2]; + assign _0213_[1] = Jimm[14]; + assign _0214_[3:1] = { _0149_[1], _0169_[2], Jimm[13] }; + assign _0216_[3:2] = { _0163_[2], _0089_[4] }; + assign _0217_[1] = _0163_[3]; + assign _0218_[2] = _0152_[2]; + assign _0219_[1] = Jimm[14]; + assign _0220_[1] = Jimm[14]; + assign _0221_[1] = Jimm[14]; + assign _0222_[1] = Jimm[14]; + assign _0223_[3:2] = { _0134_[0], loadstore_addr[1] }; + assign _0224_[1] = _0097_[3]; + assign _0225_[1:0] = { _0223_[0], Jimm[13] }; + assign { _0226_[3], _0226_[1:0] } = { _0149_[1], PCplusImm[12], _0151_[1] }; + assign _0227_[1:0] = { _0171_[1], Jimm[12] }; + assign _0228_[2] = _0152_[2]; + assign _0229_[1:0] = { _0151_[1], PCplusImm[11] }; + assign _0230_[2:0] = { _0225_[2], _0145_[0], Jimm[13] }; + assign _0231_[1] = _0149_[1]; + assign _0232_[1] = Jimm[14]; + assign _0233_[2] = _0152_[2]; + assign _0234_[1] = Jimm[14]; + assign _0235_[2] = loadstore_addr[1]; + assign _0236_[3:1] = { Jimm[13], _0235_[0], Jimm[12] }; + assign _0237_[1:0] = { _0151_[1], PCplusImm[10] }; + assign { _0238_[2], _0238_[0] } = { _0149_[1], _0225_[2] }; + assign _0239_[2] = _0152_[2]; + assign _0240_[3] = _0089_[3]; + assign _0241_[3:1] = { _0098_[2], _0163_[2], _0089_[4] }; + assign _0242_[1] = Jimm[14]; + assign _0243_[3:2] = { _0134_[0], loadstore_addr[1] }; + assign _0244_[2:0] = { _0225_[2], _0243_[0], Jimm[13] }; + assign _0245_[0] = _0149_[1]; + assign _0246_[3:1] = { _0089_[3:2], _0132_[0] }; + assign _0247_[2] = _0089_[3]; + assign _0248_[3:2] = { _0089_[3], _0105_[0] }; + assign _0249_[3] = _0089_[4]; + assign _0250_[1] = _0163_[3]; + assign _0251_[2] = _0152_[2]; + assign _0252_[2:1] = { Jimm[14], _0097_[3] }; + assign _0253_[1] = _0098_[2]; + assign _0254_[3:2] = { _0089_[4], _0163_[0] }; + assign _0255_[1] = _0163_[3]; + assign { _0256_[2], _0256_[0] } = { _0149_[1], _0224_[0] }; + assign _0257_[1:0] = { _0151_[1], PCplusImm[7] }; + assign _0258_[2:1] = { Jimm[14], _0152_[2] }; + assign _0259_[1:0] = { _0258_[3], _0152_[2] }; + assign _0260_[1] = Jimm[14]; + assign _0261_[3:2] = { loadstore_addr[1], _0144_[2] }; + assign _0262_[3:2] = { _0145_[3], loadstore_addr[1] }; + assign _0263_[1:0] = { _0261_[0], Jimm[13] }; + assign _0264_[1] = _0149_[1]; + assign { _0265_[2], _0265_[0] } = { _0089_[1], _0176_[1] }; + assign { _0266_[3:2], _0266_[0] } = { _0089_[3:2], _0187_[1] }; + assign _0267_[3:2] = { _0089_[4], _0241_[0] }; + assign _0268_[1] = _0163_[3]; + assign _0269_[2] = _0152_[2]; + assign _0270_[3:1] = { _0098_[2], _0163_[2], _0089_[4] }; + assign _0271_[1] = Jimm[14]; + assign _0272_[3:1] = { _0145_[3], _0236_[0], Jimm[13] }; + assign _0273_[2] = _0149_[1]; + assign _0274_[1:0] = { _0151_[1], PCplusImm[2] }; + assign { _0275_[2], _0275_[0] } = { _0089_[0], _0137_[1] }; + assign _0276_[2] = _0089_[1]; + assign { _0277_[3:2], _0277_[0] } = { _0089_[3:2], _0266_[1] }; + assign { _0278_[3], _0278_[1:0] } = { _0089_[4:3], _0188_[1] }; + assign _0279_[2] = _0163_[3]; + assign _0280_[2] = _0152_[2]; + assign _0281_[1] = Jimm[14]; + assign { _0282_[2], _0282_[0] } = { _0089_[0], _0275_[1] }; + assign { _0283_[3:2], _0283_[0] } = { _0089_[2:1], _0128_[1] }; + assign _0284_[2:0] = { _0089_[1], _0138_[0], _0128_[0] }; + assign { _0285_[3], _0285_[0] } = _0089_[4:3]; + assign _0286_[1:0] = Jimm[13:12]; + assign { _0287_[3:2], _0287_[0] } = { _0089_[1:0], _0275_[1] }; + assign _0288_[2:0] = { _0089_[0], _0137_[1], _0282_[1] }; + assign _0289_[2] = _0089_[2]; + assign { _0290_[3:2], _0290_[0] } = { _0089_[4:3], _0178_[1] }; + assign _0291_[2:0] = { _0167_[2], loadstore_addr[1], Jimm[13] }; + assign { _0292_[3], _0292_[1:0] } = { state[0], state[2], instr[5] }; + assign _0294_[3:2] = { aluIn1[31], _0089_[31] }; + assign _0295_[1:0] = { _0089_[31], aluIn1[31] }; + assign _0296_[0] = _0163_[3]; + assign _0297_[2] = _0098_[2]; + assign _0298_[2] = _0152_[2]; + assign _0299_[1:0] = { _0143_[2], cycles[30] }; + assign _0300_[2:0] = { aluIn1[30], _0294_[0], _0089_[30] }; + assign _0301_[0] = _0163_[3]; + assign _0302_[2] = _0089_[4]; + assign _0303_[2] = _0098_[2]; + assign _0304_[1] = _0152_[2]; + assign _0306_[2:0] = { _0098_[2], _0279_[1:0] }; + assign _0307_[2] = _0152_[2]; + assign _0308_[0] = _0097_[3]; + assign _0309_[1:0] = { _0111_[0], _0163_[3] }; + assign { _0310_[3], _0310_[1:0] } = { _0152_[2], _0098_[2], _0142_[0] }; + assign _0313_[3:1] = { _0163_[3:2], _0089_[4] }; + assign _0314_[2:0] = { aluIn1[27], _0294_[0], _0089_[27] }; + assign _0315_[3:2] = { _0089_[4], _0193_[0] }; + assign _0316_[0] = _0098_[2]; + assign _0317_[2] = _0152_[2]; + assign _0319_[0] = _0097_[3]; + assign _0320_[1:0] = { _0108_[0], _0163_[3] }; + assign _0321_[2] = _0152_[2]; + assign _0322_[1:0] = { _0268_[0], _0098_[2] }; + assign _0323_[0] = _0152_[2]; + assign _0324_[3:1] = { _0149_[1], _0169_[2], Jimm[13] }; + assign _0325_[1:0] = { _0255_[0], _0098_[2] }; + assign _0326_[0] = _0152_[2]; + assign _0327_[1:0] = { _0143_[1], PCplus4[22] }; + assign _0328_[1:0] = { _0143_[2], cycles[22] }; + assign _0329_[1:0] = { _0250_[0], _0098_[2] }; + assign _0330_[0] = _0152_[2]; + assign _0331_[3:1] = { _0149_[1], _0169_[2], Jimm[13] }; + assign _0332_[1:0] = { _0151_[1], PCplusImm[20] }; + assign _0333_[1:0] = { _0143_[1], PCplus4[20] }; + assign _0334_[3:1] = { _0149_[1], _0169_[2], Jimm[13] }; + assign _0335_[1:0] = { _0151_[1], PCplusImm[17] }; + assign _0336_[1:0] = { _0143_[2], cycles[17] }; + assign _0337_[2:0] = { aluIn1[17], _0294_[0], _0089_[17] }; + assign _0339_[0] = _0098_[2]; + assign _0340_[1] = _0163_[3]; + assign _0341_[2] = _0152_[2]; + assign _0342_[2:1] = { _0149_[1], _0225_[2] }; + assign _0344_[1:0] = { _0217_[0], _0098_[2] }; + assign _0345_[1] = _0152_[2]; + assign _0346_[2:0] = { _0225_[2], _0262_[0], Jimm[13] }; + assign _0347_[0] = _0149_[1]; + assign _0348_[1:0] = { _0340_[0], _0098_[2] }; + assign _0349_[1] = _0152_[2]; + assign _0350_[2:0] = { _0225_[2], _0154_[0], Jimm[13] }; + assign { _0351_[3], _0351_[1:0] } = { _0149_[1], PCplusImm[13], _0151_[1] }; + assign _0352_[1:0] = { _0143_[2], cycles[13] }; + assign _0353_[1:0] = { _0208_[0], _0098_[2] }; + assign _0354_[1] = _0152_[2]; + assign _0355_[2:1] = { loadstore_addr[1], _0324_[0] }; + assign _0356_[3:1] = { Jimm[13], _0355_[0], Jimm[12] }; + assign { _0357_[2], _0357_[0] } = { _0149_[1], _0225_[2] }; + assign _0358_[1:0] = { _0151_[1], PCplusImm[8] }; + assign _0359_[2] = _0152_[2]; + assign _0360_[3:1] = { loadstore_addr[1], _0144_[2], _0331_[0] }; + assign _0361_[1:0] = { _0360_[0], Jimm[13] }; + assign _0362_[1] = _0149_[1]; + assign _0363_[1:0] = { _0151_[1], PCplusImm[4] }; + assign _0364_[0] = _0097_[3]; + assign _0365_[1:0] = { _0316_[1], _0163_[3] }; + assign _0366_[1] = _0152_[2]; + assign _0367_[3:1] = { loadstore_addr[1], _0144_[2], _0334_[0] }; + assign _0368_[1:0] = { _0367_[0], Jimm[13] }; + assign { _0369_[3], _0369_[1:0] } = { _0149_[1], PCplusImm[1], _0151_[1] }; + assign _0371_[1:0] = { _0301_[1], _0098_[2] }; + assign _0372_[2] = _0152_[2]; + assign _0373_[3:1] = { Jimm[13:12], Jimm[14] }; + assign { _0374_[3:2], _0374_[0] } = { loadstore_addr[1], _0144_[2], _0214_[0] }; + assign _0375_[1:0] = { _0374_[1], Jimm[13] }; + assign { _0376_[3], _0376_[1:0] } = { _0149_[1], _0145_[3], _0356_[0] }; + assign _0377_[2:0] = { PC[0], _0143_[1], _0151_[1] }; + assign _0378_[1:0] = { _0143_[2], cycles[0] }; + assign _0379_[1:0] = { _0296_[1], _0098_[2] }; + assign _0380_[2:0] = { _0163_[3], _0297_[1:0] }; + assign _0381_[2] = _0152_[2]; + assign _0385_[1:0] = { _0097_[3], _0098_[2] }; + assign { _0386_[3], _0386_[1:0] } = { LTU, _0294_[0], _0295_[2] }; + assign _0387_[2] = _0143_[1]; + assign _0388_[1:0] = { PCplus4[23], PCplusImm[23] }; + assign _0389_[0] = aluPlus[23]; + assign { _0391_[2], _0391_[0] } = { _0389_[2], aluPlus[22] }; + assign _0392_[1] = _0390_[1]; + assign { _0393_[2], _0393_[0] } = { _0389_[2], aluPlus[21] }; + assign _0394_[1] = _0390_[1]; + assign { _0395_[2], _0395_[0] } = { _0389_[2], aluPlus[20] }; + assign _0396_[1] = _0390_[1]; + assign { _0397_[2], _0397_[0] } = { _0389_[2], aluPlus[19] }; + assign _0398_[1] = _0390_[1]; + assign { _0399_[2], _0399_[0] } = { _0389_[2], aluPlus[18] }; + assign _0400_[1] = _0390_[1]; + assign { _0401_[2], _0401_[0] } = { _0389_[2], aluPlus[17] }; + assign _0402_[1] = _0390_[1]; + assign { _0403_[2], _0403_[0] } = { _0389_[2], aluPlus[16] }; + assign _0404_[1] = _0390_[1]; + assign { _0405_[2], _0405_[0] } = { _0389_[2], aluPlus[15] }; + assign _0406_[1] = _0390_[1]; + assign { _0407_[2], _0407_[0] } = { _0389_[2], aluPlus[14] }; + assign _0408_[1] = _0390_[1]; + assign { _0409_[2], _0409_[0] } = { _0389_[2], aluPlus[13] }; + assign _0410_[1] = _0390_[1]; + assign { _0411_[2], _0411_[0] } = { _0389_[2], aluPlus[12] }; + assign _0412_[1] = _0390_[1]; + assign { _0413_[2], _0413_[0] } = { _0389_[2], aluPlus[11] }; + assign _0414_[1] = _0390_[1]; + assign { _0415_[2], _0415_[0] } = { _0389_[2], aluPlus[10] }; + assign _0416_[1] = _0390_[1]; + assign { _0417_[2], _0417_[0] } = { _0389_[2], aluPlus[9] }; + assign _0418_[1] = _0390_[1]; + assign { _0419_[2], _0419_[0] } = { _0389_[2], aluPlus[8] }; + assign _0420_[1] = _0390_[1]; + assign { _0421_[2], _0421_[0] } = { _0389_[2], aluPlus[7] }; + assign _0422_[1] = _0390_[1]; + assign { _0423_[2], _0423_[0] } = { _0389_[2], aluPlus[6] }; + assign _0424_[1] = _0390_[1]; + assign { _0425_[2], _0425_[0] } = { _0389_[2], aluPlus[5] }; + assign _0426_[1] = _0390_[1]; + assign { _0427_[2], _0427_[0] } = { _0389_[2], aluPlus[4] }; + assign _0428_[1] = _0390_[1]; + assign { _0429_[2], _0429_[0] } = { _0389_[2], aluPlus[3] }; + assign _0430_[1] = _0390_[1]; + assign { _0431_[2], _0431_[0] } = { _0389_[2], aluPlus[2] }; + assign _0432_[1] = _0390_[1]; + assign { _0433_[2], _0433_[0] } = { _0389_[2], aluPlus[1] }; + assign _0434_[1] = _0390_[1]; + assign _0435_[2:1] = { state[3], _0096_[9] }; + assign { _0436_[3], _0436_[1:0] } = { _0390_[1], _0148_[1], state[2] }; + assign { _0437_[3:2], _0437_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[31] }; + assign { _0438_[3:2], _0438_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[30] }; + assign { _0439_[3:2], _0439_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[29] }; + assign { _0440_[3:2], _0440_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[28] }; + assign { _0441_[3:2], _0441_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[27] }; + assign { _0442_[3:2], _0442_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[26] }; + assign { _0443_[3:2], _0443_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[25] }; + assign { _0444_[3:2], _0444_[0] } = { loadstore_addr[0], loadstore_addr[1], rs2[24] }; + assign _0445_[1:0] = { _0292_[2], _0390_[0] }; + assign _0446_[1:0] = { _0292_[2], _0392_[0] }; + assign _0447_[1:0] = { _0292_[2], _0394_[0] }; + assign _0448_[1:0] = { _0292_[2], _0396_[0] }; + assign _0449_[1:0] = { _0292_[2], _0398_[0] }; + assign _0450_[1:0] = { _0292_[2], _0400_[0] }; + assign _0451_[1:0] = { _0292_[2], _0402_[0] }; + assign _0452_[1:0] = { _0292_[2], _0404_[0] }; + assign _0453_[1:0] = { _0292_[2], _0406_[0] }; + assign _0454_[1:0] = { _0292_[2], _0408_[0] }; + assign _0455_[1:0] = { _0292_[2], _0410_[0] }; + assign _0456_[1:0] = { _0292_[2], _0412_[0] }; + assign _0457_[1:0] = { _0292_[2], _0414_[0] }; + assign _0458_[1:0] = { _0292_[2], _0416_[0] }; + assign _0459_[1:0] = { _0292_[2], _0418_[0] }; + assign _0460_[1:0] = { _0292_[2], _0420_[0] }; + assign _0461_[1:0] = { _0292_[2], _0422_[0] }; + assign _0462_[1:0] = { _0292_[2], _0424_[0] }; + assign _0463_[1:0] = { _0292_[2], _0426_[0] }; + assign _0464_[1:0] = { _0292_[2], _0428_[0] }; + assign _0465_[1:0] = { _0292_[2], _0430_[0] }; + assign _0466_[1:0] = { _0292_[2], _0432_[0] }; + assign _0467_[1:0] = { _0292_[2], _0434_[0] }; + assign _0468_[3:1] = { state[0], state[1], PC[0] }; + assign _0469_[2:1] = { _0390_[1], _0292_[2] }; + assign { _0470_[3:2], _0470_[0] } = { _0099_[2], instr[4], Bimm[4] }; + assign _0471_[1:0] = { state[2], state[3] }; + assign { Bimm[30:12], Bimm[0] } = { Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], 1'h0 }; + assign Iimm[31:5] = { Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[10:5] }; + assign { Jimm[31:20], Jimm[11:0] } = { Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Bimm[31], Iimm[0], Bimm[10:5], Iimm[4:1], 1'h0 }; + assign PCplus4[1:0] = PC[1:0]; + assign PCplusImm[0] = PC[0]; + assign aluMinus[32] = LTU; + assign instr[31:7] = { Bimm[31], Bimm[10:5], Iimm[4:0], Jimm[19:12], Bimm[4:1], Bimm[11] }; + assign _0000_[30:0] = { _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31], _0000_[31] }; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/3.femtorv32-quark-bicycle-gowin/src/femtorv32_quark_bicycle.v b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/3.femtorv32-quark-bicycle-gowin/src/femtorv32_quark_bicycle.v new file mode 100644 index 0000000000000000000000000000000000000000..e8890100f799f4e4bb87431a0af6d380aa428979 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/3.femtorv32-quark-bicycle-gowin/src/femtorv32_quark_bicycle.v @@ -0,0 +1,409 @@ +/*******************************************************************/ +// FemtoRV32, a collection of minimalistic RISC-V RV32 cores. +// This version: The "Quark", the most elementary version of FemtoRV32. +// A single VERILOG file, compact & understandable code. +// (200 lines of code, 400 lines counting comments) +// +// Instruction set: RV32I + RDCYCLES +// +// Parameters: +// Reset address can be defined using RESET_ADDR (default is 0). +// +// The ADDR_WIDTH parameter lets you define the width of the internal +// address bus (and address computation logic). +// +// Macros: +// optionally one may define NRV_IS_IO_ADDR(addr), that is supposed to: +// evaluate to 1 if addr is in mapped IO space, +// evaluate to 0 otherwise +// (additional wait states are used when in IO space). +// If left undefined, wait states are always used. +// +// NRV_COUNTER_WIDTH may be defined to reduce the number of bits used +// by the ticks counter. If not defined, a 32-bits counter is generated. +// (reducing its width may be useful for space-constrained designs). +// +// Bruno Levy, Matthias Koch, 2020-2021 +/*******************************************************************/ + +// Firmware generation flags for this processor +`define NRV_ARCH "rv32i" +`define NRV_ABI "ilp32" +`define NRV_OPTIMIZE "-Os" + +module FemtoRV32( + input clk, + + output [31:0] mem_addr, // address bus + output [31:0] mem_wdata, // data to be written + output [3:0] mem_wmask, // write mask for the 4 bytes of each word + input [31:0] mem_rdata, // input lines for both data and instr + output mem_rstrb, // active to initiate memory read (used by IO) + input mem_rbusy, // asserted if memory is busy reading value + input mem_wbusy, // asserted if memory is busy writing value + + input reset // set to 0 to reset the processor +); + + parameter RESET_ADDR = 32'h00000000; + parameter ADDR_WIDTH = 24; + + /***************************************************************************/ + // Instruction decoding. + /***************************************************************************/ + + // Extracts rd,rs1,rs2,funct3,imm and opcode from instruction. + // Reference: Table page 104 of: + // https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf + + // The destination register + wire [4:0] rdId = instr[11:7]; + + // The ALU function, decoded in 1-hot form (doing so reduces LUT count) + // It is used as follows: funct3Is[val] <=> funct3 == val + (* onehot *) + wire [7:0] funct3Is = 8'b00000001 << instr[14:12]; + + // The five immediate formats, see RiscV reference (link above), Fig. 2.4 p. 12 + wire [31:0] Uimm = { instr[31], instr[30:12], {12{1'b0}}}; + wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]}; + /* verilator lint_off UNUSED */ // MSBs of SBJimms are not used by addr adder. + wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]}; + wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0}; + wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0}; + /* verilator lint_on UNUSED */ + + // Base RISC-V (RV32I) has only 10 different instructions ! + wire isLoad = (instr[6:2] == 5'b00000); // rd <- mem[rs1+Iimm] + wire isALUimm = (instr[6:2] == 5'b00100); // rd <- rs1 OP Iimm + wire isAUIPC = (instr[6:2] == 5'b00101); // rd <- PC + Uimm + wire isStore = (instr[6:2] == 5'b01000); // mem[rs1+Simm] <- rs2 + wire isALUreg = (instr[6:2] == 5'b01100); // rd <- rs1 OP rs2 + wire isLUI = (instr[6:2] == 5'b01101); // rd <- Uimm + wire isBranch = (instr[6:2] == 5'b11000); // if(rs1 OP rs2) PC<-PC+Bimm + wire isJALR = (instr[6:2] == 5'b11001); // rd <- PC+4; PC<-rs1+Iimm + wire isJAL = (instr[6:2] == 5'b11011); // rd <- PC+4; PC<-PC+Jimm + wire isSYSTEM = (instr[6:2] == 5'b11100); // rd <- cycles + + wire isALU = isALUimm | isALUreg; + + /***************************************************************************/ + // The register file. + /***************************************************************************/ + + reg [31:0] rs1; + reg [31:0] rs2; + reg [31:0] registerFile [31:0]; + + always @(posedge clk) begin + if (writeBack) + if (rdId != 0) + registerFile[rdId] <= writeBackData; + end + + /***************************************************************************/ + // The ALU. Does operations and tests combinatorially, except shifts. + /***************************************************************************/ + + // First ALU source, always rs1 + wire [31:0] aluIn1 = rs1; + + // Second ALU source, depends on opcode: + // ALUreg, Branch: rs2 + // ALUimm, Load, JALR: Iimm + wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm; + + // The adder is used by both arithmetic instructions and JALR. + wire [31:0] aluPlus = aluIn1 + aluIn2; + + // Use a single 33 bits subtract to do subtraction and all comparisons + // (trick borrowed from swapforth/J1) + wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1; + wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32]; + wire LTU = aluMinus[32]; + wire EQ = (aluMinus[31:0] == 0); + + /***************************************************************************/ + + // Use the same shifter both for left and right shifts by + // applying bit reversal + + wire [31:0] shifter_in = funct3Is[1] ? + {aluIn1[ 0], aluIn1[ 1], aluIn1[ 2], aluIn1[ 3], aluIn1[ 4], aluIn1[ 5], + aluIn1[ 6], aluIn1[ 7], aluIn1[ 8], aluIn1[ 9], aluIn1[10], aluIn1[11], + aluIn1[12], aluIn1[13], aluIn1[14], aluIn1[15], aluIn1[16], aluIn1[17], + aluIn1[18], aluIn1[19], aluIn1[20], aluIn1[21], aluIn1[22], aluIn1[23], + aluIn1[24], aluIn1[25], aluIn1[26], aluIn1[27], aluIn1[28], aluIn1[29], + aluIn1[30], aluIn1[31]} : aluIn1; + + /* verilator lint_off WIDTH */ + wire [31:0] shifter = + $signed({instr[30] & aluIn1[31], shifter_in}) >>> aluIn2[4:0]; + /* verilator lint_on WIDTH */ + + wire [31:0] leftshift = { + shifter[ 0], shifter[ 1], shifter[ 2], shifter[ 3], shifter[ 4], + shifter[ 5], shifter[ 6], shifter[ 7], shifter[ 8], shifter[ 9], + shifter[10], shifter[11], shifter[12], shifter[13], shifter[14], + shifter[15], shifter[16], shifter[17], shifter[18], shifter[19], + shifter[20], shifter[21], shifter[22], shifter[23], shifter[24], + shifter[25], shifter[26], shifter[27], shifter[28], shifter[29], + shifter[30], shifter[31]}; + + /***************************************************************************/ + + // Notes: + // - instr[30] is 1 for SUB and 0 for ADD + // - for SUB, need to test also instr[5] to discriminate ADDI: + // (1 for ADD/SUB, 0 for ADDI, and Iimm used by ADDI overlaps bit 30 !) + // - instr[30] is 1 for SRA (do sign extension) and 0 for SRL + + wire [31:0] aluOut = + (funct3Is[0] ? instr[30] & instr[5] ? aluMinus[31:0] : aluPlus : 32'b0) | + (funct3Is[1] ? leftshift : 32'b0) | + (funct3Is[2] ? {31'b0, LT} : 32'b0) | + (funct3Is[3] ? {31'b0, LTU} : 32'b0) | + (funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b0) | + (funct3Is[5] ? shifter : 32'b0) | + (funct3Is[6] ? aluIn1 | aluIn2 : 32'b0) | + (funct3Is[7] ? aluIn1 & aluIn2 : 32'b0) ; + + /***************************************************************************/ + // The predicate for conditional branches. + /***************************************************************************/ + + wire predicate = + funct3Is[0] & EQ | // BEQ + funct3Is[1] & !EQ | // BNE + funct3Is[4] & LT | // BLT + funct3Is[5] & !LT | // BGE + funct3Is[6] & LTU | // BLTU + funct3Is[7] & !LTU ; // BGEU + + /***************************************************************************/ + // Program counter and branch target computation. + /***************************************************************************/ + + reg [ADDR_WIDTH-1:0] PC; // The program counter. + reg [31:2] instr; // Latched instruction. Note that bits 0 and 1 are + // ignored (not used in RV32I base instr set). + + wire [ADDR_WIDTH-1:0] PCplus4 = PC + 4; + + // An adder used to compute branch address, JAL address and AUIPC. + // branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm + // Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm) + wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] : + instr[4] ? Uimm[ADDR_WIDTH-1:0] : + Bimm[ADDR_WIDTH-1:0] ); + + // A separate adder to compute the destination of load/store. + // testing instr[5] is equivalent to testing isStore in this context. + wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] + + (instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]); + + /* verilator lint_off WIDTH */ + // internal address registers and cycles counter may have less than + // 32 bits, so we deactivate width test for mem_addr and writeBackData + + wire [ADDR_WIDTH-1:0] PC_new = + isJALR ? {aluPlus[ADDR_WIDTH-1:1],1'b0} : + jumpToPCplusImm ? PCplusImm : + PCplus4; + + assign mem_addr = state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ? PC : + state[EXECUTE_bit] & ~isLoad & ~isStore ? PC_new : + loadstore_addr ; + + /***************************************************************************/ + // The value written back to the register file. + /***************************************************************************/ + + wire [31:0] writeBackData = + (isSYSTEM ? cycles : 32'b0) | // SYSTEM + (isLUI ? Uimm : 32'b0) | // LUI + (isALU ? aluOut : 32'b0) | // ALUreg, ALUimm + (isAUIPC ? PCplusImm : 32'b0) | // AUIPC + (isJALR | isJAL ? PCplus4 : 32'b0) | // JAL, JALR + (isLoad ? LOAD_data : 32'b0) ; // Load + + /* verilator lint_on WIDTH */ + + + /***************************************************************************/ + // LOAD/STORE + /***************************************************************************/ + + // All memory accesses are aligned on 32 bits boundary. For this + // reason, we need some circuitry that does unaligned halfword + // and byte load/store, based on: + // - funct3[1:0]: 00->byte 01->halfword 10->word + // - mem_addr[1:0]: indicates which byte/halfword is accessed + + wire mem_byteAccess = instr[13:12] == 2'b00; // funct3[1:0] == 2'b00; + wire mem_halfwordAccess = instr[13:12] == 2'b01; // funct3[1:0] == 2'b01; + + // LOAD, in addition to funct3[1:0], LOAD depends on: + // - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion + + wire LOAD_sign = + !instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]); + + wire [31:0] LOAD_data = + mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} : + mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} : + mem_rdata ; + + wire [15:0] LOAD_halfword = + loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0]; + + wire [7:0] LOAD_byte = + loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0]; + + // STORE + + assign mem_wdata[ 7: 0] = rs2[7:0]; + assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8]; + assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16]; + assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] : + loadstore_addr[1] ? rs2[15:8] : rs2[31:24]; + + // The memory write mask: + // 1111 if writing a word + // 0011 or 1100 if writing a halfword + // (depending on loadstore_addr[1]) + // 0001, 0010, 0100 or 1000 if writing a byte + // (depending on loadstore_addr[1:0]) + + wire [3:0] STORE_wmask = + mem_byteAccess ? + (loadstore_addr[1] ? + (loadstore_addr[0] ? 4'b1000 : 4'b0100) : + (loadstore_addr[0] ? 4'b0010 : 4'b0001) + ) : + mem_halfwordAccess ? + (loadstore_addr[1] ? 4'b1100 : 4'b0011) : + 4'b1111; + + /*************************************************************************/ + // And, last but not least, the state machine. + /*************************************************************************/ + + localparam FETCH_INSTR_bit = 0; + localparam WAIT_INSTR_bit = 1; + localparam EXECUTE_bit = 2; + localparam WAIT_ALU_OR_MEM_bit = 3; + localparam NB_STATES = 4; + + localparam FETCH_INSTR = 1 << FETCH_INSTR_bit; + localparam WAIT_INSTR = 1 << WAIT_INSTR_bit; + localparam EXECUTE = 1 << EXECUTE_bit; + localparam WAIT_ALU_OR_MEM = 1 << WAIT_ALU_OR_MEM_bit; + + (* onehot *) + reg [NB_STATES-1:0] state; + + // The signals (internal and external) that are determined + // combinatorially from state and other signals. + + // register write-back enable. + wire writeBack = ~(isBranch | isStore ) & + (state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]); + + // The memory-read signal. + assign mem_rstrb = state[EXECUTE_bit] & ~isStore | state[FETCH_INSTR_bit]; + + // The mask for memory-write. + assign mem_wmask = {4{state[EXECUTE_bit] & isStore}} & STORE_wmask; + + wire jumpToPCplusImm = isJAL | (isBranch & predicate); +`ifdef NRV_IS_IO_ADDR + wire needToWait = isLoad | + isStore & `NRV_IS_IO_ADDR(mem_addr) ; +`else + wire needToWait = isLoad | isStore ; +`endif + + always @(posedge clk) begin + if(!reset) begin + state <= WAIT_ALU_OR_MEM; // Just waiting for !mem_wbusy + PC <= RESET_ADDR[ADDR_WIDTH-1:0]; + end else + + // See note [1] at the end of this file. + (* parallel_case *) + case(1'b1) + + state[WAIT_INSTR_bit]: begin + if(!mem_rbusy) begin // may be high when executing from SPI flash + rs1 <= registerFile[mem_rdata[19:15]]; + rs2 <= registerFile[mem_rdata[24:20]]; + instr <= mem_rdata[31:2]; // Bits 0 and 1 are ignored (see + state <= EXECUTE; // also the declaration of instr). + end + end + + state[EXECUTE_bit]: begin + PC <= PC_new; + state <= needToWait ? WAIT_ALU_OR_MEM : WAIT_INSTR; + end + + state[WAIT_ALU_OR_MEM_bit]: begin + if(!mem_rbusy & !mem_wbusy) state <= FETCH_INSTR; + end + + default: begin // FETCH_INSTR + state <= WAIT_INSTR; + end + + endcase + end + + /***************************************************************************/ + // Cycle counter + /***************************************************************************/ + +`ifdef NRV_COUNTER_WIDTH + reg [`NRV_COUNTER_WIDTH-1:0] cycles; +`else + reg [31:0] cycles; +`endif + always @(posedge clk) cycles <= cycles + 1; + +`ifdef BENCH + initial begin + cycles = 0; + registerFile[0] = 0; + end +`endif + +endmodule + +/*****************************************************************************/ +// Notes: +// +// [1] About the "reverse case" statement, also used in Claire Wolf's picorv32: +// It is just a cleaner way of writing a series of cascaded if() statements, +// To understand it, think about the case statement *in general* as follows: +// case (expr) +// val_1: statement_1 +// val_2: statement_2 +// ... val_n: statement_n +// endcase +// The first statement_i such that expr == val_i is executed. +// Now if expr is 1'b1: +// case (1'b1) +// cond_1: statement_1 +// cond_2: statement_2 +// ... cond_n: statement_n +// endcase +// It is *exactly the same thing*, the first statement_i such that +// expr == cond_i is executed (that is, such that 1'b1 == cond_i, +// in other words, such that cond_i is true) +// More on this: +// https://stackoverflow.com/questions/15418636/case-statement-in-verilog +// +// [2] state uses 1-hot encoding (at any time, state has only one bit set to 1). +// It uses a larger number of bits (one bit per state), but often results in +// a both more compact (fewer LUTs) and faster state machine. + diff --git a/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/README.md b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/README.md new file mode 100644 index 0000000000000000000000000000000000000000..f0315790c236e34a37588ed76ac18d66fd71d620 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/10.femtorv32-quark-bicycle/README.md @@ -0,0 +1,17 @@ +# FemtoRV32-Quark-Bicycle - A Minimalist RV32I RISC-V Implementation + +## * WORK IN PROGRESS * UNDER CONSTRUCTION * +> WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN' + +## Resource Utilization +FemtoRV32-Quark-Bicycle is a compact, 400-line RV32I implementation derived from the [learn_fpga](https://github.com/BrunoLevy/learn-fpga) repository. This project originates from a [discussion](https://github.com/chili-chips-ba/openCologne/issues/57) aimed at identifying optimal design cases where GateMate FPGA can excel and demonstrate strengths in specific scenarios. **In this case, we're porting only the CPU, without any periferals, as a theoretical consideration on how well the FPGA hosts CPUs.** + +Below are the resource utilization figures. The [discussion](https://github.com/chili-chips-ba/openCologne/issues/57) highlights the potential advantages of GateMate's multiplexing capabilities, particularly in scenarios involving wide multiplexers for register file writebacks and program counter control. While this test case is comparable in terms of resource usage, GateMate's efficiency per configuration bit (area) still falls short of being a clear winner. + +>Note: Contrary to [spaceinvaders-fpga](https://github.com/chili-chips-ba/openCologne/tree/main/8.StressTest/8.spaceinvaders-fpga), Gowin uses Semi-Dual Port BRAM in this design which brings the two chips equal in BRAM blocks utilization. + +| **Resource** | **GW2AR-18C** | **CCGM1A1** | +|----------------|--------------------------------------------|---------------------------------------| +| **Logic/CPE** | 1019 (877 LUT, 142 ALU) / 20736 (~5% usage) | 1116 CPEs / 20480 (5.4% usage) | +| **Registers** | 89 / 15730 (<1% usage) | 90 / 40960 (<1% usage) | +| **Block RAM** | 2 / 46 (~5% usage) | 2 / 32 (6.3% usage) | diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/constraints/top.timing.sdc b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/constraints/top.timing.sdc new file mode 100644 index 0000000000000000000000000000000000000000..e468e4b9e70a2cadd389eb5bdedef77bd9a7536e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/constraints/top.timing.sdc @@ -0,0 +1,8 @@ +#======================================= +# Timing Constraints file +#======================================= + +# 37ns = 27MHz, which is the frequency of external XTAL oscillator +create_clock -name clk -period 37.037 -waveform {0 18.518} [get_ports {clk}] + +#___End-of-File \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/lutram_16x10.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/lutram_16x10.sv new file mode 100644 index 0000000000000000000000000000000000000000..28310dff351447237a60b2f6f27ea6ac38866901 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/lutram_16x10.sv @@ -0,0 +1,44 @@ +//======================================================================== +// openCologne * NLnet-sponsored open-source design ware for GateMate +//========================================================================== +// Copyright (C) 2023 Chili.CHIPS*ba +//-------------------------------------------------------------------------- +// PROPRIETARY INFORMATION +// +// The information contained in this file is the property of CHILI CHIPS LLC. +// Except as specifically authorized in writing by CHILI CHIPS LLC, the holder +// of this file: (1) shall keep all information contained herein confidential; +// and (2) shall protect the same in whole or in part from disclosure and +// dissemination to all third parties; and (3) shall use the same for operation +// and maintenance purposes only. +//-------------------------------------------------------------------------- +// Description: +// +//========================================================================== +module lutram_16x10( + input logic clk, + input logic [9:0] wdat, + input logic [3:0] addr, + input logic we, + output logic [9:0] rdat +); + +logic [9:0] dist_mem [16]; + +always_comb begin : _read_block + rdat = dist_mem[addr]; +end: _read_block + +always_ff @(posedge clk) begin : _write_block + if(we == 1'b1) begin + dist_mem[addr] <= wdat; + end +end: _write_block + +endmodule +/* +------------------------------------------------------------------------------ +Version History: +------------------------------------------------------------------------------ + 2024/8/20 Tarik Ibrahimovic: Initial Creation +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/top.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/top.sv new file mode 100644 index 0000000000000000000000000000000000000000..9a2d462e073c6de5c5017dcc93f145a20d6f3b3f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/1.hw/top.sv @@ -0,0 +1,68 @@ +//========================================================================== +// Copyright (C) 2023 Chili.CHIPS*ba +//-------------------------------------------------------------------------- +// PROPRIETARY INFORMATION +// +// The information contained in this file is the property of CHILI CHIPS LLC. +// Except as specifically authorized in writing by CHILI CHIPS LLC, the holder +// of this file: (1) shall keep all information contained herein confidential; +// and (2) shall protect the same in whole or in part from disclosure and +// dissemination to all third parties; and (3) shall use the same for operation +// and maintenance purposes only. +//-------------------------------------------------------------------------- +// Description: LUTRAM arrays for capacity stress testing different FPGAs +//========================================================================== + +/* verilator lint_off PINMISSING */ +module top +#( + parameter LUTRAM16X10 = 30 +) +( + input logic clk, + + input logic [$clog2(LUTRAM16X10 * 16)-1 : 0] addr, + input logic we, + input logic [9:0] wdat, + output logic [9:0] rdat +); +localparam ADDR_BITS = $clog2(LUTRAM16X10 * 16)-1; + +logic [9:0] read_all [LUTRAM16X10]; + + +logic [LUTRAM16X10-1:0] we_dec; + +always_comb begin : _decode + we_dec = '0; // Initialize to 0 + if(LUTRAM16X10 > 1) begin + we_dec [addr[ADDR_BITS:4]] = 1'b1 & we; + rdat = read_all [addr[ADDR_BITS:4]]; + end + else begin // corner cases + we_dec = we; + rdat = read_all[0]; + end + +end +genvar i; +generate + for(i = 0; i < LUTRAM16X10; i++) begin + lutram_16x10 u_lut( + .clk(clk), + .addr(addr[3:0]), + .rdat(read_all[i]), //maybe ill need a better description of a read mux + .wdat(wdat), + .we(we_dec[i]) + ); + end +endgenerate + +endmodule: top + +/* +------------------------------------------------------------------------------ +Version History: +------------------------------------------------------------------------------ + 2024/8/20 Tarik Ibrahimovic: Initial Creation +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/models/cpelib_prim_sim.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/models/cpelib_prim_sim.sv new file mode 100644 index 0000000000000000000000000000000000000000..182886de4887feda8ecd9b5afdab38c4a682cff3 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/models/cpelib_prim_sim.sv @@ -0,0 +1,3134 @@ +/* + * cpelib.v + * + * Gate level description of a CPE using a set of simplified library elements + * for post-implementation simulation with back annotated timings. + * + * Copyright (C) 2024 Cologne Chip AG + * + * Revision history: + * 2024-03-27 - Fixed CPE_TOBF enable polarity. + * 2024-01-31 - Added missing C_D, C_DST and C_DRS specify timing constraints. + * 2023-12-20 - Added CINY2 path for timing simulation. + * 2023-12-20 - Added CC_PLL lock in time and specify block. + * 2023-12-19 - Fixed C_ADDF2 and C_ADDF2x CIN signal declaration. + * 2023-12-19 - Fixed CC_IO_SEL GPIO_EN signal. + * 2023-12-19 - Added CPE_TOBF module. + * 2023-06-19 - Prevent implicit declarations. + * 2023-05-18 - Add FIFO status signals to Block RAM. + * 2023-03-20 - Enable Block RAM initialization. + * 2023-02-21 - Added C_D, C_DST and C_DRS initial values. + * 2023-02-13 - Fixed CADD_{A,S} in C_ADDFx. + * 2022-12-02 - Added CC_IO_SEL module. + * 2022-11-01 - C_D, C_DST, C_DRS revision. + * 2022-08-29 - C_MULT, C_AND and C_OR revision. + * 2022-06-01 - Initial version. + */ + +`timescale 1 ps / 1 ps + +`define USE_PLL +`define xUSE_RAM +`define xUSE_TIMING +`define xUSE_TIMINGCHECKS + +module CPE_IBF #( + parameter [71:0] BUF_CFG = 72'b0 +)( + input I, + output Y +); + assign Y = I; + +`ifdef USE_TIMING + specify + (I => Y) = 0; + endspecify +`endif +endmodule + + +module CPE_OBF #( + parameter [71:0] BUF_CFG = 72'b0 +)( + input A, + output O +); + assign O = A; + +`ifdef USE_TIMING + specify + (A => O) = 0; + endspecify +`endif +endmodule + + +module CPE_TOBF #( + parameter [71:0] BUF_CFG = 72'b0 +)( + input A, EN, + output O +); + assign O = EN ? A : 1'bz; + +endmodule + + +module CPE_IOBF #( + parameter [71:0] BUF_CFG = 72'b0 +)( + input A, EN, + output Y, + inout O +); + assign O = EN ? A : 1'bz; + assign Y = O; + +`ifdef USE_TIMING + specify + (A => O) = 0; + (EN => O) = 0; + (A => Y) = 0; + (EN => Y) = 0; + (O => Y) = 0; + endspecify +`endif +endmodule + + +module CPE_LVDS_IBF #( + parameter [71:0] BUF_CFG = 72'b0 +)( + input I, IB, + output Y +); + + assign Y = I; + +`ifdef USE_TIMING + specify + (I => Y) = 0; + (IB => Y) = 0; + endspecify +`endif +endmodule + + +module CPE_LVDS_OBF #( + parameter [71:0] BUF_CFG = 72'b0 +)( + input A, + output O, OB +); + + assign O = A; + assign OB = ~A; + +`ifdef USE_TIMING + specify + (A => O) = 0; + (A => OB) = 0; + endspecify +`endif +endmodule + + +module CC_IO_SEL #( + parameter [71:0] IO_SEL_CFG = 72'b0 +)( + output IN1_O, IN2_O, + output GPIO_OUT, GPIO_EN, + input CLOCK1, CLOCK2, CLOCK3, CLOCK4, + input OUT1_I, OUT2_I, OUT3_I, OUT4_I, + input GPIO_IN, + input RESET, // does not exist + input DDR_I +); + reg q0_o = 1'bx; + reg q1_o = 1'bx; + reg q2_o = 1'bx; + reg q3_o = 1'bx; + + wire q0_i = IO_SEL_CFG[9] ? OUT4_I : OUT1_I; + wire q1_i = IO_SEL_CFG[10] ? OUT3_I : OUT2_I; + wire q2_i = GPIO_IN; + wire q3_i = GPIO_IN; + + wire q0mx_o = IO_SEL_CFG[20] ? q0_o : q0_i; + wire q1mx_o = IO_SEL_CFG[21] ? q1_o : q1_i; + + wire OMUX_SEL = (IO_SEL_CFG[13] & ~IO_SEL_CFG[12]) ? DDR_I : IO_SEL_CFG[11]; + assign GPIO_OUT = IO_SEL_CFG[8] ? (OMUX_SEL ? q1mx_o : q0mx_o) : (OMUX_SEL ? 1'b1 : 1'b0); + + wire clk_o = IO_SEL_CFG[25] ? (IO_SEL_CFG[24] ? CLOCK4 : CLOCK3) : (IO_SEL_CFG[24] ? CLOCK2 : CLOCK1); + wire clk_i = IO_SEL_CFG[29] ? (IO_SEL_CFG[28] ? CLOCK4 : CLOCK3) : (IO_SEL_CFG[28] ? CLOCK2 : CLOCK1); + + wire q0clk = IO_SEL_CFG[26] ^ clk_o; + wire q1clk = IO_SEL_CFG[27] ^ clk_o; + wire q2clk = IO_SEL_CFG[30] ^ clk_i; + wire q3clk = IO_SEL_CFG[31] ^ clk_i; + + assign IN1_O = IO_SEL_CFG[22] ? q2_o : q2_i; + assign IN2_O = IO_SEL_CFG[23] ? q3_o : q3_i; + + assign GPIO_EN = IO_SEL_CFG[17] ? (IO_SEL_CFG[18] ? OUT4_I : OUT2_I) : (IO_SEL_CFG[18] ? OUT3_I : IO_SEL_CFG[16]); + + always @(posedge q0clk) + begin + q0_o <= q0_i; + end + + always @(posedge q1clk) + begin + q1_o <= q1_i; + end + + always @(posedge q2clk) + begin + q2_o <= q2_i; + end + + always @(posedge q3clk) + begin + q3_o <= q3_i; + end + +endmodule + + +module C_L2T4( + output O, + input I0, I1, I2, I3 +); + parameter [3:0] INIT_L00 = 4'b0000; + parameter [3:0] INIT_L01 = 4'b0000; + parameter [3:0] INIT_L10 = 4'b0000; + + wire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0]; + wire l00 = I0 ? l00_s1[1] : l00_s1[0]; + + wire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0]; + wire l01 = I2 ? l01_s1[1] : l01_s1[0]; + + wire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0]; + assign O = l00 ? l10_s1[1] : l10_s1[0]; + +endmodule + + +module C_L2T5( + output O, + input I0, I1, I2, I3, I4 +); + parameter [3:0] INIT_L02 = 4'b0000; + parameter [3:0] INIT_L03 = 4'b0000; + parameter [3:0] INIT_L11 = 4'b0000; + parameter [3:0] INIT_L20 = 4'b0000; + + wire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0]; + wire l02 = I0 ? l02_s1[1] : l02_s1[0]; + + wire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0]; + wire l03 = I2 ? l03_s1[1] : l03_s1[0]; + + wire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0]; + wire l11 = l02 ? l11_s1[1] : l11_s1[0]; + + wire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0]; + assign O = I4 ? l20_s1[1] : l20_s1[0]; + +endmodule + + +module C_AND #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire CIN = CPE_CFG[6] ? CINX : CINY1; // C_HORIZ + wire L10 = &cpe_i[4:1]; + wire L20 = (&cpe_i[6:5]) & (CPE_CFG[4] ? CINY1 : &cpe_i[8:7]); // handle C_EN_CIN + wire LUT = (L10 & L20) ^ (CPE_CFG[5] & CIN); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINX => OUT) = 0; + (CINY1 => OUT) = 0; + (PINX => OUT) = 0; + (PINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_OR #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire L10 = |cpe_i[4:1]; + wire L20 = (|cpe_i[6:5]) | (CPE_CFG[4] ? CINY1 : |cpe_i[8:7]); // handle C_EN_CIN + wire LUT = (L10 | L20); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINX => OUT) = 0; + (CINY1 => OUT) = 0; + (PINX => OUT) = 0; + (PINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_XOR #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire LUT = ^cpe_i[8:1]; + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + (PINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_ORAND #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire LUT = (|cpe_i[2:1]) & (|cpe_i[4:3]) & (|cpe_i[6:5]) & (|cpe_i[8:7]); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + (PINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_ANDXOR #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire LUT = (~&cpe_i[2:1]) ^ (~&cpe_i[4:3]) ^ (~&cpe_i[6:5]) ^ (~&cpe_i[8:7]); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + (PINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_ICOMP #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire LUT = (~^cpe_i[2:1]) & (~^cpe_i[4:3]) & (~^cpe_i[6:5]) & (~^cpe_i[8:7]); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + (PINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_C_OR #( + parameter [6:0] CPE_CFG = 7'b0 +)( + output OUT, COUTY1, POUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + + assign COUTY1 = (|cpe_i[6:1]) | CINY1; + assign POUTY1 = (|cpe_i[6:1]) | PINY1; + +`ifdef USE_TIMING + specify + (IN1 => COUTY1) = 0; + (IN2 => COUTY1) = 0; + (IN3 => COUTY1) = 0; + (IN4 => COUTY1) = 0; + (IN5 => COUTY1) = 0; + (IN6 => COUTY1) = 0; + (IN7 => COUTY1) = 0; + (IN8 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (CINY1 => COUTY1) = 0; + (PINY1 => COUTY1) = 0; + (IN1 => POUTY1) = 0; + (IN2 => POUTY1) = 0; + (IN3 => POUTY1) = 0; + (IN4 => POUTY1) = 0; + (IN5 => POUTY1) = 0; + (IN6 => POUTY1) = 0; + (IN7 => POUTY1) = 0; + (IN8 => POUTY1) = 0; + (CINX => POUTY1) = 0; + (PINY1 => POUTY1) = 0; + endspecify +`endif +endmodule + + +module C_C_XOR #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTY1, POUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + //assign COUTY1 = (|cpe_i[6:1]) ^ CINY1; + //assign POUTY1 = (|cpe_i[6:1]) ^ PINY1; + wire LUT = (^cpe_i[8:1]) ^ CINY1; + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + (CINY1 => OUT) = 0; + (PINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_MX2a #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire s1 = (IN7 & IN8); + wire s0 = (IN5 & IN6); + + wire LUT = s1 ? (s0 ? IN4 : IN3) : (s0 ? IN2 : IN1); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_MX2b #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire s0 = (IN1 & IN2); + wire s1 = (IN3 & IN4); + + wire LUT = s1 ? (s0 ? IN8 : IN7) : (s0 ? IN6 : IN5); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_MX4a #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire s1 = (IN7 & IN8); + wire s0 = (IN5 & IN6); + + wire LUT = s1 ? (s0 ? IN4 : IN3) : (s0 ? IN2 : IN1); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_MX4b #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + wire s0 = (IN1 & IN2); + wire s1 = (IN3 & IN4); + + wire LUT = s1 ? (s0 ? IN8 : IN7) : (s0 ? IN6 : IN5); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_O_MUX ( + output COMP_OUT, + input COMB1, COMB2 +); + + assign COMP_OUT = COMB1; + +`ifdef USE_TIMING + specify + (COMB1 => COMP_OUT) = 0; + endspecify +`endif +endmodule + + +module C_O_OR2 ( + output COMP_OUT, + input COMB1, COMB2 +); + + assign COMP_OUT = COMB1 | COMB2; + +`ifdef USE_TIMING + specify + (COMB1 => COMP_OUT) = 0; + (COMB2 => COMP_OUT) = 0; + endspecify +`endif +endmodule + + +module C_0 #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + + assign OUT = 0; + +endmodule + + +module C_1 #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + + assign OUT = 1; + +endmodule + + +module C_C_0_1 #( + parameter [7:0] CPE_CFG = 8'b0 +)( + output OUT, COUTY1, + input CLK, EN, SR, + input CINY2, PINY2, + input RAM_I, CP_O, D_IN +); + + assign OUT = SR; + +endmodule + + +module C_C_CAT #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + + // COMB01 + wire OROUT = ~(~((IN1 & IN2) | (IN3 & IN4)) & ~(IN5 & IN6)); + wire L11 = IN7 & IN8; + wire COMBOUT = IN7 & IN8; + + // COMB02 + wire CADD_S = L11; + wire CADD_A = OROUT; + + // COMB03 + assign COUTY1 = CADD_S ? CADD_A : CINY1; + + // SEQ01 + assign OUT = COMBOUT; + +endmodule + + +module C_ADDF #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire CIN = CPE_CFG[6] ? CINX : CINY1; // C_HORIZ + wire LUT = (&cpe_i[2:1]) ^ (&cpe_i[4:3]) ^ (&cpe_i[6:5]) ^ (&cpe_i[8:7] ^ CIN); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + + wire CADD_A = (&cpe_i[2:1]) | (&cpe_i[4:3]) | (&cpe_i[6:5]); // OR3 + wire CADD_S = (&cpe_i[2:1]) ^ (&cpe_i[4:3]) ^ (&cpe_i[6:5]) ^ (&cpe_i[8:7]); + + generate + if (CPE_CFG[6]) begin + assign COUTX = CADD_S ? CIN : CADD_A; + end + else begin + assign COUTY1 = CADD_S ? CIN : CADD_A; + end + endgenerate + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINY1 => OUT) = 0; + (PINY1 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + + (IN1 => COUTY1) = 0; + (IN2 => COUTY1) = 0; + (IN3 => COUTY1) = 0; + (IN4 => COUTY1) = 0; + (IN5 => COUTY1) = 0; + (IN6 => COUTY1) = 0; + (IN7 => COUTY1) = 0; + (IN8 => COUTY1) = 0; + (CINY1 => COUTY1) = 0; + (PINY1 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (PINX => COUTY1) = 0; + endspecify +`endif +endmodule + + +module C_ADDFx #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire CIN = CPE_CFG[6] ? CINX : CINY1; // C_HORIZ + wire LUT = (^cpe_i[2:1]) ^ (^cpe_i[4:3]) ^ (^cpe_i[6:5]) ^ (^cpe_i[8:7] ^ CIN); + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + + wire CADD_A = (^cpe_i[2:1]) | (^cpe_i[4:3]) | (^cpe_i[6:5]); // OR3 + wire CADD_S = (^cpe_i[2:1]) ^ (^cpe_i[4:3]) ^ (^cpe_i[6:5]) ^ (^cpe_i[8:7]); + + generate + if (CPE_CFG[6]) begin + assign COUTX = CADD_S ? CIN : CADD_A; + end + else begin + assign COUTY1 = CADD_S ? CIN : CADD_A; + end + endgenerate + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINY1 => OUT) = 0; + (PINY1 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + + (IN1 => COUTY1) = 0; + (IN2 => COUTY1) = 0; + (IN3 => COUTY1) = 0; + (IN4 => COUTY1) = 0; + (IN5 => COUTY1) = 0; + (IN6 => COUTY1) = 0; + (IN7 => COUTY1) = 0; + (IN8 => COUTY1) = 0; + (CINY1 => COUTY1) = 0; + (PINY1 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (PINX => COUTY1) = 0; + endspecify +`endif +endmodule + + +module C_ADDF2 #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + + wire [8:1] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire L10 = (&cpe_i[2:1]) ^ (&cpe_i[4:3]); + wire L11 = (&cpe_i[6:5]) ^ (&cpe_i[8:7]); + wire L02 = &cpe_i[6:5]; + + wire CIN = CPE_CFG[6] ? CINX : CINY1; // C_HORIZ + + wire na2_1 = ~(~CIN & L11); + wire na2_2 = ~(L02 & ~L11); + wire na3_1 = ~(na2_1 & na2_1); + + wire na2_3 = ~(L10 & na3_1); + wire or2_1 = (L10 | na3_1); + wire COMB2OUT = ~(na2_3 & or2_1); + wire COMB1OUT = CIN ^ L11; // CIN ? 0 : L11; + + wire o2 = ~(L10 ^ (L11 ? ~CIN : ~L02)); + wire LUT = CPE_CFG[7] ? o2 : COMB1OUT; + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + + wire CADD_A = (L10) ? (&cpe_i[6:5]) : ((&cpe_i[2:1]) | (&cpe_i[4:3])); + wire CADD_S = (L10) & (L11); + + generate + if (CPE_CFG[6]) begin + assign COUTX = CADD_S ? CIN : CADD_A; + end + else begin + assign COUTY1 = CADD_S ? CIN : CADD_A; + end + endgenerate + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINY1 => OUT) = 0; + (PINY1 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + + (IN1 => COUTY1) = 0; + (IN2 => COUTY1) = 0; + (IN3 => COUTY1) = 0; + (IN4 => COUTY1) = 0; + (IN5 => COUTY1) = 0; + (IN6 => COUTY1) = 0; + (IN7 => COUTY1) = 0; + (IN8 => COUTY1) = 0; + (CINY1 => COUTY1) = 0; + (PINY1 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (PINX => COUTY1) = 0; + endspecify +`endif +endmodule + + +module C_ADDF2x #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, COUTX, COUTY1, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + + wire [8:1] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = CPE_CFG[0] ? PINY1 : IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = CPE_CFG[1] ? CINX : IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = CPE_CFG[2] ? PINY1 : IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = CPE_CFG[3] ? PINX : IN8; + + wire L10 = (^cpe_i[2:1]) ^ (^cpe_i[4:3]); + wire L11 = (^cpe_i[6:5]) ^ (^cpe_i[8:7]); + wire L02 = ^cpe_i[6:5]; + + wire CIN = CPE_CFG[6] ? CINX : CINY1; // C_HORIZ + + wire na2_1 = ~(~CIN & L11); + wire na2_2 = ~(L02 & ~L11); + wire na3_1 = ~(na2_1 & na2_1); + + wire na2_3 = ~(L10 & na3_1); + wire or2_1 = (L10 | na3_1); + wire COMB2OUT = ~(na2_3 & or2_1); + wire COMB1OUT = CIN ^ L11; // CIN ? 0 : L11; + + wire o2 = ~(L10 ^ (L11 ? ~CIN : ~L02)); + wire LUT = CPE_CFG[7] ? o2 : COMB1OUT; + assign OUT = CPE_CFG[8] ? ~LUT : LUT; + + wire CADD_A = (L10) ? (^cpe_i[6:5]) : ((^cpe_i[2:1]) | (^cpe_i[4:3])); + wire CADD_S = (L10) & (L11); + + generate + if (CPE_CFG[6]) begin + assign COUTX = CADD_S ? CIN : CADD_A; + end + else begin + assign COUTY1 = CADD_S ? CIN : CADD_A; + end + endgenerate + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + (CINY1 => OUT) = 0; + (PINY1 => OUT) = 0; + (CINX => OUT) = 0; + (PINX => OUT) = 0; + + (IN1 => COUTX) = 0; + (IN2 => COUTX) = 0; + (IN3 => COUTX) = 0; + (IN4 => COUTX) = 0; + (IN5 => COUTX) = 0; + (IN6 => COUTX) = 0; + (IN7 => COUTX) = 0; + (IN8 => COUTX) = 0; + (CINY1 => COUTX) = 0; + (PINY1 => COUTX) = 0; + (CINX => COUTX) = 0; + (PINX => COUTX) = 0; + + (IN1 => COUTY1) = 0; + (IN2 => COUTY1) = 0; + (IN3 => COUTY1) = 0; + (IN4 => COUTY1) = 0; + (IN5 => COUTY1) = 0; + (IN6 => COUTY1) = 0; + (IN7 => COUTY1) = 0; + (IN8 => COUTY1) = 0; + (CINY1 => COUTY1) = 0; + (PINY1 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (PINX => COUTY1) = 0; + endspecify +`endif +endmodule + + +module C_Carry #( + parameter [7:0] CPE_CFG = 8'b0 +)( + output OUT, RAM_O, + input CLK, EN, SR, + input CINY2, PINY2, + input RAM_I, CP_O, D_IN +); + assign OUT = CP_O; + +`ifdef USE_TIMING + specify + (CP_O => OUT) = 0; + endspecify +`endif +endmodule + + +module C_MULT #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT1, OUT2, + output COUTX, POUTX, + output COUTY1, POUTY1, + output COUTY2, POUTY2, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CLK, EN, SR, + input CINX, CINY1, CINY2, + input PINX, PINY1, PINY2, + input RAM_I1, RAM_I2 +); + + wire [8:1] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = PINY1; + assign cpe_i[4] = CINX; + assign cpe_i[5] = IN5; + assign cpe_i[6] = PINY1; + assign cpe_i[8] = PINX; + + wire L10 = ~((&cpe_i[2:1]) ^ CINX); + wire L11 = ~((&cpe_i[6:5]) ^ PINX); + wire L02OUT = &cpe_i[6:5]; + wire NOROUT = ~((&cpe_i[2:1]) | CINX); + + // COMB02 ADDF2 + wire CADD_A = ((~NOROUT | ~L10) & ~(~L02OUT & ~L10)); + wire CADD_S = (~L10) & (~L11); + wire ADDF2 = ~(~(~L11 & ~CINY1) & ~(~L02OUT & L11)); + + // COMB02 MULT + wire nand2_0 = ~(PINY2 & IN5); + wire nand2_1 = ~(PINY2 & IN8); + wire xnor3_0 = ~(nand2_0 ^ ~L10 ^ ~ADDF2); + wire xnor3_1 = ~(nand2_1 ^ CINY1 ^ ~L11); + wire mx2_0 = ~(( nand2_0 | xnor3_0) & (nand2_1 | ~xnor3_0)); + wire mx2_1 = ~((~nand2_1 | xnor3_1) & (CINY2 | ~xnor3_1)); + + wire COY2_A = mx2_0; + wire COY2_S = ~(~xnor3_0 | ~xnor3_1); + wire MULTO1 = ~(xnor3_1 ^ ~CINY2); + wire MULTO2 = ~(xnor3_0 ^ mx2_1); + + // COMB03 + assign COUTX = MULTO2; + assign COUTY1 = CADD_S ? CINY1 : CADD_A; + assign COUTY2 = COY2_S ? CINY2 : COY2_A; + assign OUT2 = COUTX; + + // COMB04 + assign POUTX = MULTO1; + assign POUTY1 = CPE_CFG[4] ? COUTX : PINY1; + assign POUTY2 = PINY2; + assign OUT1 = CPE_CFG[4] ? COUTX : POUTX; + +`ifdef USE_TIMING + specify + (IN1 => OUT1) = 0; + (IN3 => OUT1) = 0; + (IN5 => OUT1) = 0; + (IN7 => OUT1) = 0; + (IN8 => OUT1) = 0; + (CINY1 => OUT1) = 0; + (CINY2 => OUT1) = 0; + (PINY1 => OUT1) = 0; + (PINY2 => OUT1) = 0; + (CINX => OUT1) = 0; + (PINX => OUT1) = 0; + (IN1 => OUT2) = 0; + (IN3 => OUT2) = 0; + (IN5 => OUT2) = 0; + (IN7 => OUT2) = 0; + (IN8 => OUT2) = 0; + (CINY1 => OUT2) = 0; + (CINY2 => OUT2) = 0; + (PINY1 => OUT2) = 0; + (PINY2 => OUT2) = 0; + (CINX => OUT2) = 0; + (PINX => OUT2) = 0; + (IN1 => COUTX) = 0; + (IN3 => COUTX) = 0; + (IN5 => COUTX) = 0; + (IN7 => COUTX) = 0; + (IN8 => COUTX) = 0; + (CINY1 => COUTX) = 0; + (CINY2 => COUTX) = 0; + (PINY1 => COUTX) = 0; + (PINY2 => COUTX) = 0; + (CINX => COUTX) = 0; + (PINX => COUTX) = 0; + (IN1 => POUTX) = 0; + (IN3 => POUTX) = 0; + (IN5 => POUTX) = 0; + (IN7 => POUTX) = 0; + (IN8 => POUTX) = 0; + (CINY1 => POUTX) = 0; + (CINY2 => POUTX) = 0; + (PINY1 => POUTX) = 0; + (PINY2 => POUTX) = 0; + (CINX => POUTX) = 0; + (PINX => POUTX) = 0; + (IN1 => COUTY1) = 0; + (IN3 => COUTY1) = 0; + (IN5 => COUTY1) = 0; + (IN7 => COUTY1) = 0; + (IN8 => COUTY1) = 0; + (CINY1 => COUTY1) = 0; + (CINY2 => COUTY1) = 0; + (PINY1 => COUTY1) = 0; + (PINY2 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (PINX => COUTY1) = 0; + (PINY1 => POUTY1) = 0; + (IN1 => COUTY2) = 0; + (IN3 => COUTY2) = 0; + (IN5 => COUTY2) = 0; + (IN7 => COUTY2) = 0; + (IN8 => COUTY2) = 0; + (CINY1 => COUTY2) = 0; + (CINY2 => COUTY2) = 0; + (PINY1 => COUTY2) = 0; + (PINY2 => COUTY2) = 0; + (CINX => COUTY2) = 0; + (PINX => COUTY2) = 0; + (PINY2 => POUTY2) = 0; + endspecify +`endif +endmodule + + +module C_MULTFa #( + parameter [7:0] CPE_CFG = 8'b0 +)( + output COUTX, POUTX, + output COUTY1, POUTY1, + output COUTY2, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CLK, EN, SR, + input CINX, CINY1, CINY2, + input PINX, PINY1, PINY2, + input RAM_I1, RAM_I2 +); + + assign COUTY1 = PINY1 ^ CINX; + assign COUTY2 = CINY2; + assign COUTX = CINY2; + assign POUTY1 = CINY1 ^ (PINY1 & CINX); + +`ifdef USE_TIMING + specify + (CINY2 => COUTX) = 0; + (PINY1 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (CINY1 => POUTY1) = 0; + (PINY1 => POUTY1) = 0; + (CINX => POUTY1) = 0; + (CINY2 => COUTY2) = 0; + endspecify +`endif +endmodule + + +module C_MULTFb #( + parameter [7:0] CPE_CFG = 8'b0 +)( + output COUTX, POUTX, + output COUTY1, POUTY1, + output COUTY2, POUTY2, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CLK, EN, SR, + input CINX, CINY1, CINY2, + input PINX, PINY1, PINY2, + input RAM_I1, RAM_I2 +); + + assign COUTY1 = PINY1 ^ CINX; + assign COUTY2 = CINY2; + assign COUTX = CINY2; + assign POUTY1 = CINY1 ^ (PINY1 | CINX); + +`ifdef USE_TIMING + specify + (CINY2 => COUTX) = 0; + (PINY1 => COUTY1) = 0; + (CINX => COUTY1) = 0; + (CINY1 => POUTY1) = 0; + (PINY1 => POUTY1) = 0; + (CINX => POUTY1) = 0; + (CINY2 => COUTY2) = 0; + endspecify +`endif +endmodule + + +module C_O_O1 #( + parameter CPE_CFG = 0 +)( + output COMP_OUT, + input COMB1, COMB2 +); + assign COMP_OUT = COMB1; + +`ifdef USE_TIMING + specify + (COMB1 => COMP_OUT) = 0; + endspecify +`endif +endmodule + + +module C_O_O2 #( + parameter CPE_CFG = 0 +)( + output COMP_OUT, + input COMB1, COMB2 +); + assign COMP_OUT = COMB2; + +`ifdef USE_TIMING + specify + (COMB2 => COMP_OUT) = 0; + endspecify +`endif +endmodule + + +module C_O_0 #( + parameter CPE_CFG = 0 +)( + output COMP_OUT, + input COMB1, COMB2 +); + assign COMP_OUT = 1'b0; +endmodule + + +module C_D #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, RAM_O, + input CLK, EN, SR, + input CINY2, PINY2, + input RAM_I, CP_O, D_IN +); + wire CP_i, EN_i, SR_i, D_i; + reg q_i = CPE_CFG[8]; + + assign D_i = D_IN; + assign SR_i = ~SR; // reset + assign CP_i = CPE_CFG[4] ? CINY2 : CLK; // C_CLKSEL + assign EN_i = CPE_CFG[5] ? PINY2 : EN; // C_ENSEL + + assign OUT = q_i; + assign RAM_O = CPE_CFG[7] ? RAM_I : q_i; + + always @(posedge CP_i or posedge SR_i) + begin + if (SR_i) begin + q_i <= 1'b0; + end + else if (EN_i) begin + q_i <= D_i; + end + end + +`ifdef USE_TIMING + reg notifier; + specify + (CLK => OUT) = 0; + (CINY2 => OUT) = 0; + (SR => OUT) = 0; +`ifdef USE_TIMINGCHECKS + // clock via CLK + $period (posedge CLK &&& EN, 0, notifier); + $width(posedge CLK &&& EN, 0, 0, notifier); + $width(negedge CLK &&& EN, 0, 0, notifier); + $width(posedge SR, 0, 0, notifier); + $width(negedge SR, 0, 0, notifier); + $recrem(posedge SR, posedge CLK, 0, 0, notifier,,, SR_i, CP_i); + $setuphold(posedge CLK, posedge D_IN, 0, 0, notifier,,, CP_i, D_i); + $setuphold(posedge CLK, negedge D_IN, 0, 0, notifier,,, CP_i, D_i); + $setuphold(posedge CLK, posedge EN, 0, 0, notifier,,, CP_i, EN_i); + $setuphold(posedge CLK, negedge EN, 0, 0, notifier,,, CP_i, EN_i); + // clock via CINY2 + //$period (posedge CINY2 &&& EN, 0, notifier); + //$width(posedge CINY2 &&& EN, 0, 0, notifier); + //$width(negedge CINY2 &&& EN, 0, 0, notifier); + //$width(posedge SR, 0, 0, notifier); + //$width(negedge SR, 0, 0, notifier); + //$recrem(posedge SR, posedge CINY2, 0, 0, notifier,,, SR_i, CP_i); + //$setuphold(posedge CINY2, posedge D_IN, 0, 0, notifier,,, CP_i, D_i); + //$setuphold(posedge CINY2, negedge D_IN, 0, 0, notifier,,, CP_i, D_i); + //$setuphold(posedge CINY2, posedge EN, 0, 0, notifier,,, CP_i, EN_i); + //$setuphold(posedge CINY2, negedge EN, 0, 0, notifier,,, CP_i, EN_i); +`endif + endspecify +`endif +endmodule + + +module C_DST #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, RAM_O, + input CLK, EN, SR, + input CINY2, PINY2, + input RAM_I, CP_O, D_IN +); + wire CP_i, EN_i, SR_i, D_i; + reg q_i = CPE_CFG[8]; + + assign D_i = D_IN; + assign SR_i = ~SR; // set + assign CP_i = CPE_CFG[4] ? CINY2 : CLK; // C_CLKSEL + assign EN_i = CPE_CFG[5] ? PINY2 : EN; // C_ENSEL + + assign OUT = q_i; + assign RAM_O = CPE_CFG[7] ? RAM_I : q_i; + + always @(posedge CP_i or posedge SR_i) + begin + if (SR_i) begin + q_i <= 1'b1; + end + else if (EN_i) begin + q_i <= D_i; + end + end + +`ifdef USE_TIMING + reg notifier; + specify + (CLK => OUT) = 0; + (CINY2 => OUT) = 0; + (SR => OUT) = 0; +`ifdef USE_TIMINGCHECKS + $period (posedge CLK &&& EN, 0, notifier); + $width(posedge CLK &&& EN, 0, 0, notifier); + $width(negedge CLK &&& EN, 0, 0, notifier); + $width(posedge SR, 0, 0, notifier); + $width(negedge SR, 0, 0, notifier); + $recrem(posedge SR, posedge CLK, 0, 0, notifier,,, SR_i, CP_i); + $setuphold(posedge CLK, posedge D_IN, 0, 0, notifier,,, CP_i, D_i); + $setuphold(posedge CLK, negedge D_IN, 0, 0, notifier,,, CP_i, D_i); + $setuphold(posedge CLK, posedge EN, 0, 0, notifier,,, CP_i, EN_i); +`endif + endspecify +`endif +endmodule + + +module C_DRS #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, RAM_O, + input CLK, EN, SR, // EN is SET, SR is RST + input CINY2, PINY2, + input RAM_I, CP_O, D_IN +); + wire CP_i, EN_i, SR_i, D_i; + reg q_i = CPE_CFG[9]; + + assign D_i = D_IN; + assign SR_i = ~SR; // reset + assign CP_i = CPE_CFG[4] ? CINY2 : CLK; // C_CLKSEL + assign EN_i = CPE_CFG[5] ? PINY2 : EN; // C_ENSEL // set + + assign OUT = q_i; + assign RAM_O = CPE_CFG[7] ? RAM_I : q_i; // C_ENSEL + + always @(posedge CP_i or posedge SR_i or posedge EN_i) + begin + if (EN_i) begin + q_i <= 1'b1; + end + else if (SR_i) begin + q_i <= 1'b0; + end + else begin + q_i <= D_i; + end + end + +`ifdef USE_TIMING + reg notifier; + specify + (CLK => OUT) = 0; + (CINY2 => OUT) = 0; + (SR => OUT) = 0; +`ifdef USE_TIMINGCHECKS + $period (posedge CLK &&& EN, 0, notifier); + $width(posedge CLK &&& EN, 0, 0, notifier); + $width(negedge CLK &&& EN, 0, 0, notifier); + $width(posedge SR, 0, 0, notifier); + $width(negedge SR, 0, 0, notifier); + $width(negedge EN, 0, 0, notifier); + $recrem(posedge SR, posedge CLK, 0, 0, notifier,,, SR_i, CP_i); + $recrem(posedge EN, posedge CLK, 0, 0, notifier,,, EN_i, CP_i); + $setuphold(posedge CLK, posedge D_IN, 0, 0, notifier,,, CP_i, D_i); + $setuphold(posedge CLK, negedge D_IN, 0, 0, notifier,,, CP_i, D_i); + $setuphold(posedge CLK, posedge EN, 0, 0, notifier,,, CP_i, EN_i); +`endif + endspecify +`endif +endmodule + + +module C_CPlines #( + parameter [18:0] CPE_CFG = 19'b0 +)( + output RAM_O1, RAM_O2, + output COUTX, POUTX, + output COUTY1, POUTY1, + output COUTY2, POUTY2, + input OUT1, OUT2, COMP_OUT, + input CINX, CINY1, CINY2, + input PINX, PINY1, PINY2, + input RAM_I1, RAM_I2 +); + + // Decode + wire C_SELX = CPE_CFG[6]; + wire C_SELY1 = CPE_CFG[7]; + wire C_SELY2 = CPE_CFG[8]; + wire C_SEL_C = CPE_CFG[9]; + wire C_SEL_P = CPE_CFG[10]; + wire C_Y12 = CPE_CFG[11]; + wire C_CX_I = CPE_CFG[12]; + wire C_CY1_I = CPE_CFG[13]; + wire C_CY2_I = CPE_CFG[14]; + wire C_PX_I = CPE_CFG[15]; + wire C_PY1_I = CPE_CFG[16]; + wire C_PY2_I = CPE_CFG[17]; + + wire CIY12 = C_Y12 ? CINY2 : CINY1; + wire PIY12 = C_Y12 ? PINY2 : PINY1; + + wire CX_VAL = C_SEL_C ? (C_SELX ? CIY12 : COMP_OUT) : (C_SELX ? OUT2 : OUT1); + wire PX_VAL = C_SEL_P ? (C_SELX ? PIY12 : COMP_OUT) : (C_SELX ? OUT1 : OUT2); + wire CY1_VAL = C_SEL_C ? (C_SELY1 ? CINX : COMP_OUT) : (C_SELY1 ? OUT1 : OUT2); + wire PY1_VAL = C_SEL_P ? (C_SELY1 ? PINX : COMP_OUT) : (C_SELY1 ? OUT2 : OUT1); + wire CY2_VAL = C_SEL_C ? (C_SELY2 ? CINX : COMP_OUT) : (C_SELY2 ? OUT2 : OUT1); + wire PY2_VAL = C_SEL_P ? (C_SELY2 ? PINX : COMP_OUT) : (C_SELY2 ? OUT1 : OUT2); + + assign RAM_O1 = OUT1; + assign RAM_O2 = OUT2; + assign COUTX = C_CX_I ? CX_VAL : CINX; + assign COUTY1 = C_CY1_I ? CY1_VAL : CINY1; + assign COUTY2 = C_CY2_I ? CY2_VAL : CINY2; + assign POUTX = C_PX_I ? PX_VAL : PINX; + assign POUTY1 = C_PY1_I ? PY1_VAL : PINY1; + assign POUTY2 = C_PY2_I ? PY2_VAL : PINY2; + +`ifdef USE_TIMING + specify + (OUT1 => RAM_O1) = 0; + (OUT2 => RAM_O2) = 0; + (CINX => COUTX) = 0; + (CINY1 => COUTX) = 0; + (CINY2 => COUTX) = 0; + (COMP_OUT => COUTX) = 0; + (OUT1 => COUTX) = 0; + (OUT2 => COUTX) = 0; + (CINX => COUTY1) = 0; + (CINY1 => COUTY1) = 0; + (COMP_OUT => COUTY1) = 0; + (OUT1 => COUTY1) = 0; + (OUT2 => COUTY1) = 0; + (CINX => COUTY2) = 0; + (CINY2 => COUTY2) = 0; + (COMP_OUT => COUTY2) = 0; + (OUT1 => COUTY2) = 0; + (OUT2 => COUTY2) = 0; + (PINX => POUTX) = 0; + (PINY1 => POUTX) = 0; + (PINY2 => POUTX) = 0; + (COMP_OUT => POUTX) = 0; + (OUT1 => POUTX) = 0; + (OUT2 => POUTX) = 0; + (PINX => POUTY1) = 0; + (PINY1 => POUTY1) = 0; + (COMP_OUT => POUTY1) = 0; + (OUT1 => POUTY1) = 0; + (OUT2 => POUTY1) = 0; + (PINX => POUTY2) = 0; + (PINY2 => POUTY2) = 0; + (COMP_OUT => POUTY2) = 0; + (OUT1 => POUTY2) = 0; + (OUT2 => POUTY2) = 0; + endspecify +`endif +endmodule + + +module C_Route1 #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + assign OUT = CPE_CFG[8] ? ~CINY1 : CINY1; + +`ifdef USE_TIMING + specify + (CINY1 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_Route2 #( + parameter [8:0] CPE_CFG = 9'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + assign OUT = CPE_CFG[8] ? ~CINY1 : CINY1; +endmodule + + +module C_CP_route #( + parameter [6:0] CPE_CFG = 7'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8, + input CINX, CINY1, + input PINX, PINY1 +); + // blackbox +endmodule + + +module C_Bridge #( + parameter [8:0] CPE_CFG = 8'b0 +)( + output OUT, + input IN1, IN2, IN3, IN4, + input IN5, IN6, IN7, IN8 +); + wire [8:0] cpe_i; + + assign cpe_i[1] = IN1; + assign cpe_i[2] = IN2; + assign cpe_i[3] = IN3; + assign cpe_i[4] = IN4; + assign cpe_i[5] = IN5; + assign cpe_i[6] = IN6; + assign cpe_i[7] = IN7; + assign cpe_i[8] = IN8; + + assign OUT = |cpe_i[8:1]; + +`ifdef USE_TIMING + specify + (IN1 => OUT) = 0; + (IN2 => OUT) = 0; + (IN3 => OUT) = 0; + (IN4 => OUT) = 0; + (IN5 => OUT) = 0; + (IN6 => OUT) = 0; + (IN7 => OUT) = 0; + (IN8 => OUT) = 0; + endspecify +`endif +endmodule + + +module C_RAM_I1 #( + parameter [8:0] CPE_CFG = 8'b0 +)( + output OUT, RAM_O, + input CLK, EN, SR, + input CINY2, PINY2, + input RAM_I, CP_O, D_IN +); + assign OUT = RAM_I; +endmodule + + +module C_RAM_I2 #( + parameter [8:0] CPE_CFG = 8'b0 +)( + output OUT, RAM_O, + input CLK, EN, SR, + input CINY2, PINY2, + input RAM_I, CP_O, D_IN +); + assign OUT = RAM_I; +endmodule + + +`ifdef USE_PLL +module CC_PLL #( + parameter PLL_CFG = "", + parameter REF_CLK = "", // e.g. "10.0" + parameter OUT_CLK = "", // e.g. "50.0" + parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED + parameter LOCK_REQ = 0, + parameter LOW_JITTER = 1, + parameter CI_FILTER_CONST = 2, + parameter CP_FILTER_CONST = 4 +)( + input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, + input USR_LOCKED_STDY_RST, USR_SET_SEL, + output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED, + output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT +); + + reg r_user_pll_locked_stdy = 0; + reg r_user_pll_locked = 0; + reg r_clk270 = 0; + reg r_clk180 = 0; + reg r_clk90 = 0; + reg r_clk0 = 0; + reg r_clk_ref_out; + reg r_init = 0; + + assign USR_PLL_LOCKED_STDY = r_user_pll_locked_stdy; + assign USR_PLL_LOCKED = r_user_pll_locked; + assign CLK270 = r_clk270 & r_user_pll_locked; + assign CLK180 = r_clk180 & r_user_pll_locked; + assign CLK90 = r_clk90 & r_user_pll_locked; + assign CLK0 = r_clk0 & r_user_pll_locked; + assign CLK_REF_OUT = CLK_REF | USR_CLK_REF; + + reg [31:0] clkcnt = 0; + always @(CLK_REF or USR_CLK_REF) + begin + if (CLK_REF_OUT) begin + r_init = 1; + end + if (clkcnt > 57) begin + r_user_pll_locked = 1; + end + if ((clkcnt > 1) && (clkcnt % 2 == 0)) begin + r_clk0 = ~r_clk0; + end + if ((clkcnt > 2) && ((clkcnt-1) % 2 == 0)) begin + r_clk90 = ~r_clk90; + end + if ((clkcnt > 3) && ((clkcnt-2) % 2 == 0)) begin + r_clk180 = ~r_clk180; + end + if ((clkcnt > 4) && ((clkcnt-3) % 2 == 0)) begin + r_clk270 = ~r_clk270; + end + clkcnt = r_init ? clkcnt + 1 : 0; + end + +`ifdef USE_TIMING + specify + (CLK_REF => CLK270) = 0; + (CLK_REF => CLK180) = 0; + (CLK_REF => CLK90) = 0; + (CLK_REF => CLK0) = 0; + endspecify +`endif +endmodule +`endif + +module CLKIN #( + parameter [31:0] CLKIN_CFG = 32'h0 +)( + output PCLK0, PCLK1, PCLK2, PCLK3, + input CLK0, CLK1, CLK2, CLK3, + input SER_CLK, SPI_CLK, JTAG_CLK +); + + wire C4_7_NC, C4_6_NC, C4_5_NC, C4_4_NC, C4_3, C4_2, C4_1, C4_0; + wire C3_7_NC, C3_6_NC, C3_5_NC, C3_4_NC, C3_3, C3_2, C3_1, C3_0; + wire C2_7_NC, C2_6_NC, C2_5_NC, C2_4_NC, C2_3, C2_2, C2_1, C2_0; + wire C1_7_NC, C1_6_NC, C1_5_NC, C1_4_NC, C1_3, C1_2, C1_1, C1_0; + + assign {C4_7_NC, C4_6_NC, C4_5_NC, C4_4_NC, C4_3, C4_2, C4_1, C4_0} = CLKIN_CFG[31:24]; + assign {C3_7_NC, C3_6_NC, C3_5_NC, C3_4_NC, C3_3, C3_2, C3_1, C3_0} = CLKIN_CFG[23:16]; + assign {C2_7_NC, C2_6_NC, C2_5_NC, C2_4_NC, C2_3, C2_2, C2_1, C2_0} = CLKIN_CFG[15:8]; + assign {C1_7_NC, C1_6_NC, C1_5_NC, C1_4_NC, C1_3, C1_2, C1_1, C1_0} = CLKIN_CFG[7:0]; + + wire CLK1MX = C1_2 ? (C1_1 ? (C1_0 ? 1'b0 : JTAG_CLK) : (C1_0 ? SPI_CLK : SER_CLK)) : (C1_1 ? (C1_0 ? CLK3 : CLK2) : (C1_0 ? CLK1 : CLK0)); + wire CLK2MX = C2_2 ? (C1_1 ? (C2_0 ? 1'b0 : JTAG_CLK) : (C2_0 ? SPI_CLK : SER_CLK)) : (C2_1 ? (C2_0 ? CLK3 : CLK2) : (C2_0 ? CLK1 : CLK0)); + wire CLK3MX = C3_2 ? (C1_1 ? (C3_0 ? 1'b0 : JTAG_CLK) : (C3_0 ? SPI_CLK : SER_CLK)) : (C3_1 ? (C3_0 ? CLK3 : CLK2) : (C3_0 ? CLK1 : CLK0)); + wire CLK4MX = C4_2 ? (C1_1 ? (C4_0 ? 1'b0 : JTAG_CLK) : (C4_0 ? SPI_CLK : SER_CLK)) : (C4_1 ? (C4_0 ? CLK3 : CLK2) : (C4_0 ? CLK1 : CLK0)); + + assign PCLK0 = CLK1MX ^ C1_3; + assign PCLK1 = CLK2MX ^ C2_3; + assign PCLK2 = CLK3MX ^ C3_3; + assign PCLK3 = CLK4MX ^ C3_3; + +`ifdef USE_TIMING + specify + (CLK0 => PCLK0) = 0; + (CLK0 => PCLK1) = 0; + (CLK0 => PCLK2) = 0; + (CLK0 => PCLK3) = 0; + (CLK1 => PCLK0) = 0; + (CLK1 => PCLK1) = 0; + (CLK1 => PCLK2) = 0; + (CLK1 => PCLK3) = 0; + (CLK2 => PCLK0) = 0; + (CLK2 => PCLK1) = 0; + (CLK2 => PCLK2) = 0; + (CLK2 => PCLK3) = 0; + (CLK3 => PCLK0) = 0; + (CLK3 => PCLK1) = 0; + (CLK3 => PCLK2) = 0; + (CLK3 => PCLK3) = 0; + (JTAG_CLK => PCLK0) = 0; + (JTAG_CLK => PCLK1) = 0; + (JTAG_CLK => PCLK2) = 0; + (JTAG_CLK => PCLK3) = 0; + (SER_CLK => PCLK0) = 0; + (SER_CLK => PCLK1) = 0; + (SER_CLK => PCLK2) = 0; + (SER_CLK => PCLK3) = 0; + (SPI_CLK => PCLK0) = 0; + (SPI_CLK => PCLK1) = 0; + (SPI_CLK => PCLK2) = 0; + (SPI_CLK => PCLK3) = 0; + endspecify +`endif +endmodule + + +module GLBOUT #( + parameter [63:0] GLBOUT_CFG = 64'h0 +)( + output GLB0, GLB1, GLB2, GLB3, + output CLK_FB0, CLK_FB1, CLK_FB2, CLK_FB3, + input CLK0_0, CLK0_90, CLK0_180, CLK0_270, CLK0_BYP, + input CLK1_0, CLK1_90, CLK1_180, CLK1_270, CLK1_BYP, + input CLK2_0, CLK2_90, CLK2_180, CLK2_270, CLK2_BYP, + input CLK3_0, CLK3_90, CLK3_180, CLK3_270, CLK3_BYP, + input USR_GLB0, USR_GLB1, USR_GLB2, USR_GLB3, + input USR_FB0, USR_FB1, USR_FB2, USR_FB3 +); + wire C_63,C_62,C_61,C_60,C_59,C_58,C_57,C_56; + wire C_55,C_54,C_53,C_52,C_51,C_50,C_49,C_48; + wire C_47,C_46,C_45,C_44,C_43,C_42,C_41,C_40; + wire C_39,C_38,C_37,C_36,C_35,C_34,C_33,C_32; + wire C_31,C_30,C_29,C_28,C_27,C_26,C_25,C_24; + wire C_23,C_22,C_21,C_20,C_19,C_18,C_17,C_16; + wire C_15,C_14,C_13,C_12,C_11,C_10, C_9, C_8; + wire C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0; + + assign {C_63,C_62,C_61,C_60,C_59,C_58,C_57,C_56} = GLBOUT_CFG[63:56]; + assign {C_55,C_54,C_53,C_52,C_51,C_50,C_49,C_48} = GLBOUT_CFG[55:48]; + assign {C_47,C_46,C_45,C_44,C_43,C_42,C_41,C_40} = GLBOUT_CFG[47:40]; + assign {C_39,C_38,C_37,C_36,C_35,C_34,C_33,C_32} = GLBOUT_CFG[39:32]; + assign {C_31,C_30,C_29,C_28,C_27,C_26,C_25,C_24} = GLBOUT_CFG[31:24]; + assign {C_23,C_22,C_21,C_20,C_19,C_18,C_17,C_16} = GLBOUT_CFG[23:16]; + assign {C_15,C_14,C_13,C_12,C_11,C_10, C_9, C_8} = GLBOUT_CFG[15: 8]; + assign { C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0} = GLBOUT_CFG[ 7: 0]; + + wire CLK1MXO = C_2 ? ( C_1 ? ( C_0 ? CLK0_270 : CLK0_180) : ( C_0 ? CLK0_90 : CLK0_0)) : ( C_1 ? ( C_0 ? CLK3_0 : CLK2_0) : ( C_0 ? CLK1_0 : CLK0_BYP)); + wire CLK2MXO = C_18 ? (C_17 ? (C_16 ? CLK1_270 : CLK1_180) : (C_16 ? CLK1_90 : CLK1_0)) : (C_17 ? (C_16 ? CLK3_0 : CLK2_0) : (C_16 ? CLK1_0 : CLK1_BYP)); + wire CLK3MXO = C_34 ? (C_33 ? (C_32 ? CLK2_270 : CLK2_180) : (C_32 ? CLK2_90 : CLK2_0)) : (C_33 ? (C_32 ? CLK3_0 : CLK2_0) : (C_32 ? CLK1_0 : CLK2_BYP)); + wire CLK4MXO = C_50 ? (C_49 ? (C_48 ? CLK3_270 : CLK3_180) : (C_48 ? CLK3_90 : CLK3_0)) : (C_49 ? (C_48 ? CLK3_0 : CLK2_0) : (C_48 ? CLK1_0 : CLK3_BYP)); + + assign GLB0 = C_4 ? ( C_3 ? USR_GLB0 : CLK1MXO) : 1'b0; + assign GLB1 = C_20 ? (C_19 ? USR_GLB1 : CLK2MXO) : 1'b0; + assign GLB2 = C_36 ? (C_35 ? USR_GLB2 : CLK3MXO) : 1'b0; + assign GLB3 = C_52 ? (C_51 ? USR_GLB3 : CLK4MXO) : 1'b0; + + wire CLK1MXI = C_9 ? ( C_8 ? GLB3 : GLB2) : ( C_8 ? GLB1 : GLB0); + wire CLK2MXI = C_25 ? (C_24 ? GLB3 : GLB2) : (C_24 ? GLB1 : GLB0); + wire CLK3MXI = C_41 ? (C_40 ? GLB3 : GLB2) : (C_40 ? GLB1 : GLB0); + wire CLK4MXI = C_57 ? (C_56 ? GLB3 : GLB2) : (C_56 ? GLB1 : GLB0); + + assign CLK_FB0 = C_10 ? USR_FB0 : CLK1MXI; + assign CLK_FB1 = C_26 ? USR_FB1 : CLK2MXI; + assign CLK_FB2 = C_42 ? USR_FB2 : CLK3MXI; + assign CLK_FB3 = C_58 ? USR_FB3 : CLK4MXI; + +`ifdef USE_TIMING + specify + (CLK0_0 => GLB0) = 0; + (CLK0_90 => GLB0) = 0; + (CLK0_90 => GLB1) = 0; + (CLK0_180 => GLB0) = 0; + (CLK0_180 => GLB2) = 0; + (CLK0_270 => GLB0) = 0; + (CLK0_270 => GLB3) = 0; + (CLK0_BYP => GLB0) = 0; + (CLK1_0 => GLB0) = 0; + (CLK1_0 => GLB1) = 0; + (CLK1_90 => GLB1) = 0; + (CLK1_180 => GLB1) = 0; + (CLK1_180 => GLB2) = 0; + (CLK1_270 => GLB1) = 0; + (CLK1_270 => GLB3) = 0; + (CLK1_BYP => GLB1) = 0; + (CLK2_0 => GLB0) = 0; + (CLK2_0 => GLB2) = 0; + (CLK2_90 => GLB1) = 0; + (CLK2_90 => GLB2) = 0; + (CLK2_180 => GLB2) = 0; + (CLK2_270 => GLB2) = 0; + (CLK2_270 => GLB3) = 0; + (CLK2_BYP => GLB2) = 0; + (CLK3_0 => GLB0) = 0; + (CLK3_0 => GLB3) = 0; + (CLK3_90 => GLB1) = 0; + (CLK3_90 => GLB3) = 0; + (CLK3_180 => GLB2) = 0; + (CLK3_180 => GLB3) = 0; + (CLK3_270 => GLB3) = 0; + (CLK3_BYP => GLB3) = 0; + (USR_GLB0 => GLB0) = 0; + (USR_GLB1 => GLB1) = 0; + (USR_GLB2 => GLB2) = 0; + (USR_GLB3 => GLB3) = 0; + (USR_FB0 => CLK_FB0) = 0; + (USR_FB1 => CLK_FB1) = 0; + (USR_FB2 => CLK_FB2) = 0; + (USR_FB3 => CLK_FB3) = 0; + endspecify +`endif +endmodule + +`ifdef USE_RAM +module FPGA_RAM ( DOA, DOAX, DOB, DOBX, + ECC1B_ERRA, + ECC1B_ERRB, + ECC2B_ERRA, + ECC2B_ERRB, + CLKA, + CLKB, + ENA, + ENB, + GLWEA, + GLWEB, + ADDRA0, + ADDRA1, + ADDRA0X, + ADDRA1X, + ADDRB0, + ADDRB0X, + ADDRB1, + ADDRB1X, + C_ADDRA, + C_ADDRB, + DIA, + DIB, + WEA, + WEB, + + F_RSTN, + F_FULL, + F_EMPTY, + F_AL_FULL, + F_AL_EMPTY, + FRD_ERR, + FWR_ERR, + FRD_ADDR, + FWR_ADDR, + FRD_ADDRX, + FWR_ADDRX, + + FORW_CAS_WRAO, + FORW_CAS_WRBO, + FORW_CAS_BMAO, + FORW_CAS_BMBO, + FORW_CAS_RDAO, + FORW_CAS_RDBO, + + FORW_UADDRAO, + FORW_LADDRAO, + FORW_UADDRBO, + FORW_LADDRBO, + + FORW_UA0CLKO, FORW_UA0ENO, FORW_UA0WEO, FORW_LA0CLKO, FORW_LA0ENO, FORW_LA0WEO, + FORW_UA1CLKO, FORW_UA1ENO, FORW_UA1WEO, FORW_LA1CLKO, FORW_LA1ENO, FORW_LA1WEO, + FORW_UB0CLKO, FORW_UB0ENO, FORW_UB0WEO, FORW_LB0CLKO, FORW_LB0ENO, FORW_LB0WEO, + FORW_UB1CLKO, FORW_UB1ENO, FORW_UB1WEO, FORW_LB1CLKO, FORW_LB1ENO, FORW_LB1WEO, + + CLOCKA, CLOCKB, + CLOCK1, CLOCK2, CLOCK3, CLOCK4, + + FORW_CAS_WRAI, FORW_CAS_WRBI, FORW_CAS_BMAI, FORW_CAS_BMBI, + + FORW_CAS_RDAI, FORW_CAS_RDBI, + FORW_LADDRAI, FORW_UADDRAI, FORW_LADDRBI, FORW_UADDRBI, + + FORW_LA0CLKI, FORW_LA0ENI, FORW_LA0WEI, FORW_UA0CLKI, FORW_UA0ENI, FORW_UA0WEI, + FORW_LA1CLKI, FORW_LA1ENI, FORW_LA1WEI, FORW_UA1CLKI, FORW_UA1ENI, FORW_UA1WEI, + FORW_LB0CLKI, FORW_LB0ENI, FORW_LB0WEI, FORW_UB0CLKI, FORW_UB0ENI, FORW_UB0WEI, + FORW_LB1CLKI, FORW_LB1ENI, FORW_LB1WEI, FORW_UB1CLKI, FORW_UB1ENI, FORW_UB1WEI + ); + + parameter RAM_CFG = 216'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00; + + parameter INIT_00 = 320'hx; parameter INIT_01 = 320'hx; parameter INIT_02 = 320'hx; parameter INIT_03 = 320'hx; + parameter INIT_04 = 320'hx; parameter INIT_05 = 320'hx; parameter INIT_06 = 320'hx; parameter INIT_07 = 320'hx; + parameter INIT_08 = 320'hx; parameter INIT_09 = 320'hx; parameter INIT_0A = 320'hx; parameter INIT_0B = 320'hx; + parameter INIT_0C = 320'hx; parameter INIT_0D = 320'hx; parameter INIT_0E = 320'hx; parameter INIT_0F = 320'hx; + parameter INIT_10 = 320'hx; parameter INIT_11 = 320'hx; parameter INIT_12 = 320'hx; parameter INIT_13 = 320'hx; + parameter INIT_14 = 320'hx; parameter INIT_15 = 320'hx; parameter INIT_16 = 320'hx; parameter INIT_17 = 320'hx; + parameter INIT_18 = 320'hx; parameter INIT_19 = 320'hx; parameter INIT_1A = 320'hx; parameter INIT_1B = 320'hx; + parameter INIT_1C = 320'hx; parameter INIT_1D = 320'hx; parameter INIT_1E = 320'hx; parameter INIT_1F = 320'hx; + parameter INIT_20 = 320'hx; parameter INIT_21 = 320'hx; parameter INIT_22 = 320'hx; parameter INIT_23 = 320'hx; + parameter INIT_24 = 320'hx; parameter INIT_25 = 320'hx; parameter INIT_26 = 320'hx; parameter INIT_27 = 320'hx; + parameter INIT_28 = 320'hx; parameter INIT_29 = 320'hx; parameter INIT_2A = 320'hx; parameter INIT_2B = 320'hx; + parameter INIT_2C = 320'hx; parameter INIT_2D = 320'hx; parameter INIT_2E = 320'hx; parameter INIT_2F = 320'hx; + parameter INIT_30 = 320'hx; parameter INIT_31 = 320'hx; parameter INIT_32 = 320'hx; parameter INIT_33 = 320'hx; + parameter INIT_34 = 320'hx; parameter INIT_35 = 320'hx; parameter INIT_36 = 320'hx; parameter INIT_37 = 320'hx; + parameter INIT_38 = 320'hx; parameter INIT_39 = 320'hx; parameter INIT_3A = 320'hx; parameter INIT_3B = 320'hx; + parameter INIT_3C = 320'hx; parameter INIT_3D = 320'hx; parameter INIT_3E = 320'hx; parameter INIT_3F = 320'hx; + parameter INIT_40 = 320'hx; parameter INIT_41 = 320'hx; parameter INIT_42 = 320'hx; parameter INIT_43 = 320'hx; + parameter INIT_44 = 320'hx; parameter INIT_45 = 320'hx; parameter INIT_46 = 320'hx; parameter INIT_47 = 320'hx; + parameter INIT_48 = 320'hx; parameter INIT_49 = 320'hx; parameter INIT_4A = 320'hx; parameter INIT_4B = 320'hx; + parameter INIT_4C = 320'hx; parameter INIT_4D = 320'hx; parameter INIT_4E = 320'hx; parameter INIT_4F = 320'hx; + parameter INIT_50 = 320'hx; parameter INIT_51 = 320'hx; parameter INIT_52 = 320'hx; parameter INIT_53 = 320'hx; + parameter INIT_54 = 320'hx; parameter INIT_55 = 320'hx; parameter INIT_56 = 320'hx; parameter INIT_57 = 320'hx; + parameter INIT_58 = 320'hx; parameter INIT_59 = 320'hx; parameter INIT_5A = 320'hx; parameter INIT_5B = 320'hx; + parameter INIT_5C = 320'hx; parameter INIT_5D = 320'hx; parameter INIT_5E = 320'hx; parameter INIT_5F = 320'hx; + parameter INIT_60 = 320'hx; parameter INIT_61 = 320'hx; parameter INIT_62 = 320'hx; parameter INIT_63 = 320'hx; + parameter INIT_64 = 320'hx; parameter INIT_65 = 320'hx; parameter INIT_66 = 320'hx; parameter INIT_67 = 320'hx; + parameter INIT_68 = 320'hx; parameter INIT_69 = 320'hx; parameter INIT_6A = 320'hx; parameter INIT_6B = 320'hx; + parameter INIT_6C = 320'hx; parameter INIT_6D = 320'hx; parameter INIT_6E = 320'hx; parameter INIT_6F = 320'hx; + parameter INIT_70 = 320'hx; parameter INIT_71 = 320'hx; parameter INIT_72 = 320'hx; parameter INIT_73 = 320'hx; + parameter INIT_74 = 320'hx; parameter INIT_75 = 320'hx; parameter INIT_76 = 320'hx; parameter INIT_77 = 320'hx; + parameter INIT_78 = 320'hx; parameter INIT_79 = 320'hx; parameter INIT_7A = 320'hx; parameter INIT_7B = 320'hx; + parameter INIT_7C = 320'hx; parameter INIT_7D = 320'hx; parameter INIT_7E = 320'hx; parameter INIT_7F = 320'hx; + + output[39:0] DOA, DOAX, DOB,DOBX; + output [3:0] ECC1B_ERRA, ECC1B_ERRB, ECC2B_ERRA, ECC2B_ERRB; + output FORW_CAS_WRAO, FORW_CAS_WRBO, FORW_CAS_BMAO, FORW_CAS_BMBO, FORW_CAS_RDAO, FORW_CAS_RDBO; + output [15:0] FORW_UADDRAO, FORW_LADDRAO, FORW_UADDRBO, FORW_LADDRBO; + output FORW_UA0CLKO, FORW_UA0ENO, FORW_UA0WEO, FORW_LA0CLKO, FORW_LA0ENO, FORW_LA0WEO; + output FORW_UA1CLKO, FORW_UA1ENO, FORW_UA1WEO, FORW_LA1CLKO, FORW_LA1ENO, FORW_LA1WEO; + output FORW_UB0CLKO, FORW_UB0ENO, FORW_UB0WEO, FORW_LB0CLKO, FORW_LB0ENO, FORW_LB0WEO; + output FORW_UB1CLKO, FORW_UB1ENO, FORW_UB1WEO, FORW_LB1CLKO, FORW_LB1ENO, FORW_LB1WEO; + + output [3:0] CLOCKA; + output [3:0] CLOCKB; + + input CLOCK1, CLOCK2, CLOCK3, CLOCK4; + input FORW_CAS_WRAI, FORW_CAS_WRBI, FORW_CAS_BMAI, FORW_CAS_BMBI, FORW_CAS_RDAI, FORW_CAS_RDBI; + input [15:0] FORW_LADDRAI, FORW_UADDRAI, FORW_LADDRBI, FORW_UADDRBI; + + input FORW_LA0CLKI, FORW_LA0ENI, FORW_LA0WEI, FORW_UA0CLKI, FORW_UA0ENI, FORW_UA0WEI; + input FORW_LA1CLKI, FORW_LA1ENI, FORW_LA1WEI, FORW_UA1CLKI, FORW_UA1ENI, FORW_UA1WEI; + input FORW_LB0CLKI, FORW_LB0ENI, FORW_LB0WEI, FORW_UB0CLKI, FORW_UB0ENI, FORW_UB0WEI; + input FORW_LB1CLKI, FORW_LB1ENI, FORW_LB1WEI, FORW_UB1CLKI, FORW_UB1ENI, FORW_UB1WEI; + + input [3:0] CLKA,CLKB,ENA,ENB, GLWEA,GLWEB; + input [15:0] ADDRA0,ADDRA1, ADDRA0X, ADDRA1X, ADDRB0,ADDRB1, ADDRB0X, ADDRB1X; + input [39:0] DIA,DIB,WEA,WEB; + input [7:0] C_ADDRA, C_ADDRB; + + input F_RSTN; + output [1:0] F_FULL; + output [1:0] F_EMPTY; + output [1:0] F_AL_FULL; + output [1:0] F_AL_EMPTY; + output [1:0] FRD_ERR; + output [1:0] FWR_ERR; + output [15:0] FRD_ADDR; + output [15:0] FWR_ADDR; + output [15:0] FRD_ADDRX; + output [15:0] FWR_ADDRX; + + wire a0_clk1_in = CLKA[0]; + wire a0_clk2_in = CLKA[1]; + wire a1_clk1_in = CLKA[2]; + wire a1_clk2_in = CLKA[3]; + + wire b0_clk1_in = CLKB[0]; + wire b0_clk2_in = CLKB[1]; + wire b1_clk1_in = CLKB[2]; + wire b1_clk2_in = CLKB[3]; + + // forward_up + wire forward_up_a0_en_in, forward_up_a1_en_in, forward_up_b0_en_in, forward_up_b1_en_in; + wire forward_up_a0_we_in, forward_up_a1_we_in, forward_up_b0_we_in, forward_up_b1_we_in; + wire forward_up_a0_clk_in, forward_up_a1_clk_in, forward_up_b0_clk_in, forward_up_b1_clk_in; + // EN + assign forward_up_a0_en_in = FORW_UA0ENI; + assign forward_up_a1_en_in = FORW_UA1ENI; + assign forward_up_b0_en_in = FORW_UB0ENI; + assign forward_up_b1_en_in = FORW_UB1ENI; + // WE + assign forward_up_a0_we_in = FORW_UA0WEI; + assign forward_up_a1_we_in = FORW_UA1WEI; + assign forward_up_b0_we_in = FORW_UB0WEI; + assign forward_up_b1_we_in = FORW_UB1WEI; + // CLK + assign forward_up_a0_clk_in = FORW_UA0CLKI; + assign forward_up_a1_clk_in = FORW_UA1CLKI; + assign forward_up_b0_clk_in = FORW_UB0CLKI; + assign forward_up_b1_clk_in = FORW_UB1CLKI; + + // forward_low + wire forward_low_a0_en_in, forward_low_a1_en_in,forward_low_b0_en_in, forward_low_b1_en_in; + wire forward_low_a0_we_in, forward_low_a1_we_in, forward_low_b0_we_in, forward_low_b1_we_in; + wire forward_low_a0_clk_in, forward_low_a1_clk_in, forward_low_b0_clk_in, forward_low_b1_clk_in; + // EN + assign forward_low_a0_en_in = FORW_LA0ENI; + assign forward_low_a1_en_in = FORW_LA1ENI; + assign forward_low_b0_en_in = FORW_LB0ENI; + assign forward_low_b1_en_in = FORW_LB1ENI; + // WE + assign forward_low_a0_we_in = FORW_LA0WEI; + assign forward_low_a1_we_in = FORW_LA1WEI; + assign forward_low_b0_we_in = FORW_LB0WEI; + assign forward_low_b1_we_in = FORW_LB1WEI; + // CLK + assign forward_low_a0_clk_in = FORW_LA0CLKI; + assign forward_low_a1_clk_in = FORW_LA1CLKI; + assign forward_low_b0_clk_in = FORW_LB0CLKI; + assign forward_low_b1_clk_in = FORW_LB1CLKI; + + + wire [7:0] cdyn_cfg_forward_a_addr, cdyn_cfg_forward_b_addr; + assign cdyn_cfg_forward_a_addr = 8'b0; + assign cdyn_cfg_forward_b_addr = 8'b0; + + wire [15:0] a0_addr1_in; + assign a0_addr1_in = ADDRA0; + + wire [15:0] a1_addr1_in; + assign a1_addr1_in = ADDRA1; + + + wire [15:0] b0_addr1_in; + assign b0_addr1_in = ADDRB0; + + wire [15:0] b1_addr1_in; + assign b1_addr1_in = ADDRB1; + + + wire [7:0] a0_addr2_in; + assign a0_addr2_in = {ADDRA0X[14],ADDRA0X[12],ADDRA0X[11],ADDRA0X[9],ADDRA0X[7],ADDRA0X[5],ADDRA0X[3],ADDRA0X[1]}; + + wire [7:0] a1_addr2_in; + assign a1_addr2_in = {ADDRA1X[14],ADDRA1X[12],ADDRA1X[11],ADDRA1X[9],ADDRA1X[7],ADDRA1X[5],ADDRA1X[3],ADDRA1X[1]}; + + wire [7:0] b0_addr2_in; + assign b0_addr2_in = {ADDRB0X[15],ADDRB0X[13],ADDRB0X[10],ADDRB0X[8],ADDRB0X[6],ADDRB0X[4],ADDRB0X[2],ADDRB0X[0]}; + + wire [7:0] b1_addr2_in; + assign b1_addr2_in = {ADDRB1X[15],ADDRB1X[13],ADDRB1X[10],ADDRB1X[8],ADDRB1X[6],ADDRB1X[4],ADDRB1X[2],ADDRB1X[0]}; + + wire [19:0] a0_wrdata_in; + assign a0_wrdata_in = DIA[19:0]; + + wire [19:0] a1_wrdata_in; + assign a1_wrdata_in = DIA[39:20]; + + wire [19:0] b0_wrdata_in; + assign b0_wrdata_in = DIB[19:0]; + + wire [19:0] b1_wrdata_in; + assign b1_wrdata_in = DIB[39:20]; + + wire [19:0] a0_bitmask_in; + assign a0_bitmask_in = WEA[19:0]; + + wire [19:0] a1_bitmask_in; + assign a1_bitmask_in = WEA[39:20]; + + wire [19:0] b0_bitmask_in; + assign b0_bitmask_in = WEB[19:0]; + + wire [19:0] b1_bitmask_in; + assign b1_bitmask_in = WEB[39:20]; + + wire [19:0] a0_rddata_out; + assign DOA[19:0] = a0_rddata_out; + assign DOAX[19:0] = a0_rddata_out; + + wire [19:0] a1_rddata_out; + assign DOA[39:20] = a1_rddata_out; + assign DOAX[39:20] = a1_rddata_out; + + wire [19:0] b0_rddata_out; + assign DOB[19:0] = b0_rddata_out; + assign DOBX[19:0] = b0_rddata_out; + + wire [19:0] b1_rddata_out; + assign DOB[39:20] = b1_rddata_out; + assign DOBX[39:20] = b1_rddata_out; + + wire a0_en1_in = ENA[0]; + wire a0_en2_in = ENA[1]; + wire a1_en1_in = ENA[2]; + wire a1_en2_in = ENA[3]; + + wire a0_we1_in = GLWEA[0]; + wire a0_we2_in = GLWEA[1]; + wire a1_we1_in = GLWEA[2]; + wire a1_we2_in = GLWEA[3]; + + wire b0_en1_in = ENB[0]; + wire b0_en2_in = ENB[1]; + wire b1_en1_in = ENB[2]; + wire b1_en2_in = ENB[3]; + + wire b0_we1_in = GLWEB[0]; + wire b0_we2_in = GLWEB[1]; + wire b1_we1_in = GLWEB[2]; + wire b1_we2_in = GLWEB[3]; + + wire [1:0] lo_left_ecc_single_error_flag_out; + wire [1:0] up_left_ecc_single_error_flag_out; + wire [1:0] lo_right_ecc_single_error_flag_out; + wire [1:0] up_right_ecc_single_error_flag_out; + + wire [1:0] lo_left_ecc_double_error_flag_out; + wire [1:0] up_left_ecc_double_error_flag_out; + wire [1:0] lo_right_ecc_double_error_flag_out; + wire [1:0] up_right_ecc_double_error_flag_out; + + assign ECC1B_ERRA[0] = lo_left_ecc_single_error_flag_out[0]; + assign ECC1B_ERRA[1] = up_left_ecc_single_error_flag_out[0]; + assign ECC1B_ERRA[2] = lo_right_ecc_single_error_flag_out[0]; + assign ECC1B_ERRA[3] = up_right_ecc_single_error_flag_out[0]; + + assign ECC2B_ERRA[0] = lo_left_ecc_double_error_flag_out[0]; + assign ECC2B_ERRA[1] = up_left_ecc_double_error_flag_out[0]; + assign ECC2B_ERRA[2] = lo_right_ecc_double_error_flag_out[0]; + assign ECC2B_ERRA[3] = up_right_ecc_double_error_flag_out[0]; + + assign ECC1B_ERRB[0] = lo_left_ecc_single_error_flag_out[1]; + assign ECC1B_ERRB[1] = up_left_ecc_single_error_flag_out[1]; + assign ECC1B_ERRB[2] = lo_right_ecc_single_error_flag_out[1]; + assign ECC1B_ERRB[3] = up_right_ecc_single_error_flag_out[1]; + + assign ECC2B_ERRB[0] = lo_left_ecc_double_error_flag_out[1]; + assign ECC2B_ERRB[1] = up_left_ecc_double_error_flag_out[1]; + assign ECC2B_ERRB[2] = lo_right_ecc_double_error_flag_out[1]; + assign ECC2B_ERRB[3] = up_right_ecc_double_error_flag_out[1]; + + // initialize memory arrays to 0 + integer i; + + dpsram_block_4x512x20 + i_dpsram_block + ( + .testmode_i (1'b0), + .testmode_o (), + // Configuration interface + .ram_cfg(RAM_CFG), + .cfg_gx_i (1'b0 ), + .lo_y1CFG_GLOBAL_DEC_Y_i (1'b0 ), + .cfg_addr_i (5'b0), + .cfg_data_i (8'b0), + .cfg_set_all_i(1'b0), + + .cfg_gx_o (), + .cfg_addr_o (), + .cfg_data_o (), + .cfg_set_all_o(), + + .left_clock1_o(CLOCKA[0]), + .left_clock2_o(CLOCKA[1]), + .left_clock3_o(CLOCKA[2]), + .left_clock4_o(CLOCKA[3]), + + .right_clock1_o(CLOCKB[0]), + .right_clock2_o(CLOCKB[1]), + .right_clock3_o(CLOCKB[2]), + .right_clock4_o(CLOCKB[3]), + + + //.cdyn_almost_empty_offset_i(cdyn_almost_empty_offset_in), + //.cdyn_almost_full_offset_i (cdyn_almost_full_offset_in ), + .cdyn_cfg_forward_a_addr_i (cdyn_cfg_forward_a_addr), + .cdyn_cfg_forward_b_addr_i (cdyn_cfg_forward_b_addr), + + // Interface for BIST and preloading + .bist_enable_i (1'b0), + .bist_wrdata_i (40'b0), + .bist_rddata_i (40'b0), + .bist_enable_o (), + .bist_wrdata_o (), + .bist_rddata_o (), + + // Global clocks + .global_clk_x1_i(CLOCK1), + .global_clk_x2_i(CLOCK2), + .global_clk_y1_i(CLOCK3), + .global_clk_y2_i(CLOCK4), + + // DPSRAM-block port A0 + .a0_clk1_i (a0_clk1_in ), + .a0_clk2_i (a0_clk2_in ), + .a0_en1_i (a0_en1_in ), + .a0_en2_i (a0_en2_in ), + .a0_we1_i (a0_we1_in ), + .a0_we2_i (a0_we2_in ), + .a0_addr1_i (a0_addr1_in ), + .a0_addr2_dblin_i (a0_addr2_in ), + .a0_wrdata_i (a0_wrdata_in ), + .a0_bitmask_i(a0_bitmask_in), + .a0_rddata_o (a0_rddata_out ), + + // DPSRAM-block port A1 + .a1_clk1_i (a1_clk1_in ), + .a1_clk2_i (a1_clk2_in ), + .a1_en1_i (a1_en1_in ), + .a1_en2_i (a1_en2_in ), + .a1_we1_i (a1_we1_in ), + .a1_we2_i (a1_we2_in ), + .a1_addr1_i (a1_addr1_in ), + .a1_addr2_dblin_i (a1_addr2_in ), + .a1_wrdata_i (a1_wrdata_in ), + .a1_bitmask_i(a1_bitmask_in), + .a1_rddata_o (a1_rddata_out ), + + // DPSRAM-block port B0 + .b0_clk1_i (b0_clk1_in ), + .b0_clk2_i (b0_clk2_in ), + .b0_en1_i (b0_en1_in ), + .b0_en2_i (b0_en2_in ), + .b0_we1_i (b0_we1_in ), + .b0_we2_i (b0_we2_in ), + .b0_addr1_i (b0_addr1_in ), + .b0_addr2_dblin_i (b0_addr2_in ), + .b0_wrdata_i (b0_wrdata_in ), + .b0_bitmask_i(b0_bitmask_in), + .b0_rddata_o (b0_rddata_out ), + + // DPSRAM-block port B1 + .b1_clk1_i (b1_clk1_in ), + .b1_clk2_i (b1_clk2_in ), + .b1_en1_i (b1_en1_in ), + .b1_en2_i (b1_en2_in ), + .b1_we1_i (b1_we1_in ), + .b1_we2_i (b1_we2_in ), + .b1_addr1_i (b1_addr1_in ), + .b1_addr2_dblin_i (b1_addr2_in ), + .b1_wrdata_i (b1_wrdata_in ), + .b1_bitmask_i(b1_bitmask_in), + .b1_rddata_o (b1_rddata_out ), + + + // forward signals addr + .forward_low_a_addr_i(16'b0), + .forward_up_a_addr_i (16'b0 ), + .forward_low_a_addr_o(), + .forward_up_a_addr_o ( ), + .forward_low_b_addr_i(16'b0), + .forward_up_b_addr_i (16'b0 ), + .forward_low_b_addr_o(), + .forward_up_b_addr_o ( ), + + + // forward signals cascade mode + .forward_cascade_wrdata_a_i (1'b0), + .forward_cascade_wrdata_b_i (1'b0), + .forward_cascade_wrdata_a_o (FORW_CAS_WRAO), + .forward_cascade_wrdata_b_o (FORW_CAS_WRBO), + .forward_cascade_bitmask_a_i(1'b0), + .forward_cascade_bitmask_b_i(1'b0), + .forward_cascade_bitmask_a_o(FORW_CAS_BMAO), + .forward_cascade_bitmask_b_o(FORW_CAS_BMBO), + .forward_cascade_rddata_a_i (1'b0), + .forward_cascade_rddata_b_i (1'b0), + .forward_cascade_rddata_a_o (FORW_CAS_RDAO), + .forward_cascade_rddata_b_o (FORW_CAS_RDBO), + + + // forward signals port A0 + .forward_low_a0_clk_i(forward_low_a0_clk_in), + .forward_low_a0_en_i (forward_low_a0_en_in ), + .forward_low_a0_we_i (forward_low_a0_we_in ), + .forward_up_a0_clk_i (forward_up_a0_clk_in ), + .forward_up_a0_en_i (forward_up_a0_en_in ), + .forward_up_a0_we_i (forward_up_a0_we_in ), + .forward_low_a0_clk_o(), + .forward_low_a0_en_o ( ), + .forward_low_a0_we_o ( ), + .forward_up_a0_clk_o ( ), + .forward_up_a0_en_o ( ), + .forward_up_a0_we_o ( ), + + // forward signals port A1 + .forward_low_a1_clk_i(forward_low_a1_clk_in), + .forward_low_a1_en_i (forward_low_a1_en_in ), + .forward_low_a1_we_i (forward_low_a1_we_in ), + .forward_up_a1_clk_i (forward_up_a1_clk_in ), + .forward_up_a1_en_i (forward_up_a1_en_in ), + .forward_up_a1_we_i (forward_up_a1_we_in ), + .forward_low_a1_clk_o(), + .forward_low_a1_en_o ( ), + .forward_low_a1_we_o ( ), + .forward_up_a1_clk_o ( ), + .forward_up_a1_en_o ( ), + .forward_up_a1_we_o ( ), + + // forward signals port B0 + .forward_low_b0_clk_i(forward_low_b0_clk_in), + .forward_low_b0_en_i (forward_low_b0_en_in ), + .forward_low_b0_we_i (forward_low_b0_we_in ), + .forward_up_b0_clk_i (forward_up_b0_clk_in ), + .forward_up_b0_en_i (forward_up_b0_en_in ), + .forward_up_b0_we_i (forward_up_b0_we_in ), + .forward_low_b0_clk_o(), + .forward_low_b0_en_o ( ), + .forward_low_b0_we_o ( ), + .forward_up_b0_clk_o ( ), + .forward_up_b0_en_o ( ), + .forward_up_b0_we_o ( ), + + // forward signals port B1 + .forward_low_b1_clk_i(forward_low_b1_clk_in), + .forward_low_b1_en_i (forward_low_b1_en_in ), + .forward_low_b1_we_i (forward_low_b1_we_in ), + .forward_up_b1_clk_i (forward_up_b1_clk_in ), + .forward_up_b1_en_i (forward_up_b1_en_in ), + .forward_up_b1_we_i (forward_up_b1_we_in ), + .forward_low_b1_clk_o(), + .forward_low_b1_en_o ( ), + .forward_low_b1_we_o ( ), + .forward_up_b1_clk_o ( ), + .forward_up_b1_en_o ( ), + .forward_up_b1_we_o ( ), + + + // ECC status + .lo_left_ecc_single_error_flag_o(lo_left_ecc_single_error_flag_out), + .up_left_ecc_single_error_flag_o(up_left_ecc_single_error_flag_out), + .lo_right_ecc_single_error_flag_o(lo_right_ecc_single_error_flag_out), + .up_right_ecc_single_error_flag_o(up_right_ecc_single_error_flag_out), + + .lo_left_ecc_double_error_flag_o(lo_left_ecc_double_error_flag_out), + .up_left_ecc_double_error_flag_o(up_left_ecc_double_error_flag_out), + .lo_right_ecc_double_error_flag_o(lo_right_ecc_double_error_flag_out), + .up_right_ecc_double_error_flag_o(up_right_ecc_double_error_flag_out), + + + // FIFO ctrl/status data + .fifo_rstn_i (F_RSTN), + .left1_fifo_full_o (F_FULL[0]), + .left1_fifo_empty_o (F_EMPTY[0]), + .left1_fifo_almost_full_o (F_AL_FULL[0]), + .left1_fifo_almost_empty_o (F_AL_EMPTY[0]), + .left1_fifo_write_error_o (FWR_ERR[0]), + .left1_fifo_read_error_o (FRD_ERR[0]), + .left2_fifo_full_o (F_FULL[1]), + .left2_fifo_empty_o (F_EMPTY[1]), + .left2_fifo_almost_full_o (F_AL_FULL[1]), + .left2_fifo_almost_empty_o (F_AL_EMPTY[1]), + .left2_fifo_write_error_o (FWR_ERR[1]), + .left2_fifo_read_error_o (FRD_ERR[1]), + .fifo_write_address_o(FWR_ADDR), + .fifo_read_address_o (FRD_ADDR) + ); + + integer k; + + initial begin + + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[0],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[0],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[0],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[0]} = INIT_00[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[1],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[1],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[1],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[1]} = INIT_00[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[2],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[2],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[2],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[2]} = INIT_00[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[3],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[3],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[3],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[3]} = INIT_00[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[4],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[4],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[4],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[4]} = INIT_01[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[5],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[5],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[5],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[5]} = INIT_01[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[6],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[6],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[6],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[6]} = INIT_01[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[7],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[7],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[7],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[7]} = INIT_01[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[8],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[8],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[8],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[8]} = INIT_02[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[9],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[9],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[9],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[9]} = INIT_02[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[10],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[10],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[10],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[10]} = INIT_02[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[11],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[11],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[11],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[11]} = INIT_02[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[12],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[12],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[12],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[12]} = INIT_03[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[13],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[13],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[13],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[13]} = INIT_03[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[14],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[14],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[14],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[14]} = INIT_03[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[15],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[15],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[15],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[15]} = INIT_03[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[16],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[16],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[16],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[16]} = INIT_04[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[17],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[17],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[17],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[17]} = INIT_04[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[18],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[18],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[18],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[18]} = INIT_04[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[19],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[19],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[19],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[19]} = INIT_04[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[20],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[20],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[20],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[20]} = INIT_05[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[21],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[21],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[21],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[21]} = INIT_05[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[22],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[22],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[22],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[22]} = INIT_05[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[23],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[23],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[23],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[23]} = INIT_05[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[24],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[24],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[24],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[24]} = INIT_06[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[25],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[25],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[25],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[25]} = INIT_06[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[26],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[26],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[26],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[26]} = INIT_06[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[27],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[27],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[27],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[27]} = INIT_06[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[28],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[28],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[28],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[28]} = INIT_07[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[29],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[29],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[29],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[29]} = INIT_07[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[30],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[30],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[30],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[30]} = INIT_07[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[31],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[31],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[31],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[31]} = INIT_07[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[32],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[32],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[32],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[32]} = INIT_08[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[33],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[33],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[33],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[33]} = INIT_08[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[34],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[34],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[34],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[34]} = INIT_08[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[35],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[35],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[35],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[35]} = INIT_08[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[36],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[36],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[36],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[36]} = INIT_09[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[37],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[37],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[37],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[37]} = INIT_09[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[38],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[38],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[38],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[38]} = INIT_09[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[39],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[39],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[39],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[39]} = INIT_09[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[40],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[40],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[40],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[40]} = INIT_0A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[41],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[41],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[41],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[41]} = INIT_0A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[42],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[42],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[42],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[42]} = INIT_0A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[43],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[43],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[43],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[43]} = INIT_0A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[44],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[44],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[44],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[44]} = INIT_0B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[45],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[45],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[45],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[45]} = INIT_0B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[46],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[46],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[46],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[46]} = INIT_0B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[47],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[47],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[47],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[47]} = INIT_0B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[48],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[48],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[48],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[48]} = INIT_0C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[49],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[49],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[49],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[49]} = INIT_0C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[50],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[50],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[50],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[50]} = INIT_0C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[51],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[51],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[51],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[51]} = INIT_0C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[52],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[52],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[52],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[52]} = INIT_0D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[53],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[53],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[53],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[53]} = INIT_0D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[54],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[54],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[54],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[54]} = INIT_0D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[55],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[55],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[55],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[55]} = INIT_0D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[56],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[56],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[56],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[56]} = INIT_0E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[57],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[57],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[57],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[57]} = INIT_0E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[58],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[58],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[58],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[58]} = INIT_0E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[59],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[59],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[59],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[59]} = INIT_0E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[60],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[60],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[60],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[60]} = INIT_0F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[61],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[61],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[61],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[61]} = INIT_0F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[62],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[62],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[62],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[62]} = INIT_0F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[63],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[63],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[63],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[63]} = INIT_0F[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[64],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[64],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[64],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[64]} = INIT_10[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[65],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[65],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[65],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[65]} = INIT_10[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[66],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[66],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[66],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[66]} = INIT_10[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[67],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[67],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[67],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[67]} = INIT_10[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[68],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[68],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[68],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[68]} = INIT_11[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[69],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[69],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[69],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[69]} = INIT_11[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[70],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[70],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[70],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[70]} = INIT_11[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[71],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[71],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[71],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[71]} = INIT_11[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[72],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[72],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[72],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[72]} = INIT_12[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[73],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[73],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[73],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[73]} = INIT_12[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[74],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[74],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[74],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[74]} = INIT_12[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[75],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[75],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[75],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[75]} = INIT_12[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[76],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[76],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[76],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[76]} = INIT_13[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[77],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[77],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[77],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[77]} = INIT_13[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[78],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[78],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[78],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[78]} = INIT_13[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[79],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[79],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[79],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[79]} = INIT_13[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[80],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[80],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[80],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[80]} = INIT_14[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[81],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[81],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[81],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[81]} = INIT_14[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[82],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[82],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[82],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[82]} = INIT_14[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[83],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[83],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[83],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[83]} = INIT_14[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[84],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[84],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[84],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[84]} = INIT_15[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[85],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[85],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[85],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[85]} = INIT_15[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[86],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[86],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[86],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[86]} = INIT_15[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[87],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[87],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[87],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[87]} = INIT_15[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[88],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[88],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[88],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[88]} = INIT_16[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[89],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[89],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[89],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[89]} = INIT_16[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[90],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[90],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[90],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[90]} = INIT_16[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[91],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[91],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[91],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[91]} = INIT_16[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[92],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[92],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[92],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[92]} = INIT_17[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[93],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[93],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[93],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[93]} = INIT_17[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[94],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[94],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[94],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[94]} = INIT_17[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[95],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[95],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[95],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[95]} = INIT_17[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[96],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[96],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[96],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[96]} = INIT_18[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[97],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[97],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[97],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[97]} = INIT_18[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[98],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[98],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[98],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[98]} = INIT_18[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[99],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[99],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[99],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[99]} = INIT_18[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[100],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[100],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[100],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[100]} = INIT_19[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[101],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[101],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[101],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[101]} = INIT_19[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[102],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[102],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[102],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[102]} = INIT_19[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[103],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[103],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[103],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[103]} = INIT_19[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[104],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[104],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[104],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[104]} = INIT_1A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[105],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[105],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[105],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[105]} = INIT_1A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[106],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[106],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[106],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[106]} = INIT_1A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[107],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[107],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[107],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[107]} = INIT_1A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[108],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[108],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[108],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[108]} = INIT_1B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[109],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[109],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[109],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[109]} = INIT_1B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[110],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[110],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[110],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[110]} = INIT_1B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[111],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[111],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[111],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[111]} = INIT_1B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[112],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[112],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[112],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[112]} = INIT_1C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[113],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[113],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[113],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[113]} = INIT_1C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[114],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[114],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[114],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[114]} = INIT_1C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[115],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[115],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[115],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[115]} = INIT_1C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[116],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[116],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[116],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[116]} = INIT_1D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[117],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[117],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[117],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[117]} = INIT_1D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[118],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[118],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[118],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[118]} = INIT_1D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[119],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[119],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[119],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[119]} = INIT_1D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[120],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[120],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[120],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[120]} = INIT_1E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[121],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[121],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[121],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[121]} = INIT_1E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[122],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[122],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[122],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[122]} = INIT_1E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[123],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[123],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[123],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[123]} = INIT_1E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[124],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[124],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[124],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[124]} = INIT_1F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[125],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[125],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[125],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[125]} = INIT_1F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[126],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[126],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[126],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[126]} = INIT_1F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[127],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[127],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[127],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[127]} = INIT_1F[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[128],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[128],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[128],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[128]} = INIT_20[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[129],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[129],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[129],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[129]} = INIT_20[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[130],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[130],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[130],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[130]} = INIT_20[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[131],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[131],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[131],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[131]} = INIT_20[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[132],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[132],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[132],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[132]} = INIT_21[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[133],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[133],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[133],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[133]} = INIT_21[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[134],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[134],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[134],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[134]} = INIT_21[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[135],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[135],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[135],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[135]} = INIT_21[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[136],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[136],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[136],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[136]} = INIT_22[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[137],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[137],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[137],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[137]} = INIT_22[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[138],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[138],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[138],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[138]} = INIT_22[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[139],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[139],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[139],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[139]} = INIT_22[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[140],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[140],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[140],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[140]} = INIT_23[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[141],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[141],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[141],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[141]} = INIT_23[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[142],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[142],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[142],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[142]} = INIT_23[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[143],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[143],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[143],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[143]} = INIT_23[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[144],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[144],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[144],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[144]} = INIT_24[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[145],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[145],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[145],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[145]} = INIT_24[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[146],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[146],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[146],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[146]} = INIT_24[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[147],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[147],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[147],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[147]} = INIT_24[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[148],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[148],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[148],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[148]} = INIT_25[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[149],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[149],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[149],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[149]} = INIT_25[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[150],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[150],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[150],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[150]} = INIT_25[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[151],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[151],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[151],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[151]} = INIT_25[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[152],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[152],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[152],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[152]} = INIT_26[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[153],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[153],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[153],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[153]} = INIT_26[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[154],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[154],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[154],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[154]} = INIT_26[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[155],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[155],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[155],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[155]} = INIT_26[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[156],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[156],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[156],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[156]} = INIT_27[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[157],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[157],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[157],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[157]} = INIT_27[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[158],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[158],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[158],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[158]} = INIT_27[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[159],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[159],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[159],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[159]} = INIT_27[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[160],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[160],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[160],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[160]} = INIT_28[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[161],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[161],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[161],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[161]} = INIT_28[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[162],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[162],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[162],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[162]} = INIT_28[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[163],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[163],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[163],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[163]} = INIT_28[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[164],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[164],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[164],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[164]} = INIT_29[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[165],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[165],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[165],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[165]} = INIT_29[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[166],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[166],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[166],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[166]} = INIT_29[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[167],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[167],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[167],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[167]} = INIT_29[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[168],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[168],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[168],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[168]} = INIT_2A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[169],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[169],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[169],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[169]} = INIT_2A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[170],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[170],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[170],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[170]} = INIT_2A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[171],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[171],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[171],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[171]} = INIT_2A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[172],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[172],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[172],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[172]} = INIT_2B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[173],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[173],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[173],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[173]} = INIT_2B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[174],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[174],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[174],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[174]} = INIT_2B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[175],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[175],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[175],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[175]} = INIT_2B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[176],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[176],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[176],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[176]} = INIT_2C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[177],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[177],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[177],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[177]} = INIT_2C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[178],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[178],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[178],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[178]} = INIT_2C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[179],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[179],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[179],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[179]} = INIT_2C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[180],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[180],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[180],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[180]} = INIT_2D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[181],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[181],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[181],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[181]} = INIT_2D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[182],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[182],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[182],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[182]} = INIT_2D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[183],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[183],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[183],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[183]} = INIT_2D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[184],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[184],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[184],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[184]} = INIT_2E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[185],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[185],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[185],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[185]} = INIT_2E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[186],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[186],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[186],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[186]} = INIT_2E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[187],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[187],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[187],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[187]} = INIT_2E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[188],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[188],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[188],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[188]} = INIT_2F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[189],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[189],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[189],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[189]} = INIT_2F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[190],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[190],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[190],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[190]} = INIT_2F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[191],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[191],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[191],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[191]} = INIT_2F[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[192],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[192],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[192],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[192]} = INIT_30[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[193],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[193],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[193],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[193]} = INIT_30[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[194],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[194],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[194],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[194]} = INIT_30[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[195],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[195],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[195],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[195]} = INIT_30[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[196],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[196],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[196],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[196]} = INIT_31[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[197],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[197],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[197],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[197]} = INIT_31[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[198],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[198],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[198],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[198]} = INIT_31[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[199],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[199],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[199],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[199]} = INIT_31[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[200],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[200],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[200],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[200]} = INIT_32[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[201],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[201],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[201],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[201]} = INIT_32[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[202],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[202],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[202],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[202]} = INIT_32[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[203],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[203],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[203],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[203]} = INIT_32[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[204],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[204],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[204],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[204]} = INIT_33[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[205],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[205],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[205],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[205]} = INIT_33[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[206],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[206],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[206],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[206]} = INIT_33[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[207],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[207],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[207],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[207]} = INIT_33[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[208],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[208],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[208],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[208]} = INIT_34[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[209],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[209],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[209],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[209]} = INIT_34[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[210],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[210],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[210],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[210]} = INIT_34[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[211],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[211],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[211],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[211]} = INIT_34[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[212],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[212],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[212],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[212]} = INIT_35[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[213],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[213],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[213],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[213]} = INIT_35[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[214],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[214],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[214],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[214]} = INIT_35[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[215],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[215],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[215],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[215]} = INIT_35[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[216],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[216],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[216],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[216]} = INIT_36[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[217],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[217],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[217],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[217]} = INIT_36[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[218],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[218],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[218],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[218]} = INIT_36[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[219],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[219],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[219],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[219]} = INIT_36[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[220],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[220],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[220],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[220]} = INIT_37[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[221],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[221],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[221],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[221]} = INIT_37[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[222],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[222],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[222],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[222]} = INIT_37[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[223],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[223],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[223],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[223]} = INIT_37[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[224],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[224],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[224],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[224]} = INIT_38[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[225],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[225],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[225],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[225]} = INIT_38[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[226],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[226],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[226],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[226]} = INIT_38[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[227],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[227],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[227],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[227]} = INIT_38[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[228],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[228],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[228],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[228]} = INIT_39[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[229],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[229],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[229],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[229]} = INIT_39[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[230],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[230],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[230],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[230]} = INIT_39[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[231],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[231],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[231],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[231]} = INIT_39[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[232],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[232],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[232],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[232]} = INIT_3A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[233],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[233],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[233],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[233]} = INIT_3A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[234],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[234],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[234],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[234]} = INIT_3A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[235],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[235],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[235],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[235]} = INIT_3A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[236],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[236],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[236],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[236]} = INIT_3B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[237],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[237],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[237],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[237]} = INIT_3B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[238],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[238],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[238],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[238]} = INIT_3B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[239],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[239],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[239],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[239]} = INIT_3B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[240],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[240],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[240],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[240]} = INIT_3C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[241],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[241],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[241],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[241]} = INIT_3C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[242],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[242],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[242],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[242]} = INIT_3C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[243],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[243],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[243],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[243]} = INIT_3C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[244],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[244],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[244],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[244]} = INIT_3D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[245],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[245],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[245],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[245]} = INIT_3D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[246],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[246],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[246],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[246]} = INIT_3D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[247],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[247],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[247],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[247]} = INIT_3D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[248],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[248],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[248],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[248]} = INIT_3E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[249],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[249],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[249],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[249]} = INIT_3E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[250],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[250],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[250],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[250]} = INIT_3E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[251],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[251],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[251],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[251]} = INIT_3E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[252],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[252],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[252],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[252]} = INIT_3F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[253],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[253],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[253],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[253]} = INIT_3F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[254],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[254],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[254],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[254]} = INIT_3F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[255],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[255],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[255],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[255]} = INIT_3F[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[256],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[256],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[256],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[256]} = INIT_40[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[257],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[257],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[257],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[257]} = INIT_40[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[258],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[258],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[258],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[258]} = INIT_40[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[259],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[259],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[259],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[259]} = INIT_40[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[260],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[260],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[260],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[260]} = INIT_41[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[261],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[261],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[261],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[261]} = INIT_41[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[262],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[262],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[262],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[262]} = INIT_41[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[263],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[263],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[263],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[263]} = INIT_41[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[264],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[264],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[264],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[264]} = INIT_42[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[265],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[265],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[265],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[265]} = INIT_42[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[266],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[266],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[266],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[266]} = INIT_42[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[267],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[267],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[267],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[267]} = INIT_42[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[268],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[268],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[268],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[268]} = INIT_43[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[269],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[269],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[269],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[269]} = INIT_43[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[270],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[270],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[270],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[270]} = INIT_43[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[271],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[271],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[271],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[271]} = INIT_43[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[272],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[272],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[272],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[272]} = INIT_44[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[273],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[273],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[273],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[273]} = INIT_44[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[274],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[274],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[274],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[274]} = INIT_44[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[275],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[275],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[275],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[275]} = INIT_44[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[276],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[276],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[276],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[276]} = INIT_45[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[277],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[277],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[277],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[277]} = INIT_45[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[278],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[278],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[278],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[278]} = INIT_45[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[279],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[279],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[279],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[279]} = INIT_45[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[280],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[280],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[280],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[280]} = INIT_46[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[281],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[281],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[281],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[281]} = INIT_46[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[282],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[282],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[282],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[282]} = INIT_46[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[283],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[283],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[283],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[283]} = INIT_46[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[284],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[284],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[284],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[284]} = INIT_47[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[285],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[285],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[285],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[285]} = INIT_47[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[286],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[286],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[286],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[286]} = INIT_47[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[287],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[287],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[287],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[287]} = INIT_47[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[288],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[288],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[288],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[288]} = INIT_48[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[289],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[289],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[289],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[289]} = INIT_48[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[290],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[290],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[290],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[290]} = INIT_48[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[291],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[291],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[291],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[291]} = INIT_48[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[292],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[292],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[292],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[292]} = INIT_49[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[293],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[293],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[293],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[293]} = INIT_49[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[294],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[294],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[294],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[294]} = INIT_49[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[295],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[295],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[295],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[295]} = INIT_49[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[296],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[296],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[296],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[296]} = INIT_4A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[297],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[297],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[297],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[297]} = INIT_4A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[298],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[298],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[298],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[298]} = INIT_4A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[299],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[299],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[299],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[299]} = INIT_4A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[300],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[300],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[300],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[300]} = INIT_4B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[301],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[301],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[301],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[301]} = INIT_4B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[302],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[302],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[302],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[302]} = INIT_4B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[303],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[303],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[303],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[303]} = INIT_4B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[304],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[304],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[304],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[304]} = INIT_4C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[305],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[305],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[305],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[305]} = INIT_4C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[306],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[306],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[306],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[306]} = INIT_4C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[307],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[307],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[307],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[307]} = INIT_4C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[308],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[308],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[308],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[308]} = INIT_4D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[309],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[309],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[309],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[309]} = INIT_4D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[310],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[310],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[310],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[310]} = INIT_4D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[311],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[311],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[311],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[311]} = INIT_4D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[312],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[312],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[312],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[312]} = INIT_4E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[313],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[313],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[313],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[313]} = INIT_4E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[314],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[314],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[314],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[314]} = INIT_4E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[315],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[315],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[315],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[315]} = INIT_4E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[316],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[316],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[316],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[316]} = INIT_4F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[317],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[317],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[317],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[317]} = INIT_4F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[318],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[318],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[318],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[318]} = INIT_4F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[319],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[319],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[319],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[319]} = INIT_4F[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[320],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[320],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[320],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[320]} = INIT_50[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[321],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[321],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[321],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[321]} = INIT_50[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[322],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[322],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[322],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[322]} = INIT_50[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[323],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[323],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[323],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[323]} = INIT_50[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[324],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[324],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[324],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[324]} = INIT_51[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[325],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[325],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[325],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[325]} = INIT_51[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[326],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[326],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[326],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[326]} = INIT_51[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[327],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[327],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[327],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[327]} = INIT_51[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[328],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[328],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[328],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[328]} = INIT_52[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[329],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[329],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[329],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[329]} = INIT_52[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[330],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[330],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[330],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[330]} = INIT_52[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[331],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[331],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[331],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[331]} = INIT_52[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[332],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[332],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[332],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[332]} = INIT_53[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[333],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[333],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[333],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[333]} = INIT_53[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[334],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[334],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[334],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[334]} = INIT_53[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[335],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[335],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[335],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[335]} = INIT_53[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[336],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[336],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[336],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[336]} = INIT_54[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[337],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[337],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[337],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[337]} = INIT_54[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[338],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[338],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[338],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[338]} = INIT_54[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[339],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[339],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[339],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[339]} = INIT_54[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[340],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[340],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[340],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[340]} = INIT_55[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[341],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[341],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[341],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[341]} = INIT_55[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[342],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[342],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[342],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[342]} = INIT_55[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[343],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[343],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[343],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[343]} = INIT_55[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[344],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[344],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[344],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[344]} = INIT_56[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[345],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[345],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[345],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[345]} = INIT_56[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[346],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[346],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[346],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[346]} = INIT_56[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[347],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[347],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[347],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[347]} = INIT_56[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[348],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[348],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[348],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[348]} = INIT_57[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[349],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[349],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[349],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[349]} = INIT_57[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[350],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[350],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[350],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[350]} = INIT_57[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[351],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[351],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[351],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[351]} = INIT_57[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[352],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[352],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[352],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[352]} = INIT_58[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[353],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[353],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[353],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[353]} = INIT_58[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[354],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[354],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[354],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[354]} = INIT_58[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[355],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[355],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[355],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[355]} = INIT_58[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[356],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[356],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[356],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[356]} = INIT_59[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[357],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[357],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[357],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[357]} = INIT_59[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[358],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[358],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[358],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[358]} = INIT_59[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[359],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[359],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[359],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[359]} = INIT_59[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[360],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[360],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[360],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[360]} = INIT_5A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[361],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[361],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[361],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[361]} = INIT_5A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[362],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[362],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[362],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[362]} = INIT_5A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[363],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[363],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[363],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[363]} = INIT_5A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[364],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[364],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[364],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[364]} = INIT_5B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[365],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[365],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[365],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[365]} = INIT_5B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[366],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[366],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[366],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[366]} = INIT_5B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[367],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[367],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[367],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[367]} = INIT_5B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[368],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[368],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[368],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[368]} = INIT_5C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[369],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[369],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[369],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[369]} = INIT_5C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[370],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[370],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[370],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[370]} = INIT_5C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[371],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[371],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[371],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[371]} = INIT_5C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[372],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[372],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[372],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[372]} = INIT_5D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[373],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[373],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[373],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[373]} = INIT_5D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[374],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[374],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[374],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[374]} = INIT_5D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[375],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[375],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[375],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[375]} = INIT_5D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[376],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[376],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[376],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[376]} = INIT_5E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[377],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[377],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[377],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[377]} = INIT_5E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[378],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[378],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[378],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[378]} = INIT_5E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[379],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[379],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[379],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[379]} = INIT_5E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[380],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[380],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[380],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[380]} = INIT_5F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[381],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[381],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[381],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[381]} = INIT_5F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[382],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[382],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[382],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[382]} = INIT_5F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[383],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[383],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[383],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[383]} = INIT_5F[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[384],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[384],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[384],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[384]} = INIT_60[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[385],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[385],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[385],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[385]} = INIT_60[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[386],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[386],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[386],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[386]} = INIT_60[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[387],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[387],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[387],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[387]} = INIT_60[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[388],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[388],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[388],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[388]} = INIT_61[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[389],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[389],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[389],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[389]} = INIT_61[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[390],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[390],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[390],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[390]} = INIT_61[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[391],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[391],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[391],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[391]} = INIT_61[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[392],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[392],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[392],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[392]} = INIT_62[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[393],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[393],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[393],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[393]} = INIT_62[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[394],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[394],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[394],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[394]} = INIT_62[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[395],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[395],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[395],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[395]} = INIT_62[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[396],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[396],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[396],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[396]} = INIT_63[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[397],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[397],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[397],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[397]} = INIT_63[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[398],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[398],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[398],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[398]} = INIT_63[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[399],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[399],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[399],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[399]} = INIT_63[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[400],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[400],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[400],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[400]} = INIT_64[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[401],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[401],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[401],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[401]} = INIT_64[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[402],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[402],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[402],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[402]} = INIT_64[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[403],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[403],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[403],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[403]} = INIT_64[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[404],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[404],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[404],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[404]} = INIT_65[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[405],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[405],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[405],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[405]} = INIT_65[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[406],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[406],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[406],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[406]} = INIT_65[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[407],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[407],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[407],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[407]} = INIT_65[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[408],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[408],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[408],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[408]} = INIT_66[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[409],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[409],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[409],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[409]} = INIT_66[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[410],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[410],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[410],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[410]} = INIT_66[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[411],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[411],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[411],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[411]} = INIT_66[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[412],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[412],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[412],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[412]} = INIT_67[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[413],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[413],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[413],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[413]} = INIT_67[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[414],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[414],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[414],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[414]} = INIT_67[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[415],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[415],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[415],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[415]} = INIT_67[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[416],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[416],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[416],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[416]} = INIT_68[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[417],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[417],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[417],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[417]} = INIT_68[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[418],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[418],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[418],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[418]} = INIT_68[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[419],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[419],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[419],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[419]} = INIT_68[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[420],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[420],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[420],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[420]} = INIT_69[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[421],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[421],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[421],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[421]} = INIT_69[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[422],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[422],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[422],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[422]} = INIT_69[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[423],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[423],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[423],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[423]} = INIT_69[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[424],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[424],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[424],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[424]} = INIT_6A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[425],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[425],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[425],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[425]} = INIT_6A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[426],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[426],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[426],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[426]} = INIT_6A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[427],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[427],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[427],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[427]} = INIT_6A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[428],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[428],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[428],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[428]} = INIT_6B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[429],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[429],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[429],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[429]} = INIT_6B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[430],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[430],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[430],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[430]} = INIT_6B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[431],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[431],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[431],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[431]} = INIT_6B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[432],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[432],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[432],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[432]} = INIT_6C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[433],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[433],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[433],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[433]} = INIT_6C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[434],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[434],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[434],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[434]} = INIT_6C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[435],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[435],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[435],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[435]} = INIT_6C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[436],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[436],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[436],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[436]} = INIT_6D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[437],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[437],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[437],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[437]} = INIT_6D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[438],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[438],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[438],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[438]} = INIT_6D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[439],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[439],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[439],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[439]} = INIT_6D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[440],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[440],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[440],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[440]} = INIT_6E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[441],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[441],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[441],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[441]} = INIT_6E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[442],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[442],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[442],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[442]} = INIT_6E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[443],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[443],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[443],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[443]} = INIT_6E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[444],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[444],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[444],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[444]} = INIT_6F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[445],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[445],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[445],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[445]} = INIT_6F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[446],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[446],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[446],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[446]} = INIT_6F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[447],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[447],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[447],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[447]} = INIT_6F[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[448],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[448],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[448],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[448]} = INIT_70[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[449],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[449],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[449],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[449]} = INIT_70[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[450],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[450],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[450],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[450]} = INIT_70[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[451],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[451],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[451],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[451]} = INIT_70[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[452],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[452],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[452],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[452]} = INIT_71[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[453],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[453],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[453],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[453]} = INIT_71[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[454],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[454],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[454],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[454]} = INIT_71[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[455],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[455],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[455],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[455]} = INIT_71[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[456],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[456],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[456],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[456]} = INIT_72[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[457],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[457],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[457],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[457]} = INIT_72[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[458],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[458],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[458],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[458]} = INIT_72[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[459],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[459],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[459],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[459]} = INIT_72[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[460],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[460],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[460],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[460]} = INIT_73[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[461],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[461],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[461],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[461]} = INIT_73[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[462],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[462],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[462],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[462]} = INIT_73[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[463],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[463],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[463],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[463]} = INIT_73[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[464],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[464],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[464],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[464]} = INIT_74[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[465],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[465],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[465],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[465]} = INIT_74[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[466],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[466],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[466],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[466]} = INIT_74[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[467],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[467],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[467],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[467]} = INIT_74[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[468],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[468],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[468],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[468]} = INIT_75[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[469],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[469],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[469],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[469]} = INIT_75[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[470],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[470],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[470],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[470]} = INIT_75[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[471],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[471],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[471],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[471]} = INIT_75[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[472],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[472],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[472],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[472]} = INIT_76[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[473],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[473],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[473],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[473]} = INIT_76[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[474],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[474],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[474],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[474]} = INIT_76[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[475],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[475],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[475],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[475]} = INIT_76[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[476],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[476],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[476],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[476]} = INIT_77[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[477],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[477],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[477],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[477]} = INIT_77[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[478],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[478],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[478],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[478]} = INIT_77[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[479],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[479],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[479],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[479]} = INIT_77[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[480],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[480],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[480],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[480]} = INIT_78[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[481],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[481],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[481],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[481]} = INIT_78[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[482],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[482],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[482],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[482]} = INIT_78[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[483],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[483],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[483],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[483]} = INIT_78[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[484],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[484],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[484],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[484]} = INIT_79[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[485],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[485],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[485],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[485]} = INIT_79[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[486],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[486],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[486],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[486]} = INIT_79[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[487],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[487],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[487],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[487]} = INIT_79[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[488],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[488],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[488],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[488]} = INIT_7A[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[489],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[489],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[489],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[489]} = INIT_7A[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[490],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[490],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[490],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[490]} = INIT_7A[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[491],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[491],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[491],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[491]} = INIT_7A[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[492],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[492],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[492],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[492]} = INIT_7B[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[493],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[493],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[493],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[493]} = INIT_7B[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[494],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[494],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[494],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[494]} = INIT_7B[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[495],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[495],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[495],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[495]} = INIT_7B[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[496],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[496],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[496],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[496]} = INIT_7C[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[497],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[497],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[497],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[497]} = INIT_7C[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[498],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[498],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[498],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[498]} = INIT_7C[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[499],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[499],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[499],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[499]} = INIT_7C[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[500],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[500],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[500],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[500]} = INIT_7D[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[501],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[501],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[501],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[501]} = INIT_7D[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[502],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[502],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[502],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[502]} = INIT_7D[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[503],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[503],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[503],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[503]} = INIT_7D[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[504],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[504],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[504],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[504]} = INIT_7E[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[505],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[505],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[505],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[505]} = INIT_7E[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[506],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[506],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[506],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[506]} = INIT_7E[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[507],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[507],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[507],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[507]} = INIT_7E[319:240]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[508],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[508],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[508],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[508]} = INIT_7F[79:0]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[509],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[509],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[509],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[509]} = INIT_7F[159:80]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[510],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[510],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[510],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[510]} = INIT_7F[239:160]; + {i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[511],i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[511],i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[511],i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.mem_arr[511]} = INIT_7F[319:240]; + + i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_a_r=20'b0; + i_dpsram_block.RAM_i1.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_b_r=20'b0; + i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_a_r=20'b0; + i_dpsram_block.RAM_i2.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_b_r=20'b0; + i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_a_r=20'b0; + i_dpsram_block.RAM_i3.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_b_r=20'b0; + i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_a_r=20'b0; + i_dpsram_block.RAM_i4.RM_GF28SLP_2P_512x20_c2_inst.SRAM_2P_behavioral_i.dr_b_r=20'b0; + + i_dpsram_block.output_registering_i.r_a0_rddata=20'b0; + i_dpsram_block.output_registering_i.r_a1_rddata=20'b0; + i_dpsram_block.output_registering_i.r_b0_rddata=20'b0; + i_dpsram_block.output_registering_i.r_b1_rddata=20'b0; + + i_dpsram_block.output_registering_i.r_ecc_single_error_flag=2'b0; + i_dpsram_block.output_registering_i.r_ecc_double_error_flag=2'b0; + end + +`ifdef USE_TIMING + specify + (CLOCK1 => DOA[0]) = 0; + (CLOCK1 => DOA[1]) = 0; + (CLOCK1 => DOA[2]) = 0; + (CLOCK1 => DOA[3]) = 0; + (CLOCK1 => DOA[4]) = 0; + (CLOCK1 => DOA[5]) = 0; + (CLOCK1 => DOA[6]) = 0; + (CLOCK1 => DOA[7]) = 0; + (CLOCK1 => DOA[8]) = 0; + (CLOCK1 => DOA[9]) = 0; + (CLOCK1 => DOA[10]) = 0; + (CLOCK1 => DOA[11]) = 0; + (CLOCK1 => DOA[12]) = 0; + (CLOCK1 => DOA[13]) = 0; + (CLOCK1 => DOA[14]) = 0; + (CLOCK1 => DOA[15]) = 0; + (CLOCK1 => DOA[16]) = 0; + (CLOCK1 => DOA[17]) = 0; + (CLOCK1 => DOA[18]) = 0; + (CLOCK1 => DOA[19]) = 0; + (CLOCK1 => DOA[20]) = 0; + (CLOCK1 => DOA[21]) = 0; + (CLOCK1 => DOA[22]) = 0; + (CLOCK1 => DOA[23]) = 0; + (CLOCK1 => DOA[24]) = 0; + (CLOCK1 => DOA[25]) = 0; + (CLOCK1 => DOA[26]) = 0; + (CLOCK1 => DOA[27]) = 0; + (CLOCK1 => DOA[28]) = 0; + (CLOCK1 => DOA[29]) = 0; + (CLOCK1 => DOA[30]) = 0; + (CLOCK1 => DOA[31]) = 0; + (CLOCK1 => DOA[32]) = 0; + (CLOCK1 => DOA[33]) = 0; + (CLOCK1 => DOA[34]) = 0; + (CLOCK1 => DOA[35]) = 0; + (CLOCK1 => DOA[36]) = 0; + (CLOCK1 => DOA[37]) = 0; + (CLOCK1 => DOA[38]) = 0; + (CLOCK1 => DOA[39]) = 0; + (CLOCK1 => DOB[0]) = 0; + (CLOCK1 => DOB[1]) = 0; + (CLOCK1 => DOB[2]) = 0; + (CLOCK1 => DOB[3]) = 0; + (CLOCK1 => DOB[4]) = 0; + (CLOCK1 => DOB[5]) = 0; + (CLOCK1 => DOB[6]) = 0; + (CLOCK1 => DOB[7]) = 0; + (CLOCK1 => DOB[8]) = 0; + (CLOCK1 => DOB[9]) = 0; + (CLOCK1 => DOB[10]) = 0; + (CLOCK1 => DOB[11]) = 0; + (CLOCK1 => DOB[12]) = 0; + (CLOCK1 => DOB[13]) = 0; + (CLOCK1 => DOB[14]) = 0; + (CLOCK1 => DOB[15]) = 0; + (CLOCK1 => DOB[16]) = 0; + (CLOCK1 => DOB[17]) = 0; + (CLOCK1 => DOB[18]) = 0; + (CLOCK1 => DOB[19]) = 0; + (CLOCK1 => DOB[20]) = 0; + (CLOCK1 => DOB[21]) = 0; + (CLOCK1 => DOB[22]) = 0; + (CLOCK1 => DOB[23]) = 0; + (CLOCK1 => DOB[24]) = 0; + (CLOCK1 => DOB[25]) = 0; + (CLOCK1 => DOB[26]) = 0; + (CLOCK1 => DOB[27]) = 0; + (CLOCK1 => DOB[28]) = 0; + (CLOCK1 => DOB[29]) = 0; + (CLOCK1 => DOB[30]) = 0; + (CLOCK1 => DOB[31]) = 0; + (CLOCK1 => DOB[32]) = 0; + (CLOCK1 => DOB[33]) = 0; + (CLOCK1 => DOB[34]) = 0; + (CLOCK1 => DOB[35]) = 0; + (CLOCK1 => DOB[36]) = 0; + (CLOCK1 => DOB[37]) = 0; + (CLOCK1 => DOB[38]) = 0; + (CLOCK1 => DOB[39]) = 0; + endspecify +`endif + +endmodule +`endif // USE_RAM diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/tb.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..4e6b4f71d0dbadb247f25cf27bf811da4defe56a --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/tb.sv @@ -0,0 +1,112 @@ +//========================================================================== +// Copyright (C) 2024 Chili.CHIPS*ba +//-------------------------------------------------------------------------- +// PROPRIETARY INFORMATION +// +// The information contained in this file is the property of CHILI CHIPS LLC. +// Except as specifically authorized in writing by CHILI CHIPS LLC, the holder +// of this file: (1) shall keep all information contained herein confidential; +// and (2) shall protect the same in whole or in part from disclosure and +// dissemination to all third parties; and (3) shall use the same for operation +// and maintenance purposes only. +//-------------------------------------------------------------------------- +// Description: Simulation testbench for the LUTRAM arrays +//========================================================================== +`timescale 1ps/1ps +module tb #( + parameter int RUN_SIM_US = 1_000_0 +)(); + +//-------------------------------------------------------------- +// Generate clock and run sim for the specified amount of time + localparam HALF_PERIOD_PS = 50_000; // 50MHz + logic clk_10; + + logic [4:0] addr; + logic [9:0] wdat; + logic we; + logic [9:0] rdat; + + initial begin + clk_10 = 1'b0; + + $dumpfile("../2.sim/tb.vcd"); + $dumpvars(0, tb); + + fork + forever begin: clock_gen + #(HALF_PERIOD_PS * 1ps) clk_10 = ~clk_10; + end + + begin: run_sim + #(RUN_SIM_US * 1us); + $finish(); + end + + begin: seq + // write to a location + #200ns + addr = 5'h0; + we = 1; + wdat = 10'h0BC; + #200ns + // read from it + we = 0; + + #1us + // write to a location + #200ns + addr = 5'b01111; + we = 1; + wdat = 10'h1BC; + #200ns + // read from it + we = 0; + + // write to a location + #200ns + addr = 5'b11111; + we = 1; + wdat = 10'h2BC; + #200ns + // read from it + we = 0; + + + // write to a location + #200ns + addr = 5'b10000; + we = 1; + wdat = 10'h3BC; + #200ns + // read from it + we = 0; + + + + end + join + end + + top #( + .LUTRAM16X10(2) + ) + dut ( + .clk(clk_10), + .addr(addr), + .wdat(wdat), + .we(we), + .rdat(rdat) + ); + +//-------------------------------------------------------------- + + +endmodule: tb + +/* +------------------------------------------------------------------------------ +Version History: +------------------------------------------------------------------------------ + 2024/08/20 TarikI: initial creation +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/versimSV.cpp b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/versimSV.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6e3eca8c9a7b4d0b8783f07199e1acd1dd551b9e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/2.sim/versimSV.cpp @@ -0,0 +1,70 @@ +/////////////////////////////////////////////////////////////////////////////// +// +// (c) Copyright 2024 -- CHILI CHIPS LLC, All rights reserved. +// +// PROPRIETARY INFORMATION +// +// The information contained in this file is the property of CHILI CHIPS LLC. +// Except as specifically authorized in writing by CHILI CHIPS LLC, the holder +// of this file: (1) shall keep all information contained herein confidential; +// and (2) shall protect the same in whole or in part from disclosure and +// dissemination to all third parties; and (3) shall use the same for operation +// and maintenance purposes only. +//----------------------------------------------------------------------------- +// C++ DPI which allows Verilator to use System Verilog behavioral constructs, +// i.e. create SV testbenches +/////////////////////////////////////////////////////////////////////////////// + +#include +#include "verilated.h" +#include "Vtb.h" //change to V + +double sc_time_stamp() { return 0; } + +//---------------------------------------- +int main(int argc, char** argv, char**) { + // Setup context, defaults, and parse command line + Verilated::debug(0); + const std::unique_ptr contextp{new VerilatedContext}; + contextp->traceEverOn(true); + contextp->commandArgs(argc, argv); + VerilatedFstC *m_trace = new VerilatedFstC; + + // Construct the Verilated model, from Vtop.h generated from Verilating + const std::unique_ptr topp{new Vtb{contextp.get()}}; + + m_trace->set_time_resolution("1ps"); + m_trace->set_time_unit("1ps"); + topp->trace(m_trace, 20); + m_trace->open("wave.fst"); + + // Simulate until $finish + long long int t0 = 0; + while (!contextp->gotFinish()) { + // Evaluate model + topp->eval(); + m_trace->dump(contextp->time()); + + // Advance time + if (!topp->eventsPending()) break; + contextp->time(topp->nextTimeSlot()); + t0++; + } + + if (!contextp->gotFinish()) { + VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n");); + } + + m_trace->close(); + + // Closing cleanup + topp->final(); + return 0; +} + +/* +------------------------------------------------------------------------------ +Version History: +------------------------------------------------------------------------------ + 2024/02/14 TI: initial creation +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/hw_build_GUI/impl/hw_build_GUI_process_config.json b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/hw_build_GUI/impl/hw_build_GUI_process_config.json new file mode 100644 index 0000000000000000000000000000000000000000..c5d41fb7ad9802ccba89330f5648fe2c80b4a4aa --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/hw_build_GUI/impl/hw_build_GUI_process_config.json @@ -0,0 +1,92 @@ +{ + "BACKGROUND_PROGRAMMING" : "off", + "COMPRESS" : false, + "CPU" : false, + "CRC_CHECK" : true, + "Clock_Route_Order" : 0, + "Convert_SDP32_36_to_SDP16_18" : true, + "Correct_Hold_Violation" : true, + "DONE" : false, + "DOWNLOAD_SPEED" : "default", + "Disable_Insert_Pad" : false, + "ENABLE_CTP" : false, + "ENABLE_MERGE_MODE" : false, + "ENCRYPTION_KEY" : false, + "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000", + "ERROR_DECTION_AND_CORRECTION" : false, + "ERROR_DECTION_ONLY" : false, + "ERROR_INJECTION" : false, + "EXTERNAL_MASTER_CONFIG_CLOCK" : false, + "Enable_DSRM" : false, + "FORMAT" : "binary", + "FREQUENCY_DIVIDER" : "1", + "Generate_Constraint_File_of_Ports" : false, + "Generate_IBIS_File" : false, + "Generate_Plain_Text_Timing_Report" : false, + "Generate_Post_PNR_Simulation_Model_File" : false, + "Generate_Post_Place_File" : false, + "Generate_SDF_File" : false, + "Generate_VHDL_Post_PNR_Simulation_Model_File" : false, + "Global_Freq" : "default", + "GwSyn_Loop_Limit" : 2000, + "HOTBOOT" : false, + "I2C" : false, + "I2C_SLAVE_ADDR" : "00", + "INCREMENTAL_PLACE_AND_ROUTING" : "0", + "INCREMENTAL_PLACE_ONLY" : "0", + "IncludePath" : [ + + ], + "Incremental_Compile" : "", + "Initialize_Primitives" : false, + "JTAG" : false, + "MODE_IO" : false, + "MSPI" : false, + "MSPI_JUMP" : false, + "MULTIBOOT_ADDRESS_WIDTH" : "24", + "MULTIBOOT_MODE" : "Single", + "MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000", + "MULTIJUMP_ADDRESS_WIDTH" : "24", + "MULTIJUMP_MODE" : "Single", + "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000", + "Multi_Boot" : true, + "OUTPUT_BASE_NAME" : "hw_build_GUI", + "POWER_ON_RESET_MONITOR" : true, + "PRINT_BSRAM_VALUE" : true, + "PROGRAM_DONE_BYPASS" : false, + "PlaceInRegToIob" : true, + "PlaceIoRegToIob" : true, + "PlaceOutRegToIob" : true, + "Place_Option" : "1", + "Process_Configuration_Verion" : "1.0", + "Promote_Physical_Constraint_Warning_to_Error" : true, + "READY" : false, + "RECONFIG_N" : false, + "Ram_RW_Check" : false, + "Replicate_Resources" : false, + "Report_Auto-Placed_Io_Information" : false, + "Route_Maxfan" : 23, + "Route_Option" : "0", + "Run_Timing_Driven" : true, + "SECURE_MODE" : false, + "SECURITY_BIT" : true, + "SEU_HANDLER" : false, + "SEU_HANDLER_CHECKSUM" : false, + "SEU_HANDLER_MODE" : "auto", + "SSPI" : false, + "STOP_SEU_HANDLER" : false, + "Show_All_Warnings" : false, + "Synthesize_tool" : "GowinSyn", + "TclPre" : "", + "TopModule" : "", + "USERCODE" : "default", + "Unused_Pin" : "As_input_tri_stated_with_pull_up", + "VCC" : "1.0", + "VCCAUX" : 3.3, + "VCCX" : "3.3", + "VHDL_Standard" : "VHDL_Std_1993", + "Verilog_Standard" : "Vlg_Std_Sysv2017", + "WAKE_UP" : "0", + "show_all_warnings" : false, + "turn_off_bg" : false +} \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/hw_build_GUI/impl/pnr/hw_build_GUI.rpt.txt b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/hw_build_GUI/impl/pnr/hw_build_GUI.rpt.txt new file mode 100644 index 0000000000000000000000000000000000000000..22784749b4d26b0772650d23839c94970a485f4d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/hw_build_GUI/impl/pnr/hw_build_GUI.rpt.txt @@ -0,0 +1,217 @@ +//Copyright (C)2014-2025 Gowin Semiconductor Corporation. +//All rights reserved. + + +1. PnR Messages + + : PnR Report + : D:\repos\openCologne\8.StressTest\2.LUTRAM_stress_test\3.build\hw_build_GUI\impl\gwsynthesis\hw_build_GUI.vg + : D:\repos\LUTRAM_Stress_Test\1.hw\constraints\top.pinout.cst + : D:\repos\LUTRAM_Stress_Test\1.hw\constraints\top.timing.sdc + : V1.9.11.01 (64-bit) + : GW2AR-LV18QN88PC8/I7 + : GW2AR-18 + : C + :Sat Mar 22 21:06:42 2025 + + +2. PnR Details + + Running placement: + Placement Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s + Placement Phase 1: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s + Placement Phase 2: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s + Placement Phase 3: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s + ERROR (PR0003) : Failed to place with '216 REG(s) unPlaced ' in the device 'GW2AR-18C-QFN88P-8' + Total Placement: CPU time = 0h 0m 21s, Elapsed time = 0h 0m 21s + Running routing: + --- + Generate output files: + CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s + + Total Time and Memory Usage: CPU time = 0h 0m 21s, Elapsed time = 0h 0m 21s, Peak memory usage = 602MB + + +3. Resource Usage Summary + + -------------------------------------------------------------------------------- + Resources | Usage | Utilization + -------------------------------------------------------------------------------- + Logic | 10404/20736 | 51% + --LUT,ALU,ROM16 | 6516(6516 LUT, 0 ALU, 0 ROM16) | - + --SSRAM(RAM16) | 648 | - + Register | 8640/15750 | 55% + --Logic Register as Latch | 0/15552 | 0% + --Logic Register as FF | 8640/15552 | 56% + --I/O Register as Latch | 0/198 | 0% + --I/O Register as FF | 0/198 | 0% + CLS | 9101/10368 | 88% + I/O Port | 26/66 | 40% + I/O Buf | 26 | - + --Input Buf | 25 | - + --Output Buf | 1 | - + --Inout Buf | 0 | - + ================================================================================ + + + +4. I/O Bank Usage Summary + + -------------------------------------- + I/O Bank | Usage | Utilization + -------------------------------------- + bank 0 | 3/8 | 38% + bank 1 | 5/9 | 56% + bank 2 | 0/4 | 0% + bank 3 | 5/17 | 30% + bank 4 | 3/8 | 38% + bank 5 | 7/10 | 70% + bank 6 | 2/9 | 23% + bank 7 | 1/1 | 100% + ====================================== + + +5. Clock Resource Usage Summary + + + +6. Pinout by Port Name + +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | CFG | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +clk | - | 4/7 | Y | in | IOL7[A] | LPLL1_T_in | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8 +addr[0] | - | 25/5 | Y | in | IOB6[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +addr[1] | - | 28/5 | Y | in | IOB8[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +addr[2] | - | 27/5 | Y | in | IOB8[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +addr[3] | - | 75/1 | Y | in | IOT34[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +addr[4] | - | 74/1 | Y | in | IOT34[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +addr[5] | - | 73/1 | Y | in | IOT40[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +addr[6] | - | 86/0 | Y | in | IOT4[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +addr[7] | - | 49/3 | Y | in | IOR49[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +addr[8] | - | 76/1 | Y | in | IOT30[B] | GCLKC_1 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +addr[9] | - | 13/6 | N | in | IOL45[A] | LPLL2_T_in | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3 +addr[10] | - | 39/4 | N | in | IOB40[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +addr[11] | - | 32/5 | N | in | IOB18[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +addr[12] | - | 30/5 | N | in | IOB14[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +we | - | 48/3 | Y | in | IOR49[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +wdat[0] | - | 51/3 | Y | in | IOR45[A] | RPLL2_T_in | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +wdat[1] | - | 63/3 | Y | in | IOR29[A] | GCLKT_3 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +wdat[2] | - | 33/5 | Y | in | IOB24[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +wdat[3] | - | 41/4 | Y | in | IOB43[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +wdat[4] | - | 42/4 | Y | in | IOB42[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +wdat[5] | - | 80/0 | Y | in | IOT27[A] | GCLKT_0 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +wdat[6] | - | 34/5 | Y | in | IOB24[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +wdat[7] | - | 53/3 | Y | in | IOR38[B] | DOUT/WE_N | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +wdat[8] | - | 77/1 | Y | in | IOT30[A] | GCLKT_1 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +wdat[9] | - | 85/0 | Y | in | IOT4[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +rdat | - | 15/6 | Y | out | IOL47[A] | LPLL2_T_fb | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3 +================================================================================================================================================================================================================== + + + + +7. All Package Pins + +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Loc./Bank| Signal | Dir. | Site | CFG | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +86/0 | addr[6] | in | IOT4[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +85/0 | wdat[9] | in | IOT4[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +84/0 | - | in | IOT6[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +83/0 | - | in | IOT6[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +82/0 | - | in | IOT17[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +81/0 | - | in | IOT17[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +80/0 | wdat[5] | in | IOT27[A] | GCLKT_0 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +79/0 | - | in | IOT27[B] | GCLKC_0 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +77/1 | wdat[8] | in | IOT30[A] | GCLKT_1 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +76/1 | addr[8] | in | IOT30[B] | GCLKC_1 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +75/1 | addr[3] | in | IOT34[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +74/1 | addr[4] | in | IOT34[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +73/1 | addr[5] | in | IOT40[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +72/1 | - | in | IOT40[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +71/1 | - | in | IOT44[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +70/1 | - | in | IOT44[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +69/1 | - | in | IOT50[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +25/5 | addr[0] | in | IOB6[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +26/5 | - | in | IOB6[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +27/5 | addr[2] | in | IOB8[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +28/5 | addr[1] | in | IOB8[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +29/5 | - | in | IOB14[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +30/5 | addr[12] | in | IOB14[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +31/5 | - | in | IOB18[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +32/5 | addr[11] | in | IOB18[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +33/5 | wdat[2] | in | IOB24[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +34/5 | wdat[6] | in | IOB24[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +35/4 | - | in | IOB30[A] | GCLKT_4 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +36/4 | - | in | IOB30[B] | GCLKC_4 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +37/4 | - | in | IOB34[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +38/4 | - | in | IOB34[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +39/4 | addr[10] | in | IOB40[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +40/4 | - | in | IOB40[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +42/4 | wdat[4] | in | IOB42[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +41/4 | wdat[3] | in | IOB43[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +p1-14/7 | - | in | IOL3[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-13/7 | - | in | IOL3[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +4/7 | clk | in | IOL7[A] | LPLL1_T_in | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8 +p1-12/7 | - | in | IOL8[A] | LPLL1_T_fb | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-11/7 | - | in | IOL8[B] | LPLL1_C_fb | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-10/7 | - | in | IOL9[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-9/7 | - | in | IOL9[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-8/7 | - | in | IOL11[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-7/7 | - | in | IOL11[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-6/7 | - | in | IOL12[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-5/7 | - | in | IOL12[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-4/7 | - | in | IOL13[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-3/7 | - | in | IOL15[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p1-2/7 | - | in | IOL15[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +10/6 | - | in | IOL29[A] | GCLKT_6 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +11/6 | - | in | IOL29[B] | GCLKC_6 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +13/6 | addr[9] | in | IOL45[A] | LPLL2_T_in | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 3.3 +15/6 | rdat | out | IOL47[A] | LPLL2_T_fb | LVCMOS33 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 3.3 +16/6 | - | in | IOL47[B] | LPLL2_C_fb | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +17/6 | - | in | IOL49[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +18/6 | - | in | IOL49[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +19/6 | - | in | IOL51[A] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +20/6 | - | in | IOL51[B] | - | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 3.3 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +p2-2/2 | - | in | IOR3[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-3/2 | - | in | IOR3[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-4/2 | - | in | IOR4[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-5/2 | - | in | IOR5[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-6/2 | - | in | IOR5[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-7/2 | - | in | IOR7[A] | RPLL1_T_in | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-8/2 | - | in | IOR7[B] | RPLL1_C_in | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-9/2 | - | in | IOR9[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-10/2 | - | in | IOR9[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-11/2 | - | in | IOR11[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-12/2 | - | in | IOR11[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-13/2 | - | in | IOR12[A] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +p2-14/2 | - | in | IOR12[B] | - | LVCMOS18 | - | UP | - | - | - | - | - | - | - +8/2 | - | out | IOR25[A] | TDO | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8 +5/2 | - | in | IOR25[B] | TMS | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 +6/2 | - | in | IOR26[A] | TCK | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 +7/2 | - | in | IOR26[B] | TDI | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8 +63/3 | wdat[1] | in | IOR29[A] | GCLKT_3 | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +88/3 | - | in | IOR30[A] | MODE0 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +87/3 | - | in | IOR30[B] | MODE1 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +9/3 | - | in | IOR31[B] | RECONFIG_N | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +62/3 | - | in | IOR33[A] | MI/D7 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +61/3 | - | in | IOR33[B] | MO/D6 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +60/3 | - | in | IOR34[A] | MCS_N/D5 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +59/3 | - | in | IOR34[B] | MCLK/D4 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +57/3 | - | in | IOR35[A] | FASTRD_N/D3 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +56/3 | - | in | IOR36[A] | SO/D1 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +55/3 | - | in | IOR36[B] | SSPI_CS_N/D0 | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +54/3 | - | in | IOR38[A] | DIN/CLKHOLD_N | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +53/3 | wdat[7] | in | IOR38[B] | DOUT/WE_N | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +52/3 | - | in | IOR39[A] | SCLK | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.2 +51/3 | wdat[0] | in | IOR45[A] | RPLL2_T_in | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +49/3 | addr[7] | in | IOR49[A] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +48/3 | we | in | IOR49[B] | - | LVCMOS33 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.2 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +====================================================================================================================================================================================== + + diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut3.txt b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut3.txt new file mode 100644 index 0000000000000000000000000000000000000000..713d37329003040a5c93803e4c6936b7c5fba211 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut3.txt @@ -0,0 +1,3 @@ +0040 6 aBC +0080 4 ABC + Gesamt: 10 DS4: 0 diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut4.txt b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut4.txt new file mode 100644 index 0000000000000000000000000000000000000000..0d1a80ae54d44762b3bf14cf7ae4a313bcee9b4b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut4.txt @@ -0,0 +1,9 @@ +0001 2 abcd +0100 8 abcD +03FE 1 BD?/ac\:1:c:0 +0777 40 /AB\(d+c) +1000 11 abCD +4000 17 aBCD +8000 2 ABCD +8FFF 10 (AB)+c+d + Gesamt: 91 DS4: 1 diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut_report.txt b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut_report.txt new file mode 100644 index 0000000000000000000000000000000000000000..a9cf5435d162d1c7630e984a4eb5b4d77fc7c81b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lut_report.txt @@ -0,0 +1,275 @@ + 1 LUT4 8FFF (AB)+c+d + 2 LUT4 4000 aBCD + 3 LUT4 0777 /AB\(d+c) + 4 LUT4 0100 abcD + 5 LUT4 1000 abCD + 6 LUT4 0777 /AB\(d+c) + 7 LUT4 4000 aBCD + 8 LUT4 1000 abCD + 9 LUT2 4 aB + 10 LUT4 03FE BD?/ac\:1:c:0 + 11 LUT4 0777 /AB\(d+c) + 12 LUT4 1000 abCD + 13 LUT4 0100 abcD + 14 LUT4 0777 /AB\(d+c) + 15 LUT4 1000 abCD + 16 LUT4 0100 abcD + 17 LUT4 0100 abcD + 18 LUT4 8FFF (AB)+c+d + 19 LUT4 4000 aBCD + 20 LUT4 0777 /AB\(d+c) + 21 LUT4 0777 /AB\(d+c) + 22 LUT2 4 aB + 23 LUT4 0777 /AB\(d+c) + 24 LUT4 0777 /AB\(d+c) + 25 LUT4 8FFF (AB)+c+d + 26 LUT4 4000 aBCD + 27 LUT4 0777 /AB\(d+c) + 28 LUT4 0777 /AB\(d+c) + 29 LUT2 4 aB + 30 LUT4 0777 /AB\(d+c) + 31 LUT4 0777 /AB\(d+c) + 32 LUT4 8FFF (AB)+c+d + 33 LUT4 4000 aBCD + 34 LUT4 0777 /AB\(d+c) + 35 LUT4 0777 /AB\(d+c) + 36 LUT2 4 aB + 37 LUT4 0777 /AB\(d+c) + 38 LUT4 0777 /AB\(d+c) + 39 LUT4 8FFF (AB)+c+d + 40 LUT4 4000 aBCD + 41 LUT4 0777 /AB\(d+c) + 42 LUT4 0777 /AB\(d+c) + 43 LUT2 4 aB + 44 LUT4 0777 /AB\(d+c) + 45 LUT4 0777 /AB\(d+c) + 46 LUT4 8FFF (AB)+c+d + 47 LUT4 4000 aBCD + 48 LUT4 0777 /AB\(d+c) + 49 LUT4 0777 /AB\(d+c) + 50 LUT2 4 aB + 51 LUT4 0777 /AB\(d+c) + 52 LUT4 0777 /AB\(d+c) + 53 LUT4 8FFF (AB)+c+d + 54 LUT4 4000 aBCD + 55 LUT4 0777 /AB\(d+c) + 56 LUT4 0777 /AB\(d+c) + 57 LUT2 4 aB + 58 LUT4 0777 /AB\(d+c) + 59 LUT4 0777 /AB\(d+c) + 60 LUT4 8FFF (AB)+c+d + 61 LUT4 4000 aBCD + 62 LUT4 0777 /AB\(d+c) + 63 LUT4 0777 /AB\(d+c) + 64 LUT2 4 aB + 65 LUT4 0777 /AB\(d+c) + 66 LUT4 0777 /AB\(d+c) + 67 LUT4 8FFF (AB)+c+d + 68 LUT4 4000 aBCD + 69 LUT4 0777 /AB\(d+c) + 70 LUT4 0777 /AB\(d+c) + 71 LUT2 4 aB + 72 LUT4 0777 /AB\(d+c) + 73 LUT4 0777 /AB\(d+c) + 74 LUT4 8FFF (AB)+c+d + 75 LUT4 4000 aBCD + 76 LUT4 0777 /AB\(d+c) + 77 LUT4 0777 /AB\(d+c) + 78 LUT2 4 aB + 79 LUT4 0777 /AB\(d+c) + 80 LUT4 0777 /AB\(d+c) + 81 LUT2 8 AB + 82 LUT3 80 ABC + 83 LUT4 8000 ABCD + 84 LUT4 1000 abCD + 85 LUT2 8 AB + 86 LUT4 0100 abcD + 87 LUT2 8 AB + 88 LUT4 4000 aBCD + 89 LUT2 8 AB + 90 LUT4 1000 abCD + 91 LUT2 8 AB + 92 LUT4 1000 abCD + 93 LUT2 8 AB + 94 LUT4 1000 abCD + 95 LUT2 8 AB + 96 LUT4 4000 aBCD + 97 LUT2 8 AB + 98 LUT4 0100 abcD + 99 LUT2 8 AB + 100 LUT3 40 aBC + 101 LUT4 0001 abcd + 102 LUT4 8000 ABCD + 103 LUT2 8 AB + 104 LUT4 4000 aBCD + 105 LUT2 8 AB + 106 LUT4 4000 aBCD + 107 LUT2 8 AB + 108 LUT4 1000 abCD + 109 LUT2 8 AB + 110 LUT4 1000 abCD + 111 LUT2 8 AB + 112 LUT2 8 AB + 113 LUT2 8 AB + 114 LUT2 8 AB + 115 LUT2 8 AB + 116 LUT4 0100 abcD + 117 LUT2 8 AB + 118 LUT2 8 AB + 119 LUT2 8 AB + 120 LUT4 0100 abcD + 121 LUT2 8 AB + 122 LUT2 8 AB + 123 LUT2 8 AB + 124 LUT4 0001 abcd + 125 LUT2 8 AB + 126 LUT2 8 AB + 127 LUT2 8 AB + 128 LUT2 8 AB + 129 LUT2 8 AB + 130 LUT2 8 AB + 131 LUT2 8 AB + 132 LUT2 8 AB + 133 LUT2 8 AB + 134 LUT3 80 ABC + 135 LUT4 4000 aBCD + 136 LUT2 8 AB + 137 LUT2 8 AB + 138 LUT2 8 AB + 139 LUT2 8 AB + 140 LUT2 8 AB + 141 LUT2 8 AB + 142 LUT2 8 AB + 143 LUT2 8 AB + 144 LUT2 8 AB + 145 LUT2 8 AB + 146 LUT2 8 AB + 147 LUT2 8 AB + 148 LUT2 8 AB + 149 LUT2 8 AB + 150 LUT2 8 AB + 151 LUT2 8 AB + 152 LUT3 80 ABC + 153 LUT4 4000 aBCD + 154 LUT2 8 AB + 155 LUT2 8 AB + 156 LUT2 8 AB + 157 LUT2 8 AB + 158 LUT2 8 AB + 159 LUT2 8 AB + 160 LUT2 8 AB + 161 LUT2 8 AB + 162 LUT2 8 AB + 163 LUT2 8 AB + 164 LUT2 8 AB + 165 LUT2 8 AB + 166 LUT2 8 AB + 167 LUT2 8 AB + 168 LUT2 8 AB + 169 LUT2 8 AB + 170 LUT3 80 ABC + 171 LUT4 1000 abCD + 172 LUT2 8 AB + 173 LUT2 8 AB + 174 LUT2 8 AB + 175 LUT2 8 AB + 176 LUT2 8 AB + 177 LUT2 8 AB + 178 LUT2 8 AB + 179 LUT2 8 AB + 180 LUT2 8 AB + 181 LUT2 8 AB + 182 LUT2 8 AB + 183 LUT2 8 AB + 184 LUT2 8 AB + 185 LUT2 8 AB + 186 LUT2 8 AB + 187 LUT2 8 AB + 188 LUT3 40 aBC + 189 LUT2 8 AB + 190 LUT2 8 AB + 191 LUT2 8 AB + 192 LUT2 8 AB + 193 LUT2 8 AB + 194 LUT2 8 AB + 195 LUT2 8 AB + 196 LUT2 8 AB + 197 LUT2 8 AB + 198 LUT2 8 AB + 199 LUT2 8 AB + 200 LUT2 8 AB + 201 LUT2 8 AB + 202 LUT2 8 AB + 203 LUT2 8 AB + 204 LUT2 8 AB + 205 LUT3 40 aBC + 206 LUT2 8 AB + 207 LUT2 8 AB + 208 LUT2 8 AB + 209 LUT2 8 AB + 210 LUT2 8 AB + 211 LUT2 8 AB + 212 LUT2 8 AB + 213 LUT2 8 AB + 214 LUT2 8 AB + 215 LUT2 8 AB + 216 LUT2 8 AB + 217 LUT2 8 AB + 218 LUT2 8 AB + 219 LUT2 8 AB + 220 LUT2 8 AB + 221 LUT2 8 AB + 222 LUT3 40 aBC + 223 LUT2 8 AB + 224 LUT2 8 AB + 225 LUT2 8 AB + 226 LUT2 8 AB + 227 LUT2 8 AB + 228 LUT2 8 AB + 229 LUT2 8 AB + 230 LUT2 8 AB + 231 LUT2 8 AB + 232 LUT2 8 AB + 233 LUT2 8 AB + 234 LUT2 8 AB + 235 LUT2 8 AB + 236 LUT2 8 AB + 237 LUT2 8 AB + 238 LUT2 8 AB + 239 LUT3 40 aBC + 240 LUT2 8 AB + 241 LUT2 8 AB + 242 LUT2 8 AB + 243 LUT2 8 AB + 244 LUT2 8 AB + 245 LUT2 8 AB + 246 LUT2 8 AB + 247 LUT2 8 AB + 248 LUT2 8 AB + 249 LUT2 8 AB + 250 LUT2 8 AB + 251 LUT2 8 AB + 252 LUT2 8 AB + 253 LUT2 8 AB + 254 LUT2 8 AB + 255 LUT2 8 AB + 256 LUT3 40 aBC + 257 LUT2 8 AB + 258 LUT2 8 AB + 259 LUT2 8 AB + 260 LUT2 8 AB + 261 LUT2 8 AB + 262 LUT2 8 AB + 263 LUT2 8 AB + 264 LUT2 8 AB + 265 LUT2 8 AB + 266 LUT2 8 AB + 267 LUT2 8 AB + 268 LUT2 8 AB + 269 LUT2 8 AB + 270 LUT2 8 AB + 271 LUT2 8 AB + 272 LUT1 1 a deleted + 273 LUT1 1 a deleted + 274 LUT1 1 a deleted + 275 LUT1 1 a deleted diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lutram_16x10.v b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lutram_16x10.v new file mode 100644 index 0000000000000000000000000000000000000000..096773f2240af13aed7d0bd6294674c385895329 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/lutram_16x10.v @@ -0,0 +1,25 @@ +module lutram_16x10 ( + clk, + wdat, + addr, + we, + rdat +); + reg _sv2v_0; + input wire clk; + input wire [9:0] wdat; + input wire [3:0] addr; + input wire we; + output reg [9:0] rdat; + reg [9:0] dist_mem [0:15]; + always @(*) begin : _read_block + if (_sv2v_0) + ; + rdat = dist_mem[addr]; + end + always @(posedge clk) begin : _write_block + if (we == 1'b1) + dist_mem[addr] <= wdat; + end + initial _sv2v_0 = 0; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/net/top_synth.v b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/net/top_synth.v new file mode 100644 index 0000000000000000000000000000000000000000..a778ef7192624dde9c37f14bac6a87ad1c440b8f --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/net/top_synth.v @@ -0,0 +1,28067 @@ +/* Generated by Yosys 0.42+10 (git sha1 7f89a45ad, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os) */ + +module top(clk, addr, we, wdat, rdat); + wire _0000_; + wire _0001_; + wire _0002_; + wire _0003_; + wire _0004_; + wire _0005_; + wire _0006_; + wire _0007_; + wire _0008_; + wire _0009_; + wire _0010_; + wire _0011_; + wire _0012_; + wire _0013_; + wire _0014_; + wire _0015_; + wire _0016_; + wire _0017_; + wire _0018_; + wire _0019_; + wire _0020_; + wire _0021_; + wire _0022_; + wire _0023_; + wire _0024_; + wire _0025_; + wire _0026_; + wire _0027_; + wire _0028_; + wire _0029_; + wire _0030_; + wire _0031_; + wire _0032_; + wire _0033_; + wire _0034_; + wire _0035_; + wire _0036_; + wire _0037_; + wire _0038_; + wire _0039_; + wire _0040_; + wire _0041_; + wire _0042_; + wire _0043_; + wire _0044_; + wire _0045_; + wire _0046_; + wire _0047_; + wire _0048_; + wire _0049_; + wire _0050_; + wire _0051_; + wire _0052_; + wire _0053_; + wire _0054_; + wire _0055_; + wire _0056_; + wire _0057_; + wire _0058_; + wire _0059_; + wire _0060_; + wire _0061_; + wire _0062_; + wire _0063_; + wire _0064_; + wire _0065_; + wire _0066_; + wire _0067_; + wire _0068_; + wire _0069_; + wire _0070_; + wire _0071_; + wire _0072_; + wire _0073_; + wire _0074_; + wire _0075_; + wire _0076_; + wire _0077_; + wire _0078_; + wire _0079_; + wire _0080_; + wire _0081_; + wire _0082_; + wire _0083_; + wire _0084_; + wire _0085_; + wire _0086_; + wire _0087_; + wire _0088_; + wire _0089_; + wire _0090_; + wire _0091_; + wire _0092_; + wire _0093_; + wire _0094_; + wire _0095_; + wire _0096_; + wire _0097_; + wire _0098_; + wire _0099_; + wire _0100_; + wire _0101_; + wire _0102_; + wire _0103_; + wire _0104_; + wire _0105_; + wire _0106_; + wire _0107_; + wire _0108_; + wire _0109_; + wire _0110_; + wire _0111_; + wire _0112_; + wire _0113_; + wire _0114_; + wire _0115_; + wire _0116_; + wire _0117_; + wire _0118_; + wire _0119_; + wire _0120_; + wire _0121_; + wire _0122_; + wire _0123_; + wire _0124_; + wire _0125_; + wire _0126_; + wire _0127_; + wire _0128_; + wire _0129_; + wire _0130_; + wire _0131_; + wire _0132_; + wire _0133_; + wire _0134_; + wire _0135_; + wire _0136_; + wire _0137_; + wire _0138_; + wire _0139_; + wire _0140_; + wire _0141_; + wire _0142_; + wire _0143_; + wire _0144_; + wire _0145_; + wire _0146_; + wire _0147_; + wire _0148_; + wire _0149_; + wire _0150_; + wire _0151_; + wire _0152_; + wire _0153_; + wire _0154_; + wire _0155_; + wire _0156_; + wire _0157_; + wire _0158_; + wire _0159_; + wire _0160_; + wire _0161_; + wire _0162_; + wire _0163_; + wire _0164_; + wire _0165_; + wire _0166_; + wire _0167_; + wire _0168_; + wire _0169_; + wire [4:0] _0170_; + wire [4:0] _0171_; + wire [4:0] _0172_; + wire [4:0] _0173_; + wire _0174_; + wire [9:0] _0175_; + wire [9:0] _0176_; + wire [9:0] _0177_; + wire [9:0] _0178_; + wire [9:0] _0179_; + wire [9:0] _0180_; + wire [9:0] _0181_; + wire [9:0] _0182_; + wire [9:0] _0183_; + wire [9:0] _0184_; + wire [9:0] _0185_; + wire [9:0] _0186_; + wire [9:0] _0187_; + wire [9:0] _0188_; + wire [9:0] _0189_; + wire [9:0] _0190_; + wire [9:0] _0191_; + wire [9:0] _0192_; + wire [9:0] _0193_; + wire [9:0] _0194_; + wire [9:0] _0195_; + wire [9:0] _0196_; + wire [9:0] _0197_; + wire [9:0] _0198_; + wire [9:0] _0199_; + wire [9:0] _0200_; + wire [9:0] _0201_; + wire [9:0] _0202_; + wire [9:0] _0203_; + wire [9:0] _0204_; + wire [9:0] _0205_; + wire [9:0] _0206_; + wire [9:0] _0207_; + wire [9:0] _0208_; + wire [9:0] _0209_; + wire [9:0] _0210_; + wire [9:0] _0211_; + wire [9:0] _0212_; + wire [9:0] _0213_; + wire [9:0] _0214_; + wire [3:0] _0215_; + wire [3:0] _0216_; + wire [1:0] _0217_; + wire [3:0] _0218_; + wire [3:0] _0219_; + wire [3:0] _0220_; + wire [3:0] _0221_; + wire [3:0] _0222_; + wire [3:0] _0223_; + wire [3:0] _0224_; + wire [3:0] _0225_; + wire [3:0] _0226_; + wire [3:0] _0227_; + wire [3:0] _0228_; + wire [2:0] _0229_; + wire [1:0] _0230_; + wire [1:0] _0231_; + wire [1:0] _0232_; + wire [2:0] _0233_; + wire [1:0] _0234_; + wire [1:0] _0235_; + wire [1:0] _0236_; + wire [1:0] _0237_; + wire [2:0] _0238_; + wire [1:0] _0239_; + wire [1:0] _0240_; + wire [2:0] _0241_; + wire [1:0] _0242_; + wire [2:0] _0243_; + wire [1:0] _0244_; + wire [1:0] _0245_; + wire [1:0] _0246_; + wire [1:0] _0247_; + wire [1:0] _0248_; + wire [1:0] _0249_; + wire [1:0] _0250_; + wire [1:0] _0251_; + wire [1:0] _0252_; + wire [3:0] _0253_; + wire [3:0] _0254_; + wire [3:0] _0255_; + wire [3:0] _0256_; + wire [3:0] _0257_; + wire [3:0] _0258_; + wire [3:0] _0259_; + wire [3:0] _0260_; + wire [3:0] _0261_; + wire [3:0] _0262_; + wire [3:0] _0263_; + wire [3:0] _0264_; + wire [3:0] _0265_; + wire [3:0] _0266_; + wire [3:0] _0267_; + wire [3:0] _0268_; + input [7:0] addr; + wire [7:0] addr; + input clk; + wire clk; + wire [3:0] \genblk1[0].u_lut.addr ; + wire \genblk1[0].u_lut.clk ; + wire [9:0] \genblk1[0].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[0].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[0].u_lut.rdat ; + wire [9:0] \genblk1[0].u_lut.wdat ; + wire [9:0] \genblk1[1].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[1].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[1].u_lut.rdat ; + wire [9:0] \genblk1[2].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[2].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[2].u_lut.rdat ; + wire [9:0] \genblk1[3].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[3].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[3].u_lut.rdat ; + wire [9:0] \genblk1[4].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[4].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[4].u_lut.rdat ; + wire [9:0] \genblk1[5].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[5].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[5].u_lut.rdat ; + wire [9:0] \genblk1[6].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[6].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[6].u_lut.rdat ; + wire [9:0] \genblk1[7].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[7].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[7].u_lut.rdat ; + wire [9:0] \genblk1[8].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[8].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[8].u_lut.rdat ; + wire [9:0] \genblk1[9].u_lut.dist_mem[0] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[10] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[11] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[12] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[13] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[14] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[15] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[1] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[2] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[3] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[4] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[5] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[6] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[7] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[8] ; + wire [9:0] \genblk1[9].u_lut.dist_mem[9] ; + wire [9:0] \genblk1[9].u_lut.rdat ; + output [9:0] rdat; + wire [9:0] rdat; + input [9:0] wdat; + wire [9:0] wdat; + input we; + wire we; + CC_LUT4 #( + .INIT(16'h8fff) + ) _0269_ ( + .I0(\genblk1[4].u_lut.rdat [0]), + .I1(_0218_[2]), + .I2(_0254_[2]), + .I3(_0254_[3]), + .O(_0000_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0270_ ( + .I0(_0253_[0]), + .I1(_0253_[1]), + .I2(_0253_[2]), + .I3(_0253_[3]), + .O(_0254_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0271_ ( + .I0(_0216_[0]), + .I1(\genblk1[3].u_lut.rdat [0]), + .I2(_0216_[2]), + .I3(\genblk1[8].u_lut.rdat [0]), + .O(_0253_[2]) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0272_ ( + .I0(_0215_[0]), + .I1(_0215_[1]), + .I2(_0215_[2]), + .I3(_0215_[3]), + .O(_0216_[2]) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0273_ ( + .I0(_0215_[3]), + .I1(_0215_[2]), + .I2(_0215_[1]), + .I3(_0215_[0]), + .O(_0216_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0274_ ( + .I0(\genblk1[5].u_lut.rdat [0]), + .I1(_0223_[1]), + .I2(_0218_[1]), + .I3(\genblk1[7].u_lut.rdat [0]), + .O(_0253_[1]) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0275_ ( + .I0(_0215_[3]), + .I1(_0215_[0]), + .I2(_0215_[1]), + .I3(_0215_[2]), + .O(_0218_[1]) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0276_ ( + .I0(_0215_[3]), + .I1(_0215_[1]), + .I2(_0215_[0]), + .I3(_0215_[2]), + .O(_0223_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0277_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [0]), + .O(_0253_[0]) + ); + CC_LUT4 #( + .INIT(16'h03fe) + ) _0278_ ( + .I0(_0215_[0]), + .I1(_0215_[1]), + .I2(_0215_[2]), + .I3(_0215_[3]), + .O(_0217_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0279_ ( + .I0(_0219_[1]), + .I1(\genblk1[2].u_lut.rdat [0]), + .I2(_0224_[2]), + .I3(\genblk1[9].u_lut.rdat [0]), + .O(_0253_[3]) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0280_ ( + .I0(_0215_[1]), + .I1(_0215_[2]), + .I2(_0215_[3]), + .I3(_0215_[0]), + .O(_0224_[2]) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0281_ ( + .I0(_0215_[3]), + .I1(_0215_[0]), + .I2(_0215_[2]), + .I3(_0215_[1]), + .O(_0219_[1]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0282_ ( + .I0(\genblk1[1].u_lut.rdat [0]), + .I1(_0222_[1]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [0]), + .O(_0254_[3]) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0283_ ( + .I0(_0215_[3]), + .I1(_0215_[0]), + .I2(_0215_[1]), + .I3(_0215_[2]), + .O(_0220_[2]) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0284_ ( + .I0(_0215_[3]), + .I1(_0215_[1]), + .I2(_0215_[2]), + .I3(_0215_[0]), + .O(_0222_[1]) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0285_ ( + .I0(_0215_[3]), + .I1(_0215_[0]), + .I2(_0215_[1]), + .I3(_0215_[2]), + .O(_0218_[2]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0286_ ( + .I0(\genblk1[1].u_lut.rdat [1]), + .I1(_0222_[1]), + .I2(_0256_[2]), + .I3(_0256_[3]), + .O(_0001_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0287_ ( + .I0(_0255_[0]), + .I1(_0255_[1]), + .I2(_0255_[2]), + .I3(_0255_[3]), + .O(_0256_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0288_ ( + .I0(\genblk1[2].u_lut.rdat [1]), + .I1(_0219_[1]), + .I2(_0216_[0]), + .I3(\genblk1[3].u_lut.rdat [1]), + .O(_0255_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0289_ ( + .I0(\genblk1[7].u_lut.rdat [1]), + .I1(_0218_[1]), + .I2(_0218_[2]), + .I3(\genblk1[4].u_lut.rdat [1]), + .O(_0255_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0290_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [1]), + .O(_0255_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0291_ ( + .I0(\genblk1[8].u_lut.rdat [1]), + .I1(_0216_[2]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [1]), + .O(_0255_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0292_ ( + .I0(_0224_[2]), + .I1(\genblk1[9].u_lut.rdat [1]), + .I2(_0223_[1]), + .I3(\genblk1[5].u_lut.rdat [1]), + .O(_0256_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0293_ ( + .I0(\genblk1[4].u_lut.rdat [2]), + .I1(_0218_[2]), + .I2(_0258_[2]), + .I3(_0258_[3]), + .O(_0002_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0294_ ( + .I0(_0257_[0]), + .I1(_0257_[1]), + .I2(_0257_[2]), + .I3(_0257_[3]), + .O(_0258_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0295_ ( + .I0(_0216_[0]), + .I1(\genblk1[3].u_lut.rdat [2]), + .I2(_0216_[2]), + .I3(\genblk1[8].u_lut.rdat [2]), + .O(_0257_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0296_ ( + .I0(\genblk1[5].u_lut.rdat [2]), + .I1(_0223_[1]), + .I2(_0218_[1]), + .I3(\genblk1[7].u_lut.rdat [2]), + .O(_0257_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0297_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [2]), + .O(_0257_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0298_ ( + .I0(_0219_[1]), + .I1(\genblk1[2].u_lut.rdat [2]), + .I2(_0224_[2]), + .I3(\genblk1[9].u_lut.rdat [2]), + .O(_0257_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0299_ ( + .I0(\genblk1[1].u_lut.rdat [2]), + .I1(_0222_[1]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [2]), + .O(_0258_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0300_ ( + .I0(\genblk1[1].u_lut.rdat [3]), + .I1(_0222_[1]), + .I2(_0261_[2]), + .I3(_0261_[3]), + .O(_0003_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0301_ ( + .I0(_0221_[0]), + .I1(_0221_[1]), + .I2(_0221_[2]), + .I3(_0221_[3]), + .O(_0261_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0302_ ( + .I0(\genblk1[2].u_lut.rdat [3]), + .I1(_0219_[1]), + .I2(_0216_[0]), + .I3(\genblk1[3].u_lut.rdat [3]), + .O(_0221_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0303_ ( + .I0(\genblk1[7].u_lut.rdat [3]), + .I1(_0218_[1]), + .I2(_0218_[2]), + .I3(\genblk1[4].u_lut.rdat [3]), + .O(_0221_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0304_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [3]), + .O(_0221_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0305_ ( + .I0(\genblk1[8].u_lut.rdat [3]), + .I1(_0216_[2]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [3]), + .O(_0221_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0306_ ( + .I0(_0224_[2]), + .I1(\genblk1[9].u_lut.rdat [3]), + .I2(_0223_[1]), + .I3(\genblk1[5].u_lut.rdat [3]), + .O(_0261_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0307_ ( + .I0(\genblk1[4].u_lut.rdat [4]), + .I1(_0218_[2]), + .I2(_0226_[2]), + .I3(_0226_[3]), + .O(_0004_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0308_ ( + .I0(_0225_[0]), + .I1(_0225_[1]), + .I2(_0225_[2]), + .I3(_0225_[3]), + .O(_0226_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0309_ ( + .I0(_0216_[0]), + .I1(\genblk1[3].u_lut.rdat [4]), + .I2(_0216_[2]), + .I3(\genblk1[8].u_lut.rdat [4]), + .O(_0225_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0310_ ( + .I0(\genblk1[5].u_lut.rdat [4]), + .I1(_0223_[1]), + .I2(_0218_[1]), + .I3(\genblk1[7].u_lut.rdat [4]), + .O(_0225_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0311_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [4]), + .O(_0225_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0312_ ( + .I0(_0219_[1]), + .I1(\genblk1[2].u_lut.rdat [4]), + .I2(_0224_[2]), + .I3(\genblk1[9].u_lut.rdat [4]), + .O(_0225_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0313_ ( + .I0(\genblk1[1].u_lut.rdat [4]), + .I1(_0222_[1]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [4]), + .O(_0226_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0314_ ( + .I0(\genblk1[5].u_lut.rdat [5]), + .I1(_0223_[1]), + .I2(_0260_[2]), + .I3(_0260_[3]), + .O(_0005_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0315_ ( + .I0(_0259_[0]), + .I1(_0259_[1]), + .I2(_0259_[2]), + .I3(_0259_[3]), + .O(_0260_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0316_ ( + .I0(_0216_[0]), + .I1(\genblk1[3].u_lut.rdat [5]), + .I2(_0216_[2]), + .I3(\genblk1[8].u_lut.rdat [5]), + .O(_0259_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0317_ ( + .I0(\genblk1[7].u_lut.rdat [5]), + .I1(_0218_[1]), + .I2(_0218_[2]), + .I3(\genblk1[4].u_lut.rdat [5]), + .O(_0259_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0318_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [5]), + .O(_0259_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0319_ ( + .I0(_0219_[1]), + .I1(\genblk1[2].u_lut.rdat [5]), + .I2(_0224_[2]), + .I3(\genblk1[9].u_lut.rdat [5]), + .O(_0259_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0320_ ( + .I0(\genblk1[1].u_lut.rdat [5]), + .I1(_0222_[1]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [5]), + .O(_0260_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0321_ ( + .I0(\genblk1[5].u_lut.rdat [6]), + .I1(_0223_[1]), + .I2(_0263_[2]), + .I3(_0263_[3]), + .O(_0006_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0322_ ( + .I0(_0262_[0]), + .I1(_0262_[1]), + .I2(_0262_[2]), + .I3(_0262_[3]), + .O(_0263_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0323_ ( + .I0(_0216_[0]), + .I1(\genblk1[3].u_lut.rdat [6]), + .I2(_0216_[2]), + .I3(\genblk1[8].u_lut.rdat [6]), + .O(_0262_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0324_ ( + .I0(\genblk1[7].u_lut.rdat [6]), + .I1(_0218_[1]), + .I2(_0218_[2]), + .I3(\genblk1[4].u_lut.rdat [6]), + .O(_0262_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0325_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [6]), + .O(_0262_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0326_ ( + .I0(_0219_[1]), + .I1(\genblk1[2].u_lut.rdat [6]), + .I2(_0224_[2]), + .I3(\genblk1[9].u_lut.rdat [6]), + .O(_0262_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0327_ ( + .I0(\genblk1[1].u_lut.rdat [6]), + .I1(_0222_[1]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [6]), + .O(_0263_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0328_ ( + .I0(\genblk1[5].u_lut.rdat [7]), + .I1(_0223_[1]), + .I2(_0265_[2]), + .I3(_0265_[3]), + .O(_0007_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0329_ ( + .I0(_0264_[0]), + .I1(_0264_[1]), + .I2(_0264_[2]), + .I3(_0264_[3]), + .O(_0265_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0330_ ( + .I0(_0216_[0]), + .I1(\genblk1[3].u_lut.rdat [7]), + .I2(_0216_[2]), + .I3(\genblk1[8].u_lut.rdat [7]), + .O(_0264_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0331_ ( + .I0(\genblk1[7].u_lut.rdat [7]), + .I1(_0218_[1]), + .I2(_0218_[2]), + .I3(\genblk1[4].u_lut.rdat [7]), + .O(_0264_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0332_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [7]), + .O(_0264_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0333_ ( + .I0(_0219_[1]), + .I1(\genblk1[2].u_lut.rdat [7]), + .I2(_0224_[2]), + .I3(\genblk1[9].u_lut.rdat [7]), + .O(_0264_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0334_ ( + .I0(\genblk1[1].u_lut.rdat [7]), + .I1(_0222_[1]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [7]), + .O(_0265_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0335_ ( + .I0(\genblk1[4].u_lut.rdat [8]), + .I1(_0218_[2]), + .I2(_0267_[2]), + .I3(_0267_[3]), + .O(_0008_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0336_ ( + .I0(_0266_[0]), + .I1(_0266_[1]), + .I2(_0266_[2]), + .I3(_0266_[3]), + .O(_0267_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0337_ ( + .I0(_0216_[0]), + .I1(\genblk1[3].u_lut.rdat [8]), + .I2(_0216_[2]), + .I3(\genblk1[8].u_lut.rdat [8]), + .O(_0266_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0338_ ( + .I0(\genblk1[5].u_lut.rdat [8]), + .I1(_0223_[1]), + .I2(_0218_[1]), + .I3(\genblk1[7].u_lut.rdat [8]), + .O(_0266_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0339_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [8]), + .O(_0266_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0340_ ( + .I0(_0219_[1]), + .I1(\genblk1[2].u_lut.rdat [8]), + .I2(_0224_[2]), + .I3(\genblk1[9].u_lut.rdat [8]), + .O(_0266_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0341_ ( + .I0(\genblk1[1].u_lut.rdat [8]), + .I1(_0222_[1]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [8]), + .O(_0267_[3]) + ); + CC_LUT4 #( + .INIT(16'h8fff) + ) _0342_ ( + .I0(\genblk1[1].u_lut.rdat [9]), + .I1(_0222_[1]), + .I2(_0268_[2]), + .I3(_0268_[3]), + .O(_0009_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0343_ ( + .I0(_0227_[0]), + .I1(_0227_[1]), + .I2(_0227_[2]), + .I3(_0227_[3]), + .O(_0268_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0344_ ( + .I0(\genblk1[2].u_lut.rdat [9]), + .I1(_0219_[1]), + .I2(_0216_[0]), + .I3(\genblk1[3].u_lut.rdat [9]), + .O(_0227_[2]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0345_ ( + .I0(\genblk1[5].u_lut.rdat [9]), + .I1(_0223_[1]), + .I2(_0218_[1]), + .I3(\genblk1[7].u_lut.rdat [9]), + .O(_0227_[1]) + ); + CC_LUT2 #( + .INIT(4'h4) + ) _0346_ ( + .I0(_0217_[0]), + .I1(\genblk1[0].u_lut.rdat [9]), + .O(_0227_[0]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0347_ ( + .I0(\genblk1[8].u_lut.rdat [9]), + .I1(_0216_[2]), + .I2(_0220_[2]), + .I3(\genblk1[6].u_lut.rdat [9]), + .O(_0227_[3]) + ); + CC_LUT4 #( + .INIT(16'h0777) + ) _0348_ ( + .I0(\genblk1[9].u_lut.rdat [9]), + .I1(_0224_[2]), + .I2(_0218_[2]), + .I3(\genblk1[4].u_lut.rdat [9]), + .O(_0268_[3]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0349_ ( + .I0(_0230_[0]), + .I1(_0230_[1]), + .O(_0041_) + ); + CC_LUT3 #( + .INIT(8'h80) + ) _0350_ ( + .I0(_0229_[0]), + .I1(_0173_[2]), + .I2(_0173_[3]), + .O(_0230_[0]) + ); + CC_LUT4 #( + .INIT(16'h8000) + ) _0351_ ( + .I0(_0228_[0]), + .I1(_0173_[4]), + .I2(_0173_[0]), + .I3(_0173_[1]), + .O(_0229_[0]) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0352_ ( + .I0(\genblk1[0].u_lut.addr [1]), + .I1(\genblk1[0].u_lut.addr [2]), + .I2(\genblk1[0].u_lut.addr [0]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0230_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0353_ ( + .I0(_0230_[0]), + .I1(_0247_[1]), + .O(_0040_) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0354_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0247_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0355_ ( + .I0(_0230_[0]), + .I1(_0231_[1]), + .O(_0039_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0356_ ( + .I0(\genblk1[0].u_lut.addr [3]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [0]), + .O(_0231_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0357_ ( + .I0(_0230_[0]), + .I1(_0252_[1]), + .O(_0037_) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0358_ ( + .I0(\genblk1[0].u_lut.addr [1]), + .I1(\genblk1[0].u_lut.addr [3]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [0]), + .O(_0252_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0359_ ( + .I0(_0230_[0]), + .I1(_0239_[1]), + .O(_0038_) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0360_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [3]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [1]), + .O(_0239_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0361_ ( + .I0(_0230_[0]), + .I1(_0232_[1]), + .O(_0027_) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0362_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [2]), + .I2(\genblk1[0].u_lut.addr [1]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0232_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0363_ ( + .I0(_0230_[0]), + .I1(_0236_[1]), + .O(_0028_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0364_ ( + .I0(\genblk1[0].u_lut.addr [2]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [0]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0236_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0365_ ( + .I0(_0230_[0]), + .I1(_0250_[1]), + .O(_0036_) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0366_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [3]), + .I3(\genblk1[0].u_lut.addr [2]), + .O(_0250_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0367_ ( + .I0(_0234_[0]), + .I1(_0234_[1]), + .O(_0016_) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0368_ ( + .I0(_0173_[4]), + .I1(_0228_[0]), + .I2(_0233_[2]), + .O(_0234_[0]) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0369_ ( + .I0(_0173_[0]), + .I1(_0173_[1]), + .I2(_0173_[2]), + .I3(_0173_[3]), + .O(_0233_[2]) + ); + CC_LUT4 #( + .INIT(16'h8000) + ) _0370_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0234_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0371_ ( + .I0(_0234_[0]), + .I1(_0248_[1]), + .O(_0015_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0372_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0248_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0373_ ( + .I0(_0234_[0]), + .I1(_0235_[1]), + .O(_0014_) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0374_ ( + .I0(\genblk1[0].u_lut.addr [1]), + .I1(\genblk1[0].u_lut.addr [0]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0235_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0375_ ( + .I0(_0230_[0]), + .I1(_0249_[1]), + .O(_0035_) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0376_ ( + .I0(\genblk1[0].u_lut.addr [2]), + .I1(\genblk1[0].u_lut.addr [3]), + .I2(\genblk1[0].u_lut.addr [0]), + .I3(\genblk1[0].u_lut.addr [1]), + .O(_0249_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0377_ ( + .I0(_0234_[0]), + .I1(_0240_[1]), + .O(_0013_) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0378_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0240_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0379_ ( + .I0(_0234_[0]), + .I1(_0236_[1]), + .O(_0012_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0380_ ( + .I0(_0234_[0]), + .I1(_0232_[1]), + .O(_0011_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0381_ ( + .I0(_0234_[0]), + .I1(_0230_[1]), + .O(_0025_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0382_ ( + .I0(_0234_[0]), + .I1(_0247_[1]), + .O(_0024_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0383_ ( + .I0(_0230_[0]), + .I1(_0246_[1]), + .O(_0034_) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0384_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [2]), + .I2(\genblk1[0].u_lut.addr [3]), + .I3(\genblk1[0].u_lut.addr [1]), + .O(_0246_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0385_ ( + .I0(_0234_[0]), + .I1(_0231_[1]), + .O(_0023_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0386_ ( + .I0(_0234_[0]), + .I1(_0239_[1]), + .O(_0022_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0387_ ( + .I0(_0230_[0]), + .I1(_0245_[1]), + .O(_0033_) + ); + CC_LUT4 #( + .INIT(16'h0100) + ) _0388_ ( + .I0(\genblk1[0].u_lut.addr [1]), + .I1(\genblk1[0].u_lut.addr [2]), + .I2(\genblk1[0].u_lut.addr [3]), + .I3(\genblk1[0].u_lut.addr [0]), + .O(_0245_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0389_ ( + .I0(_0234_[0]), + .I1(_0252_[1]), + .O(_0021_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0390_ ( + .I0(_0234_[0]), + .I1(_0250_[1]), + .O(_0020_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0391_ ( + .I0(_0230_[0]), + .I1(_0237_[1]), + .O(_0026_) + ); + CC_LUT4 #( + .INIT(16'h0001) + ) _0392_ ( + .I0(\genblk1[0].u_lut.addr [0]), + .I1(\genblk1[0].u_lut.addr [1]), + .I2(\genblk1[0].u_lut.addr [2]), + .I3(\genblk1[0].u_lut.addr [3]), + .O(_0237_[1]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0393_ ( + .I0(_0234_[0]), + .I1(_0249_[1]), + .O(_0019_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0394_ ( + .I0(_0234_[0]), + .I1(_0246_[1]), + .O(_0018_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0395_ ( + .I0(_0234_[0]), + .I1(_0245_[1]), + .O(_0017_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0396_ ( + .I0(_0234_[0]), + .I1(_0237_[1]), + .O(_0010_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0397_ ( + .I0(_0230_[0]), + .I1(_0235_[1]), + .O(_0030_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0398_ ( + .I0(_0230_[0]), + .I1(_0240_[1]), + .O(_0029_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0399_ ( + .I0(_0230_[0]), + .I1(_0248_[1]), + .O(_0031_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0400_ ( + .I0(_0230_[0]), + .I1(_0234_[1]), + .O(_0032_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0401_ ( + .I0(_0239_[0]), + .I1(_0237_[1]), + .O(_0042_) + ); + CC_LUT3 #( + .INIT(8'h80) + ) _0402_ ( + .I0(_0238_[0]), + .I1(_0173_[2]), + .I2(_0173_[3]), + .O(_0239_[0]) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0403_ ( + .I0(_0173_[0]), + .I1(_0173_[4]), + .I2(_0228_[0]), + .I3(_0173_[1]), + .O(_0238_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0404_ ( + .I0(_0239_[0]), + .I1(_0245_[1]), + .O(_0049_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0405_ ( + .I0(_0239_[0]), + .I1(_0246_[1]), + .O(_0050_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0406_ ( + .I0(_0239_[0]), + .I1(_0249_[1]), + .O(_0051_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0407_ ( + .I0(_0239_[0]), + .I1(_0250_[1]), + .O(_0052_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0408_ ( + .I0(_0239_[0]), + .I1(_0252_[1]), + .O(_0053_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0409_ ( + .I0(_0239_[0]), + .I1(_0239_[1]), + .O(_0054_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0410_ ( + .I0(_0239_[0]), + .I1(_0231_[1]), + .O(_0055_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0411_ ( + .I0(_0239_[0]), + .I1(_0247_[1]), + .O(_0056_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0412_ ( + .I0(_0239_[0]), + .I1(_0230_[1]), + .O(_0057_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0413_ ( + .I0(_0239_[0]), + .I1(_0232_[1]), + .O(_0043_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0414_ ( + .I0(_0239_[0]), + .I1(_0236_[1]), + .O(_0044_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0415_ ( + .I0(_0239_[0]), + .I1(_0240_[1]), + .O(_0045_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0416_ ( + .I0(_0239_[0]), + .I1(_0235_[1]), + .O(_0046_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0417_ ( + .I0(_0239_[0]), + .I1(_0248_[1]), + .O(_0047_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0418_ ( + .I0(_0239_[0]), + .I1(_0234_[1]), + .O(_0048_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0419_ ( + .I0(_0242_[0]), + .I1(_0237_[1]), + .O(_0058_) + ); + CC_LUT3 #( + .INIT(8'h80) + ) _0420_ ( + .I0(_0241_[0]), + .I1(_0173_[2]), + .I2(_0173_[3]), + .O(_0242_[0]) + ); + CC_LUT4 #( + .INIT(16'h4000) + ) _0421_ ( + .I0(_0173_[1]), + .I1(_0173_[4]), + .I2(_0173_[0]), + .I3(_0228_[0]), + .O(_0241_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0422_ ( + .I0(_0242_[0]), + .I1(_0245_[1]), + .O(_0065_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0423_ ( + .I0(_0242_[0]), + .I1(_0246_[1]), + .O(_0066_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0424_ ( + .I0(_0242_[0]), + .I1(_0249_[1]), + .O(_0067_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0425_ ( + .I0(_0242_[0]), + .I1(_0250_[1]), + .O(_0068_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0426_ ( + .I0(_0242_[0]), + .I1(_0252_[1]), + .O(_0069_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0427_ ( + .I0(_0242_[0]), + .I1(_0239_[1]), + .O(_0070_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0428_ ( + .I0(_0242_[0]), + .I1(_0231_[1]), + .O(_0071_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0429_ ( + .I0(_0242_[0]), + .I1(_0247_[1]), + .O(_0072_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0430_ ( + .I0(_0242_[0]), + .I1(_0230_[1]), + .O(_0073_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0431_ ( + .I0(_0242_[0]), + .I1(_0232_[1]), + .O(_0059_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0432_ ( + .I0(_0242_[0]), + .I1(_0236_[1]), + .O(_0060_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0433_ ( + .I0(_0242_[0]), + .I1(_0240_[1]), + .O(_0061_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0434_ ( + .I0(_0242_[0]), + .I1(_0235_[1]), + .O(_0062_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0435_ ( + .I0(_0242_[0]), + .I1(_0248_[1]), + .O(_0063_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0436_ ( + .I0(_0242_[0]), + .I1(_0234_[1]), + .O(_0064_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0437_ ( + .I0(_0244_[0]), + .I1(_0237_[1]), + .O(_0074_) + ); + CC_LUT3 #( + .INIT(8'h80) + ) _0438_ ( + .I0(_0243_[0]), + .I1(_0173_[2]), + .I2(_0173_[3]), + .O(_0244_[0]) + ); + CC_LUT4 #( + .INIT(16'h1000) + ) _0439_ ( + .I0(_0173_[0]), + .I1(_0173_[1]), + .I2(_0228_[0]), + .I3(_0173_[4]), + .O(_0243_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0440_ ( + .I0(_0244_[0]), + .I1(_0245_[1]), + .O(_0081_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0441_ ( + .I0(_0244_[0]), + .I1(_0246_[1]), + .O(_0082_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0442_ ( + .I0(_0244_[0]), + .I1(_0249_[1]), + .O(_0083_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0443_ ( + .I0(_0244_[0]), + .I1(_0250_[1]), + .O(_0084_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0444_ ( + .I0(_0244_[0]), + .I1(_0252_[1]), + .O(_0085_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0445_ ( + .I0(_0244_[0]), + .I1(_0239_[1]), + .O(_0086_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0446_ ( + .I0(_0244_[0]), + .I1(_0231_[1]), + .O(_0087_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0447_ ( + .I0(_0244_[0]), + .I1(_0247_[1]), + .O(_0088_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0448_ ( + .I0(_0244_[0]), + .I1(_0230_[1]), + .O(_0089_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0449_ ( + .I0(_0244_[0]), + .I1(_0232_[1]), + .O(_0075_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0450_ ( + .I0(_0244_[0]), + .I1(_0236_[1]), + .O(_0076_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0451_ ( + .I0(_0244_[0]), + .I1(_0240_[1]), + .O(_0077_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0452_ ( + .I0(_0244_[0]), + .I1(_0235_[1]), + .O(_0078_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0453_ ( + .I0(_0244_[0]), + .I1(_0248_[1]), + .O(_0079_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0454_ ( + .I0(_0244_[0]), + .I1(_0234_[1]), + .O(_0080_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0455_ ( + .I0(_0245_[0]), + .I1(_0237_[1]), + .O(_0090_) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0456_ ( + .I0(_0173_[2]), + .I1(_0229_[0]), + .I2(_0173_[3]), + .O(_0245_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0457_ ( + .I0(_0245_[0]), + .I1(_0245_[1]), + .O(_0097_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0458_ ( + .I0(_0245_[0]), + .I1(_0246_[1]), + .O(_0098_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0459_ ( + .I0(_0245_[0]), + .I1(_0249_[1]), + .O(_0099_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0460_ ( + .I0(_0245_[0]), + .I1(_0250_[1]), + .O(_0100_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0461_ ( + .I0(_0245_[0]), + .I1(_0252_[1]), + .O(_0101_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0462_ ( + .I0(_0245_[0]), + .I1(_0239_[1]), + .O(_0102_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0463_ ( + .I0(_0245_[0]), + .I1(_0231_[1]), + .O(_0103_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0464_ ( + .I0(_0245_[0]), + .I1(_0247_[1]), + .O(_0104_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0465_ ( + .I0(_0245_[0]), + .I1(_0230_[1]), + .O(_0105_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0466_ ( + .I0(_0245_[0]), + .I1(_0232_[1]), + .O(_0091_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0467_ ( + .I0(_0245_[0]), + .I1(_0236_[1]), + .O(_0092_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0468_ ( + .I0(_0245_[0]), + .I1(_0240_[1]), + .O(_0093_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0469_ ( + .I0(_0245_[0]), + .I1(_0235_[1]), + .O(_0094_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0470_ ( + .I0(_0245_[0]), + .I1(_0248_[1]), + .O(_0095_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0471_ ( + .I0(_0245_[0]), + .I1(_0234_[1]), + .O(_0096_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0472_ ( + .I0(_0246_[0]), + .I1(_0237_[1]), + .O(_0106_) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0473_ ( + .I0(_0173_[2]), + .I1(_0238_[0]), + .I2(_0173_[3]), + .O(_0246_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0474_ ( + .I0(_0246_[0]), + .I1(_0245_[1]), + .O(_0113_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0475_ ( + .I0(_0246_[0]), + .I1(_0246_[1]), + .O(_0114_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0476_ ( + .I0(_0246_[0]), + .I1(_0249_[1]), + .O(_0115_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0477_ ( + .I0(_0246_[0]), + .I1(_0250_[1]), + .O(_0116_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0478_ ( + .I0(_0246_[0]), + .I1(_0252_[1]), + .O(_0117_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0479_ ( + .I0(_0246_[0]), + .I1(_0239_[1]), + .O(_0118_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0480_ ( + .I0(_0246_[0]), + .I1(_0231_[1]), + .O(_0119_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0481_ ( + .I0(_0246_[0]), + .I1(_0247_[1]), + .O(_0120_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0482_ ( + .I0(_0246_[0]), + .I1(_0230_[1]), + .O(_0121_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0483_ ( + .I0(_0246_[0]), + .I1(_0232_[1]), + .O(_0107_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0484_ ( + .I0(_0246_[0]), + .I1(_0236_[1]), + .O(_0108_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0485_ ( + .I0(_0246_[0]), + .I1(_0240_[1]), + .O(_0109_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0486_ ( + .I0(_0246_[0]), + .I1(_0235_[1]), + .O(_0110_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0487_ ( + .I0(_0246_[0]), + .I1(_0248_[1]), + .O(_0111_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0488_ ( + .I0(_0246_[0]), + .I1(_0234_[1]), + .O(_0112_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0489_ ( + .I0(_0249_[0]), + .I1(_0237_[1]), + .O(_0122_) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0490_ ( + .I0(_0173_[2]), + .I1(_0241_[0]), + .I2(_0173_[3]), + .O(_0249_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0491_ ( + .I0(_0249_[0]), + .I1(_0245_[1]), + .O(_0129_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0492_ ( + .I0(_0249_[0]), + .I1(_0246_[1]), + .O(_0130_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0493_ ( + .I0(_0249_[0]), + .I1(_0249_[1]), + .O(_0131_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0494_ ( + .I0(_0249_[0]), + .I1(_0250_[1]), + .O(_0132_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0495_ ( + .I0(_0249_[0]), + .I1(_0252_[1]), + .O(_0133_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0496_ ( + .I0(_0249_[0]), + .I1(_0239_[1]), + .O(_0134_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0497_ ( + .I0(_0249_[0]), + .I1(_0231_[1]), + .O(_0135_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0498_ ( + .I0(_0249_[0]), + .I1(_0247_[1]), + .O(_0136_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0499_ ( + .I0(_0249_[0]), + .I1(_0230_[1]), + .O(_0137_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0500_ ( + .I0(_0249_[0]), + .I1(_0232_[1]), + .O(_0123_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0501_ ( + .I0(_0249_[0]), + .I1(_0236_[1]), + .O(_0124_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0502_ ( + .I0(_0249_[0]), + .I1(_0240_[1]), + .O(_0125_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0503_ ( + .I0(_0249_[0]), + .I1(_0235_[1]), + .O(_0126_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0504_ ( + .I0(_0249_[0]), + .I1(_0248_[1]), + .O(_0127_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0505_ ( + .I0(_0249_[0]), + .I1(_0234_[1]), + .O(_0128_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0506_ ( + .I0(_0250_[0]), + .I1(_0237_[1]), + .O(_0138_) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0507_ ( + .I0(_0173_[2]), + .I1(_0243_[0]), + .I2(_0173_[3]), + .O(_0250_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0508_ ( + .I0(_0250_[0]), + .I1(_0245_[1]), + .O(_0145_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0509_ ( + .I0(_0250_[0]), + .I1(_0246_[1]), + .O(_0146_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0510_ ( + .I0(_0250_[0]), + .I1(_0249_[1]), + .O(_0147_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0511_ ( + .I0(_0250_[0]), + .I1(_0250_[1]), + .O(_0148_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0512_ ( + .I0(_0250_[0]), + .I1(_0252_[1]), + .O(_0149_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0513_ ( + .I0(_0250_[0]), + .I1(_0239_[1]), + .O(_0150_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0514_ ( + .I0(_0250_[0]), + .I1(_0231_[1]), + .O(_0151_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0515_ ( + .I0(_0250_[0]), + .I1(_0247_[1]), + .O(_0152_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0516_ ( + .I0(_0250_[0]), + .I1(_0230_[1]), + .O(_0153_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0517_ ( + .I0(_0250_[0]), + .I1(_0232_[1]), + .O(_0139_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0518_ ( + .I0(_0250_[0]), + .I1(_0236_[1]), + .O(_0140_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0519_ ( + .I0(_0250_[0]), + .I1(_0240_[1]), + .O(_0141_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0520_ ( + .I0(_0250_[0]), + .I1(_0235_[1]), + .O(_0142_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0521_ ( + .I0(_0250_[0]), + .I1(_0248_[1]), + .O(_0143_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0522_ ( + .I0(_0250_[0]), + .I1(_0234_[1]), + .O(_0144_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0523_ ( + .I0(_0251_[0]), + .I1(_0237_[1]), + .O(_0154_) + ); + CC_LUT3 #( + .INIT(8'h40) + ) _0524_ ( + .I0(_0173_[3]), + .I1(_0173_[2]), + .I2(_0229_[0]), + .O(_0251_[0]) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0525_ ( + .I0(_0251_[0]), + .I1(_0245_[1]), + .O(_0161_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0526_ ( + .I0(_0251_[0]), + .I1(_0246_[1]), + .O(_0162_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0527_ ( + .I0(_0251_[0]), + .I1(_0249_[1]), + .O(_0163_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0528_ ( + .I0(_0251_[0]), + .I1(_0250_[1]), + .O(_0164_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0529_ ( + .I0(_0251_[0]), + .I1(_0252_[1]), + .O(_0165_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0530_ ( + .I0(_0251_[0]), + .I1(_0239_[1]), + .O(_0166_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0531_ ( + .I0(_0251_[0]), + .I1(_0231_[1]), + .O(_0167_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0532_ ( + .I0(_0251_[0]), + .I1(_0247_[1]), + .O(_0168_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0533_ ( + .I0(_0251_[0]), + .I1(_0230_[1]), + .O(_0169_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0534_ ( + .I0(_0251_[0]), + .I1(_0232_[1]), + .O(_0155_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0535_ ( + .I0(_0251_[0]), + .I1(_0236_[1]), + .O(_0156_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0536_ ( + .I0(_0251_[0]), + .I1(_0240_[1]), + .O(_0157_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0537_ ( + .I0(_0251_[0]), + .I1(_0235_[1]), + .O(_0158_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0538_ ( + .I0(_0251_[0]), + .I1(_0248_[1]), + .O(_0159_) + ); + CC_LUT2 #( + .INIT(4'h8) + ) _0539_ ( + .I0(_0251_[0]), + .I1(_0234_[1]), + .O(_0160_) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _0540_ ( + .I0(_0215_[3]), + .O(_0170_[3]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _0541_ ( + .I0(_0215_[0]), + .O(_0170_[0]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _0542_ ( + .I0(_0215_[1]), + .O(_0170_[1]) + ); + CC_LUT1 #( + .INIT(2'h1) + ) _0543_ ( + .I0(_0215_[2]), + .O(_0170_[2]) + ); + CC_ADDF _0544_ ( + .A(1'h0), + .B(_0170_[0]), + .CI(1'h1), + .CO(_0171_[1]), + .S(_0173_[0]) + ); + CC_ADDF _0545_ ( + .A(1'h0), + .B(_0170_[1]), + .CI(_0171_[1]), + .CO(_0171_[2]), + .S(_0173_[1]) + ); + CC_ADDF _0546_ ( + .A(1'h0), + .B(_0170_[2]), + .CI(_0171_[2]), + .CO(_0171_[3]), + .S(_0173_[2]) + ); + CC_ADDF _0547_ ( + .A(1'h0), + .B(_0170_[3]), + .CI(_0171_[3]), + .CO(_0171_[4]), + .S(_0173_[3]) + ); + CC_ADDF _0548_ ( + .A(1'h0), + .B(1'h1), + .CI(_0171_[4]), + .CO(_0172_[4]), + .S(_0173_[4]) + ); + CC_BUFG _0549_ ( + .I(_0174_), + .O(\genblk1[0].u_lut.clk ) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0550_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0551_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0552_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0553_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0554_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0555_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0556_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0557_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0558_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0559_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0036_), + .Q(\genblk1[1].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0560_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0561_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0562_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0563_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0564_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0565_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0566_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0567_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0568_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0569_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0031_), + .Q(\genblk1[1].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0570_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0571_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0572_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0573_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0574_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0575_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0576_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0577_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0578_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0579_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0030_), + .Q(\genblk1[1].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0580_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0581_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0582_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0583_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0584_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0585_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0586_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0587_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0588_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0589_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0029_), + .Q(\genblk1[1].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0590_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0591_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0592_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0593_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0594_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0595_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0596_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0597_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0598_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0599_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0028_), + .Q(\genblk1[1].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0600_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0601_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0602_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0603_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0604_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0605_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0606_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0607_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0608_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0609_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0027_), + .Q(\genblk1[1].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0610_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0611_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0612_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0613_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0614_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0615_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0616_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0617_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0618_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0619_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0037_), + .Q(\genblk1[1].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0620_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0621_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0622_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0623_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0624_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0625_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0626_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0627_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0628_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0629_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0035_), + .Q(\genblk1[1].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0630_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0631_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0632_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0633_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0634_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0635_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0636_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0637_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0638_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0639_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0026_), + .Q(\genblk1[1].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0640_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0641_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0642_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0643_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0644_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0645_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0646_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0647_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0648_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0649_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0040_), + .Q(\genblk1[1].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0650_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0651_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0652_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0653_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0654_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0655_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0656_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0657_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0658_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0659_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0039_), + .Q(\genblk1[1].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0660_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0661_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0662_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0663_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0664_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0665_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0666_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0667_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0668_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0669_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0038_), + .Q(\genblk1[1].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0670_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0671_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0672_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0673_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0674_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0675_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0676_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0677_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0678_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0679_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0010_), + .Q(\genblk1[0].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0680_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0681_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0682_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0683_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0684_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0685_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0686_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0687_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0688_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0689_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0034_), + .Q(\genblk1[1].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0690_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0691_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0692_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0693_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0694_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0695_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0696_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0697_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0698_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0699_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0033_), + .Q(\genblk1[1].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0700_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0701_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0702_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0703_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0704_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0705_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0706_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0707_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0708_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0709_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0032_), + .Q(\genblk1[1].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0710_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0711_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0712_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0713_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0714_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0715_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0716_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0717_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0718_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0719_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0025_), + .Q(\genblk1[0].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0720_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0721_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0722_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0723_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0724_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0725_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0726_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0727_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0728_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0729_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0016_), + .Q(\genblk1[0].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0730_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0731_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0732_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0733_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0734_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0735_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0736_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0737_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0738_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0739_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0017_), + .Q(\genblk1[0].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0740_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0741_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0742_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0743_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0744_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0745_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0746_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0747_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0748_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0749_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0018_), + .Q(\genblk1[0].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0750_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0751_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0752_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0753_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0754_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0755_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0756_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0757_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0758_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0759_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0019_), + .Q(\genblk1[0].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0760_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0761_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0762_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0763_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0764_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0765_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0766_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0767_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0768_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0769_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0020_), + .Q(\genblk1[0].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0770_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0771_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0772_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0773_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0774_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0775_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0776_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0777_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0778_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0779_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0015_), + .Q(\genblk1[0].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0780_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0781_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0782_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0783_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0784_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0785_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0786_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0787_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0788_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0789_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0021_), + .Q(\genblk1[0].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0790_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0791_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0792_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0793_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0794_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0795_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0796_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0797_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0798_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0799_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0014_), + .Q(\genblk1[0].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0800_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0801_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0802_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0803_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0804_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0805_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0806_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0807_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0808_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0809_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0022_), + .Q(\genblk1[0].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0810_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0811_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0812_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0813_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0814_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0815_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0816_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0817_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0818_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0819_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0013_), + .Q(\genblk1[0].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0820_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0821_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0822_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0823_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0824_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0825_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0826_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0827_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0828_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0829_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0023_), + .Q(\genblk1[0].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0830_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0831_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0832_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0833_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0834_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0835_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0836_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0837_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0838_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0839_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0012_), + .Q(\genblk1[0].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0840_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0841_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0842_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0843_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0844_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0845_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0846_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0847_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0848_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0849_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0024_), + .Q(\genblk1[0].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0850_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0851_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0852_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0853_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0854_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0855_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0856_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0857_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0858_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0859_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0011_), + .Q(\genblk1[0].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0860_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0861_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0862_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0863_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0864_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0865_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0866_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0867_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0868_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0869_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0041_), + .Q(\genblk1[1].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0870_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0871_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0872_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0873_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0874_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0875_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0876_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0877_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0878_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0879_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0048_), + .Q(\genblk1[2].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0880_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0881_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0882_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0883_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0884_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0885_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0886_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0887_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0888_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0889_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0049_), + .Q(\genblk1[2].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0890_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0891_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0892_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0893_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0894_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0895_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0896_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0897_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0898_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0899_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0050_), + .Q(\genblk1[2].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0900_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0901_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0902_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0903_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0904_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0905_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0906_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0907_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0908_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0909_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0051_), + .Q(\genblk1[2].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0910_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0911_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0912_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0913_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0914_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0915_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0916_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0917_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0918_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0919_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0052_), + .Q(\genblk1[2].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0920_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0921_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0922_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0923_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0924_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0925_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0926_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0927_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0928_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0929_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0053_), + .Q(\genblk1[2].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0930_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0931_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0932_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0933_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0934_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0935_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0936_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0937_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0938_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0939_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0054_), + .Q(\genblk1[2].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0940_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0941_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0942_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0943_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0944_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0945_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0946_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0947_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0948_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0949_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0055_), + .Q(\genblk1[2].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0950_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0951_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0952_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0953_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0954_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0955_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0956_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0957_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0958_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0959_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0056_), + .Q(\genblk1[2].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0960_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0961_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0962_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0963_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0964_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0965_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0966_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0967_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0968_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0969_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0042_), + .Q(\genblk1[2].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0970_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0971_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0972_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0973_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0974_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0975_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0976_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0977_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0978_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0979_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0043_), + .Q(\genblk1[2].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0980_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0981_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0982_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0983_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0984_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0985_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0986_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0987_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0988_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0989_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0044_), + .Q(\genblk1[2].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0990_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0991_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0992_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0993_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0994_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0995_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0996_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0997_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0998_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _0999_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0045_), + .Q(\genblk1[2].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1000_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1001_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1002_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1003_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1004_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1005_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1006_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1007_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1008_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1009_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0046_), + .Q(\genblk1[2].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1010_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1011_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1012_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1013_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1014_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1015_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1016_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1017_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1018_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1019_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0047_), + .Q(\genblk1[2].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1020_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1021_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1022_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1023_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1024_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1025_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1026_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1027_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1028_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1029_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0057_), + .Q(\genblk1[2].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1030_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1031_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1032_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1033_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1034_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1035_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1036_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1037_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1038_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1039_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0064_), + .Q(\genblk1[3].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1040_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1041_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1042_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1043_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1044_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1045_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1046_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1047_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1048_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1049_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0065_), + .Q(\genblk1[3].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1050_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1051_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1052_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1053_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1054_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1055_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1056_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1057_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1058_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1059_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0066_), + .Q(\genblk1[3].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1060_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1061_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1062_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1063_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1064_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1065_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1066_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1067_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1068_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1069_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0067_), + .Q(\genblk1[3].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1070_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1071_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1072_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1073_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1074_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1075_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1076_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1077_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1078_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1079_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0068_), + .Q(\genblk1[3].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1080_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1081_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1082_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1083_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1084_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1085_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1086_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1087_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1088_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1089_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0069_), + .Q(\genblk1[3].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1090_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1091_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1092_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1093_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1094_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1095_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1096_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1097_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1098_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1099_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0070_), + .Q(\genblk1[3].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1100_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1101_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1102_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1103_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1104_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1105_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1106_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1107_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1108_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1109_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0071_), + .Q(\genblk1[3].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1110_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1111_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1112_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1113_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1114_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1115_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1116_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1117_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1118_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1119_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0072_), + .Q(\genblk1[3].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1120_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1121_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1122_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1123_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1124_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1125_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1126_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1127_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1128_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1129_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0058_), + .Q(\genblk1[3].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1130_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1131_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1132_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1133_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1134_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1135_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1136_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1137_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1138_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1139_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0059_), + .Q(\genblk1[3].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1140_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1141_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1142_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1143_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1144_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1145_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1146_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1147_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1148_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1149_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0060_), + .Q(\genblk1[3].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1150_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1151_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1152_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1153_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1154_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1155_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1156_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1157_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1158_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1159_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0061_), + .Q(\genblk1[3].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1160_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1161_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1162_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1163_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1164_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1165_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1166_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1167_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1168_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1169_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0062_), + .Q(\genblk1[3].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1170_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1171_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1172_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1173_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1174_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1175_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1176_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1177_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1178_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1179_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0063_), + .Q(\genblk1[3].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1180_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1181_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1182_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1183_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1184_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1185_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1186_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1187_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1188_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1189_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0073_), + .Q(\genblk1[3].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1190_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1191_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1192_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1193_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1194_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1195_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1196_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1197_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1198_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1199_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0080_), + .Q(\genblk1[4].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1200_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1201_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1202_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1203_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1204_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1205_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1206_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1207_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1208_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1209_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0081_), + .Q(\genblk1[4].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1210_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1211_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1212_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1213_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1214_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1215_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1216_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1217_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1218_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1219_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0082_), + .Q(\genblk1[4].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1220_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1221_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1222_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1223_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1224_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1225_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1226_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1227_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1228_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1229_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0083_), + .Q(\genblk1[4].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1230_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1231_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1232_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1233_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1234_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1235_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1236_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1237_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1238_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1239_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0084_), + .Q(\genblk1[4].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1240_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1241_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1242_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1243_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1244_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1245_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1246_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1247_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1248_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1249_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0085_), + .Q(\genblk1[4].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1250_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1251_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1252_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1253_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1254_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1255_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1256_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1257_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1258_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1259_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0086_), + .Q(\genblk1[4].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1260_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1261_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1262_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1263_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1264_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1265_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1266_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1267_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1268_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1269_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0087_), + .Q(\genblk1[4].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1270_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1271_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1272_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1273_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1274_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1275_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1276_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1277_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1278_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1279_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0088_), + .Q(\genblk1[4].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1280_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1281_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1282_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1283_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1284_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1285_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1286_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1287_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1288_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1289_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0074_), + .Q(\genblk1[4].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1290_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1291_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1292_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1293_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1294_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1295_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1296_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1297_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1298_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1299_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0075_), + .Q(\genblk1[4].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1300_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1301_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1302_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1303_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1304_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1305_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1306_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1307_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1308_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1309_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0076_), + .Q(\genblk1[4].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1310_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1311_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1312_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1313_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1314_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1315_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1316_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1317_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1318_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1319_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0077_), + .Q(\genblk1[4].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1320_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1321_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1322_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1323_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1324_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1325_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1326_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1327_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1328_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1329_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0078_), + .Q(\genblk1[4].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1330_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1331_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1332_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1333_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1334_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1335_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1336_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1337_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1338_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1339_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0079_), + .Q(\genblk1[4].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1340_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1341_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1342_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1343_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1344_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1345_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1346_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1347_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1348_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1349_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0089_), + .Q(\genblk1[4].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1350_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1351_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1352_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1353_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1354_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1355_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1356_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1357_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1358_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1359_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0096_), + .Q(\genblk1[5].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1360_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1361_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1362_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1363_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1364_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1365_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1366_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1367_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1368_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1369_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0097_), + .Q(\genblk1[5].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1370_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1371_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1372_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1373_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1374_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1375_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1376_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1377_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1378_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1379_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0098_), + .Q(\genblk1[5].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1380_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1381_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1382_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1383_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1384_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1385_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1386_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1387_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1388_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1389_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0099_), + .Q(\genblk1[5].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1390_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1391_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1392_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1393_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1394_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1395_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1396_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1397_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1398_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1399_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0100_), + .Q(\genblk1[5].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1400_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1401_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1402_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1403_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1404_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1405_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1406_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1407_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1408_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1409_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0101_), + .Q(\genblk1[5].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1410_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1411_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1412_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1413_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1414_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1415_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1416_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1417_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1418_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1419_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0102_), + .Q(\genblk1[5].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1420_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1421_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1422_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1423_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1424_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1425_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1426_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1427_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1428_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1429_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0103_), + .Q(\genblk1[5].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1430_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1431_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1432_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1433_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1434_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1435_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1436_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1437_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1438_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1439_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0104_), + .Q(\genblk1[5].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1440_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1441_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1442_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1443_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1444_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1445_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1446_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1447_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1448_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1449_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0090_), + .Q(\genblk1[5].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1450_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1451_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1452_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1453_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1454_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1455_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1456_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1457_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1458_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1459_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0091_), + .Q(\genblk1[5].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1460_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1461_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1462_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1463_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1464_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1465_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1466_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1467_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1468_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1469_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0092_), + .Q(\genblk1[5].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1470_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1471_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1472_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1473_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1474_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1475_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1476_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1477_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1478_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1479_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0093_), + .Q(\genblk1[5].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1480_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1481_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1482_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1483_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1484_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1485_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1486_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1487_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1488_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1489_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0094_), + .Q(\genblk1[5].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1490_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1491_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1492_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1493_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1494_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1495_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1496_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1497_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1498_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1499_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0095_), + .Q(\genblk1[5].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1500_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1501_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1502_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1503_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1504_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1505_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1506_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1507_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1508_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1509_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0105_), + .Q(\genblk1[5].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1510_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1511_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1512_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1513_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1514_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1515_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1516_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1517_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1518_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1519_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0112_), + .Q(\genblk1[6].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1520_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1521_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1522_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1523_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1524_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1525_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1526_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1527_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1528_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1529_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0113_), + .Q(\genblk1[6].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1530_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1531_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1532_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1533_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1534_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1535_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1536_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1537_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1538_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1539_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0114_), + .Q(\genblk1[6].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1540_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1541_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1542_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1543_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1544_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1545_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1546_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1547_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1548_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1549_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0115_), + .Q(\genblk1[6].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1550_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1551_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1552_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1553_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1554_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1555_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1556_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1557_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1558_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1559_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0116_), + .Q(\genblk1[6].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1560_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1561_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1562_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1563_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1564_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1565_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1566_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1567_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1568_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1569_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0117_), + .Q(\genblk1[6].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1570_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1571_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1572_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1573_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1574_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1575_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1576_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1577_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1578_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1579_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0118_), + .Q(\genblk1[6].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1580_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1581_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1582_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1583_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1584_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1585_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1586_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1587_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1588_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1589_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0119_), + .Q(\genblk1[6].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1590_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1591_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1592_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1593_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1594_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1595_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1596_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1597_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1598_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1599_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0120_), + .Q(\genblk1[6].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1600_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1601_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1602_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1603_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1604_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1605_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1606_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1607_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1608_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1609_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0106_), + .Q(\genblk1[6].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1610_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1611_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1612_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1613_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1614_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1615_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1616_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1617_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1618_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1619_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0107_), + .Q(\genblk1[6].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1620_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1621_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1622_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1623_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1624_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1625_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1626_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1627_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1628_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1629_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0108_), + .Q(\genblk1[6].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1630_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1631_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1632_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1633_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1634_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1635_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1636_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1637_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1638_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1639_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0109_), + .Q(\genblk1[6].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1640_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1641_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1642_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1643_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1644_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1645_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1646_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1647_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1648_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1649_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0110_), + .Q(\genblk1[6].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1650_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1651_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1652_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1653_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1654_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1655_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1656_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1657_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1658_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1659_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0111_), + .Q(\genblk1[6].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1660_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1661_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1662_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1663_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1664_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1665_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1666_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1667_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1668_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1669_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0121_), + .Q(\genblk1[6].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1670_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1671_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1672_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1673_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1674_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1675_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1676_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1677_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1678_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1679_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0128_), + .Q(\genblk1[7].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1680_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1681_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1682_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1683_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1684_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1685_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1686_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1687_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1688_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1689_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0129_), + .Q(\genblk1[7].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1690_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1691_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1692_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1693_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1694_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1695_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1696_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1697_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1698_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1699_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0130_), + .Q(\genblk1[7].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1700_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1701_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1702_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1703_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1704_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1705_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1706_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1707_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1708_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1709_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0131_), + .Q(\genblk1[7].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1710_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1711_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1712_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1713_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1714_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1715_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1716_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1717_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1718_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1719_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0132_), + .Q(\genblk1[7].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1720_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1721_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1722_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1723_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1724_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1725_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1726_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1727_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1728_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1729_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0133_), + .Q(\genblk1[7].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1730_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1731_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1732_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1733_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1734_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1735_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1736_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1737_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1738_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1739_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0134_), + .Q(\genblk1[7].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1740_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1741_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1742_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1743_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1744_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1745_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1746_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1747_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1748_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1749_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0135_), + .Q(\genblk1[7].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1750_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1751_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1752_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1753_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1754_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1755_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1756_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1757_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1758_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1759_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0136_), + .Q(\genblk1[7].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1760_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1761_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1762_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1763_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1764_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1765_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1766_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1767_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1768_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1769_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0122_), + .Q(\genblk1[7].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1770_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1771_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1772_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1773_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1774_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1775_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1776_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1777_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1778_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1779_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0123_), + .Q(\genblk1[7].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1780_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1781_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1782_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1783_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1784_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1785_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1786_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1787_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1788_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1789_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0124_), + .Q(\genblk1[7].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1790_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1791_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1792_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1793_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1794_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1795_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1796_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1797_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1798_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1799_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0125_), + .Q(\genblk1[7].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1800_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1801_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1802_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1803_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1804_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1805_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1806_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1807_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1808_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1809_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0126_), + .Q(\genblk1[7].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1810_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1811_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1812_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1813_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1814_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1815_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1816_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1817_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1818_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1819_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0127_), + .Q(\genblk1[7].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1820_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1821_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1822_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1823_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1824_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1825_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1826_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1827_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1828_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1829_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0137_), + .Q(\genblk1[7].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1830_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1831_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1832_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1833_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1834_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1835_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1836_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1837_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1838_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1839_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0144_), + .Q(\genblk1[8].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1840_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1841_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1842_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1843_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1844_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1845_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1846_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1847_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1848_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1849_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0145_), + .Q(\genblk1[8].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1850_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1851_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1852_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1853_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1854_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1855_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1856_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1857_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1858_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1859_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0146_), + .Q(\genblk1[8].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1860_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1861_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1862_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1863_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1864_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1865_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1866_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1867_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1868_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1869_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0147_), + .Q(\genblk1[8].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1870_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1871_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1872_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1873_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1874_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1875_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1876_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1877_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1878_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1879_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0148_), + .Q(\genblk1[8].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1880_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1881_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1882_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1883_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1884_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1885_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1886_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1887_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1888_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1889_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0149_), + .Q(\genblk1[8].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1890_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1891_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1892_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1893_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1894_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1895_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1896_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1897_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1898_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1899_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0150_), + .Q(\genblk1[8].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1900_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1901_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1902_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1903_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1904_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1905_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1906_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1907_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1908_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1909_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0151_), + .Q(\genblk1[8].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1910_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1911_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1912_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1913_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1914_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1915_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1916_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1917_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1918_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1919_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0152_), + .Q(\genblk1[8].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1920_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1921_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1922_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1923_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1924_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1925_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1926_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1927_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1928_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1929_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0138_), + .Q(\genblk1[8].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1930_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1931_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1932_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1933_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1934_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1935_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1936_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1937_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1938_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1939_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0139_), + .Q(\genblk1[8].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1940_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1941_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1942_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1943_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1944_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1945_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1946_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1947_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1948_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1949_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0140_), + .Q(\genblk1[8].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1950_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1951_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1952_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1953_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1954_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1955_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1956_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1957_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1958_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1959_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0141_), + .Q(\genblk1[8].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1960_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1961_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1962_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1963_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1964_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1965_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1966_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1967_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1968_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1969_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0142_), + .Q(\genblk1[8].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1970_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1971_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1972_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1973_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1974_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1975_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1976_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1977_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1978_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1979_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0143_), + .Q(\genblk1[8].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1980_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1981_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1982_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1983_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1984_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1985_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1986_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1987_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1988_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1989_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0153_), + .Q(\genblk1[8].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1990_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1991_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1992_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1993_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1994_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1995_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1996_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1997_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1998_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _1999_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0160_), + .Q(\genblk1[9].u_lut.dist_mem[15] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2000_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2001_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2002_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2003_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2004_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2005_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2006_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2007_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2008_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2009_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0161_), + .Q(\genblk1[9].u_lut.dist_mem[1] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2010_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2011_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2012_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2013_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2014_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2015_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2016_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2017_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2018_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2019_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0162_), + .Q(\genblk1[9].u_lut.dist_mem[2] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2020_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2021_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2022_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2023_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2024_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2025_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2026_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2027_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2028_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2029_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0163_), + .Q(\genblk1[9].u_lut.dist_mem[3] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2030_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2031_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2032_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2033_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2034_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2035_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2036_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2037_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2038_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2039_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0164_), + .Q(\genblk1[9].u_lut.dist_mem[4] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2040_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2041_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2042_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2043_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2044_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2045_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2046_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2047_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2048_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2049_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0165_), + .Q(\genblk1[9].u_lut.dist_mem[5] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2050_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2051_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2052_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2053_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2054_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2055_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2056_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2057_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2058_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2059_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0166_), + .Q(\genblk1[9].u_lut.dist_mem[6] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2060_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2061_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2062_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2063_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2064_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2065_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2066_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2067_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2068_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2069_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0167_), + .Q(\genblk1[9].u_lut.dist_mem[7] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2070_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2071_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2072_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2073_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2074_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2075_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2076_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2077_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2078_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2079_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0168_), + .Q(\genblk1[9].u_lut.dist_mem[8] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2080_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2081_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2082_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2083_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2084_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2085_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2086_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2087_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2088_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2089_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0154_), + .Q(\genblk1[9].u_lut.dist_mem[0] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2090_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2091_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2092_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2093_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2094_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2095_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2096_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2097_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2098_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2099_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0155_), + .Q(\genblk1[9].u_lut.dist_mem[10] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2100_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2101_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2102_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2103_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2104_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2105_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2106_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2107_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2108_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2109_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0156_), + .Q(\genblk1[9].u_lut.dist_mem[11] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2110_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2111_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2112_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2113_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2114_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2115_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2116_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2117_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2118_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2119_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0157_), + .Q(\genblk1[9].u_lut.dist_mem[12] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2120_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2121_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2122_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2123_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2124_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2125_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2126_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2127_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2128_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2129_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0158_), + .Q(\genblk1[9].u_lut.dist_mem[13] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2130_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2131_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2132_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2133_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2134_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2135_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2136_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2137_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2138_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2139_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0159_), + .Q(\genblk1[9].u_lut.dist_mem[14] [9]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2140_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [0]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [0]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2141_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [1]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [1]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2142_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [2]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [2]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2143_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [3]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [3]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2144_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [4]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [4]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2145_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [5]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [5]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2146_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [6]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [6]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2147_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [7]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [7]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2148_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [8]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [8]), + .SR(1'h0) + ); + CC_DFF #( + .CLK_INV(1'h0), + .EN_INV(1'h0), + .INIT(1'hx), + .SR_INV(1'h0), + .SR_VAL(1'h0) + ) _2149_ ( + .CLK(\genblk1[0].u_lut.clk ), + .D(\genblk1[0].u_lut.wdat [9]), + .EN(_0169_), + .Q(\genblk1[9].u_lut.dist_mem[9] [9]), + .SR(1'h0) + ); + CC_MX4 _2150_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [0]), + .D1(\genblk1[1].u_lut.dist_mem[1] [0]), + .D2(\genblk1[1].u_lut.dist_mem[2] [0]), + .D3(\genblk1[1].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[0]) + ); + CC_MX4 _2151_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [0]), + .D1(\genblk1[1].u_lut.dist_mem[5] [0]), + .D2(\genblk1[1].u_lut.dist_mem[6] [0]), + .D3(\genblk1[1].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[0]) + ); + CC_MX4 _2152_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [0]), + .D1(\genblk1[1].u_lut.dist_mem[9] [0]), + .D2(\genblk1[1].u_lut.dist_mem[10] [0]), + .D3(\genblk1[1].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[0]) + ); + CC_MX4 _2153_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [0]), + .D1(\genblk1[1].u_lut.dist_mem[13] [0]), + .D2(\genblk1[1].u_lut.dist_mem[14] [0]), + .D3(\genblk1[1].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[0]) + ); + CC_MX4 _2154_ ( + .D0(_0179_[0]), + .D1(_0180_[0]), + .D2(_0181_[0]), + .D3(_0182_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [0]) + ); + CC_MX4 _2155_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [1]), + .D1(\genblk1[1].u_lut.dist_mem[1] [1]), + .D2(\genblk1[1].u_lut.dist_mem[2] [1]), + .D3(\genblk1[1].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[1]) + ); + CC_MX4 _2156_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [1]), + .D1(\genblk1[1].u_lut.dist_mem[5] [1]), + .D2(\genblk1[1].u_lut.dist_mem[6] [1]), + .D3(\genblk1[1].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[1]) + ); + CC_MX4 _2157_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [1]), + .D1(\genblk1[1].u_lut.dist_mem[9] [1]), + .D2(\genblk1[1].u_lut.dist_mem[10] [1]), + .D3(\genblk1[1].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[1]) + ); + CC_MX4 _2158_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [1]), + .D1(\genblk1[1].u_lut.dist_mem[13] [1]), + .D2(\genblk1[1].u_lut.dist_mem[14] [1]), + .D3(\genblk1[1].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[1]) + ); + CC_MX4 _2159_ ( + .D0(_0179_[1]), + .D1(_0180_[1]), + .D2(_0181_[1]), + .D3(_0182_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [1]) + ); + CC_MX4 _2160_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [2]), + .D1(\genblk1[1].u_lut.dist_mem[1] [2]), + .D2(\genblk1[1].u_lut.dist_mem[2] [2]), + .D3(\genblk1[1].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[2]) + ); + CC_MX4 _2161_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [2]), + .D1(\genblk1[1].u_lut.dist_mem[5] [2]), + .D2(\genblk1[1].u_lut.dist_mem[6] [2]), + .D3(\genblk1[1].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[2]) + ); + CC_MX4 _2162_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [2]), + .D1(\genblk1[1].u_lut.dist_mem[9] [2]), + .D2(\genblk1[1].u_lut.dist_mem[10] [2]), + .D3(\genblk1[1].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[2]) + ); + CC_MX4 _2163_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [2]), + .D1(\genblk1[1].u_lut.dist_mem[13] [2]), + .D2(\genblk1[1].u_lut.dist_mem[14] [2]), + .D3(\genblk1[1].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[2]) + ); + CC_MX4 _2164_ ( + .D0(_0179_[2]), + .D1(_0180_[2]), + .D2(_0181_[2]), + .D3(_0182_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [2]) + ); + CC_MX4 _2165_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [3]), + .D1(\genblk1[1].u_lut.dist_mem[1] [3]), + .D2(\genblk1[1].u_lut.dist_mem[2] [3]), + .D3(\genblk1[1].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[3]) + ); + CC_MX4 _2166_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [3]), + .D1(\genblk1[1].u_lut.dist_mem[5] [3]), + .D2(\genblk1[1].u_lut.dist_mem[6] [3]), + .D3(\genblk1[1].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[3]) + ); + CC_MX4 _2167_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [3]), + .D1(\genblk1[1].u_lut.dist_mem[9] [3]), + .D2(\genblk1[1].u_lut.dist_mem[10] [3]), + .D3(\genblk1[1].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[3]) + ); + CC_MX4 _2168_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [3]), + .D1(\genblk1[1].u_lut.dist_mem[13] [3]), + .D2(\genblk1[1].u_lut.dist_mem[14] [3]), + .D3(\genblk1[1].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[3]) + ); + CC_MX4 _2169_ ( + .D0(_0179_[3]), + .D1(_0180_[3]), + .D2(_0181_[3]), + .D3(_0182_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [3]) + ); + CC_MX4 _2170_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [4]), + .D1(\genblk1[1].u_lut.dist_mem[1] [4]), + .D2(\genblk1[1].u_lut.dist_mem[2] [4]), + .D3(\genblk1[1].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[4]) + ); + CC_MX4 _2171_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [4]), + .D1(\genblk1[1].u_lut.dist_mem[5] [4]), + .D2(\genblk1[1].u_lut.dist_mem[6] [4]), + .D3(\genblk1[1].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[4]) + ); + CC_MX4 _2172_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [4]), + .D1(\genblk1[1].u_lut.dist_mem[9] [4]), + .D2(\genblk1[1].u_lut.dist_mem[10] [4]), + .D3(\genblk1[1].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[4]) + ); + CC_MX4 _2173_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [4]), + .D1(\genblk1[1].u_lut.dist_mem[13] [4]), + .D2(\genblk1[1].u_lut.dist_mem[14] [4]), + .D3(\genblk1[1].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[4]) + ); + CC_MX4 _2174_ ( + .D0(_0179_[4]), + .D1(_0180_[4]), + .D2(_0181_[4]), + .D3(_0182_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [4]) + ); + CC_MX4 _2175_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [5]), + .D1(\genblk1[1].u_lut.dist_mem[1] [5]), + .D2(\genblk1[1].u_lut.dist_mem[2] [5]), + .D3(\genblk1[1].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[5]) + ); + CC_MX4 _2176_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [5]), + .D1(\genblk1[1].u_lut.dist_mem[5] [5]), + .D2(\genblk1[1].u_lut.dist_mem[6] [5]), + .D3(\genblk1[1].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[5]) + ); + CC_MX4 _2177_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [5]), + .D1(\genblk1[1].u_lut.dist_mem[9] [5]), + .D2(\genblk1[1].u_lut.dist_mem[10] [5]), + .D3(\genblk1[1].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[5]) + ); + CC_MX4 _2178_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [5]), + .D1(\genblk1[1].u_lut.dist_mem[13] [5]), + .D2(\genblk1[1].u_lut.dist_mem[14] [5]), + .D3(\genblk1[1].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[5]) + ); + CC_MX4 _2179_ ( + .D0(_0179_[5]), + .D1(_0180_[5]), + .D2(_0181_[5]), + .D3(_0182_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [5]) + ); + CC_MX4 _2180_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [6]), + .D1(\genblk1[1].u_lut.dist_mem[1] [6]), + .D2(\genblk1[1].u_lut.dist_mem[2] [6]), + .D3(\genblk1[1].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[6]) + ); + CC_MX4 _2181_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [6]), + .D1(\genblk1[1].u_lut.dist_mem[5] [6]), + .D2(\genblk1[1].u_lut.dist_mem[6] [6]), + .D3(\genblk1[1].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[6]) + ); + CC_MX4 _2182_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [6]), + .D1(\genblk1[1].u_lut.dist_mem[9] [6]), + .D2(\genblk1[1].u_lut.dist_mem[10] [6]), + .D3(\genblk1[1].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[6]) + ); + CC_MX4 _2183_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [6]), + .D1(\genblk1[1].u_lut.dist_mem[13] [6]), + .D2(\genblk1[1].u_lut.dist_mem[14] [6]), + .D3(\genblk1[1].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[6]) + ); + CC_MX4 _2184_ ( + .D0(_0179_[6]), + .D1(_0180_[6]), + .D2(_0181_[6]), + .D3(_0182_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [6]) + ); + CC_MX4 _2185_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [7]), + .D1(\genblk1[1].u_lut.dist_mem[1] [7]), + .D2(\genblk1[1].u_lut.dist_mem[2] [7]), + .D3(\genblk1[1].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[7]) + ); + CC_MX4 _2186_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [7]), + .D1(\genblk1[1].u_lut.dist_mem[5] [7]), + .D2(\genblk1[1].u_lut.dist_mem[6] [7]), + .D3(\genblk1[1].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[7]) + ); + CC_MX4 _2187_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [7]), + .D1(\genblk1[1].u_lut.dist_mem[9] [7]), + .D2(\genblk1[1].u_lut.dist_mem[10] [7]), + .D3(\genblk1[1].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[7]) + ); + CC_MX4 _2188_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [7]), + .D1(\genblk1[1].u_lut.dist_mem[13] [7]), + .D2(\genblk1[1].u_lut.dist_mem[14] [7]), + .D3(\genblk1[1].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[7]) + ); + CC_MX4 _2189_ ( + .D0(_0179_[7]), + .D1(_0180_[7]), + .D2(_0181_[7]), + .D3(_0182_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [7]) + ); + CC_MX4 _2190_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [8]), + .D1(\genblk1[1].u_lut.dist_mem[1] [8]), + .D2(\genblk1[1].u_lut.dist_mem[2] [8]), + .D3(\genblk1[1].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[8]) + ); + CC_MX4 _2191_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [8]), + .D1(\genblk1[1].u_lut.dist_mem[5] [8]), + .D2(\genblk1[1].u_lut.dist_mem[6] [8]), + .D3(\genblk1[1].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[8]) + ); + CC_MX4 _2192_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [8]), + .D1(\genblk1[1].u_lut.dist_mem[9] [8]), + .D2(\genblk1[1].u_lut.dist_mem[10] [8]), + .D3(\genblk1[1].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[8]) + ); + CC_MX4 _2193_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [8]), + .D1(\genblk1[1].u_lut.dist_mem[13] [8]), + .D2(\genblk1[1].u_lut.dist_mem[14] [8]), + .D3(\genblk1[1].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[8]) + ); + CC_MX4 _2194_ ( + .D0(_0179_[8]), + .D1(_0180_[8]), + .D2(_0181_[8]), + .D3(_0182_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [8]) + ); + CC_MX4 _2195_ ( + .D0(\genblk1[1].u_lut.dist_mem[0] [9]), + .D1(\genblk1[1].u_lut.dist_mem[1] [9]), + .D2(\genblk1[1].u_lut.dist_mem[2] [9]), + .D3(\genblk1[1].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0179_[9]) + ); + CC_MX4 _2196_ ( + .D0(\genblk1[1].u_lut.dist_mem[4] [9]), + .D1(\genblk1[1].u_lut.dist_mem[5] [9]), + .D2(\genblk1[1].u_lut.dist_mem[6] [9]), + .D3(\genblk1[1].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0180_[9]) + ); + CC_MX4 _2197_ ( + .D0(\genblk1[1].u_lut.dist_mem[8] [9]), + .D1(\genblk1[1].u_lut.dist_mem[9] [9]), + .D2(\genblk1[1].u_lut.dist_mem[10] [9]), + .D3(\genblk1[1].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0181_[9]) + ); + CC_MX4 _2198_ ( + .D0(\genblk1[1].u_lut.dist_mem[12] [9]), + .D1(\genblk1[1].u_lut.dist_mem[13] [9]), + .D2(\genblk1[1].u_lut.dist_mem[14] [9]), + .D3(\genblk1[1].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0182_[9]) + ); + CC_MX4 _2199_ ( + .D0(_0179_[9]), + .D1(_0180_[9]), + .D2(_0181_[9]), + .D3(_0182_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[1].u_lut.rdat [9]) + ); + CC_MX4 _2200_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [0]), + .D1(\genblk1[2].u_lut.dist_mem[1] [0]), + .D2(\genblk1[2].u_lut.dist_mem[2] [0]), + .D3(\genblk1[2].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[0]) + ); + CC_MX4 _2201_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [0]), + .D1(\genblk1[2].u_lut.dist_mem[5] [0]), + .D2(\genblk1[2].u_lut.dist_mem[6] [0]), + .D3(\genblk1[2].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[0]) + ); + CC_MX4 _2202_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [0]), + .D1(\genblk1[2].u_lut.dist_mem[9] [0]), + .D2(\genblk1[2].u_lut.dist_mem[10] [0]), + .D3(\genblk1[2].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[0]) + ); + CC_MX4 _2203_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [0]), + .D1(\genblk1[2].u_lut.dist_mem[13] [0]), + .D2(\genblk1[2].u_lut.dist_mem[14] [0]), + .D3(\genblk1[2].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[0]) + ); + CC_MX4 _2204_ ( + .D0(_0183_[0]), + .D1(_0184_[0]), + .D2(_0185_[0]), + .D3(_0186_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [0]) + ); + CC_MX4 _2205_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [1]), + .D1(\genblk1[2].u_lut.dist_mem[1] [1]), + .D2(\genblk1[2].u_lut.dist_mem[2] [1]), + .D3(\genblk1[2].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[1]) + ); + CC_MX4 _2206_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [1]), + .D1(\genblk1[2].u_lut.dist_mem[5] [1]), + .D2(\genblk1[2].u_lut.dist_mem[6] [1]), + .D3(\genblk1[2].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[1]) + ); + CC_MX4 _2207_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [1]), + .D1(\genblk1[2].u_lut.dist_mem[9] [1]), + .D2(\genblk1[2].u_lut.dist_mem[10] [1]), + .D3(\genblk1[2].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[1]) + ); + CC_MX4 _2208_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [1]), + .D1(\genblk1[2].u_lut.dist_mem[13] [1]), + .D2(\genblk1[2].u_lut.dist_mem[14] [1]), + .D3(\genblk1[2].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[1]) + ); + CC_MX4 _2209_ ( + .D0(_0183_[1]), + .D1(_0184_[1]), + .D2(_0185_[1]), + .D3(_0186_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [1]) + ); + CC_MX4 _2210_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [2]), + .D1(\genblk1[2].u_lut.dist_mem[1] [2]), + .D2(\genblk1[2].u_lut.dist_mem[2] [2]), + .D3(\genblk1[2].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[2]) + ); + CC_MX4 _2211_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [2]), + .D1(\genblk1[2].u_lut.dist_mem[5] [2]), + .D2(\genblk1[2].u_lut.dist_mem[6] [2]), + .D3(\genblk1[2].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[2]) + ); + CC_MX4 _2212_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [2]), + .D1(\genblk1[2].u_lut.dist_mem[9] [2]), + .D2(\genblk1[2].u_lut.dist_mem[10] [2]), + .D3(\genblk1[2].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[2]) + ); + CC_MX4 _2213_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [2]), + .D1(\genblk1[2].u_lut.dist_mem[13] [2]), + .D2(\genblk1[2].u_lut.dist_mem[14] [2]), + .D3(\genblk1[2].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[2]) + ); + CC_MX4 _2214_ ( + .D0(_0183_[2]), + .D1(_0184_[2]), + .D2(_0185_[2]), + .D3(_0186_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [2]) + ); + CC_MX4 _2215_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [3]), + .D1(\genblk1[2].u_lut.dist_mem[1] [3]), + .D2(\genblk1[2].u_lut.dist_mem[2] [3]), + .D3(\genblk1[2].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[3]) + ); + CC_MX4 _2216_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [3]), + .D1(\genblk1[2].u_lut.dist_mem[5] [3]), + .D2(\genblk1[2].u_lut.dist_mem[6] [3]), + .D3(\genblk1[2].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[3]) + ); + CC_MX4 _2217_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [3]), + .D1(\genblk1[2].u_lut.dist_mem[9] [3]), + .D2(\genblk1[2].u_lut.dist_mem[10] [3]), + .D3(\genblk1[2].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[3]) + ); + CC_MX4 _2218_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [3]), + .D1(\genblk1[2].u_lut.dist_mem[13] [3]), + .D2(\genblk1[2].u_lut.dist_mem[14] [3]), + .D3(\genblk1[2].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[3]) + ); + CC_MX4 _2219_ ( + .D0(_0183_[3]), + .D1(_0184_[3]), + .D2(_0185_[3]), + .D3(_0186_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [3]) + ); + CC_MX4 _2220_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [4]), + .D1(\genblk1[2].u_lut.dist_mem[1] [4]), + .D2(\genblk1[2].u_lut.dist_mem[2] [4]), + .D3(\genblk1[2].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[4]) + ); + CC_MX4 _2221_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [4]), + .D1(\genblk1[2].u_lut.dist_mem[5] [4]), + .D2(\genblk1[2].u_lut.dist_mem[6] [4]), + .D3(\genblk1[2].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[4]) + ); + CC_MX4 _2222_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [4]), + .D1(\genblk1[2].u_lut.dist_mem[9] [4]), + .D2(\genblk1[2].u_lut.dist_mem[10] [4]), + .D3(\genblk1[2].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[4]) + ); + CC_MX4 _2223_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [4]), + .D1(\genblk1[2].u_lut.dist_mem[13] [4]), + .D2(\genblk1[2].u_lut.dist_mem[14] [4]), + .D3(\genblk1[2].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[4]) + ); + CC_MX4 _2224_ ( + .D0(_0183_[4]), + .D1(_0184_[4]), + .D2(_0185_[4]), + .D3(_0186_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [4]) + ); + CC_MX4 _2225_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [5]), + .D1(\genblk1[2].u_lut.dist_mem[1] [5]), + .D2(\genblk1[2].u_lut.dist_mem[2] [5]), + .D3(\genblk1[2].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[5]) + ); + CC_MX4 _2226_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [5]), + .D1(\genblk1[2].u_lut.dist_mem[5] [5]), + .D2(\genblk1[2].u_lut.dist_mem[6] [5]), + .D3(\genblk1[2].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[5]) + ); + CC_MX4 _2227_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [5]), + .D1(\genblk1[2].u_lut.dist_mem[9] [5]), + .D2(\genblk1[2].u_lut.dist_mem[10] [5]), + .D3(\genblk1[2].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[5]) + ); + CC_MX4 _2228_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [5]), + .D1(\genblk1[2].u_lut.dist_mem[13] [5]), + .D2(\genblk1[2].u_lut.dist_mem[14] [5]), + .D3(\genblk1[2].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[5]) + ); + CC_MX4 _2229_ ( + .D0(_0183_[5]), + .D1(_0184_[5]), + .D2(_0185_[5]), + .D3(_0186_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [5]) + ); + CC_MX4 _2230_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [6]), + .D1(\genblk1[2].u_lut.dist_mem[1] [6]), + .D2(\genblk1[2].u_lut.dist_mem[2] [6]), + .D3(\genblk1[2].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[6]) + ); + CC_MX4 _2231_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [6]), + .D1(\genblk1[2].u_lut.dist_mem[5] [6]), + .D2(\genblk1[2].u_lut.dist_mem[6] [6]), + .D3(\genblk1[2].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[6]) + ); + CC_MX4 _2232_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [6]), + .D1(\genblk1[2].u_lut.dist_mem[9] [6]), + .D2(\genblk1[2].u_lut.dist_mem[10] [6]), + .D3(\genblk1[2].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[6]) + ); + CC_MX4 _2233_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [6]), + .D1(\genblk1[2].u_lut.dist_mem[13] [6]), + .D2(\genblk1[2].u_lut.dist_mem[14] [6]), + .D3(\genblk1[2].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[6]) + ); + CC_MX4 _2234_ ( + .D0(_0183_[6]), + .D1(_0184_[6]), + .D2(_0185_[6]), + .D3(_0186_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [6]) + ); + CC_MX4 _2235_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [7]), + .D1(\genblk1[2].u_lut.dist_mem[1] [7]), + .D2(\genblk1[2].u_lut.dist_mem[2] [7]), + .D3(\genblk1[2].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[7]) + ); + CC_MX4 _2236_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [7]), + .D1(\genblk1[2].u_lut.dist_mem[5] [7]), + .D2(\genblk1[2].u_lut.dist_mem[6] [7]), + .D3(\genblk1[2].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[7]) + ); + CC_MX4 _2237_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [7]), + .D1(\genblk1[2].u_lut.dist_mem[9] [7]), + .D2(\genblk1[2].u_lut.dist_mem[10] [7]), + .D3(\genblk1[2].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[7]) + ); + CC_MX4 _2238_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [7]), + .D1(\genblk1[2].u_lut.dist_mem[13] [7]), + .D2(\genblk1[2].u_lut.dist_mem[14] [7]), + .D3(\genblk1[2].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[7]) + ); + CC_MX4 _2239_ ( + .D0(_0183_[7]), + .D1(_0184_[7]), + .D2(_0185_[7]), + .D3(_0186_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [7]) + ); + CC_MX4 _2240_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [8]), + .D1(\genblk1[2].u_lut.dist_mem[1] [8]), + .D2(\genblk1[2].u_lut.dist_mem[2] [8]), + .D3(\genblk1[2].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[8]) + ); + CC_MX4 _2241_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [8]), + .D1(\genblk1[2].u_lut.dist_mem[5] [8]), + .D2(\genblk1[2].u_lut.dist_mem[6] [8]), + .D3(\genblk1[2].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[8]) + ); + CC_MX4 _2242_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [8]), + .D1(\genblk1[2].u_lut.dist_mem[9] [8]), + .D2(\genblk1[2].u_lut.dist_mem[10] [8]), + .D3(\genblk1[2].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[8]) + ); + CC_MX4 _2243_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [8]), + .D1(\genblk1[2].u_lut.dist_mem[13] [8]), + .D2(\genblk1[2].u_lut.dist_mem[14] [8]), + .D3(\genblk1[2].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[8]) + ); + CC_MX4 _2244_ ( + .D0(_0183_[8]), + .D1(_0184_[8]), + .D2(_0185_[8]), + .D3(_0186_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [8]) + ); + CC_MX4 _2245_ ( + .D0(\genblk1[2].u_lut.dist_mem[0] [9]), + .D1(\genblk1[2].u_lut.dist_mem[1] [9]), + .D2(\genblk1[2].u_lut.dist_mem[2] [9]), + .D3(\genblk1[2].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0183_[9]) + ); + CC_MX4 _2246_ ( + .D0(\genblk1[2].u_lut.dist_mem[4] [9]), + .D1(\genblk1[2].u_lut.dist_mem[5] [9]), + .D2(\genblk1[2].u_lut.dist_mem[6] [9]), + .D3(\genblk1[2].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0184_[9]) + ); + CC_MX4 _2247_ ( + .D0(\genblk1[2].u_lut.dist_mem[8] [9]), + .D1(\genblk1[2].u_lut.dist_mem[9] [9]), + .D2(\genblk1[2].u_lut.dist_mem[10] [9]), + .D3(\genblk1[2].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0185_[9]) + ); + CC_MX4 _2248_ ( + .D0(\genblk1[2].u_lut.dist_mem[12] [9]), + .D1(\genblk1[2].u_lut.dist_mem[13] [9]), + .D2(\genblk1[2].u_lut.dist_mem[14] [9]), + .D3(\genblk1[2].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0186_[9]) + ); + CC_MX4 _2249_ ( + .D0(_0183_[9]), + .D1(_0184_[9]), + .D2(_0185_[9]), + .D3(_0186_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[2].u_lut.rdat [9]) + ); + CC_MX4 _2250_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [0]), + .D1(\genblk1[3].u_lut.dist_mem[1] [0]), + .D2(\genblk1[3].u_lut.dist_mem[2] [0]), + .D3(\genblk1[3].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[0]) + ); + CC_MX4 _2251_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [0]), + .D1(\genblk1[3].u_lut.dist_mem[5] [0]), + .D2(\genblk1[3].u_lut.dist_mem[6] [0]), + .D3(\genblk1[3].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[0]) + ); + CC_MX4 _2252_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [0]), + .D1(\genblk1[3].u_lut.dist_mem[9] [0]), + .D2(\genblk1[3].u_lut.dist_mem[10] [0]), + .D3(\genblk1[3].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[0]) + ); + CC_MX4 _2253_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [0]), + .D1(\genblk1[3].u_lut.dist_mem[13] [0]), + .D2(\genblk1[3].u_lut.dist_mem[14] [0]), + .D3(\genblk1[3].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[0]) + ); + CC_MX4 _2254_ ( + .D0(_0187_[0]), + .D1(_0188_[0]), + .D2(_0189_[0]), + .D3(_0190_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [0]) + ); + CC_MX4 _2255_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [1]), + .D1(\genblk1[3].u_lut.dist_mem[1] [1]), + .D2(\genblk1[3].u_lut.dist_mem[2] [1]), + .D3(\genblk1[3].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[1]) + ); + CC_MX4 _2256_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [1]), + .D1(\genblk1[3].u_lut.dist_mem[5] [1]), + .D2(\genblk1[3].u_lut.dist_mem[6] [1]), + .D3(\genblk1[3].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[1]) + ); + CC_MX4 _2257_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [1]), + .D1(\genblk1[3].u_lut.dist_mem[9] [1]), + .D2(\genblk1[3].u_lut.dist_mem[10] [1]), + .D3(\genblk1[3].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[1]) + ); + CC_MX4 _2258_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [1]), + .D1(\genblk1[3].u_lut.dist_mem[13] [1]), + .D2(\genblk1[3].u_lut.dist_mem[14] [1]), + .D3(\genblk1[3].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[1]) + ); + CC_MX4 _2259_ ( + .D0(_0187_[1]), + .D1(_0188_[1]), + .D2(_0189_[1]), + .D3(_0190_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [1]) + ); + CC_MX4 _2260_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [2]), + .D1(\genblk1[3].u_lut.dist_mem[1] [2]), + .D2(\genblk1[3].u_lut.dist_mem[2] [2]), + .D3(\genblk1[3].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[2]) + ); + CC_MX4 _2261_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [2]), + .D1(\genblk1[3].u_lut.dist_mem[5] [2]), + .D2(\genblk1[3].u_lut.dist_mem[6] [2]), + .D3(\genblk1[3].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[2]) + ); + CC_MX4 _2262_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [2]), + .D1(\genblk1[3].u_lut.dist_mem[9] [2]), + .D2(\genblk1[3].u_lut.dist_mem[10] [2]), + .D3(\genblk1[3].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[2]) + ); + CC_MX4 _2263_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [2]), + .D1(\genblk1[3].u_lut.dist_mem[13] [2]), + .D2(\genblk1[3].u_lut.dist_mem[14] [2]), + .D3(\genblk1[3].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[2]) + ); + CC_MX4 _2264_ ( + .D0(_0187_[2]), + .D1(_0188_[2]), + .D2(_0189_[2]), + .D3(_0190_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [2]) + ); + CC_MX4 _2265_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [3]), + .D1(\genblk1[3].u_lut.dist_mem[1] [3]), + .D2(\genblk1[3].u_lut.dist_mem[2] [3]), + .D3(\genblk1[3].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[3]) + ); + CC_MX4 _2266_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [3]), + .D1(\genblk1[3].u_lut.dist_mem[5] [3]), + .D2(\genblk1[3].u_lut.dist_mem[6] [3]), + .D3(\genblk1[3].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[3]) + ); + CC_MX4 _2267_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [3]), + .D1(\genblk1[3].u_lut.dist_mem[9] [3]), + .D2(\genblk1[3].u_lut.dist_mem[10] [3]), + .D3(\genblk1[3].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[3]) + ); + CC_MX4 _2268_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [3]), + .D1(\genblk1[3].u_lut.dist_mem[13] [3]), + .D2(\genblk1[3].u_lut.dist_mem[14] [3]), + .D3(\genblk1[3].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[3]) + ); + CC_MX4 _2269_ ( + .D0(_0187_[3]), + .D1(_0188_[3]), + .D2(_0189_[3]), + .D3(_0190_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [3]) + ); + CC_MX4 _2270_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [4]), + .D1(\genblk1[3].u_lut.dist_mem[1] [4]), + .D2(\genblk1[3].u_lut.dist_mem[2] [4]), + .D3(\genblk1[3].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[4]) + ); + CC_MX4 _2271_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [4]), + .D1(\genblk1[3].u_lut.dist_mem[5] [4]), + .D2(\genblk1[3].u_lut.dist_mem[6] [4]), + .D3(\genblk1[3].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[4]) + ); + CC_MX4 _2272_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [4]), + .D1(\genblk1[3].u_lut.dist_mem[9] [4]), + .D2(\genblk1[3].u_lut.dist_mem[10] [4]), + .D3(\genblk1[3].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[4]) + ); + CC_MX4 _2273_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [4]), + .D1(\genblk1[3].u_lut.dist_mem[13] [4]), + .D2(\genblk1[3].u_lut.dist_mem[14] [4]), + .D3(\genblk1[3].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[4]) + ); + CC_MX4 _2274_ ( + .D0(_0187_[4]), + .D1(_0188_[4]), + .D2(_0189_[4]), + .D3(_0190_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [4]) + ); + CC_MX4 _2275_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [5]), + .D1(\genblk1[3].u_lut.dist_mem[1] [5]), + .D2(\genblk1[3].u_lut.dist_mem[2] [5]), + .D3(\genblk1[3].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[5]) + ); + CC_MX4 _2276_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [5]), + .D1(\genblk1[3].u_lut.dist_mem[5] [5]), + .D2(\genblk1[3].u_lut.dist_mem[6] [5]), + .D3(\genblk1[3].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[5]) + ); + CC_MX4 _2277_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [5]), + .D1(\genblk1[3].u_lut.dist_mem[9] [5]), + .D2(\genblk1[3].u_lut.dist_mem[10] [5]), + .D3(\genblk1[3].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[5]) + ); + CC_MX4 _2278_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [5]), + .D1(\genblk1[3].u_lut.dist_mem[13] [5]), + .D2(\genblk1[3].u_lut.dist_mem[14] [5]), + .D3(\genblk1[3].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[5]) + ); + CC_MX4 _2279_ ( + .D0(_0187_[5]), + .D1(_0188_[5]), + .D2(_0189_[5]), + .D3(_0190_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [5]) + ); + CC_MX4 _2280_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [6]), + .D1(\genblk1[3].u_lut.dist_mem[1] [6]), + .D2(\genblk1[3].u_lut.dist_mem[2] [6]), + .D3(\genblk1[3].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[6]) + ); + CC_MX4 _2281_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [6]), + .D1(\genblk1[3].u_lut.dist_mem[5] [6]), + .D2(\genblk1[3].u_lut.dist_mem[6] [6]), + .D3(\genblk1[3].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[6]) + ); + CC_MX4 _2282_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [6]), + .D1(\genblk1[3].u_lut.dist_mem[9] [6]), + .D2(\genblk1[3].u_lut.dist_mem[10] [6]), + .D3(\genblk1[3].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[6]) + ); + CC_MX4 _2283_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [6]), + .D1(\genblk1[3].u_lut.dist_mem[13] [6]), + .D2(\genblk1[3].u_lut.dist_mem[14] [6]), + .D3(\genblk1[3].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[6]) + ); + CC_MX4 _2284_ ( + .D0(_0187_[6]), + .D1(_0188_[6]), + .D2(_0189_[6]), + .D3(_0190_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [6]) + ); + CC_MX4 _2285_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [7]), + .D1(\genblk1[3].u_lut.dist_mem[1] [7]), + .D2(\genblk1[3].u_lut.dist_mem[2] [7]), + .D3(\genblk1[3].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[7]) + ); + CC_MX4 _2286_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [7]), + .D1(\genblk1[3].u_lut.dist_mem[5] [7]), + .D2(\genblk1[3].u_lut.dist_mem[6] [7]), + .D3(\genblk1[3].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[7]) + ); + CC_MX4 _2287_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [7]), + .D1(\genblk1[3].u_lut.dist_mem[9] [7]), + .D2(\genblk1[3].u_lut.dist_mem[10] [7]), + .D3(\genblk1[3].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[7]) + ); + CC_MX4 _2288_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [7]), + .D1(\genblk1[3].u_lut.dist_mem[13] [7]), + .D2(\genblk1[3].u_lut.dist_mem[14] [7]), + .D3(\genblk1[3].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[7]) + ); + CC_MX4 _2289_ ( + .D0(_0187_[7]), + .D1(_0188_[7]), + .D2(_0189_[7]), + .D3(_0190_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [7]) + ); + CC_MX4 _2290_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [8]), + .D1(\genblk1[3].u_lut.dist_mem[1] [8]), + .D2(\genblk1[3].u_lut.dist_mem[2] [8]), + .D3(\genblk1[3].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[8]) + ); + CC_MX4 _2291_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [8]), + .D1(\genblk1[3].u_lut.dist_mem[5] [8]), + .D2(\genblk1[3].u_lut.dist_mem[6] [8]), + .D3(\genblk1[3].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[8]) + ); + CC_MX4 _2292_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [8]), + .D1(\genblk1[3].u_lut.dist_mem[9] [8]), + .D2(\genblk1[3].u_lut.dist_mem[10] [8]), + .D3(\genblk1[3].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[8]) + ); + CC_MX4 _2293_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [8]), + .D1(\genblk1[3].u_lut.dist_mem[13] [8]), + .D2(\genblk1[3].u_lut.dist_mem[14] [8]), + .D3(\genblk1[3].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[8]) + ); + CC_MX4 _2294_ ( + .D0(_0187_[8]), + .D1(_0188_[8]), + .D2(_0189_[8]), + .D3(_0190_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [8]) + ); + CC_MX4 _2295_ ( + .D0(\genblk1[3].u_lut.dist_mem[0] [9]), + .D1(\genblk1[3].u_lut.dist_mem[1] [9]), + .D2(\genblk1[3].u_lut.dist_mem[2] [9]), + .D3(\genblk1[3].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0187_[9]) + ); + CC_MX4 _2296_ ( + .D0(\genblk1[3].u_lut.dist_mem[4] [9]), + .D1(\genblk1[3].u_lut.dist_mem[5] [9]), + .D2(\genblk1[3].u_lut.dist_mem[6] [9]), + .D3(\genblk1[3].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0188_[9]) + ); + CC_MX4 _2297_ ( + .D0(\genblk1[3].u_lut.dist_mem[8] [9]), + .D1(\genblk1[3].u_lut.dist_mem[9] [9]), + .D2(\genblk1[3].u_lut.dist_mem[10] [9]), + .D3(\genblk1[3].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0189_[9]) + ); + CC_MX4 _2298_ ( + .D0(\genblk1[3].u_lut.dist_mem[12] [9]), + .D1(\genblk1[3].u_lut.dist_mem[13] [9]), + .D2(\genblk1[3].u_lut.dist_mem[14] [9]), + .D3(\genblk1[3].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0190_[9]) + ); + CC_MX4 _2299_ ( + .D0(_0187_[9]), + .D1(_0188_[9]), + .D2(_0189_[9]), + .D3(_0190_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[3].u_lut.rdat [9]) + ); + CC_MX4 _2300_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [0]), + .D1(\genblk1[4].u_lut.dist_mem[1] [0]), + .D2(\genblk1[4].u_lut.dist_mem[2] [0]), + .D3(\genblk1[4].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[0]) + ); + CC_MX4 _2301_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [0]), + .D1(\genblk1[4].u_lut.dist_mem[5] [0]), + .D2(\genblk1[4].u_lut.dist_mem[6] [0]), + .D3(\genblk1[4].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[0]) + ); + CC_MX4 _2302_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [0]), + .D1(\genblk1[4].u_lut.dist_mem[9] [0]), + .D2(\genblk1[4].u_lut.dist_mem[10] [0]), + .D3(\genblk1[4].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[0]) + ); + CC_MX4 _2303_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [0]), + .D1(\genblk1[4].u_lut.dist_mem[13] [0]), + .D2(\genblk1[4].u_lut.dist_mem[14] [0]), + .D3(\genblk1[4].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[0]) + ); + CC_MX4 _2304_ ( + .D0(_0191_[0]), + .D1(_0192_[0]), + .D2(_0193_[0]), + .D3(_0194_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [0]) + ); + CC_MX4 _2305_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [1]), + .D1(\genblk1[4].u_lut.dist_mem[1] [1]), + .D2(\genblk1[4].u_lut.dist_mem[2] [1]), + .D3(\genblk1[4].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[1]) + ); + CC_MX4 _2306_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [1]), + .D1(\genblk1[4].u_lut.dist_mem[5] [1]), + .D2(\genblk1[4].u_lut.dist_mem[6] [1]), + .D3(\genblk1[4].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[1]) + ); + CC_MX4 _2307_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [1]), + .D1(\genblk1[4].u_lut.dist_mem[9] [1]), + .D2(\genblk1[4].u_lut.dist_mem[10] [1]), + .D3(\genblk1[4].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[1]) + ); + CC_MX4 _2308_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [1]), + .D1(\genblk1[4].u_lut.dist_mem[13] [1]), + .D2(\genblk1[4].u_lut.dist_mem[14] [1]), + .D3(\genblk1[4].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[1]) + ); + CC_MX4 _2309_ ( + .D0(_0191_[1]), + .D1(_0192_[1]), + .D2(_0193_[1]), + .D3(_0194_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [1]) + ); + CC_MX4 _2310_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [2]), + .D1(\genblk1[4].u_lut.dist_mem[1] [2]), + .D2(\genblk1[4].u_lut.dist_mem[2] [2]), + .D3(\genblk1[4].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[2]) + ); + CC_MX4 _2311_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [2]), + .D1(\genblk1[4].u_lut.dist_mem[5] [2]), + .D2(\genblk1[4].u_lut.dist_mem[6] [2]), + .D3(\genblk1[4].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[2]) + ); + CC_MX4 _2312_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [2]), + .D1(\genblk1[4].u_lut.dist_mem[9] [2]), + .D2(\genblk1[4].u_lut.dist_mem[10] [2]), + .D3(\genblk1[4].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[2]) + ); + CC_MX4 _2313_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [2]), + .D1(\genblk1[4].u_lut.dist_mem[13] [2]), + .D2(\genblk1[4].u_lut.dist_mem[14] [2]), + .D3(\genblk1[4].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[2]) + ); + CC_MX4 _2314_ ( + .D0(_0191_[2]), + .D1(_0192_[2]), + .D2(_0193_[2]), + .D3(_0194_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [2]) + ); + CC_MX4 _2315_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [3]), + .D1(\genblk1[4].u_lut.dist_mem[1] [3]), + .D2(\genblk1[4].u_lut.dist_mem[2] [3]), + .D3(\genblk1[4].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[3]) + ); + CC_MX4 _2316_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [3]), + .D1(\genblk1[4].u_lut.dist_mem[5] [3]), + .D2(\genblk1[4].u_lut.dist_mem[6] [3]), + .D3(\genblk1[4].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[3]) + ); + CC_MX4 _2317_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [3]), + .D1(\genblk1[4].u_lut.dist_mem[9] [3]), + .D2(\genblk1[4].u_lut.dist_mem[10] [3]), + .D3(\genblk1[4].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[3]) + ); + CC_MX4 _2318_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [3]), + .D1(\genblk1[4].u_lut.dist_mem[13] [3]), + .D2(\genblk1[4].u_lut.dist_mem[14] [3]), + .D3(\genblk1[4].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[3]) + ); + CC_MX4 _2319_ ( + .D0(_0191_[3]), + .D1(_0192_[3]), + .D2(_0193_[3]), + .D3(_0194_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [3]) + ); + CC_MX4 _2320_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [4]), + .D1(\genblk1[4].u_lut.dist_mem[1] [4]), + .D2(\genblk1[4].u_lut.dist_mem[2] [4]), + .D3(\genblk1[4].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[4]) + ); + CC_MX4 _2321_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [4]), + .D1(\genblk1[4].u_lut.dist_mem[5] [4]), + .D2(\genblk1[4].u_lut.dist_mem[6] [4]), + .D3(\genblk1[4].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[4]) + ); + CC_MX4 _2322_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [4]), + .D1(\genblk1[4].u_lut.dist_mem[9] [4]), + .D2(\genblk1[4].u_lut.dist_mem[10] [4]), + .D3(\genblk1[4].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[4]) + ); + CC_MX4 _2323_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [4]), + .D1(\genblk1[4].u_lut.dist_mem[13] [4]), + .D2(\genblk1[4].u_lut.dist_mem[14] [4]), + .D3(\genblk1[4].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[4]) + ); + CC_MX4 _2324_ ( + .D0(_0191_[4]), + .D1(_0192_[4]), + .D2(_0193_[4]), + .D3(_0194_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [4]) + ); + CC_MX4 _2325_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [5]), + .D1(\genblk1[4].u_lut.dist_mem[1] [5]), + .D2(\genblk1[4].u_lut.dist_mem[2] [5]), + .D3(\genblk1[4].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[5]) + ); + CC_MX4 _2326_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [5]), + .D1(\genblk1[4].u_lut.dist_mem[5] [5]), + .D2(\genblk1[4].u_lut.dist_mem[6] [5]), + .D3(\genblk1[4].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[5]) + ); + CC_MX4 _2327_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [5]), + .D1(\genblk1[4].u_lut.dist_mem[9] [5]), + .D2(\genblk1[4].u_lut.dist_mem[10] [5]), + .D3(\genblk1[4].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[5]) + ); + CC_MX4 _2328_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [5]), + .D1(\genblk1[4].u_lut.dist_mem[13] [5]), + .D2(\genblk1[4].u_lut.dist_mem[14] [5]), + .D3(\genblk1[4].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[5]) + ); + CC_MX4 _2329_ ( + .D0(_0191_[5]), + .D1(_0192_[5]), + .D2(_0193_[5]), + .D3(_0194_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [5]) + ); + CC_MX4 _2330_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [6]), + .D1(\genblk1[4].u_lut.dist_mem[1] [6]), + .D2(\genblk1[4].u_lut.dist_mem[2] [6]), + .D3(\genblk1[4].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[6]) + ); + CC_MX4 _2331_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [6]), + .D1(\genblk1[4].u_lut.dist_mem[5] [6]), + .D2(\genblk1[4].u_lut.dist_mem[6] [6]), + .D3(\genblk1[4].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[6]) + ); + CC_MX4 _2332_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [6]), + .D1(\genblk1[4].u_lut.dist_mem[9] [6]), + .D2(\genblk1[4].u_lut.dist_mem[10] [6]), + .D3(\genblk1[4].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[6]) + ); + CC_MX4 _2333_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [6]), + .D1(\genblk1[4].u_lut.dist_mem[13] [6]), + .D2(\genblk1[4].u_lut.dist_mem[14] [6]), + .D3(\genblk1[4].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[6]) + ); + CC_MX4 _2334_ ( + .D0(_0191_[6]), + .D1(_0192_[6]), + .D2(_0193_[6]), + .D3(_0194_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [6]) + ); + CC_MX4 _2335_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [7]), + .D1(\genblk1[4].u_lut.dist_mem[1] [7]), + .D2(\genblk1[4].u_lut.dist_mem[2] [7]), + .D3(\genblk1[4].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[7]) + ); + CC_MX4 _2336_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [7]), + .D1(\genblk1[4].u_lut.dist_mem[5] [7]), + .D2(\genblk1[4].u_lut.dist_mem[6] [7]), + .D3(\genblk1[4].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[7]) + ); + CC_MX4 _2337_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [7]), + .D1(\genblk1[4].u_lut.dist_mem[9] [7]), + .D2(\genblk1[4].u_lut.dist_mem[10] [7]), + .D3(\genblk1[4].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[7]) + ); + CC_MX4 _2338_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [7]), + .D1(\genblk1[4].u_lut.dist_mem[13] [7]), + .D2(\genblk1[4].u_lut.dist_mem[14] [7]), + .D3(\genblk1[4].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[7]) + ); + CC_MX4 _2339_ ( + .D0(_0191_[7]), + .D1(_0192_[7]), + .D2(_0193_[7]), + .D3(_0194_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [7]) + ); + CC_MX4 _2340_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [8]), + .D1(\genblk1[4].u_lut.dist_mem[1] [8]), + .D2(\genblk1[4].u_lut.dist_mem[2] [8]), + .D3(\genblk1[4].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[8]) + ); + CC_MX4 _2341_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [8]), + .D1(\genblk1[4].u_lut.dist_mem[5] [8]), + .D2(\genblk1[4].u_lut.dist_mem[6] [8]), + .D3(\genblk1[4].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[8]) + ); + CC_MX4 _2342_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [8]), + .D1(\genblk1[4].u_lut.dist_mem[9] [8]), + .D2(\genblk1[4].u_lut.dist_mem[10] [8]), + .D3(\genblk1[4].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[8]) + ); + CC_MX4 _2343_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [8]), + .D1(\genblk1[4].u_lut.dist_mem[13] [8]), + .D2(\genblk1[4].u_lut.dist_mem[14] [8]), + .D3(\genblk1[4].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[8]) + ); + CC_MX4 _2344_ ( + .D0(_0191_[8]), + .D1(_0192_[8]), + .D2(_0193_[8]), + .D3(_0194_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [8]) + ); + CC_MX4 _2345_ ( + .D0(\genblk1[4].u_lut.dist_mem[0] [9]), + .D1(\genblk1[4].u_lut.dist_mem[1] [9]), + .D2(\genblk1[4].u_lut.dist_mem[2] [9]), + .D3(\genblk1[4].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0191_[9]) + ); + CC_MX4 _2346_ ( + .D0(\genblk1[4].u_lut.dist_mem[4] [9]), + .D1(\genblk1[4].u_lut.dist_mem[5] [9]), + .D2(\genblk1[4].u_lut.dist_mem[6] [9]), + .D3(\genblk1[4].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0192_[9]) + ); + CC_MX4 _2347_ ( + .D0(\genblk1[4].u_lut.dist_mem[8] [9]), + .D1(\genblk1[4].u_lut.dist_mem[9] [9]), + .D2(\genblk1[4].u_lut.dist_mem[10] [9]), + .D3(\genblk1[4].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0193_[9]) + ); + CC_MX4 _2348_ ( + .D0(\genblk1[4].u_lut.dist_mem[12] [9]), + .D1(\genblk1[4].u_lut.dist_mem[13] [9]), + .D2(\genblk1[4].u_lut.dist_mem[14] [9]), + .D3(\genblk1[4].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0194_[9]) + ); + CC_MX4 _2349_ ( + .D0(_0191_[9]), + .D1(_0192_[9]), + .D2(_0193_[9]), + .D3(_0194_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[4].u_lut.rdat [9]) + ); + CC_MX4 _2350_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [0]), + .D1(\genblk1[5].u_lut.dist_mem[1] [0]), + .D2(\genblk1[5].u_lut.dist_mem[2] [0]), + .D3(\genblk1[5].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[0]) + ); + CC_MX4 _2351_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [0]), + .D1(\genblk1[5].u_lut.dist_mem[5] [0]), + .D2(\genblk1[5].u_lut.dist_mem[6] [0]), + .D3(\genblk1[5].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[0]) + ); + CC_MX4 _2352_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [0]), + .D1(\genblk1[5].u_lut.dist_mem[9] [0]), + .D2(\genblk1[5].u_lut.dist_mem[10] [0]), + .D3(\genblk1[5].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[0]) + ); + CC_MX4 _2353_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [0]), + .D1(\genblk1[5].u_lut.dist_mem[13] [0]), + .D2(\genblk1[5].u_lut.dist_mem[14] [0]), + .D3(\genblk1[5].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[0]) + ); + CC_MX4 _2354_ ( + .D0(_0195_[0]), + .D1(_0196_[0]), + .D2(_0197_[0]), + .D3(_0198_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [0]) + ); + CC_MX4 _2355_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [1]), + .D1(\genblk1[5].u_lut.dist_mem[1] [1]), + .D2(\genblk1[5].u_lut.dist_mem[2] [1]), + .D3(\genblk1[5].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[1]) + ); + CC_MX4 _2356_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [1]), + .D1(\genblk1[5].u_lut.dist_mem[5] [1]), + .D2(\genblk1[5].u_lut.dist_mem[6] [1]), + .D3(\genblk1[5].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[1]) + ); + CC_MX4 _2357_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [1]), + .D1(\genblk1[5].u_lut.dist_mem[9] [1]), + .D2(\genblk1[5].u_lut.dist_mem[10] [1]), + .D3(\genblk1[5].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[1]) + ); + CC_MX4 _2358_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [1]), + .D1(\genblk1[5].u_lut.dist_mem[13] [1]), + .D2(\genblk1[5].u_lut.dist_mem[14] [1]), + .D3(\genblk1[5].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[1]) + ); + CC_MX4 _2359_ ( + .D0(_0195_[1]), + .D1(_0196_[1]), + .D2(_0197_[1]), + .D3(_0198_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [1]) + ); + CC_MX4 _2360_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [2]), + .D1(\genblk1[5].u_lut.dist_mem[1] [2]), + .D2(\genblk1[5].u_lut.dist_mem[2] [2]), + .D3(\genblk1[5].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[2]) + ); + CC_MX4 _2361_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [2]), + .D1(\genblk1[5].u_lut.dist_mem[5] [2]), + .D2(\genblk1[5].u_lut.dist_mem[6] [2]), + .D3(\genblk1[5].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[2]) + ); + CC_MX4 _2362_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [2]), + .D1(\genblk1[5].u_lut.dist_mem[9] [2]), + .D2(\genblk1[5].u_lut.dist_mem[10] [2]), + .D3(\genblk1[5].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[2]) + ); + CC_MX4 _2363_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [2]), + .D1(\genblk1[5].u_lut.dist_mem[13] [2]), + .D2(\genblk1[5].u_lut.dist_mem[14] [2]), + .D3(\genblk1[5].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[2]) + ); + CC_MX4 _2364_ ( + .D0(_0195_[2]), + .D1(_0196_[2]), + .D2(_0197_[2]), + .D3(_0198_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [2]) + ); + CC_MX4 _2365_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [3]), + .D1(\genblk1[5].u_lut.dist_mem[1] [3]), + .D2(\genblk1[5].u_lut.dist_mem[2] [3]), + .D3(\genblk1[5].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[3]) + ); + CC_MX4 _2366_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [3]), + .D1(\genblk1[5].u_lut.dist_mem[5] [3]), + .D2(\genblk1[5].u_lut.dist_mem[6] [3]), + .D3(\genblk1[5].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[3]) + ); + CC_MX4 _2367_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [3]), + .D1(\genblk1[5].u_lut.dist_mem[9] [3]), + .D2(\genblk1[5].u_lut.dist_mem[10] [3]), + .D3(\genblk1[5].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[3]) + ); + CC_MX4 _2368_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [3]), + .D1(\genblk1[5].u_lut.dist_mem[13] [3]), + .D2(\genblk1[5].u_lut.dist_mem[14] [3]), + .D3(\genblk1[5].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[3]) + ); + CC_MX4 _2369_ ( + .D0(_0195_[3]), + .D1(_0196_[3]), + .D2(_0197_[3]), + .D3(_0198_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [3]) + ); + CC_MX4 _2370_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [4]), + .D1(\genblk1[5].u_lut.dist_mem[1] [4]), + .D2(\genblk1[5].u_lut.dist_mem[2] [4]), + .D3(\genblk1[5].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[4]) + ); + CC_MX4 _2371_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [4]), + .D1(\genblk1[5].u_lut.dist_mem[5] [4]), + .D2(\genblk1[5].u_lut.dist_mem[6] [4]), + .D3(\genblk1[5].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[4]) + ); + CC_MX4 _2372_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [4]), + .D1(\genblk1[5].u_lut.dist_mem[9] [4]), + .D2(\genblk1[5].u_lut.dist_mem[10] [4]), + .D3(\genblk1[5].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[4]) + ); + CC_MX4 _2373_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [4]), + .D1(\genblk1[5].u_lut.dist_mem[13] [4]), + .D2(\genblk1[5].u_lut.dist_mem[14] [4]), + .D3(\genblk1[5].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[4]) + ); + CC_MX4 _2374_ ( + .D0(_0195_[4]), + .D1(_0196_[4]), + .D2(_0197_[4]), + .D3(_0198_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [4]) + ); + CC_MX4 _2375_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [5]), + .D1(\genblk1[5].u_lut.dist_mem[1] [5]), + .D2(\genblk1[5].u_lut.dist_mem[2] [5]), + .D3(\genblk1[5].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[5]) + ); + CC_MX4 _2376_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [5]), + .D1(\genblk1[5].u_lut.dist_mem[5] [5]), + .D2(\genblk1[5].u_lut.dist_mem[6] [5]), + .D3(\genblk1[5].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[5]) + ); + CC_MX4 _2377_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [5]), + .D1(\genblk1[5].u_lut.dist_mem[9] [5]), + .D2(\genblk1[5].u_lut.dist_mem[10] [5]), + .D3(\genblk1[5].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[5]) + ); + CC_MX4 _2378_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [5]), + .D1(\genblk1[5].u_lut.dist_mem[13] [5]), + .D2(\genblk1[5].u_lut.dist_mem[14] [5]), + .D3(\genblk1[5].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[5]) + ); + CC_MX4 _2379_ ( + .D0(_0195_[5]), + .D1(_0196_[5]), + .D2(_0197_[5]), + .D3(_0198_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [5]) + ); + CC_MX4 _2380_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [6]), + .D1(\genblk1[5].u_lut.dist_mem[1] [6]), + .D2(\genblk1[5].u_lut.dist_mem[2] [6]), + .D3(\genblk1[5].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[6]) + ); + CC_MX4 _2381_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [6]), + .D1(\genblk1[5].u_lut.dist_mem[5] [6]), + .D2(\genblk1[5].u_lut.dist_mem[6] [6]), + .D3(\genblk1[5].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[6]) + ); + CC_MX4 _2382_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [6]), + .D1(\genblk1[5].u_lut.dist_mem[9] [6]), + .D2(\genblk1[5].u_lut.dist_mem[10] [6]), + .D3(\genblk1[5].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[6]) + ); + CC_MX4 _2383_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [6]), + .D1(\genblk1[5].u_lut.dist_mem[13] [6]), + .D2(\genblk1[5].u_lut.dist_mem[14] [6]), + .D3(\genblk1[5].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[6]) + ); + CC_MX4 _2384_ ( + .D0(_0195_[6]), + .D1(_0196_[6]), + .D2(_0197_[6]), + .D3(_0198_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [6]) + ); + CC_MX4 _2385_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [7]), + .D1(\genblk1[5].u_lut.dist_mem[1] [7]), + .D2(\genblk1[5].u_lut.dist_mem[2] [7]), + .D3(\genblk1[5].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[7]) + ); + CC_MX4 _2386_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [7]), + .D1(\genblk1[5].u_lut.dist_mem[5] [7]), + .D2(\genblk1[5].u_lut.dist_mem[6] [7]), + .D3(\genblk1[5].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[7]) + ); + CC_MX4 _2387_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [7]), + .D1(\genblk1[5].u_lut.dist_mem[9] [7]), + .D2(\genblk1[5].u_lut.dist_mem[10] [7]), + .D3(\genblk1[5].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[7]) + ); + CC_MX4 _2388_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [7]), + .D1(\genblk1[5].u_lut.dist_mem[13] [7]), + .D2(\genblk1[5].u_lut.dist_mem[14] [7]), + .D3(\genblk1[5].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[7]) + ); + CC_MX4 _2389_ ( + .D0(_0195_[7]), + .D1(_0196_[7]), + .D2(_0197_[7]), + .D3(_0198_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [7]) + ); + CC_MX4 _2390_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [8]), + .D1(\genblk1[5].u_lut.dist_mem[1] [8]), + .D2(\genblk1[5].u_lut.dist_mem[2] [8]), + .D3(\genblk1[5].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[8]) + ); + CC_MX4 _2391_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [8]), + .D1(\genblk1[5].u_lut.dist_mem[5] [8]), + .D2(\genblk1[5].u_lut.dist_mem[6] [8]), + .D3(\genblk1[5].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[8]) + ); + CC_MX4 _2392_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [8]), + .D1(\genblk1[5].u_lut.dist_mem[9] [8]), + .D2(\genblk1[5].u_lut.dist_mem[10] [8]), + .D3(\genblk1[5].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[8]) + ); + CC_MX4 _2393_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [8]), + .D1(\genblk1[5].u_lut.dist_mem[13] [8]), + .D2(\genblk1[5].u_lut.dist_mem[14] [8]), + .D3(\genblk1[5].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[8]) + ); + CC_MX4 _2394_ ( + .D0(_0195_[8]), + .D1(_0196_[8]), + .D2(_0197_[8]), + .D3(_0198_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [8]) + ); + CC_MX4 _2395_ ( + .D0(\genblk1[5].u_lut.dist_mem[0] [9]), + .D1(\genblk1[5].u_lut.dist_mem[1] [9]), + .D2(\genblk1[5].u_lut.dist_mem[2] [9]), + .D3(\genblk1[5].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0195_[9]) + ); + CC_MX4 _2396_ ( + .D0(\genblk1[5].u_lut.dist_mem[4] [9]), + .D1(\genblk1[5].u_lut.dist_mem[5] [9]), + .D2(\genblk1[5].u_lut.dist_mem[6] [9]), + .D3(\genblk1[5].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0196_[9]) + ); + CC_MX4 _2397_ ( + .D0(\genblk1[5].u_lut.dist_mem[8] [9]), + .D1(\genblk1[5].u_lut.dist_mem[9] [9]), + .D2(\genblk1[5].u_lut.dist_mem[10] [9]), + .D3(\genblk1[5].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0197_[9]) + ); + CC_MX4 _2398_ ( + .D0(\genblk1[5].u_lut.dist_mem[12] [9]), + .D1(\genblk1[5].u_lut.dist_mem[13] [9]), + .D2(\genblk1[5].u_lut.dist_mem[14] [9]), + .D3(\genblk1[5].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0198_[9]) + ); + CC_MX4 _2399_ ( + .D0(_0195_[9]), + .D1(_0196_[9]), + .D2(_0197_[9]), + .D3(_0198_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[5].u_lut.rdat [9]) + ); + CC_MX4 _2400_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [0]), + .D1(\genblk1[6].u_lut.dist_mem[1] [0]), + .D2(\genblk1[6].u_lut.dist_mem[2] [0]), + .D3(\genblk1[6].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[0]) + ); + CC_MX4 _2401_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [0]), + .D1(\genblk1[6].u_lut.dist_mem[5] [0]), + .D2(\genblk1[6].u_lut.dist_mem[6] [0]), + .D3(\genblk1[6].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[0]) + ); + CC_MX4 _2402_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [0]), + .D1(\genblk1[6].u_lut.dist_mem[9] [0]), + .D2(\genblk1[6].u_lut.dist_mem[10] [0]), + .D3(\genblk1[6].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[0]) + ); + CC_MX4 _2403_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [0]), + .D1(\genblk1[6].u_lut.dist_mem[13] [0]), + .D2(\genblk1[6].u_lut.dist_mem[14] [0]), + .D3(\genblk1[6].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[0]) + ); + CC_MX4 _2404_ ( + .D0(_0199_[0]), + .D1(_0200_[0]), + .D2(_0201_[0]), + .D3(_0202_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [0]) + ); + CC_MX4 _2405_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [1]), + .D1(\genblk1[6].u_lut.dist_mem[1] [1]), + .D2(\genblk1[6].u_lut.dist_mem[2] [1]), + .D3(\genblk1[6].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[1]) + ); + CC_MX4 _2406_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [1]), + .D1(\genblk1[6].u_lut.dist_mem[5] [1]), + .D2(\genblk1[6].u_lut.dist_mem[6] [1]), + .D3(\genblk1[6].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[1]) + ); + CC_MX4 _2407_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [1]), + .D1(\genblk1[6].u_lut.dist_mem[9] [1]), + .D2(\genblk1[6].u_lut.dist_mem[10] [1]), + .D3(\genblk1[6].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[1]) + ); + CC_MX4 _2408_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [1]), + .D1(\genblk1[6].u_lut.dist_mem[13] [1]), + .D2(\genblk1[6].u_lut.dist_mem[14] [1]), + .D3(\genblk1[6].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[1]) + ); + CC_MX4 _2409_ ( + .D0(_0199_[1]), + .D1(_0200_[1]), + .D2(_0201_[1]), + .D3(_0202_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [1]) + ); + CC_MX4 _2410_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [2]), + .D1(\genblk1[6].u_lut.dist_mem[1] [2]), + .D2(\genblk1[6].u_lut.dist_mem[2] [2]), + .D3(\genblk1[6].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[2]) + ); + CC_MX4 _2411_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [2]), + .D1(\genblk1[6].u_lut.dist_mem[5] [2]), + .D2(\genblk1[6].u_lut.dist_mem[6] [2]), + .D3(\genblk1[6].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[2]) + ); + CC_MX4 _2412_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [2]), + .D1(\genblk1[6].u_lut.dist_mem[9] [2]), + .D2(\genblk1[6].u_lut.dist_mem[10] [2]), + .D3(\genblk1[6].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[2]) + ); + CC_MX4 _2413_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [2]), + .D1(\genblk1[6].u_lut.dist_mem[13] [2]), + .D2(\genblk1[6].u_lut.dist_mem[14] [2]), + .D3(\genblk1[6].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[2]) + ); + CC_MX4 _2414_ ( + .D0(_0199_[2]), + .D1(_0200_[2]), + .D2(_0201_[2]), + .D3(_0202_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [2]) + ); + CC_MX4 _2415_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [3]), + .D1(\genblk1[6].u_lut.dist_mem[1] [3]), + .D2(\genblk1[6].u_lut.dist_mem[2] [3]), + .D3(\genblk1[6].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[3]) + ); + CC_MX4 _2416_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [3]), + .D1(\genblk1[6].u_lut.dist_mem[5] [3]), + .D2(\genblk1[6].u_lut.dist_mem[6] [3]), + .D3(\genblk1[6].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[3]) + ); + CC_MX4 _2417_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [3]), + .D1(\genblk1[6].u_lut.dist_mem[9] [3]), + .D2(\genblk1[6].u_lut.dist_mem[10] [3]), + .D3(\genblk1[6].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[3]) + ); + CC_MX4 _2418_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [3]), + .D1(\genblk1[6].u_lut.dist_mem[13] [3]), + .D2(\genblk1[6].u_lut.dist_mem[14] [3]), + .D3(\genblk1[6].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[3]) + ); + CC_MX4 _2419_ ( + .D0(_0199_[3]), + .D1(_0200_[3]), + .D2(_0201_[3]), + .D3(_0202_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [3]) + ); + CC_MX4 _2420_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [4]), + .D1(\genblk1[6].u_lut.dist_mem[1] [4]), + .D2(\genblk1[6].u_lut.dist_mem[2] [4]), + .D3(\genblk1[6].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[4]) + ); + CC_MX4 _2421_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [4]), + .D1(\genblk1[6].u_lut.dist_mem[5] [4]), + .D2(\genblk1[6].u_lut.dist_mem[6] [4]), + .D3(\genblk1[6].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[4]) + ); + CC_MX4 _2422_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [4]), + .D1(\genblk1[6].u_lut.dist_mem[9] [4]), + .D2(\genblk1[6].u_lut.dist_mem[10] [4]), + .D3(\genblk1[6].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[4]) + ); + CC_MX4 _2423_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [4]), + .D1(\genblk1[6].u_lut.dist_mem[13] [4]), + .D2(\genblk1[6].u_lut.dist_mem[14] [4]), + .D3(\genblk1[6].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[4]) + ); + CC_MX4 _2424_ ( + .D0(_0199_[4]), + .D1(_0200_[4]), + .D2(_0201_[4]), + .D3(_0202_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [4]) + ); + CC_MX4 _2425_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [5]), + .D1(\genblk1[6].u_lut.dist_mem[1] [5]), + .D2(\genblk1[6].u_lut.dist_mem[2] [5]), + .D3(\genblk1[6].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[5]) + ); + CC_MX4 _2426_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [5]), + .D1(\genblk1[6].u_lut.dist_mem[5] [5]), + .D2(\genblk1[6].u_lut.dist_mem[6] [5]), + .D3(\genblk1[6].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[5]) + ); + CC_MX4 _2427_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [5]), + .D1(\genblk1[6].u_lut.dist_mem[9] [5]), + .D2(\genblk1[6].u_lut.dist_mem[10] [5]), + .D3(\genblk1[6].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[5]) + ); + CC_MX4 _2428_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [5]), + .D1(\genblk1[6].u_lut.dist_mem[13] [5]), + .D2(\genblk1[6].u_lut.dist_mem[14] [5]), + .D3(\genblk1[6].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[5]) + ); + CC_MX4 _2429_ ( + .D0(_0199_[5]), + .D1(_0200_[5]), + .D2(_0201_[5]), + .D3(_0202_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [5]) + ); + CC_MX4 _2430_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [6]), + .D1(\genblk1[6].u_lut.dist_mem[1] [6]), + .D2(\genblk1[6].u_lut.dist_mem[2] [6]), + .D3(\genblk1[6].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[6]) + ); + CC_MX4 _2431_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [6]), + .D1(\genblk1[6].u_lut.dist_mem[5] [6]), + .D2(\genblk1[6].u_lut.dist_mem[6] [6]), + .D3(\genblk1[6].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[6]) + ); + CC_MX4 _2432_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [6]), + .D1(\genblk1[6].u_lut.dist_mem[9] [6]), + .D2(\genblk1[6].u_lut.dist_mem[10] [6]), + .D3(\genblk1[6].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[6]) + ); + CC_MX4 _2433_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [6]), + .D1(\genblk1[6].u_lut.dist_mem[13] [6]), + .D2(\genblk1[6].u_lut.dist_mem[14] [6]), + .D3(\genblk1[6].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[6]) + ); + CC_MX4 _2434_ ( + .D0(_0199_[6]), + .D1(_0200_[6]), + .D2(_0201_[6]), + .D3(_0202_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [6]) + ); + CC_MX4 _2435_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [7]), + .D1(\genblk1[6].u_lut.dist_mem[1] [7]), + .D2(\genblk1[6].u_lut.dist_mem[2] [7]), + .D3(\genblk1[6].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[7]) + ); + CC_MX4 _2436_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [7]), + .D1(\genblk1[6].u_lut.dist_mem[5] [7]), + .D2(\genblk1[6].u_lut.dist_mem[6] [7]), + .D3(\genblk1[6].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[7]) + ); + CC_MX4 _2437_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [7]), + .D1(\genblk1[6].u_lut.dist_mem[9] [7]), + .D2(\genblk1[6].u_lut.dist_mem[10] [7]), + .D3(\genblk1[6].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[7]) + ); + CC_MX4 _2438_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [7]), + .D1(\genblk1[6].u_lut.dist_mem[13] [7]), + .D2(\genblk1[6].u_lut.dist_mem[14] [7]), + .D3(\genblk1[6].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[7]) + ); + CC_MX4 _2439_ ( + .D0(_0199_[7]), + .D1(_0200_[7]), + .D2(_0201_[7]), + .D3(_0202_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [7]) + ); + CC_MX4 _2440_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [8]), + .D1(\genblk1[6].u_lut.dist_mem[1] [8]), + .D2(\genblk1[6].u_lut.dist_mem[2] [8]), + .D3(\genblk1[6].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[8]) + ); + CC_MX4 _2441_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [8]), + .D1(\genblk1[6].u_lut.dist_mem[5] [8]), + .D2(\genblk1[6].u_lut.dist_mem[6] [8]), + .D3(\genblk1[6].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[8]) + ); + CC_MX4 _2442_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [8]), + .D1(\genblk1[6].u_lut.dist_mem[9] [8]), + .D2(\genblk1[6].u_lut.dist_mem[10] [8]), + .D3(\genblk1[6].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[8]) + ); + CC_MX4 _2443_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [8]), + .D1(\genblk1[6].u_lut.dist_mem[13] [8]), + .D2(\genblk1[6].u_lut.dist_mem[14] [8]), + .D3(\genblk1[6].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[8]) + ); + CC_MX4 _2444_ ( + .D0(_0199_[8]), + .D1(_0200_[8]), + .D2(_0201_[8]), + .D3(_0202_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [8]) + ); + CC_MX4 _2445_ ( + .D0(\genblk1[6].u_lut.dist_mem[0] [9]), + .D1(\genblk1[6].u_lut.dist_mem[1] [9]), + .D2(\genblk1[6].u_lut.dist_mem[2] [9]), + .D3(\genblk1[6].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0199_[9]) + ); + CC_MX4 _2446_ ( + .D0(\genblk1[6].u_lut.dist_mem[4] [9]), + .D1(\genblk1[6].u_lut.dist_mem[5] [9]), + .D2(\genblk1[6].u_lut.dist_mem[6] [9]), + .D3(\genblk1[6].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0200_[9]) + ); + CC_MX4 _2447_ ( + .D0(\genblk1[6].u_lut.dist_mem[8] [9]), + .D1(\genblk1[6].u_lut.dist_mem[9] [9]), + .D2(\genblk1[6].u_lut.dist_mem[10] [9]), + .D3(\genblk1[6].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0201_[9]) + ); + CC_MX4 _2448_ ( + .D0(\genblk1[6].u_lut.dist_mem[12] [9]), + .D1(\genblk1[6].u_lut.dist_mem[13] [9]), + .D2(\genblk1[6].u_lut.dist_mem[14] [9]), + .D3(\genblk1[6].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0202_[9]) + ); + CC_MX4 _2449_ ( + .D0(_0199_[9]), + .D1(_0200_[9]), + .D2(_0201_[9]), + .D3(_0202_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[6].u_lut.rdat [9]) + ); + CC_MX4 _2450_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [0]), + .D1(\genblk1[7].u_lut.dist_mem[1] [0]), + .D2(\genblk1[7].u_lut.dist_mem[2] [0]), + .D3(\genblk1[7].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[0]) + ); + CC_MX4 _2451_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [0]), + .D1(\genblk1[7].u_lut.dist_mem[5] [0]), + .D2(\genblk1[7].u_lut.dist_mem[6] [0]), + .D3(\genblk1[7].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[0]) + ); + CC_MX4 _2452_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [0]), + .D1(\genblk1[7].u_lut.dist_mem[9] [0]), + .D2(\genblk1[7].u_lut.dist_mem[10] [0]), + .D3(\genblk1[7].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[0]) + ); + CC_MX4 _2453_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [0]), + .D1(\genblk1[7].u_lut.dist_mem[13] [0]), + .D2(\genblk1[7].u_lut.dist_mem[14] [0]), + .D3(\genblk1[7].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[0]) + ); + CC_MX4 _2454_ ( + .D0(_0203_[0]), + .D1(_0204_[0]), + .D2(_0205_[0]), + .D3(_0206_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [0]) + ); + CC_MX4 _2455_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [1]), + .D1(\genblk1[7].u_lut.dist_mem[1] [1]), + .D2(\genblk1[7].u_lut.dist_mem[2] [1]), + .D3(\genblk1[7].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[1]) + ); + CC_MX4 _2456_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [1]), + .D1(\genblk1[7].u_lut.dist_mem[5] [1]), + .D2(\genblk1[7].u_lut.dist_mem[6] [1]), + .D3(\genblk1[7].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[1]) + ); + CC_MX4 _2457_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [1]), + .D1(\genblk1[7].u_lut.dist_mem[9] [1]), + .D2(\genblk1[7].u_lut.dist_mem[10] [1]), + .D3(\genblk1[7].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[1]) + ); + CC_MX4 _2458_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [1]), + .D1(\genblk1[7].u_lut.dist_mem[13] [1]), + .D2(\genblk1[7].u_lut.dist_mem[14] [1]), + .D3(\genblk1[7].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[1]) + ); + CC_MX4 _2459_ ( + .D0(_0203_[1]), + .D1(_0204_[1]), + .D2(_0205_[1]), + .D3(_0206_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [1]) + ); + CC_MX4 _2460_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [2]), + .D1(\genblk1[7].u_lut.dist_mem[1] [2]), + .D2(\genblk1[7].u_lut.dist_mem[2] [2]), + .D3(\genblk1[7].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[2]) + ); + CC_MX4 _2461_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [2]), + .D1(\genblk1[7].u_lut.dist_mem[5] [2]), + .D2(\genblk1[7].u_lut.dist_mem[6] [2]), + .D3(\genblk1[7].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[2]) + ); + CC_MX4 _2462_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [2]), + .D1(\genblk1[7].u_lut.dist_mem[9] [2]), + .D2(\genblk1[7].u_lut.dist_mem[10] [2]), + .D3(\genblk1[7].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[2]) + ); + CC_MX4 _2463_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [2]), + .D1(\genblk1[7].u_lut.dist_mem[13] [2]), + .D2(\genblk1[7].u_lut.dist_mem[14] [2]), + .D3(\genblk1[7].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[2]) + ); + CC_MX4 _2464_ ( + .D0(_0203_[2]), + .D1(_0204_[2]), + .D2(_0205_[2]), + .D3(_0206_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [2]) + ); + CC_MX4 _2465_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [3]), + .D1(\genblk1[7].u_lut.dist_mem[1] [3]), + .D2(\genblk1[7].u_lut.dist_mem[2] [3]), + .D3(\genblk1[7].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[3]) + ); + CC_MX4 _2466_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [3]), + .D1(\genblk1[7].u_lut.dist_mem[5] [3]), + .D2(\genblk1[7].u_lut.dist_mem[6] [3]), + .D3(\genblk1[7].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[3]) + ); + CC_MX4 _2467_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [3]), + .D1(\genblk1[7].u_lut.dist_mem[9] [3]), + .D2(\genblk1[7].u_lut.dist_mem[10] [3]), + .D3(\genblk1[7].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[3]) + ); + CC_MX4 _2468_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [3]), + .D1(\genblk1[7].u_lut.dist_mem[13] [3]), + .D2(\genblk1[7].u_lut.dist_mem[14] [3]), + .D3(\genblk1[7].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[3]) + ); + CC_MX4 _2469_ ( + .D0(_0203_[3]), + .D1(_0204_[3]), + .D2(_0205_[3]), + .D3(_0206_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [3]) + ); + CC_MX4 _2470_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [4]), + .D1(\genblk1[7].u_lut.dist_mem[1] [4]), + .D2(\genblk1[7].u_lut.dist_mem[2] [4]), + .D3(\genblk1[7].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[4]) + ); + CC_MX4 _2471_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [4]), + .D1(\genblk1[7].u_lut.dist_mem[5] [4]), + .D2(\genblk1[7].u_lut.dist_mem[6] [4]), + .D3(\genblk1[7].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[4]) + ); + CC_MX4 _2472_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [4]), + .D1(\genblk1[7].u_lut.dist_mem[9] [4]), + .D2(\genblk1[7].u_lut.dist_mem[10] [4]), + .D3(\genblk1[7].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[4]) + ); + CC_MX4 _2473_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [4]), + .D1(\genblk1[7].u_lut.dist_mem[13] [4]), + .D2(\genblk1[7].u_lut.dist_mem[14] [4]), + .D3(\genblk1[7].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[4]) + ); + CC_MX4 _2474_ ( + .D0(_0203_[4]), + .D1(_0204_[4]), + .D2(_0205_[4]), + .D3(_0206_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [4]) + ); + CC_MX4 _2475_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [5]), + .D1(\genblk1[7].u_lut.dist_mem[1] [5]), + .D2(\genblk1[7].u_lut.dist_mem[2] [5]), + .D3(\genblk1[7].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[5]) + ); + CC_MX4 _2476_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [5]), + .D1(\genblk1[7].u_lut.dist_mem[5] [5]), + .D2(\genblk1[7].u_lut.dist_mem[6] [5]), + .D3(\genblk1[7].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[5]) + ); + CC_MX4 _2477_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [5]), + .D1(\genblk1[7].u_lut.dist_mem[9] [5]), + .D2(\genblk1[7].u_lut.dist_mem[10] [5]), + .D3(\genblk1[7].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[5]) + ); + CC_MX4 _2478_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [5]), + .D1(\genblk1[7].u_lut.dist_mem[13] [5]), + .D2(\genblk1[7].u_lut.dist_mem[14] [5]), + .D3(\genblk1[7].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[5]) + ); + CC_MX4 _2479_ ( + .D0(_0203_[5]), + .D1(_0204_[5]), + .D2(_0205_[5]), + .D3(_0206_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [5]) + ); + CC_MX4 _2480_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [6]), + .D1(\genblk1[7].u_lut.dist_mem[1] [6]), + .D2(\genblk1[7].u_lut.dist_mem[2] [6]), + .D3(\genblk1[7].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[6]) + ); + CC_MX4 _2481_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [6]), + .D1(\genblk1[7].u_lut.dist_mem[5] [6]), + .D2(\genblk1[7].u_lut.dist_mem[6] [6]), + .D3(\genblk1[7].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[6]) + ); + CC_MX4 _2482_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [6]), + .D1(\genblk1[7].u_lut.dist_mem[9] [6]), + .D2(\genblk1[7].u_lut.dist_mem[10] [6]), + .D3(\genblk1[7].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[6]) + ); + CC_MX4 _2483_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [6]), + .D1(\genblk1[7].u_lut.dist_mem[13] [6]), + .D2(\genblk1[7].u_lut.dist_mem[14] [6]), + .D3(\genblk1[7].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[6]) + ); + CC_MX4 _2484_ ( + .D0(_0203_[6]), + .D1(_0204_[6]), + .D2(_0205_[6]), + .D3(_0206_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [6]) + ); + CC_MX4 _2485_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [7]), + .D1(\genblk1[7].u_lut.dist_mem[1] [7]), + .D2(\genblk1[7].u_lut.dist_mem[2] [7]), + .D3(\genblk1[7].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[7]) + ); + CC_MX4 _2486_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [7]), + .D1(\genblk1[7].u_lut.dist_mem[5] [7]), + .D2(\genblk1[7].u_lut.dist_mem[6] [7]), + .D3(\genblk1[7].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[7]) + ); + CC_MX4 _2487_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [7]), + .D1(\genblk1[7].u_lut.dist_mem[9] [7]), + .D2(\genblk1[7].u_lut.dist_mem[10] [7]), + .D3(\genblk1[7].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[7]) + ); + CC_MX4 _2488_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [7]), + .D1(\genblk1[7].u_lut.dist_mem[13] [7]), + .D2(\genblk1[7].u_lut.dist_mem[14] [7]), + .D3(\genblk1[7].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[7]) + ); + CC_MX4 _2489_ ( + .D0(_0203_[7]), + .D1(_0204_[7]), + .D2(_0205_[7]), + .D3(_0206_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [7]) + ); + CC_MX4 _2490_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [8]), + .D1(\genblk1[7].u_lut.dist_mem[1] [8]), + .D2(\genblk1[7].u_lut.dist_mem[2] [8]), + .D3(\genblk1[7].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[8]) + ); + CC_MX4 _2491_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [8]), + .D1(\genblk1[7].u_lut.dist_mem[5] [8]), + .D2(\genblk1[7].u_lut.dist_mem[6] [8]), + .D3(\genblk1[7].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[8]) + ); + CC_MX4 _2492_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [8]), + .D1(\genblk1[7].u_lut.dist_mem[9] [8]), + .D2(\genblk1[7].u_lut.dist_mem[10] [8]), + .D3(\genblk1[7].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[8]) + ); + CC_MX4 _2493_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [8]), + .D1(\genblk1[7].u_lut.dist_mem[13] [8]), + .D2(\genblk1[7].u_lut.dist_mem[14] [8]), + .D3(\genblk1[7].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[8]) + ); + CC_MX4 _2494_ ( + .D0(_0203_[8]), + .D1(_0204_[8]), + .D2(_0205_[8]), + .D3(_0206_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [8]) + ); + CC_MX4 _2495_ ( + .D0(\genblk1[7].u_lut.dist_mem[0] [9]), + .D1(\genblk1[7].u_lut.dist_mem[1] [9]), + .D2(\genblk1[7].u_lut.dist_mem[2] [9]), + .D3(\genblk1[7].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0203_[9]) + ); + CC_MX4 _2496_ ( + .D0(\genblk1[7].u_lut.dist_mem[4] [9]), + .D1(\genblk1[7].u_lut.dist_mem[5] [9]), + .D2(\genblk1[7].u_lut.dist_mem[6] [9]), + .D3(\genblk1[7].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0204_[9]) + ); + CC_MX4 _2497_ ( + .D0(\genblk1[7].u_lut.dist_mem[8] [9]), + .D1(\genblk1[7].u_lut.dist_mem[9] [9]), + .D2(\genblk1[7].u_lut.dist_mem[10] [9]), + .D3(\genblk1[7].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0205_[9]) + ); + CC_MX4 _2498_ ( + .D0(\genblk1[7].u_lut.dist_mem[12] [9]), + .D1(\genblk1[7].u_lut.dist_mem[13] [9]), + .D2(\genblk1[7].u_lut.dist_mem[14] [9]), + .D3(\genblk1[7].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0206_[9]) + ); + CC_MX4 _2499_ ( + .D0(_0203_[9]), + .D1(_0204_[9]), + .D2(_0205_[9]), + .D3(_0206_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[7].u_lut.rdat [9]) + ); + CC_MX4 _2500_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [0]), + .D1(\genblk1[8].u_lut.dist_mem[1] [0]), + .D2(\genblk1[8].u_lut.dist_mem[2] [0]), + .D3(\genblk1[8].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[0]) + ); + CC_MX4 _2501_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [0]), + .D1(\genblk1[8].u_lut.dist_mem[5] [0]), + .D2(\genblk1[8].u_lut.dist_mem[6] [0]), + .D3(\genblk1[8].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[0]) + ); + CC_MX4 _2502_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [0]), + .D1(\genblk1[8].u_lut.dist_mem[9] [0]), + .D2(\genblk1[8].u_lut.dist_mem[10] [0]), + .D3(\genblk1[8].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[0]) + ); + CC_MX4 _2503_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [0]), + .D1(\genblk1[8].u_lut.dist_mem[13] [0]), + .D2(\genblk1[8].u_lut.dist_mem[14] [0]), + .D3(\genblk1[8].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[0]) + ); + CC_MX4 _2504_ ( + .D0(_0207_[0]), + .D1(_0208_[0]), + .D2(_0209_[0]), + .D3(_0210_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [0]) + ); + CC_MX4 _2505_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [1]), + .D1(\genblk1[8].u_lut.dist_mem[1] [1]), + .D2(\genblk1[8].u_lut.dist_mem[2] [1]), + .D3(\genblk1[8].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[1]) + ); + CC_MX4 _2506_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [1]), + .D1(\genblk1[8].u_lut.dist_mem[5] [1]), + .D2(\genblk1[8].u_lut.dist_mem[6] [1]), + .D3(\genblk1[8].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[1]) + ); + CC_MX4 _2507_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [1]), + .D1(\genblk1[8].u_lut.dist_mem[9] [1]), + .D2(\genblk1[8].u_lut.dist_mem[10] [1]), + .D3(\genblk1[8].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[1]) + ); + CC_MX4 _2508_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [1]), + .D1(\genblk1[8].u_lut.dist_mem[13] [1]), + .D2(\genblk1[8].u_lut.dist_mem[14] [1]), + .D3(\genblk1[8].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[1]) + ); + CC_MX4 _2509_ ( + .D0(_0207_[1]), + .D1(_0208_[1]), + .D2(_0209_[1]), + .D3(_0210_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [1]) + ); + CC_MX4 _2510_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [2]), + .D1(\genblk1[8].u_lut.dist_mem[1] [2]), + .D2(\genblk1[8].u_lut.dist_mem[2] [2]), + .D3(\genblk1[8].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[2]) + ); + CC_MX4 _2511_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [2]), + .D1(\genblk1[8].u_lut.dist_mem[5] [2]), + .D2(\genblk1[8].u_lut.dist_mem[6] [2]), + .D3(\genblk1[8].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[2]) + ); + CC_MX4 _2512_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [2]), + .D1(\genblk1[8].u_lut.dist_mem[9] [2]), + .D2(\genblk1[8].u_lut.dist_mem[10] [2]), + .D3(\genblk1[8].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[2]) + ); + CC_MX4 _2513_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [2]), + .D1(\genblk1[8].u_lut.dist_mem[13] [2]), + .D2(\genblk1[8].u_lut.dist_mem[14] [2]), + .D3(\genblk1[8].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[2]) + ); + CC_MX4 _2514_ ( + .D0(_0207_[2]), + .D1(_0208_[2]), + .D2(_0209_[2]), + .D3(_0210_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [2]) + ); + CC_MX4 _2515_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [3]), + .D1(\genblk1[8].u_lut.dist_mem[1] [3]), + .D2(\genblk1[8].u_lut.dist_mem[2] [3]), + .D3(\genblk1[8].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[3]) + ); + CC_MX4 _2516_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [3]), + .D1(\genblk1[8].u_lut.dist_mem[5] [3]), + .D2(\genblk1[8].u_lut.dist_mem[6] [3]), + .D3(\genblk1[8].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[3]) + ); + CC_MX4 _2517_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [3]), + .D1(\genblk1[8].u_lut.dist_mem[9] [3]), + .D2(\genblk1[8].u_lut.dist_mem[10] [3]), + .D3(\genblk1[8].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[3]) + ); + CC_MX4 _2518_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [3]), + .D1(\genblk1[8].u_lut.dist_mem[13] [3]), + .D2(\genblk1[8].u_lut.dist_mem[14] [3]), + .D3(\genblk1[8].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[3]) + ); + CC_MX4 _2519_ ( + .D0(_0207_[3]), + .D1(_0208_[3]), + .D2(_0209_[3]), + .D3(_0210_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [3]) + ); + CC_MX4 _2520_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [4]), + .D1(\genblk1[8].u_lut.dist_mem[1] [4]), + .D2(\genblk1[8].u_lut.dist_mem[2] [4]), + .D3(\genblk1[8].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[4]) + ); + CC_MX4 _2521_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [4]), + .D1(\genblk1[8].u_lut.dist_mem[5] [4]), + .D2(\genblk1[8].u_lut.dist_mem[6] [4]), + .D3(\genblk1[8].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[4]) + ); + CC_MX4 _2522_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [4]), + .D1(\genblk1[8].u_lut.dist_mem[9] [4]), + .D2(\genblk1[8].u_lut.dist_mem[10] [4]), + .D3(\genblk1[8].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[4]) + ); + CC_MX4 _2523_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [4]), + .D1(\genblk1[8].u_lut.dist_mem[13] [4]), + .D2(\genblk1[8].u_lut.dist_mem[14] [4]), + .D3(\genblk1[8].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[4]) + ); + CC_MX4 _2524_ ( + .D0(_0207_[4]), + .D1(_0208_[4]), + .D2(_0209_[4]), + .D3(_0210_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [4]) + ); + CC_MX4 _2525_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [5]), + .D1(\genblk1[8].u_lut.dist_mem[1] [5]), + .D2(\genblk1[8].u_lut.dist_mem[2] [5]), + .D3(\genblk1[8].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[5]) + ); + CC_MX4 _2526_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [5]), + .D1(\genblk1[8].u_lut.dist_mem[5] [5]), + .D2(\genblk1[8].u_lut.dist_mem[6] [5]), + .D3(\genblk1[8].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[5]) + ); + CC_MX4 _2527_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [5]), + .D1(\genblk1[8].u_lut.dist_mem[9] [5]), + .D2(\genblk1[8].u_lut.dist_mem[10] [5]), + .D3(\genblk1[8].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[5]) + ); + CC_MX4 _2528_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [5]), + .D1(\genblk1[8].u_lut.dist_mem[13] [5]), + .D2(\genblk1[8].u_lut.dist_mem[14] [5]), + .D3(\genblk1[8].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[5]) + ); + CC_MX4 _2529_ ( + .D0(_0207_[5]), + .D1(_0208_[5]), + .D2(_0209_[5]), + .D3(_0210_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [5]) + ); + CC_MX4 _2530_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [6]), + .D1(\genblk1[8].u_lut.dist_mem[1] [6]), + .D2(\genblk1[8].u_lut.dist_mem[2] [6]), + .D3(\genblk1[8].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[6]) + ); + CC_MX4 _2531_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [6]), + .D1(\genblk1[8].u_lut.dist_mem[5] [6]), + .D2(\genblk1[8].u_lut.dist_mem[6] [6]), + .D3(\genblk1[8].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[6]) + ); + CC_MX4 _2532_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [6]), + .D1(\genblk1[8].u_lut.dist_mem[9] [6]), + .D2(\genblk1[8].u_lut.dist_mem[10] [6]), + .D3(\genblk1[8].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[6]) + ); + CC_MX4 _2533_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [6]), + .D1(\genblk1[8].u_lut.dist_mem[13] [6]), + .D2(\genblk1[8].u_lut.dist_mem[14] [6]), + .D3(\genblk1[8].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[6]) + ); + CC_MX4 _2534_ ( + .D0(_0207_[6]), + .D1(_0208_[6]), + .D2(_0209_[6]), + .D3(_0210_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [6]) + ); + CC_MX4 _2535_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [7]), + .D1(\genblk1[8].u_lut.dist_mem[1] [7]), + .D2(\genblk1[8].u_lut.dist_mem[2] [7]), + .D3(\genblk1[8].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[7]) + ); + CC_MX4 _2536_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [7]), + .D1(\genblk1[8].u_lut.dist_mem[5] [7]), + .D2(\genblk1[8].u_lut.dist_mem[6] [7]), + .D3(\genblk1[8].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[7]) + ); + CC_MX4 _2537_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [7]), + .D1(\genblk1[8].u_lut.dist_mem[9] [7]), + .D2(\genblk1[8].u_lut.dist_mem[10] [7]), + .D3(\genblk1[8].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[7]) + ); + CC_MX4 _2538_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [7]), + .D1(\genblk1[8].u_lut.dist_mem[13] [7]), + .D2(\genblk1[8].u_lut.dist_mem[14] [7]), + .D3(\genblk1[8].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[7]) + ); + CC_MX4 _2539_ ( + .D0(_0207_[7]), + .D1(_0208_[7]), + .D2(_0209_[7]), + .D3(_0210_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [7]) + ); + CC_MX4 _2540_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [8]), + .D1(\genblk1[8].u_lut.dist_mem[1] [8]), + .D2(\genblk1[8].u_lut.dist_mem[2] [8]), + .D3(\genblk1[8].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[8]) + ); + CC_MX4 _2541_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [8]), + .D1(\genblk1[8].u_lut.dist_mem[5] [8]), + .D2(\genblk1[8].u_lut.dist_mem[6] [8]), + .D3(\genblk1[8].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[8]) + ); + CC_MX4 _2542_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [8]), + .D1(\genblk1[8].u_lut.dist_mem[9] [8]), + .D2(\genblk1[8].u_lut.dist_mem[10] [8]), + .D3(\genblk1[8].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[8]) + ); + CC_MX4 _2543_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [8]), + .D1(\genblk1[8].u_lut.dist_mem[13] [8]), + .D2(\genblk1[8].u_lut.dist_mem[14] [8]), + .D3(\genblk1[8].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[8]) + ); + CC_MX4 _2544_ ( + .D0(_0207_[8]), + .D1(_0208_[8]), + .D2(_0209_[8]), + .D3(_0210_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [8]) + ); + CC_MX4 _2545_ ( + .D0(\genblk1[8].u_lut.dist_mem[0] [9]), + .D1(\genblk1[8].u_lut.dist_mem[1] [9]), + .D2(\genblk1[8].u_lut.dist_mem[2] [9]), + .D3(\genblk1[8].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0207_[9]) + ); + CC_MX4 _2546_ ( + .D0(\genblk1[8].u_lut.dist_mem[4] [9]), + .D1(\genblk1[8].u_lut.dist_mem[5] [9]), + .D2(\genblk1[8].u_lut.dist_mem[6] [9]), + .D3(\genblk1[8].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0208_[9]) + ); + CC_MX4 _2547_ ( + .D0(\genblk1[8].u_lut.dist_mem[8] [9]), + .D1(\genblk1[8].u_lut.dist_mem[9] [9]), + .D2(\genblk1[8].u_lut.dist_mem[10] [9]), + .D3(\genblk1[8].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0209_[9]) + ); + CC_MX4 _2548_ ( + .D0(\genblk1[8].u_lut.dist_mem[12] [9]), + .D1(\genblk1[8].u_lut.dist_mem[13] [9]), + .D2(\genblk1[8].u_lut.dist_mem[14] [9]), + .D3(\genblk1[8].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0210_[9]) + ); + CC_MX4 _2549_ ( + .D0(_0207_[9]), + .D1(_0208_[9]), + .D2(_0209_[9]), + .D3(_0210_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[8].u_lut.rdat [9]) + ); + CC_MX4 _2550_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [0]), + .D1(\genblk1[9].u_lut.dist_mem[1] [0]), + .D2(\genblk1[9].u_lut.dist_mem[2] [0]), + .D3(\genblk1[9].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[0]) + ); + CC_MX4 _2551_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [0]), + .D1(\genblk1[9].u_lut.dist_mem[5] [0]), + .D2(\genblk1[9].u_lut.dist_mem[6] [0]), + .D3(\genblk1[9].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[0]) + ); + CC_MX4 _2552_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [0]), + .D1(\genblk1[9].u_lut.dist_mem[9] [0]), + .D2(\genblk1[9].u_lut.dist_mem[10] [0]), + .D3(\genblk1[9].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[0]) + ); + CC_MX4 _2553_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [0]), + .D1(\genblk1[9].u_lut.dist_mem[13] [0]), + .D2(\genblk1[9].u_lut.dist_mem[14] [0]), + .D3(\genblk1[9].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[0]) + ); + CC_MX4 _2554_ ( + .D0(_0211_[0]), + .D1(_0212_[0]), + .D2(_0213_[0]), + .D3(_0214_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [0]) + ); + CC_MX4 _2555_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [1]), + .D1(\genblk1[9].u_lut.dist_mem[1] [1]), + .D2(\genblk1[9].u_lut.dist_mem[2] [1]), + .D3(\genblk1[9].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[1]) + ); + CC_MX4 _2556_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [1]), + .D1(\genblk1[9].u_lut.dist_mem[5] [1]), + .D2(\genblk1[9].u_lut.dist_mem[6] [1]), + .D3(\genblk1[9].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[1]) + ); + CC_MX4 _2557_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [1]), + .D1(\genblk1[9].u_lut.dist_mem[9] [1]), + .D2(\genblk1[9].u_lut.dist_mem[10] [1]), + .D3(\genblk1[9].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[1]) + ); + CC_MX4 _2558_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [1]), + .D1(\genblk1[9].u_lut.dist_mem[13] [1]), + .D2(\genblk1[9].u_lut.dist_mem[14] [1]), + .D3(\genblk1[9].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[1]) + ); + CC_MX4 _2559_ ( + .D0(_0211_[1]), + .D1(_0212_[1]), + .D2(_0213_[1]), + .D3(_0214_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [1]) + ); + CC_MX4 _2560_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [2]), + .D1(\genblk1[9].u_lut.dist_mem[1] [2]), + .D2(\genblk1[9].u_lut.dist_mem[2] [2]), + .D3(\genblk1[9].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[2]) + ); + CC_MX4 _2561_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [2]), + .D1(\genblk1[9].u_lut.dist_mem[5] [2]), + .D2(\genblk1[9].u_lut.dist_mem[6] [2]), + .D3(\genblk1[9].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[2]) + ); + CC_MX4 _2562_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [2]), + .D1(\genblk1[9].u_lut.dist_mem[9] [2]), + .D2(\genblk1[9].u_lut.dist_mem[10] [2]), + .D3(\genblk1[9].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[2]) + ); + CC_MX4 _2563_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [2]), + .D1(\genblk1[9].u_lut.dist_mem[13] [2]), + .D2(\genblk1[9].u_lut.dist_mem[14] [2]), + .D3(\genblk1[9].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[2]) + ); + CC_MX4 _2564_ ( + .D0(_0211_[2]), + .D1(_0212_[2]), + .D2(_0213_[2]), + .D3(_0214_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [2]) + ); + CC_MX4 _2565_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [3]), + .D1(\genblk1[9].u_lut.dist_mem[1] [3]), + .D2(\genblk1[9].u_lut.dist_mem[2] [3]), + .D3(\genblk1[9].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[3]) + ); + CC_MX4 _2566_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [3]), + .D1(\genblk1[9].u_lut.dist_mem[5] [3]), + .D2(\genblk1[9].u_lut.dist_mem[6] [3]), + .D3(\genblk1[9].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[3]) + ); + CC_MX4 _2567_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [3]), + .D1(\genblk1[9].u_lut.dist_mem[9] [3]), + .D2(\genblk1[9].u_lut.dist_mem[10] [3]), + .D3(\genblk1[9].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[3]) + ); + CC_MX4 _2568_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [3]), + .D1(\genblk1[9].u_lut.dist_mem[13] [3]), + .D2(\genblk1[9].u_lut.dist_mem[14] [3]), + .D3(\genblk1[9].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[3]) + ); + CC_MX4 _2569_ ( + .D0(_0211_[3]), + .D1(_0212_[3]), + .D2(_0213_[3]), + .D3(_0214_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [3]) + ); + CC_MX4 _2570_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [4]), + .D1(\genblk1[9].u_lut.dist_mem[1] [4]), + .D2(\genblk1[9].u_lut.dist_mem[2] [4]), + .D3(\genblk1[9].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[4]) + ); + CC_MX4 _2571_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [4]), + .D1(\genblk1[9].u_lut.dist_mem[5] [4]), + .D2(\genblk1[9].u_lut.dist_mem[6] [4]), + .D3(\genblk1[9].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[4]) + ); + CC_MX4 _2572_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [4]), + .D1(\genblk1[9].u_lut.dist_mem[9] [4]), + .D2(\genblk1[9].u_lut.dist_mem[10] [4]), + .D3(\genblk1[9].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[4]) + ); + CC_MX4 _2573_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [4]), + .D1(\genblk1[9].u_lut.dist_mem[13] [4]), + .D2(\genblk1[9].u_lut.dist_mem[14] [4]), + .D3(\genblk1[9].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[4]) + ); + CC_MX4 _2574_ ( + .D0(_0211_[4]), + .D1(_0212_[4]), + .D2(_0213_[4]), + .D3(_0214_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [4]) + ); + CC_MX4 _2575_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [5]), + .D1(\genblk1[9].u_lut.dist_mem[1] [5]), + .D2(\genblk1[9].u_lut.dist_mem[2] [5]), + .D3(\genblk1[9].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[5]) + ); + CC_MX4 _2576_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [5]), + .D1(\genblk1[9].u_lut.dist_mem[5] [5]), + .D2(\genblk1[9].u_lut.dist_mem[6] [5]), + .D3(\genblk1[9].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[5]) + ); + CC_MX4 _2577_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [5]), + .D1(\genblk1[9].u_lut.dist_mem[9] [5]), + .D2(\genblk1[9].u_lut.dist_mem[10] [5]), + .D3(\genblk1[9].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[5]) + ); + CC_MX4 _2578_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [5]), + .D1(\genblk1[9].u_lut.dist_mem[13] [5]), + .D2(\genblk1[9].u_lut.dist_mem[14] [5]), + .D3(\genblk1[9].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[5]) + ); + CC_MX4 _2579_ ( + .D0(_0211_[5]), + .D1(_0212_[5]), + .D2(_0213_[5]), + .D3(_0214_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [5]) + ); + CC_MX4 _2580_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [6]), + .D1(\genblk1[9].u_lut.dist_mem[1] [6]), + .D2(\genblk1[9].u_lut.dist_mem[2] [6]), + .D3(\genblk1[9].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[6]) + ); + CC_MX4 _2581_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [6]), + .D1(\genblk1[9].u_lut.dist_mem[5] [6]), + .D2(\genblk1[9].u_lut.dist_mem[6] [6]), + .D3(\genblk1[9].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[6]) + ); + CC_MX4 _2582_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [6]), + .D1(\genblk1[9].u_lut.dist_mem[9] [6]), + .D2(\genblk1[9].u_lut.dist_mem[10] [6]), + .D3(\genblk1[9].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[6]) + ); + CC_MX4 _2583_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [6]), + .D1(\genblk1[9].u_lut.dist_mem[13] [6]), + .D2(\genblk1[9].u_lut.dist_mem[14] [6]), + .D3(\genblk1[9].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[6]) + ); + CC_MX4 _2584_ ( + .D0(_0211_[6]), + .D1(_0212_[6]), + .D2(_0213_[6]), + .D3(_0214_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [6]) + ); + CC_MX4 _2585_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [7]), + .D1(\genblk1[9].u_lut.dist_mem[1] [7]), + .D2(\genblk1[9].u_lut.dist_mem[2] [7]), + .D3(\genblk1[9].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[7]) + ); + CC_MX4 _2586_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [7]), + .D1(\genblk1[9].u_lut.dist_mem[5] [7]), + .D2(\genblk1[9].u_lut.dist_mem[6] [7]), + .D3(\genblk1[9].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[7]) + ); + CC_MX4 _2587_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [7]), + .D1(\genblk1[9].u_lut.dist_mem[9] [7]), + .D2(\genblk1[9].u_lut.dist_mem[10] [7]), + .D3(\genblk1[9].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[7]) + ); + CC_MX4 _2588_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [7]), + .D1(\genblk1[9].u_lut.dist_mem[13] [7]), + .D2(\genblk1[9].u_lut.dist_mem[14] [7]), + .D3(\genblk1[9].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[7]) + ); + CC_MX4 _2589_ ( + .D0(_0211_[7]), + .D1(_0212_[7]), + .D2(_0213_[7]), + .D3(_0214_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [7]) + ); + CC_MX4 _2590_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [8]), + .D1(\genblk1[9].u_lut.dist_mem[1] [8]), + .D2(\genblk1[9].u_lut.dist_mem[2] [8]), + .D3(\genblk1[9].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[8]) + ); + CC_MX4 _2591_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [8]), + .D1(\genblk1[9].u_lut.dist_mem[5] [8]), + .D2(\genblk1[9].u_lut.dist_mem[6] [8]), + .D3(\genblk1[9].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[8]) + ); + CC_MX4 _2592_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [8]), + .D1(\genblk1[9].u_lut.dist_mem[9] [8]), + .D2(\genblk1[9].u_lut.dist_mem[10] [8]), + .D3(\genblk1[9].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[8]) + ); + CC_MX4 _2593_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [8]), + .D1(\genblk1[9].u_lut.dist_mem[13] [8]), + .D2(\genblk1[9].u_lut.dist_mem[14] [8]), + .D3(\genblk1[9].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[8]) + ); + CC_MX4 _2594_ ( + .D0(_0211_[8]), + .D1(_0212_[8]), + .D2(_0213_[8]), + .D3(_0214_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [8]) + ); + CC_MX4 _2595_ ( + .D0(\genblk1[9].u_lut.dist_mem[0] [9]), + .D1(\genblk1[9].u_lut.dist_mem[1] [9]), + .D2(\genblk1[9].u_lut.dist_mem[2] [9]), + .D3(\genblk1[9].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0211_[9]) + ); + CC_MX4 _2596_ ( + .D0(\genblk1[9].u_lut.dist_mem[4] [9]), + .D1(\genblk1[9].u_lut.dist_mem[5] [9]), + .D2(\genblk1[9].u_lut.dist_mem[6] [9]), + .D3(\genblk1[9].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0212_[9]) + ); + CC_MX4 _2597_ ( + .D0(\genblk1[9].u_lut.dist_mem[8] [9]), + .D1(\genblk1[9].u_lut.dist_mem[9] [9]), + .D2(\genblk1[9].u_lut.dist_mem[10] [9]), + .D3(\genblk1[9].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0213_[9]) + ); + CC_MX4 _2598_ ( + .D0(\genblk1[9].u_lut.dist_mem[12] [9]), + .D1(\genblk1[9].u_lut.dist_mem[13] [9]), + .D2(\genblk1[9].u_lut.dist_mem[14] [9]), + .D3(\genblk1[9].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0214_[9]) + ); + CC_MX4 _2599_ ( + .D0(_0211_[9]), + .D1(_0212_[9]), + .D2(_0213_[9]), + .D3(_0214_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[9].u_lut.rdat [9]) + ); + CC_MX4 _2600_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [0]), + .D1(\genblk1[0].u_lut.dist_mem[1] [0]), + .D2(\genblk1[0].u_lut.dist_mem[2] [0]), + .D3(\genblk1[0].u_lut.dist_mem[3] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[0]) + ); + CC_MX4 _2601_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [0]), + .D1(\genblk1[0].u_lut.dist_mem[5] [0]), + .D2(\genblk1[0].u_lut.dist_mem[6] [0]), + .D3(\genblk1[0].u_lut.dist_mem[7] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[0]) + ); + CC_MX4 _2602_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [0]), + .D1(\genblk1[0].u_lut.dist_mem[9] [0]), + .D2(\genblk1[0].u_lut.dist_mem[10] [0]), + .D3(\genblk1[0].u_lut.dist_mem[11] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[0]) + ); + CC_MX4 _2603_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [0]), + .D1(\genblk1[0].u_lut.dist_mem[13] [0]), + .D2(\genblk1[0].u_lut.dist_mem[14] [0]), + .D3(\genblk1[0].u_lut.dist_mem[15] [0]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[0]) + ); + CC_MX4 _2604_ ( + .D0(_0175_[0]), + .D1(_0176_[0]), + .D2(_0177_[0]), + .D3(_0178_[0]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [0]) + ); + CC_MX4 _2605_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [1]), + .D1(\genblk1[0].u_lut.dist_mem[1] [1]), + .D2(\genblk1[0].u_lut.dist_mem[2] [1]), + .D3(\genblk1[0].u_lut.dist_mem[3] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[1]) + ); + CC_MX4 _2606_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [1]), + .D1(\genblk1[0].u_lut.dist_mem[5] [1]), + .D2(\genblk1[0].u_lut.dist_mem[6] [1]), + .D3(\genblk1[0].u_lut.dist_mem[7] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[1]) + ); + CC_MX4 _2607_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [1]), + .D1(\genblk1[0].u_lut.dist_mem[9] [1]), + .D2(\genblk1[0].u_lut.dist_mem[10] [1]), + .D3(\genblk1[0].u_lut.dist_mem[11] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[1]) + ); + CC_MX4 _2608_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [1]), + .D1(\genblk1[0].u_lut.dist_mem[13] [1]), + .D2(\genblk1[0].u_lut.dist_mem[14] [1]), + .D3(\genblk1[0].u_lut.dist_mem[15] [1]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[1]) + ); + CC_MX4 _2609_ ( + .D0(_0175_[1]), + .D1(_0176_[1]), + .D2(_0177_[1]), + .D3(_0178_[1]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [1]) + ); + CC_MX4 _2610_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [2]), + .D1(\genblk1[0].u_lut.dist_mem[1] [2]), + .D2(\genblk1[0].u_lut.dist_mem[2] [2]), + .D3(\genblk1[0].u_lut.dist_mem[3] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[2]) + ); + CC_MX4 _2611_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [2]), + .D1(\genblk1[0].u_lut.dist_mem[5] [2]), + .D2(\genblk1[0].u_lut.dist_mem[6] [2]), + .D3(\genblk1[0].u_lut.dist_mem[7] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[2]) + ); + CC_MX4 _2612_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [2]), + .D1(\genblk1[0].u_lut.dist_mem[9] [2]), + .D2(\genblk1[0].u_lut.dist_mem[10] [2]), + .D3(\genblk1[0].u_lut.dist_mem[11] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[2]) + ); + CC_MX4 _2613_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [2]), + .D1(\genblk1[0].u_lut.dist_mem[13] [2]), + .D2(\genblk1[0].u_lut.dist_mem[14] [2]), + .D3(\genblk1[0].u_lut.dist_mem[15] [2]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[2]) + ); + CC_MX4 _2614_ ( + .D0(_0175_[2]), + .D1(_0176_[2]), + .D2(_0177_[2]), + .D3(_0178_[2]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [2]) + ); + CC_MX4 _2615_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [3]), + .D1(\genblk1[0].u_lut.dist_mem[1] [3]), + .D2(\genblk1[0].u_lut.dist_mem[2] [3]), + .D3(\genblk1[0].u_lut.dist_mem[3] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[3]) + ); + CC_MX4 _2616_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [3]), + .D1(\genblk1[0].u_lut.dist_mem[5] [3]), + .D2(\genblk1[0].u_lut.dist_mem[6] [3]), + .D3(\genblk1[0].u_lut.dist_mem[7] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[3]) + ); + CC_MX4 _2617_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [3]), + .D1(\genblk1[0].u_lut.dist_mem[9] [3]), + .D2(\genblk1[0].u_lut.dist_mem[10] [3]), + .D3(\genblk1[0].u_lut.dist_mem[11] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[3]) + ); + CC_MX4 _2618_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [3]), + .D1(\genblk1[0].u_lut.dist_mem[13] [3]), + .D2(\genblk1[0].u_lut.dist_mem[14] [3]), + .D3(\genblk1[0].u_lut.dist_mem[15] [3]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[3]) + ); + CC_MX4 _2619_ ( + .D0(_0175_[3]), + .D1(_0176_[3]), + .D2(_0177_[3]), + .D3(_0178_[3]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [3]) + ); + CC_MX4 _2620_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [4]), + .D1(\genblk1[0].u_lut.dist_mem[1] [4]), + .D2(\genblk1[0].u_lut.dist_mem[2] [4]), + .D3(\genblk1[0].u_lut.dist_mem[3] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[4]) + ); + CC_MX4 _2621_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [4]), + .D1(\genblk1[0].u_lut.dist_mem[5] [4]), + .D2(\genblk1[0].u_lut.dist_mem[6] [4]), + .D3(\genblk1[0].u_lut.dist_mem[7] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[4]) + ); + CC_MX4 _2622_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [4]), + .D1(\genblk1[0].u_lut.dist_mem[9] [4]), + .D2(\genblk1[0].u_lut.dist_mem[10] [4]), + .D3(\genblk1[0].u_lut.dist_mem[11] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[4]) + ); + CC_MX4 _2623_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [4]), + .D1(\genblk1[0].u_lut.dist_mem[13] [4]), + .D2(\genblk1[0].u_lut.dist_mem[14] [4]), + .D3(\genblk1[0].u_lut.dist_mem[15] [4]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[4]) + ); + CC_MX4 _2624_ ( + .D0(_0175_[4]), + .D1(_0176_[4]), + .D2(_0177_[4]), + .D3(_0178_[4]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [4]) + ); + CC_MX4 _2625_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [5]), + .D1(\genblk1[0].u_lut.dist_mem[1] [5]), + .D2(\genblk1[0].u_lut.dist_mem[2] [5]), + .D3(\genblk1[0].u_lut.dist_mem[3] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[5]) + ); + CC_MX4 _2626_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [5]), + .D1(\genblk1[0].u_lut.dist_mem[5] [5]), + .D2(\genblk1[0].u_lut.dist_mem[6] [5]), + .D3(\genblk1[0].u_lut.dist_mem[7] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[5]) + ); + CC_MX4 _2627_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [5]), + .D1(\genblk1[0].u_lut.dist_mem[9] [5]), + .D2(\genblk1[0].u_lut.dist_mem[10] [5]), + .D3(\genblk1[0].u_lut.dist_mem[11] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[5]) + ); + CC_MX4 _2628_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [5]), + .D1(\genblk1[0].u_lut.dist_mem[13] [5]), + .D2(\genblk1[0].u_lut.dist_mem[14] [5]), + .D3(\genblk1[0].u_lut.dist_mem[15] [5]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[5]) + ); + CC_MX4 _2629_ ( + .D0(_0175_[5]), + .D1(_0176_[5]), + .D2(_0177_[5]), + .D3(_0178_[5]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [5]) + ); + CC_MX4 _2630_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [6]), + .D1(\genblk1[0].u_lut.dist_mem[1] [6]), + .D2(\genblk1[0].u_lut.dist_mem[2] [6]), + .D3(\genblk1[0].u_lut.dist_mem[3] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[6]) + ); + CC_MX4 _2631_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [6]), + .D1(\genblk1[0].u_lut.dist_mem[5] [6]), + .D2(\genblk1[0].u_lut.dist_mem[6] [6]), + .D3(\genblk1[0].u_lut.dist_mem[7] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[6]) + ); + CC_MX4 _2632_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [6]), + .D1(\genblk1[0].u_lut.dist_mem[9] [6]), + .D2(\genblk1[0].u_lut.dist_mem[10] [6]), + .D3(\genblk1[0].u_lut.dist_mem[11] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[6]) + ); + CC_MX4 _2633_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [6]), + .D1(\genblk1[0].u_lut.dist_mem[13] [6]), + .D2(\genblk1[0].u_lut.dist_mem[14] [6]), + .D3(\genblk1[0].u_lut.dist_mem[15] [6]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[6]) + ); + CC_MX4 _2634_ ( + .D0(_0175_[6]), + .D1(_0176_[6]), + .D2(_0177_[6]), + .D3(_0178_[6]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [6]) + ); + CC_MX4 _2635_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [7]), + .D1(\genblk1[0].u_lut.dist_mem[1] [7]), + .D2(\genblk1[0].u_lut.dist_mem[2] [7]), + .D3(\genblk1[0].u_lut.dist_mem[3] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[7]) + ); + CC_MX4 _2636_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [7]), + .D1(\genblk1[0].u_lut.dist_mem[5] [7]), + .D2(\genblk1[0].u_lut.dist_mem[6] [7]), + .D3(\genblk1[0].u_lut.dist_mem[7] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[7]) + ); + CC_MX4 _2637_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [7]), + .D1(\genblk1[0].u_lut.dist_mem[9] [7]), + .D2(\genblk1[0].u_lut.dist_mem[10] [7]), + .D3(\genblk1[0].u_lut.dist_mem[11] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[7]) + ); + CC_MX4 _2638_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [7]), + .D1(\genblk1[0].u_lut.dist_mem[13] [7]), + .D2(\genblk1[0].u_lut.dist_mem[14] [7]), + .D3(\genblk1[0].u_lut.dist_mem[15] [7]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[7]) + ); + CC_MX4 _2639_ ( + .D0(_0175_[7]), + .D1(_0176_[7]), + .D2(_0177_[7]), + .D3(_0178_[7]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [7]) + ); + CC_MX4 _2640_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [8]), + .D1(\genblk1[0].u_lut.dist_mem[1] [8]), + .D2(\genblk1[0].u_lut.dist_mem[2] [8]), + .D3(\genblk1[0].u_lut.dist_mem[3] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[8]) + ); + CC_MX4 _2641_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [8]), + .D1(\genblk1[0].u_lut.dist_mem[5] [8]), + .D2(\genblk1[0].u_lut.dist_mem[6] [8]), + .D3(\genblk1[0].u_lut.dist_mem[7] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[8]) + ); + CC_MX4 _2642_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [8]), + .D1(\genblk1[0].u_lut.dist_mem[9] [8]), + .D2(\genblk1[0].u_lut.dist_mem[10] [8]), + .D3(\genblk1[0].u_lut.dist_mem[11] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[8]) + ); + CC_MX4 _2643_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [8]), + .D1(\genblk1[0].u_lut.dist_mem[13] [8]), + .D2(\genblk1[0].u_lut.dist_mem[14] [8]), + .D3(\genblk1[0].u_lut.dist_mem[15] [8]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[8]) + ); + CC_MX4 _2644_ ( + .D0(_0175_[8]), + .D1(_0176_[8]), + .D2(_0177_[8]), + .D3(_0178_[8]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [8]) + ); + CC_MX4 _2645_ ( + .D0(\genblk1[0].u_lut.dist_mem[0] [9]), + .D1(\genblk1[0].u_lut.dist_mem[1] [9]), + .D2(\genblk1[0].u_lut.dist_mem[2] [9]), + .D3(\genblk1[0].u_lut.dist_mem[3] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0175_[9]) + ); + CC_MX4 _2646_ ( + .D0(\genblk1[0].u_lut.dist_mem[4] [9]), + .D1(\genblk1[0].u_lut.dist_mem[5] [9]), + .D2(\genblk1[0].u_lut.dist_mem[6] [9]), + .D3(\genblk1[0].u_lut.dist_mem[7] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0176_[9]) + ); + CC_MX4 _2647_ ( + .D0(\genblk1[0].u_lut.dist_mem[8] [9]), + .D1(\genblk1[0].u_lut.dist_mem[9] [9]), + .D2(\genblk1[0].u_lut.dist_mem[10] [9]), + .D3(\genblk1[0].u_lut.dist_mem[11] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0177_[9]) + ); + CC_MX4 _2648_ ( + .D0(\genblk1[0].u_lut.dist_mem[12] [9]), + .D1(\genblk1[0].u_lut.dist_mem[13] [9]), + .D2(\genblk1[0].u_lut.dist_mem[14] [9]), + .D3(\genblk1[0].u_lut.dist_mem[15] [9]), + .S0(\genblk1[0].u_lut.addr [0]), + .S1(\genblk1[0].u_lut.addr [1]), + .Y(_0178_[9]) + ); + CC_MX4 _2649_ ( + .D0(_0175_[9]), + .D1(_0176_[9]), + .D2(_0177_[9]), + .D3(_0178_[9]), + .S0(\genblk1[0].u_lut.addr [2]), + .S1(\genblk1[0].u_lut.addr [3]), + .Y(\genblk1[0].u_lut.rdat [9]) + ); + CC_IBUF _2650_ ( + .I(addr[0]), + .Y(\genblk1[0].u_lut.addr [0]) + ); + CC_IBUF _2651_ ( + .I(addr[1]), + .Y(\genblk1[0].u_lut.addr [1]) + ); + CC_IBUF _2652_ ( + .I(addr[2]), + .Y(\genblk1[0].u_lut.addr [2]) + ); + CC_IBUF _2653_ ( + .I(addr[3]), + .Y(\genblk1[0].u_lut.addr [3]) + ); + CC_IBUF _2654_ ( + .I(addr[4]), + .Y(_0215_[0]) + ); + CC_IBUF _2655_ ( + .I(addr[5]), + .Y(_0215_[1]) + ); + CC_IBUF _2656_ ( + .I(addr[6]), + .Y(_0215_[2]) + ); + CC_IBUF _2657_ ( + .I(addr[7]), + .Y(_0215_[3]) + ); + CC_IBUF _2658_ ( + .I(clk), + .Y(_0174_) + ); + CC_OBUF _2659_ ( + .A(_0000_), + .O(rdat[0]) + ); + CC_OBUF _2660_ ( + .A(_0001_), + .O(rdat[1]) + ); + CC_OBUF _2661_ ( + .A(_0002_), + .O(rdat[2]) + ); + CC_OBUF _2662_ ( + .A(_0003_), + .O(rdat[3]) + ); + CC_OBUF _2663_ ( + .A(_0004_), + .O(rdat[4]) + ); + CC_OBUF _2664_ ( + .A(_0005_), + .O(rdat[5]) + ); + CC_OBUF _2665_ ( + .A(_0006_), + .O(rdat[6]) + ); + CC_OBUF _2666_ ( + .A(_0007_), + .O(rdat[7]) + ); + CC_OBUF _2667_ ( + .A(_0008_), + .O(rdat[8]) + ); + CC_OBUF _2668_ ( + .A(_0009_), + .O(rdat[9]) + ); + CC_IBUF _2669_ ( + .I(wdat[0]), + .Y(\genblk1[0].u_lut.wdat [0]) + ); + CC_IBUF _2670_ ( + .I(wdat[1]), + .Y(\genblk1[0].u_lut.wdat [1]) + ); + CC_IBUF _2671_ ( + .I(wdat[2]), + .Y(\genblk1[0].u_lut.wdat [2]) + ); + CC_IBUF _2672_ ( + .I(wdat[3]), + .Y(\genblk1[0].u_lut.wdat [3]) + ); + CC_IBUF _2673_ ( + .I(wdat[4]), + .Y(\genblk1[0].u_lut.wdat [4]) + ); + CC_IBUF _2674_ ( + .I(wdat[5]), + .Y(\genblk1[0].u_lut.wdat [5]) + ); + CC_IBUF _2675_ ( + .I(wdat[6]), + .Y(\genblk1[0].u_lut.wdat [6]) + ); + CC_IBUF _2676_ ( + .I(wdat[7]), + .Y(\genblk1[0].u_lut.wdat [7]) + ); + CC_IBUF _2677_ ( + .I(wdat[8]), + .Y(\genblk1[0].u_lut.wdat [8]) + ); + CC_IBUF _2678_ ( + .I(wdat[9]), + .Y(\genblk1[0].u_lut.wdat [9]) + ); + CC_IBUF _2679_ ( + .I(we), + .Y(_0228_[0]) + ); + assign _0170_[4] = 1'h1; + assign _0171_[0] = 1'h1; + assign _0172_[3:0] = _0171_[4:1]; + assign { _0216_[3], _0216_[1] } = { \genblk1[8].u_lut.rdat [0], \genblk1[3].u_lut.rdat [0] }; + assign _0217_[1] = \genblk1[0].u_lut.rdat [0]; + assign { _0218_[3], _0218_[0] } = { \genblk1[4].u_lut.rdat [1], \genblk1[7].u_lut.rdat [1] }; + assign { _0219_[3:2], _0219_[0] } = { \genblk1[3].u_lut.rdat [3], _0216_[0], \genblk1[2].u_lut.rdat [3] }; + assign { _0220_[3], _0220_[1:0] } = { \genblk1[6].u_lut.rdat [3], _0216_[2], \genblk1[8].u_lut.rdat [3] }; + assign { _0222_[3:2], _0222_[0] } = { \genblk1[6].u_lut.rdat [4], _0220_[2], \genblk1[1].u_lut.rdat [4] }; + assign { _0223_[3:2], _0223_[0] } = { \genblk1[7].u_lut.rdat [4], _0218_[1], \genblk1[5].u_lut.rdat [4] }; + assign { _0224_[3], _0224_[1:0] } = { \genblk1[9].u_lut.rdat [4], \genblk1[2].u_lut.rdat [4], _0219_[1] }; + assign _0226_[1:0] = { _0218_[2], \genblk1[4].u_lut.rdat [4] }; + assign _0228_[3:1] = { _0173_[1:0], _0173_[4] }; + assign _0229_[2:1] = _0173_[3:2]; + assign _0231_[0] = _0230_[0]; + assign _0232_[0] = _0230_[0]; + assign _0233_[1:0] = { _0228_[0], _0173_[4] }; + assign _0235_[0] = _0234_[0]; + assign _0236_[0] = _0234_[0]; + assign _0237_[0] = _0230_[0]; + assign _0238_[2:1] = _0173_[3:2]; + assign _0240_[0] = _0239_[0]; + assign _0241_[2:1] = _0173_[3:2]; + assign _0242_[1] = _0239_[1]; + assign _0243_[2:1] = _0173_[3:2]; + assign _0244_[1] = _0239_[1]; + assign _0247_[0] = _0246_[0]; + assign _0248_[0] = _0246_[0]; + assign _0251_[1] = _0237_[1]; + assign _0252_[0] = _0251_[0]; + assign _0254_[1:0] = { _0218_[2], \genblk1[4].u_lut.rdat [0] }; + assign _0256_[1:0] = { _0222_[1], \genblk1[1].u_lut.rdat [1] }; + assign _0258_[1:0] = { _0218_[2], \genblk1[4].u_lut.rdat [2] }; + assign _0260_[1:0] = { _0223_[1], \genblk1[5].u_lut.rdat [5] }; + assign _0261_[1:0] = { _0222_[1], \genblk1[1].u_lut.rdat [3] }; + assign _0263_[1:0] = { _0223_[1], \genblk1[5].u_lut.rdat [6] }; + assign _0265_[1:0] = { _0223_[1], \genblk1[5].u_lut.rdat [7] }; + assign _0267_[1:0] = { _0218_[2], \genblk1[4].u_lut.rdat [8] }; + assign _0268_[1:0] = { _0222_[1], \genblk1[1].u_lut.rdat [9] }; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/csr_if.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/csr_if.sv new file mode 100644 index 0000000000000000000000000000000000000000..24d82866d5871470d8e796ee69b1766d175e256d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/csr_if.sv @@ -0,0 +1,65 @@ +//========================================================================== +// Copyright (C) 2023 Chili.CHIPS*ba +//-------------------------------------------------------------------------- +// PROPRIETARY INFORMATION +// +// The information contained in this file is the property of CHILI CHIPS LLC. +// Except as specifically authorized in writing by CHILI CHIPS LLC, the holder +// of this file: (1) shall keep all information contained herein confidential; +// and (2) shall protect the same in whole or in part from disclosure and +// dissemination to all third parties; and (3) shall use the same for operation +// and maintenance purposes only. +//-------------------------------------------------------------------------- +// Description: +// - SOC-specific interface for Config and Status Registers (CSR) +// - Provides structured CSR I/O +//========================================================================== + +interface csr_if (); + import csr_pkg::*; + +// UART_TX + logic uart_tx_write; + logic uart_tx_busy; + logic [7:0] uart_tx_data; + +// UART_RX + logic uart_rx_read; + uart_rx_t uart_rx; + + + //---------------------------------------- + // master/CPU side + //---------------------------------------- + modport MST ( + output uart_tx_write, + uart_tx_data, + uart_rx_read, + + input uart_tx_busy, + uart_rx + ); + + //---------------------------------------- + // Slave/Peripheral side + //---------------------------------------- + modport SLV_UART ( + input uart_tx_write, + uart_tx_data, + uart_rx_read, + + output uart_tx_busy, + uart_rx + ); + +endinterface: csr_if + +/* +----------------------------------------------------------------------------- +Version History: +----------------------------------------------------------------------------- + 2024/1/2 JI: initial creation + 2024/3/1 JI: added ADC1/2_RX, GPO and GPI I/O + 2024/3/28 JI: added DAC1/2 + 2024/4/22 JI: added MISC +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/csr_pkg.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/csr_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..2250db8adcd5e726be84014baac80e4c2ebd5192 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/csr_pkg.sv @@ -0,0 +1,92 @@ +//========================================================================== +// Copyright (C) 2023 Chili.CHIPS*ba +//-------------------------------------------------------------------------- +// PROPRIETARY INFORMATION +// +// The information contained in this file is the property of CHILI CHIPS LLC. +// Except as specifically authorized in writing by CHILI CHIPS LLC, the holder +// of this file: (1) shall keep all information contained herein confidential; +// and (2) shall protect the same in whole or in part from disclosure and +// dissemination to all third parties; and (3) shall use the same for operation +// and maintenance purposes only. +//-------------------------------------------------------------------------- +// Description: This is a package with declarations of SOC-specific Control +// and Status registers. This is the DNA of register set. It is purposely +// structured and formal, to facilitate future automation/scripted generation. +// +// It is also designed for preservation of FPGA resources. Writeable +// registers therefore don't have HW readback path. Instead, SW can use +// own variables in places where readback is needed. And, since SW +// variables are in RAM, they cost less than FPGA flip-flops and LUTs. +//========================================================================== + +package csr_pkg; + //import soc_pkg::clog2; + +//----------------------------------------------------------- +// UART_TX +//----------------------------------------------------------- +// To send a byte over UART, SW must: +// 1) wait for 'UART_TX.busy=0' +// 2) write into 'UART_TX.data' the value it wants to send +// +// The write into this register, when 'busy=0', triggers UART transfer. +// The SW writes that come while 'busy=1' are ignored. HW therefore does +// not allow SW to corrupt transfer that may already be going on. Such SW +// writes are lost and must be reattempted until executed for 'busy=0'. +// +// UART parameters are set in HW hardware to 115.2kbps, 1 Stop, 0 Parity. +// It is not possible for SW to change them. + + localparam ADDR_UART_TX = 'h0; + + typedef struct packed { // MIXED + //------- + logic [31:31] busy; // [31] RD_ONLY: 1 when HW cannot take another 'data' + //logic [30:8] rsvd; // [30:8] + logic [7:0] data; // [7:0] WR_ONLY: Data to send out + } uart_tx_t; //------- + + +//----------------------------------------------------------- +// UART_RX +//----------------------------------------------------------- +// HW is constantly monitoring UART serial input. Whenever a byte is collected, +// HW presents it on 'UART_RX.data' slice, sets 'valid=1', and continues looking +// for more. SW is expected to poll 'valid'. The poll in which SW sees 1 on 'valid' +// is the read from which it should also take 'data'. Such SW read clears 'valid' +// and 'oflow' flags, indicating to HW that the 'data' has exchanged hands. It +// also pulls new 'data' value (if any) from the RxFIFO. +// +// SW polling is expected to be frequent enough to free up 'data' before HW comes +// around to place a new value into it. Should HW see that 'data' is still NOT +// consumed (i.e. 'valid=1') at the time a new value is ready for placement, it +// will drop the new value and raise 'oflow' flag. HW thus conveys to the SW that +// one or more data bytes have been lost in handoff. This potential loss would +// be the result of SW inability to keep up with HW. + + localparam ADDR_UART_RX = 'h1; + + typedef struct packed { // MIXED + //------- + logic [31:31] valid; // [31] ROL_CLR: 1 when 'data' is valid + logic [30:30] oflow; // [30] ROL_CLR: 1 when some 'data' bytes are lost + //logic [29:8] rsvd; // [29:8] + logic [7:0] data; // [7:0] ROL_CLR: Received data. New value is pulled + } uart_rx_t; //------- from FIFO for read with 'valid=1' + + + +endpackage: csr_pkg + +/* +----------------------------------------------------------------------------- +Version History: +----------------------------------------------------------------------------- + 2024/1/2 JI: initial creation + 2024/3/1 JI: Streamlined HW/SW handshake for area efficiency. + Added full explanation. + Added ADC1/2_RX, GPO and GPI registers. + 2024/3/28 JI: Added DAC1/2 + 2024/4/22 JI: Added MISC +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/psram.v b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/psram.v new file mode 100644 index 0000000000000000000000000000000000000000..7d2a0701a39a935badafaeee3597dc69461181f7 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/psram.v @@ -0,0 +1,367 @@ +/* + * canvas.v + * + * This module provides a scrolling background canvas, + * based on the given screen position (scan row and column), + * and the canvas scroll position. + * + * Copyright (C) 2024 Curtis Whitley + * License: APACHE + */ + +`default_nettype none + +typedef enum logic [5:0] { + RESET_JUST_NOW = 0, + RESET_CLOCK_WAIT = 1, + RESET_CLOCK_DONE = 2, + MODE_SELECT_CMD_7 = 3, + MODE_CMD_6 = 4, + MODE_CMD_5 = 5, + MODE_CMD_4 = 6, + MODE_CMD_3 = 7, + MODE_CMD_2 = 8, + MODE_CMD_1 = 9, + MODE_CMD_0 = 10, + MODE_DESELECT = 11, + IDLE = 12, + READ_CMD_3_0 = 13, + READ_ADDR_23_20 = 14, + READ_ADDR_19_16 = 15, + READ_ADDR_15_12 = 16, + READ_ADDR_11_8 = 17, + READ_ADDR_7_4 = 18, + READ_ADDR_3_0 = 19, + READ_WAIT = 20, + READ_DATA_7_4 = 21, + READ_DATA_3_0 = 22, + READ_DESELECT = 23, + WRITE_CMD_3_0 = 24, + WRITE_ADDR_23_20 = 25, + WRITE_ADDR_19_16 = 26, + WRITE_ADDR_15_12 = 27, + WRITE_ADDR_11_8 = 28, + WRITE_ADDR_7_4 = 29, + WRITE_ADDR_3_0 = 30, + WRITE_DATA_7_4 = 31, + WRITE_DATA_3_0 = 32, + WRITE_DESELECT = 33 +} MachineState; + + +module psram ( + input logic arst_n, + input logic i_clk, + + // begin read/write + input logic i_stb, + input logic i_we, + + // input address and data + input logic [23:0] i_addr, + input logic [15:0] i_din, + // read and ready signals + output logic psram_busy, + + output logic o_done, + // output logic [5:0] o_state + + // outputs + output logic [15:0] o_dout, + + output logic o_psram_csn, + output logic o_psram_sclk, + inout logic io_psram_data0, + inout logic io_psram_data1, + inout logic io_psram_data2, + inout logic io_psram_data3, + inout logic io_psram_data4, + inout logic io_psram_data5, + inout logic io_psram_data6, + inout logic io_psram_data7 +/* output logic [34:0] states_hit */ +); + +// The main clock (i_clk) here is 100 MHz, which ticks every +// 10 nS. In order to wait 150 uS upon reset, we must count +// at least 15000 ticks. So, we wait 20000, to be safe. +logic [14:0] long_delay; + +MachineState o_state; +logic [34:0] states_hit; + +logic [3:0] short_delay; +logic hold_clk_lo; +logic [7:0] out_enable; +logic [7:0] data_to_chip; + +assign o_psram_sclk = (hold_clk_lo ? 0 : i_clk); +assign io_psram_data0 = (out_enable[0] ? data_to_chip[0] : 1'bZ); +assign io_psram_data1 = (out_enable[1] ? data_to_chip[1] : 1'bZ); +assign io_psram_data2 = (out_enable[2] ? data_to_chip[2] : 1'bZ); +assign io_psram_data3 = (out_enable[3] ? data_to_chip[3] : 1'bZ); +assign io_psram_data4 = (out_enable[4] ? data_to_chip[4] : 1'bZ); +assign io_psram_data5 = (out_enable[5] ? data_to_chip[5] : 1'bZ); +assign io_psram_data6 = (out_enable[6] ? data_to_chip[6] : 1'bZ); +assign io_psram_data7 = (out_enable[7] ? data_to_chip[7] : 1'bZ); + +always @(negedge arst_n or posedge i_clk) begin + if (arst_n == 1'b0) begin + // Reset the SPI machine + long_delay <= 0; + o_state <= RESET_JUST_NOW; + psram_busy <= 1; + o_done <= 0; + o_psram_csn <= 1; // deselect + o_dout <= 0; + hold_clk_lo <= 1; + data_to_chip <= 8'd0; + states_hit <= 0; + out_enable <= 8'hFF; + end else begin + states_hit[o_state] <= 1; + case (o_state) + // Startup long_delay + RESET_JUST_NOW: begin + if (long_delay == 19999) + o_state <= RESET_CLOCK_WAIT; + else + long_delay <= long_delay + 1; + end + + // Post-reset clock wait start + RESET_CLOCK_WAIT: begin + hold_clk_lo <= 0; + o_state <= RESET_CLOCK_DONE; + end + + // Post-reset clock wait end + RESET_CLOCK_DONE: begin + psram_busy <= 0; + out_enable <= 8'h00; + o_state <= MODE_SELECT_CMD_7; + end + + // Entering QPI mode is done by command 35H + // The command bits are sent 1-at-a-time, on both PSRAM chips + MODE_SELECT_CMD_7: begin + o_psram_csn <= 0; // select + out_enable[0] <= 1; + out_enable[4] <= 1; + data_to_chip <= 8'h00; + o_state <= MODE_CMD_6; + end + + MODE_CMD_6: begin + data_to_chip <= 8'h00; + o_state <= MODE_CMD_5; + end + + MODE_CMD_5: begin + data_to_chip <= 8'hFF; + o_state <= MODE_CMD_4; + end + + MODE_CMD_4: begin + data_to_chip <= 8'hFF; + o_state <= MODE_CMD_3; + end + + MODE_CMD_3: begin + data_to_chip <= 8'h00; + o_state <= MODE_CMD_2; + end + + MODE_CMD_2: begin + data_to_chip <= 8'hFF; + o_state <= MODE_CMD_1; + end + + MODE_CMD_1: begin + data_to_chip <= 8'h00; + o_state <= MODE_CMD_0; + end + + MODE_CMD_0: begin + data_to_chip <= 8'hFF; + o_state <= MODE_DESELECT; + end + + MODE_DESELECT: begin + o_psram_csn <= 1; // deselect + out_enable <= 8'h00; + psram_busy <= 0; + o_done <= 1; + o_state <= IDLE; + end + + // Idle, awaiting command + IDLE: begin + if (i_stb) begin + if (i_we) begin + // A write to PSRAM is done by command 38H + // The command bits are sent 4-at-a-time, on both PSRAM chips + data_to_chip[3:0] <= 4'h3; + data_to_chip[7:4] <= 4'h3; + o_state <= WRITE_CMD_3_0; + end else begin + // A read from PSRAM is done by command EBH + // The command bits are sent 4-at-a-time, on both PSRAM chips + data_to_chip[3:0] <= 4'hE; + data_to_chip[7:4] <= 4'hE; + o_state <= READ_CMD_3_0; + end + o_psram_csn <= 0; // select + psram_busy <= 1; + o_done <= 0; //get this signal out a clock earlier + out_enable <= 8'hFF; + end + end + + READ_CMD_3_0: begin + data_to_chip[3:0] <= 4'hB; + data_to_chip[7:4] <= 4'hB; + o_state <= READ_ADDR_23_20; + end + + READ_ADDR_23_20: begin + data_to_chip[3:0] <= i_addr[23:20]; + data_to_chip[7:4] <= i_addr[23:20]; + o_state <= READ_ADDR_19_16; + end + + READ_ADDR_19_16: begin + data_to_chip[3:0] <= i_addr[19:16]; + data_to_chip[7:4] <= i_addr[19:16]; + o_state <= READ_ADDR_15_12; + end + + READ_ADDR_15_12: begin + data_to_chip[3:0] <= i_addr[15:12]; + data_to_chip[7:4] <= i_addr[15:12]; + o_state <= READ_ADDR_11_8; + end + + READ_ADDR_11_8: begin + data_to_chip[3:0] <= i_addr[11:8]; + data_to_chip[7:4] <= i_addr[11:8]; + o_state <= READ_ADDR_7_4; + end + + READ_ADDR_7_4: begin + data_to_chip[3:0] <= i_addr[7:4]; + data_to_chip[7:4] <= i_addr[7:4]; + o_state <= READ_ADDR_3_0; + end + + READ_ADDR_3_0: begin + data_to_chip[3:0] <= i_addr[3:0]; + data_to_chip[7:4] <= i_addr[3:0]; + short_delay <= 0; + o_state <= READ_WAIT; + end + + READ_WAIT: begin + out_enable <= 8'h00; + if (short_delay == 5)//not sure about this? + o_state <= READ_DATA_7_4; + else + short_delay <= short_delay + 1; + end + + READ_DATA_7_4: begin + o_dout[15] <= io_psram_data7; + o_dout[14] <= io_psram_data6; + o_dout[13] <= io_psram_data5; + o_dout[12] <= io_psram_data4; + o_dout[11] <= io_psram_data3; + o_dout[10] <= io_psram_data2; + o_dout[9] <= io_psram_data1; + o_dout[8] <= io_psram_data0; + o_state <= READ_DATA_3_0; + end + + READ_DATA_3_0: begin + o_dout[7] <= io_psram_data7; + o_dout[6] <= io_psram_data6; + o_dout[5] <= io_psram_data5; + o_dout[4] <= io_psram_data4; + o_dout[3] <= io_psram_data3; + o_dout[2] <= io_psram_data2; + o_dout[1] <= io_psram_data1; + o_dout[0] <= io_psram_data0; + o_state <= READ_DESELECT; + end + + READ_DESELECT: begin + o_psram_csn <= 1; // deselect + psram_busy <= 0; + o_done <= 1; + o_state <= IDLE; + end + + WRITE_CMD_3_0: begin + data_to_chip[3:0] <= 4'h8; + data_to_chip[7:4] <= 4'h8; + o_state <= WRITE_ADDR_23_20; + end + + WRITE_ADDR_23_20: begin + data_to_chip[3:0] <= i_addr[23:20]; + data_to_chip[7:4] <= i_addr[23:20]; + o_state <= WRITE_ADDR_19_16; + end + + WRITE_ADDR_19_16: begin + data_to_chip[3:0] <= i_addr[19:16]; + data_to_chip[7:4] <= i_addr[19:16]; + o_state <= WRITE_ADDR_15_12; + end + + WRITE_ADDR_15_12: begin + data_to_chip[3:0] <= i_addr[15:12]; + data_to_chip[7:4] <= i_addr[15:12]; + o_state <= WRITE_ADDR_11_8; + end + + WRITE_ADDR_11_8: begin + data_to_chip[3:0] <= i_addr[11:8]; + data_to_chip[7:4] <= i_addr[11:8]; + o_state <= WRITE_ADDR_7_4; + end + + WRITE_ADDR_7_4: begin + data_to_chip[3:0] <= i_addr[7:4]; + data_to_chip[7:4] <= i_addr[7:4]; + o_state <= WRITE_ADDR_3_0; + end + + WRITE_ADDR_3_0: begin + data_to_chip[3:0] <= i_addr[3:0]; + data_to_chip[7:4] <= i_addr[3:0]; + o_state <= WRITE_DATA_7_4; + end + + WRITE_DATA_7_4: begin + data_to_chip[7:0] <= i_din[15:8]; + o_state <= WRITE_DATA_3_0; + end + + WRITE_DATA_3_0: begin + data_to_chip[7:0] <= i_din[7:0]; + o_state <= WRITE_DESELECT; + end + + WRITE_DESELECT: begin + o_psram_csn <= 1; // deselect + out_enable <= 8'h00; + psram_busy <= 0; // get this signal out a clock earlier + o_done <= 1; + o_state <= IDLE; + end + default: o_state <= IDLE; + endcase + end +end + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/top.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/top.sv new file mode 100644 index 0000000000000000000000000000000000000000..0538a88f12048df6d9a7b3865062481573110256 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/top.sv @@ -0,0 +1,304 @@ +//======================================================================== +// openCologne * NLnet-sponsored open-source design ware for GateMate +//------------------------------------------------------------------------ +// Copyright (C) 2024 Chili.CHIPS*ba +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// 3. Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// https://opensource.org/license/bsd-3-clause +//------------------------------------------------------------------------ +// Description: +//======================================================================== + +// +/* verilator lint_off PINMISSING */ +`timescale 1ns/1ps +module top + import csr_pkg::*; +( + input logic clk, + input logic arst_n, + output logic tick_1us, + input logic uart_rx, + output logic uart_tx, + + output logic o_psram_csn, + output logic o_psram_sclk, + inout logic io_psram_data0, + inout logic io_psram_data1, + inout logic io_psram_data2, + inout logic io_psram_data3, + inout logic io_psram_data4, + inout logic io_psram_data5, + inout logic io_psram_data6, + inout logic io_psram_data7, + output logic led +); +/* + + */ + //logic tick_1us; //to do: generate this tick and check in edusoc what it is + logic psram_stb, psram_we, psram_busy; + + logic [15:0] psram_rdat; + + psram u_psram ( + .arst_n(arst_n), //i + .i_clk(clk_out), //i + + .i_stb(psram_stb), + .i_we(psram_we), + + .i_addr({command_bytes[3],command_bytes[2],command_bytes[1]}), + .i_din({command_bytes[5],command_bytes[4]}), + + .psram_busy(psram_busy), + + .o_dout(psram_rdat), + + .o_psram_csn(o_psram_csn), + .o_psram_sclk(o_psram_sclk), + .io_psram_data0(io_psram_data0), + .io_psram_data1(io_psram_data1), + .io_psram_data2(io_psram_data2), + .io_psram_data3(io_psram_data3), + .io_psram_data4(io_psram_data4), + .io_psram_data5(io_psram_data5), + .io_psram_data6(io_psram_data6), + .io_psram_data7(io_psram_data7) + ); + + + logic [7:0] uart_tx_data; + logic uart_tx_write; + logic uart_rx_read, uart_tx_busy; + uart_rx_t uart_rx_arr; + + uart u_uart( + .arst_n(arst_n), //i + .clk(clk_out), //i + + .tick_1us(tick_1us), //i + + .uart_tx_write(uart_tx_write), //i + .uart_tx_data(uart_tx_data), //i + .uart_rx_read(uart_rx_read), //i + + .uart_tx_busy(uart_tx_busy), + + + .uart_rx(uart_rx), //i + .uart_tx(uart_tx), //o + + .uart_rx_arr(uart_rx_arr) //o + ); +//---------------------------------------------------- +// 10 MHz -> 40 MHz PLL + SIM model + logic clk270, clk180, clk90, clk0, usr_ref_out, clk_out; + logic usr_pll_lock_stdy, usr_pll_lock; + + + + + + + + + CC_PLL #( + .REF_CLK("10.0"), // reference input in MHz + .OUT_CLK("40.0"), // pll output frequency in MHz + .PERF_MD("ECONOMY"), // LOWPOWER, ECONOMY, SPEED + .LOW_JITTER(1), // 0: disable, 1: enable low jitter mode + .CI_FILTER_CONST(2), // optional CI filter constant + .CP_FILTER_CONST(4) // optional CP filter constant + ) u_pll ( + .CLK_REF(clk), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0), + .USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy), .USR_PLL_LOCKED(usr_pll_lock), + .CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(clk_out), .CLK_REF_OUT(usr_ref_out) + ); + + + //-------------------------- + // Generating 1us ticks + logic [5:0] counter; + logic tick_1us_reg; + always_ff @(posedge clk_out or negedge arst_n) begin + if(arst_n == 1'b0) begin + counter <= '0; + end + else begin + if(counter == 6'd39) begin + tick_1us_reg <= 1'b1; + counter <= 6'b0; + end + else begin + tick_1us_reg <= 1'b0; + counter <= counter + 6'b1; + end + end + end + assign tick_1us = tick_1us_reg; + + + //--------------------- + // Sending to UART TX + + +/* assign uart_tx_data = uart_rx_arr.data; + assign uart_tx_write = uart_rx_arr.valid; + + assign uart_rx_read = uart_rx_arr.valid; */ + typedef enum logic [1:0] {IDLE = 2'b0, + READ_COMMAND = 2'b1, + WAIT_PSRAM = 2'b10, + PROCESS_COMMAND = 2'b11 } state_psram_t; + state_psram_t state_psram; + //----------------------------------------------------------- + // command buffer: B0 -> 0 - Read, 1 - Write + // B1-7 -> PSRAM address + // B8-11 -> PSRAM wdat (left out for reading) + logic [7:0] command_bytes [5:0]; + + logic [2:0] byte_count; + + + always_ff @(posedge clk_out or negedge arst_n) begin + if(arst_n == 1'b0) begin + state_psram <= IDLE; + byte_count <= '0; + end + else begin + unique case (state_psram) + IDLE: begin + if(uart_rx == 1'b0) begin + state_psram <= READ_COMMAND; + byte_count <= '0; + end + end + READ_COMMAND: begin //fill up the command buffer + if(uart_rx_arr.valid == 1'b1) begin + command_bytes[byte_count] <= uart_rx_arr.data; + byte_count <= byte_count + 3'b1; + end + if(byte_count == 3'd6 | (byte_count == 3'd4 & command_bytes[0] == '0)) begin + state_psram <= WAIT_PSRAM; + psram_stb <= 1'b1; + psram_we <= (byte_count == 3'd6); + end + end + WAIT_PSRAM: begin + psram_stb <= 1'b0; + psram_we <= 1'b0; + state_psram <= PROCESS_COMMAND; + end + PROCESS_COMMAND: begin + if(psram_busy == 1'b0) begin + state_psram <= IDLE; + end + end + endcase + end + end + + //---------------------------- + // Write out read data on UART + assign uart_tx_data = psram_rdat[7:0]; + assign uart_tx_write = (psram_busy == 1'b0 & state_psram == PROCESS_COMMAND); + assign uart_rx_read = uart_rx_arr.valid; + + + + //-------------------------- + // Generating 163ms ticks on 14 bits counter + logic [11:0] counter_10; + + always_ff @(posedge clk_out or negedge arst_n) begin + if(arst_n == 1'b0) begin + counter_10 <= '0; + end + else begin + counter_10 <= counter_10 + 12'b1; + end + end + + + //--------------------- + // Driving LEDs + logic [27:0] u_counter ; //25 prev + + always_ff @(posedge clk_out or negedge arst_n) begin + if(arst_n == 1'b0) begin + u_counter <= '0; + end + else begin + u_counter <= u_counter + 28'b1; + end + end + + //------------- + // Buffer fill + logic buffer [7:0]; + logic buffer_full; + + logic [2:0] in; + logic uart_tx_prev; + + always_ff @(posedge clk_out) begin + if(buffer_full == 1'b0 & uart_tx_prev != uart_tx) begin + buffer [in] <= uart_tx ; + in <= in + 3'b1; + if(in == '1) begin + buffer_full <= 1'b1; + in <= 3'b0; + end + end + else if(u_counter[27:25] == '1) begin + buffer_full <= 1'b0; + end + uart_tx_prev <= uart_tx; + end + //-------------- + // Buffer empty + + logic counter_24_prev; + + always_ff @(posedge clk_out) begin + if(u_counter[24] == 1'b1 & counter_24_prev == 1'b0 & buffer_full == 1'b1) begin + led <= buffer [u_counter[27:25]]; + end + counter_24_prev <= u_counter[24]; + end + +endmodule: top + +/* +------------------------------------------------------------------------------ +Version History: +------------------------------------------------------------------------------ + 2024/5/10 : Initial creation +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/uart.WITHOUT-FIFO.sv b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/uart.WITHOUT-FIFO.sv new file mode 100644 index 0000000000000000000000000000000000000000..eaedfe27c539e2c4fe1fcfd313419a1a570a1251 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/slpp_all/lib/work/uart.WITHOUT-FIFO.sv @@ -0,0 +1,719 @@ +//========================================================================== +// Copyright (C) 2023 Chili.CHIPS*ba +//-------------------------------------------------------------------------- +// PROPRIETARY INFORMATION +// +// The information contained in this file is the property of CHILI CHIPS LLC. +// Except as specifically authorized in writing by CHILI CHIPS LLC, the holder +// of this file: (1) shall keep all information contained herein confidential; +// and (2) shall protect the same in whole or in part from disclosure and +// dissemination to all third parties; and (3) shall use the same for operation +// and maintenance purposes only. +//-------------------------------------------------------------------------- +// Description: +// Minimal UART, with all serial parameters fixed in hardware: +// - 115.2kbps (i.e. one bit period is 8.68usec) +// - 8 Data bits +// - 1 Stop bit +// - 0 Parity +// +// It is designed for the minimal expenditure in hardware resources. +// It therefore does not have Rx/Tx FIFOs, but only single-byte buffer +// in each direction. Handshake with SW is based on 'tx.busy' and +// 'rx.valid+overflow' flags: +// - New Tx data is accepted from SW only when 'tx.busy=0' +// - New Rx data is loaded into holding register only when 'rx.valid=0'. +// Otherwise, 'rx.overflow' is raised +// +// Both Rx flags are Clear-on-Read -- Zero value on them tells HW that +// SW has got the posted value. See 'csr_pkg.sv for additional detail. +//-------------------------------------------------------------------------- +// +// This module also houses the FSM for loading new CPU program via Rx UART. +//========================================================================== + +module uart + import csr_pkg::*; +( + input logic arst_n, + input logic clk, + input logic tick_1us, + + input logic uart_rx, + output logic uart_tx, + + input logic uart_tx_write, + input logic [7:0] uart_tx_data, + input logic uart_rx_read, + + output logic uart_tx_busy, + output uart_rx_t uart_rx_arr + //csr_if.SLV_UART csr + + // IMEM Write port, for live updates of CPU program +/* output logic imem_we, + output logic [31:2] imem_waddr, + output logic [31:0] imem_wdat */ +); + +//-------------------------------------- +// Common +//-------------------------------------- + + typedef enum logic[3:0] { + IDLE = 4'd14, + + START = 4'd15, // skipped altogether in RxFSM + + D0 = 4'd0, // LSB first + D1 = 4'd1, // | + D2 = 4'd2, // | + D3 = 4'd3, // | + D4 = 4'd4, // | + D5 = 4'd5, // | + D6 = 4'd6, // V + D7 = 4'd7, // MSB last + + STOP = 4'd8 // only one Stop bit + + // Zero Parity bit + } state_t; + + + typedef logic [3:0] cnt1us_t; + + +//-------------------------------------- +// Rx +//-------------------------------------- +// To save resources, SOC-level 1us tick is used as time base for +// Rx sampling. Since one bit period is 8.68us, upon detecting START, +// the FSM first waits 9+4=13us to skip the START bit and get close to +// the middle of D0, where it samples it. It then waits 8us or 9us for +// subsequent data bits. This keep the sampling sufficiently centered, +// despite 'tick_1us' being completely asynchronous to incoming data: +// +// - START+D0center=8.68us+4.34us=13.02us is the ideal D0 sampling point. +// Given that 'tick_1us' is async to START, actual D0 sampling can fall +// anywhere in (13..14)us window. Max D0 sampling error is thus +0.98us +// +// - D1 ideal sampling is (2*8.68)+4.34=21.70us +// Actual is (13..14)+8=(21..22)us: Max error: -0.70us +// +// - D2 ideal sampling is (3*8.68)+4.34=30.38us +// Actual is (21..22)+9=(30..31)us: Max error: +0.62us +// +// - D3 ideal sampling is (4*8.68)+4.34=39.06us +// Actual is (30..31)+9=(39..40)us: Max error: +0.94us +// +// - D4 ideal sampling is (5*8.68)+4.34=47.74us +// Actual is (39..40)+8=(47..48)us: Max error: -0.74us +// +// - D5 ideal sampling is (6*8.68)+4.34=56.42us +// Actual is (47..48)+9=(56..57)us: Max error: +0.58us +// +// - D6 ideal sampling is (7*8.68)+4.34=65.10us +// Actual is (56..57)+9=(65..66)us: Max error: +0.90us +// +// - D7 ideal sampling is (8*8.68)+4.34=73.78us +// Actual is (65..66)+8=(73..74)us: Max error: -0.78us +// +// - STOP ideal sampling is (9*8.68)+4.34=82.46us +// Actual is (73..74)+9=(82..83)us: Max error: +0.54us +// +// In other words, sampling error is within +/-1us from the center +// of +/-4.34us window, thus leaving more than sufficient margin +// for reliable data reception. +//-------------------------------------- + + localparam bit[3:0] RX_WAIT_D0 = 4'd13; //=14 ticks: From 13 to 0 + localparam bit[3:0] RX_WAIT_D1 = 4'd7; + localparam bit[3:0] RX_WAIT_D2 = 4'd8; + localparam bit[3:0] RX_WAIT_D3 = 4'd8; + localparam bit[3:0] RX_WAIT_D4 = 4'd7; + localparam bit[3:0] RX_WAIT_D5 = 4'd8; + localparam bit[3:0] RX_WAIT_D6 = 4'd8; + localparam bit[3:0] RX_WAIT_D7 = 4'd7; + localparam bit[3:0] RX_WAIT_STOP = 4'd8; + + state_t rx_state; + cnt1us_t rx_cnt1us; // counts 1us ticks + logic rx_cnt1us_is0; + assign rx_cnt1us_is0 = (rx_cnt1us == '0); + + logic rx_nextbit; + assign rx_nextbit = tick_1us & rx_cnt1us_is0; + + logic [7:0] rx_shift; + + always_ff @(negedge arst_n or posedge clk) begin + if (arst_n == 1'b0) begin + rx_state <= IDLE; + rx_cnt1us <= '0; + rx_shift <= '0; + + uart_rx_arr.valid <= 1'b0; + uart_rx_arr.oflow <= 1'b0; + uart_rx_arr.data <= '0; + end + else begin + + // when not in IDLE, count 1us ticks + if ((tick_1us == 1'b1) && (rx_state != IDLE)) begin + rx_cnt1us <= cnt1us_t'(rx_cnt1us - cnt1us_t'(1)); + end + + // SW Clear-on-Read is async to UART traffic + // and with lower priority to HW Set + if (uart_rx_read == 1'b1) begin + uart_rx_arr.valid <= 1'b0; + uart_rx_arr.oflow <= 1'b0; + end + + // FSM runs on main clock, with most states gated by 'rx_cnt1us_is0' + unique case (rx_state) + + //---Wait for 'uart_rx' negedge to start reception + IDLE: begin + rx_cnt1us <= RX_WAIT_D0; + + if (uart_rx == 1'b0) begin + rx_state <= D0; + end + end + + //---New Rx data is collected: + // - if SW has already taken previous data, present the new data + // - otherwise, report overflow. New data is dropped in such case + STOP: if (rx_nextbit == 1'b1) begin + + if (uart_rx_arr.valid == 1'b1) begin + uart_rx_arr.oflow <= 1'b1; + end + else begin + uart_rx_arr.valid <= 1'b1; + uart_rx_arr.data <= rx_shift; + end + + rx_state <= IDLE; + + + + + end + + //---Wait the prescribed amount of time to position sampling + // point to Rx bit center, then capture DATA bits + default: if (rx_nextbit == 1'b1) begin + rx_shift <= {uart_rx, rx_shift[7:1]}; // MSB goes in last + + unique case (rx_state) + D0: begin + rx_cnt1us <= RX_WAIT_D1; + rx_state <= D1; + end + D1: begin + rx_cnt1us <= RX_WAIT_D2; + rx_state <= D2; + end + D2: begin + rx_cnt1us <= RX_WAIT_D3; + rx_state <= D3; + end + D3: begin + rx_cnt1us <= RX_WAIT_D4; + rx_state <= D4; + end + D4: begin + rx_cnt1us <= RX_WAIT_D5; + rx_state <= D5; + end + D5: begin + rx_cnt1us <= RX_WAIT_D6; + rx_state <= D6; + end + D6: begin + rx_cnt1us <= RX_WAIT_D7; + rx_state <= D7; + end + D7: begin + rx_cnt1us <= RX_WAIT_STOP; + rx_state <= STOP; + end + default: begin end + endcase // unique case (rx_state) + end + endcase // unique case (rx_state) + + end + end + + +//-------------------------------------- +// Tx +//-------------------------------------- +// To save resources, SOC-level 1us tick is used as Tx time base. +// Upon detecting SW request to send, and given 8.68us bit period, +// the FSM employs the following delay scheme to generate bits: +// - START ideal end: 1*8.68us= 8.68us. Actual: 9(+9). Error: +0.32us +// - D0 ideal end: 2*8.68us=17.38us. Actual:17(+8). Error: -0.38us +// - D1 ideal end: 3*8.68us=26.04us. Actual:26(+9). Error: -0.04us +// - D2 ideal end: 4*8.68us=34.72us. Actual:35(+9). Error: +0.28us +// - D3 ideal end: 5*8.68us=43.40us. Actual:43(+8). Error: -0.40us +// - D4 ideal end: 6*8.68us=52.08us. Actual:52(+9). Error: -0.08us +// - D5 ideal end: 7*8.68us=60.76us. Actual:61(+9). Error: +0.24us +// - D6 ideal end: 8*8.68us=69.44us. Actual:69(+8). Error: -0.44us +// - D7 ideal end: 9*8.68us=78.12us. Actual:78(+9). Error: -0.12us +// - STOP ideal end:10*8.68us=86.80us. Actual:87(+9). Error: +0.20us +// +// In other words, edge placement error is within +/-0.44us for 8.68us +// period, i.e. +/-5%, thus leaving sufficient margin for reliable +// data reception on the other end. +//-------------------------------------- + + localparam bit[3:0] TX_WAIT_START = 4'd9; //+1 tick for initial sync + localparam bit[3:0] TX_WAIT_D0 = 4'd7; //=8 ticks, from 7 to 0 + localparam bit[3:0] TX_WAIT_D1 = 4'd8; + localparam bit[3:0] TX_WAIT_D2 = 4'd8; + localparam bit[3:0] TX_WAIT_D3 = 4'd7; + localparam bit[3:0] TX_WAIT_D4 = 4'd8; + localparam bit[3:0] TX_WAIT_D5 = 4'd8; + localparam bit[3:0] TX_WAIT_D6 = 4'd7; + localparam bit[3:0] TX_WAIT_D7 = 4'd8; + localparam bit[3:0] TX_WAIT_STOP = 4'd8; + +/* localparam bit[3:0] TX_WAIT_START = 4'd9; //+1 tick for initial sync + localparam bit[3:0] TX_WAIT_D0 = 4'd7; //=8 ticks, from 7 to 0 + localparam bit[3:0] TX_WAIT_D1 = 4'd8; + localparam bit[3:0] TX_WAIT_D2 = 4'd8; + localparam bit[3:0] TX_WAIT_D3 = 4'd7; + localparam bit[3:0] TX_WAIT_D4 = 4'd8; + localparam bit[3:0] TX_WAIT_D5 = 4'd8; + localparam bit[3:0] TX_WAIT_D6 = 4'd7; + localparam bit[3:0] TX_WAIT_D7 = 4'd8; + localparam bit[3:0] TX_WAIT_STOP = 4'd7; */ + + state_t tx_state; + cnt1us_t tx_cnt1us; // counts 1us ticks + logic tx_cnt1us_is0; + assign tx_cnt1us_is0 = (tx_cnt1us == '0); + + logic tx_nextbit; + assign tx_nextbit = tick_1us & tx_cnt1us_is0; + + logic [7:0] tx_data; + + // SW write is ignored when sending another byte + assign uart_tx_busy = (tx_state != IDLE); + + always_ff @(negedge arst_n or posedge clk) begin + if (arst_n == 1'b0) begin + tx_state <= IDLE; + tx_cnt1us <= '0; + tx_data <= '0; + + uart_tx <= 1'b1; //STOP + end + else begin + + // when not in IDLE, count 1us ticks + if ((tick_1us == 1'b1) && (tx_state != IDLE)) begin + tx_cnt1us <= cnt1us_t'(tx_cnt1us - cnt1us_t'(1)); + end + + // FSM runs on main clock, with most states gated by 'tx_cnt1us_is0' + unique case (tx_state) + + //---Wait for SW write (which is ignored when not IDLE) + // to store SW data that needs to be sent + IDLE: begin + uart_tx <= 1'b1; //STOP + tx_cnt1us <= TX_WAIT_START; + + if (uart_tx_write == 1'b1) begin + tx_data <= uart_tx_data; + tx_state <= START; + end + end + + //---Wait for next 1us tick to start driving 0 (i.e. sync TX to + // the tick), then wait the prescribed amount of time to move on + START: if (tick_1us == 1'b1) begin + uart_tx <= 1'b0; //START + + if (tx_cnt1us_is0 == 1'b1) begin + uart_tx <= tx_data[0]; //LSB goes out first + tx_cnt1us <= TX_WAIT_D0; + tx_state <= D0; + end + end + //---Wait the prescribed amount of time while driving D0, + // then move on. Keep repeating the same, till D7 + D0: if (tx_nextbit == 1'b1) begin + uart_tx <= tx_data[1]; + tx_cnt1us <= TX_WAIT_D1; + tx_state <= D1; + end + D1: if (tx_nextbit == 1'b1) begin + uart_tx <= tx_data[2]; + tx_cnt1us <= TX_WAIT_D2; + tx_state <= D2; + end + D2: if (tx_nextbit == 1'b1) begin + uart_tx <= tx_data[3]; + tx_cnt1us <= TX_WAIT_D3; + tx_state <= D3; + end + D3: if (tx_nextbit == 1'b1) begin + uart_tx <= tx_data[4]; + tx_cnt1us <= TX_WAIT_D4; + tx_state <= D4; + end + D4: if (tx_nextbit == 1'b1) begin + uart_tx <= tx_data[5]; + tx_cnt1us <= TX_WAIT_D5; + tx_state <= D5; + end + D5: if (tx_nextbit == 1'b1) begin + uart_tx <= tx_data[6]; + tx_cnt1us <= TX_WAIT_D6; + tx_state <= D6; + end + D6: if (tx_nextbit == 1'b1) begin + uart_tx <= tx_data[7]; + tx_cnt1us <= TX_WAIT_D7; + tx_state <= D7; + end + D7: if (tx_nextbit == 1'b1) begin + uart_tx <= 1'b1; // STOP bit + tx_cnt1us <= TX_WAIT_STOP; + tx_state <= STOP; + + + + + + end + + //---Wait the prescribed amount of time while driving STOP bit + STOP: if (tx_nextbit == 1'b1) begin + tx_state <= IDLE; + end + + default: begin end + endcase // unique case (tx_state) + end + end + + +//========================================= +// TODO: FSM for loading IMEM via UART +//========================================= +/* assign imem_we = '0; + assign imem_waddr = '0; + assign imem_wdat = '0; + */ +/* Anel's code from TetriSaraj + parameter [3:0] T_STATES_WAIT_SOP = 0; + parameter [3:0] T_STATES_CMD = 1; + parameter [3:0] T_STATES_LEN_LB = 2; + parameter [3:0] T_STATES_LEN_HB = 3; + parameter [3:0] T_STATES_DATA0 = 4; + parameter [3:0] T_STATES_DATA1 = 5; + parameter [3:0] T_STATES_DATA2 = 6; + parameter [3:0] T_STATES_DATA3 = 7; + parameter [3:0] T_STATES_CS = 8; + parameter [3:0] T_STATES_EOP = 9; + parameter [3:0] T_STATES_ERROR = 10; + parameter [3:0] T_STATES_FINISH = 11; + + // command protocol constants: + parameter [7:0] C_SOP = 8'h23; + parameter [7:0] C_EOP = 8'h0d; + + // commands: + parameter [7:0] C_REGISTER_RD = 8'h08; + parameter [7:0] C_REGISTER_WR = 8'h07; + + wire rx_busy, tx_busy, converted, data_valid; + reg [15:0] data_length, data_cnt; + reg [7:0] command; + + // Local control logic variables + // FSM state + reg [3:0] state; + + // This variable is super critical in preventing wrong FSM state changes + reg allow_next; // Local signal to prevent race conditions + + // IO related variables + reg flush_ctrl; // Flush the RX data after reading + reg tx_enable_ctrl; // Allow tranmission of output, after data is settled + + wire [7:0] uart_data; // The actual RX UART data + reg [7:0] out_data; // The data that will be sent over TX + + reg ram_wen; + reg [31:0] ram_data, ram_addr; + reg [15:0] display_data; + reg [7:0] checksum; + reg [8:0] leds; + + // UART clock related variables + reg clk_uart; // (100MHz) / (BAUD_RATE*OVERSAMPLING*2) + reg [4:0] counter; + + + // Divided clock for UART @ 115200 baud + always @(posedge clk_bufg) + begin + if(sw[15]) begin + counter <= counter + 1; + if(counter == 5'd27) begin + counter <= 0; + clk_uart <= ~clk_uart; + end + end else begin + counter <= 0; + clk_uart <= 0; + end + end + + always @(posedge clk_uart) + begin + if(!resetn) begin + leds = 0; + display_data = 16'd1234; + state = T_STATES_WAIT_SOP; + ram_wen = 0; + ram_data = 0; + ram_addr = 32'hFFFFFFFF; + end else begin + case (state) + T_STATES_WAIT_SOP : begin + tx_enable_ctrl <= 0; + leds = 0; + command <= 0; + data_cnt <= 0; + if(converted) begin + if (uart_data == C_SOP) begin + leds[0] = 1; + checksum = 8'b0; + data_length = 0; + flush_ctrl <= 1; // Flush UART RX registers + state = T_STATES_CMD; + end + end + end + + T_STATES_CMD : begin + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + command <= uart_data; + state = T_STATES_LEN_LB; + end else + flush_ctrl <= 0; + end + + T_STATES_LEN_LB : begin + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + data_length <= {8'b0, uart_data}; + state = T_STATES_LEN_HB; + end else + flush_ctrl <= 0; + end + + T_STATES_LEN_HB : begin + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + data_length <= { uart_data, data_length[7:0]}; + state = T_STATES_DATA0; + end else + flush_ctrl <= 0; + end + + T_STATES_DATA0 : begin + ram_wen <= 0; + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + ram_data[7:0] <= uart_data; + checksum <= checksum + uart_data; + state = T_STATES_DATA1; + end else + flush_ctrl <= 0; + end + + T_STATES_DATA1 : begin + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + ram_data[15:8] <= uart_data; + checksum <= checksum + uart_data; + state = T_STATES_DATA2; + end else + flush_ctrl <= 0; + end + + T_STATES_DATA2 : begin + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + ram_data[23:16] <= uart_data; + checksum <= checksum + uart_data; + state = T_STATES_DATA3; + end else + flush_ctrl <= 0; + end + + T_STATES_DATA3 : begin + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + leds[1] = 1; + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + data_cnt <= data_cnt + 1; + display_data <= data_cnt + 1; + + ram_data[31:24] <= uart_data; + checksum <= checksum + uart_data; + ram_addr <= {16'd0, data_cnt}; + ram_wen <= 1; + + if (data_cnt == (data_length - 16'd1)) begin + state = T_STATES_CS; + end else + state = T_STATES_DATA0; + end else + flush_ctrl <= 0; + end + + T_STATES_CS : begin + ram_wen <= 0; + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + leds[2] = 1; + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + state = (uart_data == checksum[7:0]) ? T_STATES_EOP : T_STATES_ERROR; + end else + flush_ctrl <= 0; + end + + T_STATES_EOP : begin + // Once RX module has produced the final output(converted) + // and registers are cleared(converted is set low), go ahead + if(~flush_ctrl && ~converted) + allow_next <= 1; // Allow RX after registers cleared + + if(converted && ~flush_ctrl && allow_next) begin + leds[3] = 1; + flush_ctrl <= 1; // Data read, flush RX register + allow_next <= 0; + + state = (uart_data == C_EOP) ? T_STATES_FINISH : T_STATES_ERROR; + end else + flush_ctrl <= 0; + end + + T_STATES_ERROR : begin + leds[4] = 1; + out_data <= checksum[7:0]; + // Once TX is complete, allow going to next state + if(~tx_busy && ~allow_next) + tx_enable_ctrl <= 1; + else begin + allow_next <= 1; + flush_ctrl <= 0; + tx_enable_ctrl <= 0; + end + // TX complete, go to next state + if(~tx_busy && allow_next) begin + allow_next <= 0; + state = T_STATES_WAIT_SOP; + end + end + + T_STATES_FINISH : begin + leds[5] = 1; + out_data <= 8'h55; + // Once TX is complete, allow going to next state + if(~tx_busy && ~allow_next) + tx_enable_ctrl <= 1; + else begin + allow_next <= 1; + flush_ctrl <= 0; + tx_enable_ctrl <= 0; + end + // TX complete, go to next state + if(~tx_busy && allow_next) begin + allow_next <= 0; + state = T_STATES_WAIT_SOP; + end + end + + default:begin + state = T_STATES_WAIT_SOP; + end + endcase + end + end + + reg progmem_wen; + reg ram_wen_dl1, ram_wen_dl2; + always @(posedge clk) + begin + if(sw[15]) begin + ram_wen_dl1 <= ram_wen; + ram_wen_dl2 <= ram_wen_dl1; + if(ram_wen_dl2 == 1'b0 && ram_wen == 1'b1) + progmem_wen <= 1'b1; + else + progmem_wen <= 1'b0; + end else begin + progmem_wen <= 1'b0; + end + end +*/ + +endmodule: uart + +/* +----------------------------------------------------------------------------- +Version History: +----------------------------------------------------------------------------- + 2024/3/2 JI: original creation +*/ diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/top.v b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/top.v new file mode 100644 index 0000000000000000000000000000000000000000..d176c6c8ae42796c823af335a4aa0099afe12d6d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/top.v @@ -0,0 +1,45 @@ +module top ( + clk, + addr, + we, + wdat, + rdat +); + reg _sv2v_0; + parameter LUTRAM16X10 = 10; + input wire clk; + input wire [$clog2(LUTRAM16X10 * 16) - 1:0] addr; + input wire we; + input wire [9:0] wdat; + output reg [9:0] rdat; + localparam ADDR_BITS = $clog2(LUTRAM16X10 * 16) - 1; + wire [9:0] read_all [0:LUTRAM16X10 - 1]; + reg [LUTRAM16X10 - 1:0] we_dec; + always @(*) begin : _decode + if (_sv2v_0) + ; + we_dec = 1'sb0; + if (LUTRAM16X10 > 1) begin + we_dec[addr[ADDR_BITS:4]] = 1'b1 & we; + rdat = read_all[addr[ADDR_BITS:4]]; + end + else begin + we_dec = we; + rdat = read_all[0]; + end + end + genvar _gv_i_1; + generate + for (_gv_i_1 = 0; _gv_i_1 < LUTRAM16X10; _gv_i_1 = _gv_i_1 + 1) begin : genblk1 + localparam i = _gv_i_1; + lutram_16x10 u_lut( + .clk(clk), + .addr(addr[3:0]), + .rdat(read_all[i]), + .wdat(wdat), + .we(we_dec[i]) + ); + end + endgenerate + initial _sv2v_0 = 0; +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/top_00.v b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/top_00.v new file mode 100644 index 0000000000000000000000000000000000000000..b5c21509793d648efa74ad612cc8dfd939f840d1 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/3.build/top_00.v @@ -0,0 +1,17880 @@ +// (c) Cologne Chip AG +// FPGA Verilog netlist writer Version: Version 4.2 (1 July 2024) +// Compile Time: 2024-07-19 12:30:06 +// Program Run: 2024-08-22 16:24:05 +// Program Call: /home/tibrahimovic/0.git-repo/cc-toolchain-linux/cc-toolchain-linux/bin/p_r/p_r -i net/top_synth.v -o top -ccf /mnt/d/repos/LUTRAM_Stress_Test/3.build/../1.hw/constraints/constraints.ccf -cCP --verbose +// File Type: Verilog + +// Gatecount: 2419 +module top (addr , clk , wdat , we , + rdat + ) ; + +input [7:0]addr; +input clk; +input [9:0]wdat; +input we; + +output [9:0]rdat; + + + +wire [7:0]addr; +wire [9:0]wdat; +wire [9:0]rdat; +wire we; +wire clk; +wire na1_1; +wire na2_1; +wire na4_1; +wire na4_2; +wire na5_1; +wire na5_2; +wire na7_1; +wire na9_2; +wire na10_1; +wire na12_1; +wire na12_2; +wire na13_1; +wire na13_2; +wire na14_1; +wire na14_2; +wire na18_1; +wire na22_1; +wire na24_1; +wire na24_2; +wire na25_1; +wire na29_2; +wire na31_1; +wire na31_2; +wire na32_1; +wire na36_1; +wire na38_1; +wire na38_2; +wire na39_1; +wire na43_2; +wire na45_1; +wire na45_2; +wire na46_1; +wire na50_1; +wire na52_1; +wire na52_2; +wire na53_1; +wire na57_2; +wire na59_1; +wire na59_2; +wire na60_1; +wire na64_1; +wire na66_1; +wire na66_2; +wire na67_1; +wire na71_2; +wire na73_1; +wire na73_2; +wire na74_1; +wire na78_1; +wire na80_1; +wire na80_2; +wire na81_2; +wire na82_2; +wire na83_1; +wire na84_2; +wire na85_1; +wire na86_1; +wire na87_2; +wire na88_1; +wire na89_1; +wire na90_1; +wire na91_2; +wire na92_1; +wire na93_1; +wire na94_1; +wire na95_2; +wire na96_1; +wire na97_1; +wire na98_1; +wire na99_2; +wire na100_1; +wire na102_2; +wire na103_2; +wire na104_2; +wire na105_2; +wire na106_2; +wire na107_1; +wire na108_2; +wire na109_2; +wire na110_1; +wire na111_1; +wire na112_2; +wire na113_1; +wire na114_2; +wire na115_1; +wire na116_1; +wire na117_2; +wire na118_1; +wire na119_2; +wire na120_1; +wire na121_1; +wire na122_2; +wire na123_1; +wire na124_1; +wire na125_2; +wire na126_1; +wire na127_2; +wire na128_1; +wire na129_2; +wire na130_1; +wire na131_2; +wire na132_1; +wire na133_2; +wire na134_1; +wire na136_1; +wire na137_2; +wire na138_1; +wire na139_2; +wire na140_1; +wire na141_2; +wire na142_1; +wire na143_2; +wire na144_1; +wire na145_2; +wire na146_1; +wire na147_2; +wire na148_1; +wire na149_2; +wire na150_1; +wire na151_2; +wire na152_1; +wire na154_1; +wire na155_2; +wire na156_1; +wire na157_2; +wire na158_1; +wire na159_2; +wire na160_1; +wire na161_2; +wire na162_1; +wire na163_2; +wire na164_1; +wire na165_1; +wire na166_1; +wire na167_2; +wire na168_1; +wire na169_2; +wire na170_1; +wire na172_1; +wire na173_2; +wire na174_1; +wire na175_2; +wire na176_1; +wire na177_2; +wire na178_1; +wire na179_2; +wire na180_1; +wire na181_2; +wire na182_1; +wire na183_2; +wire na184_1; +wire na185_2; +wire na186_1; +wire na187_2; +wire na188_1; +wire na189_1; +wire na190_2; +wire na191_1; +wire na192_2; +wire na193_1; +wire na194_2; +wire na195_1; +wire na196_2; +wire na197_1; +wire na198_2; +wire na199_1; +wire na200_2; +wire na201_2; +wire na202_1; +wire na203_2; +wire na204_2; +wire na205_1; +wire na206_1; +wire na207_1; +wire na208_1; +wire na209_1; +wire na210_2; +wire na211_1; +wire na212_2; +wire na213_2; +wire na214_1; +wire na215_2; +wire na216_2; +wire na217_2; +wire na218_1; +wire na219_2; +wire na220_1; +wire na221_2; +wire na222_1; +wire na223_1; +wire na224_1; +wire na225_1; +wire na226_2; +wire na227_1; +wire na228_2; +wire na229_1; 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+wire na2359_1; +wire na2360_1; +wire na2361_1; +wire na2362_1; +wire na2363_1; +wire na2364_1; +wire na2365_1; +wire na2366_1; +wire na2367_1; +wire na2368_1; +wire na2369_1; +wire na2370_1; +wire na2371_1; +wire na2372_1; +wire na2373_1; +wire na2374_1; +wire na2375_1; +wire na2376_1; +wire na2377_1; +wire na2378_1; +wire na2379_1; +wire na2380_1; +wire na2381_1; +wire na2382_1; +wire na2383_1; +wire na2384_1; +wire na2385_1; +wire na2386_1; +wire na2387_1; +wire na2388_1; +wire na2389_1; +wire na2390_1; +wire na2401_1; +wire na2402_1; +wire na2403_1; +wire na2404_1; +wire na2405_1; +wire na2406_1; +wire na2407_1; +wire na2408_1; +wire na2409_1; +wire na2410_1; +wire na2411_1; +wire na2412_1; +wire na2412_2; +wire na2413_1; +wire na2414_1; +wire na2415_2; +wire na2416_1; +wire na2417_2; +wire na2422_1; +wire na2422_2; +wire na2423_1; +wire na2425_2; +wire na2426_1; +wire na2431_1; +wire na2431_2; +wire na2432_2; +wire na2434_1; +wire na2435_2; +wire na2440_1; +wire na2440_2; +wire na2441_1; +wire na2443_2; +wire na2444_1; +wire na2449_1; +wire na2449_2; +wire na2450_2; +wire na2452_1; +wire na2453_2; +wire na2458_1; +wire na2458_2; +wire na2459_1; +wire na2461_2; +wire na2462_1; +wire na2467_1; +wire na2467_2; +wire na2468_2; +wire na2470_1; +wire na2471_2; +wire na2476_1; +wire na2476_2; +wire na2477_1; +wire na2479_2; +wire na2480_1; +wire na2485_1; +wire na2485_2; +wire na2486_2; +wire na2488_1; +wire na2489_2; +wire na2494_1; +wire na2494_2; +wire na2495_1; +wire na2497_2; +wire na2498_1; +wire na2503_1; +wire na2504_2; +wire na2505_2; +wire na2506_2; +wire na2507_2; +wire na2508_2; +wire na2509_2; +wire na2510_2; +wire na2511_2; +wire na2512_2; +wire na2513_2; +wire na2514_2; +wire na2515_2; +wire na2516_2; +wire na2517_2; +wire na2518_2; +wire na2519_2; +wire na2520_2; +wire na2521_2; +wire na2522_2; +wire na2523_2; +wire na2524_2; +wire na2504_10; +wire na2505_10; +wire na2506_10; +wire na2507_10; +wire na2508_10; +wire na2509_10; +wire na2510_10; +wire na2511_10; +wire na2512_10; +wire na2513_10; + +// C_OR//// x136y42 80'h00_0018_00_0000_0EEE_B7ED +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a1_1 ( .OUT(na1_1), .IN1(~na14_1), .IN2(na9_2), .IN3(na2412_1), .IN4(na2416_1), .IN5(~na14_2), .IN6(~na2413_1), .IN7(na2412_2), + .IN8(~na2415_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +CLKIN #(.CLKIN_CFG (32'h0000_0000)) + _a2 ( .PCLK0(na2_1), .PCLK1(_d0), .PCLK2(_d1), .PCLK3(_d2), .CLK0(na2390_1), .CLK1(1'b0), .CLK2(1'b0), .CLK3(1'b0), .SER_CLK(1'b0), + .SPI_CLK(1'b0), .JTAG_CLK(1'b0) ); +// C_AND///AND/ x133y58 80'h00_0078_00_0000_0C88_1244 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a4_1 ( .OUT(na4_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2389_1), .IN6(~na2386_1), .IN7(~na2387_1), .IN8(~na2388_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a4_4 ( .OUT(na4_2), .IN1(~na2389_1), .IN2(na2386_1), .IN3(~na2387_1), .IN4(na2388_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x129y53 80'h00_0078_00_0000_0C88_2441 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a5_1 ( .OUT(na5_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2389_1), .IN6(na2386_1), .IN7(na2387_1), .IN8(~na2388_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a5_4 ( .OUT(na5_2), .IN1(~na2389_1), .IN2(~na2386_1), .IN3(~na2387_1), .IN4(na2388_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x124y57 80'h00_0018_00_0000_0C88_84FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a7_1 ( .OUT(na7_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2389_1), .IN6(na2386_1), .IN7(na2387_1), .IN8(na2388_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x125y46 80'h00_0060_00_0000_0C08_FF5A +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a9_4 ( .OUT(na9_2), .IN1(na2336_1), .IN2(1'b1), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x124y59 80'h00_0018_00_0040_0CDC_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a10_1 ( .OUT(na10_1), .IN1(1'b1), .IN2(1'b0), .IN3(~na2417_2), .IN4(~na2388_1), .IN5(na2389_1), .IN6(1'b1), .IN7(~na2387_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x142y53 80'h00_0078_00_0000_0C88_1881 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a12_1 ( .OUT(na12_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2389_1), .IN6(na2386_1), .IN7(~na2387_1), .IN8(~na2388_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a12_4 ( .OUT(na12_2), .IN1(~na2389_1), .IN2(~na2386_1), .IN3(na2387_1), .IN4(na2388_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x139y53 80'h00_0078_00_0000_0C88_2114 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a13_1 ( .OUT(na13_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2389_1), .IN6(~na2386_1), .IN7(na2387_1), + .IN8(~na2388_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a13_4 ( .OUT(na13_2), .IN1(~na2389_1), .IN2(na2386_1), .IN3(~na2387_1), .IN4(~na2388_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x143y41 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a14_1 ( .OUT(na14_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na13_2), .IN6(~na1886_1), .IN7(~na12_2), .IN8(~na2136_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a14_4 ( .OUT(na14_2), .IN1(~na13_1), .IN2(~na1936_1), .IN3(~na12_1), .IN4(~na2286_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x137y41 80'h00_0018_00_0000_0EEE_D7DE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a18_1 ( .OUT(na18_1), .IN1(na2426_1), .IN2(na22_1), .IN3(~na24_1), .IN4(na2422_1), .IN5(~na2425_2), .IN6(~na2423_1), .IN7(~na24_2), + .IN8(na2422_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x123y46 80'h00_0018_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a22_1 ( .OUT(na22_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2341_1), .IN6(1'b1), .IN7(~na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x134y47 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a24_1 ( .OUT(na24_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2091_1), .IN6(~na4_2), .IN7(~na12_1), .IN8(~na2291_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a24_4 ( .OUT(na24_2), .IN1(~na2241_1), .IN2(~na4_1), .IN3(~na12_2), .IN4(~na2141_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x134y48 80'h00_0018_00_0000_0EEE_B7BE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a25_1 ( .OUT(na25_1), .IN1(na2435_2), .IN2(na29_2), .IN3(na2431_1), .IN4(~na31_1), .IN5(~na2434_1), .IN6(~na2432_2), .IN7(na2431_2), + .IN8(~na31_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x123y48 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a29_4 ( .OUT(na29_2), .IN1(1'b1), .IN2(na2346_1), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x142y48 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a31_1 ( .OUT(na31_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na13_2), .IN6(~na1896_1), .IN7(~na12_2), .IN8(~na2146_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a31_4 ( .OUT(na31_2), .IN1(~na13_1), .IN2(~na1946_1), .IN3(~na12_1), .IN4(~na2296_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x134y51 80'h00_0018_00_0000_0EEE_D7ED +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a32_1 ( .OUT(na32_1), .IN1(~na38_1), .IN2(na36_1), .IN3(na2444_1), .IN4(na2440_1), .IN5(~na38_2), .IN6(~na2443_2), .IN7(~na2441_1), + .IN8(na2440_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x123y50 80'h00_0018_00_0000_0C88_5AFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a36_1 ( .OUT(na36_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2351_1), .IN6(1'b1), .IN7(~na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x135y53 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a38_1 ( .OUT(na38_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2101_1), .IN6(~na4_2), .IN7(~na12_1), .IN8(~na2301_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a38_4 ( .OUT(na38_2), .IN1(~na2251_1), .IN2(~na4_1), .IN3(~na12_2), .IN4(~na2151_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x134y53 80'h00_0018_00_0000_0EEE_D7EB +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a39_1 ( .OUT(na39_1), .IN1(na2523_2), .IN2(~na45_1), .IN3(na43_2), .IN4(na2453_2), .IN5(~na2452_1), .IN6(~na45_2), .IN7(~na2450_2), + .IN8(na2449_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x124y51 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a43_4 ( .OUT(na43_2), .IN1(1'b1), .IN2(na2356_1), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x141y50 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a45_1 ( .OUT(na45_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na13_2), .IN6(~na1906_1), .IN7(~na12_2), .IN8(~na2156_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a45_4 ( .OUT(na45_2), .IN1(~na13_1), .IN2(~na1956_1), .IN3(~na12_1), .IN4(~na2306_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x137y57 80'h00_0018_00_0000_0EEE_B7BE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a46_1 ( .OUT(na46_1), .IN1(na2462_1), .IN2(na50_1), .IN3(na2458_1), .IN4(~na52_1), .IN5(~na2461_2), .IN6(~na2459_1), .IN7(na2458_2), + .IN8(~na52_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x123y60 80'h00_0018_00_0000_0C88_5CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a50_1 ( .OUT(na50_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2361_1), .IN7(~na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x142y56 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a52_1 ( .OUT(na52_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na13_2), .IN6(~na1911_1), .IN7(~na12_2), .IN8(~na2161_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a52_4 ( .OUT(na52_2), .IN1(~na13_1), .IN2(~na1961_1), .IN3(~na12_1), .IN4(~na2311_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x135y63 80'h00_0018_00_0000_0EEE_7DBE +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a53_1 ( .OUT(na53_1), .IN1(na57_2), .IN2(na2467_1), .IN3(na2471_2), .IN4(~na59_1), .IN5(~na2468_2), .IN6(na2467_2), .IN7(~na2470_1), + .IN8(~na59_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x121y65 80'h00_0060_00_0000_0C08_FF5C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a57_4 ( .OUT(na57_2), .IN1(1'b1), .IN2(na2366_1), .IN3(~na10_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x142y58 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a59_1 ( .OUT(na59_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na13_2), .IN6(~na1916_1), .IN7(~na12_2), .IN8(~na2166_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a59_4 ( .OUT(na59_2), .IN1(~na13_1), .IN2(~na1966_1), .IN3(~na12_1), .IN4(~na2316_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x135y64 80'h00_0018_00_0000_0EEE_B7ED +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a60_1 ( .OUT(na60_1), .IN1(~na66_1), .IN2(na2480_1), .IN3(na2476_1), .IN4(na64_1), .IN5(~na66_2), .IN6(~na2479_2), .IN7(na2476_2), + .IN8(~na2477_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x122y66 80'h00_0018_00_0000_0C88_5CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a64_1 ( .OUT(na64_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2371_1), .IN7(~na10_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x145y61 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a66_1 ( .OUT(na66_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na13_2), .IN6(~na1921_1), .IN7(~na12_2), .IN8(~na2171_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a66_4 ( .OUT(na66_2), .IN1(~na13_1), .IN2(~na1971_1), .IN3(~na12_1), .IN4(~na2321_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x136y66 80'h00_0018_00_0000_0EEE_D7ED +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a67_1 ( .OUT(na67_1), .IN1(~na73_1), .IN2(na71_2), .IN3(na2489_2), .IN4(na2485_1), .IN5(~na73_2), .IN6(~na2488_1), .IN7(~na2486_2), + .IN8(na2485_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x125y66 80'h00_0060_00_0000_0C08_FF2F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a71_4 ( .OUT(na71_2), .IN1(1'b1), .IN2(1'b1), .IN3(na2376_1), .IN4(~na2518_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x145y65 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a73_1 ( .OUT(na73_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na13_2), .IN6(~na1926_1), .IN7(~na12_2), .IN8(~na2176_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a73_4 ( .OUT(na73_2), .IN1(~na13_1), .IN2(~na1976_1), .IN3(~na12_1), .IN4(~na2326_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x136y68 80'h00_0018_00_0000_0EEE_7DED +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a74_1 ( .OUT(na74_1), .IN1(~na80_1), .IN2(na2494_1), .IN3(na78_1), .IN4(na2498_1), .IN5(~na80_2), .IN6(na2494_2), .IN7(~na2495_1), + .IN8(~na2497_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x126y67 80'h00_0018_00_0000_0C88_2FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a78_1 ( .OUT(na78_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2381_1), .IN8(~na2518_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ORAND///ORAND/ x135y65 80'h00_0078_00_0000_0C88_7777 +C_ORAND #(.CPE_CFG (9'b0_0000_0000)) + _a80_1 ( .OUT(na80_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na5_2), .IN6(~na2081_1), .IN7(~na12_1), .IN8(~na2331_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_ORAND #(.CPE_CFG (9'b0_1000_0000)) + _a80_4 ( .OUT(na80_2), .IN1(~na2281_1), .IN2(~na4_1), .IN3(~na12_2), .IN4(~na2181_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x134y52 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a81_4 ( .OUT(na81_2), .IN1(na82_2), .IN2(1'b1), .IN3(na84_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x131y55 80'h00_0060_00_0000_0C08_FF8C +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a82_4 ( .OUT(na82_2), .IN1(1'b1), .IN2(na2521_2), .IN3(na83_1), .IN4(na277_2), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x134y59 80'h00_0018_00_0000_0C88_48FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a83_1 ( .OUT(na83_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2411_1), .IN6(na2386_1), .IN7(~na2524_2), .IN8(na277_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x128y61 80'h00_0060_00_0000_0C08_FF81 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a84_4 ( .OUT(na84_2), .IN1(~na2384_1), .IN2(~na2383_1), .IN3(na2385_1), .IN4(na2382_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x138y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a85_1 ( .OUT(na85_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na86_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y61 80'h00_0018_00_0000_0C88_21FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a86_1 ( .OUT(na86_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2384_1), .IN6(~na2383_1), .IN7(na2385_1), + .IN8(~na2382_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x135y49 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a87_4 ( .OUT(na87_2), .IN1(na82_2), .IN2(1'b1), .IN3(na88_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x132y61 80'h00_0018_00_0000_0C88_48FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a88_1 ( .OUT(na88_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2384_1), .IN6(na2383_1), .IN7(~na2385_1), .IN8(na2382_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x141y53 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a89_1 ( .OUT(na89_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na90_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y59 80'h00_0018_00_0000_0C88_42FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a90_1 ( .OUT(na90_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2384_1), .IN6(~na2383_1), .IN7(~na2385_1), + .IN8(na2382_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x137y50 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a91_4 ( .OUT(na91_2), .IN1(na82_2), .IN2(1'b1), .IN3(na92_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x130y61 80'h00_0018_00_0000_0C88_18FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a92_1 ( .OUT(na92_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2384_1), .IN6(na2383_1), .IN7(~na2385_1), .IN8(~na2382_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x138y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a93_1 ( .OUT(na93_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na94_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y63 80'h00_0018_00_0000_0C88_81FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a94_1 ( .OUT(na94_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2384_1), .IN6(~na2382_1), .IN7(na2385_1), + .IN8(na2383_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x135y51 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a95_4 ( .OUT(na95_2), .IN1(na82_2), .IN2(1'b1), .IN3(na96_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x132y57 80'h00_0018_00_0000_0C88_84FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a96_1 ( .OUT(na96_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2384_1), .IN6(na2383_1), .IN7(na2385_1), .IN8(na2382_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x142y54 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a97_1 ( .OUT(na97_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na98_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x130y59 80'h00_0018_00_0000_0C88_12FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a98_1 ( .OUT(na98_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2384_1), .IN6(~na2383_1), .IN7(~na2385_1), + .IN8(~na2382_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x115y64 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a99_4 ( .OUT(na99_2), .IN1(1'b1), .IN2(na100_1), .IN3(na102_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x115y62 80'h00_0018_00_0000_0888_4532 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a100_1 ( .OUT(na100_1), .IN1(na2411_1), .IN2(~na2386_1), .IN3(1'b1), .IN4(~na277_1), .IN5(~na2519_2), .IN6(1'b1), .IN7(~na279_1), + .IN8(na2503_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x128y59 80'h00_0060_00_0000_0C08_FF88 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a102_4 ( .OUT(na102_2), .IN1(na2384_1), .IN2(na2383_1), .IN3(na2385_1), .IN4(na2382_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x114y64 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a103_4 ( .OUT(na103_2), .IN1(1'b1), .IN2(na100_1), .IN3(na104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x126y63 80'h00_0060_00_0000_0C08_FF28 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a104_4 ( .OUT(na104_2), .IN1(na2384_1), .IN2(na2383_1), .IN3(na2385_1), .IN4(~na2382_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x115y63 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a105_4 ( .OUT(na105_2), .IN1(1'b1), .IN2(na100_1), .IN3(na106_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x126y61 80'h00_0060_00_0000_0C08_FF82 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a106_4 ( .OUT(na106_2), .IN1(na2384_1), .IN2(~na2383_1), .IN3(na2385_1), .IN4(na2382_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x140y53 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a107_1 ( .OUT(na107_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na108_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x128y57 80'h00_0060_00_0000_0C08_FF44 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a108_4 ( .OUT(na108_2), .IN1(~na2384_1), .IN2(na2383_1), .IN3(~na2385_1), .IN4(na2382_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x113y63 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a109_4 ( .OUT(na109_2), .IN1(1'b1), .IN2(na100_1), .IN3(na110_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x130y63 80'h00_0018_00_0000_0C88_22FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a110_1 ( .OUT(na110_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2384_1), .IN6(~na2383_1), .IN7(na2385_1), + .IN8(~na2382_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x111y62 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a111_1 ( .OUT(na111_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na100_1), .IN7(na96_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x116y66 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a112_4 ( .OUT(na112_2), .IN1(1'b1), .IN2(na100_1), .IN3(na94_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x112y62 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a113_1 ( .OUT(na113_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na100_1), .IN7(na84_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x114y61 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a114_4 ( .OUT(na114_2), .IN1(1'b1), .IN2(na100_1), .IN3(na86_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x138y53 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a115_1 ( .OUT(na115_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na116_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x126y59 80'h00_0018_00_0000_0C88_41FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a116_1 ( .OUT(na116_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2384_1), .IN6(~na2382_1), .IN7(~na2385_1), + .IN8(na2383_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x114y58 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a117_4 ( .OUT(na117_2), .IN1(1'b1), .IN2(na100_1), .IN3(na88_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x112y59 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a118_1 ( .OUT(na118_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na100_1), .IN7(na92_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x133y49 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a119_4 ( .OUT(na119_2), .IN1(na82_2), .IN2(1'b1), .IN3(na120_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x126y57 80'h00_0018_00_0000_0C88_41FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a120_1 ( .OUT(na120_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2384_1), .IN6(~na2383_1), .IN7(~na2385_1), + .IN8(na2382_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x110y62 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a121_1 ( .OUT(na121_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na100_1), .IN7(na90_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x115y58 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a122_4 ( .OUT(na122_2), .IN1(1'b1), .IN2(na100_1), .IN3(na98_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x142y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a123_1 ( .OUT(na123_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na124_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y57 80'h00_0018_00_0000_0C88_11FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a124_1 ( .OUT(na124_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(~na2384_1), .IN6(~na2383_1), .IN7(~na2385_1), + .IN8(~na2382_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x109y59 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a125_4 ( .OUT(na125_2), .IN1(1'b1), .IN2(na100_1), .IN3(na108_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x110y58 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a126_1 ( .OUT(na126_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na100_1), .IN7(na116_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x113y59 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a127_4 ( .OUT(na127_2), .IN1(1'b1), .IN2(na100_1), .IN3(na120_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x109y58 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a128_1 ( .OUT(na128_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na100_1), .IN7(na124_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x132y55 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a129_4 ( .OUT(na129_2), .IN1(na82_2), .IN2(1'b1), .IN3(na106_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x142y57 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a130_1 ( .OUT(na130_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na110_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x136y53 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a131_4 ( .OUT(na131_2), .IN1(na82_2), .IN2(1'b1), .IN3(na104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x139y56 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a132_1 ( .OUT(na132_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na82_2), .IN6(1'b1), .IN7(na102_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x137y47 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a133_4 ( .OUT(na133_2), .IN1(na134_1), .IN2(1'b1), .IN3(na124_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x141y55 80'h00_0018_00_0000_0888_C823 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a134_1 ( .OUT(na134_1), .IN1(1'b1), .IN2(~na2386_1), .IN3(na279_1), .IN4(~na2503_1), .IN5(na2411_1), .IN6(na2520_2), .IN7(1'b1), + .IN8(na277_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x141y51 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a136_1 ( .OUT(na136_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na120_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x139y52 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a137_4 ( .OUT(na137_2), .IN1(na134_1), .IN2(1'b1), .IN3(na116_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x143y54 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a138_1 ( .OUT(na138_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na108_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x137y52 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a139_4 ( .OUT(na139_2), .IN1(na134_1), .IN2(1'b1), .IN3(na98_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x141y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a140_1 ( .OUT(na140_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na90_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x136y55 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a141_4 ( .OUT(na141_2), .IN1(na134_1), .IN2(1'b1), .IN3(na92_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x145y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a142_1 ( .OUT(na142_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na88_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x138y54 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a143_4 ( .OUT(na143_2), .IN1(na134_1), .IN2(1'b1), .IN3(na86_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x145y54 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a144_1 ( .OUT(na144_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na84_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x140y53 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a145_4 ( .OUT(na145_2), .IN1(na134_1), .IN2(1'b1), .IN3(na94_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x144y54 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a146_1 ( .OUT(na146_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na96_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x137y55 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a147_4 ( .OUT(na147_2), .IN1(na134_1), .IN2(1'b1), .IN3(na110_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x145y56 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a148_1 ( .OUT(na148_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na106_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x138y56 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a149_4 ( .OUT(na149_2), .IN1(na134_1), .IN2(1'b1), .IN3(na104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x143y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a150_1 ( .OUT(na150_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na134_1), .IN6(1'b1), .IN7(na102_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x120y49 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a151_4 ( .OUT(na151_2), .IN1(na152_1), .IN2(1'b1), .IN3(na124_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x123y53 80'h00_0018_00_0000_0888_382C +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a152_1 ( .OUT(na152_1), .IN1(1'b1), .IN2(na2520_2), .IN3(na279_1), .IN4(~na2503_1), .IN5(na2411_1), .IN6(na2386_1), .IN7(1'b1), + .IN8(~na277_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x118y52 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a154_1 ( .OUT(na154_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na120_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x123y51 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a155_4 ( .OUT(na155_2), .IN1(na152_1), .IN2(1'b1), .IN3(na116_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x121y52 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a156_1 ( .OUT(na156_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na108_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x122y50 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a157_4 ( .OUT(na157_2), .IN1(na152_1), .IN2(1'b1), .IN3(na98_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x119y51 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a158_1 ( .OUT(na158_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na90_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x123y50 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a159_4 ( .OUT(na159_2), .IN1(na152_1), .IN2(1'b1), .IN3(na92_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x120y52 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a160_1 ( .OUT(na160_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na88_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x127y55 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a161_4 ( .OUT(na161_2), .IN1(na152_1), .IN2(1'b1), .IN3(na86_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x123y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a162_1 ( .OUT(na162_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na84_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x125y58 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a163_4 ( .OUT(na163_2), .IN1(na152_1), .IN2(1'b1), .IN3(na94_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x121y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a164_1 ( .OUT(na164_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na96_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x124y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a165_1 ( .OUT(na165_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na110_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x125y55 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a166_1 ( .OUT(na166_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na106_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x125y59 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a167_4 ( .OUT(na167_2), .IN1(na152_1), .IN2(1'b1), .IN3(na104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x122y56 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a168_1 ( .OUT(na168_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na152_1), .IN6(1'b1), .IN7(na102_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x119y57 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a169_4 ( .OUT(na169_2), .IN1(1'b1), .IN2(1'b1), .IN3(na124_1), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y56 80'h00_0018_00_0000_0888_3A22 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a170_1 ( .OUT(na170_1), .IN1(na2519_2), .IN2(~na2386_1), .IN3(na279_1), .IN4(~na277_1), .IN5(na2411_1), .IN6(1'b1), .IN7(1'b1), + .IN8(~na2503_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x116y54 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a172_1 ( .OUT(na172_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na120_1), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x120y57 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a173_4 ( .OUT(na173_2), .IN1(1'b1), .IN2(1'b1), .IN3(na116_1), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x116y55 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a174_1 ( .OUT(na174_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na108_2), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x122y58 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a175_4 ( .OUT(na175_2), .IN1(1'b1), .IN2(1'b1), .IN3(na98_1), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x118y53 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a176_1 ( .OUT(na176_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na90_1), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x123y57 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a177_4 ( .OUT(na177_2), .IN1(1'b1), .IN2(1'b1), .IN3(na92_1), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x118y55 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a178_1 ( .OUT(na178_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na88_1), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x122y53 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a179_4 ( .OUT(na179_2), .IN1(1'b1), .IN2(1'b1), .IN3(na86_1), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x120y54 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a180_1 ( .OUT(na180_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na84_2), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x124y53 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a181_4 ( .OUT(na181_2), .IN1(1'b1), .IN2(1'b1), .IN3(na94_1), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x119y54 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a182_1 ( .OUT(na182_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na96_1), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x121y56 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a183_4 ( .OUT(na183_2), .IN1(1'b1), .IN2(1'b1), .IN3(na110_1), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x122y54 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a184_1 ( .OUT(na184_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na106_2), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x119y55 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a185_4 ( .OUT(na185_2), .IN1(1'b1), .IN2(1'b1), .IN3(na104_2), .IN4(na170_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x122y53 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a186_1 ( .OUT(na186_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na102_2), .IN8(na170_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x123y61 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a187_4 ( .OUT(na187_2), .IN1(1'b1), .IN2(1'b1), .IN3(na124_1), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y60 80'h00_0018_00_0000_0C88_2CFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a188_1 ( .OUT(na188_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2522_2), .IN7(na83_1), .IN8(~na277_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x127y55 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a189_1 ( .OUT(na189_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na120_1), .IN8(na188_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x125y62 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a190_4 ( .OUT(na190_2), .IN1(1'b1), .IN2(1'b1), .IN3(na116_1), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x125y58 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a191_1 ( .OUT(na191_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na108_2), .IN8(na188_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x126y64 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a192_4 ( .OUT(na192_2), .IN1(1'b1), .IN2(1'b1), .IN3(na98_1), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y55 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a193_1 ( .OUT(na193_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na90_1), .IN8(na188_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x126y59 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a194_4 ( .OUT(na194_2), .IN1(1'b1), .IN2(1'b1), .IN3(na92_1), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x126y60 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a195_1 ( .OUT(na195_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na88_1), .IN8(na188_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x123y56 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a196_4 ( .OUT(na196_2), .IN1(1'b1), .IN2(1'b1), .IN3(na86_1), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x126y56 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a197_1 ( .OUT(na197_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na84_2), .IN8(na188_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x124y58 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a198_4 ( .OUT(na198_2), .IN1(1'b1), .IN2(1'b1), .IN3(na94_1), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x125y54 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a199_1 ( .OUT(na199_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na96_1), .IN8(na188_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x125y61 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a200_4 ( .OUT(na200_2), .IN1(1'b1), .IN2(1'b1), .IN3(na110_1), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x128y55 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a201_4 ( .OUT(na201_2), .IN1(1'b1), .IN2(1'b1), .IN3(na106_2), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x128y58 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a202_1 ( .OUT(na202_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na104_2), .IN8(na188_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x123y60 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a203_4 ( .OUT(na203_2), .IN1(1'b1), .IN2(1'b1), .IN3(na102_2), .IN4(na188_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x136y60 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a204_4 ( .OUT(na204_2), .IN1(na205_1), .IN2(1'b1), .IN3(na124_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x143y59 80'h00_0018_00_0000_0888_C223 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a205_1 ( .OUT(na205_1), .IN1(1'b1), .IN2(~na2386_1), .IN3(na279_1), .IN4(~na2503_1), .IN5(na2411_1), .IN6(~na2520_2), .IN7(1'b1), + .IN8(na277_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x145y59 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a206_1 ( .OUT(na206_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na120_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x144y60 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a207_1 ( .OUT(na207_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na116_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x145y60 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a208_1 ( .OUT(na208_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na108_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x143y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a209_1 ( .OUT(na209_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na98_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x137y59 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a210_4 ( .OUT(na210_2), .IN1(na205_1), .IN2(1'b1), .IN3(na90_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x146y60 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a211_1 ( .OUT(na211_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na92_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x139y59 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a212_4 ( .OUT(na212_2), .IN1(na205_1), .IN2(1'b1), .IN3(na88_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x138y58 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a213_4 ( .OUT(na213_2), .IN1(na205_1), .IN2(1'b1), .IN3(na86_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x146y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a214_1 ( .OUT(na214_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na84_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x142y57 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a215_4 ( .OUT(na215_2), .IN1(na205_1), .IN2(1'b1), .IN3(na94_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x139y57 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a216_4 ( .OUT(na216_2), .IN1(na205_1), .IN2(1'b1), .IN3(na96_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x138y57 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a217_4 ( .OUT(na217_2), .IN1(na205_1), .IN2(1'b1), .IN3(na110_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x147y60 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a218_1 ( .OUT(na218_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na106_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x140y60 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a219_4 ( .OUT(na219_2), .IN1(na205_1), .IN2(1'b1), .IN3(na104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x145y57 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a220_1 ( .OUT(na220_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na205_1), .IN6(1'b1), .IN7(na102_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x116y60 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a221_4 ( .OUT(na221_2), .IN1(na222_1), .IN2(1'b1), .IN3(na124_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x117y59 80'h00_0018_00_0000_0888_3825 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a222_1 ( .OUT(na222_1), .IN1(~na2519_2), .IN2(1'b1), .IN3(na279_1), .IN4(~na2503_1), .IN5(na2411_1), .IN6(na2386_1), .IN7(1'b1), + .IN8(~na277_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x111y57 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a223_1 ( .OUT(na223_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na120_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x112y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a224_1 ( .OUT(na224_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na116_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x116y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a225_1 ( .OUT(na225_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na108_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x117y60 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a226_4 ( .OUT(na226_2), .IN1(na222_1), .IN2(1'b1), .IN3(na98_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x117y57 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a227_1 ( .OUT(na227_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na90_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x119y59 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a228_4 ( .OUT(na228_2), .IN1(na222_1), .IN2(1'b1), .IN3(na92_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x115y58 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a229_1 ( .OUT(na229_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na88_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x120y59 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a230_4 ( .OUT(na230_2), .IN1(na222_1), .IN2(1'b1), .IN3(na86_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x114y60 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a231_1 ( .OUT(na231_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na84_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x119y61 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a232_4 ( .OUT(na232_2), .IN1(na222_1), .IN2(1'b1), .IN3(na94_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x115y59 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a233_1 ( .OUT(na233_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na96_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x118y61 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a234_4 ( .OUT(na234_2), .IN1(na222_1), .IN2(1'b1), .IN3(na110_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x113y60 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a235_1 ( .OUT(na235_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na222_1), .IN6(1'b1), .IN7(na106_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x117y64 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a236_4 ( .OUT(na236_2), .IN1(na222_1), .IN2(1'b1), .IN3(na104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x116y61 80'h00_0060_00_0000_0C08_FFAA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a237_4 ( .OUT(na237_2), .IN1(na222_1), .IN2(1'b1), .IN3(na102_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x132y60 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a238_4 ( .OUT(na238_2), .IN1(1'b1), .IN2(na239_1), .IN3(na124_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x137y62 80'h00_0018_00_0000_0888_3223 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a239_1 ( .OUT(na239_1), .IN1(1'b1), .IN2(~na2386_1), .IN3(na279_1), .IN4(~na277_1), .IN5(na2411_1), .IN6(~na2520_2), .IN7(1'b1), + .IN8(~na2503_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x135y57 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a240_1 ( .OUT(na240_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na120_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x130y59 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a241_4 ( .OUT(na241_2), .IN1(1'b1), .IN2(na239_1), .IN3(na116_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x135y58 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a242_1 ( .OUT(na242_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na108_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x127y59 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a243_4 ( .OUT(na243_2), .IN1(1'b1), .IN2(na239_1), .IN3(na98_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x132y59 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a244_1 ( .OUT(na244_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na90_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x129y59 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a245_4 ( .OUT(na245_2), .IN1(1'b1), .IN2(na239_1), .IN3(na92_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x133y61 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a246_1 ( .OUT(na246_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na88_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x131y57 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a247_4 ( .OUT(na247_2), .IN1(1'b1), .IN2(na239_1), .IN3(na86_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x135y62 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a248_1 ( .OUT(na248_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na84_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x131y60 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a249_4 ( .OUT(na249_2), .IN1(1'b1), .IN2(na239_1), .IN3(na94_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x134y62 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a250_1 ( .OUT(na250_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na96_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x133y60 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a251_1 ( .OUT(na251_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na110_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x137y60 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a252_1 ( .OUT(na252_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na106_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x132y58 80'h00_0060_00_0000_0C08_FFAC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a253_4 ( .OUT(na253_2), .IN1(1'b1), .IN2(na239_1), .IN3(na104_2), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x133y57 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a254_1 ( .OUT(na254_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na239_1), .IN7(na102_2), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x139y56 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a255_4 ( .OUT(na255_2), .IN1(1'b1), .IN2(1'b1), .IN3(na124_1), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x144y58 80'h00_0018_00_0000_0C88_83FF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a256_1 ( .OUT(na256_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(~na2521_2), .IN7(na83_1), .IN8(na277_2), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x146y56 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a257_1 ( .OUT(na257_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na120_1), .IN8(na256_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x142y55 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a258_4 ( .OUT(na258_2), .IN1(1'b1), .IN2(1'b1), .IN3(na116_1), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x147y56 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a259_1 ( .OUT(na259_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na108_2), .IN8(na256_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x138y61 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a260_4 ( .OUT(na260_2), .IN1(1'b1), .IN2(1'b1), .IN3(na98_1), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x150y55 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a261_1 ( .OUT(na261_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na90_1), .IN8(na256_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x143y61 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a262_4 ( .OUT(na262_2), .IN1(1'b1), .IN2(1'b1), .IN3(na92_1), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x149y56 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a263_1 ( .OUT(na263_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na88_1), .IN8(na256_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x142y54 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a264_4 ( .OUT(na264_2), .IN1(1'b1), .IN2(1'b1), .IN3(na86_1), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x141y64 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a265_4 ( .OUT(na265_2), .IN1(1'b1), .IN2(1'b1), .IN3(na84_2), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x141y60 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a266_4 ( .OUT(na266_2), .IN1(1'b1), .IN2(1'b1), .IN3(na94_1), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x148y56 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a267_1 ( .OUT(na267_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na96_1), .IN8(na256_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x145y63 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a268_4 ( .OUT(na268_2), .IN1(1'b1), .IN2(1'b1), .IN3(na110_1), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x147y58 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a269_1 ( .OUT(na269_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na106_2), .IN8(na256_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x144y64 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a270_4 ( .OUT(na270_2), .IN1(1'b1), .IN2(1'b1), .IN3(na104_2), .IN4(na256_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x150y56 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a271_1 ( .OUT(na271_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na102_2), .IN8(na256_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF2///ADDF2/ x130y56 80'h00_0078_00_0020_0C66_5330 +C_ADDF2 #(.CPE_CFG (9'b0_0010_0000)) + _a277_1 ( .OUT(na277_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b1), .IN6(~na2386_1), .IN7(~na2387_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(na280_4), .PINX(1'b0), .PINY1(1'b0) ); +C_ADDF2 #(.CPE_CFG (9'b0_1000_0000)) + _a277_4 ( .OUT(na277_2), .COUTY1(na277_4), .IN1(1'b0), .IN2(1'b0), .IN3(1'b1), .IN4(~na2388_1), .IN5(1'b1), .IN6(~na2386_1), + .IN7(~na2387_1), .IN8(1'b1), .CINX(1'b0), .CINY1(na280_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_ADDF//// x130y57 80'h00_0018_00_0010_0666_0005 +C_ADDF #(.CPE_CFG (9'b0_0010_0000)) + _a279_1 ( .OUT(na279_1), .COUTY1(na279_4), .IN1(~na2389_1), .IN2(1'b1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), + .IN8(1'b0), .CINX(1'b0), .CINY1(na277_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_/C_0_1/// x130y55 80'h00_CF00_12_0800_0C00_FFFF +C_C_0_1 #(.CPE_CFG (9'bX_0000_0000)) + _a280_2 ( .OUT(na280_1), .CLK(1'b1), .EN(1'b1), .SR(1'b0), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN() ); +C_CPlines #(.CPE_CFG (19'h1_2080)) + _a280_6 ( .COUTY1(na280_4), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(na280_1), + .OUT2(1'b0), .COMP_OUT(1'b0) ); +// C_///AND/D x136y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a282_4 ( .OUT(na282_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a282_5 ( .OUT(na282_2), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na282_2_i) ); +// C_AND/D/// x137y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a283_1 ( .OUT(na283_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a283_2 ( .OUT(na283_1), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na283_1_i) ); +// C_AND/D/// x146y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a284_1 ( .OUT(na284_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a284_2 ( .OUT(na284_1), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na284_1_i) ); +// C_AND/D/// x127y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a285_1 ( .OUT(na285_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a285_2 ( .OUT(na285_1), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na285_1_i) ); +// C_///AND/D x136y49 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a286_4 ( .OUT(na286_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a286_5 ( .OUT(na286_2), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na286_2_i) ); +// C_///AND/D x142y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a287_4 ( .OUT(na287_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a287_5 ( .OUT(na287_2), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na287_2_i) ); +// C_///AND/D x130y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a288_4 ( .OUT(na288_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a288_5 ( .OUT(na288_2), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na288_2_i) ); +// C_AND/D/// x142y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a289_1 ( .OUT(na289_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a289_2 ( .OUT(na289_1), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na289_1_i) ); +// C_AND/D/// x142y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a290_1 ( .OUT(na290_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a290_2 ( .OUT(na290_1), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na290_1_i) ); +// C_AND/D/// x133y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a291_1 ( .OUT(na291_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a291_2 ( .OUT(na291_1), .CLK(na2414_1), .EN(na97_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na291_1_i) ); +// C_///AND/D x142y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a292_4 ( .OUT(na292_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a292_5 ( .OUT(na292_2), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na292_2_i) ); +// C_AND/D/// x146y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a293_1 ( .OUT(na293_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a293_2 ( .OUT(na293_1), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na293_1_i) ); +// C_///AND/D x139y41 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a294_4 ( .OUT(na294_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a294_5 ( .OUT(na294_2), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na294_2_i) ); +// C_///AND/D x124y47 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a295_4 ( .OUT(na295_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a295_5 ( .OUT(na295_2), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na295_2_i) ); +// C_///AND/D x146y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a296_4 ( .OUT(na296_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a296_5 ( .OUT(na296_2), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na296_2_i) ); +// C_AND/D/// x148y53 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a297_1 ( .OUT(na297_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a297_2 ( .OUT(na297_1), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na297_1_i) ); +// C_AND/D/// x140y61 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a298_1 ( .OUT(na298_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a298_2 ( .OUT(na298_1), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na298_1_i) ); +// C_AND/D/// x139y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a299_1 ( .OUT(na299_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a299_2 ( .OUT(na299_1), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na299_1_i) ); +// C_///AND/D x142y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a300_4 ( .OUT(na300_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a300_5 ( .OUT(na300_2), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na300_2_i) ); +// C_///AND/D x134y84 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a301_4 ( .OUT(na301_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a301_5 ( .OUT(na301_2), .CLK(na2414_1), .EN(na131_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na301_2_i) ); +// C_///AND/D x139y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a302_4 ( .OUT(na302_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a302_5 ( .OUT(na302_2), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na302_2_i) ); +// C_AND/D/// x147y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a303_1 ( .OUT(na303_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a303_2 ( .OUT(na303_1), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na303_1_i) ); +// C_///AND/D x136y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a304_4 ( .OUT(na304_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a304_5 ( .OUT(na304_2), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na304_2_i) ); +// C_AND/D/// x123y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a305_1 ( .OUT(na305_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a305_2 ( .OUT(na305_1), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na305_1_i) ); +// C_AND/D/// x151y48 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a306_1 ( .OUT(na306_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a306_2 ( .OUT(na306_1), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na306_1_i) ); +// C_AND/D/// x149y54 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a307_1 ( .OUT(na307_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a307_2 ( .OUT(na307_1), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na307_1_i) ); +// C_///AND/D x133y62 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a308_4 ( .OUT(na308_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a308_5 ( .OUT(na308_2), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na308_2_i) ); +// C_///AND/D x142y72 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a309_4 ( .OUT(na309_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a309_5 ( .OUT(na309_2), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na309_2_i) ); +// C_///AND/D x143y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a310_4 ( .OUT(na310_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a310_5 ( .OUT(na310_2), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na310_2_i) ); +// C_AND/D/// x135y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a311_1 ( .OUT(na311_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a311_2 ( .OUT(na311_1), .CLK(na2414_1), .EN(na129_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na311_1_i) ); +// C_AND/D/// x147y37 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a312_1 ( .OUT(na312_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a312_2 ( .OUT(na312_1), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na312_1_i) ); +// C_AND/D/// x147y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a313_1 ( .OUT(na313_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a313_2 ( .OUT(na313_1), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na313_1_i) ); +// C_///AND/D x136y41 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a314_4 ( .OUT(na314_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a314_5 ( .OUT(na314_2), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na314_2_i) ); +// C_AND/D/// x125y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a315_1 ( .OUT(na315_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a315_2 ( .OUT(na315_1), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na315_1_i) ); +// C_///AND/D x147y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a316_4 ( .OUT(na316_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a316_5 ( .OUT(na316_2), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na316_2_i) ); +// C_///AND/D x145y59 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a317_4 ( .OUT(na317_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a317_5 ( .OUT(na317_2), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na317_2_i) ); +// C_///AND/D x137y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a318_4 ( .OUT(na318_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a318_5 ( .OUT(na318_2), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na318_2_i) ); +// C_AND/D/// x140y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a319_1 ( .OUT(na319_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a319_2 ( .OUT(na319_1), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na319_1_i) ); +// C_AND/D/// x145y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a320_1 ( .OUT(na320_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a320_2 ( .OUT(na320_1), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na320_1_i) ); +// C_AND/D/// x135y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a321_1 ( .OUT(na321_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a321_2 ( .OUT(na321_1), .CLK(na2414_1), .EN(na130_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na321_1_i) ); +// C_///AND/D x141y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a322_4 ( .OUT(na322_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a322_5 ( .OUT(na322_2), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na322_2_i) ); +// C_///AND/D x136y36 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a323_4 ( .OUT(na323_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a323_5 ( .OUT(na323_2), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na323_2_i) ); +// C_///AND/D x136y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a324_4 ( .OUT(na324_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a324_5 ( .OUT(na324_2), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na324_2_i) ); +// C_AND/D/// x121y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a325_1 ( .OUT(na325_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a325_2 ( .OUT(na325_1), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na325_1_i) ); +// C_///AND/D x144y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a326_4 ( .OUT(na326_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a326_5 ( .OUT(na326_2), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na326_2_i) ); +// C_AND/D/// x145y50 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a327_1 ( .OUT(na327_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a327_2 ( .OUT(na327_1), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na327_1_i) ); +// C_AND/D/// x141y64 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a328_1 ( .OUT(na328_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a328_2 ( .OUT(na328_1), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na328_1_i) ); +// C_AND/D/// x139y66 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a329_1 ( .OUT(na329_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a329_2 ( .OUT(na329_1), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na329_1_i) ); +// C_///AND/D x136y73 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a330_4 ( .OUT(na330_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a330_5 ( .OUT(na330_2), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na330_2_i) ); +// C_///AND/D x128y82 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a331_4 ( .OUT(na331_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a331_5 ( .OUT(na331_2), .CLK(na2414_1), .EN(na95_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na331_2_i) ); +// C_///AND/D x139y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a332_4 ( .OUT(na332_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a332_5 ( .OUT(na332_2), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na332_2_i) ); +// C_AND/D/// x136y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a333_1 ( .OUT(na333_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a333_2 ( .OUT(na333_1), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na333_1_i) ); +// C_AND/D/// x144y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a334_1 ( .OUT(na334_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a334_2 ( .OUT(na334_1), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na334_1_i) ); +// C_AND/D/// x121y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a335_1 ( .OUT(na335_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a335_2 ( .OUT(na335_1), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na335_1_i) ); +// C_///AND/D x146y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a336_4 ( .OUT(na336_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a336_5 ( .OUT(na336_2), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na336_2_i) ); +// C_AND/D/// x145y49 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a337_1 ( .OUT(na337_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a337_2 ( .OUT(na337_1), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na337_1_i) ); +// C_///AND/D x139y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a338_4 ( .OUT(na338_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a338_5 ( .OUT(na338_2), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na338_2_i) ); +// C_///AND/D x139y69 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a339_4 ( .OUT(na339_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a339_5 ( .OUT(na339_2), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na339_2_i) ); +// C_///AND/D x142y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a340_4 ( .OUT(na340_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a340_5 ( .OUT(na340_2), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na340_2_i) ); +// C_AND/D/// x122y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a341_1 ( .OUT(na341_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a341_2 ( .OUT(na341_1), .CLK(na2414_1), .EN(na93_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na341_1_i) ); +// C_AND/D/// x148y33 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a342_1 ( .OUT(na342_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a342_2 ( .OUT(na342_1), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na342_1_i) ); +// C_AND/D/// x141y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a343_1 ( .OUT(na343_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a343_2 ( .OUT(na343_1), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na343_1_i) ); +// C_///AND/D x138y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a344_4 ( .OUT(na344_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a344_5 ( .OUT(na344_2), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na344_2_i) ); +// C_///AND/D x127y45 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a345_4 ( .OUT(na345_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a345_5 ( .OUT(na345_2), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na345_2_i) ); +// C_///AND/D x136y50 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a346_4 ( .OUT(na346_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a346_5 ( .OUT(na346_2), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na346_2_i) ); +// C_AND/D/// x144y48 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a347_1 ( .OUT(na347_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a347_2 ( .OUT(na347_1), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na347_1_i) ); +// C_///AND/D x134y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a348_4 ( .OUT(na348_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a348_5 ( .OUT(na348_2), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na348_2_i) ); +// C_AND/D/// x146y66 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a349_1 ( .OUT(na349_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a349_2 ( .OUT(na349_1), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na349_1_i) ); +// C_AND/D/// x144y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a350_1 ( .OUT(na350_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a350_2 ( .OUT(na350_1), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na350_1_i) ); +// C_AND/D/// x131y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a351_1 ( .OUT(na351_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a351_2 ( .OUT(na351_1), .CLK(na2414_1), .EN(na89_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na351_1_i) ); +// C_///AND/D x136y30 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a352_4 ( .OUT(na352_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a352_5 ( .OUT(na352_2), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na352_2_i) ); +// C_///AND/D x136y37 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a353_4 ( .OUT(na353_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a353_5 ( .OUT(na353_2), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na353_2_i) ); +// C_///AND/D x139y37 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a354_4 ( .OUT(na354_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a354_5 ( .OUT(na354_2), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na354_2_i) ); +// C_AND/D/// x124y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a355_1 ( .OUT(na355_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a355_2 ( .OUT(na355_1), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na355_1_i) ); +// C_AND/D/// x148y46 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a356_1 ( .OUT(na356_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a356_2 ( .OUT(na356_1), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na356_1_i) ); +// C_AND/D/// x144y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a357_1 ( .OUT(na357_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a357_2 ( .OUT(na357_1), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na357_1_i) ); +// C_///AND/D x135y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a358_4 ( .OUT(na358_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a358_5 ( .OUT(na358_2), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na358_2_i) ); +// C_AND/D/// x143y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a359_1 ( .OUT(na359_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a359_2 ( .OUT(na359_1), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na359_1_i) ); +// C_///AND/D x143y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a360_4 ( .OUT(na360_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a360_5 ( .OUT(na360_2), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na360_2_i) ); +// C_///AND/D x132y84 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a361_4 ( .OUT(na361_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a361_5 ( .OUT(na361_2), .CLK(na2414_1), .EN(na107_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na361_2_i) ); +// C_///AND/D x137y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a362_4 ( .OUT(na362_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a362_5 ( .OUT(na362_2), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na362_2_i) ); +// C_AND/D/// x141y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a363_1 ( .OUT(na363_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a363_2 ( .OUT(na363_1), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na363_1_i) ); +// C_AND/D/// x146y38 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a364_1 ( .OUT(na364_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a364_2 ( .OUT(na364_1), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na364_1_i) ); +// C_AND/D/// x125y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a365_1 ( .OUT(na365_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a365_2 ( .OUT(na365_1), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na365_1_i) ); +// C_///AND/D x139y45 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a366_4 ( .OUT(na366_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a366_5 ( .OUT(na366_2), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na366_2_i) ); +// C_///AND/D x141y51 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a367_4 ( .OUT(na367_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a367_5 ( .OUT(na367_2), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na367_2_i) ); +// C_///AND/D x136y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a368_4 ( .OUT(na368_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a368_5 ( .OUT(na368_2), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na368_2_i) ); +// C_AND/D/// x144y65 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a369_1 ( .OUT(na369_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a369_2 ( .OUT(na369_1), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na369_1_i) ); +// C_///AND/D x148y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a370_4 ( .OUT(na370_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a370_5 ( .OUT(na370_2), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na370_2_i) ); +// C_AND/D/// x133y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a371_1 ( .OUT(na371_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a371_2 ( .OUT(na371_1), .CLK(na2414_1), .EN(na123_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na371_1_i) ); +// C_AND/D/// x150y37 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a372_1 ( .OUT(na372_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a372_2 ( .OUT(na372_1), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na372_1_i) ); +// C_AND/D/// x135y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a373_1 ( .OUT(na373_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a373_2 ( .OUT(na373_1), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na373_1_i) ); +// C_///AND/D x133y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a374_4 ( .OUT(na374_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a374_5 ( .OUT(na374_2), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na374_2_i) ); +// C_///AND/D x124y45 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a375_4 ( .OUT(na375_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a375_5 ( .OUT(na375_2), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na375_2_i) ); +// C_///AND/D x143y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a376_4 ( .OUT(na376_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a376_5 ( .OUT(na376_2), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na376_2_i) ); +// C_AND/D/// x146y51 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a377_1 ( .OUT(na377_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a377_2 ( .OUT(na377_1), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na377_1_i) ); +// C_AND/D/// x142y63 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a378_1 ( .OUT(na378_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a378_2 ( .OUT(na378_1), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na378_1_i) ); +// C_AND/D/// x140y65 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a379_1 ( .OUT(na379_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a379_2 ( .OUT(na379_1), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na379_1_i) ); +// C_///AND/D x139y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a380_4 ( .OUT(na380_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a380_5 ( .OUT(na380_2), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na380_2_i) ); +// C_AND/D/// x123y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a381_1 ( .OUT(na381_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a381_2 ( .OUT(na381_1), .CLK(na2414_1), .EN(na85_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na381_1_i) ); +// C_///AND/D x139y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a382_4 ( .OUT(na382_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a382_5 ( .OUT(na382_2), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na382_2_i) ); +// C_///AND/D x134y34 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a383_4 ( .OUT(na383_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a383_5 ( .OUT(na383_2), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na383_2_i) ); +// C_///AND/D x139y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a384_4 ( .OUT(na384_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a384_5 ( .OUT(na384_2), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na384_2_i) ); +// C_AND/D/// x130y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a385_1 ( .OUT(na385_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a385_2 ( .OUT(na385_1), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na385_1_i) ); +// C_AND/D/// x145y48 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a386_1 ( .OUT(na386_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a386_2 ( .OUT(na386_1), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na386_1_i) ); +// C_AND/D/// x141y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a387_1 ( .OUT(na387_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a387_2 ( .OUT(na387_1), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na387_1_i) ); +// C_///AND/D x133y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a388_4 ( .OUT(na388_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a388_5 ( .OUT(na388_2), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na388_2_i) ); +// C_///AND/D x141y70 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a389_4 ( .OUT(na389_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a389_5 ( .OUT(na389_2), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na389_2_i) ); +// C_///AND/D x141y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a390_4 ( .OUT(na390_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a390_5 ( .OUT(na390_2), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na390_2_i) ); +// C_AND/D/// x132y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a391_1 ( .OUT(na391_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a391_2 ( .OUT(na391_1), .CLK(na2414_1), .EN(na87_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na391_1_i) ); +// C_///AND/D x141y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a392_4 ( .OUT(na392_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a392_5 ( .OUT(na392_2), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na392_2_i) ); +// C_AND/D/// x142y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a393_1 ( .OUT(na393_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a393_2 ( .OUT(na393_1), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na393_1_i) ); +// C_AND/D/// x147y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a394_1 ( .OUT(na394_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a394_2 ( .OUT(na394_1), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na394_1_i) ); +// C_AND/D/// x130y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a395_1 ( .OUT(na395_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a395_2 ( .OUT(na395_1), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na395_1_i) ); +// C_///AND/D x139y47 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a396_4 ( .OUT(na396_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a396_5 ( .OUT(na396_2), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na396_2_i) ); +// C_///AND/D x139y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a397_4 ( .OUT(na397_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a397_5 ( .OUT(na397_2), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na397_2_i) ); +// C_///AND/D x137y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a398_4 ( .OUT(na398_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a398_5 ( .OUT(na398_2), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na398_2_i) ); +// C_AND/D/// x145y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a399_1 ( .OUT(na399_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a399_2 ( .OUT(na399_1), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na399_1_i) ); +// C_AND/D/// x143y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a400_1 ( .OUT(na400_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a400_2 ( .OUT(na400_1), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na400_1_i) ); +// C_AND/D/// x136y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a401_1 ( .OUT(na401_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a401_2 ( .OUT(na401_1), .CLK(na2414_1), .EN(na91_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na401_1_i) ); +// C_///AND/D x106y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a402_4 ( .OUT(na402_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a402_5 ( .OUT(na402_2), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na402_2_i) ); +// C_AND/D/// x105y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a403_1 ( .OUT(na403_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a403_2 ( .OUT(na403_1), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na403_1_i) ); +// C_///AND/D x109y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a404_4 ( .OUT(na404_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a404_5 ( .OUT(na404_2), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na404_2_i) ); +// C_///AND/D x113y49 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a405_4 ( .OUT(na405_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a405_5 ( .OUT(na405_2), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na405_2_i) ); +// C_///AND/D x107y53 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a406_4 ( .OUT(na406_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a406_5 ( .OUT(na406_2), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na406_2_i) ); +// C_AND/D/// x106y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a407_1 ( .OUT(na407_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a407_2 ( .OUT(na407_1), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na407_1_i) ); +// C_AND/D/// x105y70 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a408_1 ( .OUT(na408_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a408_2 ( .OUT(na408_1), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na408_1_i) ); +// C_AND/D/// x107y77 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a409_1 ( .OUT(na409_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a409_2 ( .OUT(na409_1), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na409_1_i) ); +// C_///AND/D x111y73 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a410_4 ( .OUT(na410_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a410_5 ( .OUT(na410_2), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na410_2_i) ); +// C_///AND/D x127y81 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a411_4 ( .OUT(na411_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a411_5 ( .OUT(na411_2), .CLK(na2414_1), .EN(na128_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na411_2_i) ); +// C_///AND/D x138y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a412_4 ( .OUT(na412_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a412_5 ( .OUT(na412_2), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na412_2_i) ); +// C_AND/D/// x142y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a413_1 ( .OUT(na413_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a413_2 ( .OUT(na413_1), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na413_1_i) ); +// C_///AND/D x137y38 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a414_4 ( .OUT(na414_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a414_5 ( .OUT(na414_2), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na414_2_i) ); +// C_AND/D/// x128y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a415_1 ( .OUT(na415_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a415_2 ( .OUT(na415_1), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na415_1_i) ); +// C_AND/D/// x148y45 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a416_1 ( .OUT(na416_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a416_2 ( .OUT(na416_1), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na416_1_i) ); +// C_AND/D/// x146y53 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a417_1 ( .OUT(na417_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a417_2 ( .OUT(na417_1), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na417_1_i) ); +// C_///AND/D x133y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a418_4 ( .OUT(na418_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a418_5 ( .OUT(na418_2), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na418_2_i) ); +// C_///AND/D x139y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a419_4 ( .OUT(na419_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a419_5 ( .OUT(na419_2), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na419_2_i) ); +// C_///AND/D x139y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a420_4 ( .OUT(na420_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a420_5 ( .OUT(na420_2), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na420_2_i) ); +// C_AND/D/// x130y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a421_1 ( .OUT(na421_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a421_2 ( .OUT(na421_1), .CLK(na2414_1), .EN(na115_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na421_1_i) ); +// C_AND/D/// x143y36 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a422_1 ( .OUT(na422_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a422_2 ( .OUT(na422_1), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na422_1_i) ); +// C_AND/D/// x143y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a423_1 ( .OUT(na423_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a423_2 ( .OUT(na423_1), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na423_1_i) ); +// C_///AND/D x138y37 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a424_4 ( .OUT(na424_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a424_5 ( .OUT(na424_2), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na424_2_i) ); +// C_AND/D/// x129y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a425_1 ( .OUT(na425_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a425_2 ( .OUT(na425_1), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na425_1_i) ); +// C_///AND/D x141y48 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a426_4 ( .OUT(na426_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a426_5 ( .OUT(na426_2), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na426_2_i) ); +// C_///AND/D x139y54 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a427_4 ( .OUT(na427_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a427_5 ( .OUT(na427_2), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na427_2_i) ); +// C_///AND/D x136y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a428_4 ( .OUT(na428_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a428_5 ( .OUT(na428_2), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na428_2_i) ); +// C_AND/D/// x142y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a429_1 ( .OUT(na429_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a429_2 ( .OUT(na429_1), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na429_1_i) ); +// C_AND/D/// x146y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a430_1 ( .OUT(na430_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a430_2 ( .OUT(na430_1), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na430_1_i) ); +// C_AND/D/// x131y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a431_1 ( .OUT(na431_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a431_2 ( .OUT(na431_1), .CLK(na2414_1), .EN(na119_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na431_1_i) ); +// C_///AND/D x144y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a432_4 ( .OUT(na432_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a432_5 ( .OUT(na432_2), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na432_2_i) ); +// C_///AND/D x138y42 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a433_4 ( .OUT(na433_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a433_5 ( .OUT(na433_2), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na433_2_i) ); +// C_///AND/D x139y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a434_4 ( .OUT(na434_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a434_5 ( .OUT(na434_2), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na434_2_i) ); +// C_AND/D/// x124y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a435_1 ( .OUT(na435_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a435_2 ( .OUT(na435_1), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na435_1_i) ); +// C_///AND/D x146y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a436_4 ( .OUT(na436_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a436_5 ( .OUT(na436_2), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na436_2_i) ); +// C_AND/D/// x150y54 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a437_1 ( .OUT(na437_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a437_2 ( .OUT(na437_1), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na437_1_i) ); +// C_AND/D/// x140y62 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a438_1 ( .OUT(na438_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a438_2 ( .OUT(na438_1), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na438_1_i) ); +// C_AND/D/// x139y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a439_1 ( .OUT(na439_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a439_2 ( .OUT(na439_1), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na439_1_i) ); +// C_///AND/D x146y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a440_4 ( .OUT(na440_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a440_5 ( .OUT(na440_2), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na440_2_i) ); +// C_///AND/D x134y81 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a441_4 ( .OUT(na441_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a441_5 ( .OUT(na441_2), .CLK(na2414_1), .EN(na132_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na441_2_i) ); +// C_///AND/D x113y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a442_4 ( .OUT(na442_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a442_5 ( .OUT(na442_2), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na442_2_i) ); +// C_AND/D/// x106y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a443_1 ( .OUT(na443_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a443_2 ( .OUT(na443_1), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na443_1_i) ); +// C_AND/D/// x107y44 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a444_1 ( .OUT(na444_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a444_2 ( .OUT(na444_1), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na444_1_i) ); +// C_AND/D/// x105y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a445_1 ( .OUT(na445_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a445_2 ( .OUT(na445_1), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na445_1_i) ); +// C_///AND/D x112y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a446_4 ( .OUT(na446_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a446_5 ( .OUT(na446_2), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na446_2_i) ); +// C_AND/D/// x113y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a447_1 ( .OUT(na447_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a447_2 ( .OUT(na447_1), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na447_1_i) ); +// C_///AND/D x109y75 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a448_4 ( .OUT(na448_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a448_5 ( .OUT(na448_2), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na448_2_i) ); +// C_///AND/D x109y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a449_4 ( .OUT(na449_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a449_5 ( .OUT(na449_2), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na449_2_i) ); +// C_///AND/D x114y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a450_4 ( .OUT(na450_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a450_5 ( .OUT(na450_2), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na450_2_i) ); +// C_AND/D/// x119y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a451_1 ( .OUT(na451_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a451_2 ( .OUT(na451_1), .CLK(na2414_1), .EN(na113_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na451_1_i) ); +// C_AND/D/// x110y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a452_1 ( .OUT(na452_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a452_2 ( .OUT(na452_1), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na452_1_i) ); +// C_AND/D/// x110y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a453_1 ( .OUT(na453_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a453_2 ( .OUT(na453_1), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na453_1_i) ); +// C_///AND/D x108y50 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a454_4 ( .OUT(na454_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a454_5 ( .OUT(na454_2), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na454_2_i) ); +// C_///AND/D x111y55 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a455_4 ( .OUT(na455_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a455_5 ( .OUT(na455_2), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na455_2_i) ); +// C_///AND/D x112y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a456_4 ( .OUT(na456_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a456_5 ( .OUT(na456_2), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na456_2_i) ); +// C_AND/D/// x110y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a457_1 ( .OUT(na457_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a457_2 ( .OUT(na457_1), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na457_1_i) ); +// C_///AND/D x112y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a458_4 ( .OUT(na458_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a458_5 ( .OUT(na458_2), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na458_2_i) ); +// C_AND/D/// x110y78 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a459_1 ( .OUT(na459_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a459_2 ( .OUT(na459_1), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na459_1_i) ); +// C_AND/D/// x110y79 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a460_1 ( .OUT(na460_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a460_2 ( .OUT(na460_1), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na460_1_i) ); +// C_AND/D/// x120y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a461_1 ( .OUT(na461_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a461_2 ( .OUT(na461_1), .CLK(na2414_1), .EN(na99_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na461_1_i) ); +// C_///AND/D x108y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a462_4 ( .OUT(na462_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a462_5 ( .OUT(na462_2), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na462_2_i) ); +// C_///AND/D x109y38 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a463_4 ( .OUT(na463_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a463_5 ( .OUT(na463_2), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na463_2_i) ); +// C_///AND/D x107y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a464_4 ( .OUT(na464_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a464_5 ( .OUT(na464_2), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na464_2_i) ); +// C_AND/D/// x107y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a465_1 ( .OUT(na465_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a465_2 ( .OUT(na465_1), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na465_1_i) ); +// C_AND/D/// x105y54 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a466_1 ( .OUT(na466_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a466_2 ( .OUT(na466_1), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na466_1_i) ); +// C_AND/D/// x108y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a467_1 ( .OUT(na467_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a467_2 ( .OUT(na467_1), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na467_1_i) ); +// C_///AND/D x107y75 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a468_4 ( .OUT(na468_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a468_5 ( .OUT(na468_2), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na468_2_i) ); +// C_AND/D/// x105y80 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a469_1 ( .OUT(na469_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a469_2 ( .OUT(na469_1), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na469_1_i) ); +// C_///AND/D x113y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a470_4 ( .OUT(na470_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a470_5 ( .OUT(na470_2), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na470_2_i) ); +// C_///AND/D x127y84 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a471_4 ( .OUT(na471_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a471_5 ( .OUT(na471_2), .CLK(na2414_1), .EN(na127_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na471_2_i) ); +// C_///AND/D x109y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a472_4 ( .OUT(na472_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a472_5 ( .OUT(na472_2), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na472_2_i) ); +// C_AND/D/// x108y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a473_1 ( .OUT(na473_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a473_2 ( .OUT(na473_1), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na473_1_i) ); +// C_AND/D/// x106y41 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a474_1 ( .OUT(na474_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a474_2 ( .OUT(na474_1), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na474_1_i) ); +// C_AND/D/// x108y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a475_1 ( .OUT(na475_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a475_2 ( .OUT(na475_1), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na475_1_i) ); +// C_///AND/D x104y55 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a476_4 ( .OUT(na476_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a476_5 ( .OUT(na476_2), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na476_2_i) ); +// C_///AND/D x109y63 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a477_4 ( .OUT(na477_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a477_5 ( .OUT(na477_2), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na477_2_i) ); +// C_///AND/D x108y80 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a478_4 ( .OUT(na478_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a478_5 ( .OUT(na478_2), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na478_2_i) ); +// C_AND/D/// x108y79 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a479_1 ( .OUT(na479_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a479_2 ( .OUT(na479_1), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na479_1_i) ); +// C_///AND/D x116y73 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a480_4 ( .OUT(na480_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a480_5 ( .OUT(na480_2), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na480_2_i) ); +// C_AND/D/// x120y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a481_1 ( .OUT(na481_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a481_2 ( .OUT(na481_1), .CLK(na2414_1), .EN(na126_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na481_1_i) ); +// C_AND/D/// x105y31 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a482_1 ( .OUT(na482_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a482_2 ( .OUT(na482_1), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na482_1_i) ); +// C_AND/D/// x108y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a483_1 ( .OUT(na483_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a483_2 ( .OUT(na483_1), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na483_1_i) ); +// C_///AND/D x112y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a484_4 ( .OUT(na484_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a484_5 ( .OUT(na484_2), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na484_2_i) ); +// C_///AND/D x116y56 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a485_4 ( .OUT(na485_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a485_5 ( .OUT(na485_2), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na485_2_i) ); +// C_///AND/D x106y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a486_4 ( .OUT(na486_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a486_5 ( .OUT(na486_2), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na486_2_i) ); +// C_AND/D/// x107y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a487_1 ( .OUT(na487_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a487_2 ( .OUT(na487_1), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na487_1_i) ); +// C_AND/D/// x108y69 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a488_1 ( .OUT(na488_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a488_2 ( .OUT(na488_1), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na488_1_i) ); +// C_AND/D/// x108y78 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a489_1 ( .OUT(na489_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a489_2 ( .OUT(na489_1), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na489_1_i) ); +// C_///AND/D x114y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a490_4 ( .OUT(na490_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a490_5 ( .OUT(na490_2), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na490_2_i) ); +// C_AND/D/// x118y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a491_1 ( .OUT(na491_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a491_2 ( .OUT(na491_1), .CLK(na2414_1), .EN(na125_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na491_1_i) ); +// C_///AND/D x113y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a492_4 ( .OUT(na492_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a492_5 ( .OUT(na492_2), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na492_2_i) ); +// C_///AND/D x109y33 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a493_4 ( .OUT(na493_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a493_5 ( .OUT(na493_2), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na493_2_i) ); +// C_///AND/D x106y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a494_4 ( .OUT(na494_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a494_5 ( .OUT(na494_2), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na494_2_i) ); +// C_AND/D/// x108y51 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a495_1 ( .OUT(na495_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a495_2 ( .OUT(na495_1), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na495_1_i) ); +// C_AND/D/// x106y55 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a496_1 ( .OUT(na496_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a496_2 ( .OUT(na496_1), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na496_1_i) ); +// C_AND/D/// x108y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a497_1 ( .OUT(na497_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a497_2 ( .OUT(na497_1), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na497_1_i) ); +// C_///AND/D x108y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a498_4 ( .OUT(na498_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a498_5 ( .OUT(na498_2), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na498_2_i) ); +// C_///AND/D x105y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a499_4 ( .OUT(na499_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a499_5 ( .OUT(na499_2), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na499_2_i) ); +// C_///AND/D x113y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a500_4 ( .OUT(na500_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a500_5 ( .OUT(na500_2), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na500_2_i) ); +// C_AND/D/// x116y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a501_1 ( .OUT(na501_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a501_2 ( .OUT(na501_1), .CLK(na2414_1), .EN(na122_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na501_1_i) ); +// C_///AND/D x106y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a502_4 ( .OUT(na502_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a502_5 ( .OUT(na502_2), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na502_2_i) ); +// C_AND/D/// x110y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a503_1 ( .OUT(na503_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a503_2 ( .OUT(na503_1), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na503_1_i) ); +// C_AND/D/// x106y47 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a504_1 ( .OUT(na504_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a504_2 ( .OUT(na504_1), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na504_1_i) ); +// C_AND/D/// x107y54 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a505_1 ( .OUT(na505_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a505_2 ( .OUT(na505_1), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na505_1_i) ); +// C_///AND/D x114y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a506_4 ( .OUT(na506_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a506_5 ( .OUT(na506_2), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na506_2_i) ); +// C_///AND/D x110y61 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a507_4 ( .OUT(na507_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a507_5 ( .OUT(na507_2), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na507_2_i) ); +// C_///AND/D x106y75 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a508_4 ( .OUT(na508_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a508_5 ( .OUT(na508_2), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na508_2_i) ); +// C_AND/D/// x106y79 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a509_1 ( .OUT(na509_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a509_2 ( .OUT(na509_1), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na509_1_i) ); +// C_AND/D/// x112y84 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a510_1 ( .OUT(na510_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a510_2 ( .OUT(na510_1), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na510_1_i) ); +// C_AND/D/// x120y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a511_1 ( .OUT(na511_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a511_2 ( .OUT(na511_1), .CLK(na2414_1), .EN(na103_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na511_1_i) ); +// C_///AND/D x111y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a512_4 ( .OUT(na512_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a512_5 ( .OUT(na512_2), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na512_2_i) ); +// C_AND/D/// x107y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a513_1 ( .OUT(na513_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a513_2 ( .OUT(na513_1), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na513_1_i) ); +// C_///AND/D x106y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a514_4 ( .OUT(na514_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a514_5 ( .OUT(na514_2), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na514_2_i) ); +// C_///AND/D x116y54 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a515_4 ( .OUT(na515_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a515_5 ( .OUT(na515_2), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na515_2_i) ); +// C_///AND/D x108y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a516_4 ( .OUT(na516_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a516_5 ( .OUT(na516_2), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na516_2_i) ); +// C_AND/D/// x110y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a517_1 ( .OUT(na517_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a517_2 ( .OUT(na517_1), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na517_1_i) ); +// C_AND/D/// x110y68 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a518_1 ( .OUT(na518_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a518_2 ( .OUT(na518_1), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na518_1_i) ); +// C_AND/D/// x103y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a519_1 ( .OUT(na519_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a519_2 ( .OUT(na519_1), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na519_1_i) ); +// C_///AND/D x113y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a520_4 ( .OUT(na520_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a520_5 ( .OUT(na520_2), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na520_2_i) ); +// C_///AND/D x122y82 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a521_4 ( .OUT(na521_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a521_5 ( .OUT(na521_2), .CLK(na2414_1), .EN(na121_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na521_2_i) ); +// C_///AND/D x109y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a522_4 ( .OUT(na522_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a522_5 ( .OUT(na522_2), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na522_2_i) ); +// C_AND/D/// x107y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a523_1 ( .OUT(na523_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a523_2 ( .OUT(na523_1), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na523_1_i) ); +// C_///AND/D x109y50 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a524_4 ( .OUT(na524_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a524_5 ( .OUT(na524_2), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na524_2_i) ); +// C_AND/D/// x110y53 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a525_1 ( .OUT(na525_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a525_2 ( .OUT(na525_1), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na525_1_i) ); +// C_AND/D/// x107y55 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a526_1 ( .OUT(na526_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a526_2 ( .OUT(na526_1), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na526_1_i) ); +// C_AND/D/// x109y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a527_1 ( .OUT(na527_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a527_2 ( .OUT(na527_1), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na527_1_i) ); +// C_///AND/D x111y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a528_4 ( .OUT(na528_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a528_5 ( .OUT(na528_2), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na528_2_i) ); +// C_///AND/D x107y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a529_4 ( .OUT(na529_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a529_5 ( .OUT(na529_2), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na529_2_i) ); +// C_///AND/D x111y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a530_4 ( .OUT(na530_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a530_5 ( .OUT(na530_2), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na530_2_i) ); +// C_AND/D/// x117y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a531_1 ( .OUT(na531_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a531_2 ( .OUT(na531_1), .CLK(na2414_1), .EN(na105_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na531_1_i) ); +// C_AND/D/// x108y31 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a532_1 ( .OUT(na532_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a532_2 ( .OUT(na532_1), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na532_1_i) ); +// C_AND/D/// x110y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a533_1 ( .OUT(na533_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a533_2 ( .OUT(na533_1), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na533_1_i) ); +// C_///AND/D x107y52 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a534_4 ( .OUT(na534_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a534_5 ( .OUT(na534_2), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na534_2_i) ); +// C_AND/D/// x111y51 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a535_1 ( .OUT(na535_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a535_2 ( .OUT(na535_1), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na535_1_i) ); +// C_///AND/D x109y55 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a536_4 ( .OUT(na536_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a536_5 ( .OUT(na536_2), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na536_2_i) ); +// C_///AND/D x111y61 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a537_4 ( .OUT(na537_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a537_5 ( .OUT(na537_2), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na537_2_i) ); +// C_///AND/D x109y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a538_4 ( .OUT(na538_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a538_5 ( .OUT(na538_2), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na538_2_i) ); +// C_AND/D/// x106y78 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a539_1 ( .OUT(na539_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a539_2 ( .OUT(na539_1), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na539_1_i) ); +// C_AND/D/// x112y78 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a540_1 ( .OUT(na540_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a540_2 ( .OUT(na540_1), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na540_1_i) ); +// C_AND/D/// x117y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a541_1 ( .OUT(na541_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a541_2 ( .OUT(na541_1), .CLK(na2414_1), .EN(na118_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na541_1_i) ); +// C_///AND/D x111y29 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a542_4 ( .OUT(na542_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a542_5 ( .OUT(na542_2), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na542_2_i) ); +// C_///AND/D x109y37 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a543_4 ( .OUT(na543_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a543_5 ( .OUT(na543_2), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na543_2_i) ); +// C_///AND/D x109y51 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a544_4 ( .OUT(na544_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a544_5 ( .OUT(na544_2), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na544_2_i) ); +// C_AND/D/// x110y54 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a545_1 ( .OUT(na545_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a545_2 ( .OUT(na545_1), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na545_1_i) ); +// C_///AND/D x111y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a546_4 ( .OUT(na546_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a546_5 ( .OUT(na546_2), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na546_2_i) ); +// C_AND/D/// x107y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a547_1 ( .OUT(na547_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a547_2 ( .OUT(na547_1), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na547_1_i) ); +// C_AND/D/// x111y67 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a548_1 ( .OUT(na548_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a548_2 ( .OUT(na548_1), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na548_1_i) ); +// C_AND/D/// x107y79 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a549_1 ( .OUT(na549_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a549_2 ( .OUT(na549_1), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na549_1_i) ); +// C_///AND/D x111y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a550_4 ( .OUT(na550_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a550_5 ( .OUT(na550_2), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na550_2_i) ); +// C_///AND/D x119y79 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a551_4 ( .OUT(na551_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a551_5 ( .OUT(na551_2), .CLK(na2414_1), .EN(na109_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na551_2_i) ); +// C_///AND/D x112y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a552_4 ( .OUT(na552_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a552_5 ( .OUT(na552_2), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na552_2_i) ); +// C_AND/D/// x110y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a553_1 ( .OUT(na553_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a553_2 ( .OUT(na553_1), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na553_1_i) ); +// C_AND/D/// x105y43 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a554_1 ( .OUT(na554_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a554_2 ( .OUT(na554_1), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na554_1_i) ); +// C_AND/D/// x109y52 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a555_1 ( .OUT(na555_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a555_2 ( .OUT(na555_1), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na555_1_i) ); +// C_///AND/D x107y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a556_4 ( .OUT(na556_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a556_5 ( .OUT(na556_2), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na556_2_i) ); +// C_AND/D/// x109y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a557_1 ( .OUT(na557_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a557_2 ( .OUT(na557_1), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na557_1_i) ); +// C_///AND/D x109y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a558_4 ( .OUT(na558_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a558_5 ( .OUT(na558_2), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na558_2_i) ); +// C_///AND/D x104y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a559_4 ( .OUT(na559_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a559_5 ( .OUT(na559_2), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na559_2_i) ); +// C_///AND/D x114y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a560_4 ( .OUT(na560_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a560_5 ( .OUT(na560_2), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na560_2_i) ); +// C_AND/D/// x117y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a561_1 ( .OUT(na561_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a561_2 ( .OUT(na561_1), .CLK(na2414_1), .EN(na117_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na561_1_i) ); +// C_AND/D/// x114y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a562_1 ( .OUT(na562_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a562_2 ( .OUT(na562_1), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na562_1_i) ); +// C_AND/D/// x107y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a563_1 ( .OUT(na563_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a563_2 ( .OUT(na563_1), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na563_1_i) ); +// C_///AND/D x112y50 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a564_4 ( .OUT(na564_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a564_5 ( .OUT(na564_2), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na564_2_i) ); +// C_///AND/D x106y52 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a565_4 ( .OUT(na565_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a565_5 ( .OUT(na565_2), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na565_2_i) ); +// C_///AND/D x113y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a566_4 ( .OUT(na566_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a566_5 ( .OUT(na566_2), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na566_2_i) ); +// C_AND/D/// x114y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a567_1 ( .OUT(na567_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a567_2 ( .OUT(na567_1), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na567_1_i) ); +// C_///AND/D x108y77 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a568_4 ( .OUT(na568_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a568_5 ( .OUT(na568_2), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na568_2_i) ); +// C_AND/D/// x106y81 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a569_1 ( .OUT(na569_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a569_2 ( .OUT(na569_1), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na569_1_i) ); +// C_AND/D/// x113y79 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a570_1 ( .OUT(na570_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a570_2 ( .OUT(na570_1), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na570_1_i) ); +// C_AND/D/// x120y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a571_1 ( .OUT(na571_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a571_2 ( .OUT(na571_1), .CLK(na2414_1), .EN(na111_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na571_1_i) ); +// C_///AND/D x113y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a572_4 ( .OUT(na572_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a572_5 ( .OUT(na572_2), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na572_2_i) ); +// C_///AND/D x106y36 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a573_4 ( .OUT(na573_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a573_5 ( .OUT(na573_2), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na573_2_i) ); +// C_///AND/D x113y53 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a574_4 ( .OUT(na574_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a574_5 ( .OUT(na574_2), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na574_2_i) ); +// C_AND/D/// x105y51 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a575_1 ( .OUT(na575_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a575_2 ( .OUT(na575_1), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na575_1_i) ); +// C_AND/D/// x110y55 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a576_1 ( .OUT(na576_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a576_2 ( .OUT(na576_1), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na576_1_i) ); +// C_AND/D/// x115y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a577_1 ( .OUT(na577_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a577_2 ( .OUT(na577_1), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na577_1_i) ); +// C_///AND/D x107y78 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a578_4 ( .OUT(na578_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a578_5 ( .OUT(na578_2), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na578_2_i) ); +// C_AND/D/// x107y82 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a579_1 ( .OUT(na579_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a579_2 ( .OUT(na579_1), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na579_1_i) ); +// C_///AND/D x116y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a580_4 ( .OUT(na580_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a580_5 ( .OUT(na580_2), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na580_2_i) ); +// C_///AND/D x123y77 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a581_4 ( .OUT(na581_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a581_5 ( .OUT(na581_2), .CLK(na2414_1), .EN(na114_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na581_2_i) ); +// C_///AND/D x114y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a582_4 ( .OUT(na582_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a582_5 ( .OUT(na582_2), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na582_2_i) ); +// C_AND/D/// x105y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a583_1 ( .OUT(na583_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a583_2 ( .OUT(na583_1), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na583_1_i) ); +// C_AND/D/// x110y45 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a584_1 ( .OUT(na584_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a584_2 ( .OUT(na584_1), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na584_1_i) ); +// C_AND/D/// x110y51 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a585_1 ( .OUT(na585_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a585_2 ( .OUT(na585_1), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na585_1_i) ); +// C_///AND/D x117y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a586_4 ( .OUT(na586_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a586_5 ( .OUT(na586_2), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na586_2_i) ); +// C_///AND/D x114y63 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a587_4 ( .OUT(na587_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a587_5 ( .OUT(na587_2), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na587_2_i) ); +// C_///AND/D x106y80 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a588_4 ( .OUT(na588_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a588_5 ( .OUT(na588_2), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na588_2_i) ); +// C_AND/D/// x110y82 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a589_1 ( .OUT(na589_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a589_2 ( .OUT(na589_1), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na589_1_i) ); +// C_///AND/D x117y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a590_4 ( .OUT(na590_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a590_5 ( .OUT(na590_2), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na590_2_i) ); +// C_AND/D/// x120y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a591_1 ( .OUT(na591_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a591_2 ( .OUT(na591_1), .CLK(na2414_1), .EN(na112_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na591_1_i) ); +// C_AND/D/// x150y38 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a592_1 ( .OUT(na592_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a592_2 ( .OUT(na592_1), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na592_1_i) ); +// C_AND/D/// x139y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a593_1 ( .OUT(na593_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a593_2 ( .OUT(na593_1), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na593_1_i) ); +// C_///AND/D x135y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a594_4 ( .OUT(na594_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a594_5 ( .OUT(na594_2), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na594_2_i) ); +// C_///AND/D x126y48 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a595_4 ( .OUT(na595_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a595_5 ( .OUT(na595_2), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na595_2_i) ); +// C_///AND/D x147y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a596_4 ( .OUT(na596_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a596_5 ( .OUT(na596_2), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na596_2_i) ); +// C_AND/D/// x146y50 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a597_1 ( .OUT(na597_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a597_2 ( .OUT(na597_1), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na597_1_i) ); +// C_AND/D/// x144y64 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a598_1 ( .OUT(na598_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a598_2 ( .OUT(na598_1), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na598_1_i) ); +// C_AND/D/// x140y66 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a599_1 ( .OUT(na599_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a599_2 ( .OUT(na599_1), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na599_1_i) ); +// C_///AND/D x139y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a600_4 ( .OUT(na600_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a600_5 ( .OUT(na600_2), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na600_2_i) ); +// C_AND/D/// x125y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a601_1 ( .OUT(na601_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a601_2 ( .OUT(na601_1), .CLK(na2414_1), .EN(na81_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na601_1_i) ); +// C_///AND/D x146y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a602_4 ( .OUT(na602_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a602_5 ( .OUT(na602_2), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na602_2_i) ); +// C_///AND/D x147y35 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a603_4 ( .OUT(na603_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a603_5 ( .OUT(na603_2), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na603_2_i) ); +// C_///AND/D x141y58 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a604_4 ( .OUT(na604_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a604_5 ( .OUT(na604_2), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na604_2_i) ); +// C_AND/D/// x132y54 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a605_1 ( .OUT(na605_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a605_2 ( .OUT(na605_1), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na605_1_i) ); +// C_AND/D/// x154y41 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a606_1 ( .OUT(na606_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a606_2 ( .OUT(na606_1), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na606_1_i) ); +// C_AND/D/// x150y53 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a607_1 ( .OUT(na607_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a607_2 ( .OUT(na607_1), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na607_1_i) ); +// C_///AND/D x144y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a608_4 ( .OUT(na608_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a608_5 ( .OUT(na608_2), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na608_2_i) ); +// C_///AND/D x140y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a609_4 ( .OUT(na609_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a609_5 ( .OUT(na609_2), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na609_2_i) ); +// C_///AND/D x150y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a610_4 ( .OUT(na610_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a610_5 ( .OUT(na610_2), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na610_2_i) ); +// C_AND/D/// x136y84 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a611_1 ( .OUT(na611_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a611_2 ( .OUT(na611_1), .CLK(na2414_1), .EN(na150_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na611_1_i) ); +// C_///AND/D x143y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a612_4 ( .OUT(na612_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a612_5 ( .OUT(na612_2), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na612_2_i) ); +// C_AND/D/// x146y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a613_1 ( .OUT(na613_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a613_2 ( .OUT(na613_1), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na613_1_i) ); +// C_AND/D/// x145y42 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a614_1 ( .OUT(na614_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a614_2 ( .OUT(na614_1), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na614_1_i) ); +// C_AND/D/// x129y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a615_1 ( .OUT(na615_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a615_2 ( .OUT(na615_1), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na615_1_i) ); +// C_///AND/D x151y47 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a616_4 ( .OUT(na616_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a616_5 ( .OUT(na616_2), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na616_2_i) ); +// C_///AND/D x147y62 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a617_4 ( .OUT(na617_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a617_5 ( .OUT(na617_2), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na617_2_i) ); +// C_///AND/D x135y62 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a618_4 ( .OUT(na618_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a618_5 ( .OUT(na618_2), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na618_2_i) ); +// C_AND/D/// x145y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a619_1 ( .OUT(na619_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a619_2 ( .OUT(na619_1), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na619_1_i) ); +// C_AND/D/// x150y78 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a620_1 ( .OUT(na620_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a620_2 ( .OUT(na620_1), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na620_1_i) ); +// C_AND/D/// x135y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a621_1 ( .OUT(na621_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a621_2 ( .OUT(na621_1), .CLK(na2414_1), .EN(na136_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na621_1_i) ); +// C_///AND/D x144y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a622_4 ( .OUT(na622_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a622_5 ( .OUT(na622_2), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na622_2_i) ); +// C_AND/D/// x143y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a623_1 ( .OUT(na623_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a623_2 ( .OUT(na623_1), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na623_1_i) ); +// C_///AND/D x144y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a624_4 ( .OUT(na624_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a624_5 ( .OUT(na624_2), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na624_2_i) ); +// C_///AND/D x134y45 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a625_4 ( .OUT(na625_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a625_5 ( .OUT(na625_2), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na625_2_i) ); +// C_///AND/D x156y46 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a626_4 ( .OUT(na626_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a626_5 ( .OUT(na626_2), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na626_2_i) ); +// C_AND/D/// x150y49 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a627_1 ( .OUT(na627_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a627_2 ( .OUT(na627_1), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na627_1_i) ); +// C_AND/D/// x146y63 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a628_1 ( .OUT(na628_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a628_2 ( .OUT(na628_1), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na628_1_i) ); +// C_AND/D/// x150y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a629_1 ( .OUT(na629_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a629_2 ( .OUT(na629_1), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na629_1_i) ); +// C_///AND/D x149y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a630_4 ( .OUT(na630_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a630_5 ( .OUT(na630_2), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na630_2_i) ); +// C_///AND/D x138y84 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a631_4 ( .OUT(na631_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a631_5 ( .OUT(na631_2), .CLK(na2414_1), .EN(na137_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na631_2_i) ); +// C_///AND/D x144y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a632_4 ( .OUT(na632_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a632_5 ( .OUT(na632_2), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na632_2_i) ); +// C_AND/D/// x145y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a633_1 ( .OUT(na633_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a633_2 ( .OUT(na633_1), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na633_1_i) ); +// C_///AND/D x142y52 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a634_4 ( .OUT(na634_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a634_5 ( .OUT(na634_2), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na634_2_i) ); +// C_AND/D/// x128y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a635_1 ( .OUT(na635_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a635_2 ( .OUT(na635_1), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na635_1_i) ); +// C_AND/D/// x154y39 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a636_1 ( .OUT(na636_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a636_2 ( .OUT(na636_1), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na636_1_i) ); +// C_AND/D/// x152y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a637_1 ( .OUT(na637_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a637_2 ( .OUT(na637_1), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na637_1_i) ); +// C_///AND/D x136y64 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a638_4 ( .OUT(na638_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a638_5 ( .OUT(na638_2), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na638_2_i) ); +// C_///AND/D x144y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a639_4 ( .OUT(na639_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a639_5 ( .OUT(na639_2), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na639_2_i) ); +// C_///AND/D x151y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a640_4 ( .OUT(na640_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a640_5 ( .OUT(na640_2), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na640_2_i) ); +// C_AND/D/// x136y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a641_1 ( .OUT(na641_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a641_2 ( .OUT(na641_1), .CLK(na2414_1), .EN(na138_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na641_1_i) ); +// C_AND/D/// x145y35 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a642_1 ( .OUT(na642_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a642_2 ( .OUT(na642_1), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na642_1_i) ); +// C_AND/D/// x148y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a643_1 ( .OUT(na643_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a643_2 ( .OUT(na643_1), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na643_1_i) ); +// C_///AND/D x144y50 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a644_4 ( .OUT(na644_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a644_5 ( .OUT(na644_2), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na644_2_i) ); +// C_AND/D/// x129y52 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a645_1 ( .OUT(na645_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a645_2 ( .OUT(na645_1), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na645_1_i) ); +// C_///AND/D x153y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a646_4 ( .OUT(na646_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a646_5 ( .OUT(na646_2), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na646_2_i) ); +// C_///AND/D x145y57 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a647_4 ( .OUT(na647_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a647_5 ( .OUT(na647_2), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na647_2_i) ); +// C_///AND/D x141y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a648_4 ( .OUT(na648_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a648_5 ( .OUT(na648_2), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na648_2_i) ); +// C_AND/D/// x148y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a649_1 ( .OUT(na649_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a649_2 ( .OUT(na649_1), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na649_1_i) ); +// C_AND/D/// x152y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a650_1 ( .OUT(na650_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a650_2 ( .OUT(na650_1), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na650_1_i) ); +// C_AND/D/// x131y83 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a651_1 ( .OUT(na651_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a651_2 ( .OUT(na651_1), .CLK(na2414_1), .EN(na139_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na651_1_i) ); +// C_///AND/D x145y36 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a652_4 ( .OUT(na652_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a652_5 ( .OUT(na652_2), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na652_2_i) ); +// C_///AND/D x148y34 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a653_4 ( .OUT(na653_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a653_5 ( .OUT(na653_2), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na653_2_i) ); +// C_///AND/D x148y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a654_4 ( .OUT(na654_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a654_5 ( .OUT(na654_2), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na654_2_i) ); +// C_AND/D/// x127y51 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a655_1 ( .OUT(na655_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a655_2 ( .OUT(na655_1), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na655_1_i) ); +// C_///AND/D x153y49 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a656_4 ( .OUT(na656_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a656_5 ( .OUT(na656_2), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na656_2_i) ); +// C_AND/D/// x145y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a657_1 ( .OUT(na657_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a657_2 ( .OUT(na657_1), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na657_1_i) ); +// C_AND/D/// x143y61 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a658_1 ( .OUT(na658_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a658_2 ( .OUT(na658_1), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na658_1_i) ); +// C_AND/D/// x146y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a659_1 ( .OUT(na659_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a659_2 ( .OUT(na659_1), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na659_1_i) ); +// C_///AND/D x152y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a660_4 ( .OUT(na660_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a660_5 ( .OUT(na660_2), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na660_2_i) ); +// C_///AND/D x137y84 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a661_4 ( .OUT(na661_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a661_5 ( .OUT(na661_2), .CLK(na2414_1), .EN(na140_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na661_2_i) ); +// C_///AND/D x144y37 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a662_4 ( .OUT(na662_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a662_5 ( .OUT(na662_2), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na662_2_i) ); +// C_AND/D/// x149y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a663_1 ( .OUT(na663_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a663_2 ( .OUT(na663_1), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na663_1_i) ); +// C_AND/D/// x149y42 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a664_1 ( .OUT(na664_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a664_2 ( .OUT(na664_1), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na664_1_i) ); +// C_AND/D/// x130y52 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a665_1 ( .OUT(na665_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a665_2 ( .OUT(na665_1), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na665_1_i) ); +// C_///AND/D x156y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a666_4 ( .OUT(na666_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a666_5 ( .OUT(na666_2), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na666_2_i) ); +// C_AND/D/// x150y51 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a667_1 ( .OUT(na667_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a667_2 ( .OUT(na667_1), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na667_1_i) ); +// C_///AND/D x142y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a668_4 ( .OUT(na668_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a668_5 ( .OUT(na668_2), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na668_2_i) ); +// C_///AND/D x143y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a669_4 ( .OUT(na669_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a669_5 ( .OUT(na669_2), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na669_2_i) ); +// C_///AND/D x147y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a670_4 ( .OUT(na670_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a670_5 ( .OUT(na670_2), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na670_2_i) ); +// C_AND/D/// x132y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a671_1 ( .OUT(na671_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a671_2 ( .OUT(na671_1), .CLK(na2414_1), .EN(na141_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na671_1_i) ); +// C_AND/D/// x150y34 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a672_1 ( .OUT(na672_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a672_2 ( .OUT(na672_1), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na672_1_i) ); +// C_AND/D/// x149y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a673_1 ( .OUT(na673_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a673_2 ( .OUT(na673_1), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na673_1_i) ); +// C_///AND/D x147y51 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a674_4 ( .OUT(na674_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a674_5 ( .OUT(na674_2), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na674_2_i) ); +// C_///AND/D x126y49 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a675_4 ( .OUT(na675_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a675_5 ( .OUT(na675_2), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na675_2_i) ); +// C_///AND/D x156y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a676_4 ( .OUT(na676_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a676_5 ( .OUT(na676_2), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na676_2_i) ); +// C_AND/D/// x148y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a677_1 ( .OUT(na677_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a677_2 ( .OUT(na677_1), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na677_1_i) ); +// C_///AND/D x142y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a678_4 ( .OUT(na678_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a678_5 ( .OUT(na678_2), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na678_2_i) ); +// C_AND/D/// x147y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a679_1 ( .OUT(na679_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a679_2 ( .OUT(na679_1), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na679_1_i) ); +// C_AND/D/// x151y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a680_1 ( .OUT(na680_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a680_2 ( .OUT(na680_1), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na680_1_i) ); +// C_AND/D/// x134y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a681_1 ( .OUT(na681_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a681_2 ( .OUT(na681_1), .CLK(na2414_1), .EN(na142_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na681_1_i) ); +// C_///AND/D x143y37 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a682_4 ( .OUT(na682_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a682_5 ( .OUT(na682_2), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na682_2_i) ); +// C_///AND/D x147y33 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a683_4 ( .OUT(na683_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a683_5 ( .OUT(na683_2), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na683_2_i) ); +// C_///AND/D x142y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a684_4 ( .OUT(na684_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a684_5 ( .OUT(na684_2), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na684_2_i) ); +// C_AND/D/// x131y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a685_1 ( .OUT(na685_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a685_2 ( .OUT(na685_1), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na685_1_i) ); +// C_AND/D/// x154y43 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a686_1 ( .OUT(na686_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a686_2 ( .OUT(na686_1), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na686_1_i) ); +// C_AND/D/// x155y49 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a687_1 ( .OUT(na687_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a687_2 ( .OUT(na687_1), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na687_1_i) ); +// C_///AND/D x141y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a688_4 ( .OUT(na688_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a688_5 ( .OUT(na688_2), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na688_2_i) ); +// C_AND/D/// x143y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a689_1 ( .OUT(na689_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a689_2 ( .OUT(na689_1), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na689_1_i) ); +// C_///AND/D x148y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a690_4 ( .OUT(na690_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a690_5 ( .OUT(na690_2), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na690_2_i) ); +// C_///AND/D x139y81 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a691_4 ( .OUT(na691_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a691_5 ( .OUT(na691_2), .CLK(na2414_1), .EN(na143_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na691_2_i) ); +// C_///AND/D x143y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a692_4 ( .OUT(na692_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a692_5 ( .OUT(na692_2), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na692_2_i) ); +// C_AND/D/// x146y29 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a693_1 ( .OUT(na693_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a693_2 ( .OUT(na693_1), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na693_1_i) ); +// C_AND/D/// x147y41 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a694_1 ( .OUT(na694_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a694_2 ( .OUT(na694_1), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na694_1_i) ); +// C_AND/D/// x129y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a695_1 ( .OUT(na695_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a695_2 ( .OUT(na695_1), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na695_1_i) ); +// C_///AND/D x155y48 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a696_4 ( .OUT(na696_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a696_5 ( .OUT(na696_2), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na696_2_i) ); +// C_///AND/D x147y63 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a697_4 ( .OUT(na697_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a697_5 ( .OUT(na697_2), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na697_2_i) ); +// C_///AND/D x139y63 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a698_4 ( .OUT(na698_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a698_5 ( .OUT(na698_2), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na698_2_i) ); +// C_AND/D/// x147y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a699_1 ( .OUT(na699_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a699_2 ( .OUT(na699_1), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na699_1_i) ); +// C_///AND/D x156y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a700_4 ( .OUT(na700_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a700_5 ( .OUT(na700_2), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na700_2_i) ); +// C_AND/D/// x135y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a701_1 ( .OUT(na701_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a701_2 ( .OUT(na701_1), .CLK(na2414_1), .EN(na133_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na701_1_i) ); +// C_AND/D/// x150y35 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a702_1 ( .OUT(na702_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a702_2 ( .OUT(na702_1), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na702_1_i) ); +// C_AND/D/// x154y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a703_1 ( .OUT(na703_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a703_2 ( .OUT(na703_1), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na703_1_i) ); +// C_///AND/D x137y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a704_4 ( .OUT(na704_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a704_5 ( .OUT(na704_2), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na704_2_i) ); +// C_///AND/D x136y46 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a705_4 ( .OUT(na705_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a705_5 ( .OUT(na705_2), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na705_2_i) ); +// C_///AND/D x149y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a706_4 ( .OUT(na706_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a706_5 ( .OUT(na706_2), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na706_2_i) ); +// C_AND/D/// x154y51 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a707_1 ( .OUT(na707_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a707_2 ( .OUT(na707_1), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na707_1_i) ); +// C_AND/D/// x148y63 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a708_1 ( .OUT(na708_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a708_2 ( .OUT(na708_1), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na708_1_i) ); +// C_AND/D/// x144y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a709_1 ( .OUT(na709_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a709_2 ( .OUT(na709_1), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na709_1_i) ); +// C_///AND/D x149y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a710_4 ( .OUT(na710_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a710_5 ( .OUT(na710_2), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na710_2_i) ); +// C_AND/D/// x138y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a711_1 ( .OUT(na711_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a711_2 ( .OUT(na711_1), .CLK(na2414_1), .EN(na145_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na711_1_i) ); +// C_///AND/D x142y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a712_4 ( .OUT(na712_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a712_5 ( .OUT(na712_2), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na712_2_i) ); +// C_///AND/D x154y34 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a713_4 ( .OUT(na713_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a713_5 ( .OUT(na713_2), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na713_2_i) ); +// C_///AND/D x141y47 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a714_4 ( .OUT(na714_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a714_5 ( .OUT(na714_2), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na714_2_i) ); +// C_AND/D/// x134y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a715_1 ( .OUT(na715_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a715_2 ( .OUT(na715_1), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na715_1_i) ); +// C_AND/D/// x153y44 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a716_1 ( .OUT(na716_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a716_2 ( .OUT(na716_1), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na716_1_i) ); +// C_AND/D/// x154y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a717_1 ( .OUT(na717_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a717_2 ( .OUT(na717_1), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na717_1_i) ); +// C_///AND/D x142y64 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a718_4 ( .OUT(na718_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a718_5 ( .OUT(na718_2), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na718_2_i) ); +// C_///AND/D x142y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a719_4 ( .OUT(na719_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a719_5 ( .OUT(na719_2), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na719_2_i) ); +// C_///AND/D x143y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a720_4 ( .OUT(na720_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a720_5 ( .OUT(na720_2), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na720_2_i) ); +// C_AND/D/// x134y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a721_1 ( .OUT(na721_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a721_2 ( .OUT(na721_1), .CLK(na2414_1), .EN(na146_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na721_1_i) ); +// C_///AND/D x141y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a722_4 ( .OUT(na722_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a722_5 ( .OUT(na722_2), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na722_2_i) ); +// C_AND/D/// x150y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a723_1 ( .OUT(na723_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a723_2 ( .OUT(na723_1), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na723_1_i) ); +// C_AND/D/// x148y43 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a724_1 ( .OUT(na724_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a724_2 ( .OUT(na724_1), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na724_1_i) ); +// C_AND/D/// x131y55 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a725_1 ( .OUT(na725_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a725_2 ( .OUT(na725_1), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na725_1_i) ); +// C_///AND/D x145y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a726_4 ( .OUT(na726_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a726_5 ( .OUT(na726_2), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na726_2_i) ); +// C_///AND/D x145y62 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a727_4 ( .OUT(na727_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a727_5 ( .OUT(na727_2), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na727_2_i) ); +// C_///AND/D x141y63 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a728_4 ( .OUT(na728_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a728_5 ( .OUT(na728_2), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na728_2_i) ); +// C_AND/D/// x145y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a729_1 ( .OUT(na729_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a729_2 ( .OUT(na729_1), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na729_1_i) ); +// C_AND/D/// x151y80 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a730_1 ( .OUT(na730_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a730_2 ( .OUT(na730_1), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na730_1_i) ); +// C_AND/D/// x137y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a731_1 ( .OUT(na731_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a731_2 ( .OUT(na731_1), .CLK(na2414_1), .EN(na147_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na731_1_i) ); +// C_///AND/D x143y40 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a732_4 ( .OUT(na732_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a732_5 ( .OUT(na732_2), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na732_2_i) ); +// C_AND/D/// x152y31 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a733_1 ( .OUT(na733_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a733_2 ( .OUT(na733_1), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na733_1_i) ); +// C_///AND/D x146y54 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a734_4 ( .OUT(na734_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a734_5 ( .OUT(na734_2), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na734_2_i) ); +// C_///AND/D x127y50 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a735_4 ( .OUT(na735_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a735_5 ( .OUT(na735_2), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na735_2_i) ); +// C_///AND/D x149y53 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a736_4 ( .OUT(na736_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a736_5 ( .OUT(na736_2), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na736_2_i) ); +// C_AND/D/// x149y53 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a737_1 ( .OUT(na737_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a737_2 ( .OUT(na737_1), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na737_1_i) ); +// C_AND/D/// x149y62 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a738_1 ( .OUT(na738_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a738_2 ( .OUT(na738_1), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na738_1_i) ); +// C_AND/D/// x145y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a739_1 ( .OUT(na739_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a739_2 ( .OUT(na739_1), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na739_1_i) ); +// C_///AND/D x149y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a740_4 ( .OUT(na740_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a740_5 ( .OUT(na740_2), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na740_2_i) ); +// C_///AND/D x139y84 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a741_4 ( .OUT(na741_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a741_5 ( .OUT(na741_2), .CLK(na2414_1), .EN(na148_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na741_2_i) ); +// C_///AND/D x146y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a742_4 ( .OUT(na742_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a742_5 ( .OUT(na742_2), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na742_2_i) ); +// C_AND/D/// x151y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a743_1 ( .OUT(na743_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a743_2 ( .OUT(na743_1), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na743_1_i) ); +// C_///AND/D x143y55 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a744_4 ( .OUT(na744_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a744_5 ( .OUT(na744_2), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na744_2_i) ); +// C_AND/D/// x132y55 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a745_1 ( .OUT(na745_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a745_2 ( .OUT(na745_1), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na745_1_i) ); +// C_AND/D/// x152y42 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a746_1 ( .OUT(na746_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a746_2 ( .OUT(na746_1), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na746_1_i) ); +// C_AND/D/// x152y54 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a747_1 ( .OUT(na747_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a747_2 ( .OUT(na747_1), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na747_1_i) ); +// C_///AND/D x142y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a748_4 ( .OUT(na748_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a748_5 ( .OUT(na748_2), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na748_2_i) ); +// C_///AND/D x146y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a749_4 ( .OUT(na749_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a749_5 ( .OUT(na749_2), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na749_2_i) ); +// C_///AND/D x152y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a750_4 ( .OUT(na750_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a750_5 ( .OUT(na750_2), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na750_2_i) ); +// C_AND/D/// x138y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a751_1 ( .OUT(na751_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a751_2 ( .OUT(na751_1), .CLK(na2414_1), .EN(na149_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na751_1_i) ); +// C_AND/D/// x149y36 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a752_1 ( .OUT(na752_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a752_2 ( .OUT(na752_1), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na752_1_i) ); +// C_AND/D/// x153y32 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a753_1 ( .OUT(na753_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a753_2 ( .OUT(na753_1), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na753_1_i) ); +// C_///AND/D x134y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a754_4 ( .OUT(na754_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a754_5 ( .OUT(na754_2), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na754_2_i) ); +// C_AND/D/// x133y51 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a755_1 ( .OUT(na755_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a755_2 ( .OUT(na755_1), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na755_1_i) ); +// C_///AND/D x156y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a756_4 ( .OUT(na756_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a756_5 ( .OUT(na756_2), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na756_2_i) ); +// C_///AND/D x153y64 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a757_4 ( .OUT(na757_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a757_5 ( .OUT(na757_2), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na757_2_i) ); +// C_///AND/D x143y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a758_4 ( .OUT(na758_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a758_5 ( .OUT(na758_2), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na758_2_i) ); +// C_AND/D/// x143y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a759_1 ( .OUT(na759_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a759_2 ( .OUT(na759_1), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na759_1_i) ); +// C_AND/D/// x150y80 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a760_1 ( .OUT(na760_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a760_2 ( .OUT(na760_1), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na760_1_i) ); +// C_AND/D/// x137y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a761_1 ( .OUT(na761_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a761_2 ( .OUT(na761_1), .CLK(na2414_1), .EN(na144_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na761_1_i) ); +// C_///AND/D x121y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a762_4 ( .OUT(na762_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a762_5 ( .OUT(na762_2), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na762_2_i) ); +// C_///AND/D x124y42 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a763_4 ( .OUT(na763_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a763_5 ( .OUT(na763_2), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na763_2_i) ); +// C_///AND/D x116y41 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a764_4 ( .OUT(na764_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a764_5 ( .OUT(na764_2), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na764_2_i) ); +// C_AND/D/// x120y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a765_1 ( .OUT(na765_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a765_2 ( .OUT(na765_1), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na765_1_i) ); +// C_///AND/D x118y53 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a766_4 ( .OUT(na766_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a766_5 ( .OUT(na766_2), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na766_2_i) ); +// C_AND/D/// x128y53 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a767_1 ( .OUT(na767_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a767_2 ( .OUT(na767_1), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na767_1_i) ); +// C_AND/D/// x129y66 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a768_1 ( .OUT(na768_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a768_2 ( .OUT(na768_1), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na768_1_i) ); +// C_AND/D/// x122y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a769_1 ( .OUT(na769_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a769_2 ( .OUT(na769_1), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na769_1_i) ); +// C_///AND/D x118y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a770_4 ( .OUT(na770_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a770_5 ( .OUT(na770_2), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na770_2_i) ); +// C_///AND/D x129y79 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a771_4 ( .OUT(na771_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a771_5 ( .OUT(na771_2), .CLK(na2414_1), .EN(na168_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na771_2_i) ); +// C_///AND/D x115y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a772_4 ( .OUT(na772_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a772_5 ( .OUT(na772_2), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na772_2_i) ); +// C_AND/D/// x117y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a773_1 ( .OUT(na773_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a773_2 ( .OUT(na773_1), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na773_1_i) ); +// C_AND/D/// x116y38 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a774_1 ( .OUT(na774_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a774_2 ( .OUT(na774_1), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na774_1_i) ); +// C_AND/D/// x116y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a775_1 ( .OUT(na775_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a775_2 ( .OUT(na775_1), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na775_1_i) ); +// C_///AND/D x119y50 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a776_4 ( .OUT(na776_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a776_5 ( .OUT(na776_2), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na776_2_i) ); +// C_AND/D/// x122y50 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a777_1 ( .OUT(na777_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a777_2 ( .OUT(na777_1), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na777_1_i) ); +// C_///AND/D x133y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a778_4 ( .OUT(na778_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a778_5 ( .OUT(na778_2), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na778_2_i) ); +// C_///AND/D x126y68 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a779_4 ( .OUT(na779_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a779_5 ( .OUT(na779_2), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na779_2_i) ); +// C_///AND/D x111y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a780_4 ( .OUT(na780_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a780_5 ( .OUT(na780_2), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na780_2_i) ); +// C_AND/D/// x123y73 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a781_1 ( .OUT(na781_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a781_2 ( .OUT(na781_1), .CLK(na2414_1), .EN(na154_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na781_1_i) ); +// C_AND/D/// x116y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a782_1 ( .OUT(na782_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a782_2 ( .OUT(na782_1), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na782_1_i) ); +// C_AND/D/// x120y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a783_1 ( .OUT(na783_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a783_2 ( .OUT(na783_1), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na783_1_i) ); +// C_///AND/D x119y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a784_4 ( .OUT(na784_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a784_5 ( .OUT(na784_2), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na784_2_i) ); +// C_///AND/D x119y43 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a785_4 ( .OUT(na785_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a785_5 ( .OUT(na785_2), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na785_2_i) ); +// C_///AND/D x120y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a786_4 ( .OUT(na786_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a786_5 ( .OUT(na786_2), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na786_2_i) ); +// C_AND/D/// x125y49 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a787_1 ( .OUT(na787_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a787_2 ( .OUT(na787_1), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na787_1_i) ); +// C_///AND/D x134y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a788_4 ( .OUT(na788_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a788_5 ( .OUT(na788_2), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na788_2_i) ); +// C_AND/D/// x121y65 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a789_1 ( .OUT(na789_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a789_2 ( .OUT(na789_1), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na789_1_i) ); +// C_AND/D/// x114y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a790_1 ( .OUT(na790_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a790_2 ( .OUT(na790_1), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na790_1_i) ); +// C_AND/D/// x128y76 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a791_1 ( .OUT(na791_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a791_2 ( .OUT(na791_1), .CLK(na2414_1), .EN(na155_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na791_1_i) ); +// C_///AND/D x116y29 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a792_4 ( .OUT(na792_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a792_5 ( .OUT(na792_2), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na792_2_i) ); +// C_///AND/D x122y38 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a793_4 ( .OUT(na793_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a793_5 ( .OUT(na793_2), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na793_2_i) ); +// C_///AND/D x117y50 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a794_4 ( .OUT(na794_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a794_5 ( .OUT(na794_2), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na794_2_i) ); +// C_AND/D/// x117y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a795_1 ( .OUT(na795_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a795_2 ( .OUT(na795_1), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na795_1_i) ); +// C_AND/D/// x114y50 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a796_1 ( .OUT(na796_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a796_2 ( .OUT(na796_1), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na796_1_i) ); +// C_AND/D/// x125y50 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a797_1 ( .OUT(na797_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a797_2 ( .OUT(na797_1), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na797_1_i) ); +// C_///AND/D x134y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a798_4 ( .OUT(na798_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a798_5 ( .OUT(na798_2), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na798_2_i) ); +// C_AND/D/// x121y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a799_1 ( .OUT(na799_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a799_2 ( .OUT(na799_1), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na799_1_i) ); +// C_///AND/D x114y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a800_4 ( .OUT(na800_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a800_5 ( .OUT(na800_2), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na800_2_i) ); +// C_///AND/D x124y77 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a801_4 ( .OUT(na801_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a801_5 ( .OUT(na801_2), .CLK(na2414_1), .EN(na156_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na801_2_i) ); +// C_///AND/D x114y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a802_4 ( .OUT(na802_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a802_5 ( .OUT(na802_2), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na802_2_i) ); +// C_AND/D/// x120y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a803_1 ( .OUT(na803_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a803_2 ( .OUT(na803_1), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na803_1_i) ); +// C_AND/D/// x118y35 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a804_1 ( .OUT(na804_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a804_2 ( .OUT(na804_1), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na804_1_i) ); +// C_AND/D/// x115y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a805_1 ( .OUT(na805_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a805_2 ( .OUT(na805_1), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na805_1_i) ); +// C_///AND/D x116y49 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a806_4 ( .OUT(na806_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a806_5 ( .OUT(na806_2), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na806_2_i) ); +// C_///AND/D x124y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a807_4 ( .OUT(na807_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a807_5 ( .OUT(na807_2), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na807_2_i) ); +// C_///AND/D x126y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a808_4 ( .OUT(na808_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a808_5 ( .OUT(na808_2), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na808_2_i) ); +// C_AND/D/// x123y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a809_1 ( .OUT(na809_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a809_2 ( .OUT(na809_1), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na809_1_i) ); +// C_///AND/D x114y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a810_4 ( .OUT(na810_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a810_5 ( .OUT(na810_2), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na810_2_i) ); +// C_AND/D/// x125y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a811_1 ( .OUT(na811_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a811_2 ( .OUT(na811_1), .CLK(na2414_1), .EN(na157_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na811_1_i) ); +// C_AND/D/// x116y31 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a812_1 ( .OUT(na812_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a812_2 ( .OUT(na812_1), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na812_1_i) ); +// C_AND/D/// x120y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a813_1 ( .OUT(na813_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a813_2 ( .OUT(na813_1), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na813_1_i) ); +// C_///AND/D x118y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a814_4 ( .OUT(na814_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a814_5 ( .OUT(na814_2), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na814_2_i) ); +// C_///AND/D x117y46 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a815_4 ( .OUT(na815_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a815_5 ( .OUT(na815_2), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na815_2_i) ); +// C_///AND/D x118y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a816_4 ( .OUT(na816_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a816_5 ( .OUT(na816_2), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na816_2_i) ); +// C_AND/D/// x126y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a817_1 ( .OUT(na817_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a817_2 ( .OUT(na817_1), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na817_1_i) ); +// C_AND/D/// x126y64 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a818_1 ( .OUT(na818_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a818_2 ( .OUT(na818_1), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na818_1_i) ); +// C_AND/D/// x123y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a819_1 ( .OUT(na819_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a819_2 ( .OUT(na819_1), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na819_1_i) ); +// C_///AND/D x112y70 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a820_4 ( .OUT(na820_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a820_5 ( .OUT(na820_2), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na820_2_i) ); +// C_AND/D/// x129y76 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a821_1 ( .OUT(na821_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a821_2 ( .OUT(na821_1), .CLK(na2414_1), .EN(na158_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na821_1_i) ); +// C_///AND/D x117y30 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a822_4 ( .OUT(na822_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a822_5 ( .OUT(na822_2), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na822_2_i) ); +// C_///AND/D x121y41 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a823_4 ( .OUT(na823_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a823_5 ( .OUT(na823_2), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na823_2_i) ); +// C_///AND/D x119y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a824_4 ( .OUT(na824_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a824_5 ( .OUT(na824_2), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na824_2_i) ); +// C_AND/D/// x116y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a825_1 ( .OUT(na825_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a825_2 ( .OUT(na825_1), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na825_1_i) ); +// C_AND/D/// x113y47 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a826_1 ( .OUT(na826_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a826_2 ( .OUT(na826_1), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na826_1_i) ); +// C_AND/D/// x125y51 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a827_1 ( .OUT(na827_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a827_2 ( .OUT(na827_1), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na827_1_i) ); +// C_///AND/D x129y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a828_4 ( .OUT(na828_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a828_5 ( .OUT(na828_2), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na828_2_i) ); +// C_///AND/D x124y70 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a829_4 ( .OUT(na829_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a829_5 ( .OUT(na829_2), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na829_2_i) ); +// C_///AND/D x109y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a830_4 ( .OUT(na830_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a830_5 ( .OUT(na830_2), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na830_2_i) ); +// C_AND/D/// x128y73 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a831_1 ( .OUT(na831_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a831_2 ( .OUT(na831_1), .CLK(na2414_1), .EN(na159_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na831_1_i) ); +// C_///AND/D x119y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a832_4 ( .OUT(na832_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a832_5 ( .OUT(na832_2), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na832_2_i) ); +// C_AND/D/// x119y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a833_1 ( .OUT(na833_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a833_2 ( .OUT(na833_1), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na833_1_i) ); +// C_AND/D/// x119y36 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a834_1 ( .OUT(na834_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a834_2 ( .OUT(na834_1), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na834_1_i) ); +// C_AND/D/// x118y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a835_1 ( .OUT(na835_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a835_2 ( .OUT(na835_1), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na835_1_i) ); +// C_///AND/D x113y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a836_4 ( .OUT(na836_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a836_5 ( .OUT(na836_2), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na836_2_i) ); +// C_///AND/D x119y52 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a837_4 ( .OUT(na837_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a837_5 ( .OUT(na837_2), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na837_2_i) ); +// C_///AND/D x131y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a838_4 ( .OUT(na838_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a838_5 ( .OUT(na838_2), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na838_2_i) ); +// C_AND/D/// x128y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a839_1 ( .OUT(na839_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a839_2 ( .OUT(na839_1), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na839_1_i) ); +// C_AND/D/// x111y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a840_1 ( .OUT(na840_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a840_2 ( .OUT(na840_1), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na840_1_i) ); +// C_AND/D/// x130y76 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a841_1 ( .OUT(na841_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a841_2 ( .OUT(na841_1), .CLK(na2414_1), .EN(na160_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na841_1_i) ); +// C_///AND/D x123y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a842_4 ( .OUT(na842_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a842_5 ( .OUT(na842_2), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na842_2_i) ); +// C_AND/D/// x119y47 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a843_1 ( .OUT(na843_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a843_2 ( .OUT(na843_1), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na843_1_i) ); +// C_///AND/D x120y41 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a844_4 ( .OUT(na844_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a844_5 ( .OUT(na844_2), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na844_2_i) ); +// C_///AND/D x122y45 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a845_4 ( .OUT(na845_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a845_5 ( .OUT(na845_2), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na845_2_i) ); +// C_///AND/D x113y55 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a846_4 ( .OUT(na846_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a846_5 ( .OUT(na846_2), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na846_2_i) ); +// C_AND/D/// x123y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a847_1 ( .OUT(na847_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a847_2 ( .OUT(na847_1), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na847_1_i) ); +// C_AND/D/// x131y65 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a848_1 ( .OUT(na848_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a848_2 ( .OUT(na848_1), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na848_1_i) ); +// C_AND/D/// x123y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a849_1 ( .OUT(na849_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a849_2 ( .OUT(na849_1), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na849_1_i) ); +// C_///AND/D x118y73 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a850_4 ( .OUT(na850_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a850_5 ( .OUT(na850_2), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na850_2_i) ); +// C_///AND/D x126y79 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a851_4 ( .OUT(na851_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a851_5 ( .OUT(na851_2), .CLK(na2414_1), .EN(na161_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na851_2_i) ); +// C_///AND/D x119y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a852_4 ( .OUT(na852_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a852_5 ( .OUT(na852_2), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na852_2_i) ); +// C_AND/D/// x121y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a853_1 ( .OUT(na853_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a853_2 ( .OUT(na853_1), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na853_1_i) ); +// C_///AND/D x118y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a854_4 ( .OUT(na854_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a854_5 ( .OUT(na854_2), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na854_2_i) ); +// C_AND/D/// x118y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a855_1 ( .OUT(na855_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a855_2 ( .OUT(na855_1), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na855_1_i) ); +// C_AND/D/// x113y51 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a856_1 ( .OUT(na856_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a856_2 ( .OUT(na856_1), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na856_1_i) ); +// C_AND/D/// x128y51 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a857_1 ( .OUT(na857_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a857_2 ( .OUT(na857_1), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na857_1_i) ); +// C_///AND/D x133y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a858_4 ( .OUT(na858_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a858_5 ( .OUT(na858_2), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na858_2_i) ); +// C_///AND/D x124y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a859_4 ( .OUT(na859_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a859_5 ( .OUT(na859_2), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na859_2_i) ); +// C_///AND/D x113y70 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a860_4 ( .OUT(na860_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a860_5 ( .OUT(na860_2), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na860_2_i) ); +// C_AND/D/// x125y76 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a861_1 ( .OUT(na861_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a861_2 ( .OUT(na861_1), .CLK(na2414_1), .EN(na151_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na861_1_i) ); +// C_AND/D/// x118y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a862_1 ( .OUT(na862_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a862_2 ( .OUT(na862_1), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na862_1_i) ); +// C_AND/D/// x120y43 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a863_1 ( .OUT(na863_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a863_2 ( .OUT(na863_1), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na863_1_i) ); +// C_///AND/D x121y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a864_4 ( .OUT(na864_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a864_5 ( .OUT(na864_2), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na864_2_i) ); +// C_AND/D/// x119y41 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a865_1 ( .OUT(na865_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a865_2 ( .OUT(na865_1), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na865_1_i) ); +// C_///AND/D x114y55 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a866_4 ( .OUT(na866_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a866_5 ( .OUT(na866_2), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na866_2_i) ); +// C_///AND/D x124y50 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a867_4 ( .OUT(na867_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a867_5 ( .OUT(na867_2), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na867_2_i) ); +// C_///AND/D x138y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a868_4 ( .OUT(na868_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a868_5 ( .OUT(na868_2), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na868_2_i) ); +// C_AND/D/// x126y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a869_1 ( .OUT(na869_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a869_2 ( .OUT(na869_1), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na869_1_i) ); +// C_AND/D/// x115y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a870_1 ( .OUT(na870_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a870_2 ( .OUT(na870_1), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na870_1_i) ); +// C_AND/D/// x125y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a871_1 ( .OUT(na871_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a871_2 ( .OUT(na871_1), .CLK(na2414_1), .EN(na163_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na871_1_i) ); +// C_///AND/D x118y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a872_4 ( .OUT(na872_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a872_5 ( .OUT(na872_2), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na872_2_i) ); +// C_///AND/D x122y42 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a873_4 ( .OUT(na873_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a873_5 ( .OUT(na873_2), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na873_2_i) ); +// C_///AND/D x121y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a874_4 ( .OUT(na874_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a874_5 ( .OUT(na874_2), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na874_2_i) ); +// C_AND/D/// x119y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a875_1 ( .OUT(na875_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a875_2 ( .OUT(na875_1), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na875_1_i) ); +// C_///AND/D x116y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a876_4 ( .OUT(na876_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a876_5 ( .OUT(na876_2), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na876_2_i) ); +// C_AND/D/// x124y51 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a877_1 ( .OUT(na877_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a877_2 ( .OUT(na877_1), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na877_1_i) ); +// C_AND/D/// x132y66 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a878_1 ( .OUT(na878_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a878_2 ( .OUT(na878_1), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na878_1_i) ); +// C_AND/D/// x124y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a879_1 ( .OUT(na879_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a879_2 ( .OUT(na879_1), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na879_1_i) ); +// C_///AND/D x123y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a880_4 ( .OUT(na880_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a880_5 ( .OUT(na880_2), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na880_2_i) ); +// C_///AND/D x123y82 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a881_4 ( .OUT(na881_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a881_5 ( .OUT(na881_2), .CLK(na2414_1), .EN(na164_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na881_2_i) ); +// C_///AND/D x122y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a882_4 ( .OUT(na882_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a882_5 ( .OUT(na882_2), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na882_2_i) ); +// C_AND/D/// x123y41 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a883_1 ( .OUT(na883_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a883_2 ( .OUT(na883_1), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na883_1_i) ); +// C_AND/D/// x115y36 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a884_1 ( .OUT(na884_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a884_2 ( .OUT(na884_1), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na884_1_i) ); +// C_AND/D/// x121y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a885_1 ( .OUT(na885_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a885_2 ( .OUT(na885_1), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na885_1_i) ); +// C_///AND/D x119y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a886_4 ( .OUT(na886_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a886_5 ( .OUT(na886_2), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na886_2_i) ); +// C_AND/D/// x129y54 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a887_1 ( .OUT(na887_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a887_2 ( .OUT(na887_1), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na887_1_i) ); +// C_///AND/D x134y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a888_4 ( .OUT(na888_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a888_5 ( .OUT(na888_2), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na888_2_i) ); +// C_///AND/D x123y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a889_4 ( .OUT(na889_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a889_5 ( .OUT(na889_2), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na889_2_i) ); +// C_///AND/D x113y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a890_4 ( .OUT(na890_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a890_5 ( .OUT(na890_2), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na890_2_i) ); +// C_AND/D/// x124y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a891_1 ( .OUT(na891_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a891_2 ( .OUT(na891_1), .CLK(na2414_1), .EN(na165_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na891_1_i) ); +// C_AND/D/// x120y31 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a892_1 ( .OUT(na892_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a892_2 ( .OUT(na892_1), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na892_1_i) ); +// C_AND/D/// x121y42 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a893_1 ( .OUT(na893_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a893_2 ( .OUT(na893_1), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na893_1_i) ); +// C_///AND/D x117y41 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a894_4 ( .OUT(na894_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a894_5 ( .OUT(na894_2), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na894_2_i) ); +// C_///AND/D x121y44 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a895_4 ( .OUT(na895_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a895_5 ( .OUT(na895_2), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na895_2_i) ); +// C_///AND/D x119y53 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a896_4 ( .OUT(na896_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a896_5 ( .OUT(na896_2), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na896_2_i) ); +// C_AND/D/// x131y53 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a897_1 ( .OUT(na897_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a897_2 ( .OUT(na897_1), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na897_1_i) ); +// C_///AND/D x136y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a898_4 ( .OUT(na898_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a898_5 ( .OUT(na898_2), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na898_2_i) ); +// C_AND/D/// x121y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a899_1 ( .OUT(na899_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a899_2 ( .OUT(na899_1), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na899_1_i) ); +// C_AND/D/// x113y82 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a900_1 ( .OUT(na900_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a900_2 ( .OUT(na900_1), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na900_1_i) ); +// C_AND/D/// x126y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a901_1 ( .OUT(na901_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a901_2 ( .OUT(na901_1), .CLK(na2414_1), .EN(na166_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na901_1_i) ); +// C_///AND/D x121y36 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a902_4 ( .OUT(na902_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a902_5 ( .OUT(na902_2), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na902_2_i) ); +// C_///AND/D x122y43 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a903_4 ( .OUT(na903_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a903_5 ( .OUT(na903_2), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na903_2_i) ); +// C_///AND/D x116y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a904_4 ( .OUT(na904_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a904_5 ( .OUT(na904_2), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na904_2_i) ); +// C_AND/D/// x120y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a905_1 ( .OUT(na905_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a905_2 ( .OUT(na905_1), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na905_1_i) ); +// C_AND/D/// x114y54 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a906_1 ( .OUT(na906_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a906_2 ( .OUT(na906_1), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na906_1_i) ); +// C_AND/D/// x128y54 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a907_1 ( .OUT(na907_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a907_2 ( .OUT(na907_1), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na907_1_i) ); +// C_///AND/D x137y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a908_4 ( .OUT(na908_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a908_5 ( .OUT(na908_2), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na908_2_i) ); +// C_AND/D/// x122y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a909_1 ( .OUT(na909_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a909_2 ( .OUT(na909_1), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na909_1_i) ); +// C_///AND/D x118y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a910_4 ( .OUT(na910_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a910_5 ( .OUT(na910_2), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na910_2_i) ); +// C_///AND/D x127y80 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a911_4 ( .OUT(na911_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a911_5 ( .OUT(na911_2), .CLK(na2414_1), .EN(na167_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na911_2_i) ); +// C_///AND/D x119y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a912_4 ( .OUT(na912_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a912_5 ( .OUT(na912_2), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na912_2_i) ); +// C_AND/D/// x123y44 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a913_1 ( .OUT(na913_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a913_2 ( .OUT(na913_1), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na913_1_i) ); +// C_AND/D/// x118y38 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a914_1 ( .OUT(na914_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a914_2 ( .OUT(na914_1), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na914_1_i) ); +// C_AND/D/// x120y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a915_1 ( .OUT(na915_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a915_2 ( .OUT(na915_1), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na915_1_i) ); +// C_///AND/D x113y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a916_4 ( .OUT(na916_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a916_5 ( .OUT(na916_2), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na916_2_i) ); +// C_///AND/D x121y53 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a917_4 ( .OUT(na917_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a917_5 ( .OUT(na917_2), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na917_2_i) ); +// C_///AND/D x137y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a918_4 ( .OUT(na918_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a918_5 ( .OUT(na918_2), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na918_2_i) ); +// C_AND/D/// x125y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a919_1 ( .OUT(na919_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a919_2 ( .OUT(na919_1), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na919_1_i) ); +// C_///AND/D x122y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a920_4 ( .OUT(na920_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a920_5 ( .OUT(na920_2), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na920_2_i) ); +// C_AND/D/// x122y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a921_1 ( .OUT(na921_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a921_2 ( .OUT(na921_1), .CLK(na2414_1), .EN(na162_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na921_1_i) ); +// C_AND/D/// x127y31 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a922_1 ( .OUT(na922_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a922_2 ( .OUT(na922_1), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na922_1_i) ); +// C_AND/D/// x126y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a923_1 ( .OUT(na923_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a923_2 ( .OUT(na923_1), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na923_1_i) ); +// C_///AND/D x114y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a924_4 ( .OUT(na924_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a924_5 ( .OUT(na924_2), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na924_2_i) ); +// C_///AND/D x122y47 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a925_4 ( .OUT(na925_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a925_5 ( .OUT(na925_2), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na925_2_i) ); +// C_///AND/D x122y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a926_4 ( .OUT(na926_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a926_5 ( .OUT(na926_2), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na926_2_i) ); +// C_AND/D/// x115y57 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a927_1 ( .OUT(na927_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a927_2 ( .OUT(na927_1), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na927_1_i) ); +// C_AND/D/// x116y63 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a928_1 ( .OUT(na928_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a928_2 ( .OUT(na928_1), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na928_1_i) ); +// C_AND/D/// x113y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a929_1 ( .OUT(na929_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a929_2 ( .OUT(na929_1), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na929_1_i) ); +// C_///AND/D x124y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a930_4 ( .OUT(na930_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a930_5 ( .OUT(na930_2), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na930_2_i) ); +// C_AND/D/// x140y69 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a931_1 ( .OUT(na931_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a931_2 ( .OUT(na931_1), .CLK(na2414_1), .EN(na186_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na931_1_i) ); +// C_///AND/D x123y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a932_4 ( .OUT(na932_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a932_5 ( .OUT(na932_2), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na932_2_i) ); +// C_///AND/D x121y34 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a933_4 ( .OUT(na933_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a933_5 ( .OUT(na933_2), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na933_2_i) ); +// C_///AND/D x114y47 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a934_4 ( .OUT(na934_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a934_5 ( .OUT(na934_2), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na934_2_i) ); +// C_AND/D/// x112y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a935_1 ( .OUT(na935_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a935_2 ( .OUT(na935_1), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na935_1_i) ); +// C_AND/D/// x111y53 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a936_1 ( .OUT(na936_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a936_2 ( .OUT(na936_1), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na936_1_i) ); +// C_AND/D/// x115y55 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a937_1 ( .OUT(na937_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a937_2 ( .OUT(na937_1), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na937_1_i) ); +// C_///AND/D x117y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a938_4 ( .OUT(na938_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a938_5 ( .OUT(na938_2), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na938_2_i) ); +// C_///AND/D x114y65 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a939_4 ( .OUT(na939_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a939_5 ( .OUT(na939_2), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na939_2_i) ); +// C_///AND/D x119y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a940_4 ( .OUT(na940_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a940_5 ( .OUT(na940_2), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na940_2_i) ); +// C_AND/D/// x135y74 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a941_1 ( .OUT(na941_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a941_2 ( .OUT(na941_1), .CLK(na2414_1), .EN(na172_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na941_1_i) ); +// C_///AND/D x126y30 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a942_4 ( .OUT(na942_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a942_5 ( .OUT(na942_2), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na942_2_i) ); +// C_AND/D/// x120y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a943_1 ( .OUT(na943_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a943_2 ( .OUT(na943_1), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na943_1_i) ); +// C_AND/D/// x111y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a944_1 ( .OUT(na944_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a944_2 ( .OUT(na944_1), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na944_1_i) ); +// C_AND/D/// x115y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a945_1 ( .OUT(na945_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a945_2 ( .OUT(na945_1), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na945_1_i) ); +// C_///AND/D x118y50 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a946_4 ( .OUT(na946_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a946_5 ( .OUT(na946_2), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na946_2_i) ); +// C_///AND/D x122y56 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a947_4 ( .OUT(na947_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a947_5 ( .OUT(na947_2), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na947_2_i) ); +// C_///AND/D x116y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a948_4 ( .OUT(na948_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a948_5 ( .OUT(na948_2), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na948_2_i) ); +// C_AND/D/// x111y66 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a949_1 ( .OUT(na949_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a949_2 ( .OUT(na949_1), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na949_1_i) ); +// C_AND/D/// x116y78 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a950_1 ( .OUT(na950_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a950_2 ( .OUT(na950_1), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na950_1_i) ); +// C_AND/D/// x136y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a951_1 ( .OUT(na951_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a951_2 ( .OUT(na951_1), .CLK(na2414_1), .EN(na173_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na951_1_i) ); +// C_///AND/D x126y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a952_4 ( .OUT(na952_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a952_5 ( .OUT(na952_2), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na952_2_i) ); +// C_AND/D/// x124y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a953_1 ( .OUT(na953_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a953_2 ( .OUT(na953_1), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na953_1_i) ); +// C_///AND/D x117y47 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a954_4 ( .OUT(na954_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a954_5 ( .OUT(na954_2), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na954_2_i) ); +// C_///AND/D x121y49 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a955_4 ( .OUT(na955_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a955_5 ( .OUT(na955_2), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na955_2_i) ); +// C_///AND/D x116y45 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a956_4 ( .OUT(na956_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a956_5 ( .OUT(na956_2), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na956_2_i) ); +// C_AND/D/// x112y55 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a957_1 ( .OUT(na957_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a957_2 ( .OUT(na957_1), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na957_1_i) ); +// C_AND/D/// x118y65 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a958_1 ( .OUT(na958_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a958_2 ( .OUT(na958_1), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na958_1_i) ); +// C_AND/D/// x109y65 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a959_1 ( .OUT(na959_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a959_2 ( .OUT(na959_1), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na959_1_i) ); +// C_///AND/D x122y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a960_4 ( .OUT(na960_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a960_5 ( .OUT(na960_2), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na960_2_i) ); +// C_///AND/D x136y76 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a961_4 ( .OUT(na961_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a961_5 ( .OUT(na961_2), .CLK(na2414_1), .EN(na174_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na961_2_i) ); +// C_///AND/D x132y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a962_4 ( .OUT(na962_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a962_5 ( .OUT(na962_2), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na962_2_i) ); +// C_AND/D/// x124y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a963_1 ( .OUT(na963_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a963_2 ( .OUT(na963_1), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na963_1_i) ); +// C_///AND/D x115y47 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a964_4 ( .OUT(na964_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a964_5 ( .OUT(na964_2), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na964_2_i) ); +// C_AND/D/// x116y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a965_1 ( .OUT(na965_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a965_2 ( .OUT(na965_1), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na965_1_i) ); +// C_AND/D/// x114y53 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a966_1 ( .OUT(na966_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a966_2 ( .OUT(na966_1), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na966_1_i) ); +// C_AND/D/// x116y52 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a967_1 ( .OUT(na967_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a967_2 ( .OUT(na967_1), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na967_1_i) ); +// C_///AND/D x122y64 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a968_4 ( .OUT(na968_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a968_5 ( .OUT(na968_2), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na968_2_i) ); +// C_///AND/D x113y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a969_4 ( .OUT(na969_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a969_5 ( .OUT(na969_2), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na969_2_i) ); +// C_///AND/D x118y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a970_4 ( .OUT(na970_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a970_5 ( .OUT(na970_2), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na970_2_i) ); +// C_AND/D/// x135y69 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a971_1 ( .OUT(na971_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a971_2 ( .OUT(na971_1), .CLK(na2414_1), .EN(na175_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na971_1_i) ); +// C_AND/D/// x124y31 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a972_1 ( .OUT(na972_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a972_2 ( .OUT(na972_1), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na972_1_i) ); +// C_AND/D/// x122y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a973_1 ( .OUT(na973_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a973_2 ( .OUT(na973_1), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na973_1_i) ); +// C_///AND/D x113y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a974_4 ( .OUT(na974_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a974_5 ( .OUT(na974_2), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na974_2_i) ); +// C_AND/D/// x118y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a975_1 ( .OUT(na975_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a975_2 ( .OUT(na975_1), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na975_1_i) ); +// C_///AND/D x118y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a976_4 ( .OUT(na976_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a976_5 ( .OUT(na976_2), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na976_2_i) ); +// C_///AND/D x118y55 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a977_4 ( .OUT(na977_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a977_5 ( .OUT(na977_2), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na977_2_i) ); +// C_///AND/D x122y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a978_4 ( .OUT(na978_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a978_5 ( .OUT(na978_2), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na978_2_i) ); +// C_AND/D/// x115y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a979_1 ( .OUT(na979_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a979_2 ( .OUT(na979_1), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na979_1_i) ); +// C_AND/D/// x114y80 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a980_1 ( .OUT(na980_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a980_2 ( .OUT(na980_1), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na980_1_i) ); +// C_AND/D/// x139y70 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a981_1 ( .OUT(na981_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a981_2 ( .OUT(na981_1), .CLK(na2414_1), .EN(na176_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na981_1_i) ); +// C_///AND/D x135y30 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a982_4 ( .OUT(na982_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a982_5 ( .OUT(na982_2), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na982_2_i) ); +// C_///AND/D x123y34 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a983_4 ( .OUT(na983_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a983_5 ( .OUT(na983_2), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na983_2_i) ); +// C_///AND/D x112y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a984_4 ( .OUT(na984_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a984_5 ( .OUT(na984_2), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na984_2_i) ); +// C_AND/D/// x115y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a985_1 ( .OUT(na985_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a985_2 ( .OUT(na985_1), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na985_1_i) ); +// C_AND/D/// x113y57 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a986_1 ( .OUT(na986_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a986_2 ( .OUT(na986_1), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na986_1_i) ); +// C_AND/D/// x115y50 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a987_1 ( .OUT(na987_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a987_2 ( .OUT(na987_1), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na987_1_i) ); +// C_///AND/D x119y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a988_4 ( .OUT(na988_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a988_5 ( .OUT(na988_2), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na988_2_i) ); +// C_AND/D/// x116y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a989_1 ( .OUT(na989_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a989_2 ( .OUT(na989_1), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na989_1_i) ); +// C_///AND/D x119y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a990_4 ( .OUT(na990_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a990_5 ( .OUT(na990_2), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na990_2_i) ); +// C_AND/D/// x140y71 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a991_1 ( .OUT(na991_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a991_2 ( .OUT(na991_1), .CLK(na2414_1), .EN(na177_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na991_1_i) ); +// C_///AND/D x133y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a992_4 ( .OUT(na992_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a992_5 ( .OUT(na992_2), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na992_2_i) ); +// C_///AND/D x123y35 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a993_4 ( .OUT(na993_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a993_5 ( .OUT(na993_2), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na993_2_i) ); +// C_///AND/D x112y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a994_4 ( .OUT(na994_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a994_5 ( .OUT(na994_2), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na994_2_i) ); +// C_AND/D/// x113y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a995_1 ( .OUT(na995_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a995_2 ( .OUT(na995_1), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na995_1_i) ); +// C_///AND/D x117y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a996_4 ( .OUT(na996_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a996_5 ( .OUT(na996_2), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na996_2_i) ); +// C_AND/D/// x117y51 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a997_1 ( .OUT(na997_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a997_2 ( .OUT(na997_1), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na997_1_i) ); +// C_///AND/D x123y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a998_4 ( .OUT(na998_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a998_5 ( .OUT(na998_2), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na998_2_i) ); +// C_AND/D/// x114y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a999_1 ( .OUT(na999_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a999_2 ( .OUT(na999_1), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), .D_IN(na999_1_i) ); +// C_AND/D/// x115y80 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1000_1 ( .OUT(na1000_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1000_2 ( .OUT(na1000_1), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1000_1_i) ); +// C_AND/D/// x138y72 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1001_1 ( .OUT(na1001_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1001_2 ( .OUT(na1001_1), .CLK(na2414_1), .EN(na178_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1001_1_i) ); +// C_///AND/D x141y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1002_4 ( .OUT(na1002_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1002_5 ( .OUT(na1002_2), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1002_2_i) ); +// C_AND/D/// x123y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1003_1 ( .OUT(na1003_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1003_2 ( .OUT(na1003_1), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1003_1_i) ); +// C_///AND/D x112y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1004_4 ( .OUT(na1004_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1004_5 ( .OUT(na1004_2), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1004_2_i) ); +// C_AND/D/// x118y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1005_1 ( .OUT(na1005_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1005_2 ( .OUT(na1005_1), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1005_1_i) ); +// C_///AND/D x115y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1006_4 ( .OUT(na1006_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1006_5 ( .OUT(na1006_2), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1006_2_i) ); +// C_///AND/D x121y57 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1007_4 ( .OUT(na1007_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1007_5 ( .OUT(na1007_2), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1007_2_i) ); +// C_///AND/D x117y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1008_4 ( .OUT(na1008_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1008_5 ( .OUT(na1008_2), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1008_2_i) ); +// C_AND/D/// x113y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1009_1 ( .OUT(na1009_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1009_2 ( .OUT(na1009_1), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1009_1_i) ); +// C_///AND/D x113y69 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1010_4 ( .OUT(na1010_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1010_5 ( .OUT(na1010_2), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1010_2_i) ); +// C_AND/D/// x135y72 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1011_1 ( .OUT(na1011_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1011_2 ( .OUT(na1011_1), .CLK(na2414_1), .EN(na179_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1011_1_i) ); +// C_///AND/D x129y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1012_4 ( .OUT(na1012_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1012_5 ( .OUT(na1012_2), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1012_2_i) ); +// C_AND/D/// x121y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1013_1 ( .OUT(na1013_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1013_2 ( .OUT(na1013_1), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1013_1_i) ); +// C_AND/D/// x112y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1014_1 ( .OUT(na1014_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1014_2 ( .OUT(na1014_1), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1014_1_i) ); +// C_AND/D/// x114y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1015_1 ( .OUT(na1015_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1015_2 ( .OUT(na1015_1), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1015_1_i) ); +// C_///AND/D x117y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1016_4 ( .OUT(na1016_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1016_5 ( .OUT(na1016_2), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1016_2_i) ); +// C_AND/D/// x115y56 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1017_1 ( .OUT(na1017_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1017_2 ( .OUT(na1017_1), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1017_1_i) ); +// C_///AND/D x117y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1018_4 ( .OUT(na1018_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1018_5 ( .OUT(na1018_2), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1018_2_i) ); +// C_AND/D/// x112y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1019_1 ( .OUT(na1019_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1019_2 ( .OUT(na1019_1), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1019_1_i) ); +// C_///AND/D x117y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1020_4 ( .OUT(na1020_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1020_5 ( .OUT(na1020_2), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1020_2_i) ); +// C_///AND/D x137y77 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1021_4 ( .OUT(na1021_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1021_5 ( .OUT(na1021_2), .CLK(na2414_1), .EN(na169_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1021_2_i) ); +// C_///AND/D x142y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1022_4 ( .OUT(na1022_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1022_5 ( .OUT(na1022_2), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1022_2_i) ); +// C_AND/D/// x122y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1023_1 ( .OUT(na1023_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1023_2 ( .OUT(na1023_1), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1023_1_i) ); +// C_///AND/D x111y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1024_4 ( .OUT(na1024_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1024_5 ( .OUT(na1024_2), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1024_2_i) ); +// C_AND/D/// x117y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1025_1 ( .OUT(na1025_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1025_2 ( .OUT(na1025_1), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1025_1_i) ); +// C_///AND/D x118y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1026_4 ( .OUT(na1026_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1026_5 ( .OUT(na1026_2), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1026_2_i) ); +// C_AND/D/// x120y55 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1027_1 ( .OUT(na1027_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1027_2 ( .OUT(na1027_1), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1027_1_i) ); +// C_AND/D/// x116y66 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1028_1 ( .OUT(na1028_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1028_2 ( .OUT(na1028_1), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1028_1_i) ); +// C_AND/D/// x112y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1029_1 ( .OUT(na1029_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1029_2 ( .OUT(na1029_1), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1029_1_i) ); +// C_///AND/D x116y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1030_4 ( .OUT(na1030_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1030_5 ( .OUT(na1030_2), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1030_2_i) ); +// C_AND/D/// x136y70 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1031_1 ( .OUT(na1031_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1031_2 ( .OUT(na1031_1), .CLK(na2414_1), .EN(na181_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1031_1_i) ); +// C_///AND/D x142y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1032_4 ( .OUT(na1032_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1032_5 ( .OUT(na1032_2), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1032_2_i) ); +// C_AND/D/// x122y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1033_1 ( .OUT(na1033_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1033_2 ( .OUT(na1033_1), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1033_1_i) ); +// C_///AND/D x109y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1034_4 ( .OUT(na1034_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1034_5 ( .OUT(na1034_2), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1034_2_i) ); +// C_///AND/D x121y50 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1035_4 ( .OUT(na1035_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1035_5 ( .OUT(na1035_2), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1035_2_i) ); +// C_///AND/D x118y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1036_4 ( .OUT(na1036_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1036_5 ( .OUT(na1036_2), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1036_2_i) ); +// C_AND/D/// x120y56 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1037_1 ( .OUT(na1037_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1037_2 ( .OUT(na1037_1), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1037_1_i) ); +// C_///AND/D x122y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1038_4 ( .OUT(na1038_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1038_5 ( .OUT(na1038_2), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1038_2_i) ); +// C_AND/D/// x110y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1039_1 ( .OUT(na1039_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1039_2 ( .OUT(na1039_1), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1039_1_i) ); +// C_///AND/D x114y70 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1040_4 ( .OUT(na1040_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1040_5 ( .OUT(na1040_2), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1040_2_i) ); +// C_AND/D/// x136y71 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1041_1 ( .OUT(na1041_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1041_2 ( .OUT(na1041_1), .CLK(na2414_1), .EN(na182_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1041_1_i) ); +// C_AND/D/// x126y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1042_1 ( .OUT(na1042_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1042_2 ( .OUT(na1042_1), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1042_1_i) ); +// C_AND/D/// x125y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1043_1 ( .OUT(na1043_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1043_2 ( .OUT(na1043_1), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1043_1_i) ); +// C_///AND/D x113y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1044_4 ( .OUT(na1044_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1044_5 ( .OUT(na1044_2), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1044_2_i) ); +// C_AND/D/// x117y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1045_1 ( .OUT(na1045_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1045_2 ( .OUT(na1045_1), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1045_1_i) ); +// C_///AND/D x121y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1046_4 ( .OUT(na1046_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1046_5 ( .OUT(na1046_2), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1046_2_i) ); +// C_AND/D/// x120y58 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1047_1 ( .OUT(na1047_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1047_2 ( .OUT(na1047_1), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1047_1_i) ); +// C_///AND/D x115y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1048_4 ( .OUT(na1048_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1048_5 ( .OUT(na1048_2), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1048_2_i) ); +// C_///AND/D x112y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1049_4 ( .OUT(na1049_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1049_5 ( .OUT(na1049_2), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1049_2_i) ); +// C_///AND/D x121y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1050_4 ( .OUT(na1050_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1050_5 ( .OUT(na1050_2), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1050_2_i) ); +// C_AND/D/// x139y72 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1051_1 ( .OUT(na1051_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1051_2 ( .OUT(na1051_1), .CLK(na2414_1), .EN(na183_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1051_1_i) ); +// C_///AND/D x138y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1052_4 ( .OUT(na1052_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1052_5 ( .OUT(na1052_2), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1052_2_i) ); +// C_AND/D/// x125y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1053_1 ( .OUT(na1053_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1053_2 ( .OUT(na1053_1), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1053_1_i) ); +// C_///AND/D x111y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1054_4 ( .OUT(na1054_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1054_5 ( .OUT(na1054_2), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1054_2_i) ); +// C_AND/D/// x119y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1055_1 ( .OUT(na1055_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1055_2 ( .OUT(na1055_1), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1055_1_i) ); +// C_AND/D/// x115y51 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1056_1 ( .OUT(na1056_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1056_2 ( .OUT(na1056_1), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1056_1_i) ); +// C_AND/D/// x120y57 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1057_1 ( .OUT(na1057_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1057_2 ( .OUT(na1057_1), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1057_1_i) ); +// C_///AND/D x119y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1058_4 ( .OUT(na1058_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1058_5 ( .OUT(na1058_2), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1058_2_i) ); +// C_AND/D/// x114y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1059_1 ( .OUT(na1059_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1059_2 ( .OUT(na1059_1), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1059_1_i) ); +// C_///AND/D x127y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1060_4 ( .OUT(na1060_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1060_5 ( .OUT(na1060_2), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1060_2_i) ); +// C_AND/D/// x141y71 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1061_1 ( .OUT(na1061_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1061_2 ( .OUT(na1061_1), .CLK(na2414_1), .EN(na184_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1061_1_i) ); +// C_///AND/D x137y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1062_4 ( .OUT(na1062_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1062_5 ( .OUT(na1062_2), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1062_2_i) ); +// C_///AND/D x124y37 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1063_4 ( .OUT(na1063_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1063_5 ( .OUT(na1063_2), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1063_2_i) ); +// C_///AND/D x116y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1064_4 ( .OUT(na1064_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1064_5 ( .OUT(na1064_2), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1064_2_i) ); +// C_AND/D/// x120y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1065_1 ( .OUT(na1065_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1065_2 ( .OUT(na1065_1), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1065_1_i) ); +// C_///AND/D x120y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1066_4 ( .OUT(na1066_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1066_5 ( .OUT(na1066_2), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1066_2_i) ); +// C_AND/D/// x119y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1067_1 ( .OUT(na1067_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1067_2 ( .OUT(na1067_1), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1067_1_i) ); +// C_///AND/D x122y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1068_4 ( .OUT(na1068_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1068_5 ( .OUT(na1068_2), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1068_2_i) ); +// C_AND/D/// x115y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1069_1 ( .OUT(na1069_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1069_2 ( .OUT(na1069_1), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1069_1_i) ); +// C_AND/D/// x116y83 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1070_1 ( .OUT(na1070_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1070_2 ( .OUT(na1070_1), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1070_1_i) ); +// C_AND/D/// x140y72 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1071_1 ( .OUT(na1071_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1071_2 ( .OUT(na1071_1), .CLK(na2414_1), .EN(na185_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1071_1_i) ); +// C_///AND/D x145y30 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1072_4 ( .OUT(na1072_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1072_5 ( .OUT(na1072_2), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1072_2_i) ); +// C_AND/D/// x121y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1073_1 ( .OUT(na1073_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1073_2 ( .OUT(na1073_1), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1073_1_i) ); +// C_///AND/D x112y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1074_4 ( .OUT(na1074_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1074_5 ( .OUT(na1074_2), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1074_2_i) ); +// C_AND/D/// x120y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1075_1 ( .OUT(na1075_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1075_2 ( .OUT(na1075_1), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1075_1_i) ); +// C_///AND/D x119y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1076_4 ( .OUT(na1076_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1076_5 ( .OUT(na1076_2), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1076_2_i) ); +// C_///AND/D x121y60 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1077_4 ( .OUT(na1077_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1077_5 ( .OUT(na1077_2), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1077_2_i) ); +// C_///AND/D x119y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1078_4 ( .OUT(na1078_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1078_5 ( .OUT(na1078_2), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1078_2_i) ); +// C_AND/D/// x111y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1079_1 ( .OUT(na1079_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1079_2 ( .OUT(na1079_1), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1079_1_i) ); +// C_///AND/D x119y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1080_4 ( .OUT(na1080_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1080_5 ( .OUT(na1080_2), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1080_2_i) ); +// C_AND/D/// x137y71 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1081_1 ( .OUT(na1081_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1081_2 ( .OUT(na1081_1), .CLK(na2414_1), .EN(na180_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1081_1_i) ); +// C_///AND/D x132y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1082_4 ( .OUT(na1082_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1082_5 ( .OUT(na1082_2), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1082_2_i) ); +// C_AND/D/// x130y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1083_1 ( .OUT(na1083_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1083_2 ( .OUT(na1083_1), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1083_1_i) ); +// C_AND/D/// x128y39 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1084_1 ( .OUT(na1084_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1084_2 ( .OUT(na1084_1), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1084_1_i) ); +// C_AND/D/// x138y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1085_1 ( .OUT(na1085_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1085_2 ( .OUT(na1085_1), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1085_1_i) ); +// C_///AND/D x129y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1086_4 ( .OUT(na1086_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1086_5 ( .OUT(na1086_2), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1086_2_i) ); +// C_AND/D/// x121y58 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1087_1 ( .OUT(na1087_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1087_2 ( .OUT(na1087_1), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1087_1_i) ); +// C_///AND/D x121y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1088_4 ( .OUT(na1088_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1088_5 ( .OUT(na1088_2), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1088_2_i) ); +// C_AND/D/// x117y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1089_1 ( .OUT(na1089_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1089_2 ( .OUT(na1089_1), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1089_1_i) ); +// C_///AND/D x136y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1090_4 ( .OUT(na1090_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1090_5 ( .OUT(na1090_2), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1090_2_i) ); +// C_///AND/D x133y82 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1091_4 ( .OUT(na1091_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1091_5 ( .OUT(na1091_2), .CLK(na2414_1), .EN(na203_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1091_2_i) ); +// C_///AND/D x129y37 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1092_4 ( .OUT(na1092_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1092_5 ( .OUT(na1092_2), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1092_2_i) ); +// C_AND/D/// x126y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1093_1 ( .OUT(na1093_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1093_2 ( .OUT(na1093_1), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1093_1_i) ); +// C_///AND/D x122y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1094_4 ( .OUT(na1094_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1094_5 ( .OUT(na1094_2), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1094_2_i) ); +// C_AND/D/// x136y40 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1095_1 ( .OUT(na1095_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1095_2 ( .OUT(na1095_1), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1095_1_i) ); +// C_///AND/D x127y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1096_4 ( .OUT(na1096_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1096_5 ( .OUT(na1096_2), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1096_2_i) ); +// C_AND/D/// x122y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1097_1 ( .OUT(na1097_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1097_2 ( .OUT(na1097_1), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1097_1_i) ); +// C_AND/D/// x119y67 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1098_1 ( .OUT(na1098_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1098_2 ( .OUT(na1098_1), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1098_1_i) ); +// C_AND/D/// x115y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1099_1 ( .OUT(na1099_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1099_2 ( .OUT(na1099_1), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1099_1_i) ); +// C_///AND/D x127y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1100_4 ( .OUT(na1100_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1100_5 ( .OUT(na1100_2), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1100_2_i) ); +// C_AND/D/// x127y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1101_1 ( .OUT(na1101_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1101_2 ( .OUT(na1101_1), .CLK(na2414_1), .EN(na189_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1101_1_i) ); +// C_///AND/D x132y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1102_4 ( .OUT(na1102_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1102_5 ( .OUT(na1102_2), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1102_2_i) ); +// C_AND/D/// x127y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1103_1 ( .OUT(na1103_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1103_2 ( .OUT(na1103_1), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1103_1_i) ); +// C_///AND/D x123y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1104_4 ( .OUT(na1104_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1104_5 ( .OUT(na1104_2), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1104_2_i) ); +// C_///AND/D x133y43 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1105_4 ( .OUT(na1105_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1105_5 ( .OUT(na1105_2), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1105_2_i) ); +// C_///AND/D x126y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1106_4 ( .OUT(na1106_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1106_5 ( .OUT(na1106_2), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1106_2_i) ); +// C_AND/D/// x121y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1107_1 ( .OUT(na1107_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1107_2 ( .OUT(na1107_1), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1107_1_i) ); +// C_///AND/D x122y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1108_4 ( .OUT(na1108_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1108_5 ( .OUT(na1108_2), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1108_2_i) ); +// C_AND/D/// x120y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1109_1 ( .OUT(na1109_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1109_2 ( .OUT(na1109_1), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1109_1_i) ); +// C_///AND/D x132y73 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1110_4 ( .OUT(na1110_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1110_5 ( .OUT(na1110_2), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1110_2_i) ); +// C_AND/D/// x128y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1111_1 ( .OUT(na1111_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1111_2 ( .OUT(na1111_1), .CLK(na2414_1), .EN(na190_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1111_1_i) ); +// C_AND/D/// x126y33 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1112_1 ( .OUT(na1112_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1112_2 ( .OUT(na1112_1), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1112_1_i) ); +// C_AND/D/// x129y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1113_1 ( .OUT(na1113_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1113_2 ( .OUT(na1113_1), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1113_1_i) ); +// C_///AND/D x121y37 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1114_4 ( .OUT(na1114_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1114_5 ( .OUT(na1114_2), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1114_2_i) ); +// C_AND/D/// x135y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1115_1 ( .OUT(na1115_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1115_2 ( .OUT(na1115_1), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1115_1_i) ); +// C_///AND/D x126y50 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1116_4 ( .OUT(na1116_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1116_5 ( .OUT(na1116_2), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1116_2_i) ); +// C_AND/D/// x121y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1117_1 ( .OUT(na1117_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1117_2 ( .OUT(na1117_1), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1117_1_i) ); +// C_///AND/D x124y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1118_4 ( .OUT(na1118_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1118_5 ( .OUT(na1118_2), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1118_2_i) ); +// C_///AND/D x124y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1119_4 ( .OUT(na1119_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1119_5 ( .OUT(na1119_2), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1119_2_i) ); +// C_///AND/D x126y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1120_4 ( .OUT(na1120_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1120_5 ( .OUT(na1120_2), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1120_2_i) ); +// C_AND/D/// x130y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1121_1 ( .OUT(na1121_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1121_2 ( .OUT(na1121_1), .CLK(na2414_1), .EN(na191_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1121_1_i) ); +// C_///AND/D x127y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1122_4 ( .OUT(na1122_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1122_5 ( .OUT(na1122_2), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1122_2_i) ); +// C_AND/D/// x128y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1123_1 ( .OUT(na1123_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1123_2 ( .OUT(na1123_1), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1123_1_i) ); +// C_///AND/D x122y36 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1124_4 ( .OUT(na1124_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1124_5 ( .OUT(na1124_2), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1124_2_i) ); +// C_AND/D/// x131y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1125_1 ( .OUT(na1125_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1125_2 ( .OUT(na1125_1), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1125_1_i) ); +// C_AND/D/// x134y57 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1126_1 ( .OUT(na1126_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1126_2 ( .OUT(na1126_1), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1126_1_i) ); +// C_AND/D/// x123y65 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1127_1 ( .OUT(na1127_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1127_2 ( .OUT(na1127_1), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1127_1_i) ); +// C_///AND/D x126y78 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1128_4 ( .OUT(na1128_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1128_5 ( .OUT(na1128_2), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1128_2_i) ); +// C_AND/D/// x117y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1129_1 ( .OUT(na1129_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1129_2 ( .OUT(na1129_1), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1129_1_i) ); +// C_///AND/D x134y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1130_4 ( .OUT(na1130_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1130_5 ( .OUT(na1130_2), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1130_2_i) ); +// C_AND/D/// x127y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1131_1 ( .OUT(na1131_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1131_2 ( .OUT(na1131_1), .CLK(na2414_1), .EN(na192_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1131_1_i) ); +// C_///AND/D x129y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1132_4 ( .OUT(na1132_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1132_5 ( .OUT(na1132_2), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1132_2_i) ); +// C_///AND/D x134y39 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1133_4 ( .OUT(na1133_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1133_5 ( .OUT(na1133_2), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1133_2_i) ); +// C_///AND/D x124y33 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1134_4 ( .OUT(na1134_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1134_5 ( .OUT(na1134_2), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1134_2_i) ); +// C_AND/D/// x133y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1135_1 ( .OUT(na1135_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1135_2 ( .OUT(na1135_1), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1135_1_i) ); +// C_///AND/D x126y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1136_4 ( .OUT(na1136_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1136_5 ( .OUT(na1136_2), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1136_2_i) ); +// C_AND/D/// x125y66 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1137_1 ( .OUT(na1137_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1137_2 ( .OUT(na1137_1), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1137_1_i) ); +// C_///AND/D x122y75 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1138_4 ( .OUT(na1138_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1138_5 ( .OUT(na1138_2), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1138_2_i) ); +// C_AND/D/// x115y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1139_1 ( .OUT(na1139_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1139_2 ( .OUT(na1139_1), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1139_1_i) ); +// C_AND/D/// x128y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1140_1 ( .OUT(na1140_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1140_2 ( .OUT(na1140_1), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1140_1_i) ); +// C_AND/D/// x131y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1141_1 ( .OUT(na1141_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1141_2 ( .OUT(na1141_1), .CLK(na2414_1), .EN(na193_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1141_1_i) ); +// C_///AND/D x126y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1142_4 ( .OUT(na1142_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1142_5 ( .OUT(na1142_2), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1142_2_i) ); +// C_AND/D/// x129y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1143_1 ( .OUT(na1143_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1143_2 ( .OUT(na1143_1), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1143_1_i) ); +// C_///AND/D x123y36 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1144_4 ( .OUT(na1144_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1144_5 ( .OUT(na1144_2), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1144_2_i) ); +// C_AND/D/// x136y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1145_1 ( .OUT(na1145_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1145_2 ( .OUT(na1145_1), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1145_1_i) ); +// C_///AND/D x129y55 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1146_4 ( .OUT(na1146_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1146_5 ( .OUT(na1146_2), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1146_2_i) ); +// C_///AND/D x126y65 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1147_4 ( .OUT(na1147_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1147_5 ( .OUT(na1147_2), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1147_2_i) ); +// C_///AND/D x121y76 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1148_4 ( .OUT(na1148_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1148_5 ( .OUT(na1148_2), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1148_2_i) ); +// C_AND/D/// x120y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1149_1 ( .OUT(na1149_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1149_2 ( .OUT(na1149_1), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1149_1_i) ); +// C_///AND/D x133y73 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1150_4 ( .OUT(na1150_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1150_5 ( .OUT(na1150_2), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1150_2_i) ); +// C_AND/D/// x130y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1151_1 ( .OUT(na1151_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1151_2 ( .OUT(na1151_1), .CLK(na2414_1), .EN(na194_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1151_1_i) ); +// C_///AND/D x132y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1152_4 ( .OUT(na1152_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1152_5 ( .OUT(na1152_2), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1152_2_i) ); +// C_AND/D/// x127y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1153_1 ( .OUT(na1153_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1153_2 ( .OUT(na1153_1), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1153_1_i) ); +// C_AND/D/// x125y33 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1154_1 ( .OUT(na1154_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1154_2 ( .OUT(na1154_1), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1154_1_i) ); +// C_AND/D/// x134y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1155_1 ( .OUT(na1155_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1155_2 ( .OUT(na1155_1), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1155_1_i) ); +// C_///AND/D x127y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1156_4 ( .OUT(na1156_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1156_5 ( .OUT(na1156_2), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1156_2_i) ); +// C_AND/D/// x128y66 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1157_1 ( .OUT(na1157_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1157_2 ( .OUT(na1157_1), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1157_1_i) ); +// C_///AND/D x121y77 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1158_4 ( .OUT(na1158_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1158_5 ( .OUT(na1158_2), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1158_2_i) ); +// C_AND/D/// x118y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1159_1 ( .OUT(na1159_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1159_2 ( .OUT(na1159_1), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1159_1_i) ); +// C_///AND/D x131y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1160_4 ( .OUT(na1160_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1160_5 ( .OUT(na1160_2), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1160_2_i) ); +// C_///AND/D x130y83 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1161_4 ( .OUT(na1161_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1161_5 ( .OUT(na1161_2), .CLK(na2414_1), .EN(na195_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1161_2_i) ); +// C_///AND/D x124y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1162_4 ( .OUT(na1162_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1162_5 ( .OUT(na1162_2), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1162_2_i) ); +// C_AND/D/// x127y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1163_1 ( .OUT(na1163_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1163_2 ( .OUT(na1163_1), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1163_1_i) ); +// C_///AND/D x126y35 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1164_4 ( .OUT(na1164_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1164_5 ( .OUT(na1164_2), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1164_2_i) ); +// C_AND/D/// x131y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1165_1 ( .OUT(na1165_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1165_2 ( .OUT(na1165_1), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1165_1_i) ); +// C_///AND/D x126y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1166_4 ( .OUT(na1166_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1166_5 ( .OUT(na1166_2), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1166_2_i) ); +// C_AND/D/// x126y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1167_1 ( .OUT(na1167_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1167_2 ( .OUT(na1167_1), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1167_1_i) ); +// C_AND/D/// x120y66 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1168_1 ( .OUT(na1168_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1168_2 ( .OUT(na1168_1), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1168_1_i) ); +// C_AND/D/// x120y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1169_1 ( .OUT(na1169_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1169_2 ( .OUT(na1169_1), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1169_1_i) ); +// C_///AND/D x129y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1170_4 ( .OUT(na1170_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1170_5 ( .OUT(na1170_2), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1170_2_i) ); +// C_AND/D/// x127y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1171_1 ( .OUT(na1171_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1171_2 ( .OUT(na1171_1), .CLK(na2414_1), .EN(na196_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1171_1_i) ); +// C_///AND/D x127y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1172_4 ( .OUT(na1172_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1172_5 ( .OUT(na1172_2), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1172_2_i) ); +// C_AND/D/// x130y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1173_1 ( .OUT(na1173_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1173_2 ( .OUT(na1173_1), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1173_1_i) ); +// C_///AND/D x128y40 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1174_4 ( .OUT(na1174_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1174_5 ( .OUT(na1174_2), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1174_2_i) ); +// C_///AND/D x138y43 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1175_4 ( .OUT(na1175_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1175_5 ( .OUT(na1175_2), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1175_2_i) ); +// C_///AND/D x133y47 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1176_4 ( .OUT(na1176_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1176_5 ( .OUT(na1176_2), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1176_2_i) ); +// C_AND/D/// x122y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1177_1 ( .OUT(na1177_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1177_2 ( .OUT(na1177_1), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1177_1_i) ); +// C_///AND/D x121y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1178_4 ( .OUT(na1178_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1178_5 ( .OUT(na1178_2), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1178_2_i) ); +// C_AND/D/// x115y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1179_1 ( .OUT(na1179_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1179_2 ( .OUT(na1179_1), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1179_1_i) ); +// C_///AND/D x129y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1180_4 ( .OUT(na1180_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1180_5 ( .OUT(na1180_2), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1180_2_i) ); +// C_AND/D/// x129y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1181_1 ( .OUT(na1181_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1181_2 ( .OUT(na1181_1), .CLK(na2414_1), .EN(na187_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1181_1_i) ); +// C_AND/D/// x129y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1182_1 ( .OUT(na1182_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1182_2 ( .OUT(na1182_1), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1182_1_i) ); +// C_AND/D/// x130y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1183_1 ( .OUT(na1183_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1183_2 ( .OUT(na1183_1), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1183_1_i) ); +// C_///AND/D x129y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1184_4 ( .OUT(na1184_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1184_5 ( .OUT(na1184_2), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1184_2_i) ); +// C_AND/D/// x130y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1185_1 ( .OUT(na1185_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1185_2 ( .OUT(na1185_1), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1185_1_i) ); +// C_///AND/D x129y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1186_4 ( .OUT(na1186_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1186_5 ( .OUT(na1186_2), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1186_2_i) ); +// C_AND/D/// x123y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1187_1 ( .OUT(na1187_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1187_2 ( .OUT(na1187_1), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1187_1_i) ); +// C_///AND/D x123y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1188_4 ( .OUT(na1188_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1188_5 ( .OUT(na1188_2), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1188_2_i) ); +// C_///AND/D x117y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1189_4 ( .OUT(na1189_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1189_5 ( .OUT(na1189_2), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1189_2_i) ); +// C_///AND/D x132y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1190_4 ( .OUT(na1190_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1190_5 ( .OUT(na1190_2), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1190_2_i) ); +// C_AND/D/// x128y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1191_1 ( .OUT(na1191_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1191_2 ( .OUT(na1191_1), .CLK(na2414_1), .EN(na198_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1191_1_i) ); +// C_///AND/D x131y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1192_4 ( .OUT(na1192_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1192_5 ( .OUT(na1192_2), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1192_2_i) ); +// C_AND/D/// x128y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1193_1 ( .OUT(na1193_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1193_2 ( .OUT(na1193_1), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1193_1_i) ); +// C_///AND/D x127y40 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1194_4 ( .OUT(na1194_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1194_5 ( .OUT(na1194_2), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1194_2_i) ); +// C_AND/D/// x132y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1195_1 ( .OUT(na1195_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1195_2 ( .OUT(na1195_1), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1195_1_i) ); +// C_AND/D/// x131y58 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1196_1 ( .OUT(na1196_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1196_2 ( .OUT(na1196_1), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1196_1_i) ); +// C_AND/D/// x125y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1197_1 ( .OUT(na1197_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1197_2 ( .OUT(na1197_1), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1197_1_i) ); +// C_///AND/D x125y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1198_4 ( .OUT(na1198_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1198_5 ( .OUT(na1198_2), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1198_2_i) ); +// C_AND/D/// x119y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1199_1 ( .OUT(na1199_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1199_2 ( .OUT(na1199_1), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1199_1_i) ); +// C_///AND/D x132y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1200_4 ( .OUT(na1200_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1200_5 ( .OUT(na1200_2), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1200_2_i) ); +// C_AND/D/// x130y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1201_1 ( .OUT(na1201_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1201_2 ( .OUT(na1201_1), .CLK(na2414_1), .EN(na199_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1201_1_i) ); +// C_///AND/D x131y36 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1202_4 ( .OUT(na1202_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1202_5 ( .OUT(na1202_2), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1202_2_i) ); +// C_///AND/D x131y38 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1203_4 ( .OUT(na1203_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1203_5 ( .OUT(na1203_2), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1203_2_i) ); +// C_///AND/D x127y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1204_4 ( .OUT(na1204_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1204_5 ( .OUT(na1204_2), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1204_2_i) ); +// C_AND/D/// x135y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1205_1 ( .OUT(na1205_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1205_2 ( .OUT(na1205_1), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1205_1_i) ); +// C_///AND/D x132y52 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1206_4 ( .OUT(na1206_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1206_5 ( .OUT(na1206_2), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1206_2_i) ); +// C_AND/D/// x122y57 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1207_1 ( .OUT(na1207_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1207_2 ( .OUT(na1207_1), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1207_1_i) ); +// C_///AND/D x124y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1208_4 ( .OUT(na1208_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1208_5 ( .OUT(na1208_2), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1208_2_i) ); +// C_AND/D/// x118y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1209_1 ( .OUT(na1209_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1209_2 ( .OUT(na1209_1), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1209_1_i) ); +// C_AND/D/// x129y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1210_1 ( .OUT(na1210_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1210_2 ( .OUT(na1210_1), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1210_1_i) ); +// C_AND/D/// x126y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1211_1 ( .OUT(na1211_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1211_2 ( .OUT(na1211_1), .CLK(na2414_1), .EN(na200_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1211_1_i) ); +// C_///AND/D x133y37 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1212_4 ( .OUT(na1212_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1212_5 ( .OUT(na1212_2), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1212_2_i) ); +// C_AND/D/// x129y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1213_1 ( .OUT(na1213_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1213_2 ( .OUT(na1213_1), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1213_1_i) ); +// C_///AND/D x131y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1214_4 ( .OUT(na1214_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1214_5 ( .OUT(na1214_2), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1214_2_i) ); +// C_AND/D/// x135y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1215_1 ( .OUT(na1215_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1215_2 ( .OUT(na1215_1), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1215_1_i) ); +// C_///AND/D x132y53 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1216_4 ( .OUT(na1216_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1216_5 ( .OUT(na1216_2), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1216_2_i) ); +// C_///AND/D x124y64 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1217_4 ( .OUT(na1217_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1217_5 ( .OUT(na1217_2), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1217_2_i) ); +// C_///AND/D x126y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1218_4 ( .OUT(na1218_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1218_5 ( .OUT(na1218_2), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1218_2_i) ); +// C_AND/D/// x116y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1219_1 ( .OUT(na1219_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1219_2 ( .OUT(na1219_1), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1219_1_i) ); +// C_///AND/D x131y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1220_4 ( .OUT(na1220_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1220_5 ( .OUT(na1220_2), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1220_2_i) ); +// C_AND/D/// x126y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1221_1 ( .OUT(na1221_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1221_2 ( .OUT(na1221_1), .CLK(na2414_1), .EN(na201_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1221_1_i) ); +// C_///AND/D x132y30 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1222_4 ( .OUT(na1222_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1222_5 ( .OUT(na1222_2), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1222_2_i) ); +// C_AND/D/// x130y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1223_1 ( .OUT(na1223_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1223_2 ( .OUT(na1223_1), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1223_1_i) ); +// C_AND/D/// x126y42 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1224_1 ( .OUT(na1224_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1224_2 ( .OUT(na1224_1), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1224_1_i) ); +// C_AND/D/// x138y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1225_1 ( .OUT(na1225_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1225_2 ( .OUT(na1225_1), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1225_1_i) ); +// C_///AND/D x133y50 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1226_4 ( .OUT(na1226_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1226_5 ( .OUT(na1226_2), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1226_2_i) ); +// C_AND/D/// x121y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1227_1 ( .OUT(na1227_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1227_2 ( .OUT(na1227_1), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1227_1_i) ); +// C_///AND/D x121y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1228_4 ( .OUT(na1228_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1228_5 ( .OUT(na1228_2), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1228_2_i) ); +// C_AND/D/// x115y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1229_1 ( .OUT(na1229_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1229_2 ( .OUT(na1229_1), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1229_1_i) ); +// C_///AND/D x132y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1230_4 ( .OUT(na1230_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1230_5 ( .OUT(na1230_2), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1230_2_i) ); +// C_///AND/D x129y83 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1231_4 ( .OUT(na1231_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1231_5 ( .OUT(na1231_2), .CLK(na2414_1), .EN(na202_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1231_2_i) ); +// C_///AND/D x128y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1232_4 ( .OUT(na1232_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1232_5 ( .OUT(na1232_2), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1232_2_i) ); +// C_AND/D/// x129y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1233_1 ( .OUT(na1233_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1233_2 ( .OUT(na1233_1), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1233_1_i) ); +// C_///AND/D x132y40 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1234_4 ( .OUT(na1234_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1234_5 ( .OUT(na1234_2), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1234_2_i) ); +// C_AND/D/// x131y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1235_1 ( .OUT(na1235_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1235_2 ( .OUT(na1235_1), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1235_1_i) ); +// C_///AND/D x132y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1236_4 ( .OUT(na1236_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1236_5 ( .OUT(na1236_2), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1236_2_i) ); +// C_AND/D/// x128y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1237_1 ( .OUT(na1237_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1237_2 ( .OUT(na1237_1), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1237_1_i) ); +// C_AND/D/// x120y67 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1238_1 ( .OUT(na1238_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1238_2 ( .OUT(na1238_1), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1238_1_i) ); +// C_AND/D/// x120y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1239_1 ( .OUT(na1239_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1239_2 ( .OUT(na1239_1), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1239_1_i) ); +// C_///AND/D x129y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1240_4 ( .OUT(na1240_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1240_5 ( .OUT(na1240_2), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1240_2_i) ); +// C_AND/D/// x129y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1241_1 ( .OUT(na1241_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1241_2 ( .OUT(na1241_1), .CLK(na2414_1), .EN(na197_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1241_1_i) ); +// C_///AND/D x147y42 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1242_4 ( .OUT(na1242_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1242_5 ( .OUT(na1242_2), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1242_2_i) ); +// C_AND/D/// x131y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1243_1 ( .OUT(na1243_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1243_2 ( .OUT(na1243_1), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1243_1_i) ); +// C_///AND/D x145y56 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1244_4 ( .OUT(na1244_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1244_5 ( .OUT(na1244_2), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1244_2_i) ); +// C_///AND/D x136y51 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1245_4 ( .OUT(na1245_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1245_5 ( .OUT(na1245_2), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1245_2_i) ); +// C_///AND/D x148y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1246_4 ( .OUT(na1246_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1246_5 ( .OUT(na1246_2), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1246_2_i) ); +// C_AND/D/// x154y54 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1247_1 ( .OUT(na1247_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1247_2 ( .OUT(na1247_1), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1247_1_i) ); +// C_///AND/D x143y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1248_4 ( .OUT(na1248_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1248_5 ( .OUT(na1248_2), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1248_2_i) ); +// C_AND/D/// x148y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1249_1 ( .OUT(na1249_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1249_2 ( .OUT(na1249_1), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1249_1_i) ); +// C_///AND/D x156y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1250_4 ( .OUT(na1250_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1250_5 ( .OUT(na1250_2), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1250_2_i) ); +// C_AND/D/// x143y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1251_1 ( .OUT(na1251_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1251_2 ( .OUT(na1251_1), .CLK(na2414_1), .EN(na220_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1251_1_i) ); +// C_AND/D/// x151y37 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1252_1 ( .OUT(na1252_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1252_2 ( .OUT(na1252_1), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1252_1_i) ); +// C_AND/D/// x130y43 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1253_1 ( .OUT(na1253_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1253_2 ( .OUT(na1253_1), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1253_1_i) ); +// C_///AND/D x148y54 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1254_4 ( .OUT(na1254_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1254_5 ( .OUT(na1254_2), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1254_2_i) ); +// C_AND/D/// x134y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1255_1 ( .OUT(na1255_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1255_2 ( .OUT(na1255_1), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1255_1_i) ); +// C_///AND/D x149y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1256_4 ( .OUT(na1256_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1256_5 ( .OUT(na1256_2), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1256_2_i) ); +// C_AND/D/// x152y57 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1257_1 ( .OUT(na1257_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1257_2 ( .OUT(na1257_1), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1257_1_i) ); +// C_///AND/D x144y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1258_4 ( .OUT(na1258_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1258_5 ( .OUT(na1258_2), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1258_2_i) ); +// C_///AND/D x151y66 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1259_4 ( .OUT(na1259_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1259_5 ( .OUT(na1259_2), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1259_2_i) ); +// C_///AND/D x151y70 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1260_4 ( .OUT(na1260_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1260_5 ( .OUT(na1260_2), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1260_2_i) ); +// C_AND/D/// x146y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1261_1 ( .OUT(na1261_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1261_2 ( .OUT(na1261_1), .CLK(na2414_1), .EN(na206_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1261_1_i) ); +// C_///AND/D x142y44 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1262_4 ( .OUT(na1262_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1262_5 ( .OUT(na1262_2), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1262_2_i) ); +// C_AND/D/// x129y44 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1263_1 ( .OUT(na1263_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1263_2 ( .OUT(na1263_1), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1263_1_i) ); +// C_///AND/D x147y55 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1264_4 ( .OUT(na1264_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1264_5 ( .OUT(na1264_2), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1264_2_i) ); +// C_AND/D/// x135y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1265_1 ( .OUT(na1265_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1265_2 ( .OUT(na1265_1), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1265_1_i) ); +// C_AND/D/// x152y50 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1266_1 ( .OUT(na1266_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1266_2 ( .OUT(na1266_1), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1266_1_i) ); +// C_AND/D/// x155y58 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1267_1 ( .OUT(na1267_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1267_2 ( .OUT(na1267_1), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1267_1_i) ); +// C_///AND/D x143y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1268_4 ( .OUT(na1268_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1268_5 ( .OUT(na1268_2), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1268_2_i) ); +// C_AND/D/// x156y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1269_1 ( .OUT(na1269_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1269_2 ( .OUT(na1269_1), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1269_1_i) ); +// C_///AND/D x152y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1270_4 ( .OUT(na1270_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1270_5 ( .OUT(na1270_2), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1270_2_i) ); +// C_AND/D/// x147y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1271_1 ( .OUT(na1271_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1271_2 ( .OUT(na1271_1), .CLK(na2414_1), .EN(na207_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1271_1_i) ); +// C_///AND/D x144y45 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1272_4 ( .OUT(na1272_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1272_5 ( .OUT(na1272_2), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1272_2_i) ); +// C_///AND/D x133y41 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1273_4 ( .OUT(na1273_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1273_5 ( .OUT(na1273_2), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1273_2_i) ); +// C_///AND/D x151y52 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1274_4 ( .OUT(na1274_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1274_5 ( .OUT(na1274_2), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1274_2_i) ); +// C_AND/D/// x137y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1275_1 ( .OUT(na1275_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1275_2 ( .OUT(na1275_1), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1275_1_i) ); +// C_///AND/D x152y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1276_4 ( .OUT(na1276_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1276_5 ( .OUT(na1276_2), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1276_2_i) ); +// C_AND/D/// x153y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1277_1 ( .OUT(na1277_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1277_2 ( .OUT(na1277_1), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1277_1_i) ); +// C_///AND/D x141y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1278_4 ( .OUT(na1278_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1278_5 ( .OUT(na1278_2), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1278_2_i) ); +// C_AND/D/// x154y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1279_1 ( .OUT(na1279_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1279_2 ( .OUT(na1279_1), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1279_1_i) ); +// C_AND/D/// x154y78 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1280_1 ( .OUT(na1280_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1280_2 ( .OUT(na1280_1), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1280_1_i) ); +// C_AND/D/// x145y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1281_1 ( .OUT(na1281_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1281_2 ( .OUT(na1281_1), .CLK(na2414_1), .EN(na208_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1281_1_i) ); +// C_///AND/D x149y40 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1282_4 ( .OUT(na1282_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1282_5 ( .OUT(na1282_2), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1282_2_i) ); +// C_AND/D/// x134y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1283_1 ( .OUT(na1283_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1283_2 ( .OUT(na1283_1), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1283_1_i) ); +// C_///AND/D x146y55 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1284_4 ( .OUT(na1284_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1284_5 ( .OUT(na1284_2), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1284_2_i) ); +// C_AND/D/// x135y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1285_1 ( .OUT(na1285_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1285_2 ( .OUT(na1285_1), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1285_1_i) ); +// C_///AND/D x154y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1286_4 ( .OUT(na1286_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1286_5 ( .OUT(na1286_2), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1286_2_i) ); +// C_///AND/D x149y63 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1287_4 ( .OUT(na1287_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1287_5 ( .OUT(na1287_2), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1287_2_i) ); +// C_///AND/D x145y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1288_4 ( .OUT(na1288_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1288_5 ( .OUT(na1288_2), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1288_2_i) ); +// C_AND/D/// x150y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1289_1 ( .OUT(na1289_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1289_2 ( .OUT(na1289_1), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1289_1_i) ); +// C_///AND/D x144y84 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1290_4 ( .OUT(na1290_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1290_5 ( .OUT(na1290_2), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1290_2_i) ); +// C_AND/D/// x143y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1291_1 ( .OUT(na1291_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1291_2 ( .OUT(na1291_1), .CLK(na2414_1), .EN(na209_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1291_1_i) ); +// C_///AND/D x149y43 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1292_4 ( .OUT(na1292_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1292_5 ( .OUT(na1292_2), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1292_2_i) ); +// C_AND/D/// x132y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1293_1 ( .OUT(na1293_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1293_2 ( .OUT(na1293_1), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1293_1_i) ); +// C_AND/D/// x150y48 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1294_1 ( .OUT(na1294_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1294_2 ( .OUT(na1294_1), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1294_1_i) ); +// C_AND/D/// x137y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1295_1 ( .OUT(na1295_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1295_2 ( .OUT(na1295_1), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1295_1_i) ); +// C_///AND/D x156y62 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1296_4 ( .OUT(na1296_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1296_5 ( .OUT(na1296_2), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1296_2_i) ); +// C_AND/D/// x151y58 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1297_1 ( .OUT(na1297_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1297_2 ( .OUT(na1297_1), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1297_1_i) ); +// C_///AND/D x147y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1298_4 ( .OUT(na1298_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1298_5 ( .OUT(na1298_2), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1298_2_i) ); +// C_AND/D/// x150y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1299_1 ( .OUT(na1299_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1299_2 ( .OUT(na1299_1), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1299_1_i) ); +// C_///AND/D x146y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1300_4 ( .OUT(na1300_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1300_5 ( .OUT(na1300_2), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1300_2_i) ); +// C_///AND/D x141y80 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1301_4 ( .OUT(na1301_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1301_5 ( .OUT(na1301_2), .CLK(na2414_1), .EN(na210_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1301_2_i) ); +// C_///AND/D x154y42 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1302_4 ( .OUT(na1302_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1302_5 ( .OUT(na1302_2), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1302_2_i) ); +// C_AND/D/// x131y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1303_1 ( .OUT(na1303_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1303_2 ( .OUT(na1303_1), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1303_1_i) ); +// C_///AND/D x145y55 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1304_4 ( .OUT(na1304_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1304_5 ( .OUT(na1304_2), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1304_2_i) ); +// C_AND/D/// x136y52 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1305_1 ( .OUT(na1305_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1305_2 ( .OUT(na1305_1), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1305_1_i) ); +// C_///AND/D x155y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1306_4 ( .OUT(na1306_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1306_5 ( .OUT(na1306_2), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1306_2_i) ); +// C_AND/D/// x154y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1307_1 ( .OUT(na1307_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1307_2 ( .OUT(na1307_1), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1307_1_i) ); +// C_AND/D/// x148y66 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1308_1 ( .OUT(na1308_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1308_2 ( .OUT(na1308_1), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1308_1_i) ); +// C_AND/D/// x147y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1309_1 ( .OUT(na1309_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1309_2 ( .OUT(na1309_1), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1309_1_i) ); +// C_///AND/D x147y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1310_4 ( .OUT(na1310_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1310_5 ( .OUT(na1310_2), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1310_2_i) ); +// C_AND/D/// x140y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1311_1 ( .OUT(na1311_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1311_2 ( .OUT(na1311_1), .CLK(na2414_1), .EN(na211_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1311_1_i) ); +// C_///AND/D x152y45 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1312_4 ( .OUT(na1312_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1312_5 ( .OUT(na1312_2), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1312_2_i) ); +// C_AND/D/// x135y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1313_1 ( .OUT(na1313_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1313_2 ( .OUT(na1313_1), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1313_1_i) ); +// C_///AND/D x147y56 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1314_4 ( .OUT(na1314_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1314_5 ( .OUT(na1314_2), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1314_2_i) ); +// C_///AND/D x132y49 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1315_4 ( .OUT(na1315_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1315_5 ( .OUT(na1315_2), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1315_2_i) ); +// C_///AND/D x155y64 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1316_4 ( .OUT(na1316_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1316_5 ( .OUT(na1316_2), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1316_2_i) ); +// C_AND/D/// x152y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1317_1 ( .OUT(na1317_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1317_2 ( .OUT(na1317_1), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1317_1_i) ); +// C_///AND/D x144y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1318_4 ( .OUT(na1318_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1318_5 ( .OUT(na1318_2), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1318_2_i) ); +// C_AND/D/// x149y76 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1319_1 ( .OUT(na1319_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1319_2 ( .OUT(na1319_1), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1319_1_i) ); +// C_///AND/D x149y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1320_4 ( .OUT(na1320_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1320_5 ( .OUT(na1320_2), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1320_2_i) ); +// C_AND/D/// x142y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1321_1 ( .OUT(na1321_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1321_2 ( .OUT(na1321_1), .CLK(na2414_1), .EN(na212_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1321_1_i) ); +// C_AND/D/// x150y39 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1322_1 ( .OUT(na1322_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1322_2 ( .OUT(na1322_1), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1322_1_i) ); +// C_AND/D/// x134y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1323_1 ( .OUT(na1323_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1323_2 ( .OUT(na1323_1), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1323_1_i) ); +// C_///AND/D x141y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1324_4 ( .OUT(na1324_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1324_5 ( .OUT(na1324_2), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1324_2_i) ); +// C_AND/D/// x137y53 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1325_1 ( .OUT(na1325_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1325_2 ( .OUT(na1325_1), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1325_1_i) ); +// C_///AND/D x150y55 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1326_4 ( .OUT(na1326_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1326_5 ( .OUT(na1326_2), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1326_2_i) ); +// C_AND/D/// x156y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1327_1 ( .OUT(na1327_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1327_2 ( .OUT(na1327_1), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1327_1_i) ); +// C_///AND/D x147y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1328_4 ( .OUT(na1328_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1328_5 ( .OUT(na1328_2), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1328_2_i) ); +// C_///AND/D x153y73 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1329_4 ( .OUT(na1329_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1329_5 ( .OUT(na1329_2), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1329_2_i) ); +// C_///AND/D x155y67 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1330_4 ( .OUT(na1330_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1330_5 ( .OUT(na1330_2), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1330_2_i) ); +// C_AND/D/// x142y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1331_1 ( .OUT(na1331_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1331_2 ( .OUT(na1331_1), .CLK(na2414_1), .EN(na213_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1331_1_i) ); +// C_///AND/D x143y50 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1332_4 ( .OUT(na1332_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1332_5 ( .OUT(na1332_2), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1332_2_i) ); +// C_AND/D/// x130y44 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1333_1 ( .OUT(na1333_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1333_2 ( .OUT(na1333_1), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1333_1_i) ); +// C_///AND/D x152y51 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1334_4 ( .OUT(na1334_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1334_5 ( .OUT(na1334_2), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1334_2_i) ); +// C_AND/D/// x136y53 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1335_1 ( .OUT(na1335_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1335_2 ( .OUT(na1335_1), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1335_1_i) ); +// C_AND/D/// x149y52 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1336_1 ( .OUT(na1336_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1336_2 ( .OUT(na1336_1), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1336_1_i) ); +// C_AND/D/// x154y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1337_1 ( .OUT(na1337_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1337_2 ( .OUT(na1337_1), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1337_1_i) ); +// C_///AND/D x144y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1338_4 ( .OUT(na1338_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1338_5 ( .OUT(na1338_2), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1338_2_i) ); +// C_AND/D/// x153y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1339_1 ( .OUT(na1339_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1339_2 ( .OUT(na1339_1), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1339_1_i) ); +// C_///AND/D x155y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1340_4 ( .OUT(na1340_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1340_5 ( .OUT(na1340_2), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1340_2_i) ); +// C_AND/D/// x148y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1341_1 ( .OUT(na1341_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1341_2 ( .OUT(na1341_1), .CLK(na2414_1), .EN(na204_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1341_1_i) ); +// C_///AND/D x143y47 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1342_4 ( .OUT(na1342_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1342_5 ( .OUT(na1342_2), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1342_2_i) ); +// C_///AND/D x131y42 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1343_4 ( .OUT(na1343_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1343_5 ( .OUT(na1343_2), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1343_2_i) ); +// C_///AND/D x146y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1344_4 ( .OUT(na1344_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1344_5 ( .OUT(na1344_2), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1344_2_i) ); +// C_AND/D/// x136y55 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1345_1 ( .OUT(na1345_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1345_2 ( .OUT(na1345_1), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1345_1_i) ); +// C_///AND/D x149y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1346_4 ( .OUT(na1346_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1346_5 ( .OUT(na1346_2), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1346_2_i) ); +// C_AND/D/// x153y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1347_1 ( .OUT(na1347_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1347_2 ( .OUT(na1347_1), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1347_1_i) ); +// C_///AND/D x148y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1348_4 ( .OUT(na1348_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1348_5 ( .OUT(na1348_2), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1348_2_i) ); +// C_AND/D/// x150y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1349_1 ( .OUT(na1349_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1349_2 ( .OUT(na1349_1), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1349_1_i) ); +// C_AND/D/// x154y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1350_1 ( .OUT(na1350_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1350_2 ( .OUT(na1350_1), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1350_1_i) ); +// C_AND/D/// x143y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1351_1 ( .OUT(na1351_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1351_2 ( .OUT(na1351_1), .CLK(na2414_1), .EN(na215_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1351_1_i) ); +// C_///AND/D x143y46 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1352_4 ( .OUT(na1352_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1352_5 ( .OUT(na1352_2), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1352_2_i) ); +// C_AND/D/// x131y41 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1353_1 ( .OUT(na1353_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1353_2 ( .OUT(na1353_1), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1353_1_i) ); +// C_///AND/D x142y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1354_4 ( .OUT(na1354_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1354_5 ( .OUT(na1354_2), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1354_2_i) ); +// C_AND/D/// x136y56 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1355_1 ( .OUT(na1355_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1355_2 ( .OUT(na1355_1), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1355_1_i) ); +// C_///AND/D x149y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1356_4 ( .OUT(na1356_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1356_5 ( .OUT(na1356_2), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1356_2_i) ); +// C_///AND/D x157y64 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1357_4 ( .OUT(na1357_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1357_5 ( .OUT(na1357_2), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1357_2_i) ); +// C_///AND/D x148y75 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1358_4 ( .OUT(na1358_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1358_5 ( .OUT(na1358_2), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1358_2_i) ); +// C_AND/D/// x150y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1359_1 ( .OUT(na1359_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1359_2 ( .OUT(na1359_1), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1359_1_i) ); +// C_///AND/D x156y68 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1360_4 ( .OUT(na1360_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1360_5 ( .OUT(na1360_2), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1360_2_i) ); +// C_AND/D/// x145y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1361_1 ( .OUT(na1361_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1361_2 ( .OUT(na1361_1), .CLK(na2414_1), .EN(na216_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1361_1_i) ); +// C_///AND/D x142y41 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1362_4 ( .OUT(na1362_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1362_5 ( .OUT(na1362_2), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1362_2_i) ); +// C_AND/D/// x132y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1363_1 ( .OUT(na1363_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1363_2 ( .OUT(na1363_1), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1363_1_i) ); +// C_AND/D/// x150y45 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1364_1 ( .OUT(na1364_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1364_2 ( .OUT(na1364_1), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1364_1_i) ); +// C_AND/D/// x139y52 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1365_1 ( .OUT(na1365_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1365_2 ( .OUT(na1365_1), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1365_1_i) ); +// C_///AND/D x149y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1366_4 ( .OUT(na1366_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1366_5 ( .OUT(na1366_2), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1366_2_i) ); +// C_AND/D/// x155y53 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1367_1 ( .OUT(na1367_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1367_2 ( .OUT(na1367_1), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1367_1_i) ); +// C_///AND/D x144y75 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1368_4 ( .OUT(na1368_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1368_5 ( .OUT(na1368_2), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1368_2_i) ); +// C_AND/D/// x149y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1369_1 ( .OUT(na1369_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1369_2 ( .OUT(na1369_1), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1369_1_i) ); +// C_///AND/D x155y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1370_4 ( .OUT(na1370_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1370_5 ( .OUT(na1370_2), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1370_2_i) ); +// C_///AND/D x138y80 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1371_4 ( .OUT(na1371_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1371_5 ( .OUT(na1371_2), .CLK(na2414_1), .EN(na217_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1371_2_i) ); +// C_///AND/D x146y42 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1372_4 ( .OUT(na1372_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1372_5 ( .OUT(na1372_2), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1372_2_i) ); +// C_AND/D/// x132y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1373_1 ( .OUT(na1373_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1373_2 ( .OUT(na1373_1), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1373_1_i) ); +// C_///AND/D x150y56 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1374_4 ( .OUT(na1374_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1374_5 ( .OUT(na1374_2), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1374_2_i) ); +// C_AND/D/// x139y51 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1375_1 ( .OUT(na1375_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1375_2 ( .OUT(na1375_1), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1375_1_i) ); +// C_///AND/D x149y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1376_4 ( .OUT(na1376_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1376_5 ( .OUT(na1376_2), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1376_2_i) ); +// C_AND/D/// x153y56 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1377_1 ( .OUT(na1377_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1377_2 ( .OUT(na1377_1), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1377_1_i) ); +// C_AND/D/// x146y68 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1378_1 ( .OUT(na1378_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1378_2 ( .OUT(na1378_1), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1378_1_i) ); +// C_AND/D/// x151y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1379_1 ( .OUT(na1379_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1379_2 ( .OUT(na1379_1), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1379_1_i) ); +// C_///AND/D x151y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1380_4 ( .OUT(na1380_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1380_5 ( .OUT(na1380_2), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1380_2_i) ); +// C_AND/D/// x144y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1381_1 ( .OUT(na1381_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1381_2 ( .OUT(na1381_1), .CLK(na2414_1), .EN(na218_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1381_1_i) ); +// C_///AND/D x149y41 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1382_4 ( .OUT(na1382_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1382_5 ( .OUT(na1382_2), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1382_2_i) ); +// C_AND/D/// x135y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1383_1 ( .OUT(na1383_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1383_2 ( .OUT(na1383_1), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1383_1_i) ); +// C_///AND/D x149y55 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1384_4 ( .OUT(na1384_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1384_5 ( .OUT(na1384_2), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1384_2_i) ); +// C_///AND/D x136y48 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1385_4 ( .OUT(na1385_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1385_5 ( .OUT(na1385_2), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1385_2_i) ); +// C_///AND/D x148y51 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1386_4 ( .OUT(na1386_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1386_5 ( .OUT(na1386_2), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1386_2_i) ); +// C_AND/D/// x154y55 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1387_1 ( .OUT(na1387_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1387_2 ( .OUT(na1387_1), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1387_1_i) ); +// C_///AND/D x147y77 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1388_4 ( .OUT(na1388_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1388_5 ( .OUT(na1388_2), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1388_2_i) ); +// C_AND/D/// x150y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1389_1 ( .OUT(na1389_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1389_2 ( .OUT(na1389_1), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1389_1_i) ); +// C_///AND/D x156y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1390_4 ( .OUT(na1390_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1390_5 ( .OUT(na1390_2), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1390_2_i) ); +// C_AND/D/// x147y84 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1391_1 ( .OUT(na1391_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1391_2 ( .OUT(na1391_1), .CLK(na2414_1), .EN(na219_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1391_1_i) ); +// C_AND/D/// x150y40 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1392_1 ( .OUT(na1392_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1392_2 ( .OUT(na1392_1), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1392_1_i) ); +// C_AND/D/// x132y41 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1393_1 ( .OUT(na1393_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1393_2 ( .OUT(na1393_1), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1393_1_i) ); +// C_///AND/D x143y54 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1394_4 ( .OUT(na1394_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1394_5 ( .OUT(na1394_2), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1394_2_i) ); +// C_AND/D/// x137y56 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1395_1 ( .OUT(na1395_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1395_2 ( .OUT(na1395_1), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1395_1_i) ); +// C_///AND/D x148y62 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1396_4 ( .OUT(na1396_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1396_5 ( .OUT(na1396_2), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1396_2_i) ); +// C_AND/D/// x154y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1397_1 ( .OUT(na1397_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1397_2 ( .OUT(na1397_1), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1397_1_i) ); +// C_///AND/D x149y77 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1398_4 ( .OUT(na1398_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1398_5 ( .OUT(na1398_2), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1398_2_i) ); +// C_///AND/D x149y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1399_4 ( .OUT(na1399_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1399_5 ( .OUT(na1399_2), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1399_2_i) ); +// C_///AND/D x155y70 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1400_4 ( .OUT(na1400_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1400_5 ( .OUT(na1400_2), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1400_2_i) ); +// C_AND/D/// x144y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1401_1 ( .OUT(na1401_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1401_2 ( .OUT(na1401_1), .CLK(na2414_1), .EN(na214_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1401_1_i) ); +// C_///AND/D x114y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1402_4 ( .OUT(na1402_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1402_5 ( .OUT(na1402_2), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1402_2_i) ); +// C_AND/D/// x114y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1403_1 ( .OUT(na1403_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1403_2 ( .OUT(na1403_1), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1403_1_i) ); +// C_///AND/D x108y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1404_4 ( .OUT(na1404_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1404_5 ( .OUT(na1404_2), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1404_2_i) ); +// C_AND/D/// x108y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1405_1 ( .OUT(na1405_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1405_2 ( .OUT(na1405_1), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1405_1_i) ); +// C_AND/D/// x105y59 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1406_1 ( .OUT(na1406_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1406_2 ( .OUT(na1406_1), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1406_1_i) ); +// C_AND/D/// x117y58 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1407_1 ( .OUT(na1407_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1407_2 ( .OUT(na1407_1), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1407_1_i) ); +// C_///AND/D x108y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1408_4 ( .OUT(na1408_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1408_5 ( .OUT(na1408_2), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1408_2_i) ); +// C_AND/D/// x106y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1409_1 ( .OUT(na1409_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1409_2 ( .OUT(na1409_1), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1409_1_i) ); +// C_///AND/D x116y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1410_4 ( .OUT(na1410_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1410_5 ( .OUT(na1410_2), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1410_2_i) ); +// C_AND/D/// x123y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1411_1 ( .OUT(na1411_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1411_2 ( .OUT(na1411_1), .CLK(na2414_1), .EN(na237_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1411_1_i) ); +// C_///AND/D x111y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1412_4 ( .OUT(na1412_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1412_5 ( .OUT(na1412_2), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1412_2_i) ); +// C_///AND/D x109y35 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1413_4 ( .OUT(na1413_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1413_5 ( .OUT(na1413_2), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1413_2_i) ); +// C_///AND/D x106y38 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1414_4 ( .OUT(na1414_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1414_5 ( .OUT(na1414_2), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1414_2_i) ); +// C_AND/D/// x110y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1415_1 ( .OUT(na1415_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1415_2 ( .OUT(na1415_1), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1415_1_i) ); +// C_///AND/D x107y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1416_4 ( .OUT(na1416_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1416_5 ( .OUT(na1416_2), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1416_2_i) ); +// C_AND/D/// x114y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1417_1 ( .OUT(na1417_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1417_2 ( .OUT(na1417_1), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1417_1_i) ); +// C_///AND/D x107y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1418_4 ( .OUT(na1418_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1418_5 ( .OUT(na1418_2), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1418_2_i) ); +// C_AND/D/// x106y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1419_1 ( .OUT(na1419_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1419_2 ( .OUT(na1419_1), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1419_1_i) ); +// C_AND/D/// x109y84 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1420_1 ( .OUT(na1420_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1420_2 ( .OUT(na1420_1), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1420_1_i) ); +// C_AND/D/// x120y83 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1421_1 ( .OUT(na1421_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1421_2 ( .OUT(na1421_1), .CLK(na2414_1), .EN(na223_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1421_1_i) ); +// C_///AND/D x112y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1422_4 ( .OUT(na1422_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1422_5 ( .OUT(na1422_2), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1422_2_i) ); +// C_AND/D/// x108y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1423_1 ( .OUT(na1423_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1423_2 ( .OUT(na1423_1), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1423_1_i) ); +// C_///AND/D x107y37 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1424_4 ( .OUT(na1424_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1424_5 ( .OUT(na1424_2), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1424_2_i) ); +// C_AND/D/// x111y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1425_1 ( .OUT(na1425_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1425_2 ( .OUT(na1425_1), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1425_1_i) ); +// C_///AND/D x110y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1426_4 ( .OUT(na1426_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1426_5 ( .OUT(na1426_2), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1426_2_i) ); +// C_///AND/D x121y62 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1427_4 ( .OUT(na1427_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1427_5 ( .OUT(na1427_2), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1427_2_i) ); +// C_///AND/D x112y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1428_4 ( .OUT(na1428_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1428_5 ( .OUT(na1428_2), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1428_2_i) ); +// C_AND/D/// x107y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1429_1 ( .OUT(na1429_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1429_2 ( .OUT(na1429_1), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1429_1_i) ); +// C_///AND/D x108y83 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1430_4 ( .OUT(na1430_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1430_5 ( .OUT(na1430_2), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1430_2_i) ); +// C_AND/D/// x119y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1431_1 ( .OUT(na1431_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1431_2 ( .OUT(na1431_1), .CLK(na2414_1), .EN(na224_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1431_1_i) ); +// C_///AND/D x116y40 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1432_4 ( .OUT(na1432_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1432_5 ( .OUT(na1432_2), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1432_2_i) ); +// C_AND/D/// x110y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1433_1 ( .OUT(na1433_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1433_2 ( .OUT(na1433_1), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1433_1_i) ); +// C_AND/D/// x105y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1434_1 ( .OUT(na1434_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1434_2 ( .OUT(na1434_1), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1434_1_i) ); +// C_AND/D/// x109y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1435_1 ( .OUT(na1435_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1435_2 ( .OUT(na1435_1), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1435_1_i) ); +// C_///AND/D x110y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1436_4 ( .OUT(na1436_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1436_5 ( .OUT(na1436_2), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1436_2_i) ); +// C_AND/D/// x113y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1437_1 ( .OUT(na1437_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1437_2 ( .OUT(na1437_1), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1437_1_i) ); +// C_///AND/D x108y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1438_4 ( .OUT(na1438_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1438_5 ( .OUT(na1438_2), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1438_2_i) ); +// C_AND/D/// x107y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1439_1 ( .OUT(na1439_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1439_2 ( .OUT(na1439_1), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1439_1_i) ); +// C_///AND/D x108y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1440_4 ( .OUT(na1440_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1440_5 ( .OUT(na1440_2), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1440_2_i) ); +// C_///AND/D x129y81 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1441_4 ( .OUT(na1441_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1441_5 ( .OUT(na1441_2), .CLK(na2414_1), .EN(na225_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1441_2_i) ); +// C_///AND/D x111y36 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1442_4 ( .OUT(na1442_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1442_5 ( .OUT(na1442_2), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1442_2_i) ); +// C_AND/D/// x111y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1443_1 ( .OUT(na1443_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1443_2 ( .OUT(na1443_1), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1443_1_i) ); +// C_///AND/D x113y38 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1444_4 ( .OUT(na1444_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1444_5 ( .OUT(na1444_2), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1444_2_i) ); +// C_AND/D/// x110y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1445_1 ( .OUT(na1445_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1445_2 ( .OUT(na1445_1), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1445_1_i) ); +// C_///AND/D x106y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1446_4 ( .OUT(na1446_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1446_5 ( .OUT(na1446_2), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1446_2_i) ); +// C_AND/D/// x119y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1447_1 ( .OUT(na1447_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1447_2 ( .OUT(na1447_1), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1447_1_i) ); +// C_AND/D/// x106y65 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1448_1 ( .OUT(na1448_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1448_2 ( .OUT(na1448_1), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1448_1_i) ); +// C_AND/D/// x105y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1449_1 ( .OUT(na1449_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1449_2 ( .OUT(na1449_1), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1449_1_i) ); +// C_///AND/D x116y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1450_4 ( .OUT(na1450_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1450_5 ( .OUT(na1450_2), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1450_2_i) ); +// C_AND/D/// x121y74 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1451_1 ( .OUT(na1451_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1451_2 ( .OUT(na1451_1), .CLK(na2414_1), .EN(na226_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1451_1_i) ); +// C_///AND/D x111y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1452_4 ( .OUT(na1452_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1452_5 ( .OUT(na1452_2), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1452_2_i) ); +// C_AND/D/// x111y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1453_1 ( .OUT(na1453_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1453_2 ( .OUT(na1453_1), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1453_1_i) ); +// C_///AND/D x107y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1454_4 ( .OUT(na1454_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1454_5 ( .OUT(na1454_2), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1454_2_i) ); +// C_///AND/D x114y49 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1455_4 ( .OUT(na1455_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1455_5 ( .OUT(na1455_2), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1455_2_i) ); +// C_///AND/D x112y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1456_4 ( .OUT(na1456_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1456_5 ( .OUT(na1456_2), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1456_2_i) ); +// C_AND/D/// x117y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1457_1 ( .OUT(na1457_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1457_2 ( .OUT(na1457_1), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1457_1_i) ); +// C_///AND/D x106y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1458_4 ( .OUT(na1458_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1458_5 ( .OUT(na1458_2), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1458_2_i) ); +// C_AND/D/// x109y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1459_1 ( .OUT(na1459_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1459_2 ( .OUT(na1459_1), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1459_1_i) ); +// C_///AND/D x112y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1460_4 ( .OUT(na1460_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1460_5 ( .OUT(na1460_2), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1460_2_i) ); +// C_AND/D/// x121y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1461_1 ( .OUT(na1461_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1461_2 ( .OUT(na1461_1), .CLK(na2414_1), .EN(na227_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1461_1_i) ); +// C_AND/D/// x112y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1462_1 ( .OUT(na1462_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1462_2 ( .OUT(na1462_1), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1462_1_i) ); +// C_AND/D/// x112y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1463_1 ( .OUT(na1463_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1463_2 ( .OUT(na1463_1), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1463_1_i) ); +// C_///AND/D x108y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1464_4 ( .OUT(na1464_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1464_5 ( .OUT(na1464_2), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1464_2_i) ); +// C_AND/D/// x111y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1465_1 ( .OUT(na1465_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1465_2 ( .OUT(na1465_1), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1465_1_i) ); +// C_///AND/D x107y63 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1466_4 ( .OUT(na1466_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1466_5 ( .OUT(na1466_2), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1466_2_i) ); +// C_AND/D/// x120y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1467_1 ( .OUT(na1467_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1467_2 ( .OUT(na1467_1), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1467_1_i) ); +// C_///AND/D x107y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1468_4 ( .OUT(na1468_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1468_5 ( .OUT(na1468_2), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1468_2_i) ); +// C_///AND/D x112y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1469_4 ( .OUT(na1469_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1469_5 ( .OUT(na1469_2), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1469_2_i) ); +// C_///AND/D x113y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1470_4 ( .OUT(na1470_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1470_5 ( .OUT(na1470_2), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1470_2_i) ); +// C_AND/D/// x122y76 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1471_1 ( .OUT(na1471_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1471_2 ( .OUT(na1471_1), .CLK(na2414_1), .EN(na228_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1471_1_i) ); +// C_///AND/D x114y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1472_4 ( .OUT(na1472_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1472_5 ( .OUT(na1472_2), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1472_2_i) ); +// C_AND/D/// x116y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1473_1 ( .OUT(na1473_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1473_2 ( .OUT(na1473_1), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1473_1_i) ); +// C_///AND/D x108y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1474_4 ( .OUT(na1474_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1474_5 ( .OUT(na1474_2), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1474_2_i) ); +// C_AND/D/// x111y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1475_1 ( .OUT(na1475_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1475_2 ( .OUT(na1475_1), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1475_1_i) ); +// C_AND/D/// x105y60 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1476_1 ( .OUT(na1476_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1476_2 ( .OUT(na1476_1), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1476_1_i) ); +// C_AND/D/// x120y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1477_1 ( .OUT(na1477_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1477_2 ( .OUT(na1477_1), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1477_1_i) ); +// C_///AND/D x107y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1478_4 ( .OUT(na1478_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1478_5 ( .OUT(na1478_2), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1478_2_i) ); +// C_AND/D/// x108y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1479_1 ( .OUT(na1479_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1479_2 ( .OUT(na1479_1), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1479_1_i) ); +// C_///AND/D x113y84 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1480_4 ( .OUT(na1480_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1480_5 ( .OUT(na1480_2), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1480_2_i) ); +// C_AND/D/// x124y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1481_1 ( .OUT(na1481_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1481_2 ( .OUT(na1481_1), .CLK(na2414_1), .EN(na229_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1481_1_i) ); +// C_///AND/D x116y36 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1482_4 ( .OUT(na1482_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1482_5 ( .OUT(na1482_2), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1482_2_i) ); +// C_///AND/D x118y40 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1483_4 ( .OUT(na1483_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1483_5 ( .OUT(na1483_2), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1483_2_i) ); +// C_///AND/D x111y41 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1484_4 ( .OUT(na1484_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1484_5 ( .OUT(na1484_2), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1484_2_i) ); +// C_AND/D/// x111y41 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1485_1 ( .OUT(na1485_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1485_2 ( .OUT(na1485_1), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1485_1_i) ); +// C_///AND/D x110y62 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1486_4 ( .OUT(na1486_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1486_5 ( .OUT(na1486_2), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1486_2_i) ); +// C_AND/D/// x114y58 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1487_1 ( .OUT(na1487_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1487_2 ( .OUT(na1487_1), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1487_1_i) ); +// C_///AND/D x112y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1488_4 ( .OUT(na1488_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1488_5 ( .OUT(na1488_2), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1488_2_i) ); +// C_AND/D/// x107y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1489_1 ( .OUT(na1489_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1489_2 ( .OUT(na1489_1), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1489_1_i) ); +// C_AND/D/// x114y81 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1490_1 ( .OUT(na1490_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1490_2 ( .OUT(na1490_1), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1490_1_i) ); +// C_AND/D/// x122y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1491_1 ( .OUT(na1491_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1491_2 ( .OUT(na1491_1), .CLK(na2414_1), .EN(na230_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1491_1_i) ); +// C_///AND/D x109y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1492_4 ( .OUT(na1492_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1492_5 ( .OUT(na1492_2), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1492_2_i) ); +// C_AND/D/// x107y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1493_1 ( .OUT(na1493_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1493_2 ( .OUT(na1493_1), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1493_1_i) ); +// C_///AND/D x106y39 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1494_4 ( .OUT(na1494_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1494_5 ( .OUT(na1494_2), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1494_2_i) ); +// C_AND/D/// x110y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1495_1 ( .OUT(na1495_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1495_2 ( .OUT(na1495_1), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1495_1_i) ); +// C_///AND/D x107y62 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1496_4 ( .OUT(na1496_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1496_5 ( .OUT(na1496_2), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1496_2_i) ); +// C_///AND/D x118y64 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1497_4 ( .OUT(na1497_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1497_5 ( .OUT(na1497_2), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1497_2_i) ); +// C_///AND/D x109y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1498_4 ( .OUT(na1498_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1498_5 ( .OUT(na1498_2), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1498_2_i) ); +// C_AND/D/// x110y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1499_1 ( .OUT(na1499_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1499_2 ( .OUT(na1499_1), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1499_1_i) ); +// C_///AND/D x109y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1500_4 ( .OUT(na1500_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1500_5 ( .OUT(na1500_2), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1500_2_i) ); +// C_AND/D/// x120y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1501_1 ( .OUT(na1501_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1501_2 ( .OUT(na1501_1), .CLK(na2414_1), .EN(na221_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1501_1_i) ); +// C_///AND/D x117y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1502_4 ( .OUT(na1502_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1502_5 ( .OUT(na1502_2), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1502_2_i) ); +// C_AND/D/// x113y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1503_1 ( .OUT(na1503_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1503_2 ( .OUT(na1503_1), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1503_1_i) ); +// C_AND/D/// x108y41 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1504_1 ( .OUT(na1504_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1504_2 ( .OUT(na1504_1), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1504_1_i) ); +// C_AND/D/// x112y41 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1505_1 ( .OUT(na1505_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1505_2 ( .OUT(na1505_1), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1505_1_i) ); +// C_///AND/D x113y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1506_4 ( .OUT(na1506_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1506_5 ( .OUT(na1506_2), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1506_2_i) ); +// C_AND/D/// x115y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1507_1 ( .OUT(na1507_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1507_2 ( .OUT(na1507_1), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1507_1_i) ); +// C_///AND/D x109y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1508_4 ( .OUT(na1508_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1508_5 ( .OUT(na1508_2), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1508_2_i) ); +// C_AND/D/// x108y74 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1509_1 ( .OUT(na1509_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1509_2 ( .OUT(na1509_1), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1509_1_i) ); +// C_///AND/D x119y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1510_4 ( .OUT(na1510_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1510_5 ( .OUT(na1510_2), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1510_2_i) ); +// C_///AND/D x123y80 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1511_4 ( .OUT(na1511_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1511_5 ( .OUT(na1511_2), .CLK(na2414_1), .EN(na232_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1511_2_i) ); +// C_///AND/D x119y37 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1512_4 ( .OUT(na1512_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1512_5 ( .OUT(na1512_2), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1512_2_i) ); +// C_AND/D/// x115y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1513_1 ( .OUT(na1513_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1513_2 ( .OUT(na1513_1), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1513_1_i) ); +// C_///AND/D x110y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1514_4 ( .OUT(na1514_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1514_5 ( .OUT(na1514_2), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1514_2_i) ); +// C_AND/D/// x112y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1515_1 ( .OUT(na1515_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1515_2 ( .OUT(na1515_1), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1515_1_i) ); +// C_///AND/D x113y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1516_4 ( .OUT(na1516_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1516_5 ( .OUT(na1516_2), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1516_2_i) ); +// C_AND/D/// x119y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1517_1 ( .OUT(na1517_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1517_2 ( .OUT(na1517_1), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1517_1_i) ); +// C_AND/D/// x109y66 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1518_1 ( .OUT(na1518_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1518_2 ( .OUT(na1518_1), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1518_1_i) ); +// C_AND/D/// x110y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1519_1 ( .OUT(na1519_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1519_2 ( .OUT(na1519_1), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1519_1_i) ); +// C_///AND/D x119y84 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1520_4 ( .OUT(na1520_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1520_5 ( .OUT(na1520_2), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1520_2_i) ); +// C_AND/D/// x121y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1521_1 ( .OUT(na1521_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1521_2 ( .OUT(na1521_1), .CLK(na2414_1), .EN(na233_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1521_1_i) ); +// C_///AND/D x121y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1522_4 ( .OUT(na1522_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1522_5 ( .OUT(na1522_2), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1522_2_i) ); +// C_AND/D/// x115y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1523_1 ( .OUT(na1523_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1523_2 ( .OUT(na1523_1), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1523_1_i) ); +// C_///AND/D x105y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1524_4 ( .OUT(na1524_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1524_5 ( .OUT(na1524_2), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1524_2_i) ); +// C_///AND/D x109y49 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1525_4 ( .OUT(na1525_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1525_5 ( .OUT(na1525_2), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1525_2_i) ); +// C_///AND/D x108y64 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1526_4 ( .OUT(na1526_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1526_5 ( .OUT(na1526_2), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1526_2_i) ); +// C_AND/D/// x118y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1527_1 ( .OUT(na1527_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1527_2 ( .OUT(na1527_1), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1527_1_i) ); +// C_///AND/D x109y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1528_4 ( .OUT(na1528_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1528_5 ( .OUT(na1528_2), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1528_2_i) ); +// C_AND/D/// x105y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1529_1 ( .OUT(na1529_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1529_2 ( .OUT(na1529_1), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1529_1_i) ); +// C_///AND/D x117y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1530_4 ( .OUT(na1530_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1530_5 ( .OUT(na1530_2), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1530_2_i) ); +// C_AND/D/// x126y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1531_1 ( .OUT(na1531_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1531_2 ( .OUT(na1531_1), .CLK(na2414_1), .EN(na234_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1531_1_i) ); +// C_AND/D/// x117y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1532_1 ( .OUT(na1532_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1532_2 ( .OUT(na1532_1), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1532_1_i) ); +// C_AND/D/// x115y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1533_1 ( .OUT(na1533_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1533_2 ( .OUT(na1533_1), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1533_1_i) ); +// C_///AND/D x107y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1534_4 ( .OUT(na1534_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1534_5 ( .OUT(na1534_2), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1534_2_i) ); +// C_AND/D/// x109y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1535_1 ( .OUT(na1535_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1535_2 ( .OUT(na1535_1), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1535_1_i) ); +// C_///AND/D x112y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1536_4 ( .OUT(na1536_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1536_5 ( .OUT(na1536_2), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1536_2_i) ); +// C_AND/D/// x118y58 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1537_1 ( .OUT(na1537_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1537_2 ( .OUT(na1537_1), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1537_1_i) ); +// C_///AND/D x107y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1538_4 ( .OUT(na1538_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1538_5 ( .OUT(na1538_2), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1538_2_i) ); +// C_///AND/D x109y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1539_4 ( .OUT(na1539_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1539_5 ( .OUT(na1539_2), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1539_2_i) ); +// C_///AND/D x117y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1540_4 ( .OUT(na1540_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1540_5 ( .OUT(na1540_2), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1540_2_i) ); +// C_AND/D/// x124y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1541_1 ( .OUT(na1541_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1541_2 ( .OUT(na1541_1), .CLK(na2414_1), .EN(na235_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1541_1_i) ); +// C_///AND/D x118y41 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1542_4 ( .OUT(na1542_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1542_5 ( .OUT(na1542_2), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1542_2_i) ); +// C_AND/D/// x116y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1543_1 ( .OUT(na1543_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1543_2 ( .OUT(na1543_1), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1543_1_i) ); +// C_///AND/D x106y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1544_4 ( .OUT(na1544_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1544_5 ( .OUT(na1544_2), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1544_2_i) ); +// C_AND/D/// x108y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1545_1 ( .OUT(na1545_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1545_2 ( .OUT(na1545_1), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1545_1_i) ); +// C_AND/D/// x109y60 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1546_1 ( .OUT(na1546_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1546_2 ( .OUT(na1546_1), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1546_1_i) ); +// C_AND/D/// x119y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1547_1 ( .OUT(na1547_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1547_2 ( .OUT(na1547_1), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1547_1_i) ); +// C_///AND/D x104y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1548_4 ( .OUT(na1548_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1548_5 ( .OUT(na1548_2), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1548_2_i) ); +// C_AND/D/// x110y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1549_1 ( .OUT(na1549_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1549_2 ( .OUT(na1549_1), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1549_1_i) ); +// C_///AND/D x122y83 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1550_4 ( .OUT(na1550_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1550_5 ( .OUT(na1550_2), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1550_2_i) ); +// C_AND/D/// x125y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1551_1 ( .OUT(na1551_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1551_2 ( .OUT(na1551_1), .CLK(na2414_1), .EN(na236_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1551_1_i) ); +// C_///AND/D x124y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1552_4 ( .OUT(na1552_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1552_5 ( .OUT(na1552_2), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1552_2_i) ); +// C_///AND/D x114y41 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1553_4 ( .OUT(na1553_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1553_5 ( .OUT(na1553_2), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1553_2_i) ); +// C_///AND/D x107y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1554_4 ( .OUT(na1554_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1554_5 ( .OUT(na1554_2), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1554_2_i) ); +// C_AND/D/// x111y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1555_1 ( .OUT(na1555_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1555_2 ( .OUT(na1555_1), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1555_1_i) ); +// C_///AND/D x108y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1556_4 ( .OUT(na1556_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1556_5 ( .OUT(na1556_2), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1556_2_i) ); +// C_AND/D/// x116y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1557_1 ( .OUT(na1557_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1557_2 ( .OUT(na1557_1), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1557_1_i) ); +// C_///AND/D x112y76 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1558_4 ( .OUT(na1558_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1558_5 ( .OUT(na1558_2), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1558_2_i) ); +// C_AND/D/// x111y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1559_1 ( .OUT(na1559_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1559_2 ( .OUT(na1559_1), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1559_1_i) ); +// C_AND/D/// x114y82 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1560_1 ( .OUT(na1560_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1560_2 ( .OUT(na1560_1), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1560_1_i) ); +// C_AND/D/// x122y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1561_1 ( .OUT(na1561_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1561_2 ( .OUT(na1561_1), .CLK(na2414_1), .EN(na231_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1561_1_i) ); +// C_///AND/D x151y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1562_4 ( .OUT(na1562_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1562_5 ( .OUT(na1562_2), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1562_2_i) ); +// C_AND/D/// x132y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1563_1 ( .OUT(na1563_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1563_2 ( .OUT(na1563_1), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1563_1_i) ); +// C_///AND/D x130y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1564_4 ( .OUT(na1564_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1564_5 ( .OUT(na1564_2), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1564_2_i) ); +// C_AND/D/// x137y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1565_1 ( .OUT(na1565_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1565_2 ( .OUT(na1565_1), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1565_1_i) ); +// C_///AND/D x139y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1566_4 ( .OUT(na1566_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1566_5 ( .OUT(na1566_2), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1566_2_i) ); +// C_///AND/D x133y64 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1567_4 ( .OUT(na1567_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1567_5 ( .OUT(na1567_2), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1567_2_i) ); +// C_///AND/D x130y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1568_4 ( .OUT(na1568_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1568_5 ( .OUT(na1568_2), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1568_2_i) ); +// C_AND/D/// x133y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1569_1 ( .OUT(na1569_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1569_2 ( .OUT(na1569_1), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1569_1_i) ); +// C_///AND/D x136y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1570_4 ( .OUT(na1570_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1570_5 ( .OUT(na1570_2), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1570_2_i) ); +// C_AND/D/// x150y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1571_1 ( .OUT(na1571_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1571_2 ( .OUT(na1571_1), .CLK(na2414_1), .EN(na254_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1571_1_i) ); +// C_///AND/D x149y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1572_4 ( .OUT(na1572_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1572_5 ( .OUT(na1572_2), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1572_2_i) ); +// C_AND/D/// x134y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1573_1 ( .OUT(na1573_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1573_2 ( .OUT(na1573_1), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1573_1_i) ); +// C_AND/D/// x127y43 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1574_1 ( .OUT(na1574_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1574_2 ( .OUT(na1574_1), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1574_1_i) ); +// C_AND/D/// x138y41 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1575_1 ( .OUT(na1575_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1575_2 ( .OUT(na1575_1), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1575_1_i) ); +// C_///AND/D x129y61 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1576_4 ( .OUT(na1576_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1576_5 ( .OUT(na1576_2), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1576_2_i) ); +// C_AND/D/// x135y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1577_1 ( .OUT(na1577_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1577_2 ( .OUT(na1577_1), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1577_1_i) ); +// C_///AND/D x128y78 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1578_4 ( .OUT(na1578_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1578_5 ( .OUT(na1578_2), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1578_2_i) ); +// C_AND/D/// x128y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1579_1 ( .OUT(na1579_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1579_2 ( .OUT(na1579_1), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1579_1_i) ); +// C_///AND/D x133y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1580_4 ( .OUT(na1580_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1580_5 ( .OUT(na1580_2), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1580_2_i) ); +// C_///AND/D x141y82 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1581_4 ( .OUT(na1581_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1581_5 ( .OUT(na1581_2), .CLK(na2414_1), .EN(na240_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1581_2_i) ); +// C_///AND/D x152y30 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1582_4 ( .OUT(na1582_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1582_5 ( .OUT(na1582_2), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1582_2_i) ); +// C_AND/D/// x133y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1583_1 ( .OUT(na1583_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1583_2 ( .OUT(na1583_1), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1583_1_i) ); +// C_///AND/D x128y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1584_4 ( .OUT(na1584_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1584_5 ( .OUT(na1584_2), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1584_2_i) ); +// C_AND/D/// x141y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1585_1 ( .OUT(na1585_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1585_2 ( .OUT(na1585_1), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1585_1_i) ); +// C_///AND/D x130y62 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1586_4 ( .OUT(na1586_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1586_5 ( .OUT(na1586_2), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1586_2_i) ); +// C_AND/D/// x136y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1587_1 ( .OUT(na1587_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1587_2 ( .OUT(na1587_1), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1587_1_i) ); +// C_AND/D/// x127y69 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1588_1 ( .OUT(na1588_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1588_2 ( .OUT(na1588_1), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1588_1_i) ); +// C_AND/D/// x129y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1589_1 ( .OUT(na1589_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1589_2 ( .OUT(na1589_1), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1589_1_i) ); +// C_///AND/D x136y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1590_4 ( .OUT(na1590_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1590_5 ( .OUT(na1590_2), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1590_2_i) ); +// C_AND/D/// x148y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1591_1 ( .OUT(na1591_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1591_2 ( .OUT(na1591_1), .CLK(na2414_1), .EN(na241_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1591_1_i) ); +// C_///AND/D x150y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1592_4 ( .OUT(na1592_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1592_5 ( .OUT(na1592_2), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1592_2_i) ); +// C_AND/D/// x135y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1593_1 ( .OUT(na1593_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1593_2 ( .OUT(na1593_1), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1593_1_i) ); +// C_///AND/D x126y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1594_4 ( .OUT(na1594_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1594_5 ( .OUT(na1594_2), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1594_2_i) ); +// C_///AND/D x133y45 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1595_4 ( .OUT(na1595_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1595_5 ( .OUT(na1595_2), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1595_2_i) ); +// C_///AND/D x128y63 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1596_4 ( .OUT(na1596_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1596_5 ( .OUT(na1596_2), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1596_2_i) ); +// C_AND/D/// x140y56 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1597_1 ( .OUT(na1597_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1597_2 ( .OUT(na1597_1), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1597_1_i) ); +// C_///AND/D x127y76 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1598_4 ( .OUT(na1598_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1598_5 ( .OUT(na1598_2), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1598_2_i) ); +// C_AND/D/// x129y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1599_1 ( .OUT(na1599_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1599_2 ( .OUT(na1599_1), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1599_1_i) ); +// C_///AND/D x134y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1600_4 ( .OUT(na1600_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1600_5 ( .OUT(na1600_2), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1600_2_i) ); +// C_AND/D/// x146y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1601_1 ( .OUT(na1601_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1601_2 ( .OUT(na1601_1), .CLK(na2414_1), .EN(na242_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1601_1_i) ); +// C_AND/D/// x130y31 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1602_1 ( .OUT(na1602_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1602_2 ( .OUT(na1602_1), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1602_1_i) ); +// C_AND/D/// x135y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1603_1 ( .OUT(na1603_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1603_2 ( .OUT(na1603_1), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1603_1_i) ); +// C_///AND/D x128y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1604_4 ( .OUT(na1604_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1604_5 ( .OUT(na1604_2), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1604_2_i) ); +// C_AND/D/// x136y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1605_1 ( .OUT(na1605_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1605_2 ( .OUT(na1605_1), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1605_1_i) ); +// C_///AND/D x133y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1606_4 ( .OUT(na1606_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1606_5 ( .OUT(na1606_2), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1606_2_i) ); +// C_AND/D/// x139y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1607_1 ( .OUT(na1607_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1607_2 ( .OUT(na1607_1), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1607_1_i) ); +// C_///AND/D x119y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1608_4 ( .OUT(na1608_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1608_5 ( .OUT(na1608_2), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1608_2_i) ); +// C_///AND/D x138y69 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1609_4 ( .OUT(na1609_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1609_5 ( .OUT(na1609_2), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1609_2_i) ); +// C_///AND/D x139y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1610_4 ( .OUT(na1610_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1610_5 ( .OUT(na1610_2), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1610_2_i) ); +// C_AND/D/// x141y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1611_1 ( .OUT(na1611_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1611_2 ( .OUT(na1611_1), .CLK(na2414_1), .EN(na243_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1611_1_i) ); +// C_///AND/D x144y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1612_4 ( .OUT(na1612_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1612_5 ( .OUT(na1612_2), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1612_2_i) ); +// C_AND/D/// x135y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1613_1 ( .OUT(na1613_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1613_2 ( .OUT(na1613_1), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1613_1_i) ); +// C_///AND/D x124y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1614_4 ( .OUT(na1614_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1614_5 ( .OUT(na1614_2), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1614_2_i) ); +// C_AND/D/// x138y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1615_1 ( .OUT(na1615_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1615_2 ( .OUT(na1615_1), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1615_1_i) ); +// C_AND/D/// x127y63 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1616_1 ( .OUT(na1616_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1616_2 ( .OUT(na1616_1), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1616_1_i) ); +// C_AND/D/// x139y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1617_1 ( .OUT(na1617_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1617_2 ( .OUT(na1617_1), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1617_1_i) ); +// C_///AND/D x127y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1618_4 ( .OUT(na1618_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1618_5 ( .OUT(na1618_2), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1618_2_i) ); +// C_AND/D/// x132y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1619_1 ( .OUT(na1619_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1619_2 ( .OUT(na1619_1), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1619_1_i) ); +// C_///AND/D x141y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1620_4 ( .OUT(na1620_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1620_5 ( .OUT(na1620_2), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1620_2_i) ); +// C_AND/D/// x139y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1621_1 ( .OUT(na1621_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1621_2 ( .OUT(na1621_1), .CLK(na2414_1), .EN(na244_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1621_1_i) ); +// C_///AND/D x147y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1622_4 ( .OUT(na1622_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1622_5 ( .OUT(na1622_2), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1622_2_i) ); +// C_///AND/D x126y37 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1623_4 ( .OUT(na1623_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1623_5 ( .OUT(na1623_2), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1623_2_i) ); +// C_///AND/D x123y40 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1624_4 ( .OUT(na1624_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1624_5 ( .OUT(na1624_2), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1624_2_i) ); +// C_AND/D/// x137y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1625_1 ( .OUT(na1625_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1625_2 ( .OUT(na1625_1), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1625_1_i) ); +// C_///AND/D x134y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1626_4 ( .OUT(na1626_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1626_5 ( .OUT(na1626_2), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1626_2_i) ); +// C_AND/D/// x138y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1627_1 ( .OUT(na1627_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1627_2 ( .OUT(na1627_1), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1627_1_i) ); +// C_///AND/D x132y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1628_4 ( .OUT(na1628_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1628_5 ( .OUT(na1628_2), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1628_2_i) ); +// C_AND/D/// x129y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1629_1 ( .OUT(na1629_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1629_2 ( .OUT(na1629_1), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1629_1_i) ); +// C_AND/D/// x138y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1630_1 ( .OUT(na1630_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1630_2 ( .OUT(na1630_1), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1630_1_i) ); +// C_AND/D/// x144y83 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1631_1 ( .OUT(na1631_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1631_2 ( .OUT(na1631_1), .CLK(na2414_1), .EN(na245_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1631_1_i) ); +// C_///AND/D x133y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1632_4 ( .OUT(na1632_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1632_5 ( .OUT(na1632_2), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1632_2_i) ); +// C_AND/D/// x138y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1633_1 ( .OUT(na1633_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1633_2 ( .OUT(na1633_1), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1633_1_i) ); +// C_///AND/D x125y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1634_4 ( .OUT(na1634_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1634_5 ( .OUT(na1634_2), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1634_2_i) ); +// C_AND/D/// x139y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1635_1 ( .OUT(na1635_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1635_2 ( .OUT(na1635_1), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1635_1_i) ); +// C_///AND/D x132y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1636_4 ( .OUT(na1636_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1636_5 ( .OUT(na1636_2), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1636_2_i) ); +// C_///AND/D x132y62 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1637_4 ( .OUT(na1637_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1637_5 ( .OUT(na1637_2), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1637_2_i) ); +// C_///AND/D x126y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1638_4 ( .OUT(na1638_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1638_5 ( .OUT(na1638_2), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1638_2_i) ); +// C_AND/D/// x131y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1639_1 ( .OUT(na1639_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1639_2 ( .OUT(na1639_1), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1639_1_i) ); +// C_///AND/D x138y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1640_4 ( .OUT(na1640_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1640_5 ( .OUT(na1640_2), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1640_2_i) ); +// C_AND/D/// x144y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1641_1 ( .OUT(na1641_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1641_2 ( .OUT(na1641_1), .CLK(na2414_1), .EN(na246_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1641_1_i) ); +// C_///AND/D x153y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1642_4 ( .OUT(na1642_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1642_5 ( .OUT(na1642_2), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1642_2_i) ); +// C_AND/D/// x138y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1643_1 ( .OUT(na1643_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1643_2 ( .OUT(na1643_1), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1643_1_i) ); +// C_AND/D/// x126y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1644_1 ( .OUT(na1644_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1644_2 ( .OUT(na1644_1), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1644_1_i) ); +// C_AND/D/// x140y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1645_1 ( .OUT(na1645_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1645_2 ( .OUT(na1645_1), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1645_1_i) ); +// C_///AND/D x141y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1646_4 ( .OUT(na1646_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1646_5 ( .OUT(na1646_2), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1646_2_i) ); +// C_AND/D/// x136y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1647_1 ( .OUT(na1647_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1647_2 ( .OUT(na1647_1), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1647_1_i) ); +// C_///AND/D x129y74 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1648_4 ( .OUT(na1648_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1648_5 ( .OUT(na1648_2), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1648_2_i) ); +// C_AND/D/// x134y73 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1649_1 ( .OUT(na1649_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1649_2 ( .OUT(na1649_1), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1649_1_i) ); +// C_///AND/D x134y77 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1650_4 ( .OUT(na1650_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1650_5 ( .OUT(na1650_2), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1650_2_i) ); +// C_///AND/D x142y84 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1651_4 ( .OUT(na1651_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1651_5 ( .OUT(na1651_2), .CLK(na2414_1), .EN(na247_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1651_2_i) ); +// C_///AND/D x149y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1652_4 ( .OUT(na1652_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1652_5 ( .OUT(na1652_2), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1652_2_i) ); +// C_AND/D/// x134y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1653_1 ( .OUT(na1653_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1653_2 ( .OUT(na1653_1), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1653_1_i) ); +// C_///AND/D x127y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1654_4 ( .OUT(na1654_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1654_5 ( .OUT(na1654_2), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1654_2_i) ); +// C_AND/D/// x140y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1655_1 ( .OUT(na1655_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1655_2 ( .OUT(na1655_1), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1655_1_i) ); +// C_///AND/D x131y64 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1656_4 ( .OUT(na1656_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1656_5 ( .OUT(na1656_2), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1656_2_i) ); +// C_AND/D/// x139y57 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1657_1 ( .OUT(na1657_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1657_2 ( .OUT(na1657_1), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1657_1_i) ); +// C_AND/D/// x128y71 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1658_1 ( .OUT(na1658_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1658_2 ( .OUT(na1658_1), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1658_1_i) ); +// C_AND/D/// x130y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1659_1 ( .OUT(na1659_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1659_2 ( .OUT(na1659_1), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1659_1_i) ); +// C_///AND/D x137y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1660_4 ( .OUT(na1660_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1660_5 ( .OUT(na1660_2), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1660_2_i) ); +// C_AND/D/// x147y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1661_1 ( .OUT(na1661_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1661_2 ( .OUT(na1661_1), .CLK(na2414_1), .EN(na238_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1661_1_i) ); +// C_///AND/D x156y31 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1662_4 ( .OUT(na1662_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1662_5 ( .OUT(na1662_2), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1662_2_i) ); +// C_AND/D/// x137y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1663_1 ( .OUT(na1663_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1663_2 ( .OUT(na1663_1), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1663_1_i) ); +// C_///AND/D x129y42 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1664_4 ( .OUT(na1664_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1664_5 ( .OUT(na1664_2), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1664_2_i) ); +// C_///AND/D x131y48 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1665_4 ( .OUT(na1665_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1665_5 ( .OUT(na1665_2), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1665_2_i) ); +// C_///AND/D x138y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1666_4 ( .OUT(na1666_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1666_5 ( .OUT(na1666_2), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1666_2_i) ); +// C_AND/D/// x139y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1667_1 ( .OUT(na1667_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1667_2 ( .OUT(na1667_1), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1667_1_i) ); +// C_///AND/D x124y80 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1668_4 ( .OUT(na1668_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1668_5 ( .OUT(na1668_2), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1668_2_i) ); +// C_AND/D/// x135y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1669_1 ( .OUT(na1669_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1669_2 ( .OUT(na1669_1), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1669_1_i) ); +// C_///AND/D x137y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1670_4 ( .OUT(na1670_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1670_5 ( .OUT(na1670_2), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1670_2_i) ); +// C_AND/D/// x153y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1671_1 ( .OUT(na1671_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1671_2 ( .OUT(na1671_1), .CLK(na2414_1), .EN(na249_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1671_1_i) ); +// C_AND/D/// x138y32 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1672_1 ( .OUT(na1672_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1672_2 ( .OUT(na1672_1), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1672_1_i) ); +// C_AND/D/// x139y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1673_1 ( .OUT(na1673_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1673_2 ( .OUT(na1673_1), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1673_1_i) ); +// C_///AND/D x123y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1674_4 ( .OUT(na1674_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1674_5 ( .OUT(na1674_2), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1674_2_i) ); +// C_AND/D/// x137y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1675_1 ( .OUT(na1675_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1675_2 ( .OUT(na1675_1), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1675_1_i) ); +// C_///AND/D x138y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1676_4 ( .OUT(na1676_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1676_5 ( .OUT(na1676_2), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1676_2_i) ); +// C_AND/D/// x137y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1677_1 ( .OUT(na1677_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1677_2 ( .OUT(na1677_1), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1677_1_i) ); +// C_///AND/D x128y79 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1678_4 ( .OUT(na1678_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1678_5 ( .OUT(na1678_2), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1678_2_i) ); +// C_///AND/D x137y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1679_4 ( .OUT(na1679_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1679_5 ( .OUT(na1679_2), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1679_2_i) ); +// C_///AND/D x137y78 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1680_4 ( .OUT(na1680_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1680_5 ( .OUT(na1680_2), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1680_2_i) ); +// C_AND/D/// x155y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1681_1 ( .OUT(na1681_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1681_2 ( .OUT(na1681_1), .CLK(na2414_1), .EN(na250_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1681_1_i) ); +// C_///AND/D x138y36 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1682_4 ( .OUT(na1682_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1682_5 ( .OUT(na1682_2), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1682_2_i) ); +// C_AND/D/// x135y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1683_1 ( .OUT(na1683_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1683_2 ( .OUT(na1683_1), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1683_1_i) ); +// C_///AND/D x129y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1684_4 ( .OUT(na1684_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1684_5 ( .OUT(na1684_2), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1684_2_i) ); +// C_AND/D/// x140y50 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1685_1 ( .OUT(na1685_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1685_2 ( .OUT(na1685_1), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1685_1_i) ); +// C_AND/D/// x132y64 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1686_1 ( .OUT(na1686_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1686_2 ( .OUT(na1686_1), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1686_1_i) ); +// C_AND/D/// x140y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1687_1 ( .OUT(na1687_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1687_2 ( .OUT(na1687_1), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1687_1_i) ); +// C_///AND/D x127y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1688_4 ( .OUT(na1688_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1688_5 ( .OUT(na1688_2), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1688_2_i) ); +// C_AND/D/// x138y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1689_1 ( .OUT(na1689_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1689_2 ( .OUT(na1689_1), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1689_1_i) ); +// C_///AND/D x133y84 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1690_4 ( .OUT(na1690_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1690_5 ( .OUT(na1690_2), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1690_2_i) ); +// C_AND/D/// x151y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1691_1 ( .OUT(na1691_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1691_2 ( .OUT(na1691_1), .CLK(na2414_1), .EN(na251_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1691_1_i) ); +// C_///AND/D x136y33 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1692_4 ( .OUT(na1692_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1692_5 ( .OUT(na1692_2), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1692_2_i) ); +// C_///AND/D x133y40 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1693_4 ( .OUT(na1693_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1693_5 ( .OUT(na1693_2), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1693_2_i) ); +// C_///AND/D x131y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1694_4 ( .OUT(na1694_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1694_5 ( .OUT(na1694_2), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1694_2_i) ); +// C_AND/D/// x140y49 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1695_1 ( .OUT(na1695_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1695_2 ( .OUT(na1695_1), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1695_1_i) ); +// C_///AND/D x138y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1696_4 ( .OUT(na1696_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1696_5 ( .OUT(na1696_2), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1696_2_i) ); +// C_AND/D/// x140y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1697_1 ( .OUT(na1697_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1697_2 ( .OUT(na1697_1), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1697_1_i) ); +// C_///AND/D x131y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1698_4 ( .OUT(na1698_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1698_5 ( .OUT(na1698_2), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1698_2_i) ); +// C_AND/D/// x134y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1699_1 ( .OUT(na1699_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1699_2 ( .OUT(na1699_1), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1699_1_i) ); +// C_AND/D/// x135y75 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1700_1 ( .OUT(na1700_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1700_2 ( .OUT(na1700_1), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1700_1_i) ); +// C_AND/D/// x149y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1701_1 ( .OUT(na1701_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1701_2 ( .OUT(na1701_1), .CLK(na2414_1), .EN(na252_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1701_1_i) ); +// C_///AND/D x135y34 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1702_4 ( .OUT(na1702_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1702_5 ( .OUT(na1702_2), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1702_2_i) ); +// C_AND/D/// x138y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1703_1 ( .OUT(na1703_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1703_2 ( .OUT(na1703_1), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1703_1_i) ); +// C_///AND/D x132y47 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1704_4 ( .OUT(na1704_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1704_5 ( .OUT(na1704_2), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1704_2_i) ); +// C_AND/D/// x137y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1705_1 ( .OUT(na1705_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1705_2 ( .OUT(na1705_1), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1705_1_i) ); +// C_///AND/D x135y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1706_4 ( .OUT(na1706_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1706_5 ( .OUT(na1706_2), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1706_2_i) ); +// C_///AND/D x133y63 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1707_4 ( .OUT(na1707_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1707_5 ( .OUT(na1707_2), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1707_2_i) ); +// C_///AND/D x132y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1708_4 ( .OUT(na1708_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1708_5 ( .OUT(na1708_2), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1708_2_i) ); +// C_AND/D/// x135y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1709_1 ( .OUT(na1709_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1709_2 ( .OUT(na1709_1), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1709_1_i) ); +// C_///AND/D x138y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1710_4 ( .OUT(na1710_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1710_5 ( .OUT(na1710_2), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1710_2_i) ); +// C_AND/D/// x152y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1711_1 ( .OUT(na1711_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1711_2 ( .OUT(na1711_1), .CLK(na2414_1), .EN(na253_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1711_1_i) ); +// C_///AND/D x155y32 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1712_4 ( .OUT(na1712_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1712_5 ( .OUT(na1712_2), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1712_2_i) ); +// C_AND/D/// x140y35 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1713_1 ( .OUT(na1713_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1713_2 ( .OUT(na1713_1), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1713_1_i) ); +// C_AND/D/// x126y43 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1714_1 ( .OUT(na1714_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1714_2 ( .OUT(na1714_1), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1714_1_i) ); +// C_AND/D/// x138y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1715_1 ( .OUT(na1715_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1715_2 ( .OUT(na1715_1), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1715_1_i) ); +// C_///AND/D x137y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1716_4 ( .OUT(na1716_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1716_5 ( .OUT(na1716_2), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1716_2_i) ); +// C_AND/D/// x138y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1717_1 ( .OUT(na1717_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1717_2 ( .OUT(na1717_1), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1717_1_i) ); +// C_///AND/D x131y75 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1718_4 ( .OUT(na1718_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1718_5 ( .OUT(na1718_2), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1718_2_i) ); +// C_AND/D/// x134y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1719_1 ( .OUT(na1719_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1719_2 ( .OUT(na1719_1), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1719_1_i) ); +// C_///AND/D x138y76 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1720_4 ( .OUT(na1720_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1720_5 ( .OUT(na1720_2), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1720_2_i) ); +// C_///AND/D x142y83 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1721_4 ( .OUT(na1721_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1721_5 ( .OUT(na1721_2), .CLK(na2414_1), .EN(na248_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1721_2_i) ); +// C_///AND/D x156y36 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1722_4 ( .OUT(na1722_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1722_5 ( .OUT(na1722_2), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1722_2_i) ); +// C_AND/D/// x140y36 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1723_1 ( .OUT(na1723_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1723_2 ( .OUT(na1723_1), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1723_1_i) ); +// C_///AND/D x146y48 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1724_4 ( .OUT(na1724_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1724_5 ( .OUT(na1724_2), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1724_2_i) ); +// C_AND/D/// x145y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1725_1 ( .OUT(na1725_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1725_2 ( .OUT(na1725_1), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1725_1_i) ); +// C_///AND/D x154y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1726_4 ( .OUT(na1726_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1726_5 ( .OUT(na1726_2), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1726_2_i) ); +// C_AND/D/// x153y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1727_1 ( .OUT(na1727_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1727_2 ( .OUT(na1727_1), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1727_1_i) ); +// C_AND/D/// x150y67 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1728_1 ( .OUT(na1728_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1728_2 ( .OUT(na1728_1), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1728_1_i) ); +// C_AND/D/// x156y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1729_1 ( .OUT(na1729_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1729_2 ( .OUT(na1729_1), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1729_1_i) ); +// C_///AND/D x156y79 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1730_4 ( .OUT(na1730_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1730_5 ( .OUT(na1730_2), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1730_2_i) ); +// C_AND/D/// x140y81 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1731_1 ( .OUT(na1731_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1731_2 ( .OUT(na1731_1), .CLK(na2414_1), .EN(na271_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1731_1_i) ); +// C_///AND/D x151y40 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1732_4 ( .OUT(na1732_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1732_5 ( .OUT(na1732_2), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1732_2_i) ); +// C_AND/D/// x143y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1733_1 ( .OUT(na1733_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1733_2 ( .OUT(na1733_1), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1733_1_i) ); +// C_///AND/D x147y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1734_4 ( .OUT(na1734_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1734_5 ( .OUT(na1734_2), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1734_2_i) ); +// C_///AND/D x132y46 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1735_4 ( .OUT(na1735_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1735_5 ( .OUT(na1735_2), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1735_2_i) ); +// C_///AND/D x151y54 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1736_4 ( .OUT(na1736_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1736_5 ( .OUT(na1736_2), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1736_2_i) ); +// C_AND/D/// x151y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1737_1 ( .OUT(na1737_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1737_2 ( .OUT(na1737_1), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1737_1_i) ); +// C_///AND/D x144y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1738_4 ( .OUT(na1738_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1738_5 ( .OUT(na1738_2), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1738_2_i) ); +// C_AND/D/// x149y66 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1739_1 ( .OUT(na1739_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1739_2 ( .OUT(na1739_1), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1739_1_i) ); +// C_///AND/D x153y69 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1740_4 ( .OUT(na1740_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1740_5 ( .OUT(na1740_2), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1740_2_i) ); +// C_AND/D/// x138y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1741_1 ( .OUT(na1741_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1741_2 ( .OUT(na1741_1), .CLK(na2414_1), .EN(na257_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1741_1_i) ); +// C_AND/D/// x154y35 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1742_1 ( .OUT(na1742_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1742_2 ( .OUT(na1742_1), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1742_1_i) ); +// C_AND/D/// x144y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1743_1 ( .OUT(na1743_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1743_2 ( .OUT(na1743_1), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1743_1_i) ); +// C_///AND/D x144y47 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1744_4 ( .OUT(na1744_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1744_5 ( .OUT(na1744_2), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1744_2_i) ); +// C_AND/D/// x141y41 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1745_1 ( .OUT(na1745_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1745_2 ( .OUT(na1745_1), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1745_1_i) ); +// C_///AND/D x152y53 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1746_4 ( .OUT(na1746_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1746_5 ( .OUT(na1746_2), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1746_2_i) ); +// C_AND/D/// x148y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1747_1 ( .OUT(na1747_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1747_2 ( .OUT(na1747_1), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1747_1_i) ); +// C_///AND/D x147y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1748_4 ( .OUT(na1748_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1748_5 ( .OUT(na1748_2), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1748_2_i) ); +// C_///AND/D x156y65 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1749_4 ( .OUT(na1749_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1749_5 ( .OUT(na1749_2), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1749_2_i) ); +// C_///AND/D x156y72 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1750_4 ( .OUT(na1750_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1750_5 ( .OUT(na1750_2), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1750_2_i) ); +// C_AND/D/// x139y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1751_1 ( .OUT(na1751_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1751_2 ( .OUT(na1751_1), .CLK(na2414_1), .EN(na258_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1751_1_i) ); +// C_///AND/D x150y42 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1752_4 ( .OUT(na1752_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1752_5 ( .OUT(na1752_2), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1752_2_i) ); +// C_AND/D/// x140y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1753_1 ( .OUT(na1753_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1753_2 ( .OUT(na1753_1), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1753_1_i) ); +// C_///AND/D x146y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1754_4 ( .OUT(na1754_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1754_5 ( .OUT(na1754_2), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1754_2_i) ); +// C_AND/D/// x143y42 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1755_1 ( .OUT(na1755_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1755_2 ( .OUT(na1755_1), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1755_1_i) ); +// C_AND/D/// x154y46 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1756_1 ( .OUT(na1756_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1756_2 ( .OUT(na1756_1), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1756_1_i) ); +// C_AND/D/// x150y59 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1757_1 ( .OUT(na1757_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1757_2 ( .OUT(na1757_1), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1757_1_i) ); +// C_///AND/D x143y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1758_4 ( .OUT(na1758_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1758_5 ( .OUT(na1758_2), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1758_2_i) ); +// C_AND/D/// x152y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1759_1 ( .OUT(na1759_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1759_2 ( .OUT(na1759_1), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1759_1_i) ); +// C_///AND/D x156y71 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1760_4 ( .OUT(na1760_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1760_5 ( .OUT(na1760_2), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1760_2_i) ); +// C_AND/D/// x141y79 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1761_1 ( .OUT(na1761_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1761_2 ( .OUT(na1761_1), .CLK(na2414_1), .EN(na259_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1761_1_i) ); +// C_///AND/D x153y39 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1762_4 ( .OUT(na1762_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1762_5 ( .OUT(na1762_2), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1762_2_i) ); +// C_///AND/D x137y39 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1763_4 ( .OUT(na1763_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1763_5 ( .OUT(na1763_2), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1763_2_i) ); +// C_///AND/D x142y40 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1764_4 ( .OUT(na1764_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1764_5 ( .OUT(na1764_2), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1764_2_i) ); +// C_AND/D/// x141y46 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1765_1 ( .OUT(na1765_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1765_2 ( .OUT(na1765_1), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1765_1_i) ); +// C_///AND/D x153y55 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1766_4 ( .OUT(na1766_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1766_5 ( .OUT(na1766_2), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1766_2_i) ); +// C_AND/D/// x151y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1767_1 ( .OUT(na1767_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1767_2 ( .OUT(na1767_1), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1767_1_i) ); +// C_///AND/D x148y65 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1768_4 ( .OUT(na1768_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1768_5 ( .OUT(na1768_2), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1768_2_i) ); +// C_AND/D/// x153y65 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1769_1 ( .OUT(na1769_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1769_2 ( .OUT(na1769_1), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1769_1_i) ); +// C_AND/D/// x153y79 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1770_1 ( .OUT(na1770_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1770_2 ( .OUT(na1770_1), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1770_1_i) ); +// C_AND/D/// x139y73 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1771_1 ( .OUT(na1771_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1771_2 ( .OUT(na1771_1), .CLK(na2414_1), .EN(na260_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1771_1_i) ); +// C_///AND/D x155y40 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1772_4 ( .OUT(na1772_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1772_5 ( .OUT(na1772_2), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1772_2_i) ); +// C_AND/D/// x137y40 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1773_1 ( .OUT(na1773_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1773_2 ( .OUT(na1773_1), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1773_1_i) ); +// C_///AND/D x144y41 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1774_4 ( .OUT(na1774_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1774_5 ( .OUT(na1774_2), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1774_2_i) ); +// C_AND/D/// x143y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1775_1 ( .OUT(na1775_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1775_2 ( .OUT(na1775_1), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1775_1_i) ); +// C_///AND/D x155y56 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1776_4 ( .OUT(na1776_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1776_5 ( .OUT(na1776_2), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1776_2_i) ); +// C_///AND/D x147y66 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1777_4 ( .OUT(na1777_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1777_5 ( .OUT(na1777_2), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1777_2_i) ); +// C_///AND/D x152y66 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1778_4 ( .OUT(na1778_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1778_5 ( .OUT(na1778_2), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1778_2_i) ); +// C_AND/D/// x153y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1779_1 ( .OUT(na1779_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1779_2 ( .OUT(na1779_1), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1779_1_i) ); +// C_///AND/D x155y80 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1780_4 ( .OUT(na1780_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1780_5 ( .OUT(na1780_2), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1780_2_i) ); +// C_AND/D/// x141y74 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1781_1 ( .OUT(na1781_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1781_2 ( .OUT(na1781_1), .CLK(na2414_1), .EN(na261_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1781_1_i) ); +// C_///AND/D x156y43 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1782_4 ( .OUT(na1782_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1782_5 ( .OUT(na1782_2), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1782_2_i) ); +// C_AND/D/// x140y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1783_1 ( .OUT(na1783_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1783_2 ( .OUT(na1783_1), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1783_1_i) ); +// C_AND/D/// x153y38 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1784_1 ( .OUT(na1784_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1784_2 ( .OUT(na1784_1), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1784_1_i) ); +// C_AND/D/// x140y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1785_1 ( .OUT(na1785_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1785_2 ( .OUT(na1785_1), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1785_1_i) ); +// C_///AND/D x156y57 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1786_4 ( .OUT(na1786_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1786_5 ( .OUT(na1786_2), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1786_2_i) ); +// C_AND/D/// x152y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1787_1 ( .OUT(na1787_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1787_2 ( .OUT(na1787_1), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1787_1_i) ); +// C_///AND/D x149y67 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1788_4 ( .OUT(na1788_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1788_5 ( .OUT(na1788_2), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1788_2_i) ); +// C_AND/D/// x154y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1789_1 ( .OUT(na1789_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1789_2 ( .OUT(na1789_1), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1789_1_i) ); +// C_///AND/D x148y83 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1790_4 ( .OUT(na1790_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1790_5 ( .OUT(na1790_2), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1790_2_i) ); +// C_///AND/D x136y83 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1791_4 ( .OUT(na1791_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1791_5 ( .OUT(na1791_2), .CLK(na2414_1), .EN(na262_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1791_2_i) ); +// C_///AND/D x156y44 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1792_4 ( .OUT(na1792_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1792_5 ( .OUT(na1792_2), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1792_2_i) ); +// C_AND/D/// x140y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1793_1 ( .OUT(na1793_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1793_2 ( .OUT(na1793_1), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1793_1_i) ); +// C_///AND/D x147y43 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1794_4 ( .OUT(na1794_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1794_5 ( .OUT(na1794_2), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1794_2_i) ); +// C_AND/D/// x146y45 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1795_1 ( .OUT(na1795_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1795_2 ( .OUT(na1795_1), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1795_1_i) ); +// C_///AND/D x152y58 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1796_4 ( .OUT(na1796_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1796_5 ( .OUT(na1796_2), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1796_2_i) ); +// C_AND/D/// x152y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1797_1 ( .OUT(na1797_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1797_2 ( .OUT(na1797_1), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1797_1_i) ); +// C_AND/D/// x149y64 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1798_1 ( .OUT(na1798_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1798_2 ( .OUT(na1798_1), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1798_1_i) ); +// C_AND/D/// x154y68 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1799_1 ( .OUT(na1799_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1799_2 ( .OUT(na1799_1), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1799_1_i) ); +// C_///AND/D x152y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1800_4 ( .OUT(na1800_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1800_5 ( .OUT(na1800_2), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1800_2_i) ); +// C_AND/D/// x140y76 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1801_1 ( .OUT(na1801_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1801_2 ( .OUT(na1801_1), .CLK(na2414_1), .EN(na263_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1801_1_i) ); +// C_///AND/D x152y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1802_4 ( .OUT(na1802_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1802_5 ( .OUT(na1802_2), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1802_2_i) ); +// C_AND/D/// x140y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1803_1 ( .OUT(na1803_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1803_2 ( .OUT(na1803_1), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1803_1_i) ); +// C_///AND/D x146y44 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1804_4 ( .OUT(na1804_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1804_5 ( .OUT(na1804_2), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1804_2_i) ); +// C_///AND/D x132y43 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1805_4 ( .OUT(na1805_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1805_5 ( .OUT(na1805_2), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1805_2_i) ); +// C_///AND/D x151y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1806_4 ( .OUT(na1806_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1806_5 ( .OUT(na1806_2), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1806_2_i) ); +// C_AND/D/// x150y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1807_1 ( .OUT(na1807_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1807_2 ( .OUT(na1807_1), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1807_1_i) ); +// C_///AND/D x148y68 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1808_4 ( .OUT(na1808_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1808_5 ( .OUT(na1808_2), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1808_2_i) ); +// C_AND/D/// x151y69 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1809_1 ( .OUT(na1809_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1809_2 ( .OUT(na1809_1), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1809_1_i) ); +// C_///AND/D x153y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1810_4 ( .OUT(na1810_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1810_5 ( .OUT(na1810_2), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1810_2_i) ); +// C_AND/D/// x137y75 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1811_1 ( .OUT(na1811_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1811_2 ( .OUT(na1811_1), .CLK(na2414_1), .EN(na264_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1811_1_i) ); +// C_AND/D/// x153y35 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1812_1 ( .OUT(na1812_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2401_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1812_2 ( .OUT(na1812_1), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1812_1_i) ); +// C_AND/D/// x141y39 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1813_1 ( .OUT(na1813_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1813_2 ( .OUT(na1813_1), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1813_1_i) ); +// C_///AND/D x147y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1814_4 ( .OUT(na1814_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1814_5 ( .OUT(na1814_2), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1814_2_i) ); +// C_AND/D/// x142y43 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1815_1 ( .OUT(na1815_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1815_2 ( .OUT(na1815_1), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1815_1_i) ); +// C_///AND/D x153y53 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1816_4 ( .OUT(na1816_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1816_5 ( .OUT(na1816_2), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1816_2_i) ); +// C_AND/D/// x149y60 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1817_1 ( .OUT(na1817_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1817_2 ( .OUT(na1817_1), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1817_1_i) ); +// C_///AND/D x146y70 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1818_4 ( .OUT(na1818_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1818_5 ( .OUT(na1818_2), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1818_2_i) ); +// C_///AND/D x155y65 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1819_4 ( .OUT(na1819_2_i), .IN1(na2408_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1819_5 ( .OUT(na1819_2), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1819_2_i) ); +// C_///AND/D x155y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1820_4 ( .OUT(na1820_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1820_5 ( .OUT(na1820_2), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1820_2_i) ); +// C_AND/D/// x140y80 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1821_1 ( .OUT(na1821_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1821_2 ( .OUT(na1821_1), .CLK(na2414_1), .EN(na255_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1821_1_i) ); +// C_///AND/D x149y37 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1822_4 ( .OUT(na1822_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1822_5 ( .OUT(na1822_2), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1822_2_i) ); +// C_AND/D/// x141y33 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1823_1 ( .OUT(na1823_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1823_2 ( .OUT(na1823_1), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1823_1_i) ); +// C_///AND/D x149y46 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1824_4 ( .OUT(na1824_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1824_5 ( .OUT(na1824_2), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1824_2_i) ); +// C_AND/D/// x145y41 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1825_1 ( .OUT(na1825_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1825_2 ( .OUT(na1825_1), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1825_1_i) ); +// C_AND/D/// x156y48 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1826_1 ( .OUT(na1826_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2405_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1826_2 ( .OUT(na1826_1), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1826_1_i) ); +// C_AND/D/// x151y62 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1827_1 ( .OUT(na1827_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1827_2 ( .OUT(na1827_1), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1827_1_i) ); +// C_///AND/D x151y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1828_4 ( .OUT(na1828_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1828_5 ( .OUT(na1828_2), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1828_2_i) ); +// C_AND/D/// x152y67 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1829_1 ( .OUT(na1829_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1829_2 ( .OUT(na1829_1), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1829_1_i) ); +// C_///AND/D x156y74 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1830_4 ( .OUT(na1830_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1830_5 ( .OUT(na1830_2), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1830_2_i) ); +// C_AND/D/// x140y77 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1831_1 ( .OUT(na1831_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1831_2 ( .OUT(na1831_1), .CLK(na2414_1), .EN(na266_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1831_1_i) ); +// C_///AND/D x151y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1832_4 ( .OUT(na1832_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1832_5 ( .OUT(na1832_2), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1832_2_i) ); +// C_///AND/D x137y42 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1833_4 ( .OUT(na1833_2_i), .IN1(na2402_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1833_5 ( .OUT(na1833_2), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1833_2_i) ); +// C_///AND/D x151y45 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1834_4 ( .OUT(na1834_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1834_5 ( .OUT(na1834_2), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1834_2_i) ); +// C_AND/D/// x145y44 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1835_1 ( .OUT(na1835_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1835_2 ( .OUT(na1835_1), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1835_1_i) ); +// C_///AND/D x152y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1836_4 ( .OUT(na1836_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1836_5 ( .OUT(na1836_2), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1836_2_i) ); +// C_AND/D/// x151y61 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1837_1 ( .OUT(na1837_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1837_2 ( .OUT(na1837_1), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1837_1_i) ); +// C_///AND/D x149y73 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1838_4 ( .OUT(na1838_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1838_5 ( .OUT(na1838_2), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1838_2_i) ); +// C_AND/D/// x154y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1839_1 ( .OUT(na1839_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1839_2 ( .OUT(na1839_1), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1839_1_i) ); +// C_AND/D/// x154y79 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1840_1 ( .OUT(na1840_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2409_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1840_2 ( .OUT(na1840_1), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1840_1_i) ); +// C_AND/D/// x140y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1841_1 ( .OUT(na1841_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1841_2 ( .OUT(na1841_1), .CLK(na2414_1), .EN(na267_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1841_1_i) ); +// C_///AND/D x155y35 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1842_4 ( .OUT(na1842_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1842_5 ( .OUT(na1842_2), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1842_2_i) ); +// C_AND/D/// x141y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1843_1 ( .OUT(na1843_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1843_2 ( .OUT(na1843_1), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1843_1_i) ); +// C_///AND/D x149y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1844_4 ( .OUT(na1844_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1844_5 ( .OUT(na1844_2), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1844_2_i) ); +// C_AND/D/// x148y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1845_1 ( .OUT(na1845_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1845_2 ( .OUT(na1845_1), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1845_1_i) ); +// C_///AND/D x153y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1846_4 ( .OUT(na1846_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1846_5 ( .OUT(na1846_2), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1846_2_i) ); +// C_///AND/D x156y64 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1847_4 ( .OUT(na1847_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2406_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1847_5 ( .OUT(na1847_2), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1847_2_i) ); +// C_///AND/D x147y72 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1848_4 ( .OUT(na1848_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1848_5 ( .OUT(na1848_2), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1848_2_i) ); +// C_AND/D/// x153y72 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1849_1 ( .OUT(na1849_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1849_2 ( .OUT(na1849_1), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1849_1_i) ); +// C_///AND/D x151y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1850_4 ( .OUT(na1850_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1850_5 ( .OUT(na1850_2), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1850_2_i) ); +// C_AND/D/// x141y84 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1851_1 ( .OUT(na1851_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1851_2 ( .OUT(na1851_1), .CLK(na2414_1), .EN(na268_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1851_1_i) ); +// C_///AND/D x155y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1852_4 ( .OUT(na1852_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1852_5 ( .OUT(na1852_2), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1852_2_i) ); +// C_AND/D/// x139y38 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1853_1 ( .OUT(na1853_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1853_2 ( .OUT(na1853_1), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1853_1_i) ); +// C_AND/D/// x153y40 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1854_1 ( .OUT(na1854_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2403_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1854_2 ( .OUT(na1854_1), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1854_1_i) ); +// C_AND/D/// x146y47 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1855_1 ( .OUT(na1855_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1855_2 ( .OUT(na1855_1), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1855_1_i) ); +// C_///AND/D x155y59 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1856_4 ( .OUT(na1856_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1856_5 ( .OUT(na1856_2), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1856_2_i) ); +// C_AND/D/// x154y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1857_1 ( .OUT(na1857_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1857_2 ( .OUT(na1857_1), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1857_1_i) ); +// C_///AND/D x149y69 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1858_4 ( .OUT(na1858_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1858_5 ( .OUT(na1858_2), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1858_2_i) ); +// C_AND/D/// x153y71 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1859_1 ( .OUT(na1859_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1859_2 ( .OUT(na1859_1), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1859_1_i) ); +// C_///AND/D x153y81 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1860_4 ( .OUT(na1860_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1860_5 ( .OUT(na1860_2), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1860_2_i) ); +// C_///AND/D x139y83 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1861_4 ( .OUT(na1861_2_i), .IN1(1'b1), .IN2(na2410_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1861_5 ( .OUT(na1861_2), .CLK(na2414_1), .EN(na269_1), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1861_2_i) ); +// C_///AND/D x154y37 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1862_4 ( .OUT(na1862_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1862_5 ( .OUT(na1862_2), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1862_2_i) ); +// C_AND/D/// x140y37 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1863_1 ( .OUT(na1863_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1863_2 ( .OUT(na1863_1), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1863_1_i) ); +// C_///AND/D x154y49 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1864_4 ( .OUT(na1864_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1864_5 ( .OUT(na1864_2), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1864_2_i) ); +// C_AND/D/// x147y48 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1865_1 ( .OUT(na1865_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2404_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1865_2 ( .OUT(na1865_1), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1865_1_i) ); +// C_///AND/D x156y60 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1866_4 ( .OUT(na1866_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1866_5 ( .OUT(na1866_2), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1866_2_i) ); +// C_AND/D/// x151y64 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1867_1 ( .OUT(na1867_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1867_2 ( .OUT(na1867_1), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1867_1_i) ); +// C_AND/D/// x150y68 80'h00_FA00_00_0000_0C88_AFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1868_1 ( .OUT(na1868_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na2407_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1868_2 ( .OUT(na1868_1), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1868_1_i) ); +// C_AND/D/// x154y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1869_1 ( .OUT(na1869_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1869_2 ( .OUT(na1869_1), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1869_1_i) ); +// C_///AND/D x156y82 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1870_4 ( .OUT(na1870_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1870_5 ( .OUT(na1870_2), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1870_2_i) ); +// C_AND/D/// x140y82 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1871_1 ( .OUT(na1871_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1871_2 ( .OUT(na1871_1), .CLK(na2414_1), .EN(na270_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1871_1_i) ); +// C_///AND/D x148y38 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1872_4 ( .OUT(na1872_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2401_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1872_5 ( .OUT(na1872_2), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1872_2_i) ); +// C_AND/D/// x140y34 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1873_1 ( .OUT(na1873_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2402_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1873_2 ( .OUT(na1873_1), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1873_1_i) ); +// C_///AND/D x148y47 80'h00_FA00_80_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1874_4 ( .OUT(na1874_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na2403_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1874_5 ( .OUT(na1874_2), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1874_2_i) ); +// C_///AND/D x138y48 80'h00_FA00_80_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1875_4 ( .OUT(na1875_2_i), .IN1(1'b1), .IN2(na2404_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1875_5 ( .OUT(na1875_2), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1875_2_i) ); +// C_///AND/D x155y63 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1876_4 ( .OUT(na1876_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2405_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1876_5 ( .OUT(na1876_2), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1876_2_i) ); +// C_AND/D/// x150y63 80'h00_FA00_00_0000_0C88_CFFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1877_1 ( .OUT(na1877_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(na2406_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1877_2 ( .OUT(na1877_1), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1877_1_i) ); +// C_///AND/D x154y71 80'h00_FA00_80_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1878_4 ( .OUT(na1878_2_i), .IN1(1'b1), .IN2(1'b1), .IN3(na2407_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1878_5 ( .OUT(na1878_2), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1878_2_i) ); +// C_AND/D/// x149y70 80'h00_FA00_00_0000_0C88_FAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1879_1 ( .OUT(na1879_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2408_1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1879_2 ( .OUT(na1879_1), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1879_1_i) ); +// C_///AND/D x155y75 80'h00_FA00_80_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a1880_4 ( .OUT(na1880_2_i), .IN1(na2409_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0100)) + _a1880_5 ( .OUT(na1880_2), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1880_2_i) ); +// C_AND/D/// x139y78 80'h00_FA00_00_0000_0C88_FCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a1881_1 ( .OUT(na1881_1_i), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2410_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_D #(.CPE_CFG (9'bX_0000_0000)) + _a1881_2 ( .OUT(na1881_1), .CLK(na2414_1), .EN(na265_2), .SR(1'b1), .CINY2(1'b0), .PINY2(1'b0), .RAM_I(1'b0), .CP_O(1'b0), + .D_IN(na1881_1_i) ); +// C_MX4b//// x146y36 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1882_1 ( .OUT(na1882_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na362_2), .IN6(na422_1), .IN7(na412_2), + .IN8(na352_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x146y37 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1883_1 ( .OUT(na1883_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na382_2), .IN6(na392_2), .IN7(na342_1), + .IN8(na282_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x149y38 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1884_1 ( .OUT(na1884_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na332_2), .IN6(na322_2), .IN7(na372_1), + .IN8(na592_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y37 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1885_1 ( .OUT(na1885_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na312_1), .IN6(na302_2), .IN7(na292_2), + .IN8(na432_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y38 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1886_1 ( .OUT(na1886_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1885_1), .IN6(na1884_1), .IN7(na1883_1), + .IN8(na1882_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x142y37 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1887_1 ( .OUT(na1887_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na423_1), .IN6(na363_1), .IN7(na353_2), + .IN8(na413_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x140y32 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1888_1 ( .OUT(na1888_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na283_1), .IN6(na343_1), .IN7(na393_1), + .IN8(na383_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x139y31 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1889_1 ( .OUT(na1889_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na373_1), .IN6(na593_1), .IN7(na333_1), + .IN8(na323_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y34 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1890_1 ( .OUT(na1890_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na313_1), .IN6(na303_1), .IN7(na293_1), + .IN8(na433_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x137y34 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1891_1 ( .OUT(na1891_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1889_1), .IN6(na1890_1), .IN7(na1887_1), + .IN8(na1888_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y38 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1892_1 ( .OUT(na1892_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na354_2), .IN6(na414_2), .IN7(na424_2), + .IN8(na364_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y39 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1893_1 ( .OUT(na1893_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na384_2), .IN6(na394_1), .IN7(na344_2), + .IN8(na284_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x144y42 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1894_1 ( .OUT(na1894_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na594_2), .IN6(na374_2), .IN7(na324_2), + .IN8(na334_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y39 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1895_1 ( .OUT(na1895_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na294_2), .IN6(na434_2), .IN7(na314_2), + .IN8(na304_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y44 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1896_1 ( .OUT(na1896_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1893_1), .IN6(na1892_1), .IN7(na1895_1), + .IN8(na1894_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x126y47 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1897_1 ( .OUT(na1897_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na365_1), .IN6(na425_1), .IN7(na415_1), + .IN8(na355_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x128y48 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1898_1 ( .OUT(na1898_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na345_2), .IN6(na285_1), .IN7(na385_1), + .IN8(na395_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x123y47 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1899_1 ( .OUT(na1899_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na335_1), .IN6(na325_1), .IN7(na375_2), + .IN8(na595_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y48 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1900_1 ( .OUT(na1900_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na315_1), .IN6(na305_1), .IN7(na295_2), + .IN8(na435_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y48 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1901_1 ( .OUT(na1901_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1899_1), .IN6(na1900_1), .IN7(na1897_1), + .IN8(na1898_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y47 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1902_1 ( .OUT(na1902_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na366_2), .IN6(na426_2), .IN7(na416_1), + .IN8(na356_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x149y48 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1903_1 ( .OUT(na1903_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na396_2), .IN6(na386_1), .IN7(na286_2), + .IN8(na346_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y47 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1904_1 ( .OUT(na1904_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na596_2), .IN6(na376_2), .IN7(na326_2), + .IN8(na336_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y48 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1905_1 ( .OUT(na1905_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na316_2), .IN6(na306_1), .IN7(na296_2), + .IN8(na436_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y50 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1906_1 ( .OUT(na1906_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1902_1), .IN6(na1903_1), .IN7(na1904_1), + .IN8(na1905_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x144y51 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1907_1 ( .OUT(na1907_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na367_2), .IN6(na427_2), .IN7(na417_1), + .IN8(na357_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x142y50 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1908_1 ( .OUT(na1908_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na397_2), .IN6(na387_1), .IN7(na287_2), + .IN8(na347_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y51 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1909_1 ( .OUT(na1909_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na337_1), .IN6(na327_1), .IN7(na377_1), + .IN8(na597_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y54 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1910_1 ( .OUT(na1910_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na317_2), .IN6(na307_1), .IN7(na297_1), + .IN8(na437_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y54 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1911_1 ( .OUT(na1911_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1909_1), .IN6(na1910_1), .IN7(na1907_1), + .IN8(na1908_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y56 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1912_1 ( .OUT(na1912_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na418_2), .IN6(na358_2), .IN7(na368_2), + .IN8(na428_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y59 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1913_1 ( .OUT(na1913_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na388_2), .IN6(na398_2), .IN7(na348_2), + .IN8(na288_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x142y62 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1914_1 ( .OUT(na1914_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na338_2), .IN6(na328_1), .IN7(na378_1), + .IN8(na598_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x144y61 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1915_1 ( .OUT(na1915_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na318_2), .IN6(na308_2), .IN7(na298_1), + .IN8(na438_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y60 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1916_1 ( .OUT(na1916_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1913_1), .IN6(na1912_1), .IN7(na1915_1), + .IN8(na1914_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y67 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1917_1 ( .OUT(na1917_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na419_2), .IN6(na359_1), .IN7(na369_1), + .IN8(na429_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y66 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1918_1 ( .OUT(na1918_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na399_1), .IN6(na389_2), .IN7(na289_1), + .IN8(na349_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x142y65 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1919_1 ( .OUT(na1919_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na339_2), .IN6(na329_1), .IN7(na379_1), + .IN8(na599_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x140y68 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1920_1 ( .OUT(na1920_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na299_1), .IN6(na439_1), .IN7(na319_1), + .IN8(na309_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x137y68 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1921_1 ( .OUT(na1921_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1917_1), .IN6(na1918_1), .IN7(na1919_1), + .IN8(na1920_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y73 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1922_1 ( .OUT(na1922_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na420_2), .IN6(na360_2), .IN7(na370_2), + .IN8(na430_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y74 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1923_1 ( .OUT(na1923_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na400_1), .IN6(na390_2), .IN7(na290_1), + .IN8(na350_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x142y71 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1924_1 ( .OUT(na1924_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na600_2), .IN6(na380_2), .IN7(na330_2), + .IN8(na340_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y76 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1925_1 ( .OUT(na1925_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na320_1), .IN6(na310_2), .IN7(na300_2), + .IN8(na440_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y72 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1926_1 ( .OUT(na1926_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1922_1), .IN6(na1923_1), .IN7(na1924_1), + .IN8(na1925_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y79 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1927_1 ( .OUT(na1927_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na371_1), .IN6(na431_1), .IN7(na421_1), + .IN8(na361_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y76 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1928_1 ( .OUT(na1928_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na291_1), .IN6(na351_1), .IN7(na401_1), + .IN8(na391_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x128y81 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1929_1 ( .OUT(na1929_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na381_1), .IN6(na601_1), .IN7(na341_1), + .IN8(na331_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y76 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1930_1 ( .OUT(na1930_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na311_1), .IN6(na321_1), .IN7(na441_2), + .IN8(na301_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y74 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1931_1 ( .OUT(na1931_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1927_1), .IN6(na1928_1), .IN7(na1929_1), + .IN8(na1930_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y33 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1932_1 ( .OUT(na1932_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na692_2), .IN6(na612_2), .IN7(na622_2), + .IN8(na632_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y36 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1933_1 ( .OUT(na1933_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na642_1), .IN6(na652_2), .IN7(na662_2), + .IN8(na672_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y35 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1934_1 ( .OUT(na1934_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na682_2), .IN6(na752_1), .IN7(na702_1), + .IN8(na712_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y36 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1935_1 ( .OUT(na1935_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na722_2), .IN6(na732_2), .IN7(na742_2), + .IN8(na602_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y40 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1936_1 ( .OUT(na1936_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1932_1), .IN6(na1933_1), .IN7(na1934_1), + .IN8(na1935_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y32 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1937_1 ( .OUT(na1937_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na623_1), .IN6(na633_1), .IN7(na693_1), + .IN8(na613_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y31 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1938_1 ( .OUT(na1938_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na663_1), .IN6(na673_1), .IN7(na643_1), + .IN8(na653_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y32 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1939_1 ( .OUT(na1939_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na683_2), .IN6(na753_1), .IN7(na703_1), + .IN8(na713_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y33 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1940_1 ( .OUT(na1940_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na603_2), .IN6(na743_1), .IN7(na733_1), + .IN8(na723_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y34 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1941_1 ( .OUT(na1941_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1938_1), .IN6(na1937_1), .IN7(na1940_1), + .IN8(na1939_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x146y43 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1942_1 ( .OUT(na1942_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na694_1), .IN6(na614_1), .IN7(na624_2), + .IN8(na634_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y44 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1943_1 ( .OUT(na1943_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na674_2), .IN6(na664_1), .IN7(na654_2), + .IN8(na644_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y43 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1944_1 ( .OUT(na1944_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na714_2), .IN6(na704_2), .IN7(na754_2), + .IN8(na684_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y44 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1945_1 ( .OUT(na1945_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na744_2), .IN6(na604_2), .IN7(na724_1), + .IN8(na734_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y46 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1946_1 ( .OUT(na1946_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1944_1), .IN6(na1945_1), .IN7(na1942_1), + .IN8(na1943_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y49 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1947_1 ( .OUT(na1947_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na695_1), .IN6(na615_1), .IN7(na625_2), + .IN8(na635_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y52 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1948_1 ( .OUT(na1948_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na655_1), .IN6(na645_1), .IN7(na675_2), + .IN8(na665_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y51 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1949_1 ( .OUT(na1949_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na755_1), .IN6(na685_1), .IN7(na715_1), + .IN8(na705_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x134y54 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1950_1 ( .OUT(na1950_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na725_1), .IN6(na735_2), .IN7(na745_1), + .IN8(na605_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x133y52 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1951_1 ( .OUT(na1951_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1947_1), .IN6(na1948_1), .IN7(na1949_1), + .IN8(na1950_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y42 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1952_1 ( .OUT(na1952_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na616_2), .IN6(na696_2), .IN7(na636_1), + .IN8(na626_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y41 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1953_1 ( .OUT(na1953_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na656_2), .IN6(na646_2), .IN7(na676_2), + .IN8(na666_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y44 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1954_1 ( .OUT(na1954_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na706_2), .IN6(na716_1), .IN7(na686_1), + .IN8(na756_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y43 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1955_1 ( .OUT(na1955_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na736_2), .IN6(na726_2), .IN7(na606_1), + .IN8(na746_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y44 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1956_1 ( .OUT(na1956_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1953_1), .IN6(na1952_1), .IN7(na1955_1), + .IN8(na1954_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y50 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1957_1 ( .OUT(na1957_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na697_2), .IN6(na617_2), .IN7(na627_1), + .IN8(na637_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y49 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1958_1 ( .OUT(na1958_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na647_2), .IN6(na657_1), .IN7(na667_1), + .IN8(na677_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x155y52 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1959_1 ( .OUT(na1959_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na687_1), .IN6(na757_2), .IN7(na707_1), + .IN8(na717_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y51 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1960_1 ( .OUT(na1960_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na737_1), .IN6(na727_2), .IN7(na607_1), + .IN8(na747_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y52 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1961_1 ( .OUT(na1961_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1960_1), .IN6(na1959_1), .IN7(na1958_1), + .IN8(na1957_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y62 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1962_1 ( .OUT(na1962_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na698_2), .IN6(na618_2), .IN7(na628_1), + .IN8(na638_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y63 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1963_1 ( .OUT(na1963_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na658_1), .IN6(na648_2), .IN7(na678_2), + .IN8(na668_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x146y64 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1964_1 ( .OUT(na1964_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na688_2), .IN6(na758_2), .IN7(na708_1), + .IN8(na718_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y61 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1965_1 ( .OUT(na1965_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na728_2), .IN6(na738_1), .IN7(na748_2), + .IN8(na608_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y62 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1966_1 ( .OUT(na1966_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1963_1), .IN6(na1962_1), .IN7(na1965_1), + .IN8(na1964_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x146y72 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1967_1 ( .OUT(na1967_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na619_1), .IN6(na699_1), .IN7(na639_2), + .IN8(na629_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x146y69 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1968_1 ( .OUT(na1968_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na679_1), .IN6(na669_2), .IN7(na659_1), + .IN8(na649_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y70 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1969_1 ( .OUT(na1969_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na759_1), .IN6(na689_1), .IN7(na719_2), + .IN8(na709_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y69 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1970_1 ( .OUT(na1970_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na729_1), .IN6(na739_1), .IN7(na749_2), + .IN8(na609_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y68 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1971_1 ( .OUT(na1971_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1970_1), .IN6(na1969_1), .IN7(na1968_1), + .IN8(na1967_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y76 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1972_1 ( .OUT(na1972_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na630_2), .IN6(na640_2), .IN7(na700_2), + .IN8(na620_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y77 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1973_1 ( .OUT(na1973_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na680_1), .IN6(na670_2), .IN7(na660_2), + .IN8(na650_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y78 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1974_1 ( .OUT(na1974_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na710_2), .IN6(na720_2), .IN7(na690_2), + .IN8(na760_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y79 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1975_1 ( .OUT(na1975_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na740_2), .IN6(na730_1), .IN7(na610_2), + .IN8(na750_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x149y78 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1976_1 ( .OUT(na1976_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1973_1), .IN6(na1972_1), .IN7(na1975_1), + .IN8(na1974_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x133y77 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1977_1 ( .OUT(na1977_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na621_1), .IN6(na701_1), .IN7(na641_1), + .IN8(na631_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x135y82 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1978_1 ( .OUT(na1978_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na651_1), .IN6(na661_2), .IN7(na671_1), + .IN8(na681_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x134y75 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1979_1 ( .OUT(na1979_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na691_2), .IN6(na761_1), .IN7(na711_1), + .IN8(na721_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x136y82 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1980_1 ( .OUT(na1980_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na731_1), .IN6(na741_2), .IN7(na751_1), + .IN8(na611_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x135y76 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1981_1 ( .OUT(na1981_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1977_1), .IN6(na1978_1), .IN7(na1979_1), + .IN8(na1980_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y32 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1982_1 ( .OUT(na1982_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na772_2), .IN6(na852_2), .IN7(na792_2), + .IN8(na782_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y31 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1983_1 ( .OUT(na1983_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na832_2), .IN6(na822_2), .IN7(na812_1), + .IN8(na802_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y32 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1984_1 ( .OUT(na1984_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na912_2), .IN6(na842_2), .IN7(na872_2), + .IN8(na862_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x122y31 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1985_1 ( .OUT(na1985_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na762_2), .IN6(na902_2), .IN7(na892_1), + .IN8(na882_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y34 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1986_1 ( .OUT(na1986_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na1983_1), .IN6(na1982_1), .IN7(na1985_1), + .IN8(na1984_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y37 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1987_1 ( .OUT(na1987_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na853_1), .IN6(na773_1), .IN7(na783_1), + .IN8(na793_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y38 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1988_1 ( .OUT(na1988_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na823_2), .IN6(na833_1), .IN7(na803_1), + .IN8(na813_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x123y45 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1989_1 ( .OUT(na1989_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na843_1), .IN6(na913_1), .IN7(na863_1), + .IN8(na873_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y42 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1990_1 ( .OUT(na1990_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na883_1), .IN6(na893_1), .IN7(na903_2), + .IN8(na763_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y44 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1991_1 ( .OUT(na1991_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1989_1), .IN6(na1990_1), .IN7(na1987_1), + .IN8(na1988_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x114y42 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1992_1 ( .OUT(na1992_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na784_2), .IN6(na794_2), .IN7(na854_2), + .IN8(na774_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y39 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1993_1 ( .OUT(na1993_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na824_2), .IN6(na834_1), .IN7(na804_1), + .IN8(na814_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x119y38 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1994_1 ( .OUT(na1994_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na864_2), .IN6(na874_2), .IN7(na844_2), + .IN8(na914_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y35 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1995_1 ( .OUT(na1995_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na894_2), .IN6(na884_1), .IN7(na764_2), + .IN8(na904_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y39 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1996_1 ( .OUT(na1996_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1995_1), .IN6(na1994_1), .IN7(na1993_1), + .IN8(na1992_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y47 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1997_1 ( .OUT(na1997_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na785_2), .IN6(na795_1), .IN7(na855_1), + .IN8(na775_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x114y44 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1998_1 ( .OUT(na1998_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na805_1), .IN6(na815_2), .IN7(na825_1), + .IN8(na835_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y43 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a1999_1 ( .OUT(na1999_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na865_1), .IN6(na875_1), .IN7(na845_2), + .IN8(na915_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x119y46 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2000_1 ( .OUT(na2000_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na885_1), .IN6(na895_2), .IN7(na905_1), + .IN8(na765_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y46 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2001_1 ( .OUT(na2001_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na1999_1), .IN6(na2000_1), .IN7(na1997_1), + .IN8(na1998_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x116y51 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2002_1 ( .OUT(na2002_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na856_1), .IN6(na776_2), .IN7(na786_2), + .IN8(na796_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x114y46 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2003_1 ( .OUT(na2003_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na826_1), .IN6(na836_2), .IN7(na806_2), + .IN8(na816_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x111y49 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2004_1 ( .OUT(na2004_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na846_2), .IN6(na916_2), .IN7(na866_2), + .IN8(na876_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y52 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2005_1 ( .OUT(na2005_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na896_2), .IN6(na886_2), .IN7(na766_2), + .IN8(na906_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x116y50 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2006_1 ( .OUT(na2006_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2004_1), .IN6(na2005_1), .IN7(na2002_1), + .IN8(na2003_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y52 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2007_1 ( .OUT(na2007_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na787_1), .IN6(na797_1), .IN7(na857_1), + .IN8(na777_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y53 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2008_1 ( .OUT(na2008_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na827_1), .IN6(na837_2), .IN7(na807_2), + .IN8(na817_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y56 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2009_1 ( .OUT(na2009_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na917_2), .IN6(na847_1), .IN7(na877_1), + .IN8(na867_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x126y55 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2010_1 ( .OUT(na2010_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na897_1), .IN6(na887_1), .IN7(na767_1), + .IN8(na907_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x126y53 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2011_1 ( .OUT(na2011_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2008_1), .IN6(na2007_1), .IN7(na2010_1), + .IN8(na2009_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y67 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2012_1 ( .OUT(na2012_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na858_2), .IN6(na778_2), .IN7(na788_2), + .IN8(na798_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y64 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2013_1 ( .OUT(na2013_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na828_2), .IN6(na838_2), .IN7(na808_2), + .IN8(na818_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y67 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2014_1 ( .OUT(na2014_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na848_1), .IN6(na918_2), .IN7(na868_2), + .IN8(na878_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y66 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2015_1 ( .OUT(na2015_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na908_2), .IN6(na768_1), .IN7(na888_2), + .IN8(na898_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x127y66 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2016_1 ( .OUT(na2016_1), .IN1(na2012_1), .IN2(na2013_1), .IN3(na2014_1), .IN4(na2015_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x121y67 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2017_1 ( .OUT(na2017_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na789_1), .IN6(na799_1), .IN7(na859_2), + .IN8(na779_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y68 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2018_1 ( .OUT(na2018_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na819_1), .IN6(na809_1), .IN7(na839_1), + .IN8(na829_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y69 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2019_1 ( .OUT(na2019_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na849_1), .IN6(na919_1), .IN7(na869_1), + .IN8(na879_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x122y70 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2020_1 ( .OUT(na2020_1), .IN1(na899_1), .IN2(na889_2), .IN3(na769_1), .IN4(na909_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y70 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2021_1 ( .OUT(na2021_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2017_1), .IN6(na2018_1), .IN7(na2019_1), + .IN8(na2020_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x116y76 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2022_1 ( .OUT(na2022_1), .IN1(na780_2), .IN2(na860_2), .IN3(na800_2), .IN4(na790_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x116y75 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2023_1 ( .OUT(na2023_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na830_2), .IN6(na840_1), .IN7(na810_2), + .IN8(na820_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y76 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2024_1 ( .OUT(na2024_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na870_1), .IN6(na880_2), .IN7(na850_2), + .IN8(na920_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y79 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2025_1 ( .OUT(na2025_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na890_2), .IN6(na900_1), .IN7(na910_2), + .IN8(na770_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x118y74 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2026_1 ( .OUT(na2026_1), .IN1(na2025_1), .IN2(na2024_1), .IN3(na2023_1), .IN4(na2022_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x128y74 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2027_1 ( .OUT(na2027_1), .IN1(na781_1), .IN2(na861_1), .IN3(na801_2), .IN4(na791_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y73 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2028_1 ( .OUT(na2028_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na811_1), .IN6(na821_1), .IN7(na831_1), + .IN8(na841_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y78 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2029_1 ( .OUT(na2029_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na871_1), .IN6(na881_2), .IN7(na851_2), + .IN8(na921_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y77 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2030_1 ( .OUT(na2030_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na771_2), .IN6(na911_2), .IN7(na901_1), + .IN8(na891_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x126y73 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2031_1 ( .OUT(na2031_1), .IN1(na2030_1), .IN2(na2029_1), .IN3(na2028_1), .IN4(na2027_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x121y32 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2032_1 ( .OUT(na2032_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na932_2), .IN6(na1012_2), .IN7(na952_2), + .IN8(na942_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x125y31 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2033_1 ( .OUT(na2033_1), .IN1(na992_2), .IN2(na982_2), .IN3(na972_1), .IN4(na962_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x128y32 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2034_1 ( .OUT(na2034_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1002_2), .IN6(na1072_2), .IN7(na1022_2), + .IN8(na1032_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x128y31 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2035_1 ( .OUT(na2035_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na922_1), .IN6(na1062_2), .IN7(na1052_2), + .IN8(na1042_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x122y29 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2036_1 ( .OUT(na2036_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2033_1), .IN6(na2032_1), .IN7(na2035_1), + .IN8(na2034_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x122y35 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2037_1 ( .OUT(na2037_1), .IN1(na1013_1), .IN2(na933_2), .IN3(na943_1), .IN4(na953_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x120y36 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2038_1 ( .OUT(na2038_1), .IN1(na993_2), .IN2(na983_2), .IN3(na973_1), .IN4(na963_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x123y39 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2039_1 ( .OUT(na2039_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1003_1), .IN6(na1073_1), .IN7(na1023_1), + .IN8(na1033_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x123y38 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2040_1 ( .OUT(na2040_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1043_1), .IN6(na1053_1), .IN7(na1063_2), + .IN8(na923_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y40 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2041_1 ( .OUT(na2041_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2039_1), .IN6(na2040_1), .IN7(na2037_1), + .IN8(na2038_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x114y40 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2042_1 ( .OUT(na2042_1), .IN1(na954_2), .IN2(na944_1), .IN3(na934_2), .IN4(na1014_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y41 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2043_1 ( .OUT(na2043_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na964_2), .IN6(na974_2), .IN7(na984_2), + .IN8(na994_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x113y40 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2044_1 ( .OUT(na2044_1), .IN1(na1034_2), .IN2(na1024_2), .IN3(na1074_2), .IN4(na1004_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y41 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2045_1 ( .OUT(na2045_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1054_2), .IN6(na1044_2), .IN7(na924_2), + .IN8(na1064_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y42 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2046_1 ( .OUT(na2046_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2045_1), .IN6(na2044_1), .IN7(na2043_1), + .IN8(na2042_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y45 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2047_1 ( .OUT(na2047_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na955_2), .IN6(na945_1), .IN7(na935_1), + .IN8(na1015_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x119y48 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2048_1 ( .OUT(na2048_1), .IN1(na985_1), .IN2(na995_1), .IN3(na965_1), .IN4(na975_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x122y49 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2049_1 ( .OUT(na2049_1), .IN1(na1025_1), .IN2(na1035_2), .IN3(na1005_1), .IN4(na1075_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x122y48 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2050_1 ( .OUT(na2050_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1055_1), .IN6(na1045_1), .IN7(na925_2), + .IN8(na1065_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y49 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2051_1 ( .OUT(na2051_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2047_1), .IN6(na2048_1), .IN7(na2049_1), + .IN8(na2050_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x112y54 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2052_1 ( .OUT(na2052_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na936_1), .IN6(na1016_2), .IN7(na956_2), + .IN8(na946_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x116y53 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2053_1 ( .OUT(na2053_1), .IN1(na986_1), .IN2(na996_2), .IN3(na966_1), .IN4(na976_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x113y56 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2054_1 ( .OUT(na2054_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1006_2), .IN6(na1076_2), .IN7(na1026_2), + .IN8(na1036_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x115y53 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2055_1 ( .OUT(na2055_1), .IN1(na1056_1), .IN2(na1046_2), .IN3(na926_2), .IN4(na1066_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y54 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2056_1 ( .OUT(na2056_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2055_1), .IN6(na2054_1), .IN7(na2053_1), + .IN8(na2052_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y53 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2057_1 ( .OUT(na2057_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na937_1), .IN6(na1017_1), .IN7(na957_1), + .IN8(na947_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y54 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2058_1 ( .OUT(na2058_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na997_1), .IN6(na987_1), .IN7(na977_2), + .IN8(na967_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x122y55 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2059_1 ( .OUT(na2059_1), .IN1(na1007_2), .IN2(na1077_2), .IN3(na1027_1), .IN4(na1037_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x126y54 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2060_1 ( .OUT(na2060_1), .IN1(na927_1), .IN2(na1067_1), .IN3(na1057_1), .IN4(na1047_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y53 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2061_1 ( .OUT(na2061_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2057_1), .IN6(na2058_1), .IN7(na2059_1), + .IN8(na2060_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y66 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2062_1 ( .OUT(na2062_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na938_2), .IN6(na1018_2), .IN7(na958_1), + .IN8(na948_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y65 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2063_1 ( .OUT(na2063_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na998_2), .IN6(na988_2), .IN7(na978_2), + .IN8(na968_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x117y66 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2064_1 ( .OUT(na2064_1), .IN1(na1078_2), .IN2(na1008_2), .IN3(na1038_2), .IN4(na1028_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y63 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2065_1 ( .OUT(na2065_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1058_2), .IN6(na1048_2), .IN7(na928_1), + .IN8(na1068_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x120y62 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2066_1 ( .OUT(na2066_1), .IN1(na2065_1), .IN2(na2064_1), .IN3(na2063_1), .IN4(na2062_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x113y65 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2067_1 ( .OUT(na2067_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na959_1), .IN6(na949_1), .IN7(na939_2), + .IN8(na1019_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y68 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2068_1 ( .OUT(na2068_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na969_2), .IN6(na979_1), .IN7(na989_1), + .IN8(na999_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x114y69 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2069_1 ( .OUT(na2069_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1009_1), .IN6(na1079_1), .IN7(na1029_1), + .IN8(na1039_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x116y68 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2070_1 ( .OUT(na2070_1), .IN1(na1069_1), .IN2(na929_1), .IN3(na1049_2), .IN4(na1059_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x115y65 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2071_1 ( .OUT(na2071_1), .IN1(na2067_1), .IN2(na2068_1), .IN3(na2069_1), .IN4(na2070_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x114y78 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2072_1 ( .OUT(na2072_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na940_2), .IN6(na1020_2), .IN7(na960_2), + .IN8(na950_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x116y79 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2073_1 ( .OUT(na2073_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na990_2), .IN6(na1000_1), .IN7(na970_2), + .IN8(na980_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x113y74 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2074_1 ( .OUT(na2074_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1010_2), .IN6(na1080_2), .IN7(na1030_2), + .IN8(na1040_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x117y79 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2075_1 ( .OUT(na2075_1), .IN1(na1050_2), .IN2(na1060_2), .IN3(na1070_1), .IN4(na930_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y80 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2076_1 ( .OUT(na2076_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2075_1), .IN6(na2074_1), .IN7(na2073_1), + .IN8(na2072_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x136y74 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2077_1 ( .OUT(na2077_1), .IN1(na1021_2), .IN2(na941_1), .IN3(na951_1), .IN4(na961_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x136y67 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2078_1 ( .OUT(na2078_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na971_1), .IN6(na981_1), .IN7(na991_1), + .IN8(na1001_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x137y70 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2079_1 ( .OUT(na2079_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1081_1), .IN6(na1011_1), .IN7(na1041_1), + .IN8(na1031_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x137y67 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2080_1 ( .OUT(na2080_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1061_1), .IN6(na1051_1), .IN7(na931_1), + .IN8(na1071_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x135y66 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2081_1 ( .OUT(na2081_1), .IN1(na2080_1), .IN2(na2079_1), .IN3(na2078_1), .IN4(na2077_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x128y36 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2082_1 ( .OUT(na2082_1), .IN1(na1092_2), .IN2(na1172_2), .IN3(na1112_1), .IN4(na1102_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x128y35 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2083_1 ( .OUT(na2083_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1132_2), .IN6(na1122_2), .IN7(na1152_2), + .IN8(na1142_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y32 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2084_1 ( .OUT(na2084_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1192_2), .IN6(na1182_1), .IN7(na1232_2), + .IN8(na1162_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x129y31 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2085_1 ( .OUT(na2085_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1212_2), .IN6(na1202_2), .IN7(na1082_2), + .IN8(na1222_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x130y36 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2086_1 ( .OUT(na2086_1), .IN1(na2085_1), .IN2(na2084_1), .IN3(na2083_1), .IN4(na2082_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y40 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2087_1 ( .OUT(na2087_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1103_1), .IN6(na1113_1), .IN7(na1173_1), + .IN8(na1093_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x129y41 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2088_1 ( .OUT(na2088_1), .IN1(na1153_1), .IN2(na1143_1), .IN3(na1133_2), .IN4(na1123_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y38 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2089_1 ( .OUT(na2089_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1163_1), .IN6(na1233_1), .IN7(na1183_1), + .IN8(na1193_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y37 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2090_1 ( .OUT(na2090_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1213_1), .IN6(na1203_2), .IN7(na1083_1), + .IN8(na1223_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y41 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2091_1 ( .OUT(na2091_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2088_1), .IN6(na2087_1), .IN7(na2090_1), + .IN8(na2089_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x125y39 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2092_1 ( .OUT(na2092_1), .IN1(na1114_2), .IN2(na1104_2), .IN3(na1094_2), .IN4(na1174_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x125y34 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2093_1 ( .OUT(na2093_1), .IN1(na1154_1), .IN2(na1144_2), .IN3(na1134_2), .IN4(na1124_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y35 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2094_1 ( .OUT(na2094_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1184_2), .IN6(na1194_2), .IN7(na1164_2), + .IN8(na1234_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y38 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2095_1 ( .OUT(na2095_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1214_2), .IN6(na1204_2), .IN7(na1084_1), + .IN8(na1224_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x125y41 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2096_1 ( .OUT(na2096_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2092_1), .IN6(na2093_1), .IN7(na2094_1), + .IN8(na2095_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x134y44 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2097_1 ( .OUT(na2097_1), .IN1(na1105_2), .IN2(na1115_1), .IN3(na1175_2), .IN4(na1095_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x136y47 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2098_1 ( .OUT(na2098_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1125_1), .IN6(na1135_1), .IN7(na1145_1), + .IN8(na1155_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x129y48 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2099_1 ( .OUT(na2099_1), .IN1(na1235_1), .IN2(na1165_1), .IN3(na1195_1), .IN4(na1185_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y45 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2100_1 ( .OUT(na2100_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1205_1), .IN6(na1215_1), .IN7(na1225_1), + .IN8(na1085_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x137y51 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2101_1 ( .OUT(na2101_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2100_1), .IN6(na2099_1), .IN7(na2098_1), + .IN8(na2097_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x134y56 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2102_1 ( .OUT(na2102_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1176_2), .IN6(na1096_2), .IN7(na1106_2), + .IN8(na1116_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x134y55 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2103_1 ( .OUT(na2103_1), .IN1(na1146_2), .IN2(na1156_2), .IN3(na1126_1), .IN4(na1136_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x133y56 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2104_1 ( .OUT(na2104_1), .IN1(na1186_2), .IN2(na1196_1), .IN3(na1166_2), .IN4(na1236_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x135y55 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2105_1 ( .OUT(na2105_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1086_2), .IN6(na1226_2), .IN7(na1216_2), + .IN8(na1206_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x133y55 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2106_1 ( .OUT(na2106_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2105_1), .IN6(na2104_1), .IN7(na2103_1), + .IN8(na2102_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x123y63 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2107_1 ( .OUT(na2107_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1107_1), .IN6(na1117_1), .IN7(na1177_1), + .IN8(na1097_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x123y64 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2108_1 ( .OUT(na2108_1), .IN1(na1127_1), .IN2(na1137_1), .IN3(na1147_2), .IN4(na1157_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y61 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2109_1 ( .OUT(na2109_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1187_1), .IN6(na1197_1), .IN7(na1167_1), + .IN8(na1237_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x122y60 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2110_1 ( .OUT(na2110_1), .IN1(na1227_1), .IN2(na1087_1), .IN3(na1207_1), .IN4(na1217_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x123y59 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2111_1 ( .OUT(na2111_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2107_1), .IN6(na2108_1), .IN7(na2109_1), + .IN8(na2110_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y69 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2112_1 ( .OUT(na2112_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1098_1), .IN6(na1178_2), .IN7(na1118_2), + .IN8(na1108_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x119y70 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2113_1 ( .OUT(na2113_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1158_2), .IN6(na1148_2), .IN7(na1138_2), + .IN8(na1128_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x122y67 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2114_1 ( .OUT(na2114_1), .IN1(na1198_2), .IN2(na1188_2), .IN3(na1238_1), .IN4(na1168_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x118y68 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2115_1 ( .OUT(na2115_1), .IN1(na1228_2), .IN2(na1088_2), .IN3(na1208_2), .IN4(na1218_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y63 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2116_1 ( .OUT(na2116_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2112_1), .IN6(na2113_1), .IN7(na2114_1), + .IN8(na2115_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y69 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2117_1 ( .OUT(na2117_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1179_1), .IN6(na1099_1), .IN7(na1109_1), + .IN8(na1119_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y74 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2118_1 ( .OUT(na2118_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1129_1), .IN6(na1139_1), .IN7(na1149_1), + .IN8(na1159_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x119y69 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2119_1 ( .OUT(na2119_1), .IN1(na1189_2), .IN2(na1199_1), .IN3(na1169_1), .IN4(na1239_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x119y76 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2120_1 ( .OUT(na2120_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1229_1), .IN6(na1089_1), .IN7(na1209_1), + .IN8(na1219_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x118y67 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2121_1 ( .OUT(na2121_1), .IN1(na2119_1), .IN2(na2120_1), .IN3(na2117_1), .IN4(na2118_1), .IN5(na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y72 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2122_1 ( .OUT(na2122_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1180_2), .IN6(na1100_2), .IN7(na1110_2), + .IN8(na1120_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x129y71 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2123_1 ( .OUT(na2123_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1150_2), .IN6(na1160_2), .IN7(na1130_2), + .IN8(na1140_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y72 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2124_1 ( .OUT(na2124_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1170_2), .IN6(na1240_2), .IN7(na1190_2), + .IN8(na1200_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x130y75 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2125_1 ( .OUT(na2125_1), .IN1(na1210_1), .IN2(na1220_2), .IN3(na1230_2), .IN4(na1090_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x128y70 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2126_1 ( .OUT(na2126_1), .IN1(na2123_1), .IN2(na2122_1), .IN3(na2125_1), .IN4(na2124_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y77 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2127_1 ( .OUT(na2127_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1101_1), .IN6(na1181_1), .IN7(na1121_1), + .IN8(na1111_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x129y82 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2128_1 ( .OUT(na2128_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1141_1), .IN6(na1131_1), .IN7(na1161_2), + .IN8(na1151_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y75 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2129_1 ( .OUT(na2129_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1171_1), .IN6(na1241_1), .IN7(na1191_1), + .IN8(na1201_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x128y84 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2130_1 ( .OUT(na2130_1), .IN1(na1231_2), .IN2(na1091_2), .IN3(na1211_1), .IN4(na1221_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y77 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2131_1 ( .OUT(na2131_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2127_1), .IN6(na2128_1), .IN7(na2129_1), + .IN8(na2130_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x153y37 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2132_1 ( .OUT(na2132_1), .IN1(na1252_1), .IN2(na1332_2), .IN3(na1272_2), .IN4(na1262_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y36 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2133_1 ( .OUT(na2133_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1292_2), .IN6(na1282_2), .IN7(na1312_2), + .IN8(na1302_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y39 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2134_1 ( .OUT(na2134_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1342_2), .IN6(na1352_2), .IN7(na1322_1), + .IN8(na1392_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y36 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2135_1 ( .OUT(na2135_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1382_2), .IN6(na1242_2), .IN7(na1362_2), + .IN8(na1372_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x148y42 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2136_1 ( .OUT(na2136_1), .IN1(na2132_1), .IN2(na2133_1), .IN3(na2134_1), .IN4(na2135_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x130y41 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2137_1 ( .OUT(na2137_1), .IN1(na1273_2), .IN2(na1263_1), .IN3(na1253_1), .IN4(na1333_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y40 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2138_1 ( .OUT(na2138_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1313_1), .IN6(na1303_1), .IN7(na1293_1), + .IN8(na1283_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x129y45 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2139_1 ( .OUT(na2139_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1353_1), .IN6(na1343_2), .IN7(na1393_1), + .IN8(na1323_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x133y38 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2140_1 ( .OUT(na2140_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1243_1), .IN6(na1383_1), .IN7(na1373_1), + .IN8(na1363_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x134y42 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2141_1 ( .OUT(na2141_1), .IN1(na2139_1), .IN2(na2140_1), .IN3(na2137_1), .IN4(na2138_1), .IN5(na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y44 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2142_1 ( .OUT(na2142_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1264_2), .IN6(na1274_2), .IN7(na1334_2), + .IN8(na1254_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x150y43 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2143_1 ( .OUT(na2143_1), .IN1(na1304_2), .IN2(na1314_2), .IN3(na1284_2), .IN4(na1294_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x149y44 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2144_1 ( .OUT(na2144_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1324_2), .IN6(na1394_2), .IN7(na1344_2), + .IN8(na1354_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x149y45 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2145_1 ( .OUT(na2145_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1384_2), .IN6(na1244_2), .IN7(na1364_1), + .IN8(na1374_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y46 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2146_1 ( .OUT(na2146_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2145_1), .IN6(na2144_1), .IN7(na2143_1), + .IN8(na2142_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x133y53 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2147_1 ( .OUT(na2147_1), .IN1(na1265_1), .IN2(na1275_1), .IN3(na1335_1), .IN4(na1255_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x137y54 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2148_1 ( .OUT(na2148_1), .IN1(na1295_1), .IN2(na1285_1), .IN3(na1315_2), .IN4(na1305_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x138y51 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2149_1 ( .OUT(na2149_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1325_1), .IN6(na1395_1), .IN7(na1345_1), + .IN8(na1355_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x140y52 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2150_1 ( .OUT(na2150_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1375_1), .IN6(na1365_1), .IN7(na1245_2), + .IN8(na1385_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x138y52 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2151_1 ( .OUT(na2151_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2147_1), .IN6(na2148_1), .IN7(na2149_1), + .IN8(na2150_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x151y50 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2152_1 ( .OUT(na2152_1), .IN1(na1256_2), .IN2(na1336_1), .IN3(na1276_2), .IN4(na1266_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y49 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2153_1 ( .OUT(na2153_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1306_2), .IN6(na1316_2), .IN7(na1286_2), + .IN8(na1296_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x154y48 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2154_1 ( .OUT(na2154_1), .IN1(na1346_2), .IN2(na1356_2), .IN3(na1326_2), .IN4(na1396_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y45 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2155_1 ( .OUT(na2155_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1366_2), .IN6(na1376_2), .IN7(na1386_2), + .IN8(na1246_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y50 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2156_1 ( .OUT(na2156_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2153_1), .IN6(na2152_1), .IN7(na2155_1), + .IN8(na2154_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y56 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2157_1 ( .OUT(na2157_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1277_1), .IN6(na1267_1), .IN7(na1257_1), + .IN8(na1337_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x151y55 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2158_1 ( .OUT(na2158_1), .IN1(na1287_2), .IN2(na1297_1), .IN3(na1307_1), .IN4(na1317_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x154y58 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2159_1 ( .OUT(na2159_1), .IN1(na1347_1), .IN2(na1357_2), .IN3(na1327_1), .IN4(na1397_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y55 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2160_1 ( .OUT(na2160_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1367_1), .IN6(na1377_1), .IN7(na1387_1), + .IN8(na1247_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y58 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2161_1 ( .OUT(na2161_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2158_1), .IN6(na2157_1), .IN7(na2160_1), + .IN8(na2159_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x144y68 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2162_1 ( .OUT(na2162_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1268_2), .IN6(na1278_2), .IN7(na1338_2), + .IN8(na1258_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x150y65 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2163_1 ( .OUT(na2163_1), .IN1(na1298_2), .IN2(na1288_2), .IN3(na1318_2), .IN4(na1308_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y68 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2164_1 ( .OUT(na2164_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1398_2), .IN6(na1328_2), .IN7(na1358_2), + .IN8(na1348_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x145y69 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2165_1 ( .OUT(na2165_1), .IN1(na1388_2), .IN2(na1248_2), .IN3(na1368_2), .IN4(na1378_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x144y66 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2166_1 ( .OUT(na2166_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2165_1), .IN6(na2164_1), .IN7(na2163_1), + .IN8(na2162_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x151y73 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2167_1 ( .OUT(na2167_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1339_1), .IN6(na1259_2), .IN7(na1269_1), + .IN8(na1279_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y72 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2168_1 ( .OUT(na2168_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1309_1), .IN6(na1319_1), .IN7(na1289_1), + .IN8(na1299_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x148y69 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2169_1 ( .OUT(na2169_1), .IN1(na1329_2), .IN2(na1399_2), .IN3(na1349_1), .IN4(na1359_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x152y72 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2170_1 ( .OUT(na2170_1), .IN1(na1379_1), .IN2(na1369_1), .IN3(na1249_1), .IN4(na1389_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y70 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2171_1 ( .OUT(na2171_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2167_1), .IN6(na2168_1), .IN7(na2169_1), + .IN8(na2170_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y77 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2172_1 ( .OUT(na2172_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1340_2), .IN6(na1260_2), .IN7(na1270_2), + .IN8(na1280_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y80 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2173_1 ( .OUT(na2173_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1320_2), .IN6(na1310_2), .IN7(na1300_2), + .IN8(na1290_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x152y75 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2174_1 ( .OUT(na2174_1), .IN1(na1330_2), .IN2(na1400_2), .IN3(na1350_1), .IN4(na1360_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y80 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2175_1 ( .OUT(na2175_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1380_2), .IN6(na1370_2), .IN7(na1250_2), + .IN8(na1390_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x152y76 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2176_1 ( .OUT(na2176_1), .IN1(na2172_1), .IN2(na2173_1), .IN3(na2174_1), .IN4(na2175_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y80 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2177_1 ( .OUT(na2177_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1281_1), .IN6(na1271_1), .IN7(na1261_1), + .IN8(na1341_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y75 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2178_1 ( .OUT(na2178_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1291_1), .IN6(na1301_2), .IN7(na1311_1), + .IN8(na1321_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x142y76 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2179_1 ( .OUT(na2179_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1351_1), .IN6(na1361_1), .IN7(na1331_1), + .IN8(na1401_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x142y81 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2180_1 ( .OUT(na2180_1), .IN1(na1251_1), .IN2(na1391_1), .IN3(na1381_1), .IN4(na1371_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x144y76 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2181_1 ( .OUT(na2181_1), .IN1(na2178_1), .IN2(na2177_1), .IN3(na2180_1), .IN4(na2179_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x112y33 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2182_1 ( .OUT(na2182_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1492_2), .IN6(na1412_2), .IN7(na1422_2), + .IN8(na1432_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x116y34 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2183_1 ( .OUT(na2183_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1452_2), .IN6(na1442_2), .IN7(na1472_2), + .IN8(na1462_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y33 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2184_1 ( .OUT(na2184_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1512_2), .IN6(na1502_2), .IN7(na1552_2), + .IN8(na1482_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x117y36 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2185_1 ( .OUT(na2185_1), .IN1(na1522_2), .IN2(na1532_1), .IN3(na1542_2), .IN4(na1402_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y34 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2186_1 ( .OUT(na2186_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2184_1), .IN6(na2185_1), .IN7(na2182_1), + .IN8(na2183_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x111y33 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2187_1 ( .OUT(na2187_1), .IN1(na1413_2), .IN2(na1493_1), .IN3(na1433_1), .IN4(na1423_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y38 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2188_1 ( .OUT(na2188_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1453_1), .IN6(na1443_1), .IN7(na1473_1), + .IN8(na1463_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x116y35 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2189_1 ( .OUT(na2189_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1513_1), .IN6(na1503_1), .IN7(na1553_2), + .IN8(na1483_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x114y36 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2190_1 ( .OUT(na2190_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1523_1), .IN6(na1533_1), .IN7(na1543_1), + .IN8(na1403_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x112y39 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2191_1 ( .OUT(na2191_1), .IN1(na2187_1), .IN2(na2188_1), .IN3(na2189_1), .IN4(na2190_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x110y39 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2192_1 ( .OUT(na2192_1), .IN1(na1424_2), .IN2(na1434_1), .IN3(na1494_2), .IN4(na1414_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y40 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2193_1 ( .OUT(na2193_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1454_2), .IN6(na1444_2), .IN7(na1474_2), + .IN8(na1464_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x113y43 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2194_1 ( .OUT(na2194_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1484_2), .IN6(na1554_2), .IN7(na1504_1), + .IN8(na1514_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x107y42 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2195_1 ( .OUT(na2195_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1534_2), .IN6(na1524_2), .IN7(na1404_2), + .IN8(na1544_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x111y42 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2196_1 ( .OUT(na2196_1), .IN1(na2194_1), .IN2(na2195_1), .IN3(na2192_1), .IN4(na2193_1), .IN5(na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y46 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2197_1 ( .OUT(na2197_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1425_1), .IN6(na1435_1), .IN7(na1495_1), + .IN8(na1415_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x112y47 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2198_1 ( .OUT(na2198_1), .IN1(na1475_1), .IN2(na1465_1), .IN3(na1455_2), .IN4(na1445_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x113y44 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2199_1 ( .OUT(na2199_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1485_1), .IN6(na1555_1), .IN7(na1505_1), + .IN8(na1515_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x109y47 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2200_1 ( .OUT(na2200_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1525_2), .IN6(na1535_1), .IN7(na1545_1), + .IN8(na1405_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x113y45 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2201_1 ( .OUT(na2201_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2200_1), .IN6(na2199_1), .IN7(na2198_1), + .IN8(na2197_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x106y58 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2202_1 ( .OUT(na2202_1), .IN1(na1416_2), .IN2(na1496_2), .IN3(na1436_2), .IN4(na1426_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x110y59 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2203_1 ( .OUT(na2203_1), .IN1(na1466_2), .IN2(na1476_1), .IN3(na1446_2), .IN4(na1456_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x107y58 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2204_1 ( .OUT(na2204_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1516_2), .IN6(na1506_2), .IN7(na1556_2), + .IN8(na1486_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x111y59 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2205_1 ( .OUT(na2205_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1406_1), .IN6(na1546_1), .IN7(na1536_2), + .IN8(na1526_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x108y58 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2206_1 ( .OUT(na2206_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2205_1), .IN6(na2204_1), .IN7(na2203_1), + .IN8(na2202_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x115y61 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2207_1 ( .OUT(na2207_1), .IN1(na1437_1), .IN2(na1427_2), .IN3(na1417_1), .IN4(na1497_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x119y62 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2208_1 ( .OUT(na2208_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1447_1), .IN6(na1457_1), .IN7(na1467_1), + .IN8(na1477_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x120y61 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2209_1 ( .OUT(na2209_1), .IN1(na1517_1), .IN2(na1507_1), .IN3(na1557_1), .IN4(na1487_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x118y62 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2210_1 ( .OUT(na2210_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1547_1), .IN6(na1407_1), .IN7(na1527_1), + .IN8(na1537_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y60 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2211_1 ( .OUT(na2211_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2207_1), .IN6(na2208_1), .IN7(na2209_1), + .IN8(na2210_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x105y64 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2212_1 ( .OUT(na2212_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1498_2), .IN6(na1418_2), .IN7(na1428_2), + .IN8(na1438_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x107y65 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2213_1 ( .OUT(na2213_1), .IN1(na1468_2), .IN2(na1478_2), .IN3(na1448_1), .IN4(na1458_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x110y66 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2214_1 ( .OUT(na2214_1), .IN1(na1508_2), .IN2(na1518_1), .IN3(na1488_2), .IN4(na1558_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x106y67 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2215_1 ( .OUT(na2215_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1538_2), .IN6(na1528_2), .IN7(na1408_2), + .IN8(na1548_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x112y64 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2216_1 ( .OUT(na2216_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2213_1), .IN6(na2212_1), .IN7(na2215_1), + .IN8(na2214_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x111y69 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2217_1 ( .OUT(na2217_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1429_1), .IN6(na1439_1), .IN7(na1499_1), + .IN8(na1419_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x111y74 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2218_1 ( .OUT(na2218_1), .IN1(na1449_1), .IN2(na1459_1), .IN3(na1469_2), .IN4(na1479_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x112y73 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2219_1 ( .OUT(na2219_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1559_1), .IN6(na1489_1), .IN7(na1519_1), + .IN8(na1509_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x110y76 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2220_1 ( .OUT(na2220_1), .IN1(na1529_1), .IN2(na1539_2), .IN3(na1549_1), .IN4(na1409_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y69 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2221_1 ( .OUT(na2221_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2217_1), .IN6(na2218_1), .IN7(na2219_1), + .IN8(na2220_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x109y82 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2222_1 ( .OUT(na2222_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1500_2), .IN6(na1420_1), .IN7(na1430_2), + .IN8(na1440_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x111y81 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2223_1 ( .OUT(na2223_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1470_2), .IN6(na1480_2), .IN7(na1450_2), + .IN8(na1460_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x116y84 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2224_1 ( .OUT(na2224_1), .IN1(na1510_2), .IN2(na1520_2), .IN3(na1490_1), .IN4(na1560_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x112y81 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2225_1 ( .OUT(na2225_1), .IN1(na1530_2), .IN2(na1540_2), .IN3(na1550_2), .IN4(na1410_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y81 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2226_1 ( .OUT(na2226_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2223_1), .IN6(na2222_1), .IN7(na2225_1), + .IN8(na2224_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y81 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2227_1 ( .OUT(na2227_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1441_2), .IN6(na1431_1), .IN7(na1421_1), + .IN8(na1501_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y76 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2228_1 ( .OUT(na2228_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1461_1), .IN6(na1451_1), .IN7(na1481_1), + .IN8(na1471_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x123y75 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2229_1 ( .OUT(na2229_1), .IN1(na1521_1), .IN2(na1511_2), .IN3(na1561_1), .IN4(na1491_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x123y78 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2230_1 ( .OUT(na2230_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1411_1), .IN6(na1551_1), .IN7(na1541_1), + .IN8(na1531_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x123y72 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2231_1 ( .OUT(na2231_1), .IN1(na2229_1), .IN2(na2230_1), .IN3(na2227_1), .IN4(na2228_1), .IN5(na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y31 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2232_1 ( .OUT(na2232_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1572_2), .IN6(na1652_2), .IN7(na1592_2), + .IN8(na1582_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x134y32 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2233_1 ( .OUT(na2233_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1622_2), .IN6(na1632_2), .IN7(na1602_1), + .IN8(na1612_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y31 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2234_1 ( .OUT(na2234_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1642_2), .IN6(na1712_2), .IN7(na1662_2), + .IN8(na1672_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x135y32 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2235_1 ( .OUT(na2235_1), .IN1(na1562_2), .IN2(na1702_2), .IN3(na1692_2), .IN4(na1682_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x131y34 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2236_1 ( .OUT(na2236_1), .IN1(na2234_1), .IN2(na2235_1), .IN3(na2232_1), .IN4(na2233_1), .IN5(na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x133y35 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2237_1 ( .OUT(na2237_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1593_1), .IN6(na1583_1), .IN7(na1573_1), + .IN8(na1653_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x135y36 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2238_1 ( .OUT(na2238_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1603_1), .IN6(na1613_1), .IN7(na1623_2), + .IN8(na1633_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x136y35 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2239_1 ( .OUT(na2239_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1673_1), .IN6(na1663_1), .IN7(na1713_1), + .IN8(na1643_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x136y34 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2240_1 ( .OUT(na2240_1), .IN1(na1683_1), .IN2(na1693_2), .IN3(na1703_1), .IN4(na1563_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x137y37 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2241_1 ( .OUT(na2241_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2237_1), .IN6(na2238_1), .IN7(na2239_1), + .IN8(na2240_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x127y44 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2242_1 ( .OUT(na2242_1), .IN1(na1574_1), .IN2(na1654_2), .IN3(na1594_2), .IN4(na1584_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x127y47 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2243_1 ( .OUT(na2243_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1634_2), .IN6(na1624_2), .IN7(na1614_2), + .IN8(na1604_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x128y44 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2244_1 ( .OUT(na2244_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1674_2), .IN6(na1664_2), .IN7(na1714_1), + .IN8(na1644_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x128y41 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2245_1 ( .OUT(na2245_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1684_2), .IN6(na1694_2), .IN7(na1704_2), + .IN8(na1564_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x126y44 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2246_1 ( .OUT(na2246_1), .IN1(na2243_1), .IN2(na2242_1), .IN3(na2245_1), .IN4(na2244_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x140y46 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2247_1 ( .OUT(na2247_1), .IN1(na1595_2), .IN2(na1585_1), .IN3(na1575_1), .IN4(na1655_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x140y45 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2248_1 ( .OUT(na2248_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1625_1), .IN6(na1635_1), .IN7(na1605_1), + .IN8(na1615_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x139y46 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2249_1 ( .OUT(na2249_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1675_1), .IN6(na1665_2), .IN7(na1715_1), + .IN8(na1645_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y45 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2250_1 ( .OUT(na2250_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1565_1), .IN6(na1705_1), .IN7(na1695_1), + .IN8(na1685_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x141y43 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2251_1 ( .OUT(na2251_1), .IN1(na2250_1), .IN2(na2249_1), .IN3(na2248_1), .IN4(na2247_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y62 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2252_1 ( .OUT(na2252_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1576_2), .IN6(na1656_2), .IN7(na1596_2), + .IN8(na1586_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x129y63 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2253_1 ( .OUT(na2253_1), .IN1(na1616_1), .IN2(na1606_2), .IN3(na1636_2), .IN4(na1626_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x134y64 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2254_1 ( .OUT(na2254_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1646_2), .IN6(na1716_2), .IN7(na1666_2), + .IN8(na1676_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y63 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2255_1 ( .OUT(na2255_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1566_2), .IN6(na1706_2), .IN7(na1696_2), + .IN8(na1686_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y61 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2256_1 ( .OUT(na2256_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2253_1), .IN6(na2252_1), .IN7(na2255_1), + .IN8(na2254_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x138y59 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2257_1 ( .OUT(na2257_1), .IN1(na1657_1), .IN2(na1577_1), .IN3(na1587_1), .IN4(na1597_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x138y62 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2258_1 ( .OUT(na2258_1), .IN1(na1607_1), .IN2(na1617_1), .IN3(na1627_1), .IN4(na1637_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x137y65 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2259_1 ( .OUT(na2259_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1677_1), .IN6(na1667_1), .IN7(na1717_1), + .IN8(na1647_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x139y64 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2260_1 ( .OUT(na2260_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1707_2), .IN6(na1567_2), .IN7(na1687_1), + .IN8(na1697_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x140y59 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2261_1 ( .OUT(na2261_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2259_1), .IN6(na2260_1), .IN7(na2257_1), + .IN8(na2258_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x126y70 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2262_1 ( .OUT(na2262_1), .IN1(na1588_1), .IN2(na1598_2), .IN3(na1658_1), .IN4(na1578_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x130y69 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2263_1 ( .OUT(na2263_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1608_2), .IN6(na1618_2), .IN7(na1628_2), + .IN8(na1638_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x129y72 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2264_1 ( .OUT(na2264_1), .IN1(na1718_2), .IN2(na1648_2), .IN3(na1678_2), .IN4(na1668_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y69 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2265_1 ( .OUT(na2265_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1698_2), .IN6(na1688_2), .IN7(na1568_2), + .IN8(na1708_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x124y68 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2266_1 ( .OUT(na2266_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2265_1), .IN6(na2264_1), .IN7(na2263_1), + .IN8(na2262_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x133y67 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2267_1 ( .OUT(na2267_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1599_1), .IN6(na1589_1), .IN7(na1579_1), + .IN8(na1659_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x133y68 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2268_1 ( .OUT(na2268_1), .IN1(na1629_1), .IN2(na1639_1), .IN3(na1609_2), .IN4(na1619_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x130y71 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2269_1 ( .OUT(na2269_1), .IN1(na1669_1), .IN2(na1679_2), .IN3(na1649_1), .IN4(na1719_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x132y72 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2270_1 ( .OUT(na2270_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1569_1), .IN6(na1709_1), .IN7(na1699_1), + .IN8(na1689_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x135y67 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2271_1 ( .OUT(na2271_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2267_1), .IN6(na2268_1), .IN7(na2269_1), + .IN8(na2270_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x131y73 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2272_1 ( .OUT(na2272_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1580_2), .IN6(na1660_2), .IN7(na1600_2), + .IN8(na1590_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x133y74 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2273_1 ( .OUT(na2273_1), .IN1(na1610_2), .IN2(na1620_2), .IN3(na1630_1), .IN4(na1640_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x138y75 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2274_1 ( .OUT(na2274_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1670_2), .IN6(na1680_2), .IN7(na1650_2), + .IN8(na1720_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x134y76 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2275_1 ( .OUT(na2275_1), .IN1(na1700_1), .IN2(na1690_2), .IN3(na1570_2), .IN4(na1710_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x133y72 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2276_1 ( .OUT(na2276_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2272_1), .IN6(na2273_1), .IN7(na2274_1), + .IN8(na2275_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y81 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2277_1 ( .OUT(na2277_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1661_1), .IN6(na1581_2), .IN7(na1591_1), + .IN8(na1601_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x145y82 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2278_1 ( .OUT(na2278_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1611_1), .IN6(na1621_1), .IN7(na1631_1), + .IN8(na1641_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x152y79 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2279_1 ( .OUT(na2279_1), .IN1(na1681_1), .IN2(na1671_1), .IN3(na1721_2), .IN4(na1651_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x148y82 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2280_1 ( .OUT(na2280_1), .IN1(na1691_1), .IN2(na1701_1), .IN3(na1711_1), .IN4(na1571_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y79 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2281_1 ( .OUT(na2281_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2277_1), .IN6(na2278_1), .IN7(na2279_1), + .IN8(na2280_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x155y36 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2282_1 ( .OUT(na2282_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1812_1), .IN6(na1732_2), .IN7(na1742_1), + .IN8(na1752_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y33 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2283_1 ( .OUT(na2283_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1762_2), .IN6(na1772_2), .IN7(na1782_2), + .IN8(na1792_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x152y32 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2284_1 ( .OUT(na2284_1), .IN1(na1822_2), .IN2(na1832_2), .IN3(na1802_2), .IN4(na1872_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y33 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2285_1 ( .OUT(na2285_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1842_2), .IN6(na1852_2), .IN7(na1862_2), + .IN8(na1722_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x154y36 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2286_1 ( .OUT(na2286_1), .IN1(na2283_1), .IN2(na2282_1), .IN3(na2285_1), .IN4(na2284_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x135y41 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2287_1 ( .OUT(na2287_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1813_1), .IN6(na1733_1), .IN7(na1743_1), + .IN8(na1753_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x139y40 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2288_1 ( .OUT(na2288_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1763_2), .IN6(na1773_1), .IN7(na1783_1), + .IN8(na1793_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x142y39 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2289_1 ( .OUT(na2289_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1823_1), .IN6(na1833_2), .IN7(na1803_1), + .IN8(na1873_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x138y38 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2290_1 ( .OUT(na2290_1), .IN1(na1843_1), .IN2(na1853_1), .IN3(na1863_1), .IN4(na1723_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x136y38 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2291_1 ( .OUT(na2291_1), .IN1(na2287_1), .IN2(na2288_1), .IN3(na2289_1), .IN4(na2290_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y40 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2292_1 ( .OUT(na2292_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1814_2), .IN6(na1734_2), .IN7(na1744_2), + .IN8(na1754_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y41 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2293_1 ( .OUT(na2293_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1794_2), .IN6(na1784_1), .IN7(na1774_2), + .IN8(na1764_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y36 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2294_1 ( .OUT(na2294_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1834_2), .IN6(na1824_2), .IN7(na1874_2), + .IN8(na1804_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x153y41 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2295_1 ( .OUT(na2295_1), .IN1(na1844_2), .IN2(na1854_1), .IN3(na1864_2), .IN4(na1724_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y40 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2296_1 ( .OUT(na2296_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2295_1), .IN6(na2294_1), .IN7(na2293_1), + .IN8(na2292_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x140y43 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2297_1 ( .OUT(na2297_1), .IN1(na1745_1), .IN2(na1755_1), .IN3(na1815_1), .IN4(na1735_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x144y46 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2298_1 ( .OUT(na2298_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1775_1), .IN6(na1765_1), .IN7(na1795_1), + .IN8(na1785_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y43 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2299_1 ( .OUT(na2299_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1825_1), .IN6(na1835_1), .IN7(na1805_2), + .IN8(na1875_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x143y48 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2300_1 ( .OUT(na2300_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1725_1), .IN6(na1865_1), .IN7(na1855_1), + .IN8(na1845_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x138y50 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2301_1 ( .OUT(na2301_1), .IN1(na2299_1), .IN2(na2300_1), .IN3(na2297_1), .IN4(na2298_1), .IN5(na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x152y46 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2302_1 ( .OUT(na2302_1), .IN1(na1816_2), .IN2(na1736_2), .IN3(na1746_2), .IN4(na1756_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x156y45 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2303_1 ( .OUT(na2303_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1766_2), .IN6(na1776_2), .IN7(na1786_2), + .IN8(na1796_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y48 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2304_1 ( .OUT(na2304_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1876_2), .IN6(na1806_2), .IN7(na1836_2), + .IN8(na1826_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y47 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2305_1 ( .OUT(na2305_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1856_2), .IN6(na1846_2), .IN7(na1726_2), + .IN8(na1866_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x154y50 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2306_1 ( .OUT(na2306_1), .IN1(na2305_1), .IN2(na2304_1), .IN3(na2303_1), .IN4(na2302_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x147y61 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2307_1 ( .OUT(na2307_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1737_1), .IN6(na1817_1), .IN7(na1757_1), + .IN8(na1747_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x153y62 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2308_1 ( .OUT(na2308_1), .IN1(na1767_1), .IN2(na1777_2), .IN3(na1787_1), .IN4(na1797_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y61 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2309_1 ( .OUT(na2309_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1837_1), .IN6(na1827_1), .IN7(na1877_1), + .IN8(na1807_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y62 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2310_1 ( .OUT(na2310_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1727_1), .IN6(na1867_1), .IN7(na1857_1), + .IN8(na1847_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y58 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2311_1 ( .OUT(na2311_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2307_1), .IN6(na2308_1), .IN7(na2309_1), + .IN8(na2310_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x147y65 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2312_1 ( .OUT(na2312_1), .IN1(na1758_2), .IN2(na1748_2), .IN3(na1738_2), .IN4(na1818_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x147y64 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2313_1 ( .OUT(na2313_1), .IN1(na1788_2), .IN2(na1798_1), .IN3(na1768_2), .IN4(na1778_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x152y65 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2314_1 ( .OUT(na2314_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1838_2), .IN6(na1828_2), .IN7(na1878_2), + .IN8(na1808_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x150y66 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2315_1 ( .OUT(na2315_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1858_2), .IN6(na1848_2), .IN7(na1728_1), + .IN8(na1868_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x148y64 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2316_1 ( .OUT(na2316_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2312_1), .IN6(na2313_1), .IN7(na2314_1), + .IN8(na2315_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x151y65 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2317_1 ( .OUT(na2317_1), .IN1(na1819_2), .IN2(na1739_1), .IN3(na1749_2), .IN4(na1759_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y66 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2318_1 ( .OUT(na2318_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1769_1), .IN6(na1779_1), .IN7(na1789_1), + .IN8(na1799_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x154y69 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2319_1 ( .OUT(na2319_1), .IN1(na1809_1), .IN2(na1879_1), .IN3(na1829_1), .IN4(na1839_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x156y70 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2320_1 ( .OUT(na2320_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1859_1), .IN6(na1849_1), .IN7(na1729_1), + .IN8(na1869_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y66 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2321_1 ( .OUT(na2321_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2317_1), .IN6(na2318_1), .IN7(na2319_1), + .IN8(na2320_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x153y78 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2322_1 ( .OUT(na2322_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1740_2), .IN6(na1820_2), .IN7(na1760_2), + .IN8(na1750_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x155y79 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2323_1 ( .OUT(na2323_1), .IN1(na1770_1), .IN2(na1780_2), .IN3(na1790_2), .IN4(na1800_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x156y78 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2324_1 ( .OUT(na2324_1), .IN1(na1880_2), .IN2(na1810_2), .IN3(na1840_1), .IN4(na1830_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y81 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2325_1 ( .OUT(na2325_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1860_2), .IN6(na1850_2), .IN7(na1730_2), + .IN8(na1870_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x154y76 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2326_1 ( .OUT(na2326_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2323_1), .IN6(na2322_1), .IN7(na2325_1), + .IN8(na2324_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x141y77 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2327_1 ( .OUT(na2327_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na1761_1), .IN6(na1751_1), .IN7(na1741_1), + .IN8(na1821_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x139y76 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2328_1 ( .OUT(na2328_1), .IN1(na1771_1), .IN2(na1781_1), .IN3(na1791_2), .IN4(na1801_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x140y73 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2329_1 ( .OUT(na2329_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na1811_1), .IN6(na1881_1), .IN7(na1831_1), + .IN8(na1841_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x142y78 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2330_1 ( .OUT(na2330_1), .IN1(na1861_2), .IN2(na1851_1), .IN3(na1731_1), .IN4(na1871_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x138y74 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2331_1 ( .OUT(na2331_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2327_1), .IN6(na2328_1), .IN7(na2329_1), + .IN8(na2330_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x108y32 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2332_1 ( .OUT(na2332_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na482_1), .IN6(na472_2), .IN7(na462_2), + .IN8(na402_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y31 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2333_1 ( .OUT(na2333_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na492_2), .IN6(na512_2), .IN7(na532_1), + .IN8(na552_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x113y32 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2334_1 ( .OUT(na2334_1), .IN1(na572_2), .IN2(na442_2), .IN3(na582_2), .IN4(na562_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x111y31 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2335_1 ( .OUT(na2335_1), .IN1(na542_2), .IN2(na522_2), .IN3(na502_2), .IN4(na452_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x115y37 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2336_1 ( .OUT(na2336_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2335_1), .IN6(na2334_1), .IN7(na2333_1), + .IN8(na2332_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x109y40 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2337_1 ( .OUT(na2337_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na403_1), .IN6(na463_2), .IN7(na473_1), + .IN8(na483_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x107y35 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2338_1 ( .OUT(na2338_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na493_2), .IN6(na513_1), .IN7(na533_1), + .IN8(na553_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x108y38 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2339_1 ( .OUT(na2339_1), .IN1(na563_1), .IN2(na583_1), .IN3(na443_1), .IN4(na573_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x106y37 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2340_1 ( .OUT(na2340_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na543_2), .IN6(na523_1), .IN7(na503_1), + .IN8(na453_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x113y37 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2341_1 ( .OUT(na2341_1), .IN1(na2338_1), .IN2(na2337_1), .IN3(na2340_1), .IN4(na2339_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x108y44 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2342_1 ( .OUT(na2342_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na404_2), .IN6(na464_2), .IN7(na474_1), + .IN8(na484_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x106y45 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2343_1 ( .OUT(na2343_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na554_1), .IN6(na534_2), .IN7(na514_2), + .IN8(na494_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x109y48 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2344_1 ( .OUT(na2344_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na574_2), .IN6(na444_1), .IN7(na584_1), + .IN8(na564_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x107y47 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2345_1 ( .OUT(na2345_1), .IN1(na544_2), .IN2(na524_2), .IN3(na504_1), .IN4(na454_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x105y46 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2346_1 ( .OUT(na2346_1), .IN1(na2345_1), .IN2(na2344_1), .IN3(na2343_1), .IN4(na2342_1), .IN5(~na2384_1), .IN6(1'b1), .IN7(~na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y49 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2347_1 ( .OUT(na2347_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na405_2), .IN6(na465_1), .IN7(na475_1), + .IN8(na485_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y52 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2348_1 ( .OUT(na2348_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na535_1), .IN6(na555_1), .IN7(na495_1), + .IN8(na515_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x107y49 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2349_1 ( .OUT(na2349_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na575_1), .IN6(na445_1), .IN7(na585_1), + .IN8(na565_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x109y54 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2350_1 ( .OUT(na2350_1), .IN1(na455_2), .IN2(na505_1), .IN3(na525_1), .IN4(na545_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x107y51 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2351_1 ( .OUT(na2351_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2349_1), .IN6(na2350_1), .IN7(na2347_1), + .IN8(na2348_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x109y53 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2352_1 ( .OUT(na2352_1), .IN1(na406_2), .IN2(na466_1), .IN3(na476_2), .IN4(na486_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x109y56 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2353_1 ( .OUT(na2353_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na536_2), .IN6(na556_2), .IN7(na496_1), + .IN8(na516_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x108y55 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2354_1 ( .OUT(na2354_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na586_2), .IN6(na566_2), .IN7(na576_1), + .IN8(na446_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y56 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2355_1 ( .OUT(na2355_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na526_1), .IN6(na546_2), .IN7(na456_2), + .IN8(na506_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x111y56 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2356_1 ( .OUT(na2356_1), .IN1(na2352_1), .IN2(na2353_1), .IN3(na2354_1), .IN4(na2355_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x109y61 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2357_1 ( .OUT(na2357_1), .IN1(na477_2), .IN2(na487_1), .IN3(na407_1), .IN4(na467_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x111y64 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2358_1 ( .OUT(na2358_1), .IN1(na2382_1), .IN2(1'b1), .IN3(~na2383_1), .IN4(1'b1), .IN5(na537_2), .IN6(na557_1), .IN7(na497_1), + .IN8(na517_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x112y63 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2359_1 ( .OUT(na2359_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na577_1), .IN6(na447_1), .IN7(na587_2), + .IN8(na567_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x112y66 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2360_1 ( .OUT(na2360_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na547_1), .IN6(na527_1), .IN7(na507_2), + .IN8(na457_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x113y62 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2361_1 ( .OUT(na2361_1), .IN1(na2357_1), .IN2(na2358_1), .IN3(na2359_1), .IN4(na2360_1), .IN5(na2384_1), .IN6(1'b1), .IN7(na2385_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x107y68 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2362_1 ( .OUT(na2362_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na468_2), .IN6(na408_1), .IN7(na488_1), + .IN8(na478_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x105y65 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2363_1 ( .OUT(na2363_1), .IN1(na538_2), .IN2(na558_2), .IN3(na498_2), .IN4(na518_1), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y70 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2364_1 ( .OUT(na2364_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na448_2), .IN6(na578_2), .IN7(na568_2), + .IN8(na588_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y67 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2365_1 ( .OUT(na2365_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na548_1), .IN6(na528_2), .IN7(na508_2), + .IN8(na458_2), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x113y66 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2366_1 ( .OUT(na2366_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2363_1), .IN6(na2362_1), .IN7(na2365_1), + .IN8(na2364_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x109y77 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2367_1 ( .OUT(na2367_1), .IN1(na409_1), .IN2(na469_1), .IN3(na479_1), .IN4(na489_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x107y76 80'h00_0018_00_0040_0C0F_A500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2368_1 ( .OUT(na2368_1), .IN1(na519_1), .IN2(na499_2), .IN3(na559_2), .IN4(na539_1), .IN5(~na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y81 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2369_1 ( .OUT(na2369_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na449_2), .IN6(na579_1), .IN7(na569_1), + .IN8(na589_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x110y80 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2370_1 ( .OUT(na2370_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na549_1), .IN6(na529_2), .IN7(na509_1), + .IN8(na459_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x109y76 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2371_1 ( .OUT(na2371_1), .IN1(na2384_1), .IN2(1'b1), .IN3(na2385_1), .IN4(1'b1), .IN5(na2367_1), .IN6(na2368_1), .IN7(na2369_1), + .IN8(na2370_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x110y71 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2372_1 ( .OUT(na2372_1), .IN1(na410_2), .IN2(na470_2), .IN3(na480_2), .IN4(na490_2), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x112y80 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2373_1 ( .OUT(na2373_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na520_2), .IN6(na500_2), .IN7(na560_2), + .IN8(na540_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x115y77 80'h00_0018_00_0040_0C0F_5500 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2374_1 ( .OUT(na2374_1), .IN1(na570_1), .IN2(na590_2), .IN3(na450_2), .IN4(na580_2), .IN5(~na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x111y80 80'h00_0018_00_0040_0AF0_00A5 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2375_1 ( .OUT(na2375_1), .IN1(~na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na530_2), .IN6(na550_2), .IN7(na460_1), + .IN8(na510_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x114y73 80'h00_0018_00_0040_0AF0_005A +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2376_1 ( .OUT(na2376_1), .IN1(na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2374_1), .IN6(na2375_1), .IN7(na2372_1), + .IN8(na2373_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x122y84 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2377_1 ( .OUT(na2377_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na411_2), .IN6(na471_2), .IN7(na481_1), + .IN8(na491_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x118y79 80'h00_0018_00_0040_0C0F_5A00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2378_1 ( .OUT(na2378_1), .IN1(na541_1), .IN2(na561_1), .IN3(na501_1), .IN4(na521_2), .IN5(na2382_1), .IN6(1'b1), .IN7(~na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4a//// x121y78 80'h00_0018_00_0040_0C0F_AA00 +C_MX4a #(.CPE_CFG (9'b0_0000_0000)) + _a2379_1 ( .OUT(na2379_1), .IN1(na581_2), .IN2(na451_1), .IN3(na591_1), .IN4(na571_1), .IN5(na2382_1), .IN6(1'b1), .IN7(na2383_1), + .IN8(1'b1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x117y75 80'h00_0018_00_0040_0AF0_00AA +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2380_1 ( .OUT(na2380_1), .IN1(na2382_1), .IN2(1'b1), .IN3(na2383_1), .IN4(1'b1), .IN5(na551_2), .IN6(na531_1), .IN7(na511_1), + .IN8(na461_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_MX4b//// x120y75 80'h00_0018_00_0040_0AF0_0055 +C_MX4b #(.CPE_CFG (9'b0_0000_0000)) + _a2381_1 ( .OUT(na2381_1), .IN1(~na2384_1), .IN2(1'b1), .IN3(~na2385_1), .IN4(1'b1), .IN5(na2380_1), .IN6(na2379_1), .IN7(na2378_1), + .IN8(na2377_1), .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2382 ( .Y(na2382_1), .I(addr[0]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2383 ( .Y(na2383_1), .I(addr[1]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2384 ( .Y(na2384_1), .I(addr[2]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2385 ( .Y(na2385_1), .I(addr[3]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2386 ( .Y(na2386_1), .I(addr[4]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2387 ( .Y(na2387_1), .I(addr[5]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2388 ( .Y(na2388_1), .I(addr[6]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2389 ( .Y(na2389_1), .I(addr[7]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000090)) + _a2390 ( .Y(na2390_1), .I(clk) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2391 ( .O(rdat[0]), .A(na2504_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2392 ( .O(rdat[1]), .A(na2505_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2393 ( .O(rdat[2]), .A(na2506_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2394 ( .O(rdat[3]), .A(na2507_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2395 ( .O(rdat[4]), .A(na2508_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2396 ( .O(rdat[5]), .A(na2509_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2397 ( .O(rdat[6]), .A(na2510_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2398 ( .O(rdat[7]), .A(na2511_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2399 ( .O(rdat[8]), .A(na2512_10) ); +CPE_OBF #(.BUF_CFG (72'h000000000100010900)) + _a2400 ( .O(rdat[9]), .A(na2513_10) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2401 ( .Y(na2401_1), .I(wdat[0]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2402 ( .Y(na2402_1), .I(wdat[1]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2403 ( .Y(na2403_1), .I(wdat[2]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2404 ( .Y(na2404_1), .I(wdat[3]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2405 ( .Y(na2405_1), .I(wdat[4]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2406 ( .Y(na2406_1), .I(wdat[5]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2407 ( .Y(na2407_1), .I(wdat[6]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2408 ( .Y(na2408_1), .I(wdat[7]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2409 ( .Y(na2409_1), .I(wdat[8]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2410 ( .Y(na2410_1), .I(wdat[9]) ); +CPE_IBF #(.BUF_CFG (72'h000001000000000010)) + _a2411 ( .Y(na2411_1), .I(we) ); +// C_AND///AND/ x130y45 80'h00_0078_00_0000_0C88_AACA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2412_1 ( .OUT(na2412_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na5_2), .IN6(1'b1), .IN7(na2036_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2412_4 ( .OUT(na2412_2), .IN1(na5_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1986_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x135y44 80'h00_0018_00_0000_0CEE_0700 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2413_1 ( .OUT(na2413_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na2514_2), .IN6(~na2236_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +GLBOUT #(.GLBOUT_CFG (64'h0000_0000_0000_0010)) + _a2414 ( .GLB0(na2414_1), .GLB1(_d3), .GLB2(_d4), .GLB3(_d5), .CLK_FB0(_d6), .CLK_FB1(_d7), .CLK_FB2(_d8), .CLK_FB3(_d9), + .CLK0_0(1'b0), .CLK0_90(1'b0), .CLK0_180(1'b0), .CLK0_270(1'b0), .CLK0_BYP(na2_1), .CLK1_0(1'b0), .CLK1_90(1'b0), + .CLK1_180(1'b0), .CLK1_270(1'b0), .CLK1_BYP(1'b0), .CLK2_0(1'b0), .CLK2_90(1'b0), .CLK2_180(1'b0), .CLK2_270(1'b0), + .CLK2_BYP(1'b0), .CLK3_0(1'b0), .CLK3_90(1'b0), .CLK3_180(1'b0), .CLK3_270(1'b0), .CLK3_BYP(1'b0), .USR_GLB0(1'b0), + .USR_GLB1(1'b0), .USR_GLB2(1'b0), .USR_GLB3(1'b0), .USR_FB0(1'b0), .USR_FB1(1'b0), .USR_FB2(1'b0), .USR_FB3(1'b0) ); +// C_///OR/ x130y46 80'h00_0060_00_0000_0C0E_FF53 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2415_4 ( .OUT(na2415_2), .IN1(1'b0), .IN2(~na2186_1), .IN3(~na7_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x132y44 80'h00_0018_00_0000_0C88_CCFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2416_1 ( .OUT(na2416_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4_2), .IN7(1'b1), .IN8(na2086_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x122y61 80'h00_0060_00_0000_0C08_FF33 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2417_4 ( .OUT(na2417_2), .IN1(1'b1), .IN2(~na2386_1), .IN3(1'b1), .IN4(~na2388_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x144y44 80'h00_0078_00_0000_0C88_F8CA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2422_1 ( .OUT(na2422_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na13_2), .IN6(na1891_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2422_4 ( .OUT(na2422_2), .IN1(na13_1), .IN2(1'b1), .IN3(1'b1), .IN4(na1941_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x131y48 80'h00_0018_00_0000_0CEE_0700 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2423_1 ( .OUT(na2423_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na5_1), .IN6(~na1991_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x131y47 80'h00_0060_00_0000_0C0E_FF35 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2425_4 ( .OUT(na2425_2), .IN1(~na5_2), .IN2(1'b0), .IN3(1'b0), .IN4(~na2041_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x125y45 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2426_1 ( .OUT(na2426_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na2517_2), .IN7(na2191_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x128y47 80'h00_0078_00_0000_0C88_F8AA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2431_1 ( .OUT(na2431_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na5_2), .IN6(na2046_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2431_4 ( .OUT(na2431_2), .IN1(na5_1), .IN2(1'b1), .IN3(na1996_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x129y50 80'h00_0060_00_0000_0C0E_FF33 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2432_4 ( .OUT(na2432_2), .IN1(1'b0), .IN2(~na4_1), .IN3(1'b0), .IN4(~na2246_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x121y49 80'h00_0018_00_0000_0CEE_5300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2434_1 ( .OUT(na2434_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na2196_1), .IN7(~na7_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x131y43 80'h00_0060_00_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2435_4 ( .OUT(na2435_2), .IN1(na2096_1), .IN2(na4_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x136y54 80'h00_0078_00_0000_0C88_CAF8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2440_1 ( .OUT(na2440_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na13_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1901_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2440_4 ( .OUT(na2440_2), .IN1(na13_1), .IN2(na1951_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x126y49 80'h00_0018_00_0000_0CEE_3500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2441_1 ( .OUT(na2441_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na5_1), .IN6(1'b0), .IN7(1'b0), .IN8(~na2001_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x125y50 80'h00_0060_00_0000_0C0E_FF07 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2443_4 ( .OUT(na2443_2), .IN1(~na2051_1), .IN2(~na2516_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x124y49 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2444_1 ( .OUT(na2444_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2201_1), .IN6(1'b1), .IN7(na7_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x122y52 80'h00_0078_00_0000_0C88_F8CA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2449_1 ( .OUT(na2449_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na5_2), .IN6(na2056_1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2449_4 ( .OUT(na2449_2), .IN1(na5_1), .IN2(1'b1), .IN3(1'b1), .IN4(na2006_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x132y57 80'h00_0060_00_0000_0C0E_FF07 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2450_4 ( .OUT(na2450_2), .IN1(~na2256_1), .IN2(~na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x125y53 80'h00_0018_00_0000_0CEE_7000 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2452_1 ( .OUT(na2452_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(~na7_1), .IN8(~na2206_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x128y52 80'h00_0060_00_0000_0C08_FFF8 +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2453_4 ( .OUT(na2453_2), .IN1(na2106_1), .IN2(na4_2), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x124y55 80'h00_0078_00_0000_0C88_F8AA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2458_1 ( .OUT(na2458_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2111_1), .IN6(na4_2), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2458_4 ( .OUT(na2458_2), .IN1(na5_1), .IN2(1'b1), .IN3(na2011_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x137y58 80'h00_0018_00_0000_0CEE_5300 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2459_1 ( .OUT(na2459_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(~na4_1), .IN7(~na2261_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x125y55 80'h00_0060_00_0000_0C0E_FF55 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2461_4 ( .OUT(na2461_2), .IN1(~na5_2), .IN2(1'b0), .IN3(~na2061_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x125y59 80'h00_0018_00_0000_0C88_8FFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2462_1 ( .OUT(na2462_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(na7_1), .IN8(na2211_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x129y64 80'h00_0078_00_0000_0C88_ACF8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2467_1 ( .OUT(na2467_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4_2), .IN7(na2116_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2467_4 ( .OUT(na2467_2), .IN1(na5_1), .IN2(na2016_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x127y61 80'h00_0060_00_0000_0C0E_FF33 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2468_4 ( .OUT(na2468_2), .IN1(1'b0), .IN2(~na4_1), .IN3(1'b0), .IN4(~na2266_1), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x126y63 80'h00_0018_00_0000_0CEE_3500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2470_1 ( .OUT(na2470_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na5_2), .IN6(1'b0), .IN7(1'b0), .IN8(~na2066_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x122y63 80'h00_0060_00_0000_0C08_FF8F +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2471_4 ( .OUT(na2471_2), .IN1(1'b1), .IN2(1'b1), .IN3(na7_1), .IN4(na2216_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x124y63 80'h00_0078_00_0000_0C88_ACF8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2476_1 ( .OUT(na2476_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4_2), .IN7(na2121_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2476_4 ( .OUT(na2476_2), .IN1(na5_1), .IN2(na2021_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x136y64 80'h00_0018_00_0000_0CEE_0700 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2477_1 ( .OUT(na2477_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na2271_1), .IN6(~na4_1), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x125y64 80'h00_0060_00_0000_0C0E_FF07 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2479_4 ( .OUT(na2479_2), .IN1(~na2071_1), .IN2(~na2516_2), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x125y64 80'h00_0018_00_0000_0C88_AAFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2480_1 ( .OUT(na2480_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na2221_1), .IN6(1'b1), .IN7(na7_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x126y66 80'h00_0078_00_0000_0C88_CACA +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2485_1 ( .OUT(na2485_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na5_2), .IN6(1'b1), .IN7(1'b1), .IN8(na2076_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2485_4 ( .OUT(na2485_2), .IN1(na5_1), .IN2(1'b1), .IN3(1'b1), .IN4(na2026_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x140y69 80'h00_0060_00_0000_0C0E_FF07 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2486_4 ( .OUT(na2486_2), .IN1(~na2515_2), .IN2(~na2276_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x127y68 80'h00_0018_00_0000_0CEE_5500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2488_1 ( .OUT(na2488_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na2226_1), .IN6(1'b0), .IN7(~na7_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x140y65 80'h00_0060_00_0000_0C08_FFCC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2489_4 ( .OUT(na2489_2), .IN1(1'b1), .IN2(na4_2), .IN3(1'b1), .IN4(na2126_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND///AND/ x135y68 80'h00_0078_00_0000_0C88_CAF8 +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2494_1 ( .OUT(na2494_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(na13_2), .IN6(1'b1), .IN7(1'b1), .IN8(na1931_1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2494_4 ( .OUT(na2494_2), .IN1(na13_1), .IN2(na1981_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_OR//// x130y65 80'h00_0018_00_0000_0CEE_5500 +C_OR #(.CPE_CFG (9'b0_0000_0000)) + _a2495_1 ( .OUT(na2495_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(~na5_1), .IN6(1'b0), .IN7(~na2031_1), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_///OR/ x134y70 80'h00_0060_00_0000_0C0E_FF53 +C_OR #(.CPE_CFG (9'b0_1000_0000)) + _a2497_4 ( .OUT(na2497_2), .IN1(1'b0), .IN2(~na2231_1), .IN3(~na7_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_AND//// x134y66 80'h00_0018_00_0000_0C88_ACFF +C_AND #(.CPE_CFG (9'b0_0000_0000)) + _a2498_1 ( .OUT(na2498_1), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(na4_2), .IN7(na2131_1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +// C_Route1//// x130y58 80'h00_0018_00_0050_0C66_0000 +C_Route1 #(.CPE_CFG (9'b0_0001_0000)) + _a2503_1 ( .OUT(na2503_1), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0), + .CINX(1'b0), .CINY1(na279_4), .PINX(1'b0), .PINY1(1'b0) ); +// C_///AND/ x160y27 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2504_4 ( .OUT(na2504_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na1_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2504_6 ( .RAM_O2(na2504_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2504_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y31 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2505_4 ( .OUT(na2505_2), .IN1(na18_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2505_6 ( .RAM_O2(na2505_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2505_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y35 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2506_4 ( .OUT(na2506_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na25_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2506_6 ( .RAM_O2(na2506_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2506_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y39 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2507_4 ( .OUT(na2507_2), .IN1(1'b1), .IN2(1'b1), .IN3(na32_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2507_6 ( .RAM_O2(na2507_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2507_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y43 80'h08_0060_00_0000_0C08_FFAF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2508_4 ( .OUT(na2508_2), .IN1(1'b1), .IN2(1'b1), .IN3(na39_1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2508_6 ( .RAM_O2(na2508_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2508_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y47 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2509_4 ( .OUT(na2509_2), .IN1(na46_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2509_6 ( .RAM_O2(na2509_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2509_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y51 80'h08_0060_00_0000_0C08_FFFA +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2510_4 ( .OUT(na2510_2), .IN1(na53_1), .IN2(1'b1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2510_6 ( .RAM_O2(na2510_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2510_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y55 80'h08_0060_00_0000_0C08_FFFC +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2511_4 ( .OUT(na2511_2), .IN1(1'b1), .IN2(na60_1), .IN3(1'b1), .IN4(1'b1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2511_6 ( .RAM_O2(na2511_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2511_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y59 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2512_4 ( .OUT(na2512_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na67_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2512_6 ( .RAM_O2(na2512_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2512_2), .COMP_OUT(1'b0) ); +// C_///AND/ x160y69 80'h08_0060_00_0000_0C08_FFCF +C_AND #(.CPE_CFG (9'b0_1000_0000)) + _a2513_4 ( .OUT(na2513_2), .IN1(1'b1), .IN2(1'b1), .IN3(1'b1), .IN4(na74_1), .IN5(1'b1), .IN6(1'b1), .IN7(1'b1), .IN8(1'b1), + .CINX(1'b0), .CINY1(1'b0), .PINX(1'b0), .PINY1(1'b0) ); +C_CPlines #(.CPE_CFG (19'h0_0000)) + _a2513_6 ( .RAM_O2(na2513_10), .CINX(1'b0), .CINY1(1'b0), .CINY2(1'b0), .PINX(1'b0), .PINY1(1'b0), .PINY2(1'b0), .OUT1(1'b0), + .OUT2(na2513_2), .COMP_OUT(1'b0) ); +// C_////Bridge x137y43 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2514_5 ( .OUT(na2514_2), .IN1(1'b0), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x141y69 80'h00_00A1_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2515_5 ( .OUT(na2515_2), .IN1(1'b0), .IN2(na4_1), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x127y56 80'h00_00A0_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2516_5 ( .OUT(na2516_2), .IN1(na5_2), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x127y46 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2517_5 ( .OUT(na2517_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na7_1), .IN8(1'b0) ); +// C_////Bridge x124y66 80'h00_00A6_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2518_5 ( .OUT(na2518_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(na10_1), .IN8(1'b0) ); +// C_////Bridge x121y59 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2519_5 ( .OUT(na2519_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na277_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x137y58 80'h00_00A3_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2520_5 ( .OUT(na2520_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(na277_2), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x137y56 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2521_5 ( .OUT(na2521_2), .IN1(1'b0), .IN2(1'b0), .IN3(na279_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x129y60 80'h00_00A2_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2522_5 ( .OUT(na2522_2), .IN1(1'b0), .IN2(1'b0), .IN3(na279_1), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(1'b0) ); +// C_////Bridge x133y51 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2523_5 ( .OUT(na2523_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na2449_1) ); +// C_////Bridge x134y57 80'h00_00A7_00_0000_0C00_FFFF +C_Bridge #(.CPE_CFG (9'bX_0000_1001)) + _a2524_5 ( .OUT(na2524_2), .IN1(1'b0), .IN2(1'b0), .IN3(1'b0), .IN4(1'b0), .IN5(1'b0), .IN6(1'b0), .IN7(1'b0), .IN8(na2503_1) ); +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/README.md b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/README.md new file mode 100644 index 0000000000000000000000000000000000000000..6b946bc60751aab6aa8d6928ec9bdca5e60c78b9 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/2.LUTRAM_stress_test/README.md @@ -0,0 +1,84 @@ +# LUTRAM_Stress_Test - FPGA's distributed memory capacity +## * WORK IN PROGRESS * UNDER CONSTRUCTION * +> WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN' + +An interesting twist on the CCGM1A1 is that there are no distributed memory primitives provided. This is due to multiple reasons, one being the required added complexity for decoding logic since LUT trees are used in place of classic LUTs. Instead, GateMate emulates distributed memory with flip-flops and a few muxes. Hereby we present a test for FPGAs distributed RAM capacity, expecting to examine GateMates lack of integrated LUTRAM. + +The primary motivation for examining this benchmark arises when evaluating the **portability** of other designs, as various porting attempts are likely. If the FPGA struggles to emulate a substantial amount of distributed RAM, switching to Block RAM necessitates **retiming** the entire design, which is an inconvenience. + +## Testing strategy +16x10 distributed RAM is generated in a loop, specifically so the number of outputs and inputs stays the same from the top level module, employing an output read mux, and input address decoder. This test is design to assess the LUTRAM capabilites of the different FPGA vendors, coupled with their own propriatary tools, using a generic test which hides away the vendor-specific primitives. + +![figure](0.doc/drawing.jpg) + +## Results and analysis +### Gowin GW2AR-18C - 255 modules +Tool settings: `Placer-1 priority to routability, Router-0 default, max fanout 23` + +Synthesis maximum numbers: + + - 314 modules instantiated + - Logic elements 15058/20736 + - 11170 LUT + - 648 RAM16S4 SSRAM + - 15680/15750 DFF + Error: Failed to place 10767 REG(s) + +PnR included maximum numbers: + + - 255 modules instantiated + - Logic elements 10346/20736 + - 6458 LUT + - 648 RAM16S4 SSRAM + - 8000/15750 DFF + Error: Failed to place 145 REG(s) + + +### CologneChip CCGM1A1 - 24 modules +Tool settings: `om-3 (speed), tm-3(worst timing, best routability)` + +Synthesis only maximum numbers: N/A because the number of primitives used obtained by synhtesis isn't easily mappable to the final number of CPEs used which is known only after PnR. + + + +PnR included maximum numbers: + + - 24 modules instantiated + - Logic elements 2255/20480 + - 1600/15750 DFF + FATAL ERROR: CPE_OUTMUX congestion at Component 333 with 353 + +### Conclusion +With only 24 modules instantiated before routing fails, the CCGM1A1 is severely underperforming for its weight class. For context, an 18k LUT4 Gowin FPGA would offer roughly ten times the capacity—even though the device in question seemingly has more resources. Moreover, these 24 modules only amount to 3,840 bits (480 bytes). This implies that even small distributed memories might need to be migrated to block RAMs and the design re-timed. + +It’s important to note that these results do not yet clearly define the boundaries of what’s plausible. One key variable remains: **Why did place-and-route (PnR) fail?** As indicated by the utilization figures, the CCGM1A1 is extremely underutilized, failing at just 10% of the available DFFs. This suggests that the issue lies not with the memory resources, but with limitations imposed by the routing tools and architecture. + +Another concern arises: if a 250-input multiplexer fails during routing, what does that say about our place-and-route tools and routing architecture? Notably, a 250-input mux is common in CPU designs for handling write-backs, also consider that a complete 32x32 register file requires a 1024-input mux! + +Since this test hit a wall, we conducted a similar, yet less routing-constrained more memory-oriented [test](https://github.com/chili-chips-ba/openCologne/tree/main/8.StressTest/3.LUTRAM_adjusted_stress_test). We chose to include this test despite it not fully addressing the distributed memory capacity. It serves instead as a case illustrating the limitations of the toolchain and architecture. + + + +## Reproduction steps +### Prerequsites +Gowin and CologneChip propriatary toolchains for Synthesis and Place and Route. Optionally, for simulation and verifying Verilator + GtkWave. +### Build steps +The top module provides a parameter `LUTRAM16X10` which is to set the number of 16x10 modules instantiated in the design. Once set, to run the GateMate toolchain run the following commands: +``` +cd 3.build +make hw_all +``` +Afterwards, check the `3.build/log/impl.log` for the number of CPE used or the exact error provided. Gowin propriatary toolchain is provided in GUI form only, start the project, run synhtesis and PnR, and check the Synhtesis report. + +If for any reason you want to simulate the design run: +``` +cd 2.sim +make +``` +Post-synthesis and post-pnr sims are avaliable also in iverilog and verilator, check the makefile for further information. diff --git a/chili-chips-ba_openCologne/8.StressTest/3.LUTRAM_adjusted_stress_test/README.md b/chili-chips-ba_openCologne/8.StressTest/3.LUTRAM_adjusted_stress_test/README.md new file mode 100644 index 0000000000000000000000000000000000000000..c3bb86e78c488b9d07aa82fd51a60c0047715435 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/3.LUTRAM_adjusted_stress_test/README.md @@ -0,0 +1,21 @@ +# LUTRAM_adjusted_stress_Test - FPGA's distributed memory capacity w/o heavy routing +## * WORK IN PROGRESS * UNDER CONSTRUCTION * +> WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN' + +This test is a sequel to a previous test. It's highly recommended to review that test before proceeding. Unlike the original, this version reduces routing congestion by focusing solely on memory implementation. This approach isolates the internal memory performance from the effects of the router and architecture. +## Testing strategy +We eliminated the wide output multiplexer and concatenated the 10-bit outputs via an XOR gate at each LUTRAM output. Additionally, we removed the LSB address inputs in favor of a one-hot address encoding scheme. The resulting structure is illustrated in the figure below. This approach should significantly reduce routing congestion and enable testing of the maximum number of distributed RAM modules. However, despite these improvements, routing congestion errors may still occur due to the densely packed memory elements. +![drawing](0.doc/drawing.png) +## Results and analysis + +Despite the improvements, a routing error still occurs at 58% utilization. The test now fails at 55 LUTRAM instantiations, compared to 24 in the previous version increasing the distributed memory capacity by almost double. This indicates that while the bottleneck was reduced, it remains a critical issue. This experiment demonstrates that, under certain conditions, the CCGM1A1 architecture can support more LUTRAM than suggested by the original `LUTRAM_stress_test`, confirming that our routing constraints were correctly identified. + +``` +Utilization Report + + CPEs 11921 / 20480 ( 58.2 %) + ----------------------------------------------- + CPE Registers 8800 / 40960 ( 21.5 %) + Flip-flops 8800 + Latches 0 +``` diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/README.md b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/README.md new file mode 100644 index 0000000000000000000000000000000000000000..08a8f331e378e6748f6aa2a47b090bf48f7d4eab --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/README.md @@ -0,0 +1,77 @@ +# Veerwolves - daisy chain Veerwolf core SoCs +## * WORK IN PROGRESS * UNDER CONSTRUCTION * KNOWN ISSUES!!!!!!! +> WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN' + +This work was inspired by the Intel [whitepaper](https://cdrdv2-public.intel.com/833305/comparing-the-real-world-capacity-of-agilex-5-fpgas-whitepaper.pdf) comparing Intel Agilex 5 series to Lattice Avant-E, addressing true logic capacity of these FPGA families. In particular, it investigates how Cologne Chip's GateMate handles larger cores and explores the maximum number of these that can be integrated into a daisy chain configuration. Given that a 222k LUT6 FPGA can accommodate roughly 18 cores, successfully fitting even one or two cores would be considered a considerable achievement. + +## Testing strategy +We'll quickly explain the benchmark setup and what it aims to achieve, for a more detailed explanation please refer to this [whitepaper](https://cdrdv2-public.intel.com/833305/comparing-the-real-world-capacity-of-agilex-5-fpgas-whitepaper.pdf). This test realizes a daisy-chain serial SoC connection via UART (as shown in the figure below), with the maximum number of SoCs instantiated being the output metric. + +Unlike Corescore, this design features a more homogenous logic mapping (Corescore was just a lot of independent cores feeding into a wide mux). Each SoC incorporates several interconnect conversions—primarily from AXI to WB and back—which are confined locally due to the daisy chain configuration. This setup exemplifies the FPGA’s short-wiring capabilities and raises questions about how densely the logic can be packed and what impact this may have on timing performance. + +![SOC](0.doc/veerwolf-chain.png) + + +The VeeR EL2 CPU serves as the core of the SoC and integrates the previously described AXI and WB conversions. This RV32IMC-compliant RISC-V core, complete with a branch predictor, represents the first instance of the CCGM1A1 handling multiplication and implementing a more complex architecture. The figure below illustrates the CPU design. + +![veerwolves](0.doc/veerwolf_core.png) +## Build steps +FuseSoC is again the framework for generating an arbitrary number of cores. Add FuseSoC libraries after entering this folder: +``` +cd 4.veerwolves +fusesoc library add veerwolf ./ +``` +Generating the bitstream for CologneChip is done by running: +``` +fusesoc run --target=gatemate_pack veerwolf +``` + + +## Results and analysis +``` +CPE Component Statistics: + OR 3202 8% + AND 17296 45% + XOR 1553 4% + ANDOR 1 0% + ORAND 5170 13% + ICOMP 260 0% + MX2a 3873 10% + MX4a 2764 7% + ANDXOR 146 0% + ADDF 182 0% + ADDF2 2458 6% + ADDFx 7 0% + ADDF2x 42 0% + MULT 684 1% + MULTFa 13 0% + MULTFb 11 0% + Route1 53 0% + -------- +Sum of COMB: 37715 + + D 8879 95% + DST 32 0% + C_0_1 268 2% + RAM_I1 70 0% + RAM_I2 59 0% + -------- +Sum of SEQ: 9308 + +Sum of all: 47023 + + +Number of CPEs on layer 1 / 2: 8828 / 8444 +Number of CPEs using layer 1 + 2: 16356 +Number of needed CPEs / available CPEs: 25184 / 20480 +Number of needed IO-Pins / available IO-Pins: 36 / 144 +ChipSize: X: 160 Y: 128 + +FPGA too small for circuit! +``` + +Comparable Gowin Arora GW2AR-18C device doesn't fare any better in this test: +``` +ERROR (RP0006) : The number(28340(26008 LUTs, 2284 ALUs, 0 ROM16s, 8 SSRAMs)) of logic in the design exceeds the resource limit(20736) of current device +GowinSynthesis finish +``` \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/config/common_defines.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/config/common_defines.vh new file mode 100644 index 0000000000000000000000000000000000000000..915c3bcaacb29538f9bf68572f0d8a3f5e98ad57 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/config/common_defines.vh @@ -0,0 +1,242 @@ +// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE +// This is an automatically generated file by tarik on Čet 06 Mar 2025 11:08:14 CET +// +// cmd: veer -unset=assert_on -set=reset_vec=0x80000000 -set=fpga_optimize=1 -set=ret_stack_size=2 -set=btb_size=32 -set=bht_size=128 -set=dccm_size=16 -set=dccm_num_banks=2 -set=iccm_enable=0 -set=icache_enable=0 -set=dccm_enable=0 -set=pic_total_int=8 +// +`define RV_ROOT "/home/tarik/0.git-repo/openCologne/8.StressTest/4.veerwolves/cores/chipsalliance.org_cores_VeeR_EL2_1.4" +`define RV_PIC_MEIGWCLR_COUNT 8 +`define RV_PIC_MEIPL_OFFSET 'h0000 +`define RV_PIC_MEIPT_COUNT 8 +`define RV_PIC_MEIGWCLR_OFFSET 'h5000 +`define RV_PIC_MEIGWCTRL_OFFSET 'h4000 +`define RV_PIC_OFFSET 10'hc0000 +`define RV_PIC_MPICCFG_COUNT 1 +`define RV_PIC_MPICCFG_MASK 'h1 +`define RV_PIC_TOTAL_INT_PLUS1 9 +`define RV_PIC_BITS 15 +`define RV_PIC_MEIPT_OFFSET 'h3004 +`define RV_PIC_MEIPL_COUNT 8 +`define RV_PIC_SIZE 32 +`define RV_PIC_MEIE_COUNT 8 +`define RV_PIC_MPICCFG_OFFSET 'h3000 +`define RV_PIC_MEIPT_MASK 'h0 +`define RV_PIC_MEIP_MASK 'h0 +`define RV_PIC_MEIP_OFFSET 'h1000 +`define RV_PIC_TOTAL_INT 8 +`define RV_PIC_MEIGWCLR_MASK 'h0 +`define RV_PIC_MEIPL_MASK 'hf +`define RV_PIC_MEIE_OFFSET 'h2000 +`define RV_PIC_MEIE_MASK 'h1 +`define RV_PIC_REGION 4'hf +`define RV_PIC_BASE_ADDR 32'hf00c0000 +`define RV_PIC_MEIP_COUNT 1 +`define RV_PIC_MEIGWCTRL_COUNT 8 +`define RV_PIC_INT_WORDS 1 +`define RV_PIC_MEIGWCTRL_MASK 'h3 +`define TOP tb_top +`define RV_EXT_ADDRWIDTH 32 +`define RV_BUILD_AXI4 1 +`define RV_STERR_ROLLBACK 0 +`define RV_EXT_DATAWIDTH 64 +`define CLOCK_PERIOD 100 +`define RV_LDERR_ROLLBACK 1 +`define RV_BUILD_AXI_NATIVE 1 +`define CPU_TOP `RV_TOP.swerv +`define SDVT_AHB 0 +`define RV_TOP `TOP.rvtop +`define TEC_RV_ICG clockhdr +`define RV_ICCM_BANK_INDEX_LO 4 +`define RV_ICCM_SIZE_64 +`define RV_ICCM_REGION 4'he +`define RV_ICCM_EADR 32'hee00ffff +`define RV_ICCM_NUM_BANKS 4 +`define RV_ICCM_RESERVED 'h1000 +`define RV_ICCM_BANK_BITS 2 +`define RV_ICCM_NUM_BANKS_4 +`define RV_ICCM_BANK_HI 3 +`define RV_ICCM_DATA_CELL ram_4096x39 +`define RV_ICCM_OFFSET 10'he000000 +`define RV_ICCM_SIZE 64 +`define RV_ICCM_SADR 32'hee000000 +`define RV_ICCM_BITS 16 +`define RV_ICCM_ROWS 4096 +`define RV_ICCM_INDEX_BITS 12 +`define RV_DCCM_DATA_CELL ram_2048x39 +`define RV_DCCM_FDATA_WIDTH 39 +`define RV_DCCM_BANK_BITS 1 +`define RV_DCCM_RESERVED 'h1400 +`define RV_DCCM_OFFSET 28'h40000 +`define RV_DCCM_SIZE_16 +`define RV_DCCM_WIDTH_BITS 2 +`define RV_LSU_SB_BITS 14 +`define RV_DCCM_NUM_BANKS 2 +`define RV_DCCM_EADR 32'hf0043fff +`define RV_DCCM_REGION 4'hf +`define RV_DCCM_INDEX_BITS 11 +`define RV_DCCM_ECC_WIDTH 7 +`define RV_DCCM_DATA_WIDTH 32 +`define RV_DCCM_SIZE 16 +`define RV_DCCM_ROWS 2048 +`define RV_DCCM_NUM_BANKS_2 +`define RV_DCCM_BITS 14 +`define RV_DCCM_BYTE_WIDTH 4 +`define RV_DCCM_SADR 32'hf0040000 +`define REGWIDTH 32 +`define RV_TARGET default +`define RV_BHT_ADDR_HI 7 +`define RV_BHT_ADDR_LO 2 +`define RV_BHT_ARRAY_DEPTH 64 +`define RV_BHT_GHR_RANGE 5:0 +`define RV_BHT_SIZE 128 +`define RV_BHT_GHR_HASH_1 1 +`define RV_BHT_HASH_STRING {ghr[5:4], hashin[5:2]^ghr[4-1:0]} // cf1 +`define RV_BHT_GHR_SIZE 6 +`define RV_BTB_INDEX2_HI 9 +`define RV_BTB_INDEX1_LO 2 +`define RV_BTB_ARRAY_DEPTH 16 +`define RV_BTB_SIZE 32 +`define RV_BTB_INDEX3_HI 13 +`define RV_BTB_FOLD2_INDEX_HASH 0 +`define RV_BTB_BTAG_FOLD 1 +`define RV_BTB_ADDR_HI 5 +`define RV_BTB_TOFFSET_SIZE 12 +`define RV_BTB_INDEX2_LO 6 +`define RV_BTB_INDEX1_HI 5 +`define RV_BTB_BTAG_SIZE 9 +`define RV_BTB_ENABLE 1 +`define RV_BTB_INDEX3_LO 10 +`define RV_BTB_ADDR_LO 2 +`define RV_XLEN 32 +`define RV_LSU_NUM_NBLOAD_WIDTH 2 +`define RV_BITMANIP_ZBB 1 +`define RV_BITMANIP_ZBA 1 +`define RV_NO_ICCM_NO_ICACHE 1 +`define RV_BITMANIP_ZBP 0 +`define RV_BITMANIP_ZBR 0 +`define RV_DIV_NEW 1 +`define RV_LSU_STBUF_DEPTH 4 +`define RV_BITMANIP_ZBF 0 +`define RV_FPGA_OPTIMIZE 1 +`define RV_DMA_BUF_DEPTH 5 +`define RV_DIV_BIT 4 +`define RV_LSU2DMA 0 +`define RV_TIMER_LEGAL_EN 1 +`define RV_BITMANIP_ZBE 0 +`define RV_FAST_INTERRUPT_REDIRECT 0 +`define RV_LSU_NUM_NBLOAD 4 +`define RV_BITMANIP_ZBC 1 +`define RV_BITMANIP_ZBS 1 +`define RV_CONFIG_KEY 32'hdeadbeef +`define RV_NMI_VEC 'h11110000 +`define RV_UNUSED_REGION5 'h30000000 +`define RV_UNUSED_REGION6 'h20000000 +`define RV_DEBUG_SB_MEM 'ha0580000 +`define RV_EXTERNAL_DATA 'hc0580000 +`define RV_UNUSED_REGION2 'h60000000 +`define RV_UNUSED_REGION7 'h10000000 +`define RV_UNUSED_REGION3 'h50000000 +`define RV_UNUSED_REGION8 'h00000000 +`define RV_UNUSED_REGION4 'h40000000 +`define RV_EXTERNAL_DATA_1 'hb0000000 +`define RV_UNUSED_REGION1 'h70000000 +`define RV_SERIALIO 'hd0580000 +`define RV_UNUSED_REGION0 'h90000000 +`define RV_RET_STACK_SIZE 2 +`define RV_NUMIREGS 32 +`define RV_ICACHE_TAG_LO 13 +`define RV_ICACHE_DATA_INDEX_LO 4 +`define RV_ICACHE_BANK_BITS 1 +`define RV_ICACHE_NUM_LINES 256 +`define RV_ICACHE_ECC 1 +`define RV_ICACHE_TAG_NUM_BYPASS 2 +`define RV_ICACHE_LN_SZ 64 +`define RV_ICACHE_DATA_DEPTH 512 +`define RV_ICACHE_BANK_LO 3 +`define RV_ICACHE_TAG_NUM_BYPASS_WIDTH 2 +`define RV_ICACHE_SIZE 16 +`define RV_ICACHE_SCND_LAST 6 +`define RV_ICACHE_BEAT_ADDR_HI 5 +`define RV_ICACHE_INDEX_HI 12 +`define RV_ICACHE_TAG_INDEX_LO 6 +`define RV_ICACHE_NUM_BYPASS 2 +`define RV_ICACHE_DATA_WIDTH 64 +`define RV_ICACHE_TAG_DEPTH 128 +`define RV_ICACHE_DATA_CELL ram_512x71 +`define RV_ICACHE_NUM_BYPASS_WIDTH 2 +`define RV_ICACHE_WAYPACK 1 +`define RV_ICACHE_FDATA_WIDTH 71 +`define RV_ICACHE_NUM_LINES_BANK 64 +`define RV_ICACHE_NUM_LINES_WAY 128 +`define RV_ICACHE_BANKS_WAY 2 +`define RV_ICACHE_NUM_BEATS 8 +`define RV_ICACHE_STATUS_BITS 1 +`define RV_ICACHE_BANK_HI 3 +`define RV_ICACHE_BANK_WIDTH 8 +`define RV_ICACHE_BEAT_BITS 3 +`define RV_ICACHE_BYPASS_ENABLE 1 +`define RV_ICACHE_TAG_CELL ram_128x25 +`define RV_ICACHE_TAG_BYPASS_ENABLE 1 +`define RV_ICACHE_2BANKS 1 +`define RV_ICACHE_NUM_WAYS 2 +`define RV_INST_ACCESS_ENABLE1 1'h0 +`define RV_DATA_ACCESS_MASK1 'hffffffff +`define RV_DATA_ACCESS_MASK4 'hffffffff +`define RV_INST_ACCESS_ADDR1 'h00000000 +`define RV_INST_ACCESS_ADDR4 'h00000000 +`define RV_INST_ACCESS_ENABLE3 1'h0 +`define RV_DATA_ACCESS_ENABLE5 1'h0 +`define RV_DATA_ACCESS_ENABLE6 1'h0 +`define RV_INST_ACCESS_ENABLE5 1'h0 +`define RV_INST_ACCESS_ENABLE6 1'h0 +`define RV_DATA_ACCESS_ENABLE3 1'h0 +`define RV_DATA_ACCESS_ADDR4 'h00000000 +`define RV_DATA_ACCESS_ADDR1 'h00000000 +`define RV_INST_ACCESS_MASK4 'hffffffff +`define RV_INST_ACCESS_MASK1 'hffffffff +`define RV_DATA_ACCESS_ENABLE1 1'h0 +`define RV_DATA_ACCESS_ADDR7 'h00000000 +`define RV_DATA_ACCESS_ADDR2 'h00000000 +`define RV_INST_ACCESS_MASK0 'hffffffff +`define RV_DATA_ACCESS_ADDR0 'h00000000 +`define RV_INST_ACCESS_ENABLE0 1'h0 +`define RV_DATA_ACCESS_ENABLE7 1'h0 +`define RV_INST_ACCESS_MASK2 'hffffffff +`define RV_INST_ACCESS_MASK7 'hffffffff +`define RV_DATA_ACCESS_MASK2 'hffffffff +`define RV_DATA_ACCESS_MASK7 'hffffffff +`define RV_INST_ACCESS_ENABLE7 1'h0 +`define RV_DATA_ACCESS_ENABLE0 1'h0 +`define RV_INST_ACCESS_ADDR0 'h00000000 +`define RV_DATA_ACCESS_MASK0 'hffffffff +`define RV_INST_ACCESS_ADDR7 'h00000000 +`define RV_INST_ACCESS_ADDR2 'h00000000 +`define RV_INST_ACCESS_ENABLE2 1'h0 +`define RV_DATA_ACCESS_ADDR6 'h00000000 +`define RV_INST_ACCESS_MASK6 'hffffffff +`define RV_DATA_ACCESS_MASK6 'hffffffff +`define RV_INST_ACCESS_ADDR6 'h00000000 +`define RV_DATA_ACCESS_ENABLE2 1'h0 +`define RV_INST_ACCESS_ENABLE4 1'h0 +`define RV_INST_ACCESS_MASK5 'hffffffff +`define RV_DATA_ACCESS_ADDR3 'h00000000 +`define RV_INST_ACCESS_MASK3 'hffffffff +`define RV_DATA_ACCESS_ADDR5 'h00000000 +`define RV_DATA_ACCESS_MASK3 'hffffffff +`define RV_INST_ACCESS_ADDR5 'h00000000 +`define RV_DATA_ACCESS_MASK5 'hffffffff +`define RV_INST_ACCESS_ADDR3 'h00000000 +`define RV_DATA_ACCESS_ENABLE4 1'h0 +`define RV_RESET_VEC 'h80000000 +`define RV_DMA_BUS_TAG 1 +`define RV_BUS_PRTY_DEFAULT 2'h3 +`define RV_LSU_BUS_ID 1 +`define RV_SB_BUS_PRTY 2 +`define RV_IFU_BUS_TAG 3 +`define RV_LSU_BUS_PRTY 2 +`define RV_SB_BUS_TAG 1 +`define RV_DMA_BUS_PRTY 2 +`define RV_DMA_BUS_ID 1 +`define RV_IFU_BUS_ID 1 +`define RV_IFU_BUS_PRTY 2 +`define RV_SB_BUS_ID 1 +`define RV_LSU_BUS_TAG 3 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/config/el2_pdef.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/config/el2_pdef.vh new file mode 100644 index 0000000000000000000000000000000000000000..ee6848f7da0b08dc70f01a6eaa452cb179e00efe --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/config/el2_pdef.vh @@ -0,0 +1,175 @@ +typedef struct packed { + bit [7:0] BHT_ADDR_HI; + bit [5:0] BHT_ADDR_LO; + bit [14:0] BHT_ARRAY_DEPTH; + bit [4:0] BHT_GHR_HASH_1; + bit [7:0] BHT_GHR_SIZE; + bit [15:0] BHT_SIZE; + bit [4:0] BITMANIP_ZBA; + bit [4:0] BITMANIP_ZBB; + bit [4:0] BITMANIP_ZBC; + bit [4:0] BITMANIP_ZBE; + bit [4:0] BITMANIP_ZBF; + bit [4:0] BITMANIP_ZBP; + bit [4:0] BITMANIP_ZBR; + bit [4:0] BITMANIP_ZBS; + bit [8:0] BTB_ADDR_HI; + bit [5:0] BTB_ADDR_LO; + bit [12:0] BTB_ARRAY_DEPTH; + bit [4:0] BTB_BTAG_FOLD; + bit [8:0] BTB_BTAG_SIZE; + bit [4:0] BTB_ENABLE; + bit [4:0] BTB_FOLD2_INDEX_HASH; + bit [4:0] BTB_FULLYA; + bit [8:0] BTB_INDEX1_HI; + bit [8:0] BTB_INDEX1_LO; + bit [8:0] BTB_INDEX2_HI; + bit [8:0] BTB_INDEX2_LO; + bit [8:0] BTB_INDEX3_HI; + bit [8:0] BTB_INDEX3_LO; + bit [13:0] BTB_SIZE; + bit [8:0] BTB_TOFFSET_SIZE; + bit BUILD_AHB_LITE; + bit [4:0] BUILD_AXI4; + bit [4:0] BUILD_AXI_NATIVE; + bit [5:0] BUS_PRTY_DEFAULT; + bit [35:0] DATA_ACCESS_ADDR0; + bit [35:0] DATA_ACCESS_ADDR1; + bit [35:0] DATA_ACCESS_ADDR2; + bit [35:0] DATA_ACCESS_ADDR3; + bit [35:0] DATA_ACCESS_ADDR4; + bit [35:0] DATA_ACCESS_ADDR5; + bit [35:0] DATA_ACCESS_ADDR6; + bit [35:0] DATA_ACCESS_ADDR7; + bit [4:0] DATA_ACCESS_ENABLE0; + bit [4:0] DATA_ACCESS_ENABLE1; + bit [4:0] DATA_ACCESS_ENABLE2; + bit [4:0] DATA_ACCESS_ENABLE3; + bit [4:0] DATA_ACCESS_ENABLE4; + bit [4:0] DATA_ACCESS_ENABLE5; + bit [4:0] DATA_ACCESS_ENABLE6; + bit [4:0] DATA_ACCESS_ENABLE7; + bit [35:0] DATA_ACCESS_MASK0; + bit [35:0] DATA_ACCESS_MASK1; + bit [35:0] DATA_ACCESS_MASK2; + bit [35:0] DATA_ACCESS_MASK3; + bit [35:0] DATA_ACCESS_MASK4; + bit [35:0] DATA_ACCESS_MASK5; + bit [35:0] DATA_ACCESS_MASK6; + bit [35:0] DATA_ACCESS_MASK7; + bit [6:0] DCCM_BANK_BITS; + bit [8:0] DCCM_BITS; + bit [6:0] DCCM_BYTE_WIDTH; + bit [9:0] DCCM_DATA_WIDTH; + bit [6:0] DCCM_ECC_WIDTH; + bit [4:0] DCCM_ENABLE; + bit [9:0] DCCM_FDATA_WIDTH; + bit [7:0] DCCM_INDEX_BITS; + bit [8:0] DCCM_NUM_BANKS; + bit [7:0] DCCM_REGION; + bit [35:0] DCCM_SADR; + bit [13:0] DCCM_SIZE; + bit [5:0] DCCM_WIDTH_BITS; + bit [6:0] DIV_BIT; + bit [4:0] DIV_NEW; + bit [6:0] DMA_BUF_DEPTH; + bit [8:0] DMA_BUS_ID; + bit [5:0] DMA_BUS_PRTY; + bit [7:0] DMA_BUS_TAG; + bit [4:0] FAST_INTERRUPT_REDIRECT; + bit [4:0] ICACHE_2BANKS; + bit [6:0] ICACHE_BANK_BITS; + bit [6:0] ICACHE_BANK_HI; + bit [5:0] ICACHE_BANK_LO; + bit [7:0] ICACHE_BANK_WIDTH; + bit [6:0] ICACHE_BANKS_WAY; + bit [7:0] ICACHE_BEAT_ADDR_HI; + bit [7:0] ICACHE_BEAT_BITS; + bit [4:0] ICACHE_BYPASS_ENABLE; + bit [17:0] ICACHE_DATA_DEPTH; + bit [6:0] ICACHE_DATA_INDEX_LO; + bit [10:0] ICACHE_DATA_WIDTH; + bit [4:0] ICACHE_ECC; + bit [4:0] ICACHE_ENABLE; + bit [10:0] ICACHE_FDATA_WIDTH; + bit [8:0] ICACHE_INDEX_HI; + bit [10:0] ICACHE_LN_SZ; + bit [7:0] ICACHE_NUM_BEATS; + bit [7:0] ICACHE_NUM_BYPASS; + bit [7:0] ICACHE_NUM_BYPASS_WIDTH; + bit [6:0] ICACHE_NUM_WAYS; + bit [4:0] ICACHE_ONLY; + bit [7:0] ICACHE_SCND_LAST; + bit [12:0] ICACHE_SIZE; + bit [6:0] ICACHE_STATUS_BITS; + bit [4:0] ICACHE_TAG_BYPASS_ENABLE; + bit [16:0] ICACHE_TAG_DEPTH; + bit [6:0] ICACHE_TAG_INDEX_LO; + bit [8:0] ICACHE_TAG_LO; + bit [7:0] ICACHE_TAG_NUM_BYPASS; + bit [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH; + bit [4:0] ICACHE_WAYPACK; + bit [6:0] ICCM_BANK_BITS; + bit [8:0] ICCM_BANK_HI; + bit [8:0] ICCM_BANK_INDEX_LO; + bit [8:0] ICCM_BITS; + bit [4:0] ICCM_ENABLE; + bit [4:0] ICCM_ICACHE; + bit [7:0] ICCM_INDEX_BITS; + bit [8:0] ICCM_NUM_BANKS; + bit [4:0] ICCM_ONLY; + bit [7:0] ICCM_REGION; + bit [35:0] ICCM_SADR; + bit [13:0] ICCM_SIZE; + bit [4:0] IFU_BUS_ID; + bit [5:0] IFU_BUS_PRTY; + bit [7:0] IFU_BUS_TAG; + bit [35:0] INST_ACCESS_ADDR0; + bit [35:0] INST_ACCESS_ADDR1; + bit [35:0] INST_ACCESS_ADDR2; + bit [35:0] INST_ACCESS_ADDR3; + bit [35:0] INST_ACCESS_ADDR4; + bit [35:0] INST_ACCESS_ADDR5; + bit [35:0] INST_ACCESS_ADDR6; + bit [35:0] INST_ACCESS_ADDR7; + bit [4:0] INST_ACCESS_ENABLE0; + bit [4:0] INST_ACCESS_ENABLE1; + bit [4:0] INST_ACCESS_ENABLE2; + bit [4:0] INST_ACCESS_ENABLE3; + bit [4:0] INST_ACCESS_ENABLE4; + bit [4:0] INST_ACCESS_ENABLE5; + bit [4:0] INST_ACCESS_ENABLE6; + bit [4:0] INST_ACCESS_ENABLE7; + bit [35:0] INST_ACCESS_MASK0; + bit [35:0] INST_ACCESS_MASK1; + bit [35:0] INST_ACCESS_MASK2; + bit [35:0] INST_ACCESS_MASK3; + bit [35:0] INST_ACCESS_MASK4; + bit [35:0] INST_ACCESS_MASK5; + bit [35:0] INST_ACCESS_MASK6; + bit [35:0] INST_ACCESS_MASK7; + bit [4:0] LOAD_TO_USE_PLUS1; + bit [4:0] LSU2DMA; + bit [4:0] LSU_BUS_ID; + bit [5:0] LSU_BUS_PRTY; + bit [7:0] LSU_BUS_TAG; + bit [8:0] LSU_NUM_NBLOAD; + bit [6:0] LSU_NUM_NBLOAD_WIDTH; + bit [8:0] LSU_SB_BITS; + bit [7:0] LSU_STBUF_DEPTH; + bit [4:0] NO_ICCM_NO_ICACHE; + bit [4:0] PIC_2CYCLE; + bit [35:0] PIC_BASE_ADDR; + bit [8:0] PIC_BITS; + bit [7:0] PIC_INT_WORDS; + bit [7:0] PIC_REGION; + bit [12:0] PIC_SIZE; + bit [11:0] PIC_TOTAL_INT; + bit [12:0] PIC_TOTAL_INT_PLUS1; + bit [7:0] RET_STACK_SIZE; + bit [4:0] SB_BUS_ID; + bit [5:0] SB_BUS_PRTY; + bit [7:0] SB_BUS_TAG; + bit [4:0] TIMER_LEGAL_EN; +} el2_param_t; + diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/edalize_yosys_procs.tcl b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/edalize_yosys_procs.tcl new file mode 100644 index 0000000000000000000000000000000000000000..9b6345c108d77dd2d147447e022296898cd09583 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/edalize_yosys_procs.tcl @@ -0,0 +1,25 @@ +proc read_files {} { + read_verilog -sv out.v +} + +proc set_defines {} { +set defines {{CCGM 1}} + +foreach d ${defines} { + set key [lindex $d 0] + set val [lindex $d 1] + verilog_defines "-D$key=$val" +}} + +proc set_incdirs {} { +verilog_defaults -add -Isrc/veerwolf-veer_el2_pack_config_0.7.5 -Isrc/pulp-platform.org__common_cells_1.20.0/include -Isrc/uart16550_1.5.5-r1/rtl/verilog -Isrc/wb_common_1.0.3 -Isrc/pulp-platform.org__axi_0.25.0/include -Isrc/veerwolf-intercon_0.7.5 -Isrc/veerwolf-wb_nospi_intercon_0.7.5} + +proc set_params {} { +chparam -set cpu_type {"EL2"} veerwolf_pack_cc} + +proc synth {top} { +synth_gatemate -nomx8 -top $top +} + +set top veerwolf_pack_cc +set name veerwolf_0.7.5 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/axi_intercon.v b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/axi_intercon.v new file mode 100644 index 0000000000000000000000000000000000000000..08a93a8dafdc5ae854c8e05d36242077699b3808 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/axi_intercon.v @@ -0,0 +1,474 @@ +// THIS FILE IS AUTOGENERATED BY axi_intercon_gen +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module axi_intercon + (input wire clk_i, + input wire rst_ni, + input wire [2:0] i_ifu_arid, + input wire [31:0] i_ifu_araddr, + input wire [7:0] i_ifu_arlen, + input wire [2:0] i_ifu_arsize, + input wire [1:0] i_ifu_arburst, + input wire i_ifu_arlock, + input wire [3:0] i_ifu_arcache, + input wire [2:0] i_ifu_arprot, + input wire [3:0] i_ifu_arregion, + input wire [3:0] i_ifu_arqos, + input wire i_ifu_arvalid, + output wire o_ifu_arready, + output wire [2:0] o_ifu_rid, + output wire [63:0] o_ifu_rdata, + output wire [1:0] o_ifu_rresp, + output wire o_ifu_rlast, + output wire o_ifu_rvalid, + input wire i_ifu_rready, + input wire [3:0] i_lsu_awid, + input wire [31:0] i_lsu_awaddr, + input wire [7:0] i_lsu_awlen, + input wire [2:0] i_lsu_awsize, + input wire [1:0] i_lsu_awburst, + input wire i_lsu_awlock, + input wire [3:0] i_lsu_awcache, + input wire [2:0] i_lsu_awprot, + input wire [3:0] i_lsu_awregion, + input wire [3:0] i_lsu_awqos, + input wire i_lsu_awvalid, + output wire o_lsu_awready, + input wire [3:0] i_lsu_arid, + input wire [31:0] i_lsu_araddr, + input wire [7:0] i_lsu_arlen, + input wire [2:0] i_lsu_arsize, + input wire [1:0] i_lsu_arburst, + input wire i_lsu_arlock, + input wire [3:0] i_lsu_arcache, + input wire [2:0] i_lsu_arprot, + input wire [3:0] i_lsu_arregion, + input wire [3:0] i_lsu_arqos, + input wire i_lsu_arvalid, + output wire o_lsu_arready, + input wire [63:0] i_lsu_wdata, + input wire [7:0] i_lsu_wstrb, + input wire i_lsu_wlast, + input wire i_lsu_wvalid, + output wire o_lsu_wready, + output wire [3:0] o_lsu_bid, + output wire [1:0] o_lsu_bresp, + output wire o_lsu_bvalid, + input wire i_lsu_bready, + output wire [3:0] o_lsu_rid, + output wire [63:0] o_lsu_rdata, + output wire [1:0] o_lsu_rresp, + output wire o_lsu_rlast, + output wire o_lsu_rvalid, + input wire i_lsu_rready, + input wire [0:0] i_sb_awid, + input wire [31:0] i_sb_awaddr, + input wire [7:0] i_sb_awlen, + input wire [2:0] i_sb_awsize, + input wire [1:0] i_sb_awburst, + input wire i_sb_awlock, + input wire [3:0] i_sb_awcache, + input wire [2:0] i_sb_awprot, + input wire [3:0] i_sb_awregion, + input wire [3:0] i_sb_awqos, + input wire i_sb_awvalid, + output wire o_sb_awready, + input wire [0:0] i_sb_arid, + input wire [31:0] i_sb_araddr, + input wire [7:0] i_sb_arlen, + input wire [2:0] i_sb_arsize, + input wire [1:0] i_sb_arburst, + input wire i_sb_arlock, + input wire [3:0] i_sb_arcache, + input wire [2:0] i_sb_arprot, + input wire [3:0] i_sb_arregion, + input wire [3:0] i_sb_arqos, + input wire i_sb_arvalid, + output wire o_sb_arready, + input wire [63:0] i_sb_wdata, + input wire [7:0] i_sb_wstrb, + input wire i_sb_wlast, + input wire i_sb_wvalid, + output wire o_sb_wready, + output wire [0:0] o_sb_bid, + output wire [1:0] o_sb_bresp, + output wire o_sb_bvalid, + input wire i_sb_bready, + output wire [0:0] o_sb_rid, + output wire [63:0] o_sb_rdata, + output wire [1:0] o_sb_rresp, + output wire o_sb_rlast, + output wire o_sb_rvalid, + input wire i_sb_rready, + output wire [5:0] o_io_awid, + output wire [31:0] o_io_awaddr, + output wire [7:0] o_io_awlen, + output wire [2:0] o_io_awsize, + output wire [1:0] o_io_awburst, + output wire o_io_awlock, + output wire [3:0] o_io_awcache, + output wire [2:0] o_io_awprot, + output wire [3:0] o_io_awregion, + output wire [3:0] o_io_awqos, + output wire o_io_awvalid, + input wire i_io_awready, + output wire [5:0] o_io_arid, + output wire [31:0] o_io_araddr, + output wire [7:0] o_io_arlen, + output wire [2:0] o_io_arsize, + output wire [1:0] o_io_arburst, + output wire o_io_arlock, + output wire [3:0] o_io_arcache, + output wire [2:0] o_io_arprot, + output wire [3:0] o_io_arregion, + output wire [3:0] o_io_arqos, + output wire o_io_arvalid, + input wire i_io_arready, + output wire [63:0] o_io_wdata, + output wire [7:0] o_io_wstrb, + output wire o_io_wlast, + output wire o_io_wvalid, + input wire i_io_wready, + input wire [5:0] i_io_bid, + input wire [1:0] i_io_bresp, + input wire i_io_bvalid, + output wire o_io_bready, + input wire [5:0] i_io_rid, + input wire [63:0] i_io_rdata, + input wire [1:0] i_io_rresp, + input wire i_io_rlast, + input wire i_io_rvalid, + output wire o_io_rready, + output wire [5:0] o_ram_awid, + output wire [31:0] o_ram_awaddr, + output wire [7:0] o_ram_awlen, + output wire [2:0] o_ram_awsize, + output wire [1:0] o_ram_awburst, + output wire o_ram_awlock, + output wire [3:0] o_ram_awcache, + output wire [2:0] o_ram_awprot, + output wire [3:0] o_ram_awregion, + output wire [3:0] o_ram_awqos, + output wire o_ram_awvalid, + input wire i_ram_awready, + output wire [5:0] o_ram_arid, + output wire [31:0] o_ram_araddr, + output wire [7:0] o_ram_arlen, + output wire [2:0] o_ram_arsize, + output wire [1:0] o_ram_arburst, + output wire o_ram_arlock, + output wire [3:0] o_ram_arcache, + output wire [2:0] o_ram_arprot, + output wire [3:0] o_ram_arregion, + output wire [3:0] o_ram_arqos, + output wire o_ram_arvalid, + input wire i_ram_arready, + output wire [63:0] o_ram_wdata, + output wire [7:0] o_ram_wstrb, + output wire o_ram_wlast, + output wire o_ram_wvalid, + input wire i_ram_wready, + input wire [5:0] i_ram_bid, + input wire [1:0] i_ram_bresp, + input wire i_ram_bvalid, + output wire o_ram_bready, + input wire [5:0] i_ram_rid, + input wire [63:0] i_ram_rdata, + input wire [1:0] i_ram_rresp, + input wire i_ram_rlast, + input wire i_ram_rvalid, + output wire o_ram_rready); + + + localparam int unsigned NoMasters = 32'd3; // How many Axi Masters there are + localparam int unsigned NoSlaves = 32'd2; // How many Axi Slaves there are + + // axi configuration + localparam int unsigned AxiIdWidthMasters = 32'd4; + localparam int unsigned AxiIdUsed = 32'd4; // Has to be <= AxiIdWidthMasters + localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMasters); + localparam int unsigned AxiAddrWidth = 32'd32; // Axi Address Width + localparam int unsigned AxiDataWidth = 32'd64; // Axi Data Width + localparam int unsigned AxiStrbWidth = AxiDataWidth / 8; + localparam int unsigned AxiUserWidth = 1; + localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ + + NoSlvPorts: NoMasters, + NoMstPorts: NoSlaves, + MaxMstTrans: 10, + MaxSlvTrans: 6, + FallThrough: 1'b0, + LatencyMode: axi_pkg::CUT_ALL_AX, + AxiIdWidthSlvPorts: AxiIdWidthMasters, + AxiIdUsedSlvPorts: AxiIdUsed, + AxiAddrWidth: AxiAddrWidth, + AxiDataWidth: AxiDataWidth, + NoAddrRules: NoSlaves + }; + + typedef logic [AxiIdWidthMasters-1:0] id_mst_t; + typedef logic [AxiIdWidthSlaves-1:0] id_slv_t; + typedef logic [AxiAddrWidth-1:0] addr_t; + typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr + typedef logic [AxiDataWidth-1:0] data_t; + typedef logic [AxiStrbWidth-1:0] strb_t; + typedef logic [AxiUserWidth-1:0] user_t; + + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_mst_t, id_mst_t, user_t) + `AXI_TYPEDEF_B_CHAN_T(b_chan_slv_t, id_slv_t, user_t) + + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t) + `AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_mst_t, data_t, id_mst_t, user_t) + `AXI_TYPEDEF_R_CHAN_T(r_chan_slv_t, data_t, id_slv_t, user_t) + + `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_mst_t, w_chan_t, ar_chan_mst_t) + `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_mst_t, r_chan_mst_t) + `AXI_TYPEDEF_REQ_T(mst_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t) + `AXI_TYPEDEF_RESP_T(mst_resp_t, b_chan_slv_t, r_chan_slv_t) + + localparam rule_t [1:0] AddrMap = '{ + '{idx: 32'd0, start_addr: 32'h80000000, end_addr: 32'h80004000}, + '{idx: 32'd1, start_addr: 32'h00000000, end_addr: 32'h08000000}}; + slv_req_t [2:0] masters_req; + slv_resp_t [2:0] masters_resp; + mst_req_t [1:0] slaves_req; + mst_resp_t [1:0] slaves_resp; + + //Master ifu + assign masters_req[0].aw.id = 4'd0; + assign masters_req[0].aw.addr = 32'd0; + assign masters_req[0].aw.len = 8'd0; + assign masters_req[0].aw.size = 3'd0; + assign masters_req[0].aw.burst = 2'd0; + assign masters_req[0].aw.lock = 1'd0; + assign masters_req[0].aw.cache = 4'd0; + assign masters_req[0].aw.prot = 3'd0; + assign masters_req[0].aw.region = 4'd0; + assign masters_req[0].aw.qos = 4'd0; + assign masters_req[0].aw.atop = 6'd0; + assign masters_req[0].aw_valid = 1'd0; + assign masters_req[0].ar.id = {1'd0,i_ifu_arid}; + assign masters_req[0].ar.addr = i_ifu_araddr; + assign masters_req[0].ar.len = i_ifu_arlen; + assign masters_req[0].ar.size = i_ifu_arsize; + assign masters_req[0].ar.burst = i_ifu_arburst; + assign masters_req[0].ar.lock = i_ifu_arlock; + assign masters_req[0].ar.cache = i_ifu_arcache; + assign masters_req[0].ar.prot = i_ifu_arprot; + assign masters_req[0].ar.region = i_ifu_arregion; + assign masters_req[0].ar.qos = i_ifu_arqos; + assign masters_req[0].ar_valid = i_ifu_arvalid; + assign o_ifu_arready = masters_resp[0].ar_ready; + assign masters_req[0].w.data = 64'd0; + assign masters_req[0].w.strb = 8'd0; + assign masters_req[0].w.last = 1'd0; + assign masters_req[0].w_valid = 1'd0; + assign masters_req[0].b_ready = 1'd0; + assign o_ifu_rid = masters_resp[0].r.id[2:0]; + assign o_ifu_rdata = masters_resp[0].r.data; + assign o_ifu_rresp = masters_resp[0].r.resp; + assign o_ifu_rlast = masters_resp[0].r.last; + assign o_ifu_rvalid = masters_resp[0].r_valid; + assign masters_req[0].r_ready = i_ifu_rready; + + //Master lsu + assign masters_req[1].aw.id = i_lsu_awid; + assign masters_req[1].aw.addr = i_lsu_awaddr; + assign masters_req[1].aw.len = i_lsu_awlen; + assign masters_req[1].aw.size = i_lsu_awsize; + assign masters_req[1].aw.burst = i_lsu_awburst; + assign masters_req[1].aw.lock = i_lsu_awlock; + assign masters_req[1].aw.cache = i_lsu_awcache; + assign masters_req[1].aw.prot = i_lsu_awprot; + assign masters_req[1].aw.region = i_lsu_awregion; + assign masters_req[1].aw.qos = i_lsu_awqos; + assign masters_req[1].aw.atop = 6'd0; + assign masters_req[1].aw_valid = i_lsu_awvalid; + assign o_lsu_awready = masters_resp[1].aw_ready; + assign masters_req[1].ar.id = i_lsu_arid; + assign masters_req[1].ar.addr = i_lsu_araddr; + assign masters_req[1].ar.len = i_lsu_arlen; + assign masters_req[1].ar.size = i_lsu_arsize; + assign masters_req[1].ar.burst = i_lsu_arburst; + assign masters_req[1].ar.lock = i_lsu_arlock; + assign masters_req[1].ar.cache = i_lsu_arcache; + assign masters_req[1].ar.prot = i_lsu_arprot; + assign masters_req[1].ar.region = i_lsu_arregion; + assign masters_req[1].ar.qos = i_lsu_arqos; + assign masters_req[1].ar_valid = i_lsu_arvalid; + assign o_lsu_arready = masters_resp[1].ar_ready; + assign masters_req[1].w.data = i_lsu_wdata; + assign masters_req[1].w.strb = i_lsu_wstrb; + assign masters_req[1].w.last = i_lsu_wlast; + assign masters_req[1].w_valid = i_lsu_wvalid; + assign o_lsu_wready = masters_resp[1].w_ready; + assign o_lsu_bid = masters_resp[1].b.id; + assign o_lsu_bresp = masters_resp[1].b.resp; + assign o_lsu_bvalid = masters_resp[1].b_valid; + assign masters_req[1].b_ready = i_lsu_bready; + assign o_lsu_rid = masters_resp[1].r.id; + assign o_lsu_rdata = masters_resp[1].r.data; + assign o_lsu_rresp = masters_resp[1].r.resp; + assign o_lsu_rlast = masters_resp[1].r.last; + assign o_lsu_rvalid = masters_resp[1].r_valid; + assign masters_req[1].r_ready = i_lsu_rready; + + //Master sb + assign masters_req[2].aw.id = {3'd0,i_sb_awid}; + assign masters_req[2].aw.addr = i_sb_awaddr; + assign masters_req[2].aw.len = i_sb_awlen; + assign masters_req[2].aw.size = i_sb_awsize; + assign masters_req[2].aw.burst = i_sb_awburst; + assign masters_req[2].aw.lock = i_sb_awlock; + assign masters_req[2].aw.cache = i_sb_awcache; + assign masters_req[2].aw.prot = i_sb_awprot; + assign masters_req[2].aw.region = i_sb_awregion; + assign masters_req[2].aw.qos = i_sb_awqos; + assign masters_req[2].aw.atop = 6'd0; + assign masters_req[2].aw_valid = i_sb_awvalid; + assign o_sb_awready = masters_resp[2].aw_ready; + assign masters_req[2].ar.id = {3'd0,i_sb_arid}; + assign masters_req[2].ar.addr = i_sb_araddr; + assign masters_req[2].ar.len = i_sb_arlen; + assign masters_req[2].ar.size = i_sb_arsize; + assign masters_req[2].ar.burst = i_sb_arburst; + assign masters_req[2].ar.lock = i_sb_arlock; + assign masters_req[2].ar.cache = i_sb_arcache; + assign masters_req[2].ar.prot = i_sb_arprot; + assign masters_req[2].ar.region = i_sb_arregion; + assign masters_req[2].ar.qos = i_sb_arqos; + assign masters_req[2].ar_valid = i_sb_arvalid; + assign o_sb_arready = masters_resp[2].ar_ready; + assign masters_req[2].w.data = i_sb_wdata; + assign masters_req[2].w.strb = i_sb_wstrb; + assign masters_req[2].w.last = i_sb_wlast; + assign masters_req[2].w_valid = i_sb_wvalid; + assign o_sb_wready = masters_resp[2].w_ready; + assign o_sb_bid = masters_resp[2].b.id[0:0]; + assign o_sb_bresp = masters_resp[2].b.resp; + assign o_sb_bvalid = masters_resp[2].b_valid; + assign masters_req[2].b_ready = i_sb_bready; + assign o_sb_rid = masters_resp[2].r.id[0:0]; + assign o_sb_rdata = masters_resp[2].r.data; + assign o_sb_rresp = masters_resp[2].r.resp; + assign o_sb_rlast = masters_resp[2].r.last; + assign o_sb_rvalid = masters_resp[2].r_valid; + assign masters_req[2].r_ready = i_sb_rready; + + //Slave io + assign o_io_awid = slaves_req[0].aw.id; + assign o_io_awaddr = slaves_req[0].aw.addr; + assign o_io_awlen = slaves_req[0].aw.len; + assign o_io_awsize = slaves_req[0].aw.size; + assign o_io_awburst = slaves_req[0].aw.burst; + assign o_io_awlock = slaves_req[0].aw.lock; + assign o_io_awcache = slaves_req[0].aw.cache; + assign o_io_awprot = slaves_req[0].aw.prot; + assign o_io_awregion = slaves_req[0].aw.region; + assign o_io_awqos = slaves_req[0].aw.qos; + assign o_io_awvalid = slaves_req[0].aw_valid; + assign slaves_resp[0].aw_ready = i_io_awready; + assign o_io_arid = slaves_req[0].ar.id; + assign o_io_araddr = slaves_req[0].ar.addr; + assign o_io_arlen = slaves_req[0].ar.len; + assign o_io_arsize = slaves_req[0].ar.size; + assign o_io_arburst = slaves_req[0].ar.burst; + assign o_io_arlock = slaves_req[0].ar.lock; + assign o_io_arcache = slaves_req[0].ar.cache; + assign o_io_arprot = slaves_req[0].ar.prot; + assign o_io_arregion = slaves_req[0].ar.region; + assign o_io_arqos = slaves_req[0].ar.qos; + assign o_io_arvalid = slaves_req[0].ar_valid; + assign slaves_resp[0].ar_ready = i_io_arready; + assign o_io_wdata = slaves_req[0].w.data; + assign o_io_wstrb = slaves_req[0].w.strb; + assign o_io_wlast = slaves_req[0].w.last; + assign o_io_wvalid = slaves_req[0].w_valid; + assign slaves_resp[0].w_ready = i_io_wready; + assign slaves_resp[0].b.id = i_io_bid; + assign slaves_resp[0].b.resp = i_io_bresp; + assign slaves_resp[0].b_valid = i_io_bvalid; + assign o_io_bready = slaves_req[0].b_ready; + assign slaves_resp[0].r.id = i_io_rid; + assign slaves_resp[0].r.data = i_io_rdata; + assign slaves_resp[0].r.resp = i_io_rresp; + assign slaves_resp[0].r.last = i_io_rlast; + assign slaves_resp[0].r_valid = i_io_rvalid; + assign o_io_rready = slaves_req[0].r_ready; + + //Slave ram + assign o_ram_awid = slaves_req[1].aw.id; + assign o_ram_awaddr = slaves_req[1].aw.addr; + assign o_ram_awlen = slaves_req[1].aw.len; + assign o_ram_awsize = slaves_req[1].aw.size; + assign o_ram_awburst = slaves_req[1].aw.burst; + assign o_ram_awlock = slaves_req[1].aw.lock; + assign o_ram_awcache = slaves_req[1].aw.cache; + assign o_ram_awprot = slaves_req[1].aw.prot; + assign o_ram_awregion = slaves_req[1].aw.region; + assign o_ram_awqos = slaves_req[1].aw.qos; + assign o_ram_awvalid = slaves_req[1].aw_valid; + assign slaves_resp[1].aw_ready = i_ram_awready; + assign o_ram_arid = slaves_req[1].ar.id; + assign o_ram_araddr = slaves_req[1].ar.addr; + assign o_ram_arlen = slaves_req[1].ar.len; + assign o_ram_arsize = slaves_req[1].ar.size; + assign o_ram_arburst = slaves_req[1].ar.burst; + assign o_ram_arlock = slaves_req[1].ar.lock; + assign o_ram_arcache = slaves_req[1].ar.cache; + assign o_ram_arprot = slaves_req[1].ar.prot; + assign o_ram_arregion = slaves_req[1].ar.region; + assign o_ram_arqos = slaves_req[1].ar.qos; + assign o_ram_arvalid = slaves_req[1].ar_valid; + assign slaves_resp[1].ar_ready = i_ram_arready; + assign o_ram_wdata = slaves_req[1].w.data; + assign o_ram_wstrb = slaves_req[1].w.strb; + assign o_ram_wlast = slaves_req[1].w.last; + assign o_ram_wvalid = slaves_req[1].w_valid; + assign slaves_resp[1].w_ready = i_ram_wready; + assign slaves_resp[1].b.id = i_ram_bid; + assign slaves_resp[1].b.resp = i_ram_bresp; + assign slaves_resp[1].b_valid = i_ram_bvalid; + assign o_ram_bready = slaves_req[1].b_ready; + assign slaves_resp[1].r.id = i_ram_rid; + assign slaves_resp[1].r.data = i_ram_rdata; + assign slaves_resp[1].r.resp = i_ram_rresp; + assign slaves_resp[1].r.last = i_ram_rlast; + assign slaves_resp[1].r_valid = i_ram_rvalid; + assign o_ram_rready = slaves_req[1].r_ready; + + +axi_xbar + #(.Cfg (xbar_cfg), + .ATOPs (1'b0), + .slv_aw_chan_t (aw_chan_mst_t), + .mst_aw_chan_t (aw_chan_slv_t), + .w_chan_t (w_chan_t), + .slv_b_chan_t (b_chan_mst_t), + .mst_b_chan_t (b_chan_slv_t), + .slv_ar_chan_t (ar_chan_mst_t), + .mst_ar_chan_t (ar_chan_slv_t), + .slv_r_chan_t (r_chan_mst_t), + .mst_r_chan_t (r_chan_slv_t), + .slv_req_t (slv_req_t), + .slv_resp_t (slv_resp_t), + .mst_req_t (mst_req_t), + .mst_resp_t (mst_resp_t), + .rule_t (rule_t)) + axi_xbar + (.clk_i (clk_i), + .rst_ni (rst_ni), + .test_i (1'b0), + .slv_ports_req_i (masters_req), + .slv_ports_resp_o (masters_resp), + .mst_ports_req_o (slaves_req), + .mst_ports_resp_i (slaves_resp), + .addr_map_i (AddrMap), + .en_default_mst_port_i (3'd0), + .default_mst_port_i ('0)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/axi_intercon.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/axi_intercon.vh new file mode 100644 index 0000000000000000000000000000000000000000..4a25f3205491cc2491787855d1c013b826133405 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/axi_intercon.vh @@ -0,0 +1,355 @@ +// THIS FILE IS AUTOGENERATED BY axi_intercon_gen +// ANY MANUAL CHANGES WILL BE LOST +wire [2:0] ifu_arid; +wire [31:0] ifu_araddr; +wire [7:0] ifu_arlen; +wire [2:0] ifu_arsize; +wire [1:0] ifu_arburst; +wire ifu_arlock; +wire [3:0] ifu_arcache; +wire [2:0] ifu_arprot; +wire [3:0] ifu_arregion; +wire [3:0] ifu_arqos; +wire ifu_arvalid; +wire ifu_arready; +wire [2:0] ifu_rid; +wire [63:0] ifu_rdata; +wire [1:0] ifu_rresp; +wire ifu_rlast; +wire ifu_rvalid; +wire ifu_rready; +wire [3:0] lsu_awid; +wire [31:0] lsu_awaddr; +wire [7:0] lsu_awlen; +wire [2:0] lsu_awsize; +wire [1:0] lsu_awburst; +wire lsu_awlock; +wire [3:0] lsu_awcache; +wire [2:0] lsu_awprot; +wire [3:0] lsu_awregion; +wire [3:0] lsu_awqos; +wire lsu_awvalid; +wire lsu_awready; +wire [3:0] lsu_arid; +wire [31:0] lsu_araddr; +wire [7:0] lsu_arlen; +wire [2:0] lsu_arsize; +wire [1:0] lsu_arburst; +wire lsu_arlock; +wire [3:0] lsu_arcache; +wire [2:0] lsu_arprot; +wire [3:0] lsu_arregion; +wire [3:0] lsu_arqos; +wire lsu_arvalid; +wire lsu_arready; +wire [63:0] lsu_wdata; +wire [7:0] lsu_wstrb; +wire lsu_wlast; +wire lsu_wvalid; +wire lsu_wready; +wire [3:0] lsu_bid; +wire [1:0] lsu_bresp; +wire lsu_bvalid; +wire lsu_bready; +wire [3:0] lsu_rid; +wire [63:0] lsu_rdata; +wire [1:0] lsu_rresp; +wire lsu_rlast; +wire lsu_rvalid; +wire lsu_rready; +wire [0:0] sb_awid; +wire [31:0] sb_awaddr; +wire [7:0] sb_awlen; +wire [2:0] sb_awsize; +wire [1:0] sb_awburst; +wire sb_awlock; +wire [3:0] sb_awcache; +wire [2:0] sb_awprot; +wire [3:0] sb_awregion; +wire [3:0] sb_awqos; +wire sb_awvalid; +wire sb_awready; +wire [0:0] sb_arid; +wire [31:0] sb_araddr; +wire [7:0] sb_arlen; +wire [2:0] sb_arsize; +wire [1:0] sb_arburst; +wire sb_arlock; +wire [3:0] sb_arcache; +wire [2:0] sb_arprot; +wire [3:0] sb_arregion; +wire [3:0] sb_arqos; +wire sb_arvalid; +wire sb_arready; +wire [63:0] sb_wdata; +wire [7:0] sb_wstrb; +wire sb_wlast; +wire sb_wvalid; +wire sb_wready; +wire [0:0] sb_bid; +wire [1:0] sb_bresp; +wire sb_bvalid; +wire sb_bready; +wire [0:0] sb_rid; +wire [63:0] sb_rdata; +wire [1:0] sb_rresp; +wire sb_rlast; +wire sb_rvalid; +wire sb_rready; +wire [5:0] io_awid; +wire [31:0] io_awaddr; +wire [7:0] io_awlen; +wire [2:0] io_awsize; +wire [1:0] io_awburst; +wire io_awlock; +wire [3:0] io_awcache; +wire [2:0] io_awprot; +wire [3:0] io_awregion; +wire [3:0] io_awqos; +wire io_awvalid; +wire io_awready; +wire [5:0] io_arid; +wire [31:0] io_araddr; +wire [7:0] io_arlen; +wire [2:0] io_arsize; +wire [1:0] io_arburst; +wire io_arlock; +wire [3:0] io_arcache; +wire [2:0] io_arprot; +wire [3:0] io_arregion; +wire [3:0] io_arqos; +wire io_arvalid; +wire io_arready; +wire [63:0] io_wdata; +wire [7:0] io_wstrb; +wire io_wlast; +wire io_wvalid; +wire io_wready; +wire [5:0] io_bid; +wire [1:0] io_bresp; +wire io_bvalid; +wire io_bready; +wire [5:0] io_rid; +wire [63:0] io_rdata; +wire [1:0] io_rresp; +wire io_rlast; +wire io_rvalid; +wire io_rready; +wire [5:0] ram_awid; +wire [31:0] ram_awaddr; +wire [7:0] ram_awlen; +wire [2:0] ram_awsize; +wire [1:0] ram_awburst; +wire ram_awlock; +wire [3:0] ram_awcache; +wire [2:0] ram_awprot; +wire [3:0] ram_awregion; +wire [3:0] ram_awqos; +wire ram_awvalid; +wire ram_awready; +wire [5:0] ram_arid; +wire [31:0] ram_araddr; +wire [7:0] ram_arlen; +wire [2:0] ram_arsize; +wire [1:0] ram_arburst; +wire ram_arlock; +wire [3:0] ram_arcache; +wire [2:0] ram_arprot; +wire [3:0] ram_arregion; +wire [3:0] ram_arqos; +wire ram_arvalid; +wire ram_arready; +wire [63:0] ram_wdata; +wire [7:0] ram_wstrb; +wire ram_wlast; +wire ram_wvalid; +wire ram_wready; +wire [5:0] ram_bid; +wire [1:0] ram_bresp; +wire ram_bvalid; +wire ram_bready; +wire [5:0] ram_rid; +wire [63:0] ram_rdata; +wire [1:0] ram_rresp; +wire ram_rlast; +wire ram_rvalid; +wire ram_rready; + +axi_intercon axi_intercon + (.clk_i (clk), + .rst_ni (rst_n), + .i_ifu_arid (ifu_arid), + .i_ifu_araddr (ifu_araddr), + .i_ifu_arlen (ifu_arlen), + .i_ifu_arsize (ifu_arsize), + .i_ifu_arburst (ifu_arburst), + .i_ifu_arlock (ifu_arlock), + .i_ifu_arcache (ifu_arcache), + .i_ifu_arprot (ifu_arprot), + .i_ifu_arregion (ifu_arregion), + .i_ifu_arqos (ifu_arqos), + .i_ifu_arvalid (ifu_arvalid), + .o_ifu_arready (ifu_arready), + .o_ifu_rid (ifu_rid), + .o_ifu_rdata (ifu_rdata), + .o_ifu_rresp (ifu_rresp), + .o_ifu_rlast (ifu_rlast), + .o_ifu_rvalid (ifu_rvalid), + .i_ifu_rready (ifu_rready), + .i_lsu_awid (lsu_awid), + .i_lsu_awaddr (lsu_awaddr), + .i_lsu_awlen (lsu_awlen), + .i_lsu_awsize (lsu_awsize), + .i_lsu_awburst (lsu_awburst), + .i_lsu_awlock (lsu_awlock), + .i_lsu_awcache (lsu_awcache), + .i_lsu_awprot (lsu_awprot), + .i_lsu_awregion (lsu_awregion), + .i_lsu_awqos (lsu_awqos), + .i_lsu_awvalid (lsu_awvalid), + .o_lsu_awready (lsu_awready), + .i_lsu_arid (lsu_arid), + .i_lsu_araddr (lsu_araddr), + .i_lsu_arlen (lsu_arlen), + .i_lsu_arsize (lsu_arsize), + .i_lsu_arburst (lsu_arburst), + .i_lsu_arlock (lsu_arlock), + .i_lsu_arcache (lsu_arcache), + .i_lsu_arprot (lsu_arprot), + .i_lsu_arregion (lsu_arregion), + .i_lsu_arqos (lsu_arqos), + .i_lsu_arvalid (lsu_arvalid), + .o_lsu_arready (lsu_arready), + .i_lsu_wdata (lsu_wdata), + .i_lsu_wstrb (lsu_wstrb), + .i_lsu_wlast (lsu_wlast), + .i_lsu_wvalid (lsu_wvalid), + .o_lsu_wready (lsu_wready), + .o_lsu_bid (lsu_bid), + .o_lsu_bresp (lsu_bresp), + .o_lsu_bvalid (lsu_bvalid), + .i_lsu_bready (lsu_bready), + .o_lsu_rid (lsu_rid), + .o_lsu_rdata (lsu_rdata), + .o_lsu_rresp (lsu_rresp), + .o_lsu_rlast (lsu_rlast), + .o_lsu_rvalid (lsu_rvalid), + .i_lsu_rready (lsu_rready), + .i_sb_awid (sb_awid), + .i_sb_awaddr (sb_awaddr), + .i_sb_awlen (sb_awlen), + .i_sb_awsize (sb_awsize), + .i_sb_awburst (sb_awburst), + .i_sb_awlock (sb_awlock), + .i_sb_awcache (sb_awcache), + .i_sb_awprot (sb_awprot), + .i_sb_awregion (sb_awregion), + .i_sb_awqos (sb_awqos), + .i_sb_awvalid (sb_awvalid), + .o_sb_awready (sb_awready), + .i_sb_arid (sb_arid), + .i_sb_araddr (sb_araddr), + .i_sb_arlen (sb_arlen), + .i_sb_arsize (sb_arsize), + .i_sb_arburst (sb_arburst), + .i_sb_arlock (sb_arlock), + .i_sb_arcache (sb_arcache), + .i_sb_arprot (sb_arprot), + .i_sb_arregion (sb_arregion), + .i_sb_arqos (sb_arqos), + .i_sb_arvalid (sb_arvalid), + .o_sb_arready (sb_arready), + .i_sb_wdata (sb_wdata), + .i_sb_wstrb (sb_wstrb), + .i_sb_wlast (sb_wlast), + .i_sb_wvalid (sb_wvalid), + .o_sb_wready (sb_wready), + .o_sb_bid (sb_bid), + .o_sb_bresp (sb_bresp), + .o_sb_bvalid (sb_bvalid), + .i_sb_bready (sb_bready), + .o_sb_rid (sb_rid), + .o_sb_rdata (sb_rdata), + .o_sb_rresp (sb_rresp), + .o_sb_rlast (sb_rlast), + .o_sb_rvalid (sb_rvalid), + .i_sb_rready (sb_rready), + .o_io_awid (io_awid), + .o_io_awaddr (io_awaddr), + .o_io_awlen (io_awlen), + .o_io_awsize (io_awsize), + .o_io_awburst (io_awburst), + .o_io_awlock (io_awlock), + .o_io_awcache (io_awcache), + .o_io_awprot (io_awprot), + .o_io_awregion (io_awregion), + .o_io_awqos (io_awqos), + .o_io_awvalid (io_awvalid), + .i_io_awready (io_awready), + .o_io_arid (io_arid), + .o_io_araddr (io_araddr), + .o_io_arlen (io_arlen), + .o_io_arsize (io_arsize), + .o_io_arburst (io_arburst), + .o_io_arlock (io_arlock), + .o_io_arcache (io_arcache), + .o_io_arprot (io_arprot), + .o_io_arregion (io_arregion), + .o_io_arqos (io_arqos), + .o_io_arvalid (io_arvalid), + .i_io_arready (io_arready), + .o_io_wdata (io_wdata), + .o_io_wstrb (io_wstrb), + .o_io_wlast (io_wlast), + .o_io_wvalid (io_wvalid), + .i_io_wready (io_wready), + .i_io_bid (io_bid), + .i_io_bresp (io_bresp), + .i_io_bvalid (io_bvalid), + .o_io_bready (io_bready), + .i_io_rid (io_rid), + .i_io_rdata (io_rdata), + .i_io_rresp (io_rresp), + .i_io_rlast (io_rlast), + .i_io_rvalid (io_rvalid), + .o_io_rready (io_rready), + .o_ram_awid (ram_awid), + .o_ram_awaddr (ram_awaddr), + .o_ram_awlen (ram_awlen), + .o_ram_awsize (ram_awsize), + .o_ram_awburst (ram_awburst), + .o_ram_awlock (ram_awlock), + .o_ram_awcache (ram_awcache), + .o_ram_awprot (ram_awprot), + .o_ram_awregion (ram_awregion), + .o_ram_awqos (ram_awqos), + .o_ram_awvalid (ram_awvalid), + .i_ram_awready (ram_awready), + .o_ram_arid (ram_arid), + .o_ram_araddr (ram_araddr), + .o_ram_arlen (ram_arlen), + .o_ram_arsize (ram_arsize), + .o_ram_arburst (ram_arburst), + .o_ram_arlock (ram_arlock), + .o_ram_arcache (ram_arcache), + .o_ram_arprot (ram_arprot), + .o_ram_arregion (ram_arregion), + .o_ram_arqos (ram_arqos), + .o_ram_arvalid (ram_arvalid), + .i_ram_arready (ram_arready), + .o_ram_wdata (ram_wdata), + .o_ram_wstrb (ram_wstrb), + .o_ram_wlast (ram_wlast), + .o_ram_wvalid (ram_wvalid), + .i_ram_wready (ram_wready), + .i_ram_bid (ram_bid), + .i_ram_bresp (ram_bresp), + .i_ram_bvalid (ram_bvalid), + .o_ram_bready (ram_bready), + .i_ram_rid (ram_rid), + .i_ram_rdata (ram_rdata), + .i_ram_rresp (ram_rresp), + .i_ram_rlast (ram_rlast), + .i_ram_rvalid (ram_rvalid), + .o_ram_rready (ram_rready)); + diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/intercon_input.yml b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/intercon_input.yml new file mode 100644 index 0000000000000000000000000000000000000000..e5eaa5097f01bf469ac6a80cfe26ba6965d418a0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-intercon_0.7.5-ac1faf165216c8b950370023fcb1379914164b7a29e03a61365714e182cfcb8f/intercon_input.yml @@ -0,0 +1,19 @@ +files_root: /home/tarik/0.git-repo/openCologne/8.StressTest/4.veerwolves +gapi: '1.0' +parameters: + masters: + ifu: + id_width: 3 + read_only: true + lsu: + id_width: 4 + sb: + id_width: 1 + slaves: + io: + offset: 2147483648 + size: 16384 + ram: + offset: 0 + size: 134217728 +vlnv: ::veerwolf-intercon:0.7.5 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/common_defines.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/common_defines.vh new file mode 100644 index 0000000000000000000000000000000000000000..915c3bcaacb29538f9bf68572f0d8a3f5e98ad57 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/common_defines.vh @@ -0,0 +1,242 @@ +// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE +// This is an automatically generated file by tarik on Čet 06 Mar 2025 11:08:14 CET +// +// cmd: veer -unset=assert_on -set=reset_vec=0x80000000 -set=fpga_optimize=1 -set=ret_stack_size=2 -set=btb_size=32 -set=bht_size=128 -set=dccm_size=16 -set=dccm_num_banks=2 -set=iccm_enable=0 -set=icache_enable=0 -set=dccm_enable=0 -set=pic_total_int=8 +// +`define RV_ROOT "/home/tarik/0.git-repo/openCologne/8.StressTest/4.veerwolves/cores/chipsalliance.org_cores_VeeR_EL2_1.4" +`define RV_PIC_MEIGWCLR_COUNT 8 +`define RV_PIC_MEIPL_OFFSET 'h0000 +`define RV_PIC_MEIPT_COUNT 8 +`define RV_PIC_MEIGWCLR_OFFSET 'h5000 +`define RV_PIC_MEIGWCTRL_OFFSET 'h4000 +`define RV_PIC_OFFSET 10'hc0000 +`define RV_PIC_MPICCFG_COUNT 1 +`define RV_PIC_MPICCFG_MASK 'h1 +`define RV_PIC_TOTAL_INT_PLUS1 9 +`define RV_PIC_BITS 15 +`define RV_PIC_MEIPT_OFFSET 'h3004 +`define RV_PIC_MEIPL_COUNT 8 +`define RV_PIC_SIZE 32 +`define RV_PIC_MEIE_COUNT 8 +`define RV_PIC_MPICCFG_OFFSET 'h3000 +`define RV_PIC_MEIPT_MASK 'h0 +`define RV_PIC_MEIP_MASK 'h0 +`define RV_PIC_MEIP_OFFSET 'h1000 +`define RV_PIC_TOTAL_INT 8 +`define RV_PIC_MEIGWCLR_MASK 'h0 +`define RV_PIC_MEIPL_MASK 'hf +`define RV_PIC_MEIE_OFFSET 'h2000 +`define RV_PIC_MEIE_MASK 'h1 +`define RV_PIC_REGION 4'hf +`define RV_PIC_BASE_ADDR 32'hf00c0000 +`define RV_PIC_MEIP_COUNT 1 +`define RV_PIC_MEIGWCTRL_COUNT 8 +`define RV_PIC_INT_WORDS 1 +`define RV_PIC_MEIGWCTRL_MASK 'h3 +`define TOP tb_top +`define RV_EXT_ADDRWIDTH 32 +`define RV_BUILD_AXI4 1 +`define RV_STERR_ROLLBACK 0 +`define RV_EXT_DATAWIDTH 64 +`define CLOCK_PERIOD 100 +`define RV_LDERR_ROLLBACK 1 +`define RV_BUILD_AXI_NATIVE 1 +`define CPU_TOP `RV_TOP.swerv +`define SDVT_AHB 0 +`define RV_TOP `TOP.rvtop +`define TEC_RV_ICG clockhdr +`define RV_ICCM_BANK_INDEX_LO 4 +`define RV_ICCM_SIZE_64 +`define RV_ICCM_REGION 4'he +`define RV_ICCM_EADR 32'hee00ffff +`define RV_ICCM_NUM_BANKS 4 +`define RV_ICCM_RESERVED 'h1000 +`define RV_ICCM_BANK_BITS 2 +`define RV_ICCM_NUM_BANKS_4 +`define RV_ICCM_BANK_HI 3 +`define RV_ICCM_DATA_CELL ram_4096x39 +`define RV_ICCM_OFFSET 10'he000000 +`define RV_ICCM_SIZE 64 +`define RV_ICCM_SADR 32'hee000000 +`define RV_ICCM_BITS 16 +`define RV_ICCM_ROWS 4096 +`define RV_ICCM_INDEX_BITS 12 +`define RV_DCCM_DATA_CELL ram_2048x39 +`define RV_DCCM_FDATA_WIDTH 39 +`define RV_DCCM_BANK_BITS 1 +`define RV_DCCM_RESERVED 'h1400 +`define RV_DCCM_OFFSET 28'h40000 +`define RV_DCCM_SIZE_16 +`define RV_DCCM_WIDTH_BITS 2 +`define RV_LSU_SB_BITS 14 +`define RV_DCCM_NUM_BANKS 2 +`define RV_DCCM_EADR 32'hf0043fff +`define RV_DCCM_REGION 4'hf +`define RV_DCCM_INDEX_BITS 11 +`define RV_DCCM_ECC_WIDTH 7 +`define RV_DCCM_DATA_WIDTH 32 +`define RV_DCCM_SIZE 16 +`define RV_DCCM_ROWS 2048 +`define RV_DCCM_NUM_BANKS_2 +`define RV_DCCM_BITS 14 +`define RV_DCCM_BYTE_WIDTH 4 +`define RV_DCCM_SADR 32'hf0040000 +`define REGWIDTH 32 +`define RV_TARGET default +`define RV_BHT_ADDR_HI 7 +`define RV_BHT_ADDR_LO 2 +`define RV_BHT_ARRAY_DEPTH 64 +`define RV_BHT_GHR_RANGE 5:0 +`define RV_BHT_SIZE 128 +`define RV_BHT_GHR_HASH_1 1 +`define RV_BHT_HASH_STRING {ghr[5:4], hashin[5:2]^ghr[4-1:0]} // cf1 +`define RV_BHT_GHR_SIZE 6 +`define RV_BTB_INDEX2_HI 9 +`define RV_BTB_INDEX1_LO 2 +`define RV_BTB_ARRAY_DEPTH 16 +`define RV_BTB_SIZE 32 +`define RV_BTB_INDEX3_HI 13 +`define RV_BTB_FOLD2_INDEX_HASH 0 +`define RV_BTB_BTAG_FOLD 1 +`define RV_BTB_ADDR_HI 5 +`define RV_BTB_TOFFSET_SIZE 12 +`define RV_BTB_INDEX2_LO 6 +`define RV_BTB_INDEX1_HI 5 +`define RV_BTB_BTAG_SIZE 9 +`define RV_BTB_ENABLE 1 +`define RV_BTB_INDEX3_LO 10 +`define RV_BTB_ADDR_LO 2 +`define RV_XLEN 32 +`define RV_LSU_NUM_NBLOAD_WIDTH 2 +`define RV_BITMANIP_ZBB 1 +`define RV_BITMANIP_ZBA 1 +`define RV_NO_ICCM_NO_ICACHE 1 +`define RV_BITMANIP_ZBP 0 +`define RV_BITMANIP_ZBR 0 +`define RV_DIV_NEW 1 +`define RV_LSU_STBUF_DEPTH 4 +`define RV_BITMANIP_ZBF 0 +`define RV_FPGA_OPTIMIZE 1 +`define RV_DMA_BUF_DEPTH 5 +`define RV_DIV_BIT 4 +`define RV_LSU2DMA 0 +`define RV_TIMER_LEGAL_EN 1 +`define RV_BITMANIP_ZBE 0 +`define RV_FAST_INTERRUPT_REDIRECT 0 +`define RV_LSU_NUM_NBLOAD 4 +`define RV_BITMANIP_ZBC 1 +`define RV_BITMANIP_ZBS 1 +`define RV_CONFIG_KEY 32'hdeadbeef +`define RV_NMI_VEC 'h11110000 +`define RV_UNUSED_REGION5 'h30000000 +`define RV_UNUSED_REGION6 'h20000000 +`define RV_DEBUG_SB_MEM 'ha0580000 +`define RV_EXTERNAL_DATA 'hc0580000 +`define RV_UNUSED_REGION2 'h60000000 +`define RV_UNUSED_REGION7 'h10000000 +`define RV_UNUSED_REGION3 'h50000000 +`define RV_UNUSED_REGION8 'h00000000 +`define RV_UNUSED_REGION4 'h40000000 +`define RV_EXTERNAL_DATA_1 'hb0000000 +`define RV_UNUSED_REGION1 'h70000000 +`define RV_SERIALIO 'hd0580000 +`define RV_UNUSED_REGION0 'h90000000 +`define RV_RET_STACK_SIZE 2 +`define RV_NUMIREGS 32 +`define RV_ICACHE_TAG_LO 13 +`define RV_ICACHE_DATA_INDEX_LO 4 +`define RV_ICACHE_BANK_BITS 1 +`define RV_ICACHE_NUM_LINES 256 +`define RV_ICACHE_ECC 1 +`define RV_ICACHE_TAG_NUM_BYPASS 2 +`define RV_ICACHE_LN_SZ 64 +`define RV_ICACHE_DATA_DEPTH 512 +`define RV_ICACHE_BANK_LO 3 +`define RV_ICACHE_TAG_NUM_BYPASS_WIDTH 2 +`define RV_ICACHE_SIZE 16 +`define RV_ICACHE_SCND_LAST 6 +`define RV_ICACHE_BEAT_ADDR_HI 5 +`define RV_ICACHE_INDEX_HI 12 +`define RV_ICACHE_TAG_INDEX_LO 6 +`define RV_ICACHE_NUM_BYPASS 2 +`define RV_ICACHE_DATA_WIDTH 64 +`define RV_ICACHE_TAG_DEPTH 128 +`define RV_ICACHE_DATA_CELL ram_512x71 +`define RV_ICACHE_NUM_BYPASS_WIDTH 2 +`define RV_ICACHE_WAYPACK 1 +`define RV_ICACHE_FDATA_WIDTH 71 +`define RV_ICACHE_NUM_LINES_BANK 64 +`define RV_ICACHE_NUM_LINES_WAY 128 +`define RV_ICACHE_BANKS_WAY 2 +`define RV_ICACHE_NUM_BEATS 8 +`define RV_ICACHE_STATUS_BITS 1 +`define RV_ICACHE_BANK_HI 3 +`define RV_ICACHE_BANK_WIDTH 8 +`define RV_ICACHE_BEAT_BITS 3 +`define RV_ICACHE_BYPASS_ENABLE 1 +`define RV_ICACHE_TAG_CELL ram_128x25 +`define RV_ICACHE_TAG_BYPASS_ENABLE 1 +`define RV_ICACHE_2BANKS 1 +`define RV_ICACHE_NUM_WAYS 2 +`define RV_INST_ACCESS_ENABLE1 1'h0 +`define RV_DATA_ACCESS_MASK1 'hffffffff +`define RV_DATA_ACCESS_MASK4 'hffffffff +`define RV_INST_ACCESS_ADDR1 'h00000000 +`define RV_INST_ACCESS_ADDR4 'h00000000 +`define RV_INST_ACCESS_ENABLE3 1'h0 +`define RV_DATA_ACCESS_ENABLE5 1'h0 +`define RV_DATA_ACCESS_ENABLE6 1'h0 +`define RV_INST_ACCESS_ENABLE5 1'h0 +`define RV_INST_ACCESS_ENABLE6 1'h0 +`define RV_DATA_ACCESS_ENABLE3 1'h0 +`define RV_DATA_ACCESS_ADDR4 'h00000000 +`define RV_DATA_ACCESS_ADDR1 'h00000000 +`define RV_INST_ACCESS_MASK4 'hffffffff +`define RV_INST_ACCESS_MASK1 'hffffffff +`define RV_DATA_ACCESS_ENABLE1 1'h0 +`define RV_DATA_ACCESS_ADDR7 'h00000000 +`define RV_DATA_ACCESS_ADDR2 'h00000000 +`define RV_INST_ACCESS_MASK0 'hffffffff +`define RV_DATA_ACCESS_ADDR0 'h00000000 +`define RV_INST_ACCESS_ENABLE0 1'h0 +`define RV_DATA_ACCESS_ENABLE7 1'h0 +`define RV_INST_ACCESS_MASK2 'hffffffff +`define RV_INST_ACCESS_MASK7 'hffffffff +`define RV_DATA_ACCESS_MASK2 'hffffffff +`define RV_DATA_ACCESS_MASK7 'hffffffff +`define RV_INST_ACCESS_ENABLE7 1'h0 +`define RV_DATA_ACCESS_ENABLE0 1'h0 +`define RV_INST_ACCESS_ADDR0 'h00000000 +`define RV_DATA_ACCESS_MASK0 'hffffffff +`define RV_INST_ACCESS_ADDR7 'h00000000 +`define RV_INST_ACCESS_ADDR2 'h00000000 +`define RV_INST_ACCESS_ENABLE2 1'h0 +`define RV_DATA_ACCESS_ADDR6 'h00000000 +`define RV_INST_ACCESS_MASK6 'hffffffff +`define RV_DATA_ACCESS_MASK6 'hffffffff +`define RV_INST_ACCESS_ADDR6 'h00000000 +`define RV_DATA_ACCESS_ENABLE2 1'h0 +`define RV_INST_ACCESS_ENABLE4 1'h0 +`define RV_INST_ACCESS_MASK5 'hffffffff +`define RV_DATA_ACCESS_ADDR3 'h00000000 +`define RV_INST_ACCESS_MASK3 'hffffffff +`define RV_DATA_ACCESS_ADDR5 'h00000000 +`define RV_DATA_ACCESS_MASK3 'hffffffff +`define RV_INST_ACCESS_ADDR5 'h00000000 +`define RV_DATA_ACCESS_MASK5 'hffffffff +`define RV_INST_ACCESS_ADDR3 'h00000000 +`define RV_DATA_ACCESS_ENABLE4 1'h0 +`define RV_RESET_VEC 'h80000000 +`define RV_DMA_BUS_TAG 1 +`define RV_BUS_PRTY_DEFAULT 2'h3 +`define RV_LSU_BUS_ID 1 +`define RV_SB_BUS_PRTY 2 +`define RV_IFU_BUS_TAG 3 +`define RV_LSU_BUS_PRTY 2 +`define RV_SB_BUS_TAG 1 +`define RV_DMA_BUS_PRTY 2 +`define RV_DMA_BUS_ID 1 +`define RV_IFU_BUS_ID 1 +`define RV_IFU_BUS_PRTY 2 +`define RV_SB_BUS_ID 1 +`define RV_LSU_BUS_TAG 3 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/defines.h b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/defines.h new file mode 100644 index 0000000000000000000000000000000000000000..7b287d61becbbe15c27c92b77f1784bf800da72d --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/defines.h @@ -0,0 +1,173 @@ +// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE +// This is an automatically generated file by tarik on Čet 06 Mar 2025 11:08:14 CET +// +// cmd: veer -unset=assert_on -set=reset_vec=0x80000000 -set=fpga_optimize=1 -set=ret_stack_size=2 -set=btb_size=32 -set=bht_size=128 -set=dccm_size=16 -set=dccm_num_banks=2 -set=iccm_enable=0 -set=icache_enable=0 -set=dccm_enable=0 -set=pic_total_int=8 +// +#define RV_PIC_MEIGWCLR_COUNT 8 +#define RV_PIC_MEIPL_OFFSET 0x0000 +#define RV_PIC_MEIPT_COUNT 8 +#define RV_PIC_MEIGWCLR_OFFSET 0x5000 +#define RV_PIC_MEIGWCTRL_OFFSET 0x4000 +#define RV_PIC_OFFSET 0xc0000 +#define RV_PIC_MPICCFG_COUNT 1 +#define RV_PIC_MPICCFG_MASK 0x1 +#define RV_PIC_TOTAL_INT_PLUS1 9 +#define RV_PIC_BITS 15 +#define RV_PIC_MEIPT_OFFSET 0x3004 +#define RV_PIC_MEIPL_COUNT 8 +#define RV_PIC_SIZE 32 +#define RV_PIC_MEIE_COUNT 8 +#define RV_PIC_MPICCFG_OFFSET 0x3000 +#define RV_PIC_MEIPT_MASK 0x0 +#define RV_PIC_MEIP_MASK 0x0 +#define RV_PIC_MEIP_OFFSET 0x1000 +#define RV_PIC_TOTAL_INT 8 +#define RV_PIC_MEIGWCLR_MASK 0x0 +#define RV_PIC_MEIPL_MASK 0xf +#define RV_PIC_MEIE_OFFSET 0x2000 +#define RV_PIC_MEIE_MASK 0x1 +#define RV_PIC_REGION 0xf +#define RV_PIC_BASE_ADDR 0xf00c0000 +#define RV_PIC_MEIP_COUNT 1 +#define RV_PIC_MEIGWCTRL_COUNT 8 +#define RV_PIC_INT_WORDS 1 +#define RV_PIC_MEIGWCTRL_MASK 0x3 +#define TOP tb_top +#define RV_EXT_ADDRWIDTH 32 +#define RV_BUILD_AXI4 1 +#define RV_STERR_ROLLBACK 0 +#define RV_EXT_DATAWIDTH 64 +#define CLOCK_PERIOD 100 +#define RV_LDERR_ROLLBACK 1 +#define RV_BUILD_AXI_NATIVE 1 +#define CPU_TOP `RV_TOP.swerv +#define SDVT_AHB 0 +#define RV_TOP `TOP.rvtop +#define RV_ICCM_BANK_INDEX_LO 4 +#define RV_ICCM_SIZE_64 +#define RV_ICCM_REGION 0xe +#define RV_ICCM_EADR 0xee00ffff +#define RV_ICCM_NUM_BANKS 4 +#define RV_ICCM_RESERVED 0x1000 +#define RV_ICCM_BANK_BITS 2 +#define RV_ICCM_NUM_BANKS_4 +#define RV_ICCM_BANK_HI 3 +#define RV_ICCM_DATA_CELL ram_4096x39 +#define RV_ICCM_OFFSET 0xe000000 +#define RV_ICCM_SIZE 64 +#define RV_ICCM_SADR 0xee000000 +#define RV_ICCM_BITS 16 +#define RV_ICCM_ROWS 4096 +#define RV_ICCM_INDEX_BITS 12 +#define RV_DCCM_DATA_CELL ram_2048x39 +#define RV_DCCM_FDATA_WIDTH 39 +#define RV_DCCM_BANK_BITS 1 +#define RV_DCCM_RESERVED 0x1400 +#define RV_DCCM_OFFSET 0x40000 +#define RV_DCCM_SIZE_16 +#define RV_DCCM_WIDTH_BITS 2 +#define RV_LSU_SB_BITS 14 +#define RV_DCCM_NUM_BANKS 2 +#define RV_DCCM_EADR 0xf0043fff +#define RV_DCCM_REGION 0xf +#define RV_DCCM_INDEX_BITS 11 +#define RV_DCCM_ECC_WIDTH 7 +#define RV_DCCM_DATA_WIDTH 32 +#define RV_DCCM_SIZE 16 +#define RV_DCCM_ROWS 2048 +#define RV_DCCM_NUM_BANKS_2 +#define RV_DCCM_BITS 14 +#define RV_DCCM_BYTE_WIDTH 4 +#define RV_DCCM_SADR 0xf0040000 +#define RV_TARGET default +#define RV_XLEN 32 +#define RV_LSU_NUM_NBLOAD_WIDTH 2 +#define RV_BITMANIP_ZBB 1 +#define RV_BITMANIP_ZBA 1 +#define RV_NO_ICCM_NO_ICACHE 1 +#define RV_BITMANIP_ZBP 0 +#define RV_BITMANIP_ZBR 0 +#define RV_DIV_NEW 1 +#define RV_LSU_STBUF_DEPTH 4 +#define RV_BITMANIP_ZBF 0 +#define RV_FPGA_OPTIMIZE 1 +#define RV_DMA_BUF_DEPTH 5 +#define RV_DIV_BIT 4 +#define RV_LSU2DMA 0 +#define RV_TIMER_LEGAL_EN 1 +#define RV_BITMANIP_ZBE 0 +#define RV_FAST_INTERRUPT_REDIRECT 0 +#define RV_LSU_NUM_NBLOAD 4 +#define RV_BITMANIP_ZBC 1 +#define RV_BITMANIP_ZBS 1 +#ifndef RV_NMI_VEC +#define RV_NMI_VEC 0x11110000 +#endif +#define RV_UNUSED_REGION5 0x30000000 +#define RV_UNUSED_REGION6 0x20000000 +#define RV_DEBUG_SB_MEM 0xa0580000 +#ifndef RV_EXTERNAL_DATA +#define RV_EXTERNAL_DATA 0xc0580000 +#endif +#define RV_UNUSED_REGION2 0x60000000 +#define RV_UNUSED_REGION7 0x10000000 +#define RV_UNUSED_REGION3 0x50000000 +#define RV_UNUSED_REGION8 0x00000000 +#define RV_UNUSED_REGION4 0x40000000 +#define RV_EXTERNAL_DATA_1 0xb0000000 +#define RV_UNUSED_REGION1 0x70000000 +#ifndef RV_SERIALIO +#define RV_SERIALIO 0xd0580000 +#endif +#define RV_UNUSED_REGION0 0x90000000 +#define RV_INST_ACCESS_ENABLE1 0x0 +#define RV_DATA_ACCESS_MASK1 0xffffffff +#define RV_DATA_ACCESS_MASK4 0xffffffff +#define RV_INST_ACCESS_ADDR1 0x00000000 +#define RV_INST_ACCESS_ADDR4 0x00000000 +#define RV_INST_ACCESS_ENABLE3 0x0 +#define RV_DATA_ACCESS_ENABLE5 0x0 +#define RV_DATA_ACCESS_ENABLE6 0x0 +#define RV_INST_ACCESS_ENABLE5 0x0 +#define RV_INST_ACCESS_ENABLE6 0x0 +#define RV_DATA_ACCESS_ENABLE3 0x0 +#define RV_DATA_ACCESS_ADDR4 0x00000000 +#define RV_DATA_ACCESS_ADDR1 0x00000000 +#define RV_INST_ACCESS_MASK4 0xffffffff +#define RV_INST_ACCESS_MASK1 0xffffffff +#define RV_DATA_ACCESS_ENABLE1 0x0 +#define RV_DATA_ACCESS_ADDR7 0x00000000 +#define RV_DATA_ACCESS_ADDR2 0x00000000 +#define RV_INST_ACCESS_MASK0 0xffffffff +#define RV_DATA_ACCESS_ADDR0 0x00000000 +#define RV_INST_ACCESS_ENABLE0 0x0 +#define RV_DATA_ACCESS_ENABLE7 0x0 +#define RV_INST_ACCESS_MASK2 0xffffffff +#define RV_INST_ACCESS_MASK7 0xffffffff +#define RV_DATA_ACCESS_MASK2 0xffffffff +#define RV_DATA_ACCESS_MASK7 0xffffffff +#define RV_INST_ACCESS_ENABLE7 0x0 +#define RV_DATA_ACCESS_ENABLE0 0x0 +#define RV_INST_ACCESS_ADDR0 0x00000000 +#define RV_DATA_ACCESS_MASK0 0xffffffff +#define RV_INST_ACCESS_ADDR7 0x00000000 +#define RV_INST_ACCESS_ADDR2 0x00000000 +#define RV_INST_ACCESS_ENABLE2 0x0 +#define RV_DATA_ACCESS_ADDR6 0x00000000 +#define RV_INST_ACCESS_MASK6 0xffffffff +#define RV_DATA_ACCESS_MASK6 0xffffffff +#define RV_INST_ACCESS_ADDR6 0x00000000 +#define RV_DATA_ACCESS_ENABLE2 0x0 +#define RV_INST_ACCESS_ENABLE4 0x0 +#define RV_INST_ACCESS_MASK5 0xffffffff +#define RV_DATA_ACCESS_ADDR3 0x00000000 +#define RV_INST_ACCESS_MASK3 0xffffffff +#define RV_DATA_ACCESS_ADDR5 0x00000000 +#define RV_DATA_ACCESS_MASK3 0xffffffff +#define RV_INST_ACCESS_ADDR5 0x00000000 +#define RV_DATA_ACCESS_MASK5 0xffffffff +#define RV_INST_ACCESS_ADDR3 0x00000000 +#define RV_DATA_ACCESS_ENABLE4 0x0 +#ifndef RV_RESET_VEC +#define RV_RESET_VEC 0x80000000 +#endif diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/el2_param.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/el2_param.vh new file mode 100644 index 0000000000000000000000000000000000000000..291dba83340a3b167e741ffd30fe70b0f7084bc4 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/el2_param.vh @@ -0,0 +1,175 @@ +parameter el2_param_t pt = '{ + BHT_ADDR_HI : 8'h07 , + BHT_ADDR_LO : 6'h02 , + BHT_ARRAY_DEPTH : 15'h0040 , + BHT_GHR_HASH_1 : 5'h01 , + BHT_GHR_SIZE : 8'h06 , + BHT_SIZE : 16'h0080 , + BITMANIP_ZBA : 5'h01 , + BITMANIP_ZBB : 5'h01 , + BITMANIP_ZBC : 5'h01 , + BITMANIP_ZBE : 5'h00 , + BITMANIP_ZBF : 5'h00 , + BITMANIP_ZBP : 5'h00 , + BITMANIP_ZBR : 5'h00 , + BITMANIP_ZBS : 5'h01 , + BTB_ADDR_HI : 9'h005 , + BTB_ADDR_LO : 6'h02 , + BTB_ARRAY_DEPTH : 13'h0010 , + BTB_BTAG_FOLD : 5'h01 , + BTB_BTAG_SIZE : 9'h009 , + BTB_ENABLE : 5'h01 , + BTB_FOLD2_INDEX_HASH : 5'h00 , + BTB_FULLYA : 5'h00 , + BTB_INDEX1_HI : 9'h005 , + BTB_INDEX1_LO : 9'h002 , + BTB_INDEX2_HI : 9'h009 , + BTB_INDEX2_LO : 9'h006 , + BTB_INDEX3_HI : 9'h00D , + BTB_INDEX3_LO : 9'h00A , + BTB_SIZE : 14'h0020 , + BTB_TOFFSET_SIZE : 9'h00C , + BUILD_AHB_LITE : 4'h0 , + BUILD_AXI4 : 5'h01 , + BUILD_AXI_NATIVE : 5'h01 , + BUS_PRTY_DEFAULT : 6'h03 , + DATA_ACCESS_ADDR0 : 36'h000000000 , + DATA_ACCESS_ADDR1 : 36'h000000000 , + DATA_ACCESS_ADDR2 : 36'h000000000 , + DATA_ACCESS_ADDR3 : 36'h000000000 , + DATA_ACCESS_ADDR4 : 36'h000000000 , + DATA_ACCESS_ADDR5 : 36'h000000000 , + DATA_ACCESS_ADDR6 : 36'h000000000 , + DATA_ACCESS_ADDR7 : 36'h000000000 , + DATA_ACCESS_ENABLE0 : 5'h00 , + DATA_ACCESS_ENABLE1 : 5'h00 , + DATA_ACCESS_ENABLE2 : 5'h00 , + DATA_ACCESS_ENABLE3 : 5'h00 , + DATA_ACCESS_ENABLE4 : 5'h00 , + DATA_ACCESS_ENABLE5 : 5'h00 , + DATA_ACCESS_ENABLE6 : 5'h00 , + DATA_ACCESS_ENABLE7 : 5'h00 , + DATA_ACCESS_MASK0 : 36'h0FFFFFFFF , + DATA_ACCESS_MASK1 : 36'h0FFFFFFFF , + DATA_ACCESS_MASK2 : 36'h0FFFFFFFF , + DATA_ACCESS_MASK3 : 36'h0FFFFFFFF , + DATA_ACCESS_MASK4 : 36'h0FFFFFFFF , + DATA_ACCESS_MASK5 : 36'h0FFFFFFFF , + DATA_ACCESS_MASK6 : 36'h0FFFFFFFF , + DATA_ACCESS_MASK7 : 36'h0FFFFFFFF , + DCCM_BANK_BITS : 7'h01 , + DCCM_BITS : 9'h00E , + DCCM_BYTE_WIDTH : 7'h04 , + DCCM_DATA_WIDTH : 10'h020 , + DCCM_ECC_WIDTH : 7'h07 , + DCCM_ENABLE : 5'h00 , + DCCM_FDATA_WIDTH : 10'h027 , + DCCM_INDEX_BITS : 8'h0B , + DCCM_NUM_BANKS : 9'h002 , + DCCM_REGION : 8'h0F , + DCCM_SADR : 36'h0F0040000 , + DCCM_SIZE : 14'h0010 , + DCCM_WIDTH_BITS : 6'h02 , + DIV_BIT : 7'h04 , + DIV_NEW : 5'h01 , + DMA_BUF_DEPTH : 7'h05 , + DMA_BUS_ID : 9'h001 , + DMA_BUS_PRTY : 6'h02 , + DMA_BUS_TAG : 8'h01 , + FAST_INTERRUPT_REDIRECT : 5'h00 , + ICACHE_2BANKS : 5'h01 , + ICACHE_BANK_BITS : 7'h01 , + ICACHE_BANK_HI : 7'h03 , + ICACHE_BANK_LO : 6'h03 , + ICACHE_BANK_WIDTH : 8'h08 , + ICACHE_BANKS_WAY : 7'h02 , + ICACHE_BEAT_ADDR_HI : 8'h05 , + ICACHE_BEAT_BITS : 8'h03 , + ICACHE_BYPASS_ENABLE : 5'h01 , + ICACHE_DATA_DEPTH : 18'h00200 , + ICACHE_DATA_INDEX_LO : 7'h04 , + ICACHE_DATA_WIDTH : 11'h040 , + ICACHE_ECC : 5'h01 , + ICACHE_ENABLE : 5'h00 , + ICACHE_FDATA_WIDTH : 11'h047 , + ICACHE_INDEX_HI : 9'h00C , + ICACHE_LN_SZ : 11'h040 , + ICACHE_NUM_BEATS : 8'h08 , + ICACHE_NUM_BYPASS : 8'h02 , + ICACHE_NUM_BYPASS_WIDTH : 8'h02 , + ICACHE_NUM_WAYS : 7'h02 , + ICACHE_ONLY : 5'h00 , + ICACHE_SCND_LAST : 8'h06 , + ICACHE_SIZE : 13'h0010 , + ICACHE_STATUS_BITS : 7'h01 , + ICACHE_TAG_BYPASS_ENABLE : 5'h01 , + ICACHE_TAG_DEPTH : 17'h00080 , + ICACHE_TAG_INDEX_LO : 7'h06 , + ICACHE_TAG_LO : 9'h00D , + ICACHE_TAG_NUM_BYPASS : 8'h02 , + ICACHE_TAG_NUM_BYPASS_WIDTH : 8'h02 , + ICACHE_WAYPACK : 5'h01 , + ICCM_BANK_BITS : 7'h02 , + ICCM_BANK_HI : 9'h003 , + ICCM_BANK_INDEX_LO : 9'h004 , + ICCM_BITS : 9'h010 , + ICCM_ENABLE : 5'h00 , + ICCM_ICACHE : 5'h00 , + ICCM_INDEX_BITS : 8'h0C , + ICCM_NUM_BANKS : 9'h004 , + ICCM_ONLY : 5'h00 , + ICCM_REGION : 8'h0E , + ICCM_SADR : 36'h0EE000000 , + ICCM_SIZE : 14'h0040 , + IFU_BUS_ID : 5'h01 , + IFU_BUS_PRTY : 6'h02 , + IFU_BUS_TAG : 8'h03 , + INST_ACCESS_ADDR0 : 36'h000000000 , + INST_ACCESS_ADDR1 : 36'h000000000 , + INST_ACCESS_ADDR2 : 36'h000000000 , + INST_ACCESS_ADDR3 : 36'h000000000 , + INST_ACCESS_ADDR4 : 36'h000000000 , + INST_ACCESS_ADDR5 : 36'h000000000 , + INST_ACCESS_ADDR6 : 36'h000000000 , + INST_ACCESS_ADDR7 : 36'h000000000 , + INST_ACCESS_ENABLE0 : 5'h00 , + INST_ACCESS_ENABLE1 : 5'h00 , + INST_ACCESS_ENABLE2 : 5'h00 , + INST_ACCESS_ENABLE3 : 5'h00 , + INST_ACCESS_ENABLE4 : 5'h00 , + INST_ACCESS_ENABLE5 : 5'h00 , + INST_ACCESS_ENABLE6 : 5'h00 , + INST_ACCESS_ENABLE7 : 5'h00 , + INST_ACCESS_MASK0 : 36'h0FFFFFFFF , + INST_ACCESS_MASK1 : 36'h0FFFFFFFF , + INST_ACCESS_MASK2 : 36'h0FFFFFFFF , + INST_ACCESS_MASK3 : 36'h0FFFFFFFF , + INST_ACCESS_MASK4 : 36'h0FFFFFFFF , + INST_ACCESS_MASK5 : 36'h0FFFFFFFF , + INST_ACCESS_MASK6 : 36'h0FFFFFFFF , + INST_ACCESS_MASK7 : 36'h0FFFFFFFF , + LOAD_TO_USE_PLUS1 : 5'h00 , + LSU2DMA : 5'h00 , + LSU_BUS_ID : 5'h01 , + LSU_BUS_PRTY : 6'h02 , + LSU_BUS_TAG : 8'h03 , + LSU_NUM_NBLOAD : 9'h004 , + LSU_NUM_NBLOAD_WIDTH : 7'h02 , + LSU_SB_BITS : 9'h00E , + LSU_STBUF_DEPTH : 8'h04 , + NO_ICCM_NO_ICACHE : 5'h01 , + PIC_2CYCLE : 5'h00 , + PIC_BASE_ADDR : 36'h0F00C0000 , + PIC_BITS : 9'h00F , + PIC_INT_WORDS : 8'h01 , + PIC_REGION : 8'h0F , + PIC_SIZE : 13'h0020 , + PIC_TOTAL_INT : 12'h008 , + PIC_TOTAL_INT_PLUS1 : 13'h0009 , + RET_STACK_SIZE : 8'h02 , + SB_BUS_ID : 5'h01 , + SB_BUS_PRTY : 6'h02 , + SB_BUS_TAG : 8'h01 , + TIMER_LEGAL_EN : 5'h01 +} +// parameter el2_param_t pt = 2271'h0384010020C010010840000020508020104840002808120606828020060210C00000000000000000000000000000000000000000000000000000000000000000000000000000000003FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC3FFFFFFFC083820401C013858083C3C01000000100820428042010040830C2010281840200081002008E0C0801004040800C01002100400606810104100C0810000300800E0EE00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF8001080C08081C081007806000003C043C04001000902084021 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/el2_pdef.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/el2_pdef.vh new file mode 100644 index 0000000000000000000000000000000000000000..ee6848f7da0b08dc70f01a6eaa452cb179e00efe --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/el2_pdef.vh @@ -0,0 +1,175 @@ +typedef struct packed { + bit [7:0] BHT_ADDR_HI; + bit [5:0] BHT_ADDR_LO; + bit [14:0] BHT_ARRAY_DEPTH; + bit [4:0] BHT_GHR_HASH_1; + bit [7:0] BHT_GHR_SIZE; + bit [15:0] BHT_SIZE; + bit [4:0] BITMANIP_ZBA; + bit [4:0] BITMANIP_ZBB; + bit [4:0] BITMANIP_ZBC; + bit [4:0] BITMANIP_ZBE; + bit [4:0] BITMANIP_ZBF; + bit [4:0] BITMANIP_ZBP; + bit [4:0] BITMANIP_ZBR; + bit [4:0] BITMANIP_ZBS; + bit [8:0] BTB_ADDR_HI; + bit [5:0] BTB_ADDR_LO; + bit [12:0] BTB_ARRAY_DEPTH; + bit [4:0] BTB_BTAG_FOLD; + bit [8:0] BTB_BTAG_SIZE; + bit [4:0] BTB_ENABLE; + bit [4:0] BTB_FOLD2_INDEX_HASH; + bit [4:0] BTB_FULLYA; + bit [8:0] BTB_INDEX1_HI; + bit [8:0] BTB_INDEX1_LO; + bit [8:0] BTB_INDEX2_HI; + bit [8:0] BTB_INDEX2_LO; + bit [8:0] BTB_INDEX3_HI; + bit [8:0] BTB_INDEX3_LO; + bit [13:0] BTB_SIZE; + bit [8:0] BTB_TOFFSET_SIZE; + bit BUILD_AHB_LITE; + bit [4:0] BUILD_AXI4; + bit [4:0] BUILD_AXI_NATIVE; + bit [5:0] BUS_PRTY_DEFAULT; + bit [35:0] DATA_ACCESS_ADDR0; + bit [35:0] DATA_ACCESS_ADDR1; + bit [35:0] DATA_ACCESS_ADDR2; + bit [35:0] DATA_ACCESS_ADDR3; + bit [35:0] DATA_ACCESS_ADDR4; + bit [35:0] DATA_ACCESS_ADDR5; + bit [35:0] DATA_ACCESS_ADDR6; + bit [35:0] DATA_ACCESS_ADDR7; + bit [4:0] DATA_ACCESS_ENABLE0; + bit [4:0] DATA_ACCESS_ENABLE1; + bit [4:0] DATA_ACCESS_ENABLE2; + bit [4:0] DATA_ACCESS_ENABLE3; + bit [4:0] DATA_ACCESS_ENABLE4; + bit [4:0] DATA_ACCESS_ENABLE5; + bit [4:0] DATA_ACCESS_ENABLE6; + bit [4:0] DATA_ACCESS_ENABLE7; + bit [35:0] DATA_ACCESS_MASK0; + bit [35:0] DATA_ACCESS_MASK1; + bit [35:0] DATA_ACCESS_MASK2; + bit [35:0] DATA_ACCESS_MASK3; + bit [35:0] DATA_ACCESS_MASK4; + bit [35:0] DATA_ACCESS_MASK5; + bit [35:0] DATA_ACCESS_MASK6; + bit [35:0] DATA_ACCESS_MASK7; + bit [6:0] DCCM_BANK_BITS; + bit [8:0] DCCM_BITS; + bit [6:0] DCCM_BYTE_WIDTH; + bit [9:0] DCCM_DATA_WIDTH; + bit [6:0] DCCM_ECC_WIDTH; + bit [4:0] DCCM_ENABLE; + bit [9:0] DCCM_FDATA_WIDTH; + bit [7:0] DCCM_INDEX_BITS; + bit [8:0] DCCM_NUM_BANKS; + bit [7:0] DCCM_REGION; + bit [35:0] DCCM_SADR; + bit [13:0] DCCM_SIZE; + bit [5:0] DCCM_WIDTH_BITS; + bit [6:0] DIV_BIT; + bit [4:0] DIV_NEW; + bit [6:0] DMA_BUF_DEPTH; + bit [8:0] DMA_BUS_ID; + bit [5:0] DMA_BUS_PRTY; + bit [7:0] DMA_BUS_TAG; + bit [4:0] FAST_INTERRUPT_REDIRECT; + bit [4:0] ICACHE_2BANKS; + bit [6:0] ICACHE_BANK_BITS; + bit [6:0] ICACHE_BANK_HI; + bit [5:0] ICACHE_BANK_LO; + bit [7:0] ICACHE_BANK_WIDTH; + bit [6:0] ICACHE_BANKS_WAY; + bit [7:0] ICACHE_BEAT_ADDR_HI; + bit [7:0] ICACHE_BEAT_BITS; + bit [4:0] ICACHE_BYPASS_ENABLE; + bit [17:0] ICACHE_DATA_DEPTH; + bit [6:0] ICACHE_DATA_INDEX_LO; + bit [10:0] ICACHE_DATA_WIDTH; + bit [4:0] ICACHE_ECC; + bit [4:0] ICACHE_ENABLE; + bit [10:0] ICACHE_FDATA_WIDTH; + bit [8:0] ICACHE_INDEX_HI; + bit [10:0] ICACHE_LN_SZ; + bit [7:0] ICACHE_NUM_BEATS; + bit [7:0] ICACHE_NUM_BYPASS; + bit [7:0] ICACHE_NUM_BYPASS_WIDTH; + bit [6:0] ICACHE_NUM_WAYS; + bit [4:0] ICACHE_ONLY; + bit [7:0] ICACHE_SCND_LAST; + bit [12:0] ICACHE_SIZE; + bit [6:0] ICACHE_STATUS_BITS; + bit [4:0] ICACHE_TAG_BYPASS_ENABLE; + bit [16:0] ICACHE_TAG_DEPTH; + bit [6:0] ICACHE_TAG_INDEX_LO; + bit [8:0] ICACHE_TAG_LO; + bit [7:0] ICACHE_TAG_NUM_BYPASS; + bit [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH; + bit [4:0] ICACHE_WAYPACK; + bit [6:0] ICCM_BANK_BITS; + bit [8:0] ICCM_BANK_HI; + bit [8:0] ICCM_BANK_INDEX_LO; + bit [8:0] ICCM_BITS; + bit [4:0] ICCM_ENABLE; + bit [4:0] ICCM_ICACHE; + bit [7:0] ICCM_INDEX_BITS; + bit [8:0] ICCM_NUM_BANKS; + bit [4:0] ICCM_ONLY; + bit [7:0] ICCM_REGION; + bit [35:0] ICCM_SADR; + bit [13:0] ICCM_SIZE; + bit [4:0] IFU_BUS_ID; + bit [5:0] IFU_BUS_PRTY; + bit [7:0] IFU_BUS_TAG; + bit [35:0] INST_ACCESS_ADDR0; + bit [35:0] INST_ACCESS_ADDR1; + bit [35:0] INST_ACCESS_ADDR2; + bit [35:0] INST_ACCESS_ADDR3; + bit [35:0] INST_ACCESS_ADDR4; + bit [35:0] INST_ACCESS_ADDR5; + bit [35:0] INST_ACCESS_ADDR6; + bit [35:0] INST_ACCESS_ADDR7; + bit [4:0] INST_ACCESS_ENABLE0; + bit [4:0] INST_ACCESS_ENABLE1; + bit [4:0] INST_ACCESS_ENABLE2; + bit [4:0] INST_ACCESS_ENABLE3; + bit [4:0] INST_ACCESS_ENABLE4; + bit [4:0] INST_ACCESS_ENABLE5; + bit [4:0] INST_ACCESS_ENABLE6; + bit [4:0] INST_ACCESS_ENABLE7; + bit [35:0] INST_ACCESS_MASK0; + bit [35:0] INST_ACCESS_MASK1; + bit [35:0] INST_ACCESS_MASK2; + bit [35:0] INST_ACCESS_MASK3; + bit [35:0] INST_ACCESS_MASK4; + bit [35:0] INST_ACCESS_MASK5; + bit [35:0] INST_ACCESS_MASK6; + bit [35:0] INST_ACCESS_MASK7; + bit [4:0] LOAD_TO_USE_PLUS1; + bit [4:0] LSU2DMA; + bit [4:0] LSU_BUS_ID; + bit [5:0] LSU_BUS_PRTY; + bit [7:0] LSU_BUS_TAG; + bit [8:0] LSU_NUM_NBLOAD; + bit [6:0] LSU_NUM_NBLOAD_WIDTH; + bit [8:0] LSU_SB_BITS; + bit [7:0] LSU_STBUF_DEPTH; + bit [4:0] NO_ICCM_NO_ICACHE; + bit [4:0] PIC_2CYCLE; + bit [35:0] PIC_BASE_ADDR; + bit [8:0] PIC_BITS; + bit [7:0] PIC_INT_WORDS; + bit [7:0] PIC_REGION; + bit [12:0] PIC_SIZE; + bit [11:0] PIC_TOTAL_INT; + bit [12:0] PIC_TOTAL_INT_PLUS1; + bit [7:0] RET_STACK_SIZE; + bit [4:0] SB_BUS_ID; + bit [5:0] SB_BUS_PRTY; + bit [7:0] SB_BUS_TAG; + bit [4:0] TIMER_LEGAL_EN; +} el2_param_t; + diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/pd_defines.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/pd_defines.vh new file mode 100644 index 0000000000000000000000000000000000000000..b974601595f6e7cace7e1f2b8f0cb0b248f42448 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/pd_defines.vh @@ -0,0 +1,10 @@ +// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE +// This is an automatically generated file by tarik on Čet 06 Mar 2025 11:08:14 CET +// +// cmd: veer -unset=assert_on -set=reset_vec=0x80000000 -set=fpga_optimize=1 -set=ret_stack_size=2 -set=btb_size=32 -set=bht_size=128 -set=dccm_size=16 -set=dccm_num_banks=2 -set=iccm_enable=0 -set=icache_enable=0 -set=dccm_enable=0 -set=pic_total_int=8 +// + +`include "common_defines.vh" +`undef RV_ASSERT_ON +`undef TEC_RV_ICG +`define RV_PHYSICAL 1 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/pic_map_auto.h b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/pic_map_auto.h new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/veer_el2_pack_config_input.yml b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/veer_el2_pack_config_input.yml new file mode 100644 index 0000000000000000000000000000000000000000..c50640dc4563de12c39e78b2ba7e244ad5f73ec4 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/veer_el2_pack_config_input.yml @@ -0,0 +1,17 @@ +files_root: /home/tarik/0.git-repo/openCologne/8.StressTest/4.veerwolves +gapi: '1.0' +parameters: + args: + - -unset=assert_on + - -set=reset_vec=0x80000000 + - -set=fpga_optimize=1 + - -set=ret_stack_size=2 + - -set=btb_size=32 + - -set=bht_size=128 + - -set=dccm_size=16 + - -set=dccm_num_banks=2 + - -set=iccm_enable=0 + - -set=icache_enable=0 + - -set=dccm_enable=0 + - -set=pic_total_int=8 +vlnv: ::veerwolf-veer_el2_pack_config:0.7.5 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/whisper.json b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/whisper.json new file mode 100644 index 0000000000000000000000000000000000000000..837ffd740f5b6521b294ce1158d090022833aee9 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-veer_el2_pack_config_0.7.5-6b06c5b735a773ec6b26da85aa7ec281971fbdde57b815606c8c63ed98014f43/whisper.json @@ -0,0 +1,563 @@ +{ + "xlen" : 32, + "effective_address_compatible_with_base" : "true", + "max_mmode_perf_event" : "516", + "fast_interrupt_redirect" : 0, + "enable_zbr" : 0, + "enable_zbb" : 1, + "harts" : 1, + "memory_mapped_registers" : { + "address" : "0xf00c0000", + "default_mask" : 0, + "registers" : { + "meigwclr" : { + "mask" : "0x0", + "address" : "0xf00c5004", + "count" : "8" + }, + "meie" : { + "mask" : "0x1", + "address" : "0xf00c2004", + "count" : "8" + }, + "meip" : { + "count" : 1, + "address" : "0xf00c1000", + "mask" : "0x0" + }, + "meipl" : { + "count" : "8", + "address" : "0xf00c0004", + "mask" : "0xf" + }, + "mpiccfg" : { + "mask" : "0x1", + "address" : "0xf00c3000", + "count" : 1 + }, + "meigwctrl" : { + "mask" : "0x3", + "count" : "8", + "address" : "0xf00c4004" + } + }, + "size" : "0x8000" + }, + "enable_zbc" : 1, + "enable_zbs" : 1, + "enable_zbf" : 0, + "csr" : { + "pmpaddr8" : { + "exists" : "false" + }, + "pmpaddr15" : { + "exists" : "false" + }, + "dicago" : { + "reset" : "0x0", + "number" : "0x7cb", + "debug" : "true", + "mask" : "0x0", + "comment" : "Cache diagnostics.", + "exists" : "true" + }, + "time" : { + "exists" : "false" + }, + "mhpmevent6" : { + "mask" : "0xffffffff", + "exists" : "true", + "reset" : "0x0" + }, + "mhpmcounter5" : { + "exists" : "true", + "mask" : "0xffffffff", + "reset" : "0x0" + }, + "pmpaddr0" : { + "exists" : "false" + }, + "mhpmcounter3h" : { + "mask" : "0xffffffff", + "exists" : "true", + "reset" : "0x0" + }, + "marchid" : { + "reset" : "0x00000010", + "exists" : "true", + "mask" : "0x0" + }, + "meicpct" : { + "reset" : "0x0", + "number" : "0xbca", + "mask" : "0x0", + "comment" : "External claim id/priority capture.", + "exists" : "true" + }, + "meicurpl" : { + "comment" : "External interrupt current priority level.", + "exists" : "true", + "mask" : "0xf", + "reset" : "0x0", + "number" : "0xbcc" + }, + "mcounteren" : { + "exists" : "false" + }, + "dmst" : { + "comment" : "Memory synch trigger: Flush caches in debug mode.", + "exists" : "true", + "mask" : "0x0", + "debug" : "true", + "reset" : "0x0", + "number" : "0x7c4" + }, + "pmpaddr1" : { + "exists" : "false" + }, + "dicad0" : { + "exists" : "true", + "comment" : "Cache diagnostics.", + "mask" : "0xffffffff", + "debug" : "true", + "number" : "0x7c9", + "reset" : "0x0" + }, + "dicawics" : { + "comment" : "Cache diagnostics.", + "exists" : "true", + "mask" : "0x0130fffc", + "debug" : "true", + "reset" : "0x0", + "number" : "0x7c8" + }, + "mhpmcounter4" : { + "reset" : "0x0", + "exists" : "true", + "mask" : "0xffffffff" + }, + "pmpaddr13" : { + "exists" : "false" + }, + "pmpaddr2" : { + "exists" : "false" + }, + "meicidpl" : { + "mask" : "0xf", + "comment" : "External interrupt claim id priority level.", + "exists" : "true", + "reset" : "0x0", + "number" : "0xbcb" + }, + "meipt" : { + "mask" : "0xf", + "comment" : "External interrupt priority threshold.", + "exists" : "true", + "reset" : "0x0", + "number" : "0xbc9" + }, + "mfdhs" : { + "exists" : "true", + "comment" : "Force Debug Halt Status", + "mask" : "0x00000003", + "number" : "0x7cf", + "reset" : "0x0" + }, + "mitcnt1" : { + "number" : "0x7d5", + "reset" : "0x0", + "exists" : "true", + "mask" : "0xffffffff" + }, + "mstatus" : { + "mask" : "0x88", + "exists" : "true", + "reset" : "0x1800" + }, + "mie" : { + "reset" : "0x0", + "mask" : "0x70000888", + "exists" : "true" + }, + "pmpaddr10" : { + "exists" : "false" + }, + "pmpaddr9" : { + "exists" : "false" + }, + "mhpmcounter6h" : { + "reset" : "0x0", + "exists" : "true", + "mask" : "0xffffffff" + }, + "mfdc" : { + "exists" : "true", + "mask" : "0x00071fff", + "number" : "0x7f9", + "reset" : "0x00070040" + }, + "mpmc" : { + "mask" : "0x2", + "exists" : "true", + "number" : "0x7c6", + "reset" : "0x2" + }, + "pmpcfg1" : { + "exists" : "false" + }, + "pmpaddr3" : { + "exists" : "false" + }, + "pmpaddr7" : { + "exists" : "false" + }, + "tselect" : { + "reset" : "0x0", + "exists" : "true", + "mask" : "0x3" + }, + "miccmect" : { + "mask" : "0xffffffff", + "exists" : "true", + "number" : "0x7f1", + "reset" : "0x0" + }, + "mitbnd1" : { + "reset" : "0xffffffff", + "number" : "0x7d6", + "exists" : "true", + "mask" : "0xffffffff" + }, + "micect" : { + "mask" : "0xffffffff", + "exists" : "true", + "reset" : "0x0", + "number" : "0x7f0" + }, + "mfdht" : { + "mask" : "0x0000003f", + "exists" : "true", + "comment" : "Force Debug Halt Threshold", + "number" : "0x7ce", + "reset" : "0x0", + "shared" : "true" + }, + "misa" : { + "exists" : "true", + "mask" : "0x0", + "reset" : "0x40001104" + }, + "mitctl0" : { + "number" : "0x7d4", + "reset" : "0x1", + "mask" : "0x00000007", + "exists" : "true" + }, + "mhpmcounter3" : { + "exists" : "true", + "mask" : "0xffffffff", + "reset" : "0x0" + }, + "mvendorid" : { + "exists" : "true", + "mask" : "0x0", + "reset" : "0x45" + }, + "mhpmevent5" : { + "exists" : "true", + "mask" : "0xffffffff", + "reset" : "0x0" + }, + "mhartid" : { + "reset" : "0x0", + "poke_mask" : "0xfffffff0", + "mask" : "0x0", + "exists" : "true" + }, + "dcsr" : { + "exists" : "true", + "mask" : "0x00008c04", + "debug" : "true", + "poke_mask" : "0x00008dcc", + "reset" : "0x40000003" + }, + "pmpcfg3" : { + "exists" : "false" + }, + "mhpmcounter5h" : { + "mask" : "0xffffffff", + "exists" : "true", + "reset" : "0x0" + }, + "mdccmect" : { + "number" : "0x7f2", + "reset" : "0x0", + "exists" : "true", + "mask" : "0xffffffff" + }, + "mip" : { + "reset" : "0x0", + "poke_mask" : "0x70000888", + "mask" : "0x0", + "exists" : "true" + }, + "instret" : { + "exists" : "false" + }, + "pmpaddr14" : { + "exists" : "false" + }, + "mcgc" : { + "reset" : "0x200", + "number" : "0x7f8", + "poke_mask" : "0x000003ff", + "mask" : "0x000003ff", + "exists" : "true" + }, + "mcountinhibit" : { + "poke_mask" : "0x7d", + "commnet" : "Performance counter inhibit. One bit per counter.", + "reset" : "0x0", + "exists" : "true", + "mask" : "0x7d" + }, + "pmpaddr5" : { + "exists" : "false" + }, + "dicad1" : { + "reset" : "0x0", + "number" : "0x7ca", + "debug" : "true", + "mask" : "0x3", + "comment" : "Cache diagnostics.", + "exists" : "true" + }, + "mrac" : { + "reset" : "0x0", + "number" : "0x7c0", + "shared" : "true", + "mask" : "0xffffffff", + "comment" : "Memory region io and cache control.", + "exists" : "true" + }, + "pmpaddr4" : { + "exists" : "false" + }, + "mhpmevent3" : { + "mask" : "0xffffffff", + "exists" : "true", + "reset" : "0x0" + }, + "pmpaddr12" : { + "exists" : "false" + }, + "pmpcfg2" : { + "exists" : "false" + }, + "mimpid" : { + "reset" : "0x4", + "mask" : "0x0", + "exists" : "true" + }, + "mcpc" : { + "comment" : "Core pause", + "exists" : "true", + "mask" : "0x0", + "reset" : "0x0", + "number" : "0x7c2" + }, + "pmpcfg0" : { + "exists" : "false" + }, + "mhpmcounter6" : { + "reset" : "0x0", + "exists" : "true", + "mask" : "0xffffffff" + }, + "pmpaddr6" : { + "exists" : "false" + }, + "mitcnt0" : { + "exists" : "true", + "mask" : "0xffffffff", + "number" : "0x7d2", + "reset" : "0x0" + }, + "mscause" : { + "mask" : "0x0000000f", + "exists" : "true", + "number" : "0x7ff", + "reset" : "0x0" + }, + "mhpmcounter4h" : { + "reset" : "0x0", + "mask" : "0xffffffff", + "exists" : "true" + }, + "cycle" : { + "exists" : "false" + }, + "mhpmevent4" : { + "reset" : "0x0", + "exists" : "true", + "mask" : "0xffffffff" + }, + "mitctl1" : { + "number" : "0x7d7", + "reset" : "0x1", + "exists" : "true", + "mask" : "0x0000000f" + }, + "mitbnd0" : { + "exists" : "true", + "mask" : "0xffffffff", + "number" : "0x7d3", + "reset" : "0xffffffff" + }, + "pmpaddr11" : { + "exists" : "false" + } + }, + "reset_vec" : "0x80000000", + "load_error_rollback" : "1", + "enable_zba" : 1, + "num_mmode_perf_regs" : "4", + "enable_zbe" : 0, + "mmode_perf_events" : [ + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 30, + 31, + 32, + 34, + 35, + 36, + 37, + 38, + 39, + 40, + 41, + 42, + 43, + 44, + 45, + 46, + 47, + 48, + 49, + 50, + 54, + 55, + 56, + 512, + 513, + 514, + 515, + 516 + ], + "even_odd_trigger_chains" : "true", + "store_error_rollback" : "0", + "enable_zbp" : 0, + "memmap" : { + "serialio" : "0xd0580000", + "consoleio" : "0xd0580000" + }, + "amo_illegal_outside_dccm" : "true", + "nmi_vec" : "0x11110000", + "triggers" : [ + { + "reset" : [ + "0x23e00000", + "0x00000000", + "0x00000000" + ], + "poke_mask" : [ + "0x081818c7", + "0xffffffff", + "0x00000000" + ], + "mask" : [ + "0x081818c7", + "0xffffffff", + "0x00000000" + ] + }, + { + "mask" : [ + "0x081810c7", + "0xffffffff", + "0x00000000" + ], + "poke_mask" : [ + "0x081810c7", + "0xffffffff", + "0x00000000" + ], + "reset" : [ + "0x23e00000", + "0x00000000", + "0x00000000" + ] + }, + { + "poke_mask" : [ + "0x081818c7", + "0xffffffff", + "0x00000000" + ], + "reset" : [ + "0x23e00000", + "0x00000000", + "0x00000000" + ], + "mask" : [ + "0x081818c7", + "0xffffffff", + "0x00000000" + ] + }, + { + "mask" : [ + "0x081810c7", + "0xffffffff", + "0x00000000" + ], + "reset" : [ + "0x23e00000", + "0x00000000", + "0x00000000" + ], + "poke_mask" : [ + "0x081810c7", + "0xffffffff", + "0x00000000" + ] + } + ] +} diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_intercon.v b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_intercon.v new file mode 100644 index 0000000000000000000000000000000000000000..3e3fc9a3859545623de9bdd47b7ba9e198fc6828 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_intercon.v @@ -0,0 +1,88 @@ +// THIS FILE IS AUTOGENERATED BY wb_intercon_gen +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module wb_intercon + (input wire wb_clk_i, + input wire wb_rst_i, + input wire [31:0] wb_io_adr_i, + input wire [31:0] wb_io_dat_i, + input wire [3:0] wb_io_sel_i, + input wire wb_io_we_i, + input wire wb_io_cyc_i, + input wire wb_io_stb_i, + input wire [2:0] wb_io_cti_i, + input wire [1:0] wb_io_bte_i, + output wire [31:0] wb_io_rdt_o, + output wire wb_io_ack_o, + output wire wb_io_err_o, + output wire wb_io_rty_o, + output wire [31:0] wb_rom_adr_o, + output wire [31:0] wb_rom_dat_o, + output wire [3:0] wb_rom_sel_o, + output wire wb_rom_we_o, + output wire wb_rom_cyc_o, + output wire wb_rom_stb_o, + output wire [2:0] wb_rom_cti_o, + output wire [1:0] wb_rom_bte_o, + input wire [31:0] wb_rom_rdt_i, + input wire wb_rom_ack_i, + input wire wb_rom_err_i, + input wire wb_rom_rty_i, + output wire [31:0] wb_sys_adr_o, + output wire [31:0] wb_sys_dat_o, + output wire [3:0] wb_sys_sel_o, + output wire wb_sys_we_o, + output wire wb_sys_cyc_o, + output wire wb_sys_stb_o, + output wire [2:0] wb_sys_cti_o, + output wire [1:0] wb_sys_bte_o, + input wire [31:0] wb_sys_rdt_i, + input wire wb_sys_ack_i, + input wire wb_sys_err_i, + input wire wb_sys_rty_i, + output wire [31:0] wb_uart_adr_o, + output wire [31:0] wb_uart_dat_o, + output wire [3:0] wb_uart_sel_o, + output wire wb_uart_we_o, + output wire wb_uart_cyc_o, + output wire wb_uart_stb_o, + output wire [2:0] wb_uart_cti_o, + output wire [1:0] wb_uart_bte_o, + input wire [31:0] wb_uart_rdt_i, + input wire wb_uart_ack_i, + input wire wb_uart_err_i, + input wire wb_uart_rty_i); + +wb_mux + #(.num_devices (3), + .MATCH_ADDR ({32'h00000000, 32'h00001000, 32'h00002000}), + .MATCH_MASK ({32'hfffff000, 32'hffffffc0, 32'hfffff000})) + wb_mux_io + (.wb_clk_i (wb_clk_i), + .wb_rst_i (wb_rst_i), + .wbm_adr_i (wb_io_adr_i), + .wbm_dat_i (wb_io_dat_i), + .wbm_sel_i (wb_io_sel_i), + .wbm_we_i (wb_io_we_i), + .wbm_cyc_i (wb_io_cyc_i), + .wbm_stb_i (wb_io_stb_i), + .wbm_cti_i (wb_io_cti_i), + .wbm_bte_i (wb_io_bte_i), + .wbm_dat_o (wb_io_rdt_o), + .wbm_ack_o (wb_io_ack_o), + .wbm_err_o (wb_io_err_o), + .wbm_rty_o (wb_io_rty_o), + .wbs_adr_o ({wb_rom_adr_o, wb_sys_adr_o, wb_uart_adr_o}), + .wbs_dat_o ({wb_rom_dat_o, wb_sys_dat_o, wb_uart_dat_o}), + .wbs_sel_o ({wb_rom_sel_o, wb_sys_sel_o, wb_uart_sel_o}), + .wbs_we_o ({wb_rom_we_o, wb_sys_we_o, wb_uart_we_o}), + .wbs_cyc_o ({wb_rom_cyc_o, wb_sys_cyc_o, wb_uart_cyc_o}), + .wbs_stb_o ({wb_rom_stb_o, wb_sys_stb_o, wb_uart_stb_o}), + .wbs_cti_o ({wb_rom_cti_o, wb_sys_cti_o, wb_uart_cti_o}), + .wbs_bte_o ({wb_rom_bte_o, wb_sys_bte_o, wb_uart_bte_o}), + .wbs_dat_i ({wb_rom_rdt_i, wb_sys_rdt_i, wb_uart_rdt_i}), + .wbs_ack_i ({wb_rom_ack_i, wb_sys_ack_i, wb_uart_ack_i}), + .wbs_err_i ({wb_rom_err_i, wb_sys_err_i, wb_uart_err_i}), + .wbs_rty_i ({wb_rom_rty_i, wb_sys_rty_i, wb_uart_rty_i})); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_intercon.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_intercon.vh new file mode 100644 index 0000000000000000000000000000000000000000..647991cb244ec59044ad10398931d24532922b73 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_intercon.vh @@ -0,0 +1,101 @@ +wire [31:0] wb_io_adr; +wire [31:0] wb_io_dat; +wire [3:0] wb_io_sel; +wire wb_io_we; +wire wb_io_cyc; +wire wb_io_stb; +wire [2:0] wb_io_cti; +wire [1:0] wb_io_bte; +wire [31:0] wb_io_rdt; +wire wb_io_ack; +wire wb_io_err; +wire wb_io_rty; +wire [31:0] wb_rom_adr; +wire [31:0] wb_rom_dat; +wire [3:0] wb_rom_sel; +wire wb_rom_we; +wire wb_rom_cyc; +wire wb_rom_stb; +wire [2:0] wb_rom_cti; +wire [1:0] wb_rom_bte; +wire [31:0] wb_rom_rdt; +wire wb_rom_ack; +wire wb_rom_err; +wire wb_rom_rty; +wire [31:0] wb_sys_adr; +wire [31:0] wb_sys_dat; +wire [3:0] wb_sys_sel; +wire wb_sys_we; +wire wb_sys_cyc; +wire wb_sys_stb; +wire [2:0] wb_sys_cti; +wire [1:0] wb_sys_bte; +wire [31:0] wb_sys_rdt; +wire wb_sys_ack; +wire wb_sys_err; +wire wb_sys_rty; +wire [31:0] wb_uart_adr; +wire [31:0] wb_uart_dat; +wire [3:0] wb_uart_sel; +wire wb_uart_we; +wire wb_uart_cyc; +wire wb_uart_stb; +wire [2:0] wb_uart_cti; +wire [1:0] wb_uart_bte; +wire [31:0] wb_uart_rdt; +wire wb_uart_ack; +wire wb_uart_err; +wire wb_uart_rty; + +wb_intercon wb_intercon0 + (.wb_clk_i (wb_clk), + .wb_rst_i (wb_rst), + .wb_io_adr_i (wb_io_adr), + .wb_io_dat_i (wb_io_dat), + .wb_io_sel_i (wb_io_sel), + .wb_io_we_i (wb_io_we), + .wb_io_cyc_i (wb_io_cyc), + .wb_io_stb_i (wb_io_stb), + .wb_io_cti_i (wb_io_cti), + .wb_io_bte_i (wb_io_bte), + .wb_io_rdt_o (wb_io_rdt), + .wb_io_ack_o (wb_io_ack), + .wb_io_err_o (wb_io_err), + .wb_io_rty_o (wb_io_rty), + .wb_rom_adr_o (wb_rom_adr), + .wb_rom_dat_o (wb_rom_dat), + .wb_rom_sel_o (wb_rom_sel), + .wb_rom_we_o (wb_rom_we), + .wb_rom_cyc_o (wb_rom_cyc), + .wb_rom_stb_o (wb_rom_stb), + .wb_rom_cti_o (wb_rom_cti), + .wb_rom_bte_o (wb_rom_bte), + .wb_rom_rdt_i (wb_rom_rdt), + .wb_rom_ack_i (wb_rom_ack), + .wb_rom_err_i (wb_rom_err), + .wb_rom_rty_i (wb_rom_rty), + .wb_sys_adr_o (wb_sys_adr), + .wb_sys_dat_o (wb_sys_dat), + .wb_sys_sel_o (wb_sys_sel), + .wb_sys_we_o (wb_sys_we), + .wb_sys_cyc_o (wb_sys_cyc), + .wb_sys_stb_o (wb_sys_stb), + .wb_sys_cti_o (wb_sys_cti), + .wb_sys_bte_o (wb_sys_bte), + .wb_sys_rdt_i (wb_sys_rdt), + .wb_sys_ack_i (wb_sys_ack), + .wb_sys_err_i (wb_sys_err), + .wb_sys_rty_i (wb_sys_rty), + .wb_uart_adr_o (wb_uart_adr), + .wb_uart_dat_o (wb_uart_dat), + .wb_uart_sel_o (wb_uart_sel), + .wb_uart_we_o (wb_uart_we), + .wb_uart_cyc_o (wb_uart_cyc), + .wb_uart_stb_o (wb_uart_stb), + .wb_uart_cti_o (wb_uart_cti), + .wb_uart_bte_o (wb_uart_bte), + .wb_uart_rdt_i (wb_uart_rdt), + .wb_uart_ack_i (wb_uart_ack), + .wb_uart_err_i (wb_uart_err), + .wb_uart_rty_i (wb_uart_rty)); + diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_nospi_intercon_input.yml b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_nospi_intercon_input.yml new file mode 100644 index 0000000000000000000000000000000000000000..cb4dba4587f2369c1d78c5b79112cd41264b3cf1 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wb_nospi_intercon_0.7.5-36e02a7629d589f8c029a0ac4c2668ff017dfad0f3c94c81fef65be8ea4346e7/wb_nospi_intercon_input.yml @@ -0,0 +1,20 @@ +files_root: /home/tarik/0.git-repo/openCologne/8.StressTest/4.veerwolves +gapi: '1.0' +parameters: + masters: + io: + slaves: + - rom + - sys + - uart + slaves: + rom: + offset: 0 + size: 4096 + sys: + offset: 4096 + size: 64 + uart: + offset: 8192 + size: 4096 +vlnv: ::veerwolf-wb_nospi_intercon:0.7.5 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wolfpack_0.7.5-9cf773ba949d4049dbf72f0cb4bfe2b13ec8ad8fc646ebe5d81a49aa92c69876/veerwolf_pack.v b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wolfpack_0.7.5-9cf773ba949d4049dbf72f0cb4bfe2b13ec8ad8fc646ebe5d81a49aa92c69876/veerwolf_pack.v new file mode 100644 index 0000000000000000000000000000000000000000..cf9cb185fc44ee2ace7b25cd25feb419adf74fd0 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wolfpack_0.7.5-9cf773ba949d4049dbf72f0cb4bfe2b13ec8ad8fc646ebe5d81a49aa92c69876/veerwolf_pack.v @@ -0,0 +1,33 @@ +// THIS FILE IS AUTOGENERATED BY verilogwriter.py +// ANY MANUAL CHANGES WILL BE LOST +`default_nettype none +module veerwolf_pack +#( parameter pack_code = "bootloader.vh") + (input wire clk_core, + input wire rst_core, + input wire i_uart_rx, + output wire o_uart_tx, + input wire [15:0] i_sw, + output wire [15:0] o_led); + +wire [15:0] gpio0; +wire uart0; +wire [15:0] gpio1; +wire uart1; + +assign gpio0 = i_sw; +assign o_led = gpio1; +assign uart0 = i_uart_rx; +assign o_uart_tx = uart1; + +veerwolf_tile + #(.bootrom_file (pack_code)) + tile0 + (.clk_core (clk_core), + .rst_core (rst_core), + .i_uart_rx (uart0), + .o_uart_tx (uart1), + .i_sw (gpio0), + .o_led (gpio1)); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wolfpack_0.7.5-9cf773ba949d4049dbf72f0cb4bfe2b13ec8ad8fc646ebe5d81a49aa92c69876/wolfpack_input.yml b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wolfpack_0.7.5-9cf773ba949d4049dbf72f0cb4bfe2b13ec8ad8fc646ebe5d81a49aa92c69876/wolfpack_input.yml new file mode 100644 index 0000000000000000000000000000000000000000..7fdac03eab8edfcc38b588f07c6b853bdca2afb6 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/generator_cache/veerwolf-wolfpack_0.7.5-9cf773ba949d4049dbf72f0cb4bfe2b13ec8ad8fc646ebe5d81a49aa92c69876/wolfpack_input.yml @@ -0,0 +1,5 @@ +files_root: /home/tarik/0.git-repo/openCologne/8.StressTest/4.veerwolves +gapi: '1.0' +parameters: + count: 1 +vlnv: ::veerwolf-wolfpack:0.7.5 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut3.txt b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut3.txt new file mode 100644 index 0000000000000000000000000000000000000000..188eae5b34812fc5b91e9331d3dec7a3842efe90 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut3.txt @@ -0,0 +1,58 @@ +0001 89 abc +0007 165 c/AB\ +000B 95 c/aB\ +000D 86 c/Ab\ +000E 33 c/ab\ +0010 260 abC +0014 2 (B^C)a +0017 14 AB?1:c:c:0 +001F 13 (ab)+c +002B 2 AB?c:1:0:c +002C 2 BC?0:1:A:0 +0035 579 c?b:a +003A 431 c?b:A +0040 375 aBC +0041 43 (B^c)a +004B 40 (aB)^c +004F 1081 (aB)+c +0053 62 C?b:a +005C 50 c?a:B +0060 70 C(A^B) +0069 31 A^B^c +006F 3 (A^B)+c +0070 639 C/AB\ +0071 2 AB?1:C:C:0 +0078 26 (AB)^C +007C 2 BC?0:1:1:a +007F 27 /AB\+c +0080 683 ABC +0081 1 AB?c:0:0:C +0087 27 (AB)^c +008F 225 (AB)+c +0090 110 C(a^B) +0094 1 AB?C:0:c:C +0096 74 A^B^C +009F 13 (a^B)+c +00A3 158 C?b:A +00AC 137 c?A:B +00B0 141 C/aB\ +00B2 2 AB?C:1:0:C +00B4 31 (aB)^C +00BE 2 /(B^c)a\ +00BF 7 /aB\+c +00C1 1 BC?a:0:0:1 +00C2 8 BC?A:0:0:1 +00C5 260 C?a:B +00CA 1189 C?A:B +00D0 153 C/Ab\ +00D3 4 BC?1:0:a:1 +00D4 1 AB?C:0:1:C +00E0 61 C/ab\ +00E1 1 (ab)^C +00E8 36 AB?0:C:C:1 +00EF 6 /ab\+c +00F1 20 (ab)+C +00F4 133 (aB)+C +00F8 143 (AB)+C +00FE 44 /ab\+C + Gesamt: 7894 DS4: 13 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut4.txt b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut4.txt new file mode 100644 index 0000000000000000000000000000000000000000..8c362122951854a5050dbd441534fba889203d06 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut4.txt @@ -0,0 +1,430 @@ +0001 266 abcd +0007 139 cd/AB\ +000B 37 cd/aB\ +000D 24 cd/Ab\ +000E 23 cd/ab\ +001F 20 ((ab)+c)d +004F 73 ((aB)+c)d +0071 1 d(AB?1:C:C:0) +007D 2 AD?1:B^C:0:0 +007F 51 ((/AB\)+c)d +008F 51 ((AB)+c)d +00BE 21 AD?B^C:1:0:0 +00BF 60 ((/aB\)+c)d +00D7 3 AD?1:b^C:0:0 +00EF 22 ((/ab\)+c)d +00F1 12 ((ab)+C)d +00F4 40 ((aB)+C)d +00F8 53 ((AB)+C)d +00FE 15 ((/ab\)+C)d +0100 148 abcD +010E 1 AC?B^D:d:0:0 +0110 1 ab(C^D) +01FF 2 (abc)+d +0305 90 DC?a:b:0:0 +030A 48 DC?A:b:0:0 +0356 9 AB?C^D:c:d:0 +035F 4 DC?1:b:a:0 +03A9 1 AB?c:C^D:0:d +03AF 3 DC?1:b:A:0 +03D5 1 BD?a:/Ac\:c:0 +04F0 1 DC?0:aB:1:0 +0503 34 DC?b:a:0:0 +050C 20 DC?B:a:0:0 +05F3 5 DC?b:a:1:0 +0700 396 cD/AB\ +0708 60 AC?D:B^D:0:0 +0733 2 BD?1:0:c:ac +075D 3 AC?1:B^D:d:0 +0770 14 (C^D)/AB\ +0777 2946 /AB\(d+c) +07CC 2 BD?0:1:c:ac +07F0 5 DC?0:/AB\:1:0 +07F8 12 (c/AB\)^d +07FF 12 (c/AB\)+d +0807 8 AC?d:b^D:0:0 +08F0 1 DC?0:AB:1:0 +0990 5 (a^B)(d^c) +0A03 4 DC?b:A:0:0 +0A0C 11 DC?B:A:0:0 +0AC0 4 DC?0:A:B:0 +0AF3 1 DC?b:A:1:0 +0B00 60 cD/aB\ +0B04 1 AC?B^D:D:0:0 +0B33 18 BD?1:0:c:Ac +0BAE 1 AC?B^D:1:0:d +0BBB 433 /aB\(d+c) +0BF0 1 DC?0:/aB\:1:0 +0BF4 1 (c/aB\)^d +0BFF 6 (c/aB\)+d +0C05 14 DC?a:B:0:0 +0C0A 143 DC?A:B:0:0 +0C0B 2 BC?d:/ad\:0:0 +0C5F 1 DC?1:B:a:0 +0CAF 2 DC?1:B:A:0 +0CCA 1 DC?A:B:B:0 +0CFE 1 BD?/ac\:1:0:c +0D00 127 cD/Ab\ +0D57 1 AC?1:b^D:d:0 +0DCC 4 BD?0:1:ac:c +0DF0 1 DC?0:/Ab\:1:0 +0E00 66 cD/ab\ +0EAB 3 AC?b^D:1:0:d +0EC0 1 DC?0:/ab\:B:0 +0ECC 2 BD?0:1:Ac:c +0EE0 11 (A+B)(C^D) +0EEE 8 /ab\(d+c) +0F11 3 D?ab:c +0F37 2 BC?1:/Ad\:d:0 +0F44 6 D?aB:c +0F77 8 D?/AB\:c +0F88 5 D?AB:c +0FBB 46 D?/aB\:c +0FDC 1 DC?B:1:/Ab\:0 +0FEE 7 D?/ab\:c +0FF1 1 DC?ab:1:1:0 +0FF4 1 DC?aB:1:1:0 +0FFB 1 DC?/aB\:1:1:0 +1000 304 abCD +1001 16 ab(c^D) +10EF 1 (abC)^d +10FF 7 (abC)+d +110F 2 D?c:ab +111F 1 (ab)+(cd) +11F0 5 D?C:ab +124F 1 AC?d:/BD\:B^D:0 +133F 3 BD?1:c:/AC\:0 +1351 2 AB?1:cD:Cd:0 +13FC 1 BD?C:1:/AC\:0 +1400 33 D(B^C)a +1428 46 (B^C)(A^D) +1513 1 AB?1:cd:cD:0 +17E8 2 (AB?1:c:c:0)^d +1E4C 1 AC?B:/bd\:B^D:0 +1F00 25 ((ab)+c)D +1F11 2 (ab)+(cD) +1FD0 1 BC?D:D:a:d +1FE0 1 AC?D:D:B^D:d +1FFF 3 (ab)+c+d +233F 3 BD?1:c:/aC\:0 +2372 1 AB?C^D:1:Cd:0 +2ACF 1 BD?c:1:A:Ac +2CC0 1 BD?0:C:AC:c +2DDD 7 AC?1:B:d:B^D +2F70 2 AC?D:D:d:b +2FFF 3 (Ab)+c+d +3007 1 DC?/AB\:0:0:b +300D 1 DC?/Ab\:0:0:b +3037 3 BD?1:ac:C:0 +30F5 3 DC?a:0:1:b +30FA 4 DC?A:0:1:b +3115 1 AB?1:CD:cd:0 +311F 1 DC?1:ab:ab:b +31F3 3 BD?1:C:/Ac\:0 +3307 2 BD?c:ac:1:0 +333A 1 DC?A:b:b:b +3500 94 D(c?b:a) +3533 7 DC?b:a:b:b +3553 1 DC?b:a:a:b +35FF 18 (c?b:a)+d +37F0 1 DC?0:/AB\:1:b +37F3 4 BD?1:C:1:ac +3807 1 BC?d:a^D:D:0 +390A 63 AB?D:c^D:0:c +3A00 43 D(c?b:A) +3A33 22 DC?b:A:b:b +3AFF 1 (c?b:A)+d +3B30 4 BD?C:0:1:Ac +3BB0 2 DC?0:/aB\:/aB\:b +3BF3 2 BD?1:C:1:Ac +3C55 1 D?a:B^C +3CAA 1 D?A:B^C +3CFA 1 DC?A:B:1:b +3F0A 3 DC?A:1:0:b +3F40 4 BD?0:aC:1:c +3F50 48 DC?0:1:a:b +3FA0 2 DC?0:1:A:b +3FD5 1 BD?a:/Ac\:1:c +3FF5 1 DC?a:1:1:b +4000 255 aBCD +4001 1 AB?cd:0:CD:0 +400B 1 DC?/aB\:0:0:aB +40FF 11 (aBC)+d +4100 37 D(B^c)a +4114 7 AB?C^D:0:c^D:0 +4182 6 (b^C)(A^D) +4200 1 D(AB?0:c:C:0) +4300 3 D(BC?1:0:0:a) +440F 38 D?c:aB +444F 2 (aB)+(cd) +44F0 27 D?C:aB +453F 1 BD?1:c:ac:a +4B00 1 AD?0:0:b^C:c +4BB4 32 (aB)^c^d +4CC5 1 AB?cd:0:1:C^D +4DDD 1 AB?/CD\:0:1:/CD\ +4DFF 1 (AB?c:0:1:c)+d +4F00 90 ((aB)+c)D +4F44 73 (aB)+(cD) +4FF0 1 DC?0:1:1:aB +4FF4 1 (aB)+(D^C) +4FFF 6 (aB)+c+d +50B8 10 BD?C:A:aC:aC +50CF 11 DC?1:0:B:a +5130 1 BD?C:0:a:aC +5300 80 D(C?b:a) +5333 36 DC?b:b:b:a +533F 2 DC?1:b:b:a +53AC 8 (C?b:a)^d +53FC 1 DC?B:b:1:a +53FF 2 (C?b:a)+d +547F 1 AD?1:/BC\:/bc\:0 +553C 8 D?B^C:a +5603 2 AB?c^D:c:D:0 +5A3C 5 DC?B:A:b:a +5C00 1 D(c?a:B) +5CCC 11 DC?B:B:B:a +5CFF 1 (c?a:B)+d +5F03 3 DC?b:1:0:a +5F0C 3 DC?B:1:0:a +5FF3 2 DC?b:1:1:a +6000 67 CD(A^B) +6100 1 D(AB?c:C:C:0) +6350 2 AB?C^D:D:C:0 +6900 7 D(A^B^c) +6996 42 A^B^c^d +6FFF 4 (A^B)+c+d +7000 444 CD/AB\ +7007 30 (c^D)/AB\ +7077 895 /AB\(d+C) +7088 1 AD?0:B:C:bC +70CC 19 BD?0:1:C:aC +70FF 22 (C/AB\)+d +712B 1 AC?b:d:D:b +7150 1 AC?bD:0:1:bD +7303 1 BD?c:0:1:aC +730F 1 DC?1:b:0:/AB\ +733F 1 BD?1:c:1:aC +73C0 1 BD?0:C:1:aC +770F 134 D?c:/AB\ +7770 9 /AB\(D+C) +778F 2 AD?c:/bC\:1:b +77F0 7 D?C:/AB\ +7800 1 AD?0:0:C:B^C +7887 4 (AB)^C^d +78E1 1 AB?c^D:C:C:C^D +7C00 1 D(BC?0:1:1:a) +7C8C 1 BC?0:1:D:A^D +7D00 2 AD?0:0:1:B^C +7D0C 1 BC?aD:1:D:aD +7D55 8 AD?1:0:1:B^C +7EFF 1 (AB?C:1:1:c)+d +7F00 49 ((/AB\)+c)D +7F30 1 BD?C:0:1:/AC\ +7F50 1 AD?C:0:1:/BC\ +7F80 1 AD?0:BC:1:/BC\ +7FFF 25 /AB\+c+d +8000 884 ABCD +8001 58 AB?cd:0:0:CD +800D 1 DC?/Ab\:0:0:AB +8075 6 AC?d:0:d:b^D +80FF 8 (ABC)+d +8100 6 D(AB?c:0:0:C) +8700 15 AD?0:0:c:b^C +8778 7 (AB)^C^D +8788 7 (AB)^(cD) +87FF 1 AD?1:1:c:b^C +880F 2 D?c:AB +887C 1 BD?C:/AC\:0:A +888F 1 (AB)+(cd) +88F0 8 D?C:AB +8A3F 1 BD?1:c:Ac:A +8EE8 1 AB?0:C^D:C^D:1 +8F00 147 ((AB)+c)D +8F23 1 BD?/aC\:0:c:/aC\ +8F30 2 DC?0:1:b:AB +8F70 1 (C/AB\)^D +8F88 22 (AB)+(cD) +8FD0 1 AC?D:D:d:B +8FF0 1 DC?0:1:1:AB +8FFF 64 (AB)+c+d +9000 131 CD(a^B) +9003 2 DC?b:0:0:a^B +9009 205 (a^B)(D^c) +94DD 1 AD?1:B:B^C:BC +9600 7 D(A^B^C) +9669 33 A^B^c^D +9768 1 (AB?0:C:C:c)^D +9C0F 4 DC?1:B:0:a^B +9FFF 1 (a^B)+c+d +A03F 1 DC?1:0:b:A +A0CF 2 DC?1:0:B:A +A300 6 D(C?b:A) +A333 9 DC?b:b:b:A +A35C 2 (c?a:B)^D +A87F 1 AD?1:/BC\:0:/bc\ +AA3C 1 D?B^C:A +AB0E 6 AC?B^D:1:0:D +AC00 69 D(c?A:B) +AC53 9 (C?b:a)^D +ACCC 22 DC?B:B:B:A +ACFF 1 (c?A:B)+d +AF03 2 DC?b:1:0:A +B000 36 CD/aB\ +B00B 93 /aB\/D^C\ +B033 66 BD?1:0:C:AC +B0A2 2 AC?0:bd:bD:1 +B0BB 410 /aB\(d+C) +B0FF 14 (C/aB\)+d +B303 11 BD?c:0:1:AC +B30F 1 DC?1:b:0:/aB\ +B35C 1 DC?B:b:a:/aB\ +B3D5 1 AB?1:D:d:C +B400 2 AD?0:0:B^C:C +B44B 42 (aB)^c^D +B850 1 BD?aC:aC:C:A +BB0F 13 D?c:/aB\ +BBB0 18 /aB\(D+C) +BBF0 11 D?C:/aB\ +BC00 1 D(BC?0:1:1:A) +BCFF 1 (BC?0:1:1:A)+d +BE00 6 AD?0:0:B^C:1 +BEA0 10 AD?0:C:B^C:1 +BEAA 1 AD?0:1:B^C:1 +BEFF 1 A+d+(B^C) +BF00 102 ((/aB\)+c)D +BF30 6 BD?C:0:1:/aC\ +BF40 4 (aBC)^D +BF4C 1 BC?D:1:D:a^D +BFA0 1 AD?0:C:/BC\:1 +BFFF 7 /aB\+c+d +C00A 4 DC?A:0:0:B +C051 1 AB?d:0:C:CD +C0BE 1 BD?/ac\:/aC\:0:C +C0CD 3 BD?ac:1:0:C +C0F5 1 DC?a:0:1:B +C0FA 1 DC?A:0:1:B +C200 1 D(BC?A:0:0:1) +C230 1 BC?AD:0:d:D +C305 3 DC?a:b:0:B +C3AA 1 D?A:b^C +C3FA 1 DC?A:b:1:B +C500 20 D(C?a:B) +C531 1 BC?a:aD:d:D +C5FF 2 (C?a:B)+d +C6F5 325 AB?d:C^D:1:C +C700 2 D(BC?1:a:0:1) +CA00 178 D(C?A:B) +CACC 6 DC?B:A:B:B +CAFF 5 (C?A:B)+d +CB00 2 D(BC?1:A:0:1) +CC0B 1 BD?c:Ac:0:1 +CC0D 2 BD?ac:c:0:1 +CC70 18 BD?C:aC:0:1 +CCCA 1 DC?A:B:B:B +CDC0 1 BD?0:C:ac:1 +CDD0 4 DC?0:/Ab\:/Ab\:B +CDFC 1 BD?C:1:ac:1 +CE03 1 BD?c:0:Ac:1 +CEC0 30 BD?0:C:Ac:1 +CF0A 1 DC?A:1:0:B +CF10 1 BD?aC:0:c:1 +CF50 35 DC?0:1:a:B +CFA0 44 DC?0:1:A:B +CFFD 1 BD?/Ac\:1:c:1 +D000 74 CD/Ab\ +D222 1 AC?0:b:D:b^D +D300 2 D(BC?1:0:a:1) +D3FE 1 BD?/ac\:1:/AC\:C +D3FF 1 (BC?1:0:a:1)+d +D557 1 AB?1:cd:1:CD +D5F0 5 AC?D:0:1:/bD\ +D700 24 AD?0:0:1:b^C +D755 28 AD?1:0:1:b^C +DC03 1 BD?c:0:aC:1 +DC30 1 BD?C:0:aC:1 +DCAF 1 AD?c:1:/bc\:B +DCCF 1 BD?c:1:aC:1 +DFC0 16 BD?0:C:/AC\:1 +E000 28 CD/ab\ +E0EE 35 /ab\(d+C) +E0FF 8 (C/ab\)+d +E100 1 AD?0:0:b^C:C +E1FF 1 AD?1:1:b^C:C +E3FF 1 (BC?1:0:A:1)+d +E800 1 D(AB?0:C:C:1) +E888 1 AB?0:CD:CD:1 +E8EE 1 AB?0:/cD\:/cD\:1 +EBFF 4 A+d+(b^C) +EC0C 3 BD?0:c:AC:1 +EC0E 2 DC?/ab\:B:0:/ab\ +EC30 1 BD?C:0:AC:1 +ECC0 1 BD?0:C:AC:1 +EE0F 2 D?c:/ab\ +EEE0 6 /ab\(D+C) +EEF0 26 D?C:/ab\ +EF00 69 ((/ab\)+c)D +EF10 3 (abC)^D +EF30 1 BD?C:0:/aC\:1 +EFA0 1 AD?0:C:/bC\:1 +EFC0 9 BD?0:C:/aC\:1 +EFFF 3 /ab\+c+d +F011 5 D?ab:C +F044 23 D?aB:C +F077 4 D?/AB\:C +F088 48 D?AB:C +F0BA 1 AC?0:d:/Bd\:1 +F0BB 10 D?/aB\:C +F0D5 5 AC?d:0:1:/bd\ +F0EE 48 D?/ab\:C +F100 15 ((ab)+C)D +F111 4 (ab)+(CD) +F1FF 2 (ab)+C+d +F2FF 39 (Ab)+C+d +F305 17 DC?a:b:0:1 +F331 3 BD?/Ac\:0:1:C +F332 1 BD?/ac\:0:1:C +F3F5 177 DC?a:b:1:1 +F3FA 1 DC?A:b:1:1 +F400 79 ((aB)+C)D +F444 82 (aB)+(CD) +F4FB 1 AC?b^D:d:1:1 +F4FF 10 (aB)+C+d +F53F 104 DC?1:a:b:1 +F5F3 1 DC?b:a:1:1 +F5FC 7 DC?B:a:1:1 +F703 1 BD?c:0:1:/Ac\ +F70F 1 DC?1:/AB\:0:1 +F800 36 ((AB)+C)D +F807 5 (c/AB\)^D +F888 152 (AB)+(CD) +F88F 1 (c^D)+(AB) +F8FF 20 (AB)+C+d +FA30 2 DC?0:A:b:1 +FAC0 1 DC?0:A:B:1 +FAFC 3 DC?B:A:1:1 +FB03 1 BD?c:0:1:/ac\ +FC0A 37 DC?A:B:0:1 +FC1F 4 DC?1:B:ab:1 +FCF5 2 DC?a:B:1:1 +FCFA 33 DC?A:B:1:1 +FE00 40 ((/ab\)+C)D +FE7F 1 AB?/cD\:1:1:/Cd\ +FEFF 15 /ab\+C+d +FF01 3 (abc)+D +FF07 1 (c/AB\)+D +FF0B 14 (c/aB\)+D +FF0E 2 (c/ab\)+D +FF10 18 (abC)+D +FF40 37 (aBC)+D +FF70 54 (C/AB\)+D +FF80 68 (ABC)+D +FFB0 13 (C/aB\)+D +FFE0 5 (C/ab\)+D +FFE8 1 (AB?0:C:C:1)+D +FFF1 4 (ab)+C+D +FFF2 31 (Ab)+C+D +FFF4 8 (aB)+C+D +FFF8 48 (AB)+C+D +FFFE 30 /ab\+C+D + Gesamt:14221 DS4: 245 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut_report.txt b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut_report.txt new file mode 100644 index 0000000000000000000000000000000000000000..517dcbf8ce76cc532601c6081a81bf696994e704 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/lut_report.txt @@ -0,0 +1,26568 @@ + 1 LUT3 E0 C/ab\ + 2 LUT3 CA C?A:B + 3 LUT4 D000 CD/Ab\ + 4 LUT3 10 abC + 5 LUT4 00BF ((/aB\)+c)d + 6 LUT4 4000 aBCD + 7 LUT2 4 aB + 8 LUT3 10 abC + 9 LUT4 1000 abCD + 10 LUT4 B000 CD/aB\ + 11 LUT4 7F00 ((/AB\)+c)D + 12 LUT4 5CCC DC?B:B:B:a + 13 LUT3 40 aBC + 14 LUT2 8 AB + 15 LUT3 80 ABC + 16 LUT3 10 abC + 17 LUT3 10 abC + 18 LUT4 7F00 ((/AB\)+c)D + 19 LUT3 E0 C/ab\ + 20 LUT4 007F ((/AB\)+c)d + 21 LUT4 001F ((ab)+c)d + 22 LUT4 001F ((ab)+c)d + 23 LUT3 E0 C/ab\ + 24 LUT4 0071 d(AB?1:C:C:0) + 25 LUT3 80 ABC + 26 LUT4 7F00 ((/AB\)+c)D + 27 LUT3 E0 C/ab\ + 28 LUT4 007F ((/AB\)+c)d + 29 LUT4 001F ((ab)+c)d + 30 LUT3 80 ABC + 31 LUT4 007F ((/AB\)+c)d + 32 LUT4 001F ((ab)+c)d + 33 LUT4 7F00 ((/AB\)+c)D + 34 LUT3 E0 C/ab\ + 35 LUT4 4000 aBCD + 36 LUT2 4 aB + 37 LUT3 10 abC + 38 LUT2 4 aB + 39 LUT4 1000 abCD + 40 LUT3 0D c/Ab\ + 41 LUT3 E0 C/ab\ + 42 LUT2 8 AB + 43 LUT3 10 abC + 44 LUT2 1 ab + 45 LUT2 8 AB + 46 LUT4 A333 DC?b:b:b:A + 47 LUT4 B0BB /aB\(d+C) + 48 LUT2 4 aB + 49 LUT2 4 aB + 50 LUT2 1 ab + 51 LUT2 8 AB + 52 LUT3 35 c?b:a + 53 LUT2 8 AB + 54 LUT2 8 AB + 55 LUT3 40 aBC + 56 LUT3 1F (ab)+c + 57 LUT2 4 aB + 58 LUT3 40 aBC + 59 LUT2 8 AB + 60 LUT3 01 abc + 61 LUT3 1F (ab)+c + 62 LUT2 4 aB + 63 LUT3 D0 C/Ab\ + 64 LUT4 FF80 (ABC)+D + 65 LUT3 80 ABC + 66 LUT3 40 aBC + 67 LUT3 40 aBC + 68 LUT4 007F ((/AB\)+c)d + 69 LUT3 80 ABC + 70 LUT3 40 aBC + 71 LUT3 40 aBC + 72 LUT4 BF00 ((/aB\)+c)D + 73 LUT4 0007 cd/AB\ + 74 LUT2 4 aB + 75 LUT3 40 aBC + 76 LUT3 40 aBC + 77 LUT4 B0BB /aB\(d+C) + 78 LUT2 4 aB + 79 LUT4 8000 ABCD + 80 LUT3 01 abc + 81 LUT4 0001 abcd + 82 LUT3 B0 C/aB\ + 83 LUT4 8000 ABCD + 84 LUT4 5CCC DC?B:B:B:a + 85 LUT4 5333 DC?b:b:b:a + 86 LUT4 E0EE /ab\(d+C) + 87 LUT4 0C0A DC?A:B:0:0 + 88 LUT4 EF00 ((/ab\)+c)D + 89 LUT4 1000 abCD + 90 LUT3 80 ABC + 91 LUT3 80 ABC + 92 LUT4 5CCC DC?B:B:B:a + 93 LUT4 5333 DC?b:b:b:a + 94 LUT4 E0EE /ab\(d+C) + 95 LUT3 B0 C/aB\ + 96 LUT4 CA00 D(C?A:B) + 97 LUT4 CA00 D(C?A:B) + 98 LUT3 10 abC + 99 LUT4 0100 abcD + 100 LUT4 00BF ((/aB\)+c)d + 101 LUT2 4 aB + 102 LUT2 4 aB + 103 LUT3 40 aBC + 104 LUT2 B /aB\ + 105 LUT2 8 AB + 106 LUT3 F1 (ab)+C + 107 LUT3 10 abC + 108 LUT3 F1 (ab)+C + 109 LUT3 80 ABC + 110 LUT3 10 abC + 111 LUT4 4000 aBCD + 112 LUT2 B /aB\ + 113 LUT2 8 AB + 114 LUT3 80 ABC + 115 LUT4 1000 abCD + 116 LUT2 4 aB + 117 LUT4 4000 aBCD + 118 LUT4 1000 abCD + 119 LUT4 4000 aBCD + 120 LUT3 40 aBC + 121 LUT3 40 aBC + 122 LUT2 6 A^B + 123 LUT3 40 aBC + 124 LUT3 10 abC + 125 LUT4 00EF ((/ab\)+c)d + 126 LUT2 4 aB + 127 LUT3 10 abC + 128 LUT4 000E cd/ab\ + 129 LUT4 0100 abcD + 130 LUT4 FF0E (c/ab\)+D + 131 LUT4 0700 cD/AB\ + 132 LUT4 4F00 ((aB)+c)D + 133 LUT4 F400 ((aB)+C)D + 134 LUT3 F8 (AB)+C + 135 LUT2 8 AB + 136 LUT2 1 ab + 137 LUT3 07 c/AB\ + 138 LUT2 8 AB + 139 LUT4 4F00 ((aB)+c)D + 140 LUT4 008F ((AB)+c)d + 141 LUT4 4F00 ((aB)+c)D + 142 LUT3 D0 C/Ab\ + 143 LUT2 8 AB + 144 LUT2 4 aB + 145 LUT4 F331 BD?/Ac\:0:1:C + 146 LUT4 00FE ((/ab\)+C)d + 147 LUT4 BF00 ((/aB\)+c)D + 148 LUT4 7F00 ((/AB\)+c)D + 149 LUT4 4F00 ((aB)+c)D + 150 LUT2 4 aB + 151 LUT4 F800 ((AB)+C)D + 152 LUT4 8000 ABCD + 153 LUT4 0D00 cD/Ab\ + 154 LUT4 0100 abcD + 155 LUT3 40 aBC + 156 LUT3 FE /ab\+C + 157 LUT3 01 abc + 158 LUT3 01 abc + 159 LUT3 FE /ab\+C + 160 LUT2 4 aB + 161 LUT3 01 abc + 162 LUT4 FF40 (aBC)+D + 163 LUT2 4 aB + 164 LUT2 1 ab + 165 LUT3 01 abc + 166 LUT3 10 abC + 167 LUT3 80 ABC + 168 LUT2 4 aB + 169 LUT2 8 AB + 170 LUT4 A333 DC?b:b:b:A + 171 LUT3 0D c/Ab\ + 172 LUT4 AC00 D(c?A:B) + 173 LUT3 10 abC + 174 LUT3 B0 C/aB\ + 175 LUT4 1000 abCD + 176 LUT4 0B00 cD/aB\ + 177 LUT4 F2FF (Ab)+C+d + 178 LUT4 F444 (aB)+(CD) + 179 LUT3 D0 C/Ab\ + 180 LUT2 8 AB + 181 LUT4 1000 abCD + 182 LUT4 1000 abCD + 183 LUT4 004F ((aB)+c)d + 184 LUT4 8F88 (AB)+(cD) + 185 LUT2 4 aB + 186 LUT2 1 ab + 187 LUT3 80 ABC + 188 LUT4 FF0B (c/aB\)+D + 189 LUT4 C5FF (C?a:B)+d + 190 LUT3 10 abC + 191 LUT3 07 c/AB\ + 192 LUT2 8 AB + 193 LUT3 3A c?b:A + 194 LUT2 8 AB + 195 LUT4 5333 DC?b:b:b:a + 196 LUT4 E0EE /ab\(d+C) + 197 LUT4 CA00 D(C?A:B) + 198 LUT3 1F (ab)+c + 199 LUT2 8 AB + 200 LUT3 3A c?b:A + 201 LUT4 5333 DC?b:b:b:a + 202 LUT4 E0EE /ab\(d+C) + 203 LUT4 CA00 D(C?A:B) + 204 LUT3 E0 C/ab\ + 205 LUT2 8 AB + 206 LUT2 8 AB + 207 LUT2 8 AB + 208 LUT2 1 ab + 209 LUT2 4 aB + 210 LUT2 4 aB + 211 LUT3 78 (AB)^C + 212 LUT2 8 AB + 213 LUT2 8 AB + 214 LUT2 8 AB + 215 LUT2 8 AB + 216 LUT2 8 AB + 217 LUT2 8 AB + 218 LUT2 8 AB + 219 LUT2 8 AB + 220 LUT2 8 AB + 221 LUT2 8 AB + 222 LUT2 8 AB + 223 LUT4 9009 (a^B)(D^c) + 224 LUT2 8 AB + 225 LUT2 8 AB + 226 LUT2 8 AB + 227 LUT2 8 AB + 228 LUT4 9009 (a^B)(D^c) + 229 LUT2 8 AB + 230 LUT2 8 AB + 231 LUT2 8 AB + 232 LUT2 8 AB + 233 LUT4 B00B /aB\/D^C\ + 234 LUT2 8 AB + 235 LUT2 8 AB + 236 LUT2 8 AB + 237 LUT2 8 AB + 238 LUT4 9009 (a^B)(D^c) + 239 LUT2 8 AB + 240 LUT2 8 AB + 241 LUT2 8 AB + 242 LUT2 8 AB + 243 LUT2 8 AB + 244 LUT2 8 AB + 245 LUT2 8 AB + 246 LUT2 8 AB + 247 LUT2 8 AB + 248 LUT2 8 AB + 249 LUT4 9009 (a^B)(D^c) + 250 LUT2 8 AB + 251 LUT2 8 AB + 252 LUT2 8 AB + 253 LUT2 8 AB + 254 LUT2 8 AB + 255 LUT2 8 AB + 256 LUT3 80 ABC + 257 LUT3 90 C(a^B) + 258 LUT4 B00B /aB\/D^C\ + 259 LUT2 8 AB + 260 LUT2 8 AB + 261 LUT2 8 AB + 262 LUT2 8 AB + 263 LUT4 9009 (a^B)(D^c) + 264 LUT2 8 AB + 265 LUT2 8 AB + 266 LUT2 8 AB + 267 LUT2 8 AB + 268 LUT4 9009 (a^B)(D^c) + 269 LUT2 8 AB + 270 LUT2 8 AB + 271 LUT2 8 AB + 272 LUT2 8 AB + 273 LUT3 90 C(a^B) + 274 LUT4 9009 (a^B)(D^c) + 275 LUT2 8 AB + 276 LUT2 8 AB + 277 LUT2 8 AB + 278 LUT2 8 AB + 279 LUT2 8 AB + 280 LUT2 8 AB + 281 LUT2 6 A^B + 282 LUT2 8 AB + 283 LUT2 8 AB + 284 LUT2 4 aB + 285 LUT2 6 A^B + 286 LUT3 40 aBC + 287 LUT4 0001 abcd + 288 LUT3 CA C?A:B + 289 LUT2 8 AB + 290 LUT4 0001 abcd + 291 LUT3 F8 (AB)+C + 292 LUT4 1000 abCD + 293 LUT4 0100 abcD + 294 LUT4 0001 abcd + 295 LUT3 AC c?A:B + 296 LUT4 FFE0 (C/ab\)+D + 297 LUT2 1 ab + 298 LUT3 40 aBC + 299 LUT3 40 aBC + 300 LUT3 0B c/aB\ + 301 LUT4 1F00 ((ab)+c)D + 302 LUT3 70 C/AB\ + 303 LUT3 CA C?A:B + 304 LUT3 CA C?A:B + 305 LUT2 8 AB + 306 LUT3 80 ABC + 307 LUT2 8 AB + 308 LUT2 8 AB + 309 LUT4 4F00 ((aB)+c)D + 310 LUT4 0100 abcD + 311 LUT4 0001 abcd + 312 LUT4 0001 abcd + 313 LUT4 FFF8 (AB)+C+D + 314 LUT2 4 aB + 315 LUT4 FFF8 (AB)+C+D + 316 LUT4 FFF8 (AB)+C+D + 317 LUT3 C5 C?a:B + 318 LUT3 35 c?b:a + 319 LUT2 B /aB\ + 320 LUT2 8 AB + 321 LUT4 BF00 ((/aB\)+c)D + 322 LUT3 C5 C?a:B + 323 LUT3 53 C?b:a + 324 LUT4 F1FF (ab)+C+d + 325 LUT3 40 aBC + 326 LUT2 4 aB + 327 LUT4 FF01 (abc)+D + 328 LUT2 8 AB + 329 LUT4 00F4 ((aB)+C)d + 330 LUT4 4F00 ((aB)+c)D + 331 LUT2 8 AB + 332 LUT2 8 AB + 333 LUT2 8 AB + 334 LUT4 8000 ABCD + 335 LUT3 90 C(a^B) + 336 LUT3 90 C(a^B) + 337 LUT3 80 ABC + 338 LUT3 90 C(a^B) + 339 LUT4 B00B /aB\/D^C\ + 340 LUT4 B00B /aB\/D^C\ + 341 LUT4 9009 (a^B)(D^c) + 342 LUT3 90 C(a^B) + 343 LUT4 9000 CD(a^B) + 344 LUT4 9000 CD(a^B) + 345 LUT4 9000 CD(a^B) + 346 LUT4 9009 (a^B)(D^c) + 347 LUT4 B00B /aB\/D^C\ + 348 LUT3 90 C(a^B) + 349 LUT4 9009 (a^B)(D^c) + 350 LUT4 0777 /AB\(d+c) + 351 LUT2 8 AB + 352 LUT4 9000 CD(a^B) + 353 LUT4 9000 CD(a^B) + 354 LUT3 40 aBC + 355 LUT4 B00B /aB\/D^C\ + 356 LUT4 9009 (a^B)(D^c) + 357 LUT4 9000 CD(a^B) + 358 LUT4 9009 (a^B)(D^c) + 359 LUT4 9009 (a^B)(D^c) + 360 LUT4 007F ((/AB\)+c)d + 361 LUT4 9000 CD(a^B) + 362 LUT3 90 C(a^B) + 363 LUT4 B0BB /aB\(d+C) + 364 LUT4 9009 (a^B)(D^c) + 365 LUT3 90 C(a^B) + 366 LUT3 90 C(a^B) + 367 LUT3 40 aBC + 368 LUT4 B0BB /aB\(d+C) + 369 LUT3 90 C(a^B) + 370 LUT4 B00B /aB\/D^C\ + 371 LUT4 9000 CD(a^B) + 372 LUT4 D000 CD/Ab\ + 373 LUT4 B0BB /aB\(d+C) + 374 LUT4 B00B /aB\/D^C\ + 375 LUT3 90 C(a^B) + 376 LUT4 B0BB /aB\(d+C) + 377 LUT4 9000 CD(a^B) + 378 LUT3 90 C(a^B) + 379 LUT4 B0BB /aB\(d+C) + 380 LUT4 9009 (a^B)(D^c) + 381 LUT4 9000 CD(a^B) + 382 LUT3 90 C(a^B) + 383 LUT4 9009 (a^B)(D^c) + 384 LUT4 9009 (a^B)(D^c) + 385 LUT4 8000 ABCD + 386 LUT3 90 C(a^B) + 387 LUT3 90 C(a^B) + 388 LUT3 40 aBC + 389 LUT4 E0EE /ab\(d+C) + 390 LUT2 4 aB + 391 LUT3 80 ABC + 392 LUT4 B00B /aB\/D^C\ + 393 LUT4 9009 (a^B)(D^c) + 394 LUT4 9009 (a^B)(D^c) + 395 LUT4 9009 (a^B)(D^c) + 396 LUT4 8000 ABCD + 397 LUT3 90 C(a^B) + 398 LUT4 9009 (a^B)(D^c) + 399 LUT4 9000 CD(a^B) + 400 LUT4 9009 (a^B)(D^c) + 401 LUT4 9009 (a^B)(D^c) + 402 LUT4 B00B /aB\/D^C\ + 403 LUT4 9009 (a^B)(D^c) + 404 LUT4 8000 ABCD + 405 LUT4 9009 (a^B)(D^c) + 406 LUT4 9009 (a^B)(D^c) + 407 LUT4 9009 (a^B)(D^c) + 408 LUT4 9009 (a^B)(D^c) + 409 LUT4 9000 CD(a^B) + 410 LUT3 90 C(a^B) + 411 LUT4 9009 (a^B)(D^c) + 412 LUT4 9009 (a^B)(D^c) + 413 LUT3 90 C(a^B) + 414 LUT4 B00B /aB\/D^C\ + 415 LUT4 1001 ab(c^D) + 416 LUT2 4 aB + 417 LUT2 4 aB + 418 LUT4 9000 CD(a^B) + 419 LUT4 9000 CD(a^B) + 420 LUT4 B0BB /aB\(d+C) + 421 LUT4 B00B /aB\/D^C\ + 422 LUT4 B00B /aB\/D^C\ + 423 LUT4 0BBB /aB\(d+c) + 424 LUT4 9000 CD(a^B) + 425 LUT3 40 aBC + 426 LUT4 9009 (a^B)(D^c) + 427 LUT4 B0BB /aB\(d+C) + 428 LUT4 B00B /aB\/D^C\ + 429 LUT4 9000 CD(a^B) + 430 LUT3 90 C(a^B) + 431 LUT4 9009 (a^B)(D^c) + 432 LUT4 9009 (a^B)(D^c) + 433 LUT3 40 aBC + 434 LUT4 1000 abCD + 435 LUT2 4 aB + 436 LUT3 0B c/aB\ + 437 LUT2 4 aB + 438 LUT3 01 abc + 439 LUT4 0001 abcd + 440 LUT2 1 ab + 441 LUT4 0700 cD/AB\ + 442 LUT2 1 ab + 443 LUT3 40 aBC + 444 LUT4 0007 cd/AB\ + 445 LUT4 0C0A DC?A:B:0:0 + 446 LUT3 10 abC + 447 LUT2 4 aB + 448 LUT2 4 aB + 449 LUT2 8 AB + 450 LUT3 40 aBC + 451 LUT4 7F00 ((/AB\)+c)D + 452 LUT2 1 ab + 453 LUT4 BF00 ((/aB\)+c)D + 454 LUT2 1 ab + 455 LUT3 10 abC + 456 LUT3 D0 C/Ab\ + 457 LUT2 4 aB + 458 LUT2 4 aB + 459 LUT2 8 AB + 460 LUT2 4 aB + 461 LUT3 10 abC + 462 LUT2 4 aB + 463 LUT3 AC c?A:B + 464 LUT3 CA C?A:B + 465 LUT3 10 abC + 466 LUT2 4 aB + 467 LUT4 F800 ((AB)+C)D + 468 LUT4 0D00 cD/Ab\ + 469 LUT2 1 ab + 470 LUT4 FF80 (ABC)+D + 471 LUT2 8 AB + 472 LUT2 1 ab + 473 LUT2 4 aB + 474 LUT2 4 aB + 475 LUT3 F8 (AB)+C + 476 LUT2 4 aB + 477 LUT2 8 AB + 478 LUT2 4 aB + 479 LUT2 4 aB + 480 LUT2 1 ab + 481 LUT2 4 aB + 482 LUT3 70 C/AB\ + 483 LUT2 8 AB + 484 LUT2 4 aB + 485 LUT3 80 ABC + 486 LUT3 80 ABC + 487 LUT2 8 AB + 488 LUT2 8 AB + 489 LUT2 8 AB + 490 LUT2 4 aB + 491 LUT2 4 aB + 492 LUT2 4 aB + 493 LUT2 8 AB + 494 LUT2 1 ab + 495 LUT2 4 aB + 496 LUT3 4F (aB)+c + 497 LUT2 8 AB + 498 LUT3 E0 C/ab\ + 499 LUT2 8 AB + 500 LUT3 40 aBC + 501 LUT2 1 ab + 502 LUT4 E000 CD/ab\ + 503 LUT2 8 AB + 504 LUT3 CA C?A:B + 505 LUT4 8000 ABCD + 506 LUT4 AC00 D(c?A:B) + 507 LUT3 CA C?A:B + 508 LUT2 8 AB + 509 LUT2 8 AB + 510 LUT3 5C c?a:B + 511 LUT3 35 c?b:a + 512 LUT2 4 aB + 513 LUT2 E /ab\ + 514 LUT4 0B00 cD/aB\ + 515 LUT4 8000 ABCD + 516 LUT4 8000 ABCD + 517 LUT4 4000 aBCD + 518 LUT4 4000 aBCD + 519 LUT2 6 A^B + 520 LUT3 D0 C/Ab\ + 521 LUT4 0700 cD/AB\ + 522 LUT4 7F00 ((/AB\)+c)D + 523 LUT2 8 AB + 524 LUT2 4 aB + 525 LUT3 10 abC + 526 LUT2 4 aB + 527 LUT4 0B00 cD/aB\ + 528 LUT3 07 c/AB\ + 529 LUT2 8 AB + 530 LUT2 8 AB + 531 LUT4 004F ((aB)+c)d + 532 LUT2 8 AB + 533 LUT4 00F4 ((aB)+C)d + 534 LUT3 3A c?b:A + 535 LUT4 0E00 cD/ab\ + 536 LUT2 1 ab + 537 LUT4 7770 /AB\(D+C) + 538 LUT2 4 aB + 539 LUT4 00F1 ((ab)+C)d + 540 LUT4 EF00 ((/ab\)+c)D + 541 LUT3 0D c/Ab\ + 542 LUT3 70 C/AB\ + 543 LUT4 0305 DC?a:b:0:0 + 544 LUT3 70 C/AB\ + 545 LUT2 4 aB + 546 LUT4 F3F5 DC?a:b:1:1 + 547 LUT3 70 C/AB\ + 548 LUT2 4 aB + 549 LUT4 F3F5 DC?a:b:1:1 + 550 LUT3 70 C/AB\ + 551 LUT2 1 ab + 552 LUT4 F53F DC?1:a:b:1 + 553 LUT2 1 ab + 554 LUT4 0305 DC?a:b:0:0 + 555 LUT3 70 C/AB\ + 556 LUT4 F53F DC?1:a:b:1 + 557 LUT3 70 C/AB\ + 558 LUT4 F53F DC?1:a:b:1 + 559 LUT4 0305 DC?a:b:0:0 + 560 LUT3 70 C/AB\ + 561 LUT4 F53F DC?1:a:b:1 + 562 LUT3 70 C/AB\ + 563 LUT4 F53F DC?1:a:b:1 + 564 LUT3 70 C/AB\ + 565 LUT4 0305 DC?a:b:0:0 + 566 LUT3 70 C/AB\ + 567 LUT4 F53F DC?1:a:b:1 + 568 LUT3 70 C/AB\ + 569 LUT4 F53F DC?1:a:b:1 + 570 LUT4 F111 (ab)+(CD) + 571 LUT4 0305 DC?a:b:0:0 + 572 LUT3 70 C/AB\ + 573 LUT4 F53F DC?1:a:b:1 + 574 LUT3 70 C/AB\ + 575 LUT4 F53F DC?1:a:b:1 + 576 LUT4 0305 DC?a:b:0:0 + 577 LUT3 70 C/AB\ + 578 LUT4 F53F DC?1:a:b:1 + 579 LUT3 70 C/AB\ + 580 LUT4 F53F DC?1:a:b:1 + 581 LUT3 E0 C/ab\ + 582 LUT3 70 C/AB\ + 583 LUT4 0305 DC?a:b:0:0 + 584 LUT3 70 C/AB\ + 585 LUT4 F53F DC?1:a:b:1 + 586 LUT3 70 C/AB\ + 587 LUT4 F53F DC?1:a:b:1 + 588 LUT2 4 aB + 589 LUT4 0305 DC?a:b:0:0 + 590 LUT3 70 C/AB\ + 591 LUT4 F53F DC?1:a:b:1 + 592 LUT3 70 C/AB\ + 593 LUT4 F53F DC?1:a:b:1 + 594 LUT3 35 c?b:a + 595 LUT3 70 C/AB\ + 596 LUT4 F53F DC?1:a:b:1 + 597 LUT3 70 C/AB\ + 598 LUT4 F53F DC?1:a:b:1 + 599 LUT4 0007 cd/AB\ + 600 LUT3 70 C/AB\ + 601 LUT4 0305 DC?a:b:0:0 + 602 LUT3 70 C/AB\ + 603 LUT4 F53F DC?1:a:b:1 + 604 LUT3 70 C/AB\ + 605 LUT4 F53F DC?1:a:b:1 + 606 LUT4 F111 (ab)+(CD) + 607 LUT4 0700 cD/AB\ + 608 LUT4 0305 DC?a:b:0:0 + 609 LUT3 70 C/AB\ + 610 LUT4 F53F DC?1:a:b:1 + 611 LUT3 70 C/AB\ + 612 LUT4 F53F DC?1:a:b:1 + 613 LUT2 4 aB + 614 LUT4 00F8 ((AB)+C)d + 615 LUT4 0100 abcD + 616 LUT3 70 C/AB\ + 617 LUT4 0700 cD/AB\ + 618 LUT4 0700 cD/AB\ + 619 LUT3 35 c?b:a + 620 LUT3 70 C/AB\ + 621 LUT4 F53F DC?1:a:b:1 + 622 LUT3 70 C/AB\ + 623 LUT4 F53F DC?1:a:b:1 + 624 LUT4 F111 (ab)+(CD) + 625 LUT4 0305 DC?a:b:0:0 + 626 LUT3 70 C/AB\ + 627 LUT4 F53F DC?1:a:b:1 + 628 LUT3 70 C/AB\ + 629 LUT4 F53F DC?1:a:b:1 + 630 LUT4 0305 DC?a:b:0:0 + 631 LUT3 70 C/AB\ + 632 LUT4 F53F DC?1:a:b:1 + 633 LUT3 70 C/AB\ + 634 LUT4 F53F DC?1:a:b:1 + 635 LUT2 4 aB + 636 LUT3 70 C/AB\ + 637 LUT2 4 aB + 638 LUT4 1F00 ((ab)+c)D + 639 LUT4 7F00 ((/AB\)+c)D + 640 LUT3 40 aBC + 641 LUT4 F111 (ab)+(CD) + 642 LUT4 0305 DC?a:b:0:0 + 643 LUT3 70 C/AB\ + 644 LUT4 F53F DC?1:a:b:1 + 645 LUT3 70 C/AB\ + 646 LUT4 F53F DC?1:a:b:1 + 647 LUT4 0305 DC?a:b:0:0 + 648 LUT3 70 C/AB\ + 649 LUT4 F53F DC?1:a:b:1 + 650 LUT3 70 C/AB\ + 651 LUT4 F53F DC?1:a:b:1 + 652 LUT4 BB0F D?c:/aB\ + 653 LUT2 4 aB + 654 LUT3 40 aBC + 655 LUT3 B0 C/aB\ + 656 LUT4 000B cd/aB\ + 657 LUT4 4000 aBCD + 658 LUT2 4 aB + 659 LUT4 0100 abcD + 660 LUT3 70 C/AB\ + 661 LUT3 40 aBC + 662 LUT2 4 aB + 663 LUT2 4 aB + 664 LUT4 0100 abcD + 665 LUT2 4 aB + 666 LUT3 E0 C/ab\ + 667 LUT2 8 AB + 668 LUT4 7770 /AB\(D+C) + 669 LUT3 01 abc + 670 LUT4 4000 aBCD + 671 LUT4 EEE0 /ab\(D+C) + 672 LUT3 0D c/Ab\ + 673 LUT3 07 c/AB\ + 674 LUT4 7770 /AB\(D+C) + 675 LUT3 40 aBC + 676 LUT4 70FF (C/AB\)+d + 677 LUT4 7077 /AB\(d+C) + 678 LUT4 8000 ABCD + 679 LUT3 F1 (ab)+C + 680 LUT4 4F00 ((aB)+c)D + 681 LUT4 00BF ((/aB\)+c)d + 682 LUT2 8 AB + 683 LUT3 40 aBC + 684 LUT2 8 AB + 685 LUT3 70 C/AB\ + 686 LUT4 FF0B (c/aB\)+D + 687 LUT4 0100 abcD + 688 LUT4 F400 ((aB)+C)D + 689 LUT4 3500 D(c?b:a) + 690 LUT3 70 C/AB\ + 691 LUT4 0777 /AB\(d+c) + 692 LUT3 70 C/AB\ + 693 LUT4 F53F DC?1:a:b:1 + 694 LUT3 70 C/AB\ + 695 LUT4 F3F5 DC?a:b:1:1 + 696 LUT2 4 aB + 697 LUT2 8 AB + 698 LUT4 EEE0 /ab\(D+C) + 699 LUT4 B0BB /aB\(d+C) + 700 LUT4 BF00 ((/aB\)+c)D + 701 LUT3 01 abc + 702 LUT2 4 aB + 703 LUT2 4 aB + 704 LUT3 07 c/AB\ + 705 LUT2 4 aB + 706 LUT2 4 aB + 707 LUT4 B0BB /aB\(d+C) + 708 LUT4 BF00 ((/aB\)+c)D + 709 LUT2 4 aB + 710 LUT4 0700 cD/AB\ + 711 LUT2 8 AB + 712 LUT3 0E c/ab\ + 713 LUT3 0E c/ab\ + 714 LUT2 4 aB + 715 LUT2 8 AB + 716 LUT4 F400 ((aB)+C)D + 717 LUT4 3500 D(c?b:a) + 718 LUT3 70 C/AB\ + 719 LUT4 0777 /AB\(d+c) + 720 LUT3 70 C/AB\ + 721 LUT4 F3F5 DC?a:b:1:1 + 722 LUT4 EEE0 /ab\(D+C) + 723 LUT4 B0BB /aB\(d+C) + 724 LUT4 BF00 ((/aB\)+c)D + 725 LUT4 B0BB /aB\(d+C) + 726 LUT3 D0 C/Ab\ + 727 LUT2 8 AB + 728 LUT4 F400 ((aB)+C)D + 729 LUT4 3500 D(c?b:a) + 730 LUT3 70 C/AB\ + 731 LUT4 0777 /AB\(d+c) + 732 LUT3 70 C/AB\ + 733 LUT4 F3F5 DC?a:b:1:1 + 734 LUT4 F400 ((aB)+C)D + 735 LUT4 3500 D(c?b:a) + 736 LUT3 70 C/AB\ + 737 LUT4 0777 /AB\(d+c) + 738 LUT3 70 C/AB\ + 739 LUT4 F3F5 DC?a:b:1:1 + 740 LUT4 0100 abcD + 741 LUT3 F4 (aB)+C + 742 LUT4 7000 CD/AB\ + 743 LUT2 1 ab + 744 LUT2 8 AB + 745 LUT4 F800 ((AB)+C)D + 746 LUT4 0100 abcD + 747 LUT4 F400 ((aB)+C)D + 748 LUT4 3500 D(c?b:a) + 749 LUT3 70 C/AB\ + 750 LUT4 0777 /AB\(d+c) + 751 LUT3 70 C/AB\ + 752 LUT4 F3F5 DC?a:b:1:1 + 753 LUT4 00F4 ((aB)+C)d + 754 LUT4 0700 cD/AB\ + 755 LUT4 F400 ((aB)+C)D + 756 LUT2 8 AB + 757 LUT3 80 ABC + 758 LUT2 1 ab + 759 LUT2 8 AB + 760 LUT3 0D c/Ab\ + 761 LUT3 70 C/AB\ + 762 LUT4 0100 abcD + 763 LUT4 8FFF (AB)+c+d + 764 LUT3 80 ABC + 765 LUT2 8 AB + 766 LUT4 00F4 ((aB)+C)d + 767 LUT4 0700 cD/AB\ + 768 LUT2 8 AB + 769 LUT3 40 aBC + 770 LUT4 5FF3 DC?b:1:1:a + 771 LUT2 4 aB + 772 LUT2 8 AB + 773 LUT4 4000 aBCD + 774 LUT4 0001 abcd + 775 LUT4 0001 abcd + 776 LUT4 4000 aBCD + 777 LUT4 00F4 ((aB)+C)d + 778 LUT3 B0 C/aB\ + 779 LUT2 4 aB + 780 LUT3 70 C/AB\ + 781 LUT4 AC00 D(c?A:B) + 782 LUT3 07 c/AB\ + 783 LUT3 40 aBC + 784 LUT4 004F ((aB)+c)d + 785 LUT3 40 aBC + 786 LUT2 4 aB + 787 LUT2 1 ab + 788 LUT3 01 abc + 789 LUT4 F400 ((aB)+C)D + 790 LUT4 3500 D(c?b:a) + 791 LUT3 70 C/AB\ + 792 LUT4 0777 /AB\(d+c) + 793 LUT3 70 C/AB\ + 794 LUT4 F3F5 DC?a:b:1:1 + 795 LUT4 F100 ((ab)+C)D + 796 LUT2 1 ab + 797 LUT3 80 ABC + 798 LUT2 4 aB + 799 LUT3 0E c/ab\ + 800 LUT4 4F00 ((aB)+c)D + 801 LUT3 40 aBC + 802 LUT4 007F ((/AB\)+c)d + 803 LUT4 001F ((ab)+c)d + 804 LUT4 F400 ((aB)+C)D + 805 LUT4 3500 D(c?b:a) + 806 LUT3 70 C/AB\ + 807 LUT4 0777 /AB\(d+c) + 808 LUT3 70 C/AB\ + 809 LUT4 F3F5 DC?a:b:1:1 + 810 LUT4 FF0B (c/aB\)+D + 811 LUT3 B0 C/aB\ + 812 LUT2 4 aB + 813 LUT3 07 c/AB\ + 814 LUT3 E0 C/ab\ + 815 LUT3 01 abc + 816 LUT2 8 AB + 817 LUT2 8 AB + 818 LUT4 F3F5 DC?a:b:1:1 + 819 LUT4 F3F5 DC?a:b:1:1 + 820 LUT4 008F ((AB)+c)d + 821 LUT4 F53F DC?1:a:b:1 + 822 LUT4 8F00 ((AB)+c)D + 823 LUT4 F53F DC?1:a:b:1 + 824 LUT3 3A c?b:A + 825 LUT2 1 ab + 826 LUT4 00F4 ((aB)+C)d + 827 LUT4 F400 ((aB)+C)D + 828 LUT4 3500 D(c?b:a) + 829 LUT3 70 C/AB\ + 830 LUT4 0777 /AB\(d+c) + 831 LUT3 70 C/AB\ + 832 LUT4 F3F5 DC?a:b:1:1 + 833 LUT4 888F (AB)+(cd) + 834 LUT3 D0 C/Ab\ + 835 LUT4 001F ((ab)+c)d + 836 LUT4 FF0B (c/aB\)+D + 837 LUT4 008F ((AB)+c)d + 838 LUT4 FE00 ((/ab\)+C)D + 839 LUT4 F400 ((aB)+C)D + 840 LUT4 3500 D(c?b:a) + 841 LUT3 70 C/AB\ + 842 LUT4 0777 /AB\(d+c) + 843 LUT3 70 C/AB\ + 844 LUT4 F3F5 DC?a:b:1:1 + 845 LUT4 F3F5 DC?a:b:1:1 + 846 LUT4 F3F5 DC?a:b:1:1 + 847 LUT3 F1 (ab)+C + 848 LUT3 40 aBC + 849 LUT3 70 C/AB\ + 850 LUT3 07 c/AB\ + 851 LUT4 D000 CD/Ab\ + 852 LUT4 F400 ((aB)+C)D + 853 LUT4 3500 D(c?b:a) + 854 LUT3 70 C/AB\ + 855 LUT4 0777 /AB\(d+c) + 856 LUT3 70 C/AB\ + 857 LUT4 F3F5 DC?a:b:1:1 + 858 LUT4 F53F DC?1:a:b:1 + 859 LUT4 F53F DC?1:a:b:1 + 860 LUT3 F1 (ab)+C + 861 LUT3 10 abC + 862 LUT3 E0 C/ab\ + 863 LUT4 1F00 ((ab)+c)D + 864 LUT4 001F ((ab)+c)d + 865 LUT4 F400 ((aB)+C)D + 866 LUT4 3500 D(c?b:a) + 867 LUT3 70 C/AB\ + 868 LUT4 0777 /AB\(d+c) + 869 LUT3 70 C/AB\ + 870 LUT4 F3F5 DC?a:b:1:1 + 871 LUT4 F3F5 DC?a:b:1:1 + 872 LUT4 F3F5 DC?a:b:1:1 + 873 LUT3 F1 (ab)+C + 874 LUT4 0D00 cD/Ab\ + 875 LUT4 0007 cd/AB\ + 876 LUT3 B0 C/aB\ + 877 LUT4 0001 abcd + 878 LUT4 F400 ((aB)+C)D + 879 LUT4 3500 D(c?b:a) + 880 LUT3 70 C/AB\ + 881 LUT4 0777 /AB\(d+c) + 882 LUT3 70 C/AB\ + 883 LUT4 F3F5 DC?a:b:1:1 + 884 LUT3 F1 (ab)+C + 885 LUT3 70 C/AB\ + 886 LUT4 0D00 cD/Ab\ + 887 LUT4 F400 ((aB)+C)D + 888 LUT4 3500 D(c?b:a) + 889 LUT3 70 C/AB\ + 890 LUT4 0777 /AB\(d+c) + 891 LUT3 70 C/AB\ + 892 LUT4 F3F5 DC?a:b:1:1 + 893 LUT3 70 C/AB\ + 894 LUT4 F3F5 DC?a:b:1:1 + 895 LUT3 70 C/AB\ + 896 LUT4 F3F5 DC?a:b:1:1 + 897 LUT3 70 C/AB\ + 898 LUT4 F3F5 DC?a:b:1:1 + 899 LUT3 70 C/AB\ + 900 LUT4 F53F DC?1:a:b:1 + 901 LUT4 F3F5 DC?a:b:1:1 + 902 LUT4 F3F5 DC?a:b:1:1 + 903 LUT3 F1 (ab)+C + 904 LUT4 0D00 cD/Ab\ + 905 LUT4 F400 ((aB)+C)D + 906 LUT4 3500 D(c?b:a) + 907 LUT3 70 C/AB\ + 908 LUT4 0777 /AB\(d+c) + 909 LUT3 70 C/AB\ + 910 LUT4 F3F5 DC?a:b:1:1 + 911 LUT4 F3F5 DC?a:b:1:1 + 912 LUT4 F3F5 DC?a:b:1:1 + 913 LUT3 70 C/AB\ + 914 LUT4 F53F DC?1:a:b:1 + 915 LUT3 70 C/AB\ + 916 LUT4 F3F5 DC?a:b:1:1 + 917 LUT3 3A c?b:A + 918 LUT3 F8 (AB)+C + 919 LUT4 004F ((aB)+c)d + 920 LUT3 70 C/AB\ + 921 LUT4 000B cd/aB\ + 922 LUT4 00F4 ((aB)+C)d + 923 LUT4 8F00 ((AB)+c)D + 924 LUT4 F400 ((aB)+C)D + 925 LUT4 3500 D(c?b:a) + 926 LUT3 70 C/AB\ + 927 LUT4 0777 /AB\(d+c) + 928 LUT3 70 C/AB\ + 929 LUT4 F3F5 DC?a:b:1:1 + 930 LUT4 8000 ABCD + 931 LUT3 3A c?b:A + 932 LUT4 00F4 ((aB)+C)d + 933 LUT3 70 C/AB\ + 934 LUT4 0700 cD/AB\ + 935 LUT4 F400 ((aB)+C)D + 936 LUT4 3500 D(c?b:a) + 937 LUT3 70 C/AB\ + 938 LUT4 0777 /AB\(d+c) + 939 LUT3 70 C/AB\ + 940 LUT4 F3F5 DC?a:b:1:1 + 941 LUT3 F1 (ab)+C + 942 LUT4 000D cd/Ab\ + 943 LUT3 40 aBC + 944 LUT2 8 AB + 945 LUT4 F3F5 DC?a:b:1:1 + 946 LUT4 F53F DC?1:a:b:1 + 947 LUT3 70 C/AB\ + 948 LUT4 F53F DC?1:a:b:1 + 949 LUT3 70 C/AB\ + 950 LUT4 F3F5 DC?a:b:1:1 + 951 LUT3 D0 C/Ab\ + 952 LUT4 0007 cd/AB\ + 953 LUT4 CEC0 BD?0:C:Ac:1 + 954 LUT3 10 abC + 955 LUT2 8 AB + 956 LUT2 1 ab + 957 LUT2 8 AB + 958 LUT2 8 AB + 959 LUT2 4 aB + 960 LUT4 E000 CD/ab\ + 961 LUT2 8 AB + 962 LUT2 4 aB + 963 LUT2 E /ab\ + 964 LUT2 E /ab\ + 965 LUT2 4 aB + 966 LUT4 1000 abCD + 967 LUT2 E /ab\ + 968 LUT2 E /ab\ + 969 LUT4 0100 abcD + 970 LUT4 000E cd/ab\ + 971 LUT2 4 aB + 972 LUT3 10 abC + 973 LUT2 1 ab + 974 LUT4 F400 ((aB)+C)D + 975 LUT4 5300 D(C?b:a) + 976 LUT3 70 C/AB\ + 977 LUT4 0777 /AB\(d+c) + 978 LUT3 70 C/AB\ + 979 LUT4 F3F5 DC?a:b:1:1 + 980 LUT3 70 C/AB\ + 981 LUT4 F3F5 DC?a:b:1:1 + 982 LUT4 0305 DC?a:b:0:0 + 983 LUT3 70 C/AB\ + 984 LUT4 F3F5 DC?a:b:1:1 + 985 LUT4 7303 BD?c:0:1:aC + 986 LUT3 0B c/aB\ + 987 LUT4 3500 D(c?b:a) + 988 LUT3 70 C/AB\ + 989 LUT4 F53F DC?1:a:b:1 + 990 LUT3 70 C/AB\ + 991 LUT4 F3F5 DC?a:b:1:1 + 992 LUT3 70 C/AB\ + 993 LUT4 F3F5 DC?a:b:1:1 + 994 LUT4 0305 DC?a:b:0:0 + 995 LUT3 70 C/AB\ + 996 LUT4 F3F5 DC?a:b:1:1 + 997 LUT4 F0EE D?/ab\:C + 998 LUT4 B0BB /aB\(d+C) + 999 LUT4 8F00 ((AB)+c)D + 1000 LUT4 0700 cD/AB\ + 1001 LUT2 8 AB + 1002 LUT4 0700 cD/AB\ + 1003 LUT4 F3F5 DC?a:b:1:1 + 1004 LUT3 70 C/AB\ + 1005 LUT4 F53F DC?1:a:b:1 + 1006 LUT3 CA C?A:B + 1007 LUT3 70 C/AB\ + 1008 LUT4 F53F DC?1:a:b:1 + 1009 LUT4 F0EE D?/ab\:C + 1010 LUT3 0B c/aB\ + 1011 LUT4 3500 D(c?b:a) + 1012 LUT3 70 C/AB\ + 1013 LUT4 F53F DC?1:a:b:1 + 1014 LUT3 70 C/AB\ + 1015 LUT4 F3F5 DC?a:b:1:1 + 1016 LUT3 70 C/AB\ + 1017 LUT4 F3F5 DC?a:b:1:1 + 1018 LUT3 CA C?A:B + 1019 LUT3 70 C/AB\ + 1020 LUT4 F3F5 DC?a:b:1:1 + 1021 LUT2 1 ab + 1022 LUT2 4 aB + 1023 LUT2 8 AB + 1024 LUT3 0E c/ab\ + 1025 LUT4 3500 D(c?b:a) + 1026 LUT2 1 ab + 1027 LUT3 70 C/AB\ + 1028 LUT4 F3F5 DC?a:b:1:1 + 1029 LUT3 70 C/AB\ + 1030 LUT4 F3F5 DC?a:b:1:1 + 1031 LUT4 0B00 cD/aB\ + 1032 LUT4 3500 D(c?b:a) + 1033 LUT3 70 C/AB\ + 1034 LUT4 F53F DC?1:a:b:1 + 1035 LUT3 70 C/AB\ + 1036 LUT4 F53F DC?1:a:b:1 + 1037 LUT3 40 aBC + 1038 LUT2 8 AB + 1039 LUT2 8 AB + 1040 LUT2 8 AB + 1041 LUT2 8 AB + 1042 LUT2 4 aB + 1043 LUT2 8 AB + 1044 LUT4 6000 CD(A^B) + 1045 LUT4 1428 (B^C)(A^D) + 1046 LUT4 1428 (B^C)(A^D) + 1047 LUT2 8 AB + 1048 LUT4 4000 aBCD + 1049 LUT3 60 C(A^B) + 1050 LUT4 1428 (B^C)(A^D) + 1051 LUT4 1428 (B^C)(A^D) + 1052 LUT3 E0 C/ab\ + 1053 LUT2 1 ab + 1054 LUT4 0100 abcD + 1055 LUT4 6000 CD(A^B) + 1056 LUT3 60 C(A^B) + 1057 LUT4 1428 (B^C)(A^D) + 1058 LUT3 70 C/AB\ + 1059 LUT4 0007 cd/AB\ + 1060 LUT2 8 AB + 1061 LUT3 90 C(a^B) + 1062 LUT3 90 C(a^B) + 1063 LUT2 E /ab\ + 1064 LUT4 0700 cD/AB\ + 1065 LUT4 0700 cD/AB\ + 1066 LUT2 E /ab\ + 1067 LUT4 0700 cD/AB\ + 1068 LUT2 8 AB + 1069 LUT3 90 C(a^B) + 1070 LUT3 90 C(a^B) + 1071 LUT3 90 C(a^B) + 1072 LUT3 90 C(a^B) + 1073 LUT3 90 C(a^B) + 1074 LUT3 90 C(a^B) + 1075 LUT4 0700 cD/AB\ + 1076 LUT4 0777 /AB\(d+c) + 1077 LUT2 8 AB + 1078 LUT2 8 AB + 1079 LUT4 0777 /AB\(d+c) + 1080 LUT4 0777 /AB\(d+c) + 1081 LUT3 60 C(A^B) + 1082 LUT2 8 AB + 1083 LUT4 0777 /AB\(d+c) + 1084 LUT4 0777 /AB\(d+c) + 1085 LUT3 10 abC + 1086 LUT2 8 AB + 1087 LUT4 0777 /AB\(d+c) + 1088 LUT4 0777 /AB\(d+c) + 1089 LUT4 0001 abcd + 1090 LUT4 0B00 cD/aB\ + 1091 LUT4 B0BB /aB\(d+C) + 1092 LUT2 9 a^B + 1093 LUT4 8000 ABCD + 1094 LUT4 7000 CD/AB\ + 1095 LUT4 0700 cD/AB\ + 1096 LUT2 8 AB + 1097 LUT2 8 AB + 1098 LUT2 4 aB + 1099 LUT2 4 aB + 1100 LUT4 0777 /AB\(d+c) + 1101 LUT3 80 ABC + 1102 LUT2 1 ab + 1103 LUT2 1 ab + 1104 LUT3 40 aBC + 1105 LUT2 8 AB + 1106 LUT3 80 ABC + 1107 LUT4 0777 /AB\(d+c) + 1108 LUT2 8 AB + 1109 LUT2 4 aB + 1110 LUT2 4 aB + 1111 LUT3 40 aBC + 1112 LUT2 8 AB + 1113 LUT3 80 ABC + 1114 LUT2 4 aB + 1115 LUT4 0700 cD/AB\ + 1116 LUT2 8 AB + 1117 LUT2 4 aB + 1118 LUT2 8 AB + 1119 LUT4 0777 /AB\(d+c) + 1120 LUT2 8 AB + 1121 LUT3 40 aBC + 1122 LUT2 8 AB + 1123 LUT4 0777 /AB\(d+c) + 1124 LUT2 8 AB + 1125 LUT2 8 AB + 1126 LUT4 0777 /AB\(d+c) + 1127 LUT2 8 AB + 1128 LUT3 80 ABC + 1129 LUT2 4 aB + 1130 LUT4 8000 ABCD + 1131 LUT4 0777 /AB\(d+c) + 1132 LUT2 8 AB + 1133 LUT2 8 AB + 1134 LUT3 40 aBC + 1135 LUT4 0777 /AB\(d+c) + 1136 LUT2 8 AB + 1137 LUT3 40 aBC + 1138 LUT4 0777 /AB\(d+c) + 1139 LUT2 8 AB + 1140 LUT3 40 aBC + 1141 LUT4 0777 /AB\(d+c) + 1142 LUT3 40 aBC + 1143 LUT3 40 aBC + 1144 LUT4 8000 ABCD + 1145 LUT4 0777 /AB\(d+c) + 1146 LUT2 8 AB + 1147 LUT3 40 aBC + 1148 LUT4 0777 /AB\(d+c) + 1149 LUT2 8 AB + 1150 LUT3 40 aBC + 1151 LUT4 0777 /AB\(d+c) + 1152 LUT2 8 AB + 1153 LUT3 80 ABC + 1154 LUT4 0777 /AB\(d+c) + 1155 LUT3 80 ABC + 1156 LUT3 40 aBC + 1157 LUT3 70 C/AB\ + 1158 LUT4 0BBB /aB\(d+c) + 1159 LUT4 440F D?c:aB + 1160 LUT4 F3F5 DC?a:b:1:1 + 1161 LUT3 07 c/AB\ + 1162 LUT3 CA C?A:B + 1163 LUT3 CA C?A:B + 1164 LUT2 8 AB + 1165 LUT4 0777 /AB\(d+c) + 1166 LUT3 70 C/AB\ + 1167 LUT4 0777 /AB\(d+c) + 1168 LUT2 8 AB + 1169 LUT4 0777 /AB\(d+c) + 1170 LUT4 0777 /AB\(d+c) + 1171 LUT4 F088 D?AB:C + 1172 LUT2 8 AB + 1173 LUT4 0777 /AB\(d+c) + 1174 LUT4 0777 /AB\(d+c) + 1175 LUT4 0777 /AB\(d+c) + 1176 LUT4 0777 /AB\(d+c) + 1177 LUT4 EF00 ((/ab\)+c)D + 1178 LUT4 3500 D(c?b:a) + 1179 LUT4 F088 D?AB:C + 1180 LUT4 0777 /AB\(d+c) + 1181 LUT3 40 aBC + 1182 LUT3 40 aBC + 1183 LUT3 80 ABC + 1184 LUT2 8 AB + 1185 LUT3 90 C(a^B) + 1186 LUT4 B00B /aB\/D^C\ + 1187 LUT4 9009 (a^B)(D^c) + 1188 LUT4 9009 (a^B)(D^c) + 1189 LUT4 B00B /aB\/D^C\ + 1190 LUT4 B0BB /aB\(d+C) + 1191 LUT3 90 C(a^B) + 1192 LUT3 90 C(a^B) + 1193 LUT4 9009 (a^B)(D^c) + 1194 LUT4 B00B /aB\/D^C\ + 1195 LUT4 9009 (a^B)(D^c) + 1196 LUT4 9009 (a^B)(D^c) + 1197 LUT4 9000 CD(a^B) + 1198 LUT3 90 C(a^B) + 1199 LUT4 B00B /aB\/D^C\ + 1200 LUT4 9009 (a^B)(D^c) + 1201 LUT2 8 AB + 1202 LUT4 8000 ABCD + 1203 LUT4 8000 ABCD + 1204 LUT4 8000 ABCD + 1205 LUT4 1000 abCD + 1206 LUT4 0B00 cD/aB\ + 1207 LUT2 4 aB + 1208 LUT4 B0BB /aB\(d+C) + 1209 LUT2 4 aB + 1210 LUT2 4 aB + 1211 LUT3 B0 C/aB\ + 1212 LUT2 4 aB + 1213 LUT4 B0BB /aB\(d+C) + 1214 LUT4 B0BB /aB\(d+C) + 1215 LUT4 1000 abCD + 1216 LUT4 1001 ab(c^D) + 1217 LUT2 4 aB + 1218 LUT2 4 aB + 1219 LUT4 B0BB /aB\(d+C) + 1220 LUT2 4 aB + 1221 LUT2 4 aB + 1222 LUT4 0D00 cD/Ab\ + 1223 LUT2 9 a^B + 1224 LUT2 4 aB + 1225 LUT4 B00B /aB\/D^C\ + 1226 LUT4 9000 CD(a^B) + 1227 LUT4 0D00 cD/Ab\ + 1228 LUT2 4 aB + 1229 LUT4 B0BB /aB\(d+C) + 1230 LUT4 B0BB /aB\(d+C) + 1231 LUT3 90 C(a^B) + 1232 LUT3 41 (B^c)a + 1233 LUT2 6 A^B + 1234 LUT2 4 aB + 1235 LUT2 4 aB + 1236 LUT4 8000 ABCD + 1237 LUT2 9 a^B + 1238 LUT4 B0BB /aB\(d+C) + 1239 LUT2 9 a^B + 1240 LUT4 B0BB /aB\(d+C) + 1241 LUT4 FFE0 (C/ab\)+D + 1242 LUT2 8 AB + 1243 LUT2 8 AB + 1244 LUT2 8 AB + 1245 LUT2 8 AB + 1246 LUT4 8000 ABCD + 1247 LUT2 4 aB + 1248 LUT2 4 aB + 1249 LUT2 4 aB + 1250 LUT4 0100 abcD + 1251 LUT4 1000 abCD + 1252 LUT4 1001 ab(c^D) + 1253 LUT2 4 aB + 1254 LUT2 4 aB + 1255 LUT2 4 aB + 1256 LUT2 4 aB + 1257 LUT4 B0BB /aB\(d+C) + 1258 LUT2 6 A^B + 1259 LUT2 6 A^B + 1260 LUT2 6 A^B + 1261 LUT2 4 aB + 1262 LUT2 9 a^B + 1263 LUT4 0B00 cD/aB\ + 1264 LUT2 4 aB + 1265 LUT4 B0BB /aB\(d+C) + 1266 LUT4 B0BB /aB\(d+C) + 1267 LUT4 B0BB /aB\(d+C) + 1268 LUT2 4 aB + 1269 LUT4 0B00 cD/aB\ + 1270 LUT2 4 aB + 1271 LUT2 9 a^B + 1272 LUT4 B0BB /aB\(d+C) + 1273 LUT4 D000 CD/Ab\ + 1274 LUT4 B0BB /aB\(d+C) + 1275 LUT2 8 AB + 1276 LUT2 4 aB + 1277 LUT3 10 abC + 1278 LUT4 4000 aBCD + 1279 LUT2 4 aB + 1280 LUT2 4 aB + 1281 LUT4 0777 /AB\(d+c) + 1282 LUT3 80 ABC + 1283 LUT2 4 aB + 1284 LUT2 4 aB + 1285 LUT2 8 AB + 1286 LUT2 4 aB + 1287 LUT2 4 aB + 1288 LUT2 4 aB + 1289 LUT4 8000 ABCD + 1290 LUT2 4 aB + 1291 LUT2 4 aB + 1292 LUT4 1000 abCD + 1293 LUT4 1001 ab(c^D) + 1294 LUT2 4 aB + 1295 LUT2 4 aB + 1296 LUT2 4 aB + 1297 LUT2 4 aB + 1298 LUT2 4 aB + 1299 LUT2 4 aB + 1300 LUT4 8000 ABCD + 1301 LUT3 90 C(a^B) + 1302 LUT3 41 (B^c)a + 1303 LUT2 6 A^B + 1304 LUT4 4100 D(B^c)a + 1305 LUT3 90 C(a^B) + 1306 LUT4 B0BB /aB\(d+C) + 1307 LUT2 6 A^B + 1308 LUT4 8000 ABCD + 1309 LUT4 B0BB /aB\(d+C) + 1310 LUT4 B0BB /aB\(d+C) + 1311 LUT4 B0BB /aB\(d+C) + 1312 LUT4 B0BB /aB\(d+C) + 1313 LUT4 8000 ABCD + 1314 LUT4 B0BB /aB\(d+C) + 1315 LUT4 B0BB /aB\(d+C) + 1316 LUT4 B0BB /aB\(d+C) + 1317 LUT4 B0BB /aB\(d+C) + 1318 LUT2 8 AB + 1319 LUT2 4 aB + 1320 LUT3 10 abC + 1321 LUT4 4000 aBCD + 1322 LUT3 10 abC + 1323 LUT2 1 ab + 1324 LUT3 10 abC + 1325 LUT4 4000 aBCD + 1326 LUT3 10 abC + 1327 LUT2 8 AB + 1328 LUT4 0007 cd/AB\ + 1329 LUT4 4000 aBCD + 1330 LUT2 8 AB + 1331 LUT2 4 aB + 1332 LUT3 10 abC + 1333 LUT4 0777 /AB\(d+c) + 1334 LUT2 1 ab + 1335 LUT3 10 abC + 1336 LUT4 4000 aBCD + 1337 LUT3 10 abC + 1338 LUT2 1 ab + 1339 LUT3 10 abC + 1340 LUT4 7F00 ((/AB\)+c)D + 1341 LUT4 1000 abCD + 1342 LUT3 80 ABC + 1343 LUT2 1 ab + 1344 LUT3 10 abC + 1345 LUT2 8 AB + 1346 LUT2 4 aB + 1347 LUT3 10 abC + 1348 LUT4 0700 cD/AB\ + 1349 LUT2 1 ab + 1350 LUT3 10 abC + 1351 LUT4 1000 abCD + 1352 LUT3 80 ABC + 1353 LUT2 1 ab + 1354 LUT3 10 abC + 1355 LUT2 8 AB + 1356 LUT2 4 aB + 1357 LUT3 10 abC + 1358 LUT4 0700 cD/AB\ + 1359 LUT2 4 aB + 1360 LUT3 10 abC + 1361 LUT2 8 AB + 1362 LUT4 3A00 D(c?b:A) + 1363 LUT4 4000 aBCD + 1364 LUT2 8 AB + 1365 LUT2 8 AB + 1366 LUT3 35 c?b:a + 1367 LUT2 8 AB + 1368 LUT2 8 AB + 1369 LUT3 CA C?A:B + 1370 LUT3 35 c?b:a + 1371 LUT4 5300 D(C?b:a) + 1372 LUT3 40 aBC + 1373 LUT3 35 c?b:a + 1374 LUT3 35 c?b:a + 1375 LUT4 5300 D(C?b:a) + 1376 LUT3 40 aBC + 1377 LUT3 35 c?b:a + 1378 LUT3 35 c?b:a + 1379 LUT3 53 C?b:a + 1380 LUT4 5300 D(C?b:a) + 1381 LUT3 80 ABC + 1382 LUT3 35 c?b:a + 1383 LUT4 5300 D(C?b:a) + 1384 LUT3 35 c?b:a + 1385 LUT4 8F00 ((AB)+c)D + 1386 LUT4 0777 /AB\(d+c) + 1387 LUT2 8 AB + 1388 LUT4 0700 cD/AB\ + 1389 LUT4 8000 ABCD + 1390 LUT2 8 AB + 1391 LUT4 440F D?c:aB + 1392 LUT2 E /ab\ + 1393 LUT2 E /ab\ + 1394 LUT4 007F ((/AB\)+c)d + 1395 LUT3 80 ABC + 1396 LUT4 8000 ABCD + 1397 LUT2 8 AB + 1398 LUT4 0777 /AB\(d+c) + 1399 LUT4 8000 ABCD + 1400 LUT2 8 AB + 1401 LUT4 8000 ABCD + 1402 LUT2 8 AB + 1403 LUT4 0007 cd/AB\ + 1404 LUT4 7000 CD/AB\ + 1405 LUT2 4 aB + 1406 LUT4 0777 /AB\(d+c) + 1407 LUT3 80 ABC + 1408 LUT4 0700 cD/AB\ + 1409 LUT4 0777 /AB\(d+c) + 1410 LUT3 80 ABC + 1411 LUT4 0700 cD/AB\ + 1412 LUT4 0777 /AB\(d+c) + 1413 LUT2 1 ab + 1414 LUT3 80 ABC + 1415 LUT4 8000 ABCD + 1416 LUT4 8000 ABCD + 1417 LUT2 9 a^B + 1418 LUT4 CA00 D(C?A:B) + 1419 LUT2 9 a^B + 1420 LUT4 CA00 D(C?A:B) + 1421 LUT4 B0BB /aB\(d+C) + 1422 LUT4 CA00 D(C?A:B) + 1423 LUT4 CA00 D(C?A:B) + 1424 LUT4 B0BB /aB\(d+C) + 1425 LUT4 CA00 D(C?A:B) + 1426 LUT4 0D00 cD/Ab\ + 1427 LUT4 B0BB /aB\(d+C) + 1428 LUT4 CA00 D(C?A:B) + 1429 LUT4 CA00 D(C?A:B) + 1430 LUT2 4 aB + 1431 LUT4 CA00 D(C?A:B) + 1432 LUT4 CA00 D(C?A:B) + 1433 LUT4 B0BB /aB\(d+C) + 1434 LUT4 CA00 D(C?A:B) + 1435 LUT4 CA00 D(C?A:B) + 1436 LUT4 B0BB /aB\(d+C) + 1437 LUT4 CA00 D(C?A:B) + 1438 LUT4 4100 D(B^c)a + 1439 LUT2 6 A^B + 1440 LUT4 CA00 D(C?A:B) + 1441 LUT4 9009 (a^B)(D^c) + 1442 LUT4 CA00 D(C?A:B) + 1443 LUT4 CA00 D(C?A:B) + 1444 LUT4 CA00 D(C?A:B) + 1445 LUT2 4 aB + 1446 LUT4 B0BB /aB\(d+C) + 1447 LUT4 CA00 D(C?A:B) + 1448 LUT4 4100 D(B^c)a + 1449 LUT3 90 C(a^B) + 1450 LUT2 4 aB + 1451 LUT4 CA00 D(C?A:B) + 1452 LUT4 CA00 D(C?A:B) + 1453 LUT2 4 aB + 1454 LUT4 CA00 D(C?A:B) + 1455 LUT4 B0BB /aB\(d+C) + 1456 LUT4 CA00 D(C?A:B) + 1457 LUT4 CA00 D(C?A:B) + 1458 LUT4 CA00 D(C?A:B) + 1459 LUT2 9 a^B + 1460 LUT4 CA00 D(C?A:B) + 1461 LUT4 B0BB /aB\(d+C) + 1462 LUT4 CA00 D(C?A:B) + 1463 LUT4 CA00 D(C?A:B) + 1464 LUT4 0D00 cD/Ab\ + 1465 LUT4 B0BB /aB\(d+C) + 1466 LUT2 4 aB + 1467 LUT4 CA00 D(C?A:B) + 1468 LUT4 CA00 D(C?A:B) + 1469 LUT2 4 aB + 1470 LUT4 CA00 D(C?A:B) + 1471 LUT4 B0BB /aB\(d+C) + 1472 LUT4 B0BB /aB\(d+C) + 1473 LUT2 8 AB + 1474 LUT2 8 AB + 1475 LUT3 40 aBC + 1476 LUT4 BB0F D?c:/aB\ + 1477 LUT3 CA C?A:B + 1478 LUT4 0777 /AB\(d+c) + 1479 LUT3 C5 C?a:B + 1480 LUT2 4 aB + 1481 LUT3 35 c?b:a + 1482 LUT2 8 AB + 1483 LUT2 8 AB + 1484 LUT4 0D00 cD/Ab\ + 1485 LUT4 8F00 ((AB)+c)D + 1486 LUT4 0777 /AB\(d+c) + 1487 LUT2 8 AB + 1488 LUT4 0700 cD/AB\ + 1489 LUT4 8000 ABCD + 1490 LUT2 8 AB + 1491 LUT3 0E c/ab\ + 1492 LUT3 80 ABC + 1493 LUT4 8000 ABCD + 1494 LUT4 0777 /AB\(d+c) + 1495 LUT4 8000 ABCD + 1496 LUT2 8 AB + 1497 LUT4 8000 ABCD + 1498 LUT2 8 AB + 1499 LUT2 8 AB + 1500 LUT4 0007 cd/AB\ + 1501 LUT4 7000 CD/AB\ + 1502 LUT2 4 aB + 1503 LUT4 0777 /AB\(d+c) + 1504 LUT3 80 ABC + 1505 LUT4 0700 cD/AB\ + 1506 LUT4 0777 /AB\(d+c) + 1507 LUT3 80 ABC + 1508 LUT4 0700 cD/AB\ + 1509 LUT4 0777 /AB\(d+c) + 1510 LUT2 1 ab + 1511 LUT3 80 ABC + 1512 LUT3 80 ABC + 1513 LUT2 1 ab + 1514 LUT4 B0BB /aB\(d+C) + 1515 LUT4 BF00 ((/aB\)+c)D + 1516 LUT4 0777 /AB\(d+c) + 1517 LUT4 7000 CD/AB\ + 1518 LUT4 4000 aBCD + 1519 LUT3 80 ABC + 1520 LUT3 80 ABC + 1521 LUT3 10 abC + 1522 LUT4 0777 /AB\(d+c) + 1523 LUT4 8000 ABCD + 1524 LUT4 8000 ABCD + 1525 LUT2 8 AB + 1526 LUT4 8000 ABCD + 1527 LUT2 8 AB + 1528 LUT2 8 AB + 1529 LUT2 8 AB + 1530 LUT4 0700 cD/AB\ + 1531 LUT4 0700 cD/AB\ + 1532 LUT4 8000 ABCD + 1533 LUT4 0777 /AB\(d+c) + 1534 LUT4 0700 cD/AB\ + 1535 LUT4 0700 cD/AB\ + 1536 LUT4 8000 ABCD + 1537 LUT4 0700 cD/AB\ + 1538 LUT4 0700 cD/AB\ + 1539 LUT4 8000 ABCD + 1540 LUT2 1 ab + 1541 LUT3 40 aBC + 1542 LUT4 533F DC?1:b:b:a + 1543 LUT4 8000 ABCD + 1544 LUT2 1 ab + 1545 LUT4 0777 /AB\(d+c) + 1546 LUT2 4 aB + 1547 LUT3 5C c?a:B + 1548 LUT2 4 aB + 1549 LUT3 4F (aB)+c + 1550 LUT3 3A c?b:A + 1551 LUT3 CA C?A:B + 1552 LUT4 E000 CD/ab\ + 1553 LUT2 4 aB + 1554 LUT2 4 aB + 1555 LUT2 4 aB + 1556 LUT2 4 aB + 1557 LUT2 4 aB + 1558 LUT2 4 aB + 1559 LUT3 8F (AB)+c + 1560 LUT3 80 ABC + 1561 LUT2 6 A^B + 1562 LUT2 9 a^B + 1563 LUT3 35 c?b:a + 1564 LUT2 8 AB + 1565 LUT4 001F ((ab)+c)d + 1566 LUT4 0007 cd/AB\ + 1567 LUT3 80 ABC + 1568 LUT3 0D c/Ab\ + 1569 LUT3 35 c?b:a + 1570 LUT3 40 aBC + 1571 LUT3 80 ABC + 1572 LUT4 CA00 D(C?A:B) + 1573 LUT4 0100 abcD + 1574 LUT2 8 AB + 1575 LUT4 F044 D?aB:C + 1576 LUT4 8000 ABCD + 1577 LUT2 4 aB + 1578 LUT4 0001 abcd + 1579 LUT2 8 AB + 1580 LUT4 0100 abcD + 1581 LUT2 8 AB + 1582 LUT2 1 ab + 1583 LUT2 1 ab + 1584 LUT3 07 c/AB\ + 1585 LUT2 1 ab + 1586 LUT2 4 aB + 1587 LUT3 07 c/AB\ + 1588 LUT2 4 aB + 1589 LUT2 4 aB + 1590 LUT3 8F (AB)+c + 1591 LUT4 0700 cD/AB\ + 1592 LUT3 70 C/AB\ + 1593 LUT3 D0 C/Ab\ + 1594 LUT4 0001 abcd + 1595 LUT4 E000 CD/ab\ + 1596 LUT4 007F ((/AB\)+c)d + 1597 LUT4 B0BB /aB\(d+C) + 1598 LUT4 AC00 D(c?A:B) + 1599 LUT2 8 AB + 1600 LUT2 4 aB + 1601 LUT2 8 AB + 1602 LUT2 8 AB + 1603 LUT3 80 ABC + 1604 LUT3 90 C(a^B) + 1605 LUT4 9009 (a^B)(D^c) + 1606 LUT4 9009 (a^B)(D^c) + 1607 LUT4 1000 abCD + 1608 LUT3 80 ABC + 1609 LUT3 90 C(a^B) + 1610 LUT4 9009 (a^B)(D^c) + 1611 LUT4 9009 (a^B)(D^c) + 1612 LUT4 4000 aBCD + 1613 LUT3 80 ABC + 1614 LUT4 0770 (C^D)/AB\ + 1615 LUT3 40 aBC + 1616 LUT4 00BF ((/aB\)+c)d + 1617 LUT2 4 aB + 1618 LUT4 1000 abCD + 1619 LUT4 8000 ABCD + 1620 LUT4 7000 CD/AB\ + 1621 LUT4 0700 cD/AB\ + 1622 LUT4 0777 /AB\(d+c) + 1623 LUT2 8 AB + 1624 LUT2 4 aB + 1625 LUT2 8 AB + 1626 LUT3 40 aBC + 1627 LUT2 4 aB + 1628 LUT2 8 AB + 1629 LUT3 40 aBC + 1630 LUT3 80 ABC + 1631 LUT4 0777 /AB\(d+c) + 1632 LUT2 8 AB + 1633 LUT2 8 AB + 1634 LUT3 40 aBC + 1635 LUT2 8 AB + 1636 LUT4 8000 ABCD + 1637 LUT4 0777 /AB\(d+c) + 1638 LUT3 40 aBC + 1639 LUT4 0777 /AB\(d+c) + 1640 LUT2 8 AB + 1641 LUT2 8 AB + 1642 LUT2 4 aB + 1643 LUT4 0777 /AB\(d+c) + 1644 LUT3 40 aBC + 1645 LUT3 40 aBC + 1646 LUT4 0777 /AB\(d+c) + 1647 LUT2 4 aB + 1648 LUT2 8 AB + 1649 LUT4 8000 ABCD + 1650 LUT4 0777 /AB\(d+c) + 1651 LUT2 8 AB + 1652 LUT3 80 ABC + 1653 LUT4 0777 /AB\(d+c) + 1654 LUT2 8 AB + 1655 LUT2 8 AB + 1656 LUT4 0777 /AB\(d+c) + 1657 LUT2 8 AB + 1658 LUT4 4000 aBCD + 1659 LUT4 0777 /AB\(d+c) + 1660 LUT3 80 ABC + 1661 LUT2 8 AB + 1662 LUT4 8000 ABCD + 1663 LUT4 0777 /AB\(d+c) + 1664 LUT4 4000 aBCD + 1665 LUT3 40 aBC + 1666 LUT4 0777 /AB\(d+c) + 1667 LUT3 80 ABC + 1668 LUT2 8 AB + 1669 LUT4 0777 /AB\(d+c) + 1670 LUT2 8 AB + 1671 LUT3 80 ABC + 1672 LUT4 0777 /AB\(d+c) + 1673 LUT4 1000 abCD + 1674 LUT3 40 aBC + 1675 LUT3 40 aBC + 1676 LUT4 4300 D(BC?1:0:0:a) + 1677 LUT3 CA C?A:B + 1678 LUT3 8F (AB)+c + 1679 LUT4 F53F DC?1:a:b:1 + 1680 LUT2 6 A^B + 1681 LUT4 E000 CD/ab\ + 1682 LUT4 7077 /AB\(d+C) + 1683 LUT2 8 AB + 1684 LUT2 8 AB + 1685 LUT2 8 AB + 1686 LUT2 8 AB + 1687 LUT2 4 aB + 1688 LUT3 0B c/aB\ + 1689 LUT3 80 ABC + 1690 LUT4 8000 ABCD + 1691 LUT4 8000 ABCD + 1692 LUT4 0777 /AB\(d+c) + 1693 LUT4 0777 /AB\(d+c) + 1694 LUT4 0777 /AB\(d+c) + 1695 LUT4 0777 /AB\(d+c) + 1696 LUT4 0777 /AB\(d+c) + 1697 LUT4 0777 /AB\(d+c) + 1698 LUT3 70 C/AB\ + 1699 LUT4 0777 /AB\(d+c) + 1700 LUT4 8000 ABCD + 1701 LUT4 0777 /AB\(d+c) + 1702 LUT4 0777 /AB\(d+c) + 1703 LUT4 0777 /AB\(d+c) + 1704 LUT4 0777 /AB\(d+c) + 1705 LUT4 8000 ABCD + 1706 LUT4 0777 /AB\(d+c) + 1707 LUT4 0777 /AB\(d+c) + 1708 LUT4 0777 /AB\(d+c) + 1709 LUT4 0777 /AB\(d+c) + 1710 LUT3 70 C/AB\ + 1711 LUT3 70 C/AB\ + 1712 LUT4 0BBB /aB\(d+c) + 1713 LUT4 440F D?c:aB + 1714 LUT4 F3F5 DC?a:b:1:1 + 1715 LUT3 07 c/AB\ + 1716 LUT3 CA C?A:B + 1717 LUT3 CA C?A:B + 1718 LUT2 8 AB + 1719 LUT4 0777 /AB\(d+c) + 1720 LUT4 0777 /AB\(d+c) + 1721 LUT2 8 AB + 1722 LUT4 0777 /AB\(d+c) + 1723 LUT4 0777 /AB\(d+c) + 1724 LUT4 F088 D?AB:C + 1725 LUT2 8 AB + 1726 LUT4 0777 /AB\(d+c) + 1727 LUT4 0777 /AB\(d+c) + 1728 LUT4 0777 /AB\(d+c) + 1729 LUT4 0777 /AB\(d+c) + 1730 LUT4 EF00 ((/ab\)+c)D + 1731 LUT4 3500 D(c?b:a) + 1732 LUT4 F088 D?AB:C + 1733 LUT4 0777 /AB\(d+c) + 1734 LUT4 0007 cd/AB\ + 1735 LUT4 1000 abCD + 1736 LUT4 1000 abCD + 1737 LUT3 CA C?A:B + 1738 LUT3 35 c?b:a + 1739 LUT4 5300 D(C?b:a) + 1740 LUT3 35 c?b:a + 1741 LUT3 35 c?b:a + 1742 LUT4 5300 D(C?b:a) + 1743 LUT3 35 c?b:a + 1744 LUT3 35 c?b:a + 1745 LUT3 53 C?b:a + 1746 LUT4 5300 D(C?b:a) + 1747 LUT3 35 c?b:a + 1748 LUT4 5300 D(C?b:a) + 1749 LUT3 35 c?b:a + 1750 LUT4 8F00 ((AB)+c)D + 1751 LUT4 0777 /AB\(d+c) + 1752 LUT2 8 AB + 1753 LUT4 0007 cd/AB\ + 1754 LUT3 80 ABC + 1755 LUT3 80 ABC + 1756 LUT4 0777 /AB\(d+c) + 1757 LUT4 440F D?c:aB + 1758 LUT3 35 c?b:a + 1759 LUT2 8 AB + 1760 LUT2 8 AB + 1761 LUT4 0D00 cD/Ab\ + 1762 LUT4 8F00 ((AB)+c)D + 1763 LUT4 0777 /AB\(d+c) + 1764 LUT4 0007 cd/AB\ + 1765 LUT2 8 AB + 1766 LUT3 80 ABC + 1767 LUT3 80 ABC + 1768 LUT4 B0BB /aB\(d+C) + 1769 LUT4 BF00 ((/aB\)+c)D + 1770 LUT4 0777 /AB\(d+c) + 1771 LUT2 8 AB + 1772 LUT4 0777 /AB\(d+c) + 1773 LUT4 0777 /AB\(d+c) + 1774 LUT3 5C c?a:B + 1775 LUT2 4 aB + 1776 LUT3 4F (aB)+c + 1777 LUT3 3A c?b:A + 1778 LUT3 CA C?A:B + 1779 LUT3 80 ABC + 1780 LUT3 35 c?b:a + 1781 LUT3 80 ABC + 1782 LUT3 0D c/Ab\ + 1783 LUT3 35 c?b:a + 1784 LUT3 80 ABC + 1785 LUT4 CA00 D(C?A:B) + 1786 LUT2 8 AB + 1787 LUT4 F044 D?aB:C + 1788 LUT4 7007 (c^D)/AB\ + 1789 LUT3 07 c/AB\ + 1790 LUT4 FF40 (aBC)+D + 1791 LUT2 8 AB + 1792 LUT2 4 aB + 1793 LUT2 8 AB + 1794 LUT2 8 AB + 1795 LUT3 8F (AB)+c + 1796 LUT4 0700 cD/AB\ + 1797 LUT3 70 C/AB\ + 1798 LUT4 00BF ((/aB\)+c)d + 1799 LUT2 4 aB + 1800 LUT4 1000 abCD + 1801 LUT4 8000 ABCD + 1802 LUT4 7000 CD/AB\ + 1803 LUT4 0700 cD/AB\ + 1804 LUT4 0777 /AB\(d+c) + 1805 LUT2 8 AB + 1806 LUT4 0777 /AB\(d+c) + 1807 LUT4 8000 ABCD + 1808 LUT4 0777 /AB\(d+c) + 1809 LUT4 0777 /AB\(d+c) + 1810 LUT4 0777 /AB\(d+c) + 1811 LUT4 0777 /AB\(d+c) + 1812 LUT4 8000 ABCD + 1813 LUT4 0777 /AB\(d+c) + 1814 LUT4 0777 /AB\(d+c) + 1815 LUT4 0777 /AB\(d+c) + 1816 LUT4 0777 /AB\(d+c) + 1817 LUT4 8000 ABCD + 1818 LUT4 0777 /AB\(d+c) + 1819 LUT4 0777 /AB\(d+c) + 1820 LUT4 0777 /AB\(d+c) + 1821 LUT4 0777 /AB\(d+c) + 1822 LUT3 CA C?A:B + 1823 LUT3 8F (AB)+c + 1824 LUT4 F3F5 DC?a:b:1:1 + 1825 LUT2 9 a^B + 1826 LUT2 4 aB + 1827 LUT3 D0 C/Ab\ + 1828 LUT3 B0 C/aB\ + 1829 LUT4 0BBB /aB\(d+c) + 1830 LUT4 440F D?c:aB + 1831 LUT4 F3F5 DC?a:b:1:1 + 1832 LUT3 0D c/Ab\ + 1833 LUT4 0001 abcd + 1834 LUT3 CA C?A:B + 1835 LUT3 AC c?A:B + 1836 LUT2 8 AB + 1837 LUT4 0777 /AB\(d+c) + 1838 LUT4 0777 /AB\(d+c) + 1839 LUT2 8 AB + 1840 LUT4 0777 /AB\(d+c) + 1841 LUT4 0777 /AB\(d+c) + 1842 LUT4 F088 D?AB:C + 1843 LUT2 8 AB + 1844 LUT4 0777 /AB\(d+c) + 1845 LUT4 0777 /AB\(d+c) + 1846 LUT4 0777 /AB\(d+c) + 1847 LUT4 0777 /AB\(d+c) + 1848 LUT3 AC c?A:B + 1849 LUT3 CA C?A:B + 1850 LUT3 AC c?A:B + 1851 LUT2 8 AB + 1852 LUT4 0777 /AB\(d+c) + 1853 LUT3 80 ABC + 1854 LUT4 4000 aBCD + 1855 LUT4 0777 /AB\(d+c) + 1856 LUT4 4000 aBCD + 1857 LUT4 4000 aBCD + 1858 LUT2 6 A^B + 1859 LUT2 1 ab + 1860 LUT4 EF00 ((/ab\)+c)D + 1861 LUT4 A300 D(C?b:A) + 1862 LUT4 8F00 ((AB)+c)D + 1863 LUT3 07 c/AB\ + 1864 LUT3 80 ABC + 1865 LUT4 0007 cd/AB\ + 1866 LUT3 80 ABC + 1867 LUT3 80 ABC + 1868 LUT4 0777 /AB\(d+c) + 1869 LUT3 C5 C?a:B + 1870 LUT2 4 aB + 1871 LUT4 3A00 D(c?b:A) + 1872 LUT3 35 c?b:a + 1873 LUT3 CA C?A:B + 1874 LUT3 35 c?b:a + 1875 LUT4 3500 D(c?b:a) + 1876 LUT3 35 c?b:a + 1877 LUT3 35 c?b:a + 1878 LUT4 3500 D(c?b:a) + 1879 LUT3 35 c?b:a + 1880 LUT2 8 AB + 1881 LUT2 8 AB + 1882 LUT4 3500 D(c?b:a) + 1883 LUT3 35 c?b:a + 1884 LUT4 00BF ((/aB\)+c)d + 1885 LUT4 0007 cd/AB\ + 1886 LUT3 80 ABC + 1887 LUT2 8 AB + 1888 LUT3 10 abC + 1889 LUT4 0777 /AB\(d+c) + 1890 LUT3 10 abC + 1891 LUT2 8 AB + 1892 LUT3 CA C?A:B + 1893 LUT3 35 c?b:a + 1894 LUT3 53 C?b:a + 1895 LUT4 0D00 cD/Ab\ + 1896 LUT4 8F00 ((AB)+c)D + 1897 LUT3 07 c/AB\ + 1898 LUT2 8 AB + 1899 LUT3 80 ABC + 1900 LUT4 0007 cd/AB\ + 1901 LUT3 80 ABC + 1902 LUT3 80 ABC + 1903 LUT4 B0BB /aB\(d+C) + 1904 LUT4 BF00 ((/aB\)+c)D + 1905 LUT4 0777 /AB\(d+c) + 1906 LUT2 8 AB + 1907 LUT4 0777 /AB\(d+c) + 1908 LUT4 0777 /AB\(d+c) + 1909 LUT2 4 aB + 1910 LUT3 5C c?a:B + 1911 LUT2 1 ab + 1912 LUT1 1 a deleted + 1913 LUT3 5C c?a:B + 1914 LUT3 35 c?b:a + 1915 LUT3 80 ABC + 1916 LUT3 AC c?A:B + 1917 LUT3 35 c?b:a + 1918 LUT3 80 ABC + 1919 LUT2 4 aB + 1920 LUT3 07 c/AB\ + 1921 LUT2 4 aB + 1922 LUT4 FE00 ((/ab\)+C)D + 1923 LUT4 5C00 D(c?a:B) + 1924 LUT4 8F00 ((AB)+c)D + 1925 LUT4 0777 /AB\(d+c) + 1926 LUT2 8 AB + 1927 LUT4 0700 cD/AB\ + 1928 LUT4 8000 ABCD + 1929 LUT2 8 AB + 1930 LUT3 CA C?A:B + 1931 LUT2 9 a^B + 1932 LUT2 8 AB + 1933 LUT3 CA C?A:B + 1934 LUT2 8 AB + 1935 LUT3 CA C?A:B + 1936 LUT2 8 AB + 1937 LUT3 CA C?A:B + 1938 LUT2 8 AB + 1939 LUT3 CA C?A:B + 1940 LUT2 8 AB + 1941 LUT3 CA C?A:B + 1942 LUT4 B0BB /aB\(d+C) + 1943 LUT2 8 AB + 1944 LUT3 CA C?A:B + 1945 LUT2 8 AB + 1946 LUT3 CA C?A:B + 1947 LUT2 8 AB + 1948 LUT3 CA C?A:B + 1949 LUT4 B0BB /aB\(d+C) + 1950 LUT2 8 AB + 1951 LUT3 CA C?A:B + 1952 LUT4 B0BB /aB\(d+C) + 1953 LUT2 8 AB + 1954 LUT3 CA C?A:B + 1955 LUT2 8 AB + 1956 LUT3 CA C?A:B + 1957 LUT2 8 AB + 1958 LUT3 CA C?A:B + 1959 LUT2 8 AB + 1960 LUT3 CA C?A:B + 1961 LUT2 8 AB + 1962 LUT3 CA C?A:B + 1963 LUT2 8 AB + 1964 LUT3 CA C?A:B + 1965 LUT2 8 AB + 1966 LUT3 CA C?A:B + 1967 LUT2 8 AB + 1968 LUT3 CA C?A:B + 1969 LUT2 8 AB + 1970 LUT3 CA C?A:B + 1971 LUT4 8000 ABCD + 1972 LUT2 9 a^B + 1973 LUT2 8 AB + 1974 LUT3 CA C?A:B + 1975 LUT2 9 a^B + 1976 LUT2 8 AB + 1977 LUT3 CA C?A:B + 1978 LUT4 B0BB /aB\(d+C) + 1979 LUT4 B0BB /aB\(d+C) + 1980 LUT2 8 AB + 1981 LUT3 CA C?A:B + 1982 LUT4 9000 CD(a^B) + 1983 LUT4 B0BB /aB\(d+C) + 1984 LUT4 9009 (a^B)(D^c) + 1985 LUT2 8 AB + 1986 LUT3 CA C?A:B + 1987 LUT2 8 AB + 1988 LUT3 CA C?A:B + 1989 LUT2 8 AB + 1990 LUT3 CA C?A:B + 1991 LUT2 8 AB + 1992 LUT3 CA C?A:B + 1993 LUT3 90 C(a^B) + 1994 LUT2 8 AB + 1995 LUT4 9009 (a^B)(D^c) + 1996 LUT2 8 AB + 1997 LUT3 CA C?A:B + 1998 LUT2 8 AB + 1999 LUT3 CA C?A:B + 2000 LUT2 8 AB + 2001 LUT3 CA C?A:B + 2002 LUT4 B0BB /aB\(d+C) + 2003 LUT4 B0BB /aB\(d+C) + 2004 LUT4 B0BB /aB\(d+C) + 2005 LUT2 8 AB + 2006 LUT4 00F8 ((AB)+C)d + 2007 LUT3 07 c/AB\ + 2008 LUT4 8000 ABCD + 2009 LUT4 0D00 cD/Ab\ + 2010 LUT4 B0BB /aB\(d+C) + 2011 LUT2 4 aB + 2012 LUT3 90 C(a^B) + 2013 LUT4 B0BB /aB\(d+C) + 2014 LUT2 4 aB + 2015 LUT4 B0BB /aB\(d+C) + 2016 LUT2 4 aB + 2017 LUT4 B00B /aB\/D^C\ + 2018 LUT4 B0BB /aB\(d+C) + 2019 LUT4 B0BB /aB\(d+C) + 2020 LUT4 B0BB /aB\(d+C) + 2021 LUT4 B0BB /aB\(d+C) + 2022 LUT4 8000 ABCD + 2023 LUT4 8000 ABCD + 2024 LUT4 8000 ABCD + 2025 LUT4 9000 CD(a^B) + 2026 LUT4 0D00 cD/Ab\ + 2027 LUT4 B0BB /aB\(d+C) + 2028 LUT2 4 aB + 2029 LUT4 B0BB /aB\(d+C) + 2030 LUT4 0D00 cD/Ab\ + 2031 LUT2 4 aB + 2032 LUT4 B0BB /aB\(d+C) + 2033 LUT4 B0BB /aB\(d+C) + 2034 LUT4 B0BB /aB\(d+C) + 2035 LUT4 9000 CD(a^B) + 2036 LUT4 0B00 cD/aB\ + 2037 LUT2 4 aB + 2038 LUT4 B0BB /aB\(d+C) + 2039 LUT4 B0BB /aB\(d+C) + 2040 LUT4 0D00 cD/Ab\ + 2041 LUT4 B0BB /aB\(d+C) + 2042 LUT2 4 aB + 2043 LUT4 B000 CD/aB\ + 2044 LUT4 B0BB /aB\(d+C) + 2045 LUT3 90 C(a^B) + 2046 LUT4 B0BB /aB\(d+C) + 2047 LUT4 B0BB /aB\(d+C) + 2048 LUT4 B0BB /aB\(d+C) + 2049 LUT4 B0BB /aB\(d+C) + 2050 LUT4 8000 ABCD + 2051 LUT4 B0BB /aB\(d+C) + 2052 LUT4 B0BB /aB\(d+C) + 2053 LUT4 B0BB /aB\(d+C) + 2054 LUT4 B0BB /aB\(d+C) + 2055 LUT2 8 AB + 2056 LUT4 0777 /AB\(d+c) + 2057 LUT4 8000 ABCD + 2058 LUT4 B0BB /aB\(d+C) + 2059 LUT4 B0BB /aB\(d+C) + 2060 LUT4 B0BB /aB\(d+C) + 2061 LUT2 4 aB + 2062 LUT4 4100 D(B^c)a + 2063 LUT2 6 A^B + 2064 LUT4 9009 (a^B)(D^c) + 2065 LUT4 B0BB /aB\(d+C) + 2066 LUT3 90 C(a^B) + 2067 LUT4 B0BB /aB\(d+C) + 2068 LUT4 B0BB /aB\(d+C) + 2069 LUT4 1001 ab(c^D) + 2070 LUT2 4 aB + 2071 LUT2 4 aB + 2072 LUT4 0D00 cD/Ab\ + 2073 LUT2 4 aB + 2074 LUT4 B0BB /aB\(d+C) + 2075 LUT4 B00B /aB\/D^C\ + 2076 LUT2 8 AB + 2077 LUT4 8000 ABCD + 2078 LUT4 8000 ABCD + 2079 LUT4 9000 CD(a^B) + 2080 LUT3 90 C(a^B) + 2081 LUT3 B0 C/aB\ + 2082 LUT4 9000 CD(a^B) + 2083 LUT4 B0BB /aB\(d+C) + 2084 LUT4 B0BB /aB\(d+C) + 2085 LUT4 B0BB /aB\(d+C) + 2086 LUT4 9009 (a^B)(D^c) + 2087 LUT4 B0BB /aB\(d+C) + 2088 LUT4 9009 (a^B)(D^c) + 2089 LUT4 8000 ABCD + 2090 LUT4 9000 CD(a^B) + 2091 LUT4 0D00 cD/Ab\ + 2092 LUT4 B0BB /aB\(d+C) + 2093 LUT2 4 aB + 2094 LUT4 B0BB /aB\(d+C) + 2095 LUT3 D0 C/Ab\ + 2096 LUT4 B0BB /aB\(d+C) + 2097 LUT4 8000 ABCD + 2098 LUT4 B0BB /aB\(d+C) + 2099 LUT4 B0BB /aB\(d+C) + 2100 LUT4 B0BB /aB\(d+C) + 2101 LUT4 B0BB /aB\(d+C) + 2102 LUT2 8 AB + 2103 LUT2 8 AB + 2104 LUT4 0007 cd/AB\ + 2105 LUT2 8 AB + 2106 LUT4 0700 cD/AB\ + 2107 LUT4 0777 /AB\(d+c) + 2108 LUT3 80 ABC + 2109 LUT4 0700 cD/AB\ + 2110 LUT4 0777 /AB\(d+c) + 2111 LUT3 80 ABC + 2112 LUT4 0700 cD/AB\ + 2113 LUT4 0777 /AB\(d+c) + 2114 LUT2 1 ab + 2115 LUT4 8000 ABCD + 2116 LUT4 0B00 cD/aB\ + 2117 LUT4 B0BB /aB\(d+C) + 2118 LUT2 4 aB + 2119 LUT4 B0BB /aB\(d+C) + 2120 LUT4 9000 CD(a^B) + 2121 LUT4 D000 CD/Ab\ + 2122 LUT4 B0BB /aB\(d+C) + 2123 LUT3 90 C(a^B) + 2124 LUT4 B0BB /aB\(d+C) + 2125 LUT4 4100 D(B^c)a + 2126 LUT3 78 (AB)^C + 2127 LUT4 9009 (a^B)(D^c) + 2128 LUT4 B00B /aB\/D^C\ + 2129 LUT4 B0BB /aB\(d+C) + 2130 LUT4 B0BB /aB\(d+C) + 2131 LUT4 B0BB /aB\(d+C) + 2132 LUT3 40 aBC + 2133 LUT2 4 aB + 2134 LUT4 B0BB /aB\(d+C) + 2135 LUT4 4100 D(B^c)a + 2136 LUT2 6 A^B + 2137 LUT4 9009 (a^B)(D^c) + 2138 LUT3 90 C(a^B) + 2139 LUT2 9 a^B + 2140 LUT4 9009 (a^B)(D^c) + 2141 LUT4 B0BB /aB\(d+C) + 2142 LUT4 B0BB /aB\(d+C) + 2143 LUT2 9 a^B + 2144 LUT4 0777 /AB\(d+c) + 2145 LUT3 35 c?b:a + 2146 LUT2 4 aB + 2147 LUT3 4F (aB)+c + 2148 LUT3 C5 C?a:B + 2149 LUT3 35 c?b:a + 2150 LUT4 0100 abcD + 2151 LUT4 8000 ABCD + 2152 LUT4 1000 abCD + 2153 LUT4 1001 ab(c^D) + 2154 LUT2 4 aB + 2155 LUT2 4 aB + 2156 LUT2 4 aB + 2157 LUT2 4 aB + 2158 LUT2 9 a^B + 2159 LUT2 4 aB + 2160 LUT2 4 aB + 2161 LUT2 4 aB + 2162 LUT2 4 aB + 2163 LUT2 4 aB + 2164 LUT4 1000 abCD + 2165 LUT4 1000 abCD + 2166 LUT4 0100 abcD + 2167 LUT2 4 aB + 2168 LUT2 4 aB + 2169 LUT2 4 aB + 2170 LUT4 4100 D(B^c)a + 2171 LUT4 B0BB /aB\(d+C) + 2172 LUT2 4 aB + 2173 LUT2 4 aB + 2174 LUT2 6 A^B + 2175 LUT2 6 A^B + 2176 LUT4 9009 (a^B)(D^c) + 2177 LUT4 4100 D(B^c)a + 2178 LUT4 9009 (a^B)(D^c) + 2179 LUT2 6 A^B + 2180 LUT4 0001 abcd + 2181 LUT2 6 A^B + 2182 LUT2 6 A^B + 2183 LUT2 6 A^B + 2184 LUT2 6 A^B + 2185 LUT4 FCFA DC?A:B:1:1 + 2186 LUT4 FE00 ((/ab\)+C)D + 2187 LUT2 4 aB + 2188 LUT4 8000 ABCD + 2189 LUT4 8000 ABCD + 2190 LUT4 7000 CD/AB\ + 2191 LUT4 0777 /AB\(d+c) + 2192 LUT4 0777 /AB\(d+c) + 2193 LUT4 7000 CD/AB\ + 2194 LUT3 70 C/AB\ + 2195 LUT4 0777 /AB\(d+c) + 2196 LUT4 0777 /AB\(d+c) + 2197 LUT3 40 aBC + 2198 LUT2 8 AB + 2199 LUT4 0700 cD/AB\ + 2200 LUT2 8 AB + 2201 LUT4 0777 /AB\(d+c) + 2202 LUT4 7000 CD/AB\ + 2203 LUT4 0777 /AB\(d+c) + 2204 LUT4 0777 /AB\(d+c) + 2205 LUT4 0700 cD/AB\ + 2206 LUT2 8 AB + 2207 LUT4 0777 /AB\(d+c) + 2208 LUT4 0007 cd/AB\ + 2209 LUT2 8 AB + 2210 LUT2 8 AB + 2211 LUT4 0700 cD/AB\ + 2212 LUT4 0777 /AB\(d+c) + 2213 LUT2 8 AB + 2214 LUT2 8 AB + 2215 LUT2 8 AB + 2216 LUT4 F8FF (AB)+C+d + 2217 LUT4 1F00 ((ab)+c)D + 2218 LUT3 B0 C/aB\ + 2219 LUT4 00BF ((/aB\)+c)d + 2220 LUT2 4 aB + 2221 LUT4 1000 abCD + 2222 LUT2 4 aB + 2223 LUT4 1428 (B^C)(A^D) + 2224 LUT3 80 ABC + 2225 LUT4 8000 ABCD + 2226 LUT4 8000 ABCD + 2227 LUT4 0777 /AB\(d+c) + 2228 LUT4 0777 /AB\(d+c) + 2229 LUT4 0777 /AB\(d+c) + 2230 LUT4 0777 /AB\(d+c) + 2231 LUT3 70 C/AB\ + 2232 LUT4 0777 /AB\(d+c) + 2233 LUT4 0777 /AB\(d+c) + 2234 LUT4 0777 /AB\(d+c) + 2235 LUT4 8000 ABCD + 2236 LUT4 0777 /AB\(d+c) + 2237 LUT4 0777 /AB\(d+c) + 2238 LUT4 0777 /AB\(d+c) + 2239 LUT4 0777 /AB\(d+c) + 2240 LUT4 8000 ABCD + 2241 LUT4 0777 /AB\(d+c) + 2242 LUT4 0777 /AB\(d+c) + 2243 LUT4 0777 /AB\(d+c) + 2244 LUT4 0777 /AB\(d+c) + 2245 LUT3 CA C?A:B + 2246 LUT3 8F (AB)+c + 2247 LUT4 F3F5 DC?a:b:1:1 + 2248 LUT2 6 A^B + 2249 LUT4 B000 CD/aB\ + 2250 LUT3 70 C/AB\ + 2251 LUT3 70 C/AB\ + 2252 LUT4 0BBB /aB\(d+c) + 2253 LUT4 440F D?c:aB + 2254 LUT4 F3F5 DC?a:b:1:1 + 2255 LUT3 07 c/AB\ + 2256 LUT3 CA C?A:B + 2257 LUT3 CA C?A:B + 2258 LUT2 8 AB + 2259 LUT4 0777 /AB\(d+c) + 2260 LUT4 0777 /AB\(d+c) + 2261 LUT2 8 AB + 2262 LUT4 0777 /AB\(d+c) + 2263 LUT4 0777 /AB\(d+c) + 2264 LUT4 F088 D?AB:C + 2265 LUT2 8 AB + 2266 LUT4 0777 /AB\(d+c) + 2267 LUT4 0777 /AB\(d+c) + 2268 LUT4 0777 /AB\(d+c) + 2269 LUT4 0777 /AB\(d+c) + 2270 LUT4 EF00 ((/ab\)+c)D + 2271 LUT4 3500 D(c?b:a) + 2272 LUT4 F088 D?AB:C + 2273 LUT4 0777 /AB\(d+c) + 2274 LUT4 0007 cd/AB\ + 2275 LUT4 4000 aBCD + 2276 LUT4 1000 abCD + 2277 LUT3 CA C?A:B + 2278 LUT3 35 c?b:a + 2279 LUT4 3500 D(c?b:a) + 2280 LUT3 35 c?b:a + 2281 LUT3 35 c?b:a + 2282 LUT4 3500 D(c?b:a) + 2283 LUT3 35 c?b:a + 2284 LUT3 35 c?b:a + 2285 LUT3 53 C?b:a + 2286 LUT4 3500 D(c?b:a) + 2287 LUT3 35 c?b:a + 2288 LUT4 3500 D(c?b:a) + 2289 LUT3 35 c?b:a + 2290 LUT4 8F00 ((AB)+c)D + 2291 LUT4 0777 /AB\(d+c) + 2292 LUT2 8 AB + 2293 LUT4 0007 cd/AB\ + 2294 LUT3 80 ABC + 2295 LUT3 80 ABC + 2296 LUT4 0777 /AB\(d+c) + 2297 LUT4 440F D?c:aB + 2298 LUT3 35 c?b:a + 2299 LUT2 8 AB + 2300 LUT2 8 AB + 2301 LUT4 0D00 cD/Ab\ + 2302 LUT4 8F00 ((AB)+c)D + 2303 LUT4 0777 /AB\(d+c) + 2304 LUT4 0007 cd/AB\ + 2305 LUT3 80 ABC + 2306 LUT3 80 ABC + 2307 LUT4 B0BB /aB\(d+C) + 2308 LUT4 BF00 ((/aB\)+c)D + 2309 LUT4 0777 /AB\(d+c) + 2310 LUT2 8 AB + 2311 LUT4 0777 /AB\(d+c) + 2312 LUT4 0777 /AB\(d+c) + 2313 LUT3 5C c?a:B + 2314 LUT2 4 aB + 2315 LUT2 B /aB\ + 2316 LUT4 AC00 D(c?A:B) + 2317 LUT2 4 aB + 2318 LUT3 40 aBC + 2319 LUT4 0100 abcD + 2320 LUT4 4000 aBCD + 2321 LUT3 80 ABC + 2322 LUT2 4 aB + 2323 LUT2 8 AB + 2324 LUT4 8000 ABCD + 2325 LUT4 0BBB /aB\(d+c) + 2326 LUT2 8 AB + 2327 LUT4 4000 aBCD + 2328 LUT4 7007 (c^D)/AB\ + 2329 LUT2 8 AB + 2330 LUT4 8000 ABCD + 2331 LUT4 4000 aBCD + 2332 LUT4 4000 aBCD + 2333 LUT2 8 AB + 2334 LUT2 8 AB + 2335 LUT3 40 aBC + 2336 LUT4 F0BB D?/aB\:C + 2337 LUT3 3A c?b:A + 2338 LUT3 CA C?A:B + 2339 LUT3 80 ABC + 2340 LUT3 35 c?b:a + 2341 LUT3 80 ABC + 2342 LUT3 35 c?b:a + 2343 LUT3 80 ABC + 2344 LUT4 0EEE /ab\(d+c) + 2345 LUT4 8000 ABCD + 2346 LUT4 7000 CD/AB\ + 2347 LUT4 0700 cD/AB\ + 2348 LUT4 0777 /AB\(d+c) + 2349 LUT2 8 AB + 2350 LUT4 0777 /AB\(d+c) + 2351 LUT4 8000 ABCD + 2352 LUT4 0777 /AB\(d+c) + 2353 LUT4 0777 /AB\(d+c) + 2354 LUT4 0777 /AB\(d+c) + 2355 LUT4 0777 /AB\(d+c) + 2356 LUT4 8000 ABCD + 2357 LUT4 0777 /AB\(d+c) + 2358 LUT4 0777 /AB\(d+c) + 2359 LUT4 0777 /AB\(d+c) + 2360 LUT4 0777 /AB\(d+c) + 2361 LUT4 8000 ABCD + 2362 LUT4 0777 /AB\(d+c) + 2363 LUT4 0777 /AB\(d+c) + 2364 LUT4 0777 /AB\(d+c) + 2365 LUT4 0777 /AB\(d+c) + 2366 LUT3 8F (AB)+c + 2367 LUT4 0700 cD/AB\ + 2368 LUT3 70 C/AB\ + 2369 LUT4 00BF ((/aB\)+c)d + 2370 LUT2 4 aB + 2371 LUT4 1000 abCD + 2372 LUT4 1000 abCD + 2373 LUT2 8 AB + 2374 LUT2 8 AB + 2375 LUT4 0777 /AB\(d+c) + 2376 LUT4 0777 /AB\(d+c) + 2377 LUT2 8 AB + 2378 LUT4 7000 CD/AB\ + 2379 LUT4 0777 /AB\(d+c) + 2380 LUT4 0777 /AB\(d+c) + 2381 LUT4 7000 CD/AB\ + 2382 LUT4 7000 CD/AB\ + 2383 LUT4 0777 /AB\(d+c) + 2384 LUT4 0777 /AB\(d+c) + 2385 LUT4 0777 /AB\(d+c) + 2386 LUT4 7000 CD/AB\ + 2387 LUT4 7000 CD/AB\ + 2388 LUT4 0777 /AB\(d+c) + 2389 LUT4 0777 /AB\(d+c) + 2390 LUT4 0777 /AB\(d+c) + 2391 LUT3 CA C?A:B + 2392 LUT3 8F (AB)+c + 2393 LUT4 F53F DC?1:a:b:1 + 2394 LUT3 80 ABC + 2395 LUT2 6 A^B + 2396 LUT4 E000 CD/ab\ + 2397 LUT4 7077 /AB\(d+C) + 2398 LUT2 8 AB + 2399 LUT4 8000 ABCD + 2400 LUT4 8000 ABCD + 2401 LUT4 0777 /AB\(d+c) + 2402 LUT4 0777 /AB\(d+c) + 2403 LUT4 0777 /AB\(d+c) + 2404 LUT4 0777 /AB\(d+c) + 2405 LUT4 0700 cD/AB\ + 2406 LUT4 0777 /AB\(d+c) + 2407 LUT2 8 AB + 2408 LUT4 0777 /AB\(d+c) + 2409 LUT4 0777 /AB\(d+c) + 2410 LUT4 8000 ABCD + 2411 LUT3 70 C/AB\ + 2412 LUT4 0777 /AB\(d+c) + 2413 LUT4 8000 ABCD + 2414 LUT4 0777 /AB\(d+c) + 2415 LUT4 0777 /AB\(d+c) + 2416 LUT4 0777 /AB\(d+c) + 2417 LUT4 0777 /AB\(d+c) + 2418 LUT4 0777 /AB\(d+c) + 2419 LUT4 0777 /AB\(d+c) + 2420 LUT3 70 C/AB\ + 2421 LUT3 70 C/AB\ + 2422 LUT4 0BBB /aB\(d+c) + 2423 LUT4 440F D?c:aB + 2424 LUT4 F3F5 DC?a:b:1:1 + 2425 LUT3 07 c/AB\ + 2426 LUT3 CA C?A:B + 2427 LUT3 CA C?A:B + 2428 LUT2 8 AB + 2429 LUT4 0777 /AB\(d+c) + 2430 LUT4 0777 /AB\(d+c) + 2431 LUT2 8 AB + 2432 LUT4 0777 /AB\(d+c) + 2433 LUT4 0777 /AB\(d+c) + 2434 LUT4 F088 D?AB:C + 2435 LUT2 8 AB + 2436 LUT4 0777 /AB\(d+c) + 2437 LUT4 0777 /AB\(d+c) + 2438 LUT4 0777 /AB\(d+c) + 2439 LUT4 0777 /AB\(d+c) + 2440 LUT4 EF00 ((/ab\)+c)D + 2441 LUT4 3500 D(c?b:a) + 2442 LUT4 F088 D?AB:C + 2443 LUT4 0777 /AB\(d+c) + 2444 LUT4 0007 cd/AB\ + 2445 LUT4 4000 aBCD + 2446 LUT4 1000 abCD + 2447 LUT3 CA C?A:B + 2448 LUT3 35 c?b:a + 2449 LUT4 3500 D(c?b:a) + 2450 LUT3 35 c?b:a + 2451 LUT3 35 c?b:a + 2452 LUT4 3500 D(c?b:a) + 2453 LUT3 35 c?b:a + 2454 LUT3 35 c?b:a + 2455 LUT3 53 C?b:a + 2456 LUT4 3500 D(c?b:a) + 2457 LUT3 35 c?b:a + 2458 LUT4 3500 D(c?b:a) + 2459 LUT3 35 c?b:a + 2460 LUT4 8F00 ((AB)+c)D + 2461 LUT4 0777 /AB\(d+c) + 2462 LUT4 0007 cd/AB\ + 2463 LUT3 80 ABC + 2464 LUT3 80 ABC + 2465 LUT4 0777 /AB\(d+c) + 2466 LUT3 C5 C?a:B + 2467 LUT2 4 aB + 2468 LUT3 35 c?b:a + 2469 LUT2 8 AB + 2470 LUT2 8 AB + 2471 LUT4 0D00 cD/Ab\ + 2472 LUT4 8F00 ((AB)+c)D + 2473 LUT4 0777 /AB\(d+c) + 2474 LUT4 0007 cd/AB\ + 2475 LUT3 80 ABC + 2476 LUT3 80 ABC + 2477 LUT4 B0BB /aB\(d+C) + 2478 LUT4 BF00 ((/aB\)+c)D + 2479 LUT4 0777 /AB\(d+c) + 2480 LUT2 8 AB + 2481 LUT4 0777 /AB\(d+c) + 2482 LUT4 0777 /AB\(d+c) + 2483 LUT2 4 aB + 2484 LUT3 5C c?a:B + 2485 LUT2 4 aB + 2486 LUT4 FFF2 (Ab)+C+D + 2487 LUT4 AC00 D(c?A:B) + 2488 LUT2 4 aB + 2489 LUT4 0BBB /aB\(d+c) + 2490 LUT3 07 c/AB\ + 2491 LUT4 0777 /AB\(d+c) + 2492 LUT3 3A c?b:A + 2493 LUT3 CA C?A:B + 2494 LUT3 80 ABC + 2495 LUT3 35 c?b:a + 2496 LUT3 80 ABC + 2497 LUT2 4 aB + 2498 LUT3 35 c?b:a + 2499 LUT3 80 ABC + 2500 LUT3 8F (AB)+c + 2501 LUT4 0700 cD/AB\ + 2502 LUT3 70 C/AB\ + 2503 LUT4 00BF ((/aB\)+c)d + 2504 LUT2 4 aB + 2505 LUT4 1000 abCD + 2506 LUT4 8000 ABCD + 2507 LUT4 7000 CD/AB\ + 2508 LUT4 7000 CD/AB\ + 2509 LUT4 0007 cd/AB\ + 2510 LUT2 8 AB + 2511 LUT2 8 AB + 2512 LUT4 0700 cD/AB\ + 2513 LUT2 8 AB + 2514 LUT4 0777 /AB\(d+c) + 2515 LUT4 7000 CD/AB\ + 2516 LUT4 0700 cD/AB\ + 2517 LUT2 8 AB + 2518 LUT4 0777 /AB\(d+c) + 2519 LUT4 0777 /AB\(d+c) + 2520 LUT4 7000 CD/AB\ + 2521 LUT4 7000 CD/AB\ + 2522 LUT4 0777 /AB\(d+c) + 2523 LUT4 0777 /AB\(d+c) + 2524 LUT4 0777 /AB\(d+c) + 2525 LUT4 7000 CD/AB\ + 2526 LUT4 0777 /AB\(d+c) + 2527 LUT4 0777 /AB\(d+c) + 2528 LUT4 0777 /AB\(d+c) + 2529 LUT3 CA C?A:B + 2530 LUT3 8F (AB)+c + 2531 LUT4 F3F5 DC?a:b:1:1 + 2532 LUT2 6 A^B + 2533 LUT4 0D00 cD/Ab\ + 2534 LUT4 7F00 ((/AB\)+c)D + 2535 LUT4 8000 ABCD + 2536 LUT4 4000 aBCD + 2537 LUT4 0777 /AB\(d+c) + 2538 LUT4 0777 /AB\(d+c) + 2539 LUT2 8 AB + 2540 LUT4 0777 /AB\(d+c) + 2541 LUT4 0777 /AB\(d+c) + 2542 LUT4 0777 /AB\(d+c) + 2543 LUT4 0700 cD/AB\ + 2544 LUT2 8 AB + 2545 LUT4 0777 /AB\(d+c) + 2546 LUT4 8000 ABCD + 2547 LUT4 0777 /AB\(d+c) + 2548 LUT4 0777 /AB\(d+c) + 2549 LUT4 0777 /AB\(d+c) + 2550 LUT4 0777 /AB\(d+c) + 2551 LUT4 8000 ABCD + 2552 LUT4 0777 /AB\(d+c) + 2553 LUT4 0777 /AB\(d+c) + 2554 LUT4 0777 /AB\(d+c) + 2555 LUT4 0777 /AB\(d+c) + 2556 LUT3 70 C/AB\ + 2557 LUT3 70 C/AB\ + 2558 LUT4 0BBB /aB\(d+c) + 2559 LUT4 440F D?c:aB + 2560 LUT4 F3F5 DC?a:b:1:1 + 2561 LUT3 07 c/AB\ + 2562 LUT3 E0 C/ab\ + 2563 LUT2 B /aB\ + 2564 LUT3 8F (AB)+c + 2565 LUT4 0700 cD/AB\ + 2566 LUT3 70 C/AB\ + 2567 LUT4 00BF ((/aB\)+c)d + 2568 LUT2 4 aB + 2569 LUT4 EF00 ((/ab\)+c)D + 2570 LUT4 BF00 ((/aB\)+c)D + 2571 LUT2 8 AB + 2572 LUT4 0700 cD/AB\ + 2573 LUT2 8 AB + 2574 LUT4 8000 ABCD + 2575 LUT4 000D cd/Ab\ + 2576 LUT4 1001 ab(c^D) + 2577 LUT4 9009 (a^B)(D^c) + 2578 LUT4 B0BB /aB\(d+C) + 2579 LUT4 B000 CD/aB\ + 2580 LUT4 B0BB /aB\(d+C) + 2581 LUT4 0700 cD/AB\ + 2582 LUT4 8000 ABCD + 2583 LUT4 8000 ABCD + 2584 LUT4 8000 ABCD + 2585 LUT3 80 ABC + 2586 LUT4 1001 ab(c^D) + 2587 LUT4 B0BB /aB\(d+C) + 2588 LUT4 1001 ab(c^D) + 2589 LUT4 B0BB /aB\(d+C) + 2590 LUT4 B0BB /aB\(d+C) + 2591 LUT4 B0BB /aB\(d+C) + 2592 LUT4 000B cd/aB\ + 2593 LUT4 9000 CD(a^B) + 2594 LUT4 9000 CD(a^B) + 2595 LUT4 B000 CD/aB\ + 2596 LUT4 B0BB /aB\(d+C) + 2597 LUT4 9009 (a^B)(D^c) + 2598 LUT4 9000 CD(a^B) + 2599 LUT3 10 abC + 2600 LUT4 4100 D(B^c)a + 2601 LUT3 90 C(a^B) + 2602 LUT4 8000 ABCD + 2603 LUT4 8000 ABCD + 2604 LUT4 0D00 cD/Ab\ + 2605 LUT3 0D c/Ab\ + 2606 LUT3 40 aBC + 2607 LUT4 8000 ABCD + 2608 LUT4 B0BB /aB\(d+C) + 2609 LUT4 B0BB /aB\(d+C) + 2610 LUT4 8000 ABCD + 2611 LUT4 9000 CD(a^B) + 2612 LUT4 B0BB /aB\(d+C) + 2613 LUT4 9009 (a^B)(D^c) + 2614 LUT4 1001 ab(c^D) + 2615 LUT4 9000 CD(a^B) + 2616 LUT4 B0BB /aB\(d+C) + 2617 LUT4 9009 (a^B)(D^c) + 2618 LUT4 4100 D(B^c)a + 2619 LUT4 9009 (a^B)(D^c) + 2620 LUT4 8000 ABCD + 2621 LUT4 9009 (a^B)(D^c) + 2622 LUT4 B0BB /aB\(d+C) + 2623 LUT4 9009 (a^B)(D^c) + 2624 LUT4 B0BB /aB\(d+C) + 2625 LUT4 9009 (a^B)(D^c) + 2626 LUT4 9000 CD(a^B) + 2627 LUT3 41 (B^c)a + 2628 LUT4 4100 D(B^c)a + 2629 LUT4 9009 (a^B)(D^c) + 2630 LUT4 9000 CD(a^B) + 2631 LUT3 01 abc + 2632 LUT4 B0BB /aB\(d+C) + 2633 LUT4 0777 /AB\(d+c) + 2634 LUT4 0700 cD/AB\ + 2635 LUT2 8 AB + 2636 LUT4 0700 cD/AB\ + 2637 LUT4 0777 /AB\(d+c) + 2638 LUT4 0700 cD/AB\ + 2639 LUT2 8 AB + 2640 LUT4 0700 cD/AB\ + 2641 LUT4 0700 cD/AB\ + 2642 LUT2 8 AB + 2643 LUT4 0700 cD/AB\ + 2644 LUT2 1 ab + 2645 LUT3 40 aBC + 2646 LUT4 8000 ABCD + 2647 LUT4 9000 CD(a^B) + 2648 LUT4 4000 aBCD + 2649 LUT3 90 C(a^B) + 2650 LUT3 B0 C/aB\ + 2651 LUT4 B0BB /aB\(d+C) + 2652 LUT4 9009 (a^B)(D^c) + 2653 LUT3 40 aBC + 2654 LUT4 9009 (a^B)(D^c) + 2655 LUT4 4000 aBCD + 2656 LUT4 B00B /aB\/D^C\ + 2657 LUT3 90 C(a^B) + 2658 LUT4 9000 CD(a^B) + 2659 LUT4 9009 (a^B)(D^c) + 2660 LUT3 90 C(a^B) + 2661 LUT4 8000 ABCD + 2662 LUT2 8 AB + 2663 LUT4 0700 cD/AB\ + 2664 LUT2 8 AB + 2665 LUT4 8000 ABCD + 2666 LUT4 0700 cD/AB\ + 2667 LUT4 8000 ABCD + 2668 LUT4 8000 ABCD + 2669 LUT4 8000 ABCD + 2670 LUT4 0700 cD/AB\ + 2671 LUT4 007F ((/AB\)+c)d + 2672 LUT4 0777 /AB\(d+c) + 2673 LUT4 0700 cD/AB\ + 2674 LUT4 0700 cD/AB\ + 2675 LUT2 8 AB + 2676 LUT4 0700 cD/AB\ + 2677 LUT3 80 ABC + 2678 LUT4 0777 /AB\(d+c) + 2679 LUT4 0700 cD/AB\ + 2680 LUT4 0777 /AB\(d+c) + 2681 LUT4 C500 D(C?a:B) + 2682 LUT4 0FBB D?/aB\:c + 2683 LUT2 8 AB + 2684 LUT4 7000 CD/AB\ + 2685 LUT2 4 aB + 2686 LUT3 80 ABC + 2687 LUT2 8 AB + 2688 LUT3 80 ABC + 2689 LUT4 0777 /AB\(d+c) + 2690 LUT3 80 ABC + 2691 LUT3 80 ABC + 2692 LUT4 0700 cD/AB\ + 2693 LUT4 0700 cD/AB\ + 2694 LUT2 8 AB + 2695 LUT4 0700 cD/AB\ + 2696 LUT3 80 ABC + 2697 LUT4 0777 /AB\(d+c) + 2698 LUT4 7000 CD/AB\ + 2699 LUT4 007F ((/AB\)+c)d + 2700 LUT4 0777 /AB\(d+c) + 2701 LUT4 7000 CD/AB\ + 2702 LUT4 4F00 ((aB)+c)D + 2703 LUT2 8 AB + 2704 LUT4 0700 cD/AB\ + 2705 LUT4 0700 cD/AB\ + 2706 LUT3 80 ABC + 2707 LUT4 8000 ABCD + 2708 LUT2 8 AB + 2709 LUT3 80 ABC + 2710 LUT3 80 ABC + 2711 LUT4 0700 cD/AB\ + 2712 LUT4 007F ((/AB\)+c)d + 2713 LUT4 0777 /AB\(d+c) + 2714 LUT4 0700 cD/AB\ + 2715 LUT3 80 ABC + 2716 LUT4 0700 cD/AB\ + 2717 LUT4 0777 /AB\(d+c) + 2718 LUT4 0700 cD/AB\ + 2719 LUT2 8 AB + 2720 LUT4 0700 cD/AB\ + 2721 LUT2 1 ab + 2722 LUT3 80 ABC + 2723 LUT3 40 aBC + 2724 LUT4 0777 /AB\(d+c) + 2725 LUT2 1 ab + 2726 LUT4 F011 D?ab:C + 2727 LUT4 1000 abCD + 2728 LUT4 9000 CD(a^B) + 2729 LUT3 90 C(a^B) + 2730 LUT4 9009 (a^B)(D^c) + 2731 LUT3 90 C(a^B) + 2732 LUT4 B0BB /aB\(d+C) + 2733 LUT3 01 abc + 2734 LUT4 9009 (a^B)(D^c) + 2735 LUT4 9000 CD(a^B) + 2736 LUT4 D000 CD/Ab\ + 2737 LUT3 0B c/aB\ + 2738 LUT4 B0BB /aB\(d+C) + 2739 LUT3 90 C(a^B) + 2740 LUT4 B0BB /aB\(d+C) + 2741 LUT4 D000 CD/Ab\ + 2742 LUT4 B0BB /aB\(d+C) + 2743 LUT4 B0BB /aB\(d+C) + 2744 LUT4 B0BB /aB\(d+C) + 2745 LUT4 B0BB /aB\(d+C) + 2746 LUT4 D000 CD/Ab\ + 2747 LUT4 B0BB /aB\(d+C) + 2748 LUT4 B0BB /aB\(d+C) + 2749 LUT3 80 ABC + 2750 LUT4 9009 (a^B)(D^c) + 2751 LUT4 AC00 D(c?A:B) + 2752 LUT4 AC00 D(c?A:B) + 2753 LUT4 0FBB D?/aB\:c + 2754 LUT4 1000 abCD + 2755 LUT3 80 ABC + 2756 LUT4 8000 ABCD + 2757 LUT4 8000 ABCD + 2758 LUT4 0777 /AB\(d+c) + 2759 LUT4 0777 /AB\(d+c) + 2760 LUT4 0777 /AB\(d+c) + 2761 LUT4 0777 /AB\(d+c) + 2762 LUT3 70 C/AB\ + 2763 LUT4 0777 /AB\(d+c) + 2764 LUT4 0777 /AB\(d+c) + 2765 LUT4 0777 /AB\(d+c) + 2766 LUT4 8000 ABCD + 2767 LUT4 0777 /AB\(d+c) + 2768 LUT4 0777 /AB\(d+c) + 2769 LUT4 0777 /AB\(d+c) + 2770 LUT4 0777 /AB\(d+c) + 2771 LUT4 8000 ABCD + 2772 LUT4 0777 /AB\(d+c) + 2773 LUT4 0777 /AB\(d+c) + 2774 LUT4 0777 /AB\(d+c) + 2775 LUT4 0777 /AB\(d+c) + 2776 LUT3 CA C?A:B + 2777 LUT3 8F (AB)+c + 2778 LUT4 F53F DC?1:a:b:1 + 2779 LUT2 6 A^B + 2780 LUT3 40 aBC + 2781 LUT4 7F00 ((/AB\)+c)D + 2782 LUT4 8000 ABCD + 2783 LUT4 7000 CD/AB\ + 2784 LUT4 0700 cD/AB\ + 2785 LUT4 0777 /AB\(d+c) + 2786 LUT2 8 AB + 2787 LUT4 0777 /AB\(d+c) + 2788 LUT4 0700 cD/AB\ + 2789 LUT4 0777 /AB\(d+c) + 2790 LUT2 8 AB + 2791 LUT4 0777 /AB\(d+c) + 2792 LUT4 0777 /AB\(d+c) + 2793 LUT4 8000 ABCD + 2794 LUT4 0777 /AB\(d+c) + 2795 LUT4 0777 /AB\(d+c) + 2796 LUT4 0777 /AB\(d+c) + 2797 LUT4 0777 /AB\(d+c) + 2798 LUT4 8000 ABCD + 2799 LUT4 0777 /AB\(d+c) + 2800 LUT4 0777 /AB\(d+c) + 2801 LUT4 0777 /AB\(d+c) + 2802 LUT4 0777 /AB\(d+c) + 2803 LUT3 70 C/AB\ + 2804 LUT3 70 C/AB\ + 2805 LUT4 0BBB /aB\(d+c) + 2806 LUT4 440F D?c:aB + 2807 LUT4 F3F5 DC?a:b:1:1 + 2808 LUT3 07 c/AB\ + 2809 LUT3 CA C?A:B + 2810 LUT3 AC c?A:B + 2811 LUT2 8 AB + 2812 LUT4 0777 /AB\(d+c) + 2813 LUT4 0777 /AB\(d+c) + 2814 LUT2 8 AB + 2815 LUT4 0777 /AB\(d+c) + 2816 LUT4 0777 /AB\(d+c) + 2817 LUT4 F088 D?AB:C + 2818 LUT2 8 AB + 2819 LUT4 0777 /AB\(d+c) + 2820 LUT4 0777 /AB\(d+c) + 2821 LUT4 0777 /AB\(d+c) + 2822 LUT4 0777 /AB\(d+c) + 2823 LUT4 EF00 ((/ab\)+c)D + 2824 LUT4 5300 D(C?b:a) + 2825 LUT4 8F00 ((AB)+c)D + 2826 LUT4 0777 /AB\(d+c) + 2827 LUT4 0007 cd/AB\ + 2828 LUT3 80 ABC + 2829 LUT3 80 ABC + 2830 LUT4 0777 /AB\(d+c) + 2831 LUT3 C5 C?a:B + 2832 LUT2 4 aB + 2833 LUT4 3500 D(c?b:a) + 2834 LUT3 35 c?b:a + 2835 LUT3 53 C?b:a + 2836 LUT3 35 c?b:a + 2837 LUT4 5300 D(C?b:a) + 2838 LUT3 53 C?b:a + 2839 LUT3 35 c?b:a + 2840 LUT4 3500 D(c?b:a) + 2841 LUT3 35 c?b:a + 2842 LUT2 8 AB + 2843 LUT2 8 AB + 2844 LUT4 5300 D(C?b:a) + 2845 LUT3 35 c?b:a + 2846 LUT4 F088 D?AB:C + 2847 LUT4 0777 /AB\(d+c) + 2848 LUT4 0007 cd/AB\ + 2849 LUT4 4000 aBCD + 2850 LUT4 1000 abCD + 2851 LUT3 CA C?A:B + 2852 LUT3 35 c?b:a + 2853 LUT3 35 c?b:a + 2854 LUT4 0D00 cD/Ab\ + 2855 LUT4 8F00 ((AB)+c)D + 2856 LUT4 0777 /AB\(d+c) + 2857 LUT4 0007 cd/AB\ + 2858 LUT3 80 ABC + 2859 LUT3 80 ABC + 2860 LUT3 0B c/aB\ + 2861 LUT2 4 aB + 2862 LUT4 BF00 ((/aB\)+c)D + 2863 LUT4 0777 /AB\(d+c) + 2864 LUT2 8 AB + 2865 LUT4 0777 /AB\(d+c) + 2866 LUT4 0777 /AB\(d+c) + 2867 LUT2 4 aB + 2868 LUT3 5C c?a:B + 2869 LUT2 4 aB + 2870 LUT2 B /aB\ + 2871 LUT4 AC00 D(c?A:B) + 2872 LUT2 8 AB + 2873 LUT3 80 ABC + 2874 LUT4 4000 aBCD + 2875 LUT4 4000 aBCD + 2876 LUT4 7F00 ((/AB\)+c)D + 2877 LUT4 0777 /AB\(d+c) + 2878 LUT4 F0BB D?/aB\:C + 2879 LUT3 5C c?a:B + 2880 LUT3 35 c?b:a + 2881 LUT3 80 ABC + 2882 LUT3 CA C?A:B + 2883 LUT3 80 ABC + 2884 LUT4 0F77 D?/AB\:c + 2885 LUT4 F044 D?aB:C + 2886 LUT3 07 c/AB\ + 2887 LUT4 0BBB /aB\(d+c) + 2888 LUT4 F8FF (AB)+C+d + 2889 LUT3 70 C/AB\ + 2890 LUT4 00BF ((/aB\)+c)d + 2891 LUT2 4 aB + 2892 LUT4 1000 abCD + 2893 LUT3 80 ABC + 2894 LUT4 7000 CD/AB\ + 2895 LUT4 7000 CD/AB\ + 2896 LUT4 0700 cD/AB\ + 2897 LUT2 8 AB + 2898 LUT4 0777 /AB\(d+c) + 2899 LUT4 0777 /AB\(d+c) + 2900 LUT4 0007 cd/AB\ + 2901 LUT2 8 AB + 2902 LUT2 8 AB + 2903 LUT4 8000 ABCD + 2904 LUT3 70 C/AB\ + 2905 LUT3 70 C/AB\ + 2906 LUT4 0777 /AB\(d+c) + 2907 LUT4 0700 cD/AB\ + 2908 LUT2 8 AB + 2909 LUT4 0777 /AB\(d+c) + 2910 LUT4 0777 /AB\(d+c) + 2911 LUT4 0777 /AB\(d+c) + 2912 LUT4 7000 CD/AB\ + 2913 LUT4 7000 CD/AB\ + 2914 LUT4 0777 /AB\(d+c) + 2915 LUT4 0777 /AB\(d+c) + 2916 LUT4 0777 /AB\(d+c) + 2917 LUT2 9 a^B + 2918 LUT3 40 aBC + 2919 LUT4 7F00 ((/AB\)+c)D + 2920 LUT4 8000 ABCD + 2921 LUT4 8000 ABCD + 2922 LUT4 0777 /AB\(d+c) + 2923 LUT4 0777 /AB\(d+c) + 2924 LUT4 0777 /AB\(d+c) + 2925 LUT4 0777 /AB\(d+c) + 2926 LUT2 8 AB + 2927 LUT4 0777 /AB\(d+c) + 2928 LUT4 0777 /AB\(d+c) + 2929 LUT4 0777 /AB\(d+c) + 2930 LUT4 0777 /AB\(d+c) + 2931 LUT4 7000 CD/AB\ + 2932 LUT4 0700 cD/AB\ + 2933 LUT4 0777 /AB\(d+c) + 2934 LUT2 8 AB + 2935 LUT4 0777 /AB\(d+c) + 2936 LUT4 8000 ABCD + 2937 LUT4 0777 /AB\(d+c) + 2938 LUT4 0777 /AB\(d+c) + 2939 LUT4 0777 /AB\(d+c) + 2940 LUT4 0777 /AB\(d+c) + 2941 LUT3 70 C/AB\ + 2942 LUT3 70 C/AB\ + 2943 LUT4 0BBB /aB\(d+c) + 2944 LUT4 440F D?c:aB + 2945 LUT4 F3F5 DC?a:b:1:1 + 2946 LUT3 07 c/AB\ + 2947 LUT3 CA C?A:B + 2948 LUT3 CA C?A:B + 2949 LUT2 8 AB + 2950 LUT4 0777 /AB\(d+c) + 2951 LUT4 0777 /AB\(d+c) + 2952 LUT2 8 AB + 2953 LUT4 0777 /AB\(d+c) + 2954 LUT4 0777 /AB\(d+c) + 2955 LUT4 F088 D?AB:C + 2956 LUT2 8 AB + 2957 LUT4 0777 /AB\(d+c) + 2958 LUT4 0777 /AB\(d+c) + 2959 LUT4 0777 /AB\(d+c) + 2960 LUT4 0777 /AB\(d+c) + 2961 LUT4 EF00 ((/ab\)+c)D + 2962 LUT4 3500 D(c?b:a) + 2963 LUT4 F088 D?AB:C + 2964 LUT4 0777 /AB\(d+c) + 2965 LUT4 0007 cd/AB\ + 2966 LUT4 4000 aBCD + 2967 LUT4 1000 abCD + 2968 LUT3 CA C?A:B + 2969 LUT3 35 c?b:a + 2970 LUT4 5300 D(C?b:a) + 2971 LUT3 35 c?b:a + 2972 LUT3 35 c?b:a + 2973 LUT4 5300 D(C?b:a) + 2974 LUT3 35 c?b:a + 2975 LUT3 35 c?b:a + 2976 LUT3 53 C?b:a + 2977 LUT4 5300 D(C?b:a) + 2978 LUT3 35 c?b:a + 2979 LUT4 5300 D(C?b:a) + 2980 LUT3 35 c?b:a + 2981 LUT4 8F00 ((AB)+c)D + 2982 LUT4 0777 /AB\(d+c) + 2983 LUT4 0007 cd/AB\ + 2984 LUT3 80 ABC + 2985 LUT3 80 ABC + 2986 LUT4 0777 /AB\(d+c) + 2987 LUT3 C5 C?a:B + 2988 LUT2 4 aB + 2989 LUT3 35 c?b:a + 2990 LUT2 8 AB + 2991 LUT2 8 AB + 2992 LUT4 0D00 cD/Ab\ + 2993 LUT4 8F00 ((AB)+c)D + 2994 LUT4 0777 /AB\(d+c) + 2995 LUT4 0007 cd/AB\ + 2996 LUT3 80 ABC + 2997 LUT3 80 ABC + 2998 LUT4 B0BB /aB\(d+C) + 2999 LUT4 BF00 ((/aB\)+c)D + 3000 LUT4 0777 /AB\(d+c) + 3001 LUT2 8 AB + 3002 LUT4 0777 /AB\(d+c) + 3003 LUT4 0777 /AB\(d+c) + 3004 LUT2 4 aB + 3005 LUT3 5C c?a:B + 3006 LUT2 4 aB + 3007 LUT2 B /aB\ + 3008 LUT4 AC00 D(c?A:B) + 3009 LUT4 007F ((/AB\)+c)d + 3010 LUT2 8 AB + 3011 LUT3 0B c/aB\ + 3012 LUT4 7007 (c^D)/AB\ + 3013 LUT4 F0BB D?/aB\:C + 3014 LUT3 3A c?b:A + 3015 LUT3 CA C?A:B + 3016 LUT3 80 ABC + 3017 LUT3 35 c?b:a + 3018 LUT3 80 ABC + 3019 LUT3 35 c?b:a + 3020 LUT3 80 ABC + 3021 LUT4 0EEE /ab\(d+c) + 3022 LUT3 8F (AB)+c + 3023 LUT4 0700 cD/AB\ + 3024 LUT3 70 C/AB\ + 3025 LUT4 00BF ((/aB\)+c)d + 3026 LUT2 4 aB + 3027 LUT4 1000 abCD + 3028 LUT2 8 AB + 3029 LUT4 8000 ABCD + 3030 LUT4 8000 ABCD + 3031 LUT4 0777 /AB\(d+c) + 3032 LUT4 0777 /AB\(d+c) + 3033 LUT4 0777 /AB\(d+c) + 3034 LUT4 0777 /AB\(d+c) + 3035 LUT3 70 C/AB\ + 3036 LUT4 0777 /AB\(d+c) + 3037 LUT4 0777 /AB\(d+c) + 3038 LUT4 0777 /AB\(d+c) + 3039 LUT4 8000 ABCD + 3040 LUT4 8000 ABCD + 3041 LUT4 0777 /AB\(d+c) + 3042 LUT4 0777 /AB\(d+c) + 3043 LUT4 0777 /AB\(d+c) + 3044 LUT4 0777 /AB\(d+c) + 3045 LUT4 0700 cD/AB\ + 3046 LUT4 0777 /AB\(d+c) + 3047 LUT2 8 AB + 3048 LUT4 0777 /AB\(d+c) + 3049 LUT4 0777 /AB\(d+c) + 3050 LUT3 CA C?A:B + 3051 LUT3 8F (AB)+c + 3052 LUT4 F3F5 DC?a:b:1:1 + 3053 LUT2 6 A^B + 3054 LUT2 8 AB + 3055 LUT4 B0BB /aB\(d+C) + 3056 LUT4 8000 ABCD + 3057 LUT4 7000 CD/AB\ + 3058 LUT4 7000 CD/AB\ + 3059 LUT4 0700 cD/AB\ + 3060 LUT2 8 AB + 3061 LUT4 0777 /AB\(d+c) + 3062 LUT4 0777 /AB\(d+c) + 3063 LUT3 70 C/AB\ + 3064 LUT4 0777 /AB\(d+c) + 3065 LUT4 8000 ABCD + 3066 LUT4 7000 CD/AB\ + 3067 LUT4 0777 /AB\(d+c) + 3068 LUT4 0777 /AB\(d+c) + 3069 LUT3 70 C/AB\ + 3070 LUT4 0777 /AB\(d+c) + 3071 LUT4 0777 /AB\(d+c) + 3072 LUT4 0777 /AB\(d+c) + 3073 LUT4 0700 cD/AB\ + 3074 LUT2 8 AB + 3075 LUT4 0777 /AB\(d+c) + 3076 LUT4 0700 cD/AB\ + 3077 LUT2 8 AB + 3078 LUT4 0777 /AB\(d+c) + 3079 LUT3 70 C/AB\ + 3080 LUT3 70 C/AB\ + 3081 LUT4 0BBB /aB\(d+c) + 3082 LUT4 440F D?c:aB + 3083 LUT4 F3F5 DC?a:b:1:1 + 3084 LUT3 07 c/AB\ + 3085 LUT3 CA C?A:B + 3086 LUT3 AC c?A:B + 3087 LUT2 8 AB + 3088 LUT4 0777 /AB\(d+c) + 3089 LUT4 0777 /AB\(d+c) + 3090 LUT2 8 AB + 3091 LUT4 0777 /AB\(d+c) + 3092 LUT4 0777 /AB\(d+c) + 3093 LUT4 F088 D?AB:C + 3094 LUT2 8 AB + 3095 LUT4 0777 /AB\(d+c) + 3096 LUT4 0777 /AB\(d+c) + 3097 LUT4 0777 /AB\(d+c) + 3098 LUT4 0777 /AB\(d+c) + 3099 LUT4 EF00 ((/ab\)+c)D + 3100 LUT4 5300 D(C?b:a) + 3101 LUT4 8F00 ((AB)+c)D + 3102 LUT4 0777 /AB\(d+c) + 3103 LUT4 0007 cd/AB\ + 3104 LUT3 80 ABC + 3105 LUT3 80 ABC + 3106 LUT4 0777 /AB\(d+c) + 3107 LUT4 440F D?c:aB + 3108 LUT4 5300 D(C?b:a) + 3109 LUT3 35 c?b:a + 3110 LUT3 35 c?b:a + 3111 LUT3 35 c?b:a + 3112 LUT4 3500 D(c?b:a) + 3113 LUT3 35 c?b:a + 3114 LUT3 35 c?b:a + 3115 LUT4 5300 D(C?b:a) + 3116 LUT3 35 c?b:a + 3117 LUT2 8 AB + 3118 LUT2 8 AB + 3119 LUT4 3500 D(c?b:a) + 3120 LUT3 35 c?b:a + 3121 LUT4 F088 D?AB:C + 3122 LUT4 0777 /AB\(d+c) + 3123 LUT4 0007 cd/AB\ + 3124 LUT4 1000 abCD + 3125 LUT4 1000 abCD + 3126 LUT3 CA C?A:B + 3127 LUT3 35 c?b:a + 3128 LUT3 53 C?b:a + 3129 LUT4 0D00 cD/Ab\ + 3130 LUT4 8F00 ((AB)+c)D + 3131 LUT4 0777 /AB\(d+c) + 3132 LUT4 0007 cd/AB\ + 3133 LUT3 80 ABC + 3134 LUT3 80 ABC + 3135 LUT4 B0BB /aB\(d+C) + 3136 LUT4 BF00 ((/aB\)+c)D + 3137 LUT4 0777 /AB\(d+c) + 3138 LUT2 8 AB + 3139 LUT4 0777 /AB\(d+c) + 3140 LUT4 0777 /AB\(d+c) + 3141 LUT3 5C c?a:B + 3142 LUT2 4 aB + 3143 LUT3 4F (aB)+c + 3144 LUT3 5C c?a:B + 3145 LUT3 35 c?b:a + 3146 LUT3 80 ABC + 3147 LUT3 CA C?A:B + 3148 LUT3 80 ABC + 3149 LUT3 0D c/Ab\ + 3150 LUT3 35 c?b:a + 3151 LUT3 80 ABC + 3152 LUT4 CA00 D(C?A:B) + 3153 LUT2 8 AB + 3154 LUT4 F044 D?aB:C + 3155 LUT3 07 c/AB\ + 3156 LUT3 8F (AB)+c + 3157 LUT4 0700 cD/AB\ + 3158 LUT3 70 C/AB\ + 3159 LUT4 00BF ((/aB\)+c)d + 3160 LUT2 4 aB + 3161 LUT4 1000 abCD + 3162 LUT4 8000 ABCD + 3163 LUT4 7000 CD/AB\ + 3164 LUT4 0700 cD/AB\ + 3165 LUT2 8 AB + 3166 LUT4 0777 /AB\(d+c) + 3167 LUT4 0777 /AB\(d+c) + 3168 LUT4 8000 ABCD + 3169 LUT4 0777 /AB\(d+c) + 3170 LUT4 0777 /AB\(d+c) + 3171 LUT4 0777 /AB\(d+c) + 3172 LUT4 0777 /AB\(d+c) + 3173 LUT4 8000 ABCD + 3174 LUT4 0777 /AB\(d+c) + 3175 LUT4 0777 /AB\(d+c) + 3176 LUT4 0777 /AB\(d+c) + 3177 LUT4 0777 /AB\(d+c) + 3178 LUT4 8000 ABCD + 3179 LUT4 0777 /AB\(d+c) + 3180 LUT4 0777 /AB\(d+c) + 3181 LUT4 0777 /AB\(d+c) + 3182 LUT4 0777 /AB\(d+c) + 3183 LUT3 CA C?A:B + 3184 LUT3 8F (AB)+c + 3185 LUT4 F53F DC?1:a:b:1 + 3186 LUT4 0100 abcD + 3187 LUT2 9 a^B + 3188 LUT4 0D00 cD/Ab\ + 3189 LUT4 7F00 ((/AB\)+c)D + 3190 LUT4 8000 ABCD + 3191 LUT3 70 C/AB\ + 3192 LUT4 0777 /AB\(d+c) + 3193 LUT4 8000 ABCD + 3194 LUT4 0777 /AB\(d+c) + 3195 LUT4 0777 /AB\(d+c) + 3196 LUT4 0777 /AB\(d+c) + 3197 LUT4 0777 /AB\(d+c) + 3198 LUT4 0777 /AB\(d+c) + 3199 LUT4 0777 /AB\(d+c) + 3200 LUT4 8000 ABCD + 3201 LUT4 0777 /AB\(d+c) + 3202 LUT4 0777 /AB\(d+c) + 3203 LUT4 0777 /AB\(d+c) + 3204 LUT4 0777 /AB\(d+c) + 3205 LUT4 8000 ABCD + 3206 LUT4 0777 /AB\(d+c) + 3207 LUT4 0777 /AB\(d+c) + 3208 LUT4 0777 /AB\(d+c) + 3209 LUT4 0777 /AB\(d+c) + 3210 LUT3 D0 C/Ab\ + 3211 LUT3 B0 C/aB\ + 3212 LUT4 0BBB /aB\(d+c) + 3213 LUT4 440F D?c:aB + 3214 LUT4 F3F5 DC?a:b:1:1 + 3215 LUT4 00EF ((/ab\)+c)d + 3216 LUT4 AC00 D(c?A:B) + 3217 LUT2 8 AB + 3218 LUT4 0777 /AB\(d+c) + 3219 LUT4 0777 /AB\(d+c) + 3220 LUT4 0C0A DC?A:B:0:0 + 3221 LUT2 1 ab + 3222 LUT4 EF00 ((/ab\)+c)D + 3223 LUT4 5300 D(C?b:a) + 3224 LUT4 8F00 ((AB)+c)D + 3225 LUT4 0777 /AB\(d+c) + 3226 LUT4 0007 cd/AB\ + 3227 LUT2 8 AB + 3228 LUT3 80 ABC + 3229 LUT3 80 ABC + 3230 LUT4 0777 /AB\(d+c) + 3231 LUT3 CA C?A:B + 3232 LUT2 4 aB + 3233 LUT3 4F (aB)+c + 3234 LUT3 C5 C?a:B + 3235 LUT3 35 c?b:a + 3236 LUT4 B0BB /aB\(d+C) + 3237 LUT4 F8FF (AB)+C+d + 3238 LUT4 1F00 ((ab)+c)D + 3239 LUT3 B0 C/aB\ + 3240 LUT4 00BF ((/aB\)+c)d + 3241 LUT2 4 aB + 3242 LUT4 1000 abCD + 3243 LUT4 0700 cD/AB\ + 3244 LUT4 0777 /AB\(d+c) + 3245 LUT2 8 AB + 3246 LUT4 0777 /AB\(d+c) + 3247 LUT4 0777 /AB\(d+c) + 3248 LUT4 0777 /AB\(d+c) + 3249 LUT4 0777 /AB\(d+c) + 3250 LUT4 8000 ABCD + 3251 LUT4 0700 cD/AB\ + 3252 LUT4 0777 /AB\(d+c) + 3253 LUT2 8 AB + 3254 LUT4 8000 ABCD + 3255 LUT4 0777 /AB\(d+c) + 3256 LUT4 0777 /AB\(d+c) + 3257 LUT4 0777 /AB\(d+c) + 3258 LUT4 0777 /AB\(d+c) + 3259 LUT4 0777 /AB\(d+c) + 3260 LUT4 0777 /AB\(d+c) + 3261 LUT3 CA C?A:B + 3262 LUT3 8F (AB)+c + 3263 LUT4 F3F5 DC?a:b:1:1 + 3264 LUT2 9 a^B + 3265 LUT3 B0 C/aB\ + 3266 LUT3 D0 C/Ab\ + 3267 LUT3 B0 C/aB\ + 3268 LUT4 0BBB /aB\(d+c) + 3269 LUT4 440F D?c:aB + 3270 LUT4 F3F5 DC?a:b:1:1 + 3271 LUT2 1 ab + 3272 LUT4 0100 abcD + 3273 LUT2 8 AB + 3274 LUT4 0777 /AB\(d+c) + 3275 LUT4 0777 /AB\(d+c) + 3276 LUT2 8 AB + 3277 LUT4 0777 /AB\(d+c) + 3278 LUT4 0777 /AB\(d+c) + 3279 LUT4 7000 CD/AB\ + 3280 LUT3 70 C/AB\ + 3281 LUT4 0777 /AB\(d+c) + 3282 LUT2 4 aB + 3283 LUT2 1 ab + 3284 LUT4 FE00 ((/ab\)+C)D + 3285 LUT2 4 aB + 3286 LUT4 EF00 ((/ab\)+c)D + 3287 LUT4 0503 DC?b:a:0:0 + 3288 LUT4 8F00 ((AB)+c)D + 3289 LUT4 0777 /AB\(d+c) + 3290 LUT4 0007 cd/AB\ + 3291 LUT3 80 ABC + 3292 LUT3 80 ABC + 3293 LUT4 0777 /AB\(d+c) + 3294 LUT4 0E00 cD/ab\ + 3295 LUT4 8F00 ((AB)+c)D + 3296 LUT4 0777 /AB\(d+c) + 3297 LUT2 8 AB + 3298 LUT4 0700 cD/AB\ + 3299 LUT4 8000 ABCD + 3300 LUT4 8000 ABCD + 3301 LUT2 8 AB + 3302 LUT2 8 AB + 3303 LUT4 8000 ABCD + 3304 LUT2 8 AB + 3305 LUT4 0777 /AB\(d+c) + 3306 LUT4 8000 ABCD + 3307 LUT2 8 AB + 3308 LUT4 8000 ABCD + 3309 LUT2 8 AB + 3310 LUT2 8 AB + 3311 LUT4 0007 cd/AB\ + 3312 LUT2 8 AB + 3313 LUT4 0700 cD/AB\ + 3314 LUT4 0777 /AB\(d+c) + 3315 LUT3 80 ABC + 3316 LUT4 0700 cD/AB\ + 3317 LUT4 0777 /AB\(d+c) + 3318 LUT3 80 ABC + 3319 LUT4 0700 cD/AB\ + 3320 LUT4 0777 /AB\(d+c) + 3321 LUT2 1 ab + 3322 LUT3 80 ABC + 3323 LUT3 80 ABC + 3324 LUT4 0777 /AB\(d+c) + 3325 LUT2 1 ab + 3326 LUT2 4 aB + 3327 LUT4 BF00 ((/aB\)+c)D + 3328 LUT4 0777 /AB\(d+c) + 3329 LUT2 8 AB + 3330 LUT4 0700 cD/AB\ + 3331 LUT4 8000 ABCD + 3332 LUT4 8000 ABCD + 3333 LUT3 80 ABC + 3334 LUT4 8000 ABCD + 3335 LUT3 80 ABC + 3336 LUT4 0777 /AB\(d+c) + 3337 LUT4 8000 ABCD + 3338 LUT3 80 ABC + 3339 LUT4 8000 ABCD + 3340 LUT3 80 ABC + 3341 LUT3 80 ABC + 3342 LUT2 8 AB + 3343 LUT2 8 AB + 3344 LUT4 0700 cD/AB\ + 3345 LUT4 0777 /AB\(d+c) + 3346 LUT4 0777 /AB\(d+c) + 3347 LUT2 8 AB + 3348 LUT4 0700 cD/AB\ + 3349 LUT4 0777 /AB\(d+c) + 3350 LUT2 8 AB + 3351 LUT4 0700 cD/AB\ + 3352 LUT4 0777 /AB\(d+c) + 3353 LUT2 1 ab + 3354 LUT4 4000 aBCD + 3355 LUT4 8000 ABCD + 3356 LUT4 0777 /AB\(d+c) + 3357 LUT2 4 aB + 3358 LUT3 1F (ab)+c + 3359 LUT3 C5 C?a:B + 3360 LUT3 53 C?b:a + 3361 LUT3 0D c/Ab\ + 3362 LUT3 35 c?b:a + 3363 LUT3 40 aBC + 3364 LUT4 CA00 D(C?A:B) + 3365 LUT2 8 AB + 3366 LUT2 8 AB + 3367 LUT2 4 aB + 3368 LUT4 0007 cd/AB\ + 3369 LUT2 4 aB + 3370 LUT2 4 aB + 3371 LUT2 4 aB + 3372 LUT4 8000 ABCD + 3373 LUT4 8000 ABCD + 3374 LUT4 0777 /AB\(d+c) + 3375 LUT4 0777 /AB\(d+c) + 3376 LUT4 0777 /AB\(d+c) + 3377 LUT4 0777 /AB\(d+c) + 3378 LUT4 8000 ABCD + 3379 LUT4 0777 /AB\(d+c) + 3380 LUT4 0777 /AB\(d+c) + 3381 LUT4 0777 /AB\(d+c) + 3382 LUT4 0777 /AB\(d+c) + 3383 LUT4 7000 CD/AB\ + 3384 LUT4 0700 cD/AB\ + 3385 LUT4 0777 /AB\(d+c) + 3386 LUT2 8 AB + 3387 LUT4 0777 /AB\(d+c) + 3388 LUT4 8000 ABCD + 3389 LUT4 0777 /AB\(d+c) + 3390 LUT4 0777 /AB\(d+c) + 3391 LUT4 0777 /AB\(d+c) + 3392 LUT4 0777 /AB\(d+c) + 3393 LUT4 FEFF /ab\+C+d + 3394 LUT4 FE00 ((/ab\)+C)D + 3395 LUT3 B0 C/aB\ + 3396 LUT4 0BBB /aB\(d+c) + 3397 LUT4 1000 abCD + 3398 LUT4 8000 ABCD + 3399 LUT4 7000 CD/AB\ + 3400 LUT4 0700 cD/AB\ + 3401 LUT2 8 AB + 3402 LUT4 0777 /AB\(d+c) + 3403 LUT4 0777 /AB\(d+c) + 3404 LUT4 8000 ABCD + 3405 LUT4 0777 /AB\(d+c) + 3406 LUT4 0777 /AB\(d+c) + 3407 LUT4 0777 /AB\(d+c) + 3408 LUT4 0777 /AB\(d+c) + 3409 LUT4 8000 ABCD + 3410 LUT4 0777 /AB\(d+c) + 3411 LUT4 0777 /AB\(d+c) + 3412 LUT4 0777 /AB\(d+c) + 3413 LUT4 0777 /AB\(d+c) + 3414 LUT4 8000 ABCD + 3415 LUT4 0777 /AB\(d+c) + 3416 LUT4 0777 /AB\(d+c) + 3417 LUT4 0777 /AB\(d+c) + 3418 LUT4 0777 /AB\(d+c) + 3419 LUT2 8 AB + 3420 LUT3 CA C?A:B + 3421 LUT3 8F (AB)+c + 3422 LUT4 F3F5 DC?a:b:1:1 + 3423 LUT2 9 a^B + 3424 LUT2 4 aB + 3425 LUT3 D0 C/Ab\ + 3426 LUT3 B0 C/aB\ + 3427 LUT4 0BBB /aB\(d+c) + 3428 LUT4 440F D?c:aB + 3429 LUT4 F3F5 DC?a:b:1:1 + 3430 LUT2 1 ab + 3431 LUT4 3A00 D(c?b:A) + 3432 LUT3 AC c?A:B + 3433 LUT2 8 AB + 3434 LUT4 0777 /AB\(d+c) + 3435 LUT4 0777 /AB\(d+c) + 3436 LUT3 35 c?b:a + 3437 LUT2 1 ab + 3438 LUT4 EF00 ((/ab\)+c)D + 3439 LUT4 5300 D(C?b:a) + 3440 LUT4 8F00 ((AB)+c)D + 3441 LUT4 0777 /AB\(d+c) + 3442 LUT4 0007 cd/AB\ + 3443 LUT3 80 ABC + 3444 LUT3 80 ABC + 3445 LUT4 0777 /AB\(d+c) + 3446 LUT3 CA C?A:B + 3447 LUT2 4 aB + 3448 LUT3 4F (aB)+c + 3449 LUT3 C5 C?a:B + 3450 LUT3 35 c?b:a + 3451 LUT4 FCFA DC?A:B:1:1 + 3452 LUT4 4F00 ((aB)+c)D + 3453 LUT2 8 AB + 3454 LUT4 8000 ABCD + 3455 LUT3 80 ABC + 3456 LUT4 0700 cD/AB\ + 3457 LUT4 0777 /AB\(d+c) + 3458 LUT2 8 AB + 3459 LUT4 0777 /AB\(d+c) + 3460 LUT4 0777 /AB\(d+c) + 3461 LUT4 0777 /AB\(d+c) + 3462 LUT4 0777 /AB\(d+c) + 3463 LUT3 70 C/AB\ + 3464 LUT4 0777 /AB\(d+c) + 3465 LUT4 8000 ABCD + 3466 LUT4 8000 ABCD + 3467 LUT4 0777 /AB\(d+c) + 3468 LUT4 0777 /AB\(d+c) + 3469 LUT4 0777 /AB\(d+c) + 3470 LUT4 0777 /AB\(d+c) + 3471 LUT4 0777 /AB\(d+c) + 3472 LUT4 0777 /AB\(d+c) + 3473 LUT4 0700 cD/AB\ + 3474 LUT4 0777 /AB\(d+c) + 3475 LUT2 8 AB + 3476 LUT3 0B c/aB\ + 3477 LUT4 F8FF (AB)+C+d + 3478 LUT4 1F00 ((ab)+c)D + 3479 LUT3 B0 C/aB\ + 3480 LUT4 00BF ((/aB\)+c)d + 3481 LUT2 4 aB + 3482 LUT4 1000 abCD + 3483 LUT2 8 AB + 3484 LUT4 8000 ABCD + 3485 LUT3 80 ABC + 3486 LUT4 0700 cD/AB\ + 3487 LUT2 8 AB + 3488 LUT4 0777 /AB\(d+c) + 3489 LUT4 0777 /AB\(d+c) + 3490 LUT4 0777 /AB\(d+c) + 3491 LUT4 0700 cD/AB\ + 3492 LUT2 8 AB + 3493 LUT4 0777 /AB\(d+c) + 3494 LUT4 0777 /AB\(d+c) + 3495 LUT4 0777 /AB\(d+c) + 3496 LUT4 8000 ABCD + 3497 LUT4 8000 ABCD + 3498 LUT4 0777 /AB\(d+c) + 3499 LUT4 0777 /AB\(d+c) + 3500 LUT4 0777 /AB\(d+c) + 3501 LUT4 0777 /AB\(d+c) + 3502 LUT3 70 C/AB\ + 3503 LUT4 0777 /AB\(d+c) + 3504 LUT4 0777 /AB\(d+c) + 3505 LUT4 0777 /AB\(d+c) + 3506 LUT3 CA C?A:B + 3507 LUT3 8F (AB)+c + 3508 LUT4 F53F DC?1:a:b:1 + 3509 LUT2 6 A^B + 3510 LUT4 B000 CD/aB\ + 3511 LUT3 D0 C/Ab\ + 3512 LUT3 B0 C/aB\ + 3513 LUT4 0BBB /aB\(d+c) + 3514 LUT4 440F D?c:aB + 3515 LUT4 F3F5 DC?a:b:1:1 + 3516 LUT3 AC c?A:B + 3517 LUT2 8 AB + 3518 LUT4 0777 /AB\(d+c) + 3519 LUT4 0777 /AB\(d+c) + 3520 LUT2 1 ab + 3521 LUT4 EF00 ((/ab\)+c)D + 3522 LUT4 5300 D(C?b:a) + 3523 LUT4 8F00 ((AB)+c)D + 3524 LUT4 0777 /AB\(d+c) + 3525 LUT4 0007 cd/AB\ + 3526 LUT3 80 ABC + 3527 LUT3 80 ABC + 3528 LUT4 0777 /AB\(d+c) + 3529 LUT3 CA C?A:B + 3530 LUT2 4 aB + 3531 LUT3 4F (aB)+c + 3532 LUT3 C5 C?a:B + 3533 LUT3 35 c?b:a + 3534 LUT4 FCFA DC?A:B:1:1 + 3535 LUT4 8000 ABCD + 3536 LUT4 8000 ABCD + 3537 LUT4 7000 CD/AB\ + 3538 LUT3 70 C/AB\ + 3539 LUT4 0777 /AB\(d+c) + 3540 LUT4 0777 /AB\(d+c) + 3541 LUT4 7000 CD/AB\ + 3542 LUT4 0777 /AB\(d+c) + 3543 LUT4 0700 cD/AB\ + 3544 LUT2 8 AB + 3545 LUT4 0777 /AB\(d+c) + 3546 LUT4 0777 /AB\(d+c) + 3547 LUT4 0777 /AB\(d+c) + 3548 LUT4 7000 CD/AB\ + 3549 LUT4 7000 CD/AB\ + 3550 LUT4 0700 cD/AB\ + 3551 LUT4 0777 /AB\(d+c) + 3552 LUT2 8 AB + 3553 LUT4 0777 /AB\(d+c) + 3554 LUT4 0777 /AB\(d+c) + 3555 LUT4 0777 /AB\(d+c) + 3556 LUT4 0777 /AB\(d+c) + 3557 LUT4 00BF ((/aB\)+c)d + 3558 LUT4 F8FF (AB)+C+d + 3559 LUT4 1F00 ((ab)+c)D + 3560 LUT3 B0 C/aB\ + 3561 LUT4 00BF ((/aB\)+c)d + 3562 LUT2 4 aB + 3563 LUT4 1000 abCD + 3564 LUT4 8000 ABCD + 3565 LUT4 8000 ABCD + 3566 LUT4 0777 /AB\(d+c) + 3567 LUT4 0777 /AB\(d+c) + 3568 LUT4 0777 /AB\(d+c) + 3569 LUT4 0777 /AB\(d+c) + 3570 LUT4 4000 aBCD + 3571 LUT2 8 AB + 3572 LUT4 0777 /AB\(d+c) + 3573 LUT4 0777 /AB\(d+c) + 3574 LUT4 0777 /AB\(d+c) + 3575 LUT4 8000 ABCD + 3576 LUT4 0777 /AB\(d+c) + 3577 LUT4 0777 /AB\(d+c) + 3578 LUT4 0777 /AB\(d+c) + 3579 LUT4 0777 /AB\(d+c) + 3580 LUT4 8000 ABCD + 3581 LUT4 0777 /AB\(d+c) + 3582 LUT4 0777 /AB\(d+c) + 3583 LUT4 0777 /AB\(d+c) + 3584 LUT4 0777 /AB\(d+c) + 3585 LUT3 CA C?A:B + 3586 LUT3 8F (AB)+c + 3587 LUT4 F3F5 DC?a:b:1:1 + 3588 LUT4 4000 aBCD + 3589 LUT2 6 A^B + 3590 LUT4 0D00 cD/Ab\ + 3591 LUT4 7F00 ((/AB\)+c)D + 3592 LUT4 8000 ABCD + 3593 LUT4 7000 CD/AB\ + 3594 LUT4 0777 /AB\(d+c) + 3595 LUT4 0777 /AB\(d+c) + 3596 LUT4 7000 CD/AB\ + 3597 LUT3 70 C/AB\ + 3598 LUT4 0777 /AB\(d+c) + 3599 LUT4 0777 /AB\(d+c) + 3600 LUT4 7000 CD/AB\ + 3601 LUT4 0777 /AB\(d+c) + 3602 LUT4 0777 /AB\(d+c) + 3603 LUT3 70 C/AB\ + 3604 LUT4 0777 /AB\(d+c) + 3605 LUT4 7000 CD/AB\ + 3606 LUT4 0777 /AB\(d+c) + 3607 LUT4 0777 /AB\(d+c) + 3608 LUT4 4000 aBCD + 3609 LUT2 8 AB + 3610 LUT4 0777 /AB\(d+c) + 3611 LUT4 0777 /AB\(d+c) + 3612 LUT4 0777 /AB\(d+c) + 3613 LUT3 D0 C/Ab\ + 3614 LUT3 B0 C/aB\ + 3615 LUT4 0BBB /aB\(d+c) + 3616 LUT4 440F D?c:aB + 3617 LUT4 F3F5 DC?a:b:1:1 + 3618 LUT3 07 c/AB\ + 3619 LUT3 3A c?b:A + 3620 LUT3 AC c?A:B + 3621 LUT2 8 AB + 3622 LUT4 0777 /AB\(d+c) + 3623 LUT4 0777 /AB\(d+c) + 3624 LUT3 35 c?b:a + 3625 LUT2 1 ab + 3626 LUT4 EF00 ((/ab\)+c)D + 3627 LUT4 5300 D(C?b:a) + 3628 LUT4 8F00 ((AB)+c)D + 3629 LUT4 0777 /AB\(d+c) + 3630 LUT4 0007 cd/AB\ + 3631 LUT3 80 ABC + 3632 LUT3 80 ABC + 3633 LUT4 0777 /AB\(d+c) + 3634 LUT3 CA C?A:B + 3635 LUT2 4 aB + 3636 LUT3 4F (aB)+c + 3637 LUT3 C5 C?a:B + 3638 LUT3 53 C?b:a + 3639 LUT4 FCFA DC?A:B:1:1 + 3640 LUT4 F8FF (AB)+C+d + 3641 LUT4 1F00 ((ab)+c)D + 3642 LUT3 B0 C/aB\ + 3643 LUT4 00BF ((/aB\)+c)d + 3644 LUT2 4 aB + 3645 LUT4 1000 abCD + 3646 LUT3 80 ABC + 3647 LUT4 8000 ABCD + 3648 LUT4 8000 ABCD + 3649 LUT4 0777 /AB\(d+c) + 3650 LUT4 0777 /AB\(d+c) + 3651 LUT4 0777 /AB\(d+c) + 3652 LUT4 0777 /AB\(d+c) + 3653 LUT3 70 C/AB\ + 3654 LUT4 0777 /AB\(d+c) + 3655 LUT4 0777 /AB\(d+c) + 3656 LUT4 0777 /AB\(d+c) + 3657 LUT4 8000 ABCD + 3658 LUT4 0777 /AB\(d+c) + 3659 LUT4 0777 /AB\(d+c) + 3660 LUT4 0777 /AB\(d+c) + 3661 LUT4 0777 /AB\(d+c) + 3662 LUT4 8000 ABCD + 3663 LUT4 0777 /AB\(d+c) + 3664 LUT4 0777 /AB\(d+c) + 3665 LUT4 0777 /AB\(d+c) + 3666 LUT4 0777 /AB\(d+c) + 3667 LUT3 CA C?A:B + 3668 LUT3 8F (AB)+c + 3669 LUT4 F53F DC?1:a:b:1 + 3670 LUT2 9 a^B + 3671 LUT2 4 aB + 3672 LUT3 D0 C/Ab\ + 3673 LUT3 B0 C/aB\ + 3674 LUT4 0BBB /aB\(d+c) + 3675 LUT4 440F D?c:aB + 3676 LUT4 F3F5 DC?a:b:1:1 + 3677 LUT3 B0 C/aB\ + 3678 LUT4 0B00 cD/aB\ + 3679 LUT4 AC00 D(c?A:B) + 3680 LUT2 4 aB + 3681 LUT4 FE00 ((/ab\)+C)D + 3682 LUT4 0305 DC?a:b:0:0 + 3683 LUT3 53 C?b:a + 3684 LUT2 4 aB + 3685 LUT3 70 C/AB\ + 3686 LUT4 770F D?c:/AB\ + 3687 LUT4 4F00 ((aB)+c)D + 3688 LUT3 07 c/AB\ + 3689 LUT4 8000 ABCD + 3690 LUT4 7000 CD/AB\ + 3691 LUT4 0700 cD/AB\ + 3692 LUT4 0777 /AB\(d+c) + 3693 LUT2 8 AB + 3694 LUT4 0777 /AB\(d+c) + 3695 LUT4 8000 ABCD + 3696 LUT4 0777 /AB\(d+c) + 3697 LUT4 0777 /AB\(d+c) + 3698 LUT4 0777 /AB\(d+c) + 3699 LUT4 0777 /AB\(d+c) + 3700 LUT4 8000 ABCD + 3701 LUT4 0777 /AB\(d+c) + 3702 LUT4 0777 /AB\(d+c) + 3703 LUT4 0777 /AB\(d+c) + 3704 LUT4 0777 /AB\(d+c) + 3705 LUT4 8000 ABCD + 3706 LUT4 0777 /AB\(d+c) + 3707 LUT4 0777 /AB\(d+c) + 3708 LUT4 0777 /AB\(d+c) + 3709 LUT4 0777 /AB\(d+c) + 3710 LUT4 FEFF /ab\+C+d + 3711 LUT4 FE00 ((/ab\)+C)D + 3712 LUT3 B0 C/aB\ + 3713 LUT4 0BBB /aB\(d+c) + 3714 LUT4 1000 abCD + 3715 LUT4 8000 ABCD + 3716 LUT4 7000 CD/AB\ + 3717 LUT4 0700 cD/AB\ + 3718 LUT2 8 AB + 3719 LUT4 0777 /AB\(d+c) + 3720 LUT4 0777 /AB\(d+c) + 3721 LUT4 8000 ABCD + 3722 LUT4 0777 /AB\(d+c) + 3723 LUT4 0777 /AB\(d+c) + 3724 LUT4 0777 /AB\(d+c) + 3725 LUT4 0777 /AB\(d+c) + 3726 LUT4 8000 ABCD + 3727 LUT4 0777 /AB\(d+c) + 3728 LUT4 0777 /AB\(d+c) + 3729 LUT4 0777 /AB\(d+c) + 3730 LUT4 0777 /AB\(d+c) + 3731 LUT4 8000 ABCD + 3732 LUT4 0777 /AB\(d+c) + 3733 LUT4 0777 /AB\(d+c) + 3734 LUT4 0777 /AB\(d+c) + 3735 LUT4 0777 /AB\(d+c) + 3736 LUT2 8 AB + 3737 LUT3 CA C?A:B + 3738 LUT3 8F (AB)+c + 3739 LUT4 F53F DC?1:a:b:1 + 3740 LUT2 6 A^B + 3741 LUT4 0B00 cD/aB\ + 3742 LUT3 D0 C/Ab\ + 3743 LUT3 B0 C/aB\ + 3744 LUT4 0BBB /aB\(d+c) + 3745 LUT4 440F D?c:aB + 3746 LUT4 F3F5 DC?a:b:1:1 + 3747 LUT3 D0 C/Ab\ + 3748 LUT4 F400 ((aB)+C)D + 3749 LUT4 7000 CD/AB\ + 3750 LUT4 0007 cd/AB\ + 3751 LUT2 8 AB + 3752 LUT2 8 AB + 3753 LUT2 8 AB + 3754 LUT4 0777 /AB\(d+c) + 3755 LUT4 0777 /AB\(d+c) + 3756 LUT4 0B00 cD/aB\ + 3757 LUT3 01 abc + 3758 LUT4 EF00 ((/ab\)+c)D + 3759 LUT4 0503 DC?b:a:0:0 + 3760 LUT4 0E00 cD/ab\ + 3761 LUT4 8F00 ((AB)+c)D + 3762 LUT4 0777 /AB\(d+c) + 3763 LUT2 8 AB + 3764 LUT4 0007 cd/AB\ + 3765 LUT3 80 ABC + 3766 LUT3 80 ABC + 3767 LUT4 0777 /AB\(d+c) + 3768 LUT2 1 ab + 3769 LUT2 4 aB + 3770 LUT4 BF00 ((/aB\)+c)D + 3771 LUT4 0777 /AB\(d+c) + 3772 LUT2 8 AB + 3773 LUT4 0777 /AB\(d+c) + 3774 LUT4 0777 /AB\(d+c) + 3775 LUT2 4 aB + 3776 LUT3 1F (ab)+c + 3777 LUT3 0D c/Ab\ + 3778 LUT4 0F77 D?/AB\:c + 3779 LUT4 CA00 D(C?A:B) + 3780 LUT4 F400 ((aB)+C)D + 3781 LUT3 80 ABC + 3782 LUT4 8000 ABCD + 3783 LUT3 70 C/AB\ + 3784 LUT4 0777 /AB\(d+c) + 3785 LUT4 8000 ABCD + 3786 LUT4 0777 /AB\(d+c) + 3787 LUT4 0777 /AB\(d+c) + 3788 LUT4 0777 /AB\(d+c) + 3789 LUT4 0777 /AB\(d+c) + 3790 LUT4 0777 /AB\(d+c) + 3791 LUT4 0777 /AB\(d+c) + 3792 LUT4 8000 ABCD + 3793 LUT4 0777 /AB\(d+c) + 3794 LUT4 0777 /AB\(d+c) + 3795 LUT4 0777 /AB\(d+c) + 3796 LUT4 0777 /AB\(d+c) + 3797 LUT4 8000 ABCD + 3798 LUT4 0777 /AB\(d+c) + 3799 LUT4 0777 /AB\(d+c) + 3800 LUT4 0777 /AB\(d+c) + 3801 LUT4 0777 /AB\(d+c) + 3802 LUT2 B /aB\ + 3803 LUT4 0D00 cD/Ab\ + 3804 LUT3 B0 C/aB\ + 3805 LUT4 0BBB /aB\(d+c) + 3806 LUT4 1000 abCD + 3807 LUT3 80 ABC + 3808 LUT4 7000 CD/AB\ + 3809 LUT4 0700 cD/AB\ + 3810 LUT2 8 AB + 3811 LUT4 0777 /AB\(d+c) + 3812 LUT4 0777 /AB\(d+c) + 3813 LUT4 8000 ABCD + 3814 LUT4 0700 cD/AB\ + 3815 LUT4 0777 /AB\(d+c) + 3816 LUT2 8 AB + 3817 LUT4 8000 ABCD + 3818 LUT4 0777 /AB\(d+c) + 3819 LUT4 0777 /AB\(d+c) + 3820 LUT4 0777 /AB\(d+c) + 3821 LUT4 0777 /AB\(d+c) + 3822 LUT4 0777 /AB\(d+c) + 3823 LUT4 0777 /AB\(d+c) + 3824 LUT4 8000 ABCD + 3825 LUT4 0777 /AB\(d+c) + 3826 LUT4 0777 /AB\(d+c) + 3827 LUT4 0777 /AB\(d+c) + 3828 LUT4 0777 /AB\(d+c) + 3829 LUT2 8 AB + 3830 LUT3 CA C?A:B + 3831 LUT3 8F (AB)+c + 3832 LUT4 F3F5 DC?a:b:1:1 + 3833 LUT2 6 A^B + 3834 LUT4 0B00 cD/aB\ + 3835 LUT3 D0 C/Ab\ + 3836 LUT3 B0 C/aB\ + 3837 LUT4 0BBB /aB\(d+c) + 3838 LUT4 440F D?c:aB + 3839 LUT4 F3F5 DC?a:b:1:1 + 3840 LUT4 4F00 ((aB)+c)D + 3841 LUT4 0D00 cD/Ab\ + 3842 LUT4 BB0F D?c:/aB\ + 3843 LUT2 8 AB + 3844 LUT4 0777 /AB\(d+c) + 3845 LUT4 0777 /AB\(d+c) + 3846 LUT2 8 AB + 3847 LUT3 70 C/AB\ + 3848 LUT4 0777 /AB\(d+c) + 3849 LUT3 AC c?A:B + 3850 LUT2 8 AB + 3851 LUT4 0777 /AB\(d+c) + 3852 LUT4 0777 /AB\(d+c) + 3853 LUT3 01 abc + 3854 LUT4 EF00 ((/ab\)+c)D + 3855 LUT4 0503 DC?b:a:0:0 + 3856 LUT4 8F00 ((AB)+c)D + 3857 LUT4 0777 /AB\(d+c) + 3858 LUT4 0007 cd/AB\ + 3859 LUT3 80 ABC + 3860 LUT3 80 ABC + 3861 LUT4 0777 /AB\(d+c) + 3862 LUT4 0E00 cD/ab\ + 3863 LUT4 8F00 ((AB)+c)D + 3864 LUT4 0777 /AB\(d+c) + 3865 LUT4 0007 cd/AB\ + 3866 LUT3 80 ABC + 3867 LUT3 80 ABC + 3868 LUT4 0777 /AB\(d+c) + 3869 LUT2 1 ab + 3870 LUT2 4 aB + 3871 LUT4 BF00 ((/aB\)+c)D + 3872 LUT4 0777 /AB\(d+c) + 3873 LUT2 8 AB + 3874 LUT4 0777 /AB\(d+c) + 3875 LUT4 0777 /AB\(d+c) + 3876 LUT2 4 aB + 3877 LUT4 FFF1 (ab)+C+D + 3878 LUT3 C5 C?a:B + 3879 LUT3 35 c?b:a + 3880 LUT2 4 aB + 3881 LUT3 35 c?b:a + 3882 LUT4 CA00 D(C?A:B) + 3883 LUT4 F800 ((AB)+C)D + 3884 LUT4 8000 ABCD + 3885 LUT4 7000 CD/AB\ + 3886 LUT4 0700 cD/AB\ + 3887 LUT4 0777 /AB\(d+c) + 3888 LUT2 8 AB + 3889 LUT4 0777 /AB\(d+c) + 3890 LUT4 0777 /AB\(d+c) + 3891 LUT4 0777 /AB\(d+c) + 3892 LUT4 4000 aBCD + 3893 LUT4 7000 CD/AB\ + 3894 LUT4 0777 /AB\(d+c) + 3895 LUT4 0777 /AB\(d+c) + 3896 LUT3 70 C/AB\ + 3897 LUT4 0777 /AB\(d+c) + 3898 LUT4 0777 /AB\(d+c) + 3899 LUT2 8 AB + 3900 LUT4 7000 CD/AB\ + 3901 LUT4 0777 /AB\(d+c) + 3902 LUT4 0777 /AB\(d+c) + 3903 LUT2 B /aB\ + 3904 LUT4 0D00 cD/Ab\ + 3905 LUT3 B0 C/aB\ + 3906 LUT4 0BBB /aB\(d+c) + 3907 LUT4 1000 abCD + 3908 LUT2 8 AB + 3909 LUT4 8000 ABCD + 3910 LUT4 8000 ABCD + 3911 LUT4 0777 /AB\(d+c) + 3912 LUT4 0777 /AB\(d+c) + 3913 LUT4 0777 /AB\(d+c) + 3914 LUT4 0777 /AB\(d+c) + 3915 LUT3 70 C/AB\ + 3916 LUT4 0777 /AB\(d+c) + 3917 LUT4 0777 /AB\(d+c) + 3918 LUT4 0777 /AB\(d+c) + 3919 LUT4 8000 ABCD + 3920 LUT4 8000 ABCD + 3921 LUT4 0777 /AB\(d+c) + 3922 LUT4 0777 /AB\(d+c) + 3923 LUT4 0777 /AB\(d+c) + 3924 LUT4 0777 /AB\(d+c) + 3925 LUT4 0700 cD/AB\ + 3926 LUT2 8 AB + 3927 LUT4 0777 /AB\(d+c) + 3928 LUT4 0777 /AB\(d+c) + 3929 LUT4 0777 /AB\(d+c) + 3930 LUT2 8 AB + 3931 LUT3 CA C?A:B + 3932 LUT3 8F (AB)+c + 3933 LUT4 F3F5 DC?a:b:1:1 + 3934 LUT4 0100 abcD + 3935 LUT2 9 a^B + 3936 LUT2 8 AB + 3937 LUT4 B0BB /aB\(d+C) + 3938 LUT4 7000 CD/AB\ + 3939 LUT4 7000 CD/AB\ + 3940 LUT4 0777 /AB\(d+c) + 3941 LUT4 0777 /AB\(d+c) + 3942 LUT4 0777 /AB\(d+c) + 3943 LUT4 7000 CD/AB\ + 3944 LUT4 7000 CD/AB\ + 3945 LUT4 0777 /AB\(d+c) + 3946 LUT4 0777 /AB\(d+c) + 3947 LUT4 0777 /AB\(d+c) + 3948 LUT4 7000 CD/AB\ + 3949 LUT3 70 C/AB\ + 3950 LUT4 0777 /AB\(d+c) + 3951 LUT4 0777 /AB\(d+c) + 3952 LUT4 0777 /AB\(d+c) + 3953 LUT4 0777 /AB\(d+c) + 3954 LUT4 0777 /AB\(d+c) + 3955 LUT3 D0 C/Ab\ + 3956 LUT3 B0 C/aB\ + 3957 LUT4 0BBB /aB\(d+c) + 3958 LUT4 440F D?c:aB + 3959 LUT4 F3F5 DC?a:b:1:1 + 3960 LUT4 00EF ((/ab\)+c)d + 3961 LUT4 AC00 D(c?A:B) + 3962 LUT4 0C0A DC?A:B:0:0 + 3963 LUT2 1 ab + 3964 LUT4 EF00 ((/ab\)+c)D + 3965 LUT4 5300 D(C?b:a) + 3966 LUT3 CA C?A:B + 3967 LUT2 4 aB + 3968 LUT3 4F (aB)+c + 3969 LUT4 FCFA DC?A:B:1:1 + 3970 LUT4 F8FF (AB)+C+d + 3971 LUT4 1F00 ((ab)+c)D + 3972 LUT3 B0 C/aB\ + 3973 LUT4 00BF ((/aB\)+c)d + 3974 LUT2 4 aB + 3975 LUT4 1000 abCD + 3976 LUT3 80 ABC + 3977 LUT4 8000 ABCD + 3978 LUT4 8000 ABCD + 3979 LUT4 0777 /AB\(d+c) + 3980 LUT4 0777 /AB\(d+c) + 3981 LUT4 0777 /AB\(d+c) + 3982 LUT4 0777 /AB\(d+c) + 3983 LUT3 70 C/AB\ + 3984 LUT4 0777 /AB\(d+c) + 3985 LUT4 0777 /AB\(d+c) + 3986 LUT4 0777 /AB\(d+c) + 3987 LUT4 8000 ABCD + 3988 LUT4 0777 /AB\(d+c) + 3989 LUT4 0777 /AB\(d+c) + 3990 LUT4 0777 /AB\(d+c) + 3991 LUT4 0777 /AB\(d+c) + 3992 LUT4 8000 ABCD + 3993 LUT4 0777 /AB\(d+c) + 3994 LUT4 0777 /AB\(d+c) + 3995 LUT4 0777 /AB\(d+c) + 3996 LUT4 0777 /AB\(d+c) + 3997 LUT3 CA C?A:B + 3998 LUT3 8F (AB)+c + 3999 LUT4 F3F5 DC?a:b:1:1 + 4000 LUT2 9 a^B + 4001 LUT4 0B00 cD/aB\ + 4002 LUT3 D0 C/Ab\ + 4003 LUT3 B0 C/aB\ + 4004 LUT4 0BBB /aB\(d+c) + 4005 LUT4 440F D?c:aB + 4006 LUT4 F3F5 DC?a:b:1:1 + 4007 LUT4 7000 CD/AB\ + 4008 LUT4 0007 cd/AB\ + 4009 LUT2 8 AB + 4010 LUT2 8 AB + 4011 LUT2 8 AB + 4012 LUT4 0777 /AB\(d+c) + 4013 LUT4 0777 /AB\(d+c) + 4014 LUT2 4 aB + 4015 LUT4 EF00 ((/ab\)+c)D + 4016 LUT4 0503 DC?b:a:0:0 + 4017 LUT4 0E00 cD/ab\ + 4018 LUT4 8F00 ((AB)+c)D + 4019 LUT4 0777 /AB\(d+c) + 4020 LUT4 0007 cd/AB\ + 4021 LUT3 80 ABC + 4022 LUT3 80 ABC + 4023 LUT4 0777 /AB\(d+c) + 4024 LUT2 1 ab + 4025 LUT2 4 aB + 4026 LUT4 BF00 ((/aB\)+c)D + 4027 LUT4 0777 /AB\(d+c) + 4028 LUT2 8 AB + 4029 LUT4 0777 /AB\(d+c) + 4030 LUT4 0777 /AB\(d+c) + 4031 LUT2 4 aB + 4032 LUT3 1F (ab)+c + 4033 LUT3 0D c/Ab\ + 4034 LUT3 35 c?b:a + 4035 LUT4 CA00 D(C?A:B) + 4036 LUT4 F800 ((AB)+C)D + 4037 LUT3 80 ABC + 4038 LUT3 80 ABC + 4039 LUT4 7000 CD/AB\ + 4040 LUT4 0700 cD/AB\ + 4041 LUT4 0777 /AB\(d+c) + 4042 LUT2 8 AB + 4043 LUT4 0777 /AB\(d+c) + 4044 LUT4 0700 cD/AB\ + 4045 LUT2 8 AB + 4046 LUT4 0777 /AB\(d+c) + 4047 LUT4 0700 cD/AB\ + 4048 LUT4 0777 /AB\(d+c) + 4049 LUT2 8 AB + 4050 LUT4 1000 abCD + 4051 LUT4 0700 cD/AB\ + 4052 LUT4 0777 /AB\(d+c) + 4053 LUT2 8 AB + 4054 LUT4 0777 /AB\(d+c) + 4055 LUT2 8 AB + 4056 LUT2 8 AB + 4057 LUT4 8000 ABCD + 4058 LUT4 0777 /AB\(d+c) + 4059 LUT4 0777 /AB\(d+c) + 4060 LUT4 0777 /AB\(d+c) + 4061 LUT4 0777 /AB\(d+c) + 4062 LUT4 FEFF /ab\+C+d + 4063 LUT4 FE00 ((/ab\)+C)D + 4064 LUT3 B0 C/aB\ + 4065 LUT4 0BBB /aB\(d+c) + 4066 LUT4 1000 abCD + 4067 LUT3 80 ABC + 4068 LUT4 8000 ABCD + 4069 LUT4 8000 ABCD + 4070 LUT4 0777 /AB\(d+c) + 4071 LUT4 0777 /AB\(d+c) + 4072 LUT4 0777 /AB\(d+c) + 4073 LUT4 0777 /AB\(d+c) + 4074 LUT3 70 C/AB\ + 4075 LUT4 0777 /AB\(d+c) + 4076 LUT4 0777 /AB\(d+c) + 4077 LUT4 0777 /AB\(d+c) + 4078 LUT4 8000 ABCD + 4079 LUT4 0777 /AB\(d+c) + 4080 LUT4 0777 /AB\(d+c) + 4081 LUT4 0777 /AB\(d+c) + 4082 LUT4 0777 /AB\(d+c) + 4083 LUT4 8000 ABCD + 4084 LUT4 0777 /AB\(d+c) + 4085 LUT4 0777 /AB\(d+c) + 4086 LUT4 0777 /AB\(d+c) + 4087 LUT4 0777 /AB\(d+c) + 4088 LUT2 8 AB + 4089 LUT3 CA C?A:B + 4090 LUT3 8F (AB)+c + 4091 LUT4 F3F5 DC?a:b:1:1 + 4092 LUT2 9 a^B + 4093 LUT4 0B00 cD/aB\ + 4094 LUT3 D0 C/Ab\ + 4095 LUT3 B0 C/aB\ + 4096 LUT4 0BBB /aB\(d+c) + 4097 LUT4 440F D?c:aB + 4098 LUT4 F3F5 DC?a:b:1:1 + 4099 LUT3 B0 C/aB\ + 4100 LUT4 0B00 cD/aB\ + 4101 LUT4 F400 ((aB)+C)D + 4102 LUT2 8 AB + 4103 LUT4 0777 /AB\(d+c) + 4104 LUT4 0777 /AB\(d+c) + 4105 LUT4 7000 CD/AB\ + 4106 LUT3 70 C/AB\ + 4107 LUT4 0777 /AB\(d+c) + 4108 LUT3 01 abc + 4109 LUT4 EF00 ((/ab\)+c)D + 4110 LUT4 0503 DC?b:a:0:0 + 4111 LUT4 0E00 cD/ab\ + 4112 LUT4 8F00 ((AB)+c)D + 4113 LUT4 0777 /AB\(d+c) + 4114 LUT4 0007 cd/AB\ + 4115 LUT2 8 AB + 4116 LUT3 80 ABC + 4117 LUT3 80 ABC + 4118 LUT4 0777 /AB\(d+c) + 4119 LUT2 1 ab + 4120 LUT2 4 aB + 4121 LUT4 BF00 ((/aB\)+c)D + 4122 LUT4 0777 /AB\(d+c) + 4123 LUT2 8 AB + 4124 LUT4 0777 /AB\(d+c) + 4125 LUT4 0777 /AB\(d+c) + 4126 LUT2 4 aB + 4127 LUT4 FFF1 (ab)+C+D + 4128 LUT4 CA00 D(C?A:B) + 4129 LUT4 CA00 D(C?A:B) + 4130 LUT4 F800 ((AB)+C)D + 4131 LUT4 8000 ABCD + 4132 LUT4 7000 CD/AB\ + 4133 LUT3 70 C/AB\ + 4134 LUT4 0777 /AB\(d+c) + 4135 LUT4 7000 CD/AB\ + 4136 LUT4 0777 /AB\(d+c) + 4137 LUT4 0700 cD/AB\ + 4138 LUT2 8 AB + 4139 LUT4 0777 /AB\(d+c) + 4140 LUT4 4000 aBCD + 4141 LUT4 0700 cD/AB\ + 4142 LUT2 8 AB + 4143 LUT4 0777 /AB\(d+c) + 4144 LUT4 0777 /AB\(d+c) + 4145 LUT2 8 AB + 4146 LUT4 0777 /AB\(d+c) + 4147 LUT4 7000 CD/AB\ + 4148 LUT4 0777 /AB\(d+c) + 4149 LUT4 0777 /AB\(d+c) + 4150 LUT4 7000 CD/AB\ + 4151 LUT3 70 C/AB\ + 4152 LUT4 0777 /AB\(d+c) + 4153 LUT4 0777 /AB\(d+c) + 4154 LUT2 B /aB\ + 4155 LUT4 0D00 cD/Ab\ + 4156 LUT3 B0 C/aB\ + 4157 LUT4 0BBB /aB\(d+c) + 4158 LUT4 1000 abCD + 4159 LUT2 8 AB + 4160 LUT4 8000 ABCD + 4161 LUT4 8000 ABCD + 4162 LUT4 0777 /AB\(d+c) + 4163 LUT4 0777 /AB\(d+c) + 4164 LUT4 0777 /AB\(d+c) + 4165 LUT4 0777 /AB\(d+c) + 4166 LUT3 70 C/AB\ + 4167 LUT4 0777 /AB\(d+c) + 4168 LUT4 0777 /AB\(d+c) + 4169 LUT4 0777 /AB\(d+c) + 4170 LUT4 8000 ABCD + 4171 LUT4 8000 ABCD + 4172 LUT4 0777 /AB\(d+c) + 4173 LUT4 0777 /AB\(d+c) + 4174 LUT4 0777 /AB\(d+c) + 4175 LUT4 0777 /AB\(d+c) + 4176 LUT4 0700 cD/AB\ + 4177 LUT2 8 AB + 4178 LUT4 0777 /AB\(d+c) + 4179 LUT4 0777 /AB\(d+c) + 4180 LUT4 0777 /AB\(d+c) + 4181 LUT2 8 AB + 4182 LUT3 CA C?A:B + 4183 LUT3 8F (AB)+c + 4184 LUT4 F3F5 DC?a:b:1:1 + 4185 LUT2 6 A^B + 4186 LUT2 4 aB + 4187 LUT3 D0 C/Ab\ + 4188 LUT3 B0 C/aB\ + 4189 LUT4 0BBB /aB\(d+c) + 4190 LUT4 440F D?c:aB + 4191 LUT4 F3F5 DC?a:b:1:1 + 4192 LUT3 B0 C/aB\ + 4193 LUT4 0B00 cD/aB\ + 4194 LUT4 AC00 D(c?A:B) + 4195 LUT2 4 aB + 4196 LUT4 EF00 ((/ab\)+c)D + 4197 LUT4 0305 DC?a:b:0:0 + 4198 LUT3 AC c?A:B + 4199 LUT2 4 aB + 4200 LUT3 70 C/AB\ + 4201 LUT4 0BBB /aB\(d+c) + 4202 LUT4 4F00 ((aB)+c)D + 4203 LUT3 07 c/AB\ + 4204 LUT3 80 ABC + 4205 LUT4 8000 ABCD + 4206 LUT3 70 C/AB\ + 4207 LUT4 0777 /AB\(d+c) + 4208 LUT4 8000 ABCD + 4209 LUT4 0777 /AB\(d+c) + 4210 LUT4 0777 /AB\(d+c) + 4211 LUT4 0777 /AB\(d+c) + 4212 LUT4 0777 /AB\(d+c) + 4213 LUT4 0777 /AB\(d+c) + 4214 LUT4 0777 /AB\(d+c) + 4215 LUT4 8000 ABCD + 4216 LUT4 0777 /AB\(d+c) + 4217 LUT4 0777 /AB\(d+c) + 4218 LUT4 0777 /AB\(d+c) + 4219 LUT4 0777 /AB\(d+c) + 4220 LUT4 8000 ABCD + 4221 LUT4 0777 /AB\(d+c) + 4222 LUT4 0777 /AB\(d+c) + 4223 LUT4 0777 /AB\(d+c) + 4224 LUT4 0777 /AB\(d+c) + 4225 LUT4 FEFF /ab\+C+d + 4226 LUT4 FE00 ((/ab\)+C)D + 4227 LUT3 B0 C/aB\ + 4228 LUT4 0BBB /aB\(d+c) + 4229 LUT4 1000 abCD + 4230 LUT4 8000 ABCD + 4231 LUT4 7000 CD/AB\ + 4232 LUT4 0700 cD/AB\ + 4233 LUT2 8 AB + 4234 LUT4 0777 /AB\(d+c) + 4235 LUT4 0777 /AB\(d+c) + 4236 LUT4 8000 ABCD + 4237 LUT4 0777 /AB\(d+c) + 4238 LUT4 0777 /AB\(d+c) + 4239 LUT4 0777 /AB\(d+c) + 4240 LUT4 0777 /AB\(d+c) + 4241 LUT4 8000 ABCD + 4242 LUT4 0777 /AB\(d+c) + 4243 LUT4 0777 /AB\(d+c) + 4244 LUT4 0777 /AB\(d+c) + 4245 LUT4 0777 /AB\(d+c) + 4246 LUT4 8000 ABCD + 4247 LUT4 0777 /AB\(d+c) + 4248 LUT4 0777 /AB\(d+c) + 4249 LUT4 0777 /AB\(d+c) + 4250 LUT4 0777 /AB\(d+c) + 4251 LUT2 8 AB + 4252 LUT3 CA C?A:B + 4253 LUT3 8F (AB)+c + 4254 LUT4 F3F5 DC?a:b:1:1 + 4255 LUT3 01 abc + 4256 LUT2 9 a^B + 4257 LUT4 4F00 ((aB)+c)D + 4258 LUT3 D0 C/Ab\ + 4259 LUT3 B0 C/aB\ + 4260 LUT4 0BBB /aB\(d+c) + 4261 LUT4 440F D?c:aB + 4262 LUT4 F3F5 DC?a:b:1:1 + 4263 LUT4 00EF ((/ab\)+c)d + 4264 LUT4 AC00 D(c?A:B) + 4265 LUT2 8 AB + 4266 LUT4 0777 /AB\(d+c) + 4267 LUT4 0777 /AB\(d+c) + 4268 LUT4 0C0A DC?A:B:0:0 + 4269 LUT2 1 ab + 4270 LUT4 EF00 ((/ab\)+c)D + 4271 LUT4 5300 D(C?b:a) + 4272 LUT4 8F00 ((AB)+c)D + 4273 LUT4 0777 /AB\(d+c) + 4274 LUT2 8 AB + 4275 LUT4 0007 cd/AB\ + 4276 LUT3 80 ABC + 4277 LUT3 80 ABC + 4278 LUT4 0777 /AB\(d+c) + 4279 LUT3 CA C?A:B + 4280 LUT2 4 aB + 4281 LUT3 4F (aB)+c + 4282 LUT3 C5 C?a:B + 4283 LUT3 35 c?b:a + 4284 LUT4 FAFC DC?B:A:1:1 + 4285 LUT4 B0BB /aB\(d+C) + 4286 LUT3 80 ABC + 4287 LUT4 8000 ABCD + 4288 LUT3 70 C/AB\ + 4289 LUT4 0777 /AB\(d+c) + 4290 LUT4 8000 ABCD + 4291 LUT4 0777 /AB\(d+c) + 4292 LUT4 0777 /AB\(d+c) + 4293 LUT4 0777 /AB\(d+c) + 4294 LUT4 0777 /AB\(d+c) + 4295 LUT4 0777 /AB\(d+c) + 4296 LUT4 0777 /AB\(d+c) + 4297 LUT4 8000 ABCD + 4298 LUT4 0777 /AB\(d+c) + 4299 LUT4 0777 /AB\(d+c) + 4300 LUT4 0777 /AB\(d+c) + 4301 LUT4 0777 /AB\(d+c) + 4302 LUT4 8000 ABCD + 4303 LUT4 0777 /AB\(d+c) + 4304 LUT4 0777 /AB\(d+c) + 4305 LUT4 0777 /AB\(d+c) + 4306 LUT4 0777 /AB\(d+c) + 4307 LUT4 F8FF (AB)+C+d + 4308 LUT4 1F00 ((ab)+c)D + 4309 LUT3 B0 C/aB\ + 4310 LUT4 00BF ((/aB\)+c)d + 4311 LUT2 4 aB + 4312 LUT4 1000 abCD + 4313 LUT4 8000 ABCD + 4314 LUT4 7000 CD/AB\ + 4315 LUT4 7000 CD/AB\ + 4316 LUT3 70 C/AB\ + 4317 LUT4 0777 /AB\(d+c) + 4318 LUT4 0700 cD/AB\ + 4319 LUT2 8 AB + 4320 LUT4 0777 /AB\(d+c) + 4321 LUT3 80 ABC + 4322 LUT4 0777 /AB\(d+c) + 4323 LUT4 0777 /AB\(d+c) + 4324 LUT4 0777 /AB\(d+c) + 4325 LUT4 7000 CD/AB\ + 4326 LUT4 7000 CD/AB\ + 4327 LUT4 0777 /AB\(d+c) + 4328 LUT4 0777 /AB\(d+c) + 4329 LUT4 0777 /AB\(d+c) + 4330 LUT4 0700 cD/AB\ + 4331 LUT2 8 AB + 4332 LUT4 0777 /AB\(d+c) + 4333 LUT4 0700 cD/AB\ + 4334 LUT2 8 AB + 4335 LUT4 0777 /AB\(d+c) + 4336 LUT3 CA C?A:B + 4337 LUT3 8F (AB)+c + 4338 LUT4 F3F5 DC?a:b:1:1 + 4339 LUT2 9 a^B + 4340 LUT4 0B00 cD/aB\ + 4341 LUT3 D0 C/Ab\ + 4342 LUT3 B0 C/aB\ + 4343 LUT4 0BBB /aB\(d+c) + 4344 LUT4 440F D?c:aB + 4345 LUT4 F3F5 DC?a:b:1:1 + 4346 LUT3 B0 C/aB\ + 4347 LUT4 0B00 cD/aB\ + 4348 LUT4 AC00 D(c?A:B) + 4349 LUT2 8 AB + 4350 LUT4 0777 /AB\(d+c) + 4351 LUT4 0777 /AB\(d+c) + 4352 LUT2 4 aB + 4353 LUT4 EF00 ((/ab\)+c)D + 4354 LUT4 0A03 DC?b:A:0:0 + 4355 LUT3 AC c?A:B + 4356 LUT4 8F00 ((AB)+c)D + 4357 LUT4 0777 /AB\(d+c) + 4358 LUT4 0007 cd/AB\ + 4359 LUT3 80 ABC + 4360 LUT3 80 ABC + 4361 LUT4 0777 /AB\(d+c) + 4362 LUT2 1 ab + 4363 LUT2 4 aB + 4364 LUT2 4 aB + 4365 LUT3 70 C/AB\ + 4366 LUT4 770F D?c:/AB\ + 4367 LUT3 35 c?b:a + 4368 LUT4 F400 ((aB)+C)D + 4369 LUT3 80 ABC + 4370 LUT4 8000 ABCD + 4371 LUT4 8000 ABCD + 4372 LUT4 0777 /AB\(d+c) + 4373 LUT4 0777 /AB\(d+c) + 4374 LUT4 0777 /AB\(d+c) + 4375 LUT4 0777 /AB\(d+c) + 4376 LUT4 0777 /AB\(d+c) + 4377 LUT4 0777 /AB\(d+c) + 4378 LUT3 70 C/AB\ + 4379 LUT4 0777 /AB\(d+c) + 4380 LUT4 8000 ABCD + 4381 LUT4 0777 /AB\(d+c) + 4382 LUT4 0777 /AB\(d+c) + 4383 LUT4 0777 /AB\(d+c) + 4384 LUT4 0777 /AB\(d+c) + 4385 LUT4 8000 ABCD + 4386 LUT4 0777 /AB\(d+c) + 4387 LUT4 0777 /AB\(d+c) + 4388 LUT4 0777 /AB\(d+c) + 4389 LUT4 0777 /AB\(d+c) + 4390 LUT4 FEFF /ab\+C+d + 4391 LUT4 FE00 ((/ab\)+C)D + 4392 LUT3 B0 C/aB\ + 4393 LUT4 0BBB /aB\(d+c) + 4394 LUT4 1000 abCD + 4395 LUT4 8000 ABCD + 4396 LUT4 7000 CD/AB\ + 4397 LUT4 0700 cD/AB\ + 4398 LUT2 8 AB + 4399 LUT4 0777 /AB\(d+c) + 4400 LUT4 0777 /AB\(d+c) + 4401 LUT4 8000 ABCD + 4402 LUT4 0777 /AB\(d+c) + 4403 LUT4 0777 /AB\(d+c) + 4404 LUT4 0777 /AB\(d+c) + 4405 LUT4 0777 /AB\(d+c) + 4406 LUT4 8000 ABCD + 4407 LUT4 0777 /AB\(d+c) + 4408 LUT4 0777 /AB\(d+c) + 4409 LUT4 0777 /AB\(d+c) + 4410 LUT4 0777 /AB\(d+c) + 4411 LUT4 8000 ABCD + 4412 LUT4 0777 /AB\(d+c) + 4413 LUT4 0777 /AB\(d+c) + 4414 LUT4 0777 /AB\(d+c) + 4415 LUT4 0777 /AB\(d+c) + 4416 LUT2 8 AB + 4417 LUT3 CA C?A:B + 4418 LUT3 8F (AB)+c + 4419 LUT4 F3F5 DC?a:b:1:1 + 4420 LUT2 9 a^B + 4421 LUT4 0B00 cD/aB\ + 4422 LUT3 D0 C/Ab\ + 4423 LUT3 B0 C/aB\ + 4424 LUT4 0BBB /aB\(d+c) + 4425 LUT4 440F D?c:aB + 4426 LUT4 F3F5 DC?a:b:1:1 + 4427 LUT3 D0 C/Ab\ + 4428 LUT4 F400 ((aB)+C)D + 4429 LUT4 7000 CD/AB\ + 4430 LUT4 0007 cd/AB\ + 4431 LUT2 8 AB + 4432 LUT2 8 AB + 4433 LUT2 8 AB + 4434 LUT4 0777 /AB\(d+c) + 4435 LUT4 0777 /AB\(d+c) + 4436 LUT4 0B00 cD/aB\ + 4437 LUT2 4 aB + 4438 LUT4 EF00 ((/ab\)+c)D + 4439 LUT4 0503 DC?b:a:0:0 + 4440 LUT4 0E00 cD/ab\ + 4441 LUT4 8F00 ((AB)+c)D + 4442 LUT4 0777 /AB\(d+c) + 4443 LUT4 0007 cd/AB\ + 4444 LUT3 80 ABC + 4445 LUT3 80 ABC + 4446 LUT4 0777 /AB\(d+c) + 4447 LUT2 1 ab + 4448 LUT2 4 aB + 4449 LUT4 BF00 ((/aB\)+c)D + 4450 LUT4 0777 /AB\(d+c) + 4451 LUT2 8 AB + 4452 LUT4 0777 /AB\(d+c) + 4453 LUT4 0777 /AB\(d+c) + 4454 LUT2 4 aB + 4455 LUT3 1F (ab)+c + 4456 LUT3 0D c/Ab\ + 4457 LUT3 35 c?b:a + 4458 LUT4 CA00 D(C?A:B) + 4459 LUT4 F800 ((AB)+C)D + 4460 LUT4 8000 ABCD + 4461 LUT3 80 ABC + 4462 LUT4 7000 CD/AB\ + 4463 LUT3 70 C/AB\ + 4464 LUT4 0777 /AB\(d+c) + 4465 LUT4 0777 /AB\(d+c) + 4466 LUT4 7000 CD/AB\ + 4467 LUT4 0777 /AB\(d+c) + 4468 LUT4 0777 /AB\(d+c) + 4469 LUT4 0700 cD/AB\ + 4470 LUT2 8 AB + 4471 LUT4 0777 /AB\(d+c) + 4472 LUT4 7000 CD/AB\ + 4473 LUT3 70 C/AB\ + 4474 LUT4 0777 /AB\(d+c) + 4475 LUT4 0777 /AB\(d+c) + 4476 LUT4 7000 CD/AB\ + 4477 LUT4 0777 /AB\(d+c) + 4478 LUT4 0777 /AB\(d+c) + 4479 LUT4 7000 CD/AB\ + 4480 LUT4 0777 /AB\(d+c) + 4481 LUT4 0777 /AB\(d+c) + 4482 LUT4 FEFF /ab\+C+d + 4483 LUT4 FE00 ((/ab\)+C)D + 4484 LUT3 B0 C/aB\ + 4485 LUT4 0BBB /aB\(d+c) + 4486 LUT4 1000 abCD + 4487 LUT4 8000 ABCD + 4488 LUT4 8000 ABCD + 4489 LUT4 8000 ABCD + 4490 LUT4 0777 /AB\(d+c) + 4491 LUT4 0777 /AB\(d+c) + 4492 LUT4 0777 /AB\(d+c) + 4493 LUT4 0777 /AB\(d+c) + 4494 LUT3 70 C/AB\ + 4495 LUT4 0777 /AB\(d+c) + 4496 LUT4 0777 /AB\(d+c) + 4497 LUT4 0777 /AB\(d+c) + 4498 LUT4 8000 ABCD + 4499 LUT4 0777 /AB\(d+c) + 4500 LUT4 0777 /AB\(d+c) + 4501 LUT4 0777 /AB\(d+c) + 4502 LUT4 0777 /AB\(d+c) + 4503 LUT4 0700 cD/AB\ + 4504 LUT4 0777 /AB\(d+c) + 4505 LUT2 8 AB + 4506 LUT4 0700 cD/AB\ + 4507 LUT4 0777 /AB\(d+c) + 4508 LUT2 8 AB + 4509 LUT2 8 AB + 4510 LUT3 CA C?A:B + 4511 LUT3 8F (AB)+c + 4512 LUT4 F53F DC?1:a:b:1 + 4513 LUT4 8000 ABCD + 4514 LUT2 6 A^B + 4515 LUT4 0B00 cD/aB\ + 4516 LUT3 D0 C/Ab\ + 4517 LUT3 B0 C/aB\ + 4518 LUT4 0BBB /aB\(d+c) + 4519 LUT4 440F D?c:aB + 4520 LUT4 F3F5 DC?a:b:1:1 + 4521 LUT3 D0 C/Ab\ + 4522 LUT4 F400 ((aB)+C)D + 4523 LUT4 7000 CD/AB\ + 4524 LUT4 0007 cd/AB\ + 4525 LUT2 8 AB + 4526 LUT2 8 AB + 4527 LUT4 0B00 cD/aB\ + 4528 LUT3 01 abc + 4529 LUT4 EF00 ((/ab\)+c)D + 4530 LUT4 050C DC?B:a:0:0 + 4531 LUT4 0E00 cD/ab\ + 4532 LUT4 BF00 ((/aB\)+c)D + 4533 LUT4 0777 /AB\(d+c) + 4534 LUT2 8 AB + 4535 LUT4 0777 /AB\(d+c) + 4536 LUT4 0777 /AB\(d+c) + 4537 LUT2 4 aB + 4538 LUT3 1F (ab)+c + 4539 LUT3 0D c/Ab\ + 4540 LUT4 CA00 D(C?A:B) + 4541 LUT4 F800 ((AB)+C)D + 4542 LUT4 8000 ABCD + 4543 LUT4 8000 ABCD + 4544 LUT4 0777 /AB\(d+c) + 4545 LUT4 0777 /AB\(d+c) + 4546 LUT4 0777 /AB\(d+c) + 4547 LUT4 0777 /AB\(d+c) + 4548 LUT4 8000 ABCD + 4549 LUT4 0777 /AB\(d+c) + 4550 LUT4 0777 /AB\(d+c) + 4551 LUT4 0777 /AB\(d+c) + 4552 LUT4 0777 /AB\(d+c) + 4553 LUT4 4000 aBCD + 4554 LUT4 0777 /AB\(d+c) + 4555 LUT4 0777 /AB\(d+c) + 4556 LUT4 0777 /AB\(d+c) + 4557 LUT2 8 AB + 4558 LUT4 8000 ABCD + 4559 LUT4 0777 /AB\(d+c) + 4560 LUT4 0777 /AB\(d+c) + 4561 LUT4 0777 /AB\(d+c) + 4562 LUT4 0777 /AB\(d+c) + 4563 LUT2 B /aB\ + 4564 LUT4 0D00 cD/Ab\ + 4565 LUT3 B0 C/aB\ + 4566 LUT4 0BBB /aB\(d+c) + 4567 LUT4 1000 abCD + 4568 LUT4 8000 ABCD + 4569 LUT4 8000 ABCD + 4570 LUT4 0777 /AB\(d+c) + 4571 LUT4 0777 /AB\(d+c) + 4572 LUT4 0777 /AB\(d+c) + 4573 LUT4 0777 /AB\(d+c) + 4574 LUT4 4000 aBCD + 4575 LUT2 8 AB + 4576 LUT4 0777 /AB\(d+c) + 4577 LUT4 0777 /AB\(d+c) + 4578 LUT4 0777 /AB\(d+c) + 4579 LUT4 8000 ABCD + 4580 LUT4 0777 /AB\(d+c) + 4581 LUT4 0777 /AB\(d+c) + 4582 LUT4 0777 /AB\(d+c) + 4583 LUT4 0777 /AB\(d+c) + 4584 LUT4 8000 ABCD + 4585 LUT4 0777 /AB\(d+c) + 4586 LUT4 0777 /AB\(d+c) + 4587 LUT4 0777 /AB\(d+c) + 4588 LUT4 0777 /AB\(d+c) + 4589 LUT2 8 AB + 4590 LUT3 CA C?A:B + 4591 LUT3 8F (AB)+c + 4592 LUT4 F3F5 DC?a:b:1:1 + 4593 LUT2 6 A^B + 4594 LUT4 0B00 cD/aB\ + 4595 LUT3 D0 C/Ab\ + 4596 LUT3 B0 C/aB\ + 4597 LUT4 0BBB /aB\(d+c) + 4598 LUT4 440F D?c:aB + 4599 LUT4 F3F5 DC?a:b:1:1 + 4600 LUT3 B0 C/aB\ + 4601 LUT4 0B00 cD/aB\ + 4602 LUT4 AC00 D(c?A:B) + 4603 LUT2 8 AB + 4604 LUT4 0777 /AB\(d+c) + 4605 LUT4 0777 /AB\(d+c) + 4606 LUT2 4 aB + 4607 LUT4 EF00 ((/ab\)+c)D + 4608 LUT4 0305 DC?a:b:0:0 + 4609 LUT3 AC c?A:B + 4610 LUT4 8F00 ((AB)+c)D + 4611 LUT4 0777 /AB\(d+c) + 4612 LUT4 0007 cd/AB\ + 4613 LUT3 80 ABC + 4614 LUT3 80 ABC + 4615 LUT4 0777 /AB\(d+c) + 4616 LUT2 1 ab + 4617 LUT2 4 aB + 4618 LUT2 4 aB + 4619 LUT3 70 C/AB\ + 4620 LUT4 0BBB /aB\(d+c) + 4621 LUT3 35 c?b:a + 4622 LUT4 F400 ((aB)+C)D + 4623 LUT3 80 ABC + 4624 LUT3 70 C/AB\ + 4625 LUT4 0777 /AB\(d+c) + 4626 LUT4 0777 /AB\(d+c) + 4627 LUT4 0777 /AB\(d+c) + 4628 LUT4 0777 /AB\(d+c) + 4629 LUT4 0777 /AB\(d+c) + 4630 LUT4 8000 ABCD + 4631 LUT4 8000 ABCD + 4632 LUT4 0777 /AB\(d+c) + 4633 LUT4 0777 /AB\(d+c) + 4634 LUT4 0777 /AB\(d+c) + 4635 LUT4 0777 /AB\(d+c) + 4636 LUT4 0700 cD/AB\ + 4637 LUT4 0777 /AB\(d+c) + 4638 LUT2 8 AB + 4639 LUT4 0777 /AB\(d+c) + 4640 LUT4 0777 /AB\(d+c) + 4641 LUT4 FEFF /ab\+C+d + 4642 LUT4 FE00 ((/ab\)+C)D + 4643 LUT3 B0 C/aB\ + 4644 LUT4 0BBB /aB\(d+c) + 4645 LUT4 1000 abCD + 4646 LUT4 8000 ABCD + 4647 LUT4 7000 CD/AB\ + 4648 LUT4 0700 cD/AB\ + 4649 LUT2 8 AB + 4650 LUT4 0777 /AB\(d+c) + 4651 LUT4 0777 /AB\(d+c) + 4652 LUT4 8000 ABCD + 4653 LUT4 0777 /AB\(d+c) + 4654 LUT4 0777 /AB\(d+c) + 4655 LUT4 0777 /AB\(d+c) + 4656 LUT4 0777 /AB\(d+c) + 4657 LUT4 8000 ABCD + 4658 LUT4 0777 /AB\(d+c) + 4659 LUT4 0777 /AB\(d+c) + 4660 LUT4 0777 /AB\(d+c) + 4661 LUT4 0777 /AB\(d+c) + 4662 LUT4 8000 ABCD + 4663 LUT4 0777 /AB\(d+c) + 4664 LUT4 0777 /AB\(d+c) + 4665 LUT4 0777 /AB\(d+c) + 4666 LUT4 0777 /AB\(d+c) + 4667 LUT2 8 AB + 4668 LUT3 CA C?A:B + 4669 LUT3 8F (AB)+c + 4670 LUT4 F3F5 DC?a:b:1:1 + 4671 LUT2 6 A^B + 4672 LUT2 4 aB + 4673 LUT3 D0 C/Ab\ + 4674 LUT3 B0 C/aB\ + 4675 LUT4 0BBB /aB\(d+c) + 4676 LUT4 440F D?c:aB + 4677 LUT4 F3F5 DC?a:b:1:1 + 4678 LUT2 1 ab + 4679 LUT4 3A00 D(c?b:A) + 4680 LUT3 35 c?b:a + 4681 LUT2 1 ab + 4682 LUT4 FE00 ((/ab\)+C)D + 4683 LUT4 5300 D(C?b:a) + 4684 LUT3 53 C?b:a + 4685 LUT2 4 aB + 4686 LUT3 4F (aB)+c + 4687 LUT4 FAFC DC?B:A:1:1 + 4688 LUT4 4F00 ((aB)+c)D + 4689 LUT3 0B c/aB\ + 4690 LUT4 8000 ABCD + 4691 LUT4 7000 CD/AB\ + 4692 LUT4 0700 cD/AB\ + 4693 LUT4 0777 /AB\(d+c) + 4694 LUT2 8 AB + 4695 LUT4 0777 /AB\(d+c) + 4696 LUT4 8000 ABCD + 4697 LUT4 0777 /AB\(d+c) + 4698 LUT4 0777 /AB\(d+c) + 4699 LUT4 0777 /AB\(d+c) + 4700 LUT4 0777 /AB\(d+c) + 4701 LUT4 8000 ABCD + 4702 LUT4 0777 /AB\(d+c) + 4703 LUT4 0777 /AB\(d+c) + 4704 LUT4 0777 /AB\(d+c) + 4705 LUT4 0777 /AB\(d+c) + 4706 LUT4 8000 ABCD + 4707 LUT4 0777 /AB\(d+c) + 4708 LUT4 0777 /AB\(d+c) + 4709 LUT4 0777 /AB\(d+c) + 4710 LUT4 0777 /AB\(d+c) + 4711 LUT4 F8FF (AB)+C+d + 4712 LUT4 1F00 ((ab)+c)D + 4713 LUT3 B0 C/aB\ + 4714 LUT4 00BF ((/aB\)+c)d + 4715 LUT2 4 aB + 4716 LUT4 1000 abCD + 4717 LUT3 80 ABC + 4718 LUT4 8000 ABCD + 4719 LUT3 80 ABC + 4720 LUT4 0700 cD/AB\ + 4721 LUT4 0777 /AB\(d+c) + 4722 LUT2 8 AB + 4723 LUT4 0777 /AB\(d+c) + 4724 LUT4 0777 /AB\(d+c) + 4725 LUT3 70 C/AB\ + 4726 LUT4 0777 /AB\(d+c) + 4727 LUT4 0777 /AB\(d+c) + 4728 LUT4 0777 /AB\(d+c) + 4729 LUT4 8000 ABCD + 4730 LUT4 0777 /AB\(d+c) + 4731 LUT4 0777 /AB\(d+c) + 4732 LUT4 0777 /AB\(d+c) + 4733 LUT4 0777 /AB\(d+c) + 4734 LUT4 8000 ABCD + 4735 LUT4 0777 /AB\(d+c) + 4736 LUT4 0777 /AB\(d+c) + 4737 LUT4 0777 /AB\(d+c) + 4738 LUT4 0777 /AB\(d+c) + 4739 LUT3 CA C?A:B + 4740 LUT3 8F (AB)+c + 4741 LUT4 F53F DC?1:a:b:1 + 4742 LUT2 6 A^B + 4743 LUT4 0B00 cD/aB\ + 4744 LUT3 D0 C/Ab\ + 4745 LUT3 B0 C/aB\ + 4746 LUT4 0BBB /aB\(d+c) + 4747 LUT4 440F D?c:aB + 4748 LUT4 F3F5 DC?a:b:1:1 + 4749 LUT3 B0 C/aB\ + 4750 LUT4 0B00 cD/aB\ + 4751 LUT4 AC00 D(c?A:B) + 4752 LUT2 4 aB + 4753 LUT4 EF00 ((/ab\)+c)D + 4754 LUT4 0305 DC?a:b:0:0 + 4755 LUT3 AC c?A:B + 4756 LUT2 4 aB + 4757 LUT3 70 C/AB\ + 4758 LUT4 BB0F D?c:/aB\ + 4759 LUT4 F400 ((aB)+C)D + 4760 LUT4 8000 ABCD + 4761 LUT4 8000 ABCD + 4762 LUT4 7000 CD/AB\ + 4763 LUT4 0700 cD/AB\ + 4764 LUT2 8 AB + 4765 LUT4 0777 /AB\(d+c) + 4766 LUT4 0777 /AB\(d+c) + 4767 LUT3 70 C/AB\ + 4768 LUT4 0777 /AB\(d+c) + 4769 LUT4 0777 /AB\(d+c) + 4770 LUT4 0777 /AB\(d+c) + 4771 LUT4 7000 CD/AB\ + 4772 LUT4 7000 CD/AB\ + 4773 LUT4 0700 cD/AB\ + 4774 LUT4 0777 /AB\(d+c) + 4775 LUT2 8 AB + 4776 LUT4 0777 /AB\(d+c) + 4777 LUT4 0777 /AB\(d+c) + 4778 LUT4 7000 CD/AB\ + 4779 LUT4 0777 /AB\(d+c) + 4780 LUT4 0777 /AB\(d+c) + 4781 LUT4 0777 /AB\(d+c) + 4782 LUT4 FEFF /ab\+C+d + 4783 LUT4 FE00 ((/ab\)+C)D + 4784 LUT3 B0 C/aB\ + 4785 LUT4 0BBB /aB\(d+c) + 4786 LUT4 1000 abCD + 4787 LUT4 8000 ABCD + 4788 LUT4 7000 CD/AB\ + 4789 LUT4 7000 CD/AB\ + 4790 LUT4 0700 cD/AB\ + 4791 LUT4 0777 /AB\(d+c) + 4792 LUT2 8 AB + 4793 LUT4 0777 /AB\(d+c) + 4794 LUT3 70 C/AB\ + 4795 LUT4 0777 /AB\(d+c) + 4796 LUT4 7000 CD/AB\ + 4797 LUT4 0700 cD/AB\ + 4798 LUT2 8 AB + 4799 LUT4 0777 /AB\(d+c) + 4800 LUT4 0777 /AB\(d+c) + 4801 LUT4 7000 CD/AB\ + 4802 LUT4 7000 CD/AB\ + 4803 LUT4 0777 /AB\(d+c) + 4804 LUT4 0777 /AB\(d+c) + 4805 LUT4 0777 /AB\(d+c) + 4806 LUT4 0700 cD/AB\ + 4807 LUT3 70 C/AB\ + 4808 LUT4 0777 /AB\(d+c) + 4809 LUT2 8 AB + 4810 LUT2 8 AB + 4811 LUT3 CA C?A:B + 4812 LUT3 8F (AB)+c + 4813 LUT4 F3F5 DC?a:b:1:1 + 4814 LUT4 8000 ABCD + 4815 LUT2 6 A^B + 4816 LUT2 4 aB + 4817 LUT3 D0 C/Ab\ + 4818 LUT3 B0 C/aB\ + 4819 LUT4 0BBB /aB\(d+c) + 4820 LUT4 440F D?c:aB + 4821 LUT4 F3F5 DC?a:b:1:1 + 4822 LUT3 B0 C/aB\ + 4823 LUT4 0B00 cD/aB\ + 4824 LUT4 CA00 D(C?A:B) + 4825 LUT2 4 aB + 4826 LUT4 EF00 ((/ab\)+c)D + 4827 LUT4 0305 DC?a:b:0:0 + 4828 LUT3 AC c?A:B + 4829 LUT2 4 aB + 4830 LUT3 70 C/AB\ + 4831 LUT4 770F D?c:/AB\ + 4832 LUT4 4F00 ((aB)+c)D + 4833 LUT3 07 c/AB\ + 4834 LUT4 8000 ABCD + 4835 LUT4 1000 abCD + 4836 LUT3 70 C/AB\ + 4837 LUT4 0777 /AB\(d+c) + 4838 LUT4 7000 CD/AB\ + 4839 LUT4 0777 /AB\(d+c) + 4840 LUT4 0777 /AB\(d+c) + 4841 LUT2 8 AB + 4842 LUT2 8 AB + 4843 LUT4 7000 CD/AB\ + 4844 LUT4 0007 cd/AB\ + 4845 LUT2 8 AB + 4846 LUT2 8 AB + 4847 LUT3 80 ABC + 4848 LUT4 0777 /AB\(d+c) + 4849 LUT3 70 C/AB\ + 4850 LUT4 0777 /AB\(d+c) + 4851 LUT4 0777 /AB\(d+c) + 4852 LUT4 7000 CD/AB\ + 4853 LUT3 70 C/AB\ + 4854 LUT4 0777 /AB\(d+c) + 4855 LUT4 0777 /AB\(d+c) + 4856 LUT4 0700 cD/AB\ + 4857 LUT2 8 AB + 4858 LUT4 0777 /AB\(d+c) + 4859 LUT4 FEFF /ab\+C+d + 4860 LUT4 FE00 ((/ab\)+C)D + 4861 LUT3 B0 C/aB\ + 4862 LUT4 0BBB /aB\(d+c) + 4863 LUT4 1000 abCD + 4864 LUT4 8000 ABCD + 4865 LUT4 7000 CD/AB\ + 4866 LUT4 7000 CD/AB\ + 4867 LUT4 0007 cd/AB\ + 4868 LUT2 8 AB + 4869 LUT2 8 AB + 4870 LUT4 0700 cD/AB\ + 4871 LUT2 8 AB + 4872 LUT4 0777 /AB\(d+c) + 4873 LUT4 7000 CD/AB\ + 4874 LUT4 0700 cD/AB\ + 4875 LUT2 8 AB + 4876 LUT4 0777 /AB\(d+c) + 4877 LUT4 0777 /AB\(d+c) + 4878 LUT4 7000 CD/AB\ + 4879 LUT4 7000 CD/AB\ + 4880 LUT4 0777 /AB\(d+c) + 4881 LUT4 0777 /AB\(d+c) + 4882 LUT4 0777 /AB\(d+c) + 4883 LUT4 7000 CD/AB\ + 4884 LUT4 0777 /AB\(d+c) + 4885 LUT4 0777 /AB\(d+c) + 4886 LUT4 0777 /AB\(d+c) + 4887 LUT2 8 AB + 4888 LUT3 CA C?A:B + 4889 LUT3 8F (AB)+c + 4890 LUT4 F3F5 DC?a:b:1:1 + 4891 LUT2 6 A^B + 4892 LUT4 0B00 cD/aB\ + 4893 LUT3 D0 C/Ab\ + 4894 LUT3 B0 C/aB\ + 4895 LUT4 0BBB /aB\(d+c) + 4896 LUT4 440F D?c:aB + 4897 LUT4 F3F5 DC?a:b:1:1 + 4898 LUT3 B0 C/aB\ + 4899 LUT4 0B00 cD/aB\ + 4900 LUT4 AC00 D(c?A:B) + 4901 LUT2 4 aB + 4902 LUT4 FE00 ((/ab\)+C)D + 4903 LUT4 0503 DC?b:a:0:0 + 4904 LUT3 53 C?b:a + 4905 LUT2 4 aB + 4906 LUT3 70 C/AB\ + 4907 LUT3 0B c/aB\ + 4908 LUT4 3500 D(c?b:a) + 4909 LUT4 F400 ((aB)+C)D + 4910 LUT4 8000 ABCD + 4911 LUT4 7000 CD/AB\ + 4912 LUT4 0700 cD/AB\ + 4913 LUT4 0777 /AB\(d+c) + 4914 LUT2 8 AB + 4915 LUT4 0777 /AB\(d+c) + 4916 LUT4 8000 ABCD + 4917 LUT4 0777 /AB\(d+c) + 4918 LUT4 0777 /AB\(d+c) + 4919 LUT4 0777 /AB\(d+c) + 4920 LUT4 0777 /AB\(d+c) + 4921 LUT4 8000 ABCD + 4922 LUT4 0777 /AB\(d+c) + 4923 LUT4 0777 /AB\(d+c) + 4924 LUT4 0777 /AB\(d+c) + 4925 LUT4 0777 /AB\(d+c) + 4926 LUT4 8000 ABCD + 4927 LUT4 0777 /AB\(d+c) + 4928 LUT4 0777 /AB\(d+c) + 4929 LUT4 0777 /AB\(d+c) + 4930 LUT4 0777 /AB\(d+c) + 4931 LUT4 FEFF /ab\+C+d + 4932 LUT4 FE00 ((/ab\)+C)D + 4933 LUT3 B0 C/aB\ + 4934 LUT4 0BBB /aB\(d+c) + 4935 LUT4 1000 abCD + 4936 LUT4 8000 ABCD + 4937 LUT4 4000 aBCD + 4938 LUT4 7000 CD/AB\ + 4939 LUT4 7000 CD/AB\ + 4940 LUT4 0777 /AB\(d+c) + 4941 LUT4 0777 /AB\(d+c) + 4942 LUT4 0777 /AB\(d+c) + 4943 LUT2 8 AB + 4944 LUT4 0777 /AB\(d+c) + 4945 LUT4 0777 /AB\(d+c) + 4946 LUT2 8 AB + 4947 LUT4 0777 /AB\(d+c) + 4948 LUT4 0777 /AB\(d+c) + 4949 LUT2 8 AB + 4950 LUT4 0777 /AB\(d+c) + 4951 LUT4 0700 cD/AB\ + 4952 LUT2 8 AB + 4953 LUT4 0777 /AB\(d+c) + 4954 LUT4 0700 cD/AB\ + 4955 LUT2 8 AB + 4956 LUT4 0777 /AB\(d+c) + 4957 LUT2 8 AB + 4958 LUT3 CA C?A:B + 4959 LUT3 8F (AB)+c + 4960 LUT4 F53F DC?1:a:b:1 + 4961 LUT2 6 A^B + 4962 LUT2 4 aB + 4963 LUT3 D0 C/Ab\ + 4964 LUT3 B0 C/aB\ + 4965 LUT4 0BBB /aB\(d+c) + 4966 LUT4 440F D?c:aB + 4967 LUT4 F3F5 DC?a:b:1:1 + 4968 LUT3 B0 C/aB\ + 4969 LUT4 0B00 cD/aB\ + 4970 LUT4 CA00 D(C?A:B) + 4971 LUT2 4 aB + 4972 LUT4 EF00 ((/ab\)+c)D + 4973 LUT4 0503 DC?b:a:0:0 + 4974 LUT3 CA C?A:B + 4975 LUT2 4 aB + 4976 LUT3 70 C/AB\ + 4977 LUT4 770F D?c:/AB\ + 4978 LUT4 FE00 ((/ab\)+C)D + 4979 LUT2 4 aB + 4980 LUT4 8000 ABCD + 4981 LUT4 7000 CD/AB\ + 4982 LUT4 0700 cD/AB\ + 4983 LUT4 0777 /AB\(d+c) + 4984 LUT2 8 AB + 4985 LUT4 0777 /AB\(d+c) + 4986 LUT4 8000 ABCD + 4987 LUT4 0777 /AB\(d+c) + 4988 LUT4 0777 /AB\(d+c) + 4989 LUT4 0777 /AB\(d+c) + 4990 LUT4 0777 /AB\(d+c) + 4991 LUT4 8000 ABCD + 4992 LUT4 0777 /AB\(d+c) + 4993 LUT4 0777 /AB\(d+c) + 4994 LUT4 0777 /AB\(d+c) + 4995 LUT4 0777 /AB\(d+c) + 4996 LUT4 8000 ABCD + 4997 LUT4 0777 /AB\(d+c) + 4998 LUT4 0777 /AB\(d+c) + 4999 LUT4 0777 /AB\(d+c) + 5000 LUT4 0777 /AB\(d+c) + 5001 LUT2 8 AB + 5002 LUT4 FEFF /ab\+C+d + 5003 LUT4 FE00 ((/ab\)+C)D + 5004 LUT3 B0 C/aB\ + 5005 LUT4 0BBB /aB\(d+c) + 5006 LUT4 1000 abCD + 5007 LUT3 80 ABC + 5008 LUT4 8000 ABCD + 5009 LUT3 80 ABC + 5010 LUT4 0700 cD/AB\ + 5011 LUT4 0777 /AB\(d+c) + 5012 LUT2 8 AB + 5013 LUT4 0777 /AB\(d+c) + 5014 LUT4 0777 /AB\(d+c) + 5015 LUT3 70 C/AB\ + 5016 LUT4 0777 /AB\(d+c) + 5017 LUT4 0777 /AB\(d+c) + 5018 LUT4 0777 /AB\(d+c) + 5019 LUT4 8000 ABCD + 5020 LUT4 0777 /AB\(d+c) + 5021 LUT4 0777 /AB\(d+c) + 5022 LUT4 0777 /AB\(d+c) + 5023 LUT4 0777 /AB\(d+c) + 5024 LUT4 8000 ABCD + 5025 LUT4 0777 /AB\(d+c) + 5026 LUT4 0777 /AB\(d+c) + 5027 LUT4 0777 /AB\(d+c) + 5028 LUT4 0777 /AB\(d+c) + 5029 LUT2 8 AB + 5030 LUT3 CA C?A:B + 5031 LUT3 8F (AB)+c + 5032 LUT4 F53F DC?1:a:b:1 + 5033 LUT2 6 A^B + 5034 LUT3 B0 C/aB\ + 5035 LUT3 D0 C/Ab\ + 5036 LUT3 B0 C/aB\ + 5037 LUT4 0BBB /aB\(d+c) + 5038 LUT4 440F D?c:aB + 5039 LUT4 F3F5 DC?a:b:1:1 + 5040 LUT4 7000 CD/AB\ + 5041 LUT4 0007 cd/AB\ + 5042 LUT2 8 AB + 5043 LUT2 8 AB + 5044 LUT2 4 aB + 5045 LUT4 EF00 ((/ab\)+c)D + 5046 LUT4 0503 DC?b:a:0:0 + 5047 LUT4 0E00 cD/ab\ + 5048 LUT4 BF00 ((/aB\)+c)D + 5049 LUT4 0777 /AB\(d+c) + 5050 LUT2 8 AB + 5051 LUT4 0777 /AB\(d+c) + 5052 LUT4 0777 /AB\(d+c) + 5053 LUT2 4 aB + 5054 LUT4 FFF1 (ab)+C+D + 5055 LUT2 4 aB + 5056 LUT4 CA00 D(C?A:B) + 5057 LUT4 0007 cd/AB\ + 5058 LUT2 4 aB + 5059 LUT3 80 ABC + 5060 LUT4 8000 ABCD + 5061 LUT4 0700 cD/AB\ + 5062 LUT4 0777 /AB\(d+c) + 5063 LUT2 8 AB + 5064 LUT4 8000 ABCD + 5065 LUT4 0777 /AB\(d+c) + 5066 LUT4 0777 /AB\(d+c) + 5067 LUT4 0777 /AB\(d+c) + 5068 LUT4 0777 /AB\(d+c) + 5069 LUT4 0777 /AB\(d+c) + 5070 LUT4 0777 /AB\(d+c) + 5071 LUT4 4000 aBCD + 5072 LUT4 0777 /AB\(d+c) + 5073 LUT4 0777 /AB\(d+c) + 5074 LUT4 0777 /AB\(d+c) + 5075 LUT2 8 AB + 5076 LUT4 8000 ABCD + 5077 LUT4 0777 /AB\(d+c) + 5078 LUT4 0777 /AB\(d+c) + 5079 LUT4 0777 /AB\(d+c) + 5080 LUT4 0777 /AB\(d+c) + 5081 LUT4 FEFF /ab\+C+d + 5082 LUT4 FE00 ((/ab\)+C)D + 5083 LUT3 B0 C/aB\ + 5084 LUT4 0BBB /aB\(d+c) + 5085 LUT4 1000 abCD + 5086 LUT4 8000 ABCD + 5087 LUT4 7000 CD/AB\ + 5088 LUT4 0700 cD/AB\ + 5089 LUT2 8 AB + 5090 LUT4 0777 /AB\(d+c) + 5091 LUT4 0777 /AB\(d+c) + 5092 LUT4 8000 ABCD + 5093 LUT4 0777 /AB\(d+c) + 5094 LUT4 0777 /AB\(d+c) + 5095 LUT4 0777 /AB\(d+c) + 5096 LUT4 0777 /AB\(d+c) + 5097 LUT4 8000 ABCD + 5098 LUT4 0777 /AB\(d+c) + 5099 LUT4 0777 /AB\(d+c) + 5100 LUT4 0777 /AB\(d+c) + 5101 LUT4 0777 /AB\(d+c) + 5102 LUT4 8000 ABCD + 5103 LUT4 0777 /AB\(d+c) + 5104 LUT4 0777 /AB\(d+c) + 5105 LUT4 0777 /AB\(d+c) + 5106 LUT4 0777 /AB\(d+c) + 5107 LUT2 8 AB + 5108 LUT3 CA C?A:B + 5109 LUT3 8F (AB)+c + 5110 LUT4 F3F5 DC?a:b:1:1 + 5111 LUT2 8 AB + 5112 LUT3 AC c?A:B + 5113 LUT3 17 AB?1:c:c:0 + 5114 LUT2 9 a^B + 5115 LUT2 7 /AB\ + 5116 LUT2 1 ab + 5117 LUT4 F800 ((AB)+C)D + 5118 LUT2 8 AB + 5119 LUT2 8 AB + 5120 LUT2 4 aB + 5121 LUT2 4 aB + 5122 LUT2 1 ab + 5123 LUT3 80 ABC + 5124 LUT2 8 AB + 5125 LUT2 4 aB + 5126 LUT3 40 aBC + 5127 LUT4 007F ((/AB\)+c)d + 5128 LUT2 8 AB + 5129 LUT2 1 ab + 5130 LUT2 8 AB + 5131 LUT2 4 aB + 5132 LUT3 B0 C/aB\ + 5133 LUT4 00EF ((/ab\)+c)d + 5134 LUT4 F400 ((aB)+C)D + 5135 LUT3 80 ABC + 5136 LUT2 1 ab + 5137 LUT4 FF0B (c/aB\)+D + 5138 LUT2 4 aB + 5139 LUT2 8 AB + 5140 LUT2 8 AB + 5141 LUT2 8 AB + 5142 LUT2 4 aB + 5143 LUT3 01 abc + 5144 LUT3 40 aBC + 5145 LUT2 8 AB + 5146 LUT3 0E c/ab\ + 5147 LUT2 1 ab + 5148 LUT4 F3F5 DC?a:b:1:1 + 5149 LUT4 F3F5 DC?a:b:1:1 + 5150 LUT3 70 C/AB\ + 5151 LUT4 F3F5 DC?a:b:1:1 + 5152 LUT3 70 C/AB\ + 5153 LUT4 F3F5 DC?a:b:1:1 + 5154 LUT3 70 C/AB\ + 5155 LUT4 F3F5 DC?a:b:1:1 + 5156 LUT3 70 C/AB\ + 5157 LUT4 F53F DC?1:a:b:1 + 5158 LUT4 F53F DC?1:a:b:1 + 5159 LUT4 F53F DC?1:a:b:1 + 5160 LUT4 53AC (C?b:a)^d + 5161 LUT3 70 C/AB\ + 5162 LUT4 F53F DC?1:a:b:1 + 5163 LUT3 70 C/AB\ + 5164 LUT4 F3F5 DC?a:b:1:1 + 5165 LUT4 F3F5 DC?a:b:1:1 + 5166 LUT4 F3F5 DC?a:b:1:1 + 5167 LUT4 F53F DC?1:a:b:1 + 5168 LUT4 F53F DC?1:a:b:1 + 5169 LUT4 AC53 (C?b:a)^D + 5170 LUT3 70 C/AB\ + 5171 LUT4 F3F5 DC?a:b:1:1 + 5172 LUT3 70 C/AB\ + 5173 LUT4 F3F5 DC?a:b:1:1 + 5174 LUT4 0305 DC?a:b:0:0 + 5175 LUT3 70 C/AB\ + 5176 LUT4 F3F5 DC?a:b:1:1 + 5177 LUT3 70 C/AB\ + 5178 LUT4 F3F5 DC?a:b:1:1 + 5179 LUT4 AC53 (C?b:a)^D + 5180 LUT3 70 C/AB\ + 5181 LUT4 F53F DC?1:a:b:1 + 5182 LUT3 70 C/AB\ + 5183 LUT4 F3F5 DC?a:b:1:1 + 5184 LUT4 F53F DC?1:a:b:1 + 5185 LUT4 F53F DC?1:a:b:1 + 5186 LUT4 AC53 (C?b:a)^D + 5187 LUT3 70 C/AB\ + 5188 LUT4 F3F5 DC?a:b:1:1 + 5189 LUT3 70 C/AB\ + 5190 LUT4 F3F5 DC?a:b:1:1 + 5191 LUT4 F3F5 DC?a:b:1:1 + 5192 LUT4 F3F5 DC?a:b:1:1 + 5193 LUT4 F3F5 DC?a:b:1:1 + 5194 LUT4 F3F5 DC?a:b:1:1 + 5195 LUT4 F53F DC?1:a:b:1 + 5196 LUT4 F53F DC?1:a:b:1 + 5197 LUT4 53AC (C?b:a)^d + 5198 LUT3 70 C/AB\ + 5199 LUT4 F3F5 DC?a:b:1:1 + 5200 LUT3 70 C/AB\ + 5201 LUT4 F53F DC?1:a:b:1 + 5202 LUT4 53AC (C?b:a)^d + 5203 LUT3 70 C/AB\ + 5204 LUT4 F3F5 DC?a:b:1:1 + 5205 LUT3 70 C/AB\ + 5206 LUT4 F53F DC?1:a:b:1 + 5207 LUT4 53AC (C?b:a)^d + 5208 LUT3 70 C/AB\ + 5209 LUT4 F3F5 DC?a:b:1:1 + 5210 LUT3 70 C/AB\ + 5211 LUT4 F3F5 DC?a:b:1:1 + 5212 LUT4 F53F DC?1:a:b:1 + 5213 LUT4 F3F5 DC?a:b:1:1 + 5214 LUT4 F3F5 DC?a:b:1:1 + 5215 LUT4 F3F5 DC?a:b:1:1 + 5216 LUT4 1000 abCD + 5217 LUT4 AC53 (C?b:a)^D + 5218 LUT3 70 C/AB\ + 5219 LUT4 F3F5 DC?a:b:1:1 + 5220 LUT3 70 C/AB\ + 5221 LUT4 F3F5 DC?a:b:1:1 + 5222 LUT4 AC53 (C?b:a)^D + 5223 LUT3 70 C/AB\ + 5224 LUT4 F53F DC?1:a:b:1 + 5225 LUT3 70 C/AB\ + 5226 LUT4 F53F DC?1:a:b:1 + 5227 LUT4 53AC (C?b:a)^d + 5228 LUT3 70 C/AB\ + 5229 LUT4 F3F5 DC?a:b:1:1 + 5230 LUT3 70 C/AB\ + 5231 LUT4 F3F5 DC?a:b:1:1 + 5232 LUT4 53AC (C?b:a)^d + 5233 LUT3 70 C/AB\ + 5234 LUT4 F53F DC?1:a:b:1 + 5235 LUT3 70 C/AB\ + 5236 LUT4 F3F5 DC?a:b:1:1 + 5237 LUT4 F3F5 DC?a:b:1:1 + 5238 LUT4 F53F DC?1:a:b:1 + 5239 LUT4 AC53 (C?b:a)^D + 5240 LUT3 70 C/AB\ + 5241 LUT4 F53F DC?1:a:b:1 + 5242 LUT3 70 C/AB\ + 5243 LUT4 F3F5 DC?a:b:1:1 + 5244 LUT4 F3F5 DC?a:b:1:1 + 5245 LUT4 F3F5 DC?a:b:1:1 + 5246 LUT4 AC53 (C?b:a)^D + 5247 LUT3 70 C/AB\ + 5248 LUT4 F3F5 DC?a:b:1:1 + 5249 LUT3 70 C/AB\ + 5250 LUT4 F53F DC?1:a:b:1 + 5251 LUT4 F3F5 DC?a:b:1:1 + 5252 LUT4 F3F5 DC?a:b:1:1 + 5253 LUT3 70 C/AB\ + 5254 LUT4 F53F DC?1:a:b:1 + 5255 LUT3 70 C/AB\ + 5256 LUT4 F3F5 DC?a:b:1:1 + 5257 LUT4 53AC (C?b:a)^d + 5258 LUT3 70 C/AB\ + 5259 LUT4 F53F DC?1:a:b:1 + 5260 LUT3 70 C/AB\ + 5261 LUT4 F53F DC?1:a:b:1 + 5262 LUT2 8 AB + 5263 LUT3 10 abC + 5264 LUT3 0D c/Ab\ + 5265 LUT4 001F ((ab)+c)d + 5266 LUT3 B0 C/aB\ + 5267 LUT4 0007 cd/AB\ + 5268 LUT4 0100 abcD + 5269 LUT2 8 AB + 5270 LUT2 1 ab + 5271 LUT2 1 ab + 5272 LUT2 1 ab + 5273 LUT3 70 C/AB\ + 5274 LUT2 1 ab + 5275 LUT2 4 aB + 5276 LUT2 1 ab + 5277 LUT2 1 ab + 5278 LUT2 8 AB + 5279 LUT2 4 aB + 5280 LUT2 8 AB + 5281 LUT2 8 AB + 5282 LUT3 10 abC + 5283 LUT3 80 ABC + 5284 LUT2 8 AB + 5285 LUT2 1 ab + 5286 LUT2 4 aB + 5287 LUT4 00BF ((/aB\)+c)d + 5288 LUT4 0503 DC?b:a:0:0 + 5289 LUT4 000E cd/ab\ + 5290 LUT2 4 aB + 5291 LUT3 B0 C/aB\ + 5292 LUT3 0D c/Ab\ + 5293 LUT4 8000 ABCD + 5294 LUT2 1 ab + 5295 LUT4 0007 cd/AB\ + 5296 LUT3 40 aBC + 5297 LUT4 5300 D(C?b:a) + 5298 LUT3 40 aBC + 5299 LUT4 0100 abcD + 5300 LUT3 70 C/AB\ + 5301 LUT3 10 abC + 5302 LUT4 1000 abCD + 5303 LUT4 0100 abcD + 5304 LUT4 1000 abCD + 5305 LUT4 0100 abcD + 5306 LUT4 1000 abCD + 5307 LUT3 40 aBC + 5308 LUT4 4000 aBCD + 5309 LUT3 01 abc + 5310 LUT3 10 abC + 5311 LUT3 01 abc + 5312 LUT4 0100 abcD + 5313 LUT4 1000 abCD + 5314 LUT3 40 aBC + 5315 LUT3 40 aBC + 5316 LUT3 01 abc + 5317 LUT4 0100 abcD + 5318 LUT4 1000 abCD + 5319 LUT3 60 C(A^B) + 5320 LUT4 1428 (B^C)(A^D) + 5321 LUT2 8 AB + 5322 LUT2 8 AB + 5323 LUT2 8 AB + 5324 LUT4 1428 (B^C)(A^D) + 5325 LUT2 8 AB + 5326 LUT2 8 AB + 5327 LUT4 9000 CD(a^B) + 5328 LUT4 9009 (a^B)(D^c) + 5329 LUT4 9009 (a^B)(D^c) + 5330 LUT4 FE00 ((/ab\)+C)D + 5331 LUT4 0B00 cD/aB\ + 5332 LUT2 1 ab + 5333 LUT4 0001 abcd + 5334 LUT3 B0 C/aB\ + 5335 LUT3 B0 C/aB\ + 5336 LUT3 B0 C/aB\ + 5337 LUT3 B0 C/aB\ + 5338 LUT3 80 ABC + 5339 LUT3 90 C(a^B) + 5340 LUT4 9009 (a^B)(D^c) + 5341 LUT4 9009 (a^B)(D^c) + 5342 LUT4 9009 (a^B)(D^c) + 5343 LUT4 9000 CD(a^B) + 5344 LUT4 9009 (a^B)(D^c) + 5345 LUT4 9009 (a^B)(D^c) + 5346 LUT4 9009 (a^B)(D^c) + 5347 LUT4 9009 (a^B)(D^c) + 5348 LUT4 1428 (B^C)(A^D) + 5349 LUT2 B /aB\ + 5350 LUT2 B /aB\ + 5351 LUT4 0A0C DC?B:A:0:0 + 5352 LUT2 1 ab + 5353 LUT2 8 AB + 5354 LUT2 8 AB + 5355 LUT3 80 ABC + 5356 LUT2 1 ab + 5357 LUT2 8 AB + 5358 LUT2 4 aB + 5359 LUT2 8 AB + 5360 LUT2 8 AB + 5361 LUT3 80 ABC + 5362 LUT2 8 AB + 5363 LUT2 8 AB + 5364 LUT3 40 aBC + 5365 LUT4 FE00 ((/ab\)+C)D + 5366 LUT3 E0 C/ab\ + 5367 LUT4 1000 abCD + 5368 LUT3 80 ABC + 5369 LUT3 40 aBC + 5370 LUT3 40 aBC + 5371 LUT4 0B00 cD/aB\ + 5372 LUT4 1000 abCD + 5373 LUT3 40 aBC + 5374 LUT4 00BF ((/aB\)+c)d + 5375 LUT3 80 ABC + 5376 LUT3 40 aBC + 5377 LUT2 4 aB + 5378 LUT4 1000 abCD + 5379 LUT2 4 aB + 5380 LUT4 F800 ((AB)+C)D + 5381 LUT2 8 AB + 5382 LUT2 4 aB + 5383 LUT4 0100 abcD + 5384 LUT3 80 ABC + 5385 LUT3 40 aBC + 5386 LUT4 00FE ((/ab\)+C)d + 5387 LUT4 00BF ((/aB\)+c)d + 5388 LUT4 FE00 ((/ab\)+C)D + 5389 LUT4 7000 CD/AB\ + 5390 LUT3 07 c/AB\ + 5391 LUT4 0007 cd/AB\ + 5392 LUT4 8000 ABCD + 5393 LUT2 8 AB + 5394 LUT2 8 AB + 5395 LUT2 4 aB + 5396 LUT2 8 AB + 5397 LUT3 10 abC + 5398 LUT2 8 AB + 5399 LUT2 8 AB + 5400 LUT4 0100 abcD + 5401 LUT2 8 AB + 5402 LUT2 8 AB + 5403 LUT4 0007 cd/AB\ + 5404 LUT2 8 AB + 5405 LUT3 40 aBC + 5406 LUT3 80 ABC + 5407 LUT4 0100 abcD + 5408 LUT3 40 aBC + 5409 LUT4 0F44 D?aB:c + 5410 LUT3 0B c/aB\ + 5411 LUT2 4 aB + 5412 LUT4 4000 aBCD + 5413 LUT2 8 AB + 5414 LUT2 4 aB + 5415 LUT2 4 aB + 5416 LUT4 F400 ((aB)+C)D + 5417 LUT4 7F00 ((/AB\)+c)D + 5418 LUT3 70 C/AB\ + 5419 LUT4 007F ((/AB\)+c)d + 5420 LUT3 80 ABC + 5421 LUT2 4 aB + 5422 LUT2 4 aB + 5423 LUT2 8 AB + 5424 LUT2 8 AB + 5425 LUT2 8 AB + 5426 LUT2 1 ab + 5427 LUT2 8 AB + 5428 LUT4 007F ((/AB\)+c)d + 5429 LUT3 40 aBC + 5430 LUT2 4 aB + 5431 LUT3 01 abc + 5432 LUT4 F800 ((AB)+C)D + 5433 LUT4 8000 ABCD + 5434 LUT2 4 aB + 5435 LUT3 80 ABC + 5436 LUT2 8 AB + 5437 LUT2 4 aB + 5438 LUT4 004F ((aB)+c)d + 5439 LUT3 10 abC + 5440 LUT4 BF00 ((/aB\)+c)D + 5441 LUT4 001F ((ab)+c)d + 5442 LUT2 8 AB + 5443 LUT2 4 aB + 5444 LUT2 8 AB + 5445 LUT3 70 C/AB\ + 5446 LUT3 01 abc + 5447 LUT3 80 ABC + 5448 LUT3 80 ABC + 5449 LUT4 8000 ABCD + 5450 LUT4 010E AC?B^D:d:0:0 + 5451 LUT4 F400 ((aB)+C)D + 5452 LUT4 0777 /AB\(d+c) + 5453 LUT4 8000 ABCD + 5454 LUT2 8 AB + 5455 LUT2 4 aB + 5456 LUT2 1 ab + 5457 LUT2 8 AB + 5458 LUT2 8 AB + 5459 LUT4 1000 abCD + 5460 LUT3 10 abC + 5461 LUT4 8000 ABCD + 5462 LUT2 1 ab + 5463 LUT3 40 aBC + 5464 LUT3 40 aBC + 5465 LUT4 BBB0 /aB\(D+C) + 5466 LUT4 0777 /AB\(d+c) + 5467 LUT2 8 AB + 5468 LUT2 4 aB + 5469 LUT4 4300 D(BC?1:0:0:a) + 5470 LUT3 10 abC + 5471 LUT4 07FF (c/AB\)+d + 5472 LUT2 8 AB + 5473 LUT3 80 ABC + 5474 LUT4 1000 abCD + 5475 LUT3 10 abC + 5476 LUT3 80 ABC + 5477 LUT2 4 aB + 5478 LUT4 F800 ((AB)+C)D + 5479 LUT3 40 aBC + 5480 LUT2 1 ab + 5481 LUT2 4 aB + 5482 LUT2 8 AB + 5483 LUT4 F100 ((ab)+C)D + 5484 LUT2 8 AB + 5485 LUT2 4 aB + 5486 LUT4 4F00 ((aB)+c)D + 5487 LUT3 80 ABC + 5488 LUT2 4 aB + 5489 LUT4 0EEE /ab\(d+c) + 5490 LUT4 0700 cD/AB\ + 5491 LUT4 0007 cd/AB\ + 5492 LUT2 8 AB + 5493 LUT3 40 aBC + 5494 LUT3 10 abC + 5495 LUT2 8 AB + 5496 LUT2 4 aB + 5497 LUT4 0D00 cD/Ab\ + 5498 LUT4 0100 abcD + 5499 LUT2 4 aB + 5500 LUT2 8 AB + 5501 LUT3 80 ABC + 5502 LUT2 8 AB + 5503 LUT2 8 AB + 5504 LUT3 F8 (AB)+C + 5505 LUT2 1 ab + 5506 LUT4 F044 D?aB:C + 5507 LUT2 1 ab + 5508 LUT2 8 AB + 5509 LUT4 4000 aBCD + 5510 LUT2 8 AB + 5511 LUT4 1000 abCD + 5512 LUT4 0001 abcd + 5513 LUT4 8000 ABCD + 5514 LUT4 8000 ABCD + 5515 LUT4 8000 ABCD + 5516 LUT4 8000 ABCD + 5517 LUT2 1 ab + 5518 LUT4 8000 ABCD + 5519 LUT4 8000 ABCD + 5520 LUT4 8000 ABCD + 5521 LUT4 8000 ABCD + 5522 LUT4 0100 abcD + 5523 LUT4 0001 abcd + 5524 LUT4 8000 ABCD + 5525 LUT4 8000 ABCD + 5526 LUT4 8000 ABCD + 5527 LUT4 8000 ABCD + 5528 LUT4 8000 ABCD + 5529 LUT4 8000 ABCD + 5530 LUT4 8000 ABCD + 5531 LUT4 BE00 AD?0:0:B^C:1 + 5532 LUT2 6 A^B + 5533 LUT3 CA C?A:B + 5534 LUT3 CA C?A:B + 5535 LUT4 7F00 ((/AB\)+c)D + 5536 LUT3 E0 C/ab\ + 5537 LUT4 0001 abcd + 5538 LUT4 4000 aBCD + 5539 LUT4 0001 abcd + 5540 LUT4 0001 abcd + 5541 LUT4 8000 ABCD + 5542 LUT4 0001 abcd + 5543 LUT3 80 ABC + 5544 LUT3 80 ABC + 5545 LUT4 8000 ABCD + 5546 LUT4 0001 abcd + 5547 LUT4 0001 abcd + 5548 LUT4 0001 abcd + 5549 LUT4 0001 abcd + 5550 LUT4 0001 abcd + 5551 LUT4 8000 ABCD + 5552 LUT4 8000 ABCD + 5553 LUT4 8000 ABCD + 5554 LUT4 8000 ABCD + 5555 LUT4 0001 abcd + 5556 LUT4 8000 ABCD + 5557 LUT4 8000 ABCD + 5558 LUT4 8000 ABCD + 5559 LUT4 8000 ABCD + 5560 LUT4 0001 abcd + 5561 LUT4 8000 ABCD + 5562 LUT4 8000 ABCD + 5563 LUT4 8000 ABCD + 5564 LUT4 8000 ABCD + 5565 LUT4 0001 abcd + 5566 LUT4 8000 ABCD + 5567 LUT4 8000 ABCD + 5568 LUT4 8000 ABCD + 5569 LUT4 8000 ABCD + 5570 LUT2 1 ab + 5571 LUT3 AC c?A:B + 5572 LUT3 CA C?A:B + 5573 LUT2 8 AB + 5574 LUT2 1 ab + 5575 LUT3 70 C/AB\ + 5576 LUT3 CA C?A:B + 5577 LUT3 CA C?A:B + 5578 LUT2 8 AB + 5579 LUT2 8 AB + 5580 LUT3 80 ABC + 5581 LUT2 8 AB + 5582 LUT2 8 AB + 5583 LUT2 8 AB + 5584 LUT2 4 aB + 5585 LUT2 1 ab + 5586 LUT3 80 ABC + 5587 LUT2 8 AB + 5588 LUT2 4 aB + 5589 LUT3 0D c/Ab\ + 5590 LUT2 1 ab + 5591 LUT2 4 aB + 5592 LUT2 4 aB + 5593 LUT2 4 aB + 5594 LUT2 4 aB + 5595 LUT4 F800 ((AB)+C)D + 5596 LUT2 8 AB + 5597 LUT3 0B c/aB\ + 5598 LUT4 E000 CD/ab\ + 5599 LUT3 D0 C/Ab\ + 5600 LUT2 4 aB + 5601 LUT2 4 aB + 5602 LUT2 1 ab + 5603 LUT2 8 AB + 5604 LUT3 D0 C/Ab\ + 5605 LUT3 D0 C/Ab\ + 5606 LUT2 4 aB + 5607 LUT2 4 aB + 5608 LUT2 8 AB + 5609 LUT2 4 aB + 5610 LUT2 4 aB + 5611 LUT2 4 aB + 5612 LUT2 8 AB + 5613 LUT2 4 aB + 5614 LUT2 8 AB + 5615 LUT3 80 ABC + 5616 LUT2 8 AB + 5617 LUT2 8 AB + 5618 LUT3 CA C?A:B + 5619 LUT2 8 AB + 5620 LUT3 CA C?A:B + 5621 LUT2 8 AB + 5622 LUT2 8 AB + 5623 LUT2 E /ab\ + 5624 LUT2 4 aB + 5625 LUT2 4 aB + 5626 LUT2 4 aB + 5627 LUT2 4 aB + 5628 LUT3 80 ABC + 5629 LUT2 8 AB + 5630 LUT2 8 AB + 5631 LUT3 E0 C/ab\ + 5632 LUT3 80 ABC + 5633 LUT4 CA00 D(C?A:B) + 5634 LUT2 8 AB + 5635 LUT3 10 abC + 5636 LUT4 EF00 ((/ab\)+c)D + 5637 LUT3 01 abc + 5638 LUT2 8 AB + 5639 LUT3 CA C?A:B + 5640 LUT2 8 AB + 5641 LUT4 CA00 D(C?A:B) + 5642 LUT4 0F88 D?AB:c + 5643 LUT4 770F D?c:/AB\ + 5644 LUT2 4 aB + 5645 LUT2 4 aB + 5646 LUT2 4 aB + 5647 LUT2 4 aB + 5648 LUT3 53 C?b:a + 5649 LUT3 40 aBC + 5650 LUT3 80 ABC + 5651 LUT4 E000 CD/ab\ + 5652 LUT4 0700 cD/AB\ + 5653 LUT4 0100 abcD + 5654 LUT2 4 aB + 5655 LUT2 8 AB + 5656 LUT3 80 ABC + 5657 LUT2 8 AB + 5658 LUT2 8 AB + 5659 LUT2 8 AB + 5660 LUT4 F044 D?aB:C + 5661 LUT2 4 aB + 5662 LUT4 0BBB /aB\(d+c) + 5663 LUT2 8 AB + 5664 LUT2 8 AB + 5665 LUT3 F8 (AB)+C + 5666 LUT2 1 ab + 5667 LUT2 8 AB + 5668 LUT3 FE /ab\+C + 5669 LUT3 E0 C/ab\ + 5670 LUT3 69 A^B^c + 5671 LUT3 69 A^B^c + 5672 LUT2 8 AB + 5673 LUT3 80 ABC + 5674 LUT2 8 AB + 5675 LUT2 8 AB + 5676 LUT2 8 AB + 5677 LUT2 4 aB + 5678 LUT2 8 AB + 5679 LUT4 0001 abcd + 5680 LUT2 8 AB + 5681 LUT2 8 AB + 5682 LUT4 8F00 ((AB)+c)D + 5683 LUT4 004F ((aB)+c)d + 5684 LUT2 8 AB + 5685 LUT4 8000 ABCD + 5686 LUT2 8 AB + 5687 LUT2 8 AB + 5688 LUT4 8000 ABCD + 5689 LUT2 8 AB + 5690 LUT4 004F ((aB)+c)d + 5691 LUT4 8F00 ((AB)+c)D + 5692 LUT4 004F ((aB)+c)d + 5693 LUT4 8F00 ((AB)+c)D + 5694 LUT3 AC c?A:B + 5695 LUT4 8000 ABCD + 5696 LUT4 0777 /AB\(d+c) + 5697 LUT4 B000 CD/aB\ + 5698 LUT3 CA C?A:B + 5699 LUT2 8 AB + 5700 LUT3 80 ABC + 5701 LUT4 F888 (AB)+(CD) + 5702 LUT4 4000 aBCD + 5703 LUT2 8 AB + 5704 LUT3 8F (AB)+c + 5705 LUT2 1 ab + 5706 LUT3 F8 (AB)+C + 5707 LUT2 1 ab + 5708 LUT3 10 abC + 5709 LUT3 10 abC + 5710 LUT3 70 C/AB\ + 5711 LUT4 0777 /AB\(d+c) + 5712 LUT3 70 C/AB\ + 5713 LUT3 8F (AB)+c + 5714 LUT4 0777 /AB\(d+c) + 5715 LUT3 8F (AB)+c + 5716 LUT4 0777 /AB\(d+c) + 5717 LUT2 4 aB + 5718 LUT2 4 aB + 5719 LUT4 00F4 ((aB)+C)d + 5720 LUT4 4F00 ((aB)+c)D + 5721 LUT4 7F00 ((/AB\)+c)D + 5722 LUT4 3A33 DC?b:A:b:b + 5723 LUT3 53 C?b:a + 5724 LUT4 3A33 DC?b:A:b:b + 5725 LUT3 35 c?b:a + 5726 LUT4 3A33 DC?b:A:b:b + 5727 LUT3 35 c?b:a + 5728 LUT4 3A33 DC?b:A:b:b + 5729 LUT3 35 c?b:a + 5730 LUT4 3A33 DC?b:A:b:b + 5731 LUT3 35 c?b:a + 5732 LUT4 3A33 DC?b:A:b:b + 5733 LUT3 35 c?b:a + 5734 LUT4 3A33 DC?b:A:b:b + 5735 LUT3 35 c?b:a + 5736 LUT4 3A33 DC?b:A:b:b + 5737 LUT3 35 c?b:a + 5738 LUT4 3A33 DC?b:A:b:b + 5739 LUT3 35 c?b:a + 5740 LUT4 3A33 DC?b:A:b:b + 5741 LUT3 35 c?b:a + 5742 LUT4 3A33 DC?b:A:b:b + 5743 LUT3 35 c?b:a + 5744 LUT4 3A33 DC?b:A:b:b + 5745 LUT3 35 c?b:a + 5746 LUT4 3A33 DC?b:A:b:b + 5747 LUT3 35 c?b:a + 5748 LUT4 3A33 DC?b:A:b:b + 5749 LUT3 35 c?b:a + 5750 LUT4 3A33 DC?b:A:b:b + 5751 LUT3 35 c?b:a + 5752 LUT4 3A33 DC?b:A:b:b + 5753 LUT3 35 c?b:a + 5754 LUT3 A3 C?b:A + 5755 LUT3 53 C?b:a + 5756 LUT3 A3 C?b:A + 5757 LUT3 35 c?b:a + 5758 LUT3 A3 C?b:A + 5759 LUT3 35 c?b:a + 5760 LUT3 A3 C?b:A + 5761 LUT3 35 c?b:a + 5762 LUT3 A3 C?b:A + 5763 LUT3 35 c?b:a + 5764 LUT3 A3 C?b:A + 5765 LUT3 35 c?b:a + 5766 LUT3 A3 C?b:A + 5767 LUT3 35 c?b:a + 5768 LUT3 A3 C?b:A + 5769 LUT3 35 c?b:a + 5770 LUT3 A3 C?b:A + 5771 LUT3 35 c?b:a + 5772 LUT3 A3 C?b:A + 5773 LUT3 35 c?b:a + 5774 LUT3 A3 C?b:A + 5775 LUT3 35 c?b:a + 5776 LUT3 A3 C?b:A + 5777 LUT3 35 c?b:a + 5778 LUT3 A3 C?b:A + 5779 LUT3 35 c?b:a + 5780 LUT3 A3 C?b:A + 5781 LUT3 35 c?b:a + 5782 LUT3 A3 C?b:A + 5783 LUT3 35 c?b:a + 5784 LUT3 A3 C?b:A + 5785 LUT3 35 c?b:a + 5786 LUT2 4 aB + 5787 LUT4 0100 abcD + 5788 LUT3 D0 C/Ab\ + 5789 LUT3 07 c/AB\ + 5790 LUT2 1 ab + 5791 LUT3 40 aBC + 5792 LUT3 40 aBC + 5793 LUT2 8 AB + 5794 LUT4 0007 cd/AB\ + 5795 LUT2 1 ab + 5796 LUT3 40 aBC + 5797 LUT3 40 aBC + 5798 LUT3 70 C/AB\ + 5799 LUT4 0C0A DC?A:B:0:0 + 5800 LUT2 8 AB + 5801 LUT2 8 AB + 5802 LUT3 80 ABC + 5803 LUT3 40 aBC + 5804 LUT4 4000 aBCD + 5805 LUT4 030A DC?A:b:0:0 + 5806 LUT3 E0 C/ab\ + 5807 LUT3 35 c?b:a + 5808 LUT4 0C0A DC?A:B:0:0 + 5809 LUT2 4 aB + 5810 LUT4 0C0A DC?A:B:0:0 + 5811 LUT4 0C0A DC?A:B:0:0 + 5812 LUT4 0C0A DC?A:B:0:0 + 5813 LUT4 0C0A DC?A:B:0:0 + 5814 LUT4 0C0A DC?A:B:0:0 + 5815 LUT2 4 aB + 5816 LUT2 4 aB + 5817 LUT4 0C0A DC?A:B:0:0 + 5818 LUT4 0C0A DC?A:B:0:0 + 5819 LUT2 4 aB + 5820 LUT4 0C0A DC?A:B:0:0 + 5821 LUT4 0C0A DC?A:B:0:0 + 5822 LUT4 0C0A DC?A:B:0:0 + 5823 LUT4 1000 abCD + 5824 LUT3 0E c/ab\ + 5825 LUT2 E /ab\ + 5826 LUT4 EF00 ((/ab\)+c)D + 5827 LUT4 EF00 ((/ab\)+c)D + 5828 LUT4 EF00 ((/ab\)+c)D + 5829 LUT2 4 aB + 5830 LUT3 10 abC + 5831 LUT2 4 aB + 5832 LUT2 4 aB + 5833 LUT3 EF /ab\+c + 5834 LUT4 001F ((ab)+c)d + 5835 LUT2 8 AB + 5836 LUT4 44F0 D?C:aB + 5837 LUT2 4 aB + 5838 LUT3 10 abC + 5839 LUT4 8000 ABCD + 5840 LUT2 8 AB + 5841 LUT3 40 aBC + 5842 LUT3 80 ABC + 5843 LUT2 4 aB + 5844 LUT3 10 abC + 5845 LUT3 80 ABC + 5846 LUT4 8000 ABCD + 5847 LUT4 0001 abcd + 5848 LUT4 0100 abcD + 5849 LUT4 0001 abcd + 5850 LUT4 0001 abcd + 5851 LUT3 10 abC + 5852 LUT4 0001 abcd + 5853 LUT4 1000 abCD + 5854 LUT4 0001 abcd + 5855 LUT4 0001 abcd + 5856 LUT3 01 abc + 5857 LUT4 00EF ((/ab\)+c)d + 5858 LUT4 1000 abCD + 5859 LUT4 4000 aBCD + 5860 LUT4 EE0F D?c:/ab\ + 5861 LUT3 40 aBC + 5862 LUT3 E0 C/ab\ + 5863 LUT3 40 aBC + 5864 LUT4 0C0A DC?A:B:0:0 + 5865 LUT2 4 aB + 5866 LUT4 030A DC?A:b:0:0 + 5867 LUT3 35 c?b:a + 5868 LUT2 4 aB + 5869 LUT3 3A c?b:A + 5870 LUT4 FFE0 (C/ab\)+D + 5871 LUT3 10 abC + 5872 LUT2 4 aB + 5873 LUT2 E /ab\ + 5874 LUT2 4 aB + 5875 LUT2 8 AB + 5876 LUT3 01 abc + 5877 LUT3 3A c?b:A + 5878 LUT3 10 abC + 5879 LUT4 4000 aBCD + 5880 LUT4 000B cd/aB\ + 5881 LUT4 004F ((aB)+c)d + 5882 LUT2 8 AB + 5883 LUT3 FE /ab\+C + 5884 LUT4 FE00 ((/ab\)+C)D + 5885 LUT3 D0 C/Ab\ + 5886 LUT4 00F4 ((aB)+C)d + 5887 LUT4 4F00 ((aB)+c)D + 5888 LUT3 10 abC + 5889 LUT4 4000 aBCD + 5890 LUT3 40 aBC + 5891 LUT2 E /ab\ + 5892 LUT2 4 aB + 5893 LUT2 8 AB + 5894 LUT3 10 abC + 5895 LUT3 3A c?b:A + 5896 LUT3 40 aBC + 5897 LUT3 10 abC + 5898 LUT4 000E cd/ab\ + 5899 LUT4 0700 cD/AB\ + 5900 LUT3 FE /ab\+C + 5901 LUT4 FE00 ((/ab\)+C)D + 5902 LUT2 4 aB + 5903 LUT2 4 aB + 5904 LUT2 4 aB + 5905 LUT2 8 AB + 5906 LUT3 80 ABC + 5907 LUT2 4 aB + 5908 LUT3 40 aBC + 5909 LUT2 E /ab\ + 5910 LUT2 4 aB + 5911 LUT2 8 AB + 5912 LUT3 10 abC + 5913 LUT3 3A c?b:A + 5914 LUT3 40 aBC + 5915 LUT2 8 AB + 5916 LUT3 CA C?A:B + 5917 LUT3 FE /ab\+C + 5918 LUT4 FE00 ((/ab\)+C)D + 5919 LUT2 8 AB + 5920 LUT2 8 AB + 5921 LUT4 0E00 cD/ab\ + 5922 LUT3 40 aBC + 5923 LUT3 80 ABC + 5924 LUT2 E /ab\ + 5925 LUT2 4 aB + 5926 LUT2 8 AB + 5927 LUT3 40 aBC + 5928 LUT3 3A c?b:A + 5929 LUT3 80 ABC + 5930 LUT2 8 AB + 5931 LUT4 0C0A DC?A:B:0:0 + 5932 LUT3 FE /ab\+C + 5933 LUT4 FE00 ((/ab\)+C)D + 5934 LUT2 8 AB + 5935 LUT2 8 AB + 5936 LUT3 CA C?A:B + 5937 LUT3 A3 C?b:A + 5938 LUT3 5C c?a:B + 5939 LUT3 5C c?a:B + 5940 LUT3 9F (a^B)+c + 5941 LUT2 4 aB + 5942 LUT3 60 C(A^B) + 5943 LUT2 4 aB + 5944 LUT3 A3 C?b:A + 5945 LUT3 9F (a^B)+c + 5946 LUT2 4 aB + 5947 LUT4 1400 D(B^C)a + 5948 LUT3 A3 C?b:A + 5949 LUT3 3A c?b:A + 5950 LUT3 60 C(A^B) + 5951 LUT2 4 aB + 5952 LUT4 EBFF A+d+(b^C) + 5953 LUT4 1400 D(B^C)a + 5954 LUT3 C5 C?a:B + 5955 LUT3 9F (a^B)+c + 5956 LUT2 4 aB + 5957 LUT3 A3 C?b:A + 5958 LUT3 5C c?a:B + 5959 LUT3 5C c?a:B + 5960 LUT3 9F (a^B)+c + 5961 LUT3 60 C(A^B) + 5962 LUT3 A3 C?b:A + 5963 LUT3 9F (a^B)+c + 5964 LUT4 1400 D(B^C)a + 5965 LUT3 A3 C?b:A + 5966 LUT3 3A c?b:A + 5967 LUT3 60 C(A^B) + 5968 LUT4 EBFF A+d+(b^C) + 5969 LUT4 1400 D(B^C)a + 5970 LUT3 C5 C?a:B + 5971 LUT3 9F (a^B)+c + 5972 LUT3 A3 C?b:A + 5973 LUT3 5C c?a:B + 5974 LUT3 5C c?a:B + 5975 LUT3 9F (a^B)+c + 5976 LUT3 60 C(A^B) + 5977 LUT3 A3 C?b:A + 5978 LUT3 9F (a^B)+c + 5979 LUT4 1400 D(B^C)a + 5980 LUT3 0B c/aB\ + 5981 LUT3 3A c?b:A + 5982 LUT3 60 C(A^B) + 5983 LUT4 EBFF A+d+(b^C) + 5984 LUT2 4 aB + 5985 LUT4 1400 D(B^C)a + 5986 LUT3 C5 C?a:B + 5987 LUT3 9F (a^B)+c + 5988 LUT3 A3 C?b:A + 5989 LUT3 5C c?a:B + 5990 LUT3 5C c?a:B + 5991 LUT3 9F (a^B)+c + 5992 LUT3 60 C(A^B) + 5993 LUT3 A3 C?b:A + 5994 LUT3 9F (a^B)+c + 5995 LUT4 1400 D(B^C)a + 5996 LUT3 A3 C?b:A + 5997 LUT3 3A c?b:A + 5998 LUT3 60 C(A^B) + 5999 LUT4 EBFF A+d+(b^C) + 6000 LUT4 1400 D(B^C)a + 6001 LUT3 C5 C?a:B + 6002 LUT3 9F (a^B)+c + 6003 LUT3 F4 (aB)+C + 6004 LUT4 0100 abcD + 6005 LUT4 3500 D(c?b:a) + 6006 LUT2 4 aB + 6007 LUT4 D000 CD/Ab\ + 6008 LUT4 5300 D(C?b:a) + 6009 LUT2 6 A^B + 6010 LUT2 6 A^B + 6011 LUT2 6 A^B + 6012 LUT2 6 A^B + 6013 LUT2 4 aB + 6014 LUT2 4 aB + 6015 LUT4 0C0A DC?A:B:0:0 + 6016 LUT2 E /ab\ + 6017 LUT4 B000 CD/aB\ + 6018 LUT3 80 ABC + 6019 LUT4 7FFF /AB\+c+d + 6020 LUT3 8F (AB)+c + 6021 LUT2 1 ab + 6022 LUT2 4 aB + 6023 LUT2 8 AB + 6024 LUT2 4 aB + 6025 LUT4 1FFF (ab)+c+d + 6026 LUT2 8 AB + 6027 LUT2 8 AB + 6028 LUT2 4 aB + 6029 LUT4 0777 /AB\(d+c) + 6030 LUT4 4F44 (aB)+(cD) + 6031 LUT2 1 ab + 6032 LUT3 E0 C/ab\ + 6033 LUT3 80 ABC + 6034 LUT2 E /ab\ + 6035 LUT2 8 AB + 6036 LUT2 8 AB + 6037 LUT2 8 AB + 6038 LUT4 B0BB /aB\(d+C) + 6039 LUT2 4 aB + 6040 LUT2 4 aB + 6041 LUT2 4 aB + 6042 LUT3 80 ABC + 6043 LUT3 8F (AB)+c + 6044 LUT4 0777 /AB\(d+c) + 6045 LUT3 F4 (aB)+C + 6046 LUT4 F400 ((aB)+C)D + 6047 LUT2 4 aB + 6048 LUT3 D0 C/Ab\ + 6049 LUT3 8F (AB)+c + 6050 LUT4 0777 /AB\(d+c) + 6051 LUT3 F4 (aB)+C + 6052 LUT4 F400 ((aB)+C)D + 6053 LUT2 4 aB + 6054 LUT3 D0 C/Ab\ + 6055 LUT3 8F (AB)+c + 6056 LUT4 0777 /AB\(d+c) + 6057 LUT3 F4 (aB)+C + 6058 LUT4 F400 ((aB)+C)D + 6059 LUT2 4 aB + 6060 LUT3 D0 C/Ab\ + 6061 LUT2 8 AB + 6062 LUT2 8 AB + 6063 LUT3 D0 C/Ab\ + 6064 LUT3 14 (B^C)a + 6065 LUT2 4 aB + 6066 LUT4 00EF ((/ab\)+c)d + 6067 LUT3 F8 (AB)+C + 6068 LUT3 40 aBC + 6069 LUT2 4 aB + 6070 LUT2 8 AB + 6071 LUT4 9009 (a^B)(D^c) + 6072 LUT4 9009 (a^B)(D^c) + 6073 LUT4 CDC0 BD?0:C:ac:1 + 6074 LUT2 4 aB + 6075 LUT4 BBB0 /aB\(D+C) + 6076 LUT3 40 aBC + 6077 LUT3 10 abC + 6078 LUT4 0001 abcd + 6079 LUT3 8F (AB)+c + 6080 LUT4 0777 /AB\(d+c) + 6081 LUT4 4F44 (aB)+(cD) + 6082 LUT4 B0BB /aB\(d+C) + 6083 LUT2 4 aB + 6084 LUT3 8F (AB)+c + 6085 LUT4 0777 /AB\(d+c) + 6086 LUT4 4F44 (aB)+(cD) + 6087 LUT4 B0BB /aB\(d+C) + 6088 LUT2 4 aB + 6089 LUT3 8F (AB)+c + 6090 LUT4 0777 /AB\(d+c) + 6091 LUT4 4F44 (aB)+(cD) + 6092 LUT4 B0BB /aB\(d+C) + 6093 LUT2 4 aB + 6094 LUT3 8F (AB)+c + 6095 LUT4 0777 /AB\(d+c) + 6096 LUT3 F4 (aB)+C + 6097 LUT4 F400 ((aB)+C)D + 6098 LUT2 4 aB + 6099 LUT2 4 aB + 6100 LUT3 8F (AB)+c + 6101 LUT4 0777 /AB\(d+c) + 6102 LUT4 4F44 (aB)+(cD) + 6103 LUT4 B0BB /aB\(d+C) + 6104 LUT2 4 aB + 6105 LUT3 8F (AB)+c + 6106 LUT4 0777 /AB\(d+c) + 6107 LUT4 4F44 (aB)+(cD) + 6108 LUT4 B0BB /aB\(d+C) + 6109 LUT2 4 aB + 6110 LUT4 4000 aBCD + 6111 LUT4 0001 abcd + 6112 LUT3 8F (AB)+c + 6113 LUT4 0777 /AB\(d+c) + 6114 LUT3 F4 (aB)+C + 6115 LUT4 F400 ((aB)+C)D + 6116 LUT2 4 aB + 6117 LUT3 D0 C/Ab\ + 6118 LUT3 8F (AB)+c + 6119 LUT4 0777 /AB\(d+c) + 6120 LUT4 4F44 (aB)+(cD) + 6121 LUT4 B0BB /aB\(d+C) + 6122 LUT2 4 aB + 6123 LUT3 8F (AB)+c + 6124 LUT4 0777 /AB\(d+c) + 6125 LUT4 4F44 (aB)+(cD) + 6126 LUT4 B0BB /aB\(d+C) + 6127 LUT2 4 aB + 6128 LUT3 8F (AB)+c + 6129 LUT4 0777 /AB\(d+c) + 6130 LUT4 4F44 (aB)+(cD) + 6131 LUT4 B0BB /aB\(d+C) + 6132 LUT3 8F (AB)+c + 6133 LUT4 0777 /AB\(d+c) + 6134 LUT4 4F44 (aB)+(cD) + 6135 LUT4 B0BB /aB\(d+C) + 6136 LUT2 4 aB + 6137 LUT3 8F (AB)+c + 6138 LUT4 0777 /AB\(d+c) + 6139 LUT4 4F44 (aB)+(cD) + 6140 LUT4 B0BB /aB\(d+C) + 6141 LUT2 4 aB + 6142 LUT3 8F (AB)+c + 6143 LUT4 0777 /AB\(d+c) + 6144 LUT4 4F44 (aB)+(cD) + 6145 LUT4 B0BB /aB\(d+C) + 6146 LUT2 4 aB + 6147 LUT3 80 ABC + 6148 LUT3 80 ABC + 6149 LUT4 0001 abcd + 6150 LUT4 0100 abcD + 6151 LUT4 0001 abcd + 6152 LUT4 8000 ABCD + 6153 LUT2 6 A^B + 6154 LUT4 8000 ABCD + 6155 LUT4 FF01 (abc)+D + 6156 LUT2 4 aB + 6157 LUT4 EF00 ((/ab\)+c)D + 6158 LUT2 8 AB + 6159 LUT4 0D00 cD/Ab\ + 6160 LUT3 C5 C?a:B + 6161 LUT4 1000 abCD + 6162 LUT4 0BBB /aB\(d+c) + 6163 LUT2 4 aB + 6164 LUT3 C5 C?a:B + 6165 LUT4 0BBB /aB\(d+c) + 6166 LUT3 C5 C?a:B + 6167 LUT4 B0BB /aB\(d+C) + 6168 LUT2 8 AB + 6169 LUT3 C5 C?a:B + 6170 LUT4 B0BB /aB\(d+C) + 6171 LUT3 C5 C?a:B + 6172 LUT4 B0BB /aB\(d+C) + 6173 LUT3 C5 C?a:B + 6174 LUT4 B0BB /aB\(d+C) + 6175 LUT4 F044 D?aB:C + 6176 LUT3 C5 C?a:B + 6177 LUT4 0BBB /aB\(d+c) + 6178 LUT3 35 c?b:a + 6179 LUT4 0BBB /aB\(d+c) + 6180 LUT3 35 c?b:a + 6181 LUT4 B0BB /aB\(d+C) + 6182 LUT3 35 c?b:a + 6183 LUT4 0BBB /aB\(d+c) + 6184 LUT3 35 c?b:a + 6185 LUT4 B0BB /aB\(d+C) + 6186 LUT3 35 c?b:a + 6187 LUT4 B0BB /aB\(d+C) + 6188 LUT3 35 c?b:a + 6189 LUT4 B0BB /aB\(d+C) + 6190 LUT3 35 c?b:a + 6191 LUT4 B0BB /aB\(d+C) + 6192 LUT3 35 c?b:a + 6193 LUT4 B0BB /aB\(d+C) + 6194 LUT3 35 c?b:a + 6195 LUT4 B0BB /aB\(d+C) + 6196 LUT3 35 c?b:a + 6197 LUT4 B0BB /aB\(d+C) + 6198 LUT3 35 c?b:a + 6199 LUT4 B0BB /aB\(d+C) + 6200 LUT3 35 c?b:a + 6201 LUT4 B0BB /aB\(d+C) + 6202 LUT3 35 c?b:a + 6203 LUT4 B0BB /aB\(d+C) + 6204 LUT3 35 c?b:a + 6205 LUT4 B0BB /aB\(d+C) + 6206 LUT3 35 c?b:a + 6207 LUT4 B0BB /aB\(d+C) + 6208 LUT3 35 c?b:a + 6209 LUT4 B0BB /aB\(d+C) + 6210 LUT3 35 c?b:a + 6211 LUT4 B0BB /aB\(d+C) + 6212 LUT3 35 c?b:a + 6213 LUT4 B0BB /aB\(d+C) + 6214 LUT3 35 c?b:a + 6215 LUT4 B0BB /aB\(d+C) + 6216 LUT3 35 c?b:a + 6217 LUT4 B0BB /aB\(d+C) + 6218 LUT3 35 c?b:a + 6219 LUT4 B0BB /aB\(d+C) + 6220 LUT3 35 c?b:a + 6221 LUT4 B0BB /aB\(d+C) + 6222 LUT3 35 c?b:a + 6223 LUT4 B0BB /aB\(d+C) + 6224 LUT3 35 c?b:a + 6225 LUT4 B0BB /aB\(d+C) + 6226 LUT2 4 aB + 6227 LUT4 8F88 (AB)+(cD) + 6228 LUT3 0B c/aB\ + 6229 LUT4 8F00 ((AB)+c)D + 6230 LUT4 8F88 (AB)+(cD) + 6231 LUT3 0B c/aB\ + 6232 LUT4 8F00 ((AB)+c)D + 6233 LUT4 8F88 (AB)+(cD) + 6234 LUT3 0B c/aB\ + 6235 LUT4 8F00 ((AB)+c)D + 6236 LUT3 F8 (AB)+C + 6237 LUT4 F400 ((aB)+C)D + 6238 LUT2 4 aB + 6239 LUT3 70 C/AB\ + 6240 LUT3 F8 (AB)+C + 6241 LUT4 F400 ((aB)+C)D + 6242 LUT2 4 aB + 6243 LUT3 70 C/AB\ + 6244 LUT3 F8 (AB)+C + 6245 LUT4 F400 ((aB)+C)D + 6246 LUT2 4 aB + 6247 LUT3 70 C/AB\ + 6248 LUT3 F8 (AB)+C + 6249 LUT4 F400 ((aB)+C)D + 6250 LUT2 4 aB + 6251 LUT3 70 C/AB\ + 6252 LUT3 F8 (AB)+C + 6253 LUT4 F400 ((aB)+C)D + 6254 LUT2 4 aB + 6255 LUT3 70 C/AB\ + 6256 LUT3 F4 (aB)+C + 6257 LUT4 F400 ((aB)+C)D + 6258 LUT2 4 aB + 6259 LUT3 F4 (aB)+C + 6260 LUT4 F400 ((aB)+C)D + 6261 LUT2 4 aB + 6262 LUT3 F4 (aB)+C + 6263 LUT4 F400 ((aB)+C)D + 6264 LUT2 4 aB + 6265 LUT3 F4 (aB)+C + 6266 LUT4 F400 ((aB)+C)D + 6267 LUT2 4 aB + 6268 LUT3 F4 (aB)+C + 6269 LUT4 F400 ((aB)+C)D + 6270 LUT2 4 aB + 6271 LUT3 F4 (aB)+C + 6272 LUT4 F400 ((aB)+C)D + 6273 LUT2 4 aB + 6274 LUT3 F4 (aB)+C + 6275 LUT4 F400 ((aB)+C)D + 6276 LUT2 4 aB + 6277 LUT3 0B c/aB\ + 6278 LUT3 D3 BC?1:0:a:1 + 6279 LUT3 80 ABC + 6280 LUT4 8000 ABCD + 6281 LUT2 4 aB + 6282 LUT3 C5 C?a:B + 6283 LUT3 35 c?b:a + 6284 LUT3 C5 C?a:B + 6285 LUT3 53 C?b:a + 6286 LUT4 0B00 cD/aB\ + 6287 LUT2 4 aB + 6288 LUT4 0001 abcd + 6289 LUT4 0001 abcd + 6290 LUT4 0001 abcd + 6291 LUT4 0E00 cD/ab\ + 6292 LUT4 0B00 cD/aB\ + 6293 LUT2 B /aB\ + 6294 LUT2 B /aB\ + 6295 LUT2 B /aB\ + 6296 LUT2 B /aB\ + 6297 LUT2 B /aB\ + 6298 LUT2 B /aB\ + 6299 LUT2 B /aB\ + 6300 LUT2 B /aB\ + 6301 LUT2 B /aB\ + 6302 LUT2 B /aB\ + 6303 LUT2 B /aB\ + 6304 LUT2 B /aB\ + 6305 LUT2 B /aB\ + 6306 LUT2 E /ab\ + 6307 LUT2 E /ab\ + 6308 LUT2 B /aB\ + 6309 LUT2 E /ab\ + 6310 LUT2 B /aB\ + 6311 LUT2 B /aB\ + 6312 LUT2 B /aB\ + 6313 LUT2 E /ab\ + 6314 LUT2 B /aB\ + 6315 LUT2 B /aB\ + 6316 LUT2 B /aB\ + 6317 LUT2 B /aB\ + 6318 LUT2 B /aB\ + 6319 LUT2 B /aB\ + 6320 LUT2 B /aB\ + 6321 LUT2 B /aB\ + 6322 LUT2 B /aB\ + 6323 LUT2 B /aB\ + 6324 LUT4 0C0A DC?A:B:0:0 + 6325 LUT4 00F8 ((AB)+C)d + 6326 LUT4 AC00 D(c?A:B) + 6327 LUT4 8F00 ((AB)+c)D + 6328 LUT3 D0 C/Ab\ + 6329 LUT4 8F00 ((AB)+c)D + 6330 LUT4 00BF ((/aB\)+c)d + 6331 LUT3 80 ABC + 6332 LUT4 00F8 ((AB)+C)d + 6333 LUT4 AC00 D(c?A:B) + 6334 LUT4 8F00 ((AB)+c)D + 6335 LUT4 8F00 ((AB)+c)D + 6336 LUT4 8F00 ((AB)+c)D + 6337 LUT4 00F8 ((AB)+C)d + 6338 LUT4 AC00 D(c?A:B) + 6339 LUT4 8F00 ((AB)+c)D + 6340 LUT4 8F00 ((AB)+c)D + 6341 LUT4 8F00 ((AB)+c)D + 6342 LUT4 00F8 ((AB)+C)d + 6343 LUT4 AC00 D(c?A:B) + 6344 LUT4 8F00 ((AB)+c)D + 6345 LUT4 8F00 ((AB)+c)D + 6346 LUT4 8F00 ((AB)+c)D + 6347 LUT4 00F8 ((AB)+C)d + 6348 LUT4 AC00 D(c?A:B) + 6349 LUT4 8F00 ((AB)+c)D + 6350 LUT4 8F00 ((AB)+c)D + 6351 LUT4 8F00 ((AB)+c)D + 6352 LUT4 00F8 ((AB)+C)d + 6353 LUT4 AC00 D(c?A:B) + 6354 LUT4 8F00 ((AB)+c)D + 6355 LUT4 8F00 ((AB)+c)D + 6356 LUT4 8F00 ((AB)+c)D + 6357 LUT4 00F8 ((AB)+C)d + 6358 LUT4 AC00 D(c?A:B) + 6359 LUT4 8F00 ((AB)+c)D + 6360 LUT4 8F00 ((AB)+c)D + 6361 LUT4 8F00 ((AB)+c)D + 6362 LUT4 00F8 ((AB)+C)d + 6363 LUT4 AC00 D(c?A:B) + 6364 LUT4 8F00 ((AB)+c)D + 6365 LUT4 8F00 ((AB)+c)D + 6366 LUT4 8F00 ((AB)+c)D + 6367 LUT4 4000 aBCD + 6368 LUT3 53 C?b:a + 6369 LUT4 4000 aBCD + 6370 LUT3 53 C?b:a + 6371 LUT4 4000 aBCD + 6372 LUT3 53 C?b:a + 6373 LUT4 4000 aBCD + 6374 LUT3 53 C?b:a + 6375 LUT4 4000 aBCD + 6376 LUT3 53 C?b:a + 6377 LUT4 4000 aBCD + 6378 LUT3 53 C?b:a + 6379 LUT4 4000 aBCD + 6380 LUT3 53 C?b:a + 6381 LUT4 4000 aBCD + 6382 LUT3 53 C?b:a + 6383 LUT4 8000 ABCD + 6384 LUT4 8000 ABCD + 6385 LUT4 8000 ABCD + 6386 LUT4 8000 ABCD + 6387 LUT4 8000 ABCD + 6388 LUT4 8000 ABCD + 6389 LUT4 8000 ABCD + 6390 LUT4 8000 ABCD + 6391 LUT3 80 ABC + 6392 LUT3 D0 C/Ab\ + 6393 LUT2 8 AB + 6394 LUT3 80 ABC + 6395 LUT3 D0 C/Ab\ + 6396 LUT3 80 ABC + 6397 LUT3 70 C/AB\ + 6398 LUT3 80 ABC + 6399 LUT3 70 C/AB\ + 6400 LUT3 80 ABC + 6401 LUT3 D0 C/Ab\ + 6402 LUT3 80 ABC + 6403 LUT3 D0 C/Ab\ + 6404 LUT3 80 ABC + 6405 LUT3 D0 C/Ab\ + 6406 LUT3 80 ABC + 6407 LUT3 70 C/AB\ + 6408 LUT2 4 aB + 6409 LUT3 35 c?b:a + 6410 LUT2 4 aB + 6411 LUT3 E0 C/ab\ + 6412 LUT2 4 aB + 6413 LUT3 35 c?b:a + 6414 LUT2 4 aB + 6415 LUT3 35 c?b:a + 6416 LUT2 4 aB + 6417 LUT3 35 c?b:a + 6418 LUT2 4 aB + 6419 LUT3 53 C?b:a + 6420 LUT2 4 aB + 6421 LUT3 53 C?b:a + 6422 LUT2 4 aB + 6423 LUT3 53 C?b:a + 6424 LUT2 4 aB + 6425 LUT3 35 c?b:a + 6426 LUT4 00F8 ((AB)+C)d + 6427 LUT4 0A0C DC?B:A:0:0 + 6428 LUT3 07 c/AB\ + 6429 LUT3 10 abC + 6430 LUT4 00F8 ((AB)+C)d + 6431 LUT4 0A0C DC?B:A:0:0 + 6432 LUT4 00F8 ((AB)+C)d + 6433 LUT4 0A0C DC?B:A:0:0 + 6434 LUT4 00F8 ((AB)+C)d + 6435 LUT4 0A0C DC?B:A:0:0 + 6436 LUT4 00F8 ((AB)+C)d + 6437 LUT4 0A0C DC?B:A:0:0 + 6438 LUT4 00F8 ((AB)+C)d + 6439 LUT4 0A0C DC?B:A:0:0 + 6440 LUT4 00F8 ((AB)+C)d + 6441 LUT4 0A0C DC?B:A:0:0 + 6442 LUT4 00F8 ((AB)+C)d + 6443 LUT4 0A0C DC?B:A:0:0 + 6444 LUT4 0305 DC?a:b:0:0 + 6445 LUT3 1F (ab)+c + 6446 LUT4 0305 DC?a:b:0:0 + 6447 LUT4 0305 DC?a:b:0:0 + 6448 LUT4 0305 DC?a:b:0:0 + 6449 LUT4 0503 DC?b:a:0:0 + 6450 LUT4 0503 DC?b:a:0:0 + 6451 LUT4 0503 DC?b:a:0:0 + 6452 LUT4 0305 DC?a:b:0:0 + 6453 LUT3 3A c?b:A + 6454 LUT3 53 C?b:a + 6455 LUT4 F888 (AB)+(CD) + 6456 LUT2 4 aB + 6457 LUT2 4 aB + 6458 LUT2 4 aB + 6459 LUT4 ECC0 BD?0:C:AC:1 + 6460 LUT2 4 aB + 6461 LUT2 4 aB + 6462 LUT3 8F (AB)+c + 6463 LUT4 11F0 D?C:ab + 6464 LUT3 F8 (AB)+C + 6465 LUT3 CA C?A:B + 6466 LUT3 CA C?A:B + 6467 LUT3 CA C?A:B + 6468 LUT3 CA C?A:B + 6469 LUT3 CA C?A:B + 6470 LUT3 CA C?A:B + 6471 LUT3 CA C?A:B + 6472 LUT3 CA C?A:B + 6473 LUT3 CA C?A:B + 6474 LUT3 CA C?A:B + 6475 LUT3 CA C?A:B + 6476 LUT3 CA C?A:B + 6477 LUT3 CA C?A:B + 6478 LUT4 88F0 D?C:AB + 6479 LUT3 CA C?A:B + 6480 LUT3 CA C?A:B + 6481 LUT3 CA C?A:B + 6482 LUT3 CA C?A:B + 6483 LUT3 CA C?A:B + 6484 LUT3 CA C?A:B + 6485 LUT3 CA C?A:B + 6486 LUT3 CA C?A:B + 6487 LUT3 CA C?A:B + 6488 LUT3 CA C?A:B + 6489 LUT3 CA C?A:B + 6490 LUT3 CA C?A:B + 6491 LUT3 CA C?A:B + 6492 LUT3 CA C?A:B + 6493 LUT3 CA C?A:B + 6494 LUT3 CA C?A:B + 6495 LUT3 CA C?A:B + 6496 LUT3 CA C?A:B + 6497 LUT3 CA C?A:B + 6498 LUT3 CA C?A:B + 6499 LUT3 CA C?A:B + 6500 LUT3 CA C?A:B + 6501 LUT3 CA C?A:B + 6502 LUT2 8 AB + 6503 LUT2 8 AB + 6504 LUT2 8 AB + 6505 LUT2 4 aB + 6506 LUT2 4 aB + 6507 LUT2 4 aB + 6508 LUT2 4 aB + 6509 LUT2 8 AB + 6510 LUT4 0E00 cD/ab\ + 6511 LUT2 4 aB + 6512 LUT4 CA00 D(C?A:B) + 6513 LUT4 CA00 D(C?A:B) + 6514 LUT3 F8 (AB)+C + 6515 LUT2 4 aB + 6516 LUT4 9009 (a^B)(D^c) + 6517 LUT4 B0BB /aB\(d+C) + 6518 LUT4 9009 (a^B)(D^c) + 6519 LUT2 4 aB + 6520 LUT2 9 a^B + 6521 LUT2 6 A^B + 6522 LUT2 6 A^B + 6523 LUT3 AC c?A:B + 6524 LUT3 8F (AB)+c + 6525 LUT4 5FF3 DC?b:1:1:a + 6526 LUT3 F8 (AB)+C + 6527 LUT3 CA C?A:B + 6528 LUT4 F444 (aB)+(CD) + 6529 LUT3 8F (AB)+c + 6530 LUT4 7077 /AB\(d+C) + 6531 LUT3 0D c/Ab\ + 6532 LUT2 1 ab + 6533 LUT4 B00B /aB\/D^C\ + 6534 LUT4 9009 (a^B)(D^c) + 6535 LUT4 9000 CD(a^B) + 6536 LUT4 8000 ABCD + 6537 LUT3 90 C(a^B) + 6538 LUT3 90 C(a^B) + 6539 LUT4 4100 D(B^c)a + 6540 LUT4 4100 D(B^c)a + 6541 LUT3 8F (AB)+c + 6542 LUT4 7077 /AB\(d+C) + 6543 LUT3 0D c/Ab\ + 6544 LUT3 8F (AB)+c + 6545 LUT4 035F DC?1:b:a:0 + 6546 LUT2 4 aB + 6547 LUT3 8F (AB)+c + 6548 LUT4 035F DC?1:b:a:0 + 6549 LUT2 4 aB + 6550 LUT3 8F (AB)+c + 6551 LUT4 035F DC?1:b:a:0 + 6552 LUT2 4 aB + 6553 LUT3 8F (AB)+c + 6554 LUT4 7077 /AB\(d+C) + 6555 LUT3 0D c/Ab\ + 6556 LUT3 A3 C?b:A + 6557 LUT4 00BF ((/aB\)+c)d + 6558 LUT3 8F (AB)+c + 6559 LUT4 035F DC?1:b:a:0 + 6560 LUT2 4 aB + 6561 LUT3 D0 C/Ab\ + 6562 LUT4 FF0B (c/aB\)+D + 6563 LUT2 4 aB + 6564 LUT3 D0 C/Ab\ + 6565 LUT4 FF0B (c/aB\)+D + 6566 LUT2 4 aB + 6567 LUT3 D0 C/Ab\ + 6568 LUT4 FF0B (c/aB\)+D + 6569 LUT2 4 aB + 6570 LUT3 D0 C/Ab\ + 6571 LUT4 FF0B (c/aB\)+D + 6572 LUT2 4 aB + 6573 LUT3 D0 C/Ab\ + 6574 LUT4 FF0B (c/aB\)+D + 6575 LUT2 4 aB + 6576 LUT3 D0 C/Ab\ + 6577 LUT4 FF0B (c/aB\)+D + 6578 LUT2 4 aB + 6579 LUT3 D0 C/Ab\ + 6580 LUT4 FF0B (c/aB\)+D + 6581 LUT2 4 aB + 6582 LUT3 D0 C/Ab\ + 6583 LUT4 FF0B (c/aB\)+D + 6584 LUT2 4 aB + 6585 LUT3 A3 C?b:A + 6586 LUT4 00BF ((/aB\)+c)d + 6587 LUT3 8F (AB)+c + 6588 LUT4 7077 /AB\(d+C) + 6589 LUT2 4 aB + 6590 LUT3 0D c/Ab\ + 6591 LUT3 A3 C?b:A + 6592 LUT4 00BF ((/aB\)+c)d + 6593 LUT3 8F (AB)+c + 6594 LUT4 7077 /AB\(d+C) + 6595 LUT3 0D c/Ab\ + 6596 LUT3 8F (AB)+c + 6597 LUT4 7077 /AB\(d+C) + 6598 LUT3 0D c/Ab\ + 6599 LUT3 8F (AB)+c + 6600 LUT4 7077 /AB\(d+C) + 6601 LUT3 0D c/Ab\ + 6602 LUT3 A3 C?b:A + 6603 LUT4 00BF ((/aB\)+c)d + 6604 LUT3 A3 C?b:A + 6605 LUT4 00BF ((/aB\)+c)d + 6606 LUT3 F1 (ab)+C + 6607 LUT3 40 aBC + 6608 LUT3 F1 (ab)+C + 6609 LUT3 40 aBC + 6610 LUT3 F1 (ab)+C + 6611 LUT3 40 aBC + 6612 LUT3 F1 (ab)+C + 6613 LUT3 40 aBC + 6614 LUT3 F1 (ab)+C + 6615 LUT3 40 aBC + 6616 LUT3 F1 (ab)+C + 6617 LUT3 40 aBC + 6618 LUT3 F1 (ab)+C + 6619 LUT3 40 aBC + 6620 LUT3 F1 (ab)+C + 6621 LUT3 40 aBC + 6622 LUT2 4 aB + 6623 LUT2 4 aB + 6624 LUT2 4 aB + 6625 LUT3 B0 C/aB\ + 6626 LUT4 000D cd/Ab\ + 6627 LUT3 0D c/Ab\ + 6628 LUT4 7000 CD/AB\ + 6629 LUT4 008F ((AB)+c)d + 6630 LUT4 0700 cD/AB\ + 6631 LUT2 8 AB + 6632 LUT4 0777 /AB\(d+c) + 6633 LUT4 1000 abCD + 6634 LUT3 40 aBC + 6635 LUT3 10 abC + 6636 LUT4 8000 ABCD + 6637 LUT4 8000 ABCD + 6638 LUT4 9000 CD(a^B) + 6639 LUT3 90 C(a^B) + 6640 LUT4 B0BB /aB\(d+C) + 6641 LUT4 B0BB /aB\(d+C) + 6642 LUT4 9000 CD(a^B) + 6643 LUT4 B0BB /aB\(d+C) + 6644 LUT4 9009 (a^B)(D^c) + 6645 LUT4 9000 CD(a^B) + 6646 LUT2 9 a^B + 6647 LUT4 9009 (a^B)(D^c) + 6648 LUT4 9009 (a^B)(D^c) + 6649 LUT4 8000 ABCD + 6650 LUT3 90 C(a^B) + 6651 LUT4 B0BB /aB\(d+C) + 6652 LUT4 9009 (a^B)(D^c) + 6653 LUT4 9009 (a^B)(D^c) + 6654 LUT4 9009 (a^B)(D^c) + 6655 LUT4 9000 CD(a^B) + 6656 LUT4 B0BB /aB\(d+C) + 6657 LUT4 9009 (a^B)(D^c) + 6658 LUT4 9000 CD(a^B) + 6659 LUT4 B0BB /aB\(d+C) + 6660 LUT4 9009 (a^B)(D^c) + 6661 LUT4 0100 abcD + 6662 LUT2 4 aB + 6663 LUT2 8 AB + 6664 LUT3 01 abc + 6665 LUT3 B0 C/aB\ + 6666 LUT4 BF00 ((/aB\)+c)D + 6667 LUT4 0100 abcD + 6668 LUT3 B0 C/aB\ + 6669 LUT4 BF00 ((/aB\)+c)D + 6670 LUT2 8 AB + 6671 LUT3 01 abc + 6672 LUT3 B0 C/aB\ + 6673 LUT4 BF00 ((/aB\)+c)D + 6674 LUT2 8 AB + 6675 LUT3 01 abc + 6676 LUT3 B0 C/aB\ + 6677 LUT4 BF00 ((/aB\)+c)D + 6678 LUT2 4 aB + 6679 LUT3 40 aBC + 6680 LUT4 0700 cD/AB\ + 6681 LUT3 01 abc + 6682 LUT2 E /ab\ + 6683 LUT4 0100 abcD + 6684 LUT3 0B c/aB\ + 6685 LUT3 07 c/AB\ + 6686 LUT4 0007 cd/AB\ + 6687 LUT3 D0 C/Ab\ + 6688 LUT4 B000 CD/aB\ + 6689 LUT3 40 aBC + 6690 LUT4 8000 ABCD + 6691 LUT4 8000 ABCD + 6692 LUT3 40 aBC + 6693 LUT2 8 AB + 6694 LUT4 D000 CD/Ab\ + 6695 LUT3 80 ABC + 6696 LUT3 40 aBC + 6697 LUT4 0100 abcD + 6698 LUT4 4000 aBCD + 6699 LUT3 01 abc + 6700 LUT3 80 ABC + 6701 LUT2 E /ab\ + 6702 LUT3 CA C?A:B + 6703 LUT3 CA C?A:B + 6704 LUT2 E /ab\ + 6705 LUT4 0D00 cD/Ab\ + 6706 LUT4 0D00 cD/Ab\ + 6707 LUT3 CA C?A:B + 6708 LUT3 CA C?A:B + 6709 LUT3 CA C?A:B + 6710 LUT3 CA C?A:B + 6711 LUT3 CA C?A:B + 6712 LUT2 4 aB + 6713 LUT4 00EF ((/ab\)+c)d + 6714 LUT3 80 ABC + 6715 LUT4 9FFF (a^B)+c+d + 6716 LUT4 9009 (a^B)(D^c) + 6717 LUT4 1000 abCD + 6718 LUT4 1000 abCD + 6719 LUT3 CA C?A:B + 6720 LUT3 CA C?A:B + 6721 LUT3 CA C?A:B + 6722 LUT3 CA C?A:B + 6723 LUT3 CA C?A:B + 6724 LUT3 CA C?A:B + 6725 LUT3 CA C?A:B + 6726 LUT3 CA C?A:B + 6727 LUT2 4 aB + 6728 LUT3 CA C?A:B + 6729 LUT3 CA C?A:B + 6730 LUT3 CA C?A:B + 6731 LUT3 CA C?A:B + 6732 LUT3 CA C?A:B + 6733 LUT3 CA C?A:B + 6734 LUT3 CA C?A:B + 6735 LUT3 CA C?A:B + 6736 LUT2 4 aB + 6737 LUT3 CA C?A:B + 6738 LUT3 CA C?A:B + 6739 LUT3 CA C?A:B + 6740 LUT3 CA C?A:B + 6741 LUT3 CA C?A:B + 6742 LUT3 CA C?A:B + 6743 LUT3 CA C?A:B + 6744 LUT2 4 aB + 6745 LUT2 1 ab + 6746 LUT2 4 aB + 6747 LUT2 4 aB + 6748 LUT2 1 ab + 6749 LUT2 4 aB + 6750 LUT2 4 aB + 6751 LUT2 1 ab + 6752 LUT2 4 aB + 6753 LUT2 4 aB + 6754 LUT2 1 ab + 6755 LUT2 4 aB + 6756 LUT2 4 aB + 6757 LUT2 1 ab + 6758 LUT2 4 aB + 6759 LUT2 4 aB + 6760 LUT2 1 ab + 6761 LUT2 4 aB + 6762 LUT2 4 aB + 6763 LUT2 1 ab + 6764 LUT2 4 aB + 6765 LUT2 4 aB + 6766 LUT2 1 ab + 6767 LUT2 4 aB + 6768 LUT3 CA C?A:B + 6769 LUT2 4 aB + 6770 LUT3 CA C?A:B + 6771 LUT3 CA C?A:B + 6772 LUT3 CA C?A:B + 6773 LUT3 CA C?A:B + 6774 LUT3 CA C?A:B + 6775 LUT3 CA C?A:B + 6776 LUT3 CA C?A:B + 6777 LUT3 CA C?A:B + 6778 LUT2 4 aB + 6779 LUT3 CA C?A:B + 6780 LUT3 CA C?A:B + 6781 LUT3 CA C?A:B + 6782 LUT3 CA C?A:B + 6783 LUT3 CA C?A:B + 6784 LUT3 CA C?A:B + 6785 LUT3 CA C?A:B + 6786 LUT3 CA C?A:B + 6787 LUT2 4 aB + 6788 LUT3 CA C?A:B + 6789 LUT3 CA C?A:B + 6790 LUT3 CA C?A:B + 6791 LUT3 CA C?A:B + 6792 LUT3 CA C?A:B + 6793 LUT3 CA C?A:B + 6794 LUT3 CA C?A:B + 6795 LUT2 8 AB + 6796 LUT2 4 aB + 6797 LUT2 8 AB + 6798 LUT2 8 AB + 6799 LUT2 4 aB + 6800 LUT2 8 AB + 6801 LUT2 8 AB + 6802 LUT2 4 aB + 6803 LUT2 8 AB + 6804 LUT2 8 AB + 6805 LUT2 4 aB + 6806 LUT2 8 AB + 6807 LUT2 8 AB + 6808 LUT2 4 aB + 6809 LUT2 8 AB + 6810 LUT2 8 AB + 6811 LUT2 4 aB + 6812 LUT2 8 AB + 6813 LUT2 8 AB + 6814 LUT2 4 aB + 6815 LUT2 8 AB + 6816 LUT2 8 AB + 6817 LUT2 4 aB + 6818 LUT2 8 AB + 6819 LUT2 4 aB + 6820 LUT2 4 aB + 6821 LUT2 4 aB + 6822 LUT4 94DD AD?1:B:B^C:BC + 6823 LUT3 10 abC + 6824 LUT3 10 abC + 6825 LUT2 8 AB + 6826 LUT4 0777 /AB\(d+c) + 6827 LUT2 1 ab + 6828 LUT2 1 ab + 6829 LUT3 40 aBC + 6830 LUT3 40 aBC + 6831 LUT4 0777 /AB\(d+c) + 6832 LUT2 4 aB + 6833 LUT2 4 aB + 6834 LUT4 BF00 ((/aB\)+c)D + 6835 LUT3 70 C/AB\ + 6836 LUT4 00BF ((/aB\)+c)d + 6837 LUT2 4 aB + 6838 LUT3 2B AB?c:1:0:c + 6839 LUT2 B /aB\ + 6840 LUT4 00F4 ((aB)+C)d + 6841 LUT2 8 AB + 6842 LUT3 D0 C/Ab\ + 6843 LUT2 4 aB + 6844 LUT4 0100 abcD + 6845 LUT3 B0 C/aB\ + 6846 LUT3 40 aBC + 6847 LUT4 4000 aBCD + 6848 LUT3 07 c/AB\ + 6849 LUT3 10 abC + 6850 LUT2 8 AB + 6851 LUT3 0E c/ab\ + 6852 LUT4 0D00 cD/Ab\ + 6853 LUT2 4 aB + 6854 LUT3 D0 C/Ab\ + 6855 LUT3 07 c/AB\ + 6856 LUT3 60 C(A^B) + 6857 LUT3 60 C(A^B) + 6858 LUT3 70 C/AB\ + 6859 LUT4 0BBB /aB\(d+c) + 6860 LUT4 0700 cD/AB\ + 6861 LUT3 70 C/AB\ + 6862 LUT4 7077 /AB\(d+C) + 6863 LUT3 80 ABC + 6864 LUT3 70 C/AB\ + 6865 LUT4 7077 /AB\(d+C) + 6866 LUT4 007F ((/AB\)+c)d + 6867 LUT4 1428 (B^C)(A^D) + 6868 LUT2 8 AB + 6869 LUT2 B /aB\ + 6870 LUT4 0100 abcD + 6871 LUT4 CA00 D(C?A:B) + 6872 LUT3 EF /ab\+c + 6873 LUT4 4000 aBCD + 6874 LUT3 10 abC + 6875 LUT4 001F ((ab)+c)d + 6876 LUT3 60 C(A^B) + 6877 LUT3 60 C(A^B) + 6878 LUT4 0D00 cD/Ab\ + 6879 LUT3 0D c/Ab\ + 6880 LUT4 008F ((AB)+c)d + 6881 LUT2 1 ab + 6882 LUT4 0700 cD/AB\ + 6883 LUT4 0700 cD/AB\ + 6884 LUT2 8 AB + 6885 LUT3 40 aBC + 6886 LUT3 40 aBC + 6887 LUT3 40 aBC + 6888 LUT3 40 aBC + 6889 LUT4 0700 cD/AB\ + 6890 LUT2 8 AB + 6891 LUT4 0700 cD/AB\ + 6892 LUT2 1 ab + 6893 LUT2 8 AB + 6894 LUT4 0700 cD/AB\ + 6895 LUT4 0777 /AB\(d+c) + 6896 LUT4 FA30 DC?0:A:b:1 + 6897 LUT3 70 C/AB\ + 6898 LUT4 FC1F DC?1:B:ab:1 + 6899 LUT4 10FF (abC)+d + 6900 LUT4 0D00 cD/Ab\ + 6901 LUT2 8 AB + 6902 LUT4 004F ((aB)+c)d + 6903 LUT2 4 aB + 6904 LUT4 0001 abcd + 6905 LUT2 4 aB + 6906 LUT2 4 aB + 6907 LUT3 10 abC + 6908 LUT4 EF00 ((/ab\)+c)D + 6909 LUT3 10 abC + 6910 LUT3 4F (aB)+c + 6911 LUT2 8 AB + 6912 LUT3 60 C(A^B) + 6913 LUT3 60 C(A^B) + 6914 LUT4 BF00 ((/aB\)+c)D + 6915 LUT4 EF00 ((/ab\)+c)D + 6916 LUT4 BF00 ((/aB\)+c)D + 6917 LUT4 FFF8 (AB)+C+D + 6918 LUT3 C5 C?a:B + 6919 LUT3 07 c/AB\ + 6920 LUT3 C5 C?a:B + 6921 LUT3 07 c/AB\ + 6922 LUT3 CA C?A:B + 6923 LUT3 CA C?A:B + 6924 LUT3 3A c?b:A + 6925 LUT2 1 ab + 6926 LUT3 F8 (AB)+C + 6927 LUT4 40FF (aBC)+d + 6928 LUT4 4000 aBCD + 6929 LUT4 3533 DC?b:a:b:b + 6930 LUT2 8 AB + 6931 LUT2 8 AB + 6932 LUT3 CA C?A:B + 6933 LUT3 CA C?A:B + 6934 LUT3 CA C?A:B + 6935 LUT3 CA C?A:B + 6936 LUT3 CA C?A:B + 6937 LUT3 C5 C?a:B + 6938 LUT4 35FF (c?b:a)+d + 6939 LUT3 C5 C?a:B + 6940 LUT4 35FF (c?b:a)+d + 6941 LUT3 CA C?A:B + 6942 LUT3 CA C?A:B + 6943 LUT3 C5 C?a:B + 6944 LUT3 35 c?b:a + 6945 LUT3 C5 C?a:B + 6946 LUT3 35 c?b:a + 6947 LUT3 C5 C?a:B + 6948 LUT3 35 c?b:a + 6949 LUT3 C5 C?a:B + 6950 LUT3 35 c?b:a + 6951 LUT3 C5 C?a:B + 6952 LUT3 35 c?b:a + 6953 LUT3 C5 C?a:B + 6954 LUT3 35 c?b:a + 6955 LUT3 C5 C?a:B + 6956 LUT3 35 c?b:a + 6957 LUT3 C5 C?a:B + 6958 LUT3 35 c?b:a + 6959 LUT3 C5 C?a:B + 6960 LUT3 35 c?b:a + 6961 LUT3 C5 C?a:B + 6962 LUT4 0F77 D?/AB\:c + 6963 LUT3 C5 C?a:B + 6964 LUT3 35 c?b:a + 6965 LUT3 C5 C?a:B + 6966 LUT3 35 c?b:a + 6967 LUT3 C5 C?a:B + 6968 LUT3 35 c?b:a + 6969 LUT3 C5 C?a:B + 6970 LUT3 35 c?b:a + 6971 LUT3 C5 C?a:B + 6972 LUT3 35 c?b:a + 6973 LUT3 C5 C?a:B + 6974 LUT3 35 c?b:a + 6975 LUT3 C5 C?a:B + 6976 LUT3 35 c?b:a + 6977 LUT3 C5 C?a:B + 6978 LUT3 35 c?b:a + 6979 LUT3 C5 C?a:B + 6980 LUT3 35 c?b:a + 6981 LUT3 C5 C?a:B + 6982 LUT3 35 c?b:a + 6983 LUT3 C5 C?a:B + 6984 LUT3 35 c?b:a + 6985 LUT3 C5 C?a:B + 6986 LUT3 35 c?b:a + 6987 LUT3 C5 C?a:B + 6988 LUT3 35 c?b:a + 6989 LUT3 C5 C?a:B + 6990 LUT3 35 c?b:a + 6991 LUT3 C5 C?a:B + 6992 LUT3 35 c?b:a + 6993 LUT3 C5 C?a:B + 6994 LUT3 35 c?b:a + 6995 LUT3 C5 C?a:B + 6996 LUT3 35 c?b:a + 6997 LUT3 C5 C?a:B + 6998 LUT3 35 c?b:a + 6999 LUT3 C5 C?a:B + 7000 LUT3 35 c?b:a + 7001 LUT3 35 c?b:a + 7002 LUT3 35 c?b:a + 7003 LUT3 07 c/AB\ + 7004 LUT2 8 AB + 7005 LUT3 35 c?b:a + 7006 LUT3 35 c?b:a + 7007 LUT3 07 c/AB\ + 7008 LUT3 35 c?b:a + 7009 LUT3 35 c?b:a + 7010 LUT3 07 c/AB\ + 7011 LUT4 0F44 D?aB:c + 7012 LUT3 07 c/AB\ + 7013 LUT4 FFF2 (Ab)+C+D + 7014 LUT4 030A DC?A:b:0:0 + 7015 LUT3 C5 C?a:B + 7016 LUT4 ACCC DC?B:B:B:A + 7017 LUT2 4 aB + 7018 LUT4 7077 /AB\(d+C) + 7019 LUT2 4 aB + 7020 LUT4 0777 /AB\(d+c) + 7021 LUT2 8 AB + 7022 LUT4 0777 /AB\(d+c) + 7023 LUT2 8 AB + 7024 LUT4 5300 D(C?b:a) + 7025 LUT3 C5 C?a:B + 7026 LUT4 B0BB /aB\(d+C) + 7027 LUT2 8 AB + 7028 LUT4 B0BB /aB\(d+C) + 7029 LUT2 8 AB + 7030 LUT4 0B33 BD?1:0:c:Ac + 7031 LUT4 B0BB /aB\(d+C) + 7032 LUT2 8 AB + 7033 LUT4 B0BB /aB\(d+C) + 7034 LUT2 8 AB + 7035 LUT4 0B33 BD?1:0:c:Ac + 7036 LUT4 B0BB /aB\(d+C) + 7037 LUT2 8 AB + 7038 LUT4 B0BB /aB\(d+C) + 7039 LUT2 8 AB + 7040 LUT4 0B33 BD?1:0:c:Ac + 7041 LUT4 B0BB /aB\(d+C) + 7042 LUT2 8 AB + 7043 LUT4 B0BB /aB\(d+C) + 7044 LUT2 8 AB + 7045 LUT3 C5 C?a:B + 7046 LUT4 0777 /AB\(d+c) + 7047 LUT2 8 AB + 7048 LUT4 0777 /AB\(d+c) + 7049 LUT2 8 AB + 7050 LUT4 0B33 BD?1:0:c:Ac + 7051 LUT4 0777 /AB\(d+c) + 7052 LUT2 8 AB + 7053 LUT4 0777 /AB\(d+c) + 7054 LUT2 8 AB + 7055 LUT4 0B33 BD?1:0:c:Ac + 7056 LUT4 0777 /AB\(d+c) + 7057 LUT2 8 AB + 7058 LUT4 0777 /AB\(d+c) + 7059 LUT2 8 AB + 7060 LUT4 0B33 BD?1:0:c:Ac + 7061 LUT4 B0BB /aB\(d+C) + 7062 LUT2 8 AB + 7063 LUT4 B0BB /aB\(d+C) + 7064 LUT2 8 AB + 7065 LUT4 0B33 BD?1:0:c:Ac + 7066 LUT4 B0BB /aB\(d+C) + 7067 LUT2 8 AB + 7068 LUT4 B0BB /aB\(d+C) + 7069 LUT2 8 AB + 7070 LUT4 FFF2 (Ab)+C+D + 7071 LUT4 030A DC?A:b:0:0 + 7072 LUT4 0B33 BD?1:0:c:Ac + 7073 LUT4 ACCC DC?B:B:B:A + 7074 LUT4 0777 /AB\(d+c) + 7075 LUT2 8 AB + 7076 LUT4 0777 /AB\(d+c) + 7077 LUT2 8 AB + 7078 LUT4 5300 D(C?b:a) + 7079 LUT4 0B33 BD?1:0:c:Ac + 7080 LUT4 B0BB /aB\(d+C) + 7081 LUT2 8 AB + 7082 LUT4 B0BB /aB\(d+C) + 7083 LUT2 8 AB + 7084 LUT4 0B33 BD?1:0:c:Ac + 7085 LUT4 0777 /AB\(d+c) + 7086 LUT2 8 AB + 7087 LUT4 0777 /AB\(d+c) + 7088 LUT2 8 AB + 7089 LUT4 0B33 BD?1:0:c:Ac + 7090 LUT4 B0BB /aB\(d+C) + 7091 LUT2 8 AB + 7092 LUT4 B0BB /aB\(d+C) + 7093 LUT2 8 AB + 7094 LUT4 0B33 BD?1:0:c:Ac + 7095 LUT4 0777 /AB\(d+c) + 7096 LUT2 8 AB + 7097 LUT4 0777 /AB\(d+c) + 7098 LUT2 8 AB + 7099 LUT4 0B33 BD?1:0:c:Ac + 7100 LUT4 B0BB /aB\(d+C) + 7101 LUT2 8 AB + 7102 LUT4 B0BB /aB\(d+C) + 7103 LUT2 8 AB + 7104 LUT3 4F (aB)+c + 7105 LUT4 00EF ((/ab\)+c)d + 7106 LUT4 030A DC?A:b:0:0 + 7107 LUT4 0B33 BD?1:0:c:Ac + 7108 LUT3 5C c?a:B + 7109 LUT4 0777 /AB\(d+c) + 7110 LUT2 8 AB + 7111 LUT4 B0BB /aB\(d+C) + 7112 LUT2 8 AB + 7113 LUT2 8 AB + 7114 LUT3 CA C?A:B + 7115 LUT3 C5 C?a:B + 7116 LUT4 0777 /AB\(d+c) + 7117 LUT2 8 AB + 7118 LUT4 0777 /AB\(d+c) + 7119 LUT2 8 AB + 7120 LUT3 4F (aB)+c + 7121 LUT4 004F ((aB)+c)d + 7122 LUT4 030A DC?A:b:0:0 + 7123 LUT4 0B33 BD?1:0:c:Ac + 7124 LUT3 A3 C?b:A + 7125 LUT4 B0BB /aB\(d+C) + 7126 LUT2 8 AB + 7127 LUT4 0777 /AB\(d+c) + 7128 LUT2 8 AB + 7129 LUT3 C5 C?a:B + 7130 LUT3 4F (aB)+c + 7131 LUT4 004F ((aB)+c)d + 7132 LUT4 030A DC?A:b:0:0 + 7133 LUT3 C5 C?a:B + 7134 LUT3 A3 C?b:A + 7135 LUT4 B0BB /aB\(d+C) + 7136 LUT2 8 AB + 7137 LUT4 0777 /AB\(d+c) + 7138 LUT2 8 AB + 7139 LUT3 C5 C?a:B + 7140 LUT3 C5 C?a:B + 7141 LUT4 B0BB /aB\(d+C) + 7142 LUT2 8 AB + 7143 LUT4 B0BB /aB\(d+C) + 7144 LUT2 8 AB + 7145 LUT4 FFF2 (Ab)+C+D + 7146 LUT4 030A DC?A:b:0:0 + 7147 LUT3 C5 C?a:B + 7148 LUT4 ACCC DC?B:B:B:A + 7149 LUT4 0777 /AB\(d+c) + 7150 LUT2 8 AB + 7151 LUT4 0777 /AB\(d+c) + 7152 LUT2 8 AB + 7153 LUT4 5300 D(C?b:a) + 7154 LUT3 4F (aB)+c + 7155 LUT4 004F ((aB)+c)d + 7156 LUT4 030A DC?A:b:0:0 + 7157 LUT4 0B33 BD?1:0:c:Ac + 7158 LUT3 A3 C?b:A + 7159 LUT4 B0BB /aB\(d+C) + 7160 LUT2 8 AB + 7161 LUT4 0777 /AB\(d+c) + 7162 LUT2 8 AB + 7163 LUT3 C5 C?a:B + 7164 LUT3 4F (aB)+c + 7165 LUT4 004F ((aB)+c)d + 7166 LUT4 030A DC?A:b:0:0 + 7167 LUT4 0B33 BD?1:0:c:Ac + 7168 LUT3 A3 C?b:A + 7169 LUT4 B0BB /aB\(d+C) + 7170 LUT2 8 AB + 7171 LUT4 0777 /AB\(d+c) + 7172 LUT2 8 AB + 7173 LUT3 C5 C?a:B + 7174 LUT4 B303 BD?c:0:1:AC + 7175 LUT4 0777 /AB\(d+c) + 7176 LUT2 8 AB + 7177 LUT4 0777 /AB\(d+c) + 7178 LUT2 8 AB + 7179 LUT4 B303 BD?c:0:1:AC + 7180 LUT4 B0BB /aB\(d+C) + 7181 LUT2 8 AB + 7182 LUT4 B0BB /aB\(d+C) + 7183 LUT2 8 AB + 7184 LUT4 B303 BD?c:0:1:AC + 7185 LUT4 0777 /AB\(d+c) + 7186 LUT2 8 AB + 7187 LUT4 0777 /AB\(d+c) + 7188 LUT2 8 AB + 7189 LUT4 B303 BD?c:0:1:AC + 7190 LUT4 B0BB /aB\(d+C) + 7191 LUT2 8 AB + 7192 LUT4 B0BB /aB\(d+C) + 7193 LUT2 8 AB + 7194 LUT3 4F (aB)+c + 7195 LUT4 004F ((aB)+c)d + 7196 LUT4 0305 DC?a:b:0:0 + 7197 LUT4 B303 BD?c:0:1:AC + 7198 LUT3 A3 C?b:A + 7199 LUT4 B0BB /aB\(d+C) + 7200 LUT2 8 AB + 7201 LUT4 0777 /AB\(d+c) + 7202 LUT2 8 AB + 7203 LUT3 C5 C?a:B + 7204 LUT3 4F (aB)+c + 7205 LUT4 004F ((aB)+c)d + 7206 LUT4 0305 DC?a:b:0:0 + 7207 LUT4 B303 BD?c:0:1:AC + 7208 LUT3 A3 C?b:A + 7209 LUT4 B0BB /aB\(d+C) + 7210 LUT2 8 AB + 7211 LUT4 0777 /AB\(d+c) + 7212 LUT2 8 AB + 7213 LUT3 C5 C?a:B + 7214 LUT3 4F (aB)+c + 7215 LUT4 00EF ((/ab\)+c)d + 7216 LUT4 0305 DC?a:b:0:0 + 7217 LUT4 B303 BD?c:0:1:AC + 7218 LUT3 5C c?a:B + 7219 LUT4 0777 /AB\(d+c) + 7220 LUT2 8 AB + 7221 LUT4 B0BB /aB\(d+C) + 7222 LUT2 8 AB + 7223 LUT3 CA C?A:B + 7224 LUT4 B303 BD?c:0:1:AC + 7225 LUT4 B0BB /aB\(d+C) + 7226 LUT2 8 AB + 7227 LUT4 B0BB /aB\(d+C) + 7228 LUT2 8 AB + 7229 LUT3 F4 (aB)+C + 7230 LUT4 7077 /AB\(d+C) + 7231 LUT4 F400 ((aB)+C)D + 7232 LUT2 8 AB + 7233 LUT3 07 c/AB\ + 7234 LUT3 40 aBC + 7235 LUT2 4 aB + 7236 LUT2 4 aB + 7237 LUT4 7077 /AB\(d+C) + 7238 LUT4 00D7 AD?1:b^C:0:0 + 7239 LUT3 40 aBC + 7240 LUT4 6000 CD(A^B) + 7241 LUT3 60 C(A^B) + 7242 LUT3 60 C(A^B) + 7243 LUT4 4000 aBCD + 7244 LUT4 1000 abCD + 7245 LUT3 10 abC + 7246 LUT3 01 abc + 7247 LUT3 80 ABC + 7248 LUT4 1428 (B^C)(A^D) + 7249 LUT4 FAC0 DC?0:A:B:1 + 7250 LUT4 FC1F DC?1:B:ab:1 + 7251 LUT4 10FF (abC)+d + 7252 LUT4 0D00 cD/Ab\ + 7253 LUT4 004F ((aB)+c)d + 7254 LUT2 4 aB + 7255 LUT2 4 aB + 7256 LUT2 4 aB + 7257 LUT3 10 abC + 7258 LUT4 EF00 ((/ab\)+c)D + 7259 LUT3 10 abC + 7260 LUT3 4F (aB)+c + 7261 LUT4 BF00 ((/aB\)+c)D + 7262 LUT4 EF00 ((/ab\)+c)D + 7263 LUT4 00BF ((/aB\)+c)d + 7264 LUT4 FFF8 (AB)+C+D + 7265 LUT4 F044 D?aB:C + 7266 LUT4 1000 abCD + 7267 LUT3 C5 C?a:B + 7268 LUT3 07 c/AB\ + 7269 LUT3 CA C?A:B + 7270 LUT3 CA C?A:B + 7271 LUT3 3A c?b:A + 7272 LUT3 F8 (AB)+C + 7273 LUT4 40FF (aBC)+d + 7274 LUT4 4000 aBCD + 7275 LUT4 3533 DC?b:a:b:b + 7276 LUT2 8 AB + 7277 LUT2 8 AB + 7278 LUT3 CA C?A:B + 7279 LUT3 CA C?A:B + 7280 LUT3 CA C?A:B + 7281 LUT3 CA C?A:B + 7282 LUT3 CA C?A:B + 7283 LUT3 C5 C?a:B + 7284 LUT4 35FF (c?b:a)+d + 7285 LUT3 C5 C?a:B + 7286 LUT4 35FF (c?b:a)+d + 7287 LUT3 C5 C?a:B + 7288 LUT3 35 c?b:a + 7289 LUT3 C5 C?a:B + 7290 LUT3 35 c?b:a + 7291 LUT3 C5 C?a:B + 7292 LUT3 35 c?b:a + 7293 LUT3 C5 C?a:B + 7294 LUT3 35 c?b:a + 7295 LUT3 C5 C?a:B + 7296 LUT3 35 c?b:a + 7297 LUT3 C5 C?a:B + 7298 LUT3 35 c?b:a + 7299 LUT3 C5 C?a:B + 7300 LUT3 35 c?b:a + 7301 LUT3 C5 C?a:B + 7302 LUT3 35 c?b:a + 7303 LUT3 C5 C?a:B + 7304 LUT3 35 c?b:a + 7305 LUT3 C5 C?a:B + 7306 LUT3 35 c?b:a + 7307 LUT3 C5 C?a:B + 7308 LUT4 0F77 D?/AB\:c + 7309 LUT3 C5 C?a:B + 7310 LUT3 35 c?b:a + 7311 LUT3 C5 C?a:B + 7312 LUT3 35 c?b:a + 7313 LUT3 C5 C?a:B + 7314 LUT3 35 c?b:a + 7315 LUT3 C5 C?a:B + 7316 LUT3 35 c?b:a + 7317 LUT3 C5 C?a:B + 7318 LUT3 35 c?b:a + 7319 LUT3 C5 C?a:B + 7320 LUT3 35 c?b:a + 7321 LUT3 C5 C?a:B + 7322 LUT3 35 c?b:a + 7323 LUT3 C5 C?a:B + 7324 LUT3 35 c?b:a + 7325 LUT3 C5 C?a:B + 7326 LUT3 35 c?b:a + 7327 LUT3 C5 C?a:B + 7328 LUT3 35 c?b:a + 7329 LUT3 C5 C?a:B + 7330 LUT3 35 c?b:a + 7331 LUT3 C5 C?a:B + 7332 LUT3 35 c?b:a + 7333 LUT3 C5 C?a:B + 7334 LUT3 35 c?b:a + 7335 LUT3 C5 C?a:B + 7336 LUT3 35 c?b:a + 7337 LUT3 C5 C?a:B + 7338 LUT3 35 c?b:a + 7339 LUT3 C5 C?a:B + 7340 LUT3 35 c?b:a + 7341 LUT3 C5 C?a:B + 7342 LUT3 35 c?b:a + 7343 LUT3 C5 C?a:B + 7344 LUT3 35 c?b:a + 7345 LUT3 C5 C?a:B + 7346 LUT3 35 c?b:a + 7347 LUT3 35 c?b:a + 7348 LUT3 35 c?b:a + 7349 LUT3 35 c?b:a + 7350 LUT3 35 c?b:a + 7351 LUT3 35 c?b:a + 7352 LUT3 35 c?b:a + 7353 LUT4 0F44 D?aB:c + 7354 LUT2 4 aB + 7355 LUT4 7077 /AB\(d+C) + 7356 LUT4 FFF2 (Ab)+C+D + 7357 LUT4 3A00 D(c?b:A) + 7358 LUT4 3500 D(c?b:a) + 7359 LUT3 AC c?A:B + 7360 LUT2 E /ab\ + 7361 LUT4 3A00 D(c?b:A) + 7362 LUT4 3F0A DC?A:1:0:b + 7363 LUT3 D0 C/Ab\ + 7364 LUT3 5C c?a:B + 7365 LUT2 4 aB + 7366 LUT2 8 AB + 7367 LUT2 B /aB\ + 7368 LUT4 3A00 D(c?b:A) + 7369 LUT4 004F ((aB)+c)d + 7370 LUT4 3A00 D(c?b:A) + 7371 LUT3 A3 C?b:A + 7372 LUT3 4F (aB)+c + 7373 LUT4 004F ((aB)+c)d + 7374 LUT4 3A00 D(c?b:A) + 7375 LUT3 A3 C?b:A + 7376 LUT3 C5 C?a:B + 7377 LUT4 FFF2 (Ab)+C+D + 7378 LUT4 3A00 D(c?b:A) + 7379 LUT4 A333 DC?b:b:b:A + 7380 LUT2 4 aB + 7381 LUT4 0A03 DC?b:A:0:0 + 7382 LUT3 4F (aB)+c + 7383 LUT4 004F ((aB)+c)d + 7384 LUT4 3A00 D(c?b:A) + 7385 LUT3 A3 C?b:A + 7386 LUT3 C5 C?a:B + 7387 LUT3 4F (aB)+c + 7388 LUT4 004F ((aB)+c)d + 7389 LUT4 3500 D(c?b:a) + 7390 LUT3 A3 C?b:A + 7391 LUT3 C5 C?a:B + 7392 LUT3 4F (aB)+c + 7393 LUT4 004F ((aB)+c)d + 7394 LUT4 3500 D(c?b:a) + 7395 LUT3 A3 C?b:A + 7396 LUT3 C5 C?a:B + 7397 LUT2 E /ab\ + 7398 LUT4 3500 D(c?b:a) + 7399 LUT4 3F0A DC?A:1:0:b + 7400 LUT3 D0 C/Ab\ + 7401 LUT3 5C c?a:B + 7402 LUT2 E /ab\ + 7403 LUT4 F800 ((AB)+C)D + 7404 LUT2 4 aB + 7405 LUT2 B /aB\ + 7406 LUT4 00F4 ((aB)+C)d + 7407 LUT3 40 aBC + 7408 LUT3 07 c/AB\ + 7409 LUT3 40 aBC + 7410 LUT4 0D00 cD/Ab\ + 7411 LUT2 4 aB + 7412 LUT3 D0 C/Ab\ + 7413 LUT3 07 c/AB\ + 7414 LUT3 60 C(A^B) + 7415 LUT3 60 C(A^B) + 7416 LUT3 40 aBC + 7417 LUT4 007F ((/AB\)+c)d + 7418 LUT4 1428 (B^C)(A^D) + 7419 LUT4 1000 abCD + 7420 LUT4 4000 aBCD + 7421 LUT3 10 abC + 7422 LUT4 001F ((ab)+c)d + 7423 LUT3 60 C(A^B) + 7424 LUT3 60 C(A^B) + 7425 LUT3 10 abC + 7426 LUT4 F400 ((aB)+C)D + 7427 LUT4 1E4C AC?B:/bd\:B^D:0 + 7428 LUT3 07 c/AB\ + 7429 LUT4 FC1F DC?1:B:ab:1 + 7430 LUT4 10FF (abC)+d + 7431 LUT4 0D00 cD/Ab\ + 7432 LUT4 004F ((aB)+c)d + 7433 LUT2 4 aB + 7434 LUT2 4 aB + 7435 LUT2 4 aB + 7436 LUT3 10 abC + 7437 LUT4 EF00 ((/ab\)+c)D + 7438 LUT3 10 abC + 7439 LUT3 4F (aB)+c + 7440 LUT4 BF00 ((/aB\)+c)D + 7441 LUT4 EF00 ((/ab\)+c)D + 7442 LUT4 BF00 ((/aB\)+c)D + 7443 LUT4 FFF8 (AB)+C+D + 7444 LUT3 C5 C?a:B + 7445 LUT3 07 c/AB\ + 7446 LUT4 F044 D?aB:C + 7447 LUT4 1000 abCD + 7448 LUT3 CA C?A:B + 7449 LUT3 CA C?A:B + 7450 LUT3 3A c?b:A + 7451 LUT3 F8 (AB)+C + 7452 LUT4 FCFA DC?A:B:1:1 + 7453 LUT3 40 aBC + 7454 LUT4 4000 aBCD + 7455 LUT2 8 AB + 7456 LUT2 8 AB + 7457 LUT3 CA C?A:B + 7458 LUT3 CA C?A:B + 7459 LUT3 CA C?A:B + 7460 LUT3 CA C?A:B + 7461 LUT3 CA C?A:B + 7462 LUT3 C5 C?a:B + 7463 LUT4 35FF (c?b:a)+d + 7464 LUT3 C5 C?a:B + 7465 LUT4 35FF (c?b:a)+d + 7466 LUT3 C5 C?a:B + 7467 LUT3 35 c?b:a + 7468 LUT3 C5 C?a:B + 7469 LUT3 35 c?b:a + 7470 LUT3 C5 C?a:B + 7471 LUT3 35 c?b:a + 7472 LUT3 C5 C?a:B + 7473 LUT3 35 c?b:a + 7474 LUT3 C5 C?a:B + 7475 LUT3 35 c?b:a + 7476 LUT3 C5 C?a:B + 7477 LUT3 35 c?b:a + 7478 LUT3 C5 C?a:B + 7479 LUT3 35 c?b:a + 7480 LUT3 C5 C?a:B + 7481 LUT3 35 c?b:a + 7482 LUT3 C5 C?a:B + 7483 LUT3 35 c?b:a + 7484 LUT3 C5 C?a:B + 7485 LUT3 35 c?b:a + 7486 LUT3 C5 C?a:B + 7487 LUT4 0F77 D?/AB\:c + 7488 LUT3 C5 C?a:B + 7489 LUT3 35 c?b:a + 7490 LUT3 C5 C?a:B + 7491 LUT3 35 c?b:a + 7492 LUT3 C5 C?a:B + 7493 LUT3 35 c?b:a + 7494 LUT3 C5 C?a:B + 7495 LUT3 35 c?b:a + 7496 LUT3 C5 C?a:B + 7497 LUT3 35 c?b:a + 7498 LUT3 C5 C?a:B + 7499 LUT3 35 c?b:a + 7500 LUT3 C5 C?a:B + 7501 LUT3 35 c?b:a + 7502 LUT3 C5 C?a:B + 7503 LUT3 35 c?b:a + 7504 LUT3 C5 C?a:B + 7505 LUT3 35 c?b:a + 7506 LUT3 C5 C?a:B + 7507 LUT3 35 c?b:a + 7508 LUT3 C5 C?a:B + 7509 LUT3 35 c?b:a + 7510 LUT3 C5 C?a:B + 7511 LUT3 35 c?b:a + 7512 LUT3 C5 C?a:B + 7513 LUT3 35 c?b:a + 7514 LUT3 C5 C?a:B + 7515 LUT3 35 c?b:a + 7516 LUT3 C5 C?a:B + 7517 LUT3 35 c?b:a + 7518 LUT3 C5 C?a:B + 7519 LUT3 35 c?b:a + 7520 LUT3 C5 C?a:B + 7521 LUT3 35 c?b:a + 7522 LUT3 C5 C?a:B + 7523 LUT3 35 c?b:a + 7524 LUT3 C5 C?a:B + 7525 LUT3 35 c?b:a + 7526 LUT3 35 c?b:a + 7527 LUT3 35 c?b:a + 7528 LUT3 35 c?b:a + 7529 LUT3 35 c?b:a + 7530 LUT3 35 c?b:a + 7531 LUT3 35 c?b:a + 7532 LUT4 0F44 D?aB:c + 7533 LUT4 FFF2 (Ab)+C+D + 7534 LUT4 030A DC?A:b:0:0 + 7535 LUT4 ACCC DC?B:B:B:A + 7536 LUT2 4 aB + 7537 LUT4 7077 /AB\(d+C) + 7538 LUT4 5300 D(C?b:a) + 7539 LUT4 FFF2 (Ab)+C+D + 7540 LUT4 030A DC?A:b:0:0 + 7541 LUT4 5333 DC?b:b:b:a + 7542 LUT4 AC00 D(c?A:B) + 7543 LUT4 FFF2 (Ab)+C+D + 7544 LUT4 030A DC?A:b:0:0 + 7545 LUT4 5333 DC?b:b:b:a + 7546 LUT4 AC00 D(c?A:B) + 7547 LUT4 FFF2 (Ab)+C+D + 7548 LUT4 030A DC?A:b:0:0 + 7549 LUT4 5333 DC?b:b:b:a + 7550 LUT4 AC00 D(c?A:B) + 7551 LUT4 030A DC?A:b:0:0 + 7552 LUT3 53 C?b:a + 7553 LUT4 FFF2 (Ab)+C+D + 7554 LUT4 030A DC?A:b:0:0 + 7555 LUT4 3500 D(c?b:a) + 7556 LUT3 AC c?A:B + 7557 LUT4 030A DC?A:b:0:0 + 7558 LUT3 AC c?A:B + 7559 LUT4 FFF2 (Ab)+C+D + 7560 LUT4 030A DC?A:b:0:0 + 7561 LUT4 ACCC DC?B:B:B:A + 7562 LUT4 5300 D(C?b:a) + 7563 LUT4 030A DC?A:b:0:0 + 7564 LUT3 53 C?b:a + 7565 LUT4 FFF2 (Ab)+C+D + 7566 LUT4 030A DC?A:b:0:0 + 7567 LUT4 5333 DC?b:b:b:a + 7568 LUT4 AC00 D(c?A:B) + 7569 LUT4 FFF2 (Ab)+C+D + 7570 LUT4 030A DC?A:b:0:0 + 7571 LUT4 3500 D(c?b:a) + 7572 LUT3 AC c?A:B + 7573 LUT4 FFF2 (Ab)+C+D + 7574 LUT4 030A DC?A:b:0:0 + 7575 LUT4 5333 DC?b:b:b:a + 7576 LUT4 AC00 D(c?A:B) + 7577 LUT4 FFF2 (Ab)+C+D + 7578 LUT4 030A DC?A:b:0:0 + 7579 LUT4 3500 D(c?b:a) + 7580 LUT3 AC c?A:B + 7581 LUT4 FFF2 (Ab)+C+D + 7582 LUT4 030A DC?A:b:0:0 + 7583 LUT4 5333 DC?b:b:b:a + 7584 LUT4 AC00 D(c?A:B) + 7585 LUT4 030A DC?A:b:0:0 + 7586 LUT3 AC c?A:B + 7587 LUT4 FFF2 (Ab)+C+D + 7588 LUT4 030A DC?A:b:0:0 + 7589 LUT4 5333 DC?b:b:b:a + 7590 LUT4 AC00 D(c?A:B) + 7591 LUT3 4F (aB)+c + 7592 LUT4 00EF ((/ab\)+c)d + 7593 LUT4 030A DC?A:b:0:0 + 7594 LUT3 5C c?a:B + 7595 LUT2 8 AB + 7596 LUT3 CA C?A:B + 7597 LUT4 FFF2 (Ab)+C+D + 7598 LUT4 030A DC?A:b:0:0 + 7599 LUT4 ACCC DC?B:B:B:A + 7600 LUT4 5300 D(C?b:a) + 7601 LUT3 4F (aB)+c + 7602 LUT4 004F ((aB)+c)d + 7603 LUT4 030A DC?A:b:0:0 + 7604 LUT3 A3 C?b:A + 7605 LUT3 C5 C?a:B + 7606 LUT2 B /aB\ + 7607 LUT4 030A DC?A:b:0:0 + 7608 LUT4 004F ((aB)+c)d + 7609 LUT4 3A00 D(c?b:A) + 7610 LUT3 A3 C?b:A + 7611 LUT4 030A DC?A:b:0:0 + 7612 LUT4 030A DC?A:b:0:0 + 7613 LUT3 AC c?A:B + 7614 LUT4 FFF2 (Ab)+C+D + 7615 LUT4 030A DC?A:b:0:0 + 7616 LUT4 3A00 D(c?b:A) + 7617 LUT3 A3 C?b:A + 7618 LUT2 4 aB + 7619 LUT2 B /aB\ + 7620 LUT4 030A DC?A:b:0:0 + 7621 LUT4 004F ((aB)+c)d + 7622 LUT4 3A00 D(c?b:A) + 7623 LUT3 A3 C?b:A + 7624 LUT4 0305 DC?a:b:0:0 + 7625 LUT3 AC c?A:B + 7626 LUT4 0305 DC?a:b:0:0 + 7627 LUT3 53 C?b:a + 7628 LUT4 FFF2 (Ab)+C+D + 7629 LUT4 0305 DC?a:b:0:0 + 7630 LUT4 3500 D(c?b:a) + 7631 LUT3 AC c?A:B + 7632 LUT4 0305 DC?a:b:0:0 + 7633 LUT3 53 C?b:a + 7634 LUT2 B /aB\ + 7635 LUT4 0305 DC?a:b:0:0 + 7636 LUT4 004F ((aB)+c)d + 7637 LUT4 3A00 D(c?b:A) + 7638 LUT3 A3 C?b:A + 7639 LUT3 4F (aB)+c + 7640 LUT4 004F ((aB)+c)d + 7641 LUT4 0305 DC?a:b:0:0 + 7642 LUT3 A3 C?b:A + 7643 LUT3 C5 C?a:B + 7644 LUT3 4F (aB)+c + 7645 LUT4 00EF ((/ab\)+c)d + 7646 LUT4 0305 DC?a:b:0:0 + 7647 LUT3 5C c?a:B + 7648 LUT3 CA C?A:B + 7649 LUT4 0305 DC?a:b:0:0 + 7650 LUT3 53 C?b:a + 7651 LUT3 F4 (aB)+C + 7652 LUT4 7077 /AB\(d+C) + 7653 LUT4 F400 ((aB)+C)D + 7654 LUT3 80 ABC + 7655 LUT3 07 c/AB\ + 7656 LUT3 80 ABC + 7657 LUT2 8 AB + 7658 LUT2 4 aB + 7659 LUT2 1 ab + 7660 LUT4 8F00 ((AB)+c)D + 7661 LUT3 07 c/AB\ + 7662 LUT3 60 C(A^B) + 7663 LUT3 60 C(A^B) + 7664 LUT3 10 abC + 7665 LUT4 4000 aBCD + 7666 LUT3 60 C(A^B) + 7667 LUT3 60 C(A^B) + 7668 LUT4 4000 aBCD + 7669 LUT4 0100 abcD + 7670 LUT4 0007 cd/AB\ + 7671 LUT3 80 ABC + 7672 LUT4 1428 (B^C)(A^D) + 7673 LUT4 124F AC?d:/BD\:B^D:0 + 7674 LUT4 FC1F DC?1:B:ab:1 + 7675 LUT4 10FF (abC)+d + 7676 LUT4 0D00 cD/Ab\ + 7677 LUT4 004F ((aB)+c)d + 7678 LUT2 4 aB + 7679 LUT2 4 aB + 7680 LUT2 4 aB + 7681 LUT3 10 abC + 7682 LUT4 EF00 ((/ab\)+c)D + 7683 LUT3 10 abC + 7684 LUT3 4F (aB)+c + 7685 LUT4 BF00 ((/aB\)+c)D + 7686 LUT4 EF00 ((/ab\)+c)D + 7687 LUT4 00BF ((/aB\)+c)d + 7688 LUT4 FFF8 (AB)+C+D + 7689 LUT3 CA C?A:B + 7690 LUT4 BF00 ((/aB\)+c)D + 7691 LUT3 CA C?A:B + 7692 LUT4 BF00 ((/aB\)+c)D + 7693 LUT3 CA C?A:B + 7694 LUT3 CA C?A:B + 7695 LUT3 3A c?b:A + 7696 LUT3 F8 (AB)+C + 7697 LUT4 40FF (aBC)+d + 7698 LUT4 4000 aBCD + 7699 LUT4 3533 DC?b:a:b:b + 7700 LUT2 8 AB + 7701 LUT2 8 AB + 7702 LUT3 CA C?A:B + 7703 LUT3 CA C?A:B + 7704 LUT3 CA C?A:B + 7705 LUT3 CA C?A:B + 7706 LUT3 CA C?A:B + 7707 LUT3 C5 C?a:B + 7708 LUT4 35FF (c?b:a)+d + 7709 LUT3 C5 C?a:B + 7710 LUT4 35FF (c?b:a)+d + 7711 LUT3 C5 C?a:B + 7712 LUT3 35 c?b:a + 7713 LUT3 C5 C?a:B + 7714 LUT3 35 c?b:a + 7715 LUT3 C5 C?a:B + 7716 LUT3 35 c?b:a + 7717 LUT3 C5 C?a:B + 7718 LUT3 35 c?b:a + 7719 LUT3 C5 C?a:B + 7720 LUT3 35 c?b:a + 7721 LUT3 C5 C?a:B + 7722 LUT3 35 c?b:a + 7723 LUT3 C5 C?a:B + 7724 LUT3 35 c?b:a + 7725 LUT3 C5 C?a:B + 7726 LUT3 35 c?b:a + 7727 LUT3 C5 C?a:B + 7728 LUT3 35 c?b:a + 7729 LUT3 C5 C?a:B + 7730 LUT3 35 c?b:a + 7731 LUT3 C5 C?a:B + 7732 LUT4 0F77 D?/AB\:c + 7733 LUT3 C5 C?a:B + 7734 LUT3 35 c?b:a + 7735 LUT3 C5 C?a:B + 7736 LUT3 35 c?b:a + 7737 LUT3 C5 C?a:B + 7738 LUT3 35 c?b:a + 7739 LUT3 C5 C?a:B + 7740 LUT3 35 c?b:a + 7741 LUT3 C5 C?a:B + 7742 LUT3 35 c?b:a + 7743 LUT3 C5 C?a:B + 7744 LUT3 35 c?b:a + 7745 LUT3 C5 C?a:B + 7746 LUT3 35 c?b:a + 7747 LUT3 C5 C?a:B + 7748 LUT3 35 c?b:a + 7749 LUT3 C5 C?a:B + 7750 LUT3 35 c?b:a + 7751 LUT3 C5 C?a:B + 7752 LUT3 35 c?b:a + 7753 LUT3 C5 C?a:B + 7754 LUT3 35 c?b:a + 7755 LUT3 C5 C?a:B + 7756 LUT3 35 c?b:a + 7757 LUT3 C5 C?a:B + 7758 LUT3 35 c?b:a + 7759 LUT3 C5 C?a:B + 7760 LUT3 35 c?b:a + 7761 LUT3 C5 C?a:B + 7762 LUT3 35 c?b:a + 7763 LUT3 C5 C?a:B + 7764 LUT3 35 c?b:a + 7765 LUT3 C5 C?a:B + 7766 LUT3 35 c?b:a + 7767 LUT3 C5 C?a:B + 7768 LUT3 35 c?b:a + 7769 LUT3 C5 C?a:B + 7770 LUT3 35 c?b:a + 7771 LUT3 35 c?b:a + 7772 LUT3 35 c?b:a + 7773 LUT3 35 c?b:a + 7774 LUT3 35 c?b:a + 7775 LUT3 35 c?b:a + 7776 LUT3 35 c?b:a + 7777 LUT4 0F44 D?aB:c + 7778 LUT2 4 aB + 7779 LUT4 7077 /AB\(d+C) + 7780 LUT4 FFF2 (Ab)+C+D + 7781 LUT4 3A00 D(c?b:A) + 7782 LUT4 3A00 D(c?b:A) + 7783 LUT3 53 C?b:a + 7784 LUT4 FFF2 (Ab)+C+D + 7785 LUT4 3A00 D(c?b:A) + 7786 LUT4 5333 DC?b:b:b:a + 7787 LUT4 AC00 D(c?A:B) + 7788 LUT4 FFF2 (Ab)+C+D + 7789 LUT4 3A00 D(c?b:A) + 7790 LUT4 3500 D(c?b:a) + 7791 LUT3 5C c?a:B + 7792 LUT2 4 aB + 7793 LUT2 8 AB + 7794 LUT3 4F (aB)+c + 7795 LUT4 004F ((aB)+c)d + 7796 LUT4 3A00 D(c?b:A) + 7797 LUT3 A3 C?b:A + 7798 LUT3 C5 C?a:B + 7799 LUT3 4F (aB)+c + 7800 LUT4 004F ((aB)+c)d + 7801 LUT4 3A00 D(c?b:A) + 7802 LUT3 A3 C?b:A + 7803 LUT3 C5 C?a:B + 7804 LUT4 FFF2 (Ab)+C+D + 7805 LUT4 3A00 D(c?b:A) + 7806 LUT4 5333 DC?b:b:b:a + 7807 LUT4 AC00 D(c?A:B) + 7808 LUT4 FFF2 (Ab)+C+D + 7809 LUT4 3A00 D(c?b:A) + 7810 LUT4 3A00 D(c?b:A) + 7811 LUT3 A3 C?b:A + 7812 LUT2 4 aB + 7813 LUT2 B /aB\ + 7814 LUT4 3A00 D(c?b:A) + 7815 LUT4 004F ((aB)+c)d + 7816 LUT4 3A00 D(c?b:A) + 7817 LUT3 A3 C?b:A + 7818 LUT4 FFF2 (Ab)+C+D + 7819 LUT4 3500 D(c?b:a) + 7820 LUT4 ACCC DC?B:B:B:A + 7821 LUT4 5300 D(C?b:a) + 7822 LUT4 FFF2 (Ab)+C+D + 7823 LUT4 3500 D(c?b:a) + 7824 LUT4 3A00 D(c?b:A) + 7825 LUT3 53 C?b:a + 7826 LUT3 4F (aB)+c + 7827 LUT4 004F ((aB)+c)d + 7828 LUT4 3500 D(c?b:a) + 7829 LUT3 A3 C?b:A + 7830 LUT3 C5 C?a:B + 7831 LUT3 4F (aB)+c + 7832 LUT4 004F ((aB)+c)d + 7833 LUT4 3500 D(c?b:a) + 7834 LUT3 A3 C?b:A + 7835 LUT3 C5 C?a:B + 7836 LUT2 E /ab\ + 7837 LUT4 3500 D(c?b:a) + 7838 LUT4 3F0A DC?A:1:0:b + 7839 LUT3 D0 C/Ab\ + 7840 LUT3 5C c?a:B + 7841 LUT4 FFF2 (Ab)+C+D + 7842 LUT4 3500 D(c?b:a) + 7843 LUT4 5333 DC?b:b:b:a + 7844 LUT4 AC00 D(c?A:B) + 7845 LUT2 E /ab\ + 7846 LUT4 F800 ((AB)+C)D + 7847 LUT2 4 aB + 7848 LUT2 8 AB + 7849 LUT2 8 AB + 7850 LUT2 8 AB + 7851 LUT2 8 AB + 7852 LUT2 8 AB + 7853 LUT2 8 AB + 7854 LUT2 8 AB + 7855 LUT2 8 AB + 7856 LUT2 8 AB + 7857 LUT2 8 AB + 7858 LUT2 8 AB + 7859 LUT2 8 AB + 7860 LUT3 CA C?A:B + 7861 LUT3 CA C?A:B + 7862 LUT3 CA C?A:B + 7863 LUT3 CA C?A:B + 7864 LUT3 CA C?A:B + 7865 LUT3 CA C?A:B + 7866 LUT3 CA C?A:B + 7867 LUT3 CA C?A:B + 7868 LUT3 CA C?A:B + 7869 LUT3 CA C?A:B + 7870 LUT3 CA C?A:B + 7871 LUT3 CA C?A:B + 7872 LUT3 A3 C?b:A + 7873 LUT3 70 C/AB\ + 7874 LUT2 1 ab + 7875 LUT2 4 aB + 7876 LUT2 8 AB + 7877 LUT2 4 aB + 7878 LUT2 4 aB + 7879 LUT4 0777 /AB\(d+c) + 7880 LUT3 A3 C?b:A + 7881 LUT3 70 C/AB\ + 7882 LUT4 0777 /AB\(d+c) + 7883 LUT3 A3 C?b:A + 7884 LUT3 70 C/AB\ + 7885 LUT4 0777 /AB\(d+c) + 7886 LUT3 A3 C?b:A + 7887 LUT3 70 C/AB\ + 7888 LUT4 0777 /AB\(d+c) + 7889 LUT3 A3 C?b:A + 7890 LUT3 70 C/AB\ + 7891 LUT4 0777 /AB\(d+c) + 7892 LUT3 A3 C?b:A + 7893 LUT3 70 C/AB\ + 7894 LUT4 0777 /AB\(d+c) + 7895 LUT3 A3 C?b:A + 7896 LUT3 70 C/AB\ + 7897 LUT4 0777 /AB\(d+c) + 7898 LUT3 A3 C?b:A + 7899 LUT3 70 C/AB\ + 7900 LUT4 0777 /AB\(d+c) + 7901 LUT3 A3 C?b:A + 7902 LUT3 70 C/AB\ + 7903 LUT4 0777 /AB\(d+c) + 7904 LUT3 A3 C?b:A + 7905 LUT3 70 C/AB\ + 7906 LUT4 0777 /AB\(d+c) + 7907 LUT3 A3 C?b:A + 7908 LUT3 70 C/AB\ + 7909 LUT4 0777 /AB\(d+c) + 7910 LUT3 A3 C?b:A + 7911 LUT3 70 C/AB\ + 7912 LUT4 0777 /AB\(d+c) + 7913 LUT3 A3 C?b:A + 7914 LUT3 70 C/AB\ + 7915 LUT4 0777 /AB\(d+c) + 7916 LUT3 A3 C?b:A + 7917 LUT3 70 C/AB\ + 7918 LUT4 0777 /AB\(d+c) + 7919 LUT3 A3 C?b:A + 7920 LUT3 70 C/AB\ + 7921 LUT4 0777 /AB\(d+c) + 7922 LUT3 A3 C?b:A + 7923 LUT3 70 C/AB\ + 7924 LUT4 0777 /AB\(d+c) + 7925 LUT3 A3 C?b:A + 7926 LUT3 70 C/AB\ + 7927 LUT4 0777 /AB\(d+c) + 7928 LUT3 A3 C?b:A + 7929 LUT3 70 C/AB\ + 7930 LUT4 0777 /AB\(d+c) + 7931 LUT3 A3 C?b:A + 7932 LUT3 70 C/AB\ + 7933 LUT4 0777 /AB\(d+c) + 7934 LUT2 8 AB + 7935 LUT2 8 AB + 7936 LUT2 8 AB + 7937 LUT2 8 AB + 7938 LUT2 8 AB + 7939 LUT2 8 AB + 7940 LUT2 8 AB + 7941 LUT2 8 AB + 7942 LUT2 8 AB + 7943 LUT3 C5 C?a:B + 7944 LUT3 3A c?b:A + 7945 LUT3 CA C?A:B + 7946 LUT2 8 AB + 7947 LUT2 8 AB + 7948 LUT2 8 AB + 7949 LUT2 8 AB + 7950 LUT2 8 AB + 7951 LUT2 8 AB + 7952 LUT2 8 AB + 7953 LUT2 8 AB + 7954 LUT2 8 AB + 7955 LUT3 CA C?A:B + 7956 LUT2 4 aB + 7957 LUT3 80 ABC + 7958 LUT4 0B00 cD/aB\ + 7959 LUT2 8 AB + 7960 LUT2 8 AB + 7961 LUT3 0E c/ab\ + 7962 LUT2 4 aB + 7963 LUT4 1000 abCD + 7964 LUT3 80 ABC + 7965 LUT4 BBB0 /aB\(D+C) + 7966 LUT4 3FA0 DC?0:1:A:b + 7967 LUT3 01 abc + 7968 LUT2 8 AB + 7969 LUT2 4 aB + 7970 LUT3 40 aBC + 7971 LUT3 0D c/Ab\ + 7972 LUT4 CAFF (C?A:B)+d + 7973 LUT4 0777 /AB\(d+c) + 7974 LUT4 004F ((aB)+c)d + 7975 LUT2 1 ab + 7976 LUT4 CAFF (C?A:B)+d + 7977 LUT4 0777 /AB\(d+c) + 7978 LUT2 1 ab + 7979 LUT4 000D cd/Ab\ + 7980 LUT4 004F ((aB)+c)d + 7981 LUT2 8 AB + 7982 LUT4 EEF0 D?C:/ab\ + 7983 LUT4 0777 /AB\(d+c) + 7984 LUT4 004F ((aB)+c)d + 7985 LUT4 8F00 ((AB)+c)D + 7986 LUT4 0777 /AB\(d+c) + 7987 LUT4 4F00 ((aB)+c)D + 7988 LUT4 EEF0 D?C:/ab\ + 7989 LUT4 0777 /AB\(d+c) + 7990 LUT3 B0 C/aB\ + 7991 LUT4 EEF0 D?C:/ab\ + 7992 LUT4 0777 /AB\(d+c) + 7993 LUT2 8 AB + 7994 LUT4 0BBB /aB\(d+c) + 7995 LUT4 0D00 cD/Ab\ + 7996 LUT4 000E cd/ab\ + 7997 LUT2 4 aB + 7998 LUT4 4F00 ((aB)+c)D + 7999 LUT4 4F00 ((aB)+c)D + 8000 LUT4 000D cd/Ab\ + 8001 LUT4 004F ((aB)+c)d + 8002 LUT4 4F00 ((aB)+c)D + 8003 LUT3 B0 C/aB\ + 8004 LUT4 EEF0 D?C:/ab\ + 8005 LUT4 0777 /AB\(d+c) + 8006 LUT3 40 aBC + 8007 LUT4 CFA0 DC?0:1:A:B + 8008 LUT2 1 ab + 8009 LUT4 4F00 ((aB)+c)D + 8010 LUT4 EEF0 D?C:/ab\ + 8011 LUT3 0D c/Ab\ + 8012 LUT4 F011 D?ab:C + 8013 LUT2 4 aB + 8014 LUT4 4F00 ((aB)+c)D + 8015 LUT3 AC c?A:B + 8016 LUT4 000D cd/Ab\ + 8017 LUT4 004F ((aB)+c)d + 8018 LUT4 4F00 ((aB)+c)D + 8019 LUT4 FE00 ((/ab\)+C)D + 8020 LUT3 80 ABC + 8021 LUT4 1000 abCD + 8022 LUT4 D000 CD/Ab\ + 8023 LUT3 10 abC + 8024 LUT4 BBF0 D?C:/aB\ + 8025 LUT4 000D cd/Ab\ + 8026 LUT4 004F ((aB)+c)d + 8027 LUT4 4F00 ((aB)+c)D + 8028 LUT3 B0 C/aB\ + 8029 LUT4 EEF0 D?C:/ab\ + 8030 LUT4 0777 /AB\(d+c) + 8031 LUT4 050C DC?B:a:0:0 + 8032 LUT3 53 C?b:a + 8033 LUT2 1 ab + 8034 LUT2 8 AB + 8035 LUT3 E0 C/ab\ + 8036 LUT4 CAFF (C?A:B)+d + 8037 LUT2 8 AB + 8038 LUT4 00EF ((/ab\)+c)d + 8039 LUT3 10 abC + 8040 LUT4 0E00 cD/ab\ + 8041 LUT3 0E c/ab\ + 8042 LUT4 35FF (c?b:a)+d + 8043 LUT2 8 AB + 8044 LUT4 BBB0 /aB\(D+C) + 8045 LUT3 80 ABC + 8046 LUT4 000B cd/aB\ + 8047 LUT3 10 abC + 8048 LUT2 4 aB + 8049 LUT2 4 aB + 8050 LUT4 000D cd/Ab\ + 8051 LUT4 004F ((aB)+c)d + 8052 LUT4 4F00 ((aB)+c)D + 8053 LUT4 EEF0 D?C:/ab\ + 8054 LUT4 0777 /AB\(d+c) + 8055 LUT4 EEF0 D?C:/ab\ + 8056 LUT4 0D00 cD/Ab\ + 8057 LUT4 004F ((aB)+c)d + 8058 LUT3 70 C/AB\ + 8059 LUT4 F077 D?/AB\:C + 8060 LUT2 1 ab + 8061 LUT2 8 AB + 8062 LUT3 80 ABC + 8063 LUT4 0007 cd/AB\ + 8064 LUT4 00FE ((/ab\)+C)d + 8065 LUT4 0007 cd/AB\ + 8066 LUT2 4 aB + 8067 LUT4 0001 abcd + 8068 LUT3 80 ABC + 8069 LUT2 1 ab + 8070 LUT2 4 aB + 8071 LUT3 01 abc + 8072 LUT4 004F ((aB)+c)d + 8073 LUT4 4F00 ((aB)+c)D + 8074 LUT4 4F00 ((aB)+c)D + 8075 LUT4 EEF0 D?C:/ab\ + 8076 LUT4 0777 /AB\(d+c) + 8077 LUT4 110F D?c:ab + 8078 LUT3 10 abC + 8079 LUT2 4 aB + 8080 LUT4 0BBB /aB\(d+c) + 8081 LUT3 70 C/AB\ + 8082 LUT3 D0 C/Ab\ + 8083 LUT3 01 abc + 8084 LUT4 0E00 cD/ab\ + 8085 LUT4 D000 CD/Ab\ + 8086 LUT4 FE00 ((/ab\)+C)D + 8087 LUT4 4F00 ((aB)+c)D + 8088 LUT4 EEF0 D?C:/ab\ + 8089 LUT4 0777 /AB\(d+c) + 8090 LUT4 4F00 ((aB)+c)D + 8091 LUT4 004F ((aB)+c)d + 8092 LUT4 EEF0 D?C:/ab\ + 8093 LUT3 0D c/Ab\ + 8094 LUT4 000B cd/aB\ + 8095 LUT4 0D00 cD/Ab\ + 8096 LUT3 0D c/Ab\ + 8097 LUT4 7077 /AB\(d+C) + 8098 LUT3 40 aBC + 8099 LUT2 1 ab + 8100 LUT4 8F00 ((AB)+c)D + 8101 LUT2 4 aB + 8102 LUT4 BB0F D?c:/aB\ + 8103 LUT3 01 abc + 8104 LUT3 0E c/ab\ + 8105 LUT4 0D00 cD/Ab\ + 8106 LUT3 80 ABC + 8107 LUT4 0F11 D?ab:c + 8108 LUT4 0001 abcd + 8109 LUT4 0100 abcD + 8110 LUT3 01 abc + 8111 LUT4 004F ((aB)+c)d + 8112 LUT4 4F00 ((aB)+c)D + 8113 LUT4 4F00 ((aB)+c)D + 8114 LUT4 BBF0 D?C:/aB\ + 8115 LUT4 0777 /AB\(d+c) + 8116 LUT2 8 AB + 8117 LUT3 40 aBC + 8118 LUT3 E0 C/ab\ + 8119 LUT4 00FE ((/ab\)+C)d + 8120 LUT2 1 ab + 8121 LUT2 8 AB + 8122 LUT2 4 aB + 8123 LUT4 000B cd/aB\ + 8124 LUT4 000D cd/Ab\ + 8125 LUT4 000B cd/aB\ + 8126 LUT4 00FE ((/ab\)+C)d + 8127 LUT4 D000 CD/Ab\ + 8128 LUT3 0D c/Ab\ + 8129 LUT4 C5FF (C?a:B)+d + 8130 LUT4 0305 DC?a:b:0:0 + 8131 LUT4 FE00 ((/ab\)+C)D + 8132 LUT4 004F ((aB)+c)d + 8133 LUT4 4F00 ((aB)+c)D + 8134 LUT4 4F00 ((aB)+c)D + 8135 LUT4 EEF0 D?C:/ab\ + 8136 LUT4 0777 /AB\(d+c) + 8137 LUT4 FE00 ((/ab\)+C)D + 8138 LUT4 00FE ((/ab\)+C)d + 8139 LUT4 004F ((aB)+c)d + 8140 LUT3 10 abC + 8141 LUT3 10 abC + 8142 LUT4 0700 cD/AB\ + 8143 LUT4 0007 cd/AB\ + 8144 LUT3 01 abc + 8145 LUT4 0D00 cD/Ab\ + 8146 LUT4 F011 D?ab:C + 8147 LUT3 AC c?A:B + 8148 LUT4 000B cd/aB\ + 8149 LUT2 4 aB + 8150 LUT4 00FE ((/ab\)+C)d + 8151 LUT4 D000 CD/Ab\ + 8152 LUT3 10 abC + 8153 LUT4 BB0F D?c:/aB\ + 8154 LUT4 F011 D?ab:C + 8155 LUT4 00FE ((/ab\)+C)d + 8156 LUT3 01 abc + 8157 LUT4 004F ((aB)+c)d + 8158 LUT4 4F00 ((aB)+c)D + 8159 LUT4 4F00 ((aB)+c)D + 8160 LUT4 EEF0 D?C:/ab\ + 8161 LUT4 0777 /AB\(d+c) + 8162 LUT3 D0 C/Ab\ + 8163 LUT4 000B cd/aB\ + 8164 LUT3 0D c/Ab\ + 8165 LUT3 B0 C/aB\ + 8166 LUT2 4 aB + 8167 LUT3 10 abC + 8168 LUT4 E0EE /ab\(d+C) + 8169 LUT3 01 abc + 8170 LUT3 01 abc + 8171 LUT4 4F00 ((aB)+c)D + 8172 LUT4 4F00 ((aB)+c)D + 8173 LUT4 BBF0 D?C:/aB\ + 8174 LUT4 0777 /AB\(d+c) + 8175 LUT4 004F ((aB)+c)d + 8176 LUT4 EEF0 D?C:/ab\ + 8177 LUT4 0D00 cD/Ab\ + 8178 LUT4 000B cd/aB\ + 8179 LUT3 0D c/Ab\ + 8180 LUT4 D000 CD/Ab\ + 8181 LUT4 0D00 cD/Ab\ + 8182 LUT4 77F0 D?C:/AB\ + 8183 LUT4 0F11 D?ab:c + 8184 LUT4 0100 abcD + 8185 LUT4 0001 abcd + 8186 LUT4 000D cd/Ab\ + 8187 LUT3 B0 C/aB\ + 8188 LUT4 4F00 ((aB)+c)D + 8189 LUT4 EEF0 D?C:/ab\ + 8190 LUT4 0777 /AB\(d+c) + 8191 LUT4 004F ((aB)+c)d + 8192 LUT4 BBB0 /aB\(D+C) + 8193 LUT4 050C DC?B:a:0:0 + 8194 LUT3 40 aBC + 8195 LUT2 8 AB + 8196 LUT4 4F00 ((aB)+c)D + 8197 LUT4 1F00 ((ab)+c)D + 8198 LUT4 B0BB /aB\(d+C) + 8199 LUT4 BBB0 /aB\(D+C) + 8200 LUT3 80 ABC + 8201 LUT4 000D cd/Ab\ + 8202 LUT4 008F ((AB)+c)d + 8203 LUT4 0100 abcD + 8204 LUT2 8 AB + 8205 LUT2 8 AB + 8206 LUT4 F800 ((AB)+C)D + 8207 LUT2 4 aB + 8208 LUT2 4 aB + 8209 LUT3 70 C/AB\ + 8210 LUT4 000D cd/Ab\ + 8211 LUT4 5300 D(C?b:a) + 8212 LUT4 000B cd/aB\ + 8213 LUT4 004F ((aB)+c)d + 8214 LUT2 4 aB + 8215 LUT2 8 AB + 8216 LUT4 000E cd/ab\ + 8217 LUT4 4F00 ((aB)+c)D + 8218 LUT4 4F00 ((aB)+c)D + 8219 LUT4 BBF0 D?C:/aB\ + 8220 LUT4 0777 /AB\(d+c) + 8221 LUT4 BB0F D?c:/aB\ + 8222 LUT4 0D00 cD/Ab\ + 8223 LUT4 001F ((ab)+c)d + 8224 LUT3 10 abC + 8225 LUT4 BBB0 /aB\(D+C) + 8226 LUT3 40 aBC + 8227 LUT4 44F0 D?C:aB + 8228 LUT2 1 ab + 8229 LUT3 AC c?A:B + 8230 LUT3 10 abC + 8231 LUT4 0F44 D?aB:c + 8232 LUT4 0700 cD/AB\ + 8233 LUT4 EEE0 /ab\(D+C) + 8234 LUT4 F011 D?ab:C + 8235 LUT2 4 aB + 8236 LUT3 53 C?b:a + 8237 LUT3 01 abc + 8238 LUT3 10 abC + 8239 LUT4 D000 CD/Ab\ + 8240 LUT2 4 aB + 8241 LUT4 E0EE /ab\(d+C) + 8242 LUT2 4 aB + 8243 LUT2 4 aB + 8244 LUT3 10 abC + 8245 LUT4 BBF0 D?C:/aB\ + 8246 LUT4 000D cd/Ab\ + 8247 LUT3 B0 C/aB\ + 8248 LUT4 4F00 ((aB)+c)D + 8249 LUT4 EEF0 D?C:/ab\ + 8250 LUT4 0777 /AB\(d+c) + 8251 LUT4 004F ((aB)+c)d + 8252 LUT2 1 ab + 8253 LUT4 000B cd/aB\ + 8254 LUT2 8 AB + 8255 LUT3 07 c/AB\ + 8256 LUT4 0E00 cD/ab\ + 8257 LUT4 000D cd/Ab\ + 8258 LUT2 4 aB + 8259 LUT4 004F ((aB)+c)d + 8260 LUT2 1 ab + 8261 LUT4 B0BB /aB\(d+C) + 8262 LUT4 0007 cd/AB\ + 8263 LUT4 0007 cd/AB\ + 8264 LUT2 4 aB + 8265 LUT2 1 ab + 8266 LUT4 B0BB /aB\(d+C) + 8267 LUT4 000B cd/aB\ + 8268 LUT2 4 aB + 8269 LUT3 10 abC + 8270 LUT4 D000 CD/Ab\ + 8271 LUT2 4 aB + 8272 LUT4 000E cd/ab\ + 8273 LUT4 4F00 ((aB)+c)D + 8274 LUT4 4F00 ((aB)+c)D + 8275 LUT4 EEF0 D?C:/ab\ + 8276 LUT4 0777 /AB\(d+c) + 8277 LUT4 EEF0 D?C:/ab\ + 8278 LUT4 0001 abcd + 8279 LUT4 0100 abcD + 8280 LUT3 0D c/Ab\ + 8281 LUT4 4F00 ((aB)+c)D + 8282 LUT4 E0EE /ab\(d+C) + 8283 LUT4 000B cd/aB\ + 8284 LUT4 0D00 cD/Ab\ + 8285 LUT3 B0 C/aB\ + 8286 LUT4 EEF0 D?C:/ab\ + 8287 LUT4 000E cd/ab\ + 8288 LUT3 B0 C/aB\ + 8289 LUT4 4F00 ((aB)+c)D + 8290 LUT4 BBF0 D?C:/aB\ + 8291 LUT4 004F ((aB)+c)d + 8292 LUT4 8F00 ((AB)+c)D + 8293 LUT4 4F00 ((aB)+c)D + 8294 LUT3 0D c/Ab\ + 8295 LUT2 4 aB + 8296 LUT4 0503 DC?b:a:0:0 + 8297 LUT4 0E00 cD/ab\ + 8298 LUT4 0503 DC?b:a:0:0 + 8299 LUT3 0D c/Ab\ + 8300 LUT3 E0 C/ab\ + 8301 LUT4 B0BB /aB\(d+C) + 8302 LUT2 4 aB + 8303 LUT2 8 AB + 8304 LUT4 00FE ((/ab\)+C)d + 8305 LUT4 0007 cd/AB\ + 8306 LUT4 F400 ((aB)+C)D + 8307 LUT4 5300 D(C?b:a) + 8308 LUT4 E000 CD/ab\ + 8309 LUT4 5300 D(C?b:a) + 8310 LUT2 4 aB + 8311 LUT3 E0 C/ab\ + 8312 LUT4 B0BB /aB\(d+C) + 8313 LUT4 440F D?c:aB + 8314 LUT4 4F00 ((aB)+c)D + 8315 LUT2 1 ab + 8316 LUT4 000B cd/aB\ + 8317 LUT4 0D00 cD/Ab\ + 8318 LUT3 E0 C/ab\ + 8319 LUT4 B0BB /aB\(d+C) + 8320 LUT4 000B cd/aB\ + 8321 LUT4 4000 aBCD + 8322 LUT2 8 AB + 8323 LUT4 000E cd/ab\ + 8324 LUT3 B0 C/aB\ + 8325 LUT4 4F00 ((aB)+c)D + 8326 LUT4 4F00 ((aB)+c)D + 8327 LUT4 EEF0 D?C:/ab\ + 8328 LUT4 0777 /AB\(d+c) + 8329 LUT4 BB0F D?c:/aB\ + 8330 LUT3 0D c/Ab\ + 8331 LUT3 0D c/Ab\ + 8332 LUT4 E0EE /ab\(d+C) + 8333 LUT4 00F4 ((aB)+C)d + 8334 LUT3 40 aBC + 8335 LUT3 80 ABC + 8336 LUT3 01 abc + 8337 LUT4 3F50 DC?0:1:a:b + 8338 LUT4 44F0 D?C:aB + 8339 LUT4 F400 ((aB)+C)D + 8340 LUT4 0D00 cD/Ab\ + 8341 LUT4 5300 D(C?b:a) + 8342 LUT3 AC c?A:B + 8343 LUT3 E0 C/ab\ + 8344 LUT4 B0BB /aB\(d+C) + 8345 LUT4 000D cd/Ab\ + 8346 LUT4 000B cd/aB\ + 8347 LUT4 D000 CD/Ab\ + 8348 LUT2 1 ab + 8349 LUT4 B0BB /aB\(d+C) + 8350 LUT4 0007 cd/AB\ + 8351 LUT2 4 aB + 8352 LUT4 004F ((aB)+c)d + 8353 LUT4 D000 CD/Ab\ + 8354 LUT2 4 aB + 8355 LUT4 000E cd/ab\ + 8356 LUT3 B0 C/aB\ + 8357 LUT4 4F00 ((aB)+c)D + 8358 LUT4 4F00 ((aB)+c)D + 8359 LUT4 EEF0 D?C:/ab\ + 8360 LUT4 0777 /AB\(d+c) + 8361 LUT4 EEF0 D?C:/ab\ + 8362 LUT4 004F ((aB)+c)d + 8363 LUT2 4 aB + 8364 LUT3 0E c/ab\ + 8365 LUT4 E0EE /ab\(d+C) + 8366 LUT2 4 aB + 8367 LUT2 1 ab + 8368 LUT4 E0EE /ab\(d+C) + 8369 LUT2 1 ab + 8370 LUT3 AC c?A:B + 8371 LUT4 F044 D?aB:C + 8372 LUT4 E0EE /ab\(d+C) + 8373 LUT4 000D cd/Ab\ + 8374 LUT4 5300 D(C?b:a) + 8375 LUT4 000D cd/Ab\ + 8376 LUT4 5300 D(C?b:a) + 8377 LUT4 4F00 ((aB)+c)D + 8378 LUT4 0BBB /aB\(d+c) + 8379 LUT2 4 aB + 8380 LUT4 BF00 ((/aB\)+c)D + 8381 LUT4 770F D?c:/AB\ + 8382 LUT4 000E cd/ab\ + 8383 LUT3 B0 C/aB\ + 8384 LUT4 4F00 ((aB)+c)D + 8385 LUT4 4F00 ((aB)+c)D + 8386 LUT4 BBF0 D?C:/aB\ + 8387 LUT4 0777 /AB\(d+c) + 8388 LUT4 004F ((aB)+c)d + 8389 LUT4 0503 DC?b:a:0:0 + 8390 LUT3 0D c/Ab\ + 8391 LUT4 000E cd/ab\ + 8392 LUT4 F400 ((aB)+C)D + 8393 LUT2 1 ab + 8394 LUT3 70 C/AB\ + 8395 LUT3 E0 C/ab\ + 8396 LUT3 0D c/Ab\ + 8397 LUT3 E0 C/ab\ + 8398 LUT4 0777 /AB\(d+c) + 8399 LUT4 4F00 ((aB)+c)D + 8400 LUT3 AC c?A:B + 8401 LUT4 E0EE /ab\(d+C) + 8402 LUT2 4 aB + 8403 LUT3 D0 C/Ab\ + 8404 LUT4 E0EE /ab\(d+C) + 8405 LUT4 000B cd/aB\ + 8406 LUT4 F100 ((ab)+C)D + 8407 LUT4 0C5F DC?1:B:a:0 + 8408 LUT3 AC c?A:B + 8409 LUT3 D0 C/Ab\ + 8410 LUT3 70 C/AB\ + 8411 LUT4 0BBB /aB\(d+c) + 8412 LUT4 0777 /AB\(d+c) + 8413 LUT3 40 aBC + 8414 LUT4 A300 D(C?b:A) + 8415 LUT3 A3 C?b:A + 8416 LUT3 53 C?b:a + 8417 LUT3 B0 C/aB\ + 8418 LUT4 7077 /AB\(d+C) + 8419 LUT4 0777 /AB\(d+c) + 8420 LUT4 F0EE D?/ab\:C + 8421 LUT2 8 AB + 8422 LUT4 0C0A DC?A:B:0:0 + 8423 LUT2 8 AB + 8424 LUT4 F0EE D?/ab\:C + 8425 LUT4 0C0A DC?A:B:0:0 + 8426 LUT4 F0EE D?/ab\:C + 8427 LUT3 80 ABC + 8428 LUT4 44F0 D?C:aB + 8429 LUT3 CA C?A:B + 8430 LUT4 F0EE D?/ab\:C + 8431 LUT2 8 AB + 8432 LUT4 0C0A DC?A:B:0:0 + 8433 LUT4 F0EE D?/ab\:C + 8434 LUT3 80 ABC + 8435 LUT4 44F0 D?C:aB + 8436 LUT3 CA C?A:B + 8437 LUT4 F0EE D?/ab\:C + 8438 LUT3 80 ABC + 8439 LUT4 44F0 D?C:aB + 8440 LUT3 CA C?A:B + 8441 LUT4 F0EE D?/ab\:C + 8442 LUT3 80 ABC + 8443 LUT4 44F0 D?C:aB + 8444 LUT3 CA C?A:B + 8445 LUT3 AC c?A:B + 8446 LUT2 8 AB + 8447 LUT3 CA C?A:B + 8448 LUT4 F0EE D?/ab\:C + 8449 LUT2 8 AB + 8450 LUT4 0C0A DC?A:B:0:0 + 8451 LUT4 F0EE D?/ab\:C + 8452 LUT2 8 AB + 8453 LUT4 0C0A DC?A:B:0:0 + 8454 LUT4 F0EE D?/ab\:C + 8455 LUT3 80 ABC + 8456 LUT4 44F0 D?C:aB + 8457 LUT3 CA C?A:B + 8458 LUT4 F0EE D?/ab\:C + 8459 LUT2 8 AB + 8460 LUT4 0C0A DC?A:B:0:0 + 8461 LUT4 F0EE D?/ab\:C + 8462 LUT3 80 ABC + 8463 LUT4 44F0 D?C:aB + 8464 LUT3 CA C?A:B + 8465 LUT4 F0EE D?/ab\:C + 8466 LUT3 80 ABC + 8467 LUT4 44F0 D?C:aB + 8468 LUT3 CA C?A:B + 8469 LUT4 F0EE D?/ab\:C + 8470 LUT3 80 ABC + 8471 LUT4 44F0 D?C:aB + 8472 LUT3 CA C?A:B + 8473 LUT3 AC c?A:B + 8474 LUT3 CA C?A:B + 8475 LUT4 F0EE D?/ab\:C + 8476 LUT2 8 AB + 8477 LUT4 0C0A DC?A:B:0:0 + 8478 LUT4 F0EE D?/ab\:C + 8479 LUT4 0C0A DC?A:B:0:0 + 8480 LUT4 F0EE D?/ab\:C + 8481 LUT3 80 ABC + 8482 LUT4 44F0 D?C:aB + 8483 LUT3 CA C?A:B + 8484 LUT4 F0EE D?/ab\:C + 8485 LUT2 8 AB + 8486 LUT4 0C0A DC?A:B:0:0 + 8487 LUT4 F0EE D?/ab\:C + 8488 LUT3 80 ABC + 8489 LUT4 44F0 D?C:aB + 8490 LUT3 CA C?A:B + 8491 LUT4 F0EE D?/ab\:C + 8492 LUT3 80 ABC + 8493 LUT4 44F0 D?C:aB + 8494 LUT3 CA C?A:B + 8495 LUT4 F0EE D?/ab\:C + 8496 LUT3 80 ABC + 8497 LUT4 44F0 D?C:aB + 8498 LUT3 CA C?A:B + 8499 LUT3 AC c?A:B + 8500 LUT2 8 AB + 8501 LUT3 CA C?A:B + 8502 LUT4 F0EE D?/ab\:C + 8503 LUT2 8 AB + 8504 LUT4 0C0A DC?A:B:0:0 + 8505 LUT4 F0EE D?/ab\:C + 8506 LUT4 0C0A DC?A:B:0:0 + 8507 LUT4 F0EE D?/ab\:C + 8508 LUT3 80 ABC + 8509 LUT4 44F0 D?C:aB + 8510 LUT3 CA C?A:B + 8511 LUT4 F0EE D?/ab\:C + 8512 LUT2 8 AB + 8513 LUT4 0C0A DC?A:B:0:0 + 8514 LUT4 F0EE D?/ab\:C + 8515 LUT3 80 ABC + 8516 LUT4 44F0 D?C:aB + 8517 LUT3 CA C?A:B + 8518 LUT4 F0EE D?/ab\:C + 8519 LUT3 80 ABC + 8520 LUT4 44F0 D?C:aB + 8521 LUT3 CA C?A:B + 8522 LUT4 F0EE D?/ab\:C + 8523 LUT3 80 ABC + 8524 LUT4 44F0 D?C:aB + 8525 LUT3 CA C?A:B + 8526 LUT4 CA00 D(C?A:B) + 8527 LUT2 8 AB + 8528 LUT3 CA C?A:B + 8529 LUT4 F0EE D?/ab\:C + 8530 LUT2 8 AB + 8531 LUT4 0C0A DC?A:B:0:0 + 8532 LUT4 F0EE D?/ab\:C + 8533 LUT2 8 AB + 8534 LUT4 0C0A DC?A:B:0:0 + 8535 LUT4 F0EE D?/ab\:C + 8536 LUT3 80 ABC + 8537 LUT4 44F0 D?C:aB + 8538 LUT3 CA C?A:B + 8539 LUT4 F0EE D?/ab\:C + 8540 LUT2 8 AB + 8541 LUT4 0C0A DC?A:B:0:0 + 8542 LUT4 F0EE D?/ab\:C + 8543 LUT3 80 ABC + 8544 LUT4 44F0 D?C:aB + 8545 LUT3 CA C?A:B + 8546 LUT4 F0EE D?/ab\:C + 8547 LUT3 80 ABC + 8548 LUT4 44F0 D?C:aB + 8549 LUT3 CA C?A:B + 8550 LUT4 F0EE D?/ab\:C + 8551 LUT3 80 ABC + 8552 LUT4 44F0 D?C:aB + 8553 LUT4 CA00 D(C?A:B) + 8554 LUT3 CA C?A:B + 8555 LUT4 F0EE D?/ab\:C + 8556 LUT2 8 AB + 8557 LUT4 0C0A DC?A:B:0:0 + 8558 LUT4 F0EE D?/ab\:C + 8559 LUT4 0C0A DC?A:B:0:0 + 8560 LUT4 F0EE D?/ab\:C + 8561 LUT3 80 ABC + 8562 LUT4 44F0 D?C:aB + 8563 LUT3 CA C?A:B + 8564 LUT4 F0EE D?/ab\:C + 8565 LUT2 8 AB + 8566 LUT4 0C0A DC?A:B:0:0 + 8567 LUT3 CA C?A:B + 8568 LUT4 ACCC DC?B:B:B:A + 8569 LUT4 F0EE D?/ab\:C + 8570 LUT3 40 aBC + 8571 LUT4 88F0 D?C:AB + 8572 LUT4 ACCC DC?B:B:B:A + 8573 LUT4 F0EE D?/ab\:C + 8574 LUT3 80 ABC + 8575 LUT4 44F0 D?C:aB + 8576 LUT4 ACCC DC?B:B:B:A + 8577 LUT4 CA00 D(C?A:B) + 8578 LUT2 8 AB + 8579 LUT2 9 a^B + 8580 LUT2 9 a^B + 8581 LUT2 9 a^B + 8582 LUT2 9 a^B + 8583 LUT2 9 a^B + 8584 LUT2 9 a^B + 8585 LUT2 9 a^B + 8586 LUT2 9 a^B + 8587 LUT2 9 a^B + 8588 LUT2 9 a^B + 8589 LUT2 9 a^B + 8590 LUT2 9 a^B + 8591 LUT2 9 a^B + 8592 LUT2 9 a^B + 8593 LUT2 9 a^B + 8594 LUT2 9 a^B + 8595 LUT2 9 a^B + 8596 LUT2 9 a^B + 8597 LUT2 9 a^B + 8598 LUT2 9 a^B + 8599 LUT2 9 a^B + 8600 LUT2 9 a^B + 8601 LUT2 9 a^B + 8602 LUT2 9 a^B + 8603 LUT2 9 a^B + 8604 LUT2 9 a^B + 8605 LUT2 9 a^B + 8606 LUT2 9 a^B + 8607 LUT2 9 a^B + 8608 LUT2 9 a^B + 8609 LUT2 9 a^B + 8610 LUT2 8 AB + 8611 LUT2 8 AB + 8612 LUT4 00EF ((/ab\)+c)d + 8613 LUT4 0100 abcD + 8614 LUT2 8 AB + 8615 LUT2 8 AB + 8616 LUT4 0D00 cD/Ab\ + 8617 LUT4 4000 aBCD + 8618 LUT3 D0 C/Ab\ + 8619 LUT3 D0 C/Ab\ + 8620 LUT3 D0 C/Ab\ + 8621 LUT2 4 aB + 8622 LUT4 BF00 ((/aB\)+c)D + 8623 LUT4 007F ((/AB\)+c)d + 8624 LUT3 40 aBC + 8625 LUT2 8 AB + 8626 LUT3 80 ABC + 8627 LUT3 80 ABC + 8628 LUT3 80 ABC + 8629 LUT3 80 ABC + 8630 LUT3 80 ABC + 8631 LUT4 8000 ABCD + 8632 LUT2 8 AB + 8633 LUT3 80 ABC + 8634 LUT4 8000 ABCD + 8635 LUT2 8 AB + 8636 LUT2 8 AB + 8637 LUT4 8000 ABCD + 8638 LUT2 8 AB + 8639 LUT3 80 ABC + 8640 LUT4 8000 ABCD + 8641 LUT2 8 AB + 8642 LUT2 8 AB + 8643 LUT2 8 AB + 8644 LUT2 8 AB + 8645 LUT3 80 ABC + 8646 LUT3 40 aBC + 8647 LUT4 0007 cd/AB\ + 8648 LUT4 4000 aBCD + 8649 LUT2 8 AB + 8650 LUT2 8 AB + 8651 LUT4 4000 aBCD + 8652 LUT3 80 ABC + 8653 LUT2 8 AB + 8654 LUT3 40 aBC + 8655 LUT4 4F00 ((aB)+c)D + 8656 LUT4 007F ((/AB\)+c)d + 8657 LUT4 4000 aBCD + 8658 LUT2 4 aB + 8659 LUT4 007F ((/AB\)+c)d + 8660 LUT4 4000 aBCD + 8661 LUT2 4 aB + 8662 LUT3 10 abC + 8663 LUT2 4 aB + 8664 LUT2 4 aB + 8665 LUT2 8 AB + 8666 LUT4 0100 abcD + 8667 LUT4 0100 abcD + 8668 LUT2 1 ab + 8669 LUT3 01 abc + 8670 LUT4 1000 abCD + 8671 LUT3 10 abC + 8672 LUT3 10 abC + 8673 LUT4 0001 abcd + 8674 LUT4 0001 abcd + 8675 LUT4 0100 abcD + 8676 LUT4 0BFF (c/aB\)+d + 8677 LUT3 10 abC + 8678 LUT4 0BFF (c/aB\)+d + 8679 LUT4 0001 abcd + 8680 LUT3 40 aBC + 8681 LUT4 F400 ((aB)+C)D + 8682 LUT4 00F4 ((aB)+C)d + 8683 LUT3 80 ABC + 8684 LUT2 1 ab + 8685 LUT2 1 ab + 8686 LUT2 4 aB + 8687 LUT4 7F00 ((/AB\)+c)D + 8688 LUT4 007F ((/AB\)+c)d + 8689 LUT4 4000 aBCD + 8690 LUT2 8 AB + 8691 LUT4 0100 abcD + 8692 LUT4 0777 /AB\(d+c) + 8693 LUT3 0B c/aB\ + 8694 LUT3 70 C/AB\ + 8695 LUT3 40 aBC + 8696 LUT4 0B00 cD/aB\ + 8697 LUT4 7000 CD/AB\ + 8698 LUT3 40 aBC + 8699 LUT4 4000 aBCD + 8700 LUT3 80 ABC + 8701 LUT4 1000 abCD + 8702 LUT4 0001 abcd + 8703 LUT4 0100 abcD + 8704 LUT3 70 C/AB\ + 8705 LUT4 7F00 ((/AB\)+c)D + 8706 LUT4 0001 abcd + 8707 LUT4 1000 abCD + 8708 LUT4 0E00 cD/ab\ + 8709 LUT3 E0 C/ab\ + 8710 LUT4 07FF (c/AB\)+d + 8711 LUT3 01 abc + 8712 LUT2 8 AB + 8713 LUT4 0100 abcD + 8714 LUT4 4000 aBCD + 8715 LUT4 0E00 cD/ab\ + 8716 LUT4 00EF ((/ab\)+c)d + 8717 LUT4 8000 ABCD + 8718 LUT4 001F ((ab)+c)d + 8719 LUT4 4000 aBCD + 8720 LUT4 7000 CD/AB\ + 8721 LUT3 80 ABC + 8722 LUT4 8F00 ((AB)+c)D + 8723 LUT4 8F00 ((AB)+c)D + 8724 LUT4 8000 ABCD + 8725 LUT2 4 aB + 8726 LUT4 1000 abCD + 8727 LUT4 4000 aBCD + 8728 LUT2 8 AB + 8729 LUT4 0100 abcD + 8730 LUT4 8F00 ((AB)+c)D + 8731 LUT4 0100 abcD + 8732 LUT4 00BF ((/aB\)+c)d + 8733 LUT4 1000 abCD + 8734 LUT4 E000 CD/ab\ + 8735 LUT3 10 abC + 8736 LUT4 7F00 ((/AB\)+c)D + 8737 LUT4 0BFF (c/aB\)+d + 8738 LUT4 4000 aBCD + 8739 LUT2 8 AB + 8740 LUT4 1000 abCD + 8741 LUT4 B0FF (C/aB\)+d + 8742 LUT4 00BF ((/aB\)+c)d + 8743 LUT4 007F ((/AB\)+c)d + 8744 LUT4 0700 cD/AB\ + 8745 LUT3 CA C?A:B + 8746 LUT2 4 aB + 8747 LUT3 96 A^B^C + 8748 LUT3 69 A^B^c + 8749 LUT4 0FBB D?/aB\:c + 8750 LUT3 70 C/AB\ + 8751 LUT4 F3F5 DC?a:b:1:1 + 8752 LUT4 0FBB D?/aB\:c + 8753 LUT3 70 C/AB\ + 8754 LUT4 F3F5 DC?a:b:1:1 + 8755 LUT4 0FBB D?/aB\:c + 8756 LUT3 70 C/AB\ + 8757 LUT4 F53F DC?1:a:b:1 + 8758 LUT3 C5 C?a:B + 8759 LUT3 69 A^B^c + 8760 LUT3 69 A^B^c + 8761 LUT4 0FBB D?/aB\:c + 8762 LUT3 70 C/AB\ + 8763 LUT4 F3F5 DC?a:b:1:1 + 8764 LUT4 0FBB D?/aB\:c + 8765 LUT3 70 C/AB\ + 8766 LUT4 F53F DC?1:a:b:1 + 8767 LUT4 0FBB D?/aB\:c + 8768 LUT3 70 C/AB\ + 8769 LUT4 F3F5 DC?a:b:1:1 + 8770 LUT4 C3AA D?A:b^C + 8771 LUT4 F807 (c/AB\)^D + 8772 LUT4 0FBB D?/aB\:c + 8773 LUT3 70 C/AB\ + 8774 LUT4 F3F5 DC?a:b:1:1 + 8775 LUT4 8F00 ((AB)+c)D + 8776 LUT4 F3F5 DC?a:b:1:1 + 8777 LUT3 96 A^B^C + 8778 LUT4 0FBB D?/aB\:c + 8779 LUT3 70 C/AB\ + 8780 LUT4 F53F DC?1:a:b:1 + 8781 LUT4 3CAA D?A:B^C + 8782 LUT3 96 A^B^C + 8783 LUT4 07F8 (c/AB\)^d + 8784 LUT4 0FBB D?/aB\:c + 8785 LUT3 70 C/AB\ + 8786 LUT4 F3F5 DC?a:b:1:1 + 8787 LUT4 8F00 ((AB)+c)D + 8788 LUT4 F3F5 DC?a:b:1:1 + 8789 LUT4 0FBB D?/aB\:c + 8790 LUT3 70 C/AB\ + 8791 LUT4 F3F5 DC?a:b:1:1 + 8792 LUT3 35 c?b:a + 8793 LUT3 70 C/AB\ + 8794 LUT4 F3F5 DC?a:b:1:1 + 8795 LUT3 70 C/AB\ + 8796 LUT4 F3F5 DC?a:b:1:1 + 8797 LUT4 F3F5 DC?a:b:1:1 + 8798 LUT4 F3F5 DC?a:b:1:1 + 8799 LUT4 F3F5 DC?a:b:1:1 + 8800 LUT4 F3F5 DC?a:b:1:1 + 8801 LUT4 F3F5 DC?a:b:1:1 + 8802 LUT4 F3F5 DC?a:b:1:1 + 8803 LUT4 F3F5 DC?a:b:1:1 + 8804 LUT4 F3F5 DC?a:b:1:1 + 8805 LUT4 F3F5 DC?a:b:1:1 + 8806 LUT4 F3F5 DC?a:b:1:1 + 8807 LUT4 553C D?B^C:a + 8808 LUT4 07F8 (c/AB\)^d + 8809 LUT4 8F00 ((AB)+c)D + 8810 LUT4 F3F5 DC?a:b:1:1 + 8811 LUT4 553C D?B^C:a + 8812 LUT4 07F8 (c/AB\)^d + 8813 LUT4 8F00 ((AB)+c)D + 8814 LUT4 F3F5 DC?a:b:1:1 + 8815 LUT4 553C D?B^C:a + 8816 LUT4 07F8 (c/AB\)^d + 8817 LUT4 8F00 ((AB)+c)D + 8818 LUT4 F3F5 DC?a:b:1:1 + 8819 LUT4 553C D?B^C:a + 8820 LUT4 07F8 (c/AB\)^d + 8821 LUT4 8F00 ((AB)+c)D + 8822 LUT4 F3F5 DC?a:b:1:1 + 8823 LUT4 553C D?B^C:a + 8824 LUT4 07F8 (c/AB\)^d + 8825 LUT4 8F00 ((AB)+c)D + 8826 LUT4 F3F5 DC?a:b:1:1 + 8827 LUT4 553C D?B^C:a + 8828 LUT4 07F8 (c/AB\)^d + 8829 LUT4 8F00 ((AB)+c)D + 8830 LUT4 F3F5 DC?a:b:1:1 + 8831 LUT4 553C D?B^C:a + 8832 LUT4 07F8 (c/AB\)^d + 8833 LUT4 8F00 ((AB)+c)D + 8834 LUT4 F3F5 DC?a:b:1:1 + 8835 LUT4 553C D?B^C:a + 8836 LUT4 07F8 (c/AB\)^d + 8837 LUT4 8F00 ((AB)+c)D + 8838 LUT4 F3F5 DC?a:b:1:1 + 8839 LUT4 AA3C D?B^C:A + 8840 LUT4 F807 (c/AB\)^D + 8841 LUT4 0FBB D?/aB\:c + 8842 LUT3 70 C/AB\ + 8843 LUT4 F3F5 DC?a:b:1:1 + 8844 LUT4 8F00 ((AB)+c)D + 8845 LUT4 F3F5 DC?a:b:1:1 + 8846 LUT4 F088 D?AB:C + 8847 LUT3 40 aBC + 8848 LUT2 8 AB + 8849 LUT2 8 AB + 8850 LUT4 0777 /AB\(d+c) + 8851 LUT2 4 aB + 8852 LUT2 8 AB + 8853 LUT4 9009 (a^B)(D^c) + 8854 LUT4 9000 CD(a^B) + 8855 LUT4 B000 CD/aB\ + 8856 LUT4 9009 (a^B)(D^c) + 8857 LUT4 B00B /aB\/D^C\ + 8858 LUT4 F088 D?AB:C + 8859 LUT4 F088 D?AB:C + 8860 LUT4 F088 D?AB:C + 8861 LUT4 F088 D?AB:C + 8862 LUT3 0D c/Ab\ + 8863 LUT4 F088 D?AB:C + 8864 LUT2 1 ab + 8865 LUT4 F088 D?AB:C + 8866 LUT3 40 aBC + 8867 LUT4 FF40 (aBC)+D + 8868 LUT2 8 AB + 8869 LUT4 00F8 ((AB)+C)d + 8870 LUT4 F088 D?AB:C + 8871 LUT2 4 aB + 8872 LUT3 90 C(a^B) + 8873 LUT4 9009 (a^B)(D^c) + 8874 LUT2 8 AB + 8875 LUT4 9009 (a^B)(D^c) + 8876 LUT4 F088 D?AB:C + 8877 LUT4 F088 D?AB:C + 8878 LUT4 F088 D?AB:C + 8879 LUT4 F088 D?AB:C + 8880 LUT4 F088 D?AB:C + 8881 LUT4 F088 D?AB:C + 8882 LUT3 40 aBC + 8883 LUT4 FF40 (aBC)+D + 8884 LUT2 8 AB + 8885 LUT4 00F8 ((AB)+C)d + 8886 LUT4 F088 D?AB:C + 8887 LUT2 4 aB + 8888 LUT2 8 AB + 8889 LUT4 9009 (a^B)(D^c) + 8890 LUT4 9009 (a^B)(D^c) + 8891 LUT4 F088 D?AB:C + 8892 LUT4 F088 D?AB:C + 8893 LUT4 F088 D?AB:C + 8894 LUT4 F088 D?AB:C + 8895 LUT4 F088 D?AB:C + 8896 LUT4 F088 D?AB:C + 8897 LUT3 40 aBC + 8898 LUT4 FF40 (aBC)+D + 8899 LUT2 8 AB + 8900 LUT4 00F8 ((AB)+C)d + 8901 LUT4 F088 D?AB:C + 8902 LUT2 4 aB + 8903 LUT4 0777 /AB\(d+c) + 8904 LUT2 8 AB + 8905 LUT4 9009 (a^B)(D^c) + 8906 LUT4 9000 CD(a^B) + 8907 LUT4 B000 CD/aB\ + 8908 LUT4 9009 (a^B)(D^c) + 8909 LUT4 B00B /aB\/D^C\ + 8910 LUT4 F088 D?AB:C + 8911 LUT4 F088 D?AB:C + 8912 LUT4 F088 D?AB:C + 8913 LUT4 F088 D?AB:C + 8914 LUT4 F088 D?AB:C + 8915 LUT4 F088 D?AB:C + 8916 LUT3 40 aBC + 8917 LUT4 FF40 (aBC)+D + 8918 LUT2 8 AB + 8919 LUT4 00F8 ((AB)+C)d + 8920 LUT3 3A c?b:A + 8921 LUT3 CA C?A:B + 8922 LUT2 4 aB + 8923 LUT2 4 aB + 8924 LUT2 4 aB + 8925 LUT2 4 aB + 8926 LUT2 4 aB + 8927 LUT2 4 aB + 8928 LUT2 4 aB + 8929 LUT2 4 aB + 8930 LUT2 4 aB + 8931 LUT2 4 aB + 8932 LUT3 C5 C?a:B + 8933 LUT2 8 AB + 8934 LUT3 C5 C?a:B + 8935 LUT3 C5 C?a:B + 8936 LUT3 C5 C?a:B + 8937 LUT3 C5 C?a:B + 8938 LUT3 C5 C?a:B + 8939 LUT3 C5 C?a:B + 8940 LUT3 C5 C?a:B + 8941 LUT3 35 c?b:a + 8942 LUT3 35 c?b:a + 8943 LUT3 35 c?b:a + 8944 LUT3 35 c?b:a + 8945 LUT3 35 c?b:a + 8946 LUT3 35 c?b:a + 8947 LUT3 35 c?b:a + 8948 LUT3 35 c?b:a + 8949 LUT3 35 c?b:a + 8950 LUT3 35 c?b:a + 8951 LUT3 35 c?b:a + 8952 LUT3 35 c?b:a + 8953 LUT3 35 c?b:a + 8954 LUT3 35 c?b:a + 8955 LUT3 35 c?b:a + 8956 LUT3 35 c?b:a + 8957 LUT3 35 c?b:a + 8958 LUT3 35 c?b:a + 8959 LUT3 35 c?b:a + 8960 LUT3 35 c?b:a + 8961 LUT3 35 c?b:a + 8962 LUT3 35 c?b:a + 8963 LUT3 35 c?b:a + 8964 LUT3 35 c?b:a + 8965 LUT2 8 AB + 8966 LUT2 4 aB + 8967 LUT2 4 aB + 8968 LUT2 4 aB + 8969 LUT2 4 aB + 8970 LUT2 4 aB + 8971 LUT2 8 AB + 8972 LUT2 8 AB + 8973 LUT2 8 AB + 8974 LUT2 8 AB + 8975 LUT2 8 AB + 8976 LUT2 E /ab\ + 8977 LUT2 E /ab\ + 8978 LUT2 4 aB + 8979 LUT2 4 aB + 8980 LUT2 4 aB + 8981 LUT2 4 aB + 8982 LUT2 4 aB + 8983 LUT2 4 aB + 8984 LUT2 4 aB + 8985 LUT2 4 aB + 8986 LUT2 4 aB + 8987 LUT2 E /ab\ + 8988 LUT2 4 aB + 8989 LUT2 4 aB + 8990 LUT2 4 aB + 8991 LUT2 4 aB + 8992 LUT2 4 aB + 8993 LUT4 4000 aBCD + 8994 LUT3 A3 C?b:A + 8995 LUT3 C5 C?a:B + 8996 LUT2 8 AB + 8997 LUT3 01 abc + 8998 LUT2 4 aB + 8999 LUT3 10 abC + 9000 LUT2 4 aB + 9001 LUT3 0B c/aB\ + 9002 LUT4 0305 DC?a:b:0:0 + 9003 LUT3 35 c?b:a + 9004 LUT4 A333 DC?b:b:b:A + 9005 LUT3 0D c/Ab\ + 9006 LUT4 CA00 D(C?A:B) + 9007 LUT3 A3 C?b:A + 9008 LUT3 C5 C?a:B + 9009 LUT3 0B c/aB\ + 9010 LUT4 0305 DC?a:b:0:0 + 9011 LUT3 35 c?b:a + 9012 LUT4 A333 DC?b:b:b:A + 9013 LUT3 0D c/Ab\ + 9014 LUT4 CA00 D(C?A:B) + 9015 LUT3 AC c?A:B + 9016 LUT4 0FEE D?/ab\:c + 9017 LUT2 4 aB + 9018 LUT3 35 c?b:a + 9019 LUT4 EC0C BD?0:c:AC:1 + 9020 LUT4 A333 DC?b:b:b:A + 9021 LUT3 0D c/Ab\ + 9022 LUT4 CA00 D(C?A:B) + 9023 LUT3 A3 C?b:A + 9024 LUT3 C5 C?a:B + 9025 LUT3 0B c/aB\ + 9026 LUT4 0305 DC?a:b:0:0 + 9027 LUT3 35 c?b:a + 9028 LUT4 A333 DC?b:b:b:A + 9029 LUT3 0D c/Ab\ + 9030 LUT4 CA00 D(C?A:B) + 9031 LUT3 A3 C?b:A + 9032 LUT3 C5 C?a:B + 9033 LUT3 0B c/aB\ + 9034 LUT4 0305 DC?a:b:0:0 + 9035 LUT3 35 c?b:a + 9036 LUT4 A333 DC?b:b:b:A + 9037 LUT3 0D c/Ab\ + 9038 LUT4 CA00 D(C?A:B) + 9039 LUT3 F8 (AB)+C + 9040 LUT4 0305 DC?a:b:0:0 + 9041 LUT3 07 c/AB\ + 9042 LUT4 CEC0 BD?0:C:Ac:1 + 9043 LUT2 4 aB + 9044 LUT4 A333 DC?b:b:b:A + 9045 LUT3 0D c/Ab\ + 9046 LUT4 CA00 D(C?A:B) + 9047 LUT3 F8 (AB)+C + 9048 LUT4 0305 DC?a:b:0:0 + 9049 LUT3 07 c/AB\ + 9050 LUT4 CEC0 BD?0:C:Ac:1 + 9051 LUT2 4 aB + 9052 LUT3 F8 (AB)+C + 9053 LUT4 0305 DC?a:b:0:0 + 9054 LUT3 07 c/AB\ + 9055 LUT4 CEC0 BD?0:C:Ac:1 + 9056 LUT2 4 aB + 9057 LUT4 5333 DC?b:b:b:a + 9058 LUT4 E0EE /ab\(d+C) + 9059 LUT4 0C0A DC?A:B:0:0 + 9060 LUT3 F8 (AB)+C + 9061 LUT4 0305 DC?a:b:0:0 + 9062 LUT3 07 c/AB\ + 9063 LUT4 CEC0 BD?0:C:Ac:1 + 9064 LUT2 4 aB + 9065 LUT4 5333 DC?b:b:b:a + 9066 LUT4 E0EE /ab\(d+C) + 9067 LUT4 0C0A DC?A:B:0:0 + 9068 LUT3 F8 (AB)+C + 9069 LUT4 0305 DC?a:b:0:0 + 9070 LUT3 07 c/AB\ + 9071 LUT4 CEC0 BD?0:C:Ac:1 + 9072 LUT2 4 aB + 9073 LUT4 5333 DC?b:b:b:a + 9074 LUT4 E0EE /ab\(d+C) + 9075 LUT4 0C0A DC?A:B:0:0 + 9076 LUT3 F8 (AB)+C + 9077 LUT4 0305 DC?a:b:0:0 + 9078 LUT3 07 c/AB\ + 9079 LUT4 CEC0 BD?0:C:Ac:1 + 9080 LUT2 4 aB + 9081 LUT3 F8 (AB)+C + 9082 LUT4 0305 DC?a:b:0:0 + 9083 LUT3 07 c/AB\ + 9084 LUT4 CEC0 BD?0:C:Ac:1 + 9085 LUT2 4 aB + 9086 LUT4 5333 DC?b:b:b:a + 9087 LUT4 E0EE /ab\(d+C) + 9088 LUT4 0C0A DC?A:B:0:0 + 9089 LUT3 F8 (AB)+C + 9090 LUT4 0305 DC?a:b:0:0 + 9091 LUT3 07 c/AB\ + 9092 LUT4 CEC0 BD?0:C:Ac:1 + 9093 LUT2 4 aB + 9094 LUT4 5333 DC?b:b:b:a + 9095 LUT4 E0EE /ab\(d+C) + 9096 LUT4 0C0A DC?A:B:0:0 + 9097 LUT3 F8 (AB)+C + 9098 LUT4 0305 DC?a:b:0:0 + 9099 LUT3 07 c/AB\ + 9100 LUT4 CEC0 BD?0:C:Ac:1 + 9101 LUT2 4 aB + 9102 LUT4 5333 DC?b:b:b:a + 9103 LUT4 E0EE /ab\(d+C) + 9104 LUT4 0C0A DC?A:B:0:0 + 9105 LUT3 F8 (AB)+C + 9106 LUT4 0305 DC?a:b:0:0 + 9107 LUT3 07 c/AB\ + 9108 LUT4 CEC0 BD?0:C:Ac:1 + 9109 LUT2 4 aB + 9110 LUT4 5333 DC?b:b:b:a + 9111 LUT4 E0EE /ab\(d+C) + 9112 LUT4 0C0A DC?A:B:0:0 + 9113 LUT3 F8 (AB)+C + 9114 LUT4 0305 DC?a:b:0:0 + 9115 LUT3 07 c/AB\ + 9116 LUT4 CEC0 BD?0:C:Ac:1 + 9117 LUT2 4 aB + 9118 LUT4 5333 DC?b:b:b:a + 9119 LUT4 E0EE /ab\(d+C) + 9120 LUT4 CA00 D(C?A:B) + 9121 LUT3 F8 (AB)+C + 9122 LUT4 0305 DC?a:b:0:0 + 9123 LUT3 07 c/AB\ + 9124 LUT4 CEC0 BD?0:C:Ac:1 + 9125 LUT2 4 aB + 9126 LUT4 5333 DC?b:b:b:a + 9127 LUT4 E0EE /ab\(d+C) + 9128 LUT4 CA00 D(C?A:B) + 9129 LUT3 F8 (AB)+C + 9130 LUT4 0305 DC?a:b:0:0 + 9131 LUT3 07 c/AB\ + 9132 LUT4 CEC0 BD?0:C:Ac:1 + 9133 LUT2 4 aB + 9134 LUT4 5333 DC?b:b:b:a + 9135 LUT4 E0EE /ab\(d+C) + 9136 LUT4 CA00 D(C?A:B) + 9137 LUT3 F8 (AB)+C + 9138 LUT4 0305 DC?a:b:0:0 + 9139 LUT3 07 c/AB\ + 9140 LUT4 CEC0 BD?0:C:Ac:1 + 9141 LUT2 4 aB + 9142 LUT4 5333 DC?b:b:b:a + 9143 LUT4 E0EE /ab\(d+C) + 9144 LUT4 CA00 D(C?A:B) + 9145 LUT3 F8 (AB)+C + 9146 LUT4 0305 DC?a:b:0:0 + 9147 LUT3 07 c/AB\ + 9148 LUT4 CEC0 BD?0:C:Ac:1 + 9149 LUT2 4 aB + 9150 LUT4 5333 DC?b:b:b:a + 9151 LUT4 E0EE /ab\(d+C) + 9152 LUT4 CA00 D(C?A:B) + 9153 LUT3 F8 (AB)+C + 9154 LUT4 0305 DC?a:b:0:0 + 9155 LUT3 07 c/AB\ + 9156 LUT4 CEC0 BD?0:C:Ac:1 + 9157 LUT2 4 aB + 9158 LUT4 5333 DC?b:b:b:a + 9159 LUT4 E0EE /ab\(d+C) + 9160 LUT4 CA00 D(C?A:B) + 9161 LUT3 F8 (AB)+C + 9162 LUT4 0305 DC?a:b:0:0 + 9163 LUT3 07 c/AB\ + 9164 LUT4 CEC0 BD?0:C:Ac:1 + 9165 LUT2 4 aB + 9166 LUT4 5333 DC?b:b:b:a + 9167 LUT4 E0EE /ab\(d+C) + 9168 LUT4 CA00 D(C?A:B) + 9169 LUT3 F8 (AB)+C + 9170 LUT4 0305 DC?a:b:0:0 + 9171 LUT3 07 c/AB\ + 9172 LUT4 CEC0 BD?0:C:Ac:1 + 9173 LUT2 4 aB + 9174 LUT4 5333 DC?b:b:b:a + 9175 LUT4 E0EE /ab\(d+C) + 9176 LUT4 CA00 D(C?A:B) + 9177 LUT3 F8 (AB)+C + 9178 LUT4 0305 DC?a:b:0:0 + 9179 LUT3 07 c/AB\ + 9180 LUT4 CEC0 BD?0:C:Ac:1 + 9181 LUT2 4 aB + 9182 LUT4 5333 DC?b:b:b:a + 9183 LUT4 E0EE /ab\(d+C) + 9184 LUT4 CA00 D(C?A:B) + 9185 LUT3 F8 (AB)+C + 9186 LUT4 0305 DC?a:b:0:0 + 9187 LUT3 07 c/AB\ + 9188 LUT4 CEC0 BD?0:C:Ac:1 + 9189 LUT2 4 aB + 9190 LUT4 5333 DC?b:b:b:a + 9191 LUT4 E0EE /ab\(d+C) + 9192 LUT4 CA00 D(C?A:B) + 9193 LUT3 F8 (AB)+C + 9194 LUT4 0305 DC?a:b:0:0 + 9195 LUT3 07 c/AB\ + 9196 LUT4 CEC0 BD?0:C:Ac:1 + 9197 LUT2 4 aB + 9198 LUT4 5333 DC?b:b:b:a + 9199 LUT4 E0EE /ab\(d+C) + 9200 LUT4 CA00 D(C?A:B) + 9201 LUT3 F8 (AB)+C + 9202 LUT4 0305 DC?a:b:0:0 + 9203 LUT3 07 c/AB\ + 9204 LUT4 CEC0 BD?0:C:Ac:1 + 9205 LUT2 4 aB + 9206 LUT4 5333 DC?b:b:b:a + 9207 LUT4 E0EE /ab\(d+C) + 9208 LUT4 CA00 D(C?A:B) + 9209 LUT3 F8 (AB)+C + 9210 LUT4 0305 DC?a:b:0:0 + 9211 LUT3 07 c/AB\ + 9212 LUT4 CEC0 BD?0:C:Ac:1 + 9213 LUT2 4 aB + 9214 LUT3 F8 (AB)+C + 9215 LUT4 0305 DC?a:b:0:0 + 9216 LUT3 07 c/AB\ + 9217 LUT4 CEC0 BD?0:C:Ac:1 + 9218 LUT2 4 aB + 9219 LUT3 F8 (AB)+C + 9220 LUT4 0305 DC?a:b:0:0 + 9221 LUT3 07 c/AB\ + 9222 LUT4 CEC0 BD?0:C:Ac:1 + 9223 LUT2 4 aB + 9224 LUT3 F8 (AB)+C + 9225 LUT4 0305 DC?a:b:0:0 + 9226 LUT3 07 c/AB\ + 9227 LUT4 CEC0 BD?0:C:Ac:1 + 9228 LUT2 4 aB + 9229 LUT4 5333 DC?b:b:b:a + 9230 LUT4 E0EE /ab\(d+C) + 9231 LUT4 CA00 D(C?A:B) + 9232 LUT3 F8 (AB)+C + 9233 LUT4 0305 DC?a:b:0:0 + 9234 LUT3 07 c/AB\ + 9235 LUT4 CEC0 BD?0:C:Ac:1 + 9236 LUT2 4 aB + 9237 LUT2 4 aB + 9238 LUT4 0F11 D?ab:c + 9239 LUT4 F3F5 DC?a:b:1:1 + 9240 LUT3 70 C/AB\ + 9241 LUT4 F3F5 DC?a:b:1:1 + 9242 LUT3 CA C?A:B + 9243 LUT3 70 C/AB\ + 9244 LUT4 F3F5 DC?a:b:1:1 + 9245 LUT4 0E00 cD/ab\ + 9246 LUT3 07 c/AB\ + 9247 LUT4 7770 /AB\(D+C) + 9248 LUT4 0ECC BD?0:1:Ac:c + 9249 LUT4 000E cd/ab\ + 9250 LUT2 8 AB + 9251 LUT4 8000 ABCD + 9252 LUT3 10 abC + 9253 LUT4 00BF ((/aB\)+c)d + 9254 LUT4 8000 ABCD + 9255 LUT3 80 ABC + 9256 LUT3 0B c/aB\ + 9257 LUT3 40 aBC + 9258 LUT2 4 aB + 9259 LUT3 80 ABC + 9260 LUT3 E0 C/ab\ + 9261 LUT3 0B c/aB\ + 9262 LUT4 00BF ((/aB\)+c)d + 9263 LUT4 008F ((AB)+c)d + 9264 LUT4 BF00 ((/aB\)+c)D + 9265 LUT3 E0 C/ab\ + 9266 LUT4 EF00 ((/ab\)+c)D + 9267 LUT3 0E c/ab\ + 9268 LUT2 4 aB + 9269 LUT4 00BF ((/aB\)+c)d + 9270 LUT3 40 aBC + 9271 LUT2 4 aB + 9272 LUT2 4 aB + 9273 LUT4 4000 aBCD + 9274 LUT4 F400 ((aB)+C)D + 9275 LUT2 8 AB + 9276 LUT2 8 AB + 9277 LUT3 10 abC + 9278 LUT4 F400 ((aB)+C)D + 9279 LUT3 0D c/Ab\ + 9280 LUT3 10 abC + 9281 LUT3 1F (ab)+c + 9282 LUT3 07 c/AB\ + 9283 LUT3 D0 C/Ab\ + 9284 LUT4 BF00 ((/aB\)+c)D + 9285 LUT2 4 aB + 9286 LUT2 4 aB + 9287 LUT2 4 aB + 9288 LUT4 F400 ((aB)+C)D + 9289 LUT2 8 AB + 9290 LUT2 4 aB + 9291 LUT2 8 AB + 9292 LUT2 8 AB + 9293 LUT2 4 aB + 9294 LUT2 8 AB + 9295 LUT2 8 AB + 9296 LUT3 40 aBC + 9297 LUT2 4 aB + 9298 LUT2 4 aB + 9299 LUT2 4 aB + 9300 LUT2 4 aB + 9301 LUT2 4 aB + 9302 LUT2 4 aB + 9303 LUT2 1 ab + 9304 LUT3 4F (aB)+c + 9305 LUT4 8000 ABCD + 9306 LUT4 1000 abCD + 9307 LUT4 0700 cD/AB\ + 9308 LUT4 4000 aBCD + 9309 LUT3 80 ABC + 9310 LUT4 1000 abCD + 9311 LUT2 4 aB + 9312 LUT4 4000 aBCD + 9313 LUT4 8000 ABCD + 9314 LUT2 4 aB + 9315 LUT4 8000 ABCD + 9316 LUT4 8000 ABCD + 9317 LUT4 8000 ABCD + 9318 LUT3 80 ABC + 9319 LUT4 8000 ABCD + 9320 LUT4 8000 ABCD + 9321 LUT4 008F ((AB)+c)d + 9322 LUT3 40 aBC + 9323 LUT4 FE7F AB?/cD\:1:1:/Cd\ + 9324 LUT2 4 aB + 9325 LUT4 1000 abCD + 9326 LUT2 1 ab + 9327 LUT2 1 ab + 9328 LUT2 1 ab + 9329 LUT2 1 ab + 9330 LUT2 1 ab + 9331 LUT2 1 ab + 9332 LUT2 1 ab + 9333 LUT2 1 ab + 9334 LUT2 4 aB + 9335 LUT3 3A c?b:A + 9336 LUT2 8 AB + 9337 LUT4 4000 aBCD + 9338 LUT2 8 AB + 9339 LUT3 40 aBC + 9340 LUT3 3A c?b:A + 9341 LUT3 3A c?b:A + 9342 LUT3 3A c?b:A + 9343 LUT3 3A c?b:A + 9344 LUT3 3A c?b:A + 9345 LUT3 3A c?b:A + 9346 LUT3 3A c?b:A + 9347 LUT3 3A c?b:A + 9348 LUT3 3A c?b:A + 9349 LUT3 3A c?b:A + 9350 LUT3 3A c?b:A + 9351 LUT3 3A c?b:A + 9352 LUT3 3A c?b:A + 9353 LUT3 3A c?b:A + 9354 LUT3 3A c?b:A + 9355 LUT3 3A c?b:A + 9356 LUT3 3A c?b:A + 9357 LUT3 3A c?b:A + 9358 LUT3 3A c?b:A + 9359 LUT3 3A c?b:A + 9360 LUT3 3A c?b:A + 9361 LUT3 3A c?b:A + 9362 LUT3 3A c?b:A + 9363 LUT3 3A c?b:A + 9364 LUT3 3A c?b:A + 9365 LUT3 3A c?b:A + 9366 LUT3 3A c?b:A + 9367 LUT3 3A c?b:A + 9368 LUT3 3A c?b:A + 9369 LUT3 3A c?b:A + 9370 LUT3 3A c?b:A + 9371 LUT3 3A c?b:A + 9372 LUT2 8 AB + 9373 LUT2 8 AB + 9374 LUT2 4 aB + 9375 LUT3 3A c?b:A + 9376 LUT3 3A c?b:A + 9377 LUT3 3A c?b:A + 9378 LUT3 3A c?b:A + 9379 LUT3 3A c?b:A + 9380 LUT3 3A c?b:A + 9381 LUT3 3A c?b:A + 9382 LUT3 3A c?b:A + 9383 LUT3 3A c?b:A + 9384 LUT3 3A c?b:A + 9385 LUT3 3A c?b:A + 9386 LUT3 3A c?b:A + 9387 LUT3 3A c?b:A + 9388 LUT3 3A c?b:A + 9389 LUT3 3A c?b:A + 9390 LUT3 3A c?b:A + 9391 LUT3 3A c?b:A + 9392 LUT3 3A c?b:A + 9393 LUT3 3A c?b:A + 9394 LUT3 3A c?b:A + 9395 LUT3 3A c?b:A + 9396 LUT3 3A c?b:A + 9397 LUT3 3A c?b:A + 9398 LUT3 3A c?b:A + 9399 LUT3 3A c?b:A + 9400 LUT3 3A c?b:A + 9401 LUT3 3A c?b:A + 9402 LUT3 3A c?b:A + 9403 LUT3 3A c?b:A + 9404 LUT3 3A c?b:A + 9405 LUT3 3A c?b:A + 9406 LUT3 3A c?b:A + 9407 LUT2 8 AB + 9408 LUT2 8 AB + 9409 LUT3 40 aBC + 9410 LUT3 3A c?b:A + 9411 LUT3 3A c?b:A + 9412 LUT3 3A c?b:A + 9413 LUT3 3A c?b:A + 9414 LUT3 3A c?b:A + 9415 LUT3 3A c?b:A + 9416 LUT3 3A c?b:A + 9417 LUT3 3A c?b:A + 9418 LUT3 3A c?b:A + 9419 LUT3 3A c?b:A + 9420 LUT3 3A c?b:A + 9421 LUT3 3A c?b:A + 9422 LUT3 3A c?b:A + 9423 LUT3 3A c?b:A + 9424 LUT3 3A c?b:A + 9425 LUT3 3A c?b:A + 9426 LUT3 3A c?b:A + 9427 LUT3 3A c?b:A + 9428 LUT3 3A c?b:A + 9429 LUT3 3A c?b:A + 9430 LUT3 3A c?b:A + 9431 LUT3 3A c?b:A + 9432 LUT3 3A c?b:A + 9433 LUT3 3A c?b:A + 9434 LUT3 3A c?b:A + 9435 LUT3 3A c?b:A + 9436 LUT3 3A c?b:A + 9437 LUT3 3A c?b:A + 9438 LUT3 3A c?b:A + 9439 LUT3 3A c?b:A + 9440 LUT3 3A c?b:A + 9441 LUT3 3A c?b:A + 9442 LUT2 8 AB + 9443 LUT3 3A c?b:A + 9444 LUT3 3A c?b:A + 9445 LUT3 3A c?b:A + 9446 LUT3 3A c?b:A + 9447 LUT3 3A c?b:A + 9448 LUT3 3A c?b:A + 9449 LUT3 3A c?b:A + 9450 LUT3 3A c?b:A + 9451 LUT3 3A c?b:A + 9452 LUT3 3A c?b:A + 9453 LUT3 3A c?b:A + 9454 LUT3 3A c?b:A + 9455 LUT3 3A c?b:A + 9456 LUT3 3A c?b:A + 9457 LUT3 3A c?b:A + 9458 LUT3 3A c?b:A + 9459 LUT3 3A c?b:A + 9460 LUT3 3A c?b:A + 9461 LUT3 3A c?b:A + 9462 LUT3 3A c?b:A + 9463 LUT3 3A c?b:A + 9464 LUT3 3A c?b:A + 9465 LUT3 3A c?b:A + 9466 LUT3 3A c?b:A + 9467 LUT3 3A c?b:A + 9468 LUT3 3A c?b:A + 9469 LUT3 3A c?b:A + 9470 LUT3 3A c?b:A + 9471 LUT3 3A c?b:A + 9472 LUT3 3A c?b:A + 9473 LUT3 3A c?b:A + 9474 LUT3 3A c?b:A + 9475 LUT2 8 AB + 9476 LUT3 3A c?b:A + 9477 LUT3 3A c?b:A + 9478 LUT3 3A c?b:A + 9479 LUT3 3A c?b:A + 9480 LUT3 3A c?b:A + 9481 LUT3 3A c?b:A + 9482 LUT3 3A c?b:A + 9483 LUT3 3A c?b:A + 9484 LUT3 3A c?b:A + 9485 LUT3 3A c?b:A + 9486 LUT3 3A c?b:A + 9487 LUT3 3A c?b:A + 9488 LUT3 3A c?b:A + 9489 LUT3 3A c?b:A + 9490 LUT3 3A c?b:A + 9491 LUT3 3A c?b:A + 9492 LUT3 3A c?b:A + 9493 LUT3 3A c?b:A + 9494 LUT3 3A c?b:A + 9495 LUT3 3A c?b:A + 9496 LUT3 3A c?b:A + 9497 LUT3 3A c?b:A + 9498 LUT3 3A c?b:A + 9499 LUT3 3A c?b:A + 9500 LUT3 3A c?b:A + 9501 LUT3 3A c?b:A + 9502 LUT3 3A c?b:A + 9503 LUT3 3A c?b:A + 9504 LUT3 3A c?b:A + 9505 LUT3 3A c?b:A + 9506 LUT3 3A c?b:A + 9507 LUT3 3A c?b:A + 9508 LUT2 8 AB + 9509 LUT3 3A c?b:A + 9510 LUT3 3A c?b:A + 9511 LUT3 3A c?b:A + 9512 LUT3 3A c?b:A + 9513 LUT3 3A c?b:A + 9514 LUT3 3A c?b:A + 9515 LUT3 3A c?b:A + 9516 LUT3 3A c?b:A + 9517 LUT3 3A c?b:A + 9518 LUT3 3A c?b:A + 9519 LUT3 3A c?b:A + 9520 LUT3 3A c?b:A + 9521 LUT3 3A c?b:A + 9522 LUT3 3A c?b:A + 9523 LUT3 3A c?b:A + 9524 LUT3 3A c?b:A + 9525 LUT3 3A c?b:A + 9526 LUT3 3A c?b:A + 9527 LUT3 3A c?b:A + 9528 LUT3 3A c?b:A + 9529 LUT3 3A c?b:A + 9530 LUT3 3A c?b:A + 9531 LUT3 3A c?b:A + 9532 LUT3 3A c?b:A + 9533 LUT3 3A c?b:A + 9534 LUT3 3A c?b:A + 9535 LUT3 3A c?b:A + 9536 LUT3 3A c?b:A + 9537 LUT3 3A c?b:A + 9538 LUT3 3A c?b:A + 9539 LUT3 3A c?b:A + 9540 LUT3 3A c?b:A + 9541 LUT2 8 AB + 9542 LUT3 10 abC + 9543 LUT3 80 ABC + 9544 LUT3 3A c?b:A + 9545 LUT3 3A c?b:A + 9546 LUT3 3A c?b:A + 9547 LUT3 3A c?b:A + 9548 LUT3 3A c?b:A + 9549 LUT3 3A c?b:A + 9550 LUT3 3A c?b:A + 9551 LUT3 3A c?b:A + 9552 LUT3 3A c?b:A + 9553 LUT3 3A c?b:A + 9554 LUT3 3A c?b:A + 9555 LUT3 3A c?b:A + 9556 LUT3 3A c?b:A + 9557 LUT3 3A c?b:A + 9558 LUT3 3A c?b:A + 9559 LUT3 3A c?b:A + 9560 LUT3 3A c?b:A + 9561 LUT3 3A c?b:A + 9562 LUT3 3A c?b:A + 9563 LUT3 3A c?b:A + 9564 LUT3 3A c?b:A + 9565 LUT3 3A c?b:A + 9566 LUT3 3A c?b:A + 9567 LUT3 3A c?b:A + 9568 LUT3 3A c?b:A + 9569 LUT3 3A c?b:A + 9570 LUT3 3A c?b:A + 9571 LUT3 3A c?b:A + 9572 LUT3 3A c?b:A + 9573 LUT3 3A c?b:A + 9574 LUT3 3A c?b:A + 9575 LUT3 3A c?b:A + 9576 LUT2 8 AB + 9577 LUT3 3A c?b:A + 9578 LUT3 3A c?b:A + 9579 LUT3 3A c?b:A + 9580 LUT3 3A c?b:A + 9581 LUT3 3A c?b:A + 9582 LUT3 3A c?b:A + 9583 LUT3 3A c?b:A + 9584 LUT3 3A c?b:A + 9585 LUT3 3A c?b:A + 9586 LUT3 3A c?b:A + 9587 LUT3 3A c?b:A + 9588 LUT3 3A c?b:A + 9589 LUT3 3A c?b:A + 9590 LUT3 3A c?b:A + 9591 LUT3 3A c?b:A + 9592 LUT3 3A c?b:A + 9593 LUT3 3A c?b:A + 9594 LUT3 3A c?b:A + 9595 LUT3 3A c?b:A + 9596 LUT3 3A c?b:A + 9597 LUT3 3A c?b:A + 9598 LUT3 3A c?b:A + 9599 LUT3 3A c?b:A + 9600 LUT3 3A c?b:A + 9601 LUT3 3A c?b:A + 9602 LUT3 3A c?b:A + 9603 LUT3 3A c?b:A + 9604 LUT3 3A c?b:A + 9605 LUT3 3A c?b:A + 9606 LUT3 3A c?b:A + 9607 LUT3 3A c?b:A + 9608 LUT4 0FEE D?/ab\:c + 9609 LUT4 D000 CD/Ab\ + 9610 LUT2 4 aB + 9611 LUT4 8000 ABCD + 9612 LUT3 10 abC + 9613 LUT2 4 aB + 9614 LUT4 F400 ((aB)+C)D + 9615 LUT4 004F ((aB)+c)d + 9616 LUT2 8 AB + 9617 LUT4 0FEE D?/ab\:c + 9618 LUT4 D000 CD/Ab\ + 9619 LUT2 4 aB + 9620 LUT4 0FEE D?/ab\:c + 9621 LUT4 D000 CD/Ab\ + 9622 LUT2 4 aB + 9623 LUT3 D0 C/Ab\ + 9624 LUT4 0FEE D?/ab\:c + 9625 LUT4 D000 CD/Ab\ + 9626 LUT2 1 ab + 9627 LUT2 4 aB + 9628 LUT2 8 AB + 9629 LUT3 80 ABC + 9630 LUT3 80 ABC + 9631 LUT2 4 aB + 9632 LUT2 4 aB + 9633 LUT2 4 aB + 9634 LUT2 4 aB + 9635 LUT2 4 aB + 9636 LUT2 4 aB + 9637 LUT2 4 aB + 9638 LUT2 4 aB + 9639 LUT2 4 aB + 9640 LUT2 4 aB + 9641 LUT2 4 aB + 9642 LUT2 4 aB + 9643 LUT2 4 aB + 9644 LUT2 4 aB + 9645 LUT2 4 aB + 9646 LUT2 4 aB + 9647 LUT2 4 aB + 9648 LUT2 4 aB + 9649 LUT2 4 aB + 9650 LUT2 4 aB + 9651 LUT2 4 aB + 9652 LUT2 4 aB + 9653 LUT2 4 aB + 9654 LUT2 4 aB + 9655 LUT2 4 aB + 9656 LUT2 4 aB + 9657 LUT2 4 aB + 9658 LUT2 4 aB + 9659 LUT2 4 aB + 9660 LUT2 4 aB + 9661 LUT2 4 aB + 9662 LUT2 4 aB + 9663 LUT4 8000 ABCD + 9664 LUT2 4 aB + 9665 LUT2 4 aB + 9666 LUT2 4 aB + 9667 LUT2 4 aB + 9668 LUT2 4 aB + 9669 LUT2 4 aB + 9670 LUT2 4 aB + 9671 LUT2 4 aB + 9672 LUT2 4 aB + 9673 LUT2 4 aB + 9674 LUT2 4 aB + 9675 LUT2 4 aB + 9676 LUT2 4 aB + 9677 LUT2 4 aB + 9678 LUT2 4 aB + 9679 LUT2 4 aB + 9680 LUT2 4 aB + 9681 LUT2 4 aB + 9682 LUT2 4 aB + 9683 LUT2 4 aB + 9684 LUT2 4 aB + 9685 LUT2 4 aB + 9686 LUT2 4 aB + 9687 LUT2 4 aB + 9688 LUT2 4 aB + 9689 LUT2 4 aB + 9690 LUT2 4 aB + 9691 LUT2 4 aB + 9692 LUT2 4 aB + 9693 LUT2 4 aB + 9694 LUT2 4 aB + 9695 LUT2 8 AB + 9696 LUT2 8 AB + 9697 LUT2 8 AB + 9698 LUT2 8 AB + 9699 LUT2 8 AB + 9700 LUT2 8 AB + 9701 LUT2 8 AB + 9702 LUT2 8 AB + 9703 LUT2 8 AB + 9704 LUT2 8 AB + 9705 LUT2 8 AB + 9706 LUT2 8 AB + 9707 LUT2 8 AB + 9708 LUT2 8 AB + 9709 LUT2 8 AB + 9710 LUT2 8 AB + 9711 LUT2 8 AB + 9712 LUT2 8 AB + 9713 LUT2 8 AB + 9714 LUT2 8 AB + 9715 LUT2 8 AB + 9716 LUT2 8 AB + 9717 LUT2 8 AB + 9718 LUT2 8 AB + 9719 LUT2 8 AB + 9720 LUT2 8 AB + 9721 LUT2 8 AB + 9722 LUT2 8 AB + 9723 LUT2 8 AB + 9724 LUT2 8 AB + 9725 LUT2 8 AB + 9726 LUT2 8 AB + 9727 LUT3 35 c?b:a + 9728 LUT3 80 ABC + 9729 LUT2 8 AB + 9730 LUT3 35 c?b:a + 9731 LUT3 CA C?A:B + 9732 LUT3 CA C?A:B + 9733 LUT3 CA C?A:B + 9734 LUT3 CA C?A:B + 9735 LUT3 CA C?A:B + 9736 LUT3 CA C?A:B + 9737 LUT3 CA C?A:B + 9738 LUT3 CA C?A:B + 9739 LUT3 CA C?A:B + 9740 LUT3 CA C?A:B + 9741 LUT3 CA C?A:B + 9742 LUT3 CA C?A:B + 9743 LUT3 CA C?A:B + 9744 LUT3 CA C?A:B + 9745 LUT3 CA C?A:B + 9746 LUT3 CA C?A:B + 9747 LUT3 CA C?A:B + 9748 LUT3 CA C?A:B + 9749 LUT3 CA C?A:B + 9750 LUT3 CA C?A:B + 9751 LUT3 CA C?A:B + 9752 LUT3 CA C?A:B + 9753 LUT3 CA C?A:B + 9754 LUT3 CA C?A:B + 9755 LUT3 CA C?A:B + 9756 LUT3 CA C?A:B + 9757 LUT3 CA C?A:B + 9758 LUT3 CA C?A:B + 9759 LUT3 CA C?A:B + 9760 LUT3 CA C?A:B + 9761 LUT3 CA C?A:B + 9762 LUT3 CA C?A:B + 9763 LUT3 3A c?b:A + 9764 LUT2 8 AB + 9765 LUT3 3A c?b:A + 9766 LUT3 3A c?b:A + 9767 LUT3 3A c?b:A + 9768 LUT3 3A c?b:A + 9769 LUT3 3A c?b:A + 9770 LUT3 3A c?b:A + 9771 LUT3 3A c?b:A + 9772 LUT3 3A c?b:A + 9773 LUT3 3A c?b:A + 9774 LUT3 3A c?b:A + 9775 LUT3 3A c?b:A + 9776 LUT3 3A c?b:A + 9777 LUT3 3A c?b:A + 9778 LUT3 3A c?b:A + 9779 LUT3 3A c?b:A + 9780 LUT3 3A c?b:A + 9781 LUT3 3A c?b:A + 9782 LUT3 3A c?b:A + 9783 LUT3 3A c?b:A + 9784 LUT3 3A c?b:A + 9785 LUT3 3A c?b:A + 9786 LUT3 3A c?b:A + 9787 LUT3 3A c?b:A + 9788 LUT3 3A c?b:A + 9789 LUT3 3A c?b:A + 9790 LUT3 3A c?b:A + 9791 LUT3 3A c?b:A + 9792 LUT3 3A c?b:A + 9793 LUT3 3A c?b:A + 9794 LUT3 3A c?b:A + 9795 LUT3 3A c?b:A + 9796 LUT3 3A c?b:A + 9797 LUT2 8 AB + 9798 LUT4 1F00 ((ab)+c)D + 9799 LUT3 3A c?b:A + 9800 LUT3 3A c?b:A + 9801 LUT3 3A c?b:A + 9802 LUT3 3A c?b:A + 9803 LUT3 3A c?b:A + 9804 LUT3 3A c?b:A + 9805 LUT3 3A c?b:A + 9806 LUT3 3A c?b:A + 9807 LUT3 3A c?b:A + 9808 LUT3 3A c?b:A + 9809 LUT3 3A c?b:A + 9810 LUT3 3A c?b:A + 9811 LUT3 3A c?b:A + 9812 LUT3 3A c?b:A + 9813 LUT3 3A c?b:A + 9814 LUT3 3A c?b:A + 9815 LUT3 3A c?b:A + 9816 LUT3 3A c?b:A + 9817 LUT3 3A c?b:A + 9818 LUT3 3A c?b:A + 9819 LUT3 3A c?b:A + 9820 LUT3 3A c?b:A + 9821 LUT3 3A c?b:A + 9822 LUT3 3A c?b:A + 9823 LUT3 3A c?b:A + 9824 LUT3 3A c?b:A + 9825 LUT3 3A c?b:A + 9826 LUT3 3A c?b:A + 9827 LUT3 3A c?b:A + 9828 LUT3 3A c?b:A + 9829 LUT3 3A c?b:A + 9830 LUT4 008F ((AB)+c)d + 9831 LUT2 8 AB + 9832 LUT3 D0 C/Ab\ + 9833 LUT3 D0 C/Ab\ + 9834 LUT3 70 C/AB\ + 9835 LUT3 D0 C/Ab\ + 9836 LUT2 1 ab + 9837 LUT4 0777 /AB\(d+c) + 9838 LUT4 FFF8 (AB)+C+D + 9839 LUT4 AC00 D(c?A:B) + 9840 LUT4 FCF5 DC?a:B:1:1 + 9841 LUT4 1000 abCD + 9842 LUT3 07 c/AB\ + 9843 LUT4 0EEE /ab\(d+c) + 9844 LUT3 40 aBC + 9845 LUT3 40 aBC + 9846 LUT4 0B00 cD/aB\ + 9847 LUT3 10 abC + 9848 LUT3 3A c?b:A + 9849 LUT3 53 C?b:a + 9850 LUT4 D000 CD/Ab\ + 9851 LUT4 7077 /AB\(d+C) + 9852 LUT4 7077 /AB\(d+C) + 9853 LUT3 01 abc + 9854 LUT2 4 aB + 9855 LUT4 80FF (ABC)+d + 9856 LUT4 7F00 ((/AB\)+c)D + 9857 LUT4 007F ((/AB\)+c)d + 9858 LUT2 4 aB + 9859 LUT3 80 ABC + 9860 LUT4 0100 abcD + 9861 LUT4 FFF8 (AB)+C+D + 9862 LUT4 CA00 D(C?A:B) + 9863 LUT4 1000 abCD + 9864 LUT3 07 c/AB\ + 9865 LUT4 0EEE /ab\(d+c) + 9866 LUT3 3A c?b:A + 9867 LUT3 35 c?b:a + 9868 LUT4 D000 CD/Ab\ + 9869 LUT4 7077 /AB\(d+C) + 9870 LUT4 7077 /AB\(d+C) + 9871 LUT4 FFF8 (AB)+C+D + 9872 LUT4 CA00 D(C?A:B) + 9873 LUT4 1000 abCD + 9874 LUT4 008F ((AB)+c)d + 9875 LUT2 4 aB + 9876 LUT4 0C05 DC?a:B:0:0 + 9877 LUT3 35 c?b:a + 9878 LUT4 D000 CD/Ab\ + 9879 LUT4 7077 /AB\(d+C) + 9880 LUT4 7077 /AB\(d+C) + 9881 LUT4 FFF8 (AB)+C+D + 9882 LUT4 CA00 D(C?A:B) + 9883 LUT4 1000 abCD + 9884 LUT4 008F ((AB)+c)d + 9885 LUT2 4 aB + 9886 LUT4 0C05 DC?a:B:0:0 + 9887 LUT3 35 c?b:a + 9888 LUT4 D000 CD/Ab\ + 9889 LUT4 7077 /AB\(d+C) + 9890 LUT4 7077 /AB\(d+C) + 9891 LUT4 FFF8 (AB)+C+D + 9892 LUT4 CA00 D(C?A:B) + 9893 LUT4 1000 abCD + 9894 LUT4 008F ((AB)+c)d + 9895 LUT3 D0 C/Ab\ + 9896 LUT4 0D00 cD/Ab\ + 9897 LUT4 C500 D(C?a:B) + 9898 LUT3 35 c?b:a + 9899 LUT3 D0 C/Ab\ + 9900 LUT4 0777 /AB\(d+c) + 9901 LUT4 FFF8 (AB)+C+D + 9902 LUT4 CA00 D(C?A:B) + 9903 LUT4 1000 abCD + 9904 LUT4 008F ((AB)+c)d + 9905 LUT2 4 aB + 9906 LUT4 0C05 DC?a:B:0:0 + 9907 LUT3 35 c?b:a + 9908 LUT4 D000 CD/Ab\ + 9909 LUT4 B0BB /aB\(d+C) + 9910 LUT4 0777 /AB\(d+c) + 9911 LUT4 FFF8 (AB)+C+D + 9912 LUT4 CA00 D(C?A:B) + 9913 LUT4 1000 abCD + 9914 LUT4 008F ((AB)+c)d + 9915 LUT3 D0 C/Ab\ + 9916 LUT3 70 C/AB\ + 9917 LUT4 0D00 cD/Ab\ + 9918 LUT4 0C05 DC?a:B:0:0 + 9919 LUT3 35 c?b:a + 9920 LUT4 7077 /AB\(d+C) + 9921 LUT4 FFF8 (AB)+C+D + 9922 LUT4 CA00 D(C?A:B) + 9923 LUT4 1000 abCD + 9924 LUT4 004F ((aB)+c)d + 9925 LUT3 70 C/AB\ + 9926 LUT3 40 aBC + 9927 LUT4 C500 D(C?a:B) + 9928 LUT3 35 c?b:a + 9929 LUT4 7077 /AB\(d+C) + 9930 LUT4 7077 /AB\(d+C) + 9931 LUT4 FFF8 (AB)+C+D + 9932 LUT4 CA00 D(C?A:B) + 9933 LUT4 1000 abCD + 9934 LUT4 008F ((AB)+c)d + 9935 LUT3 D0 C/Ab\ + 9936 LUT3 40 aBC + 9937 LUT4 C500 D(C?a:B) + 9938 LUT3 35 c?b:a + 9939 LUT4 B0BB /aB\(d+C) + 9940 LUT4 0777 /AB\(d+c) + 9941 LUT4 FFF8 (AB)+C+D + 9942 LUT4 CA00 D(C?A:B) + 9943 LUT4 1000 abCD + 9944 LUT4 008F ((AB)+c)d + 9945 LUT2 4 aB + 9946 LUT4 0C05 DC?a:B:0:0 + 9947 LUT3 35 c?b:a + 9948 LUT4 D000 CD/Ab\ + 9949 LUT4 7077 /AB\(d+C) + 9950 LUT4 7077 /AB\(d+C) + 9951 LUT4 FFF8 (AB)+C+D + 9952 LUT4 CA00 D(C?A:B) + 9953 LUT4 1000 abCD + 9954 LUT4 008F ((AB)+c)d + 9955 LUT3 D0 C/Ab\ + 9956 LUT3 40 aBC + 9957 LUT4 C500 D(C?a:B) + 9958 LUT3 35 c?b:a + 9959 LUT4 7077 /AB\(d+C) + 9960 LUT4 7077 /AB\(d+C) + 9961 LUT4 FFF8 (AB)+C+D + 9962 LUT4 CA00 D(C?A:B) + 9963 LUT4 1000 abCD + 9964 LUT4 008F ((AB)+c)d + 9965 LUT2 4 aB + 9966 LUT4 0C05 DC?a:B:0:0 + 9967 LUT3 35 c?b:a + 9968 LUT4 D000 CD/Ab\ + 9969 LUT4 7077 /AB\(d+C) + 9970 LUT4 7077 /AB\(d+C) + 9971 LUT4 FFF8 (AB)+C+D + 9972 LUT4 CA00 D(C?A:B) + 9973 LUT4 1000 abCD + 9974 LUT3 07 c/AB\ + 9975 LUT4 0EEE /ab\(d+c) + 9976 LUT3 3A c?b:A + 9977 LUT3 35 c?b:a + 9978 LUT4 D000 CD/Ab\ + 9979 LUT4 7077 /AB\(d+C) + 9980 LUT4 7077 /AB\(d+C) + 9981 LUT4 FFF8 (AB)+C+D + 9982 LUT4 CA00 D(C?A:B) + 9983 LUT4 1000 abCD + 9984 LUT4 008F ((AB)+c)d + 9985 LUT3 D0 C/Ab\ + 9986 LUT3 40 aBC + 9987 LUT4 C500 D(C?a:B) + 9988 LUT3 35 c?b:a + 9989 LUT4 7077 /AB\(d+C) + 9990 LUT4 7077 /AB\(d+C) + 9991 LUT4 FFF8 (AB)+C+D + 9992 LUT4 CA00 D(C?A:B) + 9993 LUT4 1000 abCD + 9994 LUT4 008F ((AB)+c)d + 9995 LUT3 D0 C/Ab\ + 9996 LUT3 40 aBC + 9997 LUT4 C500 D(C?a:B) + 9998 LUT3 35 c?b:a + 9999 LUT4 7077 /AB\(d+C) + 10000 LUT4 7077 /AB\(d+C) + 10001 LUT4 FFF8 (AB)+C+D + 10002 LUT4 CA00 D(C?A:B) + 10003 LUT4 1000 abCD + 10004 LUT4 008F ((AB)+c)d + 10005 LUT2 4 aB + 10006 LUT4 0C05 DC?a:B:0:0 + 10007 LUT3 35 c?b:a + 10008 LUT4 D000 CD/Ab\ + 10009 LUT4 7077 /AB\(d+C) + 10010 LUT4 7077 /AB\(d+C) + 10011 LUT4 FFF8 (AB)+C+D + 10012 LUT4 CA00 D(C?A:B) + 10013 LUT4 1000 abCD + 10014 LUT4 008F ((AB)+c)d + 10015 LUT2 4 aB + 10016 LUT4 0C05 DC?a:B:0:0 + 10017 LUT3 35 c?b:a + 10018 LUT4 D000 CD/Ab\ + 10019 LUT4 B0BB /aB\(d+C) + 10020 LUT4 0777 /AB\(d+c) + 10021 LUT4 FFF8 (AB)+C+D + 10022 LUT4 CA00 D(C?A:B) + 10023 LUT4 1000 abCD + 10024 LUT4 004F ((aB)+c)d + 10025 LUT3 70 C/AB\ + 10026 LUT3 40 aBC + 10027 LUT4 C500 D(C?a:B) + 10028 LUT3 35 c?b:a + 10029 LUT4 7077 /AB\(d+C) + 10030 LUT4 7077 /AB\(d+C) + 10031 LUT4 FFF8 (AB)+C+D + 10032 LUT4 CA00 D(C?A:B) + 10033 LUT4 1000 abCD + 10034 LUT4 008F ((AB)+c)d + 10035 LUT3 D0 C/Ab\ + 10036 LUT4 B000 CD/aB\ + 10037 LUT3 3A c?b:A + 10038 LUT3 35 c?b:a + 10039 LUT4 7077 /AB\(d+C) + 10040 LUT4 7077 /AB\(d+C) + 10041 LUT4 FFF8 (AB)+C+D + 10042 LUT4 CA00 D(C?A:B) + 10043 LUT4 1000 abCD + 10044 LUT4 008F ((AB)+c)d + 10045 LUT3 D0 C/Ab\ + 10046 LUT3 40 aBC + 10047 LUT4 C500 D(C?a:B) + 10048 LUT3 35 c?b:a + 10049 LUT4 B0BB /aB\(d+C) + 10050 LUT4 0777 /AB\(d+c) + 10051 LUT4 FFF8 (AB)+C+D + 10052 LUT4 CA00 D(C?A:B) + 10053 LUT4 1000 abCD + 10054 LUT4 008F ((AB)+c)d + 10055 LUT3 D0 C/Ab\ + 10056 LUT4 0D00 cD/Ab\ + 10057 LUT4 C500 D(C?a:B) + 10058 LUT3 35 c?b:a + 10059 LUT3 D0 C/Ab\ + 10060 LUT4 0777 /AB\(d+c) + 10061 LUT4 FFF8 (AB)+C+D + 10062 LUT4 CA00 D(C?A:B) + 10063 LUT4 1000 abCD + 10064 LUT4 008F ((AB)+c)d + 10065 LUT4 D000 CD/Ab\ + 10066 LUT4 BBB0 /aB\(D+C) + 10067 LUT3 3A c?b:A + 10068 LUT3 35 c?b:a + 10069 LUT3 D0 C/Ab\ + 10070 LUT4 0777 /AB\(d+c) + 10071 LUT4 FFF8 (AB)+C+D + 10072 LUT4 CA00 D(C?A:B) + 10073 LUT4 1000 abCD + 10074 LUT4 008F ((AB)+c)d + 10075 LUT4 D000 CD/Ab\ + 10076 LUT4 B0BB /aB\(d+C) + 10077 LUT3 C5 C?a:B + 10078 LUT3 35 c?b:a + 10079 LUT3 D0 C/Ab\ + 10080 LUT4 0777 /AB\(d+c) + 10081 LUT4 FFF8 (AB)+C+D + 10082 LUT4 CA00 D(C?A:B) + 10083 LUT4 1000 abCD + 10084 LUT4 008F ((AB)+c)d + 10085 LUT4 D000 CD/Ab\ + 10086 LUT4 BBB0 /aB\(D+C) + 10087 LUT3 3A c?b:A + 10088 LUT3 35 c?b:a + 10089 LUT3 70 C/AB\ + 10090 LUT4 7077 /AB\(d+C) + 10091 LUT4 FFF8 (AB)+C+D + 10092 LUT4 CA00 D(C?A:B) + 10093 LUT4 1000 abCD + 10094 LUT4 008F ((AB)+c)d + 10095 LUT3 D0 C/Ab\ + 10096 LUT3 40 aBC + 10097 LUT4 C500 D(C?a:B) + 10098 LUT3 35 c?b:a + 10099 LUT4 7077 /AB\(d+C) + 10100 LUT4 7077 /AB\(d+C) + 10101 LUT4 FFF8 (AB)+C+D + 10102 LUT4 CA00 D(C?A:B) + 10103 LUT4 1000 abCD + 10104 LUT4 008F ((AB)+c)d + 10105 LUT3 D0 C/Ab\ + 10106 LUT4 B000 CD/aB\ + 10107 LUT3 3A c?b:A + 10108 LUT3 35 c?b:a + 10109 LUT4 B0BB /aB\(d+C) + 10110 LUT4 0777 /AB\(d+c) + 10111 LUT4 FFF8 (AB)+C+D + 10112 LUT4 CA00 D(C?A:B) + 10113 LUT4 1000 abCD + 10114 LUT4 008F ((AB)+c)d + 10115 LUT2 4 aB + 10116 LUT4 0C05 DC?a:B:0:0 + 10117 LUT3 35 c?b:a + 10118 LUT4 D000 CD/Ab\ + 10119 LUT4 7077 /AB\(d+C) + 10120 LUT4 7077 /AB\(d+C) + 10121 LUT4 FFF8 (AB)+C+D + 10122 LUT4 CA00 D(C?A:B) + 10123 LUT4 1000 abCD + 10124 LUT4 004F ((aB)+c)d + 10125 LUT3 70 C/AB\ + 10126 LUT3 40 aBC + 10127 LUT4 C500 D(C?a:B) + 10128 LUT3 35 c?b:a + 10129 LUT4 7077 /AB\(d+C) + 10130 LUT4 7077 /AB\(d+C) + 10131 LUT4 FFF8 (AB)+C+D + 10132 LUT4 CA00 D(C?A:B) + 10133 LUT4 1000 abCD + 10134 LUT4 008F ((AB)+c)d + 10135 LUT3 D0 C/Ab\ + 10136 LUT3 40 aBC + 10137 LUT4 C500 D(C?a:B) + 10138 LUT3 35 c?b:a + 10139 LUT4 7077 /AB\(d+C) + 10140 LUT4 7077 /AB\(d+C) + 10141 LUT4 FFF8 (AB)+C+D + 10142 LUT4 CA00 D(C?A:B) + 10143 LUT4 1000 abCD + 10144 LUT3 8F (AB)+c + 10145 LUT4 0D00 cD/Ab\ + 10146 LUT4 0D00 cD/Ab\ + 10147 LUT4 0C05 DC?a:B:0:0 + 10148 LUT3 35 c?b:a + 10149 LUT3 D0 C/Ab\ + 10150 LUT4 0777 /AB\(d+c) + 10151 LUT4 FFF8 (AB)+C+D + 10152 LUT4 CA00 D(C?A:B) + 10153 LUT4 1000 abCD + 10154 LUT4 FF80 (ABC)+D + 10155 LUT4 6000 CD(A^B) + 10156 LUT4 0EE0 (A+B)(C^D) + 10157 LUT4 0777 /AB\(d+c) + 10158 LUT4 6000 CD(A^B) + 10159 LUT4 1428 (B^C)(A^D) + 10160 LUT4 0770 (C^D)/AB\ + 10161 LUT4 0EE0 (A+B)(C^D) + 10162 LUT4 1428 (B^C)(A^D) + 10163 LUT4 0EE0 (A+B)(C^D) + 10164 LUT4 6000 CD(A^B) + 10165 LUT4 1400 D(B^C)a + 10166 LUT2 9 a^B + 10167 LUT4 1428 (B^C)(A^D) + 10168 LUT4 1428 (B^C)(A^D) + 10169 LUT4 6000 CD(A^B) + 10170 LUT3 60 C(A^B) + 10171 LUT4 1428 (B^C)(A^D) + 10172 LUT4 0EE0 (A+B)(C^D) + 10173 LUT4 0770 (C^D)/AB\ + 10174 LUT4 1428 (B^C)(A^D) + 10175 LUT4 F444 (aB)+(CD) + 10176 LUT2 1 ab + 10177 LUT2 8 AB + 10178 LUT4 4000 aBCD + 10179 LUT4 F444 (aB)+(CD) + 10180 LUT4 F444 (aB)+(CD) + 10181 LUT4 F444 (aB)+(CD) + 10182 LUT4 F444 (aB)+(CD) + 10183 LUT4 F444 (aB)+(CD) + 10184 LUT4 F444 (aB)+(CD) + 10185 LUT4 F444 (aB)+(CD) + 10186 LUT4 F444 (aB)+(CD) + 10187 LUT4 F444 (aB)+(CD) + 10188 LUT4 F444 (aB)+(CD) + 10189 LUT4 F444 (aB)+(CD) + 10190 LUT4 F444 (aB)+(CD) + 10191 LUT4 F444 (aB)+(CD) + 10192 LUT4 F444 (aB)+(CD) + 10193 LUT4 F444 (aB)+(CD) + 10194 LUT4 F444 (aB)+(CD) + 10195 LUT4 F444 (aB)+(CD) + 10196 LUT4 F444 (aB)+(CD) + 10197 LUT4 F444 (aB)+(CD) + 10198 LUT4 F444 (aB)+(CD) + 10199 LUT4 F444 (aB)+(CD) + 10200 LUT4 F444 (aB)+(CD) + 10201 LUT4 F444 (aB)+(CD) + 10202 LUT4 F444 (aB)+(CD) + 10203 LUT4 F444 (aB)+(CD) + 10204 LUT4 F444 (aB)+(CD) + 10205 LUT4 F444 (aB)+(CD) + 10206 LUT4 F444 (aB)+(CD) + 10207 LUT4 F444 (aB)+(CD) + 10208 LUT4 F444 (aB)+(CD) + 10209 LUT4 F444 (aB)+(CD) + 10210 LUT4 0770 (C^D)/AB\ + 10211 LUT4 1428 (B^C)(A^D) + 10212 LUT4 E000 CD/ab\ + 10213 LUT4 E000 CD/ab\ + 10214 LUT4 1428 (B^C)(A^D) + 10215 LUT4 7770 /AB\(D+C) + 10216 LUT4 0EE0 (A+B)(C^D) + 10217 LUT4 0EE0 (A+B)(C^D) + 10218 LUT4 8000 ABCD + 10219 LUT4 8000 ABCD + 10220 LUT2 6 A^B + 10221 LUT4 1428 (B^C)(A^D) + 10222 LUT4 0EE0 (A+B)(C^D) + 10223 LUT4 0770 (C^D)/AB\ + 10224 LUT3 60 C(A^B) + 10225 LUT4 0777 /AB\(d+c) + 10226 LUT4 0777 /AB\(d+c) + 10227 LUT4 1428 (B^C)(A^D) + 10228 LUT4 F444 (aB)+(CD) + 10229 LUT2 1 ab + 10230 LUT2 8 AB + 10231 LUT4 F444 (aB)+(CD) + 10232 LUT4 F444 (aB)+(CD) + 10233 LUT4 F444 (aB)+(CD) + 10234 LUT4 F444 (aB)+(CD) + 10235 LUT4 F444 (aB)+(CD) + 10236 LUT4 F444 (aB)+(CD) + 10237 LUT4 F444 (aB)+(CD) + 10238 LUT4 F444 (aB)+(CD) + 10239 LUT4 F444 (aB)+(CD) + 10240 LUT4 F444 (aB)+(CD) + 10241 LUT4 F444 (aB)+(CD) + 10242 LUT4 F444 (aB)+(CD) + 10243 LUT4 F444 (aB)+(CD) + 10244 LUT4 F444 (aB)+(CD) + 10245 LUT4 F444 (aB)+(CD) + 10246 LUT4 F444 (aB)+(CD) + 10247 LUT4 F444 (aB)+(CD) + 10248 LUT4 F444 (aB)+(CD) + 10249 LUT4 F444 (aB)+(CD) + 10250 LUT4 F444 (aB)+(CD) + 10251 LUT4 F444 (aB)+(CD) + 10252 LUT4 F444 (aB)+(CD) + 10253 LUT4 F444 (aB)+(CD) + 10254 LUT4 F444 (aB)+(CD) + 10255 LUT4 F444 (aB)+(CD) + 10256 LUT4 F444 (aB)+(CD) + 10257 LUT4 F444 (aB)+(CD) + 10258 LUT4 F444 (aB)+(CD) + 10259 LUT4 F444 (aB)+(CD) + 10260 LUT4 F444 (aB)+(CD) + 10261 LUT4 F444 (aB)+(CD) + 10262 LUT2 8 AB + 10263 LUT2 8 AB + 10264 LUT2 8 AB + 10265 LUT2 4 aB + 10266 LUT2 4 aB + 10267 LUT2 4 aB + 10268 LUT2 4 aB + 10269 LUT2 4 aB + 10270 LUT2 4 aB + 10271 LUT2 4 aB + 10272 LUT2 4 aB + 10273 LUT2 4 aB + 10274 LUT2 4 aB + 10275 LUT2 4 aB + 10276 LUT2 4 aB + 10277 LUT2 4 aB + 10278 LUT2 4 aB + 10279 LUT2 4 aB + 10280 LUT2 4 aB + 10281 LUT2 4 aB + 10282 LUT2 4 aB + 10283 LUT2 4 aB + 10284 LUT2 4 aB + 10285 LUT2 4 aB + 10286 LUT2 4 aB + 10287 LUT2 4 aB + 10288 LUT2 4 aB + 10289 LUT2 4 aB + 10290 LUT2 4 aB + 10291 LUT2 4 aB + 10292 LUT2 4 aB + 10293 LUT2 4 aB + 10294 LUT2 4 aB + 10295 LUT2 1 ab + 10296 LUT2 4 aB + 10297 LUT2 B /aB\ + 10298 LUT2 1 ab + 10299 LUT2 B /aB\ + 10300 LUT2 B /aB\ + 10301 LUT2 8 AB + 10302 LUT3 A3 C?b:A + 10303 LUT3 C5 C?a:B + 10304 LUT2 8 AB + 10305 LUT2 8 AB + 10306 LUT3 A3 C?b:A + 10307 LUT3 C5 C?a:B + 10308 LUT3 A3 C?b:A + 10309 LUT3 C5 C?a:B + 10310 LUT3 A3 C?b:A + 10311 LUT3 C5 C?a:B + 10312 LUT3 3A c?b:A + 10313 LUT2 8 AB + 10314 LUT3 3A c?b:A + 10315 LUT3 3A c?b:A + 10316 LUT3 3A c?b:A + 10317 LUT3 3A c?b:A + 10318 LUT3 3A c?b:A + 10319 LUT3 3A c?b:A + 10320 LUT3 3A c?b:A + 10321 LUT3 3A c?b:A + 10322 LUT3 3A c?b:A + 10323 LUT3 3A c?b:A + 10324 LUT3 3A c?b:A + 10325 LUT3 3A c?b:A + 10326 LUT3 3A c?b:A + 10327 LUT3 3A c?b:A + 10328 LUT3 3A c?b:A + 10329 LUT3 3A c?b:A + 10330 LUT3 3A c?b:A + 10331 LUT3 3A c?b:A + 10332 LUT3 3A c?b:A + 10333 LUT3 3A c?b:A + 10334 LUT3 3A c?b:A + 10335 LUT3 3A c?b:A + 10336 LUT3 3A c?b:A + 10337 LUT3 3A c?b:A + 10338 LUT3 3A c?b:A + 10339 LUT3 3A c?b:A + 10340 LUT3 3A c?b:A + 10341 LUT3 3A c?b:A + 10342 LUT3 3A c?b:A + 10343 LUT3 3A c?b:A + 10344 LUT3 3A c?b:A + 10345 LUT3 3A c?b:A + 10346 LUT2 8 AB + 10347 LUT3 3A c?b:A + 10348 LUT3 3A c?b:A + 10349 LUT3 3A c?b:A + 10350 LUT3 3A c?b:A + 10351 LUT3 3A c?b:A + 10352 LUT3 3A c?b:A + 10353 LUT3 3A c?b:A + 10354 LUT3 3A c?b:A + 10355 LUT3 3A c?b:A + 10356 LUT3 3A c?b:A + 10357 LUT3 3A c?b:A + 10358 LUT3 3A c?b:A + 10359 LUT3 3A c?b:A + 10360 LUT3 3A c?b:A + 10361 LUT3 3A c?b:A + 10362 LUT3 3A c?b:A + 10363 LUT3 3A c?b:A + 10364 LUT3 3A c?b:A + 10365 LUT3 3A c?b:A + 10366 LUT3 3A c?b:A + 10367 LUT3 3A c?b:A + 10368 LUT3 3A c?b:A + 10369 LUT3 3A c?b:A + 10370 LUT3 3A c?b:A + 10371 LUT3 3A c?b:A + 10372 LUT3 3A c?b:A + 10373 LUT3 3A c?b:A + 10374 LUT3 3A c?b:A + 10375 LUT3 3A c?b:A + 10376 LUT3 3A c?b:A + 10377 LUT3 3A c?b:A + 10378 LUT3 CA C?A:B + 10379 LUT3 01 abc + 10380 LUT4 CA00 D(C?A:B) + 10381 LUT2 8 AB + 10382 LUT3 40 aBC + 10383 LUT2 4 aB + 10384 LUT2 B /aB\ + 10385 LUT3 F4 (aB)+C + 10386 LUT3 F8 (AB)+C + 10387 LUT2 4 aB + 10388 LUT2 4 aB + 10389 LUT2 8 AB + 10390 LUT3 40 aBC + 10391 LUT4 F044 D?aB:C + 10392 LUT3 F4 (aB)+C + 10393 LUT2 8 AB + 10394 LUT3 10 abC + 10395 LUT4 F044 D?aB:C + 10396 LUT3 F4 (aB)+C + 10397 LUT2 8 AB + 10398 LUT3 40 aBC + 10399 LUT4 F044 D?aB:C + 10400 LUT3 F4 (aB)+C + 10401 LUT2 8 AB + 10402 LUT3 10 abC + 10403 LUT4 F044 D?aB:C + 10404 LUT3 F4 (aB)+C + 10405 LUT2 8 AB + 10406 LUT3 10 abC + 10407 LUT4 F044 D?aB:C + 10408 LUT3 F4 (aB)+C + 10409 LUT2 8 AB + 10410 LUT3 01 abc + 10411 LUT4 F044 D?aB:C + 10412 LUT3 F4 (aB)+C + 10413 LUT2 8 AB + 10414 LUT3 80 ABC + 10415 LUT3 F4 (aB)+C + 10416 LUT4 F044 D?aB:C + 10417 LUT4 F044 D?aB:C + 10418 LUT3 C5 C?a:B + 10419 LUT3 53 C?b:a + 10420 LUT3 C5 C?a:B + 10421 LUT3 35 c?b:a + 10422 LUT3 C5 C?a:B + 10423 LUT3 35 c?b:a + 10424 LUT3 CA C?A:B + 10425 LUT3 CA C?A:B + 10426 LUT3 CA C?A:B + 10427 LUT3 CA C?A:B + 10428 LUT3 CA C?A:B + 10429 LUT3 CA C?A:B + 10430 LUT3 CA C?A:B + 10431 LUT3 CA C?A:B + 10432 LUT3 CA C?A:B + 10433 LUT3 CA C?A:B + 10434 LUT3 CA C?A:B + 10435 LUT3 CA C?A:B + 10436 LUT3 CA C?A:B + 10437 LUT3 CA C?A:B + 10438 LUT3 CA C?A:B + 10439 LUT3 CA C?A:B + 10440 LUT3 CA C?A:B + 10441 LUT3 CA C?A:B + 10442 LUT3 CA C?A:B + 10443 LUT3 CA C?A:B + 10444 LUT3 CA C?A:B + 10445 LUT3 CA C?A:B + 10446 LUT3 CA C?A:B + 10447 LUT3 CA C?A:B + 10448 LUT3 CA C?A:B + 10449 LUT3 CA C?A:B + 10450 LUT2 E /ab\ + 10451 LUT4 030A DC?A:b:0:0 + 10452 LUT4 000D cd/Ab\ + 10453 LUT2 8 AB + 10454 LUT3 10 abC + 10455 LUT4 001F ((ab)+c)d + 10456 LUT2 8 AB + 10457 LUT2 8 AB + 10458 LUT3 0B c/aB\ + 10459 LUT4 3500 D(c?b:a) + 10460 LUT2 8 AB + 10461 LUT3 35 c?b:a + 10462 LUT3 80 ABC + 10463 LUT2 9 a^B + 10464 LUT2 8 AB + 10465 LUT2 4 aB + 10466 LUT3 10 abC + 10467 LUT3 10 abC + 10468 LUT3 01 abc + 10469 LUT3 07 c/AB\ + 10470 LUT2 4 aB + 10471 LUT3 BF /aB\+c + 10472 LUT2 4 aB + 10473 LUT2 8 AB + 10474 LUT3 F4 (aB)+C + 10475 LUT2 8 AB + 10476 LUT4 0E00 cD/ab\ + 10477 LUT3 8F (AB)+c + 10478 LUT4 0007 cd/AB\ + 10479 LUT4 8000 ABCD + 10480 LUT4 8000 ABCD + 10481 LUT4 0777 /AB\(d+c) + 10482 LUT4 4000 aBCD + 10483 LUT3 96 A^B^C + 10484 LUT3 96 A^B^C + 10485 LUT3 96 A^B^C + 10486 LUT3 96 A^B^C + 10487 LUT4 4000 aBCD + 10488 LUT4 0777 /AB\(d+c) + 10489 LUT4 1000 abCD + 10490 LUT4 1000 abCD + 10491 LUT4 0777 /AB\(d+c) + 10492 LUT4 0001 abcd + 10493 LUT4 0100 abcD + 10494 LUT4 0777 /AB\(d+c) + 10495 LUT4 1000 abCD + 10496 LUT4 1000 abCD + 10497 LUT4 0700 cD/AB\ + 10498 LUT2 8 AB + 10499 LUT4 1000 abCD + 10500 LUT4 0777 /AB\(d+c) + 10501 LUT4 0100 abcD + 10502 LUT4 1000 abCD + 10503 LUT4 4000 aBCD + 10504 LUT4 0777 /AB\(d+c) + 10505 LUT4 0100 abcD + 10506 LUT4 0100 abcD + 10507 LUT4 0777 /AB\(d+c) + 10508 LUT4 4000 aBCD + 10509 LUT4 8000 ABCD + 10510 LUT3 80 ABC + 10511 LUT4 0700 cD/AB\ + 10512 LUT2 8 AB + 10513 LUT4 0777 /AB\(d+c) + 10514 LUT4 0700 cD/AB\ + 10515 LUT2 8 AB + 10516 LUT4 0777 /AB\(d+c) + 10517 LUT4 8000 ABCD + 10518 LUT4 0777 /AB\(d+c) + 10519 LUT4 0777 /AB\(d+c) + 10520 LUT4 0777 /AB\(d+c) + 10521 LUT4 0777 /AB\(d+c) + 10522 LUT4 7D00 AD?0:0:1:B^C + 10523 LUT4 9000 CD(a^B) + 10524 LUT4 D000 CD/Ab\ + 10525 LUT4 B00B /aB\/D^C\ + 10526 LUT4 8000 ABCD + 10527 LUT4 0700 cD/AB\ + 10528 LUT2 8 AB + 10529 LUT4 0777 /AB\(d+c) + 10530 LUT4 8000 ABCD + 10531 LUT4 0777 /AB\(d+c) + 10532 LUT4 0777 /AB\(d+c) + 10533 LUT4 0777 /AB\(d+c) + 10534 LUT4 0777 /AB\(d+c) + 10535 LUT4 0777 /AB\(d+c) + 10536 LUT4 0777 /AB\(d+c) + 10537 LUT4 8000 ABCD + 10538 LUT4 8000 ABCD + 10539 LUT4 0777 /AB\(d+c) + 10540 LUT4 0777 /AB\(d+c) + 10541 LUT4 0777 /AB\(d+c) + 10542 LUT4 0777 /AB\(d+c) + 10543 LUT4 0700 cD/AB\ + 10544 LUT2 8 AB + 10545 LUT4 0777 /AB\(d+c) + 10546 LUT4 0777 /AB\(d+c) + 10547 LUT4 0777 /AB\(d+c) + 10548 LUT4 8000 ABCD + 10549 LUT4 0700 cD/AB\ + 10550 LUT2 8 AB + 10551 LUT4 0777 /AB\(d+c) + 10552 LUT4 8000 ABCD + 10553 LUT4 0777 /AB\(d+c) + 10554 LUT4 0777 /AB\(d+c) + 10555 LUT4 0777 /AB\(d+c) + 10556 LUT4 0777 /AB\(d+c) + 10557 LUT4 0777 /AB\(d+c) + 10558 LUT4 0777 /AB\(d+c) + 10559 LUT2 9 a^B + 10560 LUT2 8 AB + 10561 LUT4 8000 ABCD + 10562 LUT4 0777 /AB\(d+c) + 10563 LUT4 0777 /AB\(d+c) + 10564 LUT4 0777 /AB\(d+c) + 10565 LUT4 0777 /AB\(d+c) + 10566 LUT4 8000 ABCD + 10567 LUT4 0777 /AB\(d+c) + 10568 LUT4 0777 /AB\(d+c) + 10569 LUT4 0777 /AB\(d+c) + 10570 LUT4 0777 /AB\(d+c) + 10571 LUT2 8 AB + 10572 LUT4 8000 ABCD + 10573 LUT4 0777 /AB\(d+c) + 10574 LUT4 0777 /AB\(d+c) + 10575 LUT4 0777 /AB\(d+c) + 10576 LUT4 0777 /AB\(d+c) + 10577 LUT4 8000 ABCD + 10578 LUT4 0777 /AB\(d+c) + 10579 LUT4 0777 /AB\(d+c) + 10580 LUT4 0777 /AB\(d+c) + 10581 LUT4 0777 /AB\(d+c) + 10582 LUT2 9 a^B + 10583 LUT4 8000 ABCD + 10584 LUT4 0700 cD/AB\ + 10585 LUT4 0777 /AB\(d+c) + 10586 LUT2 8 AB + 10587 LUT4 0700 cD/AB\ + 10588 LUT2 8 AB + 10589 LUT4 0777 /AB\(d+c) + 10590 LUT4 0700 cD/AB\ + 10591 LUT4 0777 /AB\(d+c) + 10592 LUT2 8 AB + 10593 LUT4 0700 cD/AB\ + 10594 LUT2 8 AB + 10595 LUT4 0777 /AB\(d+c) + 10596 LUT2 9 a^B + 10597 LUT3 96 A^B^C + 10598 LUT4 8000 ABCD + 10599 LUT4 0700 cD/AB\ + 10600 LUT4 0777 /AB\(d+c) + 10601 LUT2 8 AB + 10602 LUT4 8000 ABCD + 10603 LUT4 0777 /AB\(d+c) + 10604 LUT4 0777 /AB\(d+c) + 10605 LUT4 0777 /AB\(d+c) + 10606 LUT4 0777 /AB\(d+c) + 10607 LUT4 0777 /AB\(d+c) + 10608 LUT4 0777 /AB\(d+c) + 10609 LUT4 8000 ABCD + 10610 LUT4 8000 ABCD + 10611 LUT4 0777 /AB\(d+c) + 10612 LUT4 0777 /AB\(d+c) + 10613 LUT4 0777 /AB\(d+c) + 10614 LUT4 0777 /AB\(d+c) + 10615 LUT4 0700 cD/AB\ + 10616 LUT2 8 AB + 10617 LUT4 0777 /AB\(d+c) + 10618 LUT4 0777 /AB\(d+c) + 10619 LUT4 0777 /AB\(d+c) + 10620 LUT2 9 a^B + 10621 LUT2 9 a^B + 10622 LUT4 8000 ABCD + 10623 LUT3 80 ABC + 10624 LUT4 0700 cD/AB\ + 10625 LUT4 0777 /AB\(d+c) + 10626 LUT2 8 AB + 10627 LUT4 0777 /AB\(d+c) + 10628 LUT4 0777 /AB\(d+c) + 10629 LUT4 0700 cD/AB\ + 10630 LUT4 0777 /AB\(d+c) + 10631 LUT2 8 AB + 10632 LUT4 0777 /AB\(d+c) + 10633 LUT4 0777 /AB\(d+c) + 10634 LUT4 8000 ABCD + 10635 LUT4 8000 ABCD + 10636 LUT4 0777 /AB\(d+c) + 10637 LUT4 0777 /AB\(d+c) + 10638 LUT4 0777 /AB\(d+c) + 10639 LUT4 0777 /AB\(d+c) + 10640 LUT4 0700 cD/AB\ + 10641 LUT2 8 AB + 10642 LUT4 0777 /AB\(d+c) + 10643 LUT4 0777 /AB\(d+c) + 10644 LUT4 0777 /AB\(d+c) + 10645 LUT2 8 AB + 10646 LUT4 4000 aBCD + 10647 LUT4 0100 abcD + 10648 LUT3 80 ABC + 10649 LUT3 10 abC + 10650 LUT2 1 ab + 10651 LUT3 41 (B^c)a + 10652 LUT2 8 AB + 10653 LUT4 8000 ABCD + 10654 LUT4 0777 /AB\(d+c) + 10655 LUT4 0777 /AB\(d+c) + 10656 LUT4 0777 /AB\(d+c) + 10657 LUT4 0777 /AB\(d+c) + 10658 LUT4 8000 ABCD + 10659 LUT4 0777 /AB\(d+c) + 10660 LUT4 0777 /AB\(d+c) + 10661 LUT4 0777 /AB\(d+c) + 10662 LUT4 0777 /AB\(d+c) + 10663 LUT3 41 (B^c)a + 10664 LUT4 8000 ABCD + 10665 LUT4 0700 cD/AB\ + 10666 LUT2 8 AB + 10667 LUT4 0777 /AB\(d+c) + 10668 LUT4 8000 ABCD + 10669 LUT4 0777 /AB\(d+c) + 10670 LUT4 0777 /AB\(d+c) + 10671 LUT4 0777 /AB\(d+c) + 10672 LUT4 0777 /AB\(d+c) + 10673 LUT4 0777 /AB\(d+c) + 10674 LUT4 0777 /AB\(d+c) + 10675 LUT3 41 (B^c)a + 10676 LUT3 80 ABC + 10677 LUT4 0700 cD/AB\ + 10678 LUT4 0777 /AB\(d+c) + 10679 LUT2 8 AB + 10680 LUT4 0700 cD/AB\ + 10681 LUT2 8 AB + 10682 LUT4 0777 /AB\(d+c) + 10683 LUT4 8000 ABCD + 10684 LUT4 0777 /AB\(d+c) + 10685 LUT4 0777 /AB\(d+c) + 10686 LUT4 0777 /AB\(d+c) + 10687 LUT4 0777 /AB\(d+c) + 10688 LUT3 60 C(A^B) + 10689 LUT2 1 ab + 10690 LUT2 4 aB + 10691 LUT4 8000 ABCD + 10692 LUT4 7000 CD/AB\ + 10693 LUT3 70 C/AB\ + 10694 LUT4 0777 /AB\(d+c) + 10695 LUT4 0777 /AB\(d+c) + 10696 LUT4 7000 CD/AB\ + 10697 LUT4 0777 /AB\(d+c) + 10698 LUT4 0777 /AB\(d+c) + 10699 LUT4 0007 cd/AB\ + 10700 LUT2 8 AB + 10701 LUT2 8 AB + 10702 LUT4 0777 /AB\(d+c) + 10703 LUT3 60 C(A^B) + 10704 LUT2 9 a^B + 10705 LUT4 8000 ABCD + 10706 LUT4 0700 cD/AB\ + 10707 LUT4 0777 /AB\(d+c) + 10708 LUT2 8 AB + 10709 LUT4 8000 ABCD + 10710 LUT4 0777 /AB\(d+c) + 10711 LUT4 0777 /AB\(d+c) + 10712 LUT4 0777 /AB\(d+c) + 10713 LUT4 0777 /AB\(d+c) + 10714 LUT4 0777 /AB\(d+c) + 10715 LUT4 0777 /AB\(d+c) + 10716 LUT3 41 (B^c)a + 10717 LUT3 80 ABC + 10718 LUT4 0700 cD/AB\ + 10719 LUT3 70 C/AB\ + 10720 LUT4 0777 /AB\(d+c) + 10721 LUT2 8 AB + 10722 LUT4 7000 CD/AB\ + 10723 LUT4 7000 CD/AB\ + 10724 LUT4 0777 /AB\(d+c) + 10725 LUT4 0777 /AB\(d+c) + 10726 LUT4 0777 /AB\(d+c) + 10727 LUT3 70 C/AB\ + 10728 LUT4 0777 /AB\(d+c) + 10729 LUT2 4 aB + 10730 LUT3 60 C(A^B) + 10731 LUT4 4100 D(B^c)a + 10732 LUT2 4 aB + 10733 LUT3 80 ABC + 10734 LUT4 7000 CD/AB\ + 10735 LUT4 0700 cD/AB\ + 10736 LUT2 8 AB + 10737 LUT4 0777 /AB\(d+c) + 10738 LUT4 0777 /AB\(d+c) + 10739 LUT4 0700 cD/AB\ + 10740 LUT2 8 AB + 10741 LUT4 0777 /AB\(d+c) + 10742 LUT4 7000 CD/AB\ + 10743 LUT4 0777 /AB\(d+c) + 10744 LUT4 0777 /AB\(d+c) + 10745 LUT3 60 C(A^B) + 10746 LUT2 8 AB + 10747 LUT4 8000 ABCD + 10748 LUT4 0777 /AB\(d+c) + 10749 LUT4 0777 /AB\(d+c) + 10750 LUT4 0777 /AB\(d+c) + 10751 LUT4 0777 /AB\(d+c) + 10752 LUT4 8000 ABCD + 10753 LUT4 0777 /AB\(d+c) + 10754 LUT4 0777 /AB\(d+c) + 10755 LUT4 0777 /AB\(d+c) + 10756 LUT4 0777 /AB\(d+c) + 10757 LUT4 4114 AB?C^D:0:c^D:0 + 10758 LUT2 6 A^B + 10759 LUT4 8000 ABCD + 10760 LUT4 7000 CD/AB\ + 10761 LUT4 0007 cd/AB\ + 10762 LUT2 8 AB + 10763 LUT2 8 AB + 10764 LUT4 0777 /AB\(d+c) + 10765 LUT4 7000 CD/AB\ + 10766 LUT4 0777 /AB\(d+c) + 10767 LUT4 0777 /AB\(d+c) + 10768 LUT3 70 C/AB\ + 10769 LUT4 0777 /AB\(d+c) + 10770 LUT4 0777 /AB\(d+c) + 10771 LUT4 8000 ABCD + 10772 LUT4 8000 ABCD + 10773 LUT4 0777 /AB\(d+c) + 10774 LUT4 0777 /AB\(d+c) + 10775 LUT4 0777 /AB\(d+c) + 10776 LUT4 0777 /AB\(d+c) + 10777 LUT4 0700 cD/AB\ + 10778 LUT2 8 AB + 10779 LUT4 0777 /AB\(d+c) + 10780 LUT4 0777 /AB\(d+c) + 10781 LUT4 0777 /AB\(d+c) + 10782 LUT2 9 a^B + 10783 LUT4 8000 ABCD + 10784 LUT4 8000 ABCD + 10785 LUT4 0777 /AB\(d+c) + 10786 LUT4 0777 /AB\(d+c) + 10787 LUT4 0777 /AB\(d+c) + 10788 LUT4 0777 /AB\(d+c) + 10789 LUT4 0700 cD/AB\ + 10790 LUT2 8 AB + 10791 LUT4 0777 /AB\(d+c) + 10792 LUT4 0777 /AB\(d+c) + 10793 LUT4 0777 /AB\(d+c) + 10794 LUT4 8000 ABCD + 10795 LUT4 0700 cD/AB\ + 10796 LUT2 8 AB + 10797 LUT4 0777 /AB\(d+c) + 10798 LUT4 8000 ABCD + 10799 LUT4 0777 /AB\(d+c) + 10800 LUT4 0777 /AB\(d+c) + 10801 LUT4 0777 /AB\(d+c) + 10802 LUT4 0777 /AB\(d+c) + 10803 LUT4 0777 /AB\(d+c) + 10804 LUT4 0777 /AB\(d+c) + 10805 LUT2 8 AB + 10806 LUT4 8000 ABCD + 10807 LUT4 0777 /AB\(d+c) + 10808 LUT4 0777 /AB\(d+c) + 10809 LUT4 0777 /AB\(d+c) + 10810 LUT4 0777 /AB\(d+c) + 10811 LUT4 8000 ABCD + 10812 LUT4 0777 /AB\(d+c) + 10813 LUT4 0777 /AB\(d+c) + 10814 LUT4 0777 /AB\(d+c) + 10815 LUT4 0777 /AB\(d+c) + 10816 LUT4 8000 ABCD + 10817 LUT4 0700 cD/AB\ + 10818 LUT2 8 AB + 10819 LUT4 0777 /AB\(d+c) + 10820 LUT4 8000 ABCD + 10821 LUT4 0777 /AB\(d+c) + 10822 LUT4 0777 /AB\(d+c) + 10823 LUT4 0777 /AB\(d+c) + 10824 LUT4 0777 /AB\(d+c) + 10825 LUT4 0777 /AB\(d+c) + 10826 LUT4 0777 /AB\(d+c) + 10827 LUT4 B0BB /aB\(d+C) + 10828 LUT2 4 aB + 10829 LUT2 4 aB + 10830 LUT4 8000 ABCD + 10831 LUT4 8000 ABCD + 10832 LUT4 0777 /AB\(d+c) + 10833 LUT4 0777 /AB\(d+c) + 10834 LUT4 0777 /AB\(d+c) + 10835 LUT4 0777 /AB\(d+c) + 10836 LUT4 0700 cD/AB\ + 10837 LUT4 0777 /AB\(d+c) + 10838 LUT2 8 AB + 10839 LUT4 0777 /AB\(d+c) + 10840 LUT4 0777 /AB\(d+c) + 10841 LUT4 8000 ABCD + 10842 LUT4 0700 cD/AB\ + 10843 LUT4 0777 /AB\(d+c) + 10844 LUT2 8 AB + 10845 LUT4 8000 ABCD + 10846 LUT4 0777 /AB\(d+c) + 10847 LUT4 0777 /AB\(d+c) + 10848 LUT4 0777 /AB\(d+c) + 10849 LUT4 0777 /AB\(d+c) + 10850 LUT4 0777 /AB\(d+c) + 10851 LUT4 0777 /AB\(d+c) + 10852 LUT4 B0BB /aB\(d+C) + 10853 LUT2 8 AB + 10854 LUT2 8 AB + 10855 LUT4 0990 (a^B)(d^c) + 10856 LUT4 9009 (a^B)(D^c) + 10857 LUT2 4 aB + 10858 LUT4 0777 /AB\(d+c) + 10859 LUT2 8 AB + 10860 LUT2 8 AB + 10861 LUT4 9009 (a^B)(D^c) + 10862 LUT4 0990 (a^B)(d^c) + 10863 LUT2 1 ab + 10864 LUT2 8 AB + 10865 LUT2 8 AB + 10866 LUT4 1428 (B^C)(A^D) + 10867 LUT2 8 AB + 10868 LUT2 8 AB + 10869 LUT4 1428 (B^C)(A^D) + 10870 LUT2 4 aB + 10871 LUT2 8 AB + 10872 LUT2 8 AB + 10873 LUT4 4182 (b^C)(A^D) + 10874 LUT2 8 AB + 10875 LUT2 8 AB + 10876 LUT2 8 AB + 10877 LUT4 0777 /AB\(d+c) + 10878 LUT2 8 AB + 10879 LUT2 8 AB + 10880 LUT4 4182 (b^C)(A^D) + 10881 LUT2 8 AB + 10882 LUT2 8 AB + 10883 LUT2 8 AB + 10884 LUT2 8 AB + 10885 LUT2 8 AB + 10886 LUT2 8 AB + 10887 LUT2 8 AB + 10888 LUT2 8 AB + 10889 LUT2 8 AB + 10890 LUT2 8 AB + 10891 LUT2 8 AB + 10892 LUT2 8 AB + 10893 LUT2 8 AB + 10894 LUT4 4000 aBCD + 10895 LUT4 7000 CD/AB\ + 10896 LUT4 0777 /AB\(d+c) + 10897 LUT2 8 AB + 10898 LUT2 8 AB + 10899 LUT4 0777 /AB\(d+c) + 10900 LUT2 8 AB + 10901 LUT2 8 AB + 10902 LUT2 8 AB + 10903 LUT2 8 AB + 10904 LUT3 70 C/AB\ + 10905 LUT4 0777 /AB\(d+c) + 10906 LUT2 8 AB + 10907 LUT2 8 AB + 10908 LUT2 8 AB + 10909 LUT4 0777 /AB\(d+c) + 10910 LUT2 8 AB + 10911 LUT2 8 AB + 10912 LUT2 8 AB + 10913 LUT2 8 AB + 10914 LUT4 7000 CD/AB\ + 10915 LUT4 0777 /AB\(d+c) + 10916 LUT2 8 AB + 10917 LUT2 8 AB + 10918 LUT2 8 AB + 10919 LUT4 0777 /AB\(d+c) + 10920 LUT2 8 AB + 10921 LUT2 8 AB + 10922 LUT2 8 AB + 10923 LUT2 8 AB + 10924 LUT4 0700 cD/AB\ + 10925 LUT3 70 C/AB\ + 10926 LUT4 0777 /AB\(d+c) + 10927 LUT2 8 AB + 10928 LUT2 8 AB + 10929 LUT2 8 AB + 10930 LUT2 8 AB + 10931 LUT2 8 AB + 10932 LUT2 8 AB + 10933 LUT2 8 AB + 10934 LUT2 8 AB + 10935 LUT2 8 AB + 10936 LUT2 8 AB + 10937 LUT4 4000 aBCD + 10938 LUT2 8 AB + 10939 LUT2 8 AB + 10940 LUT2 8 AB + 10941 LUT2 8 AB + 10942 LUT4 0777 /AB\(d+c) + 10943 LUT2 8 AB + 10944 LUT2 8 AB + 10945 LUT2 8 AB + 10946 LUT2 8 AB + 10947 LUT3 70 C/AB\ + 10948 LUT4 0700 cD/AB\ + 10949 LUT2 8 AB + 10950 LUT2 8 AB + 10951 LUT4 0777 /AB\(d+c) + 10952 LUT2 8 AB + 10953 LUT2 8 AB + 10954 LUT2 8 AB + 10955 LUT2 8 AB + 10956 LUT2 8 AB + 10957 LUT2 8 AB + 10958 LUT4 0777 /AB\(d+c) + 10959 LUT2 8 AB + 10960 LUT2 8 AB + 10961 LUT4 7000 CD/AB\ + 10962 LUT4 0777 /AB\(d+c) + 10963 LUT2 8 AB + 10964 LUT2 8 AB + 10965 LUT4 0777 /AB\(d+c) + 10966 LUT2 8 AB + 10967 LUT2 8 AB + 10968 LUT2 8 AB + 10969 LUT2 8 AB + 10970 LUT2 8 AB + 10971 LUT2 8 AB + 10972 LUT4 0700 cD/AB\ + 10973 LUT2 8 AB + 10974 LUT4 0777 /AB\(d+c) + 10975 LUT4 0777 /AB\(d+c) + 10976 LUT4 0777 /AB\(d+c) + 10977 LUT4 0777 /AB\(d+c) + 10978 LUT2 8 AB + 10979 LUT4 0777 /AB\(d+c) + 10980 LUT4 0700 cD/AB\ + 10981 LUT4 0777 /AB\(d+c) + 10982 LUT2 8 AB + 10983 LUT4 0777 /AB\(d+c) + 10984 LUT2 8 AB + 10985 LUT4 0700 cD/AB\ + 10986 LUT2 8 AB + 10987 LUT4 0777 /AB\(d+c) + 10988 LUT4 0700 cD/AB\ + 10989 LUT4 0777 /AB\(d+c) + 10990 LUT2 8 AB + 10991 LUT4 0700 cD/AB\ + 10992 LUT4 0700 cD/AB\ + 10993 LUT2 8 AB + 10994 LUT4 0777 /AB\(d+c) + 10995 LUT4 0777 /AB\(d+c) + 10996 LUT4 0777 /AB\(d+c) + 10997 LUT2 8 AB + 10998 LUT4 0C05 DC?a:B:0:0 + 10999 LUT2 1 ab + 11000 LUT3 BF /aB\+c + 11001 LUT3 6F (A^B)+c + 11002 LUT4 4114 AB?C^D:0:c^D:0 + 11003 LUT4 7887 (AB)^C^d + 11004 LUT4 4000 aBCD + 11005 LUT3 96 A^B^C + 11006 LUT3 96 A^B^C + 11007 LUT3 96 A^B^C + 11008 LUT3 96 A^B^C + 11009 LUT4 4000 aBCD + 11010 LUT4 8000 ABCD + 11011 LUT4 4000 aBCD + 11012 LUT4 0777 /AB\(d+c) + 11013 LUT4 0100 abcD + 11014 LUT4 1000 abCD + 11015 LUT4 0777 /AB\(d+c) + 11016 LUT4 4000 aBCD + 11017 LUT4 1000 abCD + 11018 LUT4 0777 /AB\(d+c) + 11019 LUT4 1000 abCD + 11020 LUT4 0001 abcd + 11021 LUT4 7000 CD/AB\ + 11022 LUT3 70 C/AB\ + 11023 LUT4 0777 /AB\(d+c) + 11024 LUT4 0100 abcD + 11025 LUT4 1000 abCD + 11026 LUT4 1000 abCD + 11027 LUT4 0777 /AB\(d+c) + 11028 LUT4 0100 abcD + 11029 LUT4 1000 abCD + 11030 LUT4 0100 abcD + 11031 LUT4 8000 ABCD + 11032 LUT4 0700 cD/AB\ + 11033 LUT4 0777 /AB\(d+c) + 11034 LUT2 8 AB + 11035 LUT4 8000 ABCD + 11036 LUT4 0777 /AB\(d+c) + 11037 LUT4 0777 /AB\(d+c) + 11038 LUT4 0777 /AB\(d+c) + 11039 LUT4 0777 /AB\(d+c) + 11040 LUT4 0777 /AB\(d+c) + 11041 LUT4 0777 /AB\(d+c) + 11042 LUT4 8000 ABCD + 11043 LUT4 0700 cD/AB\ + 11044 LUT2 8 AB + 11045 LUT4 0777 /AB\(d+c) + 11046 LUT4 8000 ABCD + 11047 LUT4 0777 /AB\(d+c) + 11048 LUT4 0777 /AB\(d+c) + 11049 LUT4 0777 /AB\(d+c) + 11050 LUT4 0777 /AB\(d+c) + 11051 LUT4 0777 /AB\(d+c) + 11052 LUT4 0777 /AB\(d+c) + 11053 LUT4 7D00 AD?0:0:1:B^C + 11054 LUT4 9000 CD(a^B) + 11055 LUT4 D000 CD/Ab\ + 11056 LUT4 B00B /aB\/D^C\ + 11057 LUT4 8000 ABCD + 11058 LUT4 0700 cD/AB\ + 11059 LUT2 8 AB + 11060 LUT4 0777 /AB\(d+c) + 11061 LUT4 8000 ABCD + 11062 LUT4 0777 /AB\(d+c) + 11063 LUT4 0777 /AB\(d+c) + 11064 LUT4 0777 /AB\(d+c) + 11065 LUT4 0777 /AB\(d+c) + 11066 LUT4 0777 /AB\(d+c) + 11067 LUT4 0777 /AB\(d+c) + 11068 LUT3 60 C(A^B) + 11069 LUT4 8000 ABCD + 11070 LUT4 0700 cD/AB\ + 11071 LUT4 0777 /AB\(d+c) + 11072 LUT2 8 AB + 11073 LUT4 8000 ABCD + 11074 LUT4 0777 /AB\(d+c) + 11075 LUT4 0777 /AB\(d+c) + 11076 LUT4 0777 /AB\(d+c) + 11077 LUT4 0777 /AB\(d+c) + 11078 LUT4 0777 /AB\(d+c) + 11079 LUT4 0777 /AB\(d+c) + 11080 LUT4 8000 ABCD + 11081 LUT4 0700 cD/AB\ + 11082 LUT2 8 AB + 11083 LUT4 0777 /AB\(d+c) + 11084 LUT4 8000 ABCD + 11085 LUT4 0777 /AB\(d+c) + 11086 LUT4 0777 /AB\(d+c) + 11087 LUT4 0777 /AB\(d+c) + 11088 LUT4 0777 /AB\(d+c) + 11089 LUT4 0777 /AB\(d+c) + 11090 LUT4 0777 /AB\(d+c) + 11091 LUT4 8000 ABCD + 11092 LUT4 0700 cD/AB\ + 11093 LUT2 8 AB + 11094 LUT4 0777 /AB\(d+c) + 11095 LUT4 8000 ABCD + 11096 LUT4 0777 /AB\(d+c) + 11097 LUT4 0777 /AB\(d+c) + 11098 LUT4 0777 /AB\(d+c) + 11099 LUT4 0777 /AB\(d+c) + 11100 LUT4 0777 /AB\(d+c) + 11101 LUT4 0777 /AB\(d+c) + 11102 LUT3 41 (B^c)a + 11103 LUT4 8000 ABCD + 11104 LUT4 8000 ABCD + 11105 LUT4 0777 /AB\(d+c) + 11106 LUT4 0777 /AB\(d+c) + 11107 LUT4 0777 /AB\(d+c) + 11108 LUT4 0777 /AB\(d+c) + 11109 LUT4 0700 cD/AB\ + 11110 LUT2 8 AB + 11111 LUT4 0777 /AB\(d+c) + 11112 LUT4 0777 /AB\(d+c) + 11113 LUT4 0777 /AB\(d+c) + 11114 LUT2 9 a^B + 11115 LUT4 9009 (a^B)(D^c) + 11116 LUT4 8000 ABCD + 11117 LUT4 8000 ABCD + 11118 LUT4 0777 /AB\(d+c) + 11119 LUT4 0777 /AB\(d+c) + 11120 LUT4 0777 /AB\(d+c) + 11121 LUT4 0777 /AB\(d+c) + 11122 LUT4 0700 cD/AB\ + 11123 LUT2 8 AB + 11124 LUT4 0777 /AB\(d+c) + 11125 LUT4 0777 /AB\(d+c) + 11126 LUT4 0777 /AB\(d+c) + 11127 LUT4 8000 ABCD + 11128 LUT4 0700 cD/AB\ + 11129 LUT2 8 AB + 11130 LUT4 0777 /AB\(d+c) + 11131 LUT4 8000 ABCD + 11132 LUT4 0777 /AB\(d+c) + 11133 LUT4 0777 /AB\(d+c) + 11134 LUT4 0777 /AB\(d+c) + 11135 LUT4 0777 /AB\(d+c) + 11136 LUT4 0777 /AB\(d+c) + 11137 LUT4 0777 /AB\(d+c) + 11138 LUT2 9 a^B + 11139 LUT2 9 a^B + 11140 LUT4 7000 CD/AB\ + 11141 LUT4 7000 CD/AB\ + 11142 LUT4 7000 CD/AB\ + 11143 LUT3 70 C/AB\ + 11144 LUT4 0777 /AB\(d+c) + 11145 LUT4 0777 /AB\(d+c) + 11146 LUT4 0007 cd/AB\ + 11147 LUT2 8 AB + 11148 LUT2 8 AB + 11149 LUT4 7000 CD/AB\ + 11150 LUT4 0777 /AB\(d+c) + 11151 LUT4 0777 /AB\(d+c) + 11152 LUT2 8 AB + 11153 LUT4 8000 ABCD + 11154 LUT4 0777 /AB\(d+c) + 11155 LUT4 0777 /AB\(d+c) + 11156 LUT4 0777 /AB\(d+c) + 11157 LUT4 0777 /AB\(d+c) + 11158 LUT4 8000 ABCD + 11159 LUT4 0777 /AB\(d+c) + 11160 LUT4 0777 /AB\(d+c) + 11161 LUT4 0777 /AB\(d+c) + 11162 LUT4 0777 /AB\(d+c) + 11163 LUT4 8000 ABCD + 11164 LUT4 0700 cD/AB\ + 11165 LUT2 8 AB + 11166 LUT4 0777 /AB\(d+c) + 11167 LUT4 8000 ABCD + 11168 LUT4 0777 /AB\(d+c) + 11169 LUT4 0777 /AB\(d+c) + 11170 LUT4 0777 /AB\(d+c) + 11171 LUT4 0777 /AB\(d+c) + 11172 LUT4 0777 /AB\(d+c) + 11173 LUT4 0777 /AB\(d+c) + 11174 LUT2 8 AB + 11175 LUT4 7000 CD/AB\ + 11176 LUT4 7000 CD/AB\ + 11177 LUT4 7000 CD/AB\ + 11178 LUT3 70 C/AB\ + 11179 LUT4 0777 /AB\(d+c) + 11180 LUT4 0777 /AB\(d+c) + 11181 LUT4 0007 cd/AB\ + 11182 LUT2 8 AB + 11183 LUT2 8 AB + 11184 LUT4 7000 CD/AB\ + 11185 LUT4 0777 /AB\(d+c) + 11186 LUT4 0777 /AB\(d+c) + 11187 LUT3 80 ABC + 11188 LUT4 0700 cD/AB\ + 11189 LUT3 70 C/AB\ + 11190 LUT4 0777 /AB\(d+c) + 11191 LUT2 8 AB + 11192 LUT4 7000 CD/AB\ + 11193 LUT3 70 C/AB\ + 11194 LUT4 0777 /AB\(d+c) + 11195 LUT4 0777 /AB\(d+c) + 11196 LUT4 7000 CD/AB\ + 11197 LUT4 0777 /AB\(d+c) + 11198 LUT4 0777 /AB\(d+c) + 11199 LUT3 41 (B^c)a + 11200 LUT4 8000 ABCD + 11201 LUT4 0700 cD/AB\ + 11202 LUT4 0777 /AB\(d+c) + 11203 LUT2 8 AB + 11204 LUT4 8000 ABCD + 11205 LUT4 0777 /AB\(d+c) + 11206 LUT4 0777 /AB\(d+c) + 11207 LUT4 0777 /AB\(d+c) + 11208 LUT4 0777 /AB\(d+c) + 11209 LUT4 0777 /AB\(d+c) + 11210 LUT4 0777 /AB\(d+c) + 11211 LUT2 8 AB + 11212 LUT4 8000 ABCD + 11213 LUT4 0777 /AB\(d+c) + 11214 LUT4 0777 /AB\(d+c) + 11215 LUT4 0777 /AB\(d+c) + 11216 LUT4 0777 /AB\(d+c) + 11217 LUT4 8000 ABCD + 11218 LUT4 0777 /AB\(d+c) + 11219 LUT4 0777 /AB\(d+c) + 11220 LUT4 0777 /AB\(d+c) + 11221 LUT4 0777 /AB\(d+c) + 11222 LUT3 41 (B^c)a + 11223 LUT3 80 ABC + 11224 LUT4 8000 ABCD + 11225 LUT4 0777 /AB\(d+c) + 11226 LUT4 0777 /AB\(d+c) + 11227 LUT4 0777 /AB\(d+c) + 11228 LUT4 0777 /AB\(d+c) + 11229 LUT4 0700 cD/AB\ + 11230 LUT2 8 AB + 11231 LUT4 0777 /AB\(d+c) + 11232 LUT4 0700 cD/AB\ + 11233 LUT4 0777 /AB\(d+c) + 11234 LUT2 8 AB + 11235 LUT4 0100 abcD + 11236 LUT4 7887 (AB)^C^d + 11237 LUT4 7000 CD/AB\ + 11238 LUT4 7000 CD/AB\ + 11239 LUT4 7000 CD/AB\ + 11240 LUT4 0700 cD/AB\ + 11241 LUT2 8 AB + 11242 LUT4 0777 /AB\(d+c) + 11243 LUT4 0777 /AB\(d+c) + 11244 LUT3 70 C/AB\ + 11245 LUT4 0777 /AB\(d+c) + 11246 LUT4 0777 /AB\(d+c) + 11247 LUT4 0777 /AB\(d+c) + 11248 LUT4 7F80 AD?0:BC:1:/BC\ + 11249 LUT2 8 AB + 11250 LUT4 8000 ABCD + 11251 LUT4 0777 /AB\(d+c) + 11252 LUT4 0777 /AB\(d+c) + 11253 LUT4 0777 /AB\(d+c) + 11254 LUT4 0777 /AB\(d+c) + 11255 LUT4 8000 ABCD + 11256 LUT4 0777 /AB\(d+c) + 11257 LUT4 0777 /AB\(d+c) + 11258 LUT4 0777 /AB\(d+c) + 11259 LUT4 0777 /AB\(d+c) + 11260 LUT4 8000 ABCD + 11261 LUT4 0777 /AB\(d+c) + 11262 LUT4 0777 /AB\(d+c) + 11263 LUT4 0777 /AB\(d+c) + 11264 LUT4 0777 /AB\(d+c) + 11265 LUT4 0700 cD/AB\ + 11266 LUT4 0777 /AB\(d+c) + 11267 LUT2 8 AB + 11268 LUT4 0700 cD/AB\ + 11269 LUT4 0777 /AB\(d+c) + 11270 LUT2 8 AB + 11271 LUT3 60 C(A^B) + 11272 LUT2 4 aB + 11273 LUT4 8000 ABCD + 11274 LUT4 0700 cD/AB\ + 11275 LUT2 8 AB + 11276 LUT4 0777 /AB\(d+c) + 11277 LUT4 8000 ABCD + 11278 LUT4 0777 /AB\(d+c) + 11279 LUT4 0777 /AB\(d+c) + 11280 LUT4 0777 /AB\(d+c) + 11281 LUT4 0777 /AB\(d+c) + 11282 LUT4 0777 /AB\(d+c) + 11283 LUT4 0777 /AB\(d+c) + 11284 LUT4 1000 abCD + 11285 LUT4 4114 AB?C^D:0:c^D:0 + 11286 LUT3 41 (B^c)a + 11287 LUT4 8000 ABCD + 11288 LUT3 80 ABC + 11289 LUT4 0700 cD/AB\ + 11290 LUT4 0777 /AB\(d+c) + 11291 LUT2 8 AB + 11292 LUT4 0777 /AB\(d+c) + 11293 LUT4 0777 /AB\(d+c) + 11294 LUT4 0700 cD/AB\ + 11295 LUT4 0777 /AB\(d+c) + 11296 LUT2 8 AB + 11297 LUT4 0777 /AB\(d+c) + 11298 LUT4 0777 /AB\(d+c) + 11299 LUT4 8000 ABCD + 11300 LUT4 8000 ABCD + 11301 LUT4 0777 /AB\(d+c) + 11302 LUT4 0777 /AB\(d+c) + 11303 LUT4 0777 /AB\(d+c) + 11304 LUT4 0777 /AB\(d+c) + 11305 LUT4 0700 cD/AB\ + 11306 LUT2 8 AB + 11307 LUT4 0777 /AB\(d+c) + 11308 LUT4 0777 /AB\(d+c) + 11309 LUT4 0777 /AB\(d+c) + 11310 LUT3 0B c/aB\ + 11311 LUT3 60 C(A^B) + 11312 LUT2 8 AB + 11313 LUT4 8000 ABCD + 11314 LUT4 0777 /AB\(d+c) + 11315 LUT4 0777 /AB\(d+c) + 11316 LUT4 0777 /AB\(d+c) + 11317 LUT4 0777 /AB\(d+c) + 11318 LUT4 8000 ABCD + 11319 LUT4 0777 /AB\(d+c) + 11320 LUT4 0777 /AB\(d+c) + 11321 LUT4 0777 /AB\(d+c) + 11322 LUT4 0777 /AB\(d+c) + 11323 LUT2 4 aB + 11324 LUT3 60 C(A^B) + 11325 LUT4 8000 ABCD + 11326 LUT4 0700 cD/AB\ + 11327 LUT2 8 AB + 11328 LUT4 0777 /AB\(d+c) + 11329 LUT4 8000 ABCD + 11330 LUT4 0777 /AB\(d+c) + 11331 LUT4 0777 /AB\(d+c) + 11332 LUT4 0777 /AB\(d+c) + 11333 LUT4 0777 /AB\(d+c) + 11334 LUT4 0777 /AB\(d+c) + 11335 LUT4 0777 /AB\(d+c) + 11336 LUT4 050C DC?B:a:0:0 + 11337 LUT2 1 ab + 11338 LUT4 8000 ABCD + 11339 LUT4 0700 cD/AB\ + 11340 LUT2 8 AB + 11341 LUT4 0777 /AB\(d+c) + 11342 LUT4 8000 ABCD + 11343 LUT4 0777 /AB\(d+c) + 11344 LUT4 0777 /AB\(d+c) + 11345 LUT4 0777 /AB\(d+c) + 11346 LUT4 0777 /AB\(d+c) + 11347 LUT4 0777 /AB\(d+c) + 11348 LUT4 0777 /AB\(d+c) + 11349 LUT4 7F00 ((/AB\)+c)D + 11350 LUT4 7000 CD/AB\ + 11351 LUT4 7000 CD/AB\ + 11352 LUT4 0777 /AB\(d+c) + 11353 LUT4 0777 /AB\(d+c) + 11354 LUT4 0777 /AB\(d+c) + 11355 LUT4 7000 CD/AB\ + 11356 LUT4 0777 /AB\(d+c) + 11357 LUT4 0777 /AB\(d+c) + 11358 LUT4 0007 cd/AB\ + 11359 LUT2 8 AB + 11360 LUT2 8 AB + 11361 LUT4 007F ((/AB\)+c)d + 11362 LUT3 80 ABC + 11363 LUT2 8 AB + 11364 LUT4 0990 (a^B)(d^c) + 11365 LUT4 4182 (b^C)(A^D) + 11366 LUT2 8 AB + 11367 LUT4 1428 (B^C)(A^D) + 11368 LUT4 4182 (b^C)(A^D) + 11369 LUT2 8 AB + 11370 LUT4 0990 (a^B)(d^c) + 11371 LUT2 8 AB + 11372 LUT4 9009 (a^B)(D^c) + 11373 LUT2 8 AB + 11374 LUT3 80 ABC + 11375 LUT2 8 AB + 11376 LUT2 8 AB + 11377 LUT4 9009 (a^B)(D^c) + 11378 LUT2 8 AB + 11379 LUT4 007F ((/AB\)+c)d + 11380 LUT3 80 ABC + 11381 LUT2 8 AB + 11382 LUT2 8 AB + 11383 LUT4 1428 (B^C)(A^D) + 11384 LUT2 8 AB + 11385 LUT2 8 AB + 11386 LUT2 8 AB + 11387 LUT2 8 AB + 11388 LUT2 8 AB + 11389 LUT2 8 AB + 11390 LUT4 007F ((/AB\)+c)d + 11391 LUT3 80 ABC + 11392 LUT4 BF00 ((/aB\)+c)D + 11393 LUT4 770F D?c:/AB\ + 11394 LUT3 80 ABC + 11395 LUT4 1001 ab(c^D) + 11396 LUT4 0100 abcD + 11397 LUT3 40 aBC + 11398 LUT4 4200 D(AB?0:c:C:0) + 11399 LUT2 8 AB + 11400 LUT2 8 AB + 11401 LUT4 FE00 ((/ab\)+C)D + 11402 LUT2 4 aB + 11403 LUT3 01 abc + 11404 LUT4 8000 ABCD + 11405 LUT2 4 aB + 11406 LUT3 40 aBC + 11407 LUT4 9009 (a^B)(D^c) + 11408 LUT4 9000 CD(a^B) + 11409 LUT4 B00B /aB\/D^C\ + 11410 LUT4 9009 (a^B)(D^c) + 11411 LUT3 90 C(a^B) + 11412 LUT4 9009 (a^B)(D^c) + 11413 LUT3 90 C(a^B) + 11414 LUT4 B00B /aB\/D^C\ + 11415 LUT3 90 C(a^B) + 11416 LUT4 9009 (a^B)(D^c) + 11417 LUT3 90 C(a^B) + 11418 LUT3 B0 C/aB\ + 11419 LUT4 B00B /aB\/D^C\ + 11420 LUT2 8 AB + 11421 LUT3 E0 C/ab\ + 11422 LUT2 1 ab + 11423 LUT3 10 abC + 11424 LUT4 007F ((/AB\)+c)d + 11425 LUT2 1 ab + 11426 LUT3 01 abc + 11427 LUT3 E0 C/ab\ + 11428 LUT2 8 AB + 11429 LUT3 4F (aB)+c + 11430 LUT4 007D AD?1:B^C:0:0 + 11431 LUT3 07 c/AB\ + 11432 LUT3 40 aBC + 11433 LUT3 70 C/AB\ + 11434 LUT4 0777 /AB\(d+c) + 11435 LUT4 F888 (AB)+(CD) + 11436 LUT2 4 aB + 11437 LUT2 8 AB + 11438 LUT2 4 aB + 11439 LUT3 E0 C/ab\ + 11440 LUT3 E0 C/ab\ + 11441 LUT2 8 AB + 11442 LUT3 AC c?A:B + 11443 LUT3 8F (AB)+c + 11444 LUT3 70 C/AB\ + 11445 LUT3 70 C/AB\ + 11446 LUT4 0777 /AB\(d+c) + 11447 LUT4 F888 (AB)+(CD) + 11448 LUT3 AC c?A:B + 11449 LUT3 8F (AB)+c + 11450 LUT3 70 C/AB\ + 11451 LUT3 70 C/AB\ + 11452 LUT4 0777 /AB\(d+c) + 11453 LUT4 F888 (AB)+(CD) + 11454 LUT3 AC c?A:B + 11455 LUT3 8F (AB)+c + 11456 LUT3 70 C/AB\ + 11457 LUT3 70 C/AB\ + 11458 LUT4 0777 /AB\(d+c) + 11459 LUT4 F888 (AB)+(CD) + 11460 LUT3 AC c?A:B + 11461 LUT3 8F (AB)+c + 11462 LUT3 70 C/AB\ + 11463 LUT3 70 C/AB\ + 11464 LUT4 0777 /AB\(d+c) + 11465 LUT4 F888 (AB)+(CD) + 11466 LUT3 AC c?A:B + 11467 LUT3 8F (AB)+c + 11468 LUT3 70 C/AB\ + 11469 LUT3 70 C/AB\ + 11470 LUT4 0777 /AB\(d+c) + 11471 LUT4 F888 (AB)+(CD) + 11472 LUT3 AC c?A:B + 11473 LUT3 8F (AB)+c + 11474 LUT3 70 C/AB\ + 11475 LUT3 70 C/AB\ + 11476 LUT4 0777 /AB\(d+c) + 11477 LUT4 F888 (AB)+(CD) + 11478 LUT3 AC c?A:B + 11479 LUT3 8F (AB)+c + 11480 LUT3 70 C/AB\ + 11481 LUT3 70 C/AB\ + 11482 LUT4 0777 /AB\(d+c) + 11483 LUT4 F888 (AB)+(CD) + 11484 LUT3 AC c?A:B + 11485 LUT3 8F (AB)+c + 11486 LUT3 70 C/AB\ + 11487 LUT3 70 C/AB\ + 11488 LUT4 0777 /AB\(d+c) + 11489 LUT4 F888 (AB)+(CD) + 11490 LUT3 AC c?A:B + 11491 LUT3 8F (AB)+c + 11492 LUT3 70 C/AB\ + 11493 LUT3 70 C/AB\ + 11494 LUT4 0777 /AB\(d+c) + 11495 LUT4 F888 (AB)+(CD) + 11496 LUT3 AC c?A:B + 11497 LUT3 8F (AB)+c + 11498 LUT3 70 C/AB\ + 11499 LUT3 70 C/AB\ + 11500 LUT4 0777 /AB\(d+c) + 11501 LUT4 F888 (AB)+(CD) + 11502 LUT3 AC c?A:B + 11503 LUT3 8F (AB)+c + 11504 LUT3 70 C/AB\ + 11505 LUT3 70 C/AB\ + 11506 LUT4 0777 /AB\(d+c) + 11507 LUT4 F888 (AB)+(CD) + 11508 LUT3 AC c?A:B + 11509 LUT3 8F (AB)+c + 11510 LUT3 70 C/AB\ + 11511 LUT3 70 C/AB\ + 11512 LUT4 0777 /AB\(d+c) + 11513 LUT3 F8 (AB)+C + 11514 LUT4 8F00 ((AB)+c)D + 11515 LUT2 1 ab + 11516 LUT2 4 aB + 11517 LUT4 FFF4 (aB)+C+D + 11518 LUT2 1 ab + 11519 LUT2 4 aB + 11520 LUT4 F400 ((aB)+C)D + 11521 LUT4 F400 ((aB)+C)D + 11522 LUT3 07 c/AB\ + 11523 LUT4 8000 ABCD + 11524 LUT4 0777 /AB\(d+c) + 11525 LUT4 0777 /AB\(d+c) + 11526 LUT4 0777 /AB\(d+c) + 11527 LUT4 0777 /AB\(d+c) + 11528 LUT4 8000 ABCD + 11529 LUT4 0777 /AB\(d+c) + 11530 LUT4 0777 /AB\(d+c) + 11531 LUT4 0777 /AB\(d+c) + 11532 LUT4 0777 /AB\(d+c) + 11533 LUT4 8000 ABCD + 11534 LUT4 0700 cD/AB\ + 11535 LUT2 8 AB + 11536 LUT4 0777 /AB\(d+c) + 11537 LUT4 8000 ABCD + 11538 LUT4 0777 /AB\(d+c) + 11539 LUT4 0777 /AB\(d+c) + 11540 LUT4 0777 /AB\(d+c) + 11541 LUT4 0777 /AB\(d+c) + 11542 LUT4 0777 /AB\(d+c) + 11543 LUT4 0777 /AB\(d+c) + 11544 LUT4 F400 ((aB)+C)D + 11545 LUT2 4 aB + 11546 LUT4 8000 ABCD + 11547 LUT4 8000 ABCD + 11548 LUT4 0777 /AB\(d+c) + 11549 LUT4 0777 /AB\(d+c) + 11550 LUT4 0777 /AB\(d+c) + 11551 LUT4 0777 /AB\(d+c) + 11552 LUT4 0700 cD/AB\ + 11553 LUT2 8 AB + 11554 LUT4 0777 /AB\(d+c) + 11555 LUT4 0777 /AB\(d+c) + 11556 LUT4 0777 /AB\(d+c) + 11557 LUT4 8000 ABCD + 11558 LUT4 0700 cD/AB\ + 11559 LUT2 8 AB + 11560 LUT4 0777 /AB\(d+c) + 11561 LUT4 8000 ABCD + 11562 LUT4 0777 /AB\(d+c) + 11563 LUT4 0777 /AB\(d+c) + 11564 LUT4 0777 /AB\(d+c) + 11565 LUT4 0777 /AB\(d+c) + 11566 LUT4 0777 /AB\(d+c) + 11567 LUT4 0777 /AB\(d+c) + 11568 LUT4 B0BB /aB\(d+C) + 11569 LUT2 4 aB + 11570 LUT4 0777 /AB\(d+c) + 11571 LUT3 8F (AB)+c + 11572 LUT2 1 ab + 11573 LUT2 4 aB + 11574 LUT4 EE0F D?c:/ab\ + 11575 LUT4 00BF ((/aB\)+c)d + 11576 LUT3 40 aBC + 11577 LUT3 10 abC + 11578 LUT2 4 aB + 11579 LUT2 4 aB + 11580 LUT3 35 c?b:a + 11581 LUT3 4F (aB)+c + 11582 LUT4 F0BB D?/aB\:C + 11583 LUT4 0777 /AB\(d+c) + 11584 LUT3 AC c?A:B + 11585 LUT3 8F (AB)+c + 11586 LUT3 70 C/AB\ + 11587 LUT3 70 C/AB\ + 11588 LUT4 0777 /AB\(d+c) + 11589 LUT4 8F88 (AB)+(cD) + 11590 LUT3 70 C/AB\ + 11591 LUT4 0777 /AB\(d+c) + 11592 LUT3 8F (AB)+c + 11593 LUT4 0777 /AB\(d+c) + 11594 LUT3 AC c?A:B + 11595 LUT3 8F (AB)+c + 11596 LUT3 70 C/AB\ + 11597 LUT3 70 C/AB\ + 11598 LUT4 0777 /AB\(d+c) + 11599 LUT4 8F88 (AB)+(cD) + 11600 LUT3 70 C/AB\ + 11601 LUT4 0777 /AB\(d+c) + 11602 LUT3 8F (AB)+c + 11603 LUT4 0777 /AB\(d+c) + 11604 LUT3 AC c?A:B + 11605 LUT3 8F (AB)+c + 11606 LUT4 0700 cD/AB\ + 11607 LUT2 8 AB + 11608 LUT3 F8 (AB)+C + 11609 LUT4 8F00 ((AB)+c)D + 11610 LUT4 0777 /AB\(d+c) + 11611 LUT3 8F (AB)+c + 11612 LUT4 0777 /AB\(d+c) + 11613 LUT4 0777 /AB\(d+c) + 11614 LUT3 AC c?A:B + 11615 LUT3 8F (AB)+c + 11616 LUT4 0700 cD/AB\ + 11617 LUT2 8 AB + 11618 LUT3 F8 (AB)+C + 11619 LUT4 8F00 ((AB)+c)D + 11620 LUT4 0777 /AB\(d+c) + 11621 LUT3 8F (AB)+c + 11622 LUT4 0777 /AB\(d+c) + 11623 LUT4 0777 /AB\(d+c) + 11624 LUT3 AC c?A:B + 11625 LUT3 8F (AB)+c + 11626 LUT3 70 C/AB\ + 11627 LUT3 70 C/AB\ + 11628 LUT4 0777 /AB\(d+c) + 11629 LUT3 F8 (AB)+C + 11630 LUT4 8F00 ((AB)+c)D + 11631 LUT4 0777 /AB\(d+c) + 11632 LUT3 8F (AB)+c + 11633 LUT4 0777 /AB\(d+c) + 11634 LUT3 AC c?A:B + 11635 LUT3 8F (AB)+c + 11636 LUT3 70 C/AB\ + 11637 LUT3 70 C/AB\ + 11638 LUT4 0777 /AB\(d+c) + 11639 LUT3 F8 (AB)+C + 11640 LUT4 8F00 ((AB)+c)D + 11641 LUT4 0777 /AB\(d+c) + 11642 LUT3 8F (AB)+c + 11643 LUT4 0777 /AB\(d+c) + 11644 LUT3 AC c?A:B + 11645 LUT3 8F (AB)+c + 11646 LUT4 0700 cD/AB\ + 11647 LUT2 8 AB + 11648 LUT3 F8 (AB)+C + 11649 LUT4 8F00 ((AB)+c)D + 11650 LUT4 0777 /AB\(d+c) + 11651 LUT3 8F (AB)+c + 11652 LUT4 0777 /AB\(d+c) + 11653 LUT4 0777 /AB\(d+c) + 11654 LUT3 AC c?A:B + 11655 LUT3 8F (AB)+c + 11656 LUT3 70 C/AB\ + 11657 LUT3 70 C/AB\ + 11658 LUT4 0777 /AB\(d+c) + 11659 LUT3 F8 (AB)+C + 11660 LUT4 8F00 ((AB)+c)D + 11661 LUT4 0777 /AB\(d+c) + 11662 LUT3 8F (AB)+c + 11663 LUT4 0777 /AB\(d+c) + 11664 LUT3 AC c?A:B + 11665 LUT3 8F (AB)+c + 11666 LUT3 70 C/AB\ + 11667 LUT3 70 C/AB\ + 11668 LUT4 0777 /AB\(d+c) + 11669 LUT3 F8 (AB)+C + 11670 LUT4 8F00 ((AB)+c)D + 11671 LUT4 0777 /AB\(d+c) + 11672 LUT3 8F (AB)+c + 11673 LUT4 0777 /AB\(d+c) + 11674 LUT3 AC c?A:B + 11675 LUT3 8F (AB)+c + 11676 LUT3 70 C/AB\ + 11677 LUT3 70 C/AB\ + 11678 LUT4 0777 /AB\(d+c) + 11679 LUT3 F8 (AB)+C + 11680 LUT4 8F00 ((AB)+c)D + 11681 LUT4 0777 /AB\(d+c) + 11682 LUT3 8F (AB)+c + 11683 LUT4 0777 /AB\(d+c) + 11684 LUT3 AC c?A:B + 11685 LUT3 8F (AB)+c + 11686 LUT3 70 C/AB\ + 11687 LUT3 70 C/AB\ + 11688 LUT4 0777 /AB\(d+c) + 11689 LUT3 F8 (AB)+C + 11690 LUT4 8F00 ((AB)+c)D + 11691 LUT4 0777 /AB\(d+c) + 11692 LUT3 8F (AB)+c + 11693 LUT4 0777 /AB\(d+c) + 11694 LUT3 AC c?A:B + 11695 LUT3 8F (AB)+c + 11696 LUT3 70 C/AB\ + 11697 LUT3 70 C/AB\ + 11698 LUT4 0777 /AB\(d+c) + 11699 LUT3 F8 (AB)+C + 11700 LUT4 8F00 ((AB)+c)D + 11701 LUT4 0777 /AB\(d+c) + 11702 LUT3 8F (AB)+c + 11703 LUT4 0777 /AB\(d+c) + 11704 LUT3 AC c?A:B + 11705 LUT3 8F (AB)+c + 11706 LUT3 70 C/AB\ + 11707 LUT3 70 C/AB\ + 11708 LUT4 0777 /AB\(d+c) + 11709 LUT4 8F88 (AB)+(cD) + 11710 LUT3 70 C/AB\ + 11711 LUT4 0777 /AB\(d+c) + 11712 LUT3 8F (AB)+c + 11713 LUT4 0777 /AB\(d+c) + 11714 LUT3 AC c?A:B + 11715 LUT3 8F (AB)+c + 11716 LUT4 0700 cD/AB\ + 11717 LUT2 8 AB + 11718 LUT3 F8 (AB)+C + 11719 LUT4 8F00 ((AB)+c)D + 11720 LUT4 0777 /AB\(d+c) + 11721 LUT3 8F (AB)+c + 11722 LUT4 0777 /AB\(d+c) + 11723 LUT4 0777 /AB\(d+c) + 11724 LUT3 AC c?A:B + 11725 LUT3 8F (AB)+c + 11726 LUT4 0700 cD/AB\ + 11727 LUT2 8 AB + 11728 LUT3 F8 (AB)+C + 11729 LUT4 8F00 ((AB)+c)D + 11730 LUT4 0777 /AB\(d+c) + 11731 LUT3 8F (AB)+c + 11732 LUT4 0777 /AB\(d+c) + 11733 LUT4 0777 /AB\(d+c) + 11734 LUT3 AC c?A:B + 11735 LUT3 8F (AB)+c + 11736 LUT4 0700 cD/AB\ + 11737 LUT2 8 AB + 11738 LUT3 F8 (AB)+C + 11739 LUT4 8F00 ((AB)+c)D + 11740 LUT4 0777 /AB\(d+c) + 11741 LUT3 8F (AB)+c + 11742 LUT4 0777 /AB\(d+c) + 11743 LUT4 0777 /AB\(d+c) + 11744 LUT3 AC c?A:B + 11745 LUT3 8F (AB)+c + 11746 LUT3 70 C/AB\ + 11747 LUT3 70 C/AB\ + 11748 LUT4 0777 /AB\(d+c) + 11749 LUT3 F8 (AB)+C + 11750 LUT4 8F00 ((AB)+c)D + 11751 LUT4 0777 /AB\(d+c) + 11752 LUT3 8F (AB)+c + 11753 LUT4 0777 /AB\(d+c) + 11754 LUT3 AC c?A:B + 11755 LUT3 8F (AB)+c + 11756 LUT3 70 C/AB\ + 11757 LUT3 70 C/AB\ + 11758 LUT4 0777 /AB\(d+c) + 11759 LUT3 F8 (AB)+C + 11760 LUT4 8F00 ((AB)+c)D + 11761 LUT4 0777 /AB\(d+c) + 11762 LUT3 8F (AB)+c + 11763 LUT4 0777 /AB\(d+c) + 11764 LUT3 AC c?A:B + 11765 LUT4 F2FF (Ab)+C+d + 11766 LUT4 D000 CD/Ab\ + 11767 LUT3 0B c/aB\ + 11768 LUT4 BF00 ((/aB\)+c)D + 11769 LUT4 4F00 ((aB)+c)D + 11770 LUT4 7077 /AB\(d+C) + 11771 LUT2 4 aB + 11772 LUT4 0B00 cD/aB\ + 11773 LUT2 1 ab + 11774 LUT2 4 aB + 11775 LUT2 4 aB + 11776 LUT2 8 AB + 11777 LUT2 4 aB + 11778 LUT3 40 aBC + 11779 LUT2 E /ab\ + 11780 LUT4 0C0A DC?A:B:0:0 + 11781 LUT3 CA C?A:B + 11782 LUT2 8 AB + 11783 LUT4 6000 CD(A^B) + 11784 LUT3 60 C(A^B) + 11785 LUT3 60 C(A^B) + 11786 LUT3 60 C(A^B) + 11787 LUT3 60 C(A^B) + 11788 LUT4 7000 CD/AB\ + 11789 LUT2 8 AB + 11790 LUT2 8 AB + 11791 LUT3 CA C?A:B + 11792 LUT2 8 AB + 11793 LUT2 8 AB + 11794 LUT3 CA C?A:B + 11795 LUT2 8 AB + 11796 LUT4 6000 CD(A^B) + 11797 LUT3 60 C(A^B) + 11798 LUT3 60 C(A^B) + 11799 LUT3 90 C(a^B) + 11800 LUT3 CA C?A:B + 11801 LUT2 1 ab + 11802 LUT2 4 aB + 11803 LUT2 4 aB + 11804 LUT2 8 AB + 11805 LUT3 CA C?A:B + 11806 LUT2 8 AB + 11807 LUT4 6000 CD(A^B) + 11808 LUT3 60 C(A^B) + 11809 LUT3 90 C(a^B) + 11810 LUT3 CA C?A:B + 11811 LUT3 CA C?A:B + 11812 LUT2 8 AB + 11813 LUT4 6000 CD(A^B) + 11814 LUT3 60 C(A^B) + 11815 LUT3 90 C(a^B) + 11816 LUT3 CA C?A:B + 11817 LUT3 CA C?A:B + 11818 LUT2 8 AB + 11819 LUT4 6000 CD(A^B) + 11820 LUT3 90 C(a^B) + 11821 LUT3 CA C?A:B + 11822 LUT3 CA C?A:B + 11823 LUT2 8 AB + 11824 LUT4 6000 CD(A^B) + 11825 LUT3 90 C(a^B) + 11826 LUT3 CA C?A:B + 11827 LUT2 4 aB + 11828 LUT3 CA C?A:B + 11829 LUT2 8 AB + 11830 LUT4 6000 CD(A^B) + 11831 LUT3 90 C(a^B) + 11832 LUT3 CA C?A:B + 11833 LUT3 CA C?A:B + 11834 LUT2 8 AB + 11835 LUT4 6000 CD(A^B) + 11836 LUT3 90 C(a^B) + 11837 LUT3 CA C?A:B + 11838 LUT3 CA C?A:B + 11839 LUT2 8 AB + 11840 LUT4 9000 CD(a^B) + 11841 LUT3 CA C?A:B + 11842 LUT3 CA C?A:B + 11843 LUT2 8 AB + 11844 LUT4 9000 CD(a^B) + 11845 LUT3 CA C?A:B + 11846 LUT3 CA C?A:B + 11847 LUT2 8 AB + 11848 LUT4 9000 CD(a^B) + 11849 LUT3 CA C?A:B + 11850 LUT3 CA C?A:B + 11851 LUT2 8 AB + 11852 LUT4 9000 CD(a^B) + 11853 LUT3 CA C?A:B + 11854 LUT3 CA C?A:B + 11855 LUT2 8 AB + 11856 LUT4 9000 CD(a^B) + 11857 LUT3 CA C?A:B + 11858 LUT3 CA C?A:B + 11859 LUT2 8 AB + 11860 LUT4 9000 CD(a^B) + 11861 LUT3 CA C?A:B + 11862 LUT3 CA C?A:B + 11863 LUT2 8 AB + 11864 LUT4 9000 CD(a^B) + 11865 LUT3 CA C?A:B + 11866 LUT3 CA C?A:B + 11867 LUT2 8 AB + 11868 LUT4 9000 CD(a^B) + 11869 LUT3 CA C?A:B + 11870 LUT3 CA C?A:B + 11871 LUT2 8 AB + 11872 LUT4 1400 D(B^C)a + 11873 LUT3 CA C?A:B + 11874 LUT3 CA C?A:B + 11875 LUT2 8 AB + 11876 LUT4 1400 D(B^C)a + 11877 LUT3 CA C?A:B + 11878 LUT3 CA C?A:B + 11879 LUT2 8 AB + 11880 LUT4 1400 D(B^C)a + 11881 LUT3 CA C?A:B + 11882 LUT3 CA C?A:B + 11883 LUT2 8 AB + 11884 LUT4 1400 D(B^C)a + 11885 LUT3 CA C?A:B + 11886 LUT3 CA C?A:B + 11887 LUT2 8 AB + 11888 LUT4 1400 D(B^C)a + 11889 LUT3 CA C?A:B + 11890 LUT3 CA C?A:B + 11891 LUT2 8 AB + 11892 LUT4 1400 D(B^C)a + 11893 LUT3 CA C?A:B + 11894 LUT3 CA C?A:B + 11895 LUT2 8 AB + 11896 LUT4 1400 D(B^C)a + 11897 LUT3 CA C?A:B + 11898 LUT3 CA C?A:B + 11899 LUT2 8 AB + 11900 LUT4 1400 D(B^C)a + 11901 LUT3 CA C?A:B + 11902 LUT3 CA C?A:B + 11903 LUT2 8 AB + 11904 LUT4 4100 D(B^c)a + 11905 LUT3 CA C?A:B + 11906 LUT3 CA C?A:B + 11907 LUT2 8 AB + 11908 LUT4 4100 D(B^c)a + 11909 LUT3 CA C?A:B + 11910 LUT3 CA C?A:B + 11911 LUT2 8 AB + 11912 LUT4 4100 D(B^c)a + 11913 LUT3 CA C?A:B + 11914 LUT3 CA C?A:B + 11915 LUT2 8 AB + 11916 LUT4 4100 D(B^c)a + 11917 LUT3 CA C?A:B + 11918 LUT3 CA C?A:B + 11919 LUT2 8 AB + 11920 LUT4 4100 D(B^c)a + 11921 LUT3 CA C?A:B + 11922 LUT3 CA C?A:B + 11923 LUT2 8 AB + 11924 LUT4 4100 D(B^c)a + 11925 LUT3 CA C?A:B + 11926 LUT3 CA C?A:B + 11927 LUT2 8 AB + 11928 LUT4 4100 D(B^c)a + 11929 LUT3 CA C?A:B + 11930 LUT3 CA C?A:B + 11931 LUT2 8 AB + 11932 LUT4 4100 D(B^c)a + 11933 LUT3 CA C?A:B + 11934 LUT3 CA C?A:B + 11935 LUT2 4 aB + 11936 LUT3 CA C?A:B + 11937 LUT3 CA C?A:B + 11938 LUT2 4 aB + 11939 LUT3 CA C?A:B + 11940 LUT3 CA C?A:B + 11941 LUT2 4 aB + 11942 LUT3 CA C?A:B + 11943 LUT3 CA C?A:B + 11944 LUT2 4 aB + 11945 LUT3 CA C?A:B + 11946 LUT3 CA C?A:B + 11947 LUT2 4 aB + 11948 LUT3 CA C?A:B + 11949 LUT3 CA C?A:B + 11950 LUT2 4 aB + 11951 LUT3 CA C?A:B + 11952 LUT3 CA C?A:B + 11953 LUT2 4 aB + 11954 LUT3 CA C?A:B + 11955 LUT3 CA C?A:B + 11956 LUT2 4 aB + 11957 LUT3 CA C?A:B + 11958 LUT3 CA C?A:B + 11959 LUT2 4 aB + 11960 LUT3 CA C?A:B + 11961 LUT3 CA C?A:B + 11962 LUT2 4 aB + 11963 LUT3 CA C?A:B + 11964 LUT3 CA C?A:B + 11965 LUT2 4 aB + 11966 LUT3 CA C?A:B + 11967 LUT3 CA C?A:B + 11968 LUT2 4 aB + 11969 LUT3 CA C?A:B + 11970 LUT3 CA C?A:B + 11971 LUT2 4 aB + 11972 LUT3 CA C?A:B + 11973 LUT3 CA C?A:B + 11974 LUT2 4 aB + 11975 LUT3 CA C?A:B + 11976 LUT3 CA C?A:B + 11977 LUT2 4 aB + 11978 LUT3 CA C?A:B + 11979 LUT3 CA C?A:B + 11980 LUT2 4 aB + 11981 LUT3 CA C?A:B + 11982 LUT3 CA C?A:B + 11983 LUT2 4 aB + 11984 LUT3 CA C?A:B + 11985 LUT3 CA C?A:B + 11986 LUT2 4 aB + 11987 LUT3 CA C?A:B + 11988 LUT3 CA C?A:B + 11989 LUT2 4 aB + 11990 LUT3 CA C?A:B + 11991 LUT3 CA C?A:B + 11992 LUT2 4 aB + 11993 LUT3 CA C?A:B + 11994 LUT3 CA C?A:B + 11995 LUT2 4 aB + 11996 LUT3 CA C?A:B + 11997 LUT3 CA C?A:B + 11998 LUT2 4 aB + 11999 LUT3 CA C?A:B + 12000 LUT3 CA C?A:B + 12001 LUT2 4 aB + 12002 LUT3 CA C?A:B + 12003 LUT3 CA C?A:B + 12004 LUT2 4 aB + 12005 LUT3 CA C?A:B + 12006 LUT3 CA C?A:B + 12007 LUT2 4 aB + 12008 LUT3 CA C?A:B + 12009 LUT3 CA C?A:B + 12010 LUT2 4 aB + 12011 LUT3 CA C?A:B + 12012 LUT3 CA C?A:B + 12013 LUT2 4 aB + 12014 LUT3 CA C?A:B + 12015 LUT3 CA C?A:B + 12016 LUT2 4 aB + 12017 LUT3 CA C?A:B + 12018 LUT3 CA C?A:B + 12019 LUT2 4 aB + 12020 LUT3 CA C?A:B + 12021 LUT3 CA C?A:B + 12022 LUT2 4 aB + 12023 LUT3 CA C?A:B + 12024 LUT3 CA C?A:B + 12025 LUT2 4 aB + 12026 LUT3 CA C?A:B + 12027 LUT3 CA C?A:B + 12028 LUT2 4 aB + 12029 LUT3 CA C?A:B + 12030 LUT3 CA C?A:B + 12031 LUT2 8 AB + 12032 LUT4 6000 CD(A^B) + 12033 LUT3 60 C(A^B) + 12034 LUT3 60 C(A^B) + 12035 LUT3 60 C(A^B) + 12036 LUT3 90 C(a^B) + 12037 LUT3 CA C?A:B + 12038 LUT3 CA C?A:B + 12039 LUT2 8 AB + 12040 LUT4 6000 CD(A^B) + 12041 LUT3 60 C(A^B) + 12042 LUT3 60 C(A^B) + 12043 LUT3 90 C(a^B) + 12044 LUT3 CA C?A:B + 12045 LUT3 CA C?A:B + 12046 LUT2 8 AB + 12047 LUT4 6000 CD(A^B) + 12048 LUT3 60 C(A^B) + 12049 LUT3 90 C(a^B) + 12050 LUT3 CA C?A:B + 12051 LUT3 CA C?A:B + 12052 LUT2 8 AB + 12053 LUT4 6000 CD(A^B) + 12054 LUT3 60 C(A^B) + 12055 LUT3 90 C(a^B) + 12056 LUT3 CA C?A:B + 12057 LUT3 CA C?A:B + 12058 LUT2 8 AB + 12059 LUT4 6000 CD(A^B) + 12060 LUT3 90 C(a^B) + 12061 LUT3 CA C?A:B + 12062 LUT3 CA C?A:B + 12063 LUT2 8 AB + 12064 LUT4 6000 CD(A^B) + 12065 LUT3 90 C(a^B) + 12066 LUT3 CA C?A:B + 12067 LUT3 CA C?A:B + 12068 LUT2 8 AB + 12069 LUT4 6000 CD(A^B) + 12070 LUT3 90 C(a^B) + 12071 LUT3 CA C?A:B + 12072 LUT3 CA C?A:B + 12073 LUT2 8 AB + 12074 LUT4 6000 CD(A^B) + 12075 LUT3 90 C(a^B) + 12076 LUT3 CA C?A:B + 12077 LUT3 CA C?A:B + 12078 LUT2 8 AB + 12079 LUT4 9000 CD(a^B) + 12080 LUT3 CA C?A:B + 12081 LUT3 CA C?A:B + 12082 LUT2 8 AB + 12083 LUT4 9000 CD(a^B) + 12084 LUT3 CA C?A:B + 12085 LUT3 CA C?A:B + 12086 LUT2 8 AB + 12087 LUT4 9000 CD(a^B) + 12088 LUT3 CA C?A:B + 12089 LUT3 CA C?A:B + 12090 LUT2 8 AB + 12091 LUT4 9000 CD(a^B) + 12092 LUT3 CA C?A:B + 12093 LUT3 CA C?A:B + 12094 LUT2 8 AB + 12095 LUT4 9000 CD(a^B) + 12096 LUT3 CA C?A:B + 12097 LUT3 CA C?A:B + 12098 LUT2 8 AB + 12099 LUT4 9000 CD(a^B) + 12100 LUT3 CA C?A:B + 12101 LUT3 CA C?A:B + 12102 LUT2 8 AB + 12103 LUT4 9000 CD(a^B) + 12104 LUT3 CA C?A:B + 12105 LUT3 CA C?A:B + 12106 LUT2 8 AB + 12107 LUT4 9000 CD(a^B) + 12108 LUT3 CA C?A:B + 12109 LUT3 CA C?A:B + 12110 LUT2 8 AB + 12111 LUT4 1400 D(B^C)a + 12112 LUT3 CA C?A:B + 12113 LUT3 CA C?A:B + 12114 LUT2 8 AB + 12115 LUT4 1400 D(B^C)a + 12116 LUT3 CA C?A:B + 12117 LUT3 CA C?A:B + 12118 LUT2 8 AB + 12119 LUT4 1400 D(B^C)a + 12120 LUT3 CA C?A:B + 12121 LUT3 CA C?A:B + 12122 LUT2 8 AB + 12123 LUT4 1400 D(B^C)a + 12124 LUT3 CA C?A:B + 12125 LUT3 CA C?A:B + 12126 LUT2 8 AB + 12127 LUT4 1400 D(B^C)a + 12128 LUT3 CA C?A:B + 12129 LUT3 CA C?A:B + 12130 LUT2 8 AB + 12131 LUT4 1400 D(B^C)a + 12132 LUT3 CA C?A:B + 12133 LUT3 CA C?A:B + 12134 LUT2 8 AB + 12135 LUT4 1400 D(B^C)a + 12136 LUT3 CA C?A:B + 12137 LUT3 CA C?A:B + 12138 LUT2 8 AB + 12139 LUT4 1400 D(B^C)a + 12140 LUT3 CA C?A:B + 12141 LUT3 CA C?A:B + 12142 LUT2 8 AB + 12143 LUT4 4100 D(B^c)a + 12144 LUT3 CA C?A:B + 12145 LUT3 CA C?A:B + 12146 LUT2 8 AB + 12147 LUT4 4100 D(B^c)a + 12148 LUT3 CA C?A:B + 12149 LUT3 CA C?A:B + 12150 LUT2 8 AB + 12151 LUT4 4100 D(B^c)a + 12152 LUT3 CA C?A:B + 12153 LUT3 CA C?A:B + 12154 LUT2 8 AB + 12155 LUT4 4100 D(B^c)a + 12156 LUT3 CA C?A:B + 12157 LUT3 CA C?A:B + 12158 LUT2 8 AB + 12159 LUT4 4100 D(B^c)a + 12160 LUT3 CA C?A:B + 12161 LUT3 CA C?A:B + 12162 LUT2 8 AB + 12163 LUT4 4100 D(B^c)a + 12164 LUT3 CA C?A:B + 12165 LUT3 CA C?A:B + 12166 LUT2 8 AB + 12167 LUT4 4100 D(B^c)a + 12168 LUT3 CA C?A:B + 12169 LUT3 CA C?A:B + 12170 LUT2 8 AB + 12171 LUT4 4100 D(B^c)a + 12172 LUT3 CA C?A:B + 12173 LUT3 CA C?A:B + 12174 LUT2 4 aB + 12175 LUT3 CA C?A:B + 12176 LUT3 CA C?A:B + 12177 LUT2 4 aB + 12178 LUT3 CA C?A:B + 12179 LUT3 CA C?A:B + 12180 LUT2 4 aB + 12181 LUT3 CA C?A:B + 12182 LUT3 CA C?A:B + 12183 LUT2 4 aB + 12184 LUT3 CA C?A:B + 12185 LUT3 CA C?A:B + 12186 LUT2 4 aB + 12187 LUT3 CA C?A:B + 12188 LUT3 CA C?A:B + 12189 LUT2 4 aB + 12190 LUT3 CA C?A:B + 12191 LUT3 CA C?A:B + 12192 LUT2 4 aB + 12193 LUT3 CA C?A:B + 12194 LUT3 CA C?A:B + 12195 LUT2 4 aB + 12196 LUT3 CA C?A:B + 12197 LUT3 CA C?A:B + 12198 LUT2 4 aB + 12199 LUT3 CA C?A:B + 12200 LUT3 CA C?A:B + 12201 LUT2 4 aB + 12202 LUT3 CA C?A:B + 12203 LUT3 CA C?A:B + 12204 LUT2 4 aB + 12205 LUT3 CA C?A:B + 12206 LUT3 CA C?A:B + 12207 LUT2 4 aB + 12208 LUT3 CA C?A:B + 12209 LUT3 CA C?A:B + 12210 LUT2 4 aB + 12211 LUT3 CA C?A:B + 12212 LUT3 CA C?A:B + 12213 LUT2 4 aB + 12214 LUT3 CA C?A:B + 12215 LUT3 CA C?A:B + 12216 LUT2 4 aB + 12217 LUT3 CA C?A:B + 12218 LUT3 CA C?A:B + 12219 LUT2 4 aB + 12220 LUT3 CA C?A:B + 12221 LUT3 CA C?A:B + 12222 LUT2 4 aB + 12223 LUT3 CA C?A:B + 12224 LUT3 CA C?A:B + 12225 LUT2 4 aB + 12226 LUT3 CA C?A:B + 12227 LUT3 CA C?A:B + 12228 LUT2 4 aB + 12229 LUT3 CA C?A:B + 12230 LUT3 CA C?A:B + 12231 LUT2 4 aB + 12232 LUT3 CA C?A:B + 12233 LUT3 CA C?A:B + 12234 LUT2 4 aB + 12235 LUT3 CA C?A:B + 12236 LUT3 CA C?A:B + 12237 LUT2 4 aB + 12238 LUT3 CA C?A:B + 12239 LUT3 CA C?A:B + 12240 LUT2 4 aB + 12241 LUT3 CA C?A:B + 12242 LUT3 CA C?A:B + 12243 LUT2 4 aB + 12244 LUT3 CA C?A:B + 12245 LUT3 CA C?A:B + 12246 LUT2 4 aB + 12247 LUT3 CA C?A:B + 12248 LUT3 CA C?A:B + 12249 LUT2 4 aB + 12250 LUT3 CA C?A:B + 12251 LUT3 CA C?A:B + 12252 LUT2 4 aB + 12253 LUT3 CA C?A:B + 12254 LUT3 CA C?A:B + 12255 LUT2 4 aB + 12256 LUT3 CA C?A:B + 12257 LUT3 CA C?A:B + 12258 LUT2 4 aB + 12259 LUT3 CA C?A:B + 12260 LUT3 CA C?A:B + 12261 LUT2 4 aB + 12262 LUT3 CA C?A:B + 12263 LUT3 CA C?A:B + 12264 LUT2 4 aB + 12265 LUT3 CA C?A:B + 12266 LUT3 CA C?A:B + 12267 LUT2 4 aB + 12268 LUT3 CA C?A:B + 12269 LUT2 4 aB + 12270 LUT2 8 AB + 12271 LUT2 8 AB + 12272 LUT2 8 AB + 12273 LUT4 0100 abcD + 12274 LUT3 BF /aB\+c + 12275 LUT4 0700 cD/AB\ + 12276 LUT4 CA00 D(C?A:B) + 12277 LUT3 01 abc + 12278 LUT4 0777 /AB\(d+c) + 12279 LUT3 40 aBC + 12280 LUT3 40 aBC + 12281 LUT3 10 abC + 12282 LUT4 0777 /AB\(d+c) + 12283 LUT3 80 ABC + 12284 LUT3 40 aBC + 12285 LUT4 AC00 D(c?A:B) + 12286 LUT3 10 abC + 12287 LUT4 8FFF (AB)+c+d + 12288 LUT4 0001 abcd + 12289 LUT4 CA00 D(C?A:B) + 12290 LUT2 8 AB + 12291 LUT2 8 AB + 12292 LUT4 CA00 D(C?A:B) + 12293 LUT4 0777 /AB\(d+c) + 12294 LUT4 CA00 D(C?A:B) + 12295 LUT4 0700 cD/AB\ + 12296 LUT4 0777 /AB\(d+c) + 12297 LUT4 CA00 D(C?A:B) + 12298 LUT3 BF /aB\+c + 12299 LUT4 0700 cD/AB\ + 12300 LUT4 CA00 D(C?A:B) + 12301 LUT4 0777 /AB\(d+c) + 12302 LUT4 CA00 D(C?A:B) + 12303 LUT4 0777 /AB\(d+c) + 12304 LUT3 7F /AB\+c + 12305 LUT4 007F ((/AB\)+c)d + 12306 LUT4 CA00 D(C?A:B) + 12307 LUT4 0777 /AB\(d+c) + 12308 LUT4 0777 /AB\(d+c) + 12309 LUT3 BF /aB\+c + 12310 LUT4 7F00 ((/AB\)+c)D + 12311 LUT4 0777 /AB\(d+c) + 12312 LUT4 CA00 D(C?A:B) + 12313 LUT4 0777 /AB\(d+c) + 12314 LUT4 EFFF /ab\+c+d + 12315 LUT4 0007 cd/AB\ + 12316 LUT2 8 AB + 12317 LUT3 80 ABC + 12318 LUT4 CA00 D(C?A:B) + 12319 LUT4 0777 /AB\(d+c) + 12320 LUT4 F8FF (AB)+C+d + 12321 LUT4 0700 cD/AB\ + 12322 LUT4 CA00 D(C?A:B) + 12323 LUT4 F4FF (aB)+C+d + 12324 LUT4 F800 ((AB)+C)D + 12325 LUT4 BB0F D?c:/aB\ + 12326 LUT2 B /aB\ + 12327 LUT2 B /aB\ + 12328 LUT2 B /aB\ + 12329 LUT3 AC c?A:B + 12330 LUT2 7 /AB\ + 12331 LUT2 1 ab + 12332 LUT3 C5 C?a:B + 12333 LUT3 69 A^B^c + 12334 LUT3 C5 C?a:B + 12335 LUT4 17E8 (AB?1:c:c:0)^d + 12336 LUT3 C5 C?a:B + 12337 LUT4 FFE8 (AB?0:C:C:1)+D + 12338 LUT3 CA C?A:B + 12339 LUT2 B /aB\ + 12340 LUT3 01 abc + 12341 LUT2 4 aB + 12342 LUT4 0001 abcd + 12343 LUT2 4 aB + 12344 LUT2 B /aB\ + 12345 LUT2 B /aB\ + 12346 LUT2 B /aB\ + 12347 LUT2 B /aB\ + 12348 LUT3 CA C?A:B + 12349 LUT3 C5 C?a:B + 12350 LUT3 C5 C?a:B + 12351 LUT3 C5 C?a:B + 12352 LUT3 CA C?A:B + 12353 LUT2 4 aB + 12354 LUT4 A300 D(C?b:A) + 12355 LUT4 C500 D(C?a:B) + 12356 LUT2 8 AB + 12357 LUT2 8 AB + 12358 LUT2 8 AB + 12359 LUT2 8 AB + 12360 LUT4 3A00 D(c?b:A) + 12361 LUT3 40 aBC + 12362 LUT2 4 aB + 12363 LUT2 8 AB + 12364 LUT4 0001 abcd + 12365 LUT4 0001 abcd + 12366 LUT2 8 AB + 12367 LUT2 8 AB + 12368 LUT2 8 AB + 12369 LUT2 8 AB + 12370 LUT2 8 AB + 12371 LUT2 8 AB + 12372 LUT2 8 AB + 12373 LUT2 8 AB + 12374 LUT2 8 AB + 12375 LUT2 8 AB + 12376 LUT3 90 C(a^B) + 12377 LUT3 CA C?A:B + 12378 LUT3 AC c?A:B + 12379 LUT3 AC c?A:B + 12380 LUT2 B /aB\ + 12381 LUT2 8 AB + 12382 LUT3 0D c/Ab\ + 12383 LUT2 8 AB + 12384 LUT2 8 AB + 12385 LUT2 4 aB + 12386 LUT2 4 aB + 12387 LUT2 4 aB + 12388 LUT2 4 aB + 12389 LUT4 F888 (AB)+(CD) + 12390 LUT3 10 abC + 12391 LUT4 F888 (AB)+(CD) + 12392 LUT4 F888 (AB)+(CD) + 12393 LUT4 F888 (AB)+(CD) + 12394 LUT4 F888 (AB)+(CD) + 12395 LUT2 4 aB + 12396 LUT2 4 aB + 12397 LUT2 4 aB + 12398 LUT2 4 aB + 12399 LUT2 8 AB + 12400 LUT3 AC c?A:B + 12401 LUT3 CA C?A:B + 12402 LUT3 CA C?A:B + 12403 LUT3 CA C?A:B + 12404 LUT3 CA C?A:B + 12405 LUT3 CA C?A:B + 12406 LUT4 11F0 D?C:ab + 12407 LUT4 B400 AD?0:0:B^C:C + 12408 LUT3 01 abc + 12409 LUT2 1 ab + 12410 LUT3 AC c?A:B + 12411 LUT3 AC c?A:B + 12412 LUT2 B /aB\ + 12413 LUT2 4 aB + 12414 LUT2 8 AB + 12415 LUT4 0001 abcd + 12416 LUT2 4 aB + 12417 LUT2 4 aB + 12418 LUT2 B /aB\ + 12419 LUT3 3A c?b:A + 12420 LUT3 3A c?b:A + 12421 LUT2 4 aB + 12422 LUT2 4 aB + 12423 LUT2 4 aB + 12424 LUT2 4 aB + 12425 LUT4 F888 (AB)+(CD) + 12426 LUT3 0D c/Ab\ + 12427 LUT3 10 abC + 12428 LUT4 F888 (AB)+(CD) + 12429 LUT4 F888 (AB)+(CD) + 12430 LUT4 F888 (AB)+(CD) + 12431 LUT4 F888 (AB)+(CD) + 12432 LUT2 4 aB + 12433 LUT2 4 aB + 12434 LUT2 4 aB + 12435 LUT2 4 aB + 12436 LUT2 4 aB + 12437 LUT2 1 ab + 12438 LUT2 8 AB + 12439 LUT4 4100 D(B^c)a + 12440 LUT4 3007 DC?/AB\:0:0:b + 12441 LUT4 C0BE BD?/ac\:/aC\:0:C + 12442 LUT3 01 abc + 12443 LUT3 FE /ab\+C + 12444 LUT4 FF10 (abC)+D + 12445 LUT3 10 abC + 12446 LUT3 53 C?b:a + 12447 LUT4 0A0C DC?B:A:0:0 + 12448 LUT3 0D c/Ab\ + 12449 LUT3 40 aBC + 12450 LUT3 40 aBC + 12451 LUT3 40 aBC + 12452 LUT2 4 aB + 12453 LUT3 40 aBC + 12454 LUT4 00F8 ((AB)+C)d + 12455 LUT2 4 aB + 12456 LUT3 40 aBC + 12457 LUT4 1000 abCD + 12458 LUT4 0001 abcd + 12459 LUT4 0001 abcd + 12460 LUT3 10 abC + 12461 LUT3 0E c/ab\ + 12462 LUT4 0001 abcd + 12463 LUT2 8 AB + 12464 LUT4 007F ((/AB\)+c)d + 12465 LUT3 40 aBC + 12466 LUT3 80 ABC + 12467 LUT4 0001 abcd + 12468 LUT4 F400 ((aB)+C)D + 12469 LUT3 70 C/AB\ + 12470 LUT4 F100 ((ab)+C)D + 12471 LUT2 4 aB + 12472 LUT4 F100 ((ab)+C)D + 12473 LUT4 0001 abcd + 12474 LUT2 E /ab\ + 12475 LUT2 8 AB + 12476 LUT2 E /ab\ + 12477 LUT2 E /ab\ + 12478 LUT3 CA C?A:B + 12479 LUT3 CA C?A:B + 12480 LUT3 3A c?b:A + 12481 LUT4 78E1 AB?c^D:C:C:C^D + 12482 LUT4 EEF0 D?C:/ab\ + 12483 LUT3 07 c/AB\ + 12484 LUT4 001F ((ab)+c)d + 12485 LUT4 11F0 D?C:ab + 12486 LUT3 CA C?A:B + 12487 LUT2 1 ab + 12488 LUT4 8000 ABCD + 12489 LUT4 0001 abcd + 12490 LUT4 0001 abcd + 12491 LUT4 0001 abcd + 12492 LUT4 0001 abcd + 12493 LUT3 CA C?A:B + 12494 LUT3 CA C?A:B + 12495 LUT3 CA C?A:B + 12496 LUT3 CA C?A:B + 12497 LUT3 CA C?A:B + 12498 LUT3 CA C?A:B + 12499 LUT3 CA C?A:B + 12500 LUT3 CA C?A:B + 12501 LUT3 CA C?A:B + 12502 LUT3 CA C?A:B + 12503 LUT3 CA C?A:B + 12504 LUT3 CA C?A:B + 12505 LUT3 CA C?A:B + 12506 LUT3 CA C?A:B + 12507 LUT3 CA C?A:B + 12508 LUT4 00F4 ((aB)+C)d + 12509 LUT3 7F /AB\+c + 12510 LUT4 4000 aBCD + 12511 LUT4 1000 abCD + 12512 LUT4 8000 ABCD + 12513 LUT4 0001 abcd + 12514 LUT4 0001 abcd + 12515 LUT4 0001 abcd + 12516 LUT4 0001 abcd + 12517 LUT4 0001 abcd + 12518 LUT3 80 ABC + 12519 LUT3 01 abc + 12520 LUT4 0001 abcd + 12521 LUT4 0001 abcd + 12522 LUT4 0100 abcD + 12523 LUT4 0001 abcd + 12524 LUT4 0001 abcd + 12525 LUT4 0001 abcd + 12526 LUT4 00F4 ((aB)+C)d + 12527 LUT2 8 AB + 12528 LUT2 8 AB + 12529 LUT3 10 abC + 12530 LUT3 01 abc + 12531 LUT2 8 AB + 12532 LUT4 0001 abcd + 12533 LUT4 0001 abcd + 12534 LUT4 00F4 ((aB)+C)d + 12535 LUT4 00F4 ((aB)+C)d + 12536 LUT4 7FFF /AB\+c+d + 12537 LUT4 0700 cD/AB\ + 12538 LUT2 8 AB + 12539 LUT4 1000 abCD + 12540 LUT4 0777 /AB\(d+c) + 12541 LUT4 8000 ABCD + 12542 LUT4 0100 abcD + 12543 LUT4 4000 aBCD + 12544 LUT4 0700 cD/AB\ + 12545 LUT4 0777 /AB\(d+c) + 12546 LUT4 4000 aBCD + 12547 LUT4 1000 abCD + 12548 LUT2 8 AB + 12549 LUT4 0100 abcD + 12550 LUT4 0100 abcD + 12551 LUT4 0700 cD/AB\ + 12552 LUT4 0777 /AB\(d+c) + 12553 LUT4 4000 aBCD + 12554 LUT4 1000 abCD + 12555 LUT2 8 AB + 12556 LUT4 1000 abCD + 12557 LUT4 0001 abcd + 12558 LUT4 0001 abcd + 12559 LUT2 8 AB + 12560 LUT4 0100 abcD + 12561 LUT2 8 AB + 12562 LUT4 4000 aBCD + 12563 LUT2 8 AB + 12564 LUT4 1000 abCD + 12565 LUT2 8 AB + 12566 LUT4 1000 abCD + 12567 LUT4 00F4 ((aB)+C)d + 12568 LUT4 8FFF (AB)+c+d + 12569 LUT4 7000 CD/AB\ + 12570 LUT4 7000 CD/AB\ + 12571 LUT3 70 C/AB\ + 12572 LUT4 0777 /AB\(d+c) + 12573 LUT4 0777 /AB\(d+c) + 12574 LUT4 0007 cd/AB\ + 12575 LUT2 8 AB + 12576 LUT2 8 AB + 12577 LUT4 0700 cD/AB\ + 12578 LUT4 0007 cd/AB\ + 12579 LUT2 8 AB + 12580 LUT2 8 AB + 12581 LUT2 8 AB + 12582 LUT4 00F4 ((aB)+C)d + 12583 LUT4 0700 cD/AB\ + 12584 LUT2 8 AB + 12585 LUT4 0777 /AB\(d+c) + 12586 LUT4 0777 /AB\(d+c) + 12587 LUT3 70 C/AB\ + 12588 LUT4 0777 /AB\(d+c) + 12589 LUT4 7000 CD/AB\ + 12590 LUT4 0777 /AB\(d+c) + 12591 LUT4 0777 /AB\(d+c) + 12592 LUT4 00F4 ((aB)+C)d + 12593 LUT2 4 aB + 12594 LUT4 00F4 ((aB)+C)d + 12595 LUT2 8 AB + 12596 LUT4 1000 abCD + 12597 LUT4 0100 abcD + 12598 LUT3 0B c/aB\ + 12599 LUT3 0B c/aB\ + 12600 LUT3 0B c/aB\ + 12601 LUT3 0B c/aB\ + 12602 LUT2 8 AB + 12603 LUT2 8 AB + 12604 LUT2 8 AB + 12605 LUT2 4 aB + 12606 LUT2 4 aB + 12607 LUT2 8 AB + 12608 LUT2 8 AB + 12609 LUT2 8 AB + 12610 LUT2 8 AB + 12611 LUT2 E /ab\ + 12612 LUT3 C5 C?a:B + 12613 LUT2 8 AB + 12614 LUT2 8 AB + 12615 LUT4 0100 abcD + 12616 LUT4 0BBB /aB\(d+c) + 12617 LUT3 C5 C?a:B + 12618 LUT4 0BBB /aB\(d+c) + 12619 LUT4 ACCC DC?B:B:B:A + 12620 LUT2 4 aB + 12621 LUT4 4000 aBCD + 12622 LUT3 C5 C?a:B + 12623 LUT2 8 AB + 12624 LUT4 1000 abCD + 12625 LUT3 35 c?b:a + 12626 LUT3 C5 C?a:B + 12627 LUT3 35 c?b:a + 12628 LUT3 C5 C?a:B + 12629 LUT3 35 c?b:a + 12630 LUT3 C5 C?a:B + 12631 LUT3 35 c?b:a + 12632 LUT3 C5 C?a:B + 12633 LUT3 35 c?b:a + 12634 LUT3 C5 C?a:B + 12635 LUT3 35 c?b:a + 12636 LUT3 C5 C?a:B + 12637 LUT3 35 c?b:a + 12638 LUT3 C5 C?a:B + 12639 LUT3 35 c?b:a + 12640 LUT3 C5 C?a:B + 12641 LUT2 8 AB + 12642 LUT2 8 AB + 12643 LUT3 35 c?b:a + 12644 LUT3 C5 C?a:B + 12645 LUT3 35 c?b:a + 12646 LUT3 C5 C?a:B + 12647 LUT3 35 c?b:a + 12648 LUT3 C5 C?a:B + 12649 LUT3 35 c?b:a + 12650 LUT3 C5 C?a:B + 12651 LUT3 35 c?b:a + 12652 LUT3 C5 C?a:B + 12653 LUT3 35 c?b:a + 12654 LUT3 C5 C?a:B + 12655 LUT3 35 c?b:a + 12656 LUT3 C5 C?a:B + 12657 LUT3 35 c?b:a + 12658 LUT3 C5 C?a:B + 12659 LUT2 8 AB + 12660 LUT2 8 AB + 12661 LUT3 53 C?b:a + 12662 LUT3 C5 C?a:B + 12663 LUT3 35 c?b:a + 12664 LUT3 C5 C?a:B + 12665 LUT3 35 c?b:a + 12666 LUT3 C5 C?a:B + 12667 LUT3 35 c?b:a + 12668 LUT3 C5 C?a:B + 12669 LUT3 35 c?b:a + 12670 LUT3 C5 C?a:B + 12671 LUT3 35 c?b:a + 12672 LUT3 C5 C?a:B + 12673 LUT3 35 c?b:a + 12674 LUT3 C5 C?a:B + 12675 LUT3 35 c?b:a + 12676 LUT3 C5 C?a:B + 12677 LUT2 8 AB + 12678 LUT3 35 c?b:a + 12679 LUT3 C5 C?a:B + 12680 LUT3 35 c?b:a + 12681 LUT3 C5 C?a:B + 12682 LUT3 35 c?b:a + 12683 LUT3 C5 C?a:B + 12684 LUT3 35 c?b:a + 12685 LUT3 C5 C?a:B + 12686 LUT3 35 c?b:a + 12687 LUT3 C5 C?a:B + 12688 LUT3 35 c?b:a + 12689 LUT3 C5 C?a:B + 12690 LUT3 35 c?b:a + 12691 LUT3 C5 C?a:B + 12692 LUT3 35 c?b:a + 12693 LUT3 AC c?A:B + 12694 LUT3 CA C?A:B + 12695 LUT3 CA C?A:B + 12696 LUT3 CA C?A:B + 12697 LUT3 CA C?A:B + 12698 LUT3 CA C?A:B + 12699 LUT3 CA C?A:B + 12700 LUT3 CA C?A:B + 12701 LUT3 CA C?A:B + 12702 LUT3 CA C?A:B + 12703 LUT3 CA C?A:B + 12704 LUT3 CA C?A:B + 12705 LUT3 CA C?A:B + 12706 LUT3 CA C?A:B + 12707 LUT3 CA C?A:B + 12708 LUT3 CA C?A:B + 12709 LUT3 AC c?A:B + 12710 LUT3 CA C?A:B + 12711 LUT3 CA C?A:B + 12712 LUT3 CA C?A:B + 12713 LUT3 CA C?A:B + 12714 LUT3 CA C?A:B + 12715 LUT3 CA C?A:B + 12716 LUT3 CA C?A:B + 12717 LUT3 CA C?A:B + 12718 LUT3 CA C?A:B + 12719 LUT3 CA C?A:B + 12720 LUT3 CA C?A:B + 12721 LUT3 CA C?A:B + 12722 LUT3 CA C?A:B + 12723 LUT3 CA C?A:B + 12724 LUT3 CA C?A:B + 12725 LUT3 AC c?A:B + 12726 LUT3 CA C?A:B + 12727 LUT3 CA C?A:B + 12728 LUT3 CA C?A:B + 12729 LUT3 CA C?A:B + 12730 LUT3 CA C?A:B + 12731 LUT3 CA C?A:B + 12732 LUT3 CA C?A:B + 12733 LUT3 CA C?A:B + 12734 LUT3 CA C?A:B + 12735 LUT3 CA C?A:B + 12736 LUT3 CA C?A:B + 12737 LUT3 CA C?A:B + 12738 LUT3 CA C?A:B + 12739 LUT3 CA C?A:B + 12740 LUT3 CA C?A:B + 12741 LUT3 AC c?A:B + 12742 LUT3 CA C?A:B + 12743 LUT3 CA C?A:B + 12744 LUT3 CA C?A:B + 12745 LUT3 CA C?A:B + 12746 LUT3 CA C?A:B + 12747 LUT3 CA C?A:B + 12748 LUT3 CA C?A:B + 12749 LUT3 CA C?A:B + 12750 LUT3 CA C?A:B + 12751 LUT3 CA C?A:B + 12752 LUT3 CA C?A:B + 12753 LUT3 CA C?A:B + 12754 LUT3 CA C?A:B + 12755 LUT3 CA C?A:B + 12756 LUT3 CA C?A:B + 12757 LUT2 4 aB + 12758 LUT2 4 aB + 12759 LUT2 4 aB + 12760 LUT2 4 aB + 12761 LUT2 4 aB + 12762 LUT2 4 aB + 12763 LUT2 4 aB + 12764 LUT2 4 aB + 12765 LUT2 4 aB + 12766 LUT2 4 aB + 12767 LUT2 4 aB + 12768 LUT2 4 aB + 12769 LUT2 4 aB + 12770 LUT2 4 aB + 12771 LUT2 4 aB + 12772 LUT2 4 aB + 12773 LUT2 4 aB + 12774 LUT2 4 aB + 12775 LUT2 4 aB + 12776 LUT2 4 aB + 12777 LUT2 4 aB + 12778 LUT2 4 aB + 12779 LUT2 4 aB + 12780 LUT2 4 aB + 12781 LUT2 4 aB + 12782 LUT2 4 aB + 12783 LUT2 4 aB + 12784 LUT2 4 aB + 12785 LUT2 4 aB + 12786 LUT2 4 aB + 12787 LUT2 4 aB + 12788 LUT2 4 aB + 12789 LUT2 4 aB + 12790 LUT2 4 aB + 12791 LUT2 4 aB + 12792 LUT2 4 aB + 12793 LUT2 4 aB + 12794 LUT2 4 aB + 12795 LUT2 4 aB + 12796 LUT2 4 aB + 12797 LUT2 4 aB + 12798 LUT2 4 aB + 12799 LUT2 4 aB + 12800 LUT2 4 aB + 12801 LUT2 4 aB + 12802 LUT2 4 aB + 12803 LUT2 4 aB + 12804 LUT2 4 aB + 12805 LUT2 4 aB + 12806 LUT2 4 aB + 12807 LUT2 4 aB + 12808 LUT2 4 aB + 12809 LUT2 4 aB + 12810 LUT2 4 aB + 12811 LUT2 4 aB + 12812 LUT2 4 aB + 12813 LUT2 4 aB + 12814 LUT2 4 aB + 12815 LUT2 4 aB + 12816 LUT2 4 aB + 12817 LUT2 4 aB + 12818 LUT2 4 aB + 12819 LUT2 4 aB + 12820 LUT2 4 aB + 12821 LUT2 B /aB\ + 12822 LUT2 B /aB\ + 12823 LUT4 E000 CD/ab\ + 12824 LUT3 01 abc + 12825 LUT2 4 aB + 12826 LUT4 1000 abCD + 12827 LUT4 ACCC DC?B:B:B:A + 12828 LUT3 0D c/Ab\ + 12829 LUT4 FF10 (abC)+D + 12830 LUT3 10 abC + 12831 LUT4 BF00 ((/aB\)+c)D + 12832 LUT4 BF00 ((/aB\)+c)D + 12833 LUT4 BF00 ((/aB\)+c)D + 12834 LUT3 CA C?A:B + 12835 LUT3 CA C?A:B + 12836 LUT3 CA C?A:B + 12837 LUT3 CA C?A:B + 12838 LUT4 BF00 ((/aB\)+c)D + 12839 LUT4 BF00 ((/aB\)+c)D + 12840 LUT4 BF00 ((/aB\)+c)D + 12841 LUT3 CA C?A:B + 12842 LUT3 CA C?A:B + 12843 LUT3 CA C?A:B + 12844 LUT3 CA C?A:B + 12845 LUT3 CA C?A:B + 12846 LUT4 AC00 D(c?A:B) + 12847 LUT4 CA00 D(C?A:B) + 12848 LUT4 CA00 D(C?A:B) + 12849 LUT4 CA00 D(C?A:B) + 12850 LUT4 CA00 D(C?A:B) + 12851 LUT4 CA00 D(C?A:B) + 12852 LUT4 CA00 D(C?A:B) + 12853 LUT4 CA00 D(C?A:B) + 12854 LUT4 CA00 D(C?A:B) + 12855 LUT4 CA00 D(C?A:B) + 12856 LUT4 CA00 D(C?A:B) + 12857 LUT4 CA00 D(C?A:B) + 12858 LUT4 CA00 D(C?A:B) + 12859 LUT4 CA00 D(C?A:B) + 12860 LUT4 CA00 D(C?A:B) + 12861 LUT4 CA00 D(C?A:B) + 12862 LUT4 CA00 D(C?A:B) + 12863 LUT4 CA00 D(C?A:B) + 12864 LUT4 CA00 D(C?A:B) + 12865 LUT2 8 AB + 12866 LUT2 8 AB + 12867 LUT2 8 AB + 12868 LUT2 8 AB + 12869 LUT2 8 AB + 12870 LUT2 8 AB + 12871 LUT2 8 AB + 12872 LUT2 8 AB + 12873 LUT2 8 AB + 12874 LUT2 8 AB + 12875 LUT2 8 AB + 12876 LUT2 8 AB + 12877 LUT2 8 AB + 12878 LUT2 8 AB + 12879 LUT2 8 AB + 12880 LUT2 8 AB + 12881 LUT2 8 AB + 12882 LUT2 8 AB + 12883 LUT2 8 AB + 12884 LUT2 8 AB + 12885 LUT2 8 AB + 12886 LUT2 8 AB + 12887 LUT2 8 AB + 12888 LUT2 8 AB + 12889 LUT2 8 AB + 12890 LUT2 8 AB + 12891 LUT2 8 AB + 12892 LUT2 8 AB + 12893 LUT2 8 AB + 12894 LUT2 8 AB + 12895 LUT2 8 AB + 12896 LUT2 8 AB + 12897 LUT2 8 AB + 12898 LUT2 8 AB + 12899 LUT2 8 AB + 12900 LUT2 8 AB + 12901 LUT2 8 AB + 12902 LUT2 8 AB + 12903 LUT2 8 AB + 12904 LUT2 8 AB + 12905 LUT2 8 AB + 12906 LUT2 8 AB + 12907 LUT2 8 AB + 12908 LUT2 8 AB + 12909 LUT2 8 AB + 12910 LUT2 8 AB + 12911 LUT2 8 AB + 12912 LUT2 8 AB + 12913 LUT2 8 AB + 12914 LUT2 8 AB + 12915 LUT2 8 AB + 12916 LUT2 8 AB + 12917 LUT2 8 AB + 12918 LUT2 8 AB + 12919 LUT2 8 AB + 12920 LUT2 8 AB + 12921 LUT2 8 AB + 12922 LUT2 8 AB + 12923 LUT2 8 AB + 12924 LUT2 8 AB + 12925 LUT2 8 AB + 12926 LUT2 8 AB + 12927 LUT2 8 AB + 12928 LUT2 8 AB + 12929 LUT2 8 AB + 12930 LUT2 8 AB + 12931 LUT4 F044 D?aB:C + 12932 LUT2 1 ab + 12933 LUT4 F800 ((AB)+C)D + 12934 LUT3 80 ABC + 12935 LUT4 8000 ABCD + 12936 LUT3 10 abC + 12937 LUT3 E0 C/ab\ + 12938 LUT4 0001 abcd + 12939 LUT3 01 abc + 12940 LUT4 8000 ABCD + 12941 LUT4 0001 abcd + 12942 LUT4 0001 abcd + 12943 LUT4 1000 abCD + 12944 LUT3 10 abC + 12945 LUT3 01 abc + 12946 LUT4 8000 ABCD + 12947 LUT4 8000 ABCD + 12948 LUT4 8000 ABCD + 12949 LUT4 8000 ABCD + 12950 LUT4 8000 ABCD + 12951 LUT2 1 ab + 12952 LUT4 8000 ABCD + 12953 LUT4 8000 ABCD + 12954 LUT4 8000 ABCD + 12955 LUT4 8000 ABCD + 12956 LUT3 10 abC + 12957 LUT4 0001 abcd + 12958 LUT4 8000 ABCD + 12959 LUT4 8000 ABCD + 12960 LUT4 8000 ABCD + 12961 LUT4 8000 ABCD + 12962 LUT4 8000 ABCD + 12963 LUT4 8000 ABCD + 12964 LUT4 AC53 (C?b:a)^D + 12965 LUT4 AC53 (C?b:a)^D + 12966 LUT3 35 c?b:a + 12967 LUT2 4 aB + 12968 LUT4 F044 D?aB:C + 12969 LUT2 1 ab + 12970 LUT4 0E00 cD/ab\ + 12971 LUT4 BE00 AD?0:0:B^C:1 + 12972 LUT2 6 A^B + 12973 LUT2 4 aB + 12974 LUT2 8 AB + 12975 LUT3 0B c/aB\ + 12976 LUT4 FF10 (abC)+D + 12977 LUT2 1 ab + 12978 LUT3 10 abC + 12979 LUT3 CA C?A:B + 12980 LUT3 CA C?A:B + 12981 LUT3 CA C?A:B + 12982 LUT3 CA C?A:B + 12983 LUT3 CA C?A:B + 12984 LUT3 CA C?A:B + 12985 LUT3 F8 (AB)+C + 12986 LUT2 E /ab\ + 12987 LUT4 CA00 D(C?A:B) + 12988 LUT2 4 aB + 12989 LUT3 70 C/AB\ + 12990 LUT4 AC00 D(c?A:B) + 12991 LUT2 1 ab + 12992 LUT2 E /ab\ + 12993 LUT4 CA00 D(C?A:B) + 12994 LUT2 E /ab\ + 12995 LUT4 CA00 D(C?A:B) + 12996 LUT4 CA00 D(C?A:B) + 12997 LUT4 CA00 D(C?A:B) + 12998 LUT4 CA00 D(C?A:B) + 12999 LUT4 F444 (aB)+(CD) + 13000 LUT3 35 c?b:a + 13001 LUT4 F444 (aB)+(CD) + 13002 LUT3 35 c?b:a + 13003 LUT3 F4 (aB)+C + 13004 LUT2 4 aB + 13005 LUT3 35 c?b:a + 13006 LUT4 4F44 (aB)+(cD) + 13007 LUT3 35 c?b:a + 13008 LUT3 35 c?b:a + 13009 LUT4 4F44 (aB)+(cD) + 13010 LUT3 35 c?b:a + 13011 LUT3 35 c?b:a + 13012 LUT4 4F44 (aB)+(cD) + 13013 LUT3 35 c?b:a + 13014 LUT3 35 c?b:a + 13015 LUT4 4F44 (aB)+(cD) + 13016 LUT3 35 c?b:a + 13017 LUT3 35 c?b:a + 13018 LUT4 4F44 (aB)+(cD) + 13019 LUT3 35 c?b:a + 13020 LUT3 35 c?b:a + 13021 LUT4 4F44 (aB)+(cD) + 13022 LUT3 35 c?b:a + 13023 LUT3 35 c?b:a + 13024 LUT4 4F44 (aB)+(cD) + 13025 LUT3 35 c?b:a + 13026 LUT3 35 c?b:a + 13027 LUT4 4F44 (aB)+(cD) + 13028 LUT3 35 c?b:a + 13029 LUT3 35 c?b:a + 13030 LUT4 4F44 (aB)+(cD) + 13031 LUT3 35 c?b:a + 13032 LUT3 35 c?b:a + 13033 LUT4 4F44 (aB)+(cD) + 13034 LUT3 35 c?b:a + 13035 LUT3 35 c?b:a + 13036 LUT4 F888 (AB)+(CD) + 13037 LUT4 F888 (AB)+(CD) + 13038 LUT4 E000 CD/ab\ + 13039 LUT3 01 abc + 13040 LUT2 4 aB + 13041 LUT4 1000 abCD + 13042 LUT4 ACCC DC?B:B:B:A + 13043 LUT3 0D c/Ab\ + 13044 LUT4 00F4 ((aB)+C)d + 13045 LUT3 10 abC + 13046 LUT4 BF00 ((/aB\)+c)D + 13047 LUT4 BF00 ((/aB\)+c)D + 13048 LUT4 BF00 ((/aB\)+c)D + 13049 LUT2 8 AB + 13050 LUT3 CA C?A:B + 13051 LUT3 CA C?A:B + 13052 LUT3 CA C?A:B + 13053 LUT3 CA C?A:B + 13054 LUT4 BF00 ((/aB\)+c)D + 13055 LUT4 BF00 ((/aB\)+c)D + 13056 LUT4 BF00 ((/aB\)+c)D + 13057 LUT4 CA00 D(C?A:B) + 13058 LUT4 CA00 D(C?A:B) + 13059 LUT4 CA00 D(C?A:B) + 13060 LUT4 CA00 D(C?A:B) + 13061 LUT4 CA00 D(C?A:B) + 13062 LUT4 CA00 D(C?A:B) + 13063 LUT4 CA00 D(C?A:B) + 13064 LUT4 CA00 D(C?A:B) + 13065 LUT4 CA00 D(C?A:B) + 13066 LUT4 CA00 D(C?A:B) + 13067 LUT4 CA00 D(C?A:B) + 13068 LUT4 CA00 D(C?A:B) + 13069 LUT4 CA00 D(C?A:B) + 13070 LUT2 8 AB + 13071 LUT2 8 AB + 13072 LUT4 F044 D?aB:C + 13073 LUT2 1 ab + 13074 LUT4 F044 D?aB:C + 13075 LUT2 1 ab + 13076 LUT3 CA C?A:B + 13077 LUT2 1 ab + 13078 LUT3 0B c/aB\ + 13079 LUT3 0B c/aB\ + 13080 LUT2 1 ab + 13081 LUT4 EF00 ((/ab\)+c)D + 13082 LUT3 F8 (AB)+C + 13083 LUT4 CA00 D(C?A:B) + 13084 LUT2 1 ab + 13085 LUT3 70 C/AB\ + 13086 LUT4 8F88 (AB)+(cD) + 13087 LUT2 4 aB + 13088 LUT4 8F88 (AB)+(cD) + 13089 LUT3 F4 (aB)+C + 13090 LUT2 4 aB + 13091 LUT4 4F44 (aB)+(cD) + 13092 LUT4 4F44 (aB)+(cD) + 13093 LUT4 4F44 (aB)+(cD) + 13094 LUT4 4F44 (aB)+(cD) + 13095 LUT4 4F44 (aB)+(cD) + 13096 LUT4 4F44 (aB)+(cD) + 13097 LUT4 4F44 (aB)+(cD) + 13098 LUT4 4F44 (aB)+(cD) + 13099 LUT4 4F44 (aB)+(cD) + 13100 LUT4 4F44 (aB)+(cD) + 13101 LUT4 F888 (AB)+(CD) + 13102 LUT4 F888 (AB)+(CD) + 13103 LUT3 0B c/aB\ + 13104 LUT3 80 ABC + 13105 LUT3 E0 C/ab\ + 13106 LUT4 0001 abcd + 13107 LUT4 0001 abcd + 13108 LUT3 01 abc + 13109 LUT3 F1 (ab)+C + 13110 LUT2 4 aB + 13111 LUT2 4 aB + 13112 LUT2 4 aB + 13113 LUT2 4 aB + 13114 LUT2 4 aB + 13115 LUT2 4 aB + 13116 LUT2 4 aB + 13117 LUT2 4 aB + 13118 LUT2 4 aB + 13119 LUT3 80 ABC + 13120 LUT4 7770 /AB\(D+C) + 13121 LUT2 4 aB + 13122 LUT3 40 aBC + 13123 LUT2 8 AB + 13124 LUT2 4 aB + 13125 LUT2 1 ab + 13126 LUT3 0B c/aB\ + 13127 LUT4 00F1 ((ab)+C)d + 13128 LUT2 1 ab + 13129 LUT4 EF00 ((/ab\)+c)D + 13130 LUT4 F888 (AB)+(CD) + 13131 LUT3 80 ABC + 13132 LUT3 80 ABC + 13133 LUT2 8 AB + 13134 LUT2 4 aB + 13135 LUT4 444F (aB)+(cd) + 13136 LUT4 FF10 (abC)+D + 13137 LUT2 4 aB + 13138 LUT2 1 ab + 13139 LUT2 4 aB + 13140 LUT4 4000 aBCD + 13141 LUT3 01 abc + 13142 LUT4 0001 abcd + 13143 LUT4 0001 abcd + 13144 LUT2 E /ab\ + 13145 LUT4 00FE ((/ab\)+C)d + 13146 LUT3 CA C?A:B + 13147 LUT2 8 AB + 13148 LUT3 CA C?A:B + 13149 LUT3 CA C?A:B + 13150 LUT4 FE00 ((/ab\)+C)D + 13151 LUT3 CA C?A:B + 13152 LUT3 CA C?A:B + 13153 LUT3 CA C?A:B + 13154 LUT4 0C0A DC?A:B:0:0 + 13155 LUT4 0C0A DC?A:B:0:0 + 13156 LUT4 0C0A DC?A:B:0:0 + 13157 LUT4 0C0A DC?A:B:0:0 + 13158 LUT4 0C0A DC?A:B:0:0 + 13159 LUT4 0C0A DC?A:B:0:0 + 13160 LUT4 0C0A DC?A:B:0:0 + 13161 LUT4 0C0A DC?A:B:0:0 + 13162 LUT3 B0 C/aB\ + 13163 LUT3 0B c/aB\ + 13164 LUT2 4 aB + 13165 LUT4 7F00 ((/AB\)+c)D + 13166 LUT4 007F ((/AB\)+c)d + 13167 LUT4 7770 /AB\(D+C) + 13168 LUT3 CA C?A:B + 13169 LUT2 4 aB + 13170 LUT2 4 aB + 13171 LUT2 4 aB + 13172 LUT4 7000 CD/AB\ + 13173 LUT4 00BF ((/aB\)+c)d + 13174 LUT4 EF00 ((/ab\)+c)D + 13175 LUT3 2C BC?0:1:A:0 + 13176 LUT4 8000 ABCD + 13177 LUT2 8 AB + 13178 LUT4 CA00 D(C?A:B) + 13179 LUT3 CA C?A:B + 13180 LUT3 CA C?A:B + 13181 LUT3 CA C?A:B + 13182 LUT3 CA C?A:B + 13183 LUT3 CA C?A:B + 13184 LUT4 4000 aBCD + 13185 LUT3 CA C?A:B + 13186 LUT3 CA C?A:B + 13187 LUT3 CA C?A:B + 13188 LUT3 CA C?A:B + 13189 LUT3 CA C?A:B + 13190 LUT4 4000 aBCD + 13191 LUT3 CA C?A:B + 13192 LUT3 CA C?A:B + 13193 LUT3 CA C?A:B + 13194 LUT3 CA C?A:B + 13195 LUT3 CA C?A:B + 13196 LUT4 1000 abCD + 13197 LUT3 CA C?A:B + 13198 LUT3 CA C?A:B + 13199 LUT3 CA C?A:B + 13200 LUT3 CA C?A:B + 13201 LUT3 CA C?A:B + 13202 LUT2 8 AB + 13203 LUT3 CA C?A:B + 13204 LUT3 CA C?A:B + 13205 LUT3 CA C?A:B + 13206 LUT3 CA C?A:B + 13207 LUT3 CA C?A:B + 13208 LUT2 8 AB + 13209 LUT3 CA C?A:B + 13210 LUT3 CA C?A:B + 13211 LUT3 CA C?A:B + 13212 LUT3 CA C?A:B + 13213 LUT3 CA C?A:B + 13214 LUT2 8 AB + 13215 LUT3 CA C?A:B + 13216 LUT3 CA C?A:B + 13217 LUT3 CA C?A:B + 13218 LUT3 CA C?A:B + 13219 LUT3 CA C?A:B + 13220 LUT2 8 AB + 13221 LUT3 CA C?A:B + 13222 LUT3 CA C?A:B + 13223 LUT3 CA C?A:B + 13224 LUT3 CA C?A:B + 13225 LUT3 CA C?A:B + 13226 LUT4 8000 ABCD + 13227 LUT2 4 aB + 13228 LUT3 CA C?A:B + 13229 LUT3 CA C?A:B + 13230 LUT3 CA C?A:B + 13231 LUT3 CA C?A:B + 13232 LUT3 CA C?A:B + 13233 LUT4 4000 aBCD + 13234 LUT3 CA C?A:B + 13235 LUT3 CA C?A:B + 13236 LUT3 CA C?A:B + 13237 LUT3 CA C?A:B + 13238 LUT3 CA C?A:B + 13239 LUT4 4000 aBCD + 13240 LUT3 CA C?A:B + 13241 LUT3 CA C?A:B + 13242 LUT3 CA C?A:B + 13243 LUT3 CA C?A:B + 13244 LUT3 CA C?A:B + 13245 LUT4 1000 abCD + 13246 LUT3 CA C?A:B + 13247 LUT3 CA C?A:B + 13248 LUT3 CA C?A:B + 13249 LUT3 CA C?A:B + 13250 LUT3 CA C?A:B + 13251 LUT3 CA C?A:B + 13252 LUT3 10 abC + 13253 LUT2 8 AB + 13254 LUT2 8 AB + 13255 LUT3 CA C?A:B + 13256 LUT3 CA C?A:B + 13257 LUT3 CA C?A:B + 13258 LUT3 CA C?A:B + 13259 LUT3 CA C?A:B + 13260 LUT3 10 abC + 13261 LUT2 4 aB + 13262 LUT3 CA C?A:B + 13263 LUT3 CA C?A:B + 13264 LUT3 CA C?A:B + 13265 LUT3 CA C?A:B + 13266 LUT3 CA C?A:B + 13267 LUT3 10 abC + 13268 LUT2 8 AB + 13269 LUT2 4 aB + 13270 LUT3 CA C?A:B + 13271 LUT3 CA C?A:B + 13272 LUT3 CA C?A:B + 13273 LUT3 CA C?A:B + 13274 LUT3 CA C?A:B + 13275 LUT3 10 abC + 13276 LUT2 4 aB + 13277 LUT3 CA C?A:B + 13278 LUT3 CA C?A:B + 13279 LUT3 CA C?A:B + 13280 LUT3 CA C?A:B + 13281 LUT4 0C0A DC?A:B:0:0 + 13282 LUT2 4 aB + 13283 LUT2 4 aB + 13284 LUT2 4 aB + 13285 LUT4 1000 abCD + 13286 LUT2 4 aB + 13287 LUT2 4 aB + 13288 LUT2 4 aB + 13289 LUT2 4 aB + 13290 LUT3 CA C?A:B + 13291 LUT3 CA C?A:B + 13292 LUT3 CA C?A:B + 13293 LUT3 CA C?A:B + 13294 LUT3 CA C?A:B + 13295 LUT2 4 aB + 13296 LUT4 1000 abCD + 13297 LUT2 4 aB + 13298 LUT2 4 aB + 13299 LUT2 4 aB + 13300 LUT2 1 ab + 13301 LUT4 AF03 DC?b:1:0:A + 13302 LUT3 0E c/ab\ + 13303 LUT4 EF00 ((/ab\)+c)D + 13304 LUT4 0100 abcD + 13305 LUT3 10 abC + 13306 LUT4 0007 cd/AB\ + 13307 LUT3 CA C?A:B + 13308 LUT3 CA C?A:B + 13309 LUT3 CA C?A:B + 13310 LUT3 CA C?A:B + 13311 LUT3 CA C?A:B + 13312 LUT4 1000 abCD + 13313 LUT3 CA C?A:B + 13314 LUT3 CA C?A:B + 13315 LUT3 CA C?A:B + 13316 LUT3 CA C?A:B + 13317 LUT3 CA C?A:B + 13318 LUT4 1000 abCD + 13319 LUT3 CA C?A:B + 13320 LUT3 CA C?A:B + 13321 LUT3 CA C?A:B + 13322 LUT3 CA C?A:B + 13323 LUT3 CA C?A:B + 13324 LUT4 4000 aBCD + 13325 LUT3 CA C?A:B + 13326 LUT3 CA C?A:B + 13327 LUT3 CA C?A:B + 13328 LUT3 CA C?A:B + 13329 LUT3 CA C?A:B + 13330 LUT2 8 AB + 13331 LUT3 CA C?A:B + 13332 LUT3 CA C?A:B + 13333 LUT3 CA C?A:B + 13334 LUT3 CA C?A:B + 13335 LUT3 CA C?A:B + 13336 LUT2 8 AB + 13337 LUT3 CA C?A:B + 13338 LUT3 CA C?A:B + 13339 LUT3 CA C?A:B + 13340 LUT3 CA C?A:B + 13341 LUT3 CA C?A:B + 13342 LUT2 8 AB + 13343 LUT3 CA C?A:B + 13344 LUT3 CA C?A:B + 13345 LUT3 CA C?A:B + 13346 LUT3 CA C?A:B + 13347 LUT3 CA C?A:B + 13348 LUT2 8 AB + 13349 LUT3 CA C?A:B + 13350 LUT3 CA C?A:B + 13351 LUT3 CA C?A:B + 13352 LUT3 CA C?A:B + 13353 LUT3 CA C?A:B + 13354 LUT4 0100 abcD + 13355 LUT3 0D c/Ab\ + 13356 LUT3 CA C?A:B + 13357 LUT3 CA C?A:B + 13358 LUT3 CA C?A:B + 13359 LUT3 CA C?A:B + 13360 LUT3 CA C?A:B + 13361 LUT4 1000 abCD + 13362 LUT3 CA C?A:B + 13363 LUT3 CA C?A:B + 13364 LUT3 CA C?A:B + 13365 LUT3 CA C?A:B + 13366 LUT3 CA C?A:B + 13367 LUT4 1000 abCD + 13368 LUT3 CA C?A:B + 13369 LUT3 CA C?A:B + 13370 LUT3 CA C?A:B + 13371 LUT3 CA C?A:B + 13372 LUT3 CA C?A:B + 13373 LUT2 8 AB + 13374 LUT4 4000 aBCD + 13375 LUT3 CA C?A:B + 13376 LUT3 CA C?A:B + 13377 LUT3 CA C?A:B + 13378 LUT3 CA C?A:B + 13379 LUT3 CA C?A:B + 13380 LUT2 8 AB + 13381 LUT3 CA C?A:B + 13382 LUT3 40 aBC + 13383 LUT3 80 ABC + 13384 LUT2 1 ab + 13385 LUT3 CA C?A:B + 13386 LUT3 CA C?A:B + 13387 LUT3 CA C?A:B + 13388 LUT3 CA C?A:B + 13389 LUT3 CA C?A:B + 13390 LUT3 40 aBC + 13391 LUT3 40 aBC + 13392 LUT3 CA C?A:B + 13393 LUT3 CA C?A:B + 13394 LUT3 CA C?A:B + 13395 LUT3 CA C?A:B + 13396 LUT3 CA C?A:B + 13397 LUT3 CA C?A:B + 13398 LUT3 CA C?A:B + 13399 LUT3 CA C?A:B + 13400 LUT3 CA C?A:B + 13401 LUT3 CA C?A:B + 13402 LUT3 40 aBC + 13403 LUT3 40 aBC + 13404 LUT3 CA C?A:B + 13405 LUT3 CA C?A:B + 13406 LUT3 CA C?A:B + 13407 LUT3 CA C?A:B + 13408 LUT2 E /ab\ + 13409 LUT2 E /ab\ + 13410 LUT2 E /ab\ + 13411 LUT2 E /ab\ + 13412 LUT2 E /ab\ + 13413 LUT3 CA C?A:B + 13414 LUT3 40 aBC + 13415 LUT3 10 abC + 13416 LUT3 CA C?A:B + 13417 LUT3 CA C?A:B + 13418 LUT3 CA C?A:B + 13419 LUT3 CA C?A:B + 13420 LUT3 CA C?A:B + 13421 LUT2 E /ab\ + 13422 LUT3 AC c?A:B + 13423 LUT3 AC c?A:B + 13424 LUT3 AC c?A:B + 13425 LUT3 AC c?A:B + 13426 LUT3 AC c?A:B + 13427 LUT2 E /ab\ + 13428 LUT2 E /ab\ + 13429 LUT2 E /ab\ + 13430 LUT2 E /ab\ + 13431 LUT2 E /ab\ + 13432 LUT3 CA C?A:B + 13433 LUT2 E /ab\ + 13434 LUT3 AC c?A:B + 13435 LUT3 AC c?A:B + 13436 LUT3 AC c?A:B + 13437 LUT3 AC c?A:B + 13438 LUT3 AC c?A:B + 13439 LUT2 E /ab\ + 13440 LUT2 E /ab\ + 13441 LUT2 E /ab\ + 13442 LUT2 E /ab\ + 13443 LUT2 E /ab\ + 13444 LUT4 444F (aB)+(cd) + 13445 LUT4 FF10 (abC)+D + 13446 LUT2 4 aB + 13447 LUT2 8 AB + 13448 LUT2 8 AB + 13449 LUT2 8 AB + 13450 LUT3 CA C?A:B + 13451 LUT3 CA C?A:B + 13452 LUT3 CA C?A:B + 13453 LUT3 CA C?A:B + 13454 LUT3 CA C?A:B + 13455 LUT3 CA C?A:B + 13456 LUT2 E /ab\ + 13457 LUT2 E /ab\ + 13458 LUT2 E /ab\ + 13459 LUT2 E /ab\ + 13460 LUT2 E /ab\ + 13461 LUT2 E /ab\ + 13462 LUT2 1 ab + 13463 LUT2 8 AB + 13464 LUT3 01 abc + 13465 LUT4 0001 abcd + 13466 LUT2 E /ab\ + 13467 LUT4 00FE ((/ab\)+C)d + 13468 LUT3 CA C?A:B + 13469 LUT3 CA C?A:B + 13470 LUT3 CA C?A:B + 13471 LUT3 CA C?A:B + 13472 LUT3 CA C?A:B + 13473 LUT3 CA C?A:B + 13474 LUT2 E /ab\ + 13475 LUT2 E /ab\ + 13476 LUT2 E /ab\ + 13477 LUT2 E /ab\ + 13478 LUT2 E /ab\ + 13479 LUT2 E /ab\ + 13480 LUT3 CA C?A:B + 13481 LUT3 CA C?A:B + 13482 LUT3 CA C?A:B + 13483 LUT3 CA C?A:B + 13484 LUT3 CA C?A:B + 13485 LUT3 CA C?A:B + 13486 LUT2 E /ab\ + 13487 LUT2 E /ab\ + 13488 LUT2 E /ab\ + 13489 LUT2 E /ab\ + 13490 LUT2 E /ab\ + 13491 LUT2 E /ab\ + 13492 LUT3 CA C?A:B + 13493 LUT3 CA C?A:B + 13494 LUT3 CA C?A:B + 13495 LUT3 CA C?A:B + 13496 LUT3 CA C?A:B + 13497 LUT3 CA C?A:B + 13498 LUT2 E /ab\ + 13499 LUT2 E /ab\ + 13500 LUT2 E /ab\ + 13501 LUT2 E /ab\ + 13502 LUT2 E /ab\ + 13503 LUT2 E /ab\ + 13504 LUT4 FE00 ((/ab\)+C)D + 13505 LUT2 8 AB + 13506 LUT4 4000 aBCD + 13507 LUT4 0001 abcd + 13508 LUT3 CA C?A:B + 13509 LUT3 CA C?A:B + 13510 LUT3 CA C?A:B + 13511 LUT4 0C0A DC?A:B:0:0 + 13512 LUT4 0C0A DC?A:B:0:0 + 13513 LUT4 0C0A DC?A:B:0:0 + 13514 LUT4 0C0A DC?A:B:0:0 + 13515 LUT4 0C0A DC?A:B:0:0 + 13516 LUT4 0C0A DC?A:B:0:0 + 13517 LUT4 0C0A DC?A:B:0:0 + 13518 LUT4 0C0A DC?A:B:0:0 + 13519 LUT3 B0 C/aB\ + 13520 LUT2 8 AB + 13521 LUT3 0B c/aB\ + 13522 LUT2 4 aB + 13523 LUT4 4000 aBCD + 13524 LUT2 4 aB + 13525 LUT2 4 aB + 13526 LUT4 7000 CD/AB\ + 13527 LUT4 00BF ((/aB\)+c)d + 13528 LUT4 EF00 ((/ab\)+c)D + 13529 LUT3 2C BC?0:1:A:0 + 13530 LUT2 8 AB + 13531 LUT2 8 AB + 13532 LUT3 CA C?A:B + 13533 LUT3 CA C?A:B + 13534 LUT3 CA C?A:B + 13535 LUT3 CA C?A:B + 13536 LUT3 CA C?A:B + 13537 LUT2 8 AB + 13538 LUT3 CA C?A:B + 13539 LUT3 CA C?A:B + 13540 LUT3 CA C?A:B + 13541 LUT3 CA C?A:B + 13542 LUT3 CA C?A:B + 13543 LUT2 8 AB + 13544 LUT3 CA C?A:B + 13545 LUT3 CA C?A:B + 13546 LUT3 CA C?A:B + 13547 LUT3 CA C?A:B + 13548 LUT3 CA C?A:B + 13549 LUT2 8 AB + 13550 LUT3 CA C?A:B + 13551 LUT3 CA C?A:B + 13552 LUT3 CA C?A:B + 13553 LUT3 CA C?A:B + 13554 LUT3 CA C?A:B + 13555 LUT2 8 AB + 13556 LUT3 CA C?A:B + 13557 LUT3 CA C?A:B + 13558 LUT3 CA C?A:B + 13559 LUT3 CA C?A:B + 13560 LUT3 CA C?A:B + 13561 LUT2 8 AB + 13562 LUT3 CA C?A:B + 13563 LUT3 CA C?A:B + 13564 LUT3 CA C?A:B + 13565 LUT3 CA C?A:B + 13566 LUT3 CA C?A:B + 13567 LUT2 8 AB + 13568 LUT3 CA C?A:B + 13569 LUT3 CA C?A:B + 13570 LUT3 CA C?A:B + 13571 LUT3 CA C?A:B + 13572 LUT3 CA C?A:B + 13573 LUT2 8 AB + 13574 LUT3 CA C?A:B + 13575 LUT3 CA C?A:B + 13576 LUT3 CA C?A:B + 13577 LUT3 CA C?A:B + 13578 LUT3 CA C?A:B + 13579 LUT3 CA C?A:B + 13580 LUT3 10 abC + 13581 LUT3 80 ABC + 13582 LUT2 4 aB + 13583 LUT2 1 ab + 13584 LUT3 0B c/aB\ + 13585 LUT3 0E c/ab\ + 13586 LUT3 CA C?A:B + 13587 LUT3 CA C?A:B + 13588 LUT3 CA C?A:B + 13589 LUT3 CA C?A:B + 13590 LUT3 CA C?A:B + 13591 LUT3 10 abC + 13592 LUT3 40 aBC + 13593 LUT3 CA C?A:B + 13594 LUT3 CA C?A:B + 13595 LUT3 CA C?A:B + 13596 LUT3 CA C?A:B + 13597 LUT3 CA C?A:B + 13598 LUT3 10 abC + 13599 LUT3 40 aBC + 13600 LUT3 CA C?A:B + 13601 LUT3 CA C?A:B + 13602 LUT3 CA C?A:B + 13603 LUT3 CA C?A:B + 13604 LUT3 CA C?A:B + 13605 LUT3 10 abC + 13606 LUT3 10 abC + 13607 LUT3 CA C?A:B + 13608 LUT3 CA C?A:B + 13609 LUT3 CA C?A:B + 13610 LUT3 CA C?A:B + 13611 LUT3 CA C?A:B + 13612 LUT3 10 abC + 13613 LUT3 80 ABC + 13614 LUT2 8 AB + 13615 LUT3 CA C?A:B + 13616 LUT3 CA C?A:B + 13617 LUT3 CA C?A:B + 13618 LUT3 CA C?A:B + 13619 LUT3 CA C?A:B + 13620 LUT3 10 abC + 13621 LUT3 40 aBC + 13622 LUT3 CA C?A:B + 13623 LUT3 CA C?A:B + 13624 LUT3 CA C?A:B + 13625 LUT3 CA C?A:B + 13626 LUT3 CA C?A:B + 13627 LUT3 10 abC + 13628 LUT3 40 aBC + 13629 LUT3 CA C?A:B + 13630 LUT3 CA C?A:B + 13631 LUT3 CA C?A:B + 13632 LUT3 CA C?A:B + 13633 LUT3 CA C?A:B + 13634 LUT3 10 abC + 13635 LUT3 10 abC + 13636 LUT3 CA C?A:B + 13637 LUT3 CA C?A:B + 13638 LUT3 CA C?A:B + 13639 LUT3 CA C?A:B + 13640 LUT3 0D c/Ab\ + 13641 LUT4 FF10 (abC)+D + 13642 LUT3 10 abC + 13643 LUT4 F888 (AB)+(CD) + 13644 LUT4 B0BB /aB\(d+C) + 13645 LUT4 B0BB /aB\(d+C) + 13646 LUT4 B0BB /aB\(d+C) + 13647 LUT4 B0BB /aB\(d+C) + 13648 LUT4 F888 (AB)+(CD) + 13649 LUT4 F888 (AB)+(CD) + 13650 LUT4 F888 (AB)+(CD) + 13651 LUT4 B0BB /aB\(d+C) + 13652 LUT4 B0BB /aB\(d+C) + 13653 LUT4 F888 (AB)+(CD) + 13654 LUT4 B0BB /aB\(d+C) + 13655 LUT4 F888 (AB)+(CD) + 13656 LUT4 B0BB /aB\(d+C) + 13657 LUT4 F888 (AB)+(CD) + 13658 LUT4 B0BB /aB\(d+C) + 13659 LUT4 F888 (AB)+(CD) + 13660 LUT4 F888 (AB)+(CD) + 13661 LUT4 B0BB /aB\(d+C) + 13662 LUT4 B0BB /aB\(d+C) + 13663 LUT4 B0BB /aB\(d+C) + 13664 LUT4 F888 (AB)+(CD) + 13665 LUT4 B0BB /aB\(d+C) + 13666 LUT4 B0BB /aB\(d+C) + 13667 LUT4 F888 (AB)+(CD) + 13668 LUT4 B0BB /aB\(d+C) + 13669 LUT4 F888 (AB)+(CD) + 13670 LUT4 B0BB /aB\(d+C) + 13671 LUT4 B0BB /aB\(d+C) + 13672 LUT4 B0BB /aB\(d+C) + 13673 LUT4 F888 (AB)+(CD) + 13674 LUT4 B0BB /aB\(d+C) + 13675 LUT4 F888 (AB)+(CD) + 13676 LUT4 B0BB /aB\(d+C) + 13677 LUT4 B0BB /aB\(d+C) + 13678 LUT4 B0BB /aB\(d+C) + 13679 LUT4 B0BB /aB\(d+C) + 13680 LUT4 F888 (AB)+(CD) + 13681 LUT4 F888 (AB)+(CD) + 13682 LUT4 F888 (AB)+(CD) + 13683 LUT4 B0BB /aB\(d+C) + 13684 LUT4 B0BB /aB\(d+C) + 13685 LUT4 F888 (AB)+(CD) + 13686 LUT4 B0BB /aB\(d+C) + 13687 LUT4 F888 (AB)+(CD) + 13688 LUT4 B0BB /aB\(d+C) + 13689 LUT4 F888 (AB)+(CD) + 13690 LUT4 B0BB /aB\(d+C) + 13691 LUT4 B0BB /aB\(d+C) + 13692 LUT4 F888 (AB)+(CD) + 13693 LUT4 F888 (AB)+(CD) + 13694 LUT4 F888 (AB)+(CD) + 13695 LUT4 B0BB /aB\(d+C) + 13696 LUT4 F888 (AB)+(CD) + 13697 LUT4 F888 (AB)+(CD) + 13698 LUT4 F888 (AB)+(CD) + 13699 LUT4 F888 (AB)+(CD) + 13700 LUT4 B0BB /aB\(d+C) + 13701 LUT4 F888 (AB)+(CD) + 13702 LUT4 B0BB /aB\(d+C) + 13703 LUT4 F888 (AB)+(CD) + 13704 LUT4 F888 (AB)+(CD) + 13705 LUT4 B0BB /aB\(d+C) + 13706 LUT4 B0BB /aB\(d+C) + 13707 LUT3 F4 (aB)+C + 13708 LUT4 0C0A DC?A:B:0:0 + 13709 LUT2 4 aB + 13710 LUT2 8 AB + 13711 LUT2 8 AB + 13712 LUT4 0C0A DC?A:B:0:0 + 13713 LUT2 8 AB + 13714 LUT2 8 AB + 13715 LUT2 8 AB + 13716 LUT2 8 AB + 13717 LUT2 8 AB + 13718 LUT2 8 AB + 13719 LUT2 7 /AB\ + 13720 LUT2 E /ab\ + 13721 LUT2 1 ab + 13722 LUT4 004F ((aB)+c)d + 13723 LUT2 8 AB + 13724 LUT4 0001 abcd + 13725 LUT4 0001 abcd + 13726 LUT4 0E00 cD/ab\ + 13727 LUT3 40 aBC + 13728 LUT3 40 aBC + 13729 LUT3 40 aBC + 13730 LUT3 40 aBC + 13731 LUT3 40 aBC + 13732 LUT3 40 aBC + 13733 LUT3 40 aBC + 13734 LUT3 40 aBC + 13735 LUT2 4 aB + 13736 LUT3 CA C?A:B + 13737 LUT3 CA C?A:B + 13738 LUT3 0E c/ab\ + 13739 LUT4 030A DC?A:b:0:0 + 13740 LUT3 E0 C/ab\ + 13741 LUT3 35 c?b:a + 13742 LUT4 030A DC?A:b:0:0 + 13743 LUT3 35 c?b:a + 13744 LUT4 030A DC?A:b:0:0 + 13745 LUT3 35 c?b:a + 13746 LUT4 030A DC?A:b:0:0 + 13747 LUT3 35 c?b:a + 13748 LUT4 030A DC?A:b:0:0 + 13749 LUT3 35 c?b:a + 13750 LUT4 0C0A DC?A:B:0:0 + 13751 LUT2 8 AB + 13752 LUT4 1000 abCD + 13753 LUT4 0C0A DC?A:B:0:0 + 13754 LUT4 0C0A DC?A:B:0:0 + 13755 LUT4 0C0A DC?A:B:0:0 + 13756 LUT4 0C0A DC?A:B:0:0 + 13757 LUT4 0C0A DC?A:B:0:0 + 13758 LUT4 0C0A DC?A:B:0:0 + 13759 LUT4 0C0A DC?A:B:0:0 + 13760 LUT4 0C0A DC?A:B:0:0 + 13761 LUT2 8 AB + 13762 LUT4 0C0A DC?A:B:0:0 + 13763 LUT4 0C0A DC?A:B:0:0 + 13764 LUT4 0C0A DC?A:B:0:0 + 13765 LUT4 0C0A DC?A:B:0:0 + 13766 LUT4 0C0A DC?A:B:0:0 + 13767 LUT4 0C0A DC?A:B:0:0 + 13768 LUT4 0C0A DC?A:B:0:0 + 13769 LUT4 0C0A DC?A:B:0:0 + 13770 LUT2 8 AB + 13771 LUT2 4 aB + 13772 LUT4 0C0A DC?A:B:0:0 + 13773 LUT4 0C0A DC?A:B:0:0 + 13774 LUT4 0C0A DC?A:B:0:0 + 13775 LUT2 4 aB + 13776 LUT4 0C0A DC?A:B:0:0 + 13777 LUT4 0C0A DC?A:B:0:0 + 13778 LUT4 0C0A DC?A:B:0:0 + 13779 LUT4 0C0A DC?A:B:0:0 + 13780 LUT4 0C0A DC?A:B:0:0 + 13781 LUT4 0C0A DC?A:B:0:0 + 13782 LUT2 8 AB + 13783 LUT4 0C0A DC?A:B:0:0 + 13784 LUT4 0C0A DC?A:B:0:0 + 13785 LUT4 0C0A DC?A:B:0:0 + 13786 LUT4 0C0A DC?A:B:0:0 + 13787 LUT4 0C0A DC?A:B:0:0 + 13788 LUT4 0C0A DC?A:B:0:0 + 13789 LUT4 0C0A DC?A:B:0:0 + 13790 LUT4 0C0A DC?A:B:0:0 + 13791 LUT2 8 AB + 13792 LUT4 0C0A DC?A:B:0:0 + 13793 LUT4 0C0A DC?A:B:0:0 + 13794 LUT4 0C0A DC?A:B:0:0 + 13795 LUT2 4 aB + 13796 LUT4 0C0A DC?A:B:0:0 + 13797 LUT4 0C0A DC?A:B:0:0 + 13798 LUT4 0C0A DC?A:B:0:0 + 13799 LUT4 0C0A DC?A:B:0:0 + 13800 LUT4 0C0A DC?A:B:0:0 + 13801 LUT2 8 AB + 13802 LUT4 0C0A DC?A:B:0:0 + 13803 LUT4 0C0A DC?A:B:0:0 + 13804 LUT4 0C0A DC?A:B:0:0 + 13805 LUT4 0C0A DC?A:B:0:0 + 13806 LUT4 0C0A DC?A:B:0:0 + 13807 LUT4 0C0A DC?A:B:0:0 + 13808 LUT4 0C0A DC?A:B:0:0 + 13809 LUT4 0C0A DC?A:B:0:0 + 13810 LUT2 8 AB + 13811 LUT4 0C0A DC?A:B:0:0 + 13812 LUT4 0C0A DC?A:B:0:0 + 13813 LUT4 0C0A DC?A:B:0:0 + 13814 LUT4 0C0A DC?A:B:0:0 + 13815 LUT4 0C0A DC?A:B:0:0 + 13816 LUT4 0C0A DC?A:B:0:0 + 13817 LUT4 0C0A DC?A:B:0:0 + 13818 LUT4 0C0A DC?A:B:0:0 + 13819 LUT4 030A DC?A:b:0:0 + 13820 LUT4 000B cd/aB\ + 13821 LUT4 030A DC?A:b:0:0 + 13822 LUT4 10FF (abC)+d + 13823 LUT3 35 c?b:a + 13824 LUT3 0E c/ab\ + 13825 LUT2 7 /AB\ + 13826 LUT4 0700 cD/AB\ + 13827 LUT4 0700 cD/AB\ + 13828 LUT4 0777 /AB\(d+c) + 13829 LUT4 1000 abCD + 13830 LUT4 0100 abcD + 13831 LUT2 8 AB + 13832 LUT4 0100 abcD + 13833 LUT4 0100 abcD + 13834 LUT4 7000 CD/AB\ + 13835 LUT4 0777 /AB\(d+c) + 13836 LUT4 D3FE BD?/ac\:1:/AC\:C + 13837 LUT4 1000 abCD + 13838 LUT4 8FFF (AB)+c+d + 13839 LUT4 1000 abCD + 13840 LUT2 4 aB + 13841 LUT2 8 AB + 13842 LUT2 8 AB + 13843 LUT4 0777 /AB\(d+c) + 13844 LUT4 0777 /AB\(d+c) + 13845 LUT4 8FFF (AB)+c+d + 13846 LUT4 7000 CD/AB\ + 13847 LUT4 0777 /AB\(d+c) + 13848 LUT3 70 C/AB\ + 13849 LUT4 0777 /AB\(d+c) + 13850 LUT4 7FFF /AB\+c+d + 13851 LUT3 70 C/AB\ + 13852 LUT4 0777 /AB\(d+c) + 13853 LUT4 0777 /AB\(d+c) + 13854 LUT4 0777 /AB\(d+c) + 13855 LUT4 7FFF /AB\+c+d + 13856 LUT3 70 C/AB\ + 13857 LUT4 0777 /AB\(d+c) + 13858 LUT4 0777 /AB\(d+c) + 13859 LUT4 0777 /AB\(d+c) + 13860 LUT4 8FFF (AB)+c+d + 13861 LUT4 1000 abCD + 13862 LUT2 8 AB + 13863 LUT2 8 AB + 13864 LUT4 0777 /AB\(d+c) + 13865 LUT4 0777 /AB\(d+c) + 13866 LUT4 7FFF /AB\+c+d + 13867 LUT3 70 C/AB\ + 13868 LUT4 0777 /AB\(d+c) + 13869 LUT4 0777 /AB\(d+c) + 13870 LUT4 0777 /AB\(d+c) + 13871 LUT4 8FFF (AB)+c+d + 13872 LUT4 7000 CD/AB\ + 13873 LUT2 1 ab + 13874 LUT4 8000 ABCD + 13875 LUT4 0777 /AB\(d+c) + 13876 LUT4 7000 CD/AB\ + 13877 LUT4 0777 /AB\(d+c) + 13878 LUT4 7FFF /AB\+c+d + 13879 LUT3 70 C/AB\ + 13880 LUT4 0777 /AB\(d+c) + 13881 LUT4 0777 /AB\(d+c) + 13882 LUT4 0777 /AB\(d+c) + 13883 LUT3 7F /AB\+c + 13884 LUT4 7000 CD/AB\ + 13885 LUT4 0777 /AB\(d+c) + 13886 LUT4 0777 /AB\(d+c) + 13887 LUT4 0777 /AB\(d+c) + 13888 LUT4 7FFF /AB\+c+d + 13889 LUT3 70 C/AB\ + 13890 LUT4 0777 /AB\(d+c) + 13891 LUT4 0777 /AB\(d+c) + 13892 LUT4 0777 /AB\(d+c) + 13893 LUT4 7FFF /AB\+c+d + 13894 LUT3 70 C/AB\ + 13895 LUT4 0777 /AB\(d+c) + 13896 LUT4 0777 /AB\(d+c) + 13897 LUT4 0777 /AB\(d+c) + 13898 LUT4 8FFF (AB)+c+d + 13899 LUT4 7000 CD/AB\ + 13900 LUT4 0777 /AB\(d+c) + 13901 LUT4 7000 CD/AB\ + 13902 LUT4 0777 /AB\(d+c) + 13903 LUT4 8FFF (AB)+c+d + 13904 LUT4 7000 CD/AB\ + 13905 LUT4 0777 /AB\(d+c) + 13906 LUT4 7000 CD/AB\ + 13907 LUT4 0777 /AB\(d+c) + 13908 LUT4 8FFF (AB)+c+d + 13909 LUT4 0700 cD/AB\ + 13910 LUT4 0777 /AB\(d+c) + 13911 LUT4 7000 CD/AB\ + 13912 LUT4 0777 /AB\(d+c) + 13913 LUT4 8FFF (AB)+c+d + 13914 LUT4 7000 CD/AB\ + 13915 LUT4 0777 /AB\(d+c) + 13916 LUT4 7000 CD/AB\ + 13917 LUT4 0777 /AB\(d+c) + 13918 LUT3 40 aBC + 13919 LUT2 7 /AB\ + 13920 LUT4 7000 CD/AB\ + 13921 LUT4 0700 cD/AB\ + 13922 LUT4 0777 /AB\(d+c) + 13923 LUT4 0777 /AB\(d+c) + 13924 LUT2 7 /AB\ + 13925 LUT4 7000 CD/AB\ + 13926 LUT4 0777 /AB\(d+c) + 13927 LUT4 0777 /AB\(d+c) + 13928 LUT4 0700 cD/AB\ + 13929 LUT4 7FFF /AB\+c+d + 13930 LUT4 0777 /AB\(d+c) + 13931 LUT4 0777 /AB\(d+c) + 13932 LUT4 0777 /AB\(d+c) + 13933 LUT3 7F /AB\+c + 13934 LUT3 80 ABC + 13935 LUT4 0777 /AB\(d+c) + 13936 LUT4 0777 /AB\(d+c) + 13937 LUT4 0777 /AB\(d+c) + 13938 LUT2 7 /AB\ + 13939 LUT4 7000 CD/AB\ + 13940 LUT4 0777 /AB\(d+c) + 13941 LUT4 0777 /AB\(d+c) + 13942 LUT4 0700 cD/AB\ + 13943 LUT4 7FFF /AB\+c+d + 13944 LUT4 0700 cD/AB\ + 13945 LUT4 0777 /AB\(d+c) + 13946 LUT2 8 AB + 13947 LUT4 0777 /AB\(d+c) + 13948 LUT2 7 /AB\ + 13949 LUT4 7000 CD/AB\ + 13950 LUT4 0777 /AB\(d+c) + 13951 LUT4 0777 /AB\(d+c) + 13952 LUT4 0700 cD/AB\ + 13953 LUT3 7F /AB\+c + 13954 LUT3 80 ABC + 13955 LUT4 0777 /AB\(d+c) + 13956 LUT4 0777 /AB\(d+c) + 13957 LUT4 0777 /AB\(d+c) + 13958 LUT4 7FFF /AB\+c+d + 13959 LUT3 70 C/AB\ + 13960 LUT4 0777 /AB\(d+c) + 13961 LUT4 0777 /AB\(d+c) + 13962 LUT4 0777 /AB\(d+c) + 13963 LUT4 8FFF (AB)+c+d + 13964 LUT4 7000 CD/AB\ + 13965 LUT4 7000 CD/AB\ + 13966 LUT4 0777 /AB\(d+c) + 13967 LUT4 0777 /AB\(d+c) + 13968 LUT4 7FFF /AB\+c+d + 13969 LUT3 70 C/AB\ + 13970 LUT4 0777 /AB\(d+c) + 13971 LUT4 0777 /AB\(d+c) + 13972 LUT4 0777 /AB\(d+c) + 13973 LUT3 7F /AB\+c + 13974 LUT3 70 C/AB\ + 13975 LUT4 0777 /AB\(d+c) + 13976 LUT4 0700 cD/AB\ + 13977 LUT2 8 AB + 13978 LUT4 0777 /AB\(d+c) + 13979 LUT4 7FFF /AB\+c+d + 13980 LUT3 70 C/AB\ + 13981 LUT4 0777 /AB\(d+c) + 13982 LUT4 0777 /AB\(d+c) + 13983 LUT4 0777 /AB\(d+c) + 13984 LUT2 7 /AB\ + 13985 LUT4 7000 CD/AB\ + 13986 LUT4 0700 cD/AB\ + 13987 LUT2 8 AB + 13988 LUT4 0777 /AB\(d+c) + 13989 LUT4 0777 /AB\(d+c) + 13990 LUT4 7FFF /AB\+c+d + 13991 LUT3 70 C/AB\ + 13992 LUT4 0777 /AB\(d+c) + 13993 LUT4 0777 /AB\(d+c) + 13994 LUT4 0777 /AB\(d+c) + 13995 LUT4 7FFF /AB\+c+d + 13996 LUT3 70 C/AB\ + 13997 LUT4 0777 /AB\(d+c) + 13998 LUT4 0777 /AB\(d+c) + 13999 LUT4 0777 /AB\(d+c) + 14000 LUT2 1 ab + 14001 LUT4 FCF5 DC?a:B:1:1 + 14002 LUT3 E0 C/ab\ + 14003 LUT4 0007 cd/AB\ + 14004 LUT4 00FE ((/ab\)+C)d + 14005 LUT2 1 ab + 14006 LUT2 4 aB + 14007 LUT4 0700 cD/AB\ + 14008 LUT3 E0 C/ab\ + 14009 LUT4 007D AD?1:B^C:0:0 + 14010 LUT2 4 aB + 14011 LUT4 0100 abcD + 14012 LUT3 40 aBC + 14013 LUT3 10 abC + 14014 LUT4 4000 aBCD + 14015 LUT3 70 C/AB\ + 14016 LUT4 030A DC?A:b:0:0 + 14017 LUT3 70 C/AB\ + 14018 LUT4 0C0B BC?d:/ad\:0:0 + 14019 LUT4 030A DC?A:b:0:0 + 14020 LUT4 0D00 cD/Ab\ + 14021 LUT4 FCFA DC?A:B:1:1 + 14022 LUT4 1000 abCD + 14023 LUT4 FCFA DC?A:B:1:1 + 14024 LUT4 0C0A DC?A:B:0:0 + 14025 LUT4 00F4 ((aB)+C)d + 14026 LUT4 4F00 ((aB)+c)D + 14027 LUT4 7F00 ((/AB\)+c)D + 14028 LUT4 BF00 ((/aB\)+c)D + 14029 LUT4 FCFA DC?A:B:1:1 + 14030 LUT4 FCFA DC?A:B:1:1 + 14031 LUT4 FCFA DC?A:B:1:1 + 14032 LUT4 FCFA DC?A:B:1:1 + 14033 LUT4 0C0A DC?A:B:0:0 + 14034 LUT4 FCFA DC?A:B:1:1 + 14035 LUT4 0C0A DC?A:B:0:0 + 14036 LUT4 FCFA DC?A:B:1:1 + 14037 LUT4 0C0A DC?A:B:0:0 + 14038 LUT4 FCFA DC?A:B:1:1 + 14039 LUT4 FCFA DC?A:B:1:1 + 14040 LUT4 0C0A DC?A:B:0:0 + 14041 LUT4 FCFA DC?A:B:1:1 + 14042 LUT4 FCFA DC?A:B:1:1 + 14043 LUT4 0C0A DC?A:B:0:0 + 14044 LUT4 FCFA DC?A:B:1:1 + 14045 LUT4 FCFA DC?A:B:1:1 + 14046 LUT4 FCFA DC?A:B:1:1 + 14047 LUT4 FCFA DC?A:B:1:1 + 14048 LUT4 FCFA DC?A:B:1:1 + 14049 LUT4 0C0A DC?A:B:0:0 + 14050 LUT4 FCFA DC?A:B:1:1 + 14051 LUT4 FCFA DC?A:B:1:1 + 14052 LUT2 4 aB + 14053 LUT2 4 aB + 14054 LUT4 FCFA DC?A:B:1:1 + 14055 LUT4 0C0A DC?A:B:0:0 + 14056 LUT4 FCFA DC?A:B:1:1 + 14057 LUT4 FCFA DC?A:B:1:1 + 14058 LUT4 FCFA DC?A:B:1:1 + 14059 LUT4 FCFA DC?A:B:1:1 + 14060 LUT4 FFF2 (Ab)+C+D + 14061 LUT3 01 abc + 14062 LUT4 00BF ((/aB\)+c)d + 14063 LUT4 4000 aBCD + 14064 LUT4 030A DC?A:b:0:0 + 14065 LUT3 35 c?b:a + 14066 LUT4 030A DC?A:b:0:0 + 14067 LUT3 35 c?b:a + 14068 LUT2 4 aB + 14069 LUT3 10 abC + 14070 LUT4 00F4 ((aB)+C)d + 14071 LUT3 0D c/Ab\ + 14072 LUT4 0A0C DC?B:A:0:0 + 14073 LUT3 80 ABC + 14074 LUT3 53 C?b:a + 14075 LUT3 0B c/aB\ + 14076 LUT3 10 abC + 14077 LUT2 1 ab + 14078 LUT3 5C c?a:B + 14079 LUT3 5C c?a:B + 14080 LUT3 CA C?A:B + 14081 LUT3 53 C?b:a + 14082 LUT4 EF00 ((/ab\)+c)D + 14083 LUT3 5C c?a:B + 14084 LUT3 5C c?a:B + 14085 LUT3 CA C?A:B + 14086 LUT3 35 c?b:a + 14087 LUT2 8 AB + 14088 LUT2 8 AB + 14089 LUT2 8 AB + 14090 LUT2 8 AB + 14091 LUT2 8 AB + 14092 LUT2 8 AB + 14093 LUT2 8 AB + 14094 LUT2 8 AB + 14095 LUT2 8 AB + 14096 LUT2 8 AB + 14097 LUT2 8 AB + 14098 LUT2 8 AB + 14099 LUT2 8 AB + 14100 LUT2 8 AB + 14101 LUT2 8 AB + 14102 LUT2 8 AB + 14103 LUT4 B0BB /aB\(d+C) + 14104 LUT4 B0BB /aB\(d+C) + 14105 LUT4 B0BB /aB\(d+C) + 14106 LUT4 B0BB /aB\(d+C) + 14107 LUT4 BEFF A+d+(B^C) + 14108 LUT2 8 AB + 14109 LUT2 8 AB + 14110 LUT4 BE00 AD?0:0:B^C:1 + 14111 LUT4 8000 ABCD + 14112 LUT4 F800 ((AB)+C)D + 14113 LUT4 00F1 ((ab)+C)d + 14114 LUT3 41 (B^c)a + 14115 LUT3 80 ABC + 14116 LUT2 8 AB + 14117 LUT2 8 AB + 14118 LUT2 8 AB + 14119 LUT2 8 AB + 14120 LUT2 8 AB + 14121 LUT2 8 AB + 14122 LUT2 8 AB + 14123 LUT2 8 AB + 14124 LUT2 4 aB + 14125 LUT4 8000 ABCD + 14126 LUT3 80 ABC + 14127 LUT4 8000 ABCD + 14128 LUT4 8000 ABCD + 14129 LUT4 8000 ABCD + 14130 LUT4 8000 ABCD + 14131 LUT4 8000 ABCD + 14132 LUT4 8000 ABCD + 14133 LUT4 8000 ABCD + 14134 LUT4 8000 ABCD + 14135 LUT3 80 ABC + 14136 LUT4 770F D?c:/AB\ + 14137 LUT3 40 aBC + 14138 LUT4 0001 abcd + 14139 LUT2 4 aB + 14140 LUT3 41 (B^c)a + 14141 LUT4 770F D?c:/AB\ + 14142 LUT3 40 aBC + 14143 LUT2 4 aB + 14144 LUT2 9 a^B + 14145 LUT4 770F D?c:/AB\ + 14146 LUT3 40 aBC + 14147 LUT2 4 aB + 14148 LUT2 6 A^B + 14149 LUT4 770F D?c:/AB\ + 14150 LUT3 40 aBC + 14151 LUT2 4 aB + 14152 LUT3 80 ABC + 14153 LUT4 00BE AD?B^C:1:0:0 + 14154 LUT3 41 (B^c)a + 14155 LUT4 770F D?c:/AB\ + 14156 LUT3 40 aBC + 14157 LUT2 4 aB + 14158 LUT4 770F D?c:/AB\ + 14159 LUT3 40 aBC + 14160 LUT2 4 aB + 14161 LUT3 10 abC + 14162 LUT4 00BE AD?B^C:1:0:0 + 14163 LUT3 41 (B^c)a + 14164 LUT2 8 AB + 14165 LUT3 80 ABC + 14166 LUT2 8 AB + 14167 LUT2 8 AB + 14168 LUT4 770F D?c:/AB\ + 14169 LUT3 40 aBC + 14170 LUT2 4 aB + 14171 LUT4 770F D?c:/AB\ + 14172 LUT3 40 aBC + 14173 LUT2 4 aB + 14174 LUT3 41 (B^c)a + 14175 LUT4 770F D?c:/AB\ + 14176 LUT3 40 aBC + 14177 LUT2 4 aB + 14178 LUT2 8 AB + 14179 LUT3 41 (B^c)a + 14180 LUT4 770F D?c:/AB\ + 14181 LUT3 40 aBC + 14182 LUT2 4 aB + 14183 LUT4 00BE AD?B^C:1:0:0 + 14184 LUT4 7007 (c^D)/AB\ + 14185 LUT4 770F D?c:/AB\ + 14186 LUT3 40 aBC + 14187 LUT2 4 aB + 14188 LUT4 770F D?c:/AB\ + 14189 LUT3 40 aBC + 14190 LUT2 4 aB + 14191 LUT4 8000 ABCD + 14192 LUT4 00BE AD?B^C:1:0:0 + 14193 LUT4 7007 (c^D)/AB\ + 14194 LUT3 80 ABC + 14195 LUT2 8 AB + 14196 LUT2 8 AB + 14197 LUT2 8 AB + 14198 LUT4 770F D?c:/AB\ + 14199 LUT3 40 aBC + 14200 LUT2 4 aB + 14201 LUT4 770F D?c:/AB\ + 14202 LUT3 40 aBC + 14203 LUT2 4 aB + 14204 LUT3 40 aBC + 14205 LUT2 4 aB + 14206 LUT4 F800 ((AB)+C)D + 14207 LUT3 10 abC + 14208 LUT3 40 aBC + 14209 LUT2 4 aB + 14210 LUT2 4 aB + 14211 LUT2 8 AB + 14212 LUT2 8 AB + 14213 LUT2 8 AB + 14214 LUT4 AB0E AC?B^D:1:0:D + 14215 LUT3 80 ABC + 14216 LUT2 9 a^B + 14217 LUT4 770F D?c:/AB\ + 14218 LUT2 4 aB + 14219 LUT2 4 aB + 14220 LUT4 770F D?c:/AB\ + 14221 LUT2 4 aB + 14222 LUT2 4 aB + 14223 LUT4 AB0E AC?B^D:1:0:D + 14224 LUT4 770F D?c:/AB\ + 14225 LUT2 4 aB + 14226 LUT2 4 aB + 14227 LUT2 9 a^B + 14228 LUT4 770F D?c:/AB\ + 14229 LUT3 40 aBC + 14230 LUT2 4 aB + 14231 LUT3 80 ABC + 14232 LUT4 00BE AD?B^C:1:0:0 + 14233 LUT3 41 (B^c)a + 14234 LUT4 770F D?c:/AB\ + 14235 LUT3 40 aBC + 14236 LUT2 4 aB + 14237 LUT3 80 ABC + 14238 LUT4 770F D?c:/AB\ + 14239 LUT3 40 aBC + 14240 LUT2 4 aB + 14241 LUT4 00BE AD?B^C:1:0:0 + 14242 LUT4 7007 (c^D)/AB\ + 14243 LUT4 770F D?c:/AB\ + 14244 LUT3 40 aBC + 14245 LUT2 4 aB + 14246 LUT4 770F D?c:/AB\ + 14247 LUT3 40 aBC + 14248 LUT2 4 aB + 14249 LUT3 10 abC + 14250 LUT4 AB0E AC?B^D:1:0:D + 14251 LUT2 9 a^B + 14252 LUT4 770F D?c:/AB\ + 14253 LUT3 40 aBC + 14254 LUT2 4 aB + 14255 LUT4 770F D?c:/AB\ + 14256 LUT3 40 aBC + 14257 LUT2 4 aB + 14258 LUT4 7007 (c^D)/AB\ + 14259 LUT4 770F D?c:/AB\ + 14260 LUT3 40 aBC + 14261 LUT2 4 aB + 14262 LUT3 41 (B^c)a + 14263 LUT4 770F D?c:/AB\ + 14264 LUT3 40 aBC + 14265 LUT2 4 aB + 14266 LUT4 770F D?c:/AB\ + 14267 LUT2 4 aB + 14268 LUT2 4 aB + 14269 LUT4 BE00 AD?0:0:B^C:1 + 14270 LUT4 770F D?c:/AB\ + 14271 LUT2 4 aB + 14272 LUT2 4 aB + 14273 LUT4 BEA0 AD?0:C:B^C:1 + 14274 LUT2 6 A^B + 14275 LUT4 770F D?c:/AB\ + 14276 LUT2 4 aB + 14277 LUT2 4 aB + 14278 LUT4 770F D?c:/AB\ + 14279 LUT2 4 aB + 14280 LUT2 4 aB + 14281 LUT4 8000 ABCD + 14282 LUT4 00F8 ((AB)+C)d + 14283 LUT4 7007 (c^D)/AB\ + 14284 LUT2 8 AB + 14285 LUT2 8 AB + 14286 LUT3 80 ABC + 14287 LUT2 8 AB + 14288 LUT2 8 AB + 14289 LUT2 8 AB + 14290 LUT2 8 AB + 14291 LUT3 70 C/AB\ + 14292 LUT3 80 ABC + 14293 LUT3 80 ABC + 14294 LUT2 8 AB + 14295 LUT4 8000 ABCD + 14296 LUT4 8000 ABCD + 14297 LUT4 8000 ABCD + 14298 LUT4 8000 ABCD + 14299 LUT4 8000 ABCD + 14300 LUT4 8000 ABCD + 14301 LUT2 8 AB + 14302 LUT4 770F D?c:/AB\ + 14303 LUT2 8 AB + 14304 LUT3 80 ABC + 14305 LUT3 80 ABC + 14306 LUT2 6 A^B + 14307 LUT4 770F D?c:/AB\ + 14308 LUT3 10 abC + 14309 LUT3 41 (B^c)a + 14310 LUT4 770F D?c:/AB\ + 14311 LUT4 7007 (c^D)/AB\ + 14312 LUT4 770F D?c:/AB\ + 14313 LUT4 F800 ((AB)+C)D + 14314 LUT3 40 aBC + 14315 LUT2 1 ab + 14316 LUT4 7007 (c^D)/AB\ + 14317 LUT2 8 AB + 14318 LUT2 8 AB + 14319 LUT2 8 AB + 14320 LUT3 80 ABC + 14321 LUT4 770F D?c:/AB\ + 14322 LUT4 7007 (c^D)/AB\ + 14323 LUT2 8 AB + 14324 LUT2 8 AB + 14325 LUT4 770F D?c:/AB\ + 14326 LUT2 8 AB + 14327 LUT4 BEA0 AD?0:C:B^C:1 + 14328 LUT2 6 A^B + 14329 LUT4 770F D?c:/AB\ + 14330 LUT4 770F D?c:/AB\ + 14331 LUT4 AB0E AC?B^D:1:0:D + 14332 LUT4 770F D?c:/AB\ + 14333 LUT2 9 a^B + 14334 LUT4 770F D?c:/AB\ + 14335 LUT3 41 (B^c)a + 14336 LUT3 80 ABC + 14337 LUT4 770F D?c:/AB\ + 14338 LUT4 BE00 AD?0:0:B^C:1 + 14339 LUT4 00BE AD?B^C:1:0:0 + 14340 LUT4 0EAB AC?b^D:1:0:d + 14341 LUT2 9 a^B + 14342 LUT4 770F D?c:/AB\ + 14343 LUT4 770F D?c:/AB\ + 14344 LUT4 770F D?c:/AB\ + 14345 LUT4 770F D?c:/AB\ + 14346 LUT4 770F D?c:/AB\ + 14347 LUT3 01 abc + 14348 LUT3 41 (B^c)a + 14349 LUT4 8000 ABCD + 14350 LUT3 80 ABC + 14351 LUT4 8000 ABCD + 14352 LUT4 8000 ABCD + 14353 LUT4 770F D?c:/AB\ + 14354 LUT4 7007 (c^D)/AB\ + 14355 LUT4 770F D?c:/AB\ + 14356 LUT3 41 (B^c)a + 14357 LUT4 770F D?c:/AB\ + 14358 LUT2 6 A^B + 14359 LUT4 770F D?c:/AB\ + 14360 LUT2 8 AB + 14361 LUT4 00BE AD?B^C:1:0:0 + 14362 LUT4 7007 (c^D)/AB\ + 14363 LUT4 770F D?c:/AB\ + 14364 LUT4 770F D?c:/AB\ + 14365 LUT4 00BE AD?B^C:1:0:0 + 14366 LUT3 41 (B^c)a + 14367 LUT4 770F D?c:/AB\ + 14368 LUT4 770F D?c:/AB\ + 14369 LUT4 00BE AD?B^C:1:0:0 + 14370 LUT3 41 (B^c)a + 14371 LUT4 770F D?c:/AB\ + 14372 LUT2 8 AB + 14373 LUT2 8 AB + 14374 LUT4 770F D?c:/AB\ + 14375 LUT4 00BE AD?B^C:1:0:0 + 14376 LUT4 8000 ABCD + 14377 LUT3 41 (B^c)a + 14378 LUT4 770F D?c:/AB\ + 14379 LUT4 770F D?c:/AB\ + 14380 LUT4 00BE AD?B^C:1:0:0 + 14381 LUT4 7007 (c^D)/AB\ + 14382 LUT4 770F D?c:/AB\ + 14383 LUT4 770F D?c:/AB\ + 14384 LUT4 00BE AD?B^C:1:0:0 + 14385 LUT4 770F D?c:/AB\ + 14386 LUT3 41 (B^c)a + 14387 LUT4 770F D?c:/AB\ + 14388 LUT3 10 abC + 14389 LUT2 6 A^B + 14390 LUT4 770F D?c:/AB\ + 14391 LUT4 770F D?c:/AB\ + 14392 LUT4 7F00 ((/AB\)+c)D + 14393 LUT3 80 ABC + 14394 LUT4 8000 ABCD + 14395 LUT4 8000 ABCD + 14396 LUT4 8000 ABCD + 14397 LUT4 8000 ABCD + 14398 LUT3 80 ABC + 14399 LUT4 8000 ABCD + 14400 LUT4 8000 ABCD + 14401 LUT3 80 ABC + 14402 LUT4 8000 ABCD + 14403 LUT3 80 ABC + 14404 LUT3 41 (B^c)a + 14405 LUT4 770F D?c:/AB\ + 14406 LUT3 80 ABC + 14407 LUT2 8 AB + 14408 LUT4 7007 (c^D)/AB\ + 14409 LUT4 770F D?c:/AB\ + 14410 LUT4 0EAB AC?b^D:1:0:d + 14411 LUT2 9 a^B + 14412 LUT4 770F D?c:/AB\ + 14413 LUT4 770F D?c:/AB\ + 14414 LUT2 8 AB + 14415 LUT2 6 A^B + 14416 LUT4 770F D?c:/AB\ + 14417 LUT2 8 AB + 14418 LUT3 80 ABC + 14419 LUT3 80 ABC + 14420 LUT2 8 AB + 14421 LUT4 00BE AD?B^C:1:0:0 + 14422 LUT4 7007 (c^D)/AB\ + 14423 LUT4 770F D?c:/AB\ + 14424 LUT2 8 AB + 14425 LUT4 770F D?c:/AB\ + 14426 LUT4 7007 (c^D)/AB\ + 14427 LUT4 770F D?c:/AB\ + 14428 LUT4 8000 ABCD + 14429 LUT3 80 ABC + 14430 LUT3 41 (B^c)a + 14431 LUT4 770F D?c:/AB\ + 14432 LUT3 10 abC + 14433 LUT4 00BE AD?B^C:1:0:0 + 14434 LUT4 7007 (c^D)/AB\ + 14435 LUT4 770F D?c:/AB\ + 14436 LUT2 8 AB + 14437 LUT3 80 ABC + 14438 LUT2 8 AB + 14439 LUT4 770F D?c:/AB\ + 14440 LUT3 41 (B^c)a + 14441 LUT3 80 ABC + 14442 LUT4 8000 ABCD + 14443 LUT2 8 AB + 14444 LUT2 8 AB + 14445 LUT4 770F D?c:/AB\ + 14446 LUT3 41 (B^c)a + 14447 LUT4 770F D?c:/AB\ + 14448 LUT2 8 AB + 14449 LUT4 00BE AD?B^C:1:0:0 + 14450 LUT3 41 (B^c)a + 14451 LUT4 770F D?c:/AB\ + 14452 LUT4 770F D?c:/AB\ + 14453 LUT2 8 AB + 14454 LUT3 41 (B^c)a + 14455 LUT4 770F D?c:/AB\ + 14456 LUT4 8000 ABCD + 14457 LUT4 770F D?c:/AB\ + 14458 LUT4 00BE AD?B^C:1:0:0 + 14459 LUT4 7007 (c^D)/AB\ + 14460 LUT4 770F D?c:/AB\ + 14461 LUT4 770F D?c:/AB\ + 14462 LUT4 7007 (c^D)/AB\ + 14463 LUT4 770F D?c:/AB\ + 14464 LUT2 6 A^B + 14465 LUT4 770F D?c:/AB\ + 14466 LUT3 10 abC + 14467 LUT4 7007 (c^D)/AB\ + 14468 LUT3 53 C?b:a + 14469 LUT4 7007 (c^D)/AB\ + 14470 LUT4 770F D?c:/AB\ + 14471 LUT4 F800 ((AB)+C)D + 14472 LUT3 40 aBC + 14473 LUT4 000E cd/ab\ + 14474 LUT2 6 A^B + 14475 LUT4 770F D?c:/AB\ + 14476 LUT4 7007 (c^D)/AB\ + 14477 LUT4 770F D?c:/AB\ + 14478 LUT3 80 ABC + 14479 LUT3 41 (B^c)a + 14480 LUT4 770F D?c:/AB\ + 14481 LUT4 7007 (c^D)/AB\ + 14482 LUT4 770F D?c:/AB\ + 14483 LUT4 770F D?c:/AB\ + 14484 LUT4 BEA0 AD?0:C:B^C:1 + 14485 LUT2 6 A^B + 14486 LUT4 770F D?c:/AB\ + 14487 LUT4 770F D?c:/AB\ + 14488 LUT3 80 ABC + 14489 LUT4 00BE AD?B^C:1:0:0 + 14490 LUT2 8 AB + 14491 LUT2 8 AB + 14492 LUT2 8 AB + 14493 LUT2 8 AB + 14494 LUT2 8 AB + 14495 LUT2 8 AB + 14496 LUT2 8 AB + 14497 LUT3 70 C/AB\ + 14498 LUT4 8000 ABCD + 14499 LUT3 80 ABC + 14500 LUT3 80 ABC + 14501 LUT4 8000 ABCD + 14502 LUT4 8000 ABCD + 14503 LUT4 8000 ABCD + 14504 LUT4 8000 ABCD + 14505 LUT4 8000 ABCD + 14506 LUT4 8000 ABCD + 14507 LUT3 80 ABC + 14508 LUT4 8000 ABCD + 14509 LUT3 41 (B^c)a + 14510 LUT4 770F D?c:/AB\ + 14511 LUT2 8 AB + 14512 LUT4 770F D?c:/AB\ + 14513 LUT3 10 abC + 14514 LUT4 00BE AD?B^C:1:0:0 + 14515 LUT3 41 (B^c)a + 14516 LUT2 8 AB + 14517 LUT3 80 ABC + 14518 LUT2 8 AB + 14519 LUT2 8 AB + 14520 LUT4 770F D?c:/AB\ + 14521 LUT4 770F D?c:/AB\ + 14522 LUT3 41 (B^c)a + 14523 LUT2 8 AB + 14524 LUT2 8 AB + 14525 LUT4 770F D?c:/AB\ + 14526 LUT3 41 (B^c)a + 14527 LUT4 770F D?c:/AB\ + 14528 LUT4 00BE AD?B^C:1:0:0 + 14529 LUT4 7007 (c^D)/AB\ + 14530 LUT4 770F D?c:/AB\ + 14531 LUT4 770F D?c:/AB\ + 14532 LUT2 8 AB + 14533 LUT2 8 AB + 14534 LUT2 8 AB + 14535 LUT3 41 (B^c)a + 14536 LUT3 80 ABC + 14537 LUT4 770F D?c:/AB\ + 14538 LUT4 770F D?c:/AB\ + 14539 LUT3 01 abc + 14540 LUT3 41 (B^c)a + 14541 LUT4 770F D?c:/AB\ + 14542 LUT3 41 (B^c)a + 14543 LUT2 8 AB + 14544 LUT4 770F D?c:/AB\ + 14545 LUT3 41 (B^c)a + 14546 LUT4 770F D?c:/AB\ + 14547 LUT4 00BE AD?B^C:1:0:0 + 14548 LUT3 80 ABC + 14549 LUT4 7007 (c^D)/AB\ + 14550 LUT4 770F D?c:/AB\ + 14551 LUT4 770F D?c:/AB\ + 14552 LUT4 BEA0 AD?0:C:B^C:1 + 14553 LUT2 8 AB + 14554 LUT2 8 AB + 14555 LUT2 8 AB + 14556 LUT2 8 AB + 14557 LUT2 6 A^B + 14558 LUT4 770F D?c:/AB\ + 14559 LUT4 770F D?c:/AB\ + 14560 LUT2 9 a^B + 14561 LUT4 770F D?c:/AB\ + 14562 LUT4 D000 CD/Ab\ + 14563 LUT2 8 AB + 14564 LUT2 8 AB + 14565 LUT4 8F00 ((AB)+c)D + 14566 LUT2 9 a^B + 14567 LUT4 770F D?c:/AB\ + 14568 LUT4 F800 ((AB)+C)D + 14569 LUT3 40 aBC + 14570 LUT4 AB0E AC?B^D:1:0:D + 14571 LUT4 770F D?c:/AB\ + 14572 LUT2 9 a^B + 14573 LUT4 770F D?c:/AB\ + 14574 LUT2 9 a^B + 14575 LUT4 770F D?c:/AB\ + 14576 LUT4 770F D?c:/AB\ + 14577 LUT2 9 a^B + 14578 LUT4 770F D?c:/AB\ + 14579 LUT4 0D57 AC?1:b^D:d:0 + 14580 LUT2 6 A^B + 14581 LUT4 770F D?c:/AB\ + 14582 LUT4 770F D?c:/AB\ + 14583 LUT4 770F D?c:/AB\ + 14584 LUT4 0EAB AC?b^D:1:0:d + 14585 LUT2 9 a^B + 14586 LUT4 770F D?c:/AB\ + 14587 LUT4 770F D?c:/AB\ + 14588 LUT2 6 A^B + 14589 LUT4 770F D?c:/AB\ + 14590 LUT4 BEA0 AD?0:C:B^C:1 + 14591 LUT2 6 A^B + 14592 LUT4 770F D?c:/AB\ + 14593 LUT4 770F D?c:/AB\ + 14594 LUT2 4 aB + 14595 LUT4 F8FF (AB)+C+d + 14596 LUT4 BF00 ((/aB\)+c)D + 14597 LUT4 000E cd/ab\ + 14598 LUT2 8 AB + 14599 LUT3 40 aBC + 14600 LUT3 01 abc + 14601 LUT2 8 AB + 14602 LUT3 10 abC + 14603 LUT2 4 aB + 14604 LUT3 40 aBC + 14605 LUT3 07 c/AB\ + 14606 LUT4 C700 D(BC?1:a:0:1) + 14607 LUT4 D300 D(BC?1:0:a:1) + 14608 LUT4 7000 CD/AB\ + 14609 LUT3 81 AB?c:0:0:C + 14610 LUT4 7077 /AB\(d+C) + 14611 LUT4 7077 /AB\(d+C) + 14612 LUT4 4000 aBCD + 14613 LUT4 1000 abCD + 14614 LUT4 0001 abcd + 14615 LUT4 0001 abcd + 14616 LUT4 0001 abcd + 14617 LUT4 8000 ABCD + 14618 LUT4 0001 abcd + 14619 LUT4 0001 abcd + 14620 LUT4 0001 abcd + 14621 LUT4 0001 abcd + 14622 LUT3 FE /ab\+C + 14623 LUT4 FF40 (aBC)+D + 14624 LUT3 80 ABC + 14625 LUT3 90 C(a^B) + 14626 LUT3 90 C(a^B) + 14627 LUT4 9009 (a^B)(D^c) + 14628 LUT2 4 aB + 14629 LUT3 40 aBC + 14630 LUT2 B /aB\ + 14631 LUT4 4182 (b^C)(A^D) + 14632 LUT3 0D c/Ab\ + 14633 LUT4 0700 cD/AB\ + 14634 LUT4 9009 (a^B)(D^c) + 14635 LUT4 00FE ((/ab\)+C)d + 14636 LUT2 8 AB + 14637 LUT2 4 aB + 14638 LUT4 00EF ((/ab\)+c)d + 14639 LUT3 70 C/AB\ + 14640 LUT4 0700 cD/AB\ + 14641 LUT3 01 abc + 14642 LUT4 E8EE AB?0:/cD\:/cD\:1 + 14643 LUT4 8F00 ((AB)+c)D + 14644 LUT3 01 abc + 14645 LUT3 40 aBC + 14646 LUT4 1000 abCD + 14647 LUT2 4 aB + 14648 LUT4 FE00 ((/ab\)+C)D + 14649 LUT4 0777 /AB\(d+c) + 14650 LUT2 8 AB + 14651 LUT2 4 aB + 14652 LUT2 1 ab + 14653 LUT2 4 aB + 14654 LUT2 4 aB + 14655 LUT2 8 AB + 14656 LUT2 4 aB + 14657 LUT2 4 aB + 14658 LUT3 40 aBC + 14659 LUT4 BB0F D?c:/aB\ + 14660 LUT4 4FFF (aB)+c+d + 14661 LUT2 1 ab + 14662 LUT4 0100 abcD + 14663 LUT4 1000 abCD + 14664 LUT3 10 abC + 14665 LUT3 80 ABC + 14666 LUT4 1000 abCD + 14667 LUT3 10 abC + 14668 LUT3 40 aBC + 14669 LUT4 4000 aBCD + 14670 LUT2 8 AB + 14671 LUT3 10 abC + 14672 LUT2 8 AB + 14673 LUT4 1000 abCD + 14674 LUT4 1000 abCD + 14675 LUT4 1000 abCD + 14676 LUT4 0100 abcD + 14677 LUT2 1 ab + 14678 LUT3 01 abc + 14679 LUT4 4000 aBCD + 14680 LUT2 1 ab + 14681 LUT2 8 AB + 14682 LUT4 0100 abcD + 14683 LUT4 4000 aBCD + 14684 LUT2 8 AB + 14685 LUT2 8 AB + 14686 LUT2 4 aB + 14687 LUT3 10 abC + 14688 LUT2 8 AB + 14689 LUT2 8 AB + 14690 LUT2 8 AB + 14691 LUT2 8 AB + 14692 LUT2 8 AB + 14693 LUT2 8 AB + 14694 LUT4 E000 CD/ab\ + 14695 LUT4 4000 aBCD + 14696 LUT2 8 AB + 14697 LUT3 10 abC + 14698 LUT2 8 AB + 14699 LUT2 8 AB + 14700 LUT4 7077 /AB\(d+C) + 14701 LUT4 70FF (C/AB\)+d + 14702 LUT3 0B c/aB\ + 14703 LUT2 8 AB + 14704 LUT4 1000 abCD + 14705 LUT4 0777 /AB\(d+c) + 14706 LUT4 4000 aBCD + 14707 LUT2 8 AB + 14708 LUT4 00F8 ((AB)+C)d + 14709 LUT4 EF00 ((/ab\)+c)D + 14710 LUT3 0D c/Ab\ + 14711 LUT4 0777 /AB\(d+c) + 14712 LUT4 E3FF (BC?1:0:A:1)+d + 14713 LUT4 7000 CD/AB\ + 14714 LUT4 0777 /AB\(d+c) + 14715 LUT4 0777 /AB\(d+c) + 14716 LUT4 1000 abCD + 14717 LUT2 8 AB + 14718 LUT4 7F00 ((/AB\)+c)D + 14719 LUT2 8 AB + 14720 LUT4 007F ((/AB\)+c)d + 14721 LUT2 4 aB + 14722 LUT4 4F00 ((aB)+c)D + 14723 LUT4 0777 /AB\(d+c) + 14724 LUT4 8000 ABCD + 14725 LUT2 8 AB + 14726 LUT2 8 AB + 14727 LUT4 8000 ABCD + 14728 LUT4 007F ((/AB\)+c)d + 14729 LUT3 D0 C/Ab\ + 14730 LUT4 0BBB /aB\(d+c) + 14731 LUT3 01 abc + 14732 LUT3 01 abc + 14733 LUT3 40 aBC + 14734 LUT3 10 abC + 14735 LUT4 7000 CD/AB\ + 14736 LUT2 8 AB + 14737 LUT3 80 ABC + 14738 LUT3 40 aBC + 14739 LUT2 8 AB + 14740 LUT4 0100 abcD + 14741 LUT4 F400 ((aB)+C)D + 14742 LUT4 0100 abcD + 14743 LUT4 4000 aBCD + 14744 LUT2 8 AB + 14745 LUT3 10 abC + 14746 LUT4 1000 abCD + 14747 LUT3 07 c/AB\ + 14748 LUT3 10 abC + 14749 LUT2 4 aB + 14750 LUT4 1000 abCD + 14751 LUT4 0100 abcD + 14752 LUT4 4000 aBCD + 14753 LUT4 1000 abCD + 14754 LUT3 40 aBC + 14755 LUT3 40 aBC + 14756 LUT4 0001 abcd + 14757 LUT2 1 ab + 14758 LUT4 0001 abcd + 14759 LUT4 0100 abcD + 14760 LUT4 B0BB /aB\(d+C) + 14761 LUT4 7F00 ((/AB\)+c)D + 14762 LUT3 70 C/AB\ + 14763 LUT4 7000 CD/AB\ + 14764 LUT4 0700 cD/AB\ + 14765 LUT4 0777 /AB\(d+c) + 14766 LUT3 80 ABC + 14767 LUT3 80 ABC + 14768 LUT4 0777 /AB\(d+c) + 14769 LUT4 0777 /AB\(d+c) + 14770 LUT4 0100 abcD + 14771 LUT4 0777 /AB\(d+c) + 14772 LUT2 8 AB + 14773 LUT4 1000 abCD + 14774 LUT4 0700 cD/AB\ + 14775 LUT4 0777 /AB\(d+c) + 14776 LUT2 8 AB + 14777 LUT2 8 AB + 14778 LUT4 007F ((/AB\)+c)d + 14779 LUT4 8000 ABCD + 14780 LUT2 8 AB + 14781 LUT4 0777 /AB\(d+c) + 14782 LUT2 8 AB + 14783 LUT4 8F00 ((AB)+c)D + 14784 LUT4 1000 abCD + 14785 LUT4 1000 abCD + 14786 LUT4 1000 abCD + 14787 LUT4 0100 abcD + 14788 LUT4 0100 abcD + 14789 LUT4 0777 /AB\(d+c) + 14790 LUT4 1000 abCD + 14791 LUT4 1000 abCD + 14792 LUT4 1000 abCD + 14793 LUT4 4000 aBCD + 14794 LUT4 0100 abcD + 14795 LUT3 10 abC + 14796 LUT4 0001 abcd + 14797 LUT4 4000 aBCD + 14798 LUT3 10 abC + 14799 LUT4 0100 abcD + 14800 LUT4 4000 aBCD + 14801 LUT3 10 abC + 14802 LUT4 0100 abcD + 14803 LUT4 0100 abcD + 14804 LUT4 0777 /AB\(d+c) + 14805 LUT3 0D c/Ab\ + 14806 LUT4 1000 abCD + 14807 LUT4 0777 /AB\(d+c) + 14808 LUT3 80 ABC + 14809 LUT4 0001 abcd + 14810 LUT4 8000 ABCD + 14811 LUT3 80 ABC + 14812 LUT4 7077 /AB\(d+C) + 14813 LUT4 4000 aBCD + 14814 LUT3 40 aBC + 14815 LUT4 0777 /AB\(d+c) + 14816 LUT4 0777 /AB\(d+c) + 14817 LUT3 70 C/AB\ + 14818 LUT4 0777 /AB\(d+c) + 14819 LUT4 7000 CD/AB\ + 14820 LUT4 7000 CD/AB\ + 14821 LUT4 0777 /AB\(d+c) + 14822 LUT4 0777 /AB\(d+c) + 14823 LUT4 7F00 ((/AB\)+c)D + 14824 LUT4 0777 /AB\(d+c) + 14825 LUT4 7077 /AB\(d+C) + 14826 LUT2 8 AB + 14827 LUT3 90 C(a^B) + 14828 LUT4 8000 ABCD + 14829 LUT3 40 aBC + 14830 LUT3 90 C(a^B) + 14831 LUT4 9000 CD(a^B) + 14832 LUT4 1000 abCD + 14833 LUT4 0100 abcD + 14834 LUT4 0100 abcD + 14835 LUT4 004F ((aB)+c)d + 14836 LUT4 BF00 ((/aB\)+c)D + 14837 LUT2 1 ab + 14838 LUT2 1 ab + 14839 LUT3 D0 C/Ab\ + 14840 LUT2 1 ab + 14841 LUT3 70 C/AB\ + 14842 LUT4 0EEE /ab\(d+c) + 14843 LUT4 BF00 ((/aB\)+c)D + 14844 LUT2 1 ab + 14845 LUT3 40 aBC + 14846 LUT2 1 ab + 14847 LUT4 1F00 ((ab)+c)D + 14848 LUT4 0001 abcd + 14849 LUT3 70 C/AB\ + 14850 LUT3 F4 (aB)+C + 14851 LUT2 1 ab + 14852 LUT4 4F00 ((aB)+c)D + 14853 LUT2 4 aB + 14854 LUT2 1 ab + 14855 LUT4 1F00 ((ab)+c)D + 14856 LUT3 F8 (AB)+C + 14857 LUT3 70 C/AB\ + 14858 LUT4 FF80 (ABC)+D + 14859 LUT3 70 C/AB\ + 14860 LUT4 FF80 (ABC)+D + 14861 LUT4 4F00 ((aB)+c)D + 14862 LUT3 07 c/AB\ + 14863 LUT3 0D c/Ab\ + 14864 LUT3 70 C/AB\ + 14865 LUT3 0E c/ab\ + 14866 LUT3 07 c/AB\ + 14867 LUT3 07 c/AB\ + 14868 LUT4 0100 abcD + 14869 LUT4 0001 abcd + 14870 LUT4 EF00 ((/ab\)+c)D + 14871 LUT2 4 aB + 14872 LUT3 B0 C/aB\ + 14873 LUT2 8 AB + 14874 LUT4 7F00 ((/AB\)+c)D + 14875 LUT4 CF0A DC?A:1:0:B + 14876 LUT2 1 ab + 14877 LUT4 BF00 ((/aB\)+c)D + 14878 LUT2 4 aB + 14879 LUT4 4F00 ((aB)+c)D + 14880 LUT4 8F00 ((AB)+c)D + 14881 LUT4 0001 abcd + 14882 LUT3 D0 C/Ab\ + 14883 LUT4 4F00 ((aB)+c)D + 14884 LUT3 D0 C/Ab\ + 14885 LUT3 07 c/AB\ + 14886 LUT4 BF00 ((/aB\)+c)D + 14887 LUT3 10 abC + 14888 LUT2 4 aB + 14889 LUT4 F800 ((AB)+C)D + 14890 LUT4 4F00 ((aB)+c)D + 14891 LUT4 F331 BD?/Ac\:0:1:C + 14892 LUT4 BF00 ((/aB\)+c)D + 14893 LUT4 0700 cD/AB\ + 14894 LUT2 1 ab + 14895 LUT4 0700 cD/AB\ + 14896 LUT4 31F3 BD?1:C:/Ac\:0 + 14897 LUT4 BF00 ((/aB\)+c)D + 14898 LUT4 0007 cd/AB\ + 14899 LUT3 40 aBC + 14900 LUT4 5F0C DC?B:1:0:a + 14901 LUT3 80 ABC + 14902 LUT4 BF00 ((/aB\)+c)D + 14903 LUT4 4F00 ((aB)+c)D + 14904 LUT3 70 C/AB\ + 14905 LUT3 E0 C/ab\ + 14906 LUT4 5F0C DC?B:1:0:a + 14907 LUT3 80 ABC + 14908 LUT4 00F8 ((AB)+C)d + 14909 LUT4 4100 D(B^c)a + 14910 LUT3 01 abc + 14911 LUT3 90 C(a^B) + 14912 LUT2 E /ab\ + 14913 LUT2 8 AB + 14914 LUT4 9009 (a^B)(D^c) + 14915 LUT4 B00B /aB\/D^C\ + 14916 LUT3 F8 (AB)+C + 14917 LUT4 1000 abCD + 14918 LUT4 7007 (c^D)/AB\ + 14919 LUT2 8 AB + 14920 LUT3 80 ABC + 14921 LUT4 9009 (a^B)(D^c) + 14922 LUT4 1000 abCD + 14923 LUT3 40 aBC + 14924 LUT4 0007 cd/AB\ + 14925 LUT2 4 aB + 14926 LUT3 80 ABC + 14927 LUT4 8F00 ((AB)+c)D + 14928 LUT3 07 c/AB\ + 14929 LUT4 1000 abCD + 14930 LUT4 0100 abcD + 14931 LUT4 0100 abcD + 14932 LUT3 40 aBC + 14933 LUT2 4 aB + 14934 LUT4 1000 abCD + 14935 LUT4 4000 aBCD + 14936 LUT4 1000 abCD + 14937 LUT4 1000 abCD + 14938 LUT3 40 aBC + 14939 LUT4 0100 abcD + 14940 LUT2 8 AB + 14941 LUT2 1 ab + 14942 LUT4 0001 abcd + 14943 LUT4 4000 aBCD + 14944 LUT3 40 aBC + 14945 LUT4 1000 abCD + 14946 LUT4 0100 abcD + 14947 LUT2 8 AB + 14948 LUT4 0001 abcd + 14949 LUT4 1000 abCD + 14950 LUT4 8000 ABCD + 14951 LUT3 D0 C/Ab\ + 14952 LUT4 D000 CD/Ab\ + 14953 LUT4 0777 /AB\(d+c) + 14954 LUT3 80 ABC + 14955 LUT4 0777 /AB\(d+c) + 14956 LUT4 4000 aBCD + 14957 LUT4 00BF ((/aB\)+c)d + 14958 LUT4 7F00 ((/AB\)+c)D + 14959 LUT2 4 aB + 14960 LUT4 1000 abCD + 14961 LUT4 1000 abCD + 14962 LUT3 40 aBC + 14963 LUT4 0777 /AB\(d+c) + 14964 LUT4 7077 /AB\(d+C) + 14965 LUT4 B0BB /aB\(d+C) + 14966 LUT4 7000 CD/AB\ + 14967 LUT4 0007 cd/AB\ + 14968 LUT4 1000 abCD + 14969 LUT3 80 ABC + 14970 LUT4 7000 CD/AB\ + 14971 LUT4 0777 /AB\(d+c) + 14972 LUT4 0777 /AB\(d+c) + 14973 LUT4 7077 /AB\(d+C) + 14974 LUT2 8 AB + 14975 LUT2 8 AB + 14976 LUT4 37F3 BD?1:C:1:ac + 14977 LUT4 FF40 (aBC)+D + 14978 LUT4 1000 abCD + 14979 LUT3 10 abC + 14980 LUT3 10 abC + 14981 LUT4 00F4 ((aB)+C)d + 14982 LUT2 1 ab + 14983 LUT4 007F ((/AB\)+c)d + 14984 LUT3 0E c/ab\ + 14985 LUT3 40 aBC + 14986 LUT3 40 aBC + 14987 LUT4 7EFF (AB?C:1:1:c)+d + 14988 LUT4 5300 D(C?b:a) + 14989 LUT3 D0 C/Ab\ + 14990 LUT4 4100 D(B^c)a + 14991 LUT3 90 C(a^B) + 14992 LUT4 4100 D(B^c)a + 14993 LUT2 8 AB + 14994 LUT3 0B c/aB\ + 14995 LUT2 8 AB + 14996 LUT2 8 AB + 14997 LUT2 B /aB\ + 14998 LUT4 0BF0 DC?0:/aB\:1:0 + 14999 LUT4 BBB0 /aB\(D+C) + 15000 LUT3 0E c/ab\ + 15001 LUT3 40 aBC + 15002 LUT4 FFF2 (Ab)+C+D + 15003 LUT3 4F (aB)+c + 15004 LUT3 6F (A^B)+c + 15005 LUT4 FE00 ((/ab\)+C)D + 15006 LUT2 4 aB + 15007 LUT3 90 C(a^B) + 15008 LUT4 D300 D(BC?1:0:a:1) + 15009 LUT4 0E00 cD/ab\ + 15010 LUT4 7088 AD?0:B:C:bC + 15011 LUT3 0B c/aB\ + 15012 LUT4 F100 ((ab)+C)D + 15013 LUT4 9000 CD(a^B) + 15014 LUT3 10 abC + 15015 LUT4 BCFF (BC?0:1:1:A)+d + 15016 LUT4 9009 (a^B)(D^c) + 15017 LUT4 000B cd/aB\ + 15018 LUT3 0B c/aB\ + 15019 LUT4 FFB0 (C/aB\)+D + 15020 LUT4 BF00 ((/aB\)+c)D + 15021 LUT2 1 ab + 15022 LUT3 D0 C/Ab\ + 15023 LUT4 0777 /AB\(d+c) + 15024 LUT3 80 ABC + 15025 LUT2 8 AB + 15026 LUT4 0777 /AB\(d+c) + 15027 LUT4 000D cd/Ab\ + 15028 LUT2 8 AB + 15029 LUT4 4FF0 DC?0:1:1:aB + 15030 LUT2 8 AB + 15031 LUT4 0FFB DC?/aB\:1:1:0 + 15032 LUT4 0BBB /aB\(d+c) + 15033 LUT3 8F (AB)+c + 15034 LUT4 0100 abcD + 15035 LUT3 8F (AB)+c + 15036 LUT3 8F (AB)+c + 15037 LUT4 F888 (AB)+(CD) + 15038 LUT4 F800 ((AB)+C)D + 15039 LUT4 000D cd/Ab\ + 15040 LUT3 0D c/Ab\ + 15041 LUT4 7000 CD/AB\ + 15042 LUT4 000E cd/ab\ + 15043 LUT4 F400 ((aB)+C)D + 15044 LUT3 07 c/AB\ + 15045 LUT4 AC00 D(c?A:B) + 15046 LUT3 7F /AB\+c + 15047 LUT4 CA00 D(C?A:B) + 15048 LUT3 90 C(a^B) + 15049 LUT3 90 C(a^B) + 15050 LUT3 07 c/AB\ + 15051 LUT3 40 aBC + 15052 LUT2 4 aB + 15053 LUT2 4 aB + 15054 LUT4 FF0B (c/aB\)+D + 15055 LUT2 4 aB + 15056 LUT4 FF0E (c/ab\)+D + 15057 LUT4 6100 D(AB?c:C:C:0) + 15058 LUT2 8 AB + 15059 LUT2 8 AB + 15060 LUT3 4F (aB)+c + 15061 LUT4 0EEE /ab\(d+c) + 15062 LUT3 40 aBC + 15063 LUT4 0777 /AB\(d+c) + 15064 LUT3 40 aBC + 15065 LUT2 4 aB + 15066 LUT4 1000 abCD + 15067 LUT2 1 ab + 15068 LUT4 B0BB /aB\(d+C) + 15069 LUT3 F8 (AB)+C + 15070 LUT3 40 aBC + 15071 LUT3 07 c/AB\ + 15072 LUT4 0700 cD/AB\ + 15073 LUT3 8F (AB)+c + 15074 LUT4 B00B /aB\/D^C\ + 15075 LUT4 FF40 (aBC)+D + 15076 LUT4 F088 D?AB:C + 15077 LUT2 6 A^B + 15078 LUT2 4 aB + 15079 LUT3 70 C/AB\ + 15080 LUT3 6F (A^B)+c + 15081 LUT4 0700 cD/AB\ + 15082 LUT3 40 aBC + 15083 LUT3 90 C(a^B) + 15084 LUT4 9000 CD(a^B) + 15085 LUT4 8F00 ((AB)+c)D + 15086 LUT4 AC00 D(c?A:B) + 15087 LUT3 35 c?b:a + 15088 LUT4 9009 (a^B)(D^c) + 15089 LUT2 4 aB + 15090 LUT2 4 aB + 15091 LUT2 8 AB + 15092 LUT2 7 /AB\ + 15093 LUT4 0990 (a^B)(d^c) + 15094 LUT4 0700 cD/AB\ + 15095 LUT4 B0BB /aB\(d+C) + 15096 LUT4 F888 (AB)+(CD) + 15097 LUT3 01 abc + 15098 LUT3 10 abC + 15099 LUT4 F888 (AB)+(CD) + 15100 LUT4 F888 (AB)+(CD) + 15101 LUT4 00F8 ((AB)+C)d + 15102 LUT4 4001 AB?cd:0:CD:0 + 15103 LUT3 C2 BC?A:0:0:1 + 15104 LUT2 E /ab\ + 15105 LUT3 90 C(a^B) + 15106 LUT4 0E00 cD/ab\ + 15107 LUT2 8 AB + 15108 LUT4 000E cd/ab\ + 15109 LUT4 8000 ABCD + 15110 LUT4 0100 abcD + 15111 LUT4 00BF ((/aB\)+c)d + 15112 LUT3 E0 C/ab\ + 15113 LUT2 B /aB\ + 15114 LUT4 70FF (C/AB\)+d + 15115 LUT2 4 aB + 15116 LUT2 8 AB + 15117 LUT2 8 AB + 15118 LUT4 4000 aBCD + 15119 LUT3 8F (AB)+c + 15120 LUT4 5333 DC?b:b:b:a + 15121 LUT4 FE00 ((/ab\)+C)D + 15122 LUT4 FFF8 (AB)+C+D + 15123 LUT4 8F00 ((AB)+c)D + 15124 LUT4 1000 abCD + 15125 LUT2 1 ab + 15126 LUT2 4 aB + 15127 LUT2 4 aB + 15128 LUT4 0777 /AB\(d+c) + 15129 LUT4 00BF ((/aB\)+c)d + 15130 LUT4 CA00 D(C?A:B) + 15131 LUT2 4 aB + 15132 LUT4 FFF8 (AB)+C+D + 15133 LUT4 8F00 ((AB)+c)D + 15134 LUT4 0777 /AB\(d+c) + 15135 LUT4 CA00 D(C?A:B) + 15136 LUT3 4F (aB)+c + 15137 LUT4 0BBB /aB\(d+c) + 15138 LUT3 35 c?b:a + 15139 LUT4 0777 /AB\(d+c) + 15140 LUT4 FFF8 (AB)+C+D + 15141 LUT4 8F00 ((AB)+c)D + 15142 LUT4 CA00 D(C?A:B) + 15143 LUT4 FFF8 (AB)+C+D + 15144 LUT4 8F00 ((AB)+c)D + 15145 LUT4 0777 /AB\(d+c) + 15146 LUT4 CA00 D(C?A:B) + 15147 LUT4 FFF8 (AB)+C+D + 15148 LUT4 8F00 ((AB)+c)D + 15149 LUT4 0777 /AB\(d+c) + 15150 LUT4 CA00 D(C?A:B) + 15151 LUT4 FF80 (ABC)+D + 15152 LUT3 80 ABC + 15153 LUT4 8000 ABCD + 15154 LUT3 90 C(a^B) + 15155 LUT4 B0BB /aB\(d+C) + 15156 LUT4 9009 (a^B)(D^c) + 15157 LUT4 9009 (a^B)(D^c) + 15158 LUT4 B00B /aB\/D^C\ + 15159 LUT4 9000 CD(a^B) + 15160 LUT3 D0 C/Ab\ + 15161 LUT4 B00B /aB\/D^C\ + 15162 LUT4 9009 (a^B)(D^c) + 15163 LUT4 B00B /aB\/D^C\ + 15164 LUT2 6 A^B + 15165 LUT4 B00B /aB\/D^C\ + 15166 LUT4 B00B /aB\/D^C\ + 15167 LUT3 90 C(a^B) + 15168 LUT4 9009 (a^B)(D^c) + 15169 LUT4 B00B /aB\/D^C\ + 15170 LUT4 B00B /aB\/D^C\ + 15171 LUT4 9000 CD(a^B) + 15172 LUT4 9000 CD(a^B) + 15173 LUT4 B0BB /aB\(d+C) + 15174 LUT4 9009 (a^B)(D^c) + 15175 LUT4 9009 (a^B)(D^c) + 15176 LUT3 80 ABC + 15177 LUT3 90 C(a^B) + 15178 LUT4 9009 (a^B)(D^c) + 15179 LUT4 B00B /aB\/D^C\ + 15180 LUT4 B0BB /aB\(d+C) + 15181 LUT4 9009 (a^B)(D^c) + 15182 LUT4 8000 ABCD + 15183 LUT4 B0BB /aB\(d+C) + 15184 LUT4 B00B /aB\/D^C\ + 15185 LUT4 B00B /aB\/D^C\ + 15186 LUT4 9009 (a^B)(D^c) + 15187 LUT4 9000 CD(a^B) + 15188 LUT4 B0BB /aB\(d+C) + 15189 LUT4 B00B /aB\/D^C\ + 15190 LUT4 D000 CD/Ab\ + 15191 LUT4 B0BB /aB\(d+C) + 15192 LUT4 9009 (a^B)(D^c) + 15193 LUT3 D0 C/Ab\ + 15194 LUT4 CA00 D(C?A:B) + 15195 LUT3 70 C/AB\ + 15196 LUT3 B0 C/aB\ + 15197 LUT3 B0 C/aB\ + 15198 LUT3 69 A^B^c + 15199 LUT4 9669 A^B^c^D + 15200 LUT4 6996 A^B^c^d + 15201 LUT4 4F44 (aB)+(cD) + 15202 LUT4 0BBB /aB\(d+c) + 15203 LUT4 0100 abcD + 15204 LUT4 FFB0 (C/aB\)+D + 15205 LUT3 F4 (aB)+C + 15206 LUT2 8 AB + 15207 LUT3 D0 C/Ab\ + 15208 LUT3 B0 C/aB\ + 15209 LUT4 0BBB /aB\(d+c) + 15210 LUT3 40 aBC + 15211 LUT3 40 aBC + 15212 LUT3 10 abC + 15213 LUT4 FF40 (aBC)+D + 15214 LUT4 0ECC BD?0:1:Ac:c + 15215 LUT2 E /ab\ + 15216 LUT2 E /ab\ + 15217 LUT3 4B (aB)^c + 15218 LUT3 4B (aB)^c + 15219 LUT3 4B (aB)^c + 15220 LUT3 4B (aB)^c + 15221 LUT3 87 (AB)^c + 15222 LUT3 87 (AB)^c + 15223 LUT3 87 (AB)^c + 15224 LUT3 B0 C/aB\ + 15225 LUT3 01 abc + 15226 LUT2 1 ab + 15227 LUT3 80 ABC + 15228 LUT4 35FF (c?b:a)+d + 15229 LUT3 D0 C/Ab\ + 15230 LUT3 B0 C/aB\ + 15231 LUT3 40 aBC + 15232 LUT3 40 aBC + 15233 LUT3 D0 C/Ab\ + 15234 LUT3 B0 C/aB\ + 15235 LUT2 8 AB + 15236 LUT2 8 AB + 15237 LUT3 D0 C/Ab\ + 15238 LUT3 B0 C/aB\ + 15239 LUT2 8 AB + 15240 LUT4 000B cd/aB\ + 15241 LUT4 EF00 ((/ab\)+c)D + 15242 LUT4 FFFE /ab\+C+D + 15243 LUT4 FFFE /ab\+C+D + 15244 LUT4 FFFE /ab\+C+D + 15245 LUT4 FFFE /ab\+C+D + 15246 LUT4 000B cd/aB\ + 15247 LUT3 70 C/AB\ + 15248 LUT2 4 aB + 15249 LUT4 FFFE /ab\+C+D + 15250 LUT4 FFFE /ab\+C+D + 15251 LUT4 FFFE /ab\+C+D + 15252 LUT4 FFFE /ab\+C+D + 15253 LUT4 F888 (AB)+(CD) + 15254 LUT2 8 AB + 15255 LUT3 0B c/aB\ + 15256 LUT4 B0BB /aB\(d+C) + 15257 LUT2 1 ab + 15258 LUT2 1 ab + 15259 LUT4 4000 aBCD + 15260 LUT3 D0 C/Ab\ + 15261 LUT3 B0 C/aB\ + 15262 LUT2 8 AB + 15263 LUT3 80 ABC + 15264 LUT2 4 aB + 15265 LUT3 4B (aB)^c + 15266 LUT3 4B (aB)^c + 15267 LUT3 4B (aB)^c + 15268 LUT3 4B (aB)^c + 15269 LUT3 4B (aB)^c + 15270 LUT3 4B (aB)^c + 15271 LUT3 4B (aB)^c + 15272 LUT3 4B (aB)^c + 15273 LUT4 000B cd/aB\ + 15274 LUT3 70 C/AB\ + 15275 LUT4 000B cd/aB\ + 15276 LUT4 BF00 ((/aB\)+c)D + 15277 LUT4 000B cd/aB\ + 15278 LUT3 70 C/AB\ + 15279 LUT4 FFFE /ab\+C+D + 15280 LUT4 FFFE /ab\+C+D + 15281 LUT4 FFFE /ab\+C+D + 15282 LUT4 FFFE /ab\+C+D + 15283 LUT4 FFFE /ab\+C+D + 15284 LUT4 FFFE /ab\+C+D + 15285 LUT4 FFFE /ab\+C+D + 15286 LUT4 FFFE /ab\+C+D + 15287 LUT3 10 abC + 15288 LUT3 D0 C/Ab\ + 15289 LUT3 B0 C/aB\ + 15290 LUT2 8 AB + 15291 LUT4 FFB0 (C/aB\)+D + 15292 LUT3 F4 (aB)+C + 15293 LUT3 80 ABC + 15294 LUT2 8 AB + 15295 LUT4 44F0 D?C:aB + 15296 LUT2 E /ab\ + 15297 LUT3 CA C?A:B + 15298 LUT3 40 aBC + 15299 LUT2 E /ab\ + 15300 LUT2 E /ab\ + 15301 LUT3 F8 (AB)+C + 15302 LUT3 F4 (aB)+C + 15303 LUT3 0B c/aB\ + 15304 LUT4 DFC0 BD?0:C:/AC\:1 + 15305 LUT3 10 abC + 15306 LUT2 6 A^B + 15307 LUT3 CA C?A:B + 15308 LUT2 7 /AB\ + 15309 LUT4 0001 abcd + 15310 LUT4 0001 abcd + 15311 LUT3 0B c/aB\ + 15312 LUT4 4000 aBCD + 15313 LUT2 E /ab\ + 15314 LUT3 10 abC + 15315 LUT2 6 A^B + 15316 LUT3 F8 (AB)+C + 15317 LUT4 40FF (aBC)+d + 15318 LUT3 35 c?b:a + 15319 LUT3 F8 (AB)+C + 15320 LUT3 D0 C/Ab\ + 15321 LUT3 F1 (ab)+C + 15322 LUT3 10 abC + 15323 LUT2 6 A^B + 15324 LUT2 6 A^B + 15325 LUT2 6 A^B + 15326 LUT2 6 A^B + 15327 LUT4 00FE ((/ab\)+C)d + 15328 LUT2 4 aB + 15329 LUT3 0E c/ab\ + 15330 LUT4 00F4 ((aB)+C)d + 15331 LUT3 4F (aB)+c + 15332 LUT4 0D00 cD/Ab\ + 15333 LUT4 7F00 ((/AB\)+c)D + 15334 LUT4 0100 abcD + 15335 LUT4 0E00 cD/ab\ + 15336 LUT4 BFA0 AD?0:C:/BC\:1 + 15337 LUT3 F4 (aB)+C + 15338 LUT3 80 ABC + 15339 LUT4 88F0 D?C:AB + 15340 LUT4 FFB0 (C/aB\)+D + 15341 LUT2 8 AB + 15342 LUT3 AC c?A:B + 15343 LUT4 35FF (c?b:a)+d + 15344 LUT2 1 ab + 15345 LUT4 000B cd/aB\ + 15346 LUT4 7F00 ((/AB\)+c)D + 15347 LUT2 E /ab\ + 15348 LUT3 07 c/AB\ + 15349 LUT4 0C0B BC?d:/ad\:0:0 + 15350 LUT4 FF70 (C/AB\)+D + 15351 LUT3 80 ABC + 15352 LUT3 F4 (aB)+C + 15353 LUT2 E /ab\ + 15354 LUT2 E /ab\ + 15355 LUT2 E /ab\ + 15356 LUT2 E /ab\ + 15357 LUT2 E /ab\ + 15358 LUT3 BF /aB\+c + 15359 LUT4 0001 abcd + 15360 LUT3 E0 C/ab\ + 15361 LUT3 F4 (aB)+C + 15362 LUT3 40 aBC + 15363 LUT3 0D c/Ab\ + 15364 LUT3 E0 C/ab\ + 15365 LUT4 BFFF /aB\+c+d + 15366 LUT4 EF00 ((/ab\)+c)D + 15367 LUT3 EF /ab\+c + 15368 LUT2 8 AB + 15369 LUT2 1 ab + 15370 LUT4 00F1 ((ab)+C)d + 15371 LUT2 1 ab + 15372 LUT4 F100 ((ab)+C)D + 15373 LUT4 0001 abcd + 15374 LUT4 D3FF (BC?1:0:a:1)+d + 15375 LUT2 8 AB + 15376 LUT2 8 AB + 15377 LUT2 8 AB + 15378 LUT2 8 AB + 15379 LUT2 8 AB + 15380 LUT2 8 AB + 15381 LUT3 80 ABC + 15382 LUT3 4F (aB)+c + 15383 LUT3 F4 (aB)+C + 15384 LUT3 80 ABC + 15385 LUT3 40 aBC + 15386 LUT3 E0 C/ab\ + 15387 LUT3 D0 C/Ab\ + 15388 LUT3 B0 C/aB\ + 15389 LUT3 40 aBC + 15390 LUT3 D0 C/Ab\ + 15391 LUT3 B0 C/aB\ + 15392 LUT2 8 AB + 15393 LUT2 E /ab\ + 15394 LUT3 D0 C/Ab\ + 15395 LUT3 B0 C/aB\ + 15396 LUT2 8 AB + 15397 LUT2 E /ab\ + 15398 LUT3 87 (AB)^c + 15399 LUT2 E /ab\ + 15400 LUT4 1F00 ((ab)+c)D + 15401 LUT4 3A00 D(c?b:A) + 15402 LUT2 4 aB + 15403 LUT3 E0 C/ab\ + 15404 LUT4 BE00 AD?0:0:B^C:1 + 15405 LUT3 F4 (aB)+C + 15406 LUT3 F8 (AB)+C + 15407 LUT3 8F (AB)+c + 15408 LUT2 1 ab + 15409 LUT3 8F (AB)+c + 15410 LUT2 1 ab + 15411 LUT2 8 AB + 15412 LUT4 0777 /AB\(d+c) + 15413 LUT3 8F (AB)+c + 15414 LUT4 0777 /AB\(d+c) + 15415 LUT3 8F (AB)+c + 15416 LUT4 0777 /AB\(d+c) + 15417 LUT3 8F (AB)+c + 15418 LUT4 0777 /AB\(d+c) + 15419 LUT3 8F (AB)+c + 15420 LUT4 0777 /AB\(d+c) + 15421 LUT4 9009 (a^B)(D^c) + 15422 LUT2 8 AB + 15423 LUT3 EF /ab\+c + 15424 LUT4 EEE0 /ab\(D+C) + 15425 LUT4 0777 /AB\(d+c) + 15426 LUT2 8 AB + 15427 LUT4 8000 ABCD + 15428 LUT2 4 aB + 15429 LUT2 8 AB + 15430 LUT2 4 aB + 15431 LUT2 8 AB + 15432 LUT4 1000 abCD + 15433 LUT2 8 AB + 15434 LUT2 4 aB + 15435 LUT3 10 abC + 15436 LUT3 C2 BC?A:0:0:1 + 15437 LUT3 F4 (aB)+C + 15438 LUT3 07 c/AB\ + 15439 LUT2 4 aB + 15440 LUT3 10 abC + 15441 LUT3 C2 BC?A:0:0:1 + 15442 LUT3 53 C?b:a + 15443 LUT2 4 aB + 15444 LUT3 10 abC + 15445 LUT3 C2 BC?A:0:0:1 + 15446 LUT3 F4 (aB)+C + 15447 LUT2 1 ab + 15448 LUT2 4 aB + 15449 LUT3 10 abC + 15450 LUT3 C2 BC?A:0:0:1 + 15451 LUT3 53 C?b:a + 15452 LUT4 EEE0 /ab\(D+C) + 15453 LUT2 4 aB + 15454 LUT3 10 abC + 15455 LUT2 1 ab + 15456 LUT3 C2 BC?A:0:0:1 + 15457 LUT3 F4 (aB)+C + 15458 LUT3 10 abC + 15459 LUT3 C2 BC?A:0:0:1 + 15460 LUT3 F4 (aB)+C + 15461 LUT3 10 abC + 15462 LUT3 C2 BC?A:0:0:1 + 15463 LUT3 3A c?b:A + 15464 LUT3 CA C?A:B + 15465 LUT3 CA C?A:B + 15466 LUT3 F8 (AB)+C + 15467 LUT3 10 abC + 15468 LUT3 40 aBC + 15469 LUT3 40 aBC + 15470 LUT3 40 aBC + 15471 LUT2 7 /AB\ + 15472 LUT2 9 a^B + 15473 LUT2 9 a^B + 15474 LUT2 9 a^B + 15475 LUT2 9 a^B + 15476 LUT2 9 a^B + 15477 LUT2 9 a^B + 15478 LUT2 9 a^B + 15479 LUT2 9 a^B + 15480 LUT4 8000 ABCD + 15481 LUT4 7000 CD/AB\ + 15482 LUT3 07 c/AB\ + 15483 LUT4 8000 ABCD + 15484 LUT3 10 abC + 15485 LUT2 8 AB + 15486 LUT2 8 AB + 15487 LUT3 10 abC + 15488 LUT2 1 ab + 15489 LUT4 0001 abcd + 15490 LUT4 0001 abcd + 15491 LUT3 10 abC + 15492 LUT2 1 ab + 15493 LUT2 1 ab + 15494 LUT2 1 ab + 15495 LUT4 8000 ABCD + 15496 LUT2 8 AB + 15497 LUT3 10 abC + 15498 LUT2 8 AB + 15499 LUT2 1 ab + 15500 LUT4 0100 abcD + 15501 LUT4 0100 abcD + 15502 LUT3 07 c/AB\ + 15503 LUT4 8000 ABCD + 15504 LUT2 8 AB + 15505 LUT2 8 AB + 15506 LUT4 0001 abcd + 15507 LUT4 0100 abcD + 15508 LUT4 4000 aBCD + 15509 LUT3 10 abC + 15510 LUT2 1 ab + 15511 LUT3 40 aBC + 15512 LUT2 1 ab + 15513 LUT2 1 ab + 15514 LUT4 8000 ABCD + 15515 LUT2 4 aB + 15516 LUT4 4000 aBCD + 15517 LUT4 00BF ((/aB\)+c)d + 15518 LUT4 4000 aBCD + 15519 LUT4 BF00 ((/aB\)+c)D + 15520 LUT4 0700 cD/AB\ + 15521 LUT4 1000 abCD + 15522 LUT2 4 aB + 15523 LUT4 0007 cd/AB\ + 15524 LUT4 00F4 ((aB)+C)d + 15525 LUT4 00F4 ((aB)+C)d + 15526 LUT2 4 aB + 15527 LUT4 007F ((/AB\)+c)d + 15528 LUT2 8 AB + 15529 LUT2 8 AB + 15530 LUT2 8 AB + 15531 LUT2 8 AB + 15532 LUT3 80 ABC + 15533 LUT3 80 ABC + 15534 LUT4 8000 ABCD + 15535 LUT4 8000 ABCD + 15536 LUT4 8000 ABCD + 15537 LUT4 4000 aBCD + 15538 LUT2 8 AB + 15539 LUT3 80 ABC + 15540 LUT2 8 AB + 15541 LUT4 8000 ABCD + 15542 LUT2 8 AB + 15543 LUT3 80 ABC + 15544 LUT4 4000 aBCD + 15545 LUT3 80 ABC + 15546 LUT3 80 ABC + 15547 LUT3 40 aBC + 15548 LUT4 F800 ((AB)+C)D + 15549 LUT3 80 ABC + 15550 LUT3 40 aBC + 15551 LUT2 8 AB + 15552 LUT3 80 ABC + 15553 LUT3 40 aBC + 15554 LUT4 BF00 ((/aB\)+c)D + 15555 LUT3 0B c/aB\ + 15556 LUT2 8 AB + 15557 LUT3 80 ABC + 15558 LUT4 4000 aBCD + 15559 LUT3 80 ABC + 15560 LUT2 8 AB + 15561 LUT3 80 ABC + 15562 LUT3 80 ABC + 15563 LUT2 8 AB + 15564 LUT2 8 AB + 15565 LUT4 4F00 ((aB)+c)D + 15566 LUT3 F8 (AB)+C + 15567 LUT4 4000 aBCD + 15568 LUT3 0B c/aB\ + 15569 LUT4 4000 aBCD + 15570 LUT3 B0 C/aB\ + 15571 LUT3 0B c/aB\ + 15572 LUT3 40 aBC + 15573 LUT3 10 abC + 15574 LUT4 0B00 cD/aB\ + 15575 LUT4 BF00 ((/aB\)+c)D + 15576 LUT4 7000 CD/AB\ + 15577 LUT3 40 aBC + 15578 LUT3 80 ABC + 15579 LUT4 0700 cD/AB\ + 15580 LUT4 BF00 ((/aB\)+c)D + 15581 LUT4 00FE ((/ab\)+C)d + 15582 LUT4 000E cd/ab\ + 15583 LUT4 4000 aBCD + 15584 LUT2 4 aB + 15585 LUT3 1F (ab)+c + 15586 LUT2 8 AB + 15587 LUT3 80 ABC + 15588 LUT4 0100 abcD + 15589 LUT4 0007 cd/AB\ + 15590 LUT4 4000 aBCD + 15591 LUT4 1000 abCD + 15592 LUT4 4000 aBCD + 15593 LUT4 004F ((aB)+c)d + 15594 LUT3 80 ABC + 15595 LUT2 8 AB + 15596 LUT4 4000 aBCD + 15597 LUT3 70 C/AB\ + 15598 LUT3 70 C/AB\ + 15599 LUT3 80 ABC + 15600 LUT3 07 c/AB\ + 15601 LUT2 8 AB + 15602 LUT4 0100 abcD + 15603 LUT3 0B c/aB\ + 15604 LUT2 4 aB + 15605 LUT4 000B cd/aB\ + 15606 LUT2 8 AB + 15607 LUT4 4000 aBCD + 15608 LUT4 0B00 cD/aB\ + 15609 LUT3 07 c/AB\ + 15610 LUT3 80 ABC + 15611 LUT4 4000 aBCD + 15612 LUT4 001F ((ab)+c)d + 15613 LUT3 40 aBC + 15614 LUT4 1000 abCD + 15615 LUT4 000B cd/aB\ + 15616 LUT3 01 abc + 15617 LUT2 8 AB + 15618 LUT2 8 AB + 15619 LUT2 8 AB + 15620 LUT2 8 AB + 15621 LUT2 8 AB + 15622 LUT2 8 AB + 15623 LUT2 8 AB + 15624 LUT2 8 AB + 15625 LUT2 8 AB + 15626 LUT2 8 AB + 15627 LUT2 8 AB + 15628 LUT2 8 AB + 15629 LUT2 4 aB + 15630 LUT2 4 aB + 15631 LUT4 B0BB /aB\(d+C) + 15632 LUT2 4 aB + 15633 LUT2 4 aB + 15634 LUT4 EF00 ((/ab\)+c)D + 15635 LUT4 0001 abcd + 15636 LUT4 B0BB /aB\(d+C) + 15637 LUT4 00F4 ((aB)+C)d + 15638 LUT3 90 C(a^B) + 15639 LUT4 B0BB /aB\(d+C) + 15640 LUT2 4 aB + 15641 LUT4 B0BB /aB\(d+C) + 15642 LUT4 9000 CD(a^B) + 15643 LUT4 0B00 cD/aB\ + 15644 LUT4 B0BB /aB\(d+C) + 15645 LUT2 4 aB + 15646 LUT4 B0BB /aB\(d+C) + 15647 LUT4 9000 CD(a^B) + 15648 LUT4 0D00 cD/Ab\ + 15649 LUT4 B0BB /aB\(d+C) + 15650 LUT2 4 aB + 15651 LUT4 B0BB /aB\(d+C) + 15652 LUT4 0D00 cD/Ab\ + 15653 LUT4 00F4 ((aB)+C)d + 15654 LUT3 F1 (ab)+C + 15655 LUT4 B0BB /aB\(d+C) + 15656 LUT2 4 aB + 15657 LUT4 0007 cd/AB\ + 15658 LUT4 0100 abcD + 15659 LUT4 8000 ABCD + 15660 LUT2 1 ab + 15661 LUT4 0777 /AB\(d+c) + 15662 LUT4 8000 ABCD + 15663 LUT3 40 aBC + 15664 LUT4 8000 ABCD + 15665 LUT3 10 abC + 15666 LUT4 0001 abcd + 15667 LUT4 D755 AD?1:0:1:b^C + 15668 LUT4 F53F DC?1:a:b:1 + 15669 LUT4 D755 AD?1:0:1:b^C + 15670 LUT4 F53F DC?1:a:b:1 + 15671 LUT4 D755 AD?1:0:1:b^C + 15672 LUT4 F53F DC?1:a:b:1 + 15673 LUT4 D755 AD?1:0:1:b^C + 15674 LUT4 F53F DC?1:a:b:1 + 15675 LUT4 D755 AD?1:0:1:b^C + 15676 LUT4 F53F DC?1:a:b:1 + 15677 LUT4 D755 AD?1:0:1:b^C + 15678 LUT4 F53F DC?1:a:b:1 + 15679 LUT4 D755 AD?1:0:1:b^C + 15680 LUT4 F53F DC?1:a:b:1 + 15681 LUT4 D755 AD?1:0:1:b^C + 15682 LUT4 F53F DC?1:a:b:1 + 15683 LUT4 D755 AD?1:0:1:b^C + 15684 LUT4 F53F DC?1:a:b:1 + 15685 LUT4 D755 AD?1:0:1:b^C + 15686 LUT4 F53F DC?1:a:b:1 + 15687 LUT4 D755 AD?1:0:1:b^C + 15688 LUT4 F53F DC?1:a:b:1 + 15689 LUT4 D755 AD?1:0:1:b^C + 15690 LUT4 F53F DC?1:a:b:1 + 15691 LUT4 D755 AD?1:0:1:b^C + 15692 LUT4 F53F DC?1:a:b:1 + 15693 LUT4 D755 AD?1:0:1:b^C + 15694 LUT4 F53F DC?1:a:b:1 + 15695 LUT4 D755 AD?1:0:1:b^C + 15696 LUT4 F53F DC?1:a:b:1 + 15697 LUT4 D755 AD?1:0:1:b^C + 15698 LUT4 F53F DC?1:a:b:1 + 15699 LUT4 D755 AD?1:0:1:b^C + 15700 LUT4 F53F DC?1:a:b:1 + 15701 LUT4 D755 AD?1:0:1:b^C + 15702 LUT4 F53F DC?1:a:b:1 + 15703 LUT4 D755 AD?1:0:1:b^C + 15704 LUT4 F53F DC?1:a:b:1 + 15705 LUT2 8 AB + 15706 LUT4 0D00 cD/Ab\ + 15707 LUT2 E /ab\ + 15708 LUT3 E0 C/ab\ + 15709 LUT3 F8 (AB)+C + 15710 LUT3 10 abC + 15711 LUT3 10 abC + 15712 LUT2 E /ab\ + 15713 LUT3 FE /ab\+C + 15714 LUT2 E /ab\ + 15715 LUT2 E /ab\ + 15716 LUT2 8 AB + 15717 LUT2 8 AB + 15718 LUT3 80 ABC + 15719 LUT4 00D7 AD?1:b^C:0:0 + 15720 LUT2 8 AB + 15721 LUT2 4 aB + 15722 LUT2 4 aB + 15723 LUT2 4 aB + 15724 LUT2 4 aB + 15725 LUT4 8000 ABCD + 15726 LUT4 8000 ABCD + 15727 LUT4 00F8 ((AB)+C)d + 15728 LUT3 70 C/AB\ + 15729 LUT3 78 (AB)^C + 15730 LUT2 4 aB + 15731 LUT3 87 (AB)^c + 15732 LUT4 000E cd/ab\ + 15733 LUT4 0708 AC?D:B^D:0:0 + 15734 LUT4 0708 AC?D:B^D:0:0 + 15735 LUT3 87 (AB)^c + 15736 LUT4 0100 abcD + 15737 LUT4 0708 AC?D:B^D:0:0 + 15738 LUT3 0E c/ab\ + 15739 LUT4 0708 AC?D:B^D:0:0 + 15740 LUT4 0807 AC?d:b^D:0:0 + 15741 LUT4 0708 AC?D:B^D:0:0 + 15742 LUT4 0708 AC?D:B^D:0:0 + 15743 LUT3 70 C/AB\ + 15744 LUT3 78 (AB)^C + 15745 LUT4 1000 abCD + 15746 LUT4 0E00 cD/ab\ + 15747 LUT4 1000 abCD + 15748 LUT4 0708 AC?D:B^D:0:0 + 15749 LUT4 0708 AC?D:B^D:0:0 + 15750 LUT4 0708 AC?D:B^D:0:0 + 15751 LUT3 87 (AB)^c + 15752 LUT4 0100 abcD + 15753 LUT4 0708 AC?D:B^D:0:0 + 15754 LUT3 0E c/ab\ + 15755 LUT4 0708 AC?D:B^D:0:0 + 15756 LUT4 C305 DC?a:b:0:B + 15757 LUT4 0708 AC?D:B^D:0:0 + 15758 LUT4 0708 AC?D:B^D:0:0 + 15759 LUT3 70 C/AB\ + 15760 LUT3 78 (AB)^C + 15761 LUT4 0BAE AC?B^D:1:0:d + 15762 LUT2 8 AB + 15763 LUT3 78 (AB)^C + 15764 LUT4 0100 abcD + 15765 LUT4 0708 AC?D:B^D:0:0 + 15766 LUT4 00F1 ((ab)+C)d + 15767 LUT4 0708 AC?D:B^D:0:0 + 15768 LUT4 0708 AC?D:B^D:0:0 + 15769 LUT3 78 (AB)^C + 15770 LUT4 0708 AC?D:B^D:0:0 + 15771 LUT4 0708 AC?D:B^D:0:0 + 15772 LUT4 00F8 ((AB)+C)d + 15773 LUT4 0708 AC?D:B^D:0:0 + 15774 LUT3 87 (AB)^c + 15775 LUT4 00F8 ((AB)+C)d + 15776 LUT4 0708 AC?D:B^D:0:0 + 15777 LUT2 4 aB + 15778 LUT3 87 (AB)^c + 15779 LUT4 1000 abCD + 15780 LUT4 0708 AC?D:B^D:0:0 + 15781 LUT4 0708 AC?D:B^D:0:0 + 15782 LUT4 0708 AC?D:B^D:0:0 + 15783 LUT4 0708 AC?D:B^D:0:0 + 15784 LUT4 3CFA DC?A:B:1:b + 15785 LUT3 78 (AB)^C + 15786 LUT3 87 (AB)^c + 15787 LUT4 0708 AC?D:B^D:0:0 + 15788 LUT4 0708 AC?D:B^D:0:0 + 15789 LUT4 0708 AC?D:B^D:0:0 + 15790 LUT4 0770 (C^D)/AB\ + 15791 LUT2 8 AB + 15792 LUT3 78 (AB)^C + 15793 LUT3 87 (AB)^c + 15794 LUT4 00F8 ((AB)+C)d + 15795 LUT4 0708 AC?D:B^D:0:0 + 15796 LUT3 87 (AB)^c + 15797 LUT3 07 c/AB\ + 15798 LUT3 87 (AB)^c + 15799 LUT3 87 (AB)^c + 15800 LUT4 00F8 ((AB)+C)d + 15801 LUT4 0708 AC?D:B^D:0:0 + 15802 LUT3 87 (AB)^c + 15803 LUT3 78 (AB)^C + 15804 LUT4 008F ((AB)+c)d + 15805 LUT4 5F03 DC?b:1:0:a + 15806 LUT4 0807 AC?d:b^D:0:0 + 15807 LUT3 70 C/AB\ + 15808 LUT3 78 (AB)^C + 15809 LUT3 78 (AB)^C + 15810 LUT3 78 (AB)^C + 15811 LUT3 F8 (AB)+C + 15812 LUT4 0807 AC?d:b^D:0:0 + 15813 LUT4 075D AC?1:B^D:d:0 + 15814 LUT2 8 AB + 15815 LUT3 87 (AB)^c + 15816 LUT4 E000 CD/ab\ + 15817 LUT4 0807 AC?d:b^D:0:0 + 15818 LUT3 70 C/AB\ + 15819 LUT3 78 (AB)^C + 15820 LUT2 4 aB + 15821 LUT4 F100 ((ab)+C)D + 15822 LUT4 1000 abCD + 15823 LUT4 8000 ABCD + 15824 LUT4 000E cd/ab\ + 15825 LUT4 0708 AC?D:B^D:0:0 + 15826 LUT4 0807 AC?d:b^D:0:0 + 15827 LUT4 0708 AC?D:B^D:0:0 + 15828 LUT4 0708 AC?D:B^D:0:0 + 15829 LUT4 008F ((AB)+c)d + 15830 LUT4 0708 AC?D:B^D:0:0 + 15831 LUT3 78 (AB)^C + 15832 LUT4 1000 abCD + 15833 LUT4 00F8 ((AB)+C)d + 15834 LUT4 0708 AC?D:B^D:0:0 + 15835 LUT3 87 (AB)^c + 15836 LUT4 0708 AC?D:B^D:0:0 + 15837 LUT4 E000 CD/ab\ + 15838 LUT4 C305 DC?a:b:0:B + 15839 LUT4 0708 AC?D:B^D:0:0 + 15840 LUT4 000E cd/ab\ + 15841 LUT4 0708 AC?D:B^D:0:0 + 15842 LUT4 0708 AC?D:B^D:0:0 + 15843 LUT3 87 (AB)^c + 15844 LUT4 0100 abcD + 15845 LUT3 70 C/AB\ + 15846 LUT3 78 (AB)^C + 15847 LUT4 E000 CD/ab\ + 15848 LUT4 0001 abcd + 15849 LUT4 0708 AC?D:B^D:0:0 + 15850 LUT4 0708 AC?D:B^D:0:0 + 15851 LUT4 0708 AC?D:B^D:0:0 + 15852 LUT4 0708 AC?D:B^D:0:0 + 15853 LUT4 008F ((AB)+c)d + 15854 LUT4 0708 AC?D:B^D:0:0 + 15855 LUT3 78 (AB)^C + 15856 LUT2 8 AB + 15857 LUT3 87 (AB)^c + 15858 LUT4 0708 AC?D:B^D:0:0 + 15859 LUT3 07 c/AB\ + 15860 LUT3 87 (AB)^c + 15861 LUT4 0708 AC?D:B^D:0:0 + 15862 LUT3 70 C/AB\ + 15863 LUT3 78 (AB)^C + 15864 LUT4 075D AC?1:B^D:d:0 + 15865 LUT2 8 AB + 15866 LUT3 87 (AB)^c + 15867 LUT3 78 (AB)^C + 15868 LUT4 8000 ABCD + 15869 LUT2 E /ab\ + 15870 LUT4 F800 ((AB)+C)D + 15871 LUT4 0807 AC?d:b^D:0:0 + 15872 LUT4 0708 AC?D:B^D:0:0 + 15873 LUT2 4 aB + 15874 LUT3 87 (AB)^c + 15875 LUT3 0E c/ab\ + 15876 LUT3 70 C/AB\ + 15877 LUT3 78 (AB)^C + 15878 LUT3 87 (AB)^c + 15879 LUT4 0807 AC?d:b^D:0:0 + 15880 LUT4 0708 AC?D:B^D:0:0 + 15881 LUT4 00F8 ((AB)+C)d + 15882 LUT4 0708 AC?D:B^D:0:0 + 15883 LUT3 87 (AB)^c + 15884 LUT4 0708 AC?D:B^D:0:0 + 15885 LUT4 00F8 ((AB)+C)d + 15886 LUT4 0708 AC?D:B^D:0:0 + 15887 LUT3 87 (AB)^c + 15888 LUT4 000E cd/ab\ + 15889 LUT4 0708 AC?D:B^D:0:0 + 15890 LUT4 0708 AC?D:B^D:0:0 + 15891 LUT3 87 (AB)^c + 15892 LUT4 0708 AC?D:B^D:0:0 + 15893 LUT4 0708 AC?D:B^D:0:0 + 15894 LUT4 00F8 ((AB)+C)d + 15895 LUT4 0708 AC?D:B^D:0:0 + 15896 LUT4 C305 DC?a:b:0:B + 15897 LUT4 0708 AC?D:B^D:0:0 + 15898 LUT4 0708 AC?D:B^D:0:0 + 15899 LUT4 0708 AC?D:B^D:0:0 + 15900 LUT4 0001 abcd + 15901 LUT4 0708 AC?D:B^D:0:0 + 15902 LUT3 70 C/AB\ + 15903 LUT3 78 (AB)^C + 15904 LUT4 0708 AC?D:B^D:0:0 + 15905 LUT3 70 C/AB\ + 15906 LUT3 78 (AB)^C + 15907 LUT3 80 ABC + 15908 LUT3 40 aBC + 15909 LUT2 4 aB + 15910 LUT3 F8 (AB)+C + 15911 LUT4 00F4 ((aB)+C)d + 15912 LUT2 4 aB + 15913 LUT3 FE /ab\+C + 15914 LUT4 FE00 ((/ab\)+C)D + 15915 LUT3 E0 C/ab\ + 15916 LUT2 4 aB + 15917 LUT2 8 AB + 15918 LUT4 4000 aBCD + 15919 LUT2 8 AB + 15920 LUT4 0100 abcD + 15921 LUT2 4 aB + 15922 LUT3 40 aBC + 15923 LUT2 8 AB + 15924 LUT4 F444 (aB)+(CD) + 15925 LUT3 F4 (aB)+C + 15926 LUT3 8F (AB)+c + 15927 LUT4 0D00 cD/Ab\ + 15928 LUT4 B0BB /aB\(d+C) + 15929 LUT2 B /aB\ + 15930 LUT3 B0 C/aB\ + 15931 LUT3 4F (aB)+c + 15932 LUT3 D0 C/Ab\ + 15933 LUT3 B0 C/aB\ + 15934 LUT4 B0BB /aB\(d+C) + 15935 LUT2 8 AB + 15936 LUT2 8 AB + 15937 LUT2 E /ab\ + 15938 LUT2 7 /AB\ + 15939 LUT4 7000 CD/AB\ + 15940 LUT3 80 ABC + 15941 LUT4 0777 /AB\(d+c) + 15942 LUT2 8 AB + 15943 LUT2 4 aB + 15944 LUT3 80 ABC + 15945 LUT4 8000 ABCD + 15946 LUT4 0700 cD/AB\ + 15947 LUT4 0777 /AB\(d+c) + 15948 LUT4 4000 aBCD + 15949 LUT3 80 ABC + 15950 LUT2 4 aB + 15951 LUT3 40 aBC + 15952 LUT3 80 ABC + 15953 LUT3 70 C/AB\ + 15954 LUT4 0777 /AB\(d+c) + 15955 LUT3 80 ABC + 15956 LUT4 4000 aBCD + 15957 LUT3 80 ABC + 15958 LUT4 0777 /AB\(d+c) + 15959 LUT2 8 AB + 15960 LUT4 F400 ((aB)+C)D + 15961 LUT3 40 aBC + 15962 LUT4 0BBB /aB\(d+c) + 15963 LUT2 8 AB + 15964 LUT4 4000 aBCD + 15965 LUT4 0777 /AB\(d+c) + 15966 LUT3 80 ABC + 15967 LUT3 10 abC + 15968 LUT4 0777 /AB\(d+c) + 15969 LUT3 40 aBC + 15970 LUT3 40 aBC + 15971 LUT4 0777 /AB\(d+c) + 15972 LUT3 10 abC + 15973 LUT2 8 AB + 15974 LUT3 40 aBC + 15975 LUT4 0777 /AB\(d+c) + 15976 LUT4 1000 abCD + 15977 LUT3 40 aBC + 15978 LUT4 7000 CD/AB\ + 15979 LUT4 8000 ABCD + 15980 LUT3 80 ABC + 15981 LUT3 B0 C/aB\ + 15982 LUT3 70 C/AB\ + 15983 LUT4 0BBB /aB\(d+c) + 15984 LUT3 80 ABC + 15985 LUT3 40 aBC + 15986 LUT3 10 abC + 15987 LUT3 10 abC + 15988 LUT4 0777 /AB\(d+c) + 15989 LUT4 0777 /AB\(d+c) + 15990 LUT3 80 ABC + 15991 LUT4 0777 /AB\(d+c) + 15992 LUT3 10 abC + 15993 LUT3 80 ABC + 15994 LUT4 0777 /AB\(d+c) + 15995 LUT3 10 abC + 15996 LUT2 8 AB + 15997 LUT4 0BBB /aB\(d+c) + 15998 LUT4 4000 aBCD + 15999 LUT3 40 aBC + 16000 LUT4 0777 /AB\(d+c) + 16001 LUT2 4 aB + 16002 LUT4 1000 abCD + 16003 LUT4 0777 /AB\(d+c) + 16004 LUT3 10 abC + 16005 LUT3 80 ABC + 16006 LUT3 10 abC + 16007 LUT2 8 AB + 16008 LUT2 8 AB + 16009 LUT4 0777 /AB\(d+c) + 16010 LUT2 8 AB + 16011 LUT4 8000 ABCD + 16012 LUT4 4000 aBCD + 16013 LUT2 7 /AB\ + 16014 LUT4 7000 CD/AB\ + 16015 LUT4 8000 ABCD + 16016 LUT4 0777 /AB\(d+c) + 16017 LUT4 0777 /AB\(d+c) + 16018 LUT4 8000 ABCD + 16019 LUT4 0777 /AB\(d+c) + 16020 LUT4 0777 /AB\(d+c) + 16021 LUT4 0777 /AB\(d+c) + 16022 LUT4 0777 /AB\(d+c) + 16023 LUT4 8000 ABCD + 16024 LUT4 0777 /AB\(d+c) + 16025 LUT4 0777 /AB\(d+c) + 16026 LUT4 0777 /AB\(d+c) + 16027 LUT4 0BBB /aB\(d+c) + 16028 LUT4 0777 /AB\(d+c) + 16029 LUT4 7000 CD/AB\ + 16030 LUT3 70 C/AB\ + 16031 LUT3 B0 C/aB\ + 16032 LUT4 0777 /AB\(d+c) + 16033 LUT4 0007 cd/AB\ + 16034 LUT4 4000 aBCD + 16035 LUT4 0777 /AB\(d+c) + 16036 LUT4 0777 /AB\(d+c) + 16037 LUT4 0777 /AB\(d+c) + 16038 LUT4 0777 /AB\(d+c) + 16039 LUT2 8 AB + 16040 LUT2 8 AB + 16041 LUT4 0777 /AB\(d+c) + 16042 LUT4 0777 /AB\(d+c) + 16043 LUT4 7FFF /AB\+c+d + 16044 LUT4 7000 CD/AB\ + 16045 LUT4 0777 /AB\(d+c) + 16046 LUT4 0777 /AB\(d+c) + 16047 LUT4 0777 /AB\(d+c) + 16048 LUT4 0777 /AB\(d+c) + 16049 LUT4 4000 aBCD + 16050 LUT4 0BBB /aB\(d+c) + 16051 LUT3 07 c/AB\ + 16052 LUT2 8 AB + 16053 LUT4 0777 /AB\(d+c) + 16054 LUT4 7000 CD/AB\ + 16055 LUT4 0777 /AB\(d+c) + 16056 LUT4 0777 /AB\(d+c) + 16057 LUT2 8 AB + 16058 LUT4 0777 /AB\(d+c) + 16059 LUT4 0777 /AB\(d+c) + 16060 LUT4 7000 CD/AB\ + 16061 LUT4 0777 /AB\(d+c) + 16062 LUT3 70 C/AB\ + 16063 LUT4 0777 /AB\(d+c) + 16064 LUT4 8000 ABCD + 16065 LUT4 8000 ABCD + 16066 LUT4 0777 /AB\(d+c) + 16067 LUT4 0777 /AB\(d+c) + 16068 LUT4 0777 /AB\(d+c) + 16069 LUT4 0BBB /aB\(d+c) + 16070 LUT4 0777 /AB\(d+c) + 16071 LUT4 0777 /AB\(d+c) + 16072 LUT4 0700 cD/AB\ + 16073 LUT3 40 aBC + 16074 LUT4 0777 /AB\(d+c) + 16075 LUT4 8000 ABCD + 16076 LUT4 0777 /AB\(d+c) + 16077 LUT4 0777 /AB\(d+c) + 16078 LUT4 0700 cD/AB\ + 16079 LUT4 0777 /AB\(d+c) + 16080 LUT2 8 AB + 16081 LUT3 10 abC + 16082 LUT4 8000 ABCD + 16083 LUT2 8 AB + 16084 LUT4 0777 /AB\(d+c) + 16085 LUT4 0777 /AB\(d+c) + 16086 LUT3 80 ABC + 16087 LUT3 70 C/AB\ + 16088 LUT4 0777 /AB\(d+c) + 16089 LUT4 0777 /AB\(d+c) + 16090 LUT4 7077 /AB\(d+C) + 16091 LUT4 0777 /AB\(d+c) + 16092 LUT4 0777 /AB\(d+c) + 16093 LUT3 70 C/AB\ + 16094 LUT4 7000 CD/AB\ + 16095 LUT4 0777 /AB\(d+c) + 16096 LUT4 0777 /AB\(d+c) + 16097 LUT4 0777 /AB\(d+c) + 16098 LUT4 0777 /AB\(d+c) + 16099 LUT4 0777 /AB\(d+c) + 16100 LUT3 70 C/AB\ + 16101 LUT4 0777 /AB\(d+c) + 16102 LUT4 0777 /AB\(d+c) + 16103 LUT4 8000 ABCD + 16104 LUT4 0777 /AB\(d+c) + 16105 LUT4 0777 /AB\(d+c) + 16106 LUT4 0BBB /aB\(d+c) + 16107 LUT4 0777 /AB\(d+c) + 16108 LUT3 80 ABC + 16109 LUT3 7F /AB\+c + 16110 LUT3 80 ABC + 16111 LUT3 70 C/AB\ + 16112 LUT4 0777 /AB\(d+c) + 16113 LUT4 0777 /AB\(d+c) + 16114 LUT4 0777 /AB\(d+c) + 16115 LUT4 8000 ABCD + 16116 LUT4 0777 /AB\(d+c) + 16117 LUT4 0777 /AB\(d+c) + 16118 LUT4 0700 cD/AB\ + 16119 LUT4 8F00 ((AB)+c)D + 16120 LUT4 0777 /AB\(d+c) + 16121 LUT4 0777 /AB\(d+c) + 16122 LUT4 8000 ABCD + 16123 LUT4 8000 ABCD + 16124 LUT4 8000 ABCD + 16125 LUT4 0BBB /aB\(d+c) + 16126 LUT4 0777 /AB\(d+c) + 16127 LUT4 0777 /AB\(d+c) + 16128 LUT4 0777 /AB\(d+c) + 16129 LUT3 70 C/AB\ + 16130 LUT4 0777 /AB\(d+c) + 16131 LUT4 0777 /AB\(d+c) + 16132 LUT4 0777 /AB\(d+c) + 16133 LUT4 0777 /AB\(d+c) + 16134 LUT4 0BBB /aB\(d+c) + 16135 LUT4 7000 CD/AB\ + 16136 LUT3 70 C/AB\ + 16137 LUT4 0777 /AB\(d+c) + 16138 LUT4 0777 /AB\(d+c) + 16139 LUT3 7F /AB\+c + 16140 LUT4 8000 ABCD + 16141 LUT4 8000 ABCD + 16142 LUT4 0777 /AB\(d+c) + 16143 LUT4 0777 /AB\(d+c) + 16144 LUT4 0777 /AB\(d+c) + 16145 LUT4 0BBB /aB\(d+c) + 16146 LUT3 70 C/AB\ + 16147 LUT4 0777 /AB\(d+c) + 16148 LUT4 0777 /AB\(d+c) + 16149 LUT4 0777 /AB\(d+c) + 16150 LUT4 0777 /AB\(d+c) + 16151 LUT4 7000 CD/AB\ + 16152 LUT4 0777 /AB\(d+c) + 16153 LUT4 0777 /AB\(d+c) + 16154 LUT3 70 C/AB\ + 16155 LUT4 0777 /AB\(d+c) + 16156 LUT4 0777 /AB\(d+c) + 16157 LUT4 0777 /AB\(d+c) + 16158 LUT4 8000 ABCD + 16159 LUT4 0777 /AB\(d+c) + 16160 LUT4 0777 /AB\(d+c) + 16161 LUT4 0777 /AB\(d+c) + 16162 LUT4 0777 /AB\(d+c) + 16163 LUT4 0777 /AB\(d+c) + 16164 LUT2 7 /AB\ + 16165 LUT4 8000 ABCD + 16166 LUT4 8000 ABCD + 16167 LUT4 0777 /AB\(d+c) + 16168 LUT4 0777 /AB\(d+c) + 16169 LUT4 7000 CD/AB\ + 16170 LUT4 0777 /AB\(d+c) + 16171 LUT4 0777 /AB\(d+c) + 16172 LUT4 8000 ABCD + 16173 LUT4 0BBB /aB\(d+c) + 16174 LUT4 0777 /AB\(d+c) + 16175 LUT4 0777 /AB\(d+c) + 16176 LUT4 0BBB /aB\(d+c) + 16177 LUT4 0BBB /aB\(d+c) + 16178 LUT4 7000 CD/AB\ + 16179 LUT4 0777 /AB\(d+c) + 16180 LUT3 70 C/AB\ + 16181 LUT4 0777 /AB\(d+c) + 16182 LUT4 0777 /AB\(d+c) + 16183 LUT4 0777 /AB\(d+c) + 16184 LUT4 8000 ABCD + 16185 LUT4 0777 /AB\(d+c) + 16186 LUT3 70 C/AB\ + 16187 LUT4 0777 /AB\(d+c) + 16188 LUT4 0777 /AB\(d+c) + 16189 LUT4 0777 /AB\(d+c) + 16190 LUT4 7FFF /AB\+c+d + 16191 LUT4 8000 ABCD + 16192 LUT4 0777 /AB\(d+c) + 16193 LUT4 0700 cD/AB\ + 16194 LUT4 0777 /AB\(d+c) + 16195 LUT4 0777 /AB\(d+c) + 16196 LUT4 0777 /AB\(d+c) + 16197 LUT4 8000 ABCD + 16198 LUT4 8000 ABCD + 16199 LUT4 8000 ABCD + 16200 LUT4 0777 /AB\(d+c) + 16201 LUT4 0777 /AB\(d+c) + 16202 LUT4 0777 /AB\(d+c) + 16203 LUT4 0BBB /aB\(d+c) + 16204 LUT2 8 AB + 16205 LUT4 0777 /AB\(d+c) + 16206 LUT4 0777 /AB\(d+c) + 16207 LUT4 0777 /AB\(d+c) + 16208 LUT4 0777 /AB\(d+c) + 16209 LUT2 4 aB + 16210 LUT4 0700 cD/AB\ + 16211 LUT4 0777 /AB\(d+c) + 16212 LUT4 8F00 ((AB)+c)D + 16213 LUT4 0777 /AB\(d+c) + 16214 LUT4 0BBB /aB\(d+c) + 16215 LUT2 8 AB + 16216 LUT4 0777 /AB\(d+c) + 16217 LUT4 0777 /AB\(d+c) + 16218 LUT4 0700 cD/AB\ + 16219 LUT4 0777 /AB\(d+c) + 16220 LUT2 8 AB + 16221 LUT3 7F /AB\+c + 16222 LUT3 70 C/AB\ + 16223 LUT4 7000 CD/AB\ + 16224 LUT4 0777 /AB\(d+c) + 16225 LUT4 0777 /AB\(d+c) + 16226 LUT4 0777 /AB\(d+c) + 16227 LUT4 0777 /AB\(d+c) + 16228 LUT4 0777 /AB\(d+c) + 16229 LUT4 0BBB /aB\(d+c) + 16230 LUT4 8000 ABCD + 16231 LUT4 0777 /AB\(d+c) + 16232 LUT4 0777 /AB\(d+c) + 16233 LUT4 0777 /AB\(d+c) + 16234 LUT4 0777 /AB\(d+c) + 16235 LUT4 0700 cD/AB\ + 16236 LUT4 0777 /AB\(d+c) + 16237 LUT4 8000 ABCD + 16238 LUT4 0777 /AB\(d+c) + 16239 LUT4 0777 /AB\(d+c) + 16240 LUT4 7000 CD/AB\ + 16241 LUT4 0BBB /aB\(d+c) + 16242 LUT4 0777 /AB\(d+c) + 16243 LUT4 0777 /AB\(d+c) + 16244 LUT4 8FFF (AB)+c+d + 16245 LUT3 80 ABC + 16246 LUT4 7000 CD/AB\ + 16247 LUT4 0777 /AB\(d+c) + 16248 LUT3 70 C/AB\ + 16249 LUT4 0777 /AB\(d+c) + 16250 LUT4 0777 /AB\(d+c) + 16251 LUT4 0777 /AB\(d+c) + 16252 LUT4 8000 ABCD + 16253 LUT4 0777 /AB\(d+c) + 16254 LUT4 0BBB /aB\(d+c) + 16255 LUT4 0777 /AB\(d+c) + 16256 LUT4 0777 /AB\(d+c) + 16257 LUT4 0777 /AB\(d+c) + 16258 LUT4 7077 /AB\(d+C) + 16259 LUT4 8000 ABCD + 16260 LUT4 0777 /AB\(d+c) + 16261 LUT4 0777 /AB\(d+c) + 16262 LUT4 0777 /AB\(d+c) + 16263 LUT4 0777 /AB\(d+c) + 16264 LUT3 70 C/AB\ + 16265 LUT3 70 C/AB\ + 16266 LUT4 0BBB /aB\(d+c) + 16267 LUT3 7F /AB\+c + 16268 LUT4 7000 CD/AB\ + 16269 LUT3 80 ABC + 16270 LUT3 80 ABC + 16271 LUT4 0777 /AB\(d+c) + 16272 LUT4 7000 CD/AB\ + 16273 LUT4 0777 /AB\(d+c) + 16274 LUT4 0777 /AB\(d+c) + 16275 LUT4 0777 /AB\(d+c) + 16276 LUT4 8000 ABCD + 16277 LUT4 0777 /AB\(d+c) + 16278 LUT4 0777 /AB\(d+c) + 16279 LUT4 0BBB /aB\(d+c) + 16280 LUT4 0777 /AB\(d+c) + 16281 LUT4 7000 CD/AB\ + 16282 LUT4 0777 /AB\(d+c) + 16283 LUT4 0777 /AB\(d+c) + 16284 LUT4 0777 /AB\(d+c) + 16285 LUT4 7000 CD/AB\ + 16286 LUT4 0D00 cD/Ab\ + 16287 LUT4 8F00 ((AB)+c)D + 16288 LUT4 0777 /AB\(d+c) + 16289 LUT4 00BF ((/aB\)+c)d + 16290 LUT4 7077 /AB\(d+C) + 16291 LUT4 0777 /AB\(d+c) + 16292 LUT4 8FFF (AB)+c+d + 16293 LUT3 80 ABC + 16294 LUT4 7000 CD/AB\ + 16295 LUT4 0777 /AB\(d+c) + 16296 LUT4 7000 CD/AB\ + 16297 LUT4 8000 ABCD + 16298 LUT4 0777 /AB\(d+c) + 16299 LUT4 0777 /AB\(d+c) + 16300 LUT4 0777 /AB\(d+c) + 16301 LUT4 0777 /AB\(d+c) + 16302 LUT3 70 C/AB\ + 16303 LUT4 0777 /AB\(d+c) + 16304 LUT4 8000 ABCD + 16305 LUT4 0700 cD/AB\ + 16306 LUT4 0777 /AB\(d+c) + 16307 LUT4 8F00 ((AB)+c)D + 16308 LUT3 0D c/Ab\ + 16309 LUT4 0777 /AB\(d+c) + 16310 LUT4 0BBB /aB\(d+c) + 16311 LUT4 0777 /AB\(d+c) + 16312 LUT4 0777 /AB\(d+c) + 16313 LUT4 0BBB /aB\(d+c) + 16314 LUT3 70 C/AB\ + 16315 LUT3 70 C/AB\ + 16316 LUT4 0777 /AB\(d+c) + 16317 LUT3 7F /AB\+c + 16318 LUT4 7000 CD/AB\ + 16319 LUT4 8000 ABCD + 16320 LUT4 0777 /AB\(d+c) + 16321 LUT4 0777 /AB\(d+c) + 16322 LUT4 0777 /AB\(d+c) + 16323 LUT4 0777 /AB\(d+c) + 16324 LUT3 70 C/AB\ + 16325 LUT4 0777 /AB\(d+c) + 16326 LUT4 7077 /AB\(d+C) + 16327 LUT4 7077 /AB\(d+C) + 16328 LUT4 0BBB /aB\(d+c) + 16329 LUT4 0777 /AB\(d+c) + 16330 LUT4 8000 ABCD + 16331 LUT4 0777 /AB\(d+c) + 16332 LUT4 0777 /AB\(d+c) + 16333 LUT4 0BBB /aB\(d+c) + 16334 LUT4 0777 /AB\(d+c) + 16335 LUT4 0777 /AB\(d+c) + 16336 LUT4 7FFF /AB\+c+d + 16337 LUT3 80 ABC + 16338 LUT3 80 ABC + 16339 LUT4 0700 cD/AB\ + 16340 LUT4 0BBB /aB\(d+c) + 16341 LUT4 8F00 ((AB)+c)D + 16342 LUT3 70 C/AB\ + 16343 LUT4 0777 /AB\(d+c) + 16344 LUT4 0777 /AB\(d+c) + 16345 LUT4 7077 /AB\(d+C) + 16346 LUT3 80 ABC + 16347 LUT3 B0 C/aB\ + 16348 LUT4 0777 /AB\(d+c) + 16349 LUT4 0777 /AB\(d+c) + 16350 LUT4 0777 /AB\(d+c) + 16351 LUT3 80 ABC + 16352 LUT4 0777 /AB\(d+c) + 16353 LUT4 0777 /AB\(d+c) + 16354 LUT3 70 C/AB\ + 16355 LUT4 0777 /AB\(d+c) + 16356 LUT3 70 C/AB\ + 16357 LUT4 7000 CD/AB\ + 16358 LUT4 0777 /AB\(d+c) + 16359 LUT4 0777 /AB\(d+c) + 16360 LUT4 0777 /AB\(d+c) + 16361 LUT4 0777 /AB\(d+c) + 16362 LUT4 8FFF (AB)+c+d + 16363 LUT4 8000 ABCD + 16364 LUT4 8000 ABCD + 16365 LUT3 80 ABC + 16366 LUT3 70 C/AB\ + 16367 LUT4 0777 /AB\(d+c) + 16368 LUT4 0777 /AB\(d+c) + 16369 LUT4 0777 /AB\(d+c) + 16370 LUT4 0777 /AB\(d+c) + 16371 LUT3 70 C/AB\ + 16372 LUT4 0777 /AB\(d+c) + 16373 LUT4 0BBB /aB\(d+c) + 16374 LUT4 0777 /AB\(d+c) + 16375 LUT4 0777 /AB\(d+c) + 16376 LUT4 0BBB /aB\(d+c) + 16377 LUT4 0BBB /aB\(d+c) + 16378 LUT4 0777 /AB\(d+c) + 16379 LUT4 7000 CD/AB\ + 16380 LUT4 0777 /AB\(d+c) + 16381 LUT4 0777 /AB\(d+c) + 16382 LUT4 7000 CD/AB\ + 16383 LUT4 8000 ABCD + 16384 LUT4 7000 CD/AB\ + 16385 LUT4 8000 ABCD + 16386 LUT4 0777 /AB\(d+c) + 16387 LUT4 0777 /AB\(d+c) + 16388 LUT4 0777 /AB\(d+c) + 16389 LUT4 0777 /AB\(d+c) + 16390 LUT3 70 C/AB\ + 16391 LUT4 0BBB /aB\(d+c) + 16392 LUT4 7000 CD/AB\ + 16393 LUT4 7077 /AB\(d+C) + 16394 LUT4 0777 /AB\(d+c) + 16395 LUT4 0777 /AB\(d+c) + 16396 LUT4 0BBB /aB\(d+c) + 16397 LUT4 0777 /AB\(d+c) + 16398 LUT4 0777 /AB\(d+c) + 16399 LUT4 0777 /AB\(d+c) + 16400 LUT4 0777 /AB\(d+c) + 16401 LUT4 8000 ABCD + 16402 LUT4 0777 /AB\(d+c) + 16403 LUT4 8000 ABCD + 16404 LUT4 8000 ABCD + 16405 LUT4 0777 /AB\(d+c) + 16406 LUT4 0777 /AB\(d+c) + 16407 LUT4 0BBB /aB\(d+c) + 16408 LUT4 0777 /AB\(d+c) + 16409 LUT4 0777 /AB\(d+c) + 16410 LUT3 70 C/AB\ + 16411 LUT4 7077 /AB\(d+C) + 16412 LUT4 0777 /AB\(d+c) + 16413 LUT4 8000 ABCD + 16414 LUT4 0777 /AB\(d+c) + 16415 LUT4 0777 /AB\(d+c) + 16416 LUT4 0777 /AB\(d+c) + 16417 LUT4 0BBB /aB\(d+c) + 16418 LUT4 0777 /AB\(d+c) + 16419 LUT4 0BBB /aB\(d+c) + 16420 LUT4 8000 ABCD + 16421 LUT4 8000 ABCD + 16422 LUT3 80 ABC + 16423 LUT3 70 C/AB\ + 16424 LUT4 0777 /AB\(d+c) + 16425 LUT4 0777 /AB\(d+c) + 16426 LUT4 7077 /AB\(d+C) + 16427 LUT4 0777 /AB\(d+c) + 16428 LUT3 70 C/AB\ + 16429 LUT4 0777 /AB\(d+c) + 16430 LUT4 0BBB /aB\(d+c) + 16431 LUT4 0777 /AB\(d+c) + 16432 LUT4 0777 /AB\(d+c) + 16433 LUT4 8000 ABCD + 16434 LUT4 0BBB /aB\(d+c) + 16435 LUT4 0777 /AB\(d+c) + 16436 LUT4 0BBB /aB\(d+c) + 16437 LUT4 0777 /AB\(d+c) + 16438 LUT4 0777 /AB\(d+c) + 16439 LUT4 8FFF (AB)+c+d + 16440 LUT4 8000 ABCD + 16441 LUT4 8000 ABCD + 16442 LUT3 80 ABC + 16443 LUT3 70 C/AB\ + 16444 LUT4 0BBB /aB\(d+c) + 16445 LUT4 0BBB /aB\(d+c) + 16446 LUT4 0777 /AB\(d+c) + 16447 LUT4 0777 /AB\(d+c) + 16448 LUT4 0777 /AB\(d+c) + 16449 LUT3 70 C/AB\ + 16450 LUT4 0777 /AB\(d+c) + 16451 LUT4 0777 /AB\(d+c) + 16452 LUT4 0777 /AB\(d+c) + 16453 LUT4 8000 ABCD + 16454 LUT4 0777 /AB\(d+c) + 16455 LUT4 B0BB /aB\(d+C) + 16456 LUT4 7077 /AB\(d+C) + 16457 LUT3 70 C/AB\ + 16458 LUT3 70 C/AB\ + 16459 LUT4 0777 /AB\(d+c) + 16460 LUT4 0777 /AB\(d+c) + 16461 LUT4 7000 CD/AB\ + 16462 LUT4 0777 /AB\(d+c) + 16463 LUT4 0777 /AB\(d+c) + 16464 LUT4 8FFF (AB)+c+d + 16465 LUT4 0777 /AB\(d+c) + 16466 LUT4 0777 /AB\(d+c) + 16467 LUT4 8000 ABCD + 16468 LUT4 8000 ABCD + 16469 LUT4 0777 /AB\(d+c) + 16470 LUT4 0777 /AB\(d+c) + 16471 LUT4 0777 /AB\(d+c) + 16472 LUT4 0777 /AB\(d+c) + 16473 LUT4 0777 /AB\(d+c) + 16474 LUT4 0BBB /aB\(d+c) + 16475 LUT4 0BBB /aB\(d+c) + 16476 LUT4 0BBB /aB\(d+c) + 16477 LUT4 0777 /AB\(d+c) + 16478 LUT4 7000 CD/AB\ + 16479 LUT4 0777 /AB\(d+c) + 16480 LUT4 0777 /AB\(d+c) + 16481 LUT3 7F /AB\+c + 16482 LUT4 7000 CD/AB\ + 16483 LUT4 7000 CD/AB\ + 16484 LUT4 8000 ABCD + 16485 LUT4 0777 /AB\(d+c) + 16486 LUT4 0777 /AB\(d+c) + 16487 LUT4 0777 /AB\(d+c) + 16488 LUT4 0777 /AB\(d+c) + 16489 LUT3 B0 C/aB\ + 16490 LUT4 0777 /AB\(d+c) + 16491 LUT4 0777 /AB\(d+c) + 16492 LUT4 D000 CD/Ab\ + 16493 LUT4 0777 /AB\(d+c) + 16494 LUT4 0BBB /aB\(d+c) + 16495 LUT4 0777 /AB\(d+c) + 16496 LUT4 7000 CD/AB\ + 16497 LUT4 0700 cD/AB\ + 16498 LUT4 0777 /AB\(d+c) + 16499 LUT3 70 C/AB\ + 16500 LUT4 35FF (c?b:a)+d + 16501 LUT4 F3F5 DC?a:b:1:1 + 16502 LUT4 0777 /AB\(d+c) + 16503 LUT4 0777 /AB\(d+c) + 16504 LUT4 8FFF (AB)+c+d + 16505 LUT4 8000 ABCD + 16506 LUT4 0777 /AB\(d+c) + 16507 LUT4 0777 /AB\(d+c) + 16508 LUT4 8000 ABCD + 16509 LUT3 70 C/AB\ + 16510 LUT3 07 c/AB\ + 16511 LUT4 8000 ABCD + 16512 LUT4 0777 /AB\(d+c) + 16513 LUT4 0777 /AB\(d+c) + 16514 LUT4 0777 /AB\(d+c) + 16515 LUT4 0BBB /aB\(d+c) + 16516 LUT4 0777 /AB\(d+c) + 16517 LUT4 0777 /AB\(d+c) + 16518 LUT4 0777 /AB\(d+c) + 16519 LUT4 0777 /AB\(d+c) + 16520 LUT4 0BBB /aB\(d+c) + 16521 LUT4 7000 CD/AB\ + 16522 LUT4 0777 /AB\(d+c) + 16523 LUT4 0777 /AB\(d+c) + 16524 LUT4 8FFF (AB)+c+d + 16525 LUT4 0777 /AB\(d+c) + 16526 LUT4 8000 ABCD + 16527 LUT3 70 C/AB\ + 16528 LUT3 07 c/AB\ + 16529 LUT3 80 ABC + 16530 LUT3 70 C/AB\ + 16531 LUT4 0777 /AB\(d+c) + 16532 LUT4 0BBB /aB\(d+c) + 16533 LUT4 0777 /AB\(d+c) + 16534 LUT4 0777 /AB\(d+c) + 16535 LUT4 0777 /AB\(d+c) + 16536 LUT4 0777 /AB\(d+c) + 16537 LUT4 0777 /AB\(d+c) + 16538 LUT4 0BBB /aB\(d+c) + 16539 LUT4 0777 /AB\(d+c) + 16540 LUT4 7000 CD/AB\ + 16541 LUT4 0BBB /aB\(d+c) + 16542 LUT4 0777 /AB\(d+c) + 16543 LUT4 8FFF (AB)+c+d + 16544 LUT4 8000 ABCD + 16545 LUT4 0777 /AB\(d+c) + 16546 LUT4 0777 /AB\(d+c) + 16547 LUT4 8000 ABCD + 16548 LUT3 B0 C/aB\ + 16549 LUT3 07 c/AB\ + 16550 LUT3 80 ABC + 16551 LUT3 70 C/AB\ + 16552 LUT4 0777 /AB\(d+c) + 16553 LUT4 0777 /AB\(d+c) + 16554 LUT4 0777 /AB\(d+c) + 16555 LUT4 0BBB /aB\(d+c) + 16556 LUT4 0777 /AB\(d+c) + 16557 LUT4 0BBB /aB\(d+c) + 16558 LUT4 0777 /AB\(d+c) + 16559 LUT4 0777 /AB\(d+c) + 16560 LUT4 7000 CD/AB\ + 16561 LUT4 0777 /AB\(d+c) + 16562 LUT4 0777 /AB\(d+c) + 16563 LUT4 8FFF (AB)+c+d + 16564 LUT4 8000 ABCD + 16565 LUT4 0777 /AB\(d+c) + 16566 LUT4 0777 /AB\(d+c) + 16567 LUT4 8000 ABCD + 16568 LUT3 70 C/AB\ + 16569 LUT3 07 c/AB\ + 16570 LUT4 8000 ABCD + 16571 LUT4 0777 /AB\(d+c) + 16572 LUT4 0777 /AB\(d+c) + 16573 LUT4 0777 /AB\(d+c) + 16574 LUT4 0777 /AB\(d+c) + 16575 LUT4 0BBB /aB\(d+c) + 16576 LUT4 0777 /AB\(d+c) + 16577 LUT4 7077 /AB\(d+C) + 16578 LUT4 0BBB /aB\(d+c) + 16579 LUT4 0777 /AB\(d+c) + 16580 LUT4 7000 CD/AB\ + 16581 LUT4 0777 /AB\(d+c) + 16582 LUT4 0777 /AB\(d+c) + 16583 LUT4 8FFF (AB)+c+d + 16584 LUT4 8000 ABCD + 16585 LUT4 0777 /AB\(d+c) + 16586 LUT4 8000 ABCD + 16587 LUT3 D0 C/Ab\ + 16588 LUT3 07 c/AB\ + 16589 LUT3 80 ABC + 16590 LUT3 70 C/AB\ + 16591 LUT4 0BBB /aB\(d+c) + 16592 LUT4 0777 /AB\(d+c) + 16593 LUT4 0777 /AB\(d+c) + 16594 LUT4 0777 /AB\(d+c) + 16595 LUT4 0777 /AB\(d+c) + 16596 LUT4 0777 /AB\(d+c) + 16597 LUT4 0777 /AB\(d+c) + 16598 LUT4 0777 /AB\(d+c) + 16599 LUT4 0777 /AB\(d+c) + 16600 LUT4 7000 CD/AB\ + 16601 LUT4 0777 /AB\(d+c) + 16602 LUT4 0BBB /aB\(d+c) + 16603 LUT4 8FFF (AB)+c+d + 16604 LUT4 8000 ABCD + 16605 LUT4 0777 /AB\(d+c) + 16606 LUT4 8000 ABCD + 16607 LUT4 8000 ABCD + 16608 LUT4 0777 /AB\(d+c) + 16609 LUT4 0777 /AB\(d+c) + 16610 LUT4 0BBB /aB\(d+c) + 16611 LUT4 0777 /AB\(d+c) + 16612 LUT4 0777 /AB\(d+c) + 16613 LUT4 0777 /AB\(d+c) + 16614 LUT4 0777 /AB\(d+c) + 16615 LUT4 0777 /AB\(d+c) + 16616 LUT4 0BBB /aB\(d+c) + 16617 LUT4 0BBB /aB\(d+c) + 16618 LUT4 0777 /AB\(d+c) + 16619 LUT3 70 C/AB\ + 16620 LUT3 70 C/AB\ + 16621 LUT4 0777 /AB\(d+c) + 16622 LUT4 8000 ABCD + 16623 LUT4 0777 /AB\(d+c) + 16624 LUT4 8000 ABCD + 16625 LUT4 0777 /AB\(d+c) + 16626 LUT4 8000 ABCD + 16627 LUT4 0777 /AB\(d+c) + 16628 LUT4 0777 /AB\(d+c) + 16629 LUT4 0BBB /aB\(d+c) + 16630 LUT4 0777 /AB\(d+c) + 16631 LUT4 0777 /AB\(d+c) + 16632 LUT4 0777 /AB\(d+c) + 16633 LUT4 0BBB /aB\(d+c) + 16634 LUT4 0BBB /aB\(d+c) + 16635 LUT4 0777 /AB\(d+c) + 16636 LUT4 0777 /AB\(d+c) + 16637 LUT4 0777 /AB\(d+c) + 16638 LUT3 7F /AB\+c + 16639 LUT4 7000 CD/AB\ + 16640 LUT4 8000 ABCD + 16641 LUT4 7000 CD/AB\ + 16642 LUT4 8000 ABCD + 16643 LUT4 0777 /AB\(d+c) + 16644 LUT4 0777 /AB\(d+c) + 16645 LUT4 0777 /AB\(d+c) + 16646 LUT4 0777 /AB\(d+c) + 16647 LUT3 70 C/AB\ + 16648 LUT4 0777 /AB\(d+c) + 16649 LUT4 0777 /AB\(d+c) + 16650 LUT4 7000 CD/AB\ + 16651 LUT4 0BBB /aB\(d+c) + 16652 LUT4 0BBB /aB\(d+c) + 16653 LUT4 0777 /AB\(d+c) + 16654 LUT4 0777 /AB\(d+c) + 16655 LUT4 7000 CD/AB\ + 16656 LUT4 0700 cD/AB\ + 16657 LUT4 0BBB /aB\(d+c) + 16658 LUT3 70 C/AB\ + 16659 LUT4 F53F DC?1:a:b:1 + 16660 LUT4 3FF5 DC?a:1:1:b + 16661 LUT4 0777 /AB\(d+c) + 16662 LUT4 0777 /AB\(d+c) + 16663 LUT2 7 /AB\ + 16664 LUT4 7000 CD/AB\ + 16665 LUT3 80 ABC + 16666 LUT4 8000 ABCD + 16667 LUT4 0007 cd/AB\ + 16668 LUT3 70 C/AB\ + 16669 LUT4 35FF (c?b:a)+d + 16670 LUT4 F3F5 DC?a:b:1:1 + 16671 LUT4 0777 /AB\(d+c) + 16672 LUT4 0777 /AB\(d+c) + 16673 LUT4 0777 /AB\(d+c) + 16674 LUT4 8000 ABCD + 16675 LUT4 0777 /AB\(d+c) + 16676 LUT4 0777 /AB\(d+c) + 16677 LUT4 0BBB /aB\(d+c) + 16678 LUT4 0777 /AB\(d+c) + 16679 LUT4 7000 CD/AB\ + 16680 LUT4 0777 /AB\(d+c) + 16681 LUT4 0777 /AB\(d+c) + 16682 LUT4 0777 /AB\(d+c) + 16683 LUT4 8000 ABCD + 16684 LUT4 0777 /AB\(d+c) + 16685 LUT3 70 C/AB\ + 16686 LUT4 0777 /AB\(d+c) + 16687 LUT4 0777 /AB\(d+c) + 16688 LUT4 B0BB /aB\(d+C) + 16689 LUT3 7F /AB\+c + 16690 LUT4 7000 CD/AB\ + 16691 LUT4 8000 ABCD + 16692 LUT4 0777 /AB\(d+c) + 16693 LUT4 0777 /AB\(d+c) + 16694 LUT4 0777 /AB\(d+c) + 16695 LUT4 0BBB /aB\(d+c) + 16696 LUT3 70 C/AB\ + 16697 LUT4 0777 /AB\(d+c) + 16698 LUT4 1000 abCD + 16699 LUT4 0777 /AB\(d+c) + 16700 LUT4 0777 /AB\(d+c) + 16701 LUT4 0777 /AB\(d+c) + 16702 LUT4 0777 /AB\(d+c) + 16703 LUT4 8000 ABCD + 16704 LUT4 0777 /AB\(d+c) + 16705 LUT4 0777 /AB\(d+c) + 16706 LUT4 0777 /AB\(d+c) + 16707 LUT4 7077 /AB\(d+C) + 16708 LUT4 0777 /AB\(d+c) + 16709 LUT4 8FFF (AB)+c+d + 16710 LUT4 0777 /AB\(d+c) + 16711 LUT4 0777 /AB\(d+c) + 16712 LUT4 8000 ABCD + 16713 LUT4 8000 ABCD + 16714 LUT4 0777 /AB\(d+c) + 16715 LUT4 0777 /AB\(d+c) + 16716 LUT4 0777 /AB\(d+c) + 16717 LUT4 0777 /AB\(d+c) + 16718 LUT4 0777 /AB\(d+c) + 16719 LUT4 0777 /AB\(d+c) + 16720 LUT4 0BBB /aB\(d+c) + 16721 LUT4 0BBB /aB\(d+c) + 16722 LUT4 0BBB /aB\(d+c) + 16723 LUT4 0777 /AB\(d+c) + 16724 LUT3 70 C/AB\ + 16725 LUT3 70 C/AB\ + 16726 LUT4 0777 /AB\(d+c) + 16727 LUT3 80 ABC + 16728 LUT3 80 ABC + 16729 LUT2 8 AB + 16730 LUT4 4000 aBCD + 16731 LUT3 10 abC + 16732 LUT2 8 AB + 16733 LUT2 8 AB + 16734 LUT2 8 AB + 16735 LUT2 8 AB + 16736 LUT2 E /ab\ + 16737 LUT4 0D00 cD/Ab\ + 16738 LUT2 E /ab\ + 16739 LUT2 E /ab\ + 16740 LUT4 0D00 cD/Ab\ + 16741 LUT2 E /ab\ + 16742 LUT2 E /ab\ + 16743 LUT4 0D00 cD/Ab\ + 16744 LUT2 E /ab\ + 16745 LUT2 E /ab\ + 16746 LUT4 0D00 cD/Ab\ + 16747 LUT2 E /ab\ + 16748 LUT4 D000 CD/Ab\ + 16749 LUT4 8000 ABCD + 16750 LUT4 D000 CD/Ab\ + 16751 LUT4 D000 CD/Ab\ + 16752 LUT4 D000 CD/Ab\ + 16753 LUT2 4 aB + 16754 LUT2 4 aB + 16755 LUT2 4 aB + 16756 LUT2 4 aB + 16757 LUT4 8000 ABCD + 16758 LUT2 E /ab\ + 16759 LUT2 E /ab\ + 16760 LUT3 80 ABC + 16761 LUT2 B /aB\ + 16762 LUT3 80 ABC + 16763 LUT4 00EF ((/ab\)+c)d + 16764 LUT3 4F (aB)+c + 16765 LUT2 8 AB + 16766 LUT4 0777 /AB\(d+c) + 16767 LUT4 0100 abcD + 16768 LUT3 CA C?A:B + 16769 LUT3 4F (aB)+c + 16770 LUT4 0777 /AB\(d+c) + 16771 LUT3 CA C?A:B + 16772 LUT3 4F (aB)+c + 16773 LUT4 0777 /AB\(d+c) + 16774 LUT3 CA C?A:B + 16775 LUT3 4F (aB)+c + 16776 LUT4 0777 /AB\(d+c) + 16777 LUT3 CA C?A:B + 16778 LUT3 4F (aB)+c + 16779 LUT4 0777 /AB\(d+c) + 16780 LUT3 CA C?A:B + 16781 LUT3 4F (aB)+c + 16782 LUT4 0777 /AB\(d+c) + 16783 LUT3 CA C?A:B + 16784 LUT3 4F (aB)+c + 16785 LUT4 0777 /AB\(d+c) + 16786 LUT3 CA C?A:B + 16787 LUT3 4F (aB)+c + 16788 LUT4 0777 /AB\(d+c) + 16789 LUT3 CA C?A:B + 16790 LUT3 4F (aB)+c + 16791 LUT4 0777 /AB\(d+c) + 16792 LUT3 CA C?A:B + 16793 LUT3 4F (aB)+c + 16794 LUT4 0777 /AB\(d+c) + 16795 LUT3 CA C?A:B + 16796 LUT3 4F (aB)+c + 16797 LUT4 0777 /AB\(d+c) + 16798 LUT3 CA C?A:B + 16799 LUT3 4F (aB)+c + 16800 LUT4 0777 /AB\(d+c) + 16801 LUT3 CA C?A:B + 16802 LUT3 4F (aB)+c + 16803 LUT4 0777 /AB\(d+c) + 16804 LUT3 CA C?A:B + 16805 LUT3 4F (aB)+c + 16806 LUT4 0777 /AB\(d+c) + 16807 LUT3 CA C?A:B + 16808 LUT3 4F (aB)+c + 16809 LUT4 0777 /AB\(d+c) + 16810 LUT3 CA C?A:B + 16811 LUT3 4F (aB)+c + 16812 LUT4 0777 /AB\(d+c) + 16813 LUT3 CA C?A:B + 16814 LUT3 4F (aB)+c + 16815 LUT4 0777 /AB\(d+c) + 16816 LUT3 CA C?A:B + 16817 LUT3 4F (aB)+c + 16818 LUT4 0777 /AB\(d+c) + 16819 LUT3 CA C?A:B + 16820 LUT3 4F (aB)+c + 16821 LUT4 0777 /AB\(d+c) + 16822 LUT3 CA C?A:B + 16823 LUT3 4F (aB)+c + 16824 LUT4 0777 /AB\(d+c) + 16825 LUT3 CA C?A:B + 16826 LUT3 4F (aB)+c + 16827 LUT4 0777 /AB\(d+c) + 16828 LUT3 CA C?A:B + 16829 LUT3 4F (aB)+c + 16830 LUT4 0777 /AB\(d+c) + 16831 LUT3 CA C?A:B + 16832 LUT3 4F (aB)+c + 16833 LUT4 0777 /AB\(d+c) + 16834 LUT3 CA C?A:B + 16835 LUT3 4F (aB)+c + 16836 LUT4 0777 /AB\(d+c) + 16837 LUT3 CA C?A:B + 16838 LUT3 4F (aB)+c + 16839 LUT4 0777 /AB\(d+c) + 16840 LUT3 CA C?A:B + 16841 LUT3 4F (aB)+c + 16842 LUT4 0777 /AB\(d+c) + 16843 LUT3 CA C?A:B + 16844 LUT3 4F (aB)+c + 16845 LUT4 0777 /AB\(d+c) + 16846 LUT3 CA C?A:B + 16847 LUT3 4F (aB)+c + 16848 LUT4 0777 /AB\(d+c) + 16849 LUT3 CA C?A:B + 16850 LUT3 4F (aB)+c + 16851 LUT4 0777 /AB\(d+c) + 16852 LUT3 CA C?A:B + 16853 LUT3 4F (aB)+c + 16854 LUT4 0777 /AB\(d+c) + 16855 LUT3 CA C?A:B + 16856 LUT3 4F (aB)+c + 16857 LUT4 0777 /AB\(d+c) + 16858 LUT3 CA C?A:B + 16859 LUT2 4 aB + 16860 LUT4 0100 abcD + 16861 LUT4 8000 ABCD + 16862 LUT2 8 AB + 16863 LUT3 80 ABC + 16864 LUT4 8000 ABCD + 16865 LUT3 80 ABC + 16866 LUT3 80 ABC + 16867 LUT3 80 ABC + 16868 LUT3 80 ABC + 16869 LUT3 CA C?A:B + 16870 LUT3 F4 (aB)+C + 16871 LUT2 4 aB + 16872 LUT2 4 aB + 16873 LUT2 4 aB + 16874 LUT2 4 aB + 16875 LUT2 4 aB + 16876 LUT2 4 aB + 16877 LUT2 4 aB + 16878 LUT2 4 aB + 16879 LUT2 4 aB + 16880 LUT2 4 aB + 16881 LUT2 4 aB + 16882 LUT2 4 aB + 16883 LUT2 4 aB + 16884 LUT3 80 ABC + 16885 LUT4 8000 ABCD + 16886 LUT4 8000 ABCD + 16887 LUT2 E /ab\ + 16888 LUT2 8 AB + 16889 LUT3 8F (AB)+c + 16890 LUT3 70 C/AB\ + 16891 LUT4 0001 abcd + 16892 LUT4 7077 /AB\(d+C) + 16893 LUT2 4 aB + 16894 LUT4 1000 abCD + 16895 LUT4 8FFF (AB)+c+d + 16896 LUT3 70 C/AB\ + 16897 LUT4 7077 /AB\(d+C) + 16898 LUT4 0777 /AB\(d+c) + 16899 LUT3 80 ABC + 16900 LUT3 10 abC + 16901 LUT4 0B00 cD/aB\ + 16902 LUT3 A3 C?b:A + 16903 LUT3 7F /AB\+c + 16904 LUT4 0777 /AB\(d+c) + 16905 LUT4 0777 /AB\(d+c) + 16906 LUT4 7077 /AB\(d+C) + 16907 LUT4 8FFF (AB)+c+d + 16908 LUT3 70 C/AB\ + 16909 LUT4 7077 /AB\(d+C) + 16910 LUT4 0777 /AB\(d+c) + 16911 LUT4 8FFF (AB)+c+d + 16912 LUT4 0007 cd/AB\ + 16913 LUT2 8 AB + 16914 LUT2 8 AB + 16915 LUT4 0BBB /aB\(d+c) + 16916 LUT3 80 ABC + 16917 LUT4 1000 abCD + 16918 LUT3 80 ABC + 16919 LUT4 8FFF (AB)+c+d + 16920 LUT4 0007 cd/AB\ + 16921 LUT2 8 AB + 16922 LUT2 8 AB + 16923 LUT4 0BBB /aB\(d+c) + 16924 LUT4 8FFF (AB)+c+d + 16925 LUT4 000B cd/aB\ + 16926 LUT2 8 AB + 16927 LUT2 8 AB + 16928 LUT4 0777 /AB\(d+c) + 16929 LUT3 8F (AB)+c + 16930 LUT4 0700 cD/AB\ + 16931 LUT3 70 C/AB\ + 16932 LUT4 7077 /AB\(d+C) + 16933 LUT2 8 AB + 16934 LUT3 8F (AB)+c + 16935 LUT4 7000 CD/AB\ + 16936 LUT4 0777 /AB\(d+c) + 16937 LUT4 7077 /AB\(d+C) + 16938 LUT4 8FFF (AB)+c+d + 16939 LUT3 70 C/AB\ + 16940 LUT4 7077 /AB\(d+C) + 16941 LUT4 0777 /AB\(d+c) + 16942 LUT3 8F (AB)+c + 16943 LUT4 0700 cD/AB\ + 16944 LUT3 70 C/AB\ + 16945 LUT4 7077 /AB\(d+C) + 16946 LUT2 8 AB + 16947 LUT3 8F (AB)+c + 16948 LUT4 0700 cD/AB\ + 16949 LUT3 70 C/AB\ + 16950 LUT4 7077 /AB\(d+C) + 16951 LUT2 8 AB + 16952 LUT4 8FFF (AB)+c+d + 16953 LUT3 70 C/AB\ + 16954 LUT4 7077 /AB\(d+C) + 16955 LUT4 0777 /AB\(d+c) + 16956 LUT4 8FFF (AB)+c+d + 16957 LUT4 000B cd/aB\ + 16958 LUT2 8 AB + 16959 LUT2 8 AB + 16960 LUT4 0777 /AB\(d+c) + 16961 LUT3 8F (AB)+c + 16962 LUT4 0700 cD/AB\ + 16963 LUT3 70 C/AB\ + 16964 LUT4 7077 /AB\(d+C) + 16965 LUT2 8 AB + 16966 LUT4 8FFF (AB)+c+d + 16967 LUT4 0007 cd/AB\ + 16968 LUT2 8 AB + 16969 LUT2 8 AB + 16970 LUT4 0BBB /aB\(d+c) + 16971 LUT3 8F (AB)+c + 16972 LUT4 0700 cD/AB\ + 16973 LUT3 70 C/AB\ + 16974 LUT4 7077 /AB\(d+C) + 16975 LUT2 8 AB + 16976 LUT4 8FFF (AB)+c+d + 16977 LUT3 B0 C/aB\ + 16978 LUT4 0777 /AB\(d+c) + 16979 LUT4 0777 /AB\(d+c) + 16980 LUT3 8F (AB)+c + 16981 LUT4 0700 cD/AB\ + 16982 LUT3 70 C/AB\ + 16983 LUT4 7077 /AB\(d+C) + 16984 LUT2 8 AB + 16985 LUT4 8FFF (AB)+c+d + 16986 LUT3 70 C/AB\ + 16987 LUT4 7077 /AB\(d+C) + 16988 LUT4 0777 /AB\(d+c) + 16989 LUT3 8F (AB)+c + 16990 LUT4 7000 CD/AB\ + 16991 LUT4 0777 /AB\(d+c) + 16992 LUT4 7077 /AB\(d+C) + 16993 LUT4 8FFF (AB)+c+d + 16994 LUT4 0007 cd/AB\ + 16995 LUT2 8 AB + 16996 LUT2 8 AB + 16997 LUT4 0BBB /aB\(d+c) + 16998 LUT3 8F (AB)+c + 16999 LUT4 0700 cD/AB\ + 17000 LUT3 70 C/AB\ + 17001 LUT4 7077 /AB\(d+C) + 17002 LUT2 8 AB + 17003 LUT4 8FFF (AB)+c+d + 17004 LUT4 000B cd/aB\ + 17005 LUT2 8 AB + 17006 LUT2 8 AB + 17007 LUT4 0777 /AB\(d+c) + 17008 LUT4 8FFF (AB)+c+d + 17009 LUT4 000B cd/aB\ + 17010 LUT2 8 AB + 17011 LUT2 8 AB + 17012 LUT4 0777 /AB\(d+c) + 17013 LUT4 8FFF (AB)+c+d + 17014 LUT4 000B cd/aB\ + 17015 LUT2 8 AB + 17016 LUT2 8 AB + 17017 LUT4 0777 /AB\(d+c) + 17018 LUT4 8FFF (AB)+c+d + 17019 LUT4 0007 cd/AB\ + 17020 LUT2 8 AB + 17021 LUT2 8 AB + 17022 LUT4 0BBB /aB\(d+c) + 17023 LUT4 8FFF (AB)+c+d + 17024 LUT4 000B cd/aB\ + 17025 LUT2 8 AB + 17026 LUT2 8 AB + 17027 LUT4 0777 /AB\(d+c) + 17028 LUT3 7F /AB\+c + 17029 LUT4 0777 /AB\(d+c) + 17030 LUT4 0777 /AB\(d+c) + 17031 LUT4 7077 /AB\(d+C) + 17032 LUT4 8FFF (AB)+c+d + 17033 LUT4 0007 cd/AB\ + 17034 LUT2 8 AB + 17035 LUT2 8 AB + 17036 LUT4 0BBB /aB\(d+c) + 17037 LUT4 8FFF (AB)+c+d + 17038 LUT3 70 C/AB\ + 17039 LUT4 7077 /AB\(d+C) + 17040 LUT4 0777 /AB\(d+c) + 17041 LUT4 8FFF (AB)+c+d + 17042 LUT3 70 C/AB\ + 17043 LUT4 7077 /AB\(d+C) + 17044 LUT4 0777 /AB\(d+c) + 17045 LUT2 B /aB\ + 17046 LUT4 0BBB /aB\(d+c) + 17047 LUT4 007F ((/AB\)+c)d + 17048 LUT4 4000 aBCD + 17049 LUT4 FE00 ((/ab\)+C)D + 17050 LUT4 1000 abCD + 17051 LUT2 B /aB\ + 17052 LUT4 0BBB /aB\(d+c) + 17053 LUT4 F800 ((AB)+C)D + 17054 LUT3 4F (aB)+c + 17055 LUT4 0777 /AB\(d+c) + 17056 LUT3 8F (AB)+c + 17057 LUT4 7077 /AB\(d+C) + 17058 LUT3 F8 (AB)+C + 17059 LUT3 4F (aB)+c + 17060 LUT3 D0 C/Ab\ + 17061 LUT4 0777 /AB\(d+c) + 17062 LUT3 F4 (aB)+C + 17063 LUT3 40 aBC + 17064 LUT3 4F (aB)+c + 17065 LUT4 7077 /AB\(d+C) + 17066 LUT3 4F (aB)+c + 17067 LUT3 0D c/Ab\ + 17068 LUT3 4F (aB)+c + 17069 LUT4 0BBB /aB\(d+c) + 17070 LUT3 4F (aB)+c + 17071 LUT3 0B c/aB\ + 17072 LUT4 4F44 (aB)+(cD) + 17073 LUT4 4F44 (aB)+(cD) + 17074 LUT4 4F44 (aB)+(cD) + 17075 LUT4 4F44 (aB)+(cD) + 17076 LUT4 4F44 (aB)+(cD) + 17077 LUT4 4F44 (aB)+(cD) + 17078 LUT4 4F44 (aB)+(cD) + 17079 LUT4 4F44 (aB)+(cD) + 17080 LUT4 4F44 (aB)+(cD) + 17081 LUT4 4F44 (aB)+(cD) + 17082 LUT4 4F44 (aB)+(cD) + 17083 LUT4 4F44 (aB)+(cD) + 17084 LUT4 4F44 (aB)+(cD) + 17085 LUT4 4F44 (aB)+(cD) + 17086 LUT4 4F44 (aB)+(cD) + 17087 LUT4 4F44 (aB)+(cD) + 17088 LUT4 4F44 (aB)+(cD) + 17089 LUT4 4F44 (aB)+(cD) + 17090 LUT4 4F44 (aB)+(cD) + 17091 LUT4 4F44 (aB)+(cD) + 17092 LUT4 4F44 (aB)+(cD) + 17093 LUT4 4F44 (aB)+(cD) + 17094 LUT4 4F44 (aB)+(cD) + 17095 LUT3 4F (aB)+c + 17096 LUT3 0D c/Ab\ + 17097 LUT3 E0 C/ab\ + 17098 LUT4 F444 (aB)+(CD) + 17099 LUT3 4F (aB)+c + 17100 LUT3 0B c/aB\ + 17101 LUT3 4F (aB)+c + 17102 LUT3 0B c/aB\ + 17103 LUT3 4F (aB)+c + 17104 LUT3 0D c/Ab\ + 17105 LUT4 EF00 ((/ab\)+c)D + 17106 LUT3 F8 (AB)+C + 17107 LUT4 F2FF (Ab)+C+d + 17108 LUT4 B0BB /aB\(d+C) + 17109 LUT3 40 aBC + 17110 LUT2 4 aB + 17111 LUT2 7 /AB\ + 17112 LUT4 B0BB /aB\(d+C) + 17113 LUT4 B0BB /aB\(d+C) + 17114 LUT4 F2FF (Ab)+C+d + 17115 LUT4 B0BB /aB\(d+C) + 17116 LUT2 4 aB + 17117 LUT4 F2FF (Ab)+C+d + 17118 LUT4 B0BB /aB\(d+C) + 17119 LUT2 4 aB + 17120 LUT4 F2FF (Ab)+C+d + 17121 LUT4 B0BB /aB\(d+C) + 17122 LUT2 4 aB + 17123 LUT4 F2FF (Ab)+C+d + 17124 LUT4 B0BB /aB\(d+C) + 17125 LUT2 4 aB + 17126 LUT4 F2FF (Ab)+C+d + 17127 LUT4 B0BB /aB\(d+C) + 17128 LUT2 4 aB + 17129 LUT4 F2FF (Ab)+C+d + 17130 LUT4 B0BB /aB\(d+C) + 17131 LUT2 4 aB + 17132 LUT4 F2FF (Ab)+C+d + 17133 LUT4 B0BB /aB\(d+C) + 17134 LUT2 4 aB + 17135 LUT4 F2FF (Ab)+C+d + 17136 LUT4 B0BB /aB\(d+C) + 17137 LUT2 4 aB + 17138 LUT2 7 /AB\ + 17139 LUT4 B0BB /aB\(d+C) + 17140 LUT4 B0BB /aB\(d+C) + 17141 LUT4 F2FF (Ab)+C+d + 17142 LUT4 B0BB /aB\(d+C) + 17143 LUT2 4 aB + 17144 LUT4 F2FF (Ab)+C+d + 17145 LUT4 B0BB /aB\(d+C) + 17146 LUT2 4 aB + 17147 LUT4 F2FF (Ab)+C+d + 17148 LUT4 B0BB /aB\(d+C) + 17149 LUT2 4 aB + 17150 LUT4 F2FF (Ab)+C+d + 17151 LUT4 B0BB /aB\(d+C) + 17152 LUT2 4 aB + 17153 LUT4 F4FF (aB)+C+d + 17154 LUT4 B0BB /aB\(d+C) + 17155 LUT2 4 aB + 17156 LUT4 F2FF (Ab)+C+d + 17157 LUT4 B0BB /aB\(d+C) + 17158 LUT2 4 aB + 17159 LUT4 F2FF (Ab)+C+d + 17160 LUT4 B0BB /aB\(d+C) + 17161 LUT2 4 aB + 17162 LUT4 F2FF (Ab)+C+d + 17163 LUT4 B0BB /aB\(d+C) + 17164 LUT2 4 aB + 17165 LUT4 F2FF (Ab)+C+d + 17166 LUT4 B0BB /aB\(d+C) + 17167 LUT2 4 aB + 17168 LUT2 7 /AB\ + 17169 LUT4 B0BB /aB\(d+C) + 17170 LUT4 B0BB /aB\(d+C) + 17171 LUT4 F2FF (Ab)+C+d + 17172 LUT4 B0BB /aB\(d+C) + 17173 LUT2 4 aB + 17174 LUT2 7 /AB\ + 17175 LUT4 B0BB /aB\(d+C) + 17176 LUT4 B0BB /aB\(d+C) + 17177 LUT4 F2FF (Ab)+C+d + 17178 LUT4 B0BB /aB\(d+C) + 17179 LUT2 4 aB + 17180 LUT2 7 /AB\ + 17181 LUT4 B0BB /aB\(d+C) + 17182 LUT4 B0BB /aB\(d+C) + 17183 LUT4 F2FF (Ab)+C+d + 17184 LUT4 B0BB /aB\(d+C) + 17185 LUT2 4 aB + 17186 LUT2 7 /AB\ + 17187 LUT4 B0BB /aB\(d+C) + 17188 LUT4 B0BB /aB\(d+C) + 17189 LUT4 F2FF (Ab)+C+d + 17190 LUT4 B0BB /aB\(d+C) + 17191 LUT2 4 aB + 17192 LUT4 F2FF (Ab)+C+d + 17193 LUT4 B0BB /aB\(d+C) + 17194 LUT2 4 aB + 17195 LUT4 F2FF (Ab)+C+d + 17196 LUT4 B0BB /aB\(d+C) + 17197 LUT2 4 aB + 17198 LUT4 F2FF (Ab)+C+d + 17199 LUT4 B0BB /aB\(d+C) + 17200 LUT2 4 aB + 17201 LUT2 B /aB\ + 17202 LUT2 8 AB + 17203 LUT3 F8 (AB)+C + 17204 LUT3 E0 C/ab\ + 17205 LUT2 E /ab\ + 17206 LUT2 E /ab\ + 17207 LUT3 F8 (AB)+C + 17208 LUT3 80 ABC + 17209 LUT3 F8 (AB)+C + 17210 LUT2 4 aB + 17211 LUT3 80 ABC + 17212 LUT2 1 ab + 17213 LUT3 8F (AB)+c + 17214 LUT4 8000 ABCD + 17215 LUT2 8 AB + 17216 LUT2 8 AB + 17217 LUT2 8 AB + 17218 LUT4 0BBB /aB\(d+c) + 17219 LUT3 80 ABC + 17220 LUT2 4 aB + 17221 LUT2 1 ab + 17222 LUT2 1 ab + 17223 LUT4 8000 ABCD + 17224 LUT2 8 AB + 17225 LUT4 0700 cD/AB\ + 17226 LUT2 8 AB + 17227 LUT3 CA C?A:B + 17228 LUT3 4F (aB)+c + 17229 LUT4 0BBB /aB\(d+c) + 17230 LUT3 70 C/AB\ + 17231 LUT2 6 A^B + 17232 LUT4 0777 /AB\(d+c) + 17233 LUT3 60 C(A^B) + 17234 LUT3 01 abc + 17235 LUT3 90 C(a^B) + 17236 LUT4 0777 /AB\(d+c) + 17237 LUT4 0FBB D?/aB\:c + 17238 LUT3 4F (aB)+c + 17239 LUT4 0BBB /aB\(d+c) + 17240 LUT3 70 C/AB\ + 17241 LUT4 0FBB D?/aB\:c + 17242 LUT2 6 A^B + 17243 LUT2 8 AB + 17244 LUT4 0777 /AB\(d+c) + 17245 LUT3 4F (aB)+c + 17246 LUT4 0BBB /aB\(d+c) + 17247 LUT3 70 C/AB\ + 17248 LUT2 6 A^B + 17249 LUT2 8 AB + 17250 LUT4 0777 /AB\(d+c) + 17251 LUT4 0FBB D?/aB\:c + 17252 LUT3 4F (aB)+c + 17253 LUT4 0BBB /aB\(d+c) + 17254 LUT3 70 C/AB\ + 17255 LUT4 0FBB D?/aB\:c + 17256 LUT2 6 A^B + 17257 LUT2 8 AB + 17258 LUT4 0777 /AB\(d+c) + 17259 LUT3 4F (aB)+c + 17260 LUT4 0BBB /aB\(d+c) + 17261 LUT3 70 C/AB\ + 17262 LUT2 6 A^B + 17263 LUT2 8 AB + 17264 LUT4 0777 /AB\(d+c) + 17265 LUT4 0FBB D?/aB\:c + 17266 LUT3 4F (aB)+c + 17267 LUT4 0BBB /aB\(d+c) + 17268 LUT3 70 C/AB\ + 17269 LUT4 0FBB D?/aB\:c + 17270 LUT2 6 A^B + 17271 LUT2 8 AB + 17272 LUT4 0777 /AB\(d+c) + 17273 LUT3 4F (aB)+c + 17274 LUT4 0BBB /aB\(d+c) + 17275 LUT3 70 C/AB\ + 17276 LUT4 0FBB D?/aB\:c + 17277 LUT2 6 A^B + 17278 LUT2 8 AB + 17279 LUT4 0777 /AB\(d+c) + 17280 LUT3 4F (aB)+c + 17281 LUT4 7077 /AB\(d+C) + 17282 LUT3 70 C/AB\ + 17283 LUT4 0FBB D?/aB\:c + 17284 LUT2 6 A^B + 17285 LUT2 8 AB + 17286 LUT4 0777 /AB\(d+c) + 17287 LUT3 4F (aB)+c + 17288 LUT4 7077 /AB\(d+C) + 17289 LUT3 70 C/AB\ + 17290 LUT4 0FBB D?/aB\:c + 17291 LUT2 6 A^B + 17292 LUT2 8 AB + 17293 LUT4 0777 /AB\(d+c) + 17294 LUT3 4F (aB)+c + 17295 LUT3 70 C/AB\ + 17296 LUT4 0FBB D?/aB\:c + 17297 LUT2 6 A^B + 17298 LUT2 8 AB + 17299 LUT4 0777 /AB\(d+c) + 17300 LUT4 7077 /AB\(d+C) + 17301 LUT3 4F (aB)+c + 17302 LUT3 70 C/AB\ + 17303 LUT4 0FBB D?/aB\:c + 17304 LUT2 6 A^B + 17305 LUT2 8 AB + 17306 LUT4 0777 /AB\(d+c) + 17307 LUT4 7077 /AB\(d+C) + 17308 LUT3 4F (aB)+c + 17309 LUT3 70 C/AB\ + 17310 LUT4 0FBB D?/aB\:c + 17311 LUT2 6 A^B + 17312 LUT2 8 AB + 17313 LUT4 0777 /AB\(d+c) + 17314 LUT4 7077 /AB\(d+C) + 17315 LUT3 4F (aB)+c + 17316 LUT3 70 C/AB\ + 17317 LUT4 0FBB D?/aB\:c + 17318 LUT2 6 A^B + 17319 LUT2 8 AB + 17320 LUT4 0777 /AB\(d+c) + 17321 LUT4 7077 /AB\(d+C) + 17322 LUT3 4F (aB)+c + 17323 LUT3 70 C/AB\ + 17324 LUT4 0FBB D?/aB\:c + 17325 LUT2 6 A^B + 17326 LUT2 8 AB + 17327 LUT4 0777 /AB\(d+c) + 17328 LUT4 7077 /AB\(d+C) + 17329 LUT3 4F (aB)+c + 17330 LUT3 70 C/AB\ + 17331 LUT4 0FBB D?/aB\:c + 17332 LUT2 6 A^B + 17333 LUT2 8 AB + 17334 LUT4 0777 /AB\(d+c) + 17335 LUT4 7077 /AB\(d+C) + 17336 LUT3 4F (aB)+c + 17337 LUT3 70 C/AB\ + 17338 LUT4 0FBB D?/aB\:c + 17339 LUT2 6 A^B + 17340 LUT2 8 AB + 17341 LUT4 0777 /AB\(d+c) + 17342 LUT4 7077 /AB\(d+C) + 17343 LUT3 4F (aB)+c + 17344 LUT3 70 C/AB\ + 17345 LUT4 0FBB D?/aB\:c + 17346 LUT2 6 A^B + 17347 LUT2 8 AB + 17348 LUT4 0777 /AB\(d+c) + 17349 LUT4 7077 /AB\(d+C) + 17350 LUT3 4F (aB)+c + 17351 LUT3 70 C/AB\ + 17352 LUT4 0FBB D?/aB\:c + 17353 LUT2 6 A^B + 17354 LUT2 8 AB + 17355 LUT4 0777 /AB\(d+c) + 17356 LUT4 7077 /AB\(d+C) + 17357 LUT3 4F (aB)+c + 17358 LUT3 70 C/AB\ + 17359 LUT4 0FBB D?/aB\:c + 17360 LUT2 6 A^B + 17361 LUT2 8 AB + 17362 LUT4 0777 /AB\(d+c) + 17363 LUT4 7077 /AB\(d+C) + 17364 LUT3 4F (aB)+c + 17365 LUT3 70 C/AB\ + 17366 LUT4 0FBB D?/aB\:c + 17367 LUT2 6 A^B + 17368 LUT2 8 AB + 17369 LUT4 0777 /AB\(d+c) + 17370 LUT4 7077 /AB\(d+C) + 17371 LUT3 4F (aB)+c + 17372 LUT3 70 C/AB\ + 17373 LUT4 0FBB D?/aB\:c + 17374 LUT2 6 A^B + 17375 LUT2 8 AB + 17376 LUT4 0777 /AB\(d+c) + 17377 LUT4 7077 /AB\(d+C) + 17378 LUT3 4F (aB)+c + 17379 LUT3 70 C/AB\ + 17380 LUT4 0FBB D?/aB\:c + 17381 LUT2 6 A^B + 17382 LUT2 8 AB + 17383 LUT4 0777 /AB\(d+c) + 17384 LUT4 7077 /AB\(d+C) + 17385 LUT3 4F (aB)+c + 17386 LUT3 70 C/AB\ + 17387 LUT4 0FBB D?/aB\:c + 17388 LUT2 6 A^B + 17389 LUT2 8 AB + 17390 LUT4 0777 /AB\(d+c) + 17391 LUT4 7077 /AB\(d+C) + 17392 LUT3 4F (aB)+c + 17393 LUT3 70 C/AB\ + 17394 LUT4 0FBB D?/aB\:c + 17395 LUT2 6 A^B + 17396 LUT2 8 AB + 17397 LUT4 0777 /AB\(d+c) + 17398 LUT4 7077 /AB\(d+C) + 17399 LUT3 4F (aB)+c + 17400 LUT3 70 C/AB\ + 17401 LUT4 0FBB D?/aB\:c + 17402 LUT2 6 A^B + 17403 LUT2 8 AB + 17404 LUT4 0777 /AB\(d+c) + 17405 LUT4 7077 /AB\(d+C) + 17406 LUT3 4F (aB)+c + 17407 LUT3 70 C/AB\ + 17408 LUT4 0FBB D?/aB\:c + 17409 LUT2 6 A^B + 17410 LUT2 8 AB + 17411 LUT4 0777 /AB\(d+c) + 17412 LUT4 7077 /AB\(d+C) + 17413 LUT3 4F (aB)+c + 17414 LUT3 70 C/AB\ + 17415 LUT4 0FBB D?/aB\:c + 17416 LUT2 6 A^B + 17417 LUT2 8 AB + 17418 LUT4 0777 /AB\(d+c) + 17419 LUT4 7077 /AB\(d+C) + 17420 LUT3 4F (aB)+c + 17421 LUT3 70 C/AB\ + 17422 LUT4 0FBB D?/aB\:c + 17423 LUT2 6 A^B + 17424 LUT2 8 AB + 17425 LUT4 0777 /AB\(d+c) + 17426 LUT4 7077 /AB\(d+C) + 17427 LUT3 4F (aB)+c + 17428 LUT3 70 C/AB\ + 17429 LUT4 0FBB D?/aB\:c + 17430 LUT2 6 A^B + 17431 LUT2 8 AB + 17432 LUT4 0777 /AB\(d+c) + 17433 LUT4 7077 /AB\(d+C) + 17434 LUT3 4F (aB)+c + 17435 LUT3 70 C/AB\ + 17436 LUT4 0FBB D?/aB\:c + 17437 LUT2 6 A^B + 17438 LUT2 8 AB + 17439 LUT4 0777 /AB\(d+c) + 17440 LUT4 7077 /AB\(d+C) + 17441 LUT3 4F (aB)+c + 17442 LUT4 D700 AD?0:0:1:b^C + 17443 LUT2 8 AB + 17444 LUT4 0777 /AB\(d+c) + 17445 LUT4 0FBB D?/aB\:c + 17446 LUT4 7077 /AB\(d+C) + 17447 LUT3 8F (AB)+c + 17448 LUT3 80 ABC + 17449 LUT2 4 aB + 17450 LUT4 0BBB /aB\(d+c) + 17451 LUT3 80 ABC + 17452 LUT2 4 aB + 17453 LUT3 80 ABC + 17454 LUT2 4 aB + 17455 LUT3 4F (aB)+c + 17456 LUT4 0BBB /aB\(d+c) + 17457 LUT3 4F (aB)+c + 17458 LUT4 0BBB /aB\(d+c) + 17459 LUT3 4F (aB)+c + 17460 LUT4 0BBB /aB\(d+c) + 17461 LUT3 4F (aB)+c + 17462 LUT4 0BBB /aB\(d+c) + 17463 LUT3 4F (aB)+c + 17464 LUT4 0BBB /aB\(d+c) + 17465 LUT3 4F (aB)+c + 17466 LUT4 0BBB /aB\(d+c) + 17467 LUT3 4F (aB)+c + 17468 LUT4 0BBB /aB\(d+c) + 17469 LUT3 4F (aB)+c + 17470 LUT4 7077 /AB\(d+C) + 17471 LUT3 4F (aB)+c + 17472 LUT4 7077 /AB\(d+C) + 17473 LUT3 4F (aB)+c + 17474 LUT4 7077 /AB\(d+C) + 17475 LUT3 4F (aB)+c + 17476 LUT4 7077 /AB\(d+C) + 17477 LUT3 4F (aB)+c + 17478 LUT4 7077 /AB\(d+C) + 17479 LUT3 4F (aB)+c + 17480 LUT4 7077 /AB\(d+C) + 17481 LUT3 4F (aB)+c + 17482 LUT4 7077 /AB\(d+C) + 17483 LUT3 4F (aB)+c + 17484 LUT4 7077 /AB\(d+C) + 17485 LUT3 4F (aB)+c + 17486 LUT4 7077 /AB\(d+C) + 17487 LUT3 4F (aB)+c + 17488 LUT4 7077 /AB\(d+C) + 17489 LUT3 4F (aB)+c + 17490 LUT4 7077 /AB\(d+C) + 17491 LUT3 4F (aB)+c + 17492 LUT4 7077 /AB\(d+C) + 17493 LUT3 4F (aB)+c + 17494 LUT4 7077 /AB\(d+C) + 17495 LUT3 4F (aB)+c + 17496 LUT4 7077 /AB\(d+C) + 17497 LUT3 4F (aB)+c + 17498 LUT4 7077 /AB\(d+C) + 17499 LUT3 4F (aB)+c + 17500 LUT4 7077 /AB\(d+C) + 17501 LUT3 4F (aB)+c + 17502 LUT4 7077 /AB\(d+C) + 17503 LUT3 4F (aB)+c + 17504 LUT4 7077 /AB\(d+C) + 17505 LUT3 4F (aB)+c + 17506 LUT4 7077 /AB\(d+C) + 17507 LUT3 4F (aB)+c + 17508 LUT4 7077 /AB\(d+C) + 17509 LUT3 4F (aB)+c + 17510 LUT4 7077 /AB\(d+C) + 17511 LUT3 4F (aB)+c + 17512 LUT4 7077 /AB\(d+C) + 17513 LUT3 4F (aB)+c + 17514 LUT4 7077 /AB\(d+C) + 17515 LUT3 4F (aB)+c + 17516 LUT4 7077 /AB\(d+C) + 17517 LUT3 8F (AB)+c + 17518 LUT3 80 ABC + 17519 LUT2 4 aB + 17520 LUT4 0BBB /aB\(d+c) + 17521 LUT3 80 ABC + 17522 LUT2 4 aB + 17523 LUT3 80 ABC + 17524 LUT2 4 aB + 17525 LUT3 4F (aB)+c + 17526 LUT4 0BBB /aB\(d+c) + 17527 LUT3 4F (aB)+c + 17528 LUT4 0BBB /aB\(d+c) + 17529 LUT3 4F (aB)+c + 17530 LUT4 0BBB /aB\(d+c) + 17531 LUT3 4F (aB)+c + 17532 LUT4 0BBB /aB\(d+c) + 17533 LUT3 4F (aB)+c + 17534 LUT4 0BBB /aB\(d+c) + 17535 LUT3 4F (aB)+c + 17536 LUT4 0BBB /aB\(d+c) + 17537 LUT3 4F (aB)+c + 17538 LUT4 0BBB /aB\(d+c) + 17539 LUT3 4F (aB)+c + 17540 LUT4 7077 /AB\(d+C) + 17541 LUT3 4F (aB)+c + 17542 LUT4 7077 /AB\(d+C) + 17543 LUT3 4F (aB)+c + 17544 LUT4 7077 /AB\(d+C) + 17545 LUT3 4F (aB)+c + 17546 LUT4 7077 /AB\(d+C) + 17547 LUT3 4F (aB)+c + 17548 LUT4 7077 /AB\(d+C) + 17549 LUT3 4F (aB)+c + 17550 LUT4 7077 /AB\(d+C) + 17551 LUT3 4F (aB)+c + 17552 LUT4 7077 /AB\(d+C) + 17553 LUT3 4F (aB)+c + 17554 LUT4 7077 /AB\(d+C) + 17555 LUT3 4F (aB)+c + 17556 LUT4 7077 /AB\(d+C) + 17557 LUT3 4F (aB)+c + 17558 LUT4 7077 /AB\(d+C) + 17559 LUT3 4F (aB)+c + 17560 LUT4 7077 /AB\(d+C) + 17561 LUT3 4F (aB)+c + 17562 LUT4 7077 /AB\(d+C) + 17563 LUT3 4F (aB)+c + 17564 LUT4 7077 /AB\(d+C) + 17565 LUT3 4F (aB)+c + 17566 LUT4 7077 /AB\(d+C) + 17567 LUT3 4F (aB)+c + 17568 LUT4 7077 /AB\(d+C) + 17569 LUT3 4F (aB)+c + 17570 LUT4 7077 /AB\(d+C) + 17571 LUT3 4F (aB)+c + 17572 LUT4 7077 /AB\(d+C) + 17573 LUT3 4F (aB)+c + 17574 LUT4 7077 /AB\(d+C) + 17575 LUT3 4F (aB)+c + 17576 LUT4 7077 /AB\(d+C) + 17577 LUT3 4F (aB)+c + 17578 LUT4 7077 /AB\(d+C) + 17579 LUT3 4F (aB)+c + 17580 LUT4 7077 /AB\(d+C) + 17581 LUT3 4F (aB)+c + 17582 LUT4 7077 /AB\(d+C) + 17583 LUT3 4F (aB)+c + 17584 LUT4 7077 /AB\(d+C) + 17585 LUT3 4F (aB)+c + 17586 LUT4 7077 /AB\(d+C) + 17587 LUT3 8F (AB)+c + 17588 LUT3 80 ABC + 17589 LUT2 1 ab + 17590 LUT4 0BBB /aB\(d+c) + 17591 LUT2 8 AB + 17592 LUT3 80 ABC + 17593 LUT3 80 ABC + 17594 LUT2 1 ab + 17595 LUT3 4F (aB)+c + 17596 LUT4 0BBB /aB\(d+c) + 17597 LUT3 4F (aB)+c + 17598 LUT4 0BBB /aB\(d+c) + 17599 LUT3 4F (aB)+c + 17600 LUT4 0BBB /aB\(d+c) + 17601 LUT3 4F (aB)+c + 17602 LUT4 0BBB /aB\(d+c) + 17603 LUT3 4F (aB)+c + 17604 LUT4 0BBB /aB\(d+c) + 17605 LUT3 4F (aB)+c + 17606 LUT4 0BBB /aB\(d+c) + 17607 LUT3 4F (aB)+c + 17608 LUT4 0BBB /aB\(d+c) + 17609 LUT3 4F (aB)+c + 17610 LUT4 7077 /AB\(d+C) + 17611 LUT3 4F (aB)+c + 17612 LUT4 7077 /AB\(d+C) + 17613 LUT3 4F (aB)+c + 17614 LUT4 7077 /AB\(d+C) + 17615 LUT3 4F (aB)+c + 17616 LUT4 7077 /AB\(d+C) + 17617 LUT3 4F (aB)+c + 17618 LUT4 7077 /AB\(d+C) + 17619 LUT3 4F (aB)+c + 17620 LUT4 7077 /AB\(d+C) + 17621 LUT3 4F (aB)+c + 17622 LUT4 7077 /AB\(d+C) + 17623 LUT3 4F (aB)+c + 17624 LUT4 7077 /AB\(d+C) + 17625 LUT3 4F (aB)+c + 17626 LUT4 7077 /AB\(d+C) + 17627 LUT3 4F (aB)+c + 17628 LUT4 7077 /AB\(d+C) + 17629 LUT3 4F (aB)+c + 17630 LUT4 7077 /AB\(d+C) + 17631 LUT3 4F (aB)+c + 17632 LUT4 7077 /AB\(d+C) + 17633 LUT3 4F (aB)+c + 17634 LUT4 7077 /AB\(d+C) + 17635 LUT3 4F (aB)+c + 17636 LUT4 7077 /AB\(d+C) + 17637 LUT3 4F (aB)+c + 17638 LUT4 7077 /AB\(d+C) + 17639 LUT3 4F (aB)+c + 17640 LUT4 7077 /AB\(d+C) + 17641 LUT3 4F (aB)+c + 17642 LUT4 7077 /AB\(d+C) + 17643 LUT3 4F (aB)+c + 17644 LUT4 7077 /AB\(d+C) + 17645 LUT3 4F (aB)+c + 17646 LUT4 7077 /AB\(d+C) + 17647 LUT3 4F (aB)+c + 17648 LUT4 7077 /AB\(d+C) + 17649 LUT3 4F (aB)+c + 17650 LUT4 7077 /AB\(d+C) + 17651 LUT3 4F (aB)+c + 17652 LUT4 7077 /AB\(d+C) + 17653 LUT3 4F (aB)+c + 17654 LUT4 7077 /AB\(d+C) + 17655 LUT3 4F (aB)+c + 17656 LUT4 7077 /AB\(d+C) + 17657 LUT3 8F (AB)+c + 17658 LUT4 8000 ABCD + 17659 LUT2 4 aB + 17660 LUT4 0BBB /aB\(d+c) + 17661 LUT3 80 ABC + 17662 LUT2 4 aB + 17663 LUT4 8000 ABCD + 17664 LUT2 4 aB + 17665 LUT3 4F (aB)+c + 17666 LUT4 0BBB /aB\(d+c) + 17667 LUT3 4F (aB)+c + 17668 LUT4 0BBB /aB\(d+c) + 17669 LUT3 4F (aB)+c + 17670 LUT4 0BBB /aB\(d+c) + 17671 LUT3 4F (aB)+c + 17672 LUT4 0BBB /aB\(d+c) + 17673 LUT3 4F (aB)+c + 17674 LUT4 0BBB /aB\(d+c) + 17675 LUT3 4F (aB)+c + 17676 LUT4 0BBB /aB\(d+c) + 17677 LUT3 4F (aB)+c + 17678 LUT4 0BBB /aB\(d+c) + 17679 LUT3 4F (aB)+c + 17680 LUT4 7077 /AB\(d+C) + 17681 LUT3 4F (aB)+c + 17682 LUT4 7077 /AB\(d+C) + 17683 LUT3 4F (aB)+c + 17684 LUT4 7077 /AB\(d+C) + 17685 LUT3 4F (aB)+c + 17686 LUT4 7077 /AB\(d+C) + 17687 LUT3 4F (aB)+c + 17688 LUT4 7077 /AB\(d+C) + 17689 LUT3 4F (aB)+c + 17690 LUT4 7077 /AB\(d+C) + 17691 LUT3 4F (aB)+c + 17692 LUT4 7077 /AB\(d+C) + 17693 LUT3 4F (aB)+c + 17694 LUT4 7077 /AB\(d+C) + 17695 LUT3 4F (aB)+c + 17696 LUT4 7077 /AB\(d+C) + 17697 LUT3 4F (aB)+c + 17698 LUT4 7077 /AB\(d+C) + 17699 LUT3 4F (aB)+c + 17700 LUT4 7077 /AB\(d+C) + 17701 LUT3 4F (aB)+c + 17702 LUT4 7077 /AB\(d+C) + 17703 LUT3 4F (aB)+c + 17704 LUT4 7077 /AB\(d+C) + 17705 LUT3 4F (aB)+c + 17706 LUT4 7077 /AB\(d+C) + 17707 LUT3 4F (aB)+c + 17708 LUT4 7077 /AB\(d+C) + 17709 LUT3 4F (aB)+c + 17710 LUT4 7077 /AB\(d+C) + 17711 LUT3 4F (aB)+c + 17712 LUT4 7077 /AB\(d+C) + 17713 LUT3 4F (aB)+c + 17714 LUT4 7077 /AB\(d+C) + 17715 LUT3 4F (aB)+c + 17716 LUT4 7077 /AB\(d+C) + 17717 LUT3 4F (aB)+c + 17718 LUT4 7077 /AB\(d+C) + 17719 LUT3 4F (aB)+c + 17720 LUT4 7077 /AB\(d+C) + 17721 LUT3 4F (aB)+c + 17722 LUT4 7077 /AB\(d+C) + 17723 LUT3 4F (aB)+c + 17724 LUT4 7077 /AB\(d+C) + 17725 LUT3 4F (aB)+c + 17726 LUT4 7077 /AB\(d+C) + 17727 LUT3 8F (AB)+c + 17728 LUT3 80 ABC + 17729 LUT4 0BBB /aB\(d+c) + 17730 LUT3 80 ABC + 17731 LUT3 80 ABC + 17732 LUT3 4F (aB)+c + 17733 LUT4 0BBB /aB\(d+c) + 17734 LUT3 4F (aB)+c + 17735 LUT4 0BBB /aB\(d+c) + 17736 LUT3 4F (aB)+c + 17737 LUT4 0BBB /aB\(d+c) + 17738 LUT3 4F (aB)+c + 17739 LUT4 0BBB /aB\(d+c) + 17740 LUT3 4F (aB)+c + 17741 LUT4 0BBB /aB\(d+c) + 17742 LUT3 4F (aB)+c + 17743 LUT4 0BBB /aB\(d+c) + 17744 LUT3 4F (aB)+c + 17745 LUT4 0BBB /aB\(d+c) + 17746 LUT3 4F (aB)+c + 17747 LUT4 7077 /AB\(d+C) + 17748 LUT3 4F (aB)+c + 17749 LUT4 7077 /AB\(d+C) + 17750 LUT3 4F (aB)+c + 17751 LUT4 7077 /AB\(d+C) + 17752 LUT3 4F (aB)+c + 17753 LUT4 7077 /AB\(d+C) + 17754 LUT3 4F (aB)+c + 17755 LUT4 7077 /AB\(d+C) + 17756 LUT3 4F (aB)+c + 17757 LUT4 7077 /AB\(d+C) + 17758 LUT3 4F (aB)+c + 17759 LUT4 7077 /AB\(d+C) + 17760 LUT3 4F (aB)+c + 17761 LUT4 7077 /AB\(d+C) + 17762 LUT3 4F (aB)+c + 17763 LUT4 7077 /AB\(d+C) + 17764 LUT3 4F (aB)+c + 17765 LUT4 7077 /AB\(d+C) + 17766 LUT3 4F (aB)+c + 17767 LUT4 7077 /AB\(d+C) + 17768 LUT3 4F (aB)+c + 17769 LUT4 7077 /AB\(d+C) + 17770 LUT3 4F (aB)+c + 17771 LUT4 7077 /AB\(d+C) + 17772 LUT3 4F (aB)+c + 17773 LUT4 7077 /AB\(d+C) + 17774 LUT3 4F (aB)+c + 17775 LUT4 7077 /AB\(d+C) + 17776 LUT3 4F (aB)+c + 17777 LUT4 7077 /AB\(d+C) + 17778 LUT3 4F (aB)+c + 17779 LUT4 7077 /AB\(d+C) + 17780 LUT3 4F (aB)+c + 17781 LUT4 7077 /AB\(d+C) + 17782 LUT3 4F (aB)+c + 17783 LUT4 7077 /AB\(d+C) + 17784 LUT3 4F (aB)+c + 17785 LUT4 7077 /AB\(d+C) + 17786 LUT3 4F (aB)+c + 17787 LUT4 7077 /AB\(d+C) + 17788 LUT3 4F (aB)+c + 17789 LUT4 7077 /AB\(d+C) + 17790 LUT3 4F (aB)+c + 17791 LUT4 7077 /AB\(d+C) + 17792 LUT3 4F (aB)+c + 17793 LUT4 7077 /AB\(d+C) + 17794 LUT3 8F (AB)+c + 17795 LUT3 80 ABC + 17796 LUT4 0BBB /aB\(d+c) + 17797 LUT3 80 ABC + 17798 LUT3 80 ABC + 17799 LUT3 4F (aB)+c + 17800 LUT4 0BBB /aB\(d+c) + 17801 LUT3 4F (aB)+c + 17802 LUT4 0BBB /aB\(d+c) + 17803 LUT3 4F (aB)+c + 17804 LUT4 0BBB /aB\(d+c) + 17805 LUT3 4F (aB)+c + 17806 LUT4 0BBB /aB\(d+c) + 17807 LUT3 4F (aB)+c + 17808 LUT4 0BBB /aB\(d+c) + 17809 LUT3 4F (aB)+c + 17810 LUT4 0BBB /aB\(d+c) + 17811 LUT3 4F (aB)+c + 17812 LUT4 0BBB /aB\(d+c) + 17813 LUT3 4F (aB)+c + 17814 LUT4 7077 /AB\(d+C) + 17815 LUT3 4F (aB)+c + 17816 LUT4 7077 /AB\(d+C) + 17817 LUT3 4F (aB)+c + 17818 LUT4 7077 /AB\(d+C) + 17819 LUT3 4F (aB)+c + 17820 LUT4 7077 /AB\(d+C) + 17821 LUT3 4F (aB)+c + 17822 LUT4 7077 /AB\(d+C) + 17823 LUT3 4F (aB)+c + 17824 LUT4 7077 /AB\(d+C) + 17825 LUT3 4F (aB)+c + 17826 LUT4 7077 /AB\(d+C) + 17827 LUT3 4F (aB)+c + 17828 LUT4 7077 /AB\(d+C) + 17829 LUT3 4F (aB)+c + 17830 LUT4 7077 /AB\(d+C) + 17831 LUT3 4F (aB)+c + 17832 LUT4 7077 /AB\(d+C) + 17833 LUT3 4F (aB)+c + 17834 LUT4 7077 /AB\(d+C) + 17835 LUT3 4F (aB)+c + 17836 LUT4 7077 /AB\(d+C) + 17837 LUT3 4F (aB)+c + 17838 LUT4 7077 /AB\(d+C) + 17839 LUT3 4F (aB)+c + 17840 LUT4 7077 /AB\(d+C) + 17841 LUT3 4F (aB)+c + 17842 LUT4 7077 /AB\(d+C) + 17843 LUT3 4F (aB)+c + 17844 LUT4 7077 /AB\(d+C) + 17845 LUT3 4F (aB)+c + 17846 LUT4 7077 /AB\(d+C) + 17847 LUT3 4F (aB)+c + 17848 LUT4 7077 /AB\(d+C) + 17849 LUT3 4F (aB)+c + 17850 LUT4 7077 /AB\(d+C) + 17851 LUT3 4F (aB)+c + 17852 LUT4 7077 /AB\(d+C) + 17853 LUT3 4F (aB)+c + 17854 LUT4 7077 /AB\(d+C) + 17855 LUT3 4F (aB)+c + 17856 LUT4 7077 /AB\(d+C) + 17857 LUT3 4F (aB)+c + 17858 LUT4 7077 /AB\(d+C) + 17859 LUT3 4F (aB)+c + 17860 LUT4 7077 /AB\(d+C) + 17861 LUT3 8F (AB)+c + 17862 LUT3 80 ABC + 17863 LUT4 0BBB /aB\(d+c) + 17864 LUT2 8 AB + 17865 LUT3 80 ABC + 17866 LUT3 4F (aB)+c + 17867 LUT4 0BBB /aB\(d+c) + 17868 LUT3 4F (aB)+c + 17869 LUT4 0BBB /aB\(d+c) + 17870 LUT3 4F (aB)+c + 17871 LUT4 0BBB /aB\(d+c) + 17872 LUT3 4F (aB)+c + 17873 LUT4 0BBB /aB\(d+c) + 17874 LUT3 4F (aB)+c + 17875 LUT4 0BBB /aB\(d+c) + 17876 LUT3 4F (aB)+c + 17877 LUT4 0BBB /aB\(d+c) + 17878 LUT3 4F (aB)+c + 17879 LUT4 0BBB /aB\(d+c) + 17880 LUT3 4F (aB)+c + 17881 LUT4 7077 /AB\(d+C) + 17882 LUT3 4F (aB)+c + 17883 LUT4 7077 /AB\(d+C) + 17884 LUT3 4F (aB)+c + 17885 LUT4 7077 /AB\(d+C) + 17886 LUT3 4F (aB)+c + 17887 LUT4 7077 /AB\(d+C) + 17888 LUT3 4F (aB)+c + 17889 LUT4 7077 /AB\(d+C) + 17890 LUT3 4F (aB)+c + 17891 LUT4 7077 /AB\(d+C) + 17892 LUT3 4F (aB)+c + 17893 LUT4 7077 /AB\(d+C) + 17894 LUT3 4F (aB)+c + 17895 LUT4 7077 /AB\(d+C) + 17896 LUT3 4F (aB)+c + 17897 LUT4 7077 /AB\(d+C) + 17898 LUT3 4F (aB)+c + 17899 LUT4 7077 /AB\(d+C) + 17900 LUT3 4F (aB)+c + 17901 LUT4 7077 /AB\(d+C) + 17902 LUT3 4F (aB)+c + 17903 LUT4 7077 /AB\(d+C) + 17904 LUT3 4F (aB)+c + 17905 LUT4 7077 /AB\(d+C) + 17906 LUT3 4F (aB)+c + 17907 LUT4 7077 /AB\(d+C) + 17908 LUT3 4F (aB)+c + 17909 LUT4 7077 /AB\(d+C) + 17910 LUT3 4F (aB)+c + 17911 LUT4 7077 /AB\(d+C) + 17912 LUT3 4F (aB)+c + 17913 LUT4 7077 /AB\(d+C) + 17914 LUT3 4F (aB)+c + 17915 LUT4 7077 /AB\(d+C) + 17916 LUT3 4F (aB)+c + 17917 LUT4 7077 /AB\(d+C) + 17918 LUT3 4F (aB)+c + 17919 LUT4 7077 /AB\(d+C) + 17920 LUT3 4F (aB)+c + 17921 LUT4 7077 /AB\(d+C) + 17922 LUT3 4F (aB)+c + 17923 LUT4 7077 /AB\(d+C) + 17924 LUT3 4F (aB)+c + 17925 LUT4 7077 /AB\(d+C) + 17926 LUT3 4F (aB)+c + 17927 LUT4 7077 /AB\(d+C) + 17928 LUT3 8F (AB)+c + 17929 LUT4 8000 ABCD + 17930 LUT2 4 aB + 17931 LUT4 0BBB /aB\(d+c) + 17932 LUT3 80 ABC + 17933 LUT2 4 aB + 17934 LUT4 8000 ABCD + 17935 LUT2 4 aB + 17936 LUT3 4F (aB)+c + 17937 LUT4 0BBB /aB\(d+c) + 17938 LUT3 4F (aB)+c + 17939 LUT4 0BBB /aB\(d+c) + 17940 LUT3 4F (aB)+c + 17941 LUT4 0BBB /aB\(d+c) + 17942 LUT3 4F (aB)+c + 17943 LUT4 0BBB /aB\(d+c) + 17944 LUT3 4F (aB)+c + 17945 LUT4 0BBB /aB\(d+c) + 17946 LUT3 4F (aB)+c + 17947 LUT4 0BBB /aB\(d+c) + 17948 LUT3 4F (aB)+c + 17949 LUT4 0BBB /aB\(d+c) + 17950 LUT3 4F (aB)+c + 17951 LUT4 7077 /AB\(d+C) + 17952 LUT3 4F (aB)+c + 17953 LUT4 7077 /AB\(d+C) + 17954 LUT3 4F (aB)+c + 17955 LUT4 7077 /AB\(d+C) + 17956 LUT3 4F (aB)+c + 17957 LUT4 7077 /AB\(d+C) + 17958 LUT3 4F (aB)+c + 17959 LUT4 7077 /AB\(d+C) + 17960 LUT3 4F (aB)+c + 17961 LUT4 7077 /AB\(d+C) + 17962 LUT3 4F (aB)+c + 17963 LUT4 7077 /AB\(d+C) + 17964 LUT3 4F (aB)+c + 17965 LUT4 7077 /AB\(d+C) + 17966 LUT3 4F (aB)+c + 17967 LUT4 7077 /AB\(d+C) + 17968 LUT3 4F (aB)+c + 17969 LUT4 7077 /AB\(d+C) + 17970 LUT3 4F (aB)+c + 17971 LUT4 7077 /AB\(d+C) + 17972 LUT3 4F (aB)+c + 17973 LUT4 7077 /AB\(d+C) + 17974 LUT3 4F (aB)+c + 17975 LUT4 7077 /AB\(d+C) + 17976 LUT3 4F (aB)+c + 17977 LUT4 7077 /AB\(d+C) + 17978 LUT3 4F (aB)+c + 17979 LUT4 7077 /AB\(d+C) + 17980 LUT3 4F (aB)+c + 17981 LUT4 7077 /AB\(d+C) + 17982 LUT3 4F (aB)+c + 17983 LUT4 7077 /AB\(d+C) + 17984 LUT3 4F (aB)+c + 17985 LUT4 7077 /AB\(d+C) + 17986 LUT3 4F (aB)+c + 17987 LUT4 7077 /AB\(d+C) + 17988 LUT3 4F (aB)+c + 17989 LUT4 7077 /AB\(d+C) + 17990 LUT3 4F (aB)+c + 17991 LUT4 7077 /AB\(d+C) + 17992 LUT3 4F (aB)+c + 17993 LUT4 7077 /AB\(d+C) + 17994 LUT3 4F (aB)+c + 17995 LUT4 7077 /AB\(d+C) + 17996 LUT3 4F (aB)+c + 17997 LUT4 7077 /AB\(d+C) + 17998 LUT3 8F (AB)+c + 17999 LUT3 80 ABC + 18000 LUT4 0BBB /aB\(d+c) + 18001 LUT3 80 ABC + 18002 LUT3 80 ABC + 18003 LUT3 4F (aB)+c + 18004 LUT4 0BBB /aB\(d+c) + 18005 LUT3 4F (aB)+c + 18006 LUT4 0BBB /aB\(d+c) + 18007 LUT3 4F (aB)+c + 18008 LUT4 0BBB /aB\(d+c) + 18009 LUT3 4F (aB)+c + 18010 LUT4 0BBB /aB\(d+c) + 18011 LUT3 4F (aB)+c + 18012 LUT4 0BBB /aB\(d+c) + 18013 LUT3 4F (aB)+c + 18014 LUT4 0BBB /aB\(d+c) + 18015 LUT3 4F (aB)+c + 18016 LUT4 0BBB /aB\(d+c) + 18017 LUT3 4F (aB)+c + 18018 LUT4 7077 /AB\(d+C) + 18019 LUT3 4F (aB)+c + 18020 LUT4 7077 /AB\(d+C) + 18021 LUT3 4F (aB)+c + 18022 LUT4 7077 /AB\(d+C) + 18023 LUT3 4F (aB)+c + 18024 LUT4 7077 /AB\(d+C) + 18025 LUT3 4F (aB)+c + 18026 LUT4 7077 /AB\(d+C) + 18027 LUT3 4F (aB)+c + 18028 LUT4 7077 /AB\(d+C) + 18029 LUT3 4F (aB)+c + 18030 LUT4 7077 /AB\(d+C) + 18031 LUT3 4F (aB)+c + 18032 LUT4 7077 /AB\(d+C) + 18033 LUT3 4F (aB)+c + 18034 LUT4 7077 /AB\(d+C) + 18035 LUT3 4F (aB)+c + 18036 LUT4 7077 /AB\(d+C) + 18037 LUT3 4F (aB)+c + 18038 LUT4 7077 /AB\(d+C) + 18039 LUT3 4F (aB)+c + 18040 LUT4 7077 /AB\(d+C) + 18041 LUT3 4F (aB)+c + 18042 LUT4 7077 /AB\(d+C) + 18043 LUT3 4F (aB)+c + 18044 LUT4 7077 /AB\(d+C) + 18045 LUT3 4F (aB)+c + 18046 LUT4 7077 /AB\(d+C) + 18047 LUT3 4F (aB)+c + 18048 LUT4 7077 /AB\(d+C) + 18049 LUT3 4F (aB)+c + 18050 LUT4 7077 /AB\(d+C) + 18051 LUT3 4F (aB)+c + 18052 LUT4 7077 /AB\(d+C) + 18053 LUT3 4F (aB)+c + 18054 LUT4 7077 /AB\(d+C) + 18055 LUT3 4F (aB)+c + 18056 LUT4 7077 /AB\(d+C) + 18057 LUT3 4F (aB)+c + 18058 LUT4 7077 /AB\(d+C) + 18059 LUT3 4F (aB)+c + 18060 LUT4 7077 /AB\(d+C) + 18061 LUT3 4F (aB)+c + 18062 LUT4 7077 /AB\(d+C) + 18063 LUT3 4F (aB)+c + 18064 LUT4 7077 /AB\(d+C) + 18065 LUT3 8F (AB)+c + 18066 LUT3 80 ABC + 18067 LUT4 0BBB /aB\(d+c) + 18068 LUT3 80 ABC + 18069 LUT3 80 ABC + 18070 LUT3 4F (aB)+c + 18071 LUT4 0BBB /aB\(d+c) + 18072 LUT3 4F (aB)+c + 18073 LUT4 0BBB /aB\(d+c) + 18074 LUT3 4F (aB)+c + 18075 LUT4 0BBB /aB\(d+c) + 18076 LUT3 4F (aB)+c + 18077 LUT4 0BBB /aB\(d+c) + 18078 LUT3 4F (aB)+c + 18079 LUT4 0BBB /aB\(d+c) + 18080 LUT3 4F (aB)+c + 18081 LUT4 0BBB /aB\(d+c) + 18082 LUT3 4F (aB)+c + 18083 LUT4 0BBB /aB\(d+c) + 18084 LUT3 4F (aB)+c + 18085 LUT4 7077 /AB\(d+C) + 18086 LUT3 4F (aB)+c + 18087 LUT4 7077 /AB\(d+C) + 18088 LUT3 4F (aB)+c + 18089 LUT4 7077 /AB\(d+C) + 18090 LUT3 4F (aB)+c + 18091 LUT4 7077 /AB\(d+C) + 18092 LUT3 4F (aB)+c + 18093 LUT4 7077 /AB\(d+C) + 18094 LUT3 4F (aB)+c + 18095 LUT4 7077 /AB\(d+C) + 18096 LUT3 4F (aB)+c + 18097 LUT4 7077 /AB\(d+C) + 18098 LUT3 4F (aB)+c + 18099 LUT4 7077 /AB\(d+C) + 18100 LUT3 4F (aB)+c + 18101 LUT4 7077 /AB\(d+C) + 18102 LUT3 4F (aB)+c + 18103 LUT4 7077 /AB\(d+C) + 18104 LUT3 4F (aB)+c + 18105 LUT4 7077 /AB\(d+C) + 18106 LUT3 4F (aB)+c + 18107 LUT4 7077 /AB\(d+C) + 18108 LUT3 4F (aB)+c + 18109 LUT4 7077 /AB\(d+C) + 18110 LUT3 4F (aB)+c + 18111 LUT4 7077 /AB\(d+C) + 18112 LUT3 4F (aB)+c + 18113 LUT4 7077 /AB\(d+C) + 18114 LUT3 4F (aB)+c + 18115 LUT4 7077 /AB\(d+C) + 18116 LUT3 4F (aB)+c + 18117 LUT4 7077 /AB\(d+C) + 18118 LUT3 4F (aB)+c + 18119 LUT4 7077 /AB\(d+C) + 18120 LUT3 4F (aB)+c + 18121 LUT4 7077 /AB\(d+C) + 18122 LUT3 4F (aB)+c + 18123 LUT4 7077 /AB\(d+C) + 18124 LUT3 4F (aB)+c + 18125 LUT4 7077 /AB\(d+C) + 18126 LUT3 4F (aB)+c + 18127 LUT4 7077 /AB\(d+C) + 18128 LUT3 4F (aB)+c + 18129 LUT4 7077 /AB\(d+C) + 18130 LUT3 4F (aB)+c + 18131 LUT4 7077 /AB\(d+C) + 18132 LUT3 8F (AB)+c + 18133 LUT3 80 ABC + 18134 LUT4 0BBB /aB\(d+c) + 18135 LUT2 8 AB + 18136 LUT3 80 ABC + 18137 LUT3 4F (aB)+c + 18138 LUT4 0BBB /aB\(d+c) + 18139 LUT3 4F (aB)+c + 18140 LUT4 0BBB /aB\(d+c) + 18141 LUT3 4F (aB)+c + 18142 LUT4 0BBB /aB\(d+c) + 18143 LUT3 4F (aB)+c + 18144 LUT4 0BBB /aB\(d+c) + 18145 LUT3 4F (aB)+c + 18146 LUT4 0BBB /aB\(d+c) + 18147 LUT3 4F (aB)+c + 18148 LUT4 0BBB /aB\(d+c) + 18149 LUT3 4F (aB)+c + 18150 LUT4 0BBB /aB\(d+c) + 18151 LUT3 4F (aB)+c + 18152 LUT4 7077 /AB\(d+C) + 18153 LUT3 4F (aB)+c + 18154 LUT4 7077 /AB\(d+C) + 18155 LUT3 4F (aB)+c + 18156 LUT4 7077 /AB\(d+C) + 18157 LUT3 4F (aB)+c + 18158 LUT4 7077 /AB\(d+C) + 18159 LUT3 4F (aB)+c + 18160 LUT4 7077 /AB\(d+C) + 18161 LUT3 4F (aB)+c + 18162 LUT4 7077 /AB\(d+C) + 18163 LUT3 4F (aB)+c + 18164 LUT4 7077 /AB\(d+C) + 18165 LUT3 4F (aB)+c + 18166 LUT4 7077 /AB\(d+C) + 18167 LUT3 4F (aB)+c + 18168 LUT4 7077 /AB\(d+C) + 18169 LUT3 4F (aB)+c + 18170 LUT4 7077 /AB\(d+C) + 18171 LUT3 4F (aB)+c + 18172 LUT4 7077 /AB\(d+C) + 18173 LUT3 4F (aB)+c + 18174 LUT4 7077 /AB\(d+C) + 18175 LUT3 4F (aB)+c + 18176 LUT4 7077 /AB\(d+C) + 18177 LUT3 4F (aB)+c + 18178 LUT4 7077 /AB\(d+C) + 18179 LUT3 4F (aB)+c + 18180 LUT4 7077 /AB\(d+C) + 18181 LUT3 4F (aB)+c + 18182 LUT4 7077 /AB\(d+C) + 18183 LUT3 4F (aB)+c + 18184 LUT4 7077 /AB\(d+C) + 18185 LUT3 4F (aB)+c + 18186 LUT4 7077 /AB\(d+C) + 18187 LUT3 4F (aB)+c + 18188 LUT4 7077 /AB\(d+C) + 18189 LUT3 4F (aB)+c + 18190 LUT4 7077 /AB\(d+C) + 18191 LUT3 4F (aB)+c + 18192 LUT4 7077 /AB\(d+C) + 18193 LUT3 4F (aB)+c + 18194 LUT4 7077 /AB\(d+C) + 18195 LUT3 4F (aB)+c + 18196 LUT4 7077 /AB\(d+C) + 18197 LUT3 4F (aB)+c + 18198 LUT4 7077 /AB\(d+C) + 18199 LUT3 8F (AB)+c + 18200 LUT4 8000 ABCD + 18201 LUT2 1 ab + 18202 LUT4 0BBB /aB\(d+c) + 18203 LUT3 80 ABC + 18204 LUT2 8 AB + 18205 LUT4 8000 ABCD + 18206 LUT2 1 ab + 18207 LUT3 4F (aB)+c + 18208 LUT4 0BBB /aB\(d+c) + 18209 LUT3 4F (aB)+c + 18210 LUT4 0BBB /aB\(d+c) + 18211 LUT3 4F (aB)+c + 18212 LUT4 0BBB /aB\(d+c) + 18213 LUT3 4F (aB)+c + 18214 LUT4 0BBB /aB\(d+c) + 18215 LUT3 4F (aB)+c + 18216 LUT4 0BBB /aB\(d+c) + 18217 LUT3 4F (aB)+c + 18218 LUT4 0BBB /aB\(d+c) + 18219 LUT3 4F (aB)+c + 18220 LUT4 0BBB /aB\(d+c) + 18221 LUT3 4F (aB)+c + 18222 LUT4 7077 /AB\(d+C) + 18223 LUT3 4F (aB)+c + 18224 LUT4 7077 /AB\(d+C) + 18225 LUT3 4F (aB)+c + 18226 LUT4 7077 /AB\(d+C) + 18227 LUT3 4F (aB)+c + 18228 LUT4 7077 /AB\(d+C) + 18229 LUT3 4F (aB)+c + 18230 LUT4 7077 /AB\(d+C) + 18231 LUT3 4F (aB)+c + 18232 LUT4 7077 /AB\(d+C) + 18233 LUT3 4F (aB)+c + 18234 LUT4 7077 /AB\(d+C) + 18235 LUT3 4F (aB)+c + 18236 LUT4 7077 /AB\(d+C) + 18237 LUT3 4F (aB)+c + 18238 LUT4 7077 /AB\(d+C) + 18239 LUT3 4F (aB)+c + 18240 LUT4 7077 /AB\(d+C) + 18241 LUT3 4F (aB)+c + 18242 LUT4 7077 /AB\(d+C) + 18243 LUT3 4F (aB)+c + 18244 LUT4 7077 /AB\(d+C) + 18245 LUT3 4F (aB)+c + 18246 LUT4 7077 /AB\(d+C) + 18247 LUT3 4F (aB)+c + 18248 LUT4 7077 /AB\(d+C) + 18249 LUT3 4F (aB)+c + 18250 LUT4 7077 /AB\(d+C) + 18251 LUT3 4F (aB)+c + 18252 LUT4 7077 /AB\(d+C) + 18253 LUT3 4F (aB)+c + 18254 LUT4 7077 /AB\(d+C) + 18255 LUT3 4F (aB)+c + 18256 LUT4 7077 /AB\(d+C) + 18257 LUT3 4F (aB)+c + 18258 LUT4 7077 /AB\(d+C) + 18259 LUT3 4F (aB)+c + 18260 LUT4 7077 /AB\(d+C) + 18261 LUT3 4F (aB)+c + 18262 LUT4 7077 /AB\(d+C) + 18263 LUT3 4F (aB)+c + 18264 LUT4 7077 /AB\(d+C) + 18265 LUT3 4F (aB)+c + 18266 LUT4 7077 /AB\(d+C) + 18267 LUT3 4F (aB)+c + 18268 LUT4 7077 /AB\(d+C) + 18269 LUT3 8F (AB)+c + 18270 LUT3 80 ABC + 18271 LUT4 0BBB /aB\(d+c) + 18272 LUT3 80 ABC + 18273 LUT3 80 ABC + 18274 LUT3 4F (aB)+c + 18275 LUT4 0BBB /aB\(d+c) + 18276 LUT3 4F (aB)+c + 18277 LUT4 0BBB /aB\(d+c) + 18278 LUT3 4F (aB)+c + 18279 LUT4 0BBB /aB\(d+c) + 18280 LUT3 4F (aB)+c + 18281 LUT4 0BBB /aB\(d+c) + 18282 LUT3 4F (aB)+c + 18283 LUT4 0BBB /aB\(d+c) + 18284 LUT3 4F (aB)+c + 18285 LUT4 0BBB /aB\(d+c) + 18286 LUT3 4F (aB)+c + 18287 LUT4 0BBB /aB\(d+c) + 18288 LUT3 4F (aB)+c + 18289 LUT4 7077 /AB\(d+C) + 18290 LUT3 4F (aB)+c + 18291 LUT4 7077 /AB\(d+C) + 18292 LUT3 4F (aB)+c + 18293 LUT4 7077 /AB\(d+C) + 18294 LUT3 4F (aB)+c + 18295 LUT4 7077 /AB\(d+C) + 18296 LUT3 4F (aB)+c + 18297 LUT4 7077 /AB\(d+C) + 18298 LUT3 4F (aB)+c + 18299 LUT4 7077 /AB\(d+C) + 18300 LUT3 4F (aB)+c + 18301 LUT4 7077 /AB\(d+C) + 18302 LUT3 4F (aB)+c + 18303 LUT4 7077 /AB\(d+C) + 18304 LUT3 4F (aB)+c + 18305 LUT4 7077 /AB\(d+C) + 18306 LUT3 4F (aB)+c + 18307 LUT4 7077 /AB\(d+C) + 18308 LUT3 4F (aB)+c + 18309 LUT4 7077 /AB\(d+C) + 18310 LUT3 4F (aB)+c + 18311 LUT4 7077 /AB\(d+C) + 18312 LUT3 4F (aB)+c + 18313 LUT4 7077 /AB\(d+C) + 18314 LUT3 4F (aB)+c + 18315 LUT4 7077 /AB\(d+C) + 18316 LUT3 4F (aB)+c + 18317 LUT4 7077 /AB\(d+C) + 18318 LUT3 4F (aB)+c + 18319 LUT4 7077 /AB\(d+C) + 18320 LUT3 4F (aB)+c + 18321 LUT4 7077 /AB\(d+C) + 18322 LUT3 4F (aB)+c + 18323 LUT4 7077 /AB\(d+C) + 18324 LUT3 4F (aB)+c + 18325 LUT4 7077 /AB\(d+C) + 18326 LUT3 4F (aB)+c + 18327 LUT4 7077 /AB\(d+C) + 18328 LUT3 4F (aB)+c + 18329 LUT4 7077 /AB\(d+C) + 18330 LUT3 4F (aB)+c + 18331 LUT4 7077 /AB\(d+C) + 18332 LUT3 4F (aB)+c + 18333 LUT4 7077 /AB\(d+C) + 18334 LUT3 4F (aB)+c + 18335 LUT4 7077 /AB\(d+C) + 18336 LUT3 8F (AB)+c + 18337 LUT3 80 ABC + 18338 LUT4 0BBB /aB\(d+c) + 18339 LUT3 80 ABC + 18340 LUT3 80 ABC + 18341 LUT3 4F (aB)+c + 18342 LUT4 0BBB /aB\(d+c) + 18343 LUT3 4F (aB)+c + 18344 LUT4 0BBB /aB\(d+c) + 18345 LUT3 4F (aB)+c + 18346 LUT4 0BBB /aB\(d+c) + 18347 LUT3 4F (aB)+c + 18348 LUT4 0BBB /aB\(d+c) + 18349 LUT3 4F (aB)+c + 18350 LUT4 0BBB /aB\(d+c) + 18351 LUT3 4F (aB)+c + 18352 LUT4 0BBB /aB\(d+c) + 18353 LUT3 4F (aB)+c + 18354 LUT4 0BBB /aB\(d+c) + 18355 LUT3 4F (aB)+c + 18356 LUT4 7077 /AB\(d+C) + 18357 LUT3 4F (aB)+c + 18358 LUT4 7077 /AB\(d+C) + 18359 LUT3 4F (aB)+c + 18360 LUT4 7077 /AB\(d+C) + 18361 LUT3 4F (aB)+c + 18362 LUT4 7077 /AB\(d+C) + 18363 LUT3 4F (aB)+c + 18364 LUT4 7077 /AB\(d+C) + 18365 LUT3 4F (aB)+c + 18366 LUT4 7077 /AB\(d+C) + 18367 LUT3 4F (aB)+c + 18368 LUT4 7077 /AB\(d+C) + 18369 LUT3 4F (aB)+c + 18370 LUT4 7077 /AB\(d+C) + 18371 LUT3 4F (aB)+c + 18372 LUT4 7077 /AB\(d+C) + 18373 LUT3 4F (aB)+c + 18374 LUT4 7077 /AB\(d+C) + 18375 LUT3 4F (aB)+c + 18376 LUT4 7077 /AB\(d+C) + 18377 LUT3 4F (aB)+c + 18378 LUT4 7077 /AB\(d+C) + 18379 LUT3 4F (aB)+c + 18380 LUT4 7077 /AB\(d+C) + 18381 LUT3 4F (aB)+c + 18382 LUT4 7077 /AB\(d+C) + 18383 LUT3 4F (aB)+c + 18384 LUT4 7077 /AB\(d+C) + 18385 LUT3 4F (aB)+c + 18386 LUT4 7077 /AB\(d+C) + 18387 LUT3 4F (aB)+c + 18388 LUT4 7077 /AB\(d+C) + 18389 LUT3 4F (aB)+c + 18390 LUT4 7077 /AB\(d+C) + 18391 LUT3 4F (aB)+c + 18392 LUT4 7077 /AB\(d+C) + 18393 LUT3 4F (aB)+c + 18394 LUT4 7077 /AB\(d+C) + 18395 LUT3 4F (aB)+c + 18396 LUT4 7077 /AB\(d+C) + 18397 LUT3 4F (aB)+c + 18398 LUT4 7077 /AB\(d+C) + 18399 LUT3 4F (aB)+c + 18400 LUT4 7077 /AB\(d+C) + 18401 LUT3 4F (aB)+c + 18402 LUT4 7077 /AB\(d+C) + 18403 LUT3 8F (AB)+c + 18404 LUT3 80 ABC + 18405 LUT4 0BBB /aB\(d+c) + 18406 LUT2 8 AB + 18407 LUT3 80 ABC + 18408 LUT3 4F (aB)+c + 18409 LUT4 0BBB /aB\(d+c) + 18410 LUT3 4F (aB)+c + 18411 LUT4 0BBB /aB\(d+c) + 18412 LUT3 4F (aB)+c + 18413 LUT4 0BBB /aB\(d+c) + 18414 LUT3 4F (aB)+c + 18415 LUT4 0BBB /aB\(d+c) + 18416 LUT3 4F (aB)+c + 18417 LUT4 0BBB /aB\(d+c) + 18418 LUT3 4F (aB)+c + 18419 LUT4 0BBB /aB\(d+c) + 18420 LUT3 4F (aB)+c + 18421 LUT4 0BBB /aB\(d+c) + 18422 LUT3 4F (aB)+c + 18423 LUT4 7077 /AB\(d+C) + 18424 LUT3 4F (aB)+c + 18425 LUT4 7077 /AB\(d+C) + 18426 LUT3 4F (aB)+c + 18427 LUT4 7077 /AB\(d+C) + 18428 LUT3 4F (aB)+c + 18429 LUT4 7077 /AB\(d+C) + 18430 LUT3 4F (aB)+c + 18431 LUT4 7077 /AB\(d+C) + 18432 LUT3 4F (aB)+c + 18433 LUT4 7077 /AB\(d+C) + 18434 LUT3 4F (aB)+c + 18435 LUT4 7077 /AB\(d+C) + 18436 LUT3 4F (aB)+c + 18437 LUT4 7077 /AB\(d+C) + 18438 LUT3 4F (aB)+c + 18439 LUT4 7077 /AB\(d+C) + 18440 LUT3 4F (aB)+c + 18441 LUT4 7077 /AB\(d+C) + 18442 LUT3 4F (aB)+c + 18443 LUT4 7077 /AB\(d+C) + 18444 LUT3 4F (aB)+c + 18445 LUT4 7077 /AB\(d+C) + 18446 LUT3 4F (aB)+c + 18447 LUT4 7077 /AB\(d+C) + 18448 LUT3 4F (aB)+c + 18449 LUT4 7077 /AB\(d+C) + 18450 LUT3 4F (aB)+c + 18451 LUT4 7077 /AB\(d+C) + 18452 LUT3 4F (aB)+c + 18453 LUT4 7077 /AB\(d+C) + 18454 LUT3 4F (aB)+c + 18455 LUT4 7077 /AB\(d+C) + 18456 LUT3 4F (aB)+c + 18457 LUT4 7077 /AB\(d+C) + 18458 LUT3 4F (aB)+c + 18459 LUT4 7077 /AB\(d+C) + 18460 LUT3 4F (aB)+c + 18461 LUT4 7077 /AB\(d+C) + 18462 LUT3 4F (aB)+c + 18463 LUT4 7077 /AB\(d+C) + 18464 LUT3 4F (aB)+c + 18465 LUT4 7077 /AB\(d+C) + 18466 LUT3 4F (aB)+c + 18467 LUT4 7077 /AB\(d+C) + 18468 LUT3 4F (aB)+c + 18469 LUT4 7077 /AB\(d+C) + 18470 LUT3 8F (AB)+c + 18471 LUT4 8000 ABCD + 18472 LUT2 4 aB + 18473 LUT4 0BBB /aB\(d+c) + 18474 LUT3 80 ABC + 18475 LUT2 8 AB + 18476 LUT4 8000 ABCD + 18477 LUT2 4 aB + 18478 LUT3 4F (aB)+c + 18479 LUT4 0BBB /aB\(d+c) + 18480 LUT3 4F (aB)+c + 18481 LUT4 0BBB /aB\(d+c) + 18482 LUT3 4F (aB)+c + 18483 LUT4 0BBB /aB\(d+c) + 18484 LUT3 4F (aB)+c + 18485 LUT4 0BBB /aB\(d+c) + 18486 LUT3 4F (aB)+c + 18487 LUT4 0BBB /aB\(d+c) + 18488 LUT3 4F (aB)+c + 18489 LUT4 0BBB /aB\(d+c) + 18490 LUT3 4F (aB)+c + 18491 LUT4 0BBB /aB\(d+c) + 18492 LUT3 4F (aB)+c + 18493 LUT4 7077 /AB\(d+C) + 18494 LUT3 4F (aB)+c + 18495 LUT4 7077 /AB\(d+C) + 18496 LUT3 4F (aB)+c + 18497 LUT4 7077 /AB\(d+C) + 18498 LUT3 4F (aB)+c + 18499 LUT4 7077 /AB\(d+C) + 18500 LUT3 4F (aB)+c + 18501 LUT4 7077 /AB\(d+C) + 18502 LUT3 4F (aB)+c + 18503 LUT4 7077 /AB\(d+C) + 18504 LUT3 4F (aB)+c + 18505 LUT4 7077 /AB\(d+C) + 18506 LUT3 4F (aB)+c + 18507 LUT4 7077 /AB\(d+C) + 18508 LUT3 4F (aB)+c + 18509 LUT4 7077 /AB\(d+C) + 18510 LUT3 4F (aB)+c + 18511 LUT4 7077 /AB\(d+C) + 18512 LUT3 4F (aB)+c + 18513 LUT4 7077 /AB\(d+C) + 18514 LUT3 4F (aB)+c + 18515 LUT4 7077 /AB\(d+C) + 18516 LUT3 4F (aB)+c + 18517 LUT4 7077 /AB\(d+C) + 18518 LUT3 4F (aB)+c + 18519 LUT4 7077 /AB\(d+C) + 18520 LUT3 4F (aB)+c + 18521 LUT4 7077 /AB\(d+C) + 18522 LUT3 4F (aB)+c + 18523 LUT4 7077 /AB\(d+C) + 18524 LUT3 4F (aB)+c + 18525 LUT4 7077 /AB\(d+C) + 18526 LUT3 4F (aB)+c + 18527 LUT4 7077 /AB\(d+C) + 18528 LUT3 4F (aB)+c + 18529 LUT4 7077 /AB\(d+C) + 18530 LUT3 4F (aB)+c + 18531 LUT4 7077 /AB\(d+C) + 18532 LUT3 4F (aB)+c + 18533 LUT4 7077 /AB\(d+C) + 18534 LUT3 4F (aB)+c + 18535 LUT4 7077 /AB\(d+C) + 18536 LUT3 4F (aB)+c + 18537 LUT4 7077 /AB\(d+C) + 18538 LUT3 4F (aB)+c + 18539 LUT4 7077 /AB\(d+C) + 18540 LUT3 8F (AB)+c + 18541 LUT3 80 ABC + 18542 LUT4 0BBB /aB\(d+c) + 18543 LUT3 80 ABC + 18544 LUT3 80 ABC + 18545 LUT3 4F (aB)+c + 18546 LUT4 0BBB /aB\(d+c) + 18547 LUT3 4F (aB)+c + 18548 LUT4 0BBB /aB\(d+c) + 18549 LUT3 4F (aB)+c + 18550 LUT4 0BBB /aB\(d+c) + 18551 LUT3 4F (aB)+c + 18552 LUT4 0BBB /aB\(d+c) + 18553 LUT3 4F (aB)+c + 18554 LUT4 0BBB /aB\(d+c) + 18555 LUT3 4F (aB)+c + 18556 LUT4 0BBB /aB\(d+c) + 18557 LUT3 4F (aB)+c + 18558 LUT4 0BBB /aB\(d+c) + 18559 LUT3 4F (aB)+c + 18560 LUT4 7077 /AB\(d+C) + 18561 LUT3 4F (aB)+c + 18562 LUT4 7077 /AB\(d+C) + 18563 LUT3 4F (aB)+c + 18564 LUT4 7077 /AB\(d+C) + 18565 LUT3 4F (aB)+c + 18566 LUT4 7077 /AB\(d+C) + 18567 LUT3 4F (aB)+c + 18568 LUT4 7077 /AB\(d+C) + 18569 LUT3 4F (aB)+c + 18570 LUT4 7077 /AB\(d+C) + 18571 LUT3 4F (aB)+c + 18572 LUT4 7077 /AB\(d+C) + 18573 LUT3 4F (aB)+c + 18574 LUT4 7077 /AB\(d+C) + 18575 LUT3 4F (aB)+c + 18576 LUT4 7077 /AB\(d+C) + 18577 LUT3 4F (aB)+c + 18578 LUT4 7077 /AB\(d+C) + 18579 LUT3 4F (aB)+c + 18580 LUT4 7077 /AB\(d+C) + 18581 LUT3 4F (aB)+c + 18582 LUT4 7077 /AB\(d+C) + 18583 LUT3 4F (aB)+c + 18584 LUT4 7077 /AB\(d+C) + 18585 LUT3 4F (aB)+c + 18586 LUT4 7077 /AB\(d+C) + 18587 LUT3 4F (aB)+c + 18588 LUT4 7077 /AB\(d+C) + 18589 LUT3 4F (aB)+c + 18590 LUT4 7077 /AB\(d+C) + 18591 LUT3 4F (aB)+c + 18592 LUT4 7077 /AB\(d+C) + 18593 LUT3 4F (aB)+c + 18594 LUT4 7077 /AB\(d+C) + 18595 LUT3 4F (aB)+c + 18596 LUT4 7077 /AB\(d+C) + 18597 LUT3 4F (aB)+c + 18598 LUT4 7077 /AB\(d+C) + 18599 LUT3 4F (aB)+c + 18600 LUT4 7077 /AB\(d+C) + 18601 LUT3 4F (aB)+c + 18602 LUT4 7077 /AB\(d+C) + 18603 LUT3 4F (aB)+c + 18604 LUT4 7077 /AB\(d+C) + 18605 LUT3 4F (aB)+c + 18606 LUT4 7077 /AB\(d+C) + 18607 LUT3 8F (AB)+c + 18608 LUT3 80 ABC + 18609 LUT4 0BBB /aB\(d+c) + 18610 LUT3 80 ABC + 18611 LUT3 80 ABC + 18612 LUT3 4F (aB)+c + 18613 LUT4 0BBB /aB\(d+c) + 18614 LUT3 4F (aB)+c + 18615 LUT4 0BBB /aB\(d+c) + 18616 LUT3 4F (aB)+c + 18617 LUT4 0BBB /aB\(d+c) + 18618 LUT3 4F (aB)+c + 18619 LUT4 0BBB /aB\(d+c) + 18620 LUT3 4F (aB)+c + 18621 LUT4 0BBB /aB\(d+c) + 18622 LUT3 4F (aB)+c + 18623 LUT4 0BBB /aB\(d+c) + 18624 LUT3 4F (aB)+c + 18625 LUT4 0BBB /aB\(d+c) + 18626 LUT3 4F (aB)+c + 18627 LUT4 7077 /AB\(d+C) + 18628 LUT3 4F (aB)+c + 18629 LUT4 7077 /AB\(d+C) + 18630 LUT3 4F (aB)+c + 18631 LUT4 7077 /AB\(d+C) + 18632 LUT3 4F (aB)+c + 18633 LUT4 7077 /AB\(d+C) + 18634 LUT3 4F (aB)+c + 18635 LUT4 7077 /AB\(d+C) + 18636 LUT3 4F (aB)+c + 18637 LUT4 7077 /AB\(d+C) + 18638 LUT3 4F (aB)+c + 18639 LUT4 7077 /AB\(d+C) + 18640 LUT3 4F (aB)+c + 18641 LUT4 7077 /AB\(d+C) + 18642 LUT3 4F (aB)+c + 18643 LUT4 7077 /AB\(d+C) + 18644 LUT3 4F (aB)+c + 18645 LUT4 7077 /AB\(d+C) + 18646 LUT3 4F (aB)+c + 18647 LUT4 7077 /AB\(d+C) + 18648 LUT3 4F (aB)+c + 18649 LUT4 7077 /AB\(d+C) + 18650 LUT3 4F (aB)+c + 18651 LUT4 7077 /AB\(d+C) + 18652 LUT3 4F (aB)+c + 18653 LUT4 7077 /AB\(d+C) + 18654 LUT3 4F (aB)+c + 18655 LUT4 7077 /AB\(d+C) + 18656 LUT3 4F (aB)+c + 18657 LUT4 7077 /AB\(d+C) + 18658 LUT3 4F (aB)+c + 18659 LUT4 7077 /AB\(d+C) + 18660 LUT3 4F (aB)+c + 18661 LUT4 7077 /AB\(d+C) + 18662 LUT3 4F (aB)+c + 18663 LUT4 7077 /AB\(d+C) + 18664 LUT3 4F (aB)+c + 18665 LUT4 7077 /AB\(d+C) + 18666 LUT3 4F (aB)+c + 18667 LUT4 7077 /AB\(d+C) + 18668 LUT3 4F (aB)+c + 18669 LUT4 7077 /AB\(d+C) + 18670 LUT3 4F (aB)+c + 18671 LUT4 7077 /AB\(d+C) + 18672 LUT3 4F (aB)+c + 18673 LUT4 7077 /AB\(d+C) + 18674 LUT3 8F (AB)+c + 18675 LUT3 80 ABC + 18676 LUT4 0BBB /aB\(d+c) + 18677 LUT4 8000 ABCD + 18678 LUT3 80 ABC + 18679 LUT3 4F (aB)+c + 18680 LUT4 0BBB /aB\(d+c) + 18681 LUT3 4F (aB)+c + 18682 LUT4 0BBB /aB\(d+c) + 18683 LUT3 4F (aB)+c + 18684 LUT4 0BBB /aB\(d+c) + 18685 LUT3 4F (aB)+c + 18686 LUT4 0BBB /aB\(d+c) + 18687 LUT3 4F (aB)+c + 18688 LUT4 0BBB /aB\(d+c) + 18689 LUT3 4F (aB)+c + 18690 LUT4 0BBB /aB\(d+c) + 18691 LUT3 4F (aB)+c + 18692 LUT4 0BBB /aB\(d+c) + 18693 LUT3 4F (aB)+c + 18694 LUT4 7077 /AB\(d+C) + 18695 LUT3 4F (aB)+c + 18696 LUT4 7077 /AB\(d+C) + 18697 LUT3 4F (aB)+c + 18698 LUT4 7077 /AB\(d+C) + 18699 LUT3 4F (aB)+c + 18700 LUT4 7077 /AB\(d+C) + 18701 LUT3 4F (aB)+c + 18702 LUT4 7077 /AB\(d+C) + 18703 LUT3 4F (aB)+c + 18704 LUT4 7077 /AB\(d+C) + 18705 LUT3 4F (aB)+c + 18706 LUT4 7077 /AB\(d+C) + 18707 LUT3 4F (aB)+c + 18708 LUT4 7077 /AB\(d+C) + 18709 LUT3 4F (aB)+c + 18710 LUT4 7077 /AB\(d+C) + 18711 LUT3 4F (aB)+c + 18712 LUT4 7077 /AB\(d+C) + 18713 LUT3 4F (aB)+c + 18714 LUT4 7077 /AB\(d+C) + 18715 LUT3 4F (aB)+c + 18716 LUT4 7077 /AB\(d+C) + 18717 LUT3 4F (aB)+c + 18718 LUT4 7077 /AB\(d+C) + 18719 LUT3 4F (aB)+c + 18720 LUT4 7077 /AB\(d+C) + 18721 LUT3 4F (aB)+c + 18722 LUT4 7077 /AB\(d+C) + 18723 LUT3 4F (aB)+c + 18724 LUT4 7077 /AB\(d+C) + 18725 LUT3 4F (aB)+c + 18726 LUT4 7077 /AB\(d+C) + 18727 LUT3 4F (aB)+c + 18728 LUT4 7077 /AB\(d+C) + 18729 LUT3 4F (aB)+c + 18730 LUT4 7077 /AB\(d+C) + 18731 LUT3 4F (aB)+c + 18732 LUT4 7077 /AB\(d+C) + 18733 LUT3 4F (aB)+c + 18734 LUT4 7077 /AB\(d+C) + 18735 LUT3 4F (aB)+c + 18736 LUT4 7077 /AB\(d+C) + 18737 LUT3 4F (aB)+c + 18738 LUT4 7077 /AB\(d+C) + 18739 LUT3 4F (aB)+c + 18740 LUT4 7077 /AB\(d+C) + 18741 LUT3 8F (AB)+c + 18742 LUT4 8000 ABCD + 18743 LUT4 0BBB /aB\(d+c) + 18744 LUT3 80 ABC + 18745 LUT4 8000 ABCD + 18746 LUT3 4F (aB)+c + 18747 LUT4 0BBB /aB\(d+c) + 18748 LUT3 4F (aB)+c + 18749 LUT4 0BBB /aB\(d+c) + 18750 LUT3 4F (aB)+c + 18751 LUT4 0BBB /aB\(d+c) + 18752 LUT3 4F (aB)+c + 18753 LUT4 0BBB /aB\(d+c) + 18754 LUT3 4F (aB)+c + 18755 LUT4 0BBB /aB\(d+c) + 18756 LUT3 4F (aB)+c + 18757 LUT4 0BBB /aB\(d+c) + 18758 LUT3 4F (aB)+c + 18759 LUT4 0BBB /aB\(d+c) + 18760 LUT3 4F (aB)+c + 18761 LUT4 7077 /AB\(d+C) + 18762 LUT3 4F (aB)+c + 18763 LUT4 7077 /AB\(d+C) + 18764 LUT3 4F (aB)+c + 18765 LUT4 7077 /AB\(d+C) + 18766 LUT3 4F (aB)+c + 18767 LUT4 7077 /AB\(d+C) + 18768 LUT3 4F (aB)+c + 18769 LUT4 7077 /AB\(d+C) + 18770 LUT3 4F (aB)+c + 18771 LUT4 7077 /AB\(d+C) + 18772 LUT3 4F (aB)+c + 18773 LUT4 7077 /AB\(d+C) + 18774 LUT3 4F (aB)+c + 18775 LUT4 7077 /AB\(d+C) + 18776 LUT3 4F (aB)+c + 18777 LUT4 7077 /AB\(d+C) + 18778 LUT3 4F (aB)+c + 18779 LUT4 7077 /AB\(d+C) + 18780 LUT3 4F (aB)+c + 18781 LUT4 7077 /AB\(d+C) + 18782 LUT3 4F (aB)+c + 18783 LUT4 7077 /AB\(d+C) + 18784 LUT3 4F (aB)+c + 18785 LUT4 7077 /AB\(d+C) + 18786 LUT3 4F (aB)+c + 18787 LUT4 7077 /AB\(d+C) + 18788 LUT3 4F (aB)+c + 18789 LUT4 7077 /AB\(d+C) + 18790 LUT3 4F (aB)+c + 18791 LUT4 7077 /AB\(d+C) + 18792 LUT3 4F (aB)+c + 18793 LUT4 7077 /AB\(d+C) + 18794 LUT3 4F (aB)+c + 18795 LUT4 7077 /AB\(d+C) + 18796 LUT3 4F (aB)+c + 18797 LUT4 7077 /AB\(d+C) + 18798 LUT3 4F (aB)+c + 18799 LUT4 7077 /AB\(d+C) + 18800 LUT3 4F (aB)+c + 18801 LUT4 7077 /AB\(d+C) + 18802 LUT3 4F (aB)+c + 18803 LUT4 7077 /AB\(d+C) + 18804 LUT3 4F (aB)+c + 18805 LUT4 7077 /AB\(d+C) + 18806 LUT3 4F (aB)+c + 18807 LUT4 7077 /AB\(d+C) + 18808 LUT3 8F (AB)+c + 18809 LUT3 80 ABC + 18810 LUT4 0BBB /aB\(d+c) + 18811 LUT3 80 ABC + 18812 LUT3 80 ABC + 18813 LUT3 4F (aB)+c + 18814 LUT4 0BBB /aB\(d+c) + 18815 LUT3 4F (aB)+c + 18816 LUT4 0BBB /aB\(d+c) + 18817 LUT3 4F (aB)+c + 18818 LUT4 0BBB /aB\(d+c) + 18819 LUT3 4F (aB)+c + 18820 LUT4 0BBB /aB\(d+c) + 18821 LUT3 4F (aB)+c + 18822 LUT4 0BBB /aB\(d+c) + 18823 LUT3 4F (aB)+c + 18824 LUT4 0BBB /aB\(d+c) + 18825 LUT3 4F (aB)+c + 18826 LUT4 0BBB /aB\(d+c) + 18827 LUT3 4F (aB)+c + 18828 LUT4 7077 /AB\(d+C) + 18829 LUT3 4F (aB)+c + 18830 LUT4 7077 /AB\(d+C) + 18831 LUT3 4F (aB)+c + 18832 LUT4 7077 /AB\(d+C) + 18833 LUT3 4F (aB)+c + 18834 LUT4 7077 /AB\(d+C) + 18835 LUT3 4F (aB)+c + 18836 LUT4 7077 /AB\(d+C) + 18837 LUT3 4F (aB)+c + 18838 LUT4 7077 /AB\(d+C) + 18839 LUT3 4F (aB)+c + 18840 LUT4 7077 /AB\(d+C) + 18841 LUT3 4F (aB)+c + 18842 LUT4 7077 /AB\(d+C) + 18843 LUT3 4F (aB)+c + 18844 LUT4 7077 /AB\(d+C) + 18845 LUT3 4F (aB)+c + 18846 LUT4 7077 /AB\(d+C) + 18847 LUT3 4F (aB)+c + 18848 LUT4 7077 /AB\(d+C) + 18849 LUT3 4F (aB)+c + 18850 LUT4 7077 /AB\(d+C) + 18851 LUT3 4F (aB)+c + 18852 LUT4 7077 /AB\(d+C) + 18853 LUT3 4F (aB)+c + 18854 LUT4 7077 /AB\(d+C) + 18855 LUT3 4F (aB)+c + 18856 LUT4 7077 /AB\(d+C) + 18857 LUT3 4F (aB)+c + 18858 LUT4 7077 /AB\(d+C) + 18859 LUT3 4F (aB)+c + 18860 LUT4 7077 /AB\(d+C) + 18861 LUT3 4F (aB)+c + 18862 LUT4 7077 /AB\(d+C) + 18863 LUT3 4F (aB)+c + 18864 LUT4 7077 /AB\(d+C) + 18865 LUT3 4F (aB)+c + 18866 LUT4 7077 /AB\(d+C) + 18867 LUT3 4F (aB)+c + 18868 LUT4 7077 /AB\(d+C) + 18869 LUT3 4F (aB)+c + 18870 LUT4 7077 /AB\(d+C) + 18871 LUT3 4F (aB)+c + 18872 LUT4 7077 /AB\(d+C) + 18873 LUT3 4F (aB)+c + 18874 LUT4 7077 /AB\(d+C) + 18875 LUT3 8F (AB)+c + 18876 LUT3 80 ABC + 18877 LUT4 0BBB /aB\(d+c) + 18878 LUT3 80 ABC + 18879 LUT3 80 ABC + 18880 LUT3 4F (aB)+c + 18881 LUT4 0BBB /aB\(d+c) + 18882 LUT3 4F (aB)+c + 18883 LUT4 0BBB /aB\(d+c) + 18884 LUT3 4F (aB)+c + 18885 LUT4 0BBB /aB\(d+c) + 18886 LUT3 4F (aB)+c + 18887 LUT4 0BBB /aB\(d+c) + 18888 LUT3 4F (aB)+c + 18889 LUT4 0BBB /aB\(d+c) + 18890 LUT3 4F (aB)+c + 18891 LUT4 0BBB /aB\(d+c) + 18892 LUT3 4F (aB)+c + 18893 LUT4 0BBB /aB\(d+c) + 18894 LUT3 4F (aB)+c + 18895 LUT4 7077 /AB\(d+C) + 18896 LUT3 4F (aB)+c + 18897 LUT4 7077 /AB\(d+C) + 18898 LUT3 4F (aB)+c + 18899 LUT4 7077 /AB\(d+C) + 18900 LUT3 4F (aB)+c + 18901 LUT4 7077 /AB\(d+C) + 18902 LUT3 4F (aB)+c + 18903 LUT4 7077 /AB\(d+C) + 18904 LUT3 4F (aB)+c + 18905 LUT4 7077 /AB\(d+C) + 18906 LUT3 4F (aB)+c + 18907 LUT4 7077 /AB\(d+C) + 18908 LUT3 4F (aB)+c + 18909 LUT4 7077 /AB\(d+C) + 18910 LUT3 4F (aB)+c + 18911 LUT4 7077 /AB\(d+C) + 18912 LUT3 4F (aB)+c + 18913 LUT4 7077 /AB\(d+C) + 18914 LUT3 4F (aB)+c + 18915 LUT4 7077 /AB\(d+C) + 18916 LUT3 4F (aB)+c + 18917 LUT4 7077 /AB\(d+C) + 18918 LUT3 4F (aB)+c + 18919 LUT4 7077 /AB\(d+C) + 18920 LUT3 4F (aB)+c + 18921 LUT4 7077 /AB\(d+C) + 18922 LUT3 4F (aB)+c + 18923 LUT4 7077 /AB\(d+C) + 18924 LUT3 4F (aB)+c + 18925 LUT4 7077 /AB\(d+C) + 18926 LUT3 4F (aB)+c + 18927 LUT4 7077 /AB\(d+C) + 18928 LUT3 4F (aB)+c + 18929 LUT4 7077 /AB\(d+C) + 18930 LUT3 4F (aB)+c + 18931 LUT4 7077 /AB\(d+C) + 18932 LUT3 4F (aB)+c + 18933 LUT4 7077 /AB\(d+C) + 18934 LUT3 4F (aB)+c + 18935 LUT4 7077 /AB\(d+C) + 18936 LUT3 4F (aB)+c + 18937 LUT4 7077 /AB\(d+C) + 18938 LUT3 4F (aB)+c + 18939 LUT4 7077 /AB\(d+C) + 18940 LUT3 4F (aB)+c + 18941 LUT4 7077 /AB\(d+C) + 18942 LUT3 8F (AB)+c + 18943 LUT3 80 ABC + 18944 LUT4 0BBB /aB\(d+c) + 18945 LUT4 8000 ABCD + 18946 LUT3 80 ABC + 18947 LUT3 4F (aB)+c + 18948 LUT4 0BBB /aB\(d+c) + 18949 LUT3 4F (aB)+c + 18950 LUT4 0BBB /aB\(d+c) + 18951 LUT3 4F (aB)+c + 18952 LUT4 0BBB /aB\(d+c) + 18953 LUT3 4F (aB)+c + 18954 LUT4 0BBB /aB\(d+c) + 18955 LUT3 4F (aB)+c + 18956 LUT4 0BBB /aB\(d+c) + 18957 LUT3 4F (aB)+c + 18958 LUT4 0BBB /aB\(d+c) + 18959 LUT3 4F (aB)+c + 18960 LUT4 0BBB /aB\(d+c) + 18961 LUT3 4F (aB)+c + 18962 LUT4 7077 /AB\(d+C) + 18963 LUT3 4F (aB)+c + 18964 LUT4 7077 /AB\(d+C) + 18965 LUT3 4F (aB)+c + 18966 LUT4 7077 /AB\(d+C) + 18967 LUT3 4F (aB)+c + 18968 LUT4 7077 /AB\(d+C) + 18969 LUT3 4F (aB)+c + 18970 LUT4 7077 /AB\(d+C) + 18971 LUT3 4F (aB)+c + 18972 LUT4 7077 /AB\(d+C) + 18973 LUT3 4F (aB)+c + 18974 LUT4 7077 /AB\(d+C) + 18975 LUT3 4F (aB)+c + 18976 LUT4 7077 /AB\(d+C) + 18977 LUT3 4F (aB)+c + 18978 LUT4 7077 /AB\(d+C) + 18979 LUT3 4F (aB)+c + 18980 LUT4 7077 /AB\(d+C) + 18981 LUT3 4F (aB)+c + 18982 LUT4 7077 /AB\(d+C) + 18983 LUT3 4F (aB)+c + 18984 LUT4 7077 /AB\(d+C) + 18985 LUT3 4F (aB)+c + 18986 LUT4 7077 /AB\(d+C) + 18987 LUT3 4F (aB)+c + 18988 LUT4 7077 /AB\(d+C) + 18989 LUT3 4F (aB)+c + 18990 LUT4 7077 /AB\(d+C) + 18991 LUT3 4F (aB)+c + 18992 LUT4 7077 /AB\(d+C) + 18993 LUT3 4F (aB)+c + 18994 LUT4 7077 /AB\(d+C) + 18995 LUT3 4F (aB)+c + 18996 LUT4 7077 /AB\(d+C) + 18997 LUT3 4F (aB)+c + 18998 LUT4 7077 /AB\(d+C) + 18999 LUT3 4F (aB)+c + 19000 LUT4 7077 /AB\(d+C) + 19001 LUT3 4F (aB)+c + 19002 LUT4 7077 /AB\(d+C) + 19003 LUT3 4F (aB)+c + 19004 LUT4 7077 /AB\(d+C) + 19005 LUT3 4F (aB)+c + 19006 LUT4 7077 /AB\(d+C) + 19007 LUT3 4F (aB)+c + 19008 LUT4 7077 /AB\(d+C) + 19009 LUT3 8F (AB)+c + 19010 LUT4 8000 ABCD + 19011 LUT4 0BBB /aB\(d+c) + 19012 LUT3 80 ABC + 19013 LUT4 8000 ABCD + 19014 LUT3 4F (aB)+c + 19015 LUT4 0BBB /aB\(d+c) + 19016 LUT3 4F (aB)+c + 19017 LUT4 0BBB /aB\(d+c) + 19018 LUT3 4F (aB)+c + 19019 LUT4 0BBB /aB\(d+c) + 19020 LUT3 4F (aB)+c + 19021 LUT4 0BBB /aB\(d+c) + 19022 LUT3 4F (aB)+c + 19023 LUT4 0BBB /aB\(d+c) + 19024 LUT3 4F (aB)+c + 19025 LUT4 0BBB /aB\(d+c) + 19026 LUT3 4F (aB)+c + 19027 LUT4 0BBB /aB\(d+c) + 19028 LUT3 4F (aB)+c + 19029 LUT4 7077 /AB\(d+C) + 19030 LUT3 4F (aB)+c + 19031 LUT4 7077 /AB\(d+C) + 19032 LUT3 4F (aB)+c + 19033 LUT4 7077 /AB\(d+C) + 19034 LUT3 4F (aB)+c + 19035 LUT4 7077 /AB\(d+C) + 19036 LUT3 4F (aB)+c + 19037 LUT4 7077 /AB\(d+C) + 19038 LUT3 4F (aB)+c + 19039 LUT4 7077 /AB\(d+C) + 19040 LUT3 4F (aB)+c + 19041 LUT4 7077 /AB\(d+C) + 19042 LUT3 4F (aB)+c + 19043 LUT4 7077 /AB\(d+C) + 19044 LUT3 4F (aB)+c + 19045 LUT4 7077 /AB\(d+C) + 19046 LUT3 4F (aB)+c + 19047 LUT4 7077 /AB\(d+C) + 19048 LUT3 4F (aB)+c + 19049 LUT4 7077 /AB\(d+C) + 19050 LUT3 4F (aB)+c + 19051 LUT4 7077 /AB\(d+C) + 19052 LUT3 4F (aB)+c + 19053 LUT4 7077 /AB\(d+C) + 19054 LUT3 4F (aB)+c + 19055 LUT4 7077 /AB\(d+C) + 19056 LUT3 4F (aB)+c + 19057 LUT4 7077 /AB\(d+C) + 19058 LUT3 4F (aB)+c + 19059 LUT4 7077 /AB\(d+C) + 19060 LUT3 4F (aB)+c + 19061 LUT4 7077 /AB\(d+C) + 19062 LUT3 4F (aB)+c + 19063 LUT4 7077 /AB\(d+C) + 19064 LUT3 4F (aB)+c + 19065 LUT4 7077 /AB\(d+C) + 19066 LUT3 4F (aB)+c + 19067 LUT4 7077 /AB\(d+C) + 19068 LUT3 4F (aB)+c + 19069 LUT4 7077 /AB\(d+C) + 19070 LUT3 4F (aB)+c + 19071 LUT4 7077 /AB\(d+C) + 19072 LUT3 4F (aB)+c + 19073 LUT4 7077 /AB\(d+C) + 19074 LUT3 4F (aB)+c + 19075 LUT4 7077 /AB\(d+C) + 19076 LUT3 8F (AB)+c + 19077 LUT3 80 ABC + 19078 LUT4 0BBB /aB\(d+c) + 19079 LUT3 80 ABC + 19080 LUT3 80 ABC + 19081 LUT3 4F (aB)+c + 19082 LUT4 0BBB /aB\(d+c) + 19083 LUT3 4F (aB)+c + 19084 LUT4 0BBB /aB\(d+c) + 19085 LUT3 4F (aB)+c + 19086 LUT4 0BBB /aB\(d+c) + 19087 LUT3 4F (aB)+c + 19088 LUT4 0BBB /aB\(d+c) + 19089 LUT3 4F (aB)+c + 19090 LUT4 0BBB /aB\(d+c) + 19091 LUT3 4F (aB)+c + 19092 LUT4 0BBB /aB\(d+c) + 19093 LUT3 4F (aB)+c + 19094 LUT4 0BBB /aB\(d+c) + 19095 LUT3 4F (aB)+c + 19096 LUT4 7077 /AB\(d+C) + 19097 LUT3 4F (aB)+c + 19098 LUT4 7077 /AB\(d+C) + 19099 LUT3 4F (aB)+c + 19100 LUT4 7077 /AB\(d+C) + 19101 LUT3 4F (aB)+c + 19102 LUT4 7077 /AB\(d+C) + 19103 LUT3 4F (aB)+c + 19104 LUT4 7077 /AB\(d+C) + 19105 LUT3 4F (aB)+c + 19106 LUT4 7077 /AB\(d+C) + 19107 LUT3 4F (aB)+c + 19108 LUT4 7077 /AB\(d+C) + 19109 LUT3 4F (aB)+c + 19110 LUT4 7077 /AB\(d+C) + 19111 LUT3 4F (aB)+c + 19112 LUT4 7077 /AB\(d+C) + 19113 LUT3 4F (aB)+c + 19114 LUT4 7077 /AB\(d+C) + 19115 LUT3 4F (aB)+c + 19116 LUT4 7077 /AB\(d+C) + 19117 LUT3 4F (aB)+c + 19118 LUT4 7077 /AB\(d+C) + 19119 LUT3 4F (aB)+c + 19120 LUT4 7077 /AB\(d+C) + 19121 LUT3 4F (aB)+c + 19122 LUT4 7077 /AB\(d+C) + 19123 LUT3 4F (aB)+c + 19124 LUT4 7077 /AB\(d+C) + 19125 LUT3 4F (aB)+c + 19126 LUT4 7077 /AB\(d+C) + 19127 LUT3 4F (aB)+c + 19128 LUT4 7077 /AB\(d+C) + 19129 LUT3 4F (aB)+c + 19130 LUT4 7077 /AB\(d+C) + 19131 LUT3 4F (aB)+c + 19132 LUT4 7077 /AB\(d+C) + 19133 LUT3 4F (aB)+c + 19134 LUT4 7077 /AB\(d+C) + 19135 LUT3 4F (aB)+c + 19136 LUT4 7077 /AB\(d+C) + 19137 LUT3 4F (aB)+c + 19138 LUT4 7077 /AB\(d+C) + 19139 LUT3 4F (aB)+c + 19140 LUT4 7077 /AB\(d+C) + 19141 LUT3 4F (aB)+c + 19142 LUT4 7077 /AB\(d+C) + 19143 LUT3 8F (AB)+c + 19144 LUT3 80 ABC + 19145 LUT4 0BBB /aB\(d+c) + 19146 LUT3 80 ABC + 19147 LUT3 80 ABC + 19148 LUT3 4F (aB)+c + 19149 LUT4 0BBB /aB\(d+c) + 19150 LUT3 4F (aB)+c + 19151 LUT4 0BBB /aB\(d+c) + 19152 LUT3 4F (aB)+c + 19153 LUT4 0BBB /aB\(d+c) + 19154 LUT3 4F (aB)+c + 19155 LUT4 0BBB /aB\(d+c) + 19156 LUT3 4F (aB)+c + 19157 LUT4 0BBB /aB\(d+c) + 19158 LUT3 4F (aB)+c + 19159 LUT4 0BBB /aB\(d+c) + 19160 LUT3 4F (aB)+c + 19161 LUT4 0BBB /aB\(d+c) + 19162 LUT3 4F (aB)+c + 19163 LUT4 7077 /AB\(d+C) + 19164 LUT3 4F (aB)+c + 19165 LUT4 7077 /AB\(d+C) + 19166 LUT3 4F (aB)+c + 19167 LUT4 7077 /AB\(d+C) + 19168 LUT3 4F (aB)+c + 19169 LUT4 7077 /AB\(d+C) + 19170 LUT3 4F (aB)+c + 19171 LUT4 7077 /AB\(d+C) + 19172 LUT3 4F (aB)+c + 19173 LUT4 7077 /AB\(d+C) + 19174 LUT3 4F (aB)+c + 19175 LUT4 7077 /AB\(d+C) + 19176 LUT3 4F (aB)+c + 19177 LUT4 7077 /AB\(d+C) + 19178 LUT3 4F (aB)+c + 19179 LUT4 7077 /AB\(d+C) + 19180 LUT3 4F (aB)+c + 19181 LUT4 7077 /AB\(d+C) + 19182 LUT3 4F (aB)+c + 19183 LUT4 7077 /AB\(d+C) + 19184 LUT3 4F (aB)+c + 19185 LUT4 7077 /AB\(d+C) + 19186 LUT3 4F (aB)+c + 19187 LUT4 7077 /AB\(d+C) + 19188 LUT3 4F (aB)+c + 19189 LUT4 7077 /AB\(d+C) + 19190 LUT3 4F (aB)+c + 19191 LUT4 7077 /AB\(d+C) + 19192 LUT3 4F (aB)+c + 19193 LUT4 7077 /AB\(d+C) + 19194 LUT3 4F (aB)+c + 19195 LUT4 7077 /AB\(d+C) + 19196 LUT3 4F (aB)+c + 19197 LUT4 7077 /AB\(d+C) + 19198 LUT3 4F (aB)+c + 19199 LUT4 7077 /AB\(d+C) + 19200 LUT3 4F (aB)+c + 19201 LUT4 7077 /AB\(d+C) + 19202 LUT3 4F (aB)+c + 19203 LUT4 7077 /AB\(d+C) + 19204 LUT3 4F (aB)+c + 19205 LUT4 7077 /AB\(d+C) + 19206 LUT3 4F (aB)+c + 19207 LUT4 7077 /AB\(d+C) + 19208 LUT3 4F (aB)+c + 19209 LUT4 7077 /AB\(d+C) + 19210 LUT3 8F (AB)+c + 19211 LUT3 80 ABC + 19212 LUT4 0BBB /aB\(d+c) + 19213 LUT4 8000 ABCD + 19214 LUT3 80 ABC + 19215 LUT3 4F (aB)+c + 19216 LUT4 0BBB /aB\(d+c) + 19217 LUT3 4F (aB)+c + 19218 LUT4 0BBB /aB\(d+c) + 19219 LUT3 4F (aB)+c + 19220 LUT4 0BBB /aB\(d+c) + 19221 LUT3 4F (aB)+c + 19222 LUT4 0BBB /aB\(d+c) + 19223 LUT3 4F (aB)+c + 19224 LUT4 0BBB /aB\(d+c) + 19225 LUT3 4F (aB)+c + 19226 LUT4 0BBB /aB\(d+c) + 19227 LUT3 4F (aB)+c + 19228 LUT4 0BBB /aB\(d+c) + 19229 LUT3 4F (aB)+c + 19230 LUT4 7077 /AB\(d+C) + 19231 LUT3 4F (aB)+c + 19232 LUT4 7077 /AB\(d+C) + 19233 LUT3 4F (aB)+c + 19234 LUT4 7077 /AB\(d+C) + 19235 LUT3 4F (aB)+c + 19236 LUT4 7077 /AB\(d+C) + 19237 LUT3 4F (aB)+c + 19238 LUT4 7077 /AB\(d+C) + 19239 LUT3 4F (aB)+c + 19240 LUT4 7077 /AB\(d+C) + 19241 LUT3 4F (aB)+c + 19242 LUT4 7077 /AB\(d+C) + 19243 LUT3 4F (aB)+c + 19244 LUT4 7077 /AB\(d+C) + 19245 LUT3 4F (aB)+c + 19246 LUT4 7077 /AB\(d+C) + 19247 LUT3 4F (aB)+c + 19248 LUT4 7077 /AB\(d+C) + 19249 LUT3 4F (aB)+c + 19250 LUT4 7077 /AB\(d+C) + 19251 LUT3 4F (aB)+c + 19252 LUT4 7077 /AB\(d+C) + 19253 LUT3 4F (aB)+c + 19254 LUT4 7077 /AB\(d+C) + 19255 LUT3 4F (aB)+c + 19256 LUT4 7077 /AB\(d+C) + 19257 LUT3 4F (aB)+c + 19258 LUT4 7077 /AB\(d+C) + 19259 LUT3 4F (aB)+c + 19260 LUT4 7077 /AB\(d+C) + 19261 LUT3 4F (aB)+c + 19262 LUT4 7077 /AB\(d+C) + 19263 LUT3 4F (aB)+c + 19264 LUT4 7077 /AB\(d+C) + 19265 LUT3 4F (aB)+c + 19266 LUT4 7077 /AB\(d+C) + 19267 LUT3 4F (aB)+c + 19268 LUT4 7077 /AB\(d+C) + 19269 LUT3 4F (aB)+c + 19270 LUT4 7077 /AB\(d+C) + 19271 LUT3 4F (aB)+c + 19272 LUT4 7077 /AB\(d+C) + 19273 LUT3 4F (aB)+c + 19274 LUT4 7077 /AB\(d+C) + 19275 LUT3 4F (aB)+c + 19276 LUT4 7077 /AB\(d+C) + 19277 LUT3 8F (AB)+c + 19278 LUT4 8000 ABCD + 19279 LUT4 0BBB /aB\(d+c) + 19280 LUT3 80 ABC + 19281 LUT4 8000 ABCD + 19282 LUT3 4F (aB)+c + 19283 LUT4 0BBB /aB\(d+c) + 19284 LUT3 4F (aB)+c + 19285 LUT4 0BBB /aB\(d+c) + 19286 LUT3 4F (aB)+c + 19287 LUT4 0BBB /aB\(d+c) + 19288 LUT3 4F (aB)+c + 19289 LUT4 0BBB /aB\(d+c) + 19290 LUT3 4F (aB)+c + 19291 LUT4 0BBB /aB\(d+c) + 19292 LUT3 4F (aB)+c + 19293 LUT4 0BBB /aB\(d+c) + 19294 LUT3 4F (aB)+c + 19295 LUT4 0BBB /aB\(d+c) + 19296 LUT3 4F (aB)+c + 19297 LUT4 7077 /AB\(d+C) + 19298 LUT3 4F (aB)+c + 19299 LUT4 7077 /AB\(d+C) + 19300 LUT3 4F (aB)+c + 19301 LUT4 7077 /AB\(d+C) + 19302 LUT3 4F (aB)+c + 19303 LUT4 7077 /AB\(d+C) + 19304 LUT3 4F (aB)+c + 19305 LUT4 7077 /AB\(d+C) + 19306 LUT3 4F (aB)+c + 19307 LUT4 7077 /AB\(d+C) + 19308 LUT3 4F (aB)+c + 19309 LUT4 7077 /AB\(d+C) + 19310 LUT3 4F (aB)+c + 19311 LUT4 7077 /AB\(d+C) + 19312 LUT3 4F (aB)+c + 19313 LUT4 7077 /AB\(d+C) + 19314 LUT3 4F (aB)+c + 19315 LUT4 7077 /AB\(d+C) + 19316 LUT3 4F (aB)+c + 19317 LUT4 7077 /AB\(d+C) + 19318 LUT3 4F (aB)+c + 19319 LUT4 7077 /AB\(d+C) + 19320 LUT3 4F (aB)+c + 19321 LUT4 7077 /AB\(d+C) + 19322 LUT3 4F (aB)+c + 19323 LUT4 7077 /AB\(d+C) + 19324 LUT3 4F (aB)+c + 19325 LUT4 7077 /AB\(d+C) + 19326 LUT3 4F (aB)+c + 19327 LUT4 7077 /AB\(d+C) + 19328 LUT3 4F (aB)+c + 19329 LUT4 7077 /AB\(d+C) + 19330 LUT3 4F (aB)+c + 19331 LUT4 7077 /AB\(d+C) + 19332 LUT3 4F (aB)+c + 19333 LUT4 7077 /AB\(d+C) + 19334 LUT3 4F (aB)+c + 19335 LUT4 7077 /AB\(d+C) + 19336 LUT3 4F (aB)+c + 19337 LUT4 7077 /AB\(d+C) + 19338 LUT3 4F (aB)+c + 19339 LUT4 7077 /AB\(d+C) + 19340 LUT3 4F (aB)+c + 19341 LUT4 7077 /AB\(d+C) + 19342 LUT3 4F (aB)+c + 19343 LUT4 7077 /AB\(d+C) + 19344 LUT3 8F (AB)+c + 19345 LUT3 80 ABC + 19346 LUT4 0BBB /aB\(d+c) + 19347 LUT3 80 ABC + 19348 LUT3 80 ABC + 19349 LUT3 4F (aB)+c + 19350 LUT4 0BBB /aB\(d+c) + 19351 LUT3 4F (aB)+c + 19352 LUT4 0BBB /aB\(d+c) + 19353 LUT3 4F (aB)+c + 19354 LUT4 0BBB /aB\(d+c) + 19355 LUT3 4F (aB)+c + 19356 LUT4 0BBB /aB\(d+c) + 19357 LUT3 4F (aB)+c + 19358 LUT4 0BBB /aB\(d+c) + 19359 LUT3 4F (aB)+c + 19360 LUT4 0BBB /aB\(d+c) + 19361 LUT3 4F (aB)+c + 19362 LUT4 0BBB /aB\(d+c) + 19363 LUT3 4F (aB)+c + 19364 LUT4 7077 /AB\(d+C) + 19365 LUT3 4F (aB)+c + 19366 LUT4 7077 /AB\(d+C) + 19367 LUT3 4F (aB)+c + 19368 LUT4 7077 /AB\(d+C) + 19369 LUT3 4F (aB)+c + 19370 LUT4 7077 /AB\(d+C) + 19371 LUT3 4F (aB)+c + 19372 LUT4 7077 /AB\(d+C) + 19373 LUT3 4F (aB)+c + 19374 LUT4 7077 /AB\(d+C) + 19375 LUT3 4F (aB)+c + 19376 LUT4 7077 /AB\(d+C) + 19377 LUT3 4F (aB)+c + 19378 LUT4 7077 /AB\(d+C) + 19379 LUT3 4F (aB)+c + 19380 LUT4 7077 /AB\(d+C) + 19381 LUT3 4F (aB)+c + 19382 LUT4 7077 /AB\(d+C) + 19383 LUT3 4F (aB)+c + 19384 LUT4 7077 /AB\(d+C) + 19385 LUT3 4F (aB)+c + 19386 LUT4 7077 /AB\(d+C) + 19387 LUT3 4F (aB)+c + 19388 LUT4 7077 /AB\(d+C) + 19389 LUT3 4F (aB)+c + 19390 LUT4 7077 /AB\(d+C) + 19391 LUT3 4F (aB)+c + 19392 LUT4 7077 /AB\(d+C) + 19393 LUT3 4F (aB)+c + 19394 LUT4 7077 /AB\(d+C) + 19395 LUT3 4F (aB)+c + 19396 LUT4 7077 /AB\(d+C) + 19397 LUT3 4F (aB)+c + 19398 LUT4 7077 /AB\(d+C) + 19399 LUT3 4F (aB)+c + 19400 LUT4 7077 /AB\(d+C) + 19401 LUT3 4F (aB)+c + 19402 LUT4 7077 /AB\(d+C) + 19403 LUT3 4F (aB)+c + 19404 LUT4 7077 /AB\(d+C) + 19405 LUT3 4F (aB)+c + 19406 LUT4 7077 /AB\(d+C) + 19407 LUT3 4F (aB)+c + 19408 LUT4 7077 /AB\(d+C) + 19409 LUT3 4F (aB)+c + 19410 LUT4 7077 /AB\(d+C) + 19411 LUT3 8F (AB)+c + 19412 LUT3 80 ABC + 19413 LUT4 0BBB /aB\(d+c) + 19414 LUT3 80 ABC + 19415 LUT3 80 ABC + 19416 LUT3 4F (aB)+c + 19417 LUT4 0BBB /aB\(d+c) + 19418 LUT3 4F (aB)+c + 19419 LUT4 0BBB /aB\(d+c) + 19420 LUT3 4F (aB)+c + 19421 LUT4 0BBB /aB\(d+c) + 19422 LUT3 4F (aB)+c + 19423 LUT4 0BBB /aB\(d+c) + 19424 LUT3 4F (aB)+c + 19425 LUT4 0BBB /aB\(d+c) + 19426 LUT3 4F (aB)+c + 19427 LUT4 0BBB /aB\(d+c) + 19428 LUT3 4F (aB)+c + 19429 LUT4 0BBB /aB\(d+c) + 19430 LUT3 4F (aB)+c + 19431 LUT4 7077 /AB\(d+C) + 19432 LUT3 4F (aB)+c + 19433 LUT4 7077 /AB\(d+C) + 19434 LUT3 4F (aB)+c + 19435 LUT4 7077 /AB\(d+C) + 19436 LUT3 4F (aB)+c + 19437 LUT4 7077 /AB\(d+C) + 19438 LUT3 4F (aB)+c + 19439 LUT4 7077 /AB\(d+C) + 19440 LUT3 4F (aB)+c + 19441 LUT4 7077 /AB\(d+C) + 19442 LUT3 4F (aB)+c + 19443 LUT4 7077 /AB\(d+C) + 19444 LUT3 4F (aB)+c + 19445 LUT4 7077 /AB\(d+C) + 19446 LUT3 4F (aB)+c + 19447 LUT4 7077 /AB\(d+C) + 19448 LUT3 4F (aB)+c + 19449 LUT4 7077 /AB\(d+C) + 19450 LUT3 4F (aB)+c + 19451 LUT4 7077 /AB\(d+C) + 19452 LUT3 4F (aB)+c + 19453 LUT4 7077 /AB\(d+C) + 19454 LUT3 4F (aB)+c + 19455 LUT4 7077 /AB\(d+C) + 19456 LUT3 4F (aB)+c + 19457 LUT4 7077 /AB\(d+C) + 19458 LUT3 4F (aB)+c + 19459 LUT4 7077 /AB\(d+C) + 19460 LUT3 4F (aB)+c + 19461 LUT4 7077 /AB\(d+C) + 19462 LUT3 4F (aB)+c + 19463 LUT4 7077 /AB\(d+C) + 19464 LUT3 4F (aB)+c + 19465 LUT4 7077 /AB\(d+C) + 19466 LUT3 4F (aB)+c + 19467 LUT4 7077 /AB\(d+C) + 19468 LUT3 4F (aB)+c + 19469 LUT4 7077 /AB\(d+C) + 19470 LUT3 4F (aB)+c + 19471 LUT4 7077 /AB\(d+C) + 19472 LUT3 4F (aB)+c + 19473 LUT4 7077 /AB\(d+C) + 19474 LUT3 4F (aB)+c + 19475 LUT4 7077 /AB\(d+C) + 19476 LUT3 4F (aB)+c + 19477 LUT4 7077 /AB\(d+C) + 19478 LUT3 FE /ab\+C + 19479 LUT3 FE /ab\+C + 19480 LUT3 FE /ab\+C + 19481 LUT3 FE /ab\+C + 19482 LUT3 FE /ab\+C + 19483 LUT3 FE /ab\+C + 19484 LUT3 FE /ab\+C + 19485 LUT3 FE /ab\+C + 19486 LUT3 FE /ab\+C + 19487 LUT3 FE /ab\+C + 19488 LUT3 FE /ab\+C + 19489 LUT3 FE /ab\+C + 19490 LUT3 FE /ab\+C + 19491 LUT3 FE /ab\+C + 19492 LUT3 FE /ab\+C + 19493 LUT3 FE /ab\+C + 19494 LUT3 FE /ab\+C + 19495 LUT3 FE /ab\+C + 19496 LUT3 FE /ab\+C + 19497 LUT3 FE /ab\+C + 19498 LUT3 FE /ab\+C + 19499 LUT3 FE /ab\+C + 19500 LUT3 FE /ab\+C + 19501 LUT3 FE /ab\+C + 19502 LUT3 FE /ab\+C + 19503 LUT3 FE /ab\+C + 19504 LUT3 FE /ab\+C + 19505 LUT3 FE /ab\+C + 19506 LUT3 FE /ab\+C + 19507 LUT3 FE /ab\+C + 19508 LUT3 FE /ab\+C + 19509 LUT4 00F4 ((aB)+C)d + 19510 LUT4 00F8 ((AB)+C)d + 19511 LUT2 E /ab\ + 19512 LUT2 8 AB + 19513 LUT4 8FFF (AB)+c+d + 19514 LUT4 004F ((aB)+c)d + 19515 LUT4 F331 BD?/Ac\:0:1:C + 19516 LUT2 4 aB + 19517 LUT4 0733 BD?1:0:c:ac + 19518 LUT3 07 c/AB\ + 19519 LUT3 F8 (AB)+C + 19520 LUT3 F8 (AB)+C + 19521 LUT3 8F (AB)+c + 19522 LUT4 F3F5 DC?a:b:1:1 + 19523 LUT3 8F (AB)+c + 19524 LUT4 F5F3 DC?b:a:1:1 + 19525 LUT2 4 aB + 19526 LUT4 050C DC?B:a:0:0 + 19527 LUT3 5C c?a:B + 19528 LUT3 CA C?A:B + 19529 LUT3 35 c?b:a + 19530 LUT4 050C DC?B:a:0:0 + 19531 LUT3 5C c?a:B + 19532 LUT3 CA C?A:B + 19533 LUT3 35 c?b:a + 19534 LUT4 050C DC?B:a:0:0 + 19535 LUT3 5C c?a:B + 19536 LUT3 CA C?A:B + 19537 LUT3 35 c?b:a + 19538 LUT4 050C DC?B:a:0:0 + 19539 LUT3 5C c?a:B + 19540 LUT3 CA C?A:B + 19541 LUT3 35 c?b:a + 19542 LUT4 050C DC?B:a:0:0 + 19543 LUT3 5C c?a:B + 19544 LUT3 CA C?A:B + 19545 LUT3 35 c?b:a + 19546 LUT4 050C DC?B:a:0:0 + 19547 LUT3 5C c?a:B + 19548 LUT3 CA C?A:B + 19549 LUT3 35 c?b:a + 19550 LUT4 050C DC?B:a:0:0 + 19551 LUT3 5C c?a:B + 19552 LUT3 CA C?A:B + 19553 LUT3 35 c?b:a + 19554 LUT4 050C DC?B:a:0:0 + 19555 LUT3 5C c?a:B + 19556 LUT3 CA C?A:B + 19557 LUT3 35 c?b:a + 19558 LUT4 050C DC?B:a:0:0 + 19559 LUT3 5C c?a:B + 19560 LUT3 CA C?A:B + 19561 LUT3 35 c?b:a + 19562 LUT4 050C DC?B:a:0:0 + 19563 LUT3 5C c?a:B + 19564 LUT3 CA C?A:B + 19565 LUT3 35 c?b:a + 19566 LUT4 050C DC?B:a:0:0 + 19567 LUT3 5C c?a:B + 19568 LUT3 CA C?A:B + 19569 LUT3 35 c?b:a + 19570 LUT4 050C DC?B:a:0:0 + 19571 LUT3 5C c?a:B + 19572 LUT3 CA C?A:B + 19573 LUT3 35 c?b:a + 19574 LUT4 050C DC?B:a:0:0 + 19575 LUT3 5C c?a:B + 19576 LUT3 CA C?A:B + 19577 LUT3 35 c?b:a + 19578 LUT4 050C DC?B:a:0:0 + 19579 LUT3 5C c?a:B + 19580 LUT3 CA C?A:B + 19581 LUT3 35 c?b:a + 19582 LUT4 0503 DC?b:a:0:0 + 19583 LUT3 AC c?A:B + 19584 LUT3 35 c?b:a + 19585 LUT4 0503 DC?b:a:0:0 + 19586 LUT3 AC c?A:B + 19587 LUT3 35 c?b:a + 19588 LUT4 0503 DC?b:a:0:0 + 19589 LUT3 AC c?A:B + 19590 LUT3 35 c?b:a + 19591 LUT4 0503 DC?b:a:0:0 + 19592 LUT3 AC c?A:B + 19593 LUT3 35 c?b:a + 19594 LUT4 0503 DC?b:a:0:0 + 19595 LUT3 AC c?A:B + 19596 LUT3 35 c?b:a + 19597 LUT4 0503 DC?b:a:0:0 + 19598 LUT3 AC c?A:B + 19599 LUT3 35 c?b:a + 19600 LUT4 0503 DC?b:a:0:0 + 19601 LUT3 AC c?A:B + 19602 LUT3 35 c?b:a + 19603 LUT4 0503 DC?b:a:0:0 + 19604 LUT3 AC c?A:B + 19605 LUT3 35 c?b:a + 19606 LUT4 0503 DC?b:a:0:0 + 19607 LUT3 AC c?A:B + 19608 LUT3 35 c?b:a + 19609 LUT4 0503 DC?b:a:0:0 + 19610 LUT3 AC c?A:B + 19611 LUT3 35 c?b:a + 19612 LUT4 0503 DC?b:a:0:0 + 19613 LUT3 AC c?A:B + 19614 LUT3 35 c?b:a + 19615 LUT4 0503 DC?b:a:0:0 + 19616 LUT3 AC c?A:B + 19617 LUT3 35 c?b:a + 19618 LUT4 0503 DC?b:a:0:0 + 19619 LUT3 AC c?A:B + 19620 LUT3 35 c?b:a + 19621 LUT4 0503 DC?b:a:0:0 + 19622 LUT3 AC c?A:B + 19623 LUT3 35 c?b:a + 19624 LUT4 0503 DC?b:a:0:0 + 19625 LUT3 AC c?A:B + 19626 LUT3 35 c?b:a + 19627 LUT4 0503 DC?b:a:0:0 + 19628 LUT3 AC c?A:B + 19629 LUT3 35 c?b:a + 19630 LUT4 8F88 (AB)+(cD) + 19631 LUT3 FE /ab\+C + 19632 LUT4 E0FF (C/ab\)+d + 19633 LUT4 7077 /AB\(d+C) + 19634 LUT4 E0FF (C/ab\)+d + 19635 LUT4 7077 /AB\(d+C) + 19636 LUT3 0E c/ab\ + 19637 LUT3 01 abc + 19638 LUT3 01 abc + 19639 LUT4 8000 ABCD + 19640 LUT2 4 aB + 19641 LUT3 0E c/ab\ + 19642 LUT2 8 AB + 19643 LUT4 9000 CD(a^B) + 19644 LUT4 9000 CD(a^B) + 19645 LUT3 90 C(a^B) + 19646 LUT4 9009 (a^B)(D^c) + 19647 LUT4 9009 (a^B)(D^c) + 19648 LUT4 9009 (a^B)(D^c) + 19649 LUT3 F8 (AB)+C + 19650 LUT3 80 ABC + 19651 LUT3 60 C(A^B) + 19652 LUT4 6000 CD(A^B) + 19653 LUT3 60 C(A^B) + 19654 LUT4 6000 CD(A^B) + 19655 LUT4 6000 CD(A^B) + 19656 LUT3 10 abC + 19657 LUT3 40 aBC + 19658 LUT3 E0 C/ab\ + 19659 LUT3 F8 (AB)+C + 19660 LUT3 80 ABC + 19661 LUT3 60 C(A^B) + 19662 LUT3 60 C(A^B) + 19663 LUT4 6000 CD(A^B) + 19664 LUT4 D700 AD?0:0:1:b^C + 19665 LUT3 F8 (AB)+C + 19666 LUT3 80 ABC + 19667 LUT3 60 C(A^B) + 19668 LUT4 6000 CD(A^B) + 19669 LUT3 90 C(a^B) + 19670 LUT4 FF80 (ABC)+D + 19671 LUT4 6000 CD(A^B) + 19672 LUT4 6000 CD(A^B) + 19673 LUT4 D700 AD?0:0:1:b^C + 19674 LUT4 FF80 (ABC)+D + 19675 LUT2 8 AB + 19676 LUT4 6000 CD(A^B) + 19677 LUT4 D700 AD?0:0:1:b^C + 19678 LUT4 FF80 (ABC)+D + 19679 LUT2 8 AB + 19680 LUT4 6000 CD(A^B) + 19681 LUT3 90 C(a^B) + 19682 LUT4 FF80 (ABC)+D + 19683 LUT2 8 AB + 19684 LUT4 6000 CD(A^B) + 19685 LUT4 D700 AD?0:0:1:b^C + 19686 LUT4 FF80 (ABC)+D + 19687 LUT2 8 AB + 19688 LUT4 6000 CD(A^B) + 19689 LUT4 D700 AD?0:0:1:b^C + 19690 LUT3 F8 (AB)+C + 19691 LUT3 80 ABC + 19692 LUT3 90 C(a^B) + 19693 LUT3 F8 (AB)+C + 19694 LUT3 80 ABC + 19695 LUT3 90 C(a^B) + 19696 LUT3 F8 (AB)+C + 19697 LUT3 80 ABC + 19698 LUT3 90 C(a^B) + 19699 LUT3 F8 (AB)+C + 19700 LUT3 80 ABC + 19701 LUT3 90 C(a^B) + 19702 LUT3 F8 (AB)+C + 19703 LUT3 80 ABC + 19704 LUT4 D700 AD?0:0:1:b^C + 19705 LUT3 F8 (AB)+C + 19706 LUT3 80 ABC + 19707 LUT4 D700 AD?0:0:1:b^C + 19708 LUT3 F8 (AB)+C + 19709 LUT3 80 ABC + 19710 LUT4 D700 AD?0:0:1:b^C + 19711 LUT3 F8 (AB)+C + 19712 LUT3 80 ABC + 19713 LUT4 D700 AD?0:0:1:b^C + 19714 LUT4 FF80 (ABC)+D + 19715 LUT3 70 C/AB\ + 19716 LUT4 FF80 (ABC)+D + 19717 LUT3 70 C/AB\ + 19718 LUT4 FF80 (ABC)+D + 19719 LUT3 70 C/AB\ + 19720 LUT4 FF80 (ABC)+D + 19721 LUT4 1400 D(B^C)a + 19722 LUT4 FF80 (ABC)+D + 19723 LUT2 4 aB + 19724 LUT4 FF80 (ABC)+D + 19725 LUT2 4 aB + 19726 LUT4 FF80 (ABC)+D + 19727 LUT2 4 aB + 19728 LUT4 FF80 (ABC)+D + 19729 LUT2 4 aB + 19730 LUT4 FF80 (ABC)+D + 19731 LUT3 70 C/AB\ + 19732 LUT4 FF80 (ABC)+D + 19733 LUT3 70 C/AB\ + 19734 LUT4 FF80 (ABC)+D + 19735 LUT3 70 C/AB\ + 19736 LUT4 FF80 (ABC)+D + 19737 LUT3 70 C/AB\ + 19738 LUT4 FF80 (ABC)+D + 19739 LUT3 70 C/AB\ + 19740 LUT4 FF80 (ABC)+D + 19741 LUT3 70 C/AB\ + 19742 LUT4 FF80 (ABC)+D + 19743 LUT3 70 C/AB\ + 19744 LUT4 FF80 (ABC)+D + 19745 LUT3 70 C/AB\ + 19746 LUT3 F4 (aB)+C + 19747 LUT3 F4 (aB)+C + 19748 LUT3 F4 (aB)+C + 19749 LUT4 FF70 (C/AB\)+D + 19750 LUT4 FF70 (C/AB\)+D + 19751 LUT4 FF70 (C/AB\)+D + 19752 LUT4 FF70 (C/AB\)+D + 19753 LUT4 FF70 (C/AB\)+D + 19754 LUT3 F4 (aB)+C + 19755 LUT3 F4 (aB)+C + 19756 LUT3 F4 (aB)+C + 19757 LUT3 F4 (aB)+C + 19758 LUT3 F4 (aB)+C + 19759 LUT3 F4 (aB)+C + 19760 LUT3 F4 (aB)+C + 19761 LUT3 F4 (aB)+C + 19762 LUT4 FF70 (C/AB\)+D + 19763 LUT4 FF70 (C/AB\)+D + 19764 LUT4 FF70 (C/AB\)+D + 19765 LUT4 FF70 (C/AB\)+D + 19766 LUT4 FF70 (C/AB\)+D + 19767 LUT4 FF70 (C/AB\)+D + 19768 LUT4 FF70 (C/AB\)+D + 19769 LUT4 FF70 (C/AB\)+D + 19770 LUT4 FF70 (C/AB\)+D + 19771 LUT4 FF70 (C/AB\)+D + 19772 LUT4 FF70 (C/AB\)+D + 19773 LUT4 FF70 (C/AB\)+D + 19774 LUT4 FF70 (C/AB\)+D + 19775 LUT4 FF70 (C/AB\)+D + 19776 LUT4 FF70 (C/AB\)+D + 19777 LUT4 FF70 (C/AB\)+D + 19778 LUT2 8 AB + 19779 LUT3 F8 (AB)+C + 19780 LUT3 80 ABC + 19781 LUT3 60 C(A^B) + 19782 LUT4 6000 CD(A^B) + 19783 LUT3 60 C(A^B) + 19784 LUT4 6000 CD(A^B) + 19785 LUT4 D700 AD?0:0:1:b^C + 19786 LUT4 FF80 (ABC)+D + 19787 LUT2 8 AB + 19788 LUT4 6000 CD(A^B) + 19789 LUT3 60 C(A^B) + 19790 LUT4 6000 CD(A^B) + 19791 LUT4 D700 AD?0:0:1:b^C + 19792 LUT3 F8 (AB)+C + 19793 LUT3 80 ABC + 19794 LUT3 60 C(A^B) + 19795 LUT4 6000 CD(A^B) + 19796 LUT3 90 C(a^B) + 19797 LUT4 FF80 (ABC)+D + 19798 LUT4 6000 CD(A^B) + 19799 LUT4 6000 CD(A^B) + 19800 LUT4 D700 AD?0:0:1:b^C + 19801 LUT4 FF80 (ABC)+D + 19802 LUT2 8 AB + 19803 LUT4 6000 CD(A^B) + 19804 LUT4 D700 AD?0:0:1:b^C + 19805 LUT4 FF80 (ABC)+D + 19806 LUT2 8 AB + 19807 LUT4 6000 CD(A^B) + 19808 LUT3 90 C(a^B) + 19809 LUT4 FF80 (ABC)+D + 19810 LUT2 8 AB + 19811 LUT4 6000 CD(A^B) + 19812 LUT4 D700 AD?0:0:1:b^C + 19813 LUT4 FF80 (ABC)+D + 19814 LUT2 8 AB + 19815 LUT4 6000 CD(A^B) + 19816 LUT4 D700 AD?0:0:1:b^C + 19817 LUT3 F8 (AB)+C + 19818 LUT3 80 ABC + 19819 LUT3 90 C(a^B) + 19820 LUT3 F8 (AB)+C + 19821 LUT3 80 ABC + 19822 LUT4 D700 AD?0:0:1:b^C + 19823 LUT3 F8 (AB)+C + 19824 LUT3 80 ABC + 19825 LUT3 90 C(a^B) + 19826 LUT3 F8 (AB)+C + 19827 LUT3 80 ABC + 19828 LUT3 90 C(a^B) + 19829 LUT3 F8 (AB)+C + 19830 LUT3 80 ABC + 19831 LUT4 D700 AD?0:0:1:b^C + 19832 LUT3 F8 (AB)+C + 19833 LUT3 80 ABC + 19834 LUT4 D700 AD?0:0:1:b^C + 19835 LUT3 F8 (AB)+C + 19836 LUT3 80 ABC + 19837 LUT4 D700 AD?0:0:1:b^C + 19838 LUT3 F8 (AB)+C + 19839 LUT3 80 ABC + 19840 LUT4 D700 AD?0:0:1:b^C + 19841 LUT4 FF80 (ABC)+D + 19842 LUT3 70 C/AB\ + 19843 LUT4 FF80 (ABC)+D + 19844 LUT2 4 aB + 19845 LUT4 FF80 (ABC)+D + 19846 LUT3 70 C/AB\ + 19847 LUT4 FF80 (ABC)+D + 19848 LUT4 1400 D(B^C)a + 19849 LUT4 FF80 (ABC)+D + 19850 LUT2 4 aB + 19851 LUT4 FF80 (ABC)+D + 19852 LUT2 4 aB + 19853 LUT4 FF80 (ABC)+D + 19854 LUT2 4 aB + 19855 LUT4 FF80 (ABC)+D + 19856 LUT2 4 aB + 19857 LUT4 FF80 (ABC)+D + 19858 LUT3 70 C/AB\ + 19859 LUT4 FF80 (ABC)+D + 19860 LUT3 70 C/AB\ + 19861 LUT4 FF80 (ABC)+D + 19862 LUT3 70 C/AB\ + 19863 LUT4 FF80 (ABC)+D + 19864 LUT3 70 C/AB\ + 19865 LUT4 FF80 (ABC)+D + 19866 LUT3 70 C/AB\ + 19867 LUT4 FF80 (ABC)+D + 19868 LUT3 70 C/AB\ + 19869 LUT4 FF80 (ABC)+D + 19870 LUT3 70 C/AB\ + 19871 LUT4 FF80 (ABC)+D + 19872 LUT3 70 C/AB\ + 19873 LUT3 F4 (aB)+C + 19874 LUT4 FF70 (C/AB\)+D + 19875 LUT3 F4 (aB)+C + 19876 LUT4 FF70 (C/AB\)+D + 19877 LUT4 FF70 (C/AB\)+D + 19878 LUT4 FF70 (C/AB\)+D + 19879 LUT4 FF70 (C/AB\)+D + 19880 LUT4 FF70 (C/AB\)+D + 19881 LUT3 F4 (aB)+C + 19882 LUT3 F4 (aB)+C + 19883 LUT3 F4 (aB)+C + 19884 LUT3 F4 (aB)+C + 19885 LUT3 F4 (aB)+C + 19886 LUT3 F4 (aB)+C + 19887 LUT3 F4 (aB)+C + 19888 LUT3 F4 (aB)+C + 19889 LUT4 FF70 (C/AB\)+D + 19890 LUT4 FF70 (C/AB\)+D + 19891 LUT4 FF70 (C/AB\)+D + 19892 LUT4 FF70 (C/AB\)+D + 19893 LUT4 FF70 (C/AB\)+D + 19894 LUT4 FF70 (C/AB\)+D + 19895 LUT4 FF70 (C/AB\)+D + 19896 LUT4 FF70 (C/AB\)+D + 19897 LUT4 FF70 (C/AB\)+D + 19898 LUT4 FF70 (C/AB\)+D + 19899 LUT4 FF70 (C/AB\)+D + 19900 LUT4 FF70 (C/AB\)+D + 19901 LUT4 FF70 (C/AB\)+D + 19902 LUT4 FF70 (C/AB\)+D + 19903 LUT4 FF70 (C/AB\)+D + 19904 LUT4 FF70 (C/AB\)+D + 19905 LUT3 80 ABC + 19906 LUT4 0C0A DC?A:B:0:0 + 19907 LUT2 1 ab + 19908 LUT4 7000 CD/AB\ + 19909 LUT4 0C0A DC?A:B:0:0 + 19910 LUT3 35 c?b:a + 19911 LUT2 8 AB + 19912 LUT2 8 AB + 19913 LUT4 0C0A DC?A:B:0:0 + 19914 LUT4 0F77 D?/AB\:c + 19915 LUT2 8 AB + 19916 LUT3 80 ABC + 19917 LUT4 0305 DC?a:b:0:0 + 19918 LUT3 80 ABC + 19919 LUT4 CA00 D(C?A:B) + 19920 LUT3 80 ABC + 19921 LUT3 80 ABC + 19922 LUT4 0305 DC?a:b:0:0 + 19923 LUT3 80 ABC + 19924 LUT3 80 ABC + 19925 LUT4 3500 D(c?b:a) + 19926 LUT3 80 ABC + 19927 LUT3 80 ABC + 19928 LUT4 0305 DC?a:b:0:0 + 19929 LUT3 80 ABC + 19930 LUT3 80 ABC + 19931 LUT3 80 ABC + 19932 LUT3 80 ABC + 19933 LUT3 80 ABC + 19934 LUT3 80 ABC + 19935 LUT3 80 ABC + 19936 LUT3 80 ABC + 19937 LUT4 CA00 D(C?A:B) + 19938 LUT3 80 ABC + 19939 LUT3 80 ABC + 19940 LUT3 80 ABC + 19941 LUT3 80 ABC + 19942 LUT3 80 ABC + 19943 LUT3 80 ABC + 19944 LUT3 80 ABC + 19945 LUT3 80 ABC + 19946 LUT4 3500 D(c?b:a) + 19947 LUT3 80 ABC + 19948 LUT3 80 ABC + 19949 LUT3 80 ABC + 19950 LUT3 80 ABC + 19951 LUT3 80 ABC + 19952 LUT3 80 ABC + 19953 LUT3 80 ABC + 19954 LUT2 E /ab\ + 19955 LUT3 4F (aB)+c + 19956 LUT4 3B30 BD?C:0:1:Ac + 19957 LUT2 4 aB + 19958 LUT2 8 AB + 19959 LUT2 4 aB + 19960 LUT3 01 abc + 19961 LUT4 0777 /AB\(d+c) + 19962 LUT3 4F (aB)+c + 19963 LUT4 3B30 BD?C:0:1:Ac + 19964 LUT2 4 aB + 19965 LUT4 1000 abCD + 19966 LUT4 0777 /AB\(d+c) + 19967 LUT2 4 aB + 19968 LUT4 4000 aBCD + 19969 LUT4 1000 abCD + 19970 LUT4 1000 abCD + 19971 LUT3 01 abc + 19972 LUT3 60 C(A^B) + 19973 LUT3 41 (B^c)a + 19974 LUT2 9 a^B + 19975 LUT4 1000 abCD + 19976 LUT4 F5FC DC?B:a:1:1 + 19977 LUT3 D0 C/Ab\ + 19978 LUT2 1 ab + 19979 LUT4 0777 /AB\(d+c) + 19980 LUT4 1000 abCD + 19981 LUT4 FFF4 (aB)+C+D + 19982 LUT4 0D00 cD/Ab\ + 19983 LUT4 4000 aBCD + 19984 LUT4 00F8 ((AB)+C)d + 19985 LUT2 8 AB + 19986 LUT3 4F (aB)+c + 19987 LUT4 3B30 BD?C:0:1:Ac + 19988 LUT2 4 aB + 19989 LUT2 8 AB + 19990 LUT3 10 abC + 19991 LUT4 0777 /AB\(d+c) + 19992 LUT4 F5FC DC?B:a:1:1 + 19993 LUT3 D0 C/Ab\ + 19994 LUT4 00F8 ((AB)+C)d + 19995 LUT2 8 AB + 19996 LUT4 4000 aBCD + 19997 LUT4 F5FC DC?B:a:1:1 + 19998 LUT3 D0 C/Ab\ + 19999 LUT2 1 ab + 20000 LUT4 0777 /AB\(d+c) + 20001 LUT4 4000 aBCD + 20002 LUT4 FFF4 (aB)+C+D + 20003 LUT4 0D00 cD/Ab\ + 20004 LUT4 8000 ABCD + 20005 LUT4 00F8 ((AB)+C)d + 20006 LUT2 8 AB + 20007 LUT4 40FF (aBC)+d + 20008 LUT4 3B30 BD?C:0:1:Ac + 20009 LUT3 70 C/AB\ + 20010 LUT2 8 AB + 20011 LUT4 0777 /AB\(d+c) + 20012 LUT4 FFF4 (aB)+C+D + 20013 LUT4 0D00 cD/Ab\ + 20014 LUT4 1000 abCD + 20015 LUT4 00F8 ((AB)+C)d + 20016 LUT2 8 AB + 20017 LUT4 F5FC DC?B:a:1:1 + 20018 LUT3 D0 C/Ab\ + 20019 LUT2 1 ab + 20020 LUT4 0777 /AB\(d+c) + 20021 LUT4 1000 abCD + 20022 LUT4 F5FC DC?B:a:1:1 + 20023 LUT3 D0 C/Ab\ + 20024 LUT4 00F8 ((AB)+C)d + 20025 LUT2 8 AB + 20026 LUT4 4000 aBCD + 20027 LUT4 F5FC DC?B:a:1:1 + 20028 LUT3 D0 C/Ab\ + 20029 LUT4 00F8 ((AB)+C)d + 20030 LUT2 8 AB + 20031 LUT2 8 AB + 20032 LUT4 F5FC DC?B:a:1:1 + 20033 LUT3 D0 C/Ab\ + 20034 LUT4 00F8 ((AB)+C)d + 20035 LUT2 8 AB + 20036 LUT4 4000 aBCD + 20037 LUT4 FFF4 (aB)+C+D + 20038 LUT4 0D00 cD/Ab\ + 20039 LUT4 4000 aBCD + 20040 LUT4 00F8 ((AB)+C)d + 20041 LUT2 8 AB + 20042 LUT4 FFF4 (aB)+C+D + 20043 LUT4 0D00 cD/Ab\ + 20044 LUT4 8000 ABCD + 20045 LUT4 00F8 ((AB)+C)d + 20046 LUT2 8 AB + 20047 LUT3 8F (AB)+c + 20048 LUT3 0B c/aB\ + 20049 LUT3 69 A^B^c + 20050 LUT3 69 A^B^c + 20051 LUT3 96 A^B^C + 20052 LUT3 69 A^B^c + 20053 LUT4 7000 CD/AB\ + 20054 LUT4 8000 ABCD + 20055 LUT4 0777 /AB\(d+c) + 20056 LUT4 0777 /AB\(d+c) + 20057 LUT4 0777 /AB\(d+c) + 20058 LUT4 0777 /AB\(d+c) + 20059 LUT4 0777 /AB\(d+c) + 20060 LUT4 7000 CD/AB\ + 20061 LUT4 0777 /AB\(d+c) + 20062 LUT4 0777 /AB\(d+c) + 20063 LUT4 FFF4 (aB)+C+D + 20064 LUT3 69 A^B^c + 20065 LUT3 96 A^B^C + 20066 LUT3 90 C(a^B) + 20067 LUT4 9000 CD(a^B) + 20068 LUT3 07 c/AB\ + 20069 LUT3 14 (B^C)a + 20070 LUT3 69 A^B^c + 20071 LUT4 8000 ABCD + 20072 LUT4 0700 cD/AB\ + 20073 LUT4 0777 /AB\(d+c) + 20074 LUT2 8 AB + 20075 LUT4 8000 ABCD + 20076 LUT4 0777 /AB\(d+c) + 20077 LUT4 0777 /AB\(d+c) + 20078 LUT4 0777 /AB\(d+c) + 20079 LUT4 0777 /AB\(d+c) + 20080 LUT4 0777 /AB\(d+c) + 20081 LUT4 0777 /AB\(d+c) + 20082 LUT3 E0 C/ab\ + 20083 LUT2 4 aB + 20084 LUT3 F8 (AB)+C + 20085 LUT2 8 AB + 20086 LUT4 F888 (AB)+(CD) + 20087 LUT4 F888 (AB)+(CD) + 20088 LUT4 F888 (AB)+(CD) + 20089 LUT4 F888 (AB)+(CD) + 20090 LUT4 F888 (AB)+(CD) + 20091 LUT4 F888 (AB)+(CD) + 20092 LUT4 F888 (AB)+(CD) + 20093 LUT4 F888 (AB)+(CD) + 20094 LUT4 F888 (AB)+(CD) + 20095 LUT4 F888 (AB)+(CD) + 20096 LUT4 F888 (AB)+(CD) + 20097 LUT4 F888 (AB)+(CD) + 20098 LUT3 F8 (AB)+C + 20099 LUT4 AC00 D(c?A:B) + 20100 LUT3 F8 (AB)+C + 20101 LUT4 AC00 D(c?A:B) + 20102 LUT3 F8 (AB)+C + 20103 LUT4 AC00 D(c?A:B) + 20104 LUT3 F8 (AB)+C + 20105 LUT4 AC00 D(c?A:B) + 20106 LUT3 F8 (AB)+C + 20107 LUT4 AC00 D(c?A:B) + 20108 LUT3 F8 (AB)+C + 20109 LUT4 AC00 D(c?A:B) + 20110 LUT3 F8 (AB)+C + 20111 LUT4 AC00 D(c?A:B) + 20112 LUT3 F8 (AB)+C + 20113 LUT4 AC00 D(c?A:B) + 20114 LUT3 F8 (AB)+C + 20115 LUT4 AC00 D(c?A:B) + 20116 LUT3 F8 (AB)+C + 20117 LUT4 AC00 D(c?A:B) + 20118 LUT3 F8 (AB)+C + 20119 LUT4 AC00 D(c?A:B) + 20120 LUT3 F8 (AB)+C + 20121 LUT4 AC00 D(c?A:B) + 20122 LUT3 F8 (AB)+C + 20123 LUT4 AC00 D(c?A:B) + 20124 LUT3 F8 (AB)+C + 20125 LUT4 AC00 D(c?A:B) + 20126 LUT3 F8 (AB)+C + 20127 LUT4 AC00 D(c?A:B) + 20128 LUT3 F8 (AB)+C + 20129 LUT4 AC00 D(c?A:B) + 20130 LUT3 F8 (AB)+C + 20131 LUT4 AC00 D(c?A:B) + 20132 LUT3 F8 (AB)+C + 20133 LUT4 AC00 D(c?A:B) + 20134 LUT3 F8 (AB)+C + 20135 LUT4 AC00 D(c?A:B) + 20136 LUT2 1 ab + 20137 LUT3 8F (AB)+c + 20138 LUT4 0777 /AB\(d+c) + 20139 LUT3 8F (AB)+c + 20140 LUT4 0777 /AB\(d+c) + 20141 LUT3 8F (AB)+c + 20142 LUT4 0777 /AB\(d+c) + 20143 LUT3 8F (AB)+c + 20144 LUT4 0777 /AB\(d+c) + 20145 LUT3 8F (AB)+c + 20146 LUT4 0777 /AB\(d+c) + 20147 LUT3 8F (AB)+c + 20148 LUT4 0777 /AB\(d+c) + 20149 LUT3 8F (AB)+c + 20150 LUT4 0777 /AB\(d+c) + 20151 LUT3 8F (AB)+c + 20152 LUT4 0777 /AB\(d+c) + 20153 LUT3 8F (AB)+c + 20154 LUT4 0777 /AB\(d+c) + 20155 LUT3 8F (AB)+c + 20156 LUT4 0777 /AB\(d+c) + 20157 LUT3 8F (AB)+c + 20158 LUT4 0777 /AB\(d+c) + 20159 LUT2 9 a^B + 20160 LUT2 1 ab + 20161 LUT2 4 aB + 20162 LUT3 40 aBC + 20163 LUT3 10 abC + 20164 LUT2 8 AB + 20165 LUT4 4000 aBCD + 20166 LUT3 70 C/AB\ + 20167 LUT4 0777 /AB\(d+c) + 20168 LUT2 8 AB + 20169 LUT4 0777 /AB\(d+c) + 20170 LUT4 0777 /AB\(d+c) + 20171 LUT4 0777 /AB\(d+c) + 20172 LUT2 8 AB + 20173 LUT4 0777 /AB\(d+c) + 20174 LUT4 0777 /AB\(d+c) + 20175 LUT4 4000 aBCD + 20176 LUT3 70 C/AB\ + 20177 LUT4 0777 /AB\(d+c) + 20178 LUT2 8 AB + 20179 LUT4 0777 /AB\(d+c) + 20180 LUT4 0777 /AB\(d+c) + 20181 LUT3 70 C/AB\ + 20182 LUT4 0777 /AB\(d+c) + 20183 LUT3 70 C/AB\ + 20184 LUT4 0700 cD/AB\ + 20185 LUT2 8 AB + 20186 LUT4 0777 /AB\(d+c) + 20187 LUT2 8 AB + 20188 LUT4 7000 CD/AB\ + 20189 LUT4 7000 CD/AB\ + 20190 LUT4 0777 /AB\(d+c) + 20191 LUT4 0777 /AB\(d+c) + 20192 LUT4 0777 /AB\(d+c) + 20193 LUT4 7F00 ((/AB\)+c)D + 20194 LUT4 7F00 ((/AB\)+c)D + 20195 LUT3 80 ABC + 20196 LUT4 0777 /AB\(d+c) + 20197 LUT2 8 AB + 20198 LUT3 70 C/AB\ + 20199 LUT4 0777 /AB\(d+c) + 20200 LUT2 8 AB + 20201 LUT4 0777 /AB\(d+c) + 20202 LUT4 4000 aBCD + 20203 LUT4 7000 CD/AB\ + 20204 LUT3 70 C/AB\ + 20205 LUT4 0777 /AB\(d+c) + 20206 LUT4 0777 /AB\(d+c) + 20207 LUT4 0007 cd/AB\ + 20208 LUT2 8 AB + 20209 LUT2 8 AB + 20210 LUT4 0777 /AB\(d+c) + 20211 LUT3 70 C/AB\ + 20212 LUT4 0777 /AB\(d+c) + 20213 LUT4 0777 /AB\(d+c) + 20214 LUT2 8 AB + 20215 LUT4 0777 /AB\(d+c) + 20216 LUT4 0777 /AB\(d+c) + 20217 LUT2 8 AB + 20218 LUT2 8 AB + 20219 LUT4 0777 /AB\(d+c) + 20220 LUT4 0777 /AB\(d+c) + 20221 LUT2 8 AB + 20222 LUT3 4F (aB)+c + 20223 LUT4 B0BB /aB\(d+C) + 20224 LUT4 00F8 ((AB)+C)d + 20225 LUT4 8F00 ((AB)+c)D + 20226 LUT4 7000 CD/AB\ + 20227 LUT4 8000 ABCD + 20228 LUT4 0007 cd/AB\ + 20229 LUT2 8 AB + 20230 LUT2 8 AB + 20231 LUT3 70 C/AB\ + 20232 LUT4 0777 /AB\(d+c) + 20233 LUT4 0777 /AB\(d+c) + 20234 LUT4 0777 /AB\(d+c) + 20235 LUT2 8 AB + 20236 LUT4 0777 /AB\(d+c) + 20237 LUT4 0777 /AB\(d+c) + 20238 LUT2 8 AB + 20239 LUT4 7000 CD/AB\ + 20240 LUT4 0007 cd/AB\ + 20241 LUT2 8 AB + 20242 LUT2 8 AB + 20243 LUT4 0700 cD/AB\ + 20244 LUT2 8 AB + 20245 LUT4 0777 /AB\(d+c) + 20246 LUT4 7000 CD/AB\ + 20247 LUT3 70 C/AB\ + 20248 LUT4 0777 /AB\(d+c) + 20249 LUT4 0777 /AB\(d+c) + 20250 LUT4 0777 /AB\(d+c) + 20251 LUT4 B0BB /aB\(d+C) + 20252 LUT4 8000 ABCD + 20253 LUT4 7000 CD/AB\ + 20254 LUT3 70 C/AB\ + 20255 LUT4 0777 /AB\(d+c) + 20256 LUT4 0777 /AB\(d+c) + 20257 LUT4 0007 cd/AB\ + 20258 LUT2 8 AB + 20259 LUT2 8 AB + 20260 LUT4 7000 CD/AB\ + 20261 LUT4 0777 /AB\(d+c) + 20262 LUT4 0777 /AB\(d+c) + 20263 LUT4 0777 /AB\(d+c) + 20264 LUT4 8000 ABCD + 20265 LUT4 0700 cD/AB\ + 20266 LUT2 8 AB + 20267 LUT4 0777 /AB\(d+c) + 20268 LUT4 8000 ABCD + 20269 LUT4 0777 /AB\(d+c) + 20270 LUT4 0777 /AB\(d+c) + 20271 LUT4 0777 /AB\(d+c) + 20272 LUT4 0777 /AB\(d+c) + 20273 LUT4 0777 /AB\(d+c) + 20274 LUT4 0777 /AB\(d+c) + 20275 LUT4 B0BB /aB\(d+C) + 20276 LUT4 B0BB /aB\(d+C) + 20277 LUT4 008F ((AB)+c)d + 20278 LUT3 07 c/AB\ + 20279 LUT4 8000 ABCD + 20280 LUT4 0777 /AB\(d+c) + 20281 LUT4 0777 /AB\(d+c) + 20282 LUT4 0777 /AB\(d+c) + 20283 LUT4 0777 /AB\(d+c) + 20284 LUT4 8000 ABCD + 20285 LUT4 0777 /AB\(d+c) + 20286 LUT4 0777 /AB\(d+c) + 20287 LUT4 0777 /AB\(d+c) + 20288 LUT4 0777 /AB\(d+c) + 20289 LUT4 8000 ABCD + 20290 LUT4 0777 /AB\(d+c) + 20291 LUT4 0777 /AB\(d+c) + 20292 LUT4 0777 /AB\(d+c) + 20293 LUT4 0777 /AB\(d+c) + 20294 LUT4 8000 ABCD + 20295 LUT4 0777 /AB\(d+c) + 20296 LUT4 0777 /AB\(d+c) + 20297 LUT4 0777 /AB\(d+c) + 20298 LUT4 0777 /AB\(d+c) + 20299 LUT4 B0BB /aB\(d+C) + 20300 LUT4 8000 ABCD + 20301 LUT4 0700 cD/AB\ + 20302 LUT2 8 AB + 20303 LUT4 0777 /AB\(d+c) + 20304 LUT4 8000 ABCD + 20305 LUT4 0777 /AB\(d+c) + 20306 LUT4 0777 /AB\(d+c) + 20307 LUT4 0777 /AB\(d+c) + 20308 LUT4 0777 /AB\(d+c) + 20309 LUT4 0777 /AB\(d+c) + 20310 LUT4 0777 /AB\(d+c) + 20311 LUT4 8000 ABCD + 20312 LUT4 8000 ABCD + 20313 LUT4 0777 /AB\(d+c) + 20314 LUT4 0777 /AB\(d+c) + 20315 LUT4 0777 /AB\(d+c) + 20316 LUT4 0777 /AB\(d+c) + 20317 LUT4 0700 cD/AB\ + 20318 LUT2 8 AB + 20319 LUT4 0777 /AB\(d+c) + 20320 LUT4 0777 /AB\(d+c) + 20321 LUT4 0777 /AB\(d+c) + 20322 LUT2 8 AB + 20323 LUT4 4000 aBCD + 20324 LUT3 10 abC + 20325 LUT4 0001 abcd + 20326 LUT4 4000 aBCD + 20327 LUT4 0001 abcd + 20328 LUT3 10 abC + 20329 LUT3 4F (aB)+c + 20330 LUT4 B0BB /aB\(d+C) + 20331 LUT3 0B c/aB\ + 20332 LUT3 07 c/AB\ + 20333 LUT4 4000 aBCD + 20334 LUT4 7000 CD/AB\ + 20335 LUT4 7000 CD/AB\ + 20336 LUT4 0777 /AB\(d+c) + 20337 LUT4 0777 /AB\(d+c) + 20338 LUT4 0777 /AB\(d+c) + 20339 LUT3 70 C/AB\ + 20340 LUT4 0777 /AB\(d+c) + 20341 LUT2 8 AB + 20342 LUT4 0777 /AB\(d+c) + 20343 LUT4 0777 /AB\(d+c) + 20344 LUT4 8000 ABCD + 20345 LUT4 0700 cD/AB\ + 20346 LUT2 8 AB + 20347 LUT4 0777 /AB\(d+c) + 20348 LUT4 8000 ABCD + 20349 LUT4 0777 /AB\(d+c) + 20350 LUT4 0777 /AB\(d+c) + 20351 LUT4 0777 /AB\(d+c) + 20352 LUT4 0777 /AB\(d+c) + 20353 LUT4 0777 /AB\(d+c) + 20354 LUT4 0777 /AB\(d+c) + 20355 LUT4 B0BB /aB\(d+C) + 20356 LUT3 80 ABC + 20357 LUT4 0700 cD/AB\ + 20358 LUT2 8 AB + 20359 LUT4 0777 /AB\(d+c) + 20360 LUT4 0700 cD/AB\ + 20361 LUT4 0777 /AB\(d+c) + 20362 LUT2 8 AB + 20363 LUT4 8000 ABCD + 20364 LUT4 0777 /AB\(d+c) + 20365 LUT4 0777 /AB\(d+c) + 20366 LUT4 0777 /AB\(d+c) + 20367 LUT4 0777 /AB\(d+c) + 20368 LUT4 8000 ABCD + 20369 LUT4 0700 cD/AB\ + 20370 LUT2 8 AB + 20371 LUT4 0777 /AB\(d+c) + 20372 LUT4 8000 ABCD + 20373 LUT4 0777 /AB\(d+c) + 20374 LUT4 0777 /AB\(d+c) + 20375 LUT4 0777 /AB\(d+c) + 20376 LUT4 0777 /AB\(d+c) + 20377 LUT4 0777 /AB\(d+c) + 20378 LUT4 0777 /AB\(d+c) + 20379 LUT4 B0BB /aB\(d+C) + 20380 LUT3 4F (aB)+c + 20381 LUT4 B0BB /aB\(d+C) + 20382 LUT3 0B c/aB\ + 20383 LUT3 07 c/AB\ + 20384 LUT4 8000 ABCD + 20385 LUT4 0777 /AB\(d+c) + 20386 LUT4 0777 /AB\(d+c) + 20387 LUT4 0777 /AB\(d+c) + 20388 LUT4 0777 /AB\(d+c) + 20389 LUT4 8000 ABCD + 20390 LUT4 0777 /AB\(d+c) + 20391 LUT4 0777 /AB\(d+c) + 20392 LUT4 0777 /AB\(d+c) + 20393 LUT4 0777 /AB\(d+c) + 20394 LUT3 80 ABC + 20395 LUT4 8000 ABCD + 20396 LUT4 0777 /AB\(d+c) + 20397 LUT4 0777 /AB\(d+c) + 20398 LUT4 0777 /AB\(d+c) + 20399 LUT4 0777 /AB\(d+c) + 20400 LUT4 0700 cD/AB\ + 20401 LUT4 0777 /AB\(d+c) + 20402 LUT2 8 AB + 20403 LUT4 0700 cD/AB\ + 20404 LUT4 0777 /AB\(d+c) + 20405 LUT2 8 AB + 20406 LUT4 B0BB /aB\(d+C) + 20407 LUT4 8000 ABCD + 20408 LUT4 0700 cD/AB\ + 20409 LUT4 0777 /AB\(d+c) + 20410 LUT2 8 AB + 20411 LUT4 8000 ABCD + 20412 LUT4 0777 /AB\(d+c) + 20413 LUT4 0777 /AB\(d+c) + 20414 LUT4 0777 /AB\(d+c) + 20415 LUT4 0777 /AB\(d+c) + 20416 LUT4 0777 /AB\(d+c) + 20417 LUT4 0777 /AB\(d+c) + 20418 LUT4 8000 ABCD + 20419 LUT4 8000 ABCD + 20420 LUT4 0777 /AB\(d+c) + 20421 LUT4 0777 /AB\(d+c) + 20422 LUT4 0777 /AB\(d+c) + 20423 LUT4 0777 /AB\(d+c) + 20424 LUT4 0700 cD/AB\ + 20425 LUT2 8 AB + 20426 LUT4 0777 /AB\(d+c) + 20427 LUT4 0777 /AB\(d+c) + 20428 LUT4 0777 /AB\(d+c) + 20429 LUT4 B0BB /aB\(d+C) + 20430 LUT3 4F (aB)+c + 20431 LUT4 B0BB /aB\(d+C) + 20432 LUT3 0B c/aB\ + 20433 LUT4 007F ((/AB\)+c)d + 20434 LUT4 0700 cD/AB\ + 20435 LUT4 7000 CD/AB\ + 20436 LUT3 70 C/AB\ + 20437 LUT4 0777 /AB\(d+c) + 20438 LUT4 0777 /AB\(d+c) + 20439 LUT2 8 AB + 20440 LUT4 7000 CD/AB\ + 20441 LUT3 70 C/AB\ + 20442 LUT4 0777 /AB\(d+c) + 20443 LUT4 0777 /AB\(d+c) + 20444 LUT4 0777 /AB\(d+c) + 20445 LUT3 80 ABC + 20446 LUT4 0700 cD/AB\ + 20447 LUT2 8 AB + 20448 LUT4 0777 /AB\(d+c) + 20449 LUT4 0700 cD/AB\ + 20450 LUT4 0777 /AB\(d+c) + 20451 LUT2 8 AB + 20452 LUT4 8000 ABCD + 20453 LUT4 0777 /AB\(d+c) + 20454 LUT4 0777 /AB\(d+c) + 20455 LUT4 0777 /AB\(d+c) + 20456 LUT4 0777 /AB\(d+c) + 20457 LUT4 B0BB /aB\(d+C) + 20458 LUT4 8000 ABCD + 20459 LUT4 0700 cD/AB\ + 20460 LUT4 0777 /AB\(d+c) + 20461 LUT2 8 AB + 20462 LUT4 8000 ABCD + 20463 LUT4 0777 /AB\(d+c) + 20464 LUT4 0777 /AB\(d+c) + 20465 LUT4 0777 /AB\(d+c) + 20466 LUT4 0777 /AB\(d+c) + 20467 LUT4 0777 /AB\(d+c) + 20468 LUT4 0777 /AB\(d+c) + 20469 LUT3 80 ABC + 20470 LUT4 8000 ABCD + 20471 LUT4 0777 /AB\(d+c) + 20472 LUT4 0777 /AB\(d+c) + 20473 LUT4 0777 /AB\(d+c) + 20474 LUT4 0777 /AB\(d+c) + 20475 LUT4 0700 cD/AB\ + 20476 LUT4 0777 /AB\(d+c) + 20477 LUT2 8 AB + 20478 LUT4 0700 cD/AB\ + 20479 LUT2 8 AB + 20480 LUT4 0777 /AB\(d+c) + 20481 LUT4 B0BB /aB\(d+C) + 20482 LUT3 4F (aB)+c + 20483 LUT4 B0BB /aB\(d+C) + 20484 LUT4 BBB0 /aB\(D+C) + 20485 LUT2 8 AB + 20486 LUT4 8000 ABCD + 20487 LUT4 0777 /AB\(d+c) + 20488 LUT4 0777 /AB\(d+c) + 20489 LUT4 0777 /AB\(d+c) + 20490 LUT4 0777 /AB\(d+c) + 20491 LUT4 8000 ABCD + 20492 LUT4 0777 /AB\(d+c) + 20493 LUT4 0777 /AB\(d+c) + 20494 LUT4 0777 /AB\(d+c) + 20495 LUT4 0777 /AB\(d+c) + 20496 LUT4 8000 ABCD + 20497 LUT4 0700 cD/AB\ + 20498 LUT2 8 AB + 20499 LUT4 0777 /AB\(d+c) + 20500 LUT4 8000 ABCD + 20501 LUT4 0777 /AB\(d+c) + 20502 LUT4 0777 /AB\(d+c) + 20503 LUT4 0777 /AB\(d+c) + 20504 LUT4 0777 /AB\(d+c) + 20505 LUT4 0777 /AB\(d+c) + 20506 LUT4 0777 /AB\(d+c) + 20507 LUT4 B0BB /aB\(d+C) + 20508 LUT4 8000 ABCD + 20509 LUT3 80 ABC + 20510 LUT4 0700 cD/AB\ + 20511 LUT4 0777 /AB\(d+c) + 20512 LUT2 8 AB + 20513 LUT4 0777 /AB\(d+c) + 20514 LUT4 0777 /AB\(d+c) + 20515 LUT4 0700 cD/AB\ + 20516 LUT4 0777 /AB\(d+c) + 20517 LUT2 8 AB + 20518 LUT4 0777 /AB\(d+c) + 20519 LUT4 0777 /AB\(d+c) + 20520 LUT4 8000 ABCD + 20521 LUT4 8000 ABCD + 20522 LUT4 0777 /AB\(d+c) + 20523 LUT4 0777 /AB\(d+c) + 20524 LUT4 0777 /AB\(d+c) + 20525 LUT4 0777 /AB\(d+c) + 20526 LUT4 0700 cD/AB\ + 20527 LUT4 0777 /AB\(d+c) + 20528 LUT2 8 AB + 20529 LUT4 0777 /AB\(d+c) + 20530 LUT4 0777 /AB\(d+c) + 20531 LUT4 B0BB /aB\(d+C) + 20532 LUT3 4F (aB)+c + 20533 LUT4 B0BB /aB\(d+C) + 20534 LUT4 008F ((AB)+c)d + 20535 LUT3 07 c/AB\ + 20536 LUT4 8000 ABCD + 20537 LUT4 0777 /AB\(d+c) + 20538 LUT4 0777 /AB\(d+c) + 20539 LUT4 0777 /AB\(d+c) + 20540 LUT4 0777 /AB\(d+c) + 20541 LUT4 8000 ABCD + 20542 LUT4 0777 /AB\(d+c) + 20543 LUT4 0777 /AB\(d+c) + 20544 LUT4 0777 /AB\(d+c) + 20545 LUT4 0777 /AB\(d+c) + 20546 LUT4 8000 ABCD + 20547 LUT4 0777 /AB\(d+c) + 20548 LUT4 0777 /AB\(d+c) + 20549 LUT4 0777 /AB\(d+c) + 20550 LUT4 0777 /AB\(d+c) + 20551 LUT4 8000 ABCD + 20552 LUT4 0777 /AB\(d+c) + 20553 LUT4 0777 /AB\(d+c) + 20554 LUT4 0777 /AB\(d+c) + 20555 LUT4 0777 /AB\(d+c) + 20556 LUT4 B0BB /aB\(d+C) + 20557 LUT4 8000 ABCD + 20558 LUT4 0700 cD/AB\ + 20559 LUT4 0777 /AB\(d+c) + 20560 LUT2 8 AB + 20561 LUT4 8000 ABCD + 20562 LUT4 0777 /AB\(d+c) + 20563 LUT4 0777 /AB\(d+c) + 20564 LUT4 0777 /AB\(d+c) + 20565 LUT4 0777 /AB\(d+c) + 20566 LUT4 0777 /AB\(d+c) + 20567 LUT4 0777 /AB\(d+c) + 20568 LUT4 8000 ABCD + 20569 LUT4 8000 ABCD + 20570 LUT4 0777 /AB\(d+c) + 20571 LUT4 0777 /AB\(d+c) + 20572 LUT4 0777 /AB\(d+c) + 20573 LUT4 0777 /AB\(d+c) + 20574 LUT4 0700 cD/AB\ + 20575 LUT4 0777 /AB\(d+c) + 20576 LUT2 8 AB + 20577 LUT4 0777 /AB\(d+c) + 20578 LUT4 0777 /AB\(d+c) + 20579 LUT4 B0BB /aB\(d+C) + 20580 LUT4 B0BB /aB\(d+C) + 20581 LUT4 B0BB /aB\(d+C) + 20582 LUT4 7000 CD/AB\ + 20583 LUT4 7000 CD/AB\ + 20584 LUT4 7000 CD/AB\ + 20585 LUT3 70 C/AB\ + 20586 LUT4 0777 /AB\(d+c) + 20587 LUT4 0777 /AB\(d+c) + 20588 LUT4 0007 cd/AB\ + 20589 LUT2 8 AB + 20590 LUT2 8 AB + 20591 LUT4 7000 CD/AB\ + 20592 LUT4 0777 /AB\(d+c) + 20593 LUT4 0777 /AB\(d+c) + 20594 LUT4 0777 /AB\(d+c) + 20595 LUT4 0777 /AB\(d+c) + 20596 LUT4 0777 /AB\(d+c) + 20597 LUT4 0007 cd/AB\ + 20598 LUT2 8 AB + 20599 LUT2 8 AB + 20600 LUT4 0777 /AB\(d+c) + 20601 LUT4 BBB0 /aB\(D+C) + 20602 LUT4 7000 CD/AB\ + 20603 LUT4 7000 CD/AB\ + 20604 LUT4 7000 CD/AB\ + 20605 LUT4 0700 cD/AB\ + 20606 LUT2 8 AB + 20607 LUT4 0777 /AB\(d+c) + 20608 LUT4 0777 /AB\(d+c) + 20609 LUT4 0777 /AB\(d+c) + 20610 LUT4 7000 CD/AB\ + 20611 LUT4 0777 /AB\(d+c) + 20612 LUT4 0777 /AB\(d+c) + 20613 LUT4 8000 ABCD + 20614 LUT4 0700 cD/AB\ + 20615 LUT2 8 AB + 20616 LUT4 0777 /AB\(d+c) + 20617 LUT4 8000 ABCD + 20618 LUT4 0777 /AB\(d+c) + 20619 LUT4 0777 /AB\(d+c) + 20620 LUT4 0777 /AB\(d+c) + 20621 LUT4 0777 /AB\(d+c) + 20622 LUT4 0777 /AB\(d+c) + 20623 LUT4 0777 /AB\(d+c) + 20624 LUT4 FFF4 (aB)+C+D + 20625 LUT4 F400 ((aB)+C)D + 20626 LUT3 07 c/AB\ + 20627 LUT4 8000 ABCD + 20628 LUT4 7000 CD/AB\ + 20629 LUT4 0777 /AB\(d+c) + 20630 LUT4 0777 /AB\(d+c) + 20631 LUT4 0777 /AB\(d+c) + 20632 LUT4 0777 /AB\(d+c) + 20633 LUT4 0777 /AB\(d+c) + 20634 LUT4 7000 CD/AB\ + 20635 LUT4 0777 /AB\(d+c) + 20636 LUT4 0777 /AB\(d+c) + 20637 LUT4 8000 ABCD + 20638 LUT4 0700 cD/AB\ + 20639 LUT2 8 AB + 20640 LUT4 0777 /AB\(d+c) + 20641 LUT4 8000 ABCD + 20642 LUT4 0777 /AB\(d+c) + 20643 LUT4 0777 /AB\(d+c) + 20644 LUT4 0777 /AB\(d+c) + 20645 LUT4 0777 /AB\(d+c) + 20646 LUT4 0777 /AB\(d+c) + 20647 LUT4 0777 /AB\(d+c) + 20648 LUT4 F400 ((aB)+C)D + 20649 LUT2 4 aB + 20650 LUT3 80 ABC + 20651 LUT4 0700 cD/AB\ + 20652 LUT3 70 C/AB\ + 20653 LUT4 0777 /AB\(d+c) + 20654 LUT2 8 AB + 20655 LUT4 7000 CD/AB\ + 20656 LUT4 7000 CD/AB\ + 20657 LUT4 0777 /AB\(d+c) + 20658 LUT4 0777 /AB\(d+c) + 20659 LUT4 0777 /AB\(d+c) + 20660 LUT4 0007 cd/AB\ + 20661 LUT2 8 AB + 20662 LUT2 8 AB + 20663 LUT4 8000 ABCD + 20664 LUT4 8000 ABCD + 20665 LUT4 0777 /AB\(d+c) + 20666 LUT4 0777 /AB\(d+c) + 20667 LUT4 0777 /AB\(d+c) + 20668 LUT4 0777 /AB\(d+c) + 20669 LUT4 0700 cD/AB\ + 20670 LUT2 8 AB + 20671 LUT4 0777 /AB\(d+c) + 20672 LUT4 0777 /AB\(d+c) + 20673 LUT4 0777 /AB\(d+c) + 20674 LUT4 B0BB /aB\(d+C) + 20675 LUT3 4F (aB)+c + 20676 LUT4 B0BB /aB\(d+C) + 20677 LUT4 008F ((AB)+c)d + 20678 LUT4 007F ((/AB\)+c)d + 20679 LUT4 0700 cD/AB\ + 20680 LUT4 7000 CD/AB\ + 20681 LUT3 70 C/AB\ + 20682 LUT4 0777 /AB\(d+c) + 20683 LUT4 0777 /AB\(d+c) + 20684 LUT2 8 AB + 20685 LUT4 7000 CD/AB\ + 20686 LUT3 70 C/AB\ + 20687 LUT4 0777 /AB\(d+c) + 20688 LUT4 0777 /AB\(d+c) + 20689 LUT4 0777 /AB\(d+c) + 20690 LUT4 7000 CD/AB\ + 20691 LUT4 7000 CD/AB\ + 20692 LUT4 7000 CD/AB\ + 20693 LUT4 0777 /AB\(d+c) + 20694 LUT4 0777 /AB\(d+c) + 20695 LUT4 0777 /AB\(d+c) + 20696 LUT4 0777 /AB\(d+c) + 20697 LUT4 7000 CD/AB\ + 20698 LUT4 0777 /AB\(d+c) + 20699 LUT4 0777 /AB\(d+c) + 20700 LUT4 B0BB /aB\(d+C) + 20701 LUT4 8000 ABCD + 20702 LUT4 0700 cD/AB\ + 20703 LUT4 0777 /AB\(d+c) + 20704 LUT2 8 AB + 20705 LUT4 8000 ABCD + 20706 LUT4 0777 /AB\(d+c) + 20707 LUT4 0777 /AB\(d+c) + 20708 LUT4 0777 /AB\(d+c) + 20709 LUT4 0777 /AB\(d+c) + 20710 LUT4 0777 /AB\(d+c) + 20711 LUT4 0777 /AB\(d+c) + 20712 LUT4 8000 ABCD + 20713 LUT4 0700 cD/AB\ + 20714 LUT4 0777 /AB\(d+c) + 20715 LUT2 8 AB + 20716 LUT4 8000 ABCD + 20717 LUT4 0777 /AB\(d+c) + 20718 LUT4 0777 /AB\(d+c) + 20719 LUT4 0777 /AB\(d+c) + 20720 LUT4 0777 /AB\(d+c) + 20721 LUT4 0777 /AB\(d+c) + 20722 LUT4 0777 /AB\(d+c) + 20723 LUT4 B0BB /aB\(d+C) + 20724 LUT3 4F (aB)+c + 20725 LUT4 B0BB /aB\(d+C) + 20726 LUT3 0B c/aB\ + 20727 LUT3 07 c/AB\ + 20728 LUT4 8000 ABCD + 20729 LUT4 0777 /AB\(d+c) + 20730 LUT4 0777 /AB\(d+c) + 20731 LUT4 0777 /AB\(d+c) + 20732 LUT4 0777 /AB\(d+c) + 20733 LUT4 8000 ABCD + 20734 LUT4 0777 /AB\(d+c) + 20735 LUT4 0777 /AB\(d+c) + 20736 LUT4 0777 /AB\(d+c) + 20737 LUT4 0777 /AB\(d+c) + 20738 LUT4 8000 ABCD + 20739 LUT4 0700 cD/AB\ + 20740 LUT2 8 AB + 20741 LUT4 0777 /AB\(d+c) + 20742 LUT4 8000 ABCD + 20743 LUT4 0777 /AB\(d+c) + 20744 LUT4 0777 /AB\(d+c) + 20745 LUT4 0777 /AB\(d+c) + 20746 LUT4 0777 /AB\(d+c) + 20747 LUT4 0777 /AB\(d+c) + 20748 LUT4 0777 /AB\(d+c) + 20749 LUT4 B0BB /aB\(d+C) + 20750 LUT4 8000 ABCD + 20751 LUT4 0700 cD/AB\ + 20752 LUT4 0777 /AB\(d+c) + 20753 LUT2 8 AB + 20754 LUT4 8000 ABCD + 20755 LUT4 0777 /AB\(d+c) + 20756 LUT4 0777 /AB\(d+c) + 20757 LUT4 0777 /AB\(d+c) + 20758 LUT4 0777 /AB\(d+c) + 20759 LUT4 0777 /AB\(d+c) + 20760 LUT4 0777 /AB\(d+c) + 20761 LUT4 8000 ABCD + 20762 LUT4 0700 cD/AB\ + 20763 LUT4 0777 /AB\(d+c) + 20764 LUT2 8 AB + 20765 LUT4 8000 ABCD + 20766 LUT4 0777 /AB\(d+c) + 20767 LUT4 0777 /AB\(d+c) + 20768 LUT4 0777 /AB\(d+c) + 20769 LUT4 0777 /AB\(d+c) + 20770 LUT4 0777 /AB\(d+c) + 20771 LUT4 0777 /AB\(d+c) + 20772 LUT4 B0BB /aB\(d+C) + 20773 LUT2 4 aB + 20774 LUT4 8000 ABCD + 20775 LUT4 0001 abcd + 20776 LUT4 0001 abcd + 20777 LUT4 0001 abcd + 20778 LUT4 0001 abcd + 20779 LUT2 6 A^B + 20780 LUT2 E /ab\ + 20781 LUT2 8 AB + 20782 LUT2 8 AB + 20783 LUT4 0100 abcD + 20784 LUT4 FE00 ((/ab\)+C)D + 20785 LUT2 1 ab + 20786 LUT3 F4 (aB)+C + 20787 LUT4 CA00 D(C?A:B) + 20788 LUT2 8 AB + 20789 LUT4 0001 abcd + 20790 LUT3 F4 (aB)+C + 20791 LUT4 DFC0 BD?0:C:/AC\:1 + 20792 LUT3 80 ABC + 20793 LUT4 CA00 D(C?A:B) + 20794 LUT2 8 AB + 20795 LUT4 5CCC DC?B:B:B:a + 20796 LUT3 35 c?b:a + 20797 LUT3 60 C(A^B) + 20798 LUT2 8 AB + 20799 LUT4 FF40 (aBC)+D + 20800 LUT4 BF00 ((/aB\)+c)D + 20801 LUT2 4 aB + 20802 LUT4 FF80 (ABC)+D + 20803 LUT4 7F00 ((/AB\)+c)D + 20804 LUT4 5CCC DC?B:B:B:a + 20805 LUT4 FF40 (aBC)+D + 20806 LUT4 BF00 ((/aB\)+c)D + 20807 LUT3 8F (AB)+c + 20808 LUT4 0FBB D?/aB\:c + 20809 LUT2 8 AB + 20810 LUT2 4 aB + 20811 LUT4 1000 abCD + 20812 LUT4 DFC0 BD?0:C:/AC\:1 + 20813 LUT3 3A c?b:A + 20814 LUT3 80 ABC + 20815 LUT3 40 aBC + 20816 LUT2 1 ab + 20817 LUT3 F4 (aB)+C + 20818 LUT4 AC00 D(c?A:B) + 20819 LUT2 8 AB + 20820 LUT4 0001 abcd + 20821 LUT3 F4 (aB)+C + 20822 LUT4 DFC0 BD?0:C:/AC\:1 + 20823 LUT3 80 ABC + 20824 LUT4 AC00 D(c?A:B) + 20825 LUT2 8 AB + 20826 LUT4 ACCC DC?B:B:B:A + 20827 LUT3 AC c?A:B + 20828 LUT3 60 C(A^B) + 20829 LUT2 8 AB + 20830 LUT4 DFC0 BD?0:C:/AC\:1 + 20831 LUT2 4 aB + 20832 LUT2 4 aB + 20833 LUT2 4 aB + 20834 LUT4 FF80 (ABC)+D + 20835 LUT4 7F00 ((/AB\)+c)D + 20836 LUT4 ACCC DC?B:B:B:A + 20837 LUT4 DFC0 BD?0:C:/AC\:1 + 20838 LUT4 DFC0 BD?0:C:/AC\:1 + 20839 LUT2 4 aB + 20840 LUT3 CA C?A:B + 20841 LUT3 80 ABC + 20842 LUT2 4 aB + 20843 LUT3 10 abC + 20844 LUT3 10 abC + 20845 LUT3 10 abC + 20846 LUT3 40 aBC + 20847 LUT3 10 abC + 20848 LUT3 40 aBC + 20849 LUT3 10 abC + 20850 LUT3 40 aBC + 20851 LUT3 40 aBC + 20852 LUT3 EF /ab\+c + 20853 LUT3 40 aBC + 20854 LUT3 40 aBC + 20855 LUT3 40 aBC + 20856 LUT2 4 aB + 20857 LUT2 8 AB + 20858 LUT2 4 aB + 20859 LUT2 4 aB + 20860 LUT2 4 aB + 20861 LUT2 4 aB + 20862 LUT2 4 aB + 20863 LUT2 4 aB + 20864 LUT2 4 aB + 20865 LUT2 4 aB + 20866 LUT2 4 aB + 20867 LUT2 4 aB + 20868 LUT2 4 aB + 20869 LUT2 4 aB + 20870 LUT2 4 aB + 20871 LUT2 4 aB + 20872 LUT2 4 aB + 20873 LUT2 4 aB + 20874 LUT2 4 aB + 20875 LUT2 4 aB + 20876 LUT2 4 aB + 20877 LUT2 4 aB + 20878 LUT2 4 aB + 20879 LUT2 4 aB + 20880 LUT2 4 aB + 20881 LUT2 4 aB + 20882 LUT2 4 aB + 20883 LUT2 4 aB + 20884 LUT2 4 aB + 20885 LUT2 4 aB + 20886 LUT2 4 aB + 20887 LUT2 4 aB + 20888 LUT2 4 aB + 20889 LUT2 4 aB + 20890 LUT2 4 aB + 20891 LUT2 4 aB + 20892 LUT2 4 aB + 20893 LUT2 4 aB + 20894 LUT2 4 aB + 20895 LUT2 4 aB + 20896 LUT2 4 aB + 20897 LUT2 4 aB + 20898 LUT2 4 aB + 20899 LUT2 4 aB + 20900 LUT2 4 aB + 20901 LUT2 4 aB + 20902 LUT2 4 aB + 20903 LUT2 4 aB + 20904 LUT2 4 aB + 20905 LUT2 4 aB + 20906 LUT2 4 aB + 20907 LUT2 4 aB + 20908 LUT2 4 aB + 20909 LUT2 4 aB + 20910 LUT3 40 aBC + 20911 LUT2 4 aB + 20912 LUT2 4 aB + 20913 LUT2 4 aB + 20914 LUT2 4 aB + 20915 LUT2 4 aB + 20916 LUT2 4 aB + 20917 LUT3 40 aBC + 20918 LUT2 4 aB + 20919 LUT2 4 aB + 20920 LUT2 4 aB + 20921 LUT2 4 aB + 20922 LUT2 4 aB + 20923 LUT2 4 aB + 20924 LUT3 40 aBC + 20925 LUT2 4 aB + 20926 LUT2 4 aB + 20927 LUT2 4 aB + 20928 LUT2 4 aB + 20929 LUT2 4 aB + 20930 LUT2 4 aB + 20931 LUT2 4 aB + 20932 LUT2 4 aB + 20933 LUT3 80 ABC + 20934 LUT2 4 aB + 20935 LUT2 4 aB + 20936 LUT2 4 aB + 20937 LUT2 4 aB + 20938 LUT2 4 aB + 20939 LUT2 4 aB + 20940 LUT3 80 ABC + 20941 LUT2 4 aB + 20942 LUT2 4 aB + 20943 LUT2 4 aB + 20944 LUT2 4 aB + 20945 LUT2 B /aB\ + 20946 LUT3 CA C?A:B + 20947 LUT4 0100 abcD + 20948 LUT2 4 aB + 20949 LUT3 AC c?A:B + 20950 LUT3 F4 (aB)+C + 20951 LUT3 F4 (aB)+C + 20952 LUT3 80 ABC + 20953 LUT3 80 ABC + 20954 LUT2 8 AB + 20955 LUT3 F4 (aB)+C + 20956 LUT3 40 aBC + 20957 LUT4 00BF ((/aB\)+c)d + 20958 LUT3 40 aBC + 20959 LUT2 8 AB + 20960 LUT3 CA C?A:B + 20961 LUT4 BF30 BD?C:0:1:/aC\ + 20962 LUT4 87FF AD?1:1:c:b^C + 20963 LUT4 DFC0 BD?0:C:/AC\:1 + 20964 LUT3 40 aBC + 20965 LUT3 60 C(A^B) + 20966 LUT4 FF10 (abC)+D + 20967 LUT3 D0 C/Ab\ + 20968 LUT4 E1FF AD?1:1:b^C:C + 20969 LUT3 CA C?A:B + 20970 LUT3 40 aBC + 20971 LUT4 FCFA DC?A:B:1:1 + 20972 LUT3 80 ABC + 20973 LUT3 80 ABC + 20974 LUT2 4 aB + 20975 LUT4 BF00 ((/aB\)+c)D + 20976 LUT3 70 C/AB\ + 20977 LUT4 1000 abCD + 20978 LUT3 B0 C/aB\ + 20979 LUT4 ACCC DC?B:B:B:A + 20980 LUT4 5CCC DC?B:B:B:a + 20981 LUT4 0E00 cD/ab\ + 20982 LUT4 CCCA DC?A:B:B:B + 20983 LUT3 CA C?A:B + 20984 LUT4 BF30 BD?C:0:1:/aC\ + 20985 LUT4 DFC0 BD?0:C:/AC\:1 + 20986 LUT4 FF10 (abC)+D + 20987 LUT3 D0 C/Ab\ + 20988 LUT4 0007 cd/AB\ + 20989 LUT4 CA00 D(C?A:B) + 20990 LUT4 EF00 ((/ab\)+c)D + 20991 LUT3 F4 (aB)+C + 20992 LUT3 F4 (aB)+C + 20993 LUT3 F4 (aB)+C + 20994 LUT4 FF70 (C/AB\)+D + 20995 LUT4 AC00 D(c?A:B) + 20996 LUT2 4 aB + 20997 LUT2 8 AB + 20998 LUT4 7F30 BD?C:0:1:/AC\ + 20999 LUT4 00EF ((/ab\)+c)d + 21000 LUT3 AC c?A:B + 21001 LUT3 40 aBC + 21002 LUT4 7800 AD?0:0:C:B^C + 21003 LUT4 BF30 BD?C:0:1:/aC\ + 21004 LUT4 BB0F D?c:/aB\ + 21005 LUT3 9F (a^B)+c + 21006 LUT4 BF30 BD?C:0:1:/aC\ + 21007 LUT4 7077 /AB\(d+C) + 21008 LUT4 1000 abCD + 21009 LUT3 0B c/aB\ + 21010 LUT4 FF80 (ABC)+D + 21011 LUT3 CA C?A:B + 21012 LUT2 8 AB + 21013 LUT2 8 AB + 21014 LUT4 BF00 ((/aB\)+c)D + 21015 LUT3 01 abc + 21016 LUT2 8 AB + 21017 LUT3 4F (aB)+c + 21018 LUT4 007F ((/AB\)+c)d + 21019 LUT3 80 ABC + 21020 LUT2 8 AB + 21021 LUT2 4 aB + 21022 LUT4 F444 (aB)+(CD) + 21023 LUT2 8 AB + 21024 LUT4 F444 (aB)+(CD) + 21025 LUT4 0AC0 DC?0:A:B:0 + 21026 LUT3 F4 (aB)+C + 21027 LUT3 40 aBC + 21028 LUT4 80FF (ABC)+d + 21029 LUT3 0D c/Ab\ + 21030 LUT3 80 ABC + 21031 LUT3 10 abC + 21032 LUT4 F444 (aB)+(CD) + 21033 LUT4 F444 (aB)+(CD) + 21034 LUT3 F4 (aB)+C + 21035 LUT4 4000 aBCD + 21036 LUT3 F4 (aB)+C + 21037 LUT3 F4 (aB)+C + 21038 LUT3 80 ABC + 21039 LUT2 8 AB + 21040 LUT3 AC c?A:B + 21041 LUT2 8 AB + 21042 LUT2 8 AB + 21043 LUT2 8 AB + 21044 LUT3 F4 (aB)+C + 21045 LUT3 80 ABC + 21046 LUT4 0AC0 DC?0:A:B:0 + 21047 LUT4 FF80 (ABC)+D + 21048 LUT2 4 aB + 21049 LUT4 1F00 ((ab)+c)D + 21050 LUT3 F8 (AB)+C + 21051 LUT4 BF00 ((/aB\)+c)D + 21052 LUT4 B0BB /aB\(d+C) + 21053 LUT2 4 aB + 21054 LUT2 4 aB + 21055 LUT3 0B c/aB\ + 21056 LUT3 80 ABC + 21057 LUT3 F8 (AB)+C + 21058 LUT2 8 AB + 21059 LUT2 4 aB + 21060 LUT4 BF00 ((/aB\)+c)D + 21061 LUT4 3115 AB?1:CD:cd:0 + 21062 LUT3 F8 (AB)+C + 21063 LUT2 8 AB + 21064 LUT2 4 aB + 21065 LUT4 BF00 ((/aB\)+c)D + 21066 LUT4 1351 AB?1:cD:Cd:0 + 21067 LUT4 EFC0 BD?0:C:/aC\:1 + 21068 LUT3 40 aBC + 21069 LUT3 8F (AB)+c + 21070 LUT3 F4 (aB)+C + 21071 LUT4 0700 cD/AB\ + 21072 LUT2 8 AB + 21073 LUT2 8 AB + 21074 LUT2 4 aB + 21075 LUT4 D000 CD/Ab\ + 21076 LUT4 0777 /AB\(d+c) + 21077 LUT4 FF80 (ABC)+D + 21078 LUT4 0700 cD/AB\ + 21079 LUT4 D000 CD/Ab\ + 21080 LUT4 FF80 (ABC)+D + 21081 LUT4 0700 cD/AB\ + 21082 LUT4 D000 CD/Ab\ + 21083 LUT3 F4 (aB)+C + 21084 LUT3 80 ABC + 21085 LUT4 C200 D(BC?A:0:0:1) + 21086 LUT4 FF10 (abC)+D + 21087 LUT3 D0 C/Ab\ + 21088 LUT4 BF00 ((/aB\)+c)D + 21089 LUT4 FF40 (aBC)+D + 21090 LUT4 0B00 cD/aB\ + 21091 LUT2 4 aB + 21092 LUT2 8 AB + 21093 LUT4 FF40 (aBC)+D + 21094 LUT3 B0 C/aB\ + 21095 LUT3 B0 C/aB\ + 21096 LUT3 F8 (AB)+C + 21097 LUT3 10 abC + 21098 LUT4 0B00 cD/aB\ + 21099 LUT4 B0FF (C/aB\)+d + 21100 LUT3 07 c/AB\ + 21101 LUT3 80 ABC + 21102 LUT3 70 C/AB\ + 21103 LUT4 F800 ((AB)+C)D + 21104 LUT4 FF10 (abC)+D + 21105 LUT3 80 ABC + 21106 LUT3 10 abC + 21107 LUT4 FF80 (ABC)+D + 21108 LUT4 0700 cD/AB\ + 21109 LUT4 E000 CD/ab\ + 21110 LUT4 FF80 (ABC)+D + 21111 LUT4 1F00 ((ab)+c)D + 21112 LUT4 EFC0 BD?0:C:/aC\:1 + 21113 LUT4 EFC0 BD?0:C:/aC\:1 + 21114 LUT4 EFC0 BD?0:C:/aC\:1 + 21115 LUT4 EFC0 BD?0:C:/aC\:1 + 21116 LUT3 5C c?a:B + 21117 LUT4 F800 ((AB)+C)D + 21118 LUT2 4 aB + 21119 LUT4 D000 CD/Ab\ + 21120 LUT4 FF80 (ABC)+D + 21121 LUT4 0700 cD/AB\ + 21122 LUT4 D000 CD/Ab\ + 21123 LUT2 4 aB + 21124 LUT3 F4 (aB)+C + 21125 LUT4 F800 ((AB)+C)D + 21126 LUT4 0E00 cD/ab\ + 21127 LUT3 80 ABC + 21128 LUT3 F4 (aB)+C + 21129 LUT3 80 ABC + 21130 LUT4 F400 ((aB)+C)D + 21131 LUT2 8 AB + 21132 LUT4 FF10 (abC)+D + 21133 LUT3 70 C/AB\ + 21134 LUT3 B0 C/aB\ + 21135 LUT2 8 AB + 21136 LUT4 FF40 (aBC)+D + 21137 LUT3 B0 C/aB\ + 21138 LUT3 70 C/AB\ + 21139 LUT4 FF40 (aBC)+D + 21140 LUT3 D0 C/Ab\ + 21141 LUT4 1351 AB?1:cD:Cd:0 + 21142 LUT3 AC c?A:B + 21143 LUT4 F400 ((aB)+C)D + 21144 LUT4 70FF (C/AB\)+d + 21145 LUT4 0777 /AB\(d+c) + 21146 LUT3 70 C/AB\ + 21147 LUT3 F8 (AB)+C + 21148 LUT3 D0 C/Ab\ + 21149 LUT4 7077 /AB\(d+C) + 21150 LUT2 8 AB + 21151 LUT3 80 ABC + 21152 LUT3 F8 (AB)+C + 21153 LUT4 0700 cD/AB\ + 21154 LUT4 4000 aBCD + 21155 LUT4 F444 (aB)+(CD) + 21156 LUT4 E000 CD/ab\ + 21157 LUT4 4F44 (aB)+(cD) + 21158 LUT3 40 aBC + 21159 LUT3 F8 (AB)+C + 21160 LUT4 BF00 ((/aB\)+c)D + 21161 LUT4 F444 (aB)+(CD) + 21162 LUT3 40 aBC + 21163 LUT2 8 AB + 21164 LUT2 8 AB + 21165 LUT3 80 ABC + 21166 LUT3 80 ABC + 21167 LUT3 3A c?b:A + 21168 LUT3 10 abC + 21169 LUT3 35 c?b:a + 21170 LUT3 F4 (aB)+C + 21171 LUT4 5CCC DC?B:B:B:a + 21172 LUT2 8 AB + 21173 LUT2 8 AB + 21174 LUT4 DFC0 BD?0:C:/AC\:1 + 21175 LUT2 8 AB + 21176 LUT2 4 aB + 21177 LUT4 00BF ((/aB\)+c)d + 21178 LUT3 80 ABC + 21179 LUT2 4 aB + 21180 LUT2 8 AB + 21181 LUT4 6000 CD(A^B) + 21182 LUT4 5CCC DC?B:B:B:a + 21183 LUT2 8 AB + 21184 LUT4 BF30 BD?C:0:1:/aC\ + 21185 LUT4 007F ((/AB\)+c)d + 21186 LUT3 40 aBC + 21187 LUT2 4 aB + 21188 LUT3 53 C?b:a + 21189 LUT4 5CCC DC?B:B:B:a + 21190 LUT4 DFC0 BD?0:C:/AC\:1 + 21191 LUT2 1 ab + 21192 LUT4 1400 D(B^C)a + 21193 LUT3 3A c?b:A + 21194 LUT2 8 AB + 21195 LUT2 4 aB + 21196 LUT2 8 AB + 21197 LUT2 4 aB + 21198 LUT3 3A c?b:A + 21199 LUT4 DFC0 BD?0:C:/AC\:1 + 21200 LUT4 5CCC DC?B:B:B:a + 21201 LUT4 BF30 BD?C:0:1:/aC\ + 21202 LUT4 5CCC DC?B:B:B:a + 21203 LUT4 DFC0 BD?0:C:/AC\:1 + 21204 LUT3 3A c?b:A + 21205 LUT2 8 AB + 21206 LUT3 80 ABC + 21207 LUT2 4 aB + 21208 LUT3 3A c?b:A + 21209 LUT4 DFC0 BD?0:C:/AC\:1 + 21210 LUT4 FFB0 (C/aB\)+D + 21211 LUT4 1000 abCD + 21212 LUT4 0C0A DC?A:B:0:0 + 21213 LUT2 4 aB + 21214 LUT4 AC00 D(c?A:B) + 21215 LUT2 8 AB + 21216 LUT3 01 abc + 21217 LUT4 4F44 (aB)+(cD) + 21218 LUT4 007F ((/AB\)+c)d + 21219 LUT3 80 ABC + 21220 LUT2 8 AB + 21221 LUT2 4 aB + 21222 LUT4 4F44 (aB)+(cD) + 21223 LUT4 0F77 D?/AB\:c + 21224 LUT2 8 AB + 21225 LUT4 4F44 (aB)+(cD) + 21226 LUT4 35FF (c?b:a)+d + 21227 LUT2 8 AB + 21228 LUT2 4 aB + 21229 LUT3 F4 (aB)+C + 21230 LUT4 CA00 D(C?A:B) + 21231 LUT4 F444 (aB)+(CD) + 21232 LUT4 CA00 D(C?A:B) + 21233 LUT3 60 C(A^B) + 21234 LUT3 F4 (aB)+C + 21235 LUT4 CA00 D(C?A:B) + 21236 LUT3 F4 (aB)+C + 21237 LUT3 10 abC + 21238 LUT4 F444 (aB)+(CD) + 21239 LUT3 F4 (aB)+C + 21240 LUT3 F4 (aB)+C + 21241 LUT4 F444 (aB)+(CD) + 21242 LUT3 40 aBC + 21243 LUT4 35FF (c?b:a)+d + 21244 LUT2 8 AB + 21245 LUT4 EFC0 BD?0:C:/aC\:1 + 21246 LUT2 4 aB + 21247 LUT3 53 C?b:a + 21248 LUT3 10 abC + 21249 LUT3 1F (ab)+c + 21250 LUT2 8 AB + 21251 LUT3 F8 (AB)+C + 21252 LUT3 70 C/AB\ + 21253 LUT2 4 aB + 21254 LUT3 0B c/aB\ + 21255 LUT3 10 abC + 21256 LUT2 4 aB + 21257 LUT2 8 AB + 21258 LUT3 10 abC + 21259 LUT4 007F ((/AB\)+c)d + 21260 LUT3 80 ABC + 21261 LUT4 EFC0 BD?0:C:/aC\:1 + 21262 LUT3 10 abC + 21263 LUT4 0777 /AB\(d+c) + 21264 LUT4 D557 AB?1:cd:1:CD + 21265 LUT4 FF80 (ABC)+D + 21266 LUT4 BF00 ((/aB\)+c)D + 21267 LUT3 AC c?A:B + 21268 LUT2 1 ab + 21269 LUT4 DFC0 BD?0:C:/AC\:1 + 21270 LUT2 8 AB + 21271 LUT2 1 ab + 21272 LUT2 4 aB + 21273 LUT4 FF40 (aBC)+D + 21274 LUT3 70 C/AB\ + 21275 LUT2 8 AB + 21276 LUT2 8 AB + 21277 LUT2 4 aB + 21278 LUT4 BF00 ((/aB\)+c)D + 21279 LUT3 5C c?a:B + 21280 LUT3 07 c/AB\ + 21281 LUT3 40 aBC + 21282 LUT4 53FF (C?b:a)+d + 21283 LUT4 1000 abCD + 21284 LUT3 40 aBC + 21285 LUT4 A87F AD?1:/BC\:0:/bc\ + 21286 LUT4 FF40 (aBC)+D + 21287 LUT4 0700 cD/AB\ + 21288 LUT4 D000 CD/Ab\ + 21289 LUT4 FF40 (aBC)+D + 21290 LUT4 EF00 ((/ab\)+c)D + 21291 LUT4 B0FF (C/aB\)+d + 21292 LUT3 F4 (aB)+C + 21293 LUT4 EF00 ((/ab\)+c)D + 21294 LUT4 BF00 ((/aB\)+c)D + 21295 LUT2 8 AB + 21296 LUT4 7F50 AD?C:0:1:/BC\ + 21297 LUT3 B0 C/aB\ + 21298 LUT4 FF40 (aBC)+D + 21299 LUT4 BF00 ((/aB\)+c)D + 21300 LUT4 BF00 ((/aB\)+c)D + 21301 LUT4 FF40 (aBC)+D + 21302 LUT3 10 abC + 21303 LUT4 1000 abCD + 21304 LUT3 8F (AB)+c + 21305 LUT4 00BF ((/aB\)+c)d + 21306 LUT4 0B00 cD/aB\ + 21307 LUT3 40 aBC + 21308 LUT3 40 aBC + 21309 LUT3 40 aBC + 21310 LUT4 FF40 (aBC)+D + 21311 LUT4 0700 cD/AB\ + 21312 LUT4 E000 CD/ab\ + 21313 LUT4 EFC0 BD?0:C:/aC\:1 + 21314 LUT4 EFA0 AD?0:C:/bC\:1 + 21315 LUT4 EFC0 BD?0:C:/aC\:1 + 21316 LUT4 FFB0 (C/aB\)+D + 21317 LUT3 80 ABC + 21318 LUT4 DFC0 BD?0:C:/AC\:1 + 21319 LUT3 5C c?a:B + 21320 LUT4 F800 ((AB)+C)D + 21321 LUT2 4 aB + 21322 LUT3 40 aBC + 21323 LUT3 F4 (aB)+C + 21324 LUT4 0700 cD/AB\ + 21325 LUT4 D000 CD/Ab\ + 21326 LUT2 4 aB + 21327 LUT3 F4 (aB)+C + 21328 LUT4 F800 ((AB)+C)D + 21329 LUT4 D000 CD/Ab\ + 21330 LUT3 40 aBC + 21331 LUT4 FF40 (aBC)+D + 21332 LUT4 0700 cD/AB\ + 21333 LUT2 8 AB + 21334 LUT4 FF40 (aBC)+D + 21335 LUT3 70 C/AB\ + 21336 LUT3 B0 C/aB\ + 21337 LUT4 FF40 (aBC)+D + 21338 LUT3 B0 C/aB\ + 21339 LUT3 70 C/AB\ + 21340 LUT4 FF40 (aBC)+D + 21341 LUT3 70 C/AB\ + 21342 LUT3 B0 C/aB\ + 21343 LUT4 FF40 (aBC)+D + 21344 LUT3 B0 C/aB\ + 21345 LUT3 70 C/AB\ + 21346 LUT4 80FF (ABC)+d + 21347 LUT4 7077 /AB\(d+C) + 21348 LUT4 0700 cD/AB\ + 21349 LUT2 8 AB + 21350 LUT4 7F00 ((/AB\)+c)D + 21351 LUT3 4F (aB)+c + 21352 LUT4 0B33 BD?1:0:c:Ac + 21353 LUT2 4 aB + 21354 LUT2 4 aB + 21355 LUT3 F8 (AB)+C + 21356 LUT4 0700 cD/AB\ + 21357 LUT4 FF80 (ABC)+D + 21358 LUT4 BF00 ((/aB\)+c)D + 21359 LUT4 FF80 (ABC)+D + 21360 LUT3 70 C/AB\ + 21361 LUT4 FF80 (ABC)+D + 21362 LUT4 BF00 ((/aB\)+c)D + 21363 LUT3 F4 (aB)+C + 21364 LUT3 40 aBC + 21365 LUT4 8000 ABCD + 21366 LUT4 4000 aBCD + 21367 LUT3 80 ABC + 21368 LUT2 6 A^B + 21369 LUT2 6 A^B + 21370 LUT2 9 a^B + 21371 LUT2 6 A^B + 21372 LUT2 6 A^B + 21373 LUT2 6 A^B + 21374 LUT2 6 A^B + 21375 LUT3 94 AB?C:0:c:C + 21376 LUT2 6 A^B + 21377 LUT2 6 A^B + 21378 LUT2 6 A^B + 21379 LUT2 6 A^B + 21380 LUT3 69 A^B^c + 21381 LUT4 00EF ((/ab\)+c)d + 21382 LUT4 00EF ((/ab\)+c)d + 21383 LUT4 00EF ((/ab\)+c)d + 21384 LUT3 17 AB?1:c:c:0 + 21385 LUT3 40 aBC + 21386 LUT2 6 A^B + 21387 LUT2 6 A^B + 21388 LUT2 8 AB + 21389 LUT2 8 AB + 21390 LUT2 9 a^B + 21391 LUT2 E /ab\ + 21392 LUT4 6996 A^B^c^d + 21393 LUT2 6 A^B + 21394 LUT4 8EE8 AB?0:C^D:C^D:1 + 21395 LUT3 E8 AB?0:C:C:1 + 21396 LUT4 8778 (AB)^C^D + 21397 LUT2 8 AB + 21398 LUT2 8 AB + 21399 LUT4 E888 AB?0:CD:CD:1 + 21400 LUT2 6 A^B + 21401 LUT2 8 AB + 21402 LUT2 8 AB + 21403 LUT2 8 AB + 21404 LUT3 96 A^B^C + 21405 LUT3 96 A^B^C + 21406 LUT3 96 A^B^C + 21407 LUT3 96 A^B^C + 21408 LUT3 96 A^B^C + 21409 LUT3 96 A^B^C + 21410 LUT3 96 A^B^C + 21411 LUT3 96 A^B^C + 21412 LUT3 96 A^B^C + 21413 LUT3 96 A^B^C + 21414 LUT3 96 A^B^C + 21415 LUT3 96 A^B^C + 21416 LUT3 96 A^B^C + 21417 LUT3 96 A^B^C + 21418 LUT3 96 A^B^C + 21419 LUT3 96 A^B^C + 21420 LUT3 96 A^B^C + 21421 LUT3 96 A^B^C + 21422 LUT3 96 A^B^C + 21423 LUT3 96 A^B^C + 21424 LUT3 96 A^B^C + 21425 LUT3 96 A^B^C + 21426 LUT3 96 A^B^C + 21427 LUT3 96 A^B^C + 21428 LUT3 96 A^B^C + 21429 LUT3 96 A^B^C + 21430 LUT3 96 A^B^C + 21431 LUT3 96 A^B^C + 21432 LUT3 96 A^B^C + 21433 LUT3 96 A^B^C + 21434 LUT3 96 A^B^C + 21435 LUT3 96 A^B^C + 21436 LUT3 E8 AB?0:C:C:1 + 21437 LUT3 E8 AB?0:C:C:1 + 21438 LUT3 E8 AB?0:C:C:1 + 21439 LUT3 E8 AB?0:C:C:1 + 21440 LUT3 E8 AB?0:C:C:1 + 21441 LUT3 E8 AB?0:C:C:1 + 21442 LUT3 E8 AB?0:C:C:1 + 21443 LUT3 E8 AB?0:C:C:1 + 21444 LUT3 E8 AB?0:C:C:1 + 21445 LUT3 E8 AB?0:C:C:1 + 21446 LUT3 E8 AB?0:C:C:1 + 21447 LUT3 E8 AB?0:C:C:1 + 21448 LUT3 E8 AB?0:C:C:1 + 21449 LUT3 E8 AB?0:C:C:1 + 21450 LUT3 E8 AB?0:C:C:1 + 21451 LUT3 E8 AB?0:C:C:1 + 21452 LUT3 E8 AB?0:C:C:1 + 21453 LUT3 E8 AB?0:C:C:1 + 21454 LUT3 E8 AB?0:C:C:1 + 21455 LUT3 E8 AB?0:C:C:1 + 21456 LUT3 E8 AB?0:C:C:1 + 21457 LUT3 E8 AB?0:C:C:1 + 21458 LUT3 E8 AB?0:C:C:1 + 21459 LUT3 E8 AB?0:C:C:1 + 21460 LUT3 E8 AB?0:C:C:1 + 21461 LUT3 E8 AB?0:C:C:1 + 21462 LUT3 E8 AB?0:C:C:1 + 21463 LUT3 E8 AB?0:C:C:1 + 21464 LUT3 E8 AB?0:C:C:1 + 21465 LUT3 E8 AB?0:C:C:1 + 21466 LUT3 E8 AB?0:C:C:1 + 21467 LUT3 E8 AB?0:C:C:1 + 21468 LUT3 96 A^B^C + 21469 LUT3 E8 AB?0:C:C:1 + 21470 LUT2 6 A^B + 21471 LUT3 D4 AB?C:0:1:C + 21472 LUT2 6 A^B + 21473 LUT4 0FF4 DC?aB:1:1:0 + 21474 LUT2 8 AB + 21475 LUT2 9 a^B + 21476 LUT3 17 AB?1:c:c:0 + 21477 LUT3 96 A^B^C + 21478 LUT2 6 A^B + 21479 LUT3 96 A^B^C + 21480 LUT4 17E8 (AB?1:c:c:0)^d + 21481 LUT2 8 AB + 21482 LUT2 6 A^B + 21483 LUT3 17 AB?1:c:c:0 + 21484 LUT3 17 AB?1:c:c:0 + 21485 LUT4 E800 D(AB?0:C:C:1) + 21486 LUT2 1 ab + 21487 LUT3 71 AB?1:C:C:0 + 21488 LUT2 6 A^B + 21489 LUT3 69 A^B^c + 21490 LUT3 17 AB?1:c:c:0 + 21491 LUT3 96 A^B^C + 21492 LUT3 96 A^B^C + 21493 LUT3 17 AB?1:c:c:0 + 21494 LUT3 96 A^B^C + 21495 LUT3 17 AB?1:c:c:0 + 21496 LUT3 17 AB?1:c:c:0 + 21497 LUT3 96 A^B^C + 21498 LUT3 96 A^B^C + 21499 LUT3 E8 AB?0:C:C:1 + 21500 LUT4 0777 /AB\(d+c) + 21501 LUT2 1 ab + 21502 LUT3 96 A^B^C + 21503 LUT3 96 A^B^C + 21504 LUT3 96 A^B^C + 21505 LUT3 96 A^B^C + 21506 LUT3 96 A^B^C + 21507 LUT3 96 A^B^C + 21508 LUT3 96 A^B^C + 21509 LUT3 96 A^B^C + 21510 LUT3 17 AB?1:c:c:0 + 21511 LUT3 69 A^B^c + 21512 LUT3 17 AB?1:c:c:0 + 21513 LUT3 69 A^B^c + 21514 LUT2 6 A^B + 21515 LUT3 17 AB?1:c:c:0 + 21516 LUT3 17 AB?1:c:c:0 + 21517 LUT3 17 AB?1:c:c:0 + 21518 LUT3 69 A^B^c + 21519 LUT3 96 A^B^C + 21520 LUT3 2B AB?c:1:0:c + 21521 LUT2 1 ab + 21522 LUT3 E8 AB?0:C:C:1 + 21523 LUT3 71 AB?1:C:C:0 + 21524 LUT3 B2 AB?C:1:0:C + 21525 LUT4 B44B (aB)^c^D + 21526 LUT4 4DDD AB?/CD\:0:1:/CD\ + 21527 LUT4 0B04 AC?B^D:D:0:0 + 21528 LUT3 69 A^B^c + 21529 LUT4 7887 (AB)^C^d + 21530 LUT3 B2 AB?C:1:0:C + 21531 LUT2 8 AB + 21532 LUT3 40 aBC + 21533 LUT3 80 ABC + 21534 LUT2 8 AB + 21535 LUT2 8 AB + 21536 LUT2 8 AB + 21537 LUT2 8 AB + 21538 LUT3 80 ABC + 21539 LUT3 80 ABC + 21540 LUT3 80 ABC + 21541 LUT3 80 ABC + 21542 LUT2 4 aB + 21543 LUT4 BF00 ((/aB\)+c)D + 21544 LUT2 4 aB + 21545 LUT4 BF00 ((/aB\)+c)D + 21546 LUT2 4 aB + 21547 LUT4 BF00 ((/aB\)+c)D + 21548 LUT2 4 aB + 21549 LUT4 BF00 ((/aB\)+c)D + 21550 LUT2 E /ab\ + 21551 LUT4 8000 ABCD + 21552 LUT2 8 AB + 21553 LUT4 0001 abcd + 21554 LUT3 10 abC + 21555 LUT2 1 ab + 21556 LUT4 0100 abcD + 21557 LUT4 1000 abCD + 21558 LUT3 40 aBC + 21559 LUT4 D700 AD?0:0:1:b^C + 21560 LUT3 60 C(A^B) + 21561 LUT4 1428 (B^C)(A^D) + 21562 LUT4 1400 D(B^C)a + 21563 LUT2 9 a^B + 21564 LUT4 1428 (B^C)(A^D) + 21565 LUT4 E0FF (C/ab\)+d + 21566 LUT3 80 ABC + 21567 LUT2 4 aB + 21568 LUT4 8000 ABCD + 21569 LUT3 01 abc + 21570 LUT4 E000 CD/ab\ + 21571 LUT4 1000 abCD + 21572 LUT4 0001 abcd + 21573 LUT4 E0FF (C/ab\)+d + 21574 LUT4 1000 abCD + 21575 LUT3 10 abC + 21576 LUT4 0001 abcd + 21577 LUT3 40 aBC + 21578 LUT4 E0FF (C/ab\)+d + 21579 LUT3 10 abC + 21580 LUT3 40 aBC + 21581 LUT3 10 abC + 21582 LUT2 8 AB + 21583 LUT4 4000 aBCD + 21584 LUT4 4000 aBCD + 21585 LUT2 8 AB + 21586 LUT2 8 AB + 21587 LUT4 8000 ABCD + 21588 LUT2 8 AB + 21589 LUT4 4000 aBCD + 21590 LUT2 8 AB + 21591 LUT2 8 AB + 21592 LUT2 8 AB + 21593 LUT4 8000 ABCD + 21594 LUT2 8 AB + 21595 LUT2 8 AB + 21596 LUT4 1000 abCD + 21597 LUT4 1000 abCD + 21598 LUT4 1000 abCD + 21599 LUT4 4000 aBCD + 21600 LUT4 4000 aBCD + 21601 LUT4 4000 aBCD + 21602 LUT4 4000 aBCD + 21603 LUT4 4000 aBCD + 21604 LUT4 4000 aBCD + 21605 LUT4 8000 ABCD + 21606 LUT4 8000 ABCD + 21607 LUT4 8000 ABCD + 21608 LUT2 8 AB + 21609 LUT2 8 AB + 21610 LUT2 8 AB + 21611 LUT3 BE /(B^c)a\ + 21612 LUT3 70 C/AB\ + 21613 LUT4 FF70 (C/AB\)+D + 21614 LUT3 BE /(B^c)a\ + 21615 LUT3 70 C/AB\ + 21616 LUT4 4FF4 (aB)+(D^C) + 21617 LUT4 1000 abCD + 21618 LUT3 F4 (aB)+C + 21619 LUT4 4000 aBCD + 21620 LUT3 F4 (aB)+C + 21621 LUT4 4000 aBCD + 21622 LUT3 F4 (aB)+C + 21623 LUT4 8000 ABCD + 21624 LUT4 FF70 (C/AB\)+D + 21625 LUT3 70 C/AB\ + 21626 LUT3 8F (AB)+c + 21627 LUT4 0777 /AB\(d+c) + 21628 LUT3 8F (AB)+c + 21629 LUT4 0777 /AB\(d+c) + 21630 LUT3 8F (AB)+c + 21631 LUT4 0777 /AB\(d+c) + 21632 LUT4 0100 abcD + 21633 LUT2 E /ab\ + 21634 LUT2 E /ab\ + 21635 LUT3 F4 (aB)+C + 21636 LUT4 BEAA AD?0:1:B^C:1 + 21637 LUT3 B0 C/aB\ + 21638 LUT2 1 ab + 21639 LUT4 7077 /AB\(d+C) + 21640 LUT2 8 AB + 21641 LUT2 8 AB + 21642 LUT2 1 ab + 21643 LUT4 7077 /AB\(d+C) + 21644 LUT2 1 ab + 21645 LUT4 7077 /AB\(d+C) + 21646 LUT2 1 ab + 21647 LUT4 7077 /AB\(d+C) + 21648 LUT2 1 ab + 21649 LUT4 7077 /AB\(d+C) + 21650 LUT2 8 AB + 21651 LUT2 8 AB + 21652 LUT2 8 AB + 21653 LUT2 8 AB + 21654 LUT2 8 AB + 21655 LUT2 8 AB + 21656 LUT4 FF80 (ABC)+D + 21657 LUT2 8 AB + 21658 LUT3 80 ABC + 21659 LUT3 E0 C/ab\ + 21660 LUT2 4 aB + 21661 LUT3 10 abC + 21662 LUT3 70 C/AB\ + 21663 LUT3 E0 C/ab\ + 21664 LUT3 0E c/ab\ + 21665 LUT4 0D00 cD/Ab\ + 21666 LUT2 E /ab\ + 21667 LUT3 10 abC + 21668 LUT4 0007 cd/AB\ + 21669 LUT3 0D c/Ab\ + 21670 LUT4 0D00 cD/Ab\ + 21671 LUT2 8 AB + 21672 LUT3 4F (aB)+c + 21673 LUT4 0777 /AB\(d+c) + 21674 LUT3 80 ABC + 21675 LUT2 8 AB + 21676 LUT3 40 aBC + 21677 LUT2 7 /AB\ + 21678 LUT4 0777 /AB\(d+c) + 21679 LUT3 40 aBC + 21680 LUT4 7077 /AB\(d+C) + 21681 LUT2 7 /AB\ + 21682 LUT4 7077 /AB\(d+C) + 21683 LUT4 0777 /AB\(d+c) + 21684 LUT2 7 /AB\ + 21685 LUT4 0BBB /aB\(d+c) + 21686 LUT4 0777 /AB\(d+c) + 21687 LUT2 7 /AB\ + 21688 LUT4 0777 /AB\(d+c) + 21689 LUT4 0BBB /aB\(d+c) + 21690 LUT2 7 /AB\ + 21691 LUT4 7077 /AB\(d+C) + 21692 LUT4 0777 /AB\(d+c) + 21693 LUT3 4F (aB)+c + 21694 LUT3 70 C/AB\ + 21695 LUT4 0777 /AB\(d+c) + 21696 LUT4 F4FF (aB)+C+d + 21697 LUT2 8 AB + 21698 LUT4 0777 /AB\(d+c) + 21699 LUT4 F4FF (aB)+C+d + 21700 LUT4 0777 /AB\(d+c) + 21701 LUT2 8 AB + 21702 LUT4 FFFE /ab\+C+D + 21703 LUT2 8 AB + 21704 LUT2 8 AB + 21705 LUT2 8 AB + 21706 LUT2 4 aB + 21707 LUT4 FFFE /ab\+C+D + 21708 LUT2 8 AB + 21709 LUT2 4 aB + 21710 LUT2 8 AB + 21711 LUT2 8 AB + 21712 LUT4 FFFE /ab\+C+D + 21713 LUT2 8 AB + 21714 LUT2 4 aB + 21715 LUT2 8 AB + 21716 LUT2 8 AB + 21717 LUT4 FFFE /ab\+C+D + 21718 LUT2 8 AB + 21719 LUT2 8 AB + 21720 LUT2 4 aB + 21721 LUT2 8 AB + 21722 LUT4 FFFE /ab\+C+D + 21723 LUT2 8 AB + 21724 LUT2 4 aB + 21725 LUT2 8 AB + 21726 LUT2 8 AB + 21727 LUT4 FFFE /ab\+C+D + 21728 LUT2 8 AB + 21729 LUT2 8 AB + 21730 LUT2 4 aB + 21731 LUT2 8 AB + 21732 LUT4 FFFE /ab\+C+D + 21733 LUT2 8 AB + 21734 LUT2 8 AB + 21735 LUT2 4 aB + 21736 LUT2 8 AB + 21737 LUT4 FFFE /ab\+C+D + 21738 LUT2 8 AB + 21739 LUT2 8 AB + 21740 LUT2 4 aB + 21741 LUT2 8 AB + 21742 LUT4 FFFE /ab\+C+D + 21743 LUT2 4 aB + 21744 LUT2 8 AB + 21745 LUT2 8 AB + 21746 LUT2 8 AB + 21747 LUT4 FFFE /ab\+C+D + 21748 LUT2 8 AB + 21749 LUT2 4 aB + 21750 LUT2 8 AB + 21751 LUT2 8 AB + 21752 LUT4 FFFE /ab\+C+D + 21753 LUT2 8 AB + 21754 LUT2 8 AB + 21755 LUT2 8 AB + 21756 LUT2 4 aB + 21757 LUT4 FFFE /ab\+C+D + 21758 LUT2 8 AB + 21759 LUT2 8 AB + 21760 LUT2 8 AB + 21761 LUT2 4 aB + 21762 LUT4 FFFE /ab\+C+D + 21763 LUT2 8 AB + 21764 LUT2 4 aB + 21765 LUT2 8 AB + 21766 LUT2 8 AB + 21767 LUT4 F8FF (AB)+C+d + 21768 LUT4 7077 /AB\(d+C) + 21769 LUT2 8 AB + 21770 LUT4 F8FF (AB)+C+d + 21771 LUT4 0777 /AB\(d+c) + 21772 LUT2 4 aB + 21773 LUT4 F8FF (AB)+C+d + 21774 LUT4 0777 /AB\(d+c) + 21775 LUT2 4 aB + 21776 LUT4 F8FF (AB)+C+d + 21777 LUT4 0777 /AB\(d+c) + 21778 LUT2 4 aB + 21779 LUT4 FFFE /ab\+C+D + 21780 LUT2 8 AB + 21781 LUT2 8 AB + 21782 LUT2 4 aB + 21783 LUT2 8 AB + 21784 LUT4 F8FF (AB)+C+d + 21785 LUT4 7077 /AB\(d+C) + 21786 LUT2 8 AB + 21787 LUT4 F4FF (aB)+C+d + 21788 LUT4 0777 /AB\(d+c) + 21789 LUT2 8 AB + 21790 LUT4 F4FF (aB)+C+d + 21791 LUT4 0777 /AB\(d+c) + 21792 LUT2 8 AB + 21793 LUT4 8F88 (AB)+(cD) + 21794 LUT4 FF80 (ABC)+D + 21795 LUT3 10 abC + 21796 LUT2 E /ab\ + 21797 LUT2 E /ab\ + 21798 LUT2 E /ab\ + 21799 LUT2 4 aB + 21800 LUT3 40 aBC + 21801 LUT2 E /ab\ + 21802 LUT2 E /ab\ + 21803 LUT2 E /ab\ + 21804 LUT2 E /ab\ + 21805 LUT2 8 AB + 21806 LUT2 E /ab\ + 21807 LUT4 FF10 (abC)+D + 21808 LUT4 8F00 ((AB)+c)D + 21809 LUT3 70 C/AB\ + 21810 LUT2 8 AB + 21811 LUT3 E0 C/ab\ + 21812 LUT3 F4 (aB)+C + 21813 LUT3 70 C/AB\ + 21814 LUT3 70 C/AB\ + 21815 LUT3 F4 (aB)+C + 21816 LUT4 0700 cD/AB\ + 21817 LUT3 40 aBC + 21818 LUT4 FF10 (abC)+D + 21819 LUT3 F4 (aB)+C + 21820 LUT4 7F00 ((/AB\)+c)D + 21821 LUT3 07 c/AB\ + 21822 LUT4 FF70 (C/AB\)+D + 21823 LUT4 0777 /AB\(d+c) + 21824 LUT2 8 AB + 21825 LUT4 FF10 (abC)+D + 21826 LUT4 8F00 ((AB)+c)D + 21827 LUT3 70 C/AB\ + 21828 LUT4 FFB0 (C/aB\)+D + 21829 LUT3 40 aBC + 21830 LUT2 4 aB + 21831 LUT2 8 AB + 21832 LUT4 FFB0 (C/aB\)+D + 21833 LUT3 80 ABC + 21834 LUT3 07 c/AB\ + 21835 LUT4 FF70 (C/AB\)+D + 21836 LUT4 0777 /AB\(d+c) + 21837 LUT2 8 AB + 21838 LUT4 FFB0 (C/aB\)+D + 21839 LUT2 8 AB + 21840 LUT3 70 C/AB\ + 21841 LUT4 FF10 (abC)+D + 21842 LUT4 8F00 ((AB)+c)D + 21843 LUT4 BF00 ((/aB\)+c)D + 21844 LUT4 FFB0 (C/aB\)+D + 21845 LUT3 80 ABC + 21846 LUT3 07 c/AB\ + 21847 LUT4 FF70 (C/AB\)+D + 21848 LUT4 0777 /AB\(d+c) + 21849 LUT2 8 AB + 21850 LUT4 FF70 (C/AB\)+D + 21851 LUT4 0777 /AB\(d+c) + 21852 LUT4 FF70 (C/AB\)+D + 21853 LUT3 07 c/AB\ + 21854 LUT3 40 aBC + 21855 LUT4 FF10 (abC)+D + 21856 LUT4 8F00 ((AB)+c)D + 21857 LUT4 007F ((/AB\)+c)d + 21858 LUT4 8F88 (AB)+(cD) + 21859 LUT3 D0 C/Ab\ + 21860 LUT3 10 abC + 21861 LUT3 F8 (AB)+C + 21862 LUT2 4 aB + 21863 LUT2 1 ab + 21864 LUT4 8F88 (AB)+(cD) + 21865 LUT4 000D cd/Ab\ + 21866 LUT3 10 abC + 21867 LUT4 8F88 (AB)+(cD) + 21868 LUT4 0007 cd/AB\ + 21869 LUT2 1 ab + 21870 LUT2 4 aB + 21871 LUT4 8F88 (AB)+(cD) + 21872 LUT3 D0 C/Ab\ + 21873 LUT4 8F88 (AB)+(cD) + 21874 LUT4 0007 cd/AB\ + 21875 LUT3 F8 (AB)+C + 21876 LUT4 8F88 (AB)+(cD) + 21877 LUT4 0007 cd/AB\ + 21878 LUT4 8F88 (AB)+(cD) + 21879 LUT3 D0 C/Ab\ + 21880 LUT4 8F88 (AB)+(cD) + 21881 LUT2 4 aB + 21882 LUT4 8F88 (AB)+(cD) + 21883 LUT3 D0 C/Ab\ + 21884 LUT3 F8 (AB)+C + 21885 LUT4 00F8 ((AB)+C)d + 21886 LUT4 00F8 ((AB)+C)d + 21887 LUT4 EF00 ((/ab\)+c)D + 21888 LUT4 8F00 ((AB)+c)D + 21889 LUT4 004F ((aB)+c)d + 21890 LUT3 07 c/AB\ + 21891 LUT4 8F00 ((AB)+c)D + 21892 LUT4 008F ((AB)+c)d + 21893 LUT3 0D c/Ab\ + 21894 LUT4 8F00 ((AB)+c)D + 21895 LUT4 004F ((aB)+c)d + 21896 LUT3 07 c/AB\ + 21897 LUT4 8F00 ((AB)+c)D + 21898 LUT4 008F ((AB)+c)d + 21899 LUT3 0D c/Ab\ + 21900 LUT3 8F (AB)+c + 21901 LUT2 8 AB + 21902 LUT2 8 AB + 21903 LUT2 8 AB + 21904 LUT3 E0 C/ab\ + 21905 LUT3 40 aBC + 21906 LUT2 8 AB + 21907 LUT2 8 AB + 21908 LUT4 4000 aBCD + 21909 LUT3 80 ABC + 21910 LUT3 AC c?A:B + 21911 LUT3 CA C?A:B + 21912 LUT3 CA C?A:B + 21913 LUT3 CA C?A:B + 21914 LUT3 CA C?A:B + 21915 LUT3 CA C?A:B + 21916 LUT3 01 abc + 21917 LUT2 6 A^B + 21918 LUT4 333A DC?A:b:b:b + 21919 LUT4 3500 D(c?b:a) + 21920 LUT3 70 C/AB\ + 21921 LUT4 F53F DC?1:a:b:1 + 21922 LUT3 70 C/AB\ + 21923 LUT4 F3F5 DC?a:b:1:1 + 21924 LUT4 F400 ((aB)+C)D + 21925 LUT4 3500 D(c?b:a) + 21926 LUT3 70 C/AB\ + 21927 LUT4 F3F5 DC?a:b:1:1 + 21928 LUT3 70 C/AB\ + 21929 LUT4 F3F5 DC?a:b:1:1 + 21930 LUT4 CA00 D(C?A:B) + 21931 LUT2 4 aB + 21932 LUT4 F4FF (aB)+C+d + 21933 LUT4 0503 DC?b:a:0:0 + 21934 LUT2 8 AB + 21935 LUT4 0777 /AB\(d+c) + 21936 LUT2 1 ab + 21937 LUT3 53 C?b:a + 21938 LUT4 0B00 cD/aB\ + 21939 LUT3 D0 C/Ab\ + 21940 LUT4 EF00 ((/ab\)+c)D + 21941 LUT3 70 C/AB\ + 21942 LUT4 8000 ABCD + 21943 LUT3 80 ABC + 21944 LUT2 4 aB + 21945 LUT2 1 ab + 21946 LUT2 8 AB + 21947 LUT4 0001 abcd + 21948 LUT4 0001 abcd + 21949 LUT4 8000 ABCD + 21950 LUT3 10 abC + 21951 LUT2 8 AB + 21952 LUT2 8 AB + 21953 LUT4 3500 D(c?b:a) + 21954 LUT4 7000 CD/AB\ + 21955 LUT4 133F BD?1:c:/AC\:0 + 21956 LUT2 4 aB + 21957 LUT4 1000 abCD + 21958 LUT3 07 c/AB\ + 21959 LUT2 1 ab + 21960 LUT3 40 aBC + 21961 LUT4 000B cd/aB\ + 21962 LUT4 0D00 cD/Ab\ + 21963 LUT4 0777 /AB\(d+c) + 21964 LUT4 EF00 ((/ab\)+c)D + 21965 LUT4 8F00 ((AB)+c)D + 21966 LUT4 007F ((/AB\)+c)d + 21967 LUT3 40 aBC + 21968 LUT4 4000 aBCD + 21969 LUT2 4 aB + 21970 LUT4 E000 CD/ab\ + 21971 LUT3 80 ABC + 21972 LUT2 8 AB + 21973 LUT2 1 ab + 21974 LUT2 4 aB + 21975 LUT2 8 AB + 21976 LUT2 1 ab + 21977 LUT2 4 aB + 21978 LUT3 01 abc + 21979 LUT4 4000 aBCD + 21980 LUT4 00F8 ((AB)+C)d + 21981 LUT2 8 AB + 21982 LUT2 8 AB + 21983 LUT2 1 ab + 21984 LUT4 8000 ABCD + 21985 LUT3 80 ABC + 21986 LUT2 8 AB + 21987 LUT4 8000 ABCD + 21988 LUT2 1 ab + 21989 LUT4 F100 ((ab)+C)D + 21990 LUT4 A300 D(C?b:A) + 21991 LUT3 CA C?A:B + 21992 LUT3 CA C?A:B + 21993 LUT3 35 c?b:a + 21994 LUT4 BBB0 /aB\(D+C) + 21995 LUT3 10 abC + 21996 LUT3 80 ABC + 21997 LUT2 8 AB + 21998 LUT2 1 ab + 21999 LUT4 1000 abCD + 22000 LUT4 8000 ABCD + 22001 LUT3 07 c/AB\ + 22002 LUT3 80 ABC + 22003 LUT3 35 c?b:a + 22004 LUT4 BBB0 /aB\(D+C) + 22005 LUT3 CA C?A:B + 22006 LUT3 35 c?b:a + 22007 LUT3 35 c?b:a + 22008 LUT4 BBB0 /aB\(D+C) + 22009 LUT4 110F D?c:ab + 22010 LUT2 4 aB + 22011 LUT3 35 c?b:a + 22012 LUT3 CA C?A:B + 22013 LUT3 35 c?b:a + 22014 LUT3 35 c?b:a + 22015 LUT4 3500 D(c?b:a) + 22016 LUT4 BBB0 /aB\(D+C) + 22017 LUT4 BBB0 /aB\(D+C) + 22018 LUT3 CA C?A:B + 22019 LUT3 CA C?A:B + 22020 LUT3 CA C?A:B + 22021 LUT3 35 c?b:a + 22022 LUT3 35 c?b:a + 22023 LUT3 CA C?A:B + 22024 LUT3 35 c?b:a + 22025 LUT3 35 c?b:a + 22026 LUT3 CA C?A:B + 22027 LUT3 CA C?A:B + 22028 LUT3 35 c?b:a + 22029 LUT3 35 c?b:a + 22030 LUT3 CA C?A:B + 22031 LUT3 35 c?b:a + 22032 LUT3 35 c?b:a + 22033 LUT4 7077 /AB\(d+C) + 22034 LUT3 90 C(a^B) + 22035 LUT3 B0 C/aB\ + 22036 LUT3 60 C(A^B) + 22037 LUT3 4F (aB)+c + 22038 LUT3 53 C?b:a + 22039 LUT4 0B00 cD/aB\ + 22040 LUT3 D0 C/Ab\ + 22041 LUT3 70 C/AB\ + 22042 LUT4 0777 /AB\(d+c) + 22043 LUT2 4 aB + 22044 LUT4 CEC0 BD?0:C:Ac:1 + 22045 LUT4 0C0A DC?A:B:0:0 + 22046 LUT2 1 ab + 22047 LUT3 35 c?b:a + 22048 LUT4 CDD0 DC?0:/Ab\:/Ab\:B + 22049 LUT2 8 AB + 22050 LUT4 4000 aBCD + 22051 LUT3 07 c/AB\ + 22052 LUT4 3500 D(c?b:a) + 22053 LUT3 CA C?A:B + 22054 LUT4 11F0 D?C:ab + 22055 LUT2 1 ab + 22056 LUT3 35 c?b:a + 22057 LUT3 CA C?A:B + 22058 LUT3 35 c?b:a + 22059 LUT3 35 c?b:a + 22060 LUT4 CA00 D(C?A:B) + 22061 LUT3 CA C?A:B + 22062 LUT3 CA C?A:B + 22063 LUT3 35 c?b:a + 22064 LUT3 35 c?b:a + 22065 LUT3 CA C?A:B + 22066 LUT3 35 c?b:a + 22067 LUT3 35 c?b:a + 22068 LUT3 CA C?A:B + 22069 LUT3 CA C?A:B + 22070 LUT3 CA C?A:B + 22071 LUT3 35 c?b:a + 22072 LUT3 35 c?b:a + 22073 LUT3 CA C?A:B + 22074 LUT3 35 c?b:a + 22075 LUT3 35 c?b:a + 22076 LUT3 CA C?A:B + 22077 LUT3 CA C?A:B + 22078 LUT3 35 c?b:a + 22079 LUT3 35 c?b:a + 22080 LUT3 35 c?b:a + 22081 LUT3 CA C?A:B + 22082 LUT3 C5 C?a:B + 22083 LUT3 0B c/aB\ + 22084 LUT2 8 AB + 22085 LUT2 4 aB + 22086 LUT3 10 abC + 22087 LUT2 4 aB + 22088 LUT2 1 ab + 22089 LUT2 4 aB + 22090 LUT2 8 AB + 22091 LUT2 4 aB + 22092 LUT2 4 aB + 22093 LUT2 4 aB + 22094 LUT3 53 C?b:a + 22095 LUT2 8 AB + 22096 LUT3 70 C/AB\ + 22097 LUT3 70 C/AB\ + 22098 LUT4 0777 /AB\(d+c) + 22099 LUT2 4 aB + 22100 LUT4 0305 DC?a:b:0:0 + 22101 LUT4 008F ((AB)+c)d + 22102 LUT2 8 AB + 22103 LUT4 4000 aBCD + 22104 LUT4 1000 abCD + 22105 LUT4 EEF0 D?C:/ab\ + 22106 LUT3 CA C?A:B + 22107 LUT3 CA C?A:B + 22108 LUT3 CA C?A:B + 22109 LUT3 CA C?A:B + 22110 LUT3 CA C?A:B + 22111 LUT3 CA C?A:B + 22112 LUT3 C5 C?a:B + 22113 LUT3 35 c?b:a + 22114 LUT3 0B c/aB\ + 22115 LUT2 4 aB + 22116 LUT3 CA C?A:B + 22117 LUT3 CA C?A:B + 22118 LUT3 CA C?A:B + 22119 LUT4 3A00 D(c?b:A) + 22120 LUT3 35 c?b:a + 22121 LUT3 AC c?A:B + 22122 LUT3 0B c/aB\ + 22123 LUT3 53 C?b:a + 22124 LUT3 10 abC + 22125 LUT3 0E c/ab\ + 22126 LUT3 CA C?A:B + 22127 LUT3 CA C?A:B + 22128 LUT3 CA C?A:B + 22129 LUT3 CA C?A:B + 22130 LUT3 CA C?A:B + 22131 LUT3 C5 C?a:B + 22132 LUT3 35 c?b:a + 22133 LUT3 35 c?b:a + 22134 LUT3 0B c/aB\ + 22135 LUT4 A300 D(C?b:A) + 22136 LUT3 CA C?A:B + 22137 LUT3 CA C?A:B + 22138 LUT3 CA C?A:B + 22139 LUT3 C5 C?a:B + 22140 LUT3 35 c?b:a + 22141 LUT3 CA C?A:B + 22142 LUT4 0700 cD/AB\ + 22143 LUT4 1000 abCD + 22144 LUT3 70 C/AB\ + 22145 LUT3 70 C/AB\ + 22146 LUT4 0777 /AB\(d+c) + 22147 LUT4 0305 DC?a:b:0:0 + 22148 LUT4 008F ((AB)+c)d + 22149 LUT4 8F00 ((AB)+c)D + 22150 LUT3 E0 C/ab\ + 22151 LUT3 80 ABC + 22152 LUT3 4F (aB)+c + 22153 LUT3 53 C?b:a + 22154 LUT4 EF00 ((/ab\)+c)D + 22155 LUT3 70 C/AB\ + 22156 LUT4 0700 cD/AB\ + 22157 LUT4 8F00 ((AB)+c)D + 22158 LUT3 70 C/AB\ + 22159 LUT4 0777 /AB\(d+c) + 22160 LUT3 CA C?A:B + 22161 LUT4 008F ((AB)+c)d + 22162 LUT4 007F ((/AB\)+c)d + 22163 LUT3 40 aBC + 22164 LUT4 00BF ((/aB\)+c)d + 22165 LUT4 EEF0 D?C:/ab\ + 22166 LUT3 CA C?A:B + 22167 LUT3 CA C?A:B + 22168 LUT3 CA C?A:B + 22169 LUT3 35 c?b:a + 22170 LUT3 35 c?b:a + 22171 LUT3 0B c/aB\ + 22172 LUT2 4 aB + 22173 LUT3 CA C?A:B + 22174 LUT4 AC00 D(c?A:B) + 22175 LUT2 4 aB + 22176 LUT3 53 C?b:a + 22177 LUT4 0700 cD/AB\ + 22178 LUT4 3500 D(c?b:a) + 22179 LUT3 70 C/AB\ + 22180 LUT4 0777 /AB\(d+c) + 22181 LUT2 8 AB + 22182 LUT4 1000 abCD + 22183 LUT4 0D00 cD/Ab\ + 22184 LUT3 CA C?A:B + 22185 LUT3 CA C?A:B + 22186 LUT3 CA C?A:B + 22187 LUT3 CA C?A:B + 22188 LUT3 CA C?A:B + 22189 LUT3 CA C?A:B + 22190 LUT3 CA C?A:B + 22191 LUT3 35 c?b:a + 22192 LUT3 35 c?b:a + 22193 LUT3 0B c/aB\ + 22194 LUT2 4 aB + 22195 LUT4 0700 cD/AB\ + 22196 LUT4 3500 D(c?b:a) + 22197 LUT4 7000 CD/AB\ + 22198 LUT4 133F BD?1:c:/AC\:0 + 22199 LUT3 B0 C/aB\ + 22200 LUT4 0777 /AB\(d+c) + 22201 LUT2 8 AB + 22202 LUT4 1000 abCD + 22203 LUT4 3500 D(c?b:a) + 22204 LUT3 0E c/ab\ + 22205 LUT3 AC c?A:B + 22206 LUT4 5300 D(C?b:a) + 22207 LUT3 CA C?A:B + 22208 LUT3 CA C?A:B + 22209 LUT3 CA C?A:B + 22210 LUT3 35 c?b:a + 22211 LUT3 35 c?b:a + 22212 LUT3 0B c/aB\ + 22213 LUT3 70 C/AB\ + 22214 LUT4 0700 cD/AB\ + 22215 LUT4 0305 DC?a:b:0:0 + 22216 LUT4 008F ((AB)+c)d + 22217 LUT4 0777 /AB\(d+c) + 22218 LUT4 00F4 ((aB)+C)d + 22219 LUT4 00F8 ((AB)+C)d + 22220 LUT4 3500 D(c?b:a) + 22221 LUT3 CA C?A:B + 22222 LUT3 AC c?A:B + 22223 LUT3 AC c?A:B + 22224 LUT3 CA C?A:B + 22225 LUT3 CA C?A:B + 22226 LUT3 CA C?A:B + 22227 LUT3 35 c?b:a + 22228 LUT3 35 c?b:a + 22229 LUT3 0B c/aB\ + 22230 LUT3 07 c/AB\ + 22231 LUT4 7F00 ((/AB\)+c)D + 22232 LUT2 1 ab + 22233 LUT2 1 ab + 22234 LUT4 0001 abcd + 22235 LUT4 B000 CD/aB\ + 22236 LUT2 8 AB + 22237 LUT4 0D00 cD/Ab\ + 22238 LUT3 80 ABC + 22239 LUT4 0777 /AB\(d+c) + 22240 LUT4 7770 /AB\(D+C) + 22241 LUT3 0D c/Ab\ + 22242 LUT3 40 aBC + 22243 LUT4 0D00 cD/Ab\ + 22244 LUT2 4 aB + 22245 LUT2 1 ab + 22246 LUT2 4 aB + 22247 LUT3 CA C?A:B + 22248 LUT3 CA C?A:B + 22249 LUT3 CA C?A:B + 22250 LUT3 35 c?b:a + 22251 LUT3 35 c?b:a + 22252 LUT3 0B c/aB\ + 22253 LUT4 0BBB /aB\(d+c) + 22254 LUT4 0D00 cD/Ab\ + 22255 LUT4 0777 /AB\(d+c) + 22256 LUT4 1000 abCD + 22257 LUT4 0D00 cD/Ab\ + 22258 LUT4 00F1 ((ab)+C)d + 22259 LUT3 CA C?A:B + 22260 LUT3 CA C?A:B + 22261 LUT3 35 c?b:a + 22262 LUT3 35 c?b:a + 22263 LUT3 0B c/aB\ + 22264 LUT4 3500 D(c?b:a) + 22265 LUT4 00BF ((/aB\)+c)d + 22266 LUT2 8 AB + 22267 LUT2 8 AB + 22268 LUT4 1000 abCD + 22269 LUT4 0BBB /aB\(d+c) + 22270 LUT4 0D00 cD/Ab\ + 22271 LUT4 0777 /AB\(d+c) + 22272 LUT4 00F8 ((AB)+C)d + 22273 LUT3 CA C?A:B + 22274 LUT3 AC c?A:B + 22275 LUT3 CA C?A:B + 22276 LUT3 CA C?A:B + 22277 LUT3 35 c?b:a + 22278 LUT3 35 c?b:a + 22279 LUT3 0B c/aB\ + 22280 LUT4 0007 cd/AB\ + 22281 LUT4 3BB0 DC?0:/aB\:/aB\:b + 22282 LUT3 0D c/Ab\ + 22283 LUT4 EC0C BD?0:c:AC:1 + 22284 LUT4 0D00 cD/Ab\ + 22285 LUT4 0777 /AB\(d+c) + 22286 LUT2 8 AB + 22287 LUT3 40 aBC + 22288 LUT4 3500 D(c?b:a) + 22289 LUT3 AC c?A:B + 22290 LUT3 CA C?A:B + 22291 LUT3 CA C?A:B + 22292 LUT3 35 c?b:a + 22293 LUT3 35 c?b:a + 22294 LUT3 0B c/aB\ + 22295 LUT3 B0 C/aB\ + 22296 LUT4 0007 cd/AB\ + 22297 LUT4 8F23 BD?/aC\:0:c:/aC\ + 22298 LUT3 07 c/AB\ + 22299 LUT4 0D00 cD/Ab\ + 22300 LUT4 0777 /AB\(d+c) + 22301 LUT4 0F37 BC?1:/Ad\:d:0 + 22302 LUT4 1000 abCD + 22303 LUT4 3500 D(c?b:a) + 22304 LUT3 AC c?A:B + 22305 LUT3 CA C?A:B + 22306 LUT3 CA C?A:B + 22307 LUT3 35 c?b:a + 22308 LUT3 35 c?b:a + 22309 LUT3 0B c/aB\ + 22310 LUT4 EF00 ((/ab\)+c)D + 22311 LUT4 0F37 BC?1:/Ad\:d:0 + 22312 LUT2 8 AB + 22313 LUT2 8 AB + 22314 LUT4 0100 abcD + 22315 LUT3 70 C/AB\ + 22316 LUT4 0D00 cD/Ab\ + 22317 LUT4 7077 /AB\(d+C) + 22318 LUT3 CA C?A:B + 22319 LUT3 CA C?A:B + 22320 LUT3 35 c?b:a + 22321 LUT3 35 c?b:a + 22322 LUT3 0B c/aB\ + 22323 LUT3 B0 C/aB\ + 22324 LUT4 7000 CD/AB\ + 22325 LUT4 00F1 ((ab)+C)d + 22326 LUT3 0D c/Ab\ + 22327 LUT2 8 AB + 22328 LUT3 D0 C/Ab\ + 22329 LUT4 B000 CD/aB\ + 22330 LUT4 00F1 ((ab)+C)d + 22331 LUT2 8 AB + 22332 LUT4 0D00 cD/Ab\ + 22333 LUT4 7077 /AB\(d+C) + 22334 LUT4 0100 abcD + 22335 LUT4 0D00 cD/Ab\ + 22336 LUT4 00F4 ((aB)+C)d + 22337 LUT3 0E c/ab\ + 22338 LUT3 CA C?A:B + 22339 LUT3 CA C?A:B + 22340 LUT3 35 c?b:a + 22341 LUT3 35 c?b:a + 22342 LUT3 0B c/aB\ + 22343 LUT4 3500 D(c?b:a) + 22344 LUT2 8 AB + 22345 LUT2 4 aB + 22346 LUT4 3500 D(c?b:a) + 22347 LUT4 D000 CD/Ab\ + 22348 LUT4 0BBB /aB\(d+c) + 22349 LUT3 D0 C/Ab\ + 22350 LUT4 7077 /AB\(d+C) + 22351 LUT3 07 c/AB\ + 22352 LUT2 8 AB + 22353 LUT4 3500 D(c?b:a) + 22354 LUT3 CA C?A:B + 22355 LUT3 CA C?A:B + 22356 LUT3 CA C?A:B + 22357 LUT3 35 c?b:a + 22358 LUT3 35 c?b:a + 22359 LUT3 0B c/aB\ + 22360 LUT4 0700 cD/AB\ + 22361 LUT3 D0 C/Ab\ + 22362 LUT4 7077 /AB\(d+C) + 22363 LUT4 233F BD?1:c:/aC\:0 + 22364 LUT4 7F00 ((/AB\)+c)D + 22365 LUT2 1 ab + 22366 LUT2 1 ab + 22367 LUT4 0001 abcd + 22368 LUT2 1 ab + 22369 LUT4 F400 ((aB)+C)D + 22370 LUT4 0305 DC?a:b:0:0 + 22371 LUT3 CA C?A:B + 22372 LUT3 35 c?b:a + 22373 LUT3 35 c?b:a + 22374 LUT3 0B c/aB\ + 22375 LUT3 E0 C/ab\ + 22376 LUT3 0B c/aB\ + 22377 LUT2 4 aB + 22378 LUT2 8 AB + 22379 LUT3 70 C/AB\ + 22380 LUT3 D0 C/Ab\ + 22381 LUT4 7077 /AB\(d+C) + 22382 LUT4 EC0C BD?0:c:AC:1 + 22383 LUT4 F400 ((aB)+C)D + 22384 LUT2 1 ab + 22385 LUT4 000B cd/aB\ + 22386 LUT4 0C0A DC?A:B:0:0 + 22387 LUT3 CA C?A:B + 22388 LUT3 35 c?b:a + 22389 LUT3 35 c?b:a + 22390 LUT3 0B c/aB\ + 22391 LUT4 00BF ((/aB\)+c)d + 22392 LUT4 7000 CD/AB\ + 22393 LUT3 E0 C/ab\ + 22394 LUT3 D0 C/Ab\ + 22395 LUT4 7077 /AB\(d+C) + 22396 LUT4 F400 ((aB)+C)D + 22397 LUT4 0305 DC?a:b:0:0 + 22398 LUT3 CA C?A:B + 22399 LUT3 35 c?b:a + 22400 LUT3 35 c?b:a + 22401 LUT3 0B c/aB\ + 22402 LUT3 D0 C/Ab\ + 22403 LUT3 70 C/AB\ + 22404 LUT3 D0 C/Ab\ + 22405 LUT4 7077 /AB\(d+C) + 22406 LUT2 1 ab + 22407 LUT4 0305 DC?a:b:0:0 + 22408 LUT3 CA C?A:B + 22409 LUT3 CA C?A:B + 22410 LUT3 35 c?b:a + 22411 LUT3 35 c?b:a + 22412 LUT3 0B c/aB\ + 22413 LUT4 F400 ((aB)+C)D + 22414 LUT4 0305 DC?a:b:0:0 + 22415 LUT3 CA C?A:B + 22416 LUT3 35 c?b:a + 22417 LUT3 35 c?b:a + 22418 LUT3 0B c/aB\ + 22419 LUT3 70 C/AB\ + 22420 LUT2 4 aB + 22421 LUT4 7000 CD/AB\ + 22422 LUT3 D0 C/Ab\ + 22423 LUT4 7077 /AB\(d+C) + 22424 LUT2 8 AB + 22425 LUT3 70 C/AB\ + 22426 LUT3 D0 C/Ab\ + 22427 LUT4 7077 /AB\(d+C) + 22428 LUT3 0D c/Ab\ + 22429 LUT3 35 c?b:a + 22430 LUT2 4 aB + 22431 LUT4 F400 ((aB)+C)D + 22432 LUT4 0305 DC?a:b:0:0 + 22433 LUT3 CA C?A:B + 22434 LUT3 35 c?b:a + 22435 LUT3 35 c?b:a + 22436 LUT3 0B c/aB\ + 22437 LUT3 70 C/AB\ + 22438 LUT2 8 AB + 22439 LUT3 D0 C/Ab\ + 22440 LUT4 7077 /AB\(d+C) + 22441 LUT4 0305 DC?a:b:0:0 + 22442 LUT4 00F8 ((AB)+C)d + 22443 LUT4 3500 D(c?b:a) + 22444 LUT3 CA C?A:B + 22445 LUT3 CA C?A:B + 22446 LUT3 35 c?b:a + 22447 LUT3 35 c?b:a + 22448 LUT3 0B c/aB\ + 22449 LUT4 BF00 ((/aB\)+c)D + 22450 LUT3 70 C/AB\ + 22451 LUT3 D0 C/Ab\ + 22452 LUT4 7077 /AB\(d+C) + 22453 LUT4 CEC0 BD?0:C:Ac:1 + 22454 LUT3 07 c/AB\ + 22455 LUT4 EC0E DC?/ab\:B:0:/ab\ + 22456 LUT3 0E c/ab\ + 22457 LUT3 40 aBC + 22458 LUT4 3500 D(c?b:a) + 22459 LUT3 CA C?A:B + 22460 LUT3 CA C?A:B + 22461 LUT3 35 c?b:a + 22462 LUT3 35 c?b:a + 22463 LUT3 0B c/aB\ + 22464 LUT2 4 aB + 22465 LUT4 1000 abCD + 22466 LUT4 0001 abcd + 22467 LUT2 1 ab + 22468 LUT4 7000 CD/AB\ + 22469 LUT4 B0BB /aB\(d+C) + 22470 LUT4 7077 /AB\(d+C) + 22471 LUT4 0305 DC?a:b:0:0 + 22472 LUT4 00F4 ((aB)+C)d + 22473 LUT4 3500 D(c?b:a) + 22474 LUT4 00F4 ((aB)+C)d + 22475 LUT3 CA C?A:B + 22476 LUT3 CA C?A:B + 22477 LUT3 CA C?A:B + 22478 LUT3 35 c?b:a + 22479 LUT3 35 c?b:a + 22480 LUT3 0B c/aB\ + 22481 LUT4 0700 cD/AB\ + 22482 LUT4 3500 D(c?b:a) + 22483 LUT4 7077 /AB\(d+C) + 22484 LUT4 7077 /AB\(d+C) + 22485 LUT3 0D c/Ab\ + 22486 LUT4 0305 DC?a:b:0:0 + 22487 LUT3 CA C?A:B + 22488 LUT3 CA C?A:B + 22489 LUT3 35 c?b:a + 22490 LUT3 35 c?b:a + 22491 LUT3 0B c/aB\ + 22492 LUT4 00EF ((/ab\)+c)d + 22493 LUT2 8 AB + 22494 LUT4 D000 CD/Ab\ + 22495 LUT4 7077 /AB\(d+C) + 22496 LUT4 7077 /AB\(d+C) + 22497 LUT4 0305 DC?a:b:0:0 + 22498 LUT4 00F4 ((aB)+C)d + 22499 LUT3 CA C?A:B + 22500 LUT3 CA C?A:B + 22501 LUT3 CA C?A:B + 22502 LUT3 35 c?b:a + 22503 LUT3 35 c?b:a + 22504 LUT3 0B c/aB\ + 22505 LUT4 7077 /AB\(d+C) + 22506 LUT3 35 c?b:a + 22507 LUT4 00F4 ((aB)+C)d + 22508 LUT3 CA C?A:B + 22509 LUT3 CA C?A:B + 22510 LUT3 CA C?A:B + 22511 LUT3 35 c?b:a + 22512 LUT3 35 c?b:a + 22513 LUT3 0B c/aB\ + 22514 LUT4 B000 CD/aB\ + 22515 LUT4 D000 CD/Ab\ + 22516 LUT4 0BBB /aB\(d+c) + 22517 LUT4 7077 /AB\(d+C) + 22518 LUT3 CA C?A:B + 22519 LUT4 0100 abcD + 22520 LUT4 0007 cd/AB\ + 22521 LUT4 0C0A DC?A:B:0:0 + 22522 LUT3 CA C?A:B + 22523 LUT3 35 c?b:a + 22524 LUT4 0FEE D?/ab\:c + 22525 LUT2 4 aB + 22526 LUT4 00F4 ((aB)+C)d + 22527 LUT4 F2FF (Ab)+C+d + 22528 LUT4 00F1 ((ab)+C)d + 22529 LUT3 CA C?A:B + 22530 LUT4 F0EE D?/ab\:C + 22531 LUT2 8 AB + 22532 LUT4 030A DC?A:b:0:0 + 22533 LUT4 0305 DC?a:b:0:0 + 22534 LUT2 4 aB + 22535 LUT4 B000 CD/aB\ + 22536 LUT4 0007 cd/AB\ + 22537 LUT4 EC0E DC?/ab\:B:0:/ab\ + 22538 LUT4 4000 aBCD + 22539 LUT4 0B00 cD/aB\ + 22540 LUT2 4 aB + 22541 LUT4 7000 CD/AB\ + 22542 LUT4 B0BB /aB\(d+C) + 22543 LUT4 7077 /AB\(d+C) + 22544 LUT4 E0EE /ab\(d+C) + 22545 LUT4 001F ((ab)+c)d + 22546 LUT4 004F ((aB)+c)d + 22547 LUT4 0E00 cD/ab\ + 22548 LUT4 0007 cd/AB\ + 22549 LUT4 3BB0 DC?0:/aB\:/aB\:b + 22550 LUT3 0D c/Ab\ + 22551 LUT4 D000 CD/Ab\ + 22552 LUT4 D000 CD/Ab\ + 22553 LUT4 0BBB /aB\(d+c) + 22554 LUT4 7077 /AB\(d+C) + 22555 LUT4 0C0A DC?A:B:0:0 + 22556 LUT4 00F1 ((ab)+C)d + 22557 LUT4 F0EE D?/ab\:C + 22558 LUT2 8 AB + 22559 LUT4 0A03 DC?b:A:0:0 + 22560 LUT4 F0EE D?/ab\:C + 22561 LUT2 1 ab + 22562 LUT4 3500 D(c?b:a) + 22563 LUT3 07 c/AB\ + 22564 LUT4 B000 CD/aB\ + 22565 LUT4 D000 CD/Ab\ + 22566 LUT3 70 C/AB\ + 22567 LUT3 D0 C/Ab\ + 22568 LUT4 7077 /AB\(d+C) + 22569 LUT4 F400 ((aB)+C)D + 22570 LUT4 0503 DC?b:a:0:0 + 22571 LUT3 0D c/Ab\ + 22572 LUT4 050C DC?B:a:0:0 + 22573 LUT4 0FEE D?/ab\:c + 22574 LUT2 4 aB + 22575 LUT3 80 ABC + 22576 LUT2 4 aB + 22577 LUT3 8F (AB)+c + 22578 LUT3 0D c/Ab\ + 22579 LUT3 96 A^B^C + 22580 LUT4 4BB4 (aB)^c^d + 22581 LUT4 B44B (aB)^c^D + 22582 LUT4 B44B (aB)^c^D + 22583 LUT2 4 aB + 22584 LUT4 C6F5 AB?d:C^D:1:C + 22585 LUT4 C6F5 AB?d:C^D:1:C + 22586 LUT4 C6F5 AB?d:C^D:1:C + 22587 LUT4 9669 A^B^c^D + 22588 LUT3 4B (aB)^c + 22589 LUT4 C6F5 AB?d:C^D:1:C + 22590 LUT3 B4 (aB)^C + 22591 LUT4 C6F5 AB?d:C^D:1:C + 22592 LUT4 C6F5 AB?d:C^D:1:C + 22593 LUT4 390A AB?D:c^D:0:c + 22594 LUT4 6996 A^B^c^d + 22595 LUT3 B4 (aB)^C + 22596 LUT4 390A AB?D:c^D:0:c + 22597 LUT4 4BB4 (aB)^c^d + 22598 LUT4 C6F5 AB?d:C^D:1:C + 22599 LUT4 390A AB?D:c^D:0:c + 22600 LUT4 C6F5 AB?d:C^D:1:C + 22601 LUT4 2DDD AC?1:B:d:B^D + 22602 LUT3 40 aBC + 22603 LUT3 80 ABC + 22604 LUT3 80 ABC + 22605 LUT3 96 A^B^C + 22606 LUT4 4BB4 (aB)^c^d + 22607 LUT4 9669 A^B^c^D + 22608 LUT4 00BF ((/aB\)+c)d + 22609 LUT4 B0BB /aB\(d+C) + 22610 LUT4 390A AB?D:c^D:0:c + 22611 LUT4 C6F5 AB?d:C^D:1:C + 22612 LUT4 C6F5 AB?d:C^D:1:C + 22613 LUT4 B44B (aB)^c^D + 22614 LUT4 C6F5 AB?d:C^D:1:C + 22615 LUT4 C6F5 AB?d:C^D:1:C + 22616 LUT4 6996 A^B^c^d + 22617 LUT4 4BB4 (aB)^c^d + 22618 LUT4 C6F5 AB?d:C^D:1:C + 22619 LUT4 390A AB?D:c^D:0:c + 22620 LUT4 C6F5 AB?d:C^D:1:C + 22621 LUT4 C6F5 AB?d:C^D:1:C + 22622 LUT4 C6F5 AB?d:C^D:1:C + 22623 LUT4 B44B (aB)^c^D + 22624 LUT3 4B (aB)^c + 22625 LUT4 C6F5 AB?d:C^D:1:C + 22626 LUT4 C6F5 AB?d:C^D:1:C + 22627 LUT2 8 AB + 22628 LUT3 80 ABC + 22629 LUT3 8F (AB)+c + 22630 LUT4 0BBB /aB\(d+c) + 22631 LUT4 2DDD AC?1:B:d:B^D + 22632 LUT3 4B (aB)^c + 22633 LUT4 6996 A^B^c^d + 22634 LUT4 9669 A^B^c^D + 22635 LUT3 69 A^B^c + 22636 LUT4 C6F5 AB?d:C^D:1:C + 22637 LUT4 C6F5 AB?d:C^D:1:C + 22638 LUT4 C6F5 AB?d:C^D:1:C + 22639 LUT3 69 A^B^c + 22640 LUT4 C6F5 AB?d:C^D:1:C + 22641 LUT4 390A AB?D:c^D:0:c + 22642 LUT4 C6F5 AB?d:C^D:1:C + 22643 LUT4 390A AB?D:c^D:0:c + 22644 LUT4 390A AB?D:c^D:0:c + 22645 LUT3 96 A^B^C + 22646 LUT4 C6F5 AB?d:C^D:1:C + 22647 LUT4 C6F5 AB?d:C^D:1:C + 22648 LUT4 C6F5 AB?d:C^D:1:C + 22649 LUT4 4BB4 (aB)^c^d + 22650 LUT4 C6F5 AB?d:C^D:1:C + 22651 LUT4 C6F5 AB?d:C^D:1:C + 22652 LUT4 390A AB?D:c^D:0:c + 22653 LUT3 8F (AB)+c + 22654 LUT3 0D c/Ab\ + 22655 LUT4 C6F5 AB?d:C^D:1:C + 22656 LUT4 C6F5 AB?d:C^D:1:C + 22657 LUT3 B4 (aB)^C + 22658 LUT4 C6F5 AB?d:C^D:1:C + 22659 LUT4 C6F5 AB?d:C^D:1:C + 22660 LUT4 C6F5 AB?d:C^D:1:C + 22661 LUT4 9669 A^B^c^D + 22662 LUT4 6996 A^B^c^d + 22663 LUT4 C6F5 AB?d:C^D:1:C + 22664 LUT4 C6F5 AB?d:C^D:1:C + 22665 LUT4 C6F5 AB?d:C^D:1:C + 22666 LUT4 C6F5 AB?d:C^D:1:C + 22667 LUT3 B4 (aB)^C + 22668 LUT4 C6F5 AB?d:C^D:1:C + 22669 LUT4 C6F5 AB?d:C^D:1:C + 22670 LUT4 C6F5 AB?d:C^D:1:C + 22671 LUT4 8700 AD?0:0:c:b^C + 22672 LUT4 C6F5 AB?d:C^D:1:C + 22673 LUT2 4 aB + 22674 LUT4 C6F5 AB?d:C^D:1:C + 22675 LUT4 C6F5 AB?d:C^D:1:C + 22676 LUT4 C6F5 AB?d:C^D:1:C + 22677 LUT4 C6F5 AB?d:C^D:1:C + 22678 LUT3 B4 (aB)^C + 22679 LUT4 C6F5 AB?d:C^D:1:C + 22680 LUT4 C6F5 AB?d:C^D:1:C + 22681 LUT4 390A AB?D:c^D:0:c + 22682 LUT4 6996 A^B^c^d + 22683 LUT4 4BB4 (aB)^c^d + 22684 LUT4 390A AB?D:c^D:0:c + 22685 LUT4 C6F5 AB?d:C^D:1:C + 22686 LUT4 C6F5 AB?d:C^D:1:C + 22687 LUT4 C6F5 AB?d:C^D:1:C + 22688 LUT4 C6F5 AB?d:C^D:1:C + 22689 LUT4 6996 A^B^c^d + 22690 LUT4 6996 A^B^c^d + 22691 LUT3 B4 (aB)^C + 22692 LUT4 C6F5 AB?d:C^D:1:C + 22693 LUT4 B44B (aB)^c^D + 22694 LUT4 390A AB?D:c^D:0:c + 22695 LUT4 C6F5 AB?d:C^D:1:C + 22696 LUT4 C6F5 AB?d:C^D:1:C + 22697 LUT4 C6F5 AB?d:C^D:1:C + 22698 LUT4 B44B (aB)^c^D + 22699 LUT3 4B (aB)^c + 22700 LUT4 C6F5 AB?d:C^D:1:C + 22701 LUT4 C6F5 AB?d:C^D:1:C + 22702 LUT4 4BB4 (aB)^c^d + 22703 LUT4 B44B (aB)^c^D + 22704 LUT4 390A AB?D:c^D:0:c + 22705 LUT2 4 aB + 22706 LUT4 C6F5 AB?d:C^D:1:C + 22707 LUT4 C6F5 AB?d:C^D:1:C + 22708 LUT4 2DDD AC?1:B:d:B^D + 22709 LUT3 8F (AB)+c + 22710 LUT3 07 c/AB\ + 22711 LUT2 9 a^B + 22712 LUT4 6996 A^B^c^d + 22713 LUT3 96 A^B^C + 22714 LUT4 F807 (c/AB\)^D + 22715 LUT4 C6F5 AB?d:C^D:1:C + 22716 LUT2 4 aB + 22717 LUT4 B0BB /aB\(d+C) + 22718 LUT4 C6F5 AB?d:C^D:1:C + 22719 LUT4 C6F5 AB?d:C^D:1:C + 22720 LUT4 C6F5 AB?d:C^D:1:C + 22721 LUT4 C6F5 AB?d:C^D:1:C + 22722 LUT4 C6F5 AB?d:C^D:1:C + 22723 LUT4 9669 A^B^c^D + 22724 LUT4 B44B (aB)^c^D + 22725 LUT4 C6F5 AB?d:C^D:1:C + 22726 LUT4 390A AB?D:c^D:0:c + 22727 LUT3 4B (aB)^c + 22728 LUT4 C6F5 AB?d:C^D:1:C + 22729 LUT4 C6F5 AB?d:C^D:1:C + 22730 LUT4 C6F5 AB?d:C^D:1:C + 22731 LUT4 8700 AD?0:0:c:b^C + 22732 LUT4 B44B (aB)^c^D + 22733 LUT4 C6F5 AB?d:C^D:1:C + 22734 LUT4 C6F5 AB?d:C^D:1:C + 22735 LUT4 07F8 (c/AB\)^d + 22736 LUT3 0B c/aB\ + 22737 LUT2 4 aB + 22738 LUT4 C6F5 AB?d:C^D:1:C + 22739 LUT2 4 aB + 22740 LUT4 B44B (aB)^c^D + 22741 LUT4 6996 A^B^c^d + 22742 LUT3 4B (aB)^c + 22743 LUT3 4B (aB)^c + 22744 LUT4 9669 A^B^c^D + 22745 LUT4 390A AB?D:c^D:0:c + 22746 LUT4 C6F5 AB?d:C^D:1:C + 22747 LUT4 C6F5 AB?d:C^D:1:C + 22748 LUT4 C6F5 AB?d:C^D:1:C + 22749 LUT4 C6F5 AB?d:C^D:1:C + 22750 LUT4 390A AB?D:c^D:0:c + 22751 LUT4 4BB4 (aB)^c^d + 22752 LUT4 B44B (aB)^c^D + 22753 LUT4 C6F5 AB?d:C^D:1:C + 22754 LUT4 C6F5 AB?d:C^D:1:C + 22755 LUT3 4B (aB)^c + 22756 LUT4 C6F5 AB?d:C^D:1:C + 22757 LUT3 4F (aB)+c + 22758 LUT3 07 c/AB\ + 22759 LUT4 4BB4 (aB)^c^d + 22760 LUT3 B4 (aB)^C + 22761 LUT4 C6F5 AB?d:C^D:1:C + 22762 LUT4 C6F5 AB?d:C^D:1:C + 22763 LUT3 4B (aB)^c + 22764 LUT4 390A AB?D:c^D:0:c + 22765 LUT4 C6F5 AB?d:C^D:1:C + 22766 LUT4 C6F5 AB?d:C^D:1:C + 22767 LUT4 6996 A^B^c^d + 22768 LUT4 390A AB?D:c^D:0:c + 22769 LUT4 C6F5 AB?d:C^D:1:C + 22770 LUT4 C6F5 AB?d:C^D:1:C + 22771 LUT4 C6F5 AB?d:C^D:1:C + 22772 LUT4 6900 D(A^B^c) + 22773 LUT4 07F8 (c/AB\)^d + 22774 LUT2 4 aB + 22775 LUT4 B0BB /aB\(d+C) + 22776 LUT4 C6F5 AB?d:C^D:1:C + 22777 LUT4 2DDD AC?1:B:d:B^D + 22778 LUT4 390A AB?D:c^D:0:c + 22779 LUT4 4BB4 (aB)^c^d + 22780 LUT4 4BB4 (aB)^c^d + 22781 LUT4 C6F5 AB?d:C^D:1:C + 22782 LUT2 4 aB + 22783 LUT4 B44B (aB)^c^D + 22784 LUT4 C6F5 AB?d:C^D:1:C + 22785 LUT4 390A AB?D:c^D:0:c + 22786 LUT4 C6F5 AB?d:C^D:1:C + 22787 LUT4 C6F5 AB?d:C^D:1:C + 22788 LUT4 C6F5 AB?d:C^D:1:C + 22789 LUT4 B44B (aB)^c^D + 22790 LUT4 C6F5 AB?d:C^D:1:C + 22791 LUT4 390A AB?D:c^D:0:c + 22792 LUT4 B44B (aB)^c^D + 22793 LUT3 B4 (aB)^C + 22794 LUT4 C6F5 AB?d:C^D:1:C + 22795 LUT4 C6F5 AB?d:C^D:1:C + 22796 LUT3 4F (aB)+c + 22797 LUT3 0D c/Ab\ + 22798 LUT4 6996 A^B^c^d + 22799 LUT4 6996 A^B^c^d + 22800 LUT4 4BB4 (aB)^c^d + 22801 LUT3 4B (aB)^c + 22802 LUT4 C6F5 AB?d:C^D:1:C + 22803 LUT4 C6F5 AB?d:C^D:1:C + 22804 LUT3 B4 (aB)^C + 22805 LUT4 C6F5 AB?d:C^D:1:C + 22806 LUT4 C6F5 AB?d:C^D:1:C + 22807 LUT4 C6F5 AB?d:C^D:1:C + 22808 LUT4 B44B (aB)^c^D + 22809 LUT4 C6F5 AB?d:C^D:1:C + 22810 LUT4 C6F5 AB?d:C^D:1:C + 22811 LUT4 C6F5 AB?d:C^D:1:C + 22812 LUT4 C6F5 AB?d:C^D:1:C + 22813 LUT4 6900 D(A^B^c) + 22814 LUT3 96 A^B^C + 22815 LUT3 4B (aB)^c + 22816 LUT4 C6F5 AB?d:C^D:1:C + 22817 LUT4 C6F5 AB?d:C^D:1:C + 22818 LUT4 C6F5 AB?d:C^D:1:C + 22819 LUT4 C6F5 AB?d:C^D:1:C + 22820 LUT4 6996 A^B^c^d + 22821 LUT3 96 A^B^C + 22822 LUT3 B4 (aB)^C + 22823 LUT4 C6F5 AB?d:C^D:1:C + 22824 LUT4 390A AB?D:c^D:0:c + 22825 LUT4 C6F5 AB?d:C^D:1:C + 22826 LUT4 C6F5 AB?d:C^D:1:C + 22827 LUT4 C6F5 AB?d:C^D:1:C + 22828 LUT4 C6F5 AB?d:C^D:1:C + 22829 LUT2 4 aB + 22830 LUT3 B4 (aB)^C + 22831 LUT4 C6F5 AB?d:C^D:1:C + 22832 LUT4 C6F5 AB?d:C^D:1:C + 22833 LUT4 C6F5 AB?d:C^D:1:C + 22834 LUT4 C6F5 AB?d:C^D:1:C + 22835 LUT4 7887 (AB)^C^d + 22836 LUT4 C6F5 AB?d:C^D:1:C + 22837 LUT4 C6F5 AB?d:C^D:1:C + 22838 LUT4 C6F5 AB?d:C^D:1:C + 22839 LUT4 C6F5 AB?d:C^D:1:C + 22840 LUT4 6996 A^B^c^d + 22841 LUT4 C6F5 AB?d:C^D:1:C + 22842 LUT4 C6F5 AB?d:C^D:1:C + 22843 LUT4 C6F5 AB?d:C^D:1:C + 22844 LUT4 C6F5 AB?d:C^D:1:C + 22845 LUT4 C6F5 AB?d:C^D:1:C + 22846 LUT4 C6F5 AB?d:C^D:1:C + 22847 LUT4 C6F5 AB?d:C^D:1:C + 22848 LUT4 C6F5 AB?d:C^D:1:C + 22849 LUT4 390A AB?D:c^D:0:c + 22850 LUT4 B44B (aB)^c^D + 22851 LUT4 C6F5 AB?d:C^D:1:C + 22852 LUT4 390A AB?D:c^D:0:c + 22853 LUT2 B /aB\ + 22854 LUT4 0777 /AB\(d+c) + 22855 LUT4 6996 A^B^c^d + 22856 LUT3 69 A^B^c + 22857 LUT3 B4 (aB)^C + 22858 LUT4 C6F5 AB?d:C^D:1:C + 22859 LUT4 C6F5 AB?d:C^D:1:C + 22860 LUT4 390A AB?D:c^D:0:c + 22861 LUT4 6996 A^B^c^d + 22862 LUT4 C6F5 AB?d:C^D:1:C + 22863 LUT4 C6F5 AB?d:C^D:1:C + 22864 LUT4 C6F5 AB?d:C^D:1:C + 22865 LUT4 C6F5 AB?d:C^D:1:C + 22866 LUT4 C6F5 AB?d:C^D:1:C + 22867 LUT4 390A AB?D:c^D:0:c + 22868 LUT4 B400 AD?0:0:B^C:C + 22869 LUT4 6996 A^B^c^d + 22870 LUT4 4BB4 (aB)^c^d + 22871 LUT3 B4 (aB)^C + 22872 LUT4 C6F5 AB?d:C^D:1:C + 22873 LUT4 390A AB?D:c^D:0:c + 22874 LUT4 C6F5 AB?d:C^D:1:C + 22875 LUT4 C6F5 AB?d:C^D:1:C + 22876 LUT4 C6F5 AB?d:C^D:1:C + 22877 LUT4 7D55 AD?1:0:1:B^C + 22878 LUT4 0777 /AB\(d+c) + 22879 LUT4 6996 A^B^c^d + 22880 LUT4 9669 A^B^c^D + 22881 LUT3 B4 (aB)^C + 22882 LUT3 4B (aB)^c + 22883 LUT4 390A AB?D:c^D:0:c + 22884 LUT3 B4 (aB)^C + 22885 LUT4 C6F5 AB?d:C^D:1:C + 22886 LUT4 C6F5 AB?d:C^D:1:C + 22887 LUT4 C6F5 AB?d:C^D:1:C + 22888 LUT3 4B (aB)^c + 22889 LUT4 C6F5 AB?d:C^D:1:C + 22890 LUT4 C6F5 AB?d:C^D:1:C + 22891 LUT4 390A AB?D:c^D:0:c + 22892 LUT4 9669 A^B^c^D + 22893 LUT4 B44B (aB)^c^D + 22894 LUT4 C6F5 AB?d:C^D:1:C + 22895 LUT4 C6F5 AB?d:C^D:1:C + 22896 LUT3 4B (aB)^c + 22897 LUT4 390A AB?D:c^D:0:c + 22898 LUT4 C6F5 AB?d:C^D:1:C + 22899 LUT4 390A AB?D:c^D:0:c + 22900 LUT4 D222 AC?0:b:D:b^D + 22901 LUT4 B44B (aB)^c^D + 22902 LUT3 B4 (aB)^C + 22903 LUT4 C6F5 AB?d:C^D:1:C + 22904 LUT4 C6F5 AB?d:C^D:1:C + 22905 LUT4 C6F5 AB?d:C^D:1:C + 22906 LUT4 C6F5 AB?d:C^D:1:C + 22907 LUT4 C6F5 AB?d:C^D:1:C + 22908 LUT4 0777 /AB\(d+c) + 22909 LUT4 4BB4 (aB)^c^d + 22910 LUT4 6996 A^B^c^d + 22911 LUT3 4B (aB)^c + 22912 LUT4 C6F5 AB?d:C^D:1:C + 22913 LUT4 C6F5 AB?d:C^D:1:C + 22914 LUT4 C6F5 AB?d:C^D:1:C + 22915 LUT4 C6F5 AB?d:C^D:1:C + 22916 LUT3 96 A^B^C + 22917 LUT3 B4 (aB)^C + 22918 LUT4 C6F5 AB?d:C^D:1:C + 22919 LUT4 C6F5 AB?d:C^D:1:C + 22920 LUT4 C6F5 AB?d:C^D:1:C + 22921 LUT4 D755 AD?1:0:1:b^C + 22922 LUT4 0777 /AB\(d+c) + 22923 LUT3 96 A^B^C + 22924 LUT4 4BB4 (aB)^c^d + 22925 LUT3 4B (aB)^c + 22926 LUT4 C6F5 AB?d:C^D:1:C + 22927 LUT4 C6F5 AB?d:C^D:1:C + 22928 LUT4 9669 A^B^c^D + 22929 LUT4 390A AB?D:c^D:0:c + 22930 LUT4 C6F5 AB?d:C^D:1:C + 22931 LUT4 C6F5 AB?d:C^D:1:C + 22932 LUT4 C6F5 AB?d:C^D:1:C + 22933 LUT4 C6F5 AB?d:C^D:1:C + 22934 LUT3 69 A^B^c + 22935 LUT3 B4 (aB)^C + 22936 LUT4 C6F5 AB?d:C^D:1:C + 22937 LUT4 C6F5 AB?d:C^D:1:C + 22938 LUT4 390A AB?D:c^D:0:c + 22939 LUT4 9669 A^B^c^D + 22940 LUT4 00BF ((/aB\)+c)d + 22941 LUT2 4 aB + 22942 LUT4 B0BB /aB\(d+C) + 22943 LUT3 78 (AB)^C + 22944 LUT4 C6F5 AB?d:C^D:1:C + 22945 LUT4 C6F5 AB?d:C^D:1:C + 22946 LUT4 C6F5 AB?d:C^D:1:C + 22947 LUT2 B /aB\ + 22948 LUT4 4B00 AD?0:0:b^C:c + 22949 LUT4 4BB4 (aB)^c^d + 22950 LUT4 B44B (aB)^c^D + 22951 LUT3 4B (aB)^c + 22952 LUT3 4B (aB)^c + 22953 LUT4 C6F5 AB?d:C^D:1:C + 22954 LUT3 B4 (aB)^C + 22955 LUT4 C6F5 AB?d:C^D:1:C + 22956 LUT4 B44B (aB)^c^D + 22957 LUT4 4BB4 (aB)^c^d + 22958 LUT4 C6F5 AB?d:C^D:1:C + 22959 LUT4 390A AB?D:c^D:0:c + 22960 LUT4 0777 /AB\(d+c) + 22961 LUT4 C6F5 AB?d:C^D:1:C + 22962 LUT4 C6F5 AB?d:C^D:1:C + 22963 LUT4 C6F5 AB?d:C^D:1:C + 22964 LUT4 C6F5 AB?d:C^D:1:C + 22965 LUT3 07 c/AB\ + 22966 LUT2 4 aB + 22967 LUT4 B0BB /aB\(d+C) + 22968 LUT4 C6F5 AB?d:C^D:1:C + 22969 LUT4 D755 AD?1:0:1:b^C + 22970 LUT4 0BBB /aB\(d+c) + 22971 LUT2 9 a^B + 22972 LUT4 B44B (aB)^c^D + 22973 LUT3 B4 (aB)^C + 22974 LUT4 C6F5 AB?d:C^D:1:C + 22975 LUT4 C6F5 AB?d:C^D:1:C + 22976 LUT4 6996 A^B^c^d + 22977 LUT4 390A AB?D:c^D:0:c + 22978 LUT4 C6F5 AB?d:C^D:1:C + 22979 LUT4 C6F5 AB?d:C^D:1:C + 22980 LUT4 C6F5 AB?d:C^D:1:C + 22981 LUT3 96 A^B^C + 22982 LUT4 6996 A^B^c^d + 22983 LUT4 C6F5 AB?d:C^D:1:C + 22984 LUT4 C6F5 AB?d:C^D:1:C + 22985 LUT4 390A AB?D:c^D:0:c + 22986 LUT4 C6F5 AB?d:C^D:1:C + 22987 LUT4 C6F5 AB?d:C^D:1:C + 22988 LUT4 C6F5 AB?d:C^D:1:C + 22989 LUT3 69 A^B^c + 22990 LUT4 C6F5 AB?d:C^D:1:C + 22991 LUT4 C6F5 AB?d:C^D:1:C + 22992 LUT4 C6F5 AB?d:C^D:1:C + 22993 LUT2 B /aB\ + 22994 LUT4 7077 /AB\(d+C) + 22995 LUT3 B4 (aB)^C + 22996 LUT4 9669 A^B^c^D + 22997 LUT3 4B (aB)^c + 22998 LUT4 C6F5 AB?d:C^D:1:C + 22999 LUT4 B44B (aB)^c^D + 23000 LUT4 C6F5 AB?d:C^D:1:C + 23001 LUT4 390A AB?D:c^D:0:c + 23002 LUT4 C6F5 AB?d:C^D:1:C + 23003 LUT4 390A AB?D:c^D:0:c + 23004 LUT4 6900 D(A^B^c) + 23005 LUT4 4BB4 (aB)^c^d + 23006 LUT3 B4 (aB)^C + 23007 LUT4 C6F5 AB?d:C^D:1:C + 23008 LUT4 C6F5 AB?d:C^D:1:C + 23009 LUT4 B44B (aB)^c^D + 23010 LUT4 C6F5 AB?d:C^D:1:C + 23011 LUT4 C6F5 AB?d:C^D:1:C + 23012 LUT4 9669 A^B^c^D + 23013 LUT4 C6F5 AB?d:C^D:1:C + 23014 LUT4 C6F5 AB?d:C^D:1:C + 23015 LUT4 390A AB?D:c^D:0:c + 23016 LUT4 C6F5 AB?d:C^D:1:C + 23017 LUT4 D755 AD?1:0:1:b^C + 23018 LUT4 0777 /AB\(d+c) + 23019 LUT2 6 A^B + 23020 LUT4 B44B (aB)^c^D + 23021 LUT4 B44B (aB)^c^D + 23022 LUT2 4 aB + 23023 LUT4 390A AB?D:c^D:0:c + 23024 LUT4 C6F5 AB?d:C^D:1:C + 23025 LUT4 B44B (aB)^c^D + 23026 LUT4 C6F5 AB?d:C^D:1:C + 23027 LUT4 C6F5 AB?d:C^D:1:C + 23028 LUT4 8778 (AB)^C^D + 23029 LUT3 B4 (aB)^C + 23030 LUT4 C6F5 AB?d:C^D:1:C + 23031 LUT4 B44B (aB)^c^D + 23032 LUT4 C6F5 AB?d:C^D:1:C + 23033 LUT4 390A AB?D:c^D:0:c + 23034 LUT4 9669 A^B^c^D + 23035 LUT4 4BB4 (aB)^c^d + 23036 LUT4 C6F5 AB?d:C^D:1:C + 23037 LUT4 390A AB?D:c^D:0:c + 23038 LUT4 00BF ((/aB\)+c)d + 23039 LUT2 4 aB + 23040 LUT4 B0BB /aB\(d+C) + 23041 LUT4 C6F5 AB?d:C^D:1:C + 23042 LUT4 C6F5 AB?d:C^D:1:C + 23043 LUT2 B /aB\ + 23044 LUT4 0BBB /aB\(d+c) + 23045 LUT4 9669 A^B^c^D + 23046 LUT4 4BB4 (aB)^c^d + 23047 LUT4 C6F5 AB?d:C^D:1:C + 23048 LUT4 C6F5 AB?d:C^D:1:C + 23049 LUT4 C6F5 AB?d:C^D:1:C + 23050 LUT4 C6F5 AB?d:C^D:1:C + 23051 LUT4 390A AB?D:c^D:0:c + 23052 LUT4 6900 D(A^B^c) + 23053 LUT4 9669 A^B^c^D + 23054 LUT4 4BB4 (aB)^c^d + 23055 LUT4 C6F5 AB?d:C^D:1:C + 23056 LUT4 390A AB?D:c^D:0:c + 23057 LUT4 C6F5 AB?d:C^D:1:C + 23058 LUT4 C6F5 AB?d:C^D:1:C + 23059 LUT4 C6F5 AB?d:C^D:1:C + 23060 LUT4 6996 A^B^c^d + 23061 LUT4 390A AB?D:c^D:0:c + 23062 LUT4 C6F5 AB?d:C^D:1:C + 23063 LUT4 C6F5 AB?d:C^D:1:C + 23064 LUT4 C6F5 AB?d:C^D:1:C + 23065 LUT4 C6F5 AB?d:C^D:1:C + 23066 LUT2 B /aB\ + 23067 LUT4 8700 AD?0:0:c:b^C + 23068 LUT4 4BB4 (aB)^c^d + 23069 LUT4 6996 A^B^c^d + 23070 LUT4 4BB4 (aB)^c^d + 23071 LUT4 C6F5 AB?d:C^D:1:C + 23072 LUT4 C6F5 AB?d:C^D:1:C + 23073 LUT4 B44B (aB)^c^D + 23074 LUT4 390A AB?D:c^D:0:c + 23075 LUT4 C6F5 AB?d:C^D:1:C + 23076 LUT4 C6F5 AB?d:C^D:1:C + 23077 LUT4 4BB4 (aB)^c^d + 23078 LUT4 4BB4 (aB)^c^d + 23079 LUT4 C6F5 AB?d:C^D:1:C + 23080 LUT2 4 aB + 23081 LUT4 C6F5 AB?d:C^D:1:C + 23082 LUT4 7077 /AB\(d+C) + 23083 LUT4 9669 A^B^c^D + 23084 LUT3 B4 (aB)^C + 23085 LUT4 C6F5 AB?d:C^D:1:C + 23086 LUT3 B4 (aB)^C + 23087 LUT4 C6F5 AB?d:C^D:1:C + 23088 LUT4 C6F5 AB?d:C^D:1:C + 23089 LUT4 390A AB?D:c^D:0:c + 23090 LUT4 C6F5 AB?d:C^D:1:C + 23091 LUT4 C6F5 AB?d:C^D:1:C + 23092 LUT4 C6F5 AB?d:C^D:1:C + 23093 LUT4 B44B (aB)^c^D + 23094 LUT4 9669 A^B^c^D + 23095 LUT4 C6F5 AB?d:C^D:1:C + 23096 LUT4 C6F5 AB?d:C^D:1:C + 23097 LUT4 C6F5 AB?d:C^D:1:C + 23098 LUT4 C6F5 AB?d:C^D:1:C + 23099 LUT4 C6F5 AB?d:C^D:1:C + 23100 LUT4 2DDD AC?1:B:d:B^D + 23101 LUT4 0777 /AB\(d+c) + 23102 LUT4 4BB4 (aB)^c^d + 23103 LUT3 4B (aB)^c + 23104 LUT3 07 c/AB\ + 23105 LUT2 4 aB + 23106 LUT4 B0BB /aB\(d+C) + 23107 LUT4 B44B (aB)^c^D + 23108 LUT4 C6F5 AB?d:C^D:1:C + 23109 LUT4 C6F5 AB?d:C^D:1:C + 23110 LUT4 0777 /AB\(d+c) + 23111 LUT4 9669 A^B^c^D + 23112 LUT4 C6F5 AB?d:C^D:1:C + 23113 LUT4 390A AB?D:c^D:0:c + 23114 LUT4 C6F5 AB?d:C^D:1:C + 23115 LUT4 C6F5 AB?d:C^D:1:C + 23116 LUT4 6996 A^B^c^d + 23117 LUT4 C6F5 AB?d:C^D:1:C + 23118 LUT4 C6F5 AB?d:C^D:1:C + 23119 LUT4 C6F5 AB?d:C^D:1:C + 23120 LUT4 C6F5 AB?d:C^D:1:C + 23121 LUT2 4 aB + 23122 LUT4 2DDD AC?1:B:d:B^D + 23123 LUT4 390A AB?D:c^D:0:c + 23124 LUT4 6996 A^B^c^d + 23125 LUT4 C6F5 AB?d:C^D:1:C + 23126 LUT4 C6F5 AB?d:C^D:1:C + 23127 LUT4 C6F5 AB?d:C^D:1:C + 23128 LUT4 C6F5 AB?d:C^D:1:C + 23129 LUT4 C6F5 AB?d:C^D:1:C + 23130 LUT4 7D55 AD?1:0:1:B^C + 23131 LUT3 69 A^B^c + 23132 LUT4 4BB4 (aB)^c^d + 23133 LUT3 B4 (aB)^C + 23134 LUT3 4B (aB)^c + 23135 LUT2 4 aB + 23136 LUT4 C6F5 AB?d:C^D:1:C + 23137 LUT4 C6F5 AB?d:C^D:1:C + 23138 LUT4 C6F5 AB?d:C^D:1:C + 23139 LUT4 7077 /AB\(d+C) + 23140 LUT3 69 A^B^c + 23141 LUT3 4B (aB)^c + 23142 LUT3 4B (aB)^c + 23143 LUT4 C6F5 AB?d:C^D:1:C + 23144 LUT4 C6F5 AB?d:C^D:1:C + 23145 LUT4 6996 A^B^c^d + 23146 LUT3 B4 (aB)^C + 23147 LUT4 C6F5 AB?d:C^D:1:C + 23148 LUT4 9669 A^B^c^D + 23149 LUT4 C6F5 AB?d:C^D:1:C + 23150 LUT4 390A AB?D:c^D:0:c + 23151 LUT4 C6F5 AB?d:C^D:1:C + 23152 LUT4 C6F5 AB?d:C^D:1:C + 23153 LUT4 C6F5 AB?d:C^D:1:C + 23154 LUT4 C6F5 AB?d:C^D:1:C + 23155 LUT4 D755 AD?1:0:1:b^C + 23156 LUT4 7077 /AB\(d+C) + 23157 LUT3 69 A^B^c + 23158 LUT3 4B (aB)^c + 23159 LUT4 C6F5 AB?d:C^D:1:C + 23160 LUT4 C6F5 AB?d:C^D:1:C + 23161 LUT3 B4 (aB)^C + 23162 LUT4 9669 A^B^c^D + 23163 LUT4 07F8 (c/AB\)^d + 23164 LUT4 C6F5 AB?d:C^D:1:C + 23165 LUT2 4 aB + 23166 LUT4 B0BB /aB\(d+C) + 23167 LUT3 96 A^B^C + 23168 LUT4 C6F5 AB?d:C^D:1:C + 23169 LUT4 390A AB?D:c^D:0:c + 23170 LUT4 390A AB?D:c^D:0:c + 23171 LUT4 C6F5 AB?d:C^D:1:C + 23172 LUT4 390A AB?D:c^D:0:c + 23173 LUT4 9669 A^B^c^D + 23174 LUT4 4BB4 (aB)^c^d + 23175 LUT4 C6F5 AB?d:C^D:1:C + 23176 LUT4 390A AB?D:c^D:0:c + 23177 LUT4 C6F5 AB?d:C^D:1:C + 23178 LUT4 C6F5 AB?d:C^D:1:C + 23179 LUT4 390A AB?D:c^D:0:c + 23180 LUT2 B /aB\ + 23181 LUT4 8700 AD?0:0:c:b^C + 23182 LUT4 B44B (aB)^c^D + 23183 LUT4 9669 A^B^c^D + 23184 LUT3 69 A^B^c + 23185 LUT3 B4 (aB)^C + 23186 LUT4 B44B (aB)^c^D + 23187 LUT4 C6F5 AB?d:C^D:1:C + 23188 LUT4 C6F5 AB?d:C^D:1:C + 23189 LUT2 4 aB + 23190 LUT3 B4 (aB)^C + 23191 LUT2 4 aB + 23192 LUT4 C6F5 AB?d:C^D:1:C + 23193 LUT4 C6F5 AB?d:C^D:1:C + 23194 LUT4 B44B (aB)^c^D + 23195 LUT4 B44B (aB)^c^D + 23196 LUT4 00BF ((/aB\)+c)d + 23197 LUT2 4 aB + 23198 LUT4 B0BB /aB\(d+C) + 23199 LUT4 C6F5 AB?d:C^D:1:C + 23200 LUT3 4B (aB)^c + 23201 LUT4 4BB4 (aB)^c^d + 23202 LUT4 C6F5 AB?d:C^D:1:C + 23203 LUT4 0BBB /aB\(d+c) + 23204 LUT4 B44B (aB)^c^D + 23205 LUT4 C6F5 AB?d:C^D:1:C + 23206 LUT4 C6F5 AB?d:C^D:1:C + 23207 LUT4 D755 AD?1:0:1:b^C + 23208 LUT3 69 A^B^c + 23209 LUT4 9669 A^B^c^D + 23210 LUT4 F807 (c/AB\)^D + 23211 LUT4 C6F5 AB?d:C^D:1:C + 23212 LUT2 4 aB + 23213 LUT4 B0BB /aB\(d+C) + 23214 LUT4 C6F5 AB?d:C^D:1:C + 23215 LUT4 C6F5 AB?d:C^D:1:C + 23216 LUT4 C6F5 AB?d:C^D:1:C + 23217 LUT4 9669 A^B^c^D + 23218 LUT4 C6F5 AB?d:C^D:1:C + 23219 LUT4 390A AB?D:c^D:0:c + 23220 LUT4 C6F5 AB?d:C^D:1:C + 23221 LUT4 C6F5 AB?d:C^D:1:C + 23222 LUT4 C6F5 AB?d:C^D:1:C + 23223 LUT3 87 (AB)^c + 23224 LUT4 B44B (aB)^c^D + 23225 LUT4 F807 (c/AB\)^D + 23226 LUT4 C6F5 AB?d:C^D:1:C + 23227 LUT2 4 aB + 23228 LUT4 B0BB /aB\(d+C) + 23229 LUT4 C6F5 AB?d:C^D:1:C + 23230 LUT4 B0BB /aB\(d+C) + 23231 LUT2 6 A^B + 23232 LUT4 C6F5 AB?d:C^D:1:C + 23233 LUT4 390A AB?D:c^D:0:c + 23234 LUT2 B /aB\ + 23235 LUT4 9600 D(A^B^C) + 23236 LUT4 B44B (aB)^c^D + 23237 LUT4 B44B (aB)^c^D + 23238 LUT4 4BB4 (aB)^c^d + 23239 LUT3 4B (aB)^c + 23240 LUT4 C6F5 AB?d:C^D:1:C + 23241 LUT4 C6F5 AB?d:C^D:1:C + 23242 LUT4 B44B (aB)^c^D + 23243 LUT4 C6F5 AB?d:C^D:1:C + 23244 LUT4 C6F5 AB?d:C^D:1:C + 23245 LUT4 9669 A^B^c^D + 23246 LUT4 9669 A^B^c^D + 23247 LUT4 C6F5 AB?d:C^D:1:C + 23248 LUT4 390A AB?D:c^D:0:c + 23249 LUT4 C6F5 AB?d:C^D:1:C + 23250 LUT4 C6F5 AB?d:C^D:1:C + 23251 LUT4 C6F5 AB?d:C^D:1:C + 23252 LUT4 C6F5 AB?d:C^D:1:C + 23253 LUT4 C6F5 AB?d:C^D:1:C + 23254 LUT4 7077 /AB\(d+C) + 23255 LUT3 4B (aB)^c + 23256 LUT4 C6F5 AB?d:C^D:1:C + 23257 LUT4 7D55 AD?1:0:1:B^C + 23258 LUT4 9669 A^B^c^D + 23259 LUT4 9669 A^B^c^D + 23260 LUT3 4B (aB)^c + 23261 LUT4 C6F5 AB?d:C^D:1:C + 23262 LUT4 C6F5 AB?d:C^D:1:C + 23263 LUT4 C6F5 AB?d:C^D:1:C + 23264 LUT4 C6F5 AB?d:C^D:1:C + 23265 LUT4 B44B (aB)^c^D + 23266 LUT4 2DDD AC?1:B:d:B^D + 23267 LUT4 C6F5 AB?d:C^D:1:C + 23268 LUT4 C6F5 AB?d:C^D:1:C + 23269 LUT4 C6F5 AB?d:C^D:1:C + 23270 LUT3 69 A^B^c + 23271 LUT3 69 A^B^c + 23272 LUT4 B44B (aB)^c^D + 23273 LUT4 C6F5 AB?d:C^D:1:C + 23274 LUT4 C6F5 AB?d:C^D:1:C + 23275 LUT4 C6F5 AB?d:C^D:1:C + 23276 LUT4 390A AB?D:c^D:0:c + 23277 LUT4 390A AB?D:c^D:0:c + 23278 LUT4 0BBB /aB\(d+c) + 23279 LUT4 C6F5 AB?d:C^D:1:C + 23280 LUT4 D755 AD?1:0:1:b^C + 23281 LUT4 C6F5 AB?d:C^D:1:C + 23282 LUT4 C6F5 AB?d:C^D:1:C + 23283 LUT4 390A AB?D:c^D:0:c + 23284 LUT4 C6F5 AB?d:C^D:1:C + 23285 LUT4 C6F5 AB?d:C^D:1:C + 23286 LUT4 C6F5 AB?d:C^D:1:C + 23287 LUT4 C6F5 AB?d:C^D:1:C + 23288 LUT4 C6F5 AB?d:C^D:1:C + 23289 LUT4 9669 A^B^c^D + 23290 LUT3 B4 (aB)^C + 23291 LUT4 C6F5 AB?d:C^D:1:C + 23292 LUT3 69 A^B^c + 23293 LUT4 C6F5 AB?d:C^D:1:C + 23294 LUT4 390A AB?D:c^D:0:c + 23295 LUT4 390A AB?D:c^D:0:c + 23296 LUT4 C6F5 AB?d:C^D:1:C + 23297 LUT4 C6F5 AB?d:C^D:1:C + 23298 LUT4 7077 /AB\(d+C) + 23299 LUT2 4 aB + 23300 LUT4 8F88 (AB)+(cD) + 23301 LUT3 FE /ab\+C + 23302 LUT2 8 AB + 23303 LUT2 8 AB + 23304 LUT4 4F44 (aB)+(cD) + 23305 LUT2 8 AB + 23306 LUT4 4F44 (aB)+(cD) + 23307 LUT3 3A c?b:A + 23308 LUT2 B /aB\ + 23309 LUT3 EF /ab\+c + 23310 LUT3 10 abC + 23311 LUT2 8 AB + 23312 LUT2 4 aB + 23313 LUT4 0B00 cD/aB\ + 23314 LUT2 8 AB + 23315 LUT2 8 AB + 23316 LUT2 8 AB + 23317 LUT2 8 AB + 23318 LUT2 8 AB + 23319 LUT2 8 AB + 23320 LUT2 B /aB\ + 23321 LUT4 0001 abcd + 23322 LUT4 8000 ABCD + 23323 LUT2 4 aB + 23324 LUT4 0B00 cD/aB\ + 23325 LUT3 40 aBC + 23326 LUT2 8 AB + 23327 LUT2 8 AB + 23328 LUT2 8 AB + 23329 LUT2 8 AB + 23330 LUT2 8 AB + 23331 LUT2 8 AB + 23332 LUT2 8 AB + 23333 LUT2 8 AB + 23334 LUT4 8000 ABCD + 23335 LUT4 8000 ABCD + 23336 LUT3 10 abC + 23337 LUT4 0001 abcd + 23338 LUT2 8 AB + 23339 LUT4 0001 abcd + 23340 LUT4 0001 abcd + 23341 LUT4 0001 abcd + 23342 LUT4 0001 abcd + 23343 LUT4 0001 abcd + 23344 LUT4 0001 abcd + 23345 LUT4 0001 abcd + 23346 LUT4 1000 abCD + 23347 LUT4 8000 ABCD + 23348 LUT4 0001 abcd + 23349 LUT4 0001 abcd + 23350 LUT4 0001 abcd + 23351 LUT4 0001 abcd + 23352 LUT4 0001 abcd + 23353 LUT4 0001 abcd + 23354 LUT4 0001 abcd + 23355 LUT4 0001 abcd + 23356 LUT4 0770 (C^D)/AB\ + 23357 LUT3 80 ABC + 23358 LUT4 8000 ABCD + 23359 LUT4 0001 abcd + 23360 LUT4 0001 abcd + 23361 LUT4 0001 abcd + 23362 LUT4 0001 abcd + 23363 LUT3 10 abC + 23364 LUT4 0001 abcd + 23365 LUT4 8000 ABCD + 23366 LUT4 0001 abcd + 23367 LUT4 0001 abcd + 23368 LUT4 0001 abcd + 23369 LUT4 0001 abcd + 23370 LUT3 80 ABC + 23371 LUT3 80 ABC + 23372 LUT2 8 AB + 23373 LUT4 0001 abcd + 23374 LUT4 0001 abcd + 23375 LUT4 0001 abcd + 23376 LUT4 0001 abcd + 23377 LUT4 0001 abcd + 23378 LUT4 0001 abcd + 23379 LUT4 0001 abcd + 23380 LUT4 0001 abcd + 23381 LUT2 8 AB + 23382 LUT4 1000 abCD + 23383 LUT4 8000 ABCD + 23384 LUT4 0001 abcd + 23385 LUT4 0001 abcd + 23386 LUT4 0001 abcd + 23387 LUT4 0001 abcd + 23388 LUT4 0001 abcd + 23389 LUT4 0001 abcd + 23390 LUT4 0001 abcd + 23391 LUT4 0001 abcd + 23392 LUT4 8000 ABCD + 23393 LUT3 10 abC + 23394 LUT4 0001 abcd + 23395 LUT2 8 AB + 23396 LUT4 0001 abcd + 23397 LUT4 0001 abcd + 23398 LUT4 0001 abcd + 23399 LUT4 0001 abcd + 23400 LUT4 0001 abcd + 23401 LUT4 0001 abcd + 23402 LUT4 0001 abcd + 23403 LUT4 0770 (C^D)/AB\ + 23404 LUT3 80 ABC + 23405 LUT4 8000 ABCD + 23406 LUT4 8000 ABCD + 23407 LUT4 0001 abcd + 23408 LUT4 0001 abcd + 23409 LUT4 0001 abcd + 23410 LUT4 0001 abcd + 23411 LUT3 10 abC + 23412 LUT4 0001 abcd + 23413 LUT4 0001 abcd + 23414 LUT4 0001 abcd + 23415 LUT4 0001 abcd + 23416 LUT4 0001 abcd + 23417 LUT4 0770 (C^D)/AB\ + 23418 LUT4 8000 ABCD + 23419 LUT3 80 ABC + 23420 LUT4 8000 ABCD + 23421 LUT4 0001 abcd + 23422 LUT4 0001 abcd + 23423 LUT4 0001 abcd + 23424 LUT4 0001 abcd + 23425 LUT4 0001 abcd + 23426 LUT2 8 AB + 23427 LUT4 0001 abcd + 23428 LUT4 0001 abcd + 23429 LUT4 0001 abcd + 23430 LUT4 0001 abcd + 23431 LUT2 8 AB + 23432 LUT4 1000 abCD + 23433 LUT4 1000 abCD + 23434 LUT4 4000 aBCD + 23435 LUT4 0100 abcD + 23436 LUT4 0001 abcd + 23437 LUT4 0001 abcd + 23438 LUT4 0001 abcd + 23439 LUT4 0001 abcd + 23440 LUT4 0001 abcd + 23441 LUT4 0001 abcd + 23442 LUT4 0770 (C^D)/AB\ + 23443 LUT3 80 ABC + 23444 LUT4 8000 ABCD + 23445 LUT4 0001 abcd + 23446 LUT4 0001 abcd + 23447 LUT4 0001 abcd + 23448 LUT4 0001 abcd + 23449 LUT3 10 abC + 23450 LUT4 0001 abcd + 23451 LUT4 8000 ABCD + 23452 LUT4 0001 abcd + 23453 LUT4 0001 abcd + 23454 LUT4 0001 abcd + 23455 LUT4 0001 abcd + 23456 LUT4 0770 (C^D)/AB\ + 23457 LUT3 40 aBC + 23458 LUT4 1000 abCD + 23459 LUT4 8000 ABCD + 23460 LUT3 10 abC + 23461 LUT4 0001 abcd + 23462 LUT4 0100 abcD + 23463 LUT4 0001 abcd + 23464 LUT4 0001 abcd + 23465 LUT4 0001 abcd + 23466 LUT4 0100 abcD + 23467 LUT4 0001 abcd + 23468 LUT4 0100 abcD + 23469 LUT4 0001 abcd + 23470 LUT2 8 AB + 23471 LUT4 0770 (C^D)/AB\ + 23472 LUT4 8000 ABCD + 23473 LUT3 80 ABC + 23474 LUT4 8000 ABCD + 23475 LUT4 0001 abcd + 23476 LUT4 0001 abcd + 23477 LUT4 0001 abcd + 23478 LUT4 0001 abcd + 23479 LUT4 0001 abcd + 23480 LUT2 8 AB + 23481 LUT4 0001 abcd + 23482 LUT4 0001 abcd + 23483 LUT4 0001 abcd + 23484 LUT4 0001 abcd + 23485 LUT4 0770 (C^D)/AB\ + 23486 LUT4 8000 ABCD + 23487 LUT4 1000 abCD + 23488 LUT4 8000 ABCD + 23489 LUT4 0001 abcd + 23490 LUT4 0001 abcd + 23491 LUT4 0001 abcd + 23492 LUT4 0001 abcd + 23493 LUT4 0001 abcd + 23494 LUT4 0100 abcD + 23495 LUT4 0001 abcd + 23496 LUT4 0001 abcd + 23497 LUT4 0001 abcd + 23498 LUT4 0770 (C^D)/AB\ + 23499 LUT4 8000 ABCD + 23500 LUT3 80 ABC + 23501 LUT4 0001 abcd + 23502 LUT4 0001 abcd + 23503 LUT4 0001 abcd + 23504 LUT4 8000 ABCD + 23505 LUT4 0001 abcd + 23506 LUT4 0001 abcd + 23507 LUT4 0001 abcd + 23508 LUT4 0001 abcd + 23509 LUT4 0001 abcd + 23510 LUT4 0001 abcd + 23511 LUT3 40 aBC + 23512 LUT3 10 abC + 23513 LUT3 80 ABC + 23514 LUT3 40 aBC + 23515 LUT4 0100 abcD + 23516 LUT4 0001 abcd + 23517 LUT4 8000 ABCD + 23518 LUT4 0001 abcd + 23519 LUT4 0001 abcd + 23520 LUT4 0001 abcd + 23521 LUT4 0001 abcd + 23522 LUT4 0100 abcD + 23523 LUT4 0001 abcd + 23524 LUT3 10 abC + 23525 LUT2 4 aB + 23526 LUT2 4 aB + 23527 LUT4 0100 abcD + 23528 LUT2 4 aB + 23529 LUT2 4 aB + 23530 LUT2 4 aB + 23531 LUT3 10 abC + 23532 LUT2 4 aB + 23533 LUT2 8 AB + 23534 LUT3 80 ABC + 23535 LUT2 1 ab + 23536 LUT3 40 aBC + 23537 LUT2 8 AB + 23538 LUT4 4000 aBCD + 23539 LUT3 40 aBC + 23540 LUT2 8 AB + 23541 LUT4 0777 /AB\(d+c) + 23542 LUT2 8 AB + 23543 LUT2 8 AB + 23544 LUT4 4000 aBCD + 23545 LUT3 40 aBC + 23546 LUT2 8 AB + 23547 LUT3 40 aBC + 23548 LUT3 07 c/AB\ + 23549 LUT2 4 aB + 23550 LUT4 5300 D(C?b:a) + 23551 LUT2 4 aB + 23552 LUT3 53 C?b:a + 23553 LUT3 35 c?b:a + 23554 LUT4 0007 cd/AB\ + 23555 LUT3 40 aBC + 23556 LUT4 5300 D(C?b:a) + 23557 LUT2 8 AB + 23558 LUT3 35 c?b:a + 23559 LUT3 35 c?b:a + 23560 LUT2 4 aB + 23561 LUT4 0777 /AB\(d+c) + 23562 LUT2 8 AB + 23563 LUT4 4000 aBCD + 23564 LUT4 4000 aBCD + 23565 LUT4 0777 /AB\(d+c) + 23566 LUT4 7000 CD/AB\ + 23567 LUT4 0700 cD/AB\ + 23568 LUT4 0777 /AB\(d+c) + 23569 LUT4 0700 cD/AB\ + 23570 LUT3 70 C/AB\ + 23571 LUT3 07 c/AB\ + 23572 LUT4 5300 D(C?b:a) + 23573 LUT3 53 C?b:a + 23574 LUT3 35 c?b:a + 23575 LUT4 5300 D(C?b:a) + 23576 LUT3 35 c?b:a + 23577 LUT3 35 c?b:a + 23578 LUT4 0777 /AB\(d+c) + 23579 LUT4 8000 ABCD + 23580 LUT3 80 ABC + 23581 LUT4 8000 ABCD + 23582 LUT4 0777 /AB\(d+c) + 23583 LUT2 8 AB + 23584 LUT4 0777 /AB\(d+c) + 23585 LUT2 8 AB + 23586 LUT2 8 AB + 23587 LUT2 8 AB + 23588 LUT3 70 C/AB\ + 23589 LUT3 70 C/AB\ + 23590 LUT3 70 C/AB\ + 23591 LUT4 7000 CD/AB\ + 23592 LUT4 0700 cD/AB\ + 23593 LUT4 0007 cd/AB\ + 23594 LUT4 5300 D(C?b:a) + 23595 LUT3 53 C?b:a + 23596 LUT3 35 c?b:a + 23597 LUT4 5300 D(C?b:a) + 23598 LUT3 35 c?b:a + 23599 LUT3 35 c?b:a + 23600 LUT4 0777 /AB\(d+c) + 23601 LUT3 40 aBC + 23602 LUT4 0777 /AB\(d+c) + 23603 LUT3 8F (AB)+c + 23604 LUT3 80 ABC + 23605 LUT4 0777 /AB\(d+c) + 23606 LUT4 0777 /AB\(d+c) + 23607 LUT4 7000 CD/AB\ + 23608 LUT4 0777 /AB\(d+c) + 23609 LUT4 7000 CD/AB\ + 23610 LUT4 0777 /AB\(d+c) + 23611 LUT3 70 C/AB\ + 23612 LUT4 7000 CD/AB\ + 23613 LUT4 0700 cD/AB\ + 23614 LUT4 0007 cd/AB\ + 23615 LUT4 5300 D(C?b:a) + 23616 LUT3 35 c?b:a + 23617 LUT3 35 c?b:a + 23618 LUT4 5300 D(C?b:a) + 23619 LUT3 53 C?b:a + 23620 LUT3 35 c?b:a + 23621 LUT4 0777 /AB\(d+c) + 23622 LUT3 8F (AB)+c + 23623 LUT3 80 ABC + 23624 LUT4 0777 /AB\(d+c) + 23625 LUT4 0777 /AB\(d+c) + 23626 LUT4 7000 CD/AB\ + 23627 LUT4 0777 /AB\(d+c) + 23628 LUT4 7000 CD/AB\ + 23629 LUT3 70 C/AB\ + 23630 LUT4 7000 CD/AB\ + 23631 LUT4 7000 CD/AB\ + 23632 LUT4 0BBB /aB\(d+c) + 23633 LUT3 AC c?A:B + 23634 LUT3 35 c?b:a + 23635 LUT3 35 c?b:a + 23636 LUT4 0BBB /aB\(d+c) + 23637 LUT3 C5 C?a:B + 23638 LUT3 35 c?b:a + 23639 LUT3 07 c/AB\ + 23640 LUT4 0777 /AB\(d+c) + 23641 LUT3 8F (AB)+c + 23642 LUT3 80 ABC + 23643 LUT4 0777 /AB\(d+c) + 23644 LUT4 0777 /AB\(d+c) + 23645 LUT4 7000 CD/AB\ + 23646 LUT4 0777 /AB\(d+c) + 23647 LUT4 8000 ABCD + 23648 LUT4 0777 /AB\(d+c) + 23649 LUT3 70 C/AB\ + 23650 LUT3 07 c/AB\ + 23651 LUT4 5300 D(C?b:a) + 23652 LUT3 35 c?b:a + 23653 LUT3 35 c?b:a + 23654 LUT4 0777 /AB\(d+c) + 23655 LUT4 0700 cD/AB\ + 23656 LUT3 70 C/AB\ + 23657 LUT3 07 c/AB\ + 23658 LUT4 3A00 D(c?b:A) + 23659 LUT3 35 c?b:a + 23660 LUT3 8F (AB)+c + 23661 LUT3 80 ABC + 23662 LUT4 0777 /AB\(d+c) + 23663 LUT4 0777 /AB\(d+c) + 23664 LUT4 7000 CD/AB\ + 23665 LUT4 0777 /AB\(d+c) + 23666 LUT4 7000 CD/AB\ + 23667 LUT4 0777 /AB\(d+c) + 23668 LUT3 70 C/AB\ + 23669 LUT4 7000 CD/AB\ + 23670 LUT4 0700 cD/AB\ + 23671 LUT4 0007 cd/AB\ + 23672 LUT4 5300 D(C?b:a) + 23673 LUT3 35 c?b:a + 23674 LUT3 35 c?b:a + 23675 LUT4 3A00 D(c?b:A) + 23676 LUT3 35 c?b:a + 23677 LUT4 0777 /AB\(d+c) + 23678 LUT3 8F (AB)+c + 23679 LUT3 80 ABC + 23680 LUT4 7000 CD/AB\ + 23681 LUT4 0777 /AB\(d+c) + 23682 LUT4 7000 CD/AB\ + 23683 LUT4 0777 /AB\(d+c) + 23684 LUT3 70 C/AB\ + 23685 LUT4 7000 CD/AB\ + 23686 LUT4 0700 cD/AB\ + 23687 LUT4 0007 cd/AB\ + 23688 LUT4 3A00 D(c?b:A) + 23689 LUT3 35 c?b:a + 23690 LUT4 5300 D(C?b:a) + 23691 LUT3 35 c?b:a + 23692 LUT3 35 c?b:a + 23693 LUT4 0777 /AB\(d+c) + 23694 LUT4 0777 /AB\(d+c) + 23695 LUT4 0777 /AB\(d+c) + 23696 LUT4 8FFF (AB)+c+d + 23697 LUT4 7000 CD/AB\ + 23698 LUT4 7000 CD/AB\ + 23699 LUT4 0777 /AB\(d+c) + 23700 LUT4 7000 CD/AB\ + 23701 LUT4 0007 cd/AB\ + 23702 LUT2 8 AB + 23703 LUT2 8 AB + 23704 LUT4 7000 CD/AB\ + 23705 LUT4 0700 cD/AB\ + 23706 LUT4 0BBB /aB\(d+c) + 23707 LUT3 AC c?A:B + 23708 LUT4 0BBB /aB\(d+c) + 23709 LUT3 C5 C?a:B + 23710 LUT4 0777 /AB\(d+c) + 23711 LUT4 0777 /AB\(d+c) + 23712 LUT4 0777 /AB\(d+c) + 23713 LUT4 7000 CD/AB\ + 23714 LUT4 0700 cD/AB\ + 23715 LUT4 0007 cd/AB\ + 23716 LUT2 8 AB + 23717 LUT4 5300 D(C?b:a) + 23718 LUT3 70 C/AB\ + 23719 LUT3 70 C/AB\ + 23720 LUT4 0BBB /aB\(d+c) + 23721 LUT3 C5 C?a:B + 23722 LUT4 0777 /AB\(d+c) + 23723 LUT4 0777 /AB\(d+c) + 23724 LUT3 8F (AB)+c + 23725 LUT3 80 ABC + 23726 LUT4 0777 /AB\(d+c) + 23727 LUT4 0777 /AB\(d+c) + 23728 LUT4 7000 CD/AB\ + 23729 LUT4 0777 /AB\(d+c) + 23730 LUT4 7000 CD/AB\ + 23731 LUT3 70 C/AB\ + 23732 LUT4 7000 CD/AB\ + 23733 LUT3 70 C/AB\ + 23734 LUT4 0700 cD/AB\ + 23735 LUT3 0D c/Ab\ + 23736 LUT3 C5 C?a:B + 23737 LUT4 5300 D(C?b:a) + 23738 LUT4 0777 /AB\(d+c) + 23739 LUT4 0777 /AB\(d+c) + 23740 LUT4 0777 /AB\(d+c) + 23741 LUT4 0777 /AB\(d+c) + 23742 LUT4 0777 /AB\(d+c) + 23743 LUT4 7000 CD/AB\ + 23744 LUT4 0777 /AB\(d+c) + 23745 LUT4 0007 cd/AB\ + 23746 LUT2 8 AB + 23747 LUT4 3A00 D(c?b:A) + 23748 LUT4 0007 cd/AB\ + 23749 LUT4 3500 D(c?b:a) + 23750 LUT4 0777 /AB\(d+c) + 23751 LUT3 7F /AB\+c + 23752 LUT3 70 C/AB\ + 23753 LUT4 0777 /AB\(d+c) + 23754 LUT4 7000 CD/AB\ + 23755 LUT4 0777 /AB\(d+c) + 23756 LUT4 7000 CD/AB\ + 23757 LUT4 0777 /AB\(d+c) + 23758 LUT4 7000 CD/AB\ + 23759 LUT4 7000 CD/AB\ + 23760 LUT2 1 ab + 23761 LUT2 8 AB + 23762 LUT3 70 C/AB\ + 23763 LUT3 07 c/AB\ + 23764 LUT4 3500 D(c?b:a) + 23765 LUT4 0777 /AB\(d+c) + 23766 LUT4 0777 /AB\(d+c) + 23767 LUT4 7000 CD/AB\ + 23768 LUT4 7000 CD/AB\ + 23769 LUT4 0777 /AB\(d+c) + 23770 LUT4 0700 cD/AB\ + 23771 LUT4 0777 /AB\(d+c) + 23772 LUT4 3500 D(c?b:a) + 23773 LUT4 0777 /AB\(d+c) + 23774 LUT4 0777 /AB\(d+c) + 23775 LUT4 0777 /AB\(d+c) + 23776 LUT3 8F (AB)+c + 23777 LUT3 80 ABC + 23778 LUT4 0777 /AB\(d+c) + 23779 LUT4 0777 /AB\(d+c) + 23780 LUT4 7000 CD/AB\ + 23781 LUT4 0777 /AB\(d+c) + 23782 LUT4 7000 CD/AB\ + 23783 LUT3 70 C/AB\ + 23784 LUT4 7000 CD/AB\ + 23785 LUT4 7000 CD/AB\ + 23786 LUT3 07 c/AB\ + 23787 LUT4 3500 D(c?b:a) + 23788 LUT4 0777 /AB\(d+c) + 23789 LUT4 0777 /AB\(d+c) + 23790 LUT3 8F (AB)+c + 23791 LUT3 80 ABC + 23792 LUT4 0777 /AB\(d+c) + 23793 LUT4 0777 /AB\(d+c) + 23794 LUT4 7000 CD/AB\ + 23795 LUT4 0777 /AB\(d+c) + 23796 LUT4 8000 ABCD + 23797 LUT4 0777 /AB\(d+c) + 23798 LUT3 70 C/AB\ + 23799 LUT4 0007 cd/AB\ + 23800 LUT2 8 AB + 23801 LUT4 5300 D(C?b:a) + 23802 LUT4 0700 cD/AB\ + 23803 LUT2 8 AB + 23804 LUT4 0777 /AB\(d+c) + 23805 LUT3 8F (AB)+c + 23806 LUT3 80 ABC + 23807 LUT4 0777 /AB\(d+c) + 23808 LUT4 0777 /AB\(d+c) + 23809 LUT4 7000 CD/AB\ + 23810 LUT4 0777 /AB\(d+c) + 23811 LUT3 70 C/AB\ + 23812 LUT4 7000 CD/AB\ + 23813 LUT4 7000 CD/AB\ + 23814 LUT4 0777 /AB\(d+c) + 23815 LUT4 0700 cD/AB\ + 23816 LUT4 0007 cd/AB\ + 23817 LUT4 5300 D(C?b:a) + 23818 LUT4 0777 /AB\(d+c) + 23819 LUT3 8F (AB)+c + 23820 LUT3 80 ABC + 23821 LUT4 0777 /AB\(d+c) + 23822 LUT4 0777 /AB\(d+c) + 23823 LUT4 7000 CD/AB\ + 23824 LUT4 0777 /AB\(d+c) + 23825 LUT4 8000 ABCD + 23826 LUT4 0777 /AB\(d+c) + 23827 LUT3 70 C/AB\ + 23828 LUT4 0007 cd/AB\ + 23829 LUT2 8 AB + 23830 LUT4 5300 D(C?b:a) + 23831 LUT4 0700 cD/AB\ + 23832 LUT2 8 AB + 23833 LUT4 0777 /AB\(d+c) + 23834 LUT4 8FFF (AB)+c+d + 23835 LUT4 7000 CD/AB\ + 23836 LUT4 0777 /AB\(d+c) + 23837 LUT4 0777 /AB\(d+c) + 23838 LUT4 7000 CD/AB\ + 23839 LUT4 0777 /AB\(d+c) + 23840 LUT3 70 C/AB\ + 23841 LUT4 0700 cD/AB\ + 23842 LUT4 7000 CD/AB\ + 23843 LUT4 0700 cD/AB\ + 23844 LUT4 0007 cd/AB\ + 23845 LUT4 5300 D(C?b:a) + 23846 LUT4 0777 /AB\(d+c) + 23847 LUT2 8 AB + 23848 LUT4 8FFF (AB)+c+d + 23849 LUT4 7000 CD/AB\ + 23850 LUT4 0777 /AB\(d+c) + 23851 LUT4 0777 /AB\(d+c) + 23852 LUT3 70 C/AB\ + 23853 LUT4 7000 CD/AB\ + 23854 LUT4 0777 /AB\(d+c) + 23855 LUT3 70 C/AB\ + 23856 LUT3 70 C/AB\ + 23857 LUT4 7000 CD/AB\ + 23858 LUT4 0700 cD/AB\ + 23859 LUT4 0007 cd/AB\ + 23860 LUT4 5300 D(C?b:a) + 23861 LUT4 0777 /AB\(d+c) + 23862 LUT3 8F (AB)+c + 23863 LUT3 80 ABC + 23864 LUT4 0777 /AB\(d+c) + 23865 LUT4 0777 /AB\(d+c) + 23866 LUT4 7000 CD/AB\ + 23867 LUT4 0777 /AB\(d+c) + 23868 LUT4 7000 CD/AB\ + 23869 LUT3 70 C/AB\ + 23870 LUT4 7000 CD/AB\ + 23871 LUT4 D000 CD/Ab\ + 23872 LUT4 0777 /AB\(d+c) + 23873 LUT4 0777 /AB\(d+c) + 23874 LUT4 0777 /AB\(d+c) + 23875 LUT3 8F (AB)+c + 23876 LUT3 80 ABC + 23877 LUT4 0777 /AB\(d+c) + 23878 LUT4 0777 /AB\(d+c) + 23879 LUT4 7000 CD/AB\ + 23880 LUT4 0777 /AB\(d+c) + 23881 LUT4 7000 CD/AB\ + 23882 LUT3 70 C/AB\ + 23883 LUT4 7000 CD/AB\ + 23884 LUT4 7000 CD/AB\ + 23885 LUT3 07 c/AB\ + 23886 LUT4 3A00 D(c?b:A) + 23887 LUT4 0777 /AB\(d+c) + 23888 LUT4 0777 /AB\(d+c) + 23889 LUT4 0777 /AB\(d+c) + 23890 LUT4 0700 cD/AB\ + 23891 LUT2 8 AB + 23892 LUT4 7000 CD/AB\ + 23893 LUT4 0700 cD/AB\ + 23894 LUT4 0007 cd/AB\ + 23895 LUT4 3A00 D(c?b:A) + 23896 LUT4 0777 /AB\(d+c) + 23897 LUT4 0777 /AB\(d+c) + 23898 LUT4 0777 /AB\(d+c) + 23899 LUT4 0777 /AB\(d+c) + 23900 LUT4 0777 /AB\(d+c) + 23901 LUT3 70 C/AB\ + 23902 LUT3 70 C/AB\ + 23903 LUT4 7000 CD/AB\ + 23904 LUT4 0700 cD/AB\ + 23905 LUT4 0007 cd/AB\ + 23906 LUT4 3A00 D(c?b:A) + 23907 LUT4 0777 /AB\(d+c) + 23908 LUT4 0777 /AB\(d+c) + 23909 LUT3 70 C/AB\ + 23910 LUT3 70 C/AB\ + 23911 LUT4 7000 CD/AB\ + 23912 LUT4 7000 CD/AB\ + 23913 LUT4 0BBB /aB\(d+c) + 23914 LUT4 0777 /AB\(d+c) + 23915 LUT4 0777 /AB\(d+c) + 23916 LUT4 0777 /AB\(d+c) + 23917 LUT4 0777 /AB\(d+c) + 23918 LUT3 8F (AB)+c + 23919 LUT3 80 ABC + 23920 LUT4 0777 /AB\(d+c) + 23921 LUT4 0777 /AB\(d+c) + 23922 LUT4 7000 CD/AB\ + 23923 LUT4 0777 /AB\(d+c) + 23924 LUT4 7000 CD/AB\ + 23925 LUT3 70 C/AB\ + 23926 LUT4 7000 CD/AB\ + 23927 LUT4 7000 CD/AB\ + 23928 LUT4 0BBB /aB\(d+c) + 23929 LUT4 0777 /AB\(d+c) + 23930 LUT4 0777 /AB\(d+c) + 23931 LUT3 8F (AB)+c + 23932 LUT3 80 ABC + 23933 LUT4 0777 /AB\(d+c) + 23934 LUT4 0777 /AB\(d+c) + 23935 LUT4 7000 CD/AB\ + 23936 LUT4 0777 /AB\(d+c) + 23937 LUT4 7000 CD/AB\ + 23938 LUT3 70 C/AB\ + 23939 LUT4 7000 CD/AB\ + 23940 LUT4 7000 CD/AB\ + 23941 LUT4 0BBB /aB\(d+c) + 23942 LUT4 0777 /AB\(d+c) + 23943 LUT4 0777 /AB\(d+c) + 23944 LUT3 7F /AB\+c + 23945 LUT3 70 C/AB\ + 23946 LUT4 0777 /AB\(d+c) + 23947 LUT4 7000 CD/AB\ + 23948 LUT4 0777 /AB\(d+c) + 23949 LUT4 7000 CD/AB\ + 23950 LUT3 70 C/AB\ + 23951 LUT4 7000 CD/AB\ + 23952 LUT4 7000 CD/AB\ + 23953 LUT3 07 c/AB\ + 23954 LUT4 3A00 D(c?b:A) + 23955 LUT4 0777 /AB\(d+c) + 23956 LUT4 0777 /AB\(d+c) + 23957 LUT4 0777 /AB\(d+c) + 23958 LUT3 8F (AB)+c + 23959 LUT4 4000 aBCD + 23960 LUT3 80 ABC + 23961 LUT2 4 aB + 23962 LUT3 80 ABC + 23963 LUT4 0777 /AB\(d+c) + 23964 LUT4 0777 /AB\(d+c) + 23965 LUT4 7000 CD/AB\ + 23966 LUT4 0777 /AB\(d+c) + 23967 LUT4 7000 CD/AB\ + 23968 LUT3 70 C/AB\ + 23969 LUT4 0700 cD/AB\ + 23970 LUT4 7000 CD/AB\ + 23971 LUT3 07 c/AB\ + 23972 LUT4 0777 /AB\(d+c) + 23973 LUT2 8 AB + 23974 LUT4 0777 /AB\(d+c) + 23975 LUT3 8F (AB)+c + 23976 LUT3 80 ABC + 23977 LUT4 0777 /AB\(d+c) + 23978 LUT4 0777 /AB\(d+c) + 23979 LUT4 7000 CD/AB\ + 23980 LUT4 0777 /AB\(d+c) + 23981 LUT4 7000 CD/AB\ + 23982 LUT3 70 C/AB\ + 23983 LUT4 0700 cD/AB\ + 23984 LUT4 7000 CD/AB\ + 23985 LUT4 0777 /AB\(d+c) + 23986 LUT2 8 AB + 23987 LUT4 0777 /AB\(d+c) + 23988 LUT3 8F (AB)+c + 23989 LUT3 80 ABC + 23990 LUT4 0777 /AB\(d+c) + 23991 LUT4 0777 /AB\(d+c) + 23992 LUT4 7000 CD/AB\ + 23993 LUT4 0777 /AB\(d+c) + 23994 LUT4 7000 CD/AB\ + 23995 LUT3 70 C/AB\ + 23996 LUT4 7000 CD/AB\ + 23997 LUT4 0700 cD/AB\ + 23998 LUT2 8 AB + 23999 LUT4 0777 /AB\(d+c) + 24000 LUT4 0777 /AB\(d+c) + 24001 LUT3 8F (AB)+c + 24002 LUT3 80 ABC + 24003 LUT4 0777 /AB\(d+c) + 24004 LUT4 0777 /AB\(d+c) + 24005 LUT4 7000 CD/AB\ + 24006 LUT4 0777 /AB\(d+c) + 24007 LUT4 7000 CD/AB\ + 24008 LUT3 70 C/AB\ + 24009 LUT4 7000 CD/AB\ + 24010 LUT4 0700 cD/AB\ + 24011 LUT2 8 AB + 24012 LUT4 0777 /AB\(d+c) + 24013 LUT4 0777 /AB\(d+c) + 24014 LUT3 F8 (AB)+C + 24015 LUT4 1000 abCD + 24016 LUT3 F4 (aB)+C + 24017 LUT4 1000 abCD + 24018 LUT3 F4 (aB)+C + 24019 LUT4 1000 abCD + 24020 LUT3 F4 (aB)+C + 24021 LUT4 1000 abCD + 24022 LUT3 4F (aB)+c + 24023 LUT4 0777 /AB\(d+c) + 24024 LUT2 1 ab + 24025 LUT3 35 c?b:a + 24026 LUT3 4F (aB)+c + 24027 LUT4 0777 /AB\(d+c) + 24028 LUT2 1 ab + 24029 LUT3 35 c?b:a + 24030 LUT4 10FF (abC)+d + 24031 LUT4 7077 /AB\(d+C) + 24032 LUT3 35 c?b:a + 24033 LUT3 8F (AB)+c + 24034 LUT3 0D c/Ab\ + 24035 LUT3 10 abC + 24036 LUT3 35 c?b:a + 24037 LUT3 4F (aB)+c + 24038 LUT4 0BBB /aB\(d+c) + 24039 LUT4 BBF0 D?C:/aB\ + 24040 LUT3 4F (aB)+c + 24041 LUT4 0BBB /aB\(d+c) + 24042 LUT4 BBF0 D?C:/aB\ + 24043 LUT3 4F (aB)+c + 24044 LUT4 0BBB /aB\(d+c) + 24045 LUT4 BBF0 D?C:/aB\ + 24046 LUT3 4F (aB)+c + 24047 LUT4 0BBB /aB\(d+c) + 24048 LUT4 BBF0 D?C:/aB\ + 24049 LUT3 4F (aB)+c + 24050 LUT3 07 c/AB\ + 24051 LUT4 5300 D(C?b:a) + 24052 LUT3 4F (aB)+c + 24053 LUT3 07 c/AB\ + 24054 LUT4 5300 D(C?b:a) + 24055 LUT3 4F (aB)+c + 24056 LUT3 07 c/AB\ + 24057 LUT4 5300 D(C?b:a) + 24058 LUT3 4F (aB)+c + 24059 LUT3 07 c/AB\ + 24060 LUT4 5300 D(C?b:a) + 24061 LUT4 F2FF (Ab)+C+d + 24062 LUT3 07 c/AB\ + 24063 LUT4 1000 abCD + 24064 LUT4 5300 D(C?b:a) + 24065 LUT4 F2FF (Ab)+C+d + 24066 LUT3 07 c/AB\ + 24067 LUT4 1000 abCD + 24068 LUT4 5300 D(C?b:a) + 24069 LUT4 F2FF (Ab)+C+d + 24070 LUT3 07 c/AB\ + 24071 LUT4 1000 abCD + 24072 LUT4 5300 D(C?b:a) + 24073 LUT4 F2FF (Ab)+C+d + 24074 LUT3 07 c/AB\ + 24075 LUT4 1000 abCD + 24076 LUT4 5300 D(C?b:a) + 24077 LUT3 4F (aB)+c + 24078 LUT3 70 C/AB\ + 24079 LUT4 5CFF (c?a:B)+d + 24080 LUT4 F2FF (Ab)+C+d + 24081 LUT4 0777 /AB\(d+c) + 24082 LUT4 5300 D(C?b:a) + 24083 LUT3 4F (aB)+c + 24084 LUT4 0007 cd/AB\ + 24085 LUT4 5300 D(C?b:a) + 24086 LUT3 10 abC + 24087 LUT4 F2FF (Ab)+C+d + 24088 LUT3 07 c/AB\ + 24089 LUT4 5300 D(C?b:a) + 24090 LUT3 10 abC + 24091 LUT4 F2FF (Ab)+C+d + 24092 LUT4 0BBB /aB\(d+c) + 24093 LUT2 4 aB + 24094 LUT3 4F (aB)+c + 24095 LUT3 70 C/AB\ + 24096 LUT3 0D c/Ab\ + 24097 LUT4 5300 D(C?b:a) + 24098 LUT3 4F (aB)+c + 24099 LUT3 70 C/AB\ + 24100 LUT3 0D c/Ab\ + 24101 LUT4 5300 D(C?b:a) + 24102 LUT4 F2FF (Ab)+C+d + 24103 LUT4 0BBB /aB\(d+c) + 24104 LUT4 3500 D(c?b:a) + 24105 LUT4 F2FF (Ab)+C+d + 24106 LUT3 07 c/AB\ + 24107 LUT4 5300 D(C?b:a) + 24108 LUT4 3500 D(c?b:a) + 24109 LUT4 F2FF (Ab)+C+d + 24110 LUT3 07 c/AB\ + 24111 LUT4 3500 D(c?b:a) + 24112 LUT4 5300 D(C?b:a) + 24113 LUT4 F2FF (Ab)+C+d + 24114 LUT3 07 c/AB\ + 24115 LUT4 5300 D(C?b:a) + 24116 LUT4 3500 D(c?b:a) + 24117 LUT4 F2FF (Ab)+C+d + 24118 LUT3 07 c/AB\ + 24119 LUT4 5300 D(C?b:a) + 24120 LUT4 5300 D(C?b:a) + 24121 LUT2 E /ab\ + 24122 LUT3 A3 C?b:A + 24123 LUT3 A3 C?b:A + 24124 LUT3 A3 C?b:A + 24125 LUT3 A3 C?b:A + 24126 LUT3 A3 C?b:A + 24127 LUT3 A3 C?b:A + 24128 LUT3 A3 C?b:A + 24129 LUT3 A3 C?b:A + 24130 LUT3 A3 C?b:A + 24131 LUT3 A3 C?b:A + 24132 LUT3 A3 C?b:A + 24133 LUT3 A3 C?b:A + 24134 LUT3 A3 C?b:A + 24135 LUT3 A3 C?b:A + 24136 LUT3 A3 C?b:A + 24137 LUT3 A3 C?b:A + 24138 LUT3 A3 C?b:A + 24139 LUT3 A3 C?b:A + 24140 LUT3 A3 C?b:A + 24141 LUT3 A3 C?b:A + 24142 LUT3 A3 C?b:A + 24143 LUT3 A3 C?b:A + 24144 LUT3 A3 C?b:A + 24145 LUT3 A3 C?b:A + 24146 LUT3 C5 C?a:B + 24147 LUT3 C5 C?a:B + 24148 LUT3 C5 C?a:B + 24149 LUT3 C5 C?a:B + 24150 LUT3 C5 C?a:B + 24151 LUT3 C5 C?a:B + 24152 LUT3 C5 C?a:B + 24153 LUT4 3C55 D?a:B^C + 24154 LUT4 FF01 (abc)+D + 24155 LUT3 10 abC + 24156 LUT3 8F (AB)+c + 24157 LUT3 80 ABC + 24158 LUT4 0777 /AB\(d+c) + 24159 LUT4 0777 /AB\(d+c) + 24160 LUT4 7000 CD/AB\ + 24161 LUT4 0777 /AB\(d+c) + 24162 LUT4 8000 ABCD + 24163 LUT4 0777 /AB\(d+c) + 24164 LUT3 70 C/AB\ + 24165 LUT4 0777 /AB\(d+c) + 24166 LUT3 70 C/AB\ + 24167 LUT4 0777 /AB\(d+c) + 24168 LUT3 0E c/ab\ + 24169 LUT2 8 AB + 24170 LUT2 8 AB + 24171 LUT2 4 aB + 24172 LUT3 10 abC + 24173 LUT4 FF70 (C/AB\)+D + 24174 LUT4 4000 aBCD + 24175 LUT4 4300 D(BC?1:0:0:a) + 24176 LUT4 0001 abcd + 24177 LUT4 FA30 DC?0:A:b:1 + 24178 LUT3 0B c/aB\ + 24179 LUT4 7000 CD/AB\ + 24180 LUT4 1000 abCD + 24181 LUT4 CFFD BD?/Ac\:1:c:1 + 24182 LUT3 80 ABC + 24183 LUT2 4 aB + 24184 LUT4 F0BA AC?0:d:/Bd\:1 + 24185 LUT4 0BBB /aB\(d+c) + 24186 LUT2 1 ab + 24187 LUT4 B0BB /aB\(d+C) + 24188 LUT4 7150 AC?bD:0:1:bD + 24189 LUT3 D0 C/Ab\ + 24190 LUT4 FFE0 (C/ab\)+D + 24191 LUT4 0BBB /aB\(d+c) + 24192 LUT4 0D00 cD/Ab\ + 24193 LUT4 0100 abcD + 24194 LUT4 FFF1 (ab)+C+D + 24195 LUT4 1000 abCD + 24196 LUT3 F4 (aB)+C + 24197 LUT3 F4 (aB)+C + 24198 LUT3 F4 (aB)+C + 24199 LUT3 F4 (aB)+C + 24200 LUT3 F4 (aB)+C + 24201 LUT3 F4 (aB)+C + 24202 LUT3 F4 (aB)+C + 24203 LUT3 F4 (aB)+C + 24204 LUT3 F4 (aB)+C + 24205 LUT3 F4 (aB)+C + 24206 LUT3 F4 (aB)+C + 24207 LUT3 F4 (aB)+C + 24208 LUT3 F4 (aB)+C + 24209 LUT3 F4 (aB)+C + 24210 LUT3 F4 (aB)+C + 24211 LUT3 F4 (aB)+C + 24212 LUT3 F4 (aB)+C + 24213 LUT3 F4 (aB)+C + 24214 LUT3 F4 (aB)+C + 24215 LUT3 F4 (aB)+C + 24216 LUT3 F4 (aB)+C + 24217 LUT3 F4 (aB)+C + 24218 LUT3 F4 (aB)+C + 24219 LUT3 F4 (aB)+C + 24220 LUT3 F4 (aB)+C + 24221 LUT3 F4 (aB)+C + 24222 LUT3 F4 (aB)+C + 24223 LUT3 F4 (aB)+C + 24224 LUT1 1 a deleted + 24225 LUT1 1 a deleted + 24226 LUT1 1 a deleted + 24227 LUT1 1 a deleted + 24228 LUT1 1 a deleted + 24229 LUT1 1 a deleted + 24230 LUT1 1 a deleted + 24231 LUT1 1 a deleted + 24232 LUT1 1 a deleted + 24233 LUT1 1 a deleted + 24234 LUT1 1 a deleted + 24235 LUT1 1 a deleted + 24236 LUT1 1 a deleted + 24237 LUT1 1 a deleted + 24238 LUT1 1 a deleted + 24239 LUT1 1 a deleted + 24240 LUT1 1 a deleted + 24241 LUT1 1 a deleted + 24242 LUT1 1 a deleted + 24243 LUT1 1 a deleted + 24244 LUT1 1 a deleted + 24245 LUT1 1 a deleted + 24246 LUT1 1 a deleted + 24247 LUT1 1 a deleted + 24248 LUT1 1 a deleted + 24249 LUT1 1 a deleted + 24250 LUT1 1 a deleted + 24251 LUT1 1 a deleted + 24252 LUT1 1 a deleted + 24253 LUT1 1 a deleted + 24254 LUT1 1 a deleted + 24255 LUT1 1 a deleted + 24256 LUT1 1 a deleted + 24257 LUT1 1 a deleted + 24258 LUT1 1 a deleted + 24259 LUT1 1 a deleted + 24260 LUT1 1 a deleted + 24261 LUT1 1 a deleted + 24262 LUT1 1 a deleted + 24263 LUT1 1 a deleted + 24264 LUT1 1 a deleted + 24265 LUT1 1 a deleted + 24266 LUT1 1 a deleted + 24267 LUT1 1 a deleted + 24268 LUT1 1 a deleted + 24269 LUT1 1 a deleted + 24270 LUT1 1 a deleted + 24271 LUT1 1 a deleted + 24272 LUT1 1 a deleted + 24273 LUT1 1 a deleted + 24274 LUT1 1 a deleted + 24275 LUT1 1 a deleted + 24276 LUT1 1 a deleted + 24277 LUT1 1 a deleted + 24278 LUT1 1 a deleted + 24279 LUT1 1 a deleted + 24280 LUT1 1 a deleted + 24281 LUT1 1 a deleted + 24282 LUT1 1 a deleted + 24283 LUT1 1 a deleted + 24284 LUT1 1 a deleted + 24285 LUT1 1 a deleted + 24286 LUT1 1 a deleted + 24287 LUT1 1 a deleted + 24288 LUT1 1 a deleted + 24289 LUT1 1 a deleted + 24290 LUT1 1 a deleted + 24291 LUT1 1 a deleted + 24292 LUT1 1 a deleted + 24293 LUT1 1 a deleted + 24294 LUT1 1 a deleted + 24295 LUT1 1 a deleted + 24296 LUT1 1 a deleted + 24297 LUT1 1 a deleted + 24298 LUT1 1 a deleted + 24299 LUT1 1 a deleted + 24300 LUT1 1 a deleted + 24301 LUT1 1 a deleted + 24302 LUT1 1 a deleted + 24303 LUT1 1 a deleted + 24304 LUT1 1 a deleted + 24305 LUT1 1 a deleted + 24306 LUT1 1 a deleted + 24307 LUT1 1 a deleted + 24308 LUT1 1 a deleted + 24309 LUT1 1 a deleted + 24310 LUT1 1 a deleted + 24311 LUT1 1 a deleted + 24312 LUT1 1 a deleted + 24313 LUT1 1 a deleted + 24314 LUT1 1 a deleted + 24315 LUT1 1 a deleted + 24316 LUT1 1 a deleted + 24317 LUT1 1 a deleted + 24318 LUT1 1 a deleted + 24319 LUT1 1 a deleted + 24320 LUT1 1 a deleted + 24321 LUT1 1 a deleted + 24322 LUT1 1 a deleted + 24323 LUT1 1 a deleted + 24324 LUT1 1 a deleted + 24325 LUT1 1 a deleted + 24326 LUT1 1 a deleted + 24327 LUT1 1 a deleted + 24328 LUT1 1 a deleted + 24329 LUT1 1 a deleted + 24330 LUT1 1 a deleted + 24331 LUT1 1 a deleted + 24332 LUT1 1 a deleted + 24333 LUT1 1 a deleted + 24334 LUT1 1 a deleted + 24335 LUT1 1 a deleted + 24336 LUT1 1 a deleted + 24337 LUT1 1 a deleted + 24338 LUT1 1 a deleted + 24339 LUT1 1 a deleted + 24340 LUT1 1 a deleted + 24341 LUT1 1 a deleted + 24342 LUT1 1 a deleted + 24343 LUT1 1 a deleted + 24344 LUT1 1 a deleted + 24345 LUT1 1 a deleted + 24346 LUT1 1 a deleted + 24347 LUT1 1 a deleted + 24348 LUT1 1 a deleted + 24349 LUT1 1 a deleted + 24350 LUT1 1 a deleted + 24351 LUT1 1 a deleted + 24352 LUT1 1 a deleted + 24353 LUT1 1 a deleted + 24354 LUT1 1 a deleted + 24355 LUT1 1 a deleted + 24356 LUT1 1 a deleted + 24357 LUT1 1 a deleted + 24358 LUT1 1 a deleted + 24359 LUT1 1 a deleted + 24360 LUT1 1 a deleted + 24361 LUT1 1 a deleted + 24362 LUT1 1 a deleted + 24363 LUT1 1 a deleted + 24364 LUT1 1 a deleted + 24365 LUT1 1 a deleted + 24366 LUT1 1 a deleted + 24367 LUT1 1 a deleted + 24368 LUT1 1 a deleted + 24369 LUT1 1 a deleted + 24370 LUT1 1 a deleted + 24371 LUT1 1 a deleted + 24372 LUT1 1 a deleted + 24373 LUT1 1 a deleted + 24374 LUT1 1 a deleted + 24375 LUT1 1 a deleted + 24376 LUT1 1 a deleted + 24377 LUT1 1 a deleted + 24378 LUT1 1 a deleted + 24379 LUT1 1 a deleted + 24380 LUT1 1 a deleted + 24381 LUT1 1 a deleted + 24382 LUT1 1 a deleted + 24383 LUT1 1 a deleted + 24384 LUT1 1 a deleted + 24385 LUT1 1 a deleted + 24386 LUT1 1 a deleted + 24387 LUT1 1 a deleted + 24388 LUT1 1 a deleted + 24389 LUT1 1 a deleted + 24390 LUT1 1 a deleted + 24391 LUT1 1 a deleted + 24392 LUT1 1 a deleted + 24393 LUT1 1 a deleted + 24394 LUT1 1 a deleted + 24395 LUT1 1 a deleted + 24396 LUT1 1 a deleted + 24397 LUT1 1 a deleted + 24398 LUT1 1 a deleted + 24399 LUT1 1 a deleted + 24400 LUT1 1 a deleted + 24401 LUT1 1 a deleted + 24402 LUT1 1 a deleted + 24403 LUT1 1 a deleted + 24404 LUT1 1 a deleted + 24405 LUT1 1 a deleted + 24406 LUT1 1 a deleted + 24407 LUT4 F888 (AB)+(CD) + 24408 LUT4 0700 cD/AB\ + 24409 LUT4 B000 CD/aB\ + 24410 LUT4 008F ((AB)+c)d + 24411 LUT4 8F30 DC?0:1:b:AB + 24412 LUT4 0001 abcd + 24413 LUT4 8F00 ((AB)+c)D + 24414 LUT4 9009 (a^B)(D^c) + 24415 LUT4 8000 ABCD + 24416 LUT4 8001 AB?cd:0:0:CD + 24417 LUT4 8001 AB?cd:0:0:CD + 24418 LUT4 8001 AB?cd:0:0:CD + 24419 LUT4 8001 AB?cd:0:0:CD + 24420 LUT4 8001 AB?cd:0:0:CD + 24421 LUT4 9000 CD(a^B) + 24422 LUT4 8000 ABCD + 24423 LUT4 8000 ABCD + 24424 LUT4 0700 cD/AB\ + 24425 LUT4 B00B /aB\/D^C\ + 24426 LUT4 9000 CD(a^B) + 24427 LUT4 8000 ABCD + 24428 LUT4 8000 ABCD + 24429 LUT4 8001 AB?cd:0:0:CD + 24430 LUT4 8001 AB?cd:0:0:CD + 24431 LUT4 8001 AB?cd:0:0:CD + 24432 LUT4 8001 AB?cd:0:0:CD + 24433 LUT4 8001 AB?cd:0:0:CD + 24434 LUT4 3500 D(c?b:a) + 24435 LUT4 A35C (c?a:B)^D + 24436 LUT4 F088 D?AB:C + 24437 LUT3 F8 (AB)+C + 24438 LUT3 E1 (ab)^C + 24439 LUT4 A35C (c?a:B)^D + 24440 LUT4 7F00 ((/AB\)+c)D + 24441 LUT4 FF40 (aBC)+D + 24442 LUT4 F0BB D?/aB\:C + 24443 LUT4 7077 /AB\(d+C) + 24444 LUT4 0EC0 DC?0:/ab\:B:0 + 24445 LUT4 50CF DC?1:0:B:a + 24446 LUT4 00D7 AD?1:b^C:0:0 + 24447 LUT4 70CC BD?0:1:C:aC + 24448 LUT4 CC70 BD?C:aC:0:1 + 24449 LUT3 CA C?A:B + 24450 LUT3 CA C?A:B + 24451 LUT4 8F70 (C/AB\)^D + 24452 LUT4 70CC BD?0:1:C:aC + 24453 LUT4 CC70 BD?C:aC:0:1 + 24454 LUT3 CA C?A:B + 24455 LUT4 1428 (B^C)(A^D) + 24456 LUT4 DCAF AD?c:1:/bc\:B + 24457 LUT3 07 c/AB\ + 24458 LUT4 9009 (a^B)(D^c) + 24459 LUT4 9009 (a^B)(D^c) + 24460 LUT4 8000 ABCD + 24461 LUT3 40 aBC + 24462 LUT4 9009 (a^B)(D^c) + 24463 LUT4 8000 ABCD + 24464 LUT4 8000 ABCD + 24465 LUT4 9009 (a^B)(D^c) + 24466 LUT4 9009 (a^B)(D^c) + 24467 LUT4 8000 ABCD + 24468 LUT4 8000 ABCD + 24469 LUT4 9009 (a^B)(D^c) + 24470 LUT4 B0BB /aB\(d+C) + 24471 LUT4 1000 abCD + 24472 LUT4 8000 ABCD + 24473 LUT4 9009 (a^B)(D^c) + 24474 LUT4 9009 (a^B)(D^c) + 24475 LUT4 9000 CD(a^B) + 24476 LUT4 9009 (a^B)(D^c) + 24477 LUT4 D000 CD/Ab\ + 24478 LUT4 9000 CD(a^B) + 24479 LUT4 9009 (a^B)(D^c) + 24480 LUT4 B00B /aB\/D^C\ + 24481 LUT4 4000 aBCD + 24482 LUT4 D000 CD/Ab\ + 24483 LUT4 9009 (a^B)(D^c) + 24484 LUT4 4000 aBCD + 24485 LUT4 1428 (B^C)(A^D) + 24486 LUT4 0EE0 (A+B)(C^D) + 24487 LUT4 8000 ABCD + 24488 LUT4 1000 abCD + 24489 LUT4 9009 (a^B)(D^c) + 24490 LUT4 B00B /aB\/D^C\ + 24491 LUT4 9009 (a^B)(D^c) + 24492 LUT4 B000 CD/aB\ + 24493 LUT4 8000 ABCD + 24494 LUT4 8000 ABCD + 24495 LUT4 9009 (a^B)(D^c) + 24496 LUT4 B00B /aB\/D^C\ + 24497 LUT4 9009 (a^B)(D^c) + 24498 LUT4 B00B /aB\/D^C\ + 24499 LUT4 4000 aBCD + 24500 LUT3 90 C(a^B) + 24501 LUT4 9000 CD(a^B) + 24502 LUT4 9000 CD(a^B) + 24503 LUT4 B00B /aB\/D^C\ + 24504 LUT4 8000 ABCD + 24505 LUT4 B00B /aB\/D^C\ + 24506 LUT4 9009 (a^B)(D^c) + 24507 LUT4 4F44 (aB)+(cD) + 24508 LUT4 7007 (c^D)/AB\ + 24509 LUT4 9009 (a^B)(D^c) + 24510 LUT4 B0BB /aB\(d+C) + 24511 LUT4 B033 BD?1:0:C:AC + 24512 LUT4 B00B /aB\/D^C\ + 24513 LUT4 9000 CD(a^B) + 24514 LUT4 B00B /aB\/D^C\ + 24515 LUT4 8000 ABCD + 24516 LUT4 4F44 (aB)+(cD) + 24517 LUT4 7000 CD/AB\ + 24518 LUT4 4F44 (aB)+(cD) + 24519 LUT4 0BBB /aB\(d+c) + 24520 LUT4 B00B /aB\/D^C\ + 24521 LUT4 9009 (a^B)(D^c) + 24522 LUT4 8000 ABCD + 24523 LUT4 B00B /aB\/D^C\ + 24524 LUT4 8000 ABCD + 24525 LUT4 B00B /aB\/D^C\ + 24526 LUT4 B00B /aB\/D^C\ + 24527 LUT4 9009 (a^B)(D^c) + 24528 LUT4 9009 (a^B)(D^c) + 24529 LUT4 1428 (B^C)(A^D) + 24530 LUT4 6000 CD(A^B) + 24531 LUT4 1000 abCD + 24532 LUT3 40 aBC + 24533 LUT4 F888 (AB)+(CD) + 24534 LUT4 0777 /AB\(d+c) + 24535 LUT4 F888 (AB)+(CD) + 24536 LUT4 77F0 D?C:/AB\ + 24537 LUT4 0700 cD/AB\ + 24538 LUT4 8000 ABCD + 24539 LUT4 C700 D(BC?1:a:0:1) + 24540 LUT4 F888 (AB)+(CD) + 24541 LUT4 0777 /AB\(d+c) + 24542 LUT4 0F88 D?AB:c + 24543 LUT4 F888 (AB)+(CD) + 24544 LUT4 7000 CD/AB\ + 24545 LUT4 C500 D(C?a:B) + 24546 LUT4 AC00 D(c?A:B) + 24547 LUT3 CA C?A:B + 24548 LUT4 0FBB D?/aB\:c + 24549 LUT4 0700 cD/AB\ + 24550 LUT4 8700 AD?0:0:c:b^C + 24551 LUT4 B00B /aB\/D^C\ + 24552 LUT4 9000 CD(a^B) + 24553 LUT4 4F44 (aB)+(cD) + 24554 LUT4 9009 (a^B)(D^c) + 24555 LUT4 B0BB /aB\(d+C) + 24556 LUT4 9009 (a^B)(D^c) + 24557 LUT4 9009 (a^B)(D^c) + 24558 LUT4 0B00 cD/aB\ + 24559 LUT4 1000 abCD + 24560 LUT4 8000 ABCD + 24561 LUT4 0100 abcD + 24562 LUT4 9000 CD(a^B) + 24563 LUT4 B00B /aB\/D^C\ + 24564 LUT4 8000 ABCD + 24565 LUT4 8000 ABCD + 24566 LUT4 B00B /aB\/D^C\ + 24567 LUT4 9000 CD(a^B) + 24568 LUT4 B00B /aB\/D^C\ + 24569 LUT4 B00B /aB\/D^C\ + 24570 LUT4 4000 aBCD + 24571 LUT4 9000 CD(a^B) + 24572 LUT4 B00B /aB\/D^C\ + 24573 LUT4 9009 (a^B)(D^c) + 24574 LUT4 1000 abCD + 24575 LUT2 8 AB + 24576 LUT4 B00B /aB\/D^C\ + 24577 LUT4 9000 CD(a^B) + 24578 LUT4 B00B /aB\/D^C\ + 24579 LUT4 9009 (a^B)(D^c) + 24580 LUT4 B00B /aB\/D^C\ + 24581 LUT4 9009 (a^B)(D^c) + 24582 LUT4 9000 CD(a^B) + 24583 LUT4 9009 (a^B)(D^c) + 24584 LUT4 0777 /AB\(d+c) + 24585 LUT4 0777 /AB\(d+c) + 24586 LUT4 70FF (C/AB\)+d + 24587 LUT3 70 C/AB\ + 24588 LUT4 CFA0 DC?0:1:A:B + 24589 LUT4 FC0A DC?A:B:0:1 + 24590 LUT4 F888 (AB)+(CD) + 24591 LUT4 F888 (AB)+(CD) + 24592 LUT4 F888 (AB)+(CD) + 24593 LUT4 0777 /AB\(d+c) + 24594 LUT4 8000 ABCD + 24595 LUT4 8000 ABCD + 24596 LUT4 0DCC BD?0:1:ac:c + 24597 LUT4 F305 DC?a:b:0:1 + 24598 LUT4 BF00 ((/aB\)+c)D + 24599 LUT3 CA C?A:B + 24600 LUT4 ACFF (c?A:B)+d + 24601 LUT2 4 aB + 24602 LUT4 F888 (AB)+(CD) + 24603 LUT4 F888 (AB)+(CD) + 24604 LUT4 7077 /AB\(d+C) + 24605 LUT3 80 ABC + 24606 LUT4 F888 (AB)+(CD) + 24607 LUT4 0777 /AB\(d+c) + 24608 LUT4 8000 ABCD + 24609 LUT4 8000 ABCD + 24610 LUT4 05F3 DC?b:a:1:0 + 24611 LUT4 07CC BD?0:1:c:ac + 24612 LUT4 BF00 ((/aB\)+c)D + 24613 LUT4 F888 (AB)+(CD) + 24614 LUT4 7000 CD/AB\ + 24615 LUT4 0777 /AB\(d+c) + 24616 LUT4 8000 ABCD + 24617 LUT4 CA00 D(C?A:B) + 24618 LUT4 0777 /AB\(d+c) + 24619 LUT4 4000 aBCD + 24620 LUT4 05F3 DC?b:a:1:0 + 24621 LUT4 07CC BD?0:1:c:ac + 24622 LUT4 BF00 ((/aB\)+c)D + 24623 LUT4 70CC BD?0:1:C:aC + 24624 LUT4 CC70 BD?C:aC:0:1 + 24625 LUT4 1400 D(B^C)a + 24626 LUT4 70CC BD?0:1:C:aC + 24627 LUT4 CC70 BD?C:aC:0:1 + 24628 LUT4 1000 abCD + 24629 LUT4 6000 CD(A^B) + 24630 LUT4 5A3C DC?B:A:b:a + 24631 LUT4 5A3C DC?B:A:b:a + 24632 LUT4 70CC BD?0:1:C:aC + 24633 LUT4 CC70 BD?C:aC:0:1 + 24634 LUT4 6000 CD(A^B) + 24635 LUT4 70CC BD?0:1:C:aC + 24636 LUT4 CC70 BD?C:aC:0:1 + 24637 LUT4 70CC BD?0:1:C:aC + 24638 LUT4 CC70 BD?C:aC:0:1 + 24639 LUT4 1428 (B^C)(A^D) + 24640 LUT4 70CC BD?0:1:C:aC + 24641 LUT4 CC70 BD?C:aC:0:1 + 24642 LUT4 70CC BD?0:1:C:aC + 24643 LUT4 CC70 BD?C:aC:0:1 + 24644 LUT4 5A3C DC?B:A:b:a + 24645 LUT4 35FF (c?b:a)+d + 24646 LUT4 70CC BD?0:1:C:aC + 24647 LUT4 CC70 BD?C:aC:0:1 + 24648 LUT4 6000 CD(A^B) + 24649 LUT4 1000 abCD + 24650 LUT4 1000 abCD + 24651 LUT4 3AFF (c?b:A)+d + 24652 LUT4 4F00 ((aB)+c)D + 24653 LUT4 80FF (ABC)+d + 24654 LUT4 0700 cD/AB\ + 24655 LUT4 1428 (B^C)(A^D) + 24656 LUT4 6000 CD(A^B) + 24657 LUT4 1428 (B^C)(A^D) + 24658 LUT4 0700 cD/AB\ + 24659 LUT4 1428 (B^C)(A^D) + 24660 LUT4 6000 CD(A^B) + 24661 LUT4 1428 (B^C)(A^D) + 24662 LUT3 07 c/AB\ + 24663 LUT4 1428 (B^C)(A^D) + 24664 LUT4 6000 CD(A^B) + 24665 LUT4 1428 (B^C)(A^D) + 24666 LUT2 8 AB + 24667 LUT4 1428 (B^C)(A^D) + 24668 LUT4 6000 CD(A^B) + 24669 LUT4 1428 (B^C)(A^D) + 24670 LUT2 8 AB + 24671 LUT4 9000 CD(a^B) + 24672 LUT4 9009 (a^B)(D^c) + 24673 LUT4 0777 /AB\(d+c) + 24674 LUT2 4 aB + 24675 LUT4 9009 (a^B)(D^c) + 24676 LUT4 9000 CD(a^B) + 24677 LUT4 9009 (a^B)(D^c) + 24678 LUT2 8 AB + 24679 LUT4 1428 (B^C)(A^D) + 24680 LUT4 6000 CD(A^B) + 24681 LUT4 F800 ((AB)+C)D + 24682 LUT4 7077 /AB\(d+C) + 24683 LUT4 8F00 ((AB)+c)D + 24684 LUT4 0007 cd/AB\ + 24685 LUT4 0B00 cD/aB\ + 24686 LUT4 30F5 DC?a:0:1:b + 24687 LUT4 BFFF /aB\+c+d + 24688 LUT4 FFE0 (C/ab\)+D + 24689 LUT4 000D cd/Ab\ + 24690 LUT4 0700 cD/AB\ + 24691 LUT4 EF00 ((/ab\)+c)D + 24692 LUT4 007F ((/AB\)+c)d + 24693 LUT4 8F30 DC?0:1:b:AB + 24694 LUT4 77F0 D?C:/AB\ + 24695 LUT4 3807 BC?d:a^D:D:0 + 24696 LUT4 3BF3 BD?1:C:1:Ac + 24697 LUT4 F1FF (ab)+C+d + 24698 LUT4 70FF (C/AB\)+d + 24699 LUT4 8F00 ((AB)+c)D + 24700 LUT4 770F D?c:/AB\ + 24701 LUT4 FF70 (C/AB\)+D + 24702 LUT4 8001 AB?cd:0:0:CD + 24703 LUT4 8001 AB?cd:0:0:CD + 24704 LUT4 8001 AB?cd:0:0:CD + 24705 LUT4 8001 AB?cd:0:0:CD + 24706 LUT4 8001 AB?cd:0:0:CD + 24707 LUT4 8001 AB?cd:0:0:CD + 24708 LUT4 8001 AB?cd:0:0:CD + 24709 LUT4 8001 AB?cd:0:0:CD + 24710 LUT4 8001 AB?cd:0:0:CD + 24711 LUT4 8001 AB?cd:0:0:CD + 24712 LUT4 8001 AB?cd:0:0:CD + 24713 LUT3 7F /AB\+c + 24714 LUT4 CA00 D(C?A:B) + 24715 LUT4 0CCA DC?A:B:B:0 + 24716 LUT4 8001 AB?cd:0:0:CD + 24717 LUT4 8001 AB?cd:0:0:CD + 24718 LUT4 8001 AB?cd:0:0:CD + 24719 LUT4 8001 AB?cd:0:0:CD + 24720 LUT4 8001 AB?cd:0:0:CD + 24721 LUT4 7C8C BC?0:1:D:A^D + 24722 LUT4 9768 (AB?0:C:C:c)^D + 24723 LUT4 8001 AB?cd:0:0:CD + 24724 LUT4 8001 AB?cd:0:0:CD + 24725 LUT4 8001 AB?cd:0:0:CD + 24726 LUT4 8001 AB?cd:0:0:CD + 24727 LUT4 547F AD?1:/BC\:/bc\:0 + 24728 LUT3 5C c?a:B + 24729 LUT4 9009 (a^B)(D^c) + 24730 LUT4 9000 CD(a^B) + 24731 LUT4 8700 AD?0:0:c:b^C + 24732 LUT4 F0EE D?/ab\:C + 24733 LUT3 B0 C/aB\ + 24734 LUT4 B000 CD/aB\ + 24735 LUT4 F0EE D?/ab\:C + 24736 LUT3 B0 C/aB\ + 24737 LUT4 4FFF (aB)+c+d + 24738 LUT2 B /aB\ + 24739 LUT4 B033 BD?1:0:C:AC + 24740 LUT3 A3 C?b:A + 24741 LUT4 CF50 DC?0:1:a:B + 24742 LUT4 0E00 cD/ab\ + 24743 LUT4 B033 BD?1:0:C:AC + 24744 LUT3 A3 C?b:A + 24745 LUT4 CF50 DC?0:1:a:B + 24746 LUT4 0E00 cD/ab\ + 24747 LUT4 B033 BD?1:0:C:AC + 24748 LUT3 A3 C?b:A + 24749 LUT4 CF50 DC?0:1:a:B + 24750 LUT4 0E00 cD/ab\ + 24751 LUT4 B033 BD?1:0:C:AC + 24752 LUT3 A3 C?b:A + 24753 LUT4 CF50 DC?0:1:a:B + 24754 LUT4 0E00 cD/ab\ + 24755 LUT4 B033 BD?1:0:C:AC + 24756 LUT3 A3 C?b:A + 24757 LUT4 3F50 DC?0:1:a:b + 24758 LUT4 0D00 cD/Ab\ + 24759 LUT4 B033 BD?1:0:C:AC + 24760 LUT3 A3 C?b:A + 24761 LUT4 3F50 DC?0:1:a:b + 24762 LUT4 0D00 cD/Ab\ + 24763 LUT4 B033 BD?1:0:C:AC + 24764 LUT3 A3 C?b:A + 24765 LUT4 3F50 DC?0:1:a:b + 24766 LUT4 0D00 cD/Ab\ + 24767 LUT4 B033 BD?1:0:C:AC + 24768 LUT3 A3 C?b:A + 24769 LUT4 CF50 DC?0:1:a:B + 24770 LUT4 0E00 cD/ab\ + 24771 LUT4 B033 BD?1:0:C:AC + 24772 LUT3 A3 C?b:A + 24773 LUT4 CF50 DC?0:1:a:B + 24774 LUT4 0E00 cD/ab\ + 24775 LUT4 B033 BD?1:0:C:AC + 24776 LUT3 A3 C?b:A + 24777 LUT4 CF50 DC?0:1:a:B + 24778 LUT4 0E00 cD/ab\ + 24779 LUT4 B033 BD?1:0:C:AC + 24780 LUT3 A3 C?b:A + 24781 LUT4 3F50 DC?0:1:a:b + 24782 LUT4 0D00 cD/Ab\ + 24783 LUT4 B033 BD?1:0:C:AC + 24784 LUT3 A3 C?b:A + 24785 LUT4 CF50 DC?0:1:a:B + 24786 LUT4 0E00 cD/ab\ + 24787 LUT4 B033 BD?1:0:C:AC + 24788 LUT3 A3 C?b:A + 24789 LUT4 3F50 DC?0:1:a:b + 24790 LUT4 0D00 cD/Ab\ + 24791 LUT4 B033 BD?1:0:C:AC + 24792 LUT3 A3 C?b:A + 24793 LUT4 CF50 DC?0:1:a:B + 24794 LUT4 0E00 cD/ab\ + 24795 LUT4 B033 BD?1:0:C:AC + 24796 LUT3 A3 C?b:A + 24797 LUT4 3F50 DC?0:1:a:b + 24798 LUT4 0D00 cD/Ab\ + 24799 LUT4 B033 BD?1:0:C:AC + 24800 LUT3 A3 C?b:A + 24801 LUT4 CF50 DC?0:1:a:B + 24802 LUT4 0E00 cD/ab\ + 24803 LUT4 B033 BD?1:0:C:AC + 24804 LUT3 AC c?A:B + 24805 LUT4 3F50 DC?0:1:a:b + 24806 LUT4 0D00 cD/Ab\ + 24807 LUT4 B033 BD?1:0:C:AC + 24808 LUT3 AC c?A:B + 24809 LUT4 CF50 DC?0:1:a:B + 24810 LUT4 0E00 cD/ab\ + 24811 LUT4 B033 BD?1:0:C:AC + 24812 LUT3 AC c?A:B + 24813 LUT4 3F50 DC?0:1:a:b + 24814 LUT4 0D00 cD/Ab\ + 24815 LUT4 B033 BD?1:0:C:AC + 24816 LUT3 AC c?A:B + 24817 LUT4 CF50 DC?0:1:a:B + 24818 LUT4 0E00 cD/ab\ + 24819 LUT4 B033 BD?1:0:C:AC + 24820 LUT3 AC c?A:B + 24821 LUT4 CF50 DC?0:1:a:B + 24822 LUT4 0E00 cD/ab\ + 24823 LUT4 13FC BD?C:1:/AC\:0 + 24824 LUT4 07FF (c/AB\)+d + 24825 LUT4 1000 abCD + 24826 LUT4 F4FF (aB)+C+d + 24827 LUT4 B033 BD?1:0:C:AC + 24828 LUT3 A3 C?b:A + 24829 LUT4 3F50 DC?0:1:a:b + 24830 LUT4 0D00 cD/Ab\ + 24831 LUT4 B033 BD?1:0:C:AC + 24832 LUT3 A3 C?b:A + 24833 LUT4 CF50 DC?0:1:a:B + 24834 LUT4 0E00 cD/ab\ + 24835 LUT4 B033 BD?1:0:C:AC + 24836 LUT3 A3 C?b:A + 24837 LUT4 CF50 DC?0:1:a:B + 24838 LUT4 0E00 cD/ab\ + 24839 LUT4 B033 BD?1:0:C:AC + 24840 LUT3 A3 C?b:A + 24841 LUT4 CF50 DC?0:1:a:B + 24842 LUT4 0E00 cD/ab\ + 24843 LUT4 B033 BD?1:0:C:AC + 24844 LUT3 A3 C?b:A + 24845 LUT4 CF50 DC?0:1:a:B + 24846 LUT4 0E00 cD/ab\ + 24847 LUT4 B033 BD?1:0:C:AC + 24848 LUT3 A3 C?b:A + 24849 LUT4 3F50 DC?0:1:a:b + 24850 LUT4 0D00 cD/Ab\ + 24851 LUT4 B033 BD?1:0:C:AC + 24852 LUT3 A3 C?b:A + 24853 LUT4 3F50 DC?0:1:a:b + 24854 LUT4 0D00 cD/Ab\ + 24855 LUT4 B033 BD?1:0:C:AC + 24856 LUT3 A3 C?b:A + 24857 LUT4 3F50 DC?0:1:a:b + 24858 LUT4 0D00 cD/Ab\ + 24859 LUT4 B033 BD?1:0:C:AC + 24860 LUT3 A3 C?b:A + 24861 LUT4 CF50 DC?0:1:a:B + 24862 LUT4 0E00 cD/ab\ + 24863 LUT4 B033 BD?1:0:C:AC + 24864 LUT3 A3 C?b:A + 24865 LUT4 CF50 DC?0:1:a:B + 24866 LUT4 0E00 cD/ab\ + 24867 LUT4 B033 BD?1:0:C:AC + 24868 LUT3 A3 C?b:A + 24869 LUT4 3F50 DC?0:1:a:b + 24870 LUT4 0D00 cD/Ab\ + 24871 LUT4 B033 BD?1:0:C:AC + 24872 LUT3 A3 C?b:A + 24873 LUT4 CF50 DC?0:1:a:B + 24874 LUT4 0E00 cD/ab\ + 24875 LUT4 B033 BD?1:0:C:AC + 24876 LUT3 A3 C?b:A + 24877 LUT4 3F50 DC?0:1:a:b + 24878 LUT4 0D00 cD/Ab\ + 24879 LUT4 B033 BD?1:0:C:AC + 24880 LUT3 A3 C?b:A + 24881 LUT4 CF50 DC?0:1:a:B + 24882 LUT4 0E00 cD/ab\ + 24883 LUT4 B033 BD?1:0:C:AC + 24884 LUT3 A3 C?b:A + 24885 LUT4 CF50 DC?0:1:a:B + 24886 LUT4 0E00 cD/ab\ + 24887 LUT4 B033 BD?1:0:C:AC + 24888 LUT3 A3 C?b:A + 24889 LUT4 3F50 DC?0:1:a:b + 24890 LUT4 0D00 cD/Ab\ + 24891 LUT4 B033 BD?1:0:C:AC + 24892 LUT3 A3 C?b:A + 24893 LUT4 CF50 DC?0:1:a:B + 24894 LUT4 0E00 cD/ab\ + 24895 LUT4 B033 BD?1:0:C:AC + 24896 LUT3 A3 C?b:A + 24897 LUT4 3F50 DC?0:1:a:b + 24898 LUT4 0D00 cD/Ab\ + 24899 LUT4 B033 BD?1:0:C:AC + 24900 LUT3 AC c?A:B + 24901 LUT4 3F50 DC?0:1:a:b + 24902 LUT4 0D00 cD/Ab\ + 24903 LUT4 B033 BD?1:0:C:AC + 24904 LUT3 AC c?A:B + 24905 LUT4 CF50 DC?0:1:a:B + 24906 LUT4 0E00 cD/ab\ + 24907 LUT4 B033 BD?1:0:C:AC + 24908 LUT3 AC c?A:B + 24909 LUT4 3F50 DC?0:1:a:b + 24910 LUT4 0D00 cD/Ab\ + 24911 LUT4 B033 BD?1:0:C:AC + 24912 LUT3 AC c?A:B + 24913 LUT4 CF50 DC?0:1:a:B + 24914 LUT4 0E00 cD/ab\ + 24915 LUT4 B033 BD?1:0:C:AC + 24916 LUT3 AC c?A:B + 24917 LUT4 CF50 DC?0:1:a:B + 24918 LUT4 0E00 cD/ab\ + 24919 LUT4 3A33 DC?b:A:b:b + 24920 LUT4 FF40 (aBC)+D + 24921 LUT4 3533 DC?b:a:b:b + 24922 LUT4 FF40 (aBC)+D + 24923 LUT4 3A33 DC?b:A:b:b + 24924 LUT4 FF40 (aBC)+D + 24925 LUT4 3533 DC?b:a:b:b + 24926 LUT4 FF40 (aBC)+D + 24927 LUT3 B0 C/aB\ + 24928 LUT4 0C0A DC?A:B:0:0 + 24929 LUT3 F8 (AB)+C + 24930 LUT4 3533 DC?b:a:b:b + 24931 LUT4 FF40 (aBC)+D + 24932 LUT4 3533 DC?b:a:b:b + 24933 LUT4 FF40 (aBC)+D + 24934 LUT4 3A33 DC?b:A:b:b + 24935 LUT4 FF40 (aBC)+D + 24936 LUT4 3A33 DC?b:A:b:b + 24937 LUT4 FF40 (aBC)+D + 24938 LUT4 3A33 DC?b:A:b:b + 24939 LUT4 FF40 (aBC)+D + 24940 LUT4 FFF8 (AB)+C+D + 24941 LUT4 07FF (c/AB\)+d + 24942 LUT4 1000 abCD + 24943 LUT4 F4FF (aB)+C+d + 24944 LUT4 B033 BD?1:0:C:AC + 24945 LUT3 A3 C?b:A + 24946 LUT4 3F50 DC?0:1:a:b + 24947 LUT4 0D00 cD/Ab\ + 24948 LUT4 B033 BD?1:0:C:AC + 24949 LUT3 A3 C?b:A + 24950 LUT4 CF50 DC?0:1:a:B + 24951 LUT4 0E00 cD/ab\ + 24952 LUT4 B033 BD?1:0:C:AC + 24953 LUT3 A3 C?b:A + 24954 LUT4 CF50 DC?0:1:a:B + 24955 LUT4 0E00 cD/ab\ + 24956 LUT4 B033 BD?1:0:C:AC + 24957 LUT3 A3 C?b:A + 24958 LUT4 CF50 DC?0:1:a:B + 24959 LUT4 0E00 cD/ab\ + 24960 LUT4 B033 BD?1:0:C:AC + 24961 LUT3 A3 C?b:A + 24962 LUT4 3F50 DC?0:1:a:b + 24963 LUT4 0D00 cD/Ab\ + 24964 LUT4 B033 BD?1:0:C:AC + 24965 LUT3 A3 C?b:A + 24966 LUT4 3F50 DC?0:1:a:b + 24967 LUT4 0D00 cD/Ab\ + 24968 LUT4 B033 BD?1:0:C:AC + 24969 LUT3 A3 C?b:A + 24970 LUT4 3F50 DC?0:1:a:b + 24971 LUT4 0D00 cD/Ab\ + 24972 LUT4 B033 BD?1:0:C:AC + 24973 LUT3 A3 C?b:A + 24974 LUT4 CF50 DC?0:1:a:B + 24975 LUT4 0E00 cD/ab\ + 24976 LUT4 B033 BD?1:0:C:AC + 24977 LUT3 A3 C?b:A + 24978 LUT4 CF50 DC?0:1:a:B + 24979 LUT4 0E00 cD/ab\ + 24980 LUT4 B033 BD?1:0:C:AC + 24981 LUT3 A3 C?b:A + 24982 LUT4 3F50 DC?0:1:a:b + 24983 LUT4 0D00 cD/Ab\ + 24984 LUT4 B033 BD?1:0:C:AC + 24985 LUT3 A3 C?b:A + 24986 LUT4 3F50 DC?0:1:a:b + 24987 LUT4 0D00 cD/Ab\ + 24988 LUT4 B033 BD?1:0:C:AC + 24989 LUT3 A3 C?b:A + 24990 LUT4 CF50 DC?0:1:a:B + 24991 LUT4 0E00 cD/ab\ + 24992 LUT4 B033 BD?1:0:C:AC + 24993 LUT3 A3 C?b:A + 24994 LUT4 3F50 DC?0:1:a:b + 24995 LUT4 0D00 cD/Ab\ + 24996 LUT4 B033 BD?1:0:C:AC + 24997 LUT3 A3 C?b:A + 24998 LUT4 CF50 DC?0:1:a:B + 24999 LUT4 0E00 cD/ab\ + 25000 LUT4 B033 BD?1:0:C:AC + 25001 LUT3 A3 C?b:A + 25002 LUT4 3F50 DC?0:1:a:b + 25003 LUT4 0D00 cD/Ab\ + 25004 LUT4 B033 BD?1:0:C:AC + 25005 LUT3 A3 C?b:A + 25006 LUT4 3F50 DC?0:1:a:b + 25007 LUT4 0D00 cD/Ab\ + 25008 LUT4 B033 BD?1:0:C:AC + 25009 LUT3 AC c?A:B + 25010 LUT4 3F50 DC?0:1:a:b + 25011 LUT4 0D00 cD/Ab\ + 25012 LUT4 B033 BD?1:0:C:AC + 25013 LUT3 AC c?A:B + 25014 LUT4 CF50 DC?0:1:a:B + 25015 LUT4 0E00 cD/ab\ + 25016 LUT4 8FFF (AB)+c+d + 25017 LUT4 8000 ABCD + 25018 LUT4 4000 aBCD + 25019 LUT4 B000 CD/aB\ + 25020 LUT2 8 AB + 25021 LUT4 F0BB D?/aB\:C + 25022 LUT4 1FD0 BC?D:D:a:d + 25023 LUT4 0733 BD?1:0:c:ac + 25024 LUT3 C5 C?a:B + 25025 LUT3 CA C?A:B + 25026 LUT3 CA C?A:B + 25027 LUT3 CA C?A:B + 25028 LUT3 CA C?A:B + 25029 LUT4 F0BB D?/aB\:C + 25030 LUT4 2F70 AC?D:D:d:b + 25031 LUT3 CA C?A:B + 25032 LUT3 CA C?A:B + 25033 LUT4 F044 D?aB:C + 25034 LUT4 2F70 AC?D:D:d:b + 25035 LUT3 CA C?A:B + 25036 LUT4 CACC DC?B:A:B:B + 25037 LUT4 440F D?c:aB + 25038 LUT4 8FD0 AC?D:D:d:B + 25039 LUT4 44F0 D?C:aB + 25040 LUT4 ACCC DC?B:B:B:A + 25041 LUT3 CA C?A:B + 25042 LUT3 CA C?A:B + 25043 LUT4 CACC DC?B:A:B:B + 25044 LUT3 CA C?A:B + 25045 LUT4 ACCC DC?B:B:B:A + 25046 LUT3 80 ABC + 25047 LUT4 F0BB D?/aB\:C + 25048 LUT3 3A c?b:A + 25049 LUT4 B303 BD?c:0:1:AC + 25050 LUT4 EC30 BD?C:0:AC:1 + 25051 LUT3 CA C?A:B + 25052 LUT4 CACC DC?B:A:B:B + 25053 LUT4 BB0F D?c:/aB\ + 25054 LUT3 70 C/AB\ + 25055 LUT3 CA C?A:B + 25056 LUT4 CACC DC?B:A:B:B + 25057 LUT4 8000 ABCD + 25058 LUT2 8 AB + 25059 LUT4 5333 DC?b:b:b:a + 25060 LUT3 D0 C/Ab\ + 25061 LUT4 9009 (a^B)(D^c) + 25062 LUT4 0F88 D?AB:c + 25063 LUT4 2372 AB?C^D:1:Cd:0 + 25064 LUT2 7 /AB\ + 25065 LUT4 07FF (c/AB\)+d + 25066 LUT4 8000 ABCD + 25067 LUT4 007F ((/AB\)+c)d + 25068 LUT4 4F00 ((aB)+c)D + 25069 LUT3 80 ABC + 25070 LUT4 00BF ((/aB\)+c)d + 25071 LUT4 40FF (aBC)+d + 25072 LUT4 7000 CD/AB\ + 25073 LUT4 0100 abcD + 25074 LUT4 7FFF /AB\+c+d + 25075 LUT4 1F00 ((ab)+c)D + 25076 LUT4 0700 cD/AB\ + 25077 LUT4 0777 /AB\(d+c) + 25078 LUT4 8000 ABCD + 25079 LUT3 F8 (AB)+C + 25080 LUT4 C00A DC?A:0:0:B + 25081 LUT3 8F (AB)+c + 25082 LUT4 D5F0 AC?D:0:1:/bD\ + 25083 LUT4 F0D5 AC?d:0:1:/bd\ + 25084 LUT4 D5F0 AC?D:0:1:/bD\ + 25085 LUT4 F0D5 AC?d:0:1:/bd\ + 25086 LUT4 D5F0 AC?D:0:1:/bD\ + 25087 LUT4 F0D5 AC?d:0:1:/bd\ + 25088 LUT4 D5F0 AC?D:0:1:/bD\ + 25089 LUT4 F0D5 AC?d:0:1:/bd\ + 25090 LUT4 D5F0 AC?D:0:1:/bD\ + 25091 LUT4 F0D5 AC?d:0:1:/bd\ + 25092 LUT4 9009 (a^B)(D^c) + 25093 LUT4 7FFF /AB\+c+d + 25094 LUT3 70 C/AB\ + 25095 LUT4 9000 CD(a^B) + 25096 LUT4 9009 (a^B)(D^c) + 25097 LUT3 7F /AB\+c + 25098 LUT3 70 C/AB\ + 25099 LUT4 35FF (c?b:a)+d + 25100 LUT4 0777 /AB\(d+c) + 25101 LUT4 35FF (c?b:a)+d + 25102 LUT4 0BBB /aB\(d+c) + 25103 LUT4 F077 D?/AB\:C + 25104 LUT4 FEFF /ab\+C+d + 25105 LUT4 F400 ((aB)+C)D + 25106 LUT4 3A00 D(c?b:A) + 25107 LUT4 0007 cd/AB\ + 25108 LUT4 6000 CD(A^B) + 25109 LUT4 1428 (B^C)(A^D) + 25110 LUT4 8000 ABCD + 25111 LUT4 8000 ABCD + 25112 LUT4 6000 CD(A^B) + 25113 LUT4 FF80 (ABC)+D + 25114 LUT4 0777 /AB\(d+c) + 25115 LUT4 0EE0 (A+B)(C^D) + 25116 LUT4 6000 CD(A^B) + 25117 LUT4 1428 (B^C)(A^D) + 25118 LUT4 E000 CD/ab\ + 25119 LUT2 8 AB + 25120 LUT4 0700 cD/AB\ + 25121 LUT4 0FF1 DC?ab:1:1:0 + 25122 LUT4 37F3 BD?1:C:1:ac + 25123 LUT4 F4FF (aB)+C+d + 25124 LUT4 050C DC?B:a:0:0 + 25125 LUT4 5300 D(C?b:a) + 25126 LUT4 F0BB D?/aB\:C + 25127 LUT3 B0 C/aB\ + 25128 LUT4 9009 (a^B)(D^c) + 25129 LUT4 4114 AB?C^D:0:c^D:0 + 25130 LUT4 9600 D(A^B^C) + 25131 LUT4 F0BB D?/aB\:C + 25132 LUT3 B0 C/aB\ + 25133 LUT4 F888 (AB)+(CD) + 25134 LUT4 0777 /AB\(d+c) + 25135 LUT4 8000 ABCD + 25136 LUT4 0777 /AB\(d+c) + 25137 LUT4 F888 (AB)+(CD) + 25138 LUT4 8000 ABCD + 25139 LUT4 F888 (AB)+(CD) + 25140 LUT4 F888 (AB)+(CD) + 25141 LUT4 0777 /AB\(d+c) + 25142 LUT4 4000 aBCD + 25143 LUT4 0777 /AB\(d+c) + 25144 LUT4 F888 (AB)+(CD) + 25145 LUT4 0777 /AB\(d+c) + 25146 LUT4 4000 aBCD + 25147 LUT4 F888 (AB)+(CD) + 25148 LUT4 F888 (AB)+(CD) + 25149 LUT4 F888 (AB)+(CD) + 25150 LUT4 F888 (AB)+(CD) + 25151 LUT4 0777 /AB\(d+c) + 25152 LUT4 4000 aBCD + 25153 LUT4 F888 (AB)+(CD) + 25154 LUT4 7000 CD/AB\ + 25155 LUT4 F888 (AB)+(CD) + 25156 LUT4 F888 (AB)+(CD) + 25157 LUT4 EEF0 D?C:/ab\ + 25158 LUT3 B0 C/aB\ + 25159 LUT4 4114 AB?C^D:0:c^D:0 + 25160 LUT4 4000 aBCD + 25161 LUT2 4 aB + 25162 LUT4 CFA0 DC?0:1:A:B + 25163 LUT4 E000 CD/ab\ + 25164 LUT4 7000 CD/AB\ + 25165 LUT4 7000 CD/AB\ + 25166 LUT4 F888 (AB)+(CD) + 25167 LUT4 F888 (AB)+(CD) + 25168 LUT4 F888 (AB)+(CD) + 25169 LUT4 F888 (AB)+(CD) + 25170 LUT4 0777 /AB\(d+c) + 25171 LUT4 F888 (AB)+(CD) + 25172 LUT4 F888 (AB)+(CD) + 25173 LUT4 0700 cD/AB\ + 25174 LUT4 F888 (AB)+(CD) + 25175 LUT3 70 C/AB\ + 25176 LUT4 77F0 D?C:/AB\ + 25177 LUT4 88F0 D?C:AB + 25178 LUT4 730F DC?1:b:0:/AB\ + 25179 LUT4 0777 /AB\(d+c) + 25180 LUT3 70 C/AB\ + 25181 LUT4 F888 (AB)+(CD) + 25182 LUT4 F888 (AB)+(CD) + 25183 LUT4 0777 /AB\(d+c) + 25184 LUT4 0777 /AB\(d+c) + 25185 LUT4 8FFF (AB)+c+d + 25186 LUT4 F888 (AB)+(CD) + 25187 LUT4 7000 CD/AB\ + 25188 LUT4 AC00 D(c?A:B) + 25189 LUT4 88F0 D?C:AB + 25190 LUT4 3307 BD?c:ac:1:0 + 25191 LUT4 77F0 D?C:/AB\ + 25192 LUT4 0777 /AB\(d+c) + 25193 LUT4 FAFC DC?B:A:1:1 + 25194 LUT4 88F0 D?C:AB + 25195 LUT4 0100 abcD + 25196 LUT4 9600 D(A^B^C) + 25197 LUT4 4114 AB?C^D:0:c^D:0 + 25198 LUT4 8000 ABCD + 25199 LUT4 EFFF /ab\+c+d + 25200 LUT4 FFB0 (C/aB\)+D + 25201 LUT4 F8FF (AB)+C+d + 25202 LUT4 C00A DC?A:0:0:B + 25203 LUT4 F8FF (AB)+C+d + 25204 LUT4 0AC0 DC?0:A:B:0 + 25205 LUT4 EF00 ((/ab\)+c)D + 25206 LUT4 7FFF /AB\+c+d + 25207 LUT4 030A DC?A:b:0:0 + 25208 LUT3 10 abC + 25209 LUT4 3F50 DC?0:1:a:b + 25210 LUT4 F305 DC?a:b:0:1 + 25211 LUT4 3F50 DC?0:1:a:b + 25212 LUT4 F305 DC?a:b:0:1 + 25213 LUT4 B0BB /aB\(d+C) + 25214 LUT4 00BF ((/aB\)+c)d + 25215 LUT4 9C0F DC?1:B:0:a^B + 25216 LUT4 B00B /aB\/D^C\ + 25217 LUT4 9009 (a^B)(D^c) + 25218 LUT4 9000 CD(a^B) + 25219 LUT3 90 C(a^B) + 25220 LUT4 5A3C DC?B:A:b:a + 25221 LUT4 8F00 ((AB)+c)D + 25222 LUT4 88F0 D?C:AB + 25223 LUT4 F88F (c^D)+(AB) + 25224 LUT2 8 AB + 25225 LUT4 BEA0 AD?0:C:B^C:1 + 25226 LUT4 8000 ABCD + 25227 LUT4 8000 ABCD + 25228 LUT4 4000 aBCD + 25229 LUT4 BEA0 AD?0:C:B^C:1 + 25230 LUT4 1000 abCD + 25231 LUT4 BEA0 AD?0:C:B^C:1 + 25232 LUT4 0100 abcD + 25233 LUT4 4000 aBCD + 25234 LUT4 53FC DC?B:b:1:a + 25235 LUT4 1000 abCD + 25236 LUT4 3A00 D(c?b:A) + 25237 LUT4 BEA0 AD?0:C:B^C:1 + 25238 LUT2 8 AB + 25239 LUT4 AB0E AC?B^D:1:0:D + 25240 LUT4 8000 ABCD + 25241 LUT4 4000 aBCD + 25242 LUT4 007F ((/AB\)+c)d + 25243 LUT4 0100 abcD + 25244 LUT4 BF00 ((/aB\)+c)D + 25245 LUT4 008F ((AB)+c)d + 25246 LUT4 0BF4 (c/aB\)^d + 25247 LUT4 9000 CD(a^B) + 25248 LUT4 9000 CD(a^B) + 25249 LUT4 6FFF (A^B)+c+d + 25250 LUT4 9009 (a^B)(D^c) + 25251 LUT4 9009 (a^B)(D^c) + 25252 LUT3 7F /AB\+c + 25253 LUT4 008F ((AB)+c)d + 25254 LUT3 70 C/AB\ + 25255 LUT4 F444 (aB)+(CD) + 25256 LUT4 F444 (aB)+(CD) + 25257 LUT4 F888 (AB)+(CD) + 25258 LUT4 0777 /AB\(d+c) + 25259 LUT4 008F ((AB)+c)d + 25260 LUT4 004F ((aB)+c)d + 25261 LUT4 0BBB /aB\(d+c) + 25262 LUT4 0777 /AB\(d+c) + 25263 LUT4 F400 ((aB)+C)D + 25264 LUT4 0777 /AB\(d+c) + 25265 LUT4 B0FF (C/aB\)+d + 25266 LUT4 008F ((AB)+c)d + 25267 LUT4 FCFA DC?A:B:1:1 + 25268 LUT4 7000 CD/AB\ + 25269 LUT4 0BBB /aB\(d+c) + 25270 LUT4 B0FF (C/aB\)+d + 25271 LUT4 40FF (aBC)+d + 25272 LUT4 70FF (C/AB\)+d + 25273 LUT4 9009 (a^B)(D^c) + 25274 LUT4 B00B /aB\/D^C\ + 25275 LUT4 9000 CD(a^B) + 25276 LUT4 30FA DC?A:0:1:b + 25277 LUT4 30FA DC?A:0:1:b + 25278 LUT4 1000 abCD + 25279 LUT3 7F /AB\+c + 25280 LUT4 778F AD?c:/bC\:1:b + 25281 LUT4 30FA DC?A:0:1:b + 25282 LUT4 0BBB /aB\(d+c) + 25283 LUT4 4F00 ((aB)+c)D + 25284 LUT4 FFB0 (C/aB\)+D + 25285 LUT4 31F3 BD?1:C:/Ac\:0 + 25286 LUT4 30F5 DC?a:0:1:b + 25287 LUT4 0100 abcD + 25288 LUT4 FF80 (ABC)+D + 25289 LUT4 30F5 DC?a:0:1:b + 25290 LUT4 4F00 ((aB)+c)D + 25291 LUT4 F100 ((ab)+C)D + 25292 LUT3 0D c/Ab\ + 25293 LUT4 F332 BD?/ac\:0:1:C + 25294 LUT4 1000 abCD + 25295 LUT4 7077 /AB\(d+C) + 25296 LUT4 0001 abcd + 25297 LUT4 4F00 ((aB)+c)D + 25298 LUT4 C3FA DC?A:b:1:B + 25299 LUT4 DCCF BD?c:1:aC:1 + 25300 LUT2 B /aB\ + 25301 LUT4 CF50 DC?0:1:a:B + 25302 LUT4 CC0B BD?c:Ac:0:1 + 25303 LUT4 B0FF (C/aB\)+d + 25304 LUT4 F888 (AB)+(CD) + 25305 LUT4 0700 cD/AB\ + 25306 LUT4 0700 cD/AB\ + 25307 LUT4 008F ((AB)+c)d + 25308 LUT4 8F88 (AB)+(cD) + 25309 LUT4 0777 /AB\(d+c) + 25310 LUT4 880F D?c:AB + 25311 LUT4 0007 cd/AB\ + 25312 LUT4 C051 AB?d:0:C:CD + 25313 LUT4 EF00 ((/ab\)+c)D + 25314 LUT4 800D DC?/Ab\:0:0:AB + 25315 LUT4 9000 CD(a^B) + 25316 LUT4 1001 ab(c^D) + 25317 LUT4 3500 D(c?b:a) + 25318 LUT4 9000 CD(a^B) + 25319 LUT4 9000 CD(a^B) + 25320 LUT4 9009 (a^B)(D^c) + 25321 LUT4 9000 CD(a^B) + 25322 LUT4 8100 D(AB?c:0:0:C) + 25323 LUT4 0C0A DC?A:B:0:0 + 25324 LUT4 6FFF (A^B)+c+d + 25325 LUT4 4F44 (aB)+(cD) + 25326 LUT4 300D DC?/Ab\:0:0:b + 25327 LUT4 9000 CD(a^B) + 25328 LUT4 9009 (a^B)(D^c) + 25329 LUT4 6FFF (A^B)+c+d + 25330 LUT4 9009 (a^B)(D^c) + 25331 LUT4 9009 (a^B)(D^c) + 25332 LUT4 9009 (a^B)(D^c) + 25333 LUT4 7FFF /AB\+c+d + 25334 LUT4 9009 (a^B)(D^c) + 25335 LUT4 D700 AD?0:0:1:b^C + 25336 LUT4 9000 CD(a^B) + 25337 LUT4 B00B /aB\/D^C\ + 25338 LUT4 8000 ABCD + 25339 LUT4 8000 ABCD + 25340 LUT4 9009 (a^B)(D^c) + 25341 LUT4 9009 (a^B)(D^c) + 25342 LUT4 4000 aBCD + 25343 LUT4 9000 CD(a^B) + 25344 LUT4 9009 (a^B)(D^c) + 25345 LUT4 9000 CD(a^B) + 25346 LUT4 9009 (a^B)(D^c) + 25347 LUT4 8000 ABCD + 25348 LUT4 BC00 D(BC?0:1:1:A) + 25349 LUT4 BF00 ((/aB\)+c)D + 25350 LUT4 733F BD?1:c:1:aC + 25351 LUT4 0700 cD/AB\ + 25352 LUT4 BFFF /aB\+c+d + 25353 LUT4 8F00 ((AB)+c)D + 25354 LUT4 FF80 (ABC)+D + 25355 LUT4 00BF ((/aB\)+c)d + 25356 LUT4 70FF (C/AB\)+d + 25357 LUT4 7F00 ((/AB\)+c)D + 25358 LUT4 0B00 cD/aB\ + 25359 LUT4 4F00 ((aB)+c)D + 25360 LUT4 BFFF /aB\+c+d + 25361 LUT4 80FF (ABC)+d + 25362 LUT4 1FFF (ab)+c+d + 25363 LUT4 B000 CD/aB\ + 25364 LUT4 7FFF /AB\+c+d + 25365 LUT4 80FF (ABC)+d + 25366 LUT4 FF10 (abC)+D + 25367 LUT4 CE03 BD?c:0:Ac:1 + 25368 LUT4 F703 BD?c:0:1:/Ac\ + 25369 LUT4 4000 aBCD + 25370 LUT4 3FA0 DC?0:1:A:b + 25371 LUT4 B00B /aB\/D^C\ + 25372 LUT4 B0BB /aB\(d+C) + 25373 LUT4 9009 (a^B)(D^c) + 25374 LUT4 B00B /aB\/D^C\ + 25375 LUT3 78 (AB)^C + 25376 LUT4 BF40 (aBC)^D + 25377 LUT4 8000 ABCD + 25378 LUT4 A300 D(C?b:A) + 25379 LUT4 C0FA DC?A:0:1:B + 25380 LUT4 000E cd/ab\ + 25381 LUT4 D000 CD/Ab\ + 25382 LUT4 8000 ABCD + 25383 LUT4 C0F5 DC?a:0:1:B + 25384 LUT4 0E00 cD/ab\ + 25385 LUT4 0100 abcD + 25386 LUT4 4000 aBCD + 25387 LUT3 78 (AB)^C + 25388 LUT4 BF40 (aBC)^D + 25389 LUT4 0E00 cD/ab\ + 25390 LUT4 4000 aBCD + 25391 LUT4 C500 D(C?a:B) + 25392 LUT3 78 (AB)^C + 25393 LUT4 BF40 (aBC)^D + 25394 LUT4 C500 D(C?a:B) + 25395 LUT4 CFA0 DC?0:1:A:B + 25396 LUT4 FC0A DC?A:B:0:1 + 25397 LUT4 7000 CD/AB\ + 25398 LUT4 7000 CD/AB\ + 25399 LUT4 CFA0 DC?0:1:A:B + 25400 LUT4 FC0A DC?A:B:0:1 + 25401 LUT4 0777 /AB\(d+c) + 25402 LUT4 7000 CD/AB\ + 25403 LUT4 0700 cD/AB\ + 25404 LUT4 CFA0 DC?0:1:A:B + 25405 LUT4 FC0A DC?A:B:0:1 + 25406 LUT4 7000 CD/AB\ + 25407 LUT4 7000 CD/AB\ + 25408 LUT4 CFA0 DC?0:1:A:B + 25409 LUT4 FC0A DC?A:B:0:1 + 25410 LUT4 7000 CD/AB\ + 25411 LUT4 7000 CD/AB\ + 25412 LUT4 8000 ABCD + 25413 LUT4 3F50 DC?0:1:a:b + 25414 LUT3 D3 BC?1:0:a:1 + 25415 LUT4 D000 CD/Ab\ + 25416 LUT4 CFA0 DC?0:1:A:B + 25417 LUT4 FC0A DC?A:B:0:1 + 25418 LUT4 7000 CD/AB\ + 25419 LUT4 3F50 DC?0:1:a:b + 25420 LUT3 D3 BC?1:0:a:1 + 25421 LUT4 8F00 ((AB)+c)D + 25422 LUT4 05F3 DC?b:a:1:0 + 25423 LUT3 7C BC?0:1:1:a + 25424 LUT4 7000 CD/AB\ + 25425 LUT4 7000 CD/AB\ + 25426 LUT4 05F3 DC?b:a:1:0 + 25427 LUT3 7C BC?0:1:1:a + 25428 LUT4 3F50 DC?0:1:a:b + 25429 LUT3 D3 BC?1:0:a:1 + 25430 LUT4 CFA0 DC?0:1:A:B + 25431 LUT4 FC0A DC?A:B:0:1 + 25432 LUT4 7000 CD/AB\ + 25433 LUT4 7000 CD/AB\ + 25434 LUT4 7000 CD/AB\ + 25435 LUT4 CFA0 DC?0:1:A:B + 25436 LUT4 FC0A DC?A:B:0:1 + 25437 LUT4 7000 CD/AB\ + 25438 LUT4 7000 CD/AB\ + 25439 LUT4 0777 /AB\(d+c) + 25440 LUT4 0777 /AB\(d+c) + 25441 LUT4 0777 /AB\(d+c) + 25442 LUT4 CFA0 DC?0:1:A:B + 25443 LUT4 FC0A DC?A:B:0:1 + 25444 LUT4 7000 CD/AB\ + 25445 LUT4 7000 CD/AB\ + 25446 LUT4 CFA0 DC?0:1:A:B + 25447 LUT4 FC0A DC?A:B:0:1 + 25448 LUT4 B000 CD/aB\ + 25449 LUT4 7000 CD/AB\ + 25450 LUT4 7000 CD/AB\ + 25451 LUT4 CFA0 DC?0:1:A:B + 25452 LUT4 FC0A DC?A:B:0:1 + 25453 LUT4 7000 CD/AB\ + 25454 LUT4 7000 CD/AB\ + 25455 LUT4 CFA0 DC?0:1:A:B + 25456 LUT4 FC0A DC?A:B:0:1 + 25457 LUT4 7000 CD/AB\ + 25458 LUT4 7000 CD/AB\ + 25459 LUT4 7000 CD/AB\ + 25460 LUT4 CFA0 DC?0:1:A:B + 25461 LUT4 FC0A DC?A:B:0:1 + 25462 LUT4 7000 CD/AB\ + 25463 LUT4 CFA0 DC?0:1:A:B + 25464 LUT4 FC0A DC?A:B:0:1 + 25465 LUT4 7000 CD/AB\ + 25466 LUT4 7000 CD/AB\ + 25467 LUT4 7000 CD/AB\ + 25468 LUT4 CFA0 DC?0:1:A:B + 25469 LUT4 FC0A DC?A:B:0:1 + 25470 LUT4 7000 CD/AB\ + 25471 LUT4 0777 /AB\(d+c) + 25472 LUT4 B000 CD/aB\ + 25473 LUT4 7000 CD/AB\ + 25474 LUT4 0FDC DC?B:1:/Ab\:0 + 25475 LUT4 0A03 DC?b:A:0:0 + 25476 LUT4 3F50 DC?0:1:a:b + 25477 LUT4 F305 DC?a:b:0:1 + 25478 LUT4 3F50 DC?0:1:a:b + 25479 LUT4 F305 DC?a:b:0:1 + 25480 LUT4 3F50 DC?0:1:a:b + 25481 LUT4 F305 DC?a:b:0:1 + 25482 LUT4 3F50 DC?0:1:a:b + 25483 LUT4 F305 DC?a:b:0:1 + 25484 LUT4 3F50 DC?0:1:a:b + 25485 LUT4 F305 DC?a:b:0:1 + 25486 LUT4 3F50 DC?0:1:a:b + 25487 LUT4 F305 DC?a:b:0:1 + 25488 LUT4 3F50 DC?0:1:a:b + 25489 LUT4 F305 DC?a:b:0:1 + 25490 LUT4 3F50 DC?0:1:a:b + 25491 LUT4 F305 DC?a:b:0:1 + 25492 LUT4 3F50 DC?0:1:a:b + 25493 LUT4 F305 DC?a:b:0:1 + 25494 LUT4 3F50 DC?0:1:a:b + 25495 LUT4 F305 DC?a:b:0:1 + 25496 LUT4 3F50 DC?0:1:a:b + 25497 LUT4 F305 DC?a:b:0:1 + 25498 LUT4 3F50 DC?0:1:a:b + 25499 LUT4 F305 DC?a:b:0:1 + 25500 LUT4 3F50 DC?0:1:a:b + 25501 LUT4 F305 DC?a:b:0:1 + 25502 LUT4 3F50 DC?0:1:a:b + 25503 LUT4 F305 DC?a:b:0:1 + 25504 LUT4 3A33 DC?b:A:b:b + 25505 LUT4 0C05 DC?a:B:0:0 + 25506 LUT4 0EE0 (A+B)(C^D) + 25507 LUT4 F888 (AB)+(CD) + 25508 LUT4 7077 /AB\(d+C) + 25509 LUT4 F888 (AB)+(CD) + 25510 LUT4 F888 (AB)+(CD) + 25511 LUT4 F888 (AB)+(CD) + 25512 LUT4 0777 /AB\(d+c) + 25513 LUT4 F888 (AB)+(CD) + 25514 LUT4 0777 /AB\(d+c) + 25515 LUT4 F888 (AB)+(CD) + 25516 LUT4 0777 /AB\(d+c) + 25517 LUT4 0777 /AB\(d+c) + 25518 LUT4 0777 /AB\(d+c) + 25519 LUT4 0777 /AB\(d+c) + 25520 LUT4 70FF (C/AB\)+d + 25521 LUT4 F888 (AB)+(CD) + 25522 LUT4 0777 /AB\(d+c) + 25523 LUT4 F888 (AB)+(CD) + 25524 LUT4 F888 (AB)+(CD) + 25525 LUT4 0777 /AB\(d+c) + 25526 LUT4 70FF (C/AB\)+d + 25527 LUT4 0777 /AB\(d+c) + 25528 LUT4 F888 (AB)+(CD) + 25529 LUT4 F888 (AB)+(CD) + 25530 LUT4 0777 /AB\(d+c) + 25531 LUT4 F888 (AB)+(CD) + 25532 LUT4 F888 (AB)+(CD) + 25533 LUT4 F888 (AB)+(CD) + 25534 LUT4 F888 (AB)+(CD) + 25535 LUT4 F888 (AB)+(CD) + 25536 LUT4 4F44 (aB)+(cD) + 25537 LUT4 40FF (aBC)+d + 25538 LUT4 4F44 (aB)+(cD) + 25539 LUT4 40FF (aBC)+d + 25540 LUT4 8000 ABCD + 25541 LUT3 CA C?A:B + 25542 LUT4 C00A DC?A:0:0:B + 25543 LUT4 ACCC DC?B:B:B:A + 25544 LUT3 CA C?A:B + 25545 LUT4 C00A DC?A:0:0:B + 25546 LUT4 ACCC DC?B:B:B:A + 25547 LUT3 10 abC + 25548 LUT4 CA00 D(C?A:B) + 25549 LUT3 CA C?A:B + 25550 LUT3 CA C?A:B + 25551 LUT4 0AC0 DC?0:A:B:0 + 25552 LUT4 6FFF (A^B)+c+d + 25553 LUT4 004F ((aB)+c)d + 25554 LUT4 FF10 (abC)+D + 25555 LUT4 ACCC DC?B:B:B:A + 25556 LUT4 CACC DC?B:A:B:B + 25557 LUT4 ACCC DC?B:B:B:A + 25558 LUT4 CACC DC?B:A:B:B + 25559 LUT4 8000 ABCD + 25560 LUT4 0AF3 DC?b:A:1:0 + 25561 LUT3 70 C/AB\ + 25562 LUT4 B35C DC?B:b:a:/aB\ + 25563 LUT4 8FF0 DC?0:1:1:AB + 25564 LUT4 E0FF (C/ab\)+d + 25565 LUT4 B0FF (C/aB\)+d + 25566 LUT4 0700 cD/AB\ + 25567 LUT4 B000 CD/aB\ + 25568 LUT4 1000 abCD + 25569 LUT4 0700 cD/AB\ + 25570 LUT4 4F00 ((aB)+c)D + 25571 LUT4 0700 cD/AB\ + 25572 LUT4 0D00 cD/Ab\ + 25573 LUT4 50B8 BD?C:A:aC:aC + 25574 LUT4 50CF DC?1:0:B:a + 25575 LUT4 4FFF (aB)+c+d + 25576 LUT4 70CC BD?0:1:C:aC + 25577 LUT4 1000 abCD + 25578 LUT4 3500 D(c?b:a) + 25579 LUT4 3F40 BD?0:aC:1:c + 25580 LUT4 0D00 cD/Ab\ + 25581 LUT4 1F00 ((ab)+c)D + 25582 LUT4 4F00 ((aB)+c)D + 25583 LUT3 4F (aB)+c + 25584 LUT4 3037 BD?1:ac:C:0 + 25585 LUT4 00F1 ((ab)+C)d + 25586 LUT4 4000 aBCD + 25587 LUT4 0700 cD/AB\ + 25588 LUT4 EF00 ((/ab\)+c)D + 25589 LUT4 D000 CD/Ab\ + 25590 LUT3 1F (ab)+c + 25591 LUT4 233F BD?1:c:/aC\:0 + 25592 LUT3 70 C/AB\ + 25593 LUT4 E000 CD/ab\ + 25594 LUT4 0E00 cD/ab\ + 25595 LUT4 50B8 BD?C:A:aC:aC + 25596 LUT4 50CF DC?1:0:B:a + 25597 LUT2 7 /AB\ + 25598 LUT4 0007 cd/AB\ + 25599 LUT4 4CC5 AB?cd:0:1:C^D + 25600 LUT4 B850 BD?aC:aC:C:A + 25601 LUT4 50CF DC?1:0:B:a + 25602 LUT4 D000 CD/Ab\ + 25603 LUT4 3F40 BD?0:aC:1:c + 25604 LUT4 4F00 ((aB)+c)D + 25605 LUT4 8F00 ((AB)+c)D + 25606 LUT4 311F DC?1:ab:ab:b + 25607 LUT4 4000 aBCD + 25608 LUT4 0DCC BD?0:1:ac:c + 25609 LUT4 C0CD BD?ac:1:0:C + 25610 LUT4 5130 BD?C:0:a:aC + 25611 LUT4 CDD0 DC?0:/Ab\:/Ab\:B + 25612 LUT4 50B8 BD?C:A:aC:aC + 25613 LUT4 50CF DC?1:0:B:a + 25614 LUT4 50B8 BD?C:A:aC:aC + 25615 LUT4 50CF DC?1:0:B:a + 25616 LUT4 0305 DC?a:b:0:0 + 25617 LUT4 5F0C DC?B:1:0:a + 25618 LUT4 CDD0 DC?0:/Ab\:/Ab\:B + 25619 LUT4 3F40 BD?0:aC:1:c + 25620 LUT4 0D00 cD/Ab\ + 25621 LUT4 4F00 ((aB)+c)D + 25622 LUT4 70FF (C/AB\)+d + 25623 LUT4 C0CD BD?ac:1:0:C + 25624 LUT4 CDD0 DC?0:/Ab\:/Ab\:B + 25625 LUT4 7000 CD/AB\ + 25626 LUT4 B000 CD/aB\ + 25627 LUT4 3553 DC?b:a:a:b + 25628 LUT4 7000 CD/AB\ + 25629 LUT4 3037 BD?1:ac:C:0 + 25630 LUT4 4000 aBCD + 25631 LUT4 70FF (C/AB\)+d + 25632 LUT4 0C05 DC?a:B:0:0 + 25633 LUT4 04F0 DC?0:aB:1:0 + 25634 LUT4 C531 BC?a:aD:d:D + 25635 LUT4 CFA0 DC?0:1:A:B + 25636 LUT4 03AF DC?1:b:A:0 + 25637 LUT4 CFA0 DC?0:1:A:B + 25638 LUT4 FF07 (c/AB\)+D + 25639 LUT4 4F00 ((aB)+c)D + 25640 LUT3 70 C/AB\ + 25641 LUT4 233F BD?1:c:/aC\:0 + 25642 LUT4 E000 CD/ab\ + 25643 LUT4 50B8 BD?C:A:aC:aC + 25644 LUT4 50CF DC?1:0:B:a + 25645 LUT3 BF /aB\+c + 25646 LUT4 1513 AB?1:cd:cD:0 + 25647 LUT4 0D00 cD/Ab\ + 25648 LUT4 50B8 BD?C:A:aC:aC + 25649 LUT4 50CF DC?1:0:B:a + 25650 LUT2 7 /AB\ + 25651 LUT4 CC0D BD?ac:c:0:1 + 25652 LUT4 B0A2 AC?0:bd:bD:1 + 25653 LUT4 7000 CD/AB\ + 25654 LUT3 40 aBC + 25655 LUT4 7000 CD/AB\ + 25656 LUT3 B0 C/aB\ + 25657 LUT4 2FFF (Ab)+c+d + 25658 LUT4 50B8 BD?C:A:aC:aC + 25659 LUT4 50CF DC?1:0:B:a + 25660 LUT4 453F BD?1:c:ac:a + 25661 LUT4 4000 aBCD + 25662 LUT4 7000 CD/AB\ + 25663 LUT4 CFA0 DC?0:1:A:B + 25664 LUT4 0D00 cD/Ab\ + 25665 LUT4 1F00 ((ab)+c)D + 25666 LUT4 B0FF (C/aB\)+d + 25667 LUT4 CC0D BD?ac:c:0:1 + 25668 LUT4 B0A2 AC?0:bd:bD:1 + 25669 LUT3 80 ABC + 25670 LUT4 7000 CD/AB\ + 25671 LUT4 0700 cD/AB\ + 25672 LUT4 1F00 ((ab)+c)D + 25673 LUT4 00F1 ((ab)+C)d + 25674 LUT2 7 /AB\ + 25675 LUT4 FCFA DC?A:B:1:1 + 25676 LUT4 F088 D?AB:C + 25677 LUT4 CFA0 DC?0:1:A:B + 25678 LUT4 D000 CD/Ab\ + 25679 LUT4 8F00 ((AB)+c)D + 25680 LUT4 004F ((aB)+c)d + 25681 LUT2 7 /AB\ + 25682 LUT4 5F03 DC?b:1:0:a + 25683 LUT4 D000 CD/Ab\ + 25684 LUT4 7000 CD/AB\ + 25685 LUT4 0700 cD/AB\ + 25686 LUT4 BF4C BC?D:1:D:a^D + 25687 LUT4 3500 D(c?b:a) + 25688 LUT4 50B8 BD?C:A:aC:aC + 25689 LUT4 50CF DC?1:0:B:a + 25690 LUT4 FFF8 (AB)+C+D + 25691 LUT4 0700 cD/AB\ + 25692 LUT4 CFA0 DC?0:1:A:B + 25693 LUT4 0D00 cD/Ab\ + 25694 LUT3 40 aBC + 25695 LUT4 4F00 ((aB)+c)D + 25696 LUT4 70FF (C/AB\)+d + 25697 LUT4 0C05 DC?a:B:0:0 + 25698 LUT4 08F0 DC?0:AB:1:0 + 25699 LUT4 1000 abCD + 25700 LUT4 F100 ((ab)+C)D + 25701 LUT4 3BF3 BD?1:C:1:Ac + 25702 LUT4 0356 AB?C^D:c:d:0 + 25703 LUT4 8788 (AB)^(cD) + 25704 LUT4 6996 A^B^c^d + 25705 LUT4 6996 A^B^c^d + 25706 LUT4 5603 AB?c^D:c:D:0 + 25707 LUT4 8788 (AB)^(cD) + 25708 LUT4 B0BB /aB\(d+C) + 25709 LUT4 7D55 AD?1:0:1:B^C + 25710 LUT4 0356 AB?C^D:c:d:0 + 25711 LUT4 8778 (AB)^C^D + 25712 LUT4 6996 A^B^c^d + 25713 LUT4 9669 A^B^c^D + 25714 LUT4 0356 AB?C^D:c:d:0 + 25715 LUT4 8788 (AB)^(cD) + 25716 LUT4 7077 /AB\(d+C) + 25717 LUT4 D755 AD?1:0:1:b^C + 25718 LUT4 5603 AB?c^D:c:D:0 + 25719 LUT4 8788 (AB)^(cD) + 25720 LUT4 0BBB /aB\(d+c) + 25721 LUT4 7D55 AD?1:0:1:B^C + 25722 LUT4 EF10 (abC)^D + 25723 LUT4 6350 AB?C^D:D:C:0 + 25724 LUT4 6996 A^B^c^d + 25725 LUT3 96 A^B^C + 25726 LUT4 8778 (AB)^C^D + 25727 LUT4 10EF (abC)^d + 25728 LUT4 0777 /AB\(d+c) + 25729 LUT4 40FF (aBC)+d + 25730 LUT4 0356 AB?C^D:c:d:0 + 25731 LUT4 8778 (AB)^C^D + 25732 LUT4 9669 A^B^c^D + 25733 LUT4 0356 AB?C^D:c:d:0 + 25734 LUT4 8778 (AB)^C^D + 25735 LUT4 B0BB /aB\(d+C) + 25736 LUT4 D755 AD?1:0:1:b^C + 25737 LUT4 EF10 (abC)^D + 25738 LUT4 6350 AB?C^D:D:C:0 + 25739 LUT4 6996 A^B^c^d + 25740 LUT4 6996 A^B^c^d + 25741 LUT4 BF40 (aBC)^D + 25742 LUT4 0BBB /aB\(d+c) + 25743 LUT4 80FF (ABC)+d + 25744 LUT4 0356 AB?C^D:c:d:0 + 25745 LUT4 8788 (AB)^(cD) + 25746 LUT4 6996 A^B^c^d + 25747 LUT4 6996 A^B^c^d + 25748 LUT4 03A9 AB?c:C^D:0:d + 25749 LUT4 8788 (AB)^(cD) + 25750 LUT4 6996 A^B^c^d + 25751 LUT4 7D55 AD?1:0:1:B^C + 25752 LUT4 0356 AB?C^D:c:d:0 + 25753 LUT4 8788 (AB)^(cD) + 25754 LUT4 6996 A^B^c^d + 25755 LUT4 9669 A^B^c^D + 25756 LUT4 0356 AB?C^D:c:d:0 + 25757 LUT4 6996 A^B^c^d + 25758 LUT4 D755 AD?1:0:1:b^C + 25759 LUT4 EF10 (abC)^D + 25760 LUT4 4BB4 (aB)^c^d + 25761 LUT4 6996 A^B^c^d + 25762 LUT3 8F (AB)+c + 25763 LUT4 0356 AB?C^D:c:d:0 + 25764 LUT4 6996 A^B^c^d + 25765 LUT4 6996 A^B^c^d + 25766 LUT4 8778 (AB)^C^D + 25767 LUT4 7000 CD/AB\ + 25768 LUT4 FEFF /ab\+C+d + 25769 LUT4 4000 aBCD + 25770 LUT4 1000 abCD + 25771 LUT4 07F0 DC?0:/AB\:1:0 + 25772 LUT4 4000 aBCD + 25773 LUT4 1000 abCD + 25774 LUT4 07F0 DC?0:/AB\:1:0 + 25775 LUT4 4000 aBCD + 25776 LUT4 1000 abCD + 25777 LUT4 07F0 DC?0:/AB\:1:0 + 25778 LUT4 4000 aBCD + 25779 LUT4 1000 abCD + 25780 LUT4 07F0 DC?0:/AB\:1:0 + 25781 LUT4 4000 aBCD + 25782 LUT4 1000 abCD + 25783 LUT4 07F0 DC?0:/AB\:1:0 + 25784 LUT4 0001 abcd + 25785 LUT4 8000 ABCD + 25786 LUT4 0DF0 DC?0:/Ab\:1:0 + 25787 LUT4 0100 abcD + 25788 LUT3 80 ABC + 25789 LUT4 CB00 D(BC?1:A:0:1) + 25790 LUT4 01FF (abc)+d + 25791 LUT4 0777 /AB\(d+c) + 25792 LUT4 8000 ABCD + 25793 LUT4 8FFF (AB)+c+d + 25794 LUT4 1F00 ((ab)+c)D + 25795 LUT4 7000 CD/AB\ + 25796 LUT3 7F /AB\+c + 25797 LUT4 F888 (AB)+(CD) + 25798 LUT4 7000 CD/AB\ + 25799 LUT4 7000 CD/AB\ + 25800 LUT4 8FFF (AB)+c+d + 25801 LUT4 F888 (AB)+(CD) + 25802 LUT4 8000 ABCD + 25803 LUT4 7000 CD/AB\ + 25804 LUT4 8FFF (AB)+c+d + 25805 LUT4 F888 (AB)+(CD) + 25806 LUT4 7000 CD/AB\ + 25807 LUT4 7000 CD/AB\ + 25808 LUT4 8FFF (AB)+c+d + 25809 LUT4 F888 (AB)+(CD) + 25810 LUT4 7000 CD/AB\ + 25811 LUT4 7000 CD/AB\ + 25812 LUT4 8FFF (AB)+c+d + 25813 LUT4 F888 (AB)+(CD) + 25814 LUT4 7000 CD/AB\ + 25815 LUT4 7000 CD/AB\ + 25816 LUT4 8FFF (AB)+c+d + 25817 LUT4 F888 (AB)+(CD) + 25818 LUT4 7000 CD/AB\ + 25819 LUT4 7000 CD/AB\ + 25820 LUT4 8FFF (AB)+c+d + 25821 LUT4 F088 D?AB:C + 25822 LUT4 BF00 ((/aB\)+c)D + 25823 LUT3 F4 (aB)+C + 25824 LUT4 004F ((aB)+c)d + 25825 LUT3 F8 (AB)+C + 25826 LUT4 5F03 DC?b:1:0:a + 25827 LUT4 000D cd/Ab\ + 25828 LUT4 9009 (a^B)(D^c) + 25829 LUT4 8000 ABCD + 25830 LUT3 80 ABC + 25831 LUT4 9009 (a^B)(D^c) + 25832 LUT4 9009 (a^B)(D^c) + 25833 LUT4 007F ((/AB\)+c)d + 25834 LUT4 B0BB /aB\(d+C) + 25835 LUT4 0110 ab(C^D) + 25836 LUT4 7007 (c^D)/AB\ + 25837 LUT4 8000 ABCD + 25838 LUT4 9000 CD(a^B) + 25839 LUT4 0777 /AB\(d+c) + 25840 LUT4 B0FF (C/aB\)+d + 25841 LUT4 B000 CD/aB\ + 25842 LUT4 CFA0 DC?0:1:A:B + 25843 LUT4 FC0A DC?A:B:0:1 + 25844 LUT4 0777 /AB\(d+c) + 25845 LUT4 8000 ABCD + 25846 LUT4 CFA0 DC?0:1:A:B + 25847 LUT4 FC0A DC?A:B:0:1 + 25848 LUT4 8000 ABCD + 25849 LUT4 8FFF (AB)+c+d + 25850 LUT4 CFA0 DC?0:1:A:B + 25851 LUT4 FC0A DC?A:B:0:1 + 25852 LUT4 8000 ABCD + 25853 LUT4 7000 CD/AB\ + 25854 LUT4 CFA0 DC?0:1:A:B + 25855 LUT4 FC0A DC?A:B:0:1 + 25856 LUT4 8000 ABCD + 25857 LUT4 7000 CD/AB\ + 25858 LUT4 CFA0 DC?0:1:A:B + 25859 LUT4 FC0A DC?A:B:0:1 + 25860 LUT4 8000 ABCD + 25861 LUT3 70 C/AB\ + 25862 LUT4 CFA0 DC?0:1:A:B + 25863 LUT4 FC0A DC?A:B:0:1 + 25864 LUT4 7000 CD/AB\ + 25865 LUT4 7000 CD/AB\ + 25866 LUT4 CFA0 DC?0:1:A:B + 25867 LUT4 FC0A DC?A:B:0:1 + 25868 LUT4 8000 ABCD + 25869 LUT4 8FFF (AB)+c+d + 25870 LUT4 CFA0 DC?0:1:A:B + 25871 LUT4 FC0A DC?A:B:0:1 + 25872 LUT4 7000 CD/AB\ + 25873 LUT4 8FFF (AB)+c+d + 25874 LUT4 CFA0 DC?0:1:A:B + 25875 LUT4 FC0A DC?A:B:0:1 + 25876 LUT4 7000 CD/AB\ + 25877 LUT4 8FFF (AB)+c+d + 25878 LUT4 CFA0 DC?0:1:A:B + 25879 LUT4 FC0A DC?A:B:0:1 + 25880 LUT4 8000 ABCD + 25881 LUT4 7000 CD/AB\ + 25882 LUT4 CFA0 DC?0:1:A:B + 25883 LUT4 FC0A DC?A:B:0:1 + 25884 LUT4 8000 ABCD + 25885 LUT4 7000 CD/AB\ + 25886 LUT4 CFA0 DC?0:1:A:B + 25887 LUT4 FC0A DC?A:B:0:1 + 25888 LUT4 7000 CD/AB\ + 25889 LUT4 8FFF (AB)+c+d + 25890 LUT4 CFA0 DC?0:1:A:B + 25891 LUT4 FC0A DC?A:B:0:1 + 25892 LUT4 7000 CD/AB\ + 25893 LUT4 7000 CD/AB\ + 25894 LUT4 CFA0 DC?0:1:A:B + 25895 LUT4 FC0A DC?A:B:0:1 + 25896 LUT4 8000 ABCD + 25897 LUT4 7000 CD/AB\ + 25898 LUT4 EF30 BD?C:0:/aC\:1 + 25899 LUT4 075D AC?1:B^D:d:0 + 25900 LUT4 7000 CD/AB\ + 25901 LUT3 40 aBC + 25902 LUT4 2FFF (Ab)+c+d + 25903 LUT4 B00B /aB\/D^C\ + 25904 LUT4 9000 CD(a^B) + 25905 LUT4 4000 aBCD + 25906 LUT4 8001 AB?cd:0:0:CD + 25907 LUT4 8000 ABCD + 25908 LUT4 8001 AB?cd:0:0:CD + 25909 LUT4 8001 AB?cd:0:0:CD + 25910 LUT4 8001 AB?cd:0:0:CD + 25911 LUT3 80 ABC + 25912 LUT4 8000 ABCD + 25913 LUT4 8001 AB?cd:0:0:CD + 25914 LUT4 8001 AB?cd:0:0:CD + 25915 LUT4 1400 D(B^C)a + 25916 LUT4 70CC BD?0:1:C:aC + 25917 LUT4 CC70 BD?C:aC:0:1 + 25918 LUT4 70CC BD?0:1:C:aC + 25919 LUT4 CC70 BD?C:aC:0:1 + 25920 LUT4 6000 CD(A^B) + 25921 LUT3 CA C?A:B + 25922 LUT4 6000 CD(A^B) + 25923 LUT4 70CC BD?0:1:C:aC + 25924 LUT4 CC70 BD?C:aC:0:1 + 25925 LUT4 5A3C DC?B:A:b:a + 25926 LUT4 53AC (C?b:a)^d + 25927 LUT4 6000 CD(A^B) + 25928 LUT4 70CC BD?0:1:C:aC + 25929 LUT4 CC70 BD?C:aC:0:1 + 25930 LUT4 0BBB /aB\(d+c) + 25931 LUT4 1FE0 AC?D:D:B^D:d + 25932 LUT4 6000 CD(A^B) + 25933 LUT4 1001 ab(c^D) + 25934 LUT4 4000 aBCD + 25935 LUT4 4000 aBCD + 25936 LUT4 B00B /aB\/D^C\ + 25937 LUT4 9000 CD(a^B) + 25938 LUT4 4000 aBCD + 25939 LUT4 8000 ABCD + 25940 LUT4 B00B /aB\/D^C\ + 25941 LUT4 9009 (a^B)(D^c) + 25942 LUT4 8000 ABCD + 25943 LUT4 4000 aBCD + 25944 LUT4 8000 ABCD + 25945 LUT4 B0BB /aB\(d+C) + 25946 LUT4 B033 BD?1:0:C:AC + 25947 LUT4 B00B /aB\/D^C\ + 25948 LUT4 BF00 ((/aB\)+c)D + 25949 LUT4 8F00 ((AB)+c)D + 25950 LUT4 8F00 ((AB)+c)D + 25951 LUT4 8000 ABCD + 25952 LUT4 9009 (a^B)(D^c) + 25953 LUT4 B0BB /aB\(d+C) + 25954 LUT4 0B00 cD/aB\ + 25955 LUT4 9009 (a^B)(D^c) + 25956 LUT4 8000 ABCD + 25957 LUT4 4F44 (aB)+(cD) + 25958 LUT4 0BFF (c/aB\)+d + 25959 LUT4 B00B /aB\/D^C\ + 25960 LUT4 8000 ABCD + 25961 LUT4 8000 ABCD + 25962 LUT4 4F44 (aB)+(cD) + 25963 LUT4 B00B /aB\/D^C\ + 25964 LUT4 7000 CD/AB\ + 25965 LUT4 B0BB /aB\(d+C) + 25966 LUT4 B033 BD?1:0:C:AC + 25967 LUT4 B000 CD/aB\ + 25968 LUT4 8000 ABCD + 25969 LUT4 9009 (a^B)(D^c) + 25970 LUT4 B0BB /aB\(d+C) + 25971 LUT4 4000 aBCD + 25972 LUT4 8000 ABCD + 25973 LUT4 B0BB /aB\(d+C) + 25974 LUT4 9000 CD(a^B) + 25975 LUT4 8000 ABCD + 25976 LUT4 8000 ABCD + 25977 LUT4 4F44 (aB)+(cD) + 25978 LUT4 9009 (a^B)(D^c) + 25979 LUT4 8000 ABCD + 25980 LUT4 7000 CD/AB\ + 25981 LUT4 B0BB /aB\(d+C) + 25982 LUT4 B303 BD?c:0:1:AC + 25983 LUT4 9000 CD(a^B) + 25984 LUT4 B00B /aB\/D^C\ + 25985 LUT4 8000 ABCD + 25986 LUT4 8000 ABCD + 25987 LUT4 9009 (a^B)(D^c) + 25988 LUT4 B00B /aB\/D^C\ + 25989 LUT4 B00B /aB\/D^C\ + 25990 LUT4 8000 ABCD + 25991 LUT4 9009 (a^B)(D^c) + 25992 LUT4 B0BB /aB\(d+C) + 25993 LUT4 9009 (a^B)(D^c) + 25994 LUT3 80 ABC + 25995 LUT4 8700 AD?0:0:c:b^C + 25996 LUT4 8700 AD?0:0:c:b^C + 25997 LUT4 1001 ab(c^D) + 25998 LUT4 1000 abCD + 25999 LUT4 4000 aBCD + 26000 LUT4 BF00 ((/aB\)+c)D + 26001 LUT4 8700 AD?0:0:c:b^C + 26002 LUT4 4100 D(B^c)a + 26003 LUT4 8000 ABCD + 26004 LUT4 8000 ABCD + 26005 LUT4 8000 ABCD + 26006 LUT4 B00B /aB\/D^C\ + 26007 LUT4 8000 ABCD + 26008 LUT4 CFA0 DC?0:1:A:B + 26009 LUT4 1FFF (ab)+c+d + 26010 LUT4 0007 cd/AB\ + 26011 LUT3 8F (AB)+c + 26012 LUT4 0777 /AB\(d+c) + 26013 LUT4 8F00 ((AB)+c)D + 26014 LUT4 F077 D?/AB\:C + 26015 LUT4 0777 /AB\(d+c) + 26016 LUT4 10FF (abC)+d + 26017 LUT4 7000 CD/AB\ + 26018 LUT4 0777 /AB\(d+c) + 26019 LUT4 70FF (C/AB\)+d + 26020 LUT4 7FFF /AB\+c+d + 26021 LUT4 D000 CD/Ab\ + 26022 LUT4 0777 /AB\(d+c) + 26023 LUT4 70FF (C/AB\)+d + 26024 LUT4 7F00 ((/AB\)+c)D + 26025 LUT4 70CC BD?0:1:C:aC + 26026 LUT4 CC70 BD?C:aC:0:1 + 26027 LUT4 4000 aBCD + 26028 LUT4 6000 CD(A^B) + 26029 LUT4 70CC BD?0:1:C:aC + 26030 LUT4 CC70 BD?C:aC:0:1 + 26031 LUT4 1400 D(B^C)a + 26032 LUT4 9000 CD(a^B) + 26033 LUT4 0700 cD/AB\ + 26034 LUT4 70FF (C/AB\)+d + 26035 LUT4 1000 abCD + 26036 LUT4 01FF (abc)+d + 26037 LUT4 FEFF /ab\+C+d + 26038 LUT4 7770 /AB\(D+C) + 26039 LUT4 F800 ((AB)+C)D + 26040 LUT4 8001 AB?cd:0:0:CD + 26041 LUT4 8000 ABCD + 26042 LUT4 8001 AB?cd:0:0:CD + 26043 LUT4 8001 AB?cd:0:0:CD + 26044 LUT4 8001 AB?cd:0:0:CD + 26045 LUT3 80 ABC + 26046 LUT4 8000 ABCD + 26047 LUT4 8001 AB?cd:0:0:CD + 26048 LUT4 8100 D(AB?c:0:0:C) + 26049 LUT4 8001 AB?cd:0:0:CD + 26050 LUT4 8100 D(AB?c:0:0:C) + 26051 LUT4 8001 AB?cd:0:0:CD + 26052 LUT4 8001 AB?cd:0:0:CD + 26053 LUT4 8001 AB?cd:0:0:CD + 26054 LUT4 8001 AB?cd:0:0:CD + 26055 LUT4 8000 ABCD + 26056 LUT4 8000 ABCD + 26057 LUT4 8001 AB?cd:0:0:CD + 26058 LUT4 8100 D(AB?c:0:0:C) + 26059 LUT4 8001 AB?cd:0:0:CD + 26060 LUT4 4000 aBCD + 26061 LUT3 80 ABC + 26062 LUT4 8001 AB?cd:0:0:CD + 26063 LUT4 8100 D(AB?c:0:0:C) + 26064 LUT4 8001 AB?cd:0:0:CD + 26065 LUT4 8000 ABCD + 26066 LUT4 8001 AB?cd:0:0:CD + 26067 LUT4 8001 AB?cd:0:0:CD + 26068 LUT4 8001 AB?cd:0:0:CD + 26069 LUT3 80 ABC + 26070 LUT4 8000 ABCD + 26071 LUT4 8001 AB?cd:0:0:CD + 26072 LUT4 8001 AB?cd:0:0:CD + 26073 LUT4 8001 AB?cd:0:0:CD + 26074 LUT4 8000 ABCD + 26075 LUT4 8001 AB?cd:0:0:CD + 26076 LUT4 8100 D(AB?c:0:0:C) + 26077 LUT4 8000 ABCD + 26078 LUT2 8 AB + 26079 LUT4 B00B /aB\/D^C\ + 26080 LUT4 B000 CD/aB\ + 26081 LUT4 9009 (a^B)(D^c) + 26082 LUT4 B00B /aB\/D^C\ + 26083 LUT4 8000 ABCD + 26084 LUT4 8000 ABCD + 26085 LUT4 4100 D(B^c)a + 26086 LUT4 9009 (a^B)(D^c) + 26087 LUT4 9000 CD(a^B) + 26088 LUT3 80 ABC + 26089 LUT4 111F (ab)+(cd) + 26090 LUT4 8000 ABCD + 26091 LUT2 8 AB + 26092 LUT4 9009 (a^B)(D^c) + 26093 LUT4 9000 CD(a^B) + 26094 LUT4 4FFF (aB)+c+d + 26095 LUT4 40FF (aBC)+d + 26096 LUT4 007F ((/AB\)+c)d + 26097 LUT4 8000 ABCD + 26098 LUT4 1428 (B^C)(A^D) + 26099 LUT4 0EE0 (A+B)(C^D) + 26100 LUT4 8000 ABCD + 26101 LUT4 9009 (a^B)(D^c) + 26102 LUT4 F888 (AB)+(CD) + 26103 LUT4 0777 /AB\(d+c) + 26104 LUT4 7000 CD/AB\ + 26105 LUT4 F888 (AB)+(CD) + 26106 LUT4 8000 ABCD + 26107 LUT4 F888 (AB)+(CD) + 26108 LUT4 7000 CD/AB\ + 26109 LUT4 0777 /AB\(d+c) + 26110 LUT4 4F00 ((aB)+c)D + 26111 LUT4 07FF (c/AB\)+d + 26112 LUT4 4000 aBCD + 26113 LUT4 8000 ABCD + 26114 LUT4 F888 (AB)+(CD) + 26115 LUT4 0777 /AB\(d+c) + 26116 LUT4 4114 AB?C^D:0:c^D:0 + 26117 LUT4 9600 D(A^B^C) + 26118 LUT4 9000 CD(a^B) + 26119 LUT2 8 AB + 26120 LUT4 9000 CD(a^B) + 26121 LUT4 1001 ab(c^D) + 26122 LUT4 9600 D(A^B^C) + 26123 LUT3 40 aBC + 26124 LUT4 0777 /AB\(d+c) + 26125 LUT4 70FF (C/AB\)+d + 26126 LUT4 F888 (AB)+(CD) + 26127 LUT4 F70F DC?1:/AB\:0:1 + 26128 LUT4 DC30 BD?C:0:aC:1 + 26129 LUT4 11F0 D?C:ab + 26130 LUT4 05F3 DC?b:a:1:0 + 26131 LUT4 73C0 BD?0:C:1:aC + 26132 LUT4 8000 ABCD + 26133 LUT4 770F D?c:/AB\ + 26134 LUT3 07 c/AB\ + 26135 LUT4 880F D?c:AB + 26136 LUT4 7000 CD/AB\ + 26137 LUT4 3A00 D(c?b:A) + 26138 LUT4 F888 (AB)+(CD) + 26139 LUT4 7F00 ((/AB\)+c)D + 26140 LUT4 7000 CD/AB\ + 26141 LUT4 7000 CD/AB\ + 26142 LUT4 0777 /AB\(d+c) + 26143 LUT4 88F0 D?C:AB + 26144 LUT4 37F0 DC?0:/AB\:1:b + 26145 LUT4 0777 /AB\(d+c) + 26146 LUT4 FC0A DC?A:B:0:1 + 26147 LUT4 9000 CD(a^B) + 26148 LUT4 4000 aBCD + 26149 LUT4 B0BB /aB\(d+C) + 26150 LUT4 8075 AC?d:0:d:b^D + 26151 LUT3 D0 C/Ab\ + 26152 LUT4 B0BB /aB\(d+C) + 26153 LUT4 BEA0 AD?0:C:B^C:1 + 26154 LUT4 1000 abCD + 26155 LUT4 8000 ABCD + 26156 LUT3 80 ABC + 26157 LUT4 0777 /AB\(d+c) + 26158 LUT4 8F00 ((AB)+c)D + 26159 LUT4 0305 DC?a:b:0:0 + 26160 LUT4 70FF (C/AB\)+d + 26161 LUT4 7000 CD/AB\ + 26162 LUT4 0700 cD/AB\ + 26163 LUT4 FC0A DC?A:B:0:1 + 26164 LUT4 FC0A DC?A:B:0:1 + 26165 LUT4 2CC0 BD?0:C:AC:c + 26166 LUT4 0700 cD/AB\ + 26167 LUT3 D0 C/Ab\ + 26168 LUT4 0BBB /aB\(d+c) + 26169 LUT4 70FF (C/AB\)+d + 26170 LUT4 0305 DC?a:b:0:0 + 26171 LUT4 70FF (C/AB\)+d + 26172 LUT4 7000 CD/AB\ + 26173 LUT4 0700 cD/AB\ + 26174 LUT3 10 abC + 26175 LUT4 8F00 ((AB)+c)D + 26176 LUT4 8F00 ((AB)+c)D + 26177 LUT4 8FFF (AB)+c+d + 26178 LUT4 0700 cD/AB\ + 26179 LUT4 A0CF DC?1:0:B:A + 26180 LUT4 07FF (c/AB\)+d + 26181 LUT4 BF00 ((/aB\)+c)D + 26182 LUT3 80 ABC + 26183 LUT4 30FA DC?A:0:1:b + 26184 LUT4 B0FF (C/aB\)+d + 26185 LUT4 4000 aBCD + 26186 LUT3 80 ABC + 26187 LUT4 03AF DC?1:b:A:0 + 26188 LUT4 0700 cD/AB\ + 26189 LUT4 0B00 cD/aB\ + 26190 LUT4 8000 ABCD + 26191 LUT4 0777 /AB\(d+c) + 26192 LUT4 0305 DC?a:b:0:0 + 26193 LUT4 70FF (C/AB\)+d + 26194 LUT4 7000 CD/AB\ + 26195 LUT4 7000 CD/AB\ + 26196 LUT4 F077 D?/AB\:C + 26197 LUT4 CA00 D(C?A:B) + 26198 LUT4 0C0A DC?A:B:0:0 + 26199 LUT3 80 ABC + 26200 LUT4 0BFF (c/aB\)+d + 26201 LUT4 9000 CD(a^B) + 26202 LUT4 4FFF (aB)+c+d + 26203 LUT4 B000 CD/aB\ + 26204 LUT4 CA00 D(C?A:B) + 26205 LUT4 CA00 D(C?A:B) + 26206 LUT4 9009 (a^B)(D^c) + 26207 LUT4 4000 aBCD + 26208 LUT4 4000 aBCD + 26209 LUT3 80 ABC + 26210 LUT4 B00B /aB\/D^C\ + 26211 LUT4 9000 CD(a^B) + 26212 LUT4 8000 ABCD + 26213 LUT4 B00B /aB\/D^C\ + 26214 LUT4 B00B /aB\/D^C\ + 26215 LUT4 8000 ABCD + 26216 LUT4 9000 CD(a^B) + 26217 LUT4 F4FB AC?b^D:d:1:1 + 26218 LUT4 1000 abCD + 26219 LUT4 1000 abCD + 26220 LUT4 8000 ABCD + 26221 LUT4 CFA0 DC?0:1:A:B + 26222 LUT4 FC0A DC?A:B:0:1 + 26223 LUT4 0777 /AB\(d+c) + 26224 LUT4 7000 CD/AB\ + 26225 LUT4 CFA0 DC?0:1:A:B + 26226 LUT4 FC0A DC?A:B:0:1 + 26227 LUT4 7000 CD/AB\ + 26228 LUT3 70 C/AB\ + 26229 LUT4 CFA0 DC?0:1:A:B + 26230 LUT4 FC0A DC?A:B:0:1 + 26231 LUT4 0777 /AB\(d+c) + 26232 LUT4 7000 CD/AB\ + 26233 LUT4 6900 D(A^B^c) + 26234 LUT4 9000 CD(a^B) + 26235 LUT4 9009 (a^B)(D^c) + 26236 LUT4 8000 ABCD + 26237 LUT4 6900 D(A^B^c) + 26238 LUT4 1000 abCD + 26239 LUT4 6000 CD(A^B) + 26240 LUT4 F888 (AB)+(CD) + 26241 LUT4 0777 /AB\(d+c) + 26242 LUT4 8FFF (AB)+c+d + 26243 LUT4 07FF (c/AB\)+d + 26244 LUT4 0700 cD/AB\ + 26245 LUT4 8000 ABCD + 26246 LUT4 8000 ABCD + 26247 LUT4 F888 (AB)+(CD) + 26248 LUT4 0777 /AB\(d+c) + 26249 LUT4 0777 /AB\(d+c) + 26250 LUT4 007F ((/AB\)+c)d + 26251 LUT4 77F0 D?C:/AB\ + 26252 LUT4 0777 /AB\(d+c) + 26253 LUT4 53FF (C?b:a)+d + 26254 LUT4 7C00 D(BC?0:1:1:a) + 26255 LUT4 F088 D?AB:C + 26256 LUT4 0777 /AB\(d+c) + 26257 LUT4 B30F DC?1:b:0:/aB\ + 26258 LUT4 3FD5 BD?a:/Ac\:1:c + 26259 LUT4 0777 /AB\(d+c) + 26260 LUT4 0777 /AB\(d+c) + 26261 LUT4 8F00 ((AB)+c)D + 26262 LUT4 7000 CD/AB\ + 26263 LUT4 F888 (AB)+(CD) + 26264 LUT4 001F ((ab)+c)d + 26265 LUT4 FFF8 (AB)+C+D + 26266 LUT4 0777 /AB\(d+c) + 26267 LUT4 0777 /AB\(d+c) + 26268 LUT4 4F00 ((aB)+c)D + 26269 LUT4 8000 ABCD + 26270 LUT4 8000 ABCD + 26271 LUT4 0777 /AB\(d+c) + 26272 LUT4 004F ((aB)+c)d + 26273 LUT4 4000 aBCD + 26274 LUT4 F888 (AB)+(CD) + 26275 LUT4 0700 cD/AB\ + 26276 LUT4 F888 (AB)+(CD) + 26277 LUT4 7000 CD/AB\ + 26278 LUT4 CFA0 DC?0:1:A:B + 26279 LUT4 FC0A DC?A:B:0:1 + 26280 LUT4 C230 BC?AD:0:d:D + 26281 LUT4 B000 CD/aB\ + 26282 LUT4 50B8 BD?C:A:aC:aC + 26283 LUT4 A0CF DC?1:0:B:A + 26284 LUT4 000D cd/Ab\ + 26285 LUT4 CAFF (C?A:B)+d + 26286 LUT4 7FFF /AB\+c+d + 26287 LUT4 0700 cD/AB\ + 26288 LUT4 C0CD BD?ac:1:0:C + 26289 LUT4 7D0C BC?aD:1:D:aD + 26290 LUT2 7 /AB\ + 26291 LUT4 3500 D(c?b:a) + 26292 LUT4 0CAF DC?1:B:A:0 + 26293 LUT4 1000 abCD + 26294 LUT4 BFFF /aB\+c+d + 26295 LUT4 2ACF BD?c:1:A:Ac + 26296 LUT4 F100 ((ab)+C)D + 26297 LUT4 0700 cD/AB\ + 26298 LUT4 4000 aBCD + 26299 LUT2 7 /AB\ + 26300 LUT4 8A3F BD?1:c:Ac:A + 26301 LUT4 F100 ((ab)+C)D + 26302 LUT4 7000 CD/AB\ + 26303 LUT4 4000 aBCD + 26304 LUT2 7 /AB\ + 26305 LUT4 3500 D(c?b:a) + 26306 LUT4 0CAF DC?1:B:A:0 + 26307 LUT4 4000 aBCD + 26308 LUT3 CA C?A:B + 26309 LUT4 CAFF (C?A:B)+d + 26310 LUT4 BFFF /aB\+c+d + 26311 LUT4 0DCC BD?0:1:ac:c + 26312 LUT4 1000 abCD + 26313 LUT4 0700 cD/AB\ + 26314 LUT4 4F00 ((aB)+c)D + 26315 LUT4 4DFF (AB?c:0:1:c)+d + 26316 LUT4 CF10 BD?aC:0:c:1 + 26317 LUT4 FFF8 (AB)+C+D + 26318 LUT4 0D00 cD/Ab\ + 26319 LUT4 1F00 ((ab)+c)D + 26320 LUT4 B0FF (C/aB\)+d + 26321 LUT3 C1 BC?a:0:0:1 + 26322 LUT4 712B AC?b:d:D:b + 26323 LUT4 4FFF (aB)+c+d + 26324 LUT3 40 aBC + 26325 LUT4 4F00 ((aB)+c)D + 26326 LUT4 B000 CD/aB\ + 26327 LUT4 D700 AD?0:0:1:b^C + 26328 LUT4 7000 CD/AB\ + 26329 LUT4 EFFF /ab\+c+d + 26330 LUT4 4F00 ((aB)+c)D + 26331 LUT4 4000 aBCD + 26332 LUT4 7D55 AD?1:0:1:B^C + 26333 LUT4 1000 abCD + 26334 LUT4 F100 ((ab)+C)D + 26335 LUT2 6 A^B + 26336 LUT4 533F DC?1:b:b:a + 26337 LUT4 7000 CD/AB\ + 26338 LUT4 CFA0 DC?0:1:A:B + 26339 LUT4 03AF DC?1:b:A:0 + 26340 LUT4 3307 BD?c:ac:1:0 + 26341 LUT4 7000 CD/AB\ + 26342 LUT4 1000 abCD + 26343 LUT4 D000 CD/Ab\ + 26344 LUT4 F100 ((ab)+C)D + 26345 LUT4 BFFF /aB\+c+d + 26346 LUT4 3037 BD?1:ac:C:0 + 26347 LUT4 50B8 BD?C:A:aC:aC + 26348 LUT4 50CF DC?1:0:B:a + 26349 LUT4 1000 abCD + 26350 LUT3 7F /AB\+c + 26351 LUT4 CFA0 DC?0:1:A:B + 26352 LUT4 AF03 DC?b:1:0:A + 26353 LUT3 80 ABC + 26354 LUT4 133F BD?1:c:/AC\:0 + 26355 LUT4 1000 abCD + 26356 LUT4 2FFF (Ab)+c+d + 26357 LUT4 E100 AD?0:0:b^C:C + 26358 LUT4 4BB4 (aB)^c^d + 26359 LUT4 7000 CD/AB\ + 26360 LUT4 7000 CD/AB\ + 26361 LUT4 E0FF (C/ab\)+d + 26362 LUT4 BB0F D?c:/aB\ + 26363 LUT4 E0FF (C/ab\)+d + 26364 LUT4 70FF (C/AB\)+d + 26365 LUT4 F888 (AB)+(CD) + 26366 LUT4 03D5 BD?a:/Ac\:c:0 + 26367 LUT4 3A00 D(c?b:A) + 26368 LUT4 778F AD?c:/bC\:1:b + 26369 LUT4 0DCC BD?0:1:ac:c + 26370 LUT4 31F3 BD?1:C:/Ac\:0 + 26371 LUT4 FF80 (ABC)+D + 26372 LUT4 9009 (a^B)(D^c) + 26373 LUT4 8000 ABCD + 26374 LUT4 9000 CD(a^B) + 26375 LUT4 8075 AC?d:0:d:b^D + 26376 LUT4 8700 AD?0:0:c:b^C + 26377 LUT4 9C0F DC?1:B:0:a^B + 26378 LUT4 F800 ((AB)+C)D + 26379 LUT4 1F11 (ab)+(cD) + 26380 LUT4 7F00 ((/AB\)+c)D + 26381 LUT4 B000 CD/aB\ + 26382 LUT4 CFA0 DC?0:1:A:B + 26383 LUT4 FC0A DC?A:B:0:1 + 26384 LUT4 8000 ABCD + 26385 LUT4 7000 CD/AB\ + 26386 LUT4 9009 (a^B)(D^c) + 26387 LUT4 D000 CD/Ab\ + 26388 LUT4 9009 (a^B)(D^c) + 26389 LUT4 8000 ABCD + 26390 LUT4 8001 AB?cd:0:0:CD + 26391 LUT4 8000 ABCD + 26392 LUT4 8000 ABCD + 26393 LUT4 9000 CD(a^B) + 26394 LUT4 6000 CD(A^B) + 26395 LUT4 70CC BD?0:1:C:aC + 26396 LUT4 CC70 BD?C:aC:0:1 + 26397 LUT4 6000 CD(A^B) + 26398 LUT4 6000 CD(A^B) + 26399 LUT4 70CC BD?0:1:C:aC + 26400 LUT4 CC70 BD?C:aC:0:1 + 26401 LUT4 7D55 AD?1:0:1:B^C + 26402 LUT4 B00B /aB\/D^C\ + 26403 LUT4 8000 ABCD + 26404 LUT4 8000 ABCD + 26405 LUT4 9000 CD(a^B) + 26406 LUT4 4F44 (aB)+(cD) + 26407 LUT4 7007 (c^D)/AB\ + 26408 LUT4 8000 ABCD + 26409 LUT4 B0BB /aB\(d+C) + 26410 LUT4 B303 BD?c:0:1:AC + 26411 LUT4 9000 CD(a^B) + 26412 LUT4 4000 aBCD + 26413 LUT4 9000 CD(a^B) + 26414 LUT4 1001 ab(c^D) + 26415 LUT4 9009 (a^B)(D^c) + 26416 LUT4 0100 abcD + 26417 LUT3 80 ABC + 26418 LUT4 0B00 cD/aB\ + 26419 LUT4 8075 AC?d:0:d:b^D + 26420 LUT4 8000 ABCD + 26421 LUT4 9000 CD(a^B) + 26422 LUT4 B00B /aB\/D^C\ + 26423 LUT4 4000 aBCD + 26424 LUT4 8F00 ((AB)+c)D + 26425 LUT4 9000 CD(a^B) + 26426 LUT4 B0BB /aB\(d+C) + 26427 LUT4 B033 BD?1:0:C:AC + 26428 LUT4 8F00 ((AB)+c)D + 26429 LUT4 4000 aBCD + 26430 LUT4 9000 CD(a^B) + 26431 LUT4 9009 (a^B)(D^c) + 26432 LUT2 8 AB + 26433 LUT4 0777 /AB\(d+c) + 26434 LUT4 4F00 ((aB)+c)D + 26435 LUT4 F888 (AB)+(CD) + 26436 LUT4 7000 CD/AB\ + 26437 LUT4 8000 ABCD + 26438 LUT4 9600 D(A^B^C) + 26439 LUT4 9600 D(A^B^C) + 26440 LUT3 40 aBC + 26441 LUT4 F888 (AB)+(CD) + 26442 LUT4 0777 /AB\(d+c) + 26443 LUT4 07FF (c/AB\)+d + 26444 LUT4 7000 CD/AB\ + 26445 LUT4 F888 (AB)+(CD) + 26446 LUT4 0777 /AB\(d+c) + 26447 LUT4 4000 aBCD + 26448 LUT4 7000 CD/AB\ + 26449 LUT4 B0BB /aB\(d+C) + 26450 LUT4 B00B /aB\/D^C\ + 26451 LUT4 C500 D(C?a:B) + 26452 LUT4 B000 CD/aB\ + 26453 LUT4 0807 AC?d:b^D:0:0 + 26454 LUT4 B0BB /aB\(d+C) + 26455 LUT4 8075 AC?d:0:d:b^D + 26456 LUT3 7F /AB\+c + 26457 LUT4 B0FF (C/aB\)+d + 26458 LUT4 B0BB /aB\(d+C) + 26459 LUT4 C500 D(C?a:B) + 26460 LUT4 B00B /aB\/D^C\ + 26461 LUT4 F888 (AB)+(CD) + 26462 LUT4 7F00 ((/AB\)+c)D + 26463 LUT4 3A00 D(c?b:A) + 26464 LUT4 7077 /AB\(d+C) + 26465 LUT4 8F00 ((AB)+c)D + 26466 LUT4 0700 cD/AB\ + 26467 LUT4 4F00 ((aB)+c)D + 26468 LUT4 0BFF (c/aB\)+d + 26469 LUT3 40 aBC + 26470 LUT3 70 C/AB\ + 26471 LUT4 B0FF (C/aB\)+d + 26472 LUT4 7F00 ((/AB\)+c)D + 26473 LUT4 4F00 ((aB)+c)D + 26474 LUT4 0B00 cD/aB\ + 26475 LUT4 8000 ABCD + 26476 LUT4 6900 D(A^B^c) + 26477 LUT4 0700 cD/AB\ + 26478 LUT4 A03F DC?1:0:b:A + 26479 LUT4 3F40 BD?0:aC:1:c + 26480 LUT4 CB00 D(BC?1:A:0:1) + 26481 LUT4 F888 (AB)+(CD) + 26482 LUT4 0777 /AB\(d+c) + 26483 LUT4 8000 ABCD + 26484 LUT4 7000 CD/AB\ + 26485 LUT4 0777 /AB\(d+c) + 26486 LUT4 FFF8 (AB)+C+D + 26487 LUT4 0700 cD/AB\ + 26488 LUT4 8000 ABCD + 26489 LUT4 77F0 D?C:/AB\ + 26490 LUT4 B3D5 AB?1:D:d:C + 26491 LUT4 B000 CD/aB\ + 26492 LUT4 0777 /AB\(d+c) + 26493 LUT4 F8FF (AB)+C+d + 26494 LUT4 1000 abCD + 26495 LUT4 7000 CD/AB\ + 26496 LUT4 1F11 (ab)+(cD) + 26497 LUT4 FFB0 (C/aB\)+D + 26498 LUT4 8F00 ((AB)+c)D + 26499 LUT4 7000 CD/AB\ + 26500 LUT4 07FF (c/AB\)+d + 26501 LUT4 0F88 D?AB:c + 26502 LUT3 80 ABC + 26503 LUT4 8700 AD?0:0:c:b^C + 26504 LUT4 8700 AD?0:0:c:b^C + 26505 LUT4 8F00 ((AB)+c)D + 26506 LUT4 9000 CD(a^B) + 26507 LUT4 0CFE BD?/ac\:1:0:c + 26508 LUT4 400B DC?/aB\:0:0:aB + 26509 LUT4 CDFC BD?C:1:ac:1 + 26510 LUT4 008F ((AB)+c)d + 26511 LUT4 4000 aBCD + 26512 LUT4 9003 DC?b:0:0:a^B + 26513 LUT4 9C0F DC?1:B:0:a^B + 26514 LUT4 B00B /aB\/D^C\ + 26515 LUT3 80 ABC + 26516 LUT4 37F3 BD?1:C:1:ac + 26517 LUT4 B00B /aB\/D^C\ + 26518 LUT4 4100 D(B^c)a + 26519 LUT4 9009 (a^B)(D^c) + 26520 LUT4 8000 ABCD + 26521 LUT4 8000 ABCD + 26522 LUT4 8000 ABCD + 26523 LUT4 9000 CD(a^B) + 26524 LUT4 C500 D(C?a:B) + 26525 LUT4 8075 AC?d:0:d:b^D + 26526 LUT4 8700 AD?0:0:c:b^C + 26527 LUT4 9003 DC?b:0:0:a^B + 26528 LUT4 F444 (aB)+(CD) + 26529 LUT3 7F /AB\+c + 26530 LUT4 B0FF (C/aB\)+d + 26531 LUT4 0D00 cD/Ab\ + 26532 LUT4 FB03 BD?c:0:1:/ac\ + 26533 LUT4 0B00 cD/aB\ + 26534 LUT4 BBB0 /aB\(D+C) + 26535 LUT4 8F00 ((AB)+c)D + 26536 LUT4 F3FA DC?A:b:1:1 + 26537 LUT4 0777 /AB\(d+c) + 26538 LUT4 80FF (ABC)+d + 26539 LUT4 7000 CD/AB\ + 26540 LUT4 1F00 ((ab)+c)D + 26541 LUT4 F8FF (AB)+C+d + 26542 LUT4 F888 (AB)+(CD) + 26543 LUT4 07FF (c/AB\)+d + 26544 LUT4 07FF (c/AB\)+d + 26545 LUT4 E000 CD/ab\ + 26546 LUT4 8000 ABCD + 26547 LUT4 DC03 BD?c:0:aC:1 + 26548 LUT4 887C BD?C:/AC\:0:A + 26549 LUT4 1000 abCD + 26550 LUT3 80 ABC + 26551 LUT3 70 C/AB\ + 26552 LUT4 8075 AC?d:0:d:b^D + 26553 LUT4 8700 AD?0:0:c:b^C + 26554 LUT4 8700 AD?0:0:c:b^C + 26555 LUT4 9C0F DC?1:B:0:a^B + 26556 LUT4 37F3 BD?1:C:1:ac + 26557 LUT4 4182 (b^C)(A^D) + 26558 LUT4 9009 (a^B)(D^c) + 26559 LUT4 1428 (B^C)(A^D) + 26560 LUT4 8000 ABCD + 26561 LUT4 1400 D(B^C)a + 26562 LUT4 8000 ABCD + 26563 LUT3 40 aBC + 26564 LUT4 0F88 D?AB:c + 26565 LUT4 9009 (a^B)(D^c) + 26566 LUT4 B00B /aB\/D^C\ + 26567 LUT4 1000 abCD + 26568 LUT4 8000 ABCD diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/out.v b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/out.v new file mode 100644 index 0000000000000000000000000000000000000000..5200d4dce4ca8ac9734cc45d4dd94702aab270a9 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/out.v @@ -0,0 +1,66735 @@ +// Trace: ./config/el2_pdef.vh:1:1 +// removed ["el2_param_t","*el2_param_t"] +// removed package "el2_pkg" +module el2_btb_tag_hash ( + pc, + hash +); + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:4:24 + input wire [((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1] pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:5:24 + output wire [pt[2139-:9] - 1:0] hash; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:8:5 + assign hash = {(pc[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + 1] ^ pc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:(pt[2172-:9] + pt[2139-:9]) + 1]) ^ pc[pt[2172-:9] + pt[2139-:9]:pt[2172-:9] + 1]}; +endmodule +module el2_btb_tag_hash_fold ( + pc, + hash +); + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:16:24 + input wire [(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1] pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:17:24 + output wire [pt[2139-:9] - 1:0] hash; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:20:5 + assign hash = {pc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:(pt[2172-:9] + pt[2139-:9]) + 1] ^ pc[pt[2172-:9] + pt[2139-:9]:pt[2172-:9] + 1]}; +endmodule +module el2_btb_addr_hash ( + pc, + hash +); + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:29:25 + input wire [pt[2079-:9]:pt[2106-:9]] pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:30:25 + output wire [pt[2172-:9]:pt[2163-:6]] hash; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:34:1 + generate + if (pt[2125-:5]) begin : fold2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:35:4 + assign hash[pt[2172-:9]:pt[2163-:6]] = pc[pt[2115-:9]:pt[2106-:9]] ^ pc[pt[2079-:9]:pt[2070-:9]]; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:39:4 + assign hash[pt[2172-:9]:pt[2163-:6]] = (pc[pt[2115-:9]:pt[2106-:9]] ^ pc[pt[2097-:9]:pt[2088-:9]]) ^ pc[pt[2079-:9]:pt[2070-:9]]; + end + endgenerate +endmodule +module el2_btb_ghr_hash ( + hashin, + ghr, + hash +); + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:49:24 + input wire [pt[2172-:9]:pt[2163-:6]] hashin; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:50:24 + input wire [pt[2236-:8] - 1:0] ghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:51:24 + output wire [pt[2270-:8]:pt[2262-:6]] hash; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:56:4 + generate + if (pt[2241-:5]) begin : ghrhash_cfg1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:57:6 + assign hash[pt[2270-:8]:pt[2262-:6]] = {ghr[pt[2236-:8] - 1:pt[2115-:9] - 1], hashin[pt[2115-:9]:2] ^ ghr[pt[2115-:9] - 2:0]}; + end + else begin : ghrhash_cfg2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/el2_lib.sv:60:6 + assign hash[pt[2270-:8]:pt[2262-:6]] = {hashin[pt[2236-:8] + 1:2] ^ ghr[pt[2236-:8] - 1:0]}; + end + endgenerate +endmodule +module rvdff ( + din, + clk, + rst_l, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:19:27 + parameter WIDTH = 1; + parameter SHORT = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:21:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:22:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:23:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:25:6 + output reg [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:28:1 + generate + if (SHORT == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:29:4 + wire [WIDTH:1] sv2v_tmp_8E98B; + assign sv2v_tmp_8E98B = din; + always @(*) dout = sv2v_tmp_8E98B; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:38:4 + always @(posedge clk or negedge rst_l) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:39:7 + if (rst_l == 0) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:40:9 + dout[WIDTH - 1:0] <= 0; + else + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:42:9 + dout[WIDTH - 1:0] <= din[WIDTH - 1:0]; + end + endgenerate +endmodule +module rvdffs ( + din, + en, + clk, + rst_l, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:49:28 + parameter WIDTH = 1; + parameter SHORT = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:51:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:52:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:53:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:54:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:55:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:58:1 + generate + if (SHORT == 1) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:59:4 + assign dout = din; + end + else begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:62:4 + rvdff #(.WIDTH(WIDTH)) dffs( + .din((en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0])), + .clk(clk), + .rst_l(rst_l), + .dout(dout) + ); + end + endgenerate +endmodule +module rvdffsc ( + din, + en, + clear, + clk, + rst_l, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:68:29 + parameter WIDTH = 1; + parameter SHORT = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:70:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:71:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:72:6 + input wire clear; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:73:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:74:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:75:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:78:4 + wire [WIDTH - 1:0] din_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:79:1 + generate + if (SHORT == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:80:4 + assign dout = din; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:83:4 + assign din_new = {WIDTH {~clear}} & (en ? din[WIDTH - 1:0] : dout[WIDTH - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:84:4 + rvdff #(.WIDTH(WIDTH)) dffsc( + .din(din_new[WIDTH - 1:0]), + .clk(clk), + .rst_l(rst_l), + .dout(dout) + ); + end + endgenerate +endmodule +module rvdff_fpga ( + din, + clk, + clken, + rawclk, + rst_l, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:89:32 + parameter WIDTH = 1; + parameter SHORT = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:91:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:92:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:93:6 + input wire clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:94:6 + input wire rawclk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:95:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:97:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:100:1 + generate + if (SHORT == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:101:4 + assign dout = din; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:105:5 + rvdffs #(.WIDTH(WIDTH)) dffs( + .clk(rawclk), + .en(clken), + .din(din), + .rst_l(rst_l), + .dout(dout) + ); + end + endgenerate +endmodule +module rvdffs_fpga ( + din, + en, + clk, + clken, + rawclk, + rst_l, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:113:33 + parameter WIDTH = 1; + parameter SHORT = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:115:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:116:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:117:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:118:6 + input wire clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:119:6 + input wire rawclk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:120:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:122:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:125:1 + generate + if (SHORT == 1) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:126:4 + assign dout = din; + end + else begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:130:4 + rvdffs #(.WIDTH(WIDTH)) dffs( + .clk(rawclk), + .en(clken & en), + .din(din), + .rst_l(rst_l), + .dout(dout) + ); + end + endgenerate +endmodule +module rvdffsc_fpga ( + din, + en, + clear, + clk, + clken, + rawclk, + rst_l, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:139:34 + parameter WIDTH = 1; + parameter SHORT = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:141:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:142:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:143:6 + input wire clear; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:144:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:145:6 + input wire clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:146:6 + input wire rawclk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:147:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:149:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:152:4 + wire [WIDTH - 1:0] din_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:153:1 + generate + if (SHORT == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:154:4 + assign dout = din; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:158:4 + rvdffs #(.WIDTH(WIDTH)) dffs( + .clk(rawclk), + .din(din[WIDTH - 1:0] & {WIDTH {~clear}}), + .en((en | clear) & clken), + .rst_l(rst_l), + .dout(dout) + ); + end + endgenerate +endmodule +module rvdffe ( + din, + en, + clk, + rst_l, + scan_mode, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:166:28 + parameter WIDTH = 1; + parameter SHORT = 0; + parameter OVERRIDE = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:168:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:169:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:170:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:171:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:172:6 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:173:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:176:4 + wire l1clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:178:1 + generate + if (SHORT == 1) begin : genblock + if (1) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:180:7 + assign dout = din; + end + end + else begin : genblock + if ((WIDTH >= 8) || (OVERRIDE == 1)) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:190:7 + rvdffs #(.WIDTH(WIDTH)) dff( + .din(din), + .en(en), + .clk(clk), + .rst_l(rst_l), + .dout(dout) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:199:7 + $error("%m: rvdffe must be WIDTH >= 8"); + end + end + endgenerate +endmodule +module rvdffpcie ( + din, + clk, + rst_l, + en, + scan_mode, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:206:31 + parameter WIDTH = 31; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:208:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:209:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:210:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:211:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:212:6 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:213:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:219:4 + generate + if (WIDTH == 31) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:223:7 + rvdffs #(.WIDTH(WIDTH)) dff( + .din(din), + .en(en), + .clk(clk), + .rst_l(rst_l), + .dout(dout) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:233:7 + $error("%m: rvdffpcie width must be 31"); + end + endgenerate +endmodule +module rvdfflie ( + din, + clk, + rst_l, + en, + scan_mode, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:239:30 + parameter WIDTH = 16; + parameter LEFT = 8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:241:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:242:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:243:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:244:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:245:6 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:246:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:249:4 + localparam EXTRA = WIDTH - LEFT; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:257:4 + localparam LMSB = WIDTH - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:258:4 + localparam LLSB = (LMSB - LEFT) + 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:259:4 + localparam XMSB = LLSB - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:260:4 + localparam XLSB = LLSB - EXTRA; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:264:4 + generate + if (((WIDTH >= 16) && (LEFT >= 8)) && (EXTRA >= 8)) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:268:7 + rvdffs #(.WIDTH(WIDTH)) dff( + .din(din), + .en(en), + .clk(clk), + .rst_l(rst_l), + .dout(dout) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:284:7 + $error("%m: rvdfflie musb be WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8"); + end + endgenerate +endmodule +module rvdffppe ( + din, + clk, + rst_l, + en, + scan_mode, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:294:30 + parameter WIDTH = 32; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:296:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:297:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:298:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:299:6 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:300:6 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:301:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:304:4 + localparam RIGHT = 31; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:305:4 + localparam LEFT = WIDTH - RIGHT; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:307:4 + localparam LMSB = WIDTH - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:308:4 + localparam LLSB = (LMSB - LEFT) + 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:309:4 + localparam RMSB = LLSB - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:310:4 + localparam RLSB = LLSB - RIGHT; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:314:4 + generate + if (((WIDTH >= 32) && (LEFT >= 8)) && 1'd1) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:318:7 + rvdffs #(.WIDTH(WIDTH)) dff( + .din(din), + .en(en), + .clk(clk), + .rst_l(rst_l), + .dout(dout) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:330:7 + $error("%m: must be WIDTH>=32 && LEFT>=8 && RIGHT>=8"); + end + endgenerate +endmodule +module rvdffie ( + din, + clk, + rst_l, + scan_mode, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:337:29 + parameter WIDTH = 1; + parameter OVERRIDE = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:339:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:341:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:342:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:343:6 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:344:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:347:4 + wire l1clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:348:4 + wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:358:4 + generate + if ((WIDTH >= 8) || (OVERRIDE == 1)) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:361:7 + assign en = |(din ^ dout); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:364:7 + rvdffs #(.WIDTH(WIDTH)) dff( + .din(din), + .en(en), + .clk(clk), + .rst_l(rst_l), + .dout(dout) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:373:6 + $error("%m: rvdffie must be WIDTH >= 8"); + end + endgenerate +endmodule +module rvsyncss ( + clk, + rst_l, + din, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:416:29 + parameter WIDTH = 251; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:418:6 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:419:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:420:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:421:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:424:4 + wire [WIDTH - 1:0] din_ff1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:426:4 + rvdff #(.WIDTH(WIDTH)) sync_ff1( + .clk(clk), + .rst_l(rst_l), + .din(din[WIDTH - 1:0]), + .dout(din_ff1[WIDTH - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:427:4 + rvdff #(.WIDTH(WIDTH)) sync_ff2( + .clk(clk), + .rst_l(rst_l), + .din(din_ff1[WIDTH - 1:0]), + .dout(dout[WIDTH - 1:0]) + ); +endmodule +module rvsyncss_fpga ( + gw_clk, + rawclk, + clken, + rst_l, + din, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:431:34 + parameter WIDTH = 251; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:433:6 + input wire gw_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:434:6 + input wire rawclk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:435:6 + input wire clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:436:6 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:437:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:438:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:441:4 + wire [WIDTH - 1:0] din_ff1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:443:4 + rvdff_fpga #(.WIDTH(WIDTH)) sync_ff1( + .rst_l(rst_l), + .clk(gw_clk), + .rawclk(rawclk), + .clken(clken), + .din(din[WIDTH - 1:0]), + .dout(din_ff1[WIDTH - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:444:4 + rvdff_fpga #(.WIDTH(WIDTH)) sync_ff2( + .rst_l(rst_l), + .clk(gw_clk), + .rawclk(rawclk), + .clken(clken), + .din(din_ff1[WIDTH - 1:0]), + .dout(dout[WIDTH - 1:0]) + ); +endmodule +module rvlsadder ( + rs1, + offset, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:450:5 + input wire [31:0] rs1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:451:5 + input wire [11:0] offset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:453:5 + output wire [31:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:456:4 + wire cout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:457:4 + wire sign; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:459:4 + wire [31:12] rs1_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:460:4 + wire [31:12] rs1_dec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:462:4 + assign {cout, dout[11:0]} = {1'b0, rs1[11:0]} + {1'b0, offset[11:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:464:4 + assign rs1_inc[31:12] = rs1[31:12] + 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:466:4 + assign rs1_dec[31:12] = rs1[31:12] - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:468:4 + assign sign = offset[11]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:470:4 + assign dout[31:12] = (({20 {sign ~^ cout}} & rs1[31:12]) | ({20 {~sign & cout}} & rs1_inc[31:12])) | ({20 {sign & ~cout}} & rs1_dec[31:12]); +endmodule +module rvbradder ( + pc, + offset, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:480:5 + input [31:1] pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:481:5 + input [12:1] offset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:483:5 + output wire [31:1] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:486:4 + wire cout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:487:4 + wire sign; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:489:4 + wire [31:13] pc_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:490:4 + wire [31:13] pc_dec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:492:4 + assign {cout, dout[12:1]} = {1'b0, pc[12:1]} + {1'b0, offset[12:1]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:494:4 + assign pc_inc[31:13] = pc[31:13] + 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:496:4 + assign pc_dec[31:13] = pc[31:13] - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:498:4 + assign sign = offset[12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:501:4 + assign dout[31:13] = (({19 {sign ~^ cout}} & pc[31:13]) | ({19 {~sign & cout}} & pc_inc[31:13])) | ({19 {sign & ~cout}} & pc_dec[31:13]); +endmodule +module rvtwoscomp ( + din, + dout +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:510:32 + parameter WIDTH = 32; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:512:6 + input wire [WIDTH - 1:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:514:6 + output wire [WIDTH - 1:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:517:4 + wire [WIDTH - 1:1] dout_temp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:519:4 + genvar _gv_i_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:521:4 + generate + for (_gv_i_1 = 1; _gv_i_1 < WIDTH; _gv_i_1 = _gv_i_1 + 1) begin : flip_after_first_one + localparam i = _gv_i_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:522:7 + assign dout_temp[i] = (|din[i - 1:0] ? ~din[i] : din[i]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:525:4 + assign dout[WIDTH - 1:0] = {dout_temp[WIDTH - 1:1], din[0]}; +endmodule +module rvmaskandmatch ( + mask, + data, + masken, + match +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:569:36 + parameter WIDTH = 32; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:571:6 + input wire [WIDTH - 1:0] mask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:572:6 + input wire [WIDTH - 1:0] data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:573:6 + input wire masken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:574:6 + output wire match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:577:4 + wire [WIDTH - 1:0] matchvec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:578:4 + wire masken_or_fullmask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:580:4 + assign masken_or_fullmask = masken & ~(&mask[WIDTH - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:582:4 + assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:583:4 + genvar _gv_i_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:585:4 + generate + for (_gv_i_2 = 1; _gv_i_2 < WIDTH; _gv_i_2 = _gv_i_2 + 1) begin : match_after_first_zero + localparam i = _gv_i_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:586:7 + assign matchvec[i] = (&mask[i - 1:0] & masken_or_fullmask ? 1'b1 : mask[i] == data[i]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:589:4 + assign match = &matchvec[WIDTH - 1:0]; +endmodule +module rvrangecheck ( + addr, + in_range, + in_region +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:597:24 + parameter CCM_SADR = 32'h00000000; + parameter CCM_SIZE = 128; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:599:4 + input wire [31:0] addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:600:4 + output wire in_range; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:601:4 + output wire in_region; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:604:4 + localparam REGION_BITS = 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:605:4 + localparam MASK_BITS = 10 + $clog2(CCM_SIZE); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:607:4 + wire [31:0] start_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:608:4 + wire [3:0] region; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:610:4 + assign start_addr[31:0] = CCM_SADR; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:611:4 + assign region[3:0] = start_addr[31:28]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:613:4 + assign in_region = addr[31:28] == region[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:614:4 + generate + if (CCM_SIZE == 48) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:615:5 + assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS - 1:MASK_BITS - 2]); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:617:5 + assign in_range = addr[31:MASK_BITS] == start_addr[31:MASK_BITS]; + end + endgenerate +endmodule +module rveven_paritygen ( + data_in, + parity_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:622:27 + parameter WIDTH = 16; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:623:42 + input wire [WIDTH - 1:0] data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:624:42 + output wire parity_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:627:4 + assign parity_out = ^data_in[WIDTH - 1:0]; +endmodule +module rveven_paritycheck ( + data_in, + parity_in, + parity_err +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:631:29 + parameter WIDTH = 16; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:632:44 + input wire [WIDTH - 1:0] data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:633:44 + input wire parity_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:634:44 + output wire parity_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:637:4 + assign parity_err = ^data_in[WIDTH - 1:0] ^ parity_in; +endmodule +module rvecc_encode ( + din, + ecc_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:642:23 + input [31:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:643:23 + output wire [6:0] ecc_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:645:1 + wire [5:0] ecc_out_temp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:647:4 + assign ecc_out_temp[0] = ((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:648:4 + assign ecc_out_temp[1] = ((((((((((((((((din[0] ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:649:4 + assign ecc_out_temp[2] = ((((((((((((((((din[1] ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:650:4 + assign ecc_out_temp[3] = (((((((((((((din[4] ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:651:4 + assign ecc_out_temp[4] = (((((((((((((din[11] ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:652:4 + assign ecc_out_temp[5] = ((((din[26] ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:654:4 + assign ecc_out[6:0] = {^din[31:0] ^ ^ecc_out_temp[5:0], ecc_out_temp[5:0]}; +endmodule +module rvecc_decode ( + en, + din, + ecc_in, + sed_ded, + dout, + ecc_out, + single_ecc_error, + double_ecc_error +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:659:23 + input en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:660:23 + input [31:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:661:23 + input [6:0] ecc_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:662:23 + input sed_ded; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:663:23 + output wire [31:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:664:23 + output wire [6:0] ecc_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:665:23 + output wire single_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:666:23 + output wire double_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:670:4 + wire [6:0] ecc_check; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:671:4 + wire [38:0] error_mask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:672:4 + wire [38:0] din_plus_parity; + wire [38:0] dout_plus_parity; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:675:4 + assign ecc_check[0] = (((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:676:4 + assign ecc_check[1] = (((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:677:4 + assign ecc_check[2] = (((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:678:4 + assign ecc_check[3] = ((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:679:4 + assign ecc_check[4] = ((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:680:4 + assign ecc_check[5] = (((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:683:4 + assign ecc_check[6] = (^din[31:0] ^ ^ecc_in[6:0]) & ~sed_ded; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:685:4 + assign single_ecc_error = (en & (ecc_check[6:0] != 0)) & ecc_check[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:686:4 + assign double_ecc_error = (en & (ecc_check[6:0] != 0)) & ~ecc_check[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:689:4 + genvar _gv_i_3; + generate + for (_gv_i_3 = 1; _gv_i_3 < 40; _gv_i_3 = _gv_i_3 + 1) begin : genblk1 + localparam i = _gv_i_3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:690:7 + assign error_mask[i - 1] = ecc_check[5:0] == i; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:694:4 + assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:696:4 + assign dout_plus_parity[38:0] = (single_ecc_error ? error_mask[38:0] ^ din_plus_parity[38:0] : din_plus_parity[38:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:697:4 + assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:698:4 + assign ecc_out[6:0] = {dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]}; +endmodule +module rvecc_encode_64 ( + din, + ecc_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:703:23 + input [63:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:704:23 + output wire [6:0] ecc_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:706:3 + assign ecc_out[0] = (((((((((((((((((((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]) ^ din[32]) ^ din[34]) ^ din[36]) ^ din[38]) ^ din[40]) ^ din[42]) ^ din[44]) ^ din[46]) ^ din[48]) ^ din[50]) ^ din[52]) ^ din[54]) ^ din[56]) ^ din[57]) ^ din[59]) ^ din[61]) ^ din[63]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:708:4 + assign ecc_out[1] = (((((((((((((((((((((((((((((((((din[0] ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]) ^ din[32]) ^ din[35]) ^ din[36]) ^ din[39]) ^ din[40]) ^ din[43]) ^ din[44]) ^ din[47]) ^ din[48]) ^ din[51]) ^ din[52]) ^ din[55]) ^ din[56]) ^ din[58]) ^ din[59]) ^ din[62]) ^ din[63]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:710:4 + assign ecc_out[2] = (((((((((((((((((((((((((((((((((din[1] ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:712:4 + assign ecc_out[3] = (((((((((((((((((((((((((((((din[4] ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:714:4 + assign ecc_out[4] = (((((((((((((((((((((((((((((din[11] ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:716:4 + assign ecc_out[5] = (((((((((((((((((((((((((((((din[26] ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:718:4 + assign ecc_out[6] = (((((din[57] ^ din[58]) ^ din[59]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63]; +endmodule +module rvecc_decode_64 ( + en, + din, + ecc_in, + ecc_error +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:724:23 + input en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:725:23 + input [63:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:726:23 + input [6:0] ecc_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:727:23 + output wire ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:730:4 + wire [6:0] ecc_check; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:733:4 + assign ecc_check[0] = ((((((((((((((((((((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]) ^ din[32]) ^ din[34]) ^ din[36]) ^ din[38]) ^ din[40]) ^ din[42]) ^ din[44]) ^ din[46]) ^ din[48]) ^ din[50]) ^ din[52]) ^ din[54]) ^ din[56]) ^ din[57]) ^ din[59]) ^ din[61]) ^ din[63]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:735:4 + assign ecc_check[1] = ((((((((((((((((((((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]) ^ din[32]) ^ din[35]) ^ din[36]) ^ din[39]) ^ din[40]) ^ din[43]) ^ din[44]) ^ din[47]) ^ din[48]) ^ din[51]) ^ din[52]) ^ din[55]) ^ din[56]) ^ din[58]) ^ din[59]) ^ din[62]) ^ din[63]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:737:4 + assign ecc_check[2] = ((((((((((((((((((((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:739:4 + assign ecc_check[3] = ((((((((((((((((((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:741:4 + assign ecc_check[4] = ((((((((((((((((((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:743:4 + assign ecc_check[5] = ((((((((((((((((((((((((((((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:745:4 + assign ecc_check[6] = ((((((ecc_in[6] ^ din[57]) ^ din[58]) ^ din[59]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:747:4 + assign ecc_error = en & (ecc_check[6:0] != 0); +endmodule +module rvoclkhdr ( + en, + clk, + scan_mode, + l1clk +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:796:4 + input wire en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:797:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:798:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:799:4 + output wire l1clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:802:4 + wire SE; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:803:4 + assign SE = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/beh_lib.sv:806:4 + assign l1clk = clk; +endmodule +module el2_mem ( + clk, + rst_l, + dccm_clk_override, + icm_clk_override, + dec_tlu_core_ecc_disable, + dccm_wren, + dccm_rden, + dccm_wr_addr_lo, + dccm_wr_addr_hi, + dccm_rd_addr_lo, + dccm_rd_addr_hi, + dccm_wr_data_lo, + dccm_wr_data_hi, + dccm_rd_data_lo, + dccm_rd_data_hi, + dccm_ext_in_pkt, + iccm_ext_in_pkt, + iccm_rw_addr, + iccm_buf_correct_ecc, + iccm_correction_state, + iccm_wren, + iccm_rden, + iccm_wr_size, + iccm_wr_data, + iccm_rd_data, + iccm_rd_data_ecc, + ic_rw_addr, + ic_tag_valid, + ic_wr_en, + ic_rd_en, + ic_premux_data, + ic_sel_premux_data, + ic_data_ext_in_pkt, + ic_tag_ext_in_pkt, + ic_wr_data, + ic_debug_wr_data, + ic_debug_rd_data, + ic_debug_addr, + ic_debug_rd_en, + ic_debug_wr_en, + ic_debug_tag_array, + ic_debug_way, + ic_rd_data, + ictag_debug_rd_data, + ic_eccerr, + ic_parerr, + ic_rd_hit, + ic_tag_perr, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:24:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:25:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:26:4 + input wire dccm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:27:4 + input wire icm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:28:4 + input wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:31:4 + input wire dccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:32:4 + input wire dccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:33:4 + input wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:34:4 + input wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:35:4 + input wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:36:4 + input wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:37:4 + input wire [pt[1360-:10] - 1:0] dccm_wr_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:38:4 + input wire [pt[1360-:10] - 1:0] dccm_wr_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:41:4 + output wire [pt[1360-:10] - 1:0] dccm_rd_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:42:4 + output wire [pt[1360-:10] - 1:0] dccm_rd_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:45:4 + // removed localparam type el2_pkg_el2_dccm_ext_in_pkt_t + input wire [(pt[1342-:9] * 12) - 1:0] dccm_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:50:4 + // removed localparam type el2_pkg_el2_ccm_ext_in_pkt_t + input wire [(pt[909-:9] * 12) - 1:0] iccm_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:52:4 + input wire [pt[936-:9] - 1:1] iccm_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:53:4 + input wire iccm_buf_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:54:4 + input wire iccm_correction_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:55:4 + input wire iccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:56:4 + input wire iccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:57:4 + input wire [2:0] iccm_wr_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:58:4 + input wire [77:0] iccm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:60:4 + output wire [63:0] iccm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:61:4 + output wire [77:0] iccm_rd_data_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:65:4 + input wire [31:1] ic_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:66:4 + input wire [pt[1060-:7] - 1:0] ic_tag_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:67:4 + input wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:68:4 + input wire ic_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:69:4 + input wire [63:0] ic_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:70:4 + input wire ic_sel_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:71:4 + // removed localparam type el2_pkg_el2_ic_data_ext_in_pkt_t + input wire [((pt[1060-:7] * pt[1189-:7]) * 12) - 1:0] ic_data_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:72:4 + // removed localparam type el2_pkg_el2_ic_tag_ext_in_pkt_t + input wire [(pt[1060-:7] * 12) - 1:0] ic_tag_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:74:4 + input wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:75:4 + input wire [70:0] ic_debug_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:76:4 + output wire [70:0] ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:77:4 + input wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:78:4 + input wire ic_debug_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:79:4 + input wire ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:80:4 + input wire ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:81:4 + input wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:83:4 + output wire [63:0] ic_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:84:4 + output wire [25:0] ictag_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:87:4 + output wire [pt[1189-:7] - 1:0] ic_eccerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:88:4 + output wire [pt[1189-:7] - 1:0] ic_parerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:89:4 + output wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:90:4 + output wire ic_tag_perr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:93:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:97:4 + wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:98:4 + rvoclkhdr active_cg( + .en(1'b1), + .l1clk(active_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:101:4 + generate + if (pt[1365-:5] == 1) begin : Gen_dccm_enable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:102:7 + el2_lsu_dccm_mem #(.pt(pt)) dccm( + .clk_override(dccm_clk_override), + .clk(clk), + .active_clk(active_clk), + .rst_l(rst_l), + .dccm_wren(dccm_wren), + .dccm_rden(dccm_rden), + .dccm_wr_addr_lo(dccm_wr_addr_lo), + .dccm_wr_addr_hi(dccm_wr_addr_hi), + .dccm_rd_addr_lo(dccm_rd_addr_lo), + .dccm_rd_addr_hi(dccm_rd_addr_hi), + .dccm_wr_data_lo(dccm_wr_data_lo), + .dccm_wr_data_hi(dccm_wr_data_hi), + .dccm_ext_in_pkt(dccm_ext_in_pkt), + .dccm_rd_data_lo(dccm_rd_data_lo), + .dccm_rd_data_hi(dccm_rd_data_hi), + .scan_mode(scan_mode) + ); + end + else begin : Gen_dccm_disable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:107:7 + assign dccm_rd_data_lo = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:108:7 + assign dccm_rd_data_hi = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:111:1 + generate + if (pt[1120-:5]) begin : icache + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:112:4 + el2_ifu_ic_mem #(.pt(pt)) icm( + .clk_override(icm_clk_override), + .clk(clk), + .active_clk(active_clk), + .rst_l(rst_l), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .ic_rw_addr(ic_rw_addr), + .ic_wr_en(ic_wr_en), + .ic_rd_en(ic_rd_en), + .ic_debug_addr(ic_debug_addr), + .ic_debug_rd_en(ic_debug_rd_en), + .ic_debug_wr_en(ic_debug_wr_en), + .ic_debug_tag_array(ic_debug_tag_array), + .ic_debug_way(ic_debug_way), + .ic_premux_data(ic_premux_data), + .ic_sel_premux_data(ic_sel_premux_data), + .ic_wr_data(ic_wr_data), + .ic_rd_data(ic_rd_data), + .ic_debug_rd_data(ic_debug_rd_data), + .ictag_debug_rd_data(ictag_debug_rd_data), + .ic_debug_wr_data(ic_debug_wr_data), + .ic_eccerr(ic_eccerr), + .ic_parerr(ic_parerr), + .ic_tag_valid(ic_tag_valid), + .ic_data_ext_in_pkt(ic_data_ext_in_pkt), + .ic_tag_ext_in_pkt(ic_tag_ext_in_pkt), + .ic_rd_hit(ic_rd_hit), + .ic_tag_perr(ic_tag_perr), + .scan_mode(scan_mode) + ); + end + else begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:118:4 + assign ic_rd_hit[pt[1060-:7] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:119:4 + assign ic_tag_perr = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:120:4 + assign ic_rd_data = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:121:4 + assign ictag_debug_rd_data = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:126:1 + generate + if (pt[927-:5]) begin : iccm + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:127:4 + el2_ifu_iccm_mem #(.pt(pt)) iccm( + .clk(clk), + .active_clk(active_clk), + .rst_l(rst_l), + .iccm_wren(iccm_wren), + .iccm_rden(iccm_rden), + .iccm_buf_correct_ecc(iccm_buf_correct_ecc), + .iccm_correction_state(iccm_correction_state), + .iccm_wr_size(iccm_wr_size), + .iccm_wr_data(iccm_wr_data), + .iccm_ext_in_pkt(iccm_ext_in_pkt), + .iccm_rd_data_ecc(iccm_rd_data_ecc), + .scan_mode(scan_mode), + .clk_override(icm_clk_override), + .iccm_rw_addr(iccm_rw_addr[pt[936-:9] - 1:1]), + .iccm_rd_data(iccm_rd_data[63:0]) + ); + end + else begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:134:4 + assign iccm_rd_data = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_mem.sv:135:4 + assign iccm_rd_data_ecc = 1'sb0; + end + endgenerate +endmodule +module el2_pic_ctrl ( + clk, + free_clk, + rst_l, + clk_override, + io_clk_override, + extintsrc_req, + picm_rdaddr, + picm_wraddr, + picm_wr_data, + picm_wren, + picm_rden, + picm_mken, + meicurpl, + meipt, + mexintpend, + claimid, + pl, + picm_rd_data, + mhwakeup, + scan_mode +); + reg _sv2v_0; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:28:22 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:29:22 + input wire free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:30:22 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:31:22 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:32:22 + input wire io_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:33:22 + input wire [pt[44-:13] - 1:0] extintsrc_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:34:22 + input wire [31:0] picm_rdaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:35:22 + input wire [31:0] picm_wraddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:36:22 + input wire [31:0] picm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:37:22 + input wire picm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:38:22 + input wire picm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:39:22 + input wire picm_mken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:40:22 + input wire [3:0] meicurpl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:41:22 + input wire [3:0] meipt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:43:22 + output wire mexintpend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:44:22 + output wire [7:0] claimid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:45:22 + output wire [3:0] pl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:46:22 + output wire [31:0] picm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:47:22 + output wire mhwakeup; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:48:22 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:52:1 + localparam NUM_LEVELS = $clog2(pt[44-:13]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:53:1 + localparam INTPRIORITY_BASE_ADDR = pt[130-:36]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:54:1 + localparam INTPEND_BASE_ADDR = pt[130-:36] + 32'h00001000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:55:1 + localparam INTENABLE_BASE_ADDR = pt[130-:36] + 32'h00002000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:56:1 + localparam EXT_INTR_PIC_CONFIG = pt[130-:36] + 32'h00003000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:57:1 + localparam EXT_INTR_GW_CONFIG = pt[130-:36] + 32'h00004000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:58:1 + localparam EXT_INTR_GW_CLEAR = pt[130-:36] + 32'h00005000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:61:1 + localparam INTPEND_SIZE = (pt[44-:13] < 32 ? 32 : (pt[44-:13] < 64 ? 64 : (pt[44-:13] < 128 ? 128 : (pt[44-:13] < 256 ? 256 : (pt[44-:13] < 512 ? 512 : 1024))))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:67:1 + localparam INT_GRPS = INTPEND_SIZE / 32; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:68:1 + localparam INTPRIORITY_BITS = 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:69:1 + localparam ID_BITS = 8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:70:1 + localparam signed [(pt[44-:13] * 32) - 1:0] GW_CONFIG = {pt[44-:13] {32'sd0}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:72:1 + localparam INT_ENABLE_GRPS = (pt[44-:13] - 1) / 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:74:1 + wire [pt[44-:13] - 1:0] intenable_clk_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:75:1 + wire [INT_ENABLE_GRPS:0] intenable_clk_enable_grp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:76:1 + wire [INT_ENABLE_GRPS:0] gw_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:78:1 + wire addr_intpend_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:80:1 + wire raddr_config_pic_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:81:1 + wire raddr_intenable_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:82:1 + wire raddr_intpriority_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:83:1 + wire raddr_config_gw_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:85:1 + wire waddr_config_pic_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:86:1 + wire waddr_intpriority_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:87:1 + wire waddr_intenable_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:88:1 + wire waddr_config_gw_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:89:1 + wire addr_clear_gw_base_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:91:1 + wire mexintpend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:92:1 + wire mhwakeup_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:93:1 + wire intpend_reg_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:95:1 + wire [31:0] picm_rd_data_in; + reg [31:0] intpend_rd_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:96:1 + reg intenable_rd_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:97:1 + reg [3:0] intpriority_rd_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:98:1 + reg [1:0] gw_config_rd_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:100:1 + wire [(pt[44-:13] * 4) - 1:0] intpriority_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:101:1 + wire [(pt[44-:13] * 4) - 1:0] intpriority_reg_inv; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:102:1 + wire [pt[44-:13] - 1:0] intpriority_reg_we; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:103:1 + wire [pt[44-:13] - 1:0] intpriority_reg_re; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:104:1 + wire [(pt[44-:13] * 2) - 1:0] gw_config_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:106:1 + wire [pt[44-:13] - 1:0] intenable_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:107:1 + wire [pt[44-:13] - 1:0] intenable_reg_we; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:108:1 + wire [pt[44-:13] - 1:0] intenable_reg_re; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:109:1 + wire [pt[44-:13] - 1:0] gw_config_reg_we; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:110:1 + wire [pt[44-:13] - 1:0] gw_config_reg_re; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:111:1 + wire [pt[44-:13] - 1:0] gw_clear_reg_we; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:113:1 + wire [INTPEND_SIZE - 1:0] intpend_reg_extended; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:115:1 + wire [(pt[44-:13] * 4) - 1:0] intpend_w_prior_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:116:1 + wire [(pt[44-:13] * 8) - 1:0] intpend_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:117:1 + wire [3:0] maxint; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:118:1 + wire [3:0] selected_int_priority; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:119:1 + wire [(INT_GRPS * 32) - 1:0] intpend_rd_part_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:121:1 + wire config_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:122:1 + wire intpriord; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:123:1 + wire config_reg_we; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:124:1 + wire config_reg_re; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:125:1 + wire config_reg_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:126:1 + wire prithresh_reg_write; + wire prithresh_reg_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:127:1 + wire intpriority_reg_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:128:1 + wire intenable_reg_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:129:1 + wire gw_config_reg_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:130:1 + wire picm_wren_ff; + wire picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:131:1 + wire [31:0] picm_raddr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:132:1 + wire [31:0] picm_waddr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:133:1 + wire [31:0] picm_wr_data_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:134:1 + wire [3:0] mask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:135:1 + wire picm_mken_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:136:1 + wire [7:0] claimid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:137:1 + wire [3:0] pl_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:138:1 + wire [3:0] pl_in_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:140:1 + wire [pt[44-:13] - 1:0] extintsrc_req_sync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:141:1 + wire [pt[44-:13] - 1:0] extintsrc_req_gw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:142:4 + wire picm_bypass_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:145:4 + wire pic_raddr_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:146:4 + wire pic_waddr_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:147:4 + wire pic_data_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:148:4 + wire pic_pri_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:149:4 + wire pic_int_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:150:4 + wire gw_config_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:153:4 + wire pic_raddr_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:154:4 + wire pic_data_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:155:4 + wire pic_pri_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:156:4 + wire pic_int_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:157:4 + wire gw_config_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:161:4 + assign pic_raddr_c1_clken = (picm_mken | picm_rden) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:162:4 + assign pic_data_c1_clken = picm_wren | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:163:4 + assign pic_pri_c1_clken = ((waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff)) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:164:4 + assign pic_int_c1_clken = ((waddr_intenable_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff)) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:165:4 + assign gw_config_c1_clken = ((waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff)) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:168:4 + rvoclkhdr pic_addr_c1_cgc( + .en(pic_raddr_c1_clken), + .l1clk(pic_raddr_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:169:4 + rvoclkhdr pic_data_c1_cgc( + .en(pic_data_c1_clken), + .l1clk(pic_data_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:170:4 + rvoclkhdr pic_pri_c1_cgc( + .en(pic_pri_c1_clken), + .l1clk(pic_pri_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:171:4 + rvoclkhdr pic_int_c1_cgc( + .en(pic_int_c1_clken), + .l1clk(pic_int_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:172:4 + rvoclkhdr gw_config_c1_cgc( + .en(gw_config_c1_clken), + .l1clk(gw_config_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:176:1 + assign raddr_intenable_base_match = picm_raddr_ff[31:NUM_LEVELS + 2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS + 2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:177:1 + assign raddr_intpriority_base_match = picm_raddr_ff[31:NUM_LEVELS + 2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS + 2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:178:1 + assign raddr_config_gw_base_match = picm_raddr_ff[31:NUM_LEVELS + 2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS + 2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:179:1 + assign raddr_config_pic_match = picm_raddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:181:1 + assign addr_intpend_base_match = picm_raddr_ff[31:6] == INTPEND_BASE_ADDR[31:6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:183:1 + assign waddr_config_pic_match = picm_waddr_ff[31:0] == EXT_INTR_PIC_CONFIG[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:184:1 + assign addr_clear_gw_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == EXT_INTR_GW_CLEAR[31:NUM_LEVELS + 2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:185:1 + assign waddr_intpriority_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == INTPRIORITY_BASE_ADDR[31:NUM_LEVELS + 2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:186:1 + assign waddr_intenable_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == INTENABLE_BASE_ADDR[31:NUM_LEVELS + 2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:187:1 + assign waddr_config_gw_base_match = picm_waddr_ff[31:NUM_LEVELS + 2] == EXT_INTR_GW_CONFIG[31:NUM_LEVELS + 2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:189:4 + assign picm_bypass_ff = (picm_rden_ff & picm_wren_ff) & (picm_raddr_ff[31:0] == picm_waddr_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:192:1 + rvdff #(.WIDTH(32)) picm_radd_flop( + .rst_l(rst_l), + .din(picm_rdaddr), + .dout(picm_raddr_ff), + .clk(pic_raddr_c1_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:193:1 + rvdff #(.WIDTH(32)) picm_wadd_flop( + .rst_l(rst_l), + .din(picm_wraddr), + .dout(picm_waddr_ff), + .clk(pic_data_c1_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:194:1 + rvdff #(.WIDTH(1)) picm_wre_flop( + .rst_l(rst_l), + .din(picm_wren), + .dout(picm_wren_ff), + .clk(free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:195:1 + rvdff #(.WIDTH(1)) picm_rde_flop( + .rst_l(rst_l), + .din(picm_rden), + .dout(picm_rden_ff), + .clk(free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:196:1 + rvdff #(.WIDTH(1)) picm_mke_flop( + .rst_l(rst_l), + .din(picm_mken), + .dout(picm_mken_ff), + .clk(free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:197:1 + rvdff #(.WIDTH(32)) picm_dat_flop( + .rst_l(rst_l), + .din(picm_wr_data[31:0]), + .dout(picm_wr_data_ff[31:0]), + .clk(pic_data_c1_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:222:1 + genvar _gv_i_4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:223:1 + genvar _gv_p_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:224:1 + generate + for (_gv_p_1 = 0; _gv_p_1 <= INT_ENABLE_GRPS; _gv_p_1 = _gv_p_1 + 1) begin : IO_CLK_GRP + localparam p = _gv_p_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:225:1 + wire grp_clk; + wire grp_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:227:5 + assign grp_clken = |intenable_clk_enable[(p == INT_ENABLE_GRPS ? pt[44-:13] - 1 : (p * 4) + 3):p * 4] | io_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:232:5 + assign gw_clk[p] = 1'b0; + genvar _gv_i_5; + for (_gv_i_5 = (p == 0 ? 1 : 0); _gv_i_5 < (p == INT_ENABLE_GRPS ? pt[44-:13] - (p * 4) : 4); _gv_i_5 = _gv_i_5 + 1) begin : GW + localparam i = _gv_i_5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:236:9 + el2_configurable_gw gw_inst( + .rst_l(rst_l), + .gw_clk(grp_clk), + .rawclk(clk), + .clken(grp_clken), + .extintsrc_req(extintsrc_req[i + (p * 4)]), + .meigwctrl_polarity(gw_config_reg[(i + (p * 4)) * 2]), + .meigwctrl_type(gw_config_reg[((i + (p * 4)) * 2) + 1]), + .meigwclr(gw_clear_reg_we[i + (p * 4)]), + .extintsrc_req_config(extintsrc_req_gw[i + (p * 4)]) + ); + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:257:1 + generate + for (_gv_i_4 = 0; _gv_i_4 < pt[44-:13]; _gv_i_4 = _gv_i_4 + 1) begin : SETREG + localparam i = _gv_i_4; + if (i > 0) begin : NON_ZERO_INT + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:260:6 + assign intpriority_reg_we[i] = (waddr_intpriority_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:261:6 + assign intpriority_reg_re[i] = (raddr_intpriority_base_match & (picm_raddr_ff[NUM_LEVELS + 1:2] == i)) & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:263:6 + assign intenable_reg_we[i] = (waddr_intenable_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:264:6 + assign intenable_reg_re[i] = (raddr_intenable_base_match & (picm_raddr_ff[NUM_LEVELS + 1:2] == i)) & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:266:6 + assign gw_config_reg_we[i] = (waddr_config_gw_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:267:6 + assign gw_config_reg_re[i] = (raddr_config_gw_base_match & (picm_raddr_ff[NUM_LEVELS + 1:2] == i)) & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:269:6 + assign gw_clear_reg_we[i] = (addr_clear_gw_base_match & (picm_waddr_ff[NUM_LEVELS + 1:2] == i)) & picm_wren_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:271:6 + rvdffs #(.WIDTH(INTPRIORITY_BITS)) intpriority_ff( + .rst_l(rst_l), + .en(intpriority_reg_we[i]), + .din(picm_wr_data_ff[3:0]), + .dout(intpriority_reg[i * 4+:4]), + .clk(pic_pri_c1_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:272:6 + rvdffs #(.WIDTH(1)) intenable_ff( + .rst_l(rst_l), + .en(intenable_reg_we[i]), + .din(picm_wr_data_ff[0]), + .dout(intenable_reg[i]), + .clk(pic_int_c1_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:273:6 + rvdffs #(.WIDTH(2)) gw_config_ff( + .rst_l(rst_l), + .en(gw_config_reg_we[i]), + .din(picm_wr_data_ff[1:0]), + .dout(gw_config_reg[i * 2+:2]), + .clk(gw_config_c1_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:275:6 + assign intenable_clk_enable[i] = ((gw_config_reg[(i * 2) + 1] | intenable_reg_we[i]) | intenable_reg[i]) | gw_clear_reg_we[i]; + end + else begin : INT_ZERO + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:304:6 + assign intpriority_reg_we[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:305:6 + assign intpriority_reg_re[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:306:6 + assign intenable_reg_we[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:307:6 + assign intenable_reg_re[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:309:6 + assign gw_config_reg_we[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:310:6 + assign gw_config_reg_re[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:311:6 + assign gw_clear_reg_we[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:313:6 + assign gw_config_reg[i * 2+:2] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:315:6 + assign intpriority_reg[i * 4+:4] = {INTPRIORITY_BITS {1'b0}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:316:6 + assign intenable_reg[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:317:6 + assign extintsrc_req_gw[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:318:6 + assign extintsrc_req_sync[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:319:6 + assign intenable_clk_enable[i] = 1'b0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:323:5 + assign intpriority_reg_inv[i * 4+:4] = (intpriord ? ~intpriority_reg[i * 4+:4] : intpriority_reg[i * 4+:4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:325:5 + assign intpend_w_prior_en[i * 4+:4] = {INTPRIORITY_BITS {extintsrc_req_gw[i] & intenable_reg[i]}} & intpriority_reg_inv[i * 4+:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:326:5 + assign intpend_id[i * 8+:8] = i; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:330:9 + assign pl_in[3:0] = selected_int_priority[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:337:2 + genvar _gv_l_1; + genvar _gv_m_1; + genvar _gv_j_1; + genvar _gv_k_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:339:1 + generate + if (pt[135-:5] == 1) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:340:9 + wire [(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))))) + 1) * 4) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 4) - 1) : (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))) + 1) * 4) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 4) - 1)):(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 4 : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 4)] level_intpend_w_prior_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:341:9 + wire [(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))))) + 1) * 8) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 8) - 1) : (((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))) + 1) * 8) + ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 8) - 1)):(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) * 8 : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) * 8)] level_intpend_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:342:9 + wire [((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))))) + 1) * 4) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 4) - 1) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))) + 1) * 4) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 4) - 1)):((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 4 : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 4)] levelx_intpend_w_prior_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:343:9 + wire [((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))))) + 1) * 8) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 8) - 1) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))) + 1) * 8) + (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 8) - 1)):((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) * 8 : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) * 8)] levelx_intpend_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:345:9 + assign level_intpend_w_prior_en[4 * (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))))+:4 * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))] = {12'b000000000000, intpend_w_prior_en[4 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:4 * pt[44-:13]]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:346:9 + assign level_intpend_id[8 * (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - ((((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) - (((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2)) - 1) : ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) : (((((NUM_LEVELS / 2) >= 0 ? 0 : NUM_LEVELS / 2) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1) : (pt[44-:13] + 2) - ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 2 : ((pt[44-:13] + 2) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1))) + ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) - 1)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1)))))+:8 * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))] = {24'b000000000000000000000000, intpend_id[8 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:8 * pt[44-:13]]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:348:9 + wire [((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) * 4) - 1 : ((1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) * 4) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 4) - 1)):((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 4)] l2_intpend_w_prior_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:349:9 + wire [((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) * 8) - 1 : ((1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) * 8) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 8) - 1)):((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) * 8)] l2_intpend_id_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:351:9 + assign levelx_intpend_w_prior_en[4 * ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))))+:4 * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))] = {{4 {1'b0}}, l2_intpend_w_prior_en_ff[4 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)) : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)))+:4 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:352:9 + assign levelx_intpend_id[8 * ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - (((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) - ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - 1) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) : ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - ((NUM_LEVELS / 2) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) - 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)))))+:8 * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))] = {{8 {1'b1}}, l2_intpend_id_ff[8 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)) : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1) - (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2)))) - 1) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? pt[44-:13] / (2 ** (NUM_LEVELS / 2)) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))) - 1)))+:8 * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1 : 1 - (pt[44-:13] / (2 ** (NUM_LEVELS / 2))))]}; + for (_gv_l_1 = 0; _gv_l_1 < (NUM_LEVELS / 2); _gv_l_1 = _gv_l_1 + 1) begin : TOP_LEVEL + localparam l = _gv_l_1; + for (_gv_m_1 = 0; _gv_m_1 <= (pt[44-:13] / (2 ** (l + 1))); _gv_m_1 = _gv_m_1 + 1) begin : COMPARE + localparam m = _gv_m_1; + if (m == (pt[44-:13] / (2 ** (l + 1)))) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:357:13 + assign level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:358:13 + assign level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m + 1 : (pt[44-:13] + 2) - (m + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8] = 1'sb0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:360:8 + el2_cmp_and_mux #( + .ID_BITS(ID_BITS), + .INTPRIORITY_BITS(INTPRIORITY_BITS) + ) cmp_l1( + .a_id(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]), + .a_priority(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? 2 * m : (pt[44-:13] + 2) - (2 * m))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4]), + .b_id(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]), + .b_priority(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1)) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l : (NUM_LEVELS / 2) - l) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 2) - ((2 * m) + 1))) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4]), + .out_id(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]), + .out_priority(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? l + 1 : (NUM_LEVELS / 2) - (l + 1)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? m : (pt[44-:13] + 2) - m)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4]) + ); + end + end + for (_gv_i_4 = 0; _gv_i_4 <= (pt[44-:13] / (2 ** (NUM_LEVELS / 2))); _gv_i_4 = _gv_i_4 + 1) begin : MIDDLE_FLOPS + localparam i = _gv_i_4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:373:11 + rvdff #(.WIDTH(INTPRIORITY_BITS)) level2_intpend_prior_reg( + .rst_l(rst_l), + .din(level_intpend_w_prior_en[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 4+:4]), + .dout(l2_intpend_w_prior_en_ff[((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? i : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - i) * 4+:4]), + .clk(free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:374:11 + rvdff #(.WIDTH(ID_BITS)) level2_intpend_id_reg( + .rst_l(rst_l), + .din(level_intpend_id[(((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))) >= ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) ? (((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i) : ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? 0 : pt[44-:13] + 2) : ((pt[44-:13] + 2) >= 0 ? (NUM_LEVELS / 2) * (pt[44-:13] + 3) : (pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2))))) - (((((NUM_LEVELS / 2) >= 0 ? NUM_LEVELS / 2 : (NUM_LEVELS / 2) - (NUM_LEVELS / 2)) * ((pt[44-:13] + 2) >= 0 ? pt[44-:13] + 3 : 1 - (pt[44-:13] + 2))) + ((pt[44-:13] + 2) >= 0 ? i : (pt[44-:13] + 2) - i)) - ((NUM_LEVELS / 2) >= 0 ? ((pt[44-:13] + 2) >= 0 ? (((NUM_LEVELS / 2) + 1) * (pt[44-:13] + 3)) - 1 : (((NUM_LEVELS / 2) + 1) * (1 - (pt[44-:13] + 2))) + (pt[44-:13] + 1)) : ((pt[44-:13] + 2) >= 0 ? ((1 - (NUM_LEVELS / 2)) * (pt[44-:13] + 3)) + (((NUM_LEVELS / 2) * (pt[44-:13] + 3)) - 1) : ((1 - (NUM_LEVELS / 2)) * (1 - (pt[44-:13] + 2))) + (((pt[44-:13] + 2) + ((NUM_LEVELS / 2) * (1 - (pt[44-:13] + 2)))) - 1))))) * 8+:8]), + .dout(l2_intpend_id_ff[((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) >= 0 ? i : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) - i) * 8+:8]), + .clk(free_clk) + ); + end + for (_gv_j_1 = NUM_LEVELS / 2; _gv_j_1 < NUM_LEVELS; _gv_j_1 = _gv_j_1 + 1) begin : BOT_LEVELS + localparam j = _gv_j_1; + for (_gv_k_1 = 0; _gv_k_1 <= (pt[44-:13] / (2 ** (j + 1))); _gv_k_1 = _gv_k_1 + 1) begin : COMPARE + localparam k = _gv_k_1; + if (k == (pt[44-:13] / (2 ** (j + 1)))) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:380:13 + assign levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:381:13 + assign levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (k + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8] = 1'sb0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:383:13 + el2_cmp_and_mux #( + .ID_BITS(ID_BITS), + .INTPRIORITY_BITS(INTPRIORITY_BITS) + ) cmp_l1( + .a_id(levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8]), + .a_priority(levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 2 * k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - (2 * k))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4]), + .b_id(levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8]), + .b_priority(levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1)) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j : (NUM_LEVELS / 2) - (j - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (2 * k) + 1 : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - ((2 * k) + 1))) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4]), + .out_id(levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8]), + .out_priority(levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? j + 1 : (NUM_LEVELS / 2) - ((j + 1) - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? k : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) - k)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4]) + ); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:394:9 + assign claimid_in[7:0] = levelx_intpend_id[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 8+:8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:395:9 + assign selected_int_priority[3:0] = levelx_intpend_w_prior_en[((NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))) >= (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) ? ((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) : (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2) : ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))))) - ((((NUM_LEVELS >= (NUM_LEVELS / 2) ? NUM_LEVELS : (NUM_LEVELS / 2) - (NUM_LEVELS - NUM_LEVELS)) * (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2 : 1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? 0 : (pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)) - (NUM_LEVELS >= (NUM_LEVELS / 2) ? (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + (((NUM_LEVELS / 2) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : (((NUM_LEVELS - (NUM_LEVELS / 2)) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + ((NUM_LEVELS / 2) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1)) : (((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) >= 0 ? ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) + ((NUM_LEVELS * ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 2)) - 1) : ((((NUM_LEVELS / 2) - NUM_LEVELS) + 1) * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1))) + ((((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1) + (NUM_LEVELS * (1 - ((pt[44-:13] / (2 ** (NUM_LEVELS / 2))) + 1)))) - 1))))) * 4+:4]; + end + else begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:399:9 + wire [((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))))) + 1) * 4) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 4) - 1) : ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))) + 1) * 4) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 4) - 1)):((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 4 : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 4)] level_intpend_w_prior_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:400:9 + wire [((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))))) + 1) * 8) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 8) - 1) : ((((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))) + 1) * 8) + (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 8) - 1)):((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) * 8 : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) * 8)] level_intpend_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:402:9 + assign level_intpend_w_prior_en[4 * ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))))+:4 * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))] = {{8 {1'b0}}, intpend_w_prior_en[4 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:4 * pt[44-:13]]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:403:9 + assign level_intpend_id[8 * ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - (((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) - (((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1)) - 1) : ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) : ((((NUM_LEVELS >= 0 ? 0 : NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1) : (pt[44-:13] + 1) - ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 1 : ((pt[44-:13] + 1) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1))) + ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) - 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1)))))+:8 * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))] = {{16 {1'b1}}, intpend_id[8 * ((pt[44-:13] - 1) - (pt[44-:13] - 1))+:8 * pt[44-:13]]}; + for (_gv_l_1 = 0; _gv_l_1 < NUM_LEVELS; _gv_l_1 = _gv_l_1 + 1) begin : LEVEL + localparam l = _gv_l_1; + for (_gv_m_1 = 0; _gv_m_1 <= (pt[44-:13] / (2 ** (l + 1))); _gv_m_1 = _gv_m_1 + 1) begin : COMPARE + localparam m = _gv_m_1; + if (m == (pt[44-:13] / (2 ** (l + 1)))) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:410:13 + assign level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:411:13 + assign level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m + 1 : (pt[44-:13] + 1) - (m + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8] = 1'sb0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:413:8 + el2_cmp_and_mux #( + .ID_BITS(ID_BITS), + .INTPRIORITY_BITS(INTPRIORITY_BITS) + ) cmp_l1( + .a_id(level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8]), + .a_priority(level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 2 * m : (pt[44-:13] + 1) - (2 * m))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4]), + .b_id(level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8]), + .b_priority(level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1)) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l : NUM_LEVELS - l) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? (2 * m) + 1 : (pt[44-:13] + 1) - ((2 * m) + 1))) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4]), + .out_id(level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8]), + .out_priority(level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? l + 1 : NUM_LEVELS - (l + 1)) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? m : (pt[44-:13] + 1) - m)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4]) + ); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:424:9 + assign claimid_in[7:0] = level_intpend_id[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 8+:8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:425:9 + assign selected_int_priority[3:0] = level_intpend_w_prior_en[((NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))) >= (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) ? ((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1) : ((pt[44-:13] + 1) >= 0 ? NUM_LEVELS * (pt[44-:13] + 2) : (pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1))))) - ((((NUM_LEVELS >= 0 ? NUM_LEVELS : NUM_LEVELS - NUM_LEVELS) * ((pt[44-:13] + 1) >= 0 ? pt[44-:13] + 2 : 1 - (pt[44-:13] + 1))) + ((pt[44-:13] + 1) >= 0 ? 0 : pt[44-:13] + 1)) - (NUM_LEVELS >= 0 ? ((pt[44-:13] + 1) >= 0 ? ((NUM_LEVELS + 1) * (pt[44-:13] + 2)) - 1 : ((NUM_LEVELS + 1) * (1 - (pt[44-:13] + 1))) + (pt[44-:13] + 0)) : ((pt[44-:13] + 1) >= 0 ? ((1 - NUM_LEVELS) * (pt[44-:13] + 2)) + ((NUM_LEVELS * (pt[44-:13] + 2)) - 1) : ((1 - NUM_LEVELS) * (1 - (pt[44-:13] + 1))) + (((pt[44-:13] + 1) + (NUM_LEVELS * (1 - (pt[44-:13] + 1)))) - 1))))) * 4+:4]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:434:1 + assign config_reg_we = waddr_config_pic_match & picm_wren_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:435:1 + assign config_reg_re = raddr_config_pic_match & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:437:1 + assign config_reg_in = picm_wr_data_ff[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:438:1 + rvdffs #(.WIDTH(1)) config_reg_ff( + .rst_l(rst_l), + .clk(free_clk), + .en(config_reg_we), + .din(config_reg_in), + .dout(config_reg) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:440:1 + assign intpriord = config_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:451:1 + assign pl_in_q[3:0] = (intpriord ? ~pl_in : pl_in); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:452:1 + rvdff #(.WIDTH(ID_BITS)) claimid_ff( + .rst_l(rst_l), + .din(claimid_in[7:0]), + .dout(claimid[7:0]), + .clk(free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:453:1 + rvdff #(.WIDTH(INTPRIORITY_BITS)) pl_ff( + .rst_l(rst_l), + .din(pl_in_q[3:0]), + .dout(pl[3:0]), + .clk(free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:455:1 + wire [3:0] meipt_inv; + wire [3:0] meicurpl_inv; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:456:1 + assign meipt_inv[3:0] = (intpriord ? ~meipt[3:0] : meipt[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:457:1 + assign meicurpl_inv[3:0] = (intpriord ? ~meicurpl[3:0] : meicurpl[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:458:1 + assign mexintpend_in = (selected_int_priority[3:0] > meipt_inv[3:0]) & (selected_int_priority[3:0] > meicurpl_inv[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:460:1 + rvdff #(.WIDTH(1)) mexintpend_ff( + .rst_l(rst_l), + .clk(free_clk), + .din(mexintpend_in), + .dout(mexintpend) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:462:1 + assign maxint[3:0] = (intpriord ? 0 : 15); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:463:1 + assign mhwakeup_in = pl_in_q[3:0] == maxint; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:464:1 + rvdff #(.WIDTH(1)) wake_up_ff( + .rst_l(rst_l), + .clk(free_clk), + .din(mhwakeup_in), + .dout(mhwakeup) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:475:1 + assign intpend_reg_read = addr_intpend_base_match & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:476:1 + assign intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:477:1 + assign intenable_reg_read = raddr_intenable_base_match & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:478:1 + assign gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:480:1 + assign intpend_reg_extended[INTPEND_SIZE - 1:0] = {{INTPEND_SIZE - pt[44-:13] {1'b0}}, extintsrc_req_gw[pt[44-:13] - 1:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:482:4 + generate + for (_gv_i_4 = 0; _gv_i_4 < INT_GRPS; _gv_i_4 = _gv_i_4 + 1) begin : genblk4 + localparam i = _gv_i_4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:483:13 + assign intpend_rd_part_out[i * 32+:32] = {32 {intpend_reg_read & (picm_raddr_ff[5:2] == i)}} & intpend_reg_extended[(32 * i) + 31:32 * i]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:486:4 + always @(*) begin : INTPEND_RD + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:487:10 + intpend_rd_out = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:488:10 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:488:15 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:488:15 + for (i = 0; i < INT_GRPS; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:489:16 + intpend_rd_out = intpend_rd_out | intpend_rd_part_out[i * 32+:32]; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:493:4 + always @(*) begin : INTEN_RD + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:494:10 + intenable_rd_out = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:495:10 + intpriority_rd_out = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:496:10 + gw_config_rd_out = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:497:10 + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:497:15 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:497:15 + for (i = 0; i < pt[44-:13]; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:498:15 + if (intenable_reg_re[i]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:499:16 + intenable_rd_out = intenable_reg[i]; + if (intpriority_reg_re[i]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:502:16 + intpriority_rd_out = intpriority_reg[i * 4+:4]; + if (gw_config_reg_re[i]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:505:16 + gw_config_rd_out = gw_config_reg[i * 2+:2]; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:511:2 + assign picm_rd_data_in[31:0] = (((((((({32 {intpend_reg_read}} & intpend_rd_out) | ({32 {intpriority_reg_read}} & {{28 {1'b0}}, intpriority_rd_out})) | ({32 {intenable_reg_read}} & {31'b0000000000000000000000000000000, intenable_rd_out})) | ({32 {gw_config_reg_read}} & {30'b000000000000000000000000000000, gw_config_rd_out})) | ({32 {config_reg_re}} & {31'b0000000000000000000000000000000, config_reg})) | ({32 {picm_mken_ff & mask[3]}} & 32'b00000000000000000000000000000011)) | ({32 {picm_mken_ff & mask[2]}} & 32'b00000000000000000000000000000001)) | ({32 {picm_mken_ff & mask[1]}} & 32'b00000000000000000000000000001111)) | ({32 {picm_mken_ff & mask[0]}} & 32'b00000000000000000000000000000000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:522:1 + assign picm_rd_data[31:0] = (picm_bypass_ff ? picm_wr_data_ff[31:0] : picm_rd_data_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:524:1 + wire [14:0] address; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:526:1 + assign address[14:0] = picm_raddr_ff[14:0]; + initial _sv2v_0 = 0; +endmodule +module el2_cmp_and_mux ( + a_id, + a_priority, + b_id, + b_priority, + out_id, + out_priority +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:533:36 + parameter ID_BITS = 8; + parameter INTPRIORITY_BITS = 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:536:25 + input wire [ID_BITS - 1:0] a_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:537:25 + input wire [INTPRIORITY_BITS - 1:0] a_priority; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:539:25 + input wire [ID_BITS - 1:0] b_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:540:25 + input wire [INTPRIORITY_BITS - 1:0] b_priority; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:542:25 + output wire [ID_BITS - 1:0] out_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:543:25 + output wire [INTPRIORITY_BITS - 1:0] out_priority; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:547:1 + wire a_is_lt_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:549:1 + assign a_is_lt_b = a_priority[INTPRIORITY_BITS - 1:0] < b_priority[INTPRIORITY_BITS - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:551:1 + assign out_id[ID_BITS - 1:0] = (a_is_lt_b ? b_id[ID_BITS - 1:0] : a_id[ID_BITS - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:553:1 + assign out_priority[INTPRIORITY_BITS - 1:0] = (a_is_lt_b ? b_priority[INTPRIORITY_BITS - 1:0] : a_priority[INTPRIORITY_BITS - 1:0]); +endmodule +module el2_configurable_gw ( + gw_clk, + rawclk, + clken, + rst_l, + extintsrc_req, + meigwctrl_polarity, + meigwctrl_type, + meigwclr, + extintsrc_req_config +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:559:30 + input wire gw_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:560:30 + input wire rawclk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:561:30 + input wire clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:562:30 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:563:30 + input wire extintsrc_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:564:30 + input wire meigwctrl_polarity; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:565:30 + input wire meigwctrl_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:566:30 + input wire meigwclr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:568:30 + output wire extintsrc_req_config; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:572:3 + wire gw_int_pending_in; + wire gw_int_pending; + wire extintsrc_req_sync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:574:3 + rvsyncss_fpga #(.WIDTH(1)) sync_inst( + .dout(extintsrc_req_sync), + .din(extintsrc_req), + .gw_clk(gw_clk), + .rawclk(rawclk), + .clken(clken), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:580:3 + assign gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & ~meigwclr); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:581:3 + rvdff_fpga #(.WIDTH(1)) int_pend_ff( + .rst_l(rst_l), + .clk(gw_clk), + .rawclk(rawclk), + .clken(clken), + .din(gw_int_pending_in), + .dout(gw_int_pending) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_pic_ctrl.sv:584:3 + assign extintsrc_req_config = (meigwctrl_type ? (extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending : extintsrc_req_sync ^ meigwctrl_polarity); +endmodule +module el2_dma_ctrl ( + clk, + free_clk, + rst_l, + dma_bus_clk_en, + clk_override, + scan_mode, + dbg_cmd_addr, + dbg_cmd_wrdata, + dbg_cmd_valid, + dbg_cmd_write, + dbg_cmd_type, + dbg_cmd_size, + dbg_dma_bubble, + dma_dbg_ready, + dma_dbg_cmd_done, + dma_dbg_cmd_fail, + dma_dbg_rddata, + dma_dccm_req, + dma_iccm_req, + dma_mem_tag, + dma_mem_addr, + dma_mem_sz, + dma_mem_write, + dma_mem_wdata, + dccm_dma_rvalid, + dccm_dma_ecc_error, + dccm_dma_rtag, + dccm_dma_rdata, + iccm_dma_rvalid, + iccm_dma_ecc_error, + iccm_dma_rtag, + iccm_dma_rdata, + dma_active, + dma_dccm_stall_any, + dma_iccm_stall_any, + dccm_ready, + iccm_ready, + dec_tlu_dma_qos_prty, + dma_pmu_dccm_read, + dma_pmu_dccm_write, + dma_pmu_any_read, + dma_pmu_any_write, + dma_axi_awvalid, + dma_axi_awready, + dma_axi_awid, + dma_axi_awaddr, + dma_axi_awsize, + dma_axi_wvalid, + dma_axi_wready, + dma_axi_wdata, + dma_axi_wstrb, + dma_axi_bvalid, + dma_axi_bready, + dma_axi_bresp, + dma_axi_bid, + dma_axi_arvalid, + dma_axi_arready, + dma_axi_arid, + dma_axi_araddr, + dma_axi_arsize, + dma_axi_rvalid, + dma_axi_rready, + dma_axi_rid, + dma_axi_rdata, + dma_axi_rresp, + dma_axi_rlast +); + reg _sv2v_0; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:27:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:28:4 + input wire free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:29:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:30:4 + input wire dma_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:31:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:32:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:35:4 + input wire [31:0] dbg_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:36:4 + input wire [31:0] dbg_cmd_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:37:4 + input wire dbg_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:38:4 + input wire dbg_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:39:4 + input wire [1:0] dbg_cmd_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:40:4 + input wire [1:0] dbg_cmd_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:42:4 + input wire dbg_dma_bubble; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:43:4 + output wire dma_dbg_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:45:4 + output wire dma_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:46:4 + output wire dma_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:47:4 + output wire [31:0] dma_dbg_rddata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:50:4 + output wire dma_dccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:51:4 + output wire dma_iccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:52:4 + output wire [2:0] dma_mem_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:53:4 + output wire [31:0] dma_mem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:54:4 + output wire [2:0] dma_mem_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:55:4 + output wire dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:56:4 + output wire [63:0] dma_mem_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:58:4 + input wire dccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:59:4 + input wire dccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:60:4 + input wire [2:0] dccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:61:4 + input wire [63:0] dccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:62:4 + input wire iccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:63:4 + input wire iccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:64:4 + input wire [2:0] iccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:65:4 + input wire [63:0] iccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:67:4 + output wire dma_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:68:4 + output wire dma_dccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:69:4 + output wire dma_iccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:70:4 + input wire dccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:71:4 + input wire iccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:72:4 + input wire [2:0] dec_tlu_dma_qos_prty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:75:4 + output wire dma_pmu_dccm_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:76:4 + output wire dma_pmu_dccm_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:77:4 + output wire dma_pmu_any_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:78:4 + output wire dma_pmu_any_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:81:4 + input wire dma_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:82:4 + output wire dma_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:83:4 + input wire [pt[1235-:8] - 1:0] dma_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:84:4 + input wire [31:0] dma_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:85:4 + input wire [2:0] dma_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:88:4 + input wire dma_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:89:4 + output wire dma_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:90:4 + input wire [63:0] dma_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:91:4 + input wire [7:0] dma_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:93:4 + output wire dma_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:94:4 + input wire dma_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:95:4 + output wire [1:0] dma_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:96:4 + output wire [pt[1235-:8] - 1:0] dma_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:99:4 + input wire dma_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:100:4 + output wire dma_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:101:4 + input wire [pt[1235-:8] - 1:0] dma_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:102:4 + input wire [31:0] dma_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:103:4 + input wire [2:0] dma_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:105:4 + output wire dma_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:106:4 + input wire dma_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:107:4 + output wire [pt[1235-:8] - 1:0] dma_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:108:4 + output wire [63:0] dma_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:109:4 + output wire [1:0] dma_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:110:4 + output wire dma_axi_rlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:114:4 + localparam DEPTH = pt[1257-:7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:115:4 + localparam DEPTH_PTR = $clog2(DEPTH); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:116:4 + localparam NACK_COUNT = 7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:118:4 + wire [DEPTH - 1:0] fifo_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:119:4 + wire [(DEPTH * 2) - 1:0] fifo_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:120:4 + wire [DEPTH - 1:0] fifo_error_bus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:121:4 + wire [DEPTH - 1:0] fifo_rpend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:122:4 + wire [DEPTH - 1:0] fifo_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:123:4 + wire [DEPTH - 1:0] fifo_done_bus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:124:4 + wire [(DEPTH * 32) - 1:0] fifo_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:125:4 + wire [(DEPTH * 3) - 1:0] fifo_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:126:4 + wire [(DEPTH * 8) - 1:0] fifo_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:127:4 + wire [DEPTH - 1:0] fifo_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:128:4 + wire [DEPTH - 1:0] fifo_posted_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:129:4 + wire [DEPTH - 1:0] fifo_dbg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:130:4 + wire [(DEPTH * 64) - 1:0] fifo_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:131:4 + wire [(DEPTH * pt[1235-:8]) - 1:0] fifo_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:132:4 + wire [(DEPTH * pt[1250-:9]) - 1:0] fifo_mid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:133:4 + wire [(DEPTH * pt[1241-:6]) - 1:0] fifo_prty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:135:4 + wire [DEPTH - 1:0] fifo_cmd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:136:4 + wire [DEPTH - 1:0] fifo_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:137:4 + wire [DEPTH - 1:0] fifo_pend_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:138:4 + wire [DEPTH - 1:0] fifo_done_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:139:4 + wire [DEPTH - 1:0] fifo_done_bus_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:140:4 + wire [DEPTH - 1:0] fifo_error_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:141:4 + wire [DEPTH - 1:0] fifo_error_bus_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:142:4 + wire [DEPTH - 1:0] fifo_reset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:143:4 + wire [(DEPTH * 2) - 1:0] fifo_error_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:144:4 + wire [(DEPTH * 64) - 1:0] fifo_data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:146:4 + wire fifo_write_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:147:4 + wire fifo_posted_write_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:148:4 + wire fifo_dbg_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:149:4 + wire [31:0] fifo_addr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:150:4 + wire [2:0] fifo_sz_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:151:4 + wire [7:0] fifo_byteen_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:153:4 + wire [DEPTH_PTR - 1:0] RspPtr; + wire [DEPTH_PTR - 1:0] NxtRspPtr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:154:4 + wire [DEPTH_PTR - 1:0] WrPtr; + wire [DEPTH_PTR - 1:0] NxtWrPtr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:155:4 + wire [DEPTH_PTR - 1:0] RdPtr; + wire [DEPTH_PTR - 1:0] NxtRdPtr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:156:4 + wire WrPtrEn; + wire RdPtrEn; + wire RspPtrEn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:158:4 + wire [1:0] dma_dbg_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:159:4 + wire [1:0] dma_dbg_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:160:4 + wire [31:0] dma_dbg_mem_rddata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:161:4 + wire [31:0] dma_dbg_mem_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:162:4 + wire dma_dbg_cmd_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:163:4 + wire dma_dbg_cmd_done_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:165:4 + wire fifo_full; + wire fifo_full_spec; + wire fifo_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:166:4 + wire dma_address_error; + wire dma_alignment_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:167:4 + reg [3:0] num_fifo_vld; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:168:4 + wire dma_mem_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:169:4 + wire [31:0] dma_mem_addr_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:170:4 + wire [2:0] dma_mem_sz_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:171:4 + wire [7:0] dma_mem_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:172:4 + wire dma_mem_addr_in_dccm; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:173:4 + wire dma_mem_addr_in_iccm; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:174:4 + wire dma_mem_addr_in_pic; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:175:4 + wire dma_mem_addr_in_pic_region_nc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:176:4 + wire dma_mem_addr_in_dccm_region_nc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:177:4 + wire dma_mem_addr_in_iccm_region_nc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:179:4 + wire [2:0] dma_nack_count; + wire [2:0] dma_nack_count_d; + wire [2:0] dma_nack_count_csr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:181:4 + wire dma_buffer_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:182:4 + wire dma_free_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:183:4 + wire dma_buffer_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:184:4 + wire dma_free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:185:4 + wire dma_bus_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:187:4 + wire bus_rsp_valid; + wire bus_rsp_sent; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:188:4 + wire bus_cmd_valid; + wire bus_cmd_sent; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:189:4 + wire bus_cmd_write; + wire bus_cmd_posted_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:190:4 + wire [7:0] bus_cmd_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:191:4 + wire [2:0] bus_cmd_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:192:4 + wire [31:0] bus_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:193:4 + wire [63:0] bus_cmd_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:194:4 + wire [pt[1235-:8] - 1:0] bus_cmd_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:195:4 + wire [pt[1250-:9] - 1:0] bus_cmd_mid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:196:4 + wire [pt[1241-:6] - 1:0] bus_cmd_prty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:197:4 + wire bus_posted_write_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:199:4 + wire fifo_full_spec_bus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:200:4 + wire dbg_dma_bubble_bus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:201:4 + wire stall_dma_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:202:4 + wire dma_fifo_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:204:4 + wire wrbuf_en; + wire wrbuf_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:205:4 + wire wrbuf_cmd_sent; + wire wrbuf_rst; + wire wrbuf_data_rst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:206:4 + wire wrbuf_vld; + wire wrbuf_data_vld; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:207:4 + wire [pt[1235-:8] - 1:0] wrbuf_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:208:4 + wire [2:0] wrbuf_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:209:4 + wire [31:0] wrbuf_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:210:4 + wire [63:0] wrbuf_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:211:4 + wire [7:0] wrbuf_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:213:4 + wire rdbuf_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:214:4 + wire rdbuf_cmd_sent; + wire rdbuf_rst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:215:4 + wire rdbuf_vld; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:216:4 + wire [pt[1235-:8] - 1:0] rdbuf_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:217:4 + wire [2:0] rdbuf_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:218:4 + wire [31:0] rdbuf_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:220:4 + wire axi_mstr_prty_in; + wire axi_mstr_prty_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:221:4 + wire axi_mstr_priority; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:222:4 + wire axi_mstr_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:224:4 + wire axi_rsp_valid; + wire axi_rsp_sent; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:225:4 + wire axi_rsp_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:226:4 + wire [pt[1235-:8] - 1:0] axi_rsp_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:227:4 + wire [1:0] axi_rsp_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:228:4 + wire [63:0] axi_rsp_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:233:4 + assign fifo_addr_in[31:0] = (dbg_cmd_valid ? dbg_cmd_addr[31:0] : bus_cmd_addr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:234:4 + assign fifo_byteen_in[7:0] = {8 {~dbg_cmd_valid}} & bus_cmd_byteen[7:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:235:4 + assign fifo_sz_in[2:0] = (dbg_cmd_valid ? {1'b0, dbg_cmd_size[1:0]} : bus_cmd_sz[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:236:4 + assign fifo_write_in = (dbg_cmd_valid ? dbg_cmd_write : bus_cmd_write); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:237:4 + assign fifo_posted_write_in = ~dbg_cmd_valid & bus_cmd_posted_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:238:4 + assign fifo_dbg_in = dbg_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:240:4 + genvar _gv_i_6; + function automatic [DEPTH_PTR - 1:0] sv2v_cast_67AA8; + input reg [DEPTH_PTR - 1:0] inp; + sv2v_cast_67AA8 = inp; + endfunction + generate + for (_gv_i_6 = 0; _gv_i_6 < DEPTH; _gv_i_6 = _gv_i_6 + 1) begin : GenFifo + localparam i = _gv_i_6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:241:7 + assign fifo_cmd_en[i] = ((bus_cmd_sent & dma_bus_clk_en) | (dbg_cmd_valid & dbg_cmd_type[1])) & (i == WrPtr[DEPTH_PTR - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:242:7 + assign fifo_data_en[i] = ((((((bus_cmd_sent & fifo_write_in) & dma_bus_clk_en) | ((dbg_cmd_valid & dbg_cmd_type[1]) & dbg_cmd_write)) & (i == WrPtr[DEPTH_PTR - 1:0])) | ((dma_address_error | dma_alignment_error) & (i == RdPtr[DEPTH_PTR - 1:0]))) | (dccm_dma_rvalid & (i == sv2v_cast_67AA8(dccm_dma_rtag[2:0])))) | (iccm_dma_rvalid & (i == sv2v_cast_67AA8(iccm_dma_rtag[2:0]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:246:7 + assign fifo_pend_en[i] = ((dma_dccm_req | dma_iccm_req) & ~dma_mem_write) & (i == RdPtr[DEPTH_PTR - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:247:7 + assign fifo_error_en[i] = ((((dma_address_error | dma_alignment_error) | dma_dbg_cmd_error) & (i == RdPtr[DEPTH_PTR - 1:0])) | ((dccm_dma_rvalid & dccm_dma_ecc_error) & (i == sv2v_cast_67AA8(dccm_dma_rtag[2:0])))) | ((iccm_dma_rvalid & iccm_dma_ecc_error) & (i == sv2v_cast_67AA8(iccm_dma_rtag[2:0]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:250:7 + assign fifo_error_bus_en[i] = ((|fifo_error_in[(i * 2) + 1-:2] & fifo_error_en[i]) | (|fifo_error[i * 2+:2])) & dma_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:251:7 + assign fifo_done_en[i] = ((((|fifo_error[i * 2+:2] | fifo_error_en[i]) | ((dma_dccm_req | dma_iccm_req) & dma_mem_write)) & (i == RdPtr[DEPTH_PTR - 1:0])) | (dccm_dma_rvalid & (i == sv2v_cast_67AA8(dccm_dma_rtag[2:0])))) | (iccm_dma_rvalid & (i == sv2v_cast_67AA8(iccm_dma_rtag[2:0]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:254:7 + assign fifo_done_bus_en[i] = (fifo_done_en[i] | fifo_done[i]) & dma_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:255:7 + assign fifo_reset[i] = (((bus_rsp_sent | bus_posted_write_done) & dma_bus_clk_en) | dma_dbg_cmd_done) & (i == RspPtr[DEPTH_PTR - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:256:7 + assign fifo_error_in[i * 2+:2] = (dccm_dma_rvalid & (i == sv2v_cast_67AA8(dccm_dma_rtag[2:0])) ? {1'b0, dccm_dma_ecc_error} : (iccm_dma_rvalid & (i == sv2v_cast_67AA8(iccm_dma_rtag[2:0])) ? {1'b0, iccm_dma_ecc_error} : {(dma_address_error | dma_alignment_error) | dma_dbg_cmd_error, dma_alignment_error})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:258:7 + assign fifo_data_in[i * 64+:64] = (fifo_error_en[i] & |fifo_error_in[i * 2+:2] ? {32'b00000000000000000000000000000000, fifo_addr[i * 32+:32]} : (dccm_dma_rvalid & (i == sv2v_cast_67AA8(dccm_dma_rtag[2:0])) ? dccm_dma_rdata[63:0] : (iccm_dma_rvalid & (i == sv2v_cast_67AA8(iccm_dma_rtag[2:0])) ? iccm_dma_rdata[63:0] : (dbg_cmd_valid ? {2 {dma_dbg_mem_wrdata[31:0]}} : bus_cmd_wdata[63:0])))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:262:7 + rvdffsc #(.WIDTH(1)) fifo_valid_dff( + .din(1'b1), + .dout(fifo_valid[i]), + .en(fifo_cmd_en[i]), + .clear(fifo_reset[i]), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:263:7 + rvdffsc #(.WIDTH(2)) fifo_error_dff( + .din(fifo_error_in[i * 2+:2]), + .dout(fifo_error[i * 2+:2]), + .en(fifo_error_en[i]), + .clear(fifo_reset[i]), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:264:7 + rvdffsc #(.WIDTH(1)) fifo_error_bus_dff( + .din(1'b1), + .dout(fifo_error_bus[i]), + .en(fifo_error_bus_en[i]), + .clear(fifo_reset[i]), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:265:7 + rvdffsc #(.WIDTH(1)) fifo_rpend_dff( + .din(1'b1), + .dout(fifo_rpend[i]), + .en(fifo_pend_en[i]), + .clear(fifo_reset[i]), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:266:7 + rvdffsc #(.WIDTH(1)) fifo_done_dff( + .din(1'b1), + .dout(fifo_done[i]), + .en(fifo_done_en[i]), + .clear(fifo_reset[i]), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:267:7 + rvdffsc #(.WIDTH(1)) fifo_done_bus_dff( + .din(1'b1), + .dout(fifo_done_bus[i]), + .en(fifo_done_bus_en[i]), + .clear(fifo_reset[i]), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:268:7 + rvdffe #(.WIDTH(32)) fifo_addr_dff( + .din(fifo_addr_in[31:0]), + .dout(fifo_addr[i * 32+:32]), + .en(fifo_cmd_en[i]), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:269:7 + rvdffs #(.WIDTH(3)) fifo_sz_dff( + .din(fifo_sz_in[2:0]), + .dout(fifo_sz[i * 3+:3]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:270:7 + rvdffs #(.WIDTH(8)) fifo_byteen_dff( + .din(fifo_byteen_in[7:0]), + .dout(fifo_byteen[i * 8+:8]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:271:7 + rvdffs #(.WIDTH(1)) fifo_write_dff( + .din(fifo_write_in), + .dout(fifo_write[i]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:272:7 + rvdffs #(.WIDTH(1)) fifo_posted_write_dff( + .din(fifo_posted_write_in), + .dout(fifo_posted_write[i]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:273:7 + rvdffs #(.WIDTH(1)) fifo_dbg_dff( + .din(fifo_dbg_in), + .dout(fifo_dbg[i]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:274:7 + rvdffe #(.WIDTH(64)) fifo_data_dff( + .din(fifo_data_in[i * 64+:64]), + .dout(fifo_data[i * 64+:64]), + .en(fifo_data_en[i]), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:275:7 + rvdffs #(.WIDTH(pt[1235-:8])) fifo_tag_dff( + .din(bus_cmd_tag[pt[1235-:8] - 1:0]), + .dout(fifo_tag[(i * pt[1235-:8]) + (pt[1235-:8] - 1)-:pt[1235-:8]]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:276:7 + rvdffs #(.WIDTH(pt[1250-:9])) fifo_mid_dff( + .din(bus_cmd_mid[pt[1250-:9] - 1:0]), + .dout(fifo_mid[(i * pt[1250-:9]) + (pt[1250-:9] - 1)-:pt[1250-:9]]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:277:7 + rvdffs #(.WIDTH(pt[1241-:6])) fifo_prty_dff( + .din(bus_cmd_prty[pt[1241-:6] - 1:0]), + .dout(fifo_prty[(i * pt[1241-:6]) + (pt[1241-:6] - 1)-:pt[1241-:6]]), + .en(fifo_cmd_en[i]), + .clk(dma_buffer_c1_clk), + .rst_l(rst_l) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:281:4 + assign NxtWrPtr[DEPTH_PTR - 1:0] = (WrPtr[DEPTH_PTR - 1:0] == (DEPTH - 1) ? {DEPTH_PTR * 1 {1'sb0}} : WrPtr[DEPTH_PTR - 1:0] + 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:282:4 + assign NxtRdPtr[DEPTH_PTR - 1:0] = (RdPtr[DEPTH_PTR - 1:0] == (DEPTH - 1) ? {DEPTH_PTR * 1 {1'sb0}} : RdPtr[DEPTH_PTR - 1:0] + 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:283:4 + assign NxtRspPtr[DEPTH_PTR - 1:0] = (RspPtr[DEPTH_PTR - 1:0] == (DEPTH - 1) ? {DEPTH_PTR * 1 {1'sb0}} : RspPtr[DEPTH_PTR - 1:0] + 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:285:4 + assign WrPtrEn = |fifo_cmd_en[DEPTH - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:286:4 + assign RdPtrEn = (dma_dccm_req | dma_iccm_req) | ((dma_address_error | dma_alignment_error) | dma_dbg_cmd_error); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:287:4 + assign RspPtrEn = dma_dbg_cmd_done | ((bus_rsp_sent | bus_posted_write_done) & dma_bus_clk_en); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:289:4 + rvdffs #(.WIDTH(DEPTH_PTR)) WrPtr_dff( + .din(NxtWrPtr[DEPTH_PTR - 1:0]), + .dout(WrPtr[DEPTH_PTR - 1:0]), + .en(WrPtrEn), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:290:4 + rvdffs #(.WIDTH(DEPTH_PTR)) RdPtr_dff( + .din(NxtRdPtr[DEPTH_PTR - 1:0]), + .dout(RdPtr[DEPTH_PTR - 1:0]), + .en(RdPtrEn), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:291:4 + rvdffs #(.WIDTH(DEPTH_PTR)) RspPtr_dff( + .din(NxtRspPtr[DEPTH_PTR - 1:0]), + .dout(RspPtr[DEPTH_PTR - 1:0]), + .en(RspPtrEn), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:294:4 + assign fifo_full = fifo_full_spec_bus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:296:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:297:7 + num_fifo_vld[3:0] = {3'b000, bus_cmd_sent} - {3'b000, bus_rsp_sent}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:298:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:298:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:298:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:299:10 + num_fifo_vld[3:0] = num_fifo_vld[3:0] + {3'b000, fifo_valid[i]}; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:302:4 + assign fifo_full_spec = num_fifo_vld[3:0] >= DEPTH; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:304:4 + assign dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:307:4 + assign dma_address_error = ((fifo_valid[RdPtr] & ~fifo_done[RdPtr]) & ~fifo_dbg[RdPtr]) & ~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:308:4 + assign dma_alignment_error = (((fifo_valid[RdPtr] & ~fifo_done[RdPtr]) & ~fifo_dbg[RdPtr]) & ~dma_address_error) & ((((((((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0]) | ((dma_mem_sz_int[2:0] == 3'h2) & |dma_mem_addr_int[1:0])) | ((dma_mem_sz_int[2:0] == 3'h3) & |dma_mem_addr_int[2:0])) | (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11)))) | ((dma_mem_addr_in_dccm & dma_mem_write) & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11)))) | ((dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2)) & (dma_mem_byteen[dma_mem_addr_int[2:0]+:4] != 4'hf))) | ((dma_mem_write & (dma_mem_sz_int[2:0] == 3'h3)) & ~(((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0)) | (dma_mem_byteen[7:0] == 8'hff)))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:319:4 + assign dma_dbg_ready = fifo_empty & dbg_dma_bubble; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:320:4 + assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr]) & fifo_done[RspPtr]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:321:4 + assign dma_dbg_cmd_fail = |fifo_error[RspPtr * 2+:2] & dma_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:323:4 + assign dma_dbg_sz[1:0] = fifo_sz[(RspPtr * 3) + 1-:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:324:4 + assign dma_dbg_addr[1:0] = fifo_addr[(RspPtr * 32) + 1-:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:325:4 + assign dma_dbg_mem_rddata[31:0] = (fifo_addr[(RspPtr * 32) + 2] ? fifo_data[(RspPtr * 64) + 63-:32] : fifo_data[(RspPtr * 64) + 31-:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:326:4 + assign dma_dbg_rddata[31:0] = (({32 {dma_dbg_sz[1:0] == 2'h0}} & ((dma_dbg_mem_rddata[31:0] >> (8 * dma_dbg_addr[1:0])) & 32'h000000ff)) | ({32 {dma_dbg_sz[1:0] == 2'h1}} & ((dma_dbg_mem_rddata[31:0] >> (16 * dma_dbg_addr[1])) & 32'h0000ffff))) | ({32 {dma_dbg_sz[1:0] == 2'h2}} & dma_dbg_mem_rddata[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:330:4 + assign dma_dbg_cmd_error = ((fifo_valid[RdPtr] & ~fifo_done[RdPtr]) & fifo_dbg[RdPtr]) & (~((dma_mem_addr_in_dccm | dma_mem_addr_in_iccm) | dma_mem_addr_in_pic) | ((dma_mem_addr_in_iccm | dma_mem_addr_in_pic) & (dma_mem_sz_int[1:0] != 2'b10))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:334:4 + assign dma_dbg_mem_wrdata[31:0] = (({32 {dbg_cmd_size[1:0] == 2'h0}} & {4 {dbg_cmd_wrdata[7:0]}}) | ({32 {dbg_cmd_size[1:0] == 2'h1}} & {2 {dbg_cmd_wrdata[15:0]}})) | ({32 {dbg_cmd_size[1:0] == 2'h2}} & dbg_cmd_wrdata[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:339:4 + assign dma_dccm_stall_any = (dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic)) & (dma_nack_count >= dma_nack_count_csr); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:340:4 + assign dma_iccm_stall_any = (dma_mem_req & dma_mem_addr_in_iccm) & (dma_nack_count >= dma_nack_count_csr); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:343:4 + assign fifo_empty = ~(|fifo_valid[DEPTH - 1:0] | bus_cmd_sent); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:346:4 + assign dma_nack_count_csr[2:0] = dec_tlu_dma_qos_prty[2:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:347:4 + assign dma_nack_count_d[2:0] = (dma_nack_count[2:0] >= dma_nack_count_csr[2:0] ? {3 {~(dma_dccm_req | dma_iccm_req)}} & dma_nack_count[2:0] : (dma_mem_req & ~(dma_dccm_req | dma_iccm_req) ? dma_nack_count[2:0] + 1'b1 : 3'b000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:350:4 + rvdffs #(.WIDTH(3)) nack_count_dff( + .din(dma_nack_count_d[2:0]), + .dout(dma_nack_count[2:0]), + .en(dma_mem_req), + .clk(dma_free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:353:4 + assign dma_mem_req = ((fifo_valid[RdPtr] & ~fifo_rpend[RdPtr]) & ~fifo_done[RdPtr]) & ~((dma_address_error | dma_alignment_error) | dma_dbg_cmd_error); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:354:4 + assign dma_dccm_req = (dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic)) & dccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:355:4 + assign dma_iccm_req = (dma_mem_req & dma_mem_addr_in_iccm) & iccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:356:4 + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + assign dma_mem_tag[2:0] = sv2v_cast_3(RdPtr); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:357:4 + assign dma_mem_addr_int[31:0] = fifo_addr[RdPtr * 32+:32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:358:4 + assign dma_mem_sz_int[2:0] = fifo_sz[RdPtr * 3+:3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:359:4 + assign dma_mem_addr[31:0] = ((dma_mem_write & ~fifo_dbg[RdPtr]) & (dma_mem_byteen[7:0] == 8'hf0) ? {dma_mem_addr_int[31:3], 1'b1, dma_mem_addr_int[1:0]} : dma_mem_addr_int[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:360:4 + assign dma_mem_sz[2:0] = ((dma_mem_write & ~fifo_dbg[RdPtr]) & ((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0)) ? 3'h2 : dma_mem_sz_int[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:361:4 + assign dma_mem_byteen[7:0] = fifo_byteen[RdPtr * 8+:8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:362:4 + assign dma_mem_write = fifo_write[RdPtr]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:363:4 + assign dma_mem_wdata[63:0] = fifo_data[RdPtr * 64+:64]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:366:4 + assign dma_pmu_dccm_read = dma_dccm_req & ~dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:367:4 + assign dma_pmu_dccm_write = dma_dccm_req & dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:368:4 + assign dma_pmu_any_read = (dma_dccm_req | dma_iccm_req) & ~dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:369:4 + assign dma_pmu_any_write = (dma_dccm_req | dma_iccm_req) & dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:372:4 + generate + if (pt[1365-:5]) begin : Gen_dccm_enable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:373:7 + rvrangecheck #( + .CCM_SADR(pt[1325-:36]), + .CCM_SIZE(pt[1289-:14]) + ) addr_dccm_rangecheck( + .addr(dma_mem_addr_int[31:0]), + .in_range(dma_mem_addr_in_dccm), + .in_region(dma_mem_addr_in_dccm_region_nc) + ); + end + else begin : Gen_dccm_disable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:380:7 + assign dma_mem_addr_in_dccm = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:381:7 + assign dma_mem_addr_in_dccm_region_nc = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:385:4 + generate + if (pt[927-:5]) begin : Gen_iccm_enable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:386:7 + rvrangecheck #( + .CCM_SADR(pt[887-:36]), + .CCM_SIZE(pt[851-:14]) + ) addr_iccm_rangecheck( + .addr(dma_mem_addr_int[31:0]), + .in_range(dma_mem_addr_in_iccm), + .in_region(dma_mem_addr_in_iccm_region_nc) + ); + end + else begin : Gen_iccm_disable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:393:7 + assign dma_mem_addr_in_iccm = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:394:7 + assign dma_mem_addr_in_iccm_region_nc = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:399:4 + rvrangecheck #( + .CCM_SADR(pt[130-:36]), + .CCM_SIZE(pt[69-:13]) + ) addr_pic_rangecheck( + .addr(dma_mem_addr_int[31:0]), + .in_range(dma_mem_addr_in_pic), + .in_region(dma_mem_addr_in_pic_region_nc) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:407:4 + rvdff_fpga #(.WIDTH(1)) fifo_full_bus_ff( + .din(fifo_full_spec), + .dout(fifo_full_spec_bus), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:408:4 + rvdff_fpga #(.WIDTH(1)) dbg_dma_bubble_ff( + .din(dbg_dma_bubble), + .dout(dbg_dma_bubble_bus), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:409:4 + rvdff #(.WIDTH(1)) dma_dbg_cmd_doneff( + .din(dma_dbg_cmd_done), + .dout(dma_dbg_cmd_done_q), + .clk(free_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:412:4 + assign dma_buffer_c1_clken = ((bus_cmd_valid & dma_bus_clk_en) | dbg_cmd_valid) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:413:4 + assign dma_free_clken = (((((bus_cmd_valid | bus_rsp_valid) | dbg_cmd_valid) | dma_dbg_cmd_done) | dma_dbg_cmd_done_q) | (|fifo_valid[DEPTH - 1:0])) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:415:4 + rvoclkhdr dma_buffer_c1cgc( + .en(dma_buffer_c1_clken), + .l1clk(dma_buffer_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:416:4 + rvoclkhdr dma_free_cgc( + .en(dma_free_clken), + .l1clk(dma_free_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:419:4 + assign dma_bus_clk = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:425:4 + assign wrbuf_en = dma_axi_awvalid & dma_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:426:4 + assign wrbuf_data_en = dma_axi_wvalid & dma_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:427:4 + assign wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:428:4 + assign wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:429:4 + assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:431:4 + rvdffsc_fpga #(.WIDTH(1)) wrbuf_vldff( + .din(1'b1), + .dout(wrbuf_vld), + .en(wrbuf_en), + .clear(wrbuf_rst), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:432:4 + rvdffsc_fpga #(.WIDTH(1)) wrbuf_data_vldff( + .din(1'b1), + .dout(wrbuf_data_vld), + .en(wrbuf_data_en), + .clear(wrbuf_data_rst), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:433:4 + rvdffs_fpga #(.WIDTH(pt[1235-:8])) wrbuf_tagff( + .din(dma_axi_awid[pt[1235-:8] - 1:0]), + .dout(wrbuf_tag[pt[1235-:8] - 1:0]), + .en(wrbuf_en), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:434:4 + rvdffs_fpga #(.WIDTH(3)) wrbuf_szff( + .din(dma_axi_awsize[2:0]), + .dout(wrbuf_sz[2:0]), + .en(wrbuf_en), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:435:4 + rvdffe #(.WIDTH(32)) wrbuf_addrff( + .din(dma_axi_awaddr[31:0]), + .dout(wrbuf_addr[31:0]), + .en(wrbuf_en & dma_bus_clk_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:436:4 + rvdffe #(.WIDTH(64)) wrbuf_dataff( + .din(dma_axi_wdata[63:0]), + .dout(wrbuf_data[63:0]), + .en(wrbuf_data_en & dma_bus_clk_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:437:4 + rvdffs_fpga #(.WIDTH(8)) wrbuf_byteenff( + .din(dma_axi_wstrb[7:0]), + .dout(wrbuf_byteen[7:0]), + .en(wrbuf_data_en), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:440:4 + assign rdbuf_en = dma_axi_arvalid & dma_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:441:4 + assign rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:442:4 + assign rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:444:4 + rvdffsc_fpga #(.WIDTH(1)) rdbuf_vldff( + .din(1'b1), + .dout(rdbuf_vld), + .en(rdbuf_en), + .clear(rdbuf_rst), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:445:4 + rvdffs_fpga #(.WIDTH(pt[1235-:8])) rdbuf_tagff( + .din(dma_axi_arid[pt[1235-:8] - 1:0]), + .dout(rdbuf_tag[pt[1235-:8] - 1:0]), + .en(rdbuf_en), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:446:4 + rvdffs_fpga #(.WIDTH(3)) rdbuf_szff( + .din(dma_axi_arsize[2:0]), + .dout(rdbuf_sz[2:0]), + .en(rdbuf_en), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:447:4 + rvdffe #(.WIDTH(32)) rdbuf_addrff( + .din(dma_axi_araddr[31:0]), + .dout(rdbuf_addr[31:0]), + .en(rdbuf_en & dma_bus_clk_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:449:4 + assign dma_axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:450:4 + assign dma_axi_wready = ~(wrbuf_data_vld & ~wrbuf_cmd_sent); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:451:4 + assign dma_axi_arready = ~(rdbuf_vld & ~rdbuf_cmd_sent); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:454:4 + assign bus_cmd_valid = (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:455:4 + assign bus_cmd_sent = bus_cmd_valid & dma_fifo_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:456:4 + assign bus_cmd_write = axi_mstr_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:457:4 + assign bus_cmd_posted_write = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:458:4 + assign bus_cmd_addr[31:0] = (axi_mstr_sel ? wrbuf_addr[31:0] : rdbuf_addr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:459:4 + assign bus_cmd_sz[2:0] = (axi_mstr_sel ? wrbuf_sz[2:0] : rdbuf_sz[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:460:4 + assign bus_cmd_wdata[63:0] = wrbuf_data[63:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:461:4 + assign bus_cmd_byteen[7:0] = wrbuf_byteen[7:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:462:4 + assign bus_cmd_tag[pt[1235-:8] - 1:0] = (axi_mstr_sel ? wrbuf_tag[pt[1235-:8] - 1:0] : rdbuf_tag[pt[1235-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:463:4 + assign bus_cmd_mid[pt[1250-:9] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:464:4 + assign bus_cmd_prty[pt[1241-:6] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:467:4 + assign axi_mstr_sel = ((wrbuf_vld & wrbuf_data_vld) & rdbuf_vld ? axi_mstr_priority : wrbuf_vld & wrbuf_data_vld); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:468:4 + assign axi_mstr_prty_in = ~axi_mstr_priority; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:469:4 + assign axi_mstr_prty_en = bus_cmd_sent; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:470:4 + rvdffs_fpga #(.WIDTH(1)) mstr_prtyff( + .din(axi_mstr_prty_in), + .dout(axi_mstr_priority), + .en(axi_mstr_prty_en), + .clk(dma_bus_clk), + .clken(dma_bus_clk_en), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:472:4 + assign axi_rsp_valid = (fifo_valid[RspPtr] & ~fifo_dbg[RspPtr]) & fifo_done_bus[RspPtr]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:473:4 + assign axi_rsp_rdata[63:0] = fifo_data[RspPtr * 64+:64]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:474:4 + assign axi_rsp_write = fifo_write[RspPtr]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:475:4 + assign axi_rsp_error[1:0] = (fifo_error[RspPtr * 2] ? 2'b10 : (fifo_error[(RspPtr * 2) + 1] ? 2'b11 : 2'b00)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:476:4 + assign axi_rsp_tag[pt[1235-:8] - 1:0] = fifo_tag[RspPtr * pt[1235-:8]+:pt[1235-:8]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:479:4 + assign dma_axi_bvalid = axi_rsp_valid & axi_rsp_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:480:4 + assign dma_axi_bresp[1:0] = axi_rsp_error[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:481:4 + assign dma_axi_bid[pt[1235-:8] - 1:0] = axi_rsp_tag[pt[1235-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:483:4 + assign dma_axi_rvalid = axi_rsp_valid & ~axi_rsp_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:484:4 + assign dma_axi_rresp[1:0] = axi_rsp_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:485:4 + assign dma_axi_rdata[63:0] = axi_rsp_rdata[63:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:486:4 + assign dma_axi_rlast = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:487:4 + assign dma_axi_rid[pt[1235-:8] - 1:0] = axi_rsp_tag[pt[1235-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:489:4 + assign bus_posted_write_done = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:490:4 + assign bus_rsp_valid = dma_axi_bvalid | dma_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:491:4 + assign bus_rsp_sent = (dma_axi_bvalid & dma_axi_bready) | (dma_axi_rvalid & dma_axi_rready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_dma_ctrl.sv:493:4 + assign dma_active = (wrbuf_vld | rdbuf_vld) | (|fifo_valid[DEPTH - 1:0]); + initial _sv2v_0 = 0; +endmodule +module el2_ifu_aln_ctl ( + scan_mode, + rst_l, + clk, + active_clk, + ifu_async_error_start, + iccm_rd_ecc_double_err, + ic_access_fault_f, + ic_access_fault_type_f, + exu_flush_final, + dec_i0_decode_d, + ifu_fetch_data_f, + ifu_fetch_val, + ifu_fetch_pc, + ifu_i0_valid, + ifu_i0_icaf, + ifu_i0_icaf_type, + ifu_i0_icaf_second, + ifu_i0_dbecc, + ifu_i0_instr, + ifu_i0_pc, + ifu_i0_pc4, + ifu_fb_consume1, + ifu_fb_consume2, + ifu_bp_fghr_f, + ifu_bp_btb_target_f, + ifu_bp_poffset_f, + ifu_bp_fa_index_f, + ifu_bp_hist0_f, + ifu_bp_hist1_f, + ifu_bp_pc4_f, + ifu_bp_way_f, + ifu_bp_valid_f, + ifu_bp_ret_f, + i0_brp, + ifu_i0_bp_index, + ifu_i0_bp_fghr, + ifu_i0_bp_btag, + ifu_i0_fa_index, + ifu_pmu_instr_aligned, + ifu_i0_cinst +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:28:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:29:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:30:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:31:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:33:4 + input wire ifu_async_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:35:4 + input wire [1:0] iccm_rd_ecc_double_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:37:4 + input wire [1:0] ic_access_fault_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:38:4 + input wire [1:0] ic_access_fault_type_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:40:4 + input wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:42:4 + input wire dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:44:4 + input wire [31:0] ifu_fetch_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:46:4 + input wire [1:0] ifu_fetch_val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:47:4 + input wire [31:1] ifu_fetch_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:51:4 + output wire ifu_i0_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:52:4 + output wire ifu_i0_icaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:53:4 + output wire [1:0] ifu_i0_icaf_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:54:4 + output wire ifu_i0_icaf_second; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:56:4 + output wire ifu_i0_dbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:57:4 + output wire [31:0] ifu_i0_instr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:58:4 + output wire [31:1] ifu_i0_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:59:4 + output wire ifu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:61:4 + output wire ifu_fb_consume1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:62:4 + output wire ifu_fb_consume2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:65:4 + input wire [pt[2236-:8] - 1:0] ifu_bp_fghr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:66:4 + input wire [31:1] ifu_bp_btb_target_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:67:4 + input wire [11:0] ifu_bp_poffset_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:68:4 + input wire [(2 * $clog2(pt[2061-:14])) - 1:0] ifu_bp_fa_index_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:70:4 + input wire [1:0] ifu_bp_hist0_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:71:4 + input wire [1:0] ifu_bp_hist1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:72:4 + input wire [1:0] ifu_bp_pc4_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:73:4 + input wire [1:0] ifu_bp_way_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:74:4 + input wire [1:0] ifu_bp_valid_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:75:4 + input wire [1:0] ifu_bp_ret_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:78:4 + // removed localparam type el2_pkg_el2_br_pkt_t + output reg [50:0] i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:79:4 + output wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:80:4 + output wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:81:4 + output wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:83:4 + output reg [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:85:4 + output wire ifu_pmu_instr_aligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:87:4 + output wire [15:0] ifu_i0_cinst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:92:4 + wire ifvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:93:4 + wire shift_f1_f0; + wire shift_f2_f0; + wire shift_f2_f1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:94:4 + wire fetch_to_f0; + wire fetch_to_f1; + wire fetch_to_f2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:96:4 + wire [1:0] f2val_in; + wire [1:0] f2val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:97:4 + wire [1:0] f1val_in; + wire [1:0] f1val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:98:4 + wire [1:0] f0val_in; + wire [1:0] f0val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:99:4 + wire [1:0] sf1val; + wire [1:0] sf0val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:101:4 + wire [31:0] aligndata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:102:4 + wire first4B; + wire first2B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:104:4 + wire [31:0] uncompress0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:105:4 + wire i0_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:106:4 + wire shift_2B; + wire shift_4B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:107:4 + wire f1_shift_2B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:108:4 + wire f2_valid; + wire sf1_valid; + wire sf0_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:110:4 + wire [31:0] ifirst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:111:4 + wire [1:0] alignval; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:112:4 + wire [31:1] firstpc; + wire [31:1] secondpc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:114:4 + wire [11:0] f1poffset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:115:4 + wire [11:0] f0poffset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:116:4 + wire [pt[2236-:8] - 1:0] f1fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:117:4 + wire [pt[2236-:8] - 1:0] f0fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:118:4 + wire [1:0] f1hist1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:119:4 + wire [1:0] f0hist1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:120:4 + wire [1:0] f1hist0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:121:4 + wire [1:0] f0hist0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:123:4 + wire [(2 * $clog2(pt[2061-:14])) - 1:0] f0index; + wire [(2 * $clog2(pt[2061-:14])) - 1:0] f1index; + wire [(2 * $clog2(pt[2061-:14])) - 1:0] alignindex; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:125:4 + wire [1:0] f1ictype; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:126:4 + wire [1:0] f0ictype; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:128:4 + wire [1:0] f1pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:129:4 + wire [1:0] f0pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:131:4 + wire [1:0] f1ret; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:132:4 + wire [1:0] f0ret; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:133:4 + wire [1:0] f1way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:134:4 + wire [1:0] f0way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:136:4 + wire [1:0] f1brend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:137:4 + wire [1:0] f0brend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:139:4 + wire [1:0] alignbrend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:140:4 + wire [1:0] alignpc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:142:4 + wire [1:0] alignret; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:143:4 + wire [1:0] alignway; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:144:4 + wire [1:0] alignhist1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:145:4 + wire [1:0] alignhist0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:146:4 + wire [1:1] alignfromf1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:147:4 + reg i0_ends_f1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:148:4 + reg i0_br_start_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:150:4 + wire [31:1] f1prett; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:151:4 + wire [31:1] f0prett; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:152:4 + wire [1:0] f1dbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:153:4 + wire [1:0] f0dbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:154:4 + wire [1:0] f1icaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:155:4 + wire [1:0] f0icaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:157:4 + wire [1:0] aligndbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:158:4 + wire [1:0] alignicaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:159:4 + reg i0_brp_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:161:4 + wire [pt[2172-:9]:pt[2163-:6]] firstpc_hash; + wire [pt[2172-:9]:pt[2163-:6]] secondpc_hash; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:163:4 + wire first_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:165:4 + wire [1:0] wrptr; + wire [1:0] wrptr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:166:4 + wire [1:0] rdptr; + wire [1:0] rdptr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:167:4 + wire [2:0] qwen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:168:4 + wire [31:0] q2; + wire [31:0] q1; + wire [31:0] q0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:169:4 + wire q2off_in; + wire q2off; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:170:4 + wire q1off_in; + wire q1off; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:171:4 + wire q0off_in; + wire q0off; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:172:4 + wire f0_shift_2B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:174:4 + wire [31:0] q0eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:175:4 + wire [31:0] q0final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:176:4 + wire q0ptr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:177:4 + wire [1:0] q0sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:179:4 + wire [31:0] q1eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:180:4 + wire [15:0] q1final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:181:4 + wire q1ptr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:182:4 + wire [1:0] q1sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:184:4 + wire [2:0] qren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:186:4 + wire consume_fb1; + wire consume_fb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:187:4 + wire [1:0] icaf_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:189:4 + localparam BRDATA_SIZE = (pt[2130-:5] ? 16 + (($clog2(pt[2061-:14]) * 2) * pt[2120-:5]) : 4); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:190:4 + localparam BRDATA_WIDTH = (pt[2130-:5] ? 8 + ($clog2(pt[2061-:14]) * pt[2120-:5]) : 2); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:191:4 + wire [BRDATA_SIZE - 1:0] brdata_in; + wire [BRDATA_SIZE - 1:0] brdata2; + wire [BRDATA_SIZE - 1:0] brdata1; + wire [BRDATA_SIZE - 1:0] brdata0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:192:4 + wire [BRDATA_SIZE - 1:0] brdata1eff; + wire [BRDATA_SIZE - 1:0] brdata0eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:193:4 + wire [BRDATA_SIZE - 1:0] brdata1final; + wire [BRDATA_SIZE - 1:0] brdata0final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:195:4 + localparam MHI = 1 + (pt[2130-:5] * (43 + pt[2236-:8])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:196:4 + localparam MSIZE = 2 + (pt[2130-:5] * (43 + pt[2236-:8])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:198:4 + wire [MHI:0] misc_data_in; + wire [MHI:0] misc2; + wire [MHI:0] misc1; + wire [MHI:0] misc0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:199:4 + wire [MHI:0] misc1eff; + wire [MHI:0] misc0eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:201:4 + wire [pt[2139-:9] - 1:0] firstbrtag_hash; + wire [pt[2139-:9] - 1:0] secondbrtag_hash; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:203:4 + wire error_stall_in; + wire error_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:205:4 + assign error_stall_in = (error_stall | ifu_async_error_start) & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:207:4 + rvdff #(.WIDTH(7)) bundle1ff( + .rst_l(rst_l), + .clk(active_clk), + .din({wrptr_in[1:0], rdptr_in[1:0], q2off_in, q1off_in, q0off_in}), + .dout({wrptr[1:0], rdptr[1:0], q2off, q1off, q0off}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:213:4 + rvdffie #( + .WIDTH(7), + .OVERRIDE(1) + ) bundle2ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({error_stall_in, f2val_in[1:0], f1val_in[1:0], f0val_in[1:0]}), + .dout({error_stall, f2val[1:0], f1val[1:0], f0val[1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:218:1 + generate + if (pt[2130-:5] == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:219:4 + rvdffe #(.WIDTH(BRDATA_SIZE)) brdata2ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[2]), + .din(brdata_in[BRDATA_SIZE - 1:0]), + .dout(brdata2[BRDATA_SIZE - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:220:4 + rvdffe #(.WIDTH(BRDATA_SIZE)) brdata1ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[1]), + .din(brdata_in[BRDATA_SIZE - 1:0]), + .dout(brdata1[BRDATA_SIZE - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:221:4 + rvdffe #(.WIDTH(BRDATA_SIZE)) brdata0ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[0]), + .din(brdata_in[BRDATA_SIZE - 1:0]), + .dout(brdata0[BRDATA_SIZE - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:222:4 + rvdffe #(.WIDTH(MSIZE)) misc2ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[2]), + .din(misc_data_in[MHI:0]), + .dout(misc2[MHI:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:223:4 + rvdffe #(.WIDTH(MSIZE)) misc1ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[1]), + .din(misc_data_in[MHI:0]), + .dout(misc1[MHI:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:224:4 + rvdffe #(.WIDTH(MSIZE)) misc0ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[0]), + .din(misc_data_in[MHI:0]), + .dout(misc0[MHI:0]) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:228:4 + rvdffie #(.WIDTH((MSIZE * 3) + (BRDATA_SIZE * 3))) miscff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({(qwen[2] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE - 1:0]} : {misc2[MHI:0], brdata2[BRDATA_SIZE - 1:0]}), (qwen[1] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE - 1:0]} : {misc1[MHI:0], brdata1[BRDATA_SIZE - 1:0]}), (qwen[0] ? {misc_data_in[MHI:0], brdata_in[BRDATA_SIZE - 1:0]} : {misc0[MHI:0], brdata0[BRDATA_SIZE - 1:0]})}), + .dout({misc2[MHI:0], brdata2[BRDATA_SIZE - 1:0], misc1[MHI:0], brdata1[BRDATA_SIZE - 1:0], misc0[MHI:0], brdata0[BRDATA_SIZE - 1:0]}) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:238:3 + wire [31:1] q2pc; + wire [31:1] q1pc; + wire [31:1] q0pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:240:4 + rvdffe #(.WIDTH(31)) q2pcff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[2]), + .din(ifu_fetch_pc[31:1]), + .dout(q2pc[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:241:4 + rvdffe #(.WIDTH(31)) q1pcff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[1]), + .din(ifu_fetch_pc[31:1]), + .dout(q1pc[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:242:4 + rvdffe #(.WIDTH(31)) q0pcff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[0]), + .din(ifu_fetch_pc[31:1]), + .dout(q0pc[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:244:4 + rvdffe #(.WIDTH(32)) q2ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[2]), + .din(ifu_fetch_data_f[31:0]), + .dout(q2[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:245:4 + rvdffe #(.WIDTH(32)) q1ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[1]), + .din(ifu_fetch_data_f[31:0]), + .dout(q1[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:246:4 + rvdffe #(.WIDTH(32)) q0ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qwen[0]), + .din(ifu_fetch_data_f[31:0]), + .dout(q0[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:251:4 + assign qren[2:0] = {rdptr[1:0] == 2'b10, rdptr[1:0] == 2'b01, rdptr[1:0] == 2'b00}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:255:4 + assign qwen[2:0] = {(wrptr[1:0] == 2'b10) & ifvalid, (wrptr[1:0] == 2'b01) & ifvalid, (wrptr[1:0] == 2'b00) & ifvalid}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:260:4 + assign rdptr_in[1:0] = (((((({2 {(qren[0] & ifu_fb_consume1) & ~exu_flush_final}} & 2'b01) | ({2 {(qren[1] & ifu_fb_consume1) & ~exu_flush_final}} & 2'b10)) | ({2 {(qren[2] & ifu_fb_consume1) & ~exu_flush_final}} & 2'b00)) | ({2 {(qren[0] & ifu_fb_consume2) & ~exu_flush_final}} & 2'b10)) | ({2 {(qren[1] & ifu_fb_consume2) & ~exu_flush_final}} & 2'b00)) | ({2 {(qren[2] & ifu_fb_consume2) & ~exu_flush_final}} & 2'b01)) | ({2 {(~ifu_fb_consume1 & ~ifu_fb_consume2) & ~exu_flush_final}} & rdptr[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:268:4 + assign wrptr_in[1:0] = ((({2 {qwen[0] & ~exu_flush_final}} & 2'b01) | ({2 {qwen[1] & ~exu_flush_final}} & 2'b10)) | ({2 {qwen[2] & ~exu_flush_final}} & 2'b00)) | ({2 {~ifvalid & ~exu_flush_final}} & wrptr[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:275:4 + assign q2off_in = (((~qwen[2] & (rdptr[1:0] == 2'd2)) & (q2off | f0_shift_2B)) | ((~qwen[2] & (rdptr[1:0] == 2'd1)) & (q2off | f1_shift_2B))) | ((~qwen[2] & (rdptr[1:0] == 2'd0)) & q2off); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:279:4 + assign q1off_in = (((~qwen[1] & (rdptr[1:0] == 2'd1)) & (q1off | f0_shift_2B)) | ((~qwen[1] & (rdptr[1:0] == 2'd0)) & (q1off | f1_shift_2B))) | ((~qwen[1] & (rdptr[1:0] == 2'd2)) & q1off); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:283:4 + assign q0off_in = (((~qwen[0] & (rdptr[1:0] == 2'd0)) & (q0off | f0_shift_2B)) | ((~qwen[0] & (rdptr[1:0] == 2'd2)) & (q0off | f1_shift_2B))) | ((~qwen[0] & (rdptr[1:0] == 2'd1)) & q0off); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:289:4 + assign q0ptr = (((rdptr[1:0] == 2'b00) & q0off) | ((rdptr[1:0] == 2'b01) & q1off)) | ((rdptr[1:0] == 2'b10) & q2off); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:293:4 + assign q1ptr = (((rdptr[1:0] == 2'b00) & q1off) | ((rdptr[1:0] == 2'b01) & q2off)) | ((rdptr[1:0] == 2'b10) & q0off); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:297:4 + assign q0sel[1:0] = {q0ptr, ~q0ptr}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:299:4 + assign q1sel[1:0] = {q1ptr, ~q1ptr}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:306:4 + generate + if (pt[2130-:5] == 1) begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:307:6 + assign misc_data_in[MHI:0] = {ic_access_fault_type_f[1:0], ifu_bp_btb_target_f[31:1], ifu_bp_poffset_f[11:0], ifu_bp_fghr_f[pt[2236-:8] - 1:0]}; + end + else begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:315:6 + assign misc_data_in[MHI:0] = {ic_access_fault_type_f[1:0]}; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:320:4 + assign {misc1eff[MHI:0], misc0eff[MHI:0]} = (({MSIZE * 2 {qren[0]}} & {misc1[MHI:0], misc0[MHI:0]}) | ({MSIZE * 2 {qren[1]}} & {misc2[MHI:0], misc1[MHI:0]})) | ({MSIZE * 2 {qren[2]}} & {misc0[MHI:0], misc2[MHI:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:324:4 + generate + if (pt[2130-:5] == 1) begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:325:4 + assign {f1ictype[1:0], f1prett[31:1], f1poffset[11:0], f1fghr[pt[2236-:8] - 1:0]} = misc1eff[MHI:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:332:4 + assign {f0ictype[1:0], f0prett[31:1], f0poffset[11:0], f0fghr[pt[2236-:8] - 1:0]} = misc0eff[MHI:0]; + if (pt[2120-:5]) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:340:10 + assign brdata_in[BRDATA_SIZE - 1:0] = {ifu_bp_fa_index_f[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])], iccm_rd_ecc_double_err[1], ic_access_fault_f[1], ifu_bp_hist1_f[1], ifu_bp_hist0_f[1], ifu_bp_pc4_f[1], ifu_bp_way_f[1], ifu_bp_valid_f[1], ifu_bp_ret_f[1], ifu_bp_fa_index_f[0+:$clog2(pt[2061-:14])], iccm_rd_ecc_double_err[0], ic_access_fault_f[0], ifu_bp_hist1_f[0], ifu_bp_hist0_f[0], ifu_bp_pc4_f[0], ifu_bp_way_f[0], ifu_bp_valid_f[0], ifu_bp_ret_f[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:344:10 + assign {f0index[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])], f0dbecc[1], f0icaf[1], f0hist1[1], f0hist0[1], f0pc4[1], f0way[1], f0brend[1], f0ret[1], f0index[0+:$clog2(pt[2061-:14])], f0dbecc[0], f0icaf[0], f0hist1[0], f0hist0[0], f0pc4[0], f0way[0], f0brend[0], f0ret[0]} = brdata0final[BRDATA_SIZE - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:347:10 + assign {f1index[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])], f1dbecc[1], f1icaf[1], f1hist1[1], f1hist0[1], f1pc4[1], f1way[1], f1brend[1], f1ret[1], f1index[0+:$clog2(pt[2061-:14])], f1dbecc[0], f1icaf[0], f1hist1[0], f1hist0[0], f1pc4[0], f1way[0], f1brend[0], f1ret[0]} = brdata1final[BRDATA_SIZE - 1:0]; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:352:10 + assign brdata_in[BRDATA_SIZE - 1:0] = {iccm_rd_ecc_double_err[1], ic_access_fault_f[1], ifu_bp_hist1_f[1], ifu_bp_hist0_f[1], ifu_bp_pc4_f[1], ifu_bp_way_f[1], ifu_bp_valid_f[1], ifu_bp_ret_f[1], iccm_rd_ecc_double_err[0], ic_access_fault_f[0], ifu_bp_hist1_f[0], ifu_bp_hist0_f[0], ifu_bp_pc4_f[0], ifu_bp_way_f[0], ifu_bp_valid_f[0], ifu_bp_ret_f[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:356:10 + assign {f0dbecc[1], f0icaf[1], f0hist1[1], f0hist0[1], f0pc4[1], f0way[1], f0brend[1], f0ret[1], f0dbecc[0], f0icaf[0], f0hist1[0], f0hist0[0], f0pc4[0], f0way[0], f0brend[0], f0ret[0]} = brdata0final[BRDATA_SIZE - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:359:10 + assign {f1dbecc[1], f1icaf[1], f1hist1[1], f1hist0[1], f1pc4[1], f1way[1], f1brend[1], f1ret[1], f1dbecc[0], f1icaf[0], f1hist1[0], f1hist0[0], f1pc4[0], f1way[0], f1brend[0], f1ret[0]} = brdata1final[BRDATA_SIZE - 1:0]; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:367:4 + assign {brdata1eff[BRDATA_SIZE - 1:0], brdata0eff[BRDATA_SIZE - 1:0]} = (({BRDATA_SIZE * 2 {qren[0]}} & {brdata1[BRDATA_SIZE - 1:0], brdata0[BRDATA_SIZE - 1:0]}) | ({BRDATA_SIZE * 2 {qren[1]}} & {brdata2[BRDATA_SIZE - 1:0], brdata1[BRDATA_SIZE - 1:0]})) | ({BRDATA_SIZE * 2 {qren[2]}} & {brdata0[BRDATA_SIZE - 1:0], brdata2[BRDATA_SIZE - 1:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:371:4 + assign brdata0final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q0sel[0]}} & {brdata0eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q0sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata0eff[BRDATA_SIZE - 1:BRDATA_WIDTH]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:374:4 + assign brdata1final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q1sel[0]}} & {brdata1eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q1sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata1eff[BRDATA_SIZE - 1:BRDATA_WIDTH]}); + end + else begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:379:7 + assign {f1ictype[1:0]} = misc1eff[MHI:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:383:7 + assign {f0ictype[1:0]} = misc0eff[MHI:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:387:7 + assign brdata_in[BRDATA_SIZE - 1:0] = {iccm_rd_ecc_double_err[1], ic_access_fault_f[1], iccm_rd_ecc_double_err[0], ic_access_fault_f[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:391:7 + assign {f0dbecc[1], f0icaf[1], f0dbecc[0], f0icaf[0]} = brdata0final[BRDATA_SIZE - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:394:7 + assign {f1dbecc[1], f1icaf[1], f1dbecc[0], f1icaf[0]} = brdata1final[BRDATA_SIZE - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:397:7 + assign {brdata1eff[BRDATA_SIZE - 1:0], brdata0eff[BRDATA_SIZE - 1:0]} = (({BRDATA_SIZE * 2 {qren[0]}} & {brdata1[BRDATA_SIZE - 1:0], brdata0[BRDATA_SIZE - 1:0]}) | ({BRDATA_SIZE * 2 {qren[1]}} & {brdata2[BRDATA_SIZE - 1:0], brdata1[BRDATA_SIZE - 1:0]})) | ({BRDATA_SIZE * 2 {qren[2]}} & {brdata0[BRDATA_SIZE - 1:0], brdata2[BRDATA_SIZE - 1:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:401:7 + assign brdata0final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q0sel[0]}} & {brdata0eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q0sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata0eff[BRDATA_SIZE - 1:BRDATA_WIDTH]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:404:7 + assign brdata1final[BRDATA_SIZE - 1:0] = ({BRDATA_SIZE {q1sel[0]}} & {brdata1eff[(2 * BRDATA_WIDTH) - 1:0]}) | ({BRDATA_SIZE {q1sel[1]}} & {{BRDATA_WIDTH {1'b0}}, brdata1eff[BRDATA_SIZE - 1:BRDATA_WIDTH]}); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:421:4 + assign f2_valid = f2val[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:422:4 + assign sf1_valid = sf1val[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:423:4 + assign sf0_valid = sf0val[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:427:4 + assign consume_fb0 = ~sf0val[0] & f0val[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:429:4 + assign consume_fb1 = ~sf1val[0] & f1val[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:431:4 + assign ifu_fb_consume1 = (consume_fb0 & ~consume_fb1) & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:432:4 + assign ifu_fb_consume2 = (consume_fb0 & consume_fb1) & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:434:4 + assign ifvalid = ifu_fetch_val[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:436:4 + assign shift_f1_f0 = ~sf0_valid & sf1_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:437:4 + assign shift_f2_f0 = (~sf0_valid & ~sf1_valid) & f2_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:438:4 + assign shift_f2_f1 = (~sf0_valid & sf1_valid) & f2_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:440:4 + assign fetch_to_f0 = ((~sf0_valid & ~sf1_valid) & ~f2_valid) & ifvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:442:4 + assign fetch_to_f1 = ((((~sf0_valid & ~sf1_valid) & f2_valid) & ifvalid) | (((~sf0_valid & sf1_valid) & ~f2_valid) & ifvalid)) | (((sf0_valid & ~sf1_valid) & ~f2_valid) & ifvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:446:4 + assign fetch_to_f2 = (((~sf0_valid & sf1_valid) & f2_valid) & ifvalid) | (((sf0_valid & sf1_valid) & ~f2_valid) & ifvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:450:4 + assign f2val_in[1:0] = ({2 {fetch_to_f2 & ~exu_flush_final}} & ifu_fetch_val[1:0]) | ({2 {((~fetch_to_f2 & ~shift_f2_f1) & ~shift_f2_f0) & ~exu_flush_final}} & f2val[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:454:4 + assign sf1val[1:0] = ({2 {f1_shift_2B}} & {1'b0, f1val[1]}) | ({2 {~f1_shift_2B}} & f1val[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:457:4 + assign f1val_in[1:0] = (({2 {fetch_to_f1 & ~exu_flush_final}} & ifu_fetch_val[1:0]) | ({2 {shift_f2_f1 & ~exu_flush_final}} & f2val[1:0])) | ({2 {((~fetch_to_f1 & ~shift_f2_f1) & ~shift_f1_f0) & ~exu_flush_final}} & sf1val[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:463:4 + assign sf0val[1:0] = ({2 {shift_2B}} & {1'b0, f0val[1]}) | ({2 {~shift_2B & ~shift_4B}} & f0val[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:466:4 + assign f0val_in[1:0] = ((({2 {fetch_to_f0 & ~exu_flush_final}} & ifu_fetch_val[1:0]) | ({2 {shift_f2_f0 & ~exu_flush_final}} & f2val[1:0])) | ({2 {shift_f1_f0 & ~exu_flush_final}} & sf1val[1:0])) | ({2 {((~fetch_to_f0 & ~shift_f2_f0) & ~shift_f1_f0) & ~exu_flush_final}} & sf0val[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:471:4 + assign {q1eff[31:0], q0eff[31:0]} = (({64 {qren[0]}} & {q1[31:0], q0[31:0]}) | ({64 {qren[1]}} & {q2[31:0], q1[31:0]})) | ({64 {qren[2]}} & {q0[31:0], q2[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:475:4 + assign q0final[31:0] = ({32 {q0sel[0]}} & {q0eff[31:0]}) | ({32 {q0sel[1]}} & {16'b0000000000000000, q0eff[31:16]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:478:4 + assign q1final[15:0] = ({16 {q1sel[0]}} & q1eff[15:0]) | ({16 {q1sel[1]}} & q1eff[31:16]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:480:4 + wire [31:1] q0pceff; + wire [31:1] q0pcfinal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:481:4 + wire [31:1] q1pceff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:483:4 + assign {q1pceff[31:1], q0pceff[31:1]} = (({62 {qren[0]}} & {q1pc[31:1], q0pc[31:1]}) | ({62 {qren[1]}} & {q2pc[31:1], q1pc[31:1]})) | ({62 {qren[2]}} & {q0pc[31:1], q2pc[31:1]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:488:4 + assign q0pcfinal[31:1] = ({31 {q0sel[0]}} & q0pceff[31:1]) | ({31 {q0sel[1]}} & (q0pceff[31:1] + 31'd1)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:491:4 + assign aligndata[31:0] = ({32 {f0val[1]}} & {q0final[31:0]}) | ({32 {~f0val[1] & f0val[0]}} & {q1final[15:0], q0final[15:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:494:4 + assign alignval[1:0] = ({2 {f0val[1]}} & 2'b11) | ({2 {~f0val[1] & f0val[0]}} & {f1val[0], 1'b1}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:497:4 + assign alignicaf[1:0] = ({2 {f0val[1]}} & f0icaf[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1icaf[0], f0icaf[0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:500:4 + assign aligndbecc[1:0] = ({2 {f0val[1]}} & f0dbecc[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1dbecc[0], f0dbecc[0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:503:4 + generate + if (pt[2130-:5] == 1) begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:507:4 + assign alignbrend[1:0] = ({2 {f0val[1]}} & f0brend[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1brend[0], f0brend[0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:510:4 + assign alignpc4[1:0] = ({2 {f0val[1]}} & f0pc4[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1pc4[0], f0pc4[0]}); + if (pt[2120-:5]) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:514:10 + assign alignindex[0+:$clog2(pt[2061-:14])] = f0index[0+:$clog2(pt[2061-:14])]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:515:10 + assign alignindex[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])] = (f0val[1] ? f0index[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])] : f1index[0+:$clog2(pt[2061-:14])]); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:518:4 + assign alignret[1:0] = ({2 {f0val[1]}} & f0ret[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1ret[0], f0ret[0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:521:4 + assign alignway[1:0] = ({2 {f0val[1]}} & f0way[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1way[0], f0way[0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:524:4 + assign alignhist1[1:0] = ({2 {f0val[1]}} & f0hist1[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1hist1[0], f0hist1[0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:527:4 + assign alignhist0[1:0] = ({2 {f0val[1]}} & f0hist0[1:0]) | ({2 {~f0val[1] & f0val[0]}} & {f1hist0[0], f0hist0[0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:530:4 + assign secondpc[31:1] = ({31 {f0val[1]}} & (q0pceff[31:1] + 31'd1)) | ({31 {~f0val[1] & f0val[0]}} & q1pceff[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:535:4 + assign firstpc[31:1] = q0pcfinal[31:1]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:538:4 + assign alignfromf1[1] = ~f0val[1] & f0val[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:541:4 + assign ifu_i0_pc[31:1] = q0pcfinal[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:544:4 + assign ifu_i0_pc4 = first4B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:547:4 + assign ifu_i0_cinst[15:0] = aligndata[15:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:549:4 + assign first4B = aligndata[1:0] == 2'b11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:550:4 + assign first2B = ~first4B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:552:4 + assign ifu_i0_valid = (first4B & alignval[1]) | (first2B & alignval[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:556:4 + assign ifu_i0_icaf = (first4B & |alignicaf[1:0]) | (first2B & alignicaf[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:559:4 + assign ifu_i0_icaf_type[1:0] = ((((first4B & ~f0val[1]) & f0val[0]) & ~alignicaf[0]) & ~aligndbecc[0] ? f1ictype[1:0] : f0ictype[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:562:4 + assign icaf_eff[1:0] = alignicaf[1:0] | aligndbecc[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:564:4 + assign ifu_i0_icaf_second = (first4B & ~icaf_eff[0]) & icaf_eff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:566:4 + assign ifu_i0_dbecc = (first4B & |aligndbecc[1:0]) | (first2B & aligndbecc[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:570:4 + assign ifirst[31:0] = aligndata[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:573:4 + assign ifu_i0_instr[31:0] = ({32 {first4B & alignval[1]}} & ifirst[31:0]) | ({32 {first2B & alignval[0]}} & uncompress0[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:576:1 + generate + if (pt[2130-:5] == 1) begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:580:4 + el2_btb_addr_hash #(.pt(pt)) firsthash( + .pc(firstpc[pt[2079-:9]:pt[2106-:9]]), + .hash(firstpc_hash[pt[2172-:9]:pt[2163-:6]]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:582:4 + el2_btb_addr_hash #(.pt(pt)) secondhash( + .pc(secondpc[pt[2079-:9]:pt[2106-:9]]), + .hash(secondpc_hash[pt[2172-:9]:pt[2163-:6]]) + ); + if (pt[2120-:5]) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:586:7 + assign firstbrtag_hash = firstpc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:587:7 + assign secondbrtag_hash = secondpc; + end + else begin : genblk1 + if (pt[2144-:5]) begin : btbfold + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:591:10 + el2_btb_tag_hash_fold #(.pt(pt)) first_brhash( + .pc(firstpc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]), + .hash(firstbrtag_hash[pt[2139-:9] - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:593:10 + el2_btb_tag_hash_fold #(.pt(pt)) second_brhash( + .pc(secondpc[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]), + .hash(secondbrtag_hash[pt[2139-:9] - 1:0]) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:597:10 + el2_btb_tag_hash #(.pt(pt)) first_brhash( + .pc(firstpc[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]), + .hash(firstbrtag_hash[pt[2139-:9] - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:599:10 + el2_btb_tag_hash #(.pt(pt)) second_brhash( + .pc(secondpc[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]), + .hash(secondbrtag_hash[pt[2139-:9] - 1:0]) + ); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:608:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:610:7 + i0_brp = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:612:7 + i0_br_start_error = (first4B & alignval[1]) & alignbrend[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:614:7 + i0_brp[50] = ((first2B & alignbrend[0]) | (first4B & alignbrend[1])) | i0_br_start_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:618:7 + i0_brp_pc4 = (first2B & alignpc4[0]) | (first4B & alignpc4[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:621:7 + i0_brp[0] = (first2B & alignret[0]) | (first4B & alignret[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:624:7 + i0_brp[1] = (first2B | alignbrend[0] ? alignway[0] : alignway[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:626:7 + i0_brp[37] = (first2B & alignhist1[0]) | (first4B & alignhist1[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:629:7 + i0_brp[36] = (first2B & alignhist0[0]) | (first4B & alignhist0[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:632:7 + i0_ends_f1 = first4B & alignfromf1[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:634:7 + i0_brp[49:38] = (i0_ends_f1 ? f1poffset[11:0] : f0poffset[11:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:636:7 + i0_brp[32:2] = (i0_ends_f1 ? f1prett[31:1] : f0prett[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:638:7 + i0_brp[34] = i0_br_start_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:640:7 + i0_brp[33] = (first2B | alignbrend[0] ? firstpc[1] : secondpc[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:642:7 + i0_brp[35] = ((i0_brp[50] & i0_brp_pc4) & first2B) | ((i0_brp[50] & ~i0_brp_pc4) & first4B); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:645:7 + if (pt[2120-:5]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:646:9 + ifu_i0_fa_index = (first2B | alignbrend[0] ? alignindex[0+:$clog2(pt[2061-:14])] : alignindex[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])]); + else + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:648:9 + ifu_i0_fa_index = 1'sb0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:653:4 + assign ifu_i0_bp_index[pt[2172-:9]:pt[2163-:6]] = (first2B | alignbrend[0] ? firstpc_hash[pt[2172-:9]:pt[2163-:6]] : secondpc_hash[pt[2172-:9]:pt[2163-:6]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:656:4 + assign ifu_i0_bp_fghr[pt[2236-:8] - 1:0] = (i0_ends_f1 ? f1fghr[pt[2236-:8] - 1:0] : f0fghr[pt[2236-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:659:4 + assign ifu_i0_bp_btag[pt[2139-:9] - 1:0] = (first2B | alignbrend[0] ? firstbrtag_hash[pt[2139-:9] - 1:0] : secondbrtag_hash[pt[2139-:9] - 1:0]); + end + else begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:663:4 + wire [51:1] sv2v_tmp_8E3E7; + assign sv2v_tmp_8E3E7 = 1'sb0; + always @(*) i0_brp = sv2v_tmp_8E3E7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:664:4 + assign ifu_i0_bp_index = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:665:4 + assign ifu_i0_bp_fghr = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:666:4 + assign ifu_i0_bp_btag = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:672:4 + // removed localparam type sv2v_uu_compress0_din + localparam [15:0] sv2v_uu_compress0_ext_din_0 = 1'sb0; + el2_ifu_compress_ctl compress0( + .din((first2B ? aligndata[15:0] : sv2v_uu_compress0_ext_din_0)), + .dout(uncompress0[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:676:4 + assign i0_shift = dec_i0_decode_d & ~error_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:678:4 + assign ifu_pmu_instr_aligned = i0_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:683:4 + assign shift_2B = i0_shift & first2B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:685:4 + assign shift_4B = i0_shift & first4B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:688:4 + assign f0_shift_2B = (shift_2B & f0val[0]) | ((shift_4B & f0val[0]) & ~f0val[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_aln_ctl.sv:697:4 + assign f1_shift_2B = (f0val[0] & ~f0val[1]) & shift_4B; + initial _sv2v_0 = 0; +endmodule +module el2_ifu_compress_ctl ( + din, + dout +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:26:4 + input wire [15:0] din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:27:4 + output wire [31:0] dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:31:4 + wire legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:33:4 + wire [15:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:35:4 + wire [31:0] o; + wire [31:0] l1; + wire [31:0] l2; + wire [31:0] l3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:38:4 + assign i[15:0] = din[15:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:41:4 + wire [4:0] rs2d; + wire [4:0] rdd; + wire [4:0] rdpd; + wire [4:0] rs2pd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:43:4 + wire rdrd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:44:4 + wire rdrs1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:45:4 + wire rs2rs2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:46:4 + wire rdprd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:47:4 + wire rdprs1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:48:4 + wire rs2prs2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:49:4 + wire rs2prd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:50:4 + wire uimm9_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:51:4 + wire ulwimm6_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:52:4 + wire ulwspimm7_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:53:4 + wire rdeq2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:54:4 + wire rdeq1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:55:4 + wire rs1eq2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:56:4 + wire sbroffset8_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:57:4 + wire simm9_4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:58:4 + wire simm5_0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:59:4 + wire sjaloffset11_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:60:4 + wire sluimm17_12; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:61:4 + wire uimm5_0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:62:4 + wire uswimm6_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:63:4 + wire uswspimm7_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:76:4 + assign rs2d[4:0] = i[6:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:78:4 + assign rdd[4:0] = i[11:7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:80:4 + assign rdpd[4:0] = {2'b01, i[9:7]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:82:4 + assign rs2pd[4:0] = {2'b01, i[4:2]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:90:4 + assign l1[6:0] = o[6:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:92:4 + assign l1[11:7] = ((((o[11:7] | ({5 {rdrd}} & rdd[4:0])) | ({5 {rdprd}} & rdpd[4:0])) | ({5 {rs2prd}} & rs2pd[4:0])) | ({5 {rdeq1}} & 5'd1)) | ({5 {rdeq2}} & 5'd2); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:101:4 + assign l1[14:12] = o[14:12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:102:4 + assign l1[19:15] = ((o[19:15] | ({5 {rdrs1}} & rdd[4:0])) | ({5 {rdprs1}} & rdpd[4:0])) | ({5 {rs1eq2}} & 5'd2); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:109:4 + assign l1[24:20] = (o[24:20] | ({5 {rs2rs2}} & rs2d[4:0])) | ({5 {rs2prs2}} & rs2pd[4:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:113:4 + assign l1[31:25] = o[31:25]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:115:4 + wire [5:0] simm5d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:116:4 + wire [9:2] uimm9d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:118:4 + wire [9:4] simm9d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:119:4 + wire [6:2] ulwimm6d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:120:4 + wire [7:2] ulwspimm7d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:121:4 + wire [5:0] uimm5d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:122:4 + wire [20:1] sjald; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:124:4 + wire [31:12] sluimmd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:128:4 + assign simm5d[5:0] = {i[12], i[6:2]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:130:4 + assign uimm9d[9:2] = {i[10:7], i[12:11], i[5], i[6]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:132:4 + assign simm9d[9:4] = {i[12], i[4:3], i[5], i[2], i[6]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:134:4 + assign ulwimm6d[6:2] = {i[5], i[12:10], i[6]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:136:4 + assign ulwspimm7d[7:2] = {i[3:2], i[12], i[6:4]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:138:4 + assign uimm5d[5:0] = {i[12], i[6:2]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:140:4 + assign sjald[11:1] = {i[12], i[8], i[10:9], i[6], i[7], i[2], i[11], i[5:4], i[3]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:142:4 + assign sjald[20:12] = {9 {i[12]}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:146:4 + assign sluimmd[31:12] = {{15 {i[12]}}, i[6:2]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:149:4 + assign l2[31:20] = (((((((l1[31:20] | ({12 {simm5_0}} & {{7 {simm5d[5]}}, simm5d[4:0]})) | ({12 {uimm9_2}} & {2'b00, uimm9d[9:2], 2'b00})) | ({12 {simm9_4}} & {{3 {simm9d[9]}}, simm9d[8:4], 4'b0000})) | ({12 {ulwimm6_2}} & {5'b00000, ulwimm6d[6:2], 2'b00})) | ({12 {ulwspimm7_2}} & {4'b0000, ulwspimm7d[7:2], 2'b00})) | ({12 {uimm5_0}} & {6'b000000, uimm5d[5:0]})) | ({12 {sjaloffset11_1}} & {sjald[20], sjald[10:1], sjald[11]})) | ({12 {sluimm17_12}} & sluimmd[31:20]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:161:4 + assign l2[19:12] = (l1[19:12] | ({8 {sjaloffset11_1}} & sjald[19:12])) | ({8 {sluimm17_12}} & sluimmd[19:12]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:166:4 + assign l2[11:0] = l1[11:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:171:4 + wire [8:1] sbr8d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:172:4 + wire [6:2] uswimm6d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:173:4 + wire [7:2] uswspimm7d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:176:4 + assign sbr8d[8:1] = {i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:178:4 + assign uswimm6d[6:2] = {i[5], i[12:10], i[6]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:180:4 + assign uswspimm7d[7:2] = {i[8:7], i[12:9]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:182:4 + assign l3[31:25] = ((l2[31:25] | ({7 {sbroffset8_1}} & {{4 {sbr8d[8]}}, sbr8d[7:5]})) | ({7 {uswimm6_2}} & {5'b00000, uswimm6d[6:5]})) | ({7 {uswspimm7_2}} & {4'b0000, uswspimm7d[7:5]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:188:4 + assign l3[24:12] = l2[24:12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:190:4 + assign l3[11:7] = ((l2[11:7] | ({5 {sbroffset8_1}} & {sbr8d[4:1], sbr8d[8]})) | ({5 {uswimm6_2}} & {uswimm6d[4:2], 2'b00})) | ({5 {uswspimm7_2}} & {uswspimm7d[4:2], 2'b00}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:195:4 + assign l3[6:0] = l2[6:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:198:4 + assign dout[31:0] = l3[31:0] & {32 {legal}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:221:1 + assign rdrd = ((((((((((((!i[14] & i[6]) & i[1]) | (((!i[15] & i[14]) & i[11]) & i[0])) | ((!i[14] & i[5]) & i[1])) | (((!i[15] & i[14]) & i[10]) & i[0])) | ((!i[14] & i[4]) & i[1])) | (((!i[15] & i[14]) & i[9]) & i[0])) | ((!i[14] & i[3]) & i[1])) | (((!i[15] & i[14]) & !i[8]) & i[0])) | ((!i[14] & i[2]) & i[1])) | (((!i[15] & i[14]) & i[7]) & i[0])) | (!i[15] & i[1])) | ((!i[15] & !i[13]) & i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:227:1 + assign rdrs1 = ((((((((((((((!i[14] & i[12]) & i[11]) & i[1]) | (((!i[14] & i[12]) & i[10]) & i[1])) | (((!i[14] & i[12]) & i[9]) & i[1])) | (((!i[14] & i[12]) & i[8]) & i[1])) | (((!i[14] & i[12]) & i[7]) & i[1])) | (((((((!i[14] & !i[12]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | (((!i[14] & i[12]) & i[6]) & i[1])) | (((!i[14] & i[12]) & i[5]) & i[1])) | (((!i[14] & i[12]) & i[4]) & i[1])) | (((!i[14] & i[12]) & i[3]) & i[1])) | (((!i[14] & i[12]) & i[2]) & i[1])) | (((!i[15] & !i[14]) & !i[13]) & i[0])) | ((!i[15] & !i[14]) & i[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:234:1 + assign rs2rs2 = ((((((i[15] & i[6]) & i[1]) | ((i[15] & i[5]) & i[1])) | ((i[15] & i[4]) & i[1])) | ((i[15] & i[3]) & i[1])) | ((i[15] & i[2]) & i[1])) | ((i[15] & i[14]) & i[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:237:1 + assign rdprd = ((i[15] & !i[14]) & !i[13]) & i[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:239:1 + assign rdprs1 = (((i[15] & !i[13]) & i[0]) | ((i[15] & i[14]) & i[0])) | ((i[14] & !i[1]) & !i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:241:1 + assign rs2prs2 = (((((i[15] & !i[14]) & !i[13]) & i[11]) & i[10]) & i[0]) | ((i[15] & !i[1]) & !i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:243:1 + assign rs2prd = (!i[15] & !i[1]) & !i[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:245:1 + assign uimm9_2 = (!i[14] & !i[1]) & !i[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:247:1 + assign ulwimm6_2 = ((!i[15] & i[14]) & !i[1]) & !i[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:249:1 + assign ulwspimm7_2 = (!i[15] & i[14]) & i[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:251:1 + assign rdeq2 = ((((((!i[15] & i[14]) & i[13]) & !i[11]) & !i[10]) & !i[9]) & i[8]) & !i[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:253:1 + assign rdeq1 = ((((((((((((!i[14] & i[12]) & i[11]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) | ((((((((!i[14] & i[12]) & i[10]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[9]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[8]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[7]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((!i[15] & !i[14]) & i[13]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:259:1 + assign rs1eq2 = ((((((((!i[15] & i[14]) & i[13]) & !i[11]) & !i[10]) & !i[9]) & i[8]) & !i[7]) | (i[14] & i[1])) | ((!i[14] & !i[1]) & !i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:262:1 + assign sbroffset8_1 = (i[15] & i[14]) & i[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:264:1 + assign simm9_4 = ((((((!i[15] & i[14]) & i[13]) & !i[11]) & !i[10]) & !i[9]) & i[8]) & !i[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:266:1 + assign simm5_0 = ((((!i[14] & !i[13]) & i[11]) & !i[10]) & i[0]) | ((!i[15] & !i[13]) & i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:268:1 + assign sjaloffset11_1 = !i[14] & i[13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:270:1 + assign sluimm17_12 = ((((((!i[15] & i[14]) & i[13]) & i[7]) | (((!i[15] & i[14]) & i[13]) & !i[8])) | (((!i[15] & i[14]) & i[13]) & i[9])) | (((!i[15] & i[14]) & i[13]) & i[10])) | (((!i[15] & i[14]) & i[13]) & i[11]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:274:1 + assign uimm5_0 = ((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[0]) | ((!i[15] & !i[14]) & i[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:276:1 + assign uswimm6_2 = (i[15] & !i[1]) & !i[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:278:1 + assign uswspimm7_2 = (i[15] & i[14]) & i[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:280:1 + assign o[31] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:282:1 + assign o[30] = ((((((i[15] & !i[14]) & !i[13]) & i[10]) & !i[6]) & !i[5]) & i[0]) | (((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[10]) & i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:285:1 + assign o[29] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:287:1 + assign o[28] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:289:1 + assign o[27] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:291:1 + assign o[26] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:293:1 + assign o[25] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:295:1 + assign o[24] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:297:1 + assign o[23] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:299:1 + assign o[22] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:301:1 + assign o[21] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:303:1 + assign o[20] = (((((((((((!i[14] & i[12]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:306:1 + assign o[19] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:308:1 + assign o[18] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:310:1 + assign o[17] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:312:1 + assign o[16] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:314:1 + assign o[15] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:316:1 + assign o[14] = ((((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[0]) | ((((i[15] & !i[14]) & !i[13]) & !i[10]) & i[0])) | ((((i[15] & !i[14]) & !i[13]) & i[6]) & i[0])) | ((((i[15] & !i[14]) & !i[13]) & i[5]) & i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:320:1 + assign o[13] = ((((((i[15] & !i[14]) & !i[13]) & i[11]) & !i[10]) & i[0]) | (((((i[15] & !i[14]) & !i[13]) & i[11]) & i[6]) & i[0])) | (i[14] & !i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:323:1 + assign o[12] = ((((((((i[15] & !i[14]) & !i[13]) & i[6]) & i[5]) & i[0]) | ((((i[15] & !i[14]) & !i[13]) & !i[11]) & i[0])) | ((((i[15] & !i[14]) & !i[13]) & !i[10]) & i[0])) | ((!i[15] & !i[14]) & i[1])) | ((i[15] & i[14]) & i[13]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:327:1 + assign o[11] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:329:1 + assign o[10] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:331:1 + assign o[9] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:333:1 + assign o[8] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:335:1 + assign o[7] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:337:1 + assign o[6] = ((((((((i[15] & !i[14]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & !i[0]) | (!i[14] & i[13])) | ((i[15] & i[14]) & i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:340:1 + assign o[5] = ((((((((i[15] & !i[0]) | ((i[15] & i[11]) & i[10])) | (i[13] & !i[8])) | (i[13] & i[7])) | (i[13] & i[9])) | (i[13] & i[10])) | (i[13] & i[11])) | (!i[14] & i[13])) | (i[15] & i[14]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:344:1 + assign o[4] = (((((((((((((!i[14] & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[0]) | ((!i[15] & !i[14]) & !i[0])) | ((!i[14] & i[6]) & !i[0])) | ((!i[15] & i[14]) & i[0])) | ((!i[14] & i[5]) & !i[0])) | ((!i[14] & i[4]) & !i[0])) | ((!i[14] & !i[13]) & i[0])) | ((!i[14] & i[3]) & !i[0])) | ((!i[14] & i[2]) & !i[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:349:1 + assign o[3] = !i[14] & i[13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:351:1 + assign o[2] = ((((((((((((((((((!i[14] & i[12]) & i[11]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) | ((((((((!i[14] & i[12]) & i[10]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[9]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[8]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((!i[14] & i[12]) & i[7]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1])) | ((((((((i[15] & !i[14]) & !i[12]) & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & !i[0])) | ((!i[15] & i[13]) & !i[8])) | ((!i[15] & i[13]) & i[7])) | ((!i[15] & i[13]) & i[9])) | ((!i[15] & i[13]) & i[10])) | ((!i[15] & i[13]) & i[11])) | (!i[14] & i[13]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:361:1 + assign o[1] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:363:1 + assign o[0] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_compress_ctl.sv:365:1 + assign legal = (((((((((((((((((((((((((((((((((!i[13] & !i[12]) & i[11]) & i[1]) & !i[0]) | ((((!i[13] & !i[12]) & i[6]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[11]) & !i[1])) | ((((!i[13] & !i[12]) & i[5]) & i[1]) & !i[0])) | ((((!i[13] & !i[12]) & i[10]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[6]) & !i[1])) | (((i[15] & !i[12]) & !i[1]) & i[0])) | ((((!i[13] & !i[12]) & i[9]) & i[1]) & !i[0])) | (((!i[12] & i[6]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[5]) & !i[1])) | ((((!i[13] & !i[12]) & i[8]) & i[1]) & !i[0])) | (((!i[12] & i[5]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[10]) & !i[1])) | ((((!i[13] & !i[12]) & i[7]) & i[1]) & !i[0])) | ((((i[12] & i[11]) & !i[10]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[9]) & !i[1])) | ((((!i[13] & !i[12]) & i[4]) & i[1]) & !i[0])) | (((i[13] & i[12]) & !i[1]) & i[0])) | (((!i[15] & !i[13]) & i[8]) & !i[1])) | ((((!i[13] & !i[12]) & i[3]) & i[1]) & !i[0])) | (((i[13] & i[4]) & !i[1]) & i[0])) | ((((!i[13] & !i[12]) & i[2]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[7]) & !i[1])) | (((i[13] & i[3]) & !i[1]) & i[0])) | (((i[13] & i[2]) & !i[1]) & i[0])) | ((i[14] & !i[13]) & !i[1])) | (((!i[14] & !i[12]) & !i[1]) & i[0])) | ((((i[15] & !i[13]) & i[12]) & i[1]) & !i[0])) | ((((!i[15] & !i[13]) & !i[12]) & i[1]) & !i[0])) | (((!i[15] & !i[13]) & i[12]) & !i[1])) | ((i[14] & !i[13]) & !i[0]); +endmodule +module el2_ifu_ifc_ctl ( + clk, + free_l2clk, + rst_l, + scan_mode, + ic_hit_f, + ifu_ic_mb_empty, + ifu_fb_consume1, + ifu_fb_consume2, + dec_tlu_flush_noredir_wb, + exu_flush_final, + exu_flush_path_final, + ifu_bp_hit_taken_f, + ifu_bp_btb_target_f, + ic_dma_active, + ic_write_stall, + dma_iccm_stall_any, + dec_tlu_mrac_ff, + ifc_fetch_addr_f, + ifc_fetch_addr_bf, + ifc_fetch_req_f, + ifu_pmu_fetch_stall, + ifc_fetch_uncacheable_bf, + ifc_fetch_req_bf, + ifc_fetch_req_bf_raw, + ifc_iccm_access_bf, + ifc_region_acc_fault_bf, + ifc_dma_access_ok +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:29:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:30:4 + input wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:32:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:33:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:35:4 + input wire ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:36:4 + input wire ifu_ic_mb_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:38:4 + input wire ifu_fb_consume1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:39:4 + input wire ifu_fb_consume2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:41:4 + input wire dec_tlu_flush_noredir_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:42:4 + input wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:43:4 + input wire [31:1] exu_flush_path_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:45:4 + input wire ifu_bp_hit_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:46:4 + input wire [31:1] ifu_bp_btb_target_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:48:4 + input wire ic_dma_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:49:4 + input wire ic_write_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:50:4 + input wire dma_iccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:52:4 + input wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:54:4 + output wire [31:1] ifc_fetch_addr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:55:4 + output wire [31:1] ifc_fetch_addr_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:57:4 + output wire ifc_fetch_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:59:4 + output wire ifu_pmu_fetch_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:61:4 + output wire ifc_fetch_uncacheable_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:62:4 + output wire ifc_fetch_req_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:63:4 + output wire ifc_fetch_req_bf_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:64:4 + output wire ifc_iccm_access_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:65:4 + output wire ifc_region_acc_fault_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:67:4 + output wire ifc_dma_access_ok; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:72:4 + wire [31:1] fetch_addr_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:73:4 + wire [31:1] fetch_addr_next; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:74:4 + wire [3:0] fb_write_f; + wire [3:0] fb_write_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:76:4 + wire fb_full_f_ns; + wire fb_full_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:77:4 + wire fb_right; + wire fb_right2; + wire fb_left; + wire wfm; + wire idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:78:4 + wire sel_last_addr_bf; + wire sel_next_addr_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:79:4 + wire miss_f; + wire miss_a; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:80:4 + wire flush_fb; + wire dma_iccm_stall_any_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:81:4 + wire mb_empty_mod; + wire goto_idle; + wire leave_idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:82:4 + wire fetch_bf_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:83:4 + wire line_wrap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:84:4 + wire fetch_addr_next_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:87:5 + // removed localparam type state_t + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:91:4 + wire [1:0] state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:92:4 + wire [1:0] next_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:94:4 + wire dma_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:95:4 + assign dma_stall = ic_dma_active | dma_iccm_stall_any_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:104:1 + generate + if (pt[2130-:5] == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:105:4 + wire sel_btb_addr_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:107:4 + assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:108:4 + assign sel_btb_addr_bf = ((~exu_flush_final & ifc_fetch_req_f) & ifu_bp_hit_taken_f) & ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:109:4 + assign sel_next_addr_bf = ((~exu_flush_final & ifc_fetch_req_f) & ~ifu_bp_hit_taken_f) & ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:112:4 + assign fetch_addr_bf[31:1] = ((({31 {exu_flush_final}} & exu_flush_path_final[31:1]) | ({31 {sel_last_addr_bf}} & ifc_fetch_addr_f[31:1])) | ({31 {sel_btb_addr_bf}} & {ifu_bp_btb_target_f[31:1]})) | ({31 {sel_next_addr_bf}} & {fetch_addr_next[31:1]}); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:120:4 + assign sel_last_addr_bf = ~exu_flush_final & (~ifc_fetch_req_f | ~ic_hit_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:121:4 + assign sel_next_addr_bf = (~exu_flush_final & ifc_fetch_req_f) & ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:124:4 + assign fetch_addr_bf[31:1] = (({31 {exu_flush_final}} & exu_flush_path_final[31:1]) | ({31 {sel_last_addr_bf}} & ifc_fetch_addr_f[31:1])) | ({31 {sel_next_addr_bf}} & {fetch_addr_next[31:1]}); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:129:4 + assign fetch_addr_next[31:1] = {{ifc_fetch_addr_f[31:2]} + 31'b0000000000000000000000000000001, fetch_addr_next_1}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:130:4 + assign line_wrap = fetch_addr_next[pt[998-:7]] ^ ifc_fetch_addr_f[pt[998-:7]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:132:4 + assign fetch_addr_next_1 = (line_wrap ? 1'b0 : ifc_fetch_addr_f[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:134:4 + assign ifc_fetch_req_bf_raw = ~idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:135:4 + assign ifc_fetch_req_bf = (((ifc_fetch_req_bf_raw & ~(fb_full_f_ns & ~(ifu_fb_consume2 | ifu_fb_consume1))) & ~dma_stall) & ~ic_write_stall) & ~dec_tlu_flush_noredir_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:143:4 + assign fetch_bf_en = exu_flush_final | ifc_fetch_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:145:4 + assign miss_f = (ifc_fetch_req_f & ~ic_hit_f) & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:147:4 + assign mb_empty_mod = (((ifu_ic_mb_empty | exu_flush_final) & ~dma_stall) & ~miss_f) & ~miss_a; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:150:4 + assign goto_idle = exu_flush_final & dec_tlu_flush_noredir_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:152:4 + assign leave_idle = (exu_flush_final & ~dec_tlu_flush_noredir_wb) & idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:172:4 + assign next_state[1] = (((~state[1] & state[0]) & miss_f) & ~goto_idle) | ((state[1] & ~mb_empty_mod) & ~goto_idle); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:175:4 + assign next_state[0] = (~goto_idle & leave_idle) | (state[0] & ~goto_idle); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:177:4 + assign flush_fb = exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:180:4 + assign fb_right = ((ifu_fb_consume1 & ~ifu_fb_consume2) & (~ifc_fetch_req_f | miss_f)) | (ifu_fb_consume2 & ifc_fetch_req_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:184:4 + assign fb_right2 = ifu_fb_consume2 & (~ifc_fetch_req_f | miss_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:186:4 + assign fb_left = (ifc_fetch_req_f & ~(ifu_fb_consume1 | ifu_fb_consume2)) & ~miss_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:189:4 + assign fb_write_ns[3:0] = (((({4 {flush_fb}} & 4'b0001) | ({4 {~flush_fb & fb_right}} & {1'b0, fb_write_f[3:1]})) | ({4 {~flush_fb & fb_right2}} & {2'b00, fb_write_f[3:2]})) | ({4 {~flush_fb & fb_left}} & {fb_write_f[2:0], 1'b0})) | ({4 {((~flush_fb & ~fb_right) & ~fb_right2) & ~fb_left}} & fb_write_f[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:196:4 + assign fb_full_f_ns = fb_write_ns[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:198:4 + assign idle = state == 2'b00; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:199:4 + assign wfm = state == 2'b11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:201:4 + rvdffie #(.WIDTH(10)) fbwrite_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({dma_iccm_stall_any, miss_f, ifc_fetch_req_bf, next_state[1:0], fb_full_f_ns, fb_write_ns[3:0]}), + .dout({dma_iccm_stall_any_f, miss_a, ifc_fetch_req_f, state[1:0], fb_full_f, fb_write_f[3:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:205:4 + assign ifu_pmu_fetch_stall = wfm | (ifc_fetch_req_bf_raw & ((fb_full_f & ~((ifu_fb_consume2 | ifu_fb_consume1) | exu_flush_final)) | dma_stall)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:212:4 + assign ifc_fetch_addr_bf[31:1] = fetch_addr_bf[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:214:4 + rvdffpcie #(.WIDTH(31)) faddrf1_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(fetch_bf_en), + .din(fetch_addr_bf[31:1]), + .dout(ifc_fetch_addr_f[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:217:2 + generate + if (pt[927-:5]) begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:218:4 + wire iccm_acc_in_region_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:219:4 + wire iccm_acc_in_range_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:220:4 + rvrangecheck #( + .CCM_SADR(pt[887-:36]), + .CCM_SIZE(pt[851-:14]) + ) iccm_rangecheck( + .addr({ifc_fetch_addr_bf[31:1], 1'b0}), + .in_range(iccm_acc_in_range_bf), + .in_region(iccm_acc_in_region_bf) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:227:4 + assign ifc_iccm_access_bf = iccm_acc_in_range_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:229:3 + assign ifc_dma_access_ok = ((((~ifc_iccm_access_bf | (fb_full_f & ~(ifu_fb_consume2 | ifu_fb_consume1))) | (wfm & ~ifc_fetch_req_bf)) | idle) & ~exu_flush_final) | dma_iccm_stall_any_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:235:3 + assign ifc_region_acc_fault_bf = ~iccm_acc_in_range_bf & iccm_acc_in_region_bf; + end + else begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:238:4 + assign ifc_iccm_access_bf = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:239:4 + assign ifc_dma_access_ok = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:240:4 + assign ifc_region_acc_fault_bf = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ifc_ctl.sv:243:4 + assign ifc_fetch_uncacheable_bf = ~dec_tlu_mrac_ff[{ifc_fetch_addr_bf[31:28], 1'b0}]; +endmodule +module el2_ifu_bp_ctl ( + clk, + rst_l, + ic_hit_f, + ifc_fetch_addr_f, + ifc_fetch_req_f, + dec_tlu_br0_r_pkt, + exu_i0_br_fghr_r, + exu_i0_br_index_r, + dec_fa_error_index, + dec_tlu_flush_lower_wb, + dec_tlu_flush_leak_one_wb, + dec_tlu_bpred_disable, + exu_mp_pkt, + exu_mp_eghr, + exu_mp_fghr, + exu_mp_index, + exu_mp_btag, + exu_flush_final, + ifu_bp_hit_taken_f, + ifu_bp_btb_target_f, + ifu_bp_inst_mask_f, + ifu_bp_fghr_f, + ifu_bp_way_f, + ifu_bp_ret_f, + ifu_bp_hist1_f, + ifu_bp_hist0_f, + ifu_bp_pc4_f, + ifu_bp_valid_f, + ifu_bp_poffset_f, + ifu_bp_fa_index_f, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:34:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:35:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:37:4 + input wire ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:39:4 + input wire [31:1] ifc_fetch_addr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:40:4 + input wire ifc_fetch_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:42:4 + // removed localparam type el2_pkg_el2_br_tlu_pkt_t + input wire [6:0] dec_tlu_br0_r_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:43:4 + input wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:44:4 + input wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:46:4 + input wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:48:4 + input wire dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:49:4 + input wire dec_tlu_flush_leak_one_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:51:4 + input wire dec_tlu_bpred_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:53:4 + // removed localparam type el2_pkg_el2_predict_pkt_t + input wire [55:0] exu_mp_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:55:4 + input wire [pt[2236-:8] - 1:0] exu_mp_eghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:56:4 + input wire [pt[2236-:8] - 1:0] exu_mp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:57:4 + input wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:58:4 + input wire [pt[2139-:9] - 1:0] exu_mp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:60:4 + input wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:62:4 + output wire ifu_bp_hit_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:63:4 + output wire [31:1] ifu_bp_btb_target_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:64:4 + output wire ifu_bp_inst_mask_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:66:4 + output wire [pt[2236-:8] - 1:0] ifu_bp_fghr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:68:4 + output wire [1:0] ifu_bp_way_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:69:4 + output wire [1:0] ifu_bp_ret_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:70:4 + output wire [1:0] ifu_bp_hist1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:71:4 + output wire [1:0] ifu_bp_hist0_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:72:4 + output wire [1:0] ifu_bp_pc4_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:73:4 + output wire [1:0] ifu_bp_valid_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:74:4 + output wire [11:0] ifu_bp_poffset_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:76:4 + output wire [(2 * $clog2(pt[2061-:14])) - 1:0] ifu_bp_fa_index_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:78:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:82:4 + localparam BTB_DWIDTH = (pt[2047-:9] + pt[2139-:9]) + 5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:83:4 + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + localparam BTB_DWIDTH_TOP = (sv2v_cast_32_signed(pt[2047-:9]) + sv2v_cast_32_signed(pt[2139-:9])) + 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:84:4 + localparam BTB_FA_INDEX = $clog2(pt[2061-:14]) - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:85:4 + localparam FA_CMP_LOWER = $clog2(pt[1095-:11]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:86:4 + localparam FA_TAG_END_UPPER = ((5 + sv2v_cast_32_signed(pt[2047-:9])) + FA_CMP_LOWER) - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:87:4 + localparam FA_TAG_START_LOWER = (3 + sv2v_cast_32_signed(pt[2047-:9])) + FA_CMP_LOWER; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:88:4 + localparam FA_TAG_END_LOWER = 5 + sv2v_cast_32_signed(pt[2047-:9]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:90:4 + localparam TAG_START = BTB_DWIDTH - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:91:4 + localparam PC4 = 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:92:4 + localparam BOFF = 3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:93:4 + localparam CALL = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:94:4 + localparam RET = 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:95:4 + localparam BV = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:97:4 + localparam LRU_SIZE = pt[2157-:13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:98:4 + localparam NUM_BHT_LOOP = (pt[2256-:15] > 16 ? 16 : pt[2256-:15]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:99:4 + localparam NUM_BHT_LOOP_INNER_HI = (pt[2256-:15] > 16 ? pt[2262-:6] + 3 : pt[2270-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:100:4 + localparam NUM_BHT_LOOP_OUTER_LO = (pt[2256-:15] > 16 ? pt[2262-:6] + 4 : pt[2262-:6]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:101:4 + localparam BHT_NO_ADDR_MATCH = pt[2256-:15] <= 16; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:104:4 + wire exu_mp_valid_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:105:4 + wire exu_mp_ataken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:106:4 + wire exu_mp_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:107:4 + wire exu_mp_boffset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:108:4 + wire exu_mp_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:109:4 + wire exu_mp_call; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:110:4 + wire exu_mp_ret; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:111:4 + wire exu_mp_ja; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:112:4 + wire [1:0] exu_mp_hist; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:113:4 + wire [11:0] exu_mp_tgt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:114:4 + wire [pt[2172-:9]:pt[2163-:6]] exu_mp_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:115:4 + wire dec_tlu_br0_v_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:116:4 + wire [1:0] dec_tlu_br0_hist_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:117:4 + wire [pt[2172-:9]:pt[2163-:6]] dec_tlu_br0_addr_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:118:4 + wire dec_tlu_br0_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:119:4 + wire dec_tlu_br0_start_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:120:4 + wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:122:4 + wire use_mp_way; + wire use_mp_way_p1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:123:4 + wire [(pt[31-:8] * 32) - 1:0] rets_out; + wire [(pt[31-:8] * 32) - 1:0] rets_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:124:4 + wire [pt[31-:8] - 1:0] rsenable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:127:4 + wire [11:0] btb_rd_tgt_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:128:4 + wire btb_rd_pc4_f; + wire btb_rd_call_f; + wire btb_rd_ret_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:129:4 + wire [1:1] bp_total_branch_offset_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:131:4 + wire [31:1] bp_btb_target_adder_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:132:4 + wire [31:1] bp_rs_call_target_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:133:4 + wire rs_push; + wire rs_pop; + wire rs_hold; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:134:4 + wire [pt[2172-:9]:pt[2163-:6]] btb_rd_addr_p1_f; + wire [pt[2172-:9]:pt[2163-:6]] btb_wr_addr; + wire [pt[2172-:9]:pt[2163-:6]] btb_rd_addr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:135:4 + wire [pt[2139-:9] - 1:0] btb_wr_tag; + wire [pt[2139-:9] - 1:0] fetch_rd_tag_f; + wire [pt[2139-:9] - 1:0] fetch_rd_tag_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:136:4 + wire [BTB_DWIDTH - 1:0] btb_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:137:4 + wire btb_wr_en_way0; + wire btb_wr_en_way1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:140:4 + wire dec_tlu_error_wb; + wire btb_valid; + wire dec_tlu_br0_middle_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:141:4 + wire [pt[2172-:9]:pt[2163-:6]] btb_error_addr_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:142:4 + wire branch_error_collision_f; + wire fetch_mp_collision_f; + wire branch_error_collision_p1_f; + wire fetch_mp_collision_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:144:4 + wire branch_error_bank_conflict_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:145:4 + wire [pt[2236-:8] - 1:0] merged_ghr; + wire [pt[2236-:8] - 1:0] fghr_ns; + wire [pt[2236-:8] - 1:0] fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:146:4 + wire [1:0] num_valids; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:147:4 + wire [LRU_SIZE - 1:0] btb_lru_b0_f; + wire [LRU_SIZE - 1:0] btb_lru_b0_hold; + wire [LRU_SIZE - 1:0] btb_lru_b0_ns; + wire [LRU_SIZE - 1:0] fetch_wrindex_dec; + wire [LRU_SIZE - 1:0] fetch_wrindex_p1_dec; + wire [LRU_SIZE - 1:0] fetch_wrlru_b0; + wire [LRU_SIZE - 1:0] fetch_wrlru_p1_b0; + wire [LRU_SIZE - 1:0] mp_wrindex_dec; + wire [LRU_SIZE - 1:0] mp_wrlru_b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:150:4 + wire btb_lru_rd_f; + wire btb_lru_rd_p1_f; + wire lru_update_valid_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:151:4 + wire tag_match_way0_f; + wire tag_match_way1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:152:4 + wire [1:0] way_raw; + wire [1:0] bht_dir_f; + wire [1:0] btb_sel_f; + wire [1:0] wayhit_f; + wire [1:0] vwayhit_f; + wire [1:0] wayhit_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:153:4 + wire [1:0] bht_valid_f; + wire [1:0] bht_force_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:155:4 + wire leak_one_f; + wire leak_one_f_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:157:4 + wire [(LRU_SIZE * BTB_DWIDTH) - 1:0] btb_bank0_rd_data_way0_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:159:4 + wire [(LRU_SIZE * BTB_DWIDTH) - 1:0] btb_bank0_rd_data_way1_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:161:4 + reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way0_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:162:4 + reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:164:4 + reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way0_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:165:4 + reg [BTB_DWIDTH - 1:0] btb_bank0_rd_data_way1_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:167:4 + reg [BTB_DWIDTH - 1:0] btb_vbank0_rd_data_f; + reg [BTB_DWIDTH - 1:0] btb_vbank1_rd_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:169:4 + wire final_h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:170:4 + wire btb_fg_crossing_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:171:4 + wire middle_of_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:174:4 + wire [1:0] bht_vbank0_rd_data_f; + wire [1:0] bht_vbank1_rd_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:175:4 + wire branch_error_bank_conflict_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:176:4 + wire tag_match_way0_p1_f; + wire tag_match_way1_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:178:4 + wire [1:0] btb_vlru_rd_f; + wire [1:0] fetch_start_f; + wire [1:0] tag_match_vway1_expanded_f; + wire [1:0] tag_match_way0_expanded_p1_f; + wire [1:0] tag_match_way1_expanded_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:179:4 + wire [31:2] fetch_addr_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:182:4 + wire exu_mp_way; + wire exu_mp_way_f; + wire dec_tlu_br0_way_wb; + wire dec_tlu_way_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:183:4 + wire [BTB_DWIDTH - 1:0] btb_bank0e_rd_data_f; + wire [BTB_DWIDTH - 1:0] btb_bank0e_rd_data_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:185:4 + wire [BTB_DWIDTH - 1:0] btb_bank0o_rd_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:187:4 + wire [1:0] tag_match_way0_expanded_f; + wire [1:0] tag_match_way1_expanded_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:190:5 + reg [1:0] bht_bank0_rd_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:191:5 + reg [1:0] bht_bank1_rd_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:192:5 + reg [1:0] bht_bank0_rd_data_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:193:4 + genvar _gv_j_2; + genvar _gv_i_7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:195:4 + assign exu_mp_valid = exu_mp_pkt[55] & ~leak_one_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:196:4 + assign exu_mp_boffset = exu_mp_pkt[53]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:197:4 + assign exu_mp_pc4 = exu_mp_pkt[52]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:198:4 + assign exu_mp_call = exu_mp_pkt[34]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:199:4 + assign exu_mp_ret = exu_mp_pkt[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:200:4 + assign exu_mp_ja = exu_mp_pkt[33]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:201:4 + assign exu_mp_way = exu_mp_pkt[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:202:4 + assign exu_mp_hist[1:0] = exu_mp_pkt[51:50]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:203:4 + assign exu_mp_tgt[11:0] = exu_mp_pkt[49:38]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:204:4 + assign exu_mp_addr[pt[2172-:9]:pt[2163-:6]] = exu_mp_index[pt[2172-:9]:pt[2163-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:205:4 + assign exu_mp_ataken = exu_mp_pkt[54]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:208:4 + assign dec_tlu_br0_v_wb = dec_tlu_br0_r_pkt[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:209:4 + assign dec_tlu_br0_hist_wb[1:0] = dec_tlu_br0_r_pkt[5:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:210:4 + assign dec_tlu_br0_addr_wb[pt[2172-:9]:pt[2163-:6]] = exu_i0_br_index_r[pt[2172-:9]:pt[2163-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:211:4 + assign dec_tlu_br0_error_wb = dec_tlu_br0_r_pkt[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:212:4 + assign dec_tlu_br0_middle_wb = dec_tlu_br0_r_pkt[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:213:4 + assign dec_tlu_br0_way_wb = dec_tlu_br0_r_pkt[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:214:4 + assign dec_tlu_br0_start_error_wb = dec_tlu_br0_r_pkt[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:215:4 + assign exu_i0_br_fghr_wb[pt[2236-:8] - 1:0] = exu_i0_br_fghr_r[pt[2236-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:225:4 + el2_btb_addr_hash #(.pt(pt)) f1hash( + .pc(ifc_fetch_addr_f[pt[2079-:9]:pt[2106-:9]]), + .hash(btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:228:4 + assign fetch_addr_p1_f[31:2] = ifc_fetch_addr_f[31:2] + 30'b000000000000000000000000000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:229:4 + el2_btb_addr_hash #(.pt(pt)) f1hash_p1( + .pc(fetch_addr_p1_f[pt[2079-:9]:pt[2106-:9]]), + .hash(btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:231:4 + assign btb_sel_f[1] = ~bht_dir_f[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:232:4 + assign btb_sel_f[0] = bht_dir_f[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:234:4 + assign fetch_start_f[1:0] = {ifc_fetch_addr_f[1], ~ifc_fetch_addr_f[1]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:238:4 + assign branch_error_collision_f = dec_tlu_error_wb & (btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:239:4 + assign branch_error_collision_p1_f = dec_tlu_error_wb & (btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:241:4 + assign branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:242:4 + assign branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:245:4 + assign leak_one_f = (dec_tlu_flush_leak_one_wb & dec_tlu_flush_lower_wb) | (leak_one_f_d1 & ~dec_tlu_flush_lower_wb); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:247:1 + wire exu_flush_final_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:249:2 + generate + if (!pt[2120-:5]) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:250:4 + assign fetch_mp_collision_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == fetch_rd_tag_f[pt[2139-:9] - 1:0]) & exu_mp_valid) & ifc_fetch_req_f) & (exu_mp_addr[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:254:4 + assign fetch_mp_collision_p1_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == fetch_rd_tag_p1_f[pt[2139-:9] - 1:0]) & exu_mp_valid) & ifc_fetch_req_f) & (exu_mp_addr[pt[2172-:9]:pt[2163-:6]] == btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:259:4 + assign tag_match_way0_f = (((btb_bank0_rd_data_way0_f[BV] & (btb_bank0_rd_data_way0_f[TAG_START:17] == fetch_rd_tag_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_f)) & ifc_fetch_req_f) & ~leak_one_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:262:4 + assign tag_match_way1_f = (((btb_bank0_rd_data_way1_f[BV] & (btb_bank0_rd_data_way1_f[TAG_START:17] == fetch_rd_tag_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_f)) & ifc_fetch_req_f) & ~leak_one_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:265:4 + assign tag_match_way0_p1_f = (((btb_bank0_rd_data_way0_p1_f[BV] & (btb_bank0_rd_data_way0_p1_f[TAG_START:17] == fetch_rd_tag_p1_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_p1_f)) & ifc_fetch_req_f) & ~leak_one_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:268:4 + assign tag_match_way1_p1_f = (((btb_bank0_rd_data_way1_p1_f[BV] & (btb_bank0_rd_data_way1_p1_f[TAG_START:17] == fetch_rd_tag_p1_f[pt[2139-:9] - 1:0])) & ~(dec_tlu_way_wb & branch_error_bank_conflict_p1_f)) & ifc_fetch_req_f) & ~leak_one_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:274:4 + assign tag_match_way0_expanded_f[1:0] = {tag_match_way0_f & (btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4]), tag_match_way0_f & ~(btb_bank0_rd_data_way0_f[BOFF] ^ btb_bank0_rd_data_way0_f[PC4])}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:277:4 + assign tag_match_way1_expanded_f[1:0] = {tag_match_way1_f & (btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4]), tag_match_way1_f & ~(btb_bank0_rd_data_way1_f[BOFF] ^ btb_bank0_rd_data_way1_f[PC4])}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:280:4 + assign tag_match_way0_expanded_p1_f[1:0] = {tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4]), tag_match_way0_p1_f & ~(btb_bank0_rd_data_way0_p1_f[BOFF] ^ btb_bank0_rd_data_way0_p1_f[PC4])}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:283:4 + assign tag_match_way1_expanded_p1_f[1:0] = {tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4]), tag_match_way1_p1_f & ~(btb_bank0_rd_data_way1_p1_f[BOFF] ^ btb_bank0_rd_data_way1_p1_f[PC4])}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:286:4 + assign wayhit_f[1:0] = tag_match_way0_expanded_f[1:0] | tag_match_way1_expanded_f[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:287:4 + assign wayhit_p1_f[1:0] = tag_match_way0_expanded_p1_f[1:0] | tag_match_way1_expanded_p1_f[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:289:4 + assign btb_bank0o_rd_data_f[BTB_DWIDTH - 1:0] = ({17 + pt[2139-:9] {tag_match_way0_expanded_f[1]}} & btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {tag_match_way1_expanded_f[1]}} & btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:291:4 + assign btb_bank0e_rd_data_f[BTB_DWIDTH - 1:0] = ({17 + pt[2139-:9] {tag_match_way0_expanded_f[0]}} & btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {tag_match_way1_expanded_f[0]}} & btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:294:4 + assign btb_bank0e_rd_data_p1_f[BTB_DWIDTH - 1:0] = ({17 + pt[2139-:9] {tag_match_way0_expanded_p1_f[0]}} & btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {tag_match_way1_expanded_p1_f[0]}} & btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:299:4 + wire [BTB_DWIDTH * 1:1] sv2v_tmp_E33CE; + assign sv2v_tmp_E33CE = ({17 + pt[2139-:9] {fetch_start_f[0]}} & btb_bank0e_rd_data_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {fetch_start_f[1]}} & btb_bank0o_rd_data_f[BTB_DWIDTH - 1:0]); + always @(*) btb_vbank0_rd_data_f[BTB_DWIDTH - 1:0] = sv2v_tmp_E33CE; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:301:4 + wire [BTB_DWIDTH * 1:1] sv2v_tmp_72FE2; + assign sv2v_tmp_72FE2 = ({17 + pt[2139-:9] {fetch_start_f[0]}} & btb_bank0o_rd_data_f[BTB_DWIDTH - 1:0]) | ({17 + pt[2139-:9] {fetch_start_f[1]}} & btb_bank0e_rd_data_p1_f[BTB_DWIDTH - 1:0]); + always @(*) btb_vbank1_rd_data_f[BTB_DWIDTH - 1:0] = sv2v_tmp_72FE2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:304:4 + assign way_raw[1:0] = tag_match_vway1_expanded_f[1:0] | (~vwayhit_f[1:0] & btb_vlru_rd_f[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:312:4 + assign mp_wrindex_dec[LRU_SIZE - 1:0] = {{LRU_SIZE - 1 {1'b0}}, 1'b1} << exu_mp_addr[pt[2172-:9]:pt[2163-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:315:4 + assign fetch_wrindex_dec[LRU_SIZE - 1:0] = {{LRU_SIZE - 1 {1'b0}}, 1'b1} << btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:316:4 + assign fetch_wrindex_p1_dec[LRU_SIZE - 1:0] = {{LRU_SIZE - 1 {1'b0}}, 1'b1} << btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:318:4 + assign mp_wrlru_b0[LRU_SIZE - 1:0] = mp_wrindex_dec[LRU_SIZE - 1:0] & {LRU_SIZE {exu_mp_valid}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:321:4 + assign btb_lru_b0_hold[LRU_SIZE - 1:0] = ~mp_wrlru_b0[LRU_SIZE - 1:0] & ~fetch_wrlru_b0[LRU_SIZE - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:324:4 + assign use_mp_way = fetch_mp_collision_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:325:4 + assign use_mp_way_p1 = fetch_mp_collision_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:327:4 + assign lru_update_valid_f = ((vwayhit_f[0] | vwayhit_f[1]) & ifc_fetch_req_f) & ~leak_one_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:330:4 + assign fetch_wrlru_b0[LRU_SIZE - 1:0] = fetch_wrindex_dec[LRU_SIZE - 1:0] & {LRU_SIZE {lru_update_valid_f}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:332:4 + assign fetch_wrlru_p1_b0[LRU_SIZE - 1:0] = fetch_wrindex_p1_dec[LRU_SIZE - 1:0] & {LRU_SIZE {lru_update_valid_f}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:335:4 + assign btb_lru_b0_ns[LRU_SIZE - 1:0] = (((btb_lru_b0_hold[LRU_SIZE - 1:0] & btb_lru_b0_f[LRU_SIZE - 1:0]) | (mp_wrlru_b0[LRU_SIZE - 1:0] & {LRU_SIZE {~exu_mp_way}})) | (fetch_wrlru_b0[LRU_SIZE - 1:0] & {LRU_SIZE {tag_match_way0_f}})) | (fetch_wrlru_p1_b0[LRU_SIZE - 1:0] & {LRU_SIZE {tag_match_way0_p1_f}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:342:4 + assign btb_lru_rd_f = (use_mp_way ? exu_mp_way_f : |(fetch_wrindex_dec[LRU_SIZE - 1:0] & btb_lru_b0_f[LRU_SIZE - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:344:4 + assign btb_lru_rd_p1_f = (use_mp_way_p1 ? exu_mp_way_f : |(fetch_wrindex_p1_dec[LRU_SIZE - 1:0] & btb_lru_b0_f[LRU_SIZE - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:347:4 + assign btb_vlru_rd_f[1:0] = ({2 {fetch_start_f[0]}} & {btb_lru_rd_f, btb_lru_rd_f}) | ({2 {fetch_start_f[1]}} & {btb_lru_rd_p1_f, btb_lru_rd_f}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:350:4 + assign tag_match_vway1_expanded_f[1:0] = ({2 {fetch_start_f[0]}} & {tag_match_way1_expanded_f[1:0]}) | ({2 {fetch_start_f[1]}} & {tag_match_way1_expanded_p1_f[0], tag_match_way1_expanded_f[1]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:354:4 + rvdffe #(.WIDTH(LRU_SIZE)) btb_lru_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(ifc_fetch_req_f | exu_mp_valid), + .din(btb_lru_b0_ns[LRU_SIZE - 1:0]), + .dout(btb_lru_b0_f[LRU_SIZE - 1:0]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:360:4 + wire eoc_near; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:361:4 + wire eoc_mask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:362:4 + assign eoc_near = &ifc_fetch_addr_f[pt[1182-:8]:3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:363:4 + assign eoc_mask = ~eoc_near | (|(~ifc_fetch_addr_f[2:1])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:372:4 + wire [16:1] btb_sel_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:374:4 + assign btb_rd_tgt_f[11:0] = btb_sel_data_f[16:5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:375:4 + assign btb_rd_pc4_f = btb_sel_data_f[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:376:4 + assign btb_rd_call_f = btb_sel_data_f[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:377:4 + assign btb_rd_ret_f = btb_sel_data_f[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:379:4 + assign btb_sel_data_f[16:1] = ({16 {btb_sel_f[1]}} & btb_vbank1_rd_data_f[16:1]) | ({16 {btb_sel_f[0]}} & btb_vbank0_rd_data_f[16:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:383:4 + wire [1:0] hist0_raw; + wire [1:0] hist1_raw; + wire [1:0] pc4_raw; + wire [1:0] pret_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:386:4 + assign ifu_bp_hit_taken_f = ((|(vwayhit_f[1:0] & hist1_raw[1:0]) & ifc_fetch_req_f) & ~leak_one_f_d1) & ~dec_tlu_bpred_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:390:4 + assign bht_force_taken_f[1:0] = {btb_vbank1_rd_data_f[CALL] | btb_vbank1_rd_data_f[RET], btb_vbank0_rd_data_f[CALL] | btb_vbank0_rd_data_f[RET]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:395:4 + assign bht_valid_f[1:0] = vwayhit_f[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:397:4 + assign bht_vbank0_rd_data_f[1:0] = ({2 {fetch_start_f[0]}} & bht_bank0_rd_data_f[1:0]) | ({2 {fetch_start_f[1]}} & bht_bank1_rd_data_f[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:400:4 + assign bht_vbank1_rd_data_f[1:0] = ({2 {fetch_start_f[0]}} & bht_bank1_rd_data_f[1:0]) | ({2 {fetch_start_f[1]}} & bht_bank0_rd_data_p1_f[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:404:4 + assign bht_dir_f[1:0] = {(bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]) & bht_valid_f[1], (bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]) & bht_valid_f[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:407:4 + assign ifu_bp_inst_mask_f = (ifu_bp_hit_taken_f & btb_sel_f[1]) | ~ifu_bp_hit_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:427:4 + assign hist1_raw[1:0] = bht_force_taken_f[1:0] | {bht_vbank1_rd_data_f[1], bht_vbank0_rd_data_f[1]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:430:4 + assign hist0_raw[1:0] = {bht_vbank1_rd_data_f[0], bht_vbank0_rd_data_f[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:434:4 + assign pc4_raw[1:0] = {vwayhit_f[1] & btb_vbank1_rd_data_f[PC4], vwayhit_f[0] & btb_vbank0_rd_data_f[PC4]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:437:4 + assign pret_raw[1:0] = {(vwayhit_f[1] & ~btb_vbank1_rd_data_f[CALL]) & btb_vbank1_rd_data_f[RET], (vwayhit_f[0] & ~btb_vbank0_rd_data_f[CALL]) & btb_vbank0_rd_data_f[RET]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:444:4 + function [1:0] countones; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:889:7 + input [1:0] valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:891:7 + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:893:1 + countones[1:0] = {2'b00, valid[1]} + {2'b00, valid[0]}; + end + endfunction + assign num_valids[1:0] = countones(bht_valid_f[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:453:4 + assign final_h = |(btb_sel_f[1:0] & bht_dir_f[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:455:4 + assign merged_ghr[pt[2236-:8] - 1:0] = (({pt[2236-:8] {num_valids[1:0] == 2'h2}} & {fghr[pt[2236-:8] - 3:0], 1'b0, final_h}) | ({pt[2236-:8] {num_valids[1:0] == 2'h1}} & {fghr[pt[2236-:8] - 2:0], final_h})) | ({pt[2236-:8] {num_valids[1:0] == 2'h0}} & {fghr[pt[2236-:8] - 1:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:460:4 + wire [pt[2236-:8] - 1:0] exu_flush_ghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:461:4 + assign exu_flush_ghr[pt[2236-:8] - 1:0] = exu_mp_fghr[pt[2236-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:463:4 + assign fghr_ns[pt[2236-:8] - 1:0] = (({pt[2236-:8] {exu_flush_final_d1}} & exu_flush_ghr[pt[2236-:8] - 1:0]) | ({pt[2236-:8] {((~exu_flush_final_d1 & ifc_fetch_req_f) & ic_hit_f) & ~leak_one_f_d1}} & merged_ghr[pt[2236-:8] - 1:0])) | ({pt[2236-:8] {~exu_flush_final_d1 & ~((ifc_fetch_req_f & ic_hit_f) & ~leak_one_f_d1)}} & fghr[pt[2236-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:467:4 + rvdffie #( + .WIDTH(pt[2236-:8] + 3), + .OVERRIDE(1) + ) fetchghr( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({exu_flush_final, exu_mp_way, leak_one_f, fghr_ns[pt[2236-:8] - 1:0]}), + .dout({exu_flush_final_d1, exu_mp_way_f, leak_one_f_d1, fghr[pt[2236-:8] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:471:4 + assign ifu_bp_fghr_f[pt[2236-:8] - 1:0] = fghr[pt[2236-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:474:4 + assign ifu_bp_way_f[1:0] = way_raw[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:475:4 + assign ifu_bp_hist1_f[1:0] = hist1_raw[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:476:4 + assign ifu_bp_hist0_f[1:0] = hist0_raw[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:477:4 + assign ifu_bp_pc4_f[1:0] = pc4_raw[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:479:4 + assign ifu_bp_valid_f[1:0] = vwayhit_f[1:0] & ~{2 {dec_tlu_bpred_disable}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:480:4 + assign ifu_bp_ret_f[1:0] = pret_raw[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:500:1 + wire [1:0] bloc_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:501:1 + wire use_fa_plus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:502:1 + assign bloc_f[1] = (bht_dir_f[0] & ~fetch_start_f[0]) | (~bht_dir_f[0] & fetch_start_f[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:504:1 + assign bloc_f[0] = (bht_dir_f[0] & fetch_start_f[0]) | (~bht_dir_f[0] & ~fetch_start_f[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:506:1 + assign use_fa_plus = (~bht_dir_f[0] & ~fetch_start_f[0]) & ~btb_rd_pc4_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:511:5 + assign btb_fg_crossing_f = (fetch_start_f[0] & btb_sel_f[0]) & btb_rd_pc4_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:513:4 + assign bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:515:4 + wire [31:2] adder_pc_in_f; + wire [31:2] ifc_fetch_adder_prior; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:516:4 + rvdfflie #( + .WIDTH(30), + .LEFT(19) + ) faddrf_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((ifc_fetch_req_f & ~ifu_bp_hit_taken_f) & ic_hit_f), + .din(ifc_fetch_addr_f[31:2]), + .dout(ifc_fetch_adder_prior[31:2]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:519:4 + assign ifu_bp_poffset_f[11:0] = btb_rd_tgt_f[11:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:521:4 + assign adder_pc_in_f[31:2] = (({30 {use_fa_plus}} & fetch_addr_p1_f[31:2]) | ({30 {btb_fg_crossing_f}} & ifc_fetch_adder_prior[31:2])) | ({30 {~btb_fg_crossing_f & ~use_fa_plus}} & ifc_fetch_addr_f[31:2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:525:4 + rvbradder predtgt_addr( + .pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}), + .offset(btb_rd_tgt_f[11:0]), + .dout(bp_btb_target_adder_f[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:530:4 + assign ifu_bp_btb_target_f[31:1] = ({31 {((btb_rd_ret_f & ~btb_rd_call_f) & rets_out[0]) & ifu_bp_hit_taken_f}} & rets_out[31-:31]) | ({31 {~((btb_rd_ret_f & ~btb_rd_call_f) & rets_out[0]) & ifu_bp_hit_taken_f}} & bp_btb_target_adder_f[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:538:4 + rvbradder rs_addr( + .pc({adder_pc_in_f[31:2], bp_total_branch_offset_f}), + .offset({11'b00000000000, ~btb_rd_pc4_f}), + .dout(bp_rs_call_target_f[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:543:4 + assign rs_push = (btb_rd_call_f & ~btb_rd_ret_f) & ifu_bp_hit_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:544:4 + assign rs_pop = (btb_rd_ret_f & ~btb_rd_call_f) & ifu_bp_hit_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:545:4 + assign rs_hold = ~rs_push & ~rs_pop; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:550:4 + assign rets_in[31-:32] = ({32 {rs_push}} & {bp_rs_call_target_f[31:1], 1'b1}) | ({32 {rs_pop}} & rets_out[63-:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:553:4 + assign rsenable[0] = ~rs_hold; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:555:4 + generate + for (_gv_i_7 = 0; _gv_i_7 < pt[31-:8]; _gv_i_7 = _gv_i_7 + 1) begin : retstack + localparam i = _gv_i_7; + if (i == (pt[31-:8] - 1)) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:559:10 + assign rets_in[(i * 32) + 31-:32] = rets_out[((i - 1) * 32) + 31-:32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:560:10 + assign rsenable[i] = rs_push; + end + else if (i > 0) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:563:9 + assign rets_in[(i * 32) + 31-:32] = ({32 {rs_push}} & rets_out[((i - 1) * 32) + 31-:32]) | ({32 {rs_pop}} & rets_out[((i + 1) * 32) + 31-:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:565:10 + assign rsenable[i] = rs_push | rs_pop; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:567:7 + rvdffe #(.WIDTH(32)) rets_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(rsenable[i]), + .din(rets_in[(i * 32) + 31-:32]), + .dout(rets_out[(i * 32) + 31-:32]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:576:4 + assign dec_tlu_error_wb = dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:578:4 + assign btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] = dec_tlu_br0_addr_wb[pt[2172-:9]:pt[2163-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:580:4 + assign dec_tlu_way_wb = dec_tlu_br0_way_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:582:4 + assign btb_valid = exu_mp_valid & ~dec_tlu_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:584:4 + assign btb_wr_tag[pt[2139-:9] - 1:0] = exu_mp_btag[pt[2139-:9] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:586:4 + generate + if (!pt[2120-:5]) begin : genblk3 + if (pt[2144-:5]) begin : btbfold + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:589:10 + el2_btb_tag_hash_fold #(.pt(pt)) rdtagf( + .hash(fetch_rd_tag_f[pt[2139-:9] - 1:0]), + .pc({ifc_fetch_addr_f[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:591:10 + el2_btb_tag_hash_fold #(.pt(pt)) rdtagp1f( + .hash(fetch_rd_tag_p1_f[pt[2139-:9] - 1:0]), + .pc({fetch_addr_p1_f[(pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]}) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:595:10 + el2_btb_tag_hash #(.pt(pt)) rdtagf( + .hash(fetch_rd_tag_f[pt[2139-:9] - 1:0]), + .pc({ifc_fetch_addr_f[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:597:10 + el2_btb_tag_hash #(.pt(pt)) rdtagp1f( + .hash(fetch_rd_tag_p1_f[pt[2139-:9] - 1:0]), + .pc({fetch_addr_p1_f[((pt[2172-:9] + pt[2139-:9]) + pt[2139-:9]) + pt[2139-:9]:pt[2172-:9] + 1]}) + ); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:601:7 + assign btb_wr_en_way0 = {(~exu_mp_way & exu_mp_valid_write) & ~dec_tlu_error_wb} | {~dec_tlu_way_wb & dec_tlu_error_wb}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:604:7 + assign btb_wr_en_way1 = {(exu_mp_way & exu_mp_valid_write) & ~dec_tlu_error_wb} | {dec_tlu_way_wb & dec_tlu_error_wb}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:606:7 + assign btb_wr_addr[pt[2172-:9]:pt[2163-:6]] = (dec_tlu_error_wb ? btb_error_addr_wb[pt[2172-:9]:pt[2163-:6]] : exu_mp_addr[pt[2172-:9]:pt[2163-:6]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:609:7 + assign vwayhit_f[1:0] = (({2 {fetch_start_f[0]}} & {wayhit_f[1:0]}) | ({2 {fetch_start_f[1]}} & {wayhit_p1_f[0], wayhit_f[1]})) & {eoc_mask, 1'b1}; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:614:4 + assign btb_wr_data[BTB_DWIDTH - 1:0] = {btb_wr_tag[pt[2139-:9] - 1:0], exu_mp_tgt[pt[2047-:9] - 1:0], exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:617:4 + assign exu_mp_valid_write = (exu_mp_valid & exu_mp_ataken) & ~exu_mp_pkt[37]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:618:4 + wire [1:0] bht_wr_data0; + wire [1:0] bht_wr_data2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:619:4 + wire [1:0] bht_wr_en0; + wire [1:0] bht_wr_en2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:621:4 + assign middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:622:4 + assign bht_wr_en0[1:0] = {2 {((exu_mp_valid & ~exu_mp_call) & ~exu_mp_ret) & ~exu_mp_ja}} & {middle_of_bank, ~middle_of_bank}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:623:4 + assign bht_wr_en2[1:0] = {2 {dec_tlu_br0_v_wb}} & {dec_tlu_br0_middle_wb, ~dec_tlu_br0_middle_wb}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:626:4 + assign bht_wr_data0[1:0] = exu_mp_hist[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:627:4 + assign bht_wr_data2[1:0] = dec_tlu_br0_hist_wb[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:631:4 + wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_f; + wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_p1_f; + wire [pt[2270-:8]:pt[2262-:6]] bht_wr_addr0; + wire [pt[2270-:8]:pt[2262-:6]] bht_wr_addr2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:633:4 + wire [pt[2270-:8]:pt[2262-:6]] mp_hashed; + wire [pt[2270-:8]:pt[2262-:6]] br0_hashed_wb; + wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_hashed_f; + wire [pt[2270-:8]:pt[2262-:6]] bht_rd_addr_hashed_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:634:4 + el2_btb_ghr_hash #(.pt(pt)) mpghrhs( + .hashin(exu_mp_addr[pt[2172-:9]:pt[2163-:6]]), + .ghr(exu_mp_eghr[pt[2236-:8] - 1:0]), + .hash(mp_hashed[pt[2270-:8]:pt[2262-:6]]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:635:4 + el2_btb_ghr_hash #(.pt(pt)) br0ghrhs( + .hashin(dec_tlu_br0_addr_wb[pt[2172-:9]:pt[2163-:6]]), + .ghr(exu_i0_br_fghr_wb[pt[2236-:8] - 1:0]), + .hash(br0_hashed_wb[pt[2270-:8]:pt[2262-:6]]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:636:4 + el2_btb_ghr_hash #(.pt(pt)) fghrhs( + .hashin(btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]]), + .ghr(fghr[pt[2236-:8] - 1:0]), + .hash(bht_rd_addr_hashed_f[pt[2270-:8]:pt[2262-:6]]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:637:4 + el2_btb_ghr_hash #(.pt(pt)) fghrhs_p1( + .hashin(btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]]), + .ghr(fghr[pt[2236-:8] - 1:0]), + .hash(bht_rd_addr_hashed_p1_f[pt[2270-:8]:pt[2262-:6]]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:639:4 + assign bht_wr_addr0[pt[2270-:8]:pt[2262-:6]] = mp_hashed[pt[2270-:8]:pt[2262-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:640:4 + assign bht_wr_addr2[pt[2270-:8]:pt[2262-:6]] = br0_hashed_wb[pt[2270-:8]:pt[2262-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:641:4 + assign bht_rd_addr_f[pt[2270-:8]:pt[2262-:6]] = bht_rd_addr_hashed_f[pt[2270-:8]:pt[2262-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:642:4 + assign bht_rd_addr_p1_f[pt[2270-:8]:pt[2262-:6]] = bht_rd_addr_hashed_p1_f[pt[2270-:8]:pt[2262-:6]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:651:4 + function automatic signed [(((pt[2172-:9] - pt[2163-:6]) + 0) >= 0 ? (pt[2172-:9] - pt[2163-:6]) + 1 : 1 - ((pt[2172-:9] - pt[2163-:6]) + 0)) - 1:0] sv2v_cast_649B5_signed; + input reg signed [(((pt[2172-:9] - pt[2163-:6]) + 0) >= 0 ? (pt[2172-:9] - pt[2163-:6]) + 1 : 1 - ((pt[2172-:9] - pt[2163-:6]) + 0)) - 1:0] inp; + sv2v_cast_649B5_signed = inp; + endfunction + generate + if (!pt[2120-:5]) begin : genblk4 + for (_gv_j_2 = 0; _gv_j_2 < LRU_SIZE; _gv_j_2 = _gv_j_2 + 1) begin : BTB_FLOPS + localparam j = _gv_j_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:655:10 + rvdffe #(.WIDTH(17 + pt[2139-:9])) btb_bank0_way0( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((btb_wr_addr[pt[2172-:9]:pt[2163-:6]] == j) & btb_wr_en_way0), + .din(btb_wr_data[BTB_DWIDTH - 1:0]), + .dout(btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:661:10 + rvdffe #(.WIDTH(17 + pt[2139-:9])) btb_bank0_way1( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((btb_wr_addr[pt[2172-:9]:pt[2163-:6]] == j) & btb_wr_en_way1), + .din(btb_wr_data[BTB_DWIDTH - 1:0]), + .dout(btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH]) + ); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:669:5 + always @(*) begin : BTB_rd_mux + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:670:9 + btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:671:9 + btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:672:9 + btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:673:9 + btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:675:9 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:675:14 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:675:14 + for (j = 0; j < LRU_SIZE; j = j + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:676:11 + if (btb_rd_addr_f[pt[2172-:9]:pt[2163-:6]] == sv2v_cast_649B5_signed(j)) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:678:12 + btb_bank0_rd_data_way0_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:679:12 + btb_bank0_rd_data_way1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH]; + end + end + end + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:683:14 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:683:14 + for (j = 0; j < LRU_SIZE; j = j + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:684:11 + if (btb_rd_addr_p1_f[pt[2172-:9]:pt[2163-:6]] == sv2v_cast_649B5_signed(j)) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:686:12 + btb_bank0_rd_data_way0_p1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way0_out[j * BTB_DWIDTH+:BTB_DWIDTH]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:687:12 + btb_bank0_rd_data_way1_p1_f[BTB_DWIDTH - 1:0] = btb_bank0_rd_data_way1_out[j * BTB_DWIDTH+:BTB_DWIDTH]; + end + end + end + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:698:7 + function automatic signed [((BTB_FA_INDEX + 0) >= 0 ? BTB_FA_INDEX + 1 : 1 - (BTB_FA_INDEX + 0)) - 1:0] sv2v_cast_0890C_signed; + input reg signed [((BTB_FA_INDEX + 0) >= 0 ? BTB_FA_INDEX + 1 : 1 - (BTB_FA_INDEX + 0)) - 1:0] inp; + sv2v_cast_0890C_signed = inp; + endfunction + generate + if (pt[2120-:5]) begin : fa + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:700:10 + reg found1; + reg hit0; + reg hit1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:701:10 + wire btb_used_reset; + wire write_used; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:702:10 + reg [$clog2(pt[2061-:14]) - 1:0] btb_fa_wr_addr0; + reg [$clog2(pt[2061-:14]) - 1:0] hit0_index; + reg [$clog2(pt[2061-:14]) - 1:0] hit1_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:704:10 + wire [pt[2061-:14] - 1:0] btb_tag_hit; + wire [pt[2061-:14] - 1:0] btb_offset_0; + wire [pt[2061-:14] - 1:0] btb_offset_1; + wire [pt[2061-:14] - 1:0] btb_used_ns; + wire [pt[2061-:14] - 1:0] btb_used; + wire [pt[2061-:14] - 1:0] wr0_en; + wire [pt[2061-:14] - 1:0] btb_upper_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:706:10 + wire [(pt[2061-:14] * BTB_DWIDTH) - 1:0] btbdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:711:10 + wire [FA_CMP_LOWER - 1:1] ifc_fetch_addr_p1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:714:10 + assign ifc_fetch_addr_p1_f[FA_CMP_LOWER - 1:1] = ifc_fetch_addr_f[FA_CMP_LOWER - 1:1] + 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:716:10 + assign fetch_mp_collision_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == ifc_fetch_addr_f[31:1]) & exu_mp_valid) & ifc_fetch_req_f) & ~exu_mp_pkt[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:718:10 + assign fetch_mp_collision_p1_f = (((exu_mp_btag[pt[2139-:9] - 1:0] == {ifc_fetch_addr_f[31:FA_CMP_LOWER], ifc_fetch_addr_p1_f[FA_CMP_LOWER - 1:1]}) & exu_mp_valid) & ifc_fetch_req_f) & ~exu_mp_pkt[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:721:7 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:722:10 + btb_vbank0_rd_data_f = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:723:10 + btb_vbank1_rd_data_f = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:729:10 + found1 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:730:10 + hit0 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:731:10 + hit1 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:732:10 + hit0_index = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:733:10 + hit1_index = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:734:10 + btb_fa_wr_addr0 = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:736:10 + begin : sv2v_autoblock_3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:736:14 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:736:14 + for (i = 0; i < pt[2061-:14]; i = i + 1) + begin : sv2v_autoblock_4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:737:13 + reg upper_hit; + reg offset_0; + reg offset_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:746:13 + upper_hit = ((btbdata[(i * BTB_DWIDTH) + (BTB_DWIDTH_TOP >= FA_TAG_END_UPPER ? BTB_DWIDTH_TOP : (BTB_DWIDTH_TOP + (BTB_DWIDTH_TOP >= FA_TAG_END_UPPER ? (BTB_DWIDTH_TOP - FA_TAG_END_UPPER) + 1 : (FA_TAG_END_UPPER - BTB_DWIDTH_TOP) + 1)) - 1)-:(BTB_DWIDTH_TOP >= FA_TAG_END_UPPER ? (BTB_DWIDTH_TOP - FA_TAG_END_UPPER) + 1 : (FA_TAG_END_UPPER - BTB_DWIDTH_TOP) + 1)] == ifc_fetch_addr_f[31:FA_CMP_LOWER]) & btbdata[i * BTB_DWIDTH]) & ~wr0_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:747:13 + offset_0 = (btbdata[(i * BTB_DWIDTH) + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? FA_TAG_START_LOWER : (FA_TAG_START_LOWER + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)) - 1)-:(FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)] == ifc_fetch_addr_f[FA_CMP_LOWER - 1:1]) & upper_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:748:13 + offset_1 = (btbdata[(i * BTB_DWIDTH) + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? FA_TAG_START_LOWER : (FA_TAG_START_LOWER + (FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)) - 1)-:(FA_TAG_START_LOWER >= FA_TAG_END_LOWER ? (FA_TAG_START_LOWER - FA_TAG_END_LOWER) + 1 : (FA_TAG_END_LOWER - FA_TAG_START_LOWER) + 1)] == ifc_fetch_addr_p1_f[FA_CMP_LOWER - 1:1]) & upper_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:750:13 + if (~hit0) begin + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:751:16 + if (offset_0) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:752:19 + hit0_index[BTB_FA_INDEX:0] = sv2v_cast_0890C_signed(i); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:754:19 + hit0 = 1'b1; + end + end + end + if (~hit1) begin + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:758:16 + if (offset_1) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:759:19 + hit1_index[BTB_FA_INDEX:0] = sv2v_cast_0890C_signed(i); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:760:19 + hit1 = 1'b1; + end + end + end + if (offset_0) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:767:15 + btb_vbank0_rd_data_f[BTB_DWIDTH - 1:0] = (fetch_mp_collision_f ? btb_wr_data : btbdata[i * BTB_DWIDTH+:BTB_DWIDTH]); + if (offset_1) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:769:15 + btb_vbank1_rd_data_f[BTB_DWIDTH - 1:0] = (fetch_mp_collision_p1_f ? btb_wr_data : btbdata[i * BTB_DWIDTH+:BTB_DWIDTH]); + if (~found1 & ((exu_mp_valid_write & ~exu_mp_pkt[32]) | dec_tlu_error_wb)) begin + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:773:16 + if (~btb_used[i]) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:774:19 + btb_fa_wr_addr0[BTB_FA_INDEX:0] = i[BTB_FA_INDEX:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:775:19 + found1 = 1'b1; + end + end + end + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:786:4 + assign vwayhit_f[1:0] = {hit1, hit0} & {eoc_mask, 1'b1}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:789:4 + assign way_raw[1:0] = vwayhit_f[1:0] | {fetch_mp_collision_p1_f, fetch_mp_collision_f}; + for (_gv_j_2 = 0; _gv_j_2 < pt[2061-:14]; _gv_j_2 = _gv_j_2 + 1) begin : BTB_FAFLOPS + localparam j = _gv_j_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:793:7 + assign wr0_en[j] = ((btb_fa_wr_addr0[BTB_FA_INDEX:0] == j) & (exu_mp_valid_write & ~exu_mp_pkt[32])) | ((dec_fa_error_index == j) & dec_tlu_error_wb); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:796:7 + rvdffe #(.WIDTH(BTB_DWIDTH)) btb_fa( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(wr0_en[j]), + .din(btb_wr_data[BTB_DWIDTH - 1:0]), + .dout(btbdata[j * BTB_DWIDTH+:BTB_DWIDTH]) + ); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:802:4 + assign ifu_bp_fa_index_f[$clog2(pt[2061-:14])+:$clog2(pt[2061-:14])] = (hit1 ? hit1_index : {$clog2(pt[2061-:14]) * 1 {1'sb0}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:803:4 + assign ifu_bp_fa_index_f[0+:$clog2(pt[2061-:14])] = (hit0 ? hit0_index : {$clog2(pt[2061-:14]) * 1 {1'sb0}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:805:4 + assign btb_used_reset = &btb_used[pt[2061-:14] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:806:4 + assign btb_used_ns[pt[2061-:14] - 1:0] = ((((({pt[2061-:14] {vwayhit_f[1]}} & (32'b00000000000000000000000000000001 << hit1_index[BTB_FA_INDEX:0])) | ({pt[2061-:14] {vwayhit_f[0]}} & (32'b00000000000000000000000000000001 << hit0_index[BTB_FA_INDEX:0]))) | ({pt[2061-:14] {(exu_mp_valid_write & ~exu_mp_pkt[32]) & ~dec_tlu_error_wb}} & (32'b00000000000000000000000000000001 << btb_fa_wr_addr0[BTB_FA_INDEX:0]))) | ({pt[2061-:14] {btb_used_reset}} & {pt[2061-:14] {1'b0}})) | ({pt[2061-:14] {~btb_used_reset & dec_tlu_error_wb}} & (btb_used[pt[2061-:14] - 1:0] & ~(32'b00000000000000000000000000000001 << dec_fa_error_index[BTB_FA_INDEX:0])))) | (~{pt[2061-:14] {btb_used_reset | dec_tlu_error_wb}} & btb_used[pt[2061-:14] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:813:4 + assign write_used = ((btb_used_reset | ifu_bp_hit_taken_f) | exu_mp_valid_write) | dec_tlu_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:816:4 + rvdffe #(.WIDTH(pt[2061-:14])) btb_usedf( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(write_used), + .din(btb_used_ns[pt[2061-:14] - 1:0]), + .dout(btb_used[pt[2061-:14] - 1:0]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:831:4 + wire [((2 * pt[2256-:15]) * 2) - 1:0] bht_bank_rd_data_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:832:4 + wire [(2 * (pt[2256-:15] / NUM_BHT_LOOP)) - 1:0] bht_bank_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:833:4 + wire [(2 * (pt[2256-:15] / NUM_BHT_LOOP)) - 1:0] bht_bank_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:836:4 + generate + for (_gv_i_7 = 0; _gv_i_7 < 2; _gv_i_7 = _gv_i_7 + 1) begin : BANKS + localparam i = _gv_i_7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:837:6 + wire [pt[2256-:15] - 1:0] wr0; + wire [pt[2256-:15] - 1:0] wr1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:838:6 + assign wr0 = bht_wr_en0[i] << bht_wr_addr0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:839:6 + assign wr1 = bht_wr_en2[i] << bht_wr_addr2; + genvar _gv_k_2; + for (_gv_k_2 = 0; _gv_k_2 < (pt[2256-:15] / NUM_BHT_LOOP); _gv_k_2 = _gv_k_2 + 1) begin : BHT_CLK_GROUP + localparam k = _gv_k_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:841:6 + assign bht_bank_clken[(i * (pt[2256-:15] / NUM_BHT_LOOP)) + k] = (bht_wr_en0[i] & ((bht_wr_addr0[pt[2270-:8]:NUM_BHT_LOOP_OUTER_LO] == k) | BHT_NO_ADDR_MATCH)) | (bht_wr_en2[i] & ((bht_wr_addr2[pt[2270-:8]:NUM_BHT_LOOP_OUTER_LO] == k) | BHT_NO_ADDR_MATCH)); + for (_gv_j_2 = 0; _gv_j_2 < NUM_BHT_LOOP; _gv_j_2 = _gv_j_2 + 1) begin : BHT_FLOPS + localparam j = _gv_j_2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:848:6 + wire [1:0] wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:849:6 + wire bank_sel = wr1[(NUM_BHT_LOOP * k) + j] | wr0[(NUM_BHT_LOOP * k) + j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:856:8 + assign wdata = (wr1[(NUM_BHT_LOOP * k) + j] ? bht_wr_data2[1:0] : bht_wr_data0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:860:11 + rvdffs_fpga #(.WIDTH(2)) bht_bank( + .rst_l(rst_l), + .clk(bht_bank_clk[(i * (pt[2256-:15] / NUM_BHT_LOOP)) + k]), + .en(bank_sel), + .rawclk(clk), + .clken(bank_sel), + .din(wdata), + .dout(bht_bank_rd_data_out[((i * pt[2256-:15]) + ((16 * k) + j)) * 2+:2]) + ); + end + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:872:5 + function automatic signed [(((pt[2270-:8] - pt[2262-:6]) + 0) >= 0 ? (pt[2270-:8] - pt[2262-:6]) + 1 : 1 - ((pt[2270-:8] - pt[2262-:6]) + 0)) - 1:0] sv2v_cast_99427_signed; + input reg signed [(((pt[2270-:8] - pt[2262-:6]) + 0) >= 0 ? (pt[2270-:8] - pt[2262-:6]) + 1 : 1 - ((pt[2270-:8] - pt[2262-:6]) + 0)) - 1:0] inp; + sv2v_cast_99427_signed = inp; + endfunction + always @(*) begin : BHT_rd_mux + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:873:6 + bht_bank0_rd_data_f[1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:874:6 + bht_bank1_rd_data_f[1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:875:6 + bht_bank0_rd_data_p1_f[1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:876:6 + begin : sv2v_autoblock_5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:876:11 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:876:11 + for (j = 0; j < pt[2256-:15]; j = j + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:877:8 + if (bht_rd_addr_f[pt[2270-:8]:pt[2262-:6]] == sv2v_cast_99427_signed(j)) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:878:10 + bht_bank0_rd_data_f[1:0] = bht_bank_rd_data_out[(0 + j) * 2+:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:879:10 + bht_bank1_rd_data_f[1:0] = bht_bank_rd_data_out[(pt[2256-:15] + j) * 2+:2]; + end + if (bht_rd_addr_p1_f[pt[2270-:8]:pt[2262-:6]] == sv2v_cast_99427_signed(j)) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:882:10 + bht_bank0_rd_data_p1_f[1:0] = bht_bank_rd_data_out[(0 + j) * 2+:2]; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_bp_ctl.sv:888:1 + initial _sv2v_0 = 0; +endmodule +module el2_ifu_ic_mem ( + clk, + active_clk, + rst_l, + clk_override, + dec_tlu_core_ecc_disable, + ic_rw_addr, + ic_wr_en, + ic_rd_en, + ic_debug_addr, + ic_debug_rd_en, + ic_debug_wr_en, + ic_debug_tag_array, + ic_debug_way, + ic_premux_data, + ic_sel_premux_data, + ic_wr_data, + ic_rd_data, + ic_debug_rd_data, + ictag_debug_rd_data, + ic_debug_wr_data, + ic_eccerr, + ic_parerr, + ic_tag_valid, + ic_data_ext_in_pkt, + ic_tag_ext_in_pkt, + ic_rd_hit, + ic_tag_perr, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:26:7 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:27:7 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:28:7 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:29:7 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:30:7 + input wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:32:7 + input wire [31:1] ic_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:33:7 + input wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:34:7 + input wire ic_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:35:7 + input wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:36:7 + input wire ic_debug_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:37:7 + input wire ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:38:7 + input wire ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:39:7 + input wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:40:7 + input wire [63:0] ic_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:41:7 + input wire ic_sel_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:43:7 + input wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:44:7 + output wire [63:0] ic_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:45:7 + output wire [70:0] ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:46:7 + output wire [25:0] ictag_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:47:7 + input wire [70:0] ic_debug_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:49:7 + output wire [pt[1189-:7] - 1:0] ic_eccerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:50:7 + output wire [pt[1189-:7] - 1:0] ic_parerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:51:7 + input wire [pt[1060-:7] - 1:0] ic_tag_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:52:7 + // removed localparam type el2_pkg_el2_ic_data_ext_in_pkt_t + input wire [((pt[1060-:7] * pt[1189-:7]) * 12) - 1:0] ic_data_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:53:7 + // removed localparam type el2_pkg_el2_ic_tag_ext_in_pkt_t + input wire [(pt[1060-:7] * 12) - 1:0] ic_tag_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:55:7 + output wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:56:7 + output wire ic_tag_perr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:57:7 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:63:4 + EL2_IC_TAG #(.pt(pt)) ic_tag_inst( + .clk(clk), + .active_clk(active_clk), + .rst_l(rst_l), + .clk_override(clk_override), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .ic_tag_valid(ic_tag_valid), + .ic_rd_en(ic_rd_en), + .ic_debug_rd_en(ic_debug_rd_en), + .ic_debug_wr_en(ic_debug_wr_en), + .ic_debug_tag_array(ic_debug_tag_array), + .ic_debug_way(ic_debug_way), + .ic_tag_ext_in_pkt(ic_tag_ext_in_pkt), + .ictag_debug_rd_data(ictag_debug_rd_data), + .ic_debug_wr_data(ic_debug_wr_data), + .ic_rd_hit(ic_rd_hit), + .ic_tag_perr(ic_tag_perr), + .scan_mode(scan_mode), + .ic_wr_en(ic_wr_en[pt[1060-:7] - 1:0]), + .ic_debug_addr(ic_debug_addr[pt[1104-:9]:3]), + .ic_rw_addr(ic_rw_addr[31:3]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:71:4 + EL2_IC_DATA #(.pt(pt)) ic_data_inst( + .clk(clk), + .active_clk(active_clk), + .rst_l(rst_l), + .clk_override(clk_override), + .ic_rd_en(ic_rd_en), + .ic_wr_data(ic_wr_data), + .ic_rd_data(ic_rd_data), + .ic_debug_wr_data(ic_debug_wr_data), + .ic_debug_rd_data(ic_debug_rd_data), + .ic_parerr(ic_parerr), + .ic_eccerr(ic_eccerr), + .ic_debug_rd_en(ic_debug_rd_en), + .ic_debug_wr_en(ic_debug_wr_en), + .ic_debug_tag_array(ic_debug_tag_array), + .ic_debug_way(ic_debug_way), + .ic_premux_data(ic_premux_data), + .ic_sel_premux_data(ic_sel_premux_data), + .ic_rd_hit(ic_rd_hit), + .ic_data_ext_in_pkt(ic_data_ext_in_pkt), + .scan_mode(scan_mode), + .ic_wr_en(ic_wr_en[pt[1060-:7] - 1:0]), + .ic_debug_addr(ic_debug_addr[pt[1104-:9]:3]), + .ic_rw_addr(ic_rw_addr[31:1]) + ); +endmodule +module EL2_IC_DATA ( + clk, + active_clk, + rst_l, + clk_override, + ic_rw_addr, + ic_wr_en, + ic_rd_en, + ic_wr_data, + ic_rd_data, + ic_debug_wr_data, + ic_debug_rd_data, + ic_parerr, + ic_eccerr, + ic_debug_addr, + ic_debug_rd_en, + ic_debug_wr_en, + ic_debug_tag_array, + ic_debug_way, + ic_premux_data, + ic_sel_premux_data, + ic_rd_hit, + ic_data_ext_in_pkt, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:91:7 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:92:7 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:93:7 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:94:7 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:96:7 + input wire [31:1] ic_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:97:7 + input wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:98:7 + input wire ic_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:100:7 + input wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:101:7 + output reg [63:0] ic_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:102:7 + input wire [70:0] ic_debug_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:103:7 + output reg [70:0] ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:104:7 + output wire [pt[1189-:7] - 1:0] ic_parerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:105:7 + output wire [pt[1189-:7] - 1:0] ic_eccerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:106:7 + input wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:107:7 + input wire ic_debug_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:108:7 + input wire ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:109:7 + input wire ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:110:7 + input wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:111:7 + input wire [63:0] ic_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:112:7 + input wire ic_sel_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:114:7 + input wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:115:7 + // removed localparam type el2_pkg_el2_ic_data_ext_in_pkt_t + input wire [((pt[1060-:7] * pt[1189-:7]) * 12) - 1:0] ic_data_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:116:7 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:120:4 + wire [pt[998-:7] - 1:1] ic_rw_addr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:121:4 + reg [(pt[1189-:7] * pt[1060-:7]) - 1:0] ic_b_sb_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:122:4 + reg [(pt[1189-:7] * pt[1060-:7]) - 1:0] ic_b_sb_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:125:4 + reg [pt[1189-:7] - 1:0] ic_b_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:126:4 + wire [pt[1189-:7] - 1:0] ic_b_rden_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:127:4 + reg [pt[1189-:7] - 1:0] ic_debug_sel_sb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:129:4 + reg [((pt[1060-:7] * pt[1189-:7]) * 71) - 1:0] wb_dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:130:4 + reg [(pt[1189-:7] * 71) - 1:0] ic_sb_wr_data; + wire [(pt[1189-:7] * 71) - 1:0] ic_bank_wr_data; + wire [(pt[1189-:7] * 71) - 1:0] wb_dout_ecc_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:131:4 + reg [(pt[1060-:7] * 142) - 1:0] wb_dout_way_pre; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:132:4 + wire [(pt[1060-:7] * 64) - 1:0] wb_dout_way; + wire [(pt[1060-:7] * 64) - 1:0] wb_dout_way_with_premux; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:133:4 + reg [141:0] wb_dout_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:135:4 + wire [pt[1189-:7] - 1:0] bank_check_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:137:4 + reg [(pt[1189-:7] * pt[1060-:7]) - 1:0] ic_bank_way_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:138:4 + wire [pt[1189-:7] - 1:0] ic_bank_way_clken_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:139:4 + wire [(pt[1060-:7] * pt[1189-:7]) - 1:0] ic_bank_way_clken_final_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:141:4 + wire [pt[1060-:7] - 1:0] ic_debug_rd_way_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:142:4 + wire [pt[1060-:7] - 1:0] ic_debug_rd_way_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:143:4 + wire [pt[1060-:7] - 1:0] ic_debug_wr_way_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:144:4 + wire [pt[1104-:9]:1] ic_rw_addr_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:146:4 + wire [(pt[1104-:9] >= pt[1143-:7] ? (pt[1189-:7] * ((pt[1104-:9] - pt[1143-:7]) + 1)) + (pt[1143-:7] - 1) : (pt[1189-:7] * ((pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] - 1)):(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] + 0 : pt[1104-:9] + 0)] ic_rw_addr_bank_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:148:4 + wire [pt[991-:9] - 1:pt[1143-:7]] ic_rw_addr_q_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:149:4 + wire [pt[1060-:7] - 1:0] ic_rd_hit_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:153:7 + wire [pt[1189-:7] - 1:0] ic_b_sram_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:154:7 + wire [pt[1189-:7] - 1:0] ic_b_read_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:155:7 + wire [pt[1189-:7] - 1:0] ic_b_write_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:156:7 + wire [(31 >= pt[1143-:7] ? ((pt[1189-:7] * pt[1076-:8]) * (32 - pt[1143-:7])) + (pt[1143-:7] - 1) : ((pt[1189-:7] * pt[1076-:8]) * (pt[1143-:7] - 30)) + 30):(31 >= pt[1143-:7] ? pt[1143-:7] + 0 : 31)] wb_index_hold; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:157:7 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] write_bypass_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:158:7 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] write_bypass_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:159:7 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] index_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:160:7 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] ic_b_clear_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:161:7 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] ic_b_addr_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:162:7 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] ic_b_addr_match_index_only; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:164:7 + wire [(pt[1060-:7] * pt[1189-:7]) - 1:0] ic_b_sram_en_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:165:7 + wire [(pt[1060-:7] * pt[1189-:7]) - 1:0] ic_b_read_en_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:166:7 + wire [(pt[1060-:7] * pt[1189-:7]) - 1:0] ic_b_write_en_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:167:7 + wire [(31 >= pt[1143-:7] ? (((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) * (32 - pt[1143-:7])) + (pt[1143-:7] - 1) : (((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) * (pt[1143-:7] - 30)) + 30):(31 >= pt[1143-:7] ? pt[1143-:7] + 0 : 31)] wb_index_hold_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:168:7 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] write_bypass_en_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:169:7 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] write_bypass_en_ff_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:170:7 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] index_valid_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:171:7 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] ic_b_clear_en_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:172:7 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] ic_b_addr_match_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:173:7 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] ic_b_addr_match_index_only_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:176:4 + wire [(31 >= pt[1143-:7] ? (pt[1189-:7] * (32 - pt[1143-:7])) + (pt[1143-:7] - 1) : (pt[1189-:7] * (pt[1143-:7] - 30)) + 30):(31 >= pt[1143-:7] ? pt[1143-:7] + 0 : 31)] ic_b_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:177:4 + wire [(31 >= pt[1143-:7] ? (pt[1189-:7] * (32 - pt[1143-:7])) + (pt[1143-:7] - 1) : (pt[1189-:7] * (pt[1143-:7] - 30)) + 30):(31 >= pt[1143-:7] ? pt[1143-:7] + 0 : 31)] ic_b_rw_addr_index_only; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:179:4 + wire [(31 >= pt[1143-:7] ? ((pt[1060-:7] * pt[1189-:7]) * (32 - pt[1143-:7])) + (pt[1143-:7] - 1) : ((pt[1060-:7] * pt[1189-:7]) * (pt[1143-:7] - 30)) + 30):(31 >= pt[1143-:7] ? pt[1143-:7] + 0 : 31)] ic_b_rw_addr_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:180:4 + wire [(31 >= pt[1143-:7] ? ((pt[1060-:7] * pt[1189-:7]) * (32 - pt[1143-:7])) + (pt[1143-:7] - 1) : ((pt[1060-:7] * pt[1189-:7]) * (pt[1143-:7] - 30)) + 30):(31 >= pt[1143-:7] ? pt[1143-:7] + 0 : 31)] ic_b_rw_addr_index_only_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:184:4 + wire ic_rd_en_with_debug; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:185:4 + wire ic_rw_addr_wrap; + wire ic_cacheline_wrap_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:186:4 + wire ic_debug_rd_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:192:4 + assign ic_debug_rd_way_en[pt[1060-:7] - 1:0] = {pt[1060-:7] {ic_debug_rd_en & ~ic_debug_tag_array}} & ic_debug_way[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:193:4 + assign ic_debug_wr_way_en[pt[1060-:7] - 1:0] = {pt[1060-:7] {ic_debug_wr_en & ~ic_debug_tag_array}} & ic_debug_way[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:195:4 + wire end_of_cache_line; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:196:4 + assign end_of_cache_line = (pt[1095-:11] == 7'h40 ? &ic_rw_addr_q[5:4] : ic_rw_addr_q[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:197:4 + always @(*) begin : clkens + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:198:7 + ic_bank_way_clken = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:200:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:200:13 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:200:13 + for (i = 0; i < pt[1189-:7]; i = i + 1) + begin : wr_ens + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:201:8 + ic_b_sb_wren[i * pt[1060-:7]+:pt[1060-:7]] = ic_wr_en[pt[1060-:7] - 1:0] | (ic_debug_wr_way_en[pt[1060-:7] - 1:0] & {pt[1060-:7] {ic_debug_addr[pt[1210-:7]:pt[1203-:6]] == i}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:203:8 + ic_debug_sel_sb[i] = ic_debug_addr[pt[1210-:7]:pt[1203-:6]] == i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:204:8 + ic_sb_wr_data[i * 71+:71] = (ic_debug_sel_sb[i] & ic_debug_wr_en ? ic_debug_wr_data : ic_bank_wr_data[i * 71+:71]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:205:8 + ic_b_rden[i] = ic_rd_en_with_debug & ((((~ic_rw_addr_q[pt[1210-:7]] & (i == 0)) | (((ic_rw_addr_q[pt[1210-:7]] & (ic_rw_addr_q[2:1] == 2'b11)) & (i == 0)) & ~end_of_cache_line)) | (ic_rw_addr_q[pt[1210-:7]] & (i == 1))) | ((~ic_rw_addr_q[pt[1210-:7]] & (ic_rw_addr_q[2:1] == 2'b11)) & (i == 1))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:212:8 + ic_b_sb_rden[i * pt[1060-:7]+:pt[1060-:7]] = {pt[1060-:7] {ic_b_rden[i]}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:214:8 + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:214:14 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:214:14 + for (j = 0; j < pt[1060-:7]; j = j + 1) + begin : way_clkens + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:215:10 + ic_bank_way_clken[(i * pt[1060-:7]) + j] = ic_bank_way_clken[(i * pt[1060-:7]) + j] | ((ic_b_sb_rden[(i * pt[1060-:7]) + j] | clk_override) | ic_b_sb_wren[(i * pt[1060-:7]) + j]); + end + end + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:221:3 + assign ic_rd_en_with_debug = (ic_rd_en | ic_debug_rd_en) & ~(|ic_wr_en); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:222:3 + assign ic_rw_addr_q[pt[1104-:9]:1] = (ic_debug_rd_en | ic_debug_wr_en ? {ic_debug_addr[pt[1104-:9]:3], 2'b00} : ic_rw_addr[pt[1104-:9]:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:226:4 + assign ic_rw_addr_q_inc[pt[991-:9] - 1:pt[1143-:7]] = ic_rw_addr_q[pt[991-:9] - 1:pt[1143-:7]] + 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:227:4 + assign ic_rw_addr_wrap = ((ic_rw_addr_q[pt[1210-:7]] & (ic_rw_addr_q[2:1] == 2'b11)) & ic_rd_en_with_debug) & ~(|ic_wr_en[pt[1060-:7] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:228:4 + assign ic_cacheline_wrap_ff = ic_rw_addr_ff[pt[998-:7] - 1:pt[1203-:6]] == {pt[998-:7] - pt[1203-:6] {1'b1}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:231:4 + assign ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + 0+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] = (~ic_rw_addr_wrap ? ic_rw_addr_q[pt[1104-:9]:pt[1143-:7]] : {ic_rw_addr_q[pt[1104-:9]:pt[998-:7]], ic_rw_addr_q_inc[pt[998-:7] - 1:pt[1143-:7]]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:232:4 + assign ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] = ic_rw_addr_q[pt[1104-:9]:pt[1143-:7]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:235:4 + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + rvdffie #( + .WIDTH(sv2v_cast_32_signed((pt[998-:7] + pt[1189-:7]) + pt[1060-:7])), + .OVERRIDE(1) + ) miscff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({ic_b_rden[pt[1189-:7] - 1:0], ic_rw_addr_q[pt[998-:7] - 1:1], ic_debug_rd_way_en[pt[1060-:7] - 1:0], ic_debug_rd_en}), + .dout({ic_b_rden_ff[pt[1189-:7] - 1:0], ic_rw_addr_ff[pt[998-:7] - 1:1], ic_debug_rd_way_en_ff[pt[1060-:7] - 1:0], ic_debug_rd_en_ff}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:241:2 + generate + if (pt[966-:5] == 0) begin : PACKED_0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:244:5 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1068-:8]) - 1:0] wrptr_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:245:5 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1068-:8]) - 1:0] wrptr_in_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:246:5 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] sel_bypass_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:247:5 + wire [((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) - 1:0] sel_bypass_ff_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:248:5 + reg [((pt[1060-:7] * pt[1189-:7]) * (71 * pt[1060-:7])) - 1:0] sel_bypass_data_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:249:5 + reg [(pt[1060-:7] * pt[1189-:7]) - 1:0] any_bypass_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:250:5 + reg [(pt[1060-:7] * pt[1189-:7]) - 1:0] any_addr_match_up; + genvar _gv_i_8; + for (_gv_i_8 = 0; _gv_i_8 < pt[1060-:7]; _gv_i_8 = _gv_i_8 + 1) begin : WAYS + localparam i = _gv_i_8; + genvar _gv_k_3; + for (_gv_k_3 = 0; _gv_k_3 < pt[1189-:7]; _gv_k_3 = _gv_k_3 + 1) begin : BANKS_WAY + localparam k = _gv_k_3; + if (pt[1125-:5]) begin : ECC1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:325:9 + wire [((pt[1060-:7] * pt[1189-:7]) * 71) - 1:0] wb_dout_pre_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:326:9 + wire [(((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) * 71) - 1:0] wb_dout_hold_up; + if ($clog2(pt[1161-:18]) == 13) begin : size_8192 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:33 + ram_8192x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3619 + begin : sv2v_autoblock_3 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_2; + for (_gv_l_2 = 0; _gv_l_2 < pt[1076-:8]; _gv_l_2 = _gv_l_2 + 1) begin : BYPASS + localparam l = _gv_l_2; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:6475 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:7222 + begin : sv2v_autoblock_4 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:329:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 12) begin : size_4096 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:33 + ram_4096x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3619 + begin : sv2v_autoblock_5 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_3; + for (_gv_l_3 = 0; _gv_l_3 < pt[1076-:8]; _gv_l_3 = _gv_l_3 + 1) begin : BYPASS + localparam l = _gv_l_3; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:6475 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:7222 + begin : sv2v_autoblock_6 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:332:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 11) begin : size_2048 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:33 + ram_2048x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3619 + begin : sv2v_autoblock_7 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_4; + for (_gv_l_4 = 0; _gv_l_4 < pt[1076-:8]; _gv_l_4 = _gv_l_4 + 1) begin : BYPASS + localparam l = _gv_l_4; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:6475 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:7222 + begin : sv2v_autoblock_8 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:335:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 10) begin : size_1024 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:33 + ram_1024x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3619 + begin : sv2v_autoblock_9 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_5; + for (_gv_l_5 = 0; _gv_l_5 < pt[1076-:8]; _gv_l_5 = _gv_l_5 + 1) begin : BYPASS + localparam l = _gv_l_5; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:6475 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:7222 + begin : sv2v_autoblock_10 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:338:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 9) begin : size_512 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:32 + ram_512x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:2362 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:2519 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:2695 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:2810 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:2925 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3040 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3155 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3270 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3385 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3503 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3618 + begin : sv2v_autoblock_11 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3623 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3623 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:3736 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_6; + for (_gv_l_6 = 0; _gv_l_6 < pt[1076-:8]; _gv_l_6 = _gv_l_6 + 1) begin : BYPASS + localparam l = _gv_l_6; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:4229 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:4378 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:4742 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:5051 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:5349 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:5647 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:5859 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:6070 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:6281 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:6474 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:6803 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:6943 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:7082 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:7221 + begin : sv2v_autoblock_12 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:7226 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:7226 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:7363 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:7502 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:7777 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:8333 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:341:8472 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 8) begin : size_256 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:32 + ram_256x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:2362 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:2519 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:2695 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:2810 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:2925 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3040 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3155 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3270 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3385 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3503 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3618 + begin : sv2v_autoblock_13 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3623 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3623 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:3736 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_7; + for (_gv_l_7 = 0; _gv_l_7 < pt[1076-:8]; _gv_l_7 = _gv_l_7 + 1) begin : BYPASS + localparam l = _gv_l_7; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:4229 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:4378 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:4742 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:5051 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:5349 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:5647 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:5859 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:6070 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:6281 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:6474 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:6803 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:6943 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:7082 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:7221 + begin : sv2v_autoblock_14 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:7226 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:7226 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:7363 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:7502 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:7777 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:8333 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:344:8472 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 7) begin : size_128 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:32 + ram_128x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:2362 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:2519 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:2695 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:2810 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:2925 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3040 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3155 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3270 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3385 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3503 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3618 + begin : sv2v_autoblock_15 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3623 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3623 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:3736 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_8; + for (_gv_l_8 = 0; _gv_l_8 < pt[1076-:8]; _gv_l_8 = _gv_l_8 + 1) begin : BYPASS + localparam l = _gv_l_8; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:4229 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:4378 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:4742 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:5051 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:5349 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:5647 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:5859 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:6070 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:6281 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:6474 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:6803 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:6943 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:7082 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:7221 + begin : sv2v_autoblock_16 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:7226 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:7226 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:7363 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:7502 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:7777 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:8333 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:347:8472 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else begin : size_64 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:31 + ram_64x71 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 70-:71]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:2361 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:2518 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:2694 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:2809 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:2924 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3039 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3154 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3269 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3384 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3502 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3617 + begin : sv2v_autoblock_17 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3622 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3622 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:3735 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_9; + for (_gv_l_9 = 0; _gv_l_9 < pt[1076-:8]; _gv_l_9 = _gv_l_9 + 1) begin : BYPASS + localparam l = _gv_l_9; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:4228 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:4377 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:4741 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:5050 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:5348 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:5646 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:5858 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:6069 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:6280 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:6473 + rvdffe #(.WIDTH(71)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:6802 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:6942 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:7081 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:7220 + begin : sv2v_autoblock_18 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:7225 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:7225 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:7362 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:7501 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 71+:71] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:7776 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:8332 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 71+:71]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:350:8471 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + end + else begin : ECC0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:355:9 + wire [((pt[1060-:7] * pt[1189-:7]) * 68) - 1:0] wb_dout_pre_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:356:9 + wire [(((pt[1060-:7] * pt[1189-:7]) * pt[1076-:8]) * 68) - 1:0] wb_dout_hold_up; + if ($clog2(pt[1161-:18]) == 13) begin : size_8192 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:33 + ram_8192x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3619 + begin : sv2v_autoblock_19 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_10; + for (_gv_l_10 = 0; _gv_l_10 < pt[1076-:8]; _gv_l_10 = _gv_l_10 + 1) begin : BYPASS + localparam l = _gv_l_10; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:6475 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:7222 + begin : sv2v_autoblock_20 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:358:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 12) begin : size_4096 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:33 + ram_4096x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3619 + begin : sv2v_autoblock_21 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_11; + for (_gv_l_11 = 0; _gv_l_11 < pt[1076-:8]; _gv_l_11 = _gv_l_11 + 1) begin : BYPASS + localparam l = _gv_l_11; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:6475 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:7222 + begin : sv2v_autoblock_22 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:361:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 11) begin : size_2048 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:33 + ram_2048x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3619 + begin : sv2v_autoblock_23 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_12; + for (_gv_l_12 = 0; _gv_l_12 < pt[1076-:8]; _gv_l_12 = _gv_l_12 + 1) begin : BYPASS + localparam l = _gv_l_12; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:6475 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:7222 + begin : sv2v_autoblock_24 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:364:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 10) begin : size_1024 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:33 + ram_1024x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:2363 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:2520 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:2696 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:2811 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:2926 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3041 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3156 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3271 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3386 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3504 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3619 + begin : sv2v_autoblock_25 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3624 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3624 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:3737 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_13; + for (_gv_l_13 = 0; _gv_l_13 < pt[1076-:8]; _gv_l_13 = _gv_l_13 + 1) begin : BYPASS + localparam l = _gv_l_13; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:4230 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:4379 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:4743 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:5052 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:5350 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:5648 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:5860 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:6071 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:6282 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:6475 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:6804 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:6944 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:7083 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:7222 + begin : sv2v_autoblock_26 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:7227 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:7227 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:7364 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:7503 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:7778 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:8334 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:367:8473 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 9) begin : size_512 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:32 + ram_512x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:2362 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:2519 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:2695 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:2810 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:2925 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3040 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3155 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3270 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3385 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3503 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3618 + begin : sv2v_autoblock_27 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3623 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3623 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:3736 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_14; + for (_gv_l_14 = 0; _gv_l_14 < pt[1076-:8]; _gv_l_14 = _gv_l_14 + 1) begin : BYPASS + localparam l = _gv_l_14; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:4229 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:4378 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:4742 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:5051 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:5349 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:5647 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:5859 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:6070 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:6281 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:6474 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:6803 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:6943 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:7082 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:7221 + begin : sv2v_autoblock_28 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:7226 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:7226 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:7363 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:7502 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:7777 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:8333 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:370:8472 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 8) begin : size_256 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:32 + ram_256x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:2362 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:2519 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:2695 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:2810 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:2925 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3040 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3155 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3270 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3385 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3503 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3618 + begin : sv2v_autoblock_29 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3623 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3623 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:3736 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_15; + for (_gv_l_15 = 0; _gv_l_15 < pt[1076-:8]; _gv_l_15 = _gv_l_15 + 1) begin : BYPASS + localparam l = _gv_l_15; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:4229 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:4378 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:4742 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:5051 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:5349 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:5647 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:5859 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:6070 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:6281 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:6474 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:6803 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:6943 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:7082 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:7221 + begin : sv2v_autoblock_30 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:7226 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:7226 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:7363 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:7502 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:7777 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:8333 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:373:8472 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else if ($clog2(pt[1161-:18]) == 7) begin : size_128 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:32 + ram_128x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:2362 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:2519 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:2695 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:2810 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:2925 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3040 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3155 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3270 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3385 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3503 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3618 + begin : sv2v_autoblock_31 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3623 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3623 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:3736 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_16; + for (_gv_l_16 = 0; _gv_l_16 < pt[1076-:8]; _gv_l_16 = _gv_l_16 + 1) begin : BYPASS + localparam l = _gv_l_16; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:4229 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:4378 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:4742 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:5051 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:5349 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:5647 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:5859 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:6070 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:6281 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:6474 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:6803 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:6943 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:7082 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:7221 + begin : sv2v_autoblock_32 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:7226 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:7226 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:7363 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:7502 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:7777 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:8333 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:376:8472 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + else begin : size_64 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:31 + ram_64x68 ic_bank_sb_way_data( + .ME(ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k]), + .WE(ic_b_sb_wren[(k * pt[1060-:7]) + i]), + .D(ic_sb_wr_data[(k * 71) + 67-:68]), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .CLK(clk), + .ROP(), + .TEST1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[(((i * pt[1189-:7]) + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[((i * pt[1189-:7]) + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:2361 + assign wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] = (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] {1'sb0}} : wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:2518 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:2694 + assign ic_b_sram_en_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:2809 + assign ic_b_read_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_rden[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:2924 + assign ic_b_write_en_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ic_b_sb_wren[(k * pt[1060-:7]) + i]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3039 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_b_sram_en_up[(i * pt[1189-:7]) + k] & ~(|sel_bypass_up[((i * pt[1189-:7]) + k) * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3154 + assign ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3269 + assign ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3384 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3502 + any_addr_match_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3617 + begin : sv2v_autoblock_33 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3622 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3622 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:3735 + any_addr_match_up[(i * pt[1189-:7]) + k] = any_addr_match_up[(i * pt[1189-:7]) + k] | ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_17; + for (_gv_l_17 = 0; _gv_l_17 < pt[1076-:8]; _gv_l_17 = _gv_l_17 + 1) begin : BYPASS + localparam l = _gv_l_17; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:4228 + assign ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:4377 + assign ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (wb_index_hold_up[(31 >= pt[1143-:7] ? (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:4741 + assign ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_write_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_index_only_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:5050 + assign sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = ic_b_read_en_up[(i * pt[1189-:7]) + k] & ic_b_addr_match_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:5348 + assign write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] = (ic_b_read_en_up[(i * pt[1189-:7]) + k] & ~any_addr_match_up[(i * pt[1189-:7]) + k]) & (wrptr_up[((i * pt[1189-:7]) + k) * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:5646 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:5858 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] | ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(~ic_b_clear_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(index_valid_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:6069 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .dout(sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:6280 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(ic_b_rw_addr_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((i * pt[1189-:7]) + k) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold_up[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:6473 + rvdffe #(.WIDTH(68)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]), + .din(wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]), + .dout(wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68]) + ); + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:6802 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:6942 + any_bypass_up[(i * pt[1189-:7]) + k] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:7081 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:7220 + begin : sv2v_autoblock_34 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:7225 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:7225 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:7362 + any_bypass_up[(i * pt[1189-:7]) + k] = any_bypass_up[(i * pt[1189-:7]) + k] | sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:7501 + sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff_up[(((i * pt[1189-:7]) + k) * pt[1076-:8]) + l] ? wb_dout_hold_up[((((i * pt[1189-:7]) + k) * pt[1076-:8]) + l) * 68+:68] : {71 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:7776 + wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = (any_bypass_up[(i * pt[1189-:7]) + k] ? sel_bypass_data_up[((i * pt[1189-:7]) + k) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:8332 + wire [71:1] sv2v_tmp_BE754; + assign sv2v_tmp_BE754 = wb_dout_pre_up[((i * pt[1189-:7]) + k) * 68+:68]; + always @(*) wb_dout[((i * pt[1189-:7]) + k) * 71+:71] = sv2v_tmp_BE754; + // Trace: macro expansion of EL2_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:379:8471 + assign ic_bank_way_clken_final_up[(i * pt[1189-:7]) + k] = ic_bank_way_clken[(k * pt[1060-:7]) + i]; + end + end + end + end + end + end + else begin : PACKED_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:390:5 + wire [(pt[1189-:7] * pt[1068-:8]) - 1:0] wrptr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:391:5 + wire [(pt[1189-:7] * pt[1068-:8]) - 1:0] wrptr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:392:5 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] sel_bypass; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:393:5 + wire [(pt[1189-:7] * pt[1076-:8]) - 1:0] sel_bypass_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:396:5 + reg [(pt[1189-:7] * (71 * pt[1060-:7])) - 1:0] sel_bypass_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:397:5 + reg [pt[1189-:7] - 1:0] any_bypass; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:398:5 + reg [pt[1189-:7] - 1:0] any_addr_match; + genvar _gv_k_4; + for (_gv_k_4 = 0; _gv_k_4 < pt[1189-:7]; _gv_k_4 = _gv_k_4 + 1) begin : BANKS_WAY + localparam k = _gv_k_4; + if (pt[1125-:5]) begin : ECC1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:493:9 + reg [(pt[1189-:7] * (71 * pt[1060-:7])) - 1:0] wb_packeddout; + wire [(pt[1189-:7] * (71 * pt[1060-:7])) - 1:0] ic_b_sb_bit_en_vec; + wire [(pt[1189-:7] * (71 * pt[1060-:7])) - 1:0] wb_packeddout_pre; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:495:9 + wire [((pt[1189-:7] * pt[1076-:8]) * (71 * pt[1060-:7])) - 1:0] wb_packeddout_hold; + genvar _gv_i_9; + for (_gv_i_9 = 0; _gv_i_9 < pt[1060-:7]; _gv_i_9 = _gv_i_9 + 1) begin : BITEN + localparam i = _gv_i_9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:498:12 + assign ic_b_sb_bit_en_vec[(k * (71 * pt[1060-:7])) + (((71 * i) + 70) >= (71 * i) ? (71 * i) + 70 : (((71 * i) + 70) + (((71 * i) + 70) >= (71 * i) ? (((71 * i) + 70) - (71 * i)) + 1 : ((71 * i) - ((71 * i) + 70)) + 1)) - 1)-:(((71 * i) + 70) >= (71 * i) ? (((71 * i) + 70) - (71 * i)) + 1 : ((71 * i) - ((71 * i) + 70)) + 1)] = {71 {ic_b_sb_wren[(k * pt[1060-:7]) + i]}}; + end + if ($clog2(pt[1161-:18]) == 13) begin : size_8192 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:41 + ram_be_8192x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:7072 + begin : sv2v_autoblock_35 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_18; + for (_gv_l_18 = 0; _gv_l_18 < pt[1076-:8]; _gv_l_18 = _gv_l_18 + 1) begin : BYPASS + localparam l = _gv_l_18; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:12771 + begin : sv2v_autoblock_36 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:504:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:41 + ram_be_8192x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:7072 + begin : sv2v_autoblock_37 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_19; + for (_gv_l_19 = 0; _gv_l_19 < pt[1076-:8]; _gv_l_19 = _gv_l_19 + 1) begin : BYPASS + localparam l = _gv_l_19; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:12771 + begin : sv2v_autoblock_38 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:507:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 12) begin : size_4096 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:41 + ram_be_4096x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:7072 + begin : sv2v_autoblock_39 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_20; + for (_gv_l_20 = 0; _gv_l_20 < pt[1076-:8]; _gv_l_20 = _gv_l_20 + 1) begin : BYPASS + localparam l = _gv_l_20; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:12771 + begin : sv2v_autoblock_40 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:513:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:41 + ram_be_4096x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:7072 + begin : sv2v_autoblock_41 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_21; + for (_gv_l_21 = 0; _gv_l_21 < pt[1076-:8]; _gv_l_21 = _gv_l_21 + 1) begin : BYPASS + localparam l = _gv_l_21; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:12771 + begin : sv2v_autoblock_42 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:516:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 11) begin : size_2048 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:41 + ram_be_2048x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:7072 + begin : sv2v_autoblock_43 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_22; + for (_gv_l_22 = 0; _gv_l_22 < pt[1076-:8]; _gv_l_22 = _gv_l_22 + 1) begin : BYPASS + localparam l = _gv_l_22; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:12771 + begin : sv2v_autoblock_44 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:522:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:41 + ram_be_2048x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:7072 + begin : sv2v_autoblock_45 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_23; + for (_gv_l_23 = 0; _gv_l_23 < pt[1076-:8]; _gv_l_23 = _gv_l_23 + 1) begin : BYPASS + localparam l = _gv_l_23; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:12771 + begin : sv2v_autoblock_46 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:525:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 10) begin : size_1024 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:41 + ram_be_1024x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:7072 + begin : sv2v_autoblock_47 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_24; + for (_gv_l_24 = 0; _gv_l_24 < pt[1076-:8]; _gv_l_24 = _gv_l_24 + 1) begin : BYPASS + localparam l = _gv_l_24; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:12771 + begin : sv2v_autoblock_48 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:531:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:41 + ram_be_1024x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:7072 + begin : sv2v_autoblock_49 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_25; + for (_gv_l_25 = 0; _gv_l_25 < pt[1076-:8]; _gv_l_25 = _gv_l_25 + 1) begin : BYPASS + localparam l = _gv_l_25; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:11351 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:12771 + begin : sv2v_autoblock_50 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:13768 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:14402 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:534:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 9) begin : size_512 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:40 + ram_be_512x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:7071 + begin : sv2v_autoblock_51 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_26; + for (_gv_l_26 = 0; _gv_l_26 < pt[1076-:8]; _gv_l_26 = _gv_l_26 + 1) begin : BYPASS + localparam l = _gv_l_26; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:11350 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:12770 + begin : sv2v_autoblock_52 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:13767 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:14401 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:540:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:40 + ram_be_512x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:7071 + begin : sv2v_autoblock_53 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_27; + for (_gv_l_27 = 0; _gv_l_27 < pt[1076-:8]; _gv_l_27 = _gv_l_27 + 1) begin : BYPASS + localparam l = _gv_l_27; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:11350 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:12770 + begin : sv2v_autoblock_54 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:13767 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:14401 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:543:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 8) begin : size_256 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:40 + ram_be_256x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:7071 + begin : sv2v_autoblock_55 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_28; + for (_gv_l_28 = 0; _gv_l_28 < pt[1076-:8]; _gv_l_28 = _gv_l_28 + 1) begin : BYPASS + localparam l = _gv_l_28; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:11350 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:12770 + begin : sv2v_autoblock_56 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:13767 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:14401 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:549:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:40 + ram_be_256x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:7071 + begin : sv2v_autoblock_57 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_29; + for (_gv_l_29 = 0; _gv_l_29 < pt[1076-:8]; _gv_l_29 = _gv_l_29 + 1) begin : BYPASS + localparam l = _gv_l_29; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:11350 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:12770 + begin : sv2v_autoblock_58 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:13767 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:14401 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:552:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 7) begin : size_128 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:40 + ram_be_128x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:7071 + begin : sv2v_autoblock_59 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_30; + for (_gv_l_30 = 0; _gv_l_30 < pt[1076-:8]; _gv_l_30 = _gv_l_30 + 1) begin : BYPASS + localparam l = _gv_l_30; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:11350 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:12770 + begin : sv2v_autoblock_60 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:13767 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:14401 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:558:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:40 + ram_be_128x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:7071 + begin : sv2v_autoblock_61 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_31; + for (_gv_l_31 = 0; _gv_l_31 < pt[1076-:8]; _gv_l_31 = _gv_l_31 + 1) begin : BYPASS + localparam l = _gv_l_31; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:11350 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:12770 + begin : sv2v_autoblock_62 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:13767 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:14401 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:561:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else begin : size_64 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:39 + ram_be_64x284 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:3676 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:4074 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:4496 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:5093 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:5300 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:5499 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:5897 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:6096 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:6470 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:6672 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:7070 + begin : sv2v_autoblock_63 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:7075 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:7075 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:7272 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_32; + for (_gv_l_32 = 0; _gv_l_32 < pt[1076-:8]; _gv_l_32 = _gv_l_32 + 1) begin : BYPASS + localparam l = _gv_l_32; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:8499 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:8698 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:9096 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:9510 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:9908 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:10306 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:10521 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:10736 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:11150 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:11349 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:11972 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:12172 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:12371 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:12769 + begin : sv2v_autoblock_64 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:12774 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:12774 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:12971 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:13172 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:13766 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:14400 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:567:14599 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:39 + ram_be_64x142 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 70-:71]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:3676 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:4074 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:4496 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:5093 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:5300 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:5499 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:5897 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:6096 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:6470 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:6672 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:7070 + begin : sv2v_autoblock_65 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:7075 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:7075 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:7272 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_33; + for (_gv_l_33 = 0; _gv_l_33 < pt[1076-:8]; _gv_l_33 = _gv_l_33 + 1) begin : BYPASS + localparam l = _gv_l_33; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:8499 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:8698 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:9096 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:9510 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:9908 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:10306 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:10521 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:10736 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:11150 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:11349 + rvdffe #(.WIDTH(71 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:11972 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:12172 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:12371 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:12769 + begin : sv2v_autoblock_66 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:12774 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:12774 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:12971 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:13172 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:13766 + wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:14400 + wire [(71 * pt[1060-:7]) * 1:1] sv2v_tmp_57695; + assign sv2v_tmp_57695 = wb_packeddout_pre[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sv2v_tmp_57695; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:570:14599 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + genvar _gv_i_10; + for (_gv_i_10 = 0; _gv_i_10 < pt[1060-:7]; _gv_i_10 = _gv_i_10 + 1) begin : WAYS + localparam i = _gv_i_10; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:576:11 + wire [71:1] sv2v_tmp_7F04A; + assign sv2v_tmp_7F04A = wb_packeddout[(k * (71 * pt[1060-:7])) + (((71 * i) + 70) >= (71 * i) ? (71 * i) + 70 : (((71 * i) + 70) + (((71 * i) + 70) >= (71 * i) ? (((71 * i) + 70) - (71 * i)) + 1 : ((71 * i) - ((71 * i) + 70)) + 1)) - 1)-:(((71 * i) + 70) >= (71 * i) ? (((71 * i) + 70) - (71 * i)) + 1 : ((71 * i) - ((71 * i) + 70)) + 1)]; + always @(*) wb_dout[(((i * pt[1189-:7]) + k) * 71) + 70-:71] = sv2v_tmp_7F04A; + end + end + else begin : ECC0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:583:9 + reg [(pt[1189-:7] * (68 * pt[1060-:7])) - 1:0] wb_packeddout; + wire [(pt[1189-:7] * (68 * pt[1060-:7])) - 1:0] ic_b_sb_bit_en_vec; + wire [(pt[1189-:7] * (68 * pt[1060-:7])) - 1:0] wb_packeddout_pre; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:585:9 + wire [((pt[1189-:7] * pt[1076-:8]) * (68 * pt[1060-:7])) - 1:0] wb_packeddout_hold; + genvar _gv_i_11; + for (_gv_i_11 = 0; _gv_i_11 < pt[1060-:7]; _gv_i_11 = _gv_i_11 + 1) begin : BITEN + localparam i = _gv_i_11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:588:12 + assign ic_b_sb_bit_en_vec[(k * (68 * pt[1060-:7])) + (((68 * i) + 67) >= (68 * i) ? (68 * i) + 67 : (((68 * i) + 67) + (((68 * i) + 67) >= (68 * i) ? (((68 * i) + 67) - (68 * i)) + 1 : ((68 * i) - ((68 * i) + 67)) + 1)) - 1)-:(((68 * i) + 67) >= (68 * i) ? (((68 * i) + 67) - (68 * i)) + 1 : ((68 * i) - ((68 * i) + 67)) + 1)] = {68 {ic_b_sb_wren[(k * pt[1060-:7]) + i]}}; + end + if ($clog2(pt[1161-:18]) == 13) begin : size_8192 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:41 + ram_be_8192x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:7072 + begin : sv2v_autoblock_67 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_34; + for (_gv_l_34 = 0; _gv_l_34 < pt[1076-:8]; _gv_l_34 = _gv_l_34 + 1) begin : BYPASS + localparam l = _gv_l_34; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:12771 + begin : sv2v_autoblock_68 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:594:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:41 + ram_be_8192x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:7072 + begin : sv2v_autoblock_69 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_35; + for (_gv_l_35 = 0; _gv_l_35 < pt[1076-:8]; _gv_l_35 = _gv_l_35 + 1) begin : BYPASS + localparam l = _gv_l_35; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:12771 + begin : sv2v_autoblock_70 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:597:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 12) begin : size_4096 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:41 + ram_be_4096x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:7072 + begin : sv2v_autoblock_71 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_36; + for (_gv_l_36 = 0; _gv_l_36 < pt[1076-:8]; _gv_l_36 = _gv_l_36 + 1) begin : BYPASS + localparam l = _gv_l_36; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:12771 + begin : sv2v_autoblock_72 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:603:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:41 + ram_be_4096x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:7072 + begin : sv2v_autoblock_73 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_37; + for (_gv_l_37 = 0; _gv_l_37 < pt[1076-:8]; _gv_l_37 = _gv_l_37 + 1) begin : BYPASS + localparam l = _gv_l_37; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:12771 + begin : sv2v_autoblock_74 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:606:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 11) begin : size_2048 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:41 + ram_be_2048x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:7072 + begin : sv2v_autoblock_75 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_38; + for (_gv_l_38 = 0; _gv_l_38 < pt[1076-:8]; _gv_l_38 = _gv_l_38 + 1) begin : BYPASS + localparam l = _gv_l_38; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:12771 + begin : sv2v_autoblock_76 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:612:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:41 + ram_be_2048x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:7072 + begin : sv2v_autoblock_77 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_39; + for (_gv_l_39 = 0; _gv_l_39 < pt[1076-:8]; _gv_l_39 = _gv_l_39 + 1) begin : BYPASS + localparam l = _gv_l_39; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:12771 + begin : sv2v_autoblock_78 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:615:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 10) begin : size_1024 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:41 + ram_be_1024x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:7072 + begin : sv2v_autoblock_79 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_40; + for (_gv_l_40 = 0; _gv_l_40 < pt[1076-:8]; _gv_l_40 = _gv_l_40 + 1) begin : BYPASS + localparam l = _gv_l_40; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:12771 + begin : sv2v_autoblock_80 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:621:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:41 + ram_be_1024x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:3678 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:4076 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:4498 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:5095 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:5302 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:5501 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:5899 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:6098 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:6472 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:6674 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:7072 + begin : sv2v_autoblock_81 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:7077 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:7077 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:7274 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_41; + for (_gv_l_41 = 0; _gv_l_41 < pt[1076-:8]; _gv_l_41 = _gv_l_41 + 1) begin : BYPASS + localparam l = _gv_l_41; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:8501 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:8700 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:9098 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:9512 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:9910 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:10308 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:10523 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:10738 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:11152 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:11351 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:11974 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:12174 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:12373 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:12771 + begin : sv2v_autoblock_82 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:12776 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:12776 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:12973 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:13174 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:13768 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:14402 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:624:14601 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 9) begin : size_512 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:40 + ram_be_512x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:7071 + begin : sv2v_autoblock_83 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_42; + for (_gv_l_42 = 0; _gv_l_42 < pt[1076-:8]; _gv_l_42 = _gv_l_42 + 1) begin : BYPASS + localparam l = _gv_l_42; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:11350 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:12770 + begin : sv2v_autoblock_84 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:13767 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:14401 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:630:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:40 + ram_be_512x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:7071 + begin : sv2v_autoblock_85 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_43; + for (_gv_l_43 = 0; _gv_l_43 < pt[1076-:8]; _gv_l_43 = _gv_l_43 + 1) begin : BYPASS + localparam l = _gv_l_43; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:11350 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:12770 + begin : sv2v_autoblock_86 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:13767 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:14401 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:633:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 8) begin : size_256 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:40 + ram_be_256x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:7071 + begin : sv2v_autoblock_87 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_44; + for (_gv_l_44 = 0; _gv_l_44 < pt[1076-:8]; _gv_l_44 = _gv_l_44 + 1) begin : BYPASS + localparam l = _gv_l_44; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:11350 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:12770 + begin : sv2v_autoblock_88 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:13767 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:14401 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:639:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:40 + ram_be_256x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:7071 + begin : sv2v_autoblock_89 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_45; + for (_gv_l_45 = 0; _gv_l_45 < pt[1076-:8]; _gv_l_45 = _gv_l_45 + 1) begin : BYPASS + localparam l = _gv_l_45; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:11350 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:12770 + begin : sv2v_autoblock_90 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:13767 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:14401 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:642:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else if ($clog2(pt[1161-:18]) == 7) begin : size_128 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:40 + ram_be_128x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:7071 + begin : sv2v_autoblock_91 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_46; + for (_gv_l_46 = 0; _gv_l_46 < pt[1076-:8]; _gv_l_46 = _gv_l_46 + 1) begin : BYPASS + localparam l = _gv_l_46; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:11350 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:12770 + begin : sv2v_autoblock_92 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:13767 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:14401 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:648:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:40 + ram_be_128x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:3677 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:4075 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:4497 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:5094 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:5301 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:5500 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:5898 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:6097 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:6471 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:6673 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:7071 + begin : sv2v_autoblock_93 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:7076 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:7076 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:7273 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_47; + for (_gv_l_47 = 0; _gv_l_47 < pt[1076-:8]; _gv_l_47 = _gv_l_47 + 1) begin : BYPASS + localparam l = _gv_l_47; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:8500 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:8699 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:9097 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:9511 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:9909 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:10307 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:10522 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:10737 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:11151 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:11350 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:11973 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:12173 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:12372 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:12770 + begin : sv2v_autoblock_94 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:12775 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:12775 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:12972 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:13173 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:13767 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:14401 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:651:14600 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + else begin : size_64 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:39 + ram_be_64x272 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:3676 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:4074 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:4496 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:5093 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:5300 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:5499 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:5897 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:6096 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:6470 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:6672 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:7070 + begin : sv2v_autoblock_95 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:7075 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:7075 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:7272 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_48; + for (_gv_l_48 = 0; _gv_l_48 < pt[1076-:8]; _gv_l_48 = _gv_l_48 + 1) begin : BYPASS + localparam l = _gv_l_48; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:8499 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:8698 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:9096 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:9510 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:9908 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:10306 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:10521 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:10736 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:11150 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:11349 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:11972 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:12172 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:12371 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:12769 + begin : sv2v_autoblock_96 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:12774 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:12774 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:12971 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:13172 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:13766 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:14400 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:657:14599 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:39 + ram_be_64x136 ic_bank_sb_way_data( + .CLK(clk), + .WE(|ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]), + .WEM(ic_b_sb_bit_en_vec[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .D({pt[1060-:7] {ic_sb_wr_data[(k * 71) + 67-:68]}}), + .ADR(ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9])) : (((k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - pt[1104-:9]))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]), + .Q(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .ME(|ic_bank_way_clken_final[k]), + .ROP(), + .TEST1(ic_data_ext_in_pkt[((0 + k) * 12) + 11]), + .RME(ic_data_ext_in_pkt[((0 + k) * 12) + 10]), + .RM(ic_data_ext_in_pkt[((0 + k) * 12) + 9-:4]), + .LS(ic_data_ext_in_pkt[((0 + k) * 12) + 5]), + .DS(ic_data_ext_in_pkt[((0 + k) * 12) + 4]), + .SD(ic_data_ext_in_pkt[((0 + k) * 12) + 3]), + .TEST_RNM(ic_data_ext_in_pkt[((0 + k) * 12) + 2]), + .BC1(ic_data_ext_in_pkt[((0 + k) * 12) + 1]), + .BC2(ic_data_ext_in_pkt[(0 + k) * 12]) + ); + if (pt[1166-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:3676 + assign wrptr_in[k * pt[1068-:8]+:pt[1068-:8]] = (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == (pt[1076-:8] - 1) ? {pt[1068-:8] * 1 {1'sb0}} : wrptr[k * pt[1068-:8]+:pt[1068-:8]] + 1'd1); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:4074 + rvdffs #(.WIDTH(pt[1068-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[k * pt[1076-:8]+:pt[1076-:8]]), + .din(wrptr_in[k * pt[1068-:8]+:pt[1068-:8]]), + .dout(wrptr[k * pt[1068-:8]+:pt[1068-:8]]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:4496 + assign ic_b_sram_en[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:5093 + assign ic_b_read_en[k] = ic_b_sram_en[k] & |ic_b_sb_rden[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:5300 + assign ic_b_write_en[k] = ic_b_sram_en[k] & |ic_b_sb_wren[k * pt[1060-:7]+:pt[1060-:7]]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:5499 + assign ic_bank_way_clken_final[k] = ic_b_sram_en[k] & ~(|sel_bypass[k * pt[1076-:8]+:pt[1076-:8]]); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:5897 + assign ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = {ic_rw_addr[31:pt[1104-:9] + 1], ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]}; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:6096 + assign ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] = ic_rw_addr_bank_q[(pt[1104-:9] >= pt[1143-:7] ? pt[1143-:7] : pt[1104-:9]) + (k * (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:6470 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:6672 + any_addr_match[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:7070 + begin : sv2v_autoblock_97 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:7075 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:7075 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:7272 + any_addr_match[k] = any_addr_match[k] | ic_b_addr_match[(k * pt[1076-:8]) + l]; + end + end + end + genvar _gv_l_49; + for (_gv_l_49 = 0; _gv_l_49 < pt[1076-:8]; _gv_l_49 = _gv_l_49 + 1) begin : BYPASS + localparam l = _gv_l_49; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:8499 + assign ic_b_addr_match[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)] == ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:8698 + assign ic_b_addr_match_index_only[(k * pt[1076-:8]) + l] = (wb_index_hold[(31 >= pt[1143-:7] ? (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31)) : (((((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)) + (31 >= pt[1143-:7] ? (pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) : pt[1143-:7] - ((pt[1104-:9] >= pt[1143-:7] ? pt[1104-:9] : (pt[1104-:9] + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1) - 31))) + (pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)) - 1)-:(pt[1104-:9] >= pt[1143-:7] ? (pt[1104-:9] - pt[1143-:7]) + 1 : (pt[1143-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr_index_only[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) & index_valid[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:9096 + assign ic_b_clear_en[(k * pt[1076-:8]) + l] = ic_b_write_en[k] & ic_b_addr_match_index_only[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:9510 + assign sel_bypass[(k * pt[1076-:8]) + l] = ic_b_read_en[k] & ic_b_addr_match[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:9908 + assign write_bypass_en[(k * pt[1076-:8]) + l] = (ic_b_read_en[k] & ~any_addr_match[k]) & (wrptr[k * pt[1068-:8]+:pt[1068-:8]] == l); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:10306 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(k * pt[1076-:8]) + l]), + .dout(write_bypass_en_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:10521 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(k * pt[1076-:8]) + l] | ic_b_clear_en[(k * pt[1076-:8]) + l]), + .din(~ic_b_clear_en[(k * pt[1076-:8]) + l]), + .dout(index_valid[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:10736 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(k * pt[1076-:8]) + l]), + .dout(sel_bypass_ff[(k * pt[1076-:8]) + l]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:11150 + rvdffe #(.WIDTH(32 - pt[1143-:7])) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(k * pt[1076-:8]) + l]), + .din(ic_b_rw_addr[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (k * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]), + .dout(wb_index_hold[(31 >= pt[1143-:7] ? pt[1143-:7] : 31) + (((k * pt[1076-:8]) + l) * (31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30))+:(31 >= pt[1143-:7] ? 32 - pt[1143-:7] : pt[1143-:7] - 30)]) + ); + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:11349 + rvdffe #(.WIDTH(68 * pt[1060-:7])) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(k * pt[1076-:8]) + l]), + .din(wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]), + .dout(wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:11972 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:12172 + any_bypass[k] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:12371 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = 1'sb0; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:12769 + begin : sv2v_autoblock_98 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:12774 + reg signed [31:0] l; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:12774 + for (l = 0; l < pt[1076-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:12971 + any_bypass[k] = any_bypass[k] | sel_bypass_ff[(k * pt[1076-:8]) + l]; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:13172 + sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] = sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] | (sel_bypass_ff[(k * pt[1076-:8]) + l] ? wb_packeddout_hold[((k * pt[1076-:8]) + l) * (68 * pt[1060-:7])+:68 * pt[1060-:7]] : {(71 * pt[1060-:7]) * 1 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:13766 + wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = (any_bypass[k] ? sel_bypass_data[k * (71 * pt[1060-:7])+:71 * pt[1060-:7]] : wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:14400 + wire [(68 * pt[1060-:7]) * 1:1] sv2v_tmp_EF755; + assign sv2v_tmp_EF755 = wb_packeddout_pre[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]]; + always @(*) wb_packeddout[k * (68 * pt[1060-:7])+:68 * pt[1060-:7]] = sv2v_tmp_EF755; + // Trace: macro expansion of EL2_PACKED_IC_DATA_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:660:14599 + assign ic_bank_way_clken_final[k] = |ic_bank_way_clken[k * pt[1060-:7]+:pt[1060-:7]]; + end + end + end + genvar _gv_i_12; + for (_gv_i_12 = 0; _gv_i_12 < pt[1060-:7]; _gv_i_12 = _gv_i_12 + 1) begin : WAYS + localparam i = _gv_i_12; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:665:11 + wire [68:1] sv2v_tmp_A8152; + assign sv2v_tmp_A8152 = wb_packeddout[(k * (68 * pt[1060-:7])) + (((68 * i) + 67) >= (68 * i) ? (68 * i) + 67 : (((68 * i) + 67) + (((68 * i) + 67) >= (68 * i) ? (((68 * i) + 67) - (68 * i)) + 1 : ((68 * i) - ((68 * i) + 67)) + 1)) - 1)-:(((68 * i) + 67) >= (68 * i) ? (((68 * i) + 67) - (68 * i)) + 1 : ((68 * i) - ((68 * i) + 67)) + 1)]; + always @(*) wb_dout[(((i * pt[1189-:7]) + k) * 71) + 67-:68] = sv2v_tmp_A8152; + end + end + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:672:4 + assign ic_rd_hit_q[pt[1060-:7] - 1:0] = (ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff[pt[1060-:7] - 1:0] : ic_rd_hit[pt[1060-:7] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:675:2 + function automatic signed [pt[1217-:7] - 1:0] sv2v_cast_58E79_signed; + input reg signed [pt[1217-:7] - 1:0] inp; + sv2v_cast_58E79_signed = inp; + endfunction + generate + if (pt[1125-:5]) begin : ECC1_MUX + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:677:4 + assign ic_bank_wr_data[71+:71] = ic_wr_data[141-:71]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:678:4 + assign ic_bank_wr_data[0+:71] = ic_wr_data[70-:71]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:680:5 + always @(*) begin : rd_mux + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:681:7 + wb_dout_way_pre[142 * ((pt[1060-:7] - 1) - (pt[1060-:7] - 1))+:142 * pt[1060-:7]] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:683:7 + begin : sv2v_autoblock_99 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:683:13 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:683:13 + for (i = 0; i < pt[1060-:7]; i = i + 1) + begin : num_ways + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:684:9 + begin : sv2v_autoblock_100 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:684:15 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:684:15 + for (j = 0; j < pt[1189-:7]; j = j + 1) + begin : banks + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:685:10 + wb_dout_way_pre[(i * 142) + 70-:71] = wb_dout_way_pre[(i * 142) + 70-:71] | ({71 {ic_rw_addr_ff[pt[1210-:7]:pt[1203-:6]] == sv2v_cast_58E79_signed(j)}} & wb_dout[((i * pt[1189-:7]) + j) * 71+:71]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:686:10 + wb_dout_way_pre[(i * 142) + 141-:71] = wb_dout_way_pre[(i * 142) + 141-:71] | ({71 {ic_rw_addr_ff[pt[1210-:7]:pt[1203-:6]] == sv2v_cast_58E79_signed(j - 1)}} & wb_dout[((i * pt[1189-:7]) + j) * 71+:71]); + end + end + end + end + end + genvar _gv_i_13; + for (_gv_i_13 = 0; _gv_i_13 < pt[1060-:7]; _gv_i_13 = _gv_i_13 + 1) begin : num_ways_mux1 + localparam i = _gv_i_13; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:692:7 + assign wb_dout_way[(i * 64) + 63-:64] = (ic_rw_addr_ff[2:1] == 2'b00 ? wb_dout_way_pre[(i * 142) + 63-:64] : (ic_rw_addr_ff[2:1] == 2'b01 ? {wb_dout_way_pre[(i * 142) + 86-:16], wb_dout_way_pre[(i * 142) + 63-:48]} : (ic_rw_addr_ff[2:1] == 2'b10 ? {wb_dout_way_pre[(i * 142) + 102-:32], wb_dout_way_pre[(i * 142) + 63-:32]} : {wb_dout_way_pre[(i * 142) + 119-:49], wb_dout_way_pre[(i * 142) + 63-:16]}))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:697:7 + assign wb_dout_way_with_premux[(i * 64) + 63-:64] = (ic_sel_premux_data ? ic_premux_data[63:0] : wb_dout_way[(i * 64) + 63-:64]); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:700:4 + always @(*) begin : rd_out + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:701:7 + ic_debug_rd_data[70:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:702:7 + ic_rd_data[63:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:703:7 + wb_dout_ecc[141:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:704:7 + begin : sv2v_autoblock_101 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:704:13 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:704:13 + for (i = 0; i < pt[1060-:7]; i = i + 1) + begin : num_ways_mux2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:705:10 + ic_rd_data[63:0] = ic_rd_data[63:0] | ({64 {ic_rd_hit_q[i] | ic_sel_premux_data}} & wb_dout_way_with_premux[(i * 64) + 63-:64]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:706:10 + ic_debug_rd_data[70:0] = ic_debug_rd_data[70:0] | ({71 {ic_rd_hit_q[i]}} & wb_dout_way_pre[(i * 142) + 70-:71]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:707:10 + wb_dout_ecc[141:0] = wb_dout_ecc[141:0] | ({142 {ic_rd_hit_q[i]}} & wb_dout_way_pre[i * 142+:142]); + end + end + end + genvar _gv_i_14; + for (_gv_i_14 = 0; _gv_i_14 < pt[1189-:7]; _gv_i_14 = _gv_i_14 + 1) begin : ic_ecc_error + localparam i = _gv_i_14; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:713:5 + assign bank_check_en[i] = |ic_rd_hit[pt[1060-:7] - 1:0] & ((i == 0) | (~ic_cacheline_wrap_ff & (ic_b_rden_ff[pt[1189-:7] - 1:0] == {pt[1189-:7] {1'b1}}))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:714:5 + assign wb_dout_ecc_bank[i * 71+:71] = wb_dout_ecc[(71 * i) + 70:71 * i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:716:4 + rvecc_decode_64 ecc_decode_64( + .en(bank_check_en[i]), + .din(wb_dout_ecc_bank[(i * 71) + 63-:64]), + .ecc_in(wb_dout_ecc_bank[(i * 71) + 70-:7]), + .ecc_error(ic_eccerr[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:723:3 + assign ic_parerr[i] = 1'sb0; + end + end + else begin : ECC0_MUX + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:729:4 + assign ic_bank_wr_data[71+:71] = ic_wr_data[141-:71]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:730:4 + assign ic_bank_wr_data[0+:71] = ic_wr_data[70-:71]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:732:4 + always @(*) begin : rd_mux + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:733:7 + wb_dout_way_pre[142 * ((pt[1060-:7] - 1) - (pt[1060-:7] - 1))+:142 * pt[1060-:7]] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:735:4 + begin : sv2v_autoblock_102 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:735:10 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:735:10 + for (i = 0; i < pt[1060-:7]; i = i + 1) + begin : num_ways + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:736:6 + begin : sv2v_autoblock_103 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:736:12 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:736:12 + for (j = 0; j < pt[1189-:7]; j = j + 1) + begin : banks + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:737:10 + wb_dout_way_pre[(i * 142) + 67-:68] = wb_dout_way_pre[(i * 142) + 67-:68] | ({68 {ic_rw_addr_ff[pt[1210-:7]:pt[1203-:6]] == sv2v_cast_58E79_signed(j)}} & wb_dout[(((i * pt[1189-:7]) + j) * 71) + 67-:68]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:738:10 + wb_dout_way_pre[(i * 142) + 135-:68] = wb_dout_way_pre[(i * 142) + 135-:68] | ({68 {ic_rw_addr_ff[pt[1210-:7]:pt[1203-:6]] == sv2v_cast_58E79_signed(j - 1)}} & wb_dout[(((i * pt[1189-:7]) + j) * 71) + 67-:68]); + end + end + end + end + end + genvar _gv_i_15; + for (_gv_i_15 = 0; _gv_i_15 < pt[1060-:7]; _gv_i_15 = _gv_i_15 + 1) begin : num_ways_mux1 + localparam i = _gv_i_15; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:744:7 + assign wb_dout_way[(i * 64) + 63-:64] = (ic_rw_addr_ff[2:1] == 2'b00 ? wb_dout_way_pre[(i * 142) + 63-:64] : (ic_rw_addr_ff[2:1] == 2'b01 ? {wb_dout_way_pre[(i * 142) + 83-:16], wb_dout_way_pre[(i * 142) + 63-:48]} : (ic_rw_addr_ff[2:1] == 2'b10 ? {wb_dout_way_pre[(i * 142) + 99-:32], wb_dout_way_pre[(i * 142) + 63-:32]} : {wb_dout_way_pre[(i * 142) + 115-:48], wb_dout_way_pre[(i * 142) + 63-:16]}))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:749:7 + assign wb_dout_way_with_premux[(i * 64) + 63-:64] = (ic_sel_premux_data ? ic_premux_data[63:0] : wb_dout_way[(i * 64) + 63-:64]); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:752:4 + always @(*) begin : rd_out + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:753:7 + ic_rd_data[63:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:754:7 + ic_debug_rd_data[70:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:755:7 + wb_dout_ecc[135:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:757:7 + begin : sv2v_autoblock_104 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:757:13 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:757:13 + for (i = 0; i < pt[1060-:7]; i = i + 1) + begin : num_ways_mux2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:758:10 + ic_rd_data[63:0] = ic_rd_data[63:0] | ({64 {ic_rd_hit_q[i] | ic_sel_premux_data}} & wb_dout_way_with_premux[(i * 64) + 63-:64]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:759:10 + ic_debug_rd_data[70:0] = ic_debug_rd_data[70:0] | ({71 {ic_rd_hit_q[i]}} & {3'b000, wb_dout_way_pre[(i * 142) + 67-:68]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:760:10 + wb_dout_ecc[135:0] = wb_dout_ecc[135:0] | ({136 {ic_rd_hit_q[i]}} & wb_dout_way_pre[(i * 142) + 135-:136]); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:764:4 + assign wb_dout_ecc_bank[0+:71] = wb_dout_ecc[67:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:765:4 + assign wb_dout_ecc_bank[71+:71] = wb_dout_ecc[135:68]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:767:4 + wire [(pt[1189-:7] * 4) - 1:0] ic_parerr_bank; + genvar _gv_i_16; + for (_gv_i_16 = 0; _gv_i_16 < pt[1189-:7]; _gv_i_16 = _gv_i_16 + 1) begin : ic_par_error + localparam i = _gv_i_16; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:770:5 + assign bank_check_en[i] = |ic_rd_hit[pt[1060-:7] - 1:0] & ((i == 0) | (~ic_cacheline_wrap_ff & (ic_b_rden_ff[pt[1189-:7] - 1:0] == {pt[1189-:7] {1'b1}}))); + genvar _gv_j_3; + for (_gv_j_3 = 0; _gv_j_3 < 4; _gv_j_3 = _gv_j_3 + 1) begin : parity + localparam j = _gv_j_3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:772:7 + rveven_paritycheck pchk( + .data_in(wb_dout_ecc_bank[(i * 71) + (((16 * (j + 1)) - 1) >= (16 * j) ? (16 * (j + 1)) - 1 : (((16 * (j + 1)) - 1) + (((16 * (j + 1)) - 1) >= (16 * j) ? (((16 * (j + 1)) - 1) - (16 * j)) + 1 : ((16 * j) - ((16 * (j + 1)) - 1)) + 1)) - 1)-:(((16 * (j + 1)) - 1) >= (16 * j) ? (((16 * (j + 1)) - 1) - (16 * j)) + 1 : ((16 * j) - ((16 * (j + 1)) - 1)) + 1)]), + .parity_in(wb_dout_ecc_bank[(i * 71) + (64 + j)]), + .parity_err(ic_parerr_bank[(i * 4) + j]) + ); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:778:6 + assign ic_eccerr[i] = 1'sb0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:781:6 + assign ic_parerr[1] = |ic_parerr_bank[7-:4] & bank_check_en[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:782:6 + assign ic_parerr[0] = |ic_parerr_bank[3-:4] & bank_check_en[0]; + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module EL2_IC_TAG ( + clk, + active_clk, + rst_l, + clk_override, + dec_tlu_core_ecc_disable, + ic_rw_addr, + ic_wr_en, + ic_tag_valid, + ic_rd_en, + ic_debug_addr, + ic_debug_rd_en, + ic_debug_wr_en, + ic_debug_tag_array, + ic_debug_way, + ic_tag_ext_in_pkt, + ictag_debug_rd_data, + ic_debug_wr_data, + ic_rd_hit, + ic_tag_perr, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:803:7 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:804:7 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:805:7 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:806:7 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:807:7 + input wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:809:7 + input wire [31:3] ic_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:811:7 + input wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:812:7 + input wire [pt[1060-:7] - 1:0] ic_tag_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:813:7 + input wire ic_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:815:7 + input wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:816:7 + input wire ic_debug_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:817:7 + input wire ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:818:7 + input wire ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:819:7 + input wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:820:7 + // removed localparam type el2_pkg_el2_ic_tag_ext_in_pkt_t + input wire [(pt[1060-:7] * 12) - 1:0] ic_tag_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:822:7 + output reg [25:0] ictag_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:823:7 + input wire [70:0] ic_debug_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:825:7 + output wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:826:7 + output wire ic_tag_perr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:827:7 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:830:4 + reg [(pt[1060-:7] * 26) - 1:0] ic_tag_data_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:831:4 + wire [(pt[1060-:7] * 26) - 1:0] ic_tag_data_raw_pre; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:832:4 + wire [(36 >= pt[991-:9] ? (pt[1060-:7] * (37 - pt[991-:9])) + (pt[991-:9] - 1) : (pt[1060-:7] * (pt[991-:9] - 35)) + 35):(36 >= pt[991-:9] ? pt[991-:9] + 0 : 36)] w_tout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:833:4 + wire [25:0] ic_tag_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:834:4 + wire [(pt[1060-:7] * 32) - 1:0] ic_tag_corrected_data_unc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:835:4 + wire [(pt[1060-:7] * 7) - 1:0] ic_tag_corrected_ecc_unc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:836:4 + wire [pt[1060-:7] - 1:0] ic_tag_single_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:837:4 + wire [pt[1060-:7] - 1:0] ic_tag_double_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:838:4 + wire [6:0] ic_tag_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:840:4 + wire [pt[1060-:7] - 1:0] ic_tag_way_perr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:841:4 + wire [pt[1060-:7] - 1:0] ic_debug_rd_way_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:842:4 + wire [pt[1060-:7] - 1:0] ic_debug_rd_way_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:844:4 + wire [pt[1104-:9]:pt[998-:7]] ic_rw_addr_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:845:4 + wire [31:pt[991-:9]] ic_rw_addr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:846:4 + wire [pt[1060-:7] - 1:0] ic_tag_rden_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:847:4 + wire [pt[1060-:7] - 1:0] ic_tag_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:848:4 + wire [pt[1060-:7] - 1:0] ic_tag_wren_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:849:4 + wire [pt[1060-:7] - 1:0] ic_tag_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:850:4 + wire [pt[1060-:7] - 1:0] ic_debug_wr_way_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:851:4 + wire ic_rd_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:852:4 + wire ic_tag_parity; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:855:4 + assign ic_tag_wren[pt[1060-:7] - 1:0] = ic_wr_en[pt[1060-:7] - 1:0] & {pt[1060-:7] {ic_rw_addr[pt[1182-:8]:4] == {pt[1174-:8] - 1 {1'b1}}}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:856:4 + assign ic_tag_clken[pt[1060-:7] - 1:0] = (({pt[1060-:7] {ic_rd_en | clk_override}} | ic_wr_en[pt[1060-:7] - 1:0]) | ic_debug_wr_way_en[pt[1060-:7] - 1:0]) | ic_debug_rd_way_en[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:858:4 + rvdff #(.WIDTH(1)) rd_en_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(ic_rd_en), + .dout(ic_rd_en_ff) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:863:4 + rvdffie #(.WIDTH(32 - pt[991-:9])) adr_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({ic_rw_addr[31:pt[991-:9]]}), + .dout({ic_rw_addr_ff[31:pt[991-:9]]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:868:4 + localparam PAD_BITS = pt[991-:9] - 11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:871:4 + assign ic_debug_rd_way_en[pt[1060-:7] - 1:0] = {pt[1060-:7] {ic_debug_rd_en & ic_debug_tag_array}} & ic_debug_way[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:872:4 + assign ic_debug_wr_way_en[pt[1060-:7] - 1:0] = {pt[1060-:7] {ic_debug_wr_en & ic_debug_tag_array}} & ic_debug_way[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:874:4 + assign ic_tag_wren_q[pt[1060-:7] - 1:0] = ic_tag_wren[pt[1060-:7] - 1:0] | ic_debug_wr_way_en[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:877:4 + assign ic_tag_rden_q[pt[1060-:7] - 1:0] = ({pt[1060-:7] {ic_rd_en}} | ic_debug_rd_way_en[pt[1060-:7] - 1:0]) & {pt[1060-:7] {~(|ic_wr_en) & ~ic_debug_wr_en}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:879:1 + generate + if (pt[991-:9] == 11) begin : SMALLEST + if (pt[1125-:5]) begin : ECC1_W + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:881:12 + rvecc_encode tag_ecc_encode( + .din({{pt[991-:9] {1'b0}}, ic_rw_addr[31:pt[991-:9]]}), + .ecc_out({ic_tag_ecc[6:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:885:4 + assign ic_tag_wr_data[25:0] = (ic_debug_wr_en & ic_debug_tag_array ? {ic_debug_wr_data[68:64], ic_debug_wr_data[31:11]} : {ic_tag_ecc[4:0], ic_rw_addr[31:pt[991-:9]]}); + end + else begin : ECC0_W + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:891:12 + rveven_paritygen #(.WIDTH(32 - pt[991-:9])) pargen( + .data_in(ic_rw_addr[31:pt[991-:9]]), + .parity_out(ic_tag_parity) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:894:4 + assign ic_tag_wr_data[21:0] = (ic_debug_wr_en & ic_debug_tag_array ? {ic_debug_wr_data[64], ic_debug_wr_data[31:11]} : {ic_tag_parity, ic_rw_addr[31:pt[991-:9]]}); + end + end + else begin : OTHERS + if (pt[1125-:5]) begin : ECC1_W + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:904:12 + rvecc_encode tag_ecc_encode( + .din({{pt[991-:9] {1'b0}}, ic_rw_addr[31:pt[991-:9]]}), + .ecc_out({ic_tag_ecc[6:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:908:4 + assign ic_tag_wr_data[25:0] = (ic_debug_wr_en & ic_debug_tag_array ? {ic_debug_wr_data[68:64], ic_debug_wr_data[31:11]} : {ic_tag_ecc[4:0], {PAD_BITS {1'b0}}, ic_rw_addr[31:pt[991-:9]]}); + end + else begin : ECC0_W + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:914:4 + wire ic_tag_parity; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:915:12 + rveven_paritygen #(.WIDTH(32 - pt[991-:9])) pargen( + .data_in(ic_rw_addr[31:pt[991-:9]]), + .parity_out(ic_tag_parity) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:917:4 + assign ic_tag_wr_data[21:0] = (ic_debug_wr_en & ic_debug_tag_array ? {ic_debug_wr_data[64], ic_debug_wr_data[31:11]} : {ic_tag_parity, {PAD_BITS {1'b0}}, ic_rw_addr[31:pt[991-:9]]}); + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:925:5 + assign ic_rw_addr_q[pt[1104-:9]:pt[998-:7]] = (ic_debug_rd_en | ic_debug_wr_en ? ic_debug_addr[pt[1104-:9]:pt[998-:7]] : ic_rw_addr[pt[1104-:9]:pt[998-:7]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:929:4 + rvdff #(.WIDTH(pt[1060-:7])) tag_rd_wy_ff( + .rst_l(rst_l), + .clk(active_clk), + .din({ic_debug_rd_way_en[pt[1060-:7] - 1:0]}), + .dout({ic_debug_rd_way_en_ff[pt[1060-:7] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:933:2 + generate + if (pt[966-:5] == 0) begin : PACKED_0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:935:4 + wire [pt[1060-:7] - 1:0] ic_b_sram_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:936:4 + wire [pt[1060-:7] - 1:0] ic_b_read_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:937:4 + wire [pt[1060-:7] - 1:0] ic_b_write_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:938:4 + wire [(pt[1104-:9] >= pt[998-:7] ? ((pt[1060-:7] * pt[982-:8]) * ((pt[1104-:9] - pt[998-:7]) + 1)) + (pt[998-:7] - 1) : ((pt[1060-:7] * pt[982-:8]) * ((pt[998-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] - 1)):(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] + 0 : pt[1104-:9] + 0)] wb_index_hold; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:939:4 + wire [(pt[1104-:9] >= pt[998-:7] ? (pt[1060-:7] * ((pt[1104-:9] - pt[998-:7]) + 1)) + (pt[998-:7] - 1) : (pt[1060-:7] * ((pt[998-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] - 1)):(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] + 0 : pt[1104-:9] + 0)] ic_b_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:940:4 + wire [(pt[1060-:7] * pt[982-:8]) - 1:0] write_bypass_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:941:4 + wire [(pt[1060-:7] * pt[982-:8]) - 1:0] write_bypass_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:942:4 + wire [(pt[1060-:7] * pt[982-:8]) - 1:0] index_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:943:4 + wire [(pt[1060-:7] * pt[982-:8]) - 1:0] ic_b_clear_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:944:4 + wire [(pt[1060-:7] * pt[982-:8]) - 1:0] ic_b_addr_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:949:5 + wire [(pt[1060-:7] * pt[974-:8]) - 1:0] wrptr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:950:5 + wire [(pt[1060-:7] * pt[974-:8]) - 1:0] wrptr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:951:5 + wire [(pt[1060-:7] * pt[982-:8]) - 1:0] sel_bypass; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:952:5 + wire [(pt[1060-:7] * pt[982-:8]) - 1:0] sel_bypass_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:956:5 + reg [(pt[1060-:7] * 26) - 1:0] sel_bypass_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:957:5 + reg [pt[1060-:7] - 1:0] any_bypass; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:958:5 + reg [pt[1060-:7] - 1:0] any_addr_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:959:5 + wire [pt[1060-:7] - 1:0] ic_tag_clken_final; + genvar _gv_i_17; + for (_gv_i_17 = 0; _gv_i_17 < pt[1060-:7]; _gv_i_17 = _gv_i_17 + 1) begin : WAYS + localparam i = _gv_i_17; + if (pt[1125-:5]) begin : ECC1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1051:7 + wire [((pt[1060-:7] * pt[982-:8]) * 26) - 1:0] wb_dout_hold; + if (pt[1015-:17] == 32) begin : size_32 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:60 + ram_32x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:4211 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:4609 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:5007 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:5405 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:5604 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:5803 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:6219 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:6617 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:6819 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:7217 + begin : sv2v_autoblock_1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:7222 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:7222 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:7419 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_50; + for (_gv_l_50 = 0; _gv_l_50 < pt[982-:8]; _gv_l_50 = _gv_l_50 + 1) begin : BYPASS + localparam l = _gv_l_50; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:8626 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:9024 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:9422 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:9820 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:10218 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:10433 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:10648 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:11062 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:11272 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:11919 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:12119 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:12318 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:12716 + begin : sv2v_autoblock_2 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:12721 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:12721 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:12918 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:13117 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:13713 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:14347 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1054:14546 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 64) begin : size_64 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:60 + ram_64x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:4211 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:4609 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:5007 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:5405 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:5604 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:5803 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:6219 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:6617 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:6819 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:7217 + begin : sv2v_autoblock_3 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:7222 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:7222 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:7419 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_51; + for (_gv_l_51 = 0; _gv_l_51 < pt[982-:8]; _gv_l_51 = _gv_l_51 + 1) begin : BYPASS + localparam l = _gv_l_51; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:8626 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:9024 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:9422 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:9820 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:10218 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:10433 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:10648 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:11062 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:11272 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:11919 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:12119 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:12318 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:12716 + begin : sv2v_autoblock_4 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:12721 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:12721 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:12918 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:13117 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:13713 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:14347 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1057:14546 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 128) begin : size_128 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:61 + ram_128x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:4212 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:4610 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:5008 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:5406 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:5605 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:5804 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:6220 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:6618 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:6820 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:7218 + begin : sv2v_autoblock_5 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:7223 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:7223 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:7420 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_52; + for (_gv_l_52 = 0; _gv_l_52 < pt[982-:8]; _gv_l_52 = _gv_l_52 + 1) begin : BYPASS + localparam l = _gv_l_52; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:8627 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:9025 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:9423 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:9821 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:10219 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:10434 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:10649 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:11063 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:11273 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:11920 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:12120 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:12319 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:12717 + begin : sv2v_autoblock_6 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:12722 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:12722 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:12919 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:13118 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:13714 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:14348 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1060:14547 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 256) begin : size_256 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:61 + ram_256x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:4212 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:4610 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:5008 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:5406 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:5605 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:5804 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:6220 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:6618 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:6820 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:7218 + begin : sv2v_autoblock_7 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:7223 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:7223 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:7420 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_53; + for (_gv_l_53 = 0; _gv_l_53 < pt[982-:8]; _gv_l_53 = _gv_l_53 + 1) begin : BYPASS + localparam l = _gv_l_53; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:8627 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:9025 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:9423 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:9821 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:10219 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:10434 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:10649 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:11063 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:11273 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:11920 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:12120 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:12319 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:12717 + begin : sv2v_autoblock_8 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:12722 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:12722 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:12919 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:13118 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:13714 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:14348 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1063:14547 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 512) begin : size_512 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:61 + ram_512x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:4212 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:4610 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:5008 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:5406 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:5605 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:5804 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:6220 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:6618 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:6820 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:7218 + begin : sv2v_autoblock_9 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:7223 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:7223 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:7420 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_54; + for (_gv_l_54 = 0; _gv_l_54 < pt[982-:8]; _gv_l_54 = _gv_l_54 + 1) begin : BYPASS + localparam l = _gv_l_54; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:8627 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:9025 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:9423 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:9821 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:10219 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:10434 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:10649 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:11063 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:11273 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:11920 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:12120 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:12319 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:12717 + begin : sv2v_autoblock_10 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:12722 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:12722 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:12919 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:13118 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:13714 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:14348 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1066:14547 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 1024) begin : size_1024 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:62 + ram_1024x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:4213 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:4611 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:5009 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:5407 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:5606 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:5805 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:6221 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:6619 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:6821 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:7219 + begin : sv2v_autoblock_11 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:7224 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:7224 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:7421 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_55; + for (_gv_l_55 = 0; _gv_l_55 < pt[982-:8]; _gv_l_55 = _gv_l_55 + 1) begin : BYPASS + localparam l = _gv_l_55; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:8628 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:9026 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:9424 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:9822 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:10220 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:10435 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:10650 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:11064 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:11274 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:11921 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:12121 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:12320 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:12718 + begin : sv2v_autoblock_12 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:12723 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:12723 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:12920 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:13119 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:13715 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:14349 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1069:14548 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 2048) begin : size_2048 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:62 + ram_2048x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:4213 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:4611 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:5009 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:5407 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:5606 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:5805 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:6221 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:6619 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:6821 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:7219 + begin : sv2v_autoblock_13 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:7224 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:7224 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:7421 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_56; + for (_gv_l_56 = 0; _gv_l_56 < pt[982-:8]; _gv_l_56 = _gv_l_56 + 1) begin : BYPASS + localparam l = _gv_l_56; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:8628 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:9026 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:9424 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:9822 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:10220 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:10435 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:10650 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:11064 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:11274 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:11921 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:12121 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:12320 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:12718 + begin : sv2v_autoblock_14 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:12723 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:12723 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:12920 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:13119 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:13715 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:14349 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1072:14548 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 4096) begin : size_4096 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:62 + ram_4096x26 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[25:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:4213 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:4611 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:5009 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:5407 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:5606 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:5805 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:6221 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:6619 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:6821 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:7219 + begin : sv2v_autoblock_15 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:7224 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:7224 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:7421 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_57; + for (_gv_l_57 = 0; _gv_l_57 < pt[982-:8]; _gv_l_57 = _gv_l_57 + 1) begin : BYPASS + localparam l = _gv_l_57; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:8628 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:9026 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:9424 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:9822 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:10220 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:10435 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:10650 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:11064 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:11274 + rvdffe #(.WIDTH(26)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 25-:26]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:11921 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:12121 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:12320 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:12718 + begin : sv2v_autoblock_16 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:12723 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:12723 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:12920 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:13119 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 26+:26] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:13715 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:14349 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1075:14548 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1078:10 + assign w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36)) : (((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36))) + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:(31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)] = ic_tag_data_raw[(i * 26) + ((31 - pt[991-:9]) >= 0 ? 31 - pt[991-:9] : ((31 - pt[991-:9]) + ((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1079:10 + assign w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 36 : pt[991-:9]) : ((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 36 : pt[991-:9])) + 4)-:5] = ic_tag_data_raw[(i * 26) + 25-:5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1081:10 + rvecc_decode ecc_decode( + .en(~dec_tlu_core_ecc_disable & ic_rd_en_ff), + .sed_ded(1'b1), + .din({11'b00000000000, ic_tag_data_raw[(i * 26) + 20-:21]}), + .ecc_in({2'b00, ic_tag_data_raw[(i * 26) + 25-:5]}), + .dout(ic_tag_corrected_data_unc[(i * 32) + 31-:32]), + .ecc_out(ic_tag_corrected_ecc_unc[(i * 7) + 6-:7]), + .single_ecc_error(ic_tag_single_ecc_error[i]), + .double_ecc_error(ic_tag_double_ecc_error[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1091:11 + assign ic_tag_way_perr[i] = ic_tag_single_ecc_error[i] | ic_tag_double_ecc_error[i]; + end + else begin : ECC0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1094:7 + wire [((pt[1060-:7] * pt[982-:8]) * 22) - 1:0] wb_dout_hold; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1095:7 + assign ic_tag_data_raw_pre[(i * 26) + 25-:4] = 1'sb0; + if (pt[1015-:17] == 32) begin : size_32 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:60 + ram_32x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:4211 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:4609 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:5007 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:5405 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:5604 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:5803 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:6219 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:6617 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:6819 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:7217 + begin : sv2v_autoblock_17 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:7222 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:7222 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:7419 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_58; + for (_gv_l_58 = 0; _gv_l_58 < pt[982-:8]; _gv_l_58 = _gv_l_58 + 1) begin : BYPASS + localparam l = _gv_l_58; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:8626 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:9024 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:9422 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:9820 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:10218 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:10433 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:10648 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:11062 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:11272 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:11919 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:12119 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:12318 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:12716 + begin : sv2v_autoblock_18 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:12721 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:12721 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:12918 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:13117 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:13713 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:14347 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1098:14546 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 64) begin : size_64 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:60 + ram_64x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:4211 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:4609 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:5007 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:5405 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:5604 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:5803 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:6219 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:6617 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:6819 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:7217 + begin : sv2v_autoblock_19 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:7222 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:7222 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:7419 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_59; + for (_gv_l_59 = 0; _gv_l_59 < pt[982-:8]; _gv_l_59 = _gv_l_59 + 1) begin : BYPASS + localparam l = _gv_l_59; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:8626 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:9024 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:9422 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:9820 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:10218 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:10433 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:10648 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:11062 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:11272 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:11919 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:12119 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:12318 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:12716 + begin : sv2v_autoblock_20 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:12721 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:12721 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:12918 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:13117 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:13713 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:14347 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1101:14546 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 128) begin : size_128 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:61 + ram_128x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:4212 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:4610 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:5008 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:5406 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:5605 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:5804 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:6220 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:6618 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:6820 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:7218 + begin : sv2v_autoblock_21 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:7223 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:7223 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:7420 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_60; + for (_gv_l_60 = 0; _gv_l_60 < pt[982-:8]; _gv_l_60 = _gv_l_60 + 1) begin : BYPASS + localparam l = _gv_l_60; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:8627 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:9025 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:9423 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:9821 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:10219 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:10434 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:10649 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:11063 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:11273 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:11920 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:12120 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:12319 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:12717 + begin : sv2v_autoblock_22 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:12722 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:12722 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:12919 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:13118 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:13714 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:14348 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1104:14547 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 256) begin : size_256 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:61 + ram_256x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:4212 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:4610 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:5008 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:5406 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:5605 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:5804 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:6220 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:6618 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:6820 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:7218 + begin : sv2v_autoblock_23 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:7223 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:7223 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:7420 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_61; + for (_gv_l_61 = 0; _gv_l_61 < pt[982-:8]; _gv_l_61 = _gv_l_61 + 1) begin : BYPASS + localparam l = _gv_l_61; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:8627 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:9025 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:9423 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:9821 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:10219 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:10434 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:10649 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:11063 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:11273 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:11920 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:12120 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:12319 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:12717 + begin : sv2v_autoblock_24 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:12722 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:12722 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:12919 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:13118 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:13714 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:14348 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1107:14547 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 512) begin : size_512 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:61 + ram_512x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:4212 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:4610 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:5008 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:5406 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:5605 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:5804 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:6220 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:6618 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:6820 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:7218 + begin : sv2v_autoblock_25 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:7223 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:7223 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:7420 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_62; + for (_gv_l_62 = 0; _gv_l_62 < pt[982-:8]; _gv_l_62 = _gv_l_62 + 1) begin : BYPASS + localparam l = _gv_l_62; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:8627 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:9025 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:9423 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:9821 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:10219 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:10434 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:10649 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:11063 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:11273 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:11920 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:12120 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:12319 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:12717 + begin : sv2v_autoblock_26 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:12722 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:12722 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:12919 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:13118 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:13714 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:14348 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1110:14547 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 1024) begin : size_1024 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:62 + ram_1024x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:4213 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:4611 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:5009 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:5407 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:5606 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:5805 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:6221 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:6619 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:6821 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:7219 + begin : sv2v_autoblock_27 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:7224 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:7224 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:7421 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_63; + for (_gv_l_63 = 0; _gv_l_63 < pt[982-:8]; _gv_l_63 = _gv_l_63 + 1) begin : BYPASS + localparam l = _gv_l_63; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:8628 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:9026 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:9424 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:9822 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:10220 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:10435 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:10650 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:11064 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:11274 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:11921 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:12121 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:12320 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:12718 + begin : sv2v_autoblock_28 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:12723 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:12723 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:12920 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:13119 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:13715 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:14349 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1113:14548 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 2048) begin : size_2048 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:62 + ram_2048x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:4213 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:4611 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:5009 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:5407 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:5606 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:5805 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:6221 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:6619 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:6821 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:7219 + begin : sv2v_autoblock_29 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:7224 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:7224 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:7421 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_64; + for (_gv_l_64 = 0; _gv_l_64 < pt[982-:8]; _gv_l_64 = _gv_l_64 + 1) begin : BYPASS + localparam l = _gv_l_64; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:8628 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:9026 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:9424 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:9822 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:10220 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:10435 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:10650 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:11064 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:11274 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:11921 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:12121 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:12320 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:12718 + begin : sv2v_autoblock_30 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:12723 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:12723 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:12920 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:13119 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:13715 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:14349 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1116:14548 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + if (pt[1015-:17] == 4096) begin : size_4096 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:62 + ram_4096x22 ic_way_tag( + .ME(ic_tag_clken_final[i]), + .WE(ic_tag_wren_q[i]), + .D(ic_tag_wr_data[21:0]), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[(i * 12) + 11]), + .RME(ic_tag_ext_in_pkt[(i * 12) + 10]), + .RM(ic_tag_ext_in_pkt[(i * 12) + 9-:4]), + .LS(ic_tag_ext_in_pkt[(i * 12) + 5]), + .DS(ic_tag_ext_in_pkt[(i * 12) + 4]), + .SD(ic_tag_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(ic_tag_ext_in_pkt[(i * 12) + 2]), + .BC1(ic_tag_ext_in_pkt[(i * 12) + 1]), + .BC2(ic_tag_ext_in_pkt[i * 12]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:4213 + assign wrptr_in[i * pt[974-:8]+:pt[974-:8]] = (wrptr[i * pt[974-:8]+:pt[974-:8]] == (pt[982-:8] - 1) ? {pt[974-:8] * 1 {1'sb0}} : wrptr[i * pt[974-:8]+:pt[974-:8]] + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:4611 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en[i * pt[982-:8]+:pt[982-:8]]), + .din(wrptr_in[i * pt[974-:8]+:pt[974-:8]]), + .dout(wrptr[i * pt[974-:8]+:pt[974-:8]]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:5009 + assign ic_b_sram_en[i] = ic_tag_clken[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:5407 + assign ic_b_read_en[i] = ic_b_sram_en[i] & ic_tag_rden_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:5606 + assign ic_b_write_en[i] = ic_b_sram_en[i] & ic_tag_wren_q[i]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:5805 + assign ic_tag_clken_final[i] = ic_b_sram_en[i] & ~(|sel_bypass[i * pt[982-:8]+:pt[982-:8]]); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:6221 + assign ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:6619 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:6821 + any_addr_match[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:7219 + begin : sv2v_autoblock_31 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:7224 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:7224 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:7421 + any_addr_match[i] = any_addr_match[i] | (ic_b_addr_match[(i * pt[982-:8]) + l] & index_valid[(i * pt[982-:8]) + l]); + end + end + end + genvar _gv_l_65; + for (_gv_l_65 = 0; _gv_l_65 < pt[982-:8]; _gv_l_65 = _gv_l_65 + 1) begin : BYPASS + localparam l = _gv_l_65; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:8628 + assign ic_b_addr_match[(i * pt[982-:8]) + l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) & index_valid[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:9026 + assign ic_b_clear_en[(i * pt[982-:8]) + l] = ic_b_write_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:9424 + assign sel_bypass[(i * pt[982-:8]) + l] = ic_b_read_en[i] & ic_b_addr_match[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:9822 + assign write_bypass_en[(i * pt[982-:8]) + l] = (ic_b_read_en[i] & ~any_addr_match[i]) & (wrptr[i * pt[974-:8]+:pt[974-:8]] == l); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:10220 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[(i * pt[982-:8]) + l]), + .dout(write_bypass_en_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:10435 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[(i * pt[982-:8]) + l] | ic_b_clear_en[(i * pt[982-:8]) + l]), + .din(~ic_b_clear_en[(i * pt[982-:8]) + l]), + .dout(index_valid[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:10650 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[(i * pt[982-:8]) + l]), + .dout(sel_bypass_ff[(i * pt[982-:8]) + l]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:11064 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[(i * pt[982-:8]) + l]), + .din(ic_b_rw_addr[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (i * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (((i * pt[982-:8]) + l) * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:11274 + rvdffe #(.WIDTH(22)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[(i * pt[982-:8]) + l]), + .din(ic_tag_data_raw_pre[(i * 26) + 21-:22]), + .dout(wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:11921 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:12121 + any_bypass[i] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:12320 + sel_bypass_data[i * 26+:26] = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:12718 + begin : sv2v_autoblock_32 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:12723 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:12723 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:12920 + any_bypass[i] = any_bypass[i] | sel_bypass_ff[(i * pt[982-:8]) + l]; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:13119 + sel_bypass_data[i * 26+:26] = sel_bypass_data[i * 26+:26] | (sel_bypass_ff[(i * pt[982-:8]) + l] ? wb_dout_hold[((i * pt[982-:8]) + l) * 22+:22] : {26 {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:13715 + ic_tag_data_raw[i * 26+:26] = (any_bypass[i] ? sel_bypass_data[i * 26+:26] : ic_tag_data_raw_pre[i * 26+:26]); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:14349 + wire [26:1] sv2v_tmp_0112D; + assign sv2v_tmp_0112D = ic_tag_data_raw_pre[i * 26+:26]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_0112D; + // Trace: macro expansion of EL2_IC_TAG_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1119:14548 + assign ic_tag_clken_final[i] = ic_tag_clken[i]; + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1122:10 + assign w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36)) : (((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36))) + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:(31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)] = ic_tag_data_raw[(i * 26) + ((31 - pt[991-:9]) >= 0 ? 31 - pt[991-:9] : ((31 - pt[991-:9]) + ((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1123:10 + assign w_tout[(i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 32 : pt[991-:9] + 4)] = ic_tag_data_raw[(i * 26) + 21]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1125:10 + rveven_paritycheck #(.WIDTH(32 - pt[991-:9])) parcheck( + .data_in(w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36)) : (((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36))) + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:(31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)]), + .parity_in(w_tout[(i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 32 : pt[991-:9] + 4)]), + .parity_err(ic_tag_way_perr[i]) + ); + end + end + end + else begin : PACKED_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1137:4 + wire ic_b_sram_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1138:4 + wire ic_b_read_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1139:4 + wire ic_b_write_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1140:4 + wire [(pt[1104-:9] >= pt[998-:7] ? (pt[982-:8] * ((pt[1104-:9] - pt[998-:7]) + 1)) + (pt[998-:7] - 1) : (pt[982-:8] * ((pt[998-:7] - pt[1104-:9]) + 1)) + (pt[1104-:9] - 1)):(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] + 0 : pt[1104-:9] + 0)] wb_index_hold; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1141:4 + wire [pt[1104-:9]:pt[998-:7]] ic_b_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1142:4 + wire [pt[982-:8] - 1:0] write_bypass_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1143:4 + wire [pt[982-:8] - 1:0] write_bypass_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1144:4 + wire [pt[982-:8] - 1:0] index_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1145:4 + wire [pt[982-:8] - 1:0] ic_b_clear_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1146:4 + wire [pt[982-:8] - 1:0] ic_b_addr_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1151:5 + wire [pt[974-:8] - 1:0] wrptr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1152:5 + wire [pt[974-:8] - 1:0] wrptr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1153:5 + wire [pt[982-:8] - 1:0] sel_bypass; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1154:5 + wire [pt[982-:8] - 1:0] sel_bypass_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1158:5 + reg [(26 * pt[1060-:7]) - 1:0] sel_bypass_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1159:5 + reg any_bypass; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1160:5 + reg any_addr_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1161:5 + wire ic_tag_clken_final; + if (pt[1125-:5]) begin : ECC1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1251:5 + reg [(26 * pt[1060-:7]) - 1:0] ic_tag_data_raw_packed; + wire [(26 * pt[1060-:7]) - 1:0] ic_tag_wren_biten_vec; + wire [(26 * pt[1060-:7]) - 1:0] ic_tag_data_raw_packed_pre; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1252:5 + wire [(pt[982-:8] * (26 * pt[1060-:7])) - 1:0] wb_packeddout_hold; + genvar _gv_i_18; + for (_gv_i_18 = 0; _gv_i_18 < pt[1060-:7]; _gv_i_18 = _gv_i_18 + 1) begin : BITEN + localparam i = _gv_i_18; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1254:9 + assign ic_tag_wren_biten_vec[(26 * i) + 25:26 * i] = {26 {ic_tag_wren_q[i]}}; + end + if (pt[1015-:17] == 32) begin : size_32 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:45 + ram_be_32x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:6150 + begin : sv2v_autoblock_33 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_66; + for (_gv_l_66 = 0; _gv_l_66 < pt[982-:8]; _gv_l_66 = _gv_l_66 + 1) begin : BYPASS + localparam l = _gv_l_66; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:10218 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:11662 + begin : sv2v_autoblock_34 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:13293 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1258:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:44 + ram_be_32x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:3143 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:3541 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:3939 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:4337 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:4536 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:4735 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:5151 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:5549 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:5751 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:6149 + begin : sv2v_autoblock_35 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:6154 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:6154 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:6351 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_67; + for (_gv_l_67 = 0; _gv_l_67 < pt[982-:8]; _gv_l_67 = _gv_l_67 + 1) begin : BYPASS + localparam l = _gv_l_67; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:7558 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:7956 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:8354 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:8752 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:9150 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:9365 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:9580 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:10002 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:10217 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:10864 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:11064 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:11263 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:11661 + begin : sv2v_autoblock_36 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:11666 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:11666 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:11863 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:12062 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:12658 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:13292 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1261:13491 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 64) begin : size_64 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:45 + ram_be_64x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:6150 + begin : sv2v_autoblock_37 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_68; + for (_gv_l_68 = 0; _gv_l_68 < pt[982-:8]; _gv_l_68 = _gv_l_68 + 1) begin : BYPASS + localparam l = _gv_l_68; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:10218 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:11662 + begin : sv2v_autoblock_38 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:13293 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1267:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:44 + ram_be_64x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:3143 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:3541 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:3939 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:4337 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:4536 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:4735 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:5151 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:5549 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:5751 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:6149 + begin : sv2v_autoblock_39 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:6154 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:6154 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:6351 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_69; + for (_gv_l_69 = 0; _gv_l_69 < pt[982-:8]; _gv_l_69 = _gv_l_69 + 1) begin : BYPASS + localparam l = _gv_l_69; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:7558 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:7956 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:8354 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:8752 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:9150 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:9365 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:9580 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:10002 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:10217 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:10864 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:11064 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:11263 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:11661 + begin : sv2v_autoblock_40 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:11666 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:11666 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:11863 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:12062 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:12658 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:13292 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1270:13491 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 128) begin : size_128 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:46 + ram_be_128x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:6151 + begin : sv2v_autoblock_41 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_70; + for (_gv_l_70 = 0; _gv_l_70 < pt[982-:8]; _gv_l_70 = _gv_l_70 + 1) begin : BYPASS + localparam l = _gv_l_70; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:10219 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:11663 + begin : sv2v_autoblock_42 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:13294 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1276:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:45 + ram_be_128x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:6150 + begin : sv2v_autoblock_43 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_71; + for (_gv_l_71 = 0; _gv_l_71 < pt[982-:8]; _gv_l_71 = _gv_l_71 + 1) begin : BYPASS + localparam l = _gv_l_71; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:10218 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:11662 + begin : sv2v_autoblock_44 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:13293 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1279:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 256) begin : size_256 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:46 + ram_be_256x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:6151 + begin : sv2v_autoblock_45 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_72; + for (_gv_l_72 = 0; _gv_l_72 < pt[982-:8]; _gv_l_72 = _gv_l_72 + 1) begin : BYPASS + localparam l = _gv_l_72; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:10219 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:11663 + begin : sv2v_autoblock_46 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:13294 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1286:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:45 + ram_be_256x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:6150 + begin : sv2v_autoblock_47 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_73; + for (_gv_l_73 = 0; _gv_l_73 < pt[982-:8]; _gv_l_73 = _gv_l_73 + 1) begin : BYPASS + localparam l = _gv_l_73; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:10218 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:11662 + begin : sv2v_autoblock_48 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:13293 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1289:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 512) begin : size_512 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:46 + ram_be_512x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:6151 + begin : sv2v_autoblock_49 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_74; + for (_gv_l_74 = 0; _gv_l_74 < pt[982-:8]; _gv_l_74 = _gv_l_74 + 1) begin : BYPASS + localparam l = _gv_l_74; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:10219 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:11663 + begin : sv2v_autoblock_50 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:13294 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1295:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:45 + ram_be_512x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:6150 + begin : sv2v_autoblock_51 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_75; + for (_gv_l_75 = 0; _gv_l_75 < pt[982-:8]; _gv_l_75 = _gv_l_75 + 1) begin : BYPASS + localparam l = _gv_l_75; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:10218 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:11662 + begin : sv2v_autoblock_52 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:13293 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1298:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 1024) begin : size_1024 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:47 + ram_be_1024x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:3146 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:3544 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:3942 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:4340 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:4539 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:4738 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:5154 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:5552 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:5754 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:6152 + begin : sv2v_autoblock_53 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:6157 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:6157 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:6354 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_76; + for (_gv_l_76 = 0; _gv_l_76 < pt[982-:8]; _gv_l_76 = _gv_l_76 + 1) begin : BYPASS + localparam l = _gv_l_76; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:7561 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:7959 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:8357 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:8755 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:9153 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:9368 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:9583 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:10005 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:10220 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:10867 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:11067 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:11266 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:11664 + begin : sv2v_autoblock_54 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:11669 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:11669 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:11866 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:12065 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:12661 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:13295 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1304:13494 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:46 + ram_be_1024x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:6151 + begin : sv2v_autoblock_55 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_77; + for (_gv_l_77 = 0; _gv_l_77 < pt[982-:8]; _gv_l_77 = _gv_l_77 + 1) begin : BYPASS + localparam l = _gv_l_77; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:10219 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:11663 + begin : sv2v_autoblock_56 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:13294 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1307:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 2048) begin : size_2048 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:47 + ram_be_2048x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:3146 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:3544 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:3942 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:4340 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:4539 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:4738 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:5154 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:5552 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:5754 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:6152 + begin : sv2v_autoblock_57 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:6157 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:6157 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:6354 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_78; + for (_gv_l_78 = 0; _gv_l_78 < pt[982-:8]; _gv_l_78 = _gv_l_78 + 1) begin : BYPASS + localparam l = _gv_l_78; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:7561 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:7959 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:8357 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:8755 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:9153 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:9368 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:9583 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:10005 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:10220 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:10867 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:11067 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:11266 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:11664 + begin : sv2v_autoblock_58 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:11669 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:11669 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:11866 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:12065 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:12661 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:13295 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1313:13494 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:46 + ram_be_2048x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:6151 + begin : sv2v_autoblock_59 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_79; + for (_gv_l_79 = 0; _gv_l_79 < pt[982-:8]; _gv_l_79 = _gv_l_79 + 1) begin : BYPASS + localparam l = _gv_l_79; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:10219 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:11663 + begin : sv2v_autoblock_60 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:13294 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1316:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 4096) begin : size_4096 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:47 + ram_be_4096x104 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[103:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(104 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[103:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:3146 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:3544 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:3942 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:4340 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:4539 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:4738 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:5154 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:5552 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:5754 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:6152 + begin : sv2v_autoblock_61 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:6157 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:6157 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:6354 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_80; + for (_gv_l_80 = 0; _gv_l_80 < pt[982-:8]; _gv_l_80 = _gv_l_80 + 1) begin : BYPASS + localparam l = _gv_l_80; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:7561 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:7959 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:8357 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:8755 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:9153 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:9368 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:9583 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:10005 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:10220 + rvdffe #(.WIDTH(104)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[103:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:10867 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:11067 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:11266 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:11664 + begin : sv2v_autoblock_62 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:11669 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:11669 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:11866 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:12065 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:12661 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:13295 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1322:13494 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:46 + ram_be_4096x52 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[51:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(52 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[51:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:6151 + begin : sv2v_autoblock_63 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_81; + for (_gv_l_81 = 0; _gv_l_81 < pt[982-:8]; _gv_l_81 = _gv_l_81 + 1) begin : BYPASS + localparam l = _gv_l_81; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:10219 + rvdffe #(.WIDTH(52)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[51:0]), + .dout(wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:11663 + begin : sv2v_autoblock_64 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (26 * pt[1060-:7])+:26 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:13294 + wire [26 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1325:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + genvar _gv_i_19; + for (_gv_i_19 = 0; _gv_i_19 < pt[1060-:7]; _gv_i_19 = _gv_i_19 + 1) begin : genblk10 + localparam i = _gv_i_19; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1330:11 + wire [26:1] sv2v_tmp_E1490; + assign sv2v_tmp_E1490 = ic_tag_data_raw_packed[(26 * i) + 25:26 * i]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_E1490; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1331:11 + assign w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36)) : (((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36))) + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:(31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)] = ic_tag_data_raw[(i * 26) + ((31 - pt[991-:9]) >= 0 ? 31 - pt[991-:9] : ((31 - pt[991-:9]) + ((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1332:11 + assign w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 36 : pt[991-:9]) : ((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 36 : pt[991-:9])) + 4)-:5] = ic_tag_data_raw[(i * 26) + 25-:5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1333:11 + rvecc_decode ecc_decode( + .en(~dec_tlu_core_ecc_disable & ic_rd_en_ff), + .sed_ded(1'b1), + .din({11'b00000000000, ic_tag_data_raw[(i * 26) + 20-:21]}), + .ecc_in({2'b00, ic_tag_data_raw[(i * 26) + 25-:5]}), + .dout(ic_tag_corrected_data_unc[(i * 32) + 31-:32]), + .ecc_out(ic_tag_corrected_ecc_unc[(i * 7) + 6-:7]), + .single_ecc_error(ic_tag_single_ecc_error[i]), + .double_ecc_error(ic_tag_double_ecc_error[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1343:11 + assign ic_tag_way_perr[i] = ic_tag_single_ecc_error[i] | ic_tag_double_ecc_error[i]; + end + end + else begin : ECC0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1350:5 + reg [(22 * pt[1060-:7]) - 1:0] ic_tag_data_raw_packed; + wire [(22 * pt[1060-:7]) - 1:0] ic_tag_wren_biten_vec; + wire [(22 * pt[1060-:7]) - 1:0] ic_tag_data_raw_packed_pre; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1351:5 + wire [(pt[982-:8] * (22 * pt[1060-:7])) - 1:0] wb_packeddout_hold; + genvar _gv_i_20; + for (_gv_i_20 = 0; _gv_i_20 < pt[1060-:7]; _gv_i_20 = _gv_i_20 + 1) begin : BITEN + localparam i = _gv_i_20; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1353:9 + assign ic_tag_wren_biten_vec[(22 * i) + 21:22 * i] = {22 {ic_tag_wren_q[i]}}; + end + if (pt[1015-:17] == 32) begin : size_32 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:44 + ram_be_32x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:3143 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:3541 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:3939 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:4337 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:4536 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:4735 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:5151 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:5549 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:5751 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:6149 + begin : sv2v_autoblock_65 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:6154 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:6154 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:6351 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_82; + for (_gv_l_82 = 0; _gv_l_82 < pt[982-:8]; _gv_l_82 = _gv_l_82 + 1) begin : BYPASS + localparam l = _gv_l_82; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:7558 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:7956 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:8354 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:8752 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:9150 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:9365 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:9580 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:10002 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:10217 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:10864 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:11064 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:11263 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:11661 + begin : sv2v_autoblock_66 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:11666 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:11666 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:11863 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:12062 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:12658 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:13292 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1357:13491 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:44 + ram_be_32x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:3143 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:3541 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:3939 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:4337 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:4536 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:4735 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:5151 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:5549 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:5751 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:6149 + begin : sv2v_autoblock_67 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:6154 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:6154 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:6351 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_83; + for (_gv_l_83 = 0; _gv_l_83 < pt[982-:8]; _gv_l_83 = _gv_l_83 + 1) begin : BYPASS + localparam l = _gv_l_83; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:7558 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:7956 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:8354 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:8752 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:9150 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:9365 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:9580 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:10002 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:10217 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:10864 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:11064 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:11263 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:11661 + begin : sv2v_autoblock_68 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:11666 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:11666 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:11863 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:12062 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:12658 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:13292 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1360:13491 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 64) begin : size_64 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:44 + ram_be_64x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:3143 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:3541 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:3939 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:4337 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:4536 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:4735 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:5151 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:5549 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:5751 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:6149 + begin : sv2v_autoblock_69 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:6154 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:6154 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:6351 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_84; + for (_gv_l_84 = 0; _gv_l_84 < pt[982-:8]; _gv_l_84 = _gv_l_84 + 1) begin : BYPASS + localparam l = _gv_l_84; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:7558 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:7956 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:8354 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:8752 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:9150 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:9365 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:9580 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:10002 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:10217 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:10864 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:11064 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:11263 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:11661 + begin : sv2v_autoblock_70 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:11666 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:11666 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:11863 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:12062 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:12658 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:13292 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1366:13491 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:44 + ram_be_64x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:3143 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:3541 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:3939 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:4337 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:4536 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:4735 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:5151 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:5549 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:5751 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:6149 + begin : sv2v_autoblock_71 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:6154 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:6154 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:6351 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_85; + for (_gv_l_85 = 0; _gv_l_85 < pt[982-:8]; _gv_l_85 = _gv_l_85 + 1) begin : BYPASS + localparam l = _gv_l_85; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:7558 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:7956 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:8354 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:8752 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:9150 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:9365 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:9580 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:10002 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:10217 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:10864 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:11064 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:11263 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:11661 + begin : sv2v_autoblock_72 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:11666 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:11666 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:11863 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:12062 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:12658 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:13292 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1369:13491 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 128) begin : size_128 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:45 + ram_be_128x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:6150 + begin : sv2v_autoblock_73 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_86; + for (_gv_l_86 = 0; _gv_l_86 < pt[982-:8]; _gv_l_86 = _gv_l_86 + 1) begin : BYPASS + localparam l = _gv_l_86; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:10218 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:11662 + begin : sv2v_autoblock_74 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:13293 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1375:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:45 + ram_be_128x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:6150 + begin : sv2v_autoblock_75 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_87; + for (_gv_l_87 = 0; _gv_l_87 < pt[982-:8]; _gv_l_87 = _gv_l_87 + 1) begin : BYPASS + localparam l = _gv_l_87; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:10218 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:11662 + begin : sv2v_autoblock_76 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:13293 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1378:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 256) begin : size_256 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:45 + ram_be_256x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:6150 + begin : sv2v_autoblock_77 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_88; + for (_gv_l_88 = 0; _gv_l_88 < pt[982-:8]; _gv_l_88 = _gv_l_88 + 1) begin : BYPASS + localparam l = _gv_l_88; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:10218 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:11662 + begin : sv2v_autoblock_78 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:13293 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1385:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:45 + ram_be_256x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:6150 + begin : sv2v_autoblock_79 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_89; + for (_gv_l_89 = 0; _gv_l_89 < pt[982-:8]; _gv_l_89 = _gv_l_89 + 1) begin : BYPASS + localparam l = _gv_l_89; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:10218 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:11662 + begin : sv2v_autoblock_80 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:13293 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1388:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 512) begin : size_512 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:45 + ram_be_512x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:6150 + begin : sv2v_autoblock_81 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_90; + for (_gv_l_90 = 0; _gv_l_90 < pt[982-:8]; _gv_l_90 = _gv_l_90 + 1) begin : BYPASS + localparam l = _gv_l_90; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:10218 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:11662 + begin : sv2v_autoblock_82 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:13293 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1394:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:45 + ram_be_512x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:3144 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:3542 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:3940 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:4338 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:4537 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:4736 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:5152 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:5550 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:5752 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:6150 + begin : sv2v_autoblock_83 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:6155 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:6155 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:6352 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_91; + for (_gv_l_91 = 0; _gv_l_91 < pt[982-:8]; _gv_l_91 = _gv_l_91 + 1) begin : BYPASS + localparam l = _gv_l_91; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:7559 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:7957 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:8355 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:8753 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:9151 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:9366 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:9581 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:10003 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:10218 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:10865 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:11065 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:11264 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:11662 + begin : sv2v_autoblock_84 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:11667 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:11667 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:11864 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:12063 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:12659 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:13293 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1397:13492 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 1024) begin : size_1024 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:46 + ram_be_1024x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:6151 + begin : sv2v_autoblock_85 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_92; + for (_gv_l_92 = 0; _gv_l_92 < pt[982-:8]; _gv_l_92 = _gv_l_92 + 1) begin : BYPASS + localparam l = _gv_l_92; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:10219 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:11663 + begin : sv2v_autoblock_86 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:13294 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1403:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:46 + ram_be_1024x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:6151 + begin : sv2v_autoblock_87 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_93; + for (_gv_l_93 = 0; _gv_l_93 < pt[982-:8]; _gv_l_93 = _gv_l_93 + 1) begin : BYPASS + localparam l = _gv_l_93; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:10219 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:11663 + begin : sv2v_autoblock_88 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:13294 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1406:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 2048) begin : size_2048 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:46 + ram_be_2048x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:6151 + begin : sv2v_autoblock_89 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_94; + for (_gv_l_94 = 0; _gv_l_94 < pt[982-:8]; _gv_l_94 = _gv_l_94 + 1) begin : BYPASS + localparam l = _gv_l_94; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:10219 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:11663 + begin : sv2v_autoblock_90 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:13294 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1412:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:46 + ram_be_2048x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:6151 + begin : sv2v_autoblock_91 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_95; + for (_gv_l_95 = 0; _gv_l_95 < pt[982-:8]; _gv_l_95 = _gv_l_95 + 1) begin : BYPASS + localparam l = _gv_l_95; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:10219 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:11663 + begin : sv2v_autoblock_92 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:13294 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1415:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + if (pt[1015-:17] == 4096) begin : size_4096 + if (pt[1060-:7] == 4) begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:46 + ram_be_4096x88 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[87:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(88 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[87:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:6151 + begin : sv2v_autoblock_93 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_96; + for (_gv_l_96 = 0; _gv_l_96 < pt[982-:8]; _gv_l_96 = _gv_l_96 + 1) begin : BYPASS + localparam l = _gv_l_96; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:10219 + rvdffe #(.WIDTH(88)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[87:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:11663 + begin : sv2v_autoblock_94 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:13294 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1421:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + else begin : WAYS + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:46 + ram_be_4096x44 ic_way_tag( + .ME(ic_tag_clken_final), + .WE(|ic_tag_wren_q[pt[1060-:7] - 1:0]), + .WEM(ic_tag_wren_biten_vec[43:0]), + .D({pt[1060-:7] {ic_tag_wr_data[(44 / pt[1060-:7]) - 1:0]}}), + .ADR(ic_rw_addr_q[pt[1104-:9]:pt[998-:7]]), + .Q(ic_tag_data_raw_packed_pre[43:0]), + .CLK(clk), + .ROP(), + .TEST1(ic_tag_ext_in_pkt[11]), + .RME(ic_tag_ext_in_pkt[10]), + .RM(ic_tag_ext_in_pkt[9-:4]), + .LS(ic_tag_ext_in_pkt[5]), + .DS(ic_tag_ext_in_pkt[4]), + .SD(ic_tag_ext_in_pkt[3]), + .TEST_RNM(ic_tag_ext_in_pkt[2]), + .BC1(ic_tag_ext_in_pkt[1]), + .BC2(ic_tag_ext_in_pkt[0]) + ); + if (pt[1020-:5] == 1) begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:3145 + assign wrptr_in = (wrptr == (pt[982-:8] - 1) ? {pt[974-:8] {1'sb0}} : wrptr + 1'd1); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:3543 + rvdffs #(.WIDTH(pt[974-:8])) wrptr_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(|write_bypass_en), + .din(wrptr_in), + .dout(wrptr) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:3941 + assign ic_b_sram_en = |ic_tag_clken; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:4339 + assign ic_b_read_en = ic_b_sram_en & |ic_tag_rden_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:4538 + assign ic_b_write_en = ic_b_sram_en & |ic_tag_wren_q; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:4737 + assign ic_tag_clken_final = ic_b_sram_en & ~(|sel_bypass); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:5153 + assign ic_b_rw_addr = {ic_rw_addr_q}; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:5551 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:5753 + any_addr_match = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:6151 + begin : sv2v_autoblock_95 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:6156 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:6156 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:6353 + any_addr_match = any_addr_match | ic_b_addr_match[l]; + end + end + end + genvar _gv_l_97; + for (_gv_l_97 = 0; _gv_l_97 < pt[982-:8]; _gv_l_97 = _gv_l_97 + 1) begin : BYPASS + localparam l = _gv_l_97; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:7560 + assign ic_b_addr_match[l] = (wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)] == ic_b_rw_addr) & index_valid[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:7958 + assign ic_b_clear_en[l] = ic_b_write_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:8356 + assign sel_bypass[l] = ic_b_read_en & ic_b_addr_match[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:8754 + assign write_bypass_en[l] = (ic_b_read_en & ~any_addr_match) & (wrptr == l); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:9152 + rvdff #(.WIDTH(1)) write_bypass_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(write_bypass_en[l]), + .dout(write_bypass_en_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:9367 + rvdffs #(.WIDTH(1)) index_val_ff( + .rst_l(rst_l), + .clk(active_clk), + .en(write_bypass_en[l] | ic_b_clear_en[l]), + .din(~ic_b_clear_en[l]), + .dout(index_valid[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:9582 + rvdff #(.WIDTH(1)) sel_hold_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_bypass[l]), + .dout(sel_bypass_ff[l]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:10004 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) ic_addr_index( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en[l]), + .din(ic_b_rw_addr), + .dout(wb_index_hold[(pt[1104-:9] >= pt[998-:7] ? pt[998-:7] : pt[1104-:9]) + (l * (pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1))+:(pt[1104-:9] >= pt[998-:7] ? (pt[1104-:9] - pt[998-:7]) + 1 : (pt[998-:7] - pt[1104-:9]) + 1)]) + ); + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:10219 + rvdffe #(.WIDTH(44)) rd_data_hold_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_bypass_en_ff[l]), + .din(ic_tag_data_raw_packed_pre[43:0]), + .dout(wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]]) + ); + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:10866 + always @(*) begin + if (_sv2v_0) + ; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:11066 + any_bypass = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:11265 + sel_bypass_data = 1'sb0; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:11663 + begin : sv2v_autoblock_96 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:11668 + reg signed [31:0] l; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:11668 + for (l = 0; l < pt[982-:8]; l = l + 1) + begin + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:11865 + any_bypass = any_bypass | sel_bypass_ff[l]; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:12064 + sel_bypass_data = sel_bypass_data | (sel_bypass_ff[l] ? wb_packeddout_hold[l * (22 * pt[1060-:7])+:22 * pt[1060-:7]] : {26 * pt[1060-:7] {1'sb0}}); + end + end + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:12660 + ic_tag_data_raw_packed = (any_bypass ? sel_bypass_data : ic_tag_data_raw_packed_pre); + end + end + else begin : genblk1 + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:13294 + wire [22 * pt[1060-:7]:1] sv2v_tmp_6F683; + assign sv2v_tmp_6F683 = ic_tag_data_raw_packed_pre; + always @(*) ic_tag_data_raw_packed = sv2v_tmp_6F683; + // Trace: macro expansion of EL2_IC_TAG_PACKED_SRAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1424:13493 + assign ic_tag_clken_final = |ic_tag_clken; + end + end + end + genvar _gv_i_21; + for (_gv_i_21 = 0; _gv_i_21 < pt[1060-:7]; _gv_i_21 = _gv_i_21 + 1) begin : genblk10 + localparam i = _gv_i_21; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1429:11 + wire [26:1] sv2v_tmp_D6754; + assign sv2v_tmp_D6754 = ic_tag_data_raw_packed[(22 * i) + 21:22 * i]; + always @(*) ic_tag_data_raw[i * 26+:26] = sv2v_tmp_D6754; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1430:11 + assign w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36)) : (((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36))) + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:(31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)] = ic_tag_data_raw[(i * 26) + ((31 - pt[991-:9]) >= 0 ? 31 - pt[991-:9] : ((31 - pt[991-:9]) + ((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:((31 - pt[991-:9]) >= 0 ? 32 - pt[991-:9] : pt[991-:9] - 30)]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1431:11 + assign w_tout[(i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 32 : pt[991-:9] + 4)] = ic_tag_data_raw[(i * 26) + 21]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1432:11 + assign w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 36 : pt[991-:9]) : ((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 36 : pt[991-:9])) + 3)-:4] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1435:11 + rveven_paritycheck #(.WIDTH(32 - pt[991-:9])) parcheck( + .data_in(w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36)) : (((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36))) + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:(31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)]), + .parity_in(w_tout[(i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? 32 : pt[991-:9] + 4)]), + .parity_err(ic_tag_way_perr[i]) + ); + end + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1445:4 + always @(*) begin : tag_rd_out + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1446:7 + ictag_debug_rd_data[25:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1447:7 + begin : sv2v_autoblock_97 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1447:13 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1447:13 + for (j = 0; j < pt[1060-:7]; j = j + 1) + begin : debug_rd_out + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1448:10 + ictag_debug_rd_data[25:0] = ictag_debug_rd_data[25:0] | (pt[1125-:5] ? {26 {ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[j * 26+:26] : {4'b0000, {22 {ic_debug_rd_way_en_ff[j]}} & ic_tag_data_raw[(j * 26) + 21-:22]}); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1453:4 + genvar _gv_i_22; + generate + for (_gv_i_22 = 0; _gv_i_22 < pt[1060-:7]; _gv_i_22 = _gv_i_22 + 1) begin : ic_rd_hit_loop + localparam i = _gv_i_22; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1454:7 + assign ic_rd_hit[i] = (w_tout[(36 >= pt[991-:9] ? (i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36)) : (((i * (36 >= pt[991-:9] ? 37 - pt[991-:9] : pt[991-:9] - 35)) + (36 >= pt[991-:9] ? (31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) : pt[991-:9] - ((31 >= pt[991-:9] ? 31 : (31 + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1) - 36))) + (31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)) - 1)-:(31 >= pt[991-:9] ? 32 - pt[991-:9] : pt[991-:9] - 30)] == ic_rw_addr_ff[31:pt[991-:9]]) & ic_tag_valid[i]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_ic_mem.sv:1457:4 + assign ic_tag_perr = |(ic_tag_way_perr[pt[1060-:7] - 1:0] & ic_tag_valid[pt[1060-:7] - 1:0]); + initial _sv2v_0 = 0; +endmodule +module el2_ifu_mem_ctl ( + clk, + active_clk, + free_l2clk, + rst_l, + exu_flush_final, + dec_tlu_flush_lower_wb, + dec_tlu_flush_err_wb, + dec_tlu_i0_commit_cmt, + dec_tlu_force_halt, + ifc_fetch_addr_bf, + ifc_fetch_uncacheable_bf, + ifc_fetch_req_bf, + ifc_fetch_req_bf_raw, + ifc_iccm_access_bf, + ifc_region_acc_fault_bf, + ifc_dma_access_ok, + dec_tlu_fence_i_wb, + ifu_bp_hit_taken_f, + ifu_bp_inst_mask_f, + ifu_miss_state_idle, + ifu_ic_mb_empty, + ic_dma_active, + ic_write_stall, + ifu_pmu_ic_miss, + ifu_pmu_ic_hit, + ifu_pmu_bus_error, + ifu_pmu_bus_busy, + ifu_pmu_bus_trxn, + ifu_axi_awvalid, + ifu_axi_awid, + ifu_axi_awaddr, + ifu_axi_awregion, + ifu_axi_awlen, + ifu_axi_awsize, + ifu_axi_awburst, + ifu_axi_awlock, + ifu_axi_awcache, + ifu_axi_awprot, + ifu_axi_awqos, + ifu_axi_wvalid, + ifu_axi_wdata, + ifu_axi_wstrb, + ifu_axi_wlast, + ifu_axi_bready, + ifu_axi_arvalid, + ifu_axi_arready, + ifu_axi_arid, + ifu_axi_araddr, + ifu_axi_arregion, + ifu_axi_arlen, + ifu_axi_arsize, + ifu_axi_arburst, + ifu_axi_arlock, + ifu_axi_arcache, + ifu_axi_arprot, + ifu_axi_arqos, + ifu_axi_rvalid, + ifu_axi_rready, + ifu_axi_rid, + ifu_axi_rdata, + ifu_axi_rresp, + ifu_bus_clk_en, + dma_iccm_req, + dma_mem_addr, + dma_mem_sz, + dma_mem_write, + dma_mem_wdata, + dma_mem_tag, + iccm_dma_ecc_error, + iccm_dma_rvalid, + iccm_dma_rdata, + iccm_dma_rtag, + iccm_ready, + ic_rw_addr, + ic_wr_en, + ic_rd_en, + ic_wr_data, + ic_rd_data, + ic_debug_rd_data, + ictag_debug_rd_data, + ic_debug_wr_data, + ifu_ic_debug_rd_data, + ic_eccerr, + ic_parerr, + ic_debug_addr, + ic_debug_rd_en, + ic_debug_wr_en, + ic_debug_tag_array, + ic_debug_way, + ic_tag_valid, + ic_rd_hit, + ic_tag_perr, + iccm_rw_addr, + iccm_wren, + iccm_rden, + iccm_wr_data, + iccm_wr_size, + iccm_rd_data, + iccm_rd_data_ecc, + ifu_fetch_val, + ic_hit_f, + ic_access_fault_f, + ic_access_fault_type_f, + iccm_rd_ecc_single_err, + iccm_rd_ecc_double_err, + ic_error_start, + ifu_async_error_start, + iccm_dma_sb_error, + ic_fetch_val_f, + ic_data_f, + ic_premux_data, + ic_sel_premux_data, + dec_tlu_ic_diag_pkt, + dec_tlu_core_ecc_disable, + ifu_ic_debug_rd_data_valid, + iccm_buf_correct_ecc, + iccm_correction_state, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:30:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:31:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:32:4 + input wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:33:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:35:4 + input wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:36:4 + input wire dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:37:4 + input wire dec_tlu_flush_err_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:38:4 + input wire dec_tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:39:4 + input wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:41:4 + input wire [31:1] ifc_fetch_addr_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:42:4 + input wire ifc_fetch_uncacheable_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:43:4 + input wire ifc_fetch_req_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:44:4 + input wire ifc_fetch_req_bf_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:45:4 + input wire ifc_iccm_access_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:46:4 + input wire ifc_region_acc_fault_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:47:4 + input wire ifc_dma_access_ok; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:48:4 + input wire dec_tlu_fence_i_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:49:4 + input wire ifu_bp_hit_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:51:4 + input wire ifu_bp_inst_mask_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:53:4 + output wire ifu_miss_state_idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:54:4 + output wire ifu_ic_mb_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:55:4 + output wire ic_dma_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:56:4 + output wire ic_write_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:59:4 + output wire ifu_pmu_ic_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:60:4 + output wire ifu_pmu_ic_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:61:4 + output wire ifu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:62:4 + output wire ifu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:63:4 + output wire ifu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:67:4 + output wire ifu_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:68:4 + output wire [pt[826-:8] - 1:0] ifu_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:69:4 + output wire [31:0] ifu_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:70:4 + output wire [3:0] ifu_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:71:4 + output wire [7:0] ifu_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:72:4 + output wire [2:0] ifu_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:73:4 + output wire [1:0] ifu_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:74:4 + output wire ifu_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:75:4 + output wire [3:0] ifu_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:76:4 + output wire [2:0] ifu_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:77:4 + output wire [3:0] ifu_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:79:4 + output wire ifu_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:80:4 + output wire [63:0] ifu_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:81:4 + output wire [7:0] ifu_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:82:4 + output wire ifu_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:84:4 + output wire ifu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:87:4 + output wire ifu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:88:4 + input wire ifu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:89:4 + output wire [pt[826-:8] - 1:0] ifu_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:90:4 + output wire [31:0] ifu_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:91:4 + output wire [3:0] ifu_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:92:4 + output wire [7:0] ifu_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:93:4 + output wire [2:0] ifu_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:94:4 + output wire [1:0] ifu_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:95:4 + output wire ifu_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:96:4 + output wire [3:0] ifu_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:97:4 + output wire [2:0] ifu_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:98:4 + output wire [3:0] ifu_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:100:4 + input wire ifu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:101:4 + output wire ifu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:102:4 + input wire [pt[826-:8] - 1:0] ifu_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:103:4 + input wire [63:0] ifu_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:104:4 + input wire [1:0] ifu_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:106:5 + input wire ifu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:109:4 + input wire dma_iccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:110:4 + input wire [31:0] dma_mem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:111:4 + input wire [2:0] dma_mem_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:112:4 + input wire dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:113:4 + input wire [63:0] dma_mem_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:114:4 + input wire [2:0] dma_mem_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:116:4 + output wire iccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:117:4 + output wire iccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:118:4 + output wire [63:0] iccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:119:4 + output wire [2:0] iccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:120:4 + output wire iccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:124:4 + output wire [31:1] ic_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:125:4 + output wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:126:4 + output wire ic_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:128:4 + output wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:129:4 + input wire [63:0] ic_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:130:4 + input wire [70:0] ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:131:4 + input wire [25:0] ictag_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:132:4 + output wire [70:0] ic_debug_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:133:4 + output wire [70:0] ifu_ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:136:4 + input wire [pt[1189-:7] - 1:0] ic_eccerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:137:4 + input wire [pt[1189-:7] - 1:0] ic_parerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:139:4 + output wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:140:4 + output wire ic_debug_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:141:4 + output wire ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:142:4 + output wire ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:143:4 + output wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:146:4 + output wire [pt[1060-:7] - 1:0] ic_tag_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:148:4 + input wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:149:4 + input wire ic_tag_perr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:152:4 + output wire [pt[936-:9] - 1:1] iccm_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:153:4 + output wire iccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:154:4 + output wire iccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:155:4 + output wire [77:0] iccm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:156:4 + output wire [2:0] iccm_wr_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:158:4 + input wire [63:0] iccm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:159:4 + input wire [77:0] iccm_rd_data_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:160:4 + input wire [1:0] ifu_fetch_val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:162:4 + output wire ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:163:4 + output wire [1:0] ic_access_fault_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:164:4 + output wire [1:0] ic_access_fault_type_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:165:4 + output wire iccm_rd_ecc_single_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:166:4 + output wire [1:0] iccm_rd_ecc_double_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:167:4 + output wire ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:169:4 + output wire ifu_async_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:170:4 + output wire iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:171:4 + output wire [1:0] ic_fetch_val_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:172:4 + output wire [31:0] ic_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:173:4 + output wire [63:0] ic_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:174:4 + output wire ic_sel_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:177:4 + // removed localparam type el2_pkg_el2_cache_debug_pkt_t + input wire [89:0] dec_tlu_ic_diag_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:178:4 + input wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:179:4 + output wire ifu_ic_debug_rd_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:180:4 + output wire iccm_buf_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:181:4 + output reg iccm_correction_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:184:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:189:2 + localparam NUM_OF_BEATS = 8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:193:4 + wire [31:3] ifu_ic_req_addr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:194:4 + wire uncacheable_miss_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:195:4 + wire uncacheable_miss_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:199:4 + wire bus_ifu_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:200:4 + wire bus_ifu_wr_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:201:4 + wire bus_ifu_wr_en_ff_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:202:4 + wire bus_ifu_wr_en_ff_wo_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:203:4 + wire [pt[1060-:7] - 1:0] bus_ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:205:4 + wire reset_tag_valid_for_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:208:4 + reg [pt[1027-:7] - 1:0] way_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:209:4 + wire [pt[1027-:7] - 1:0] way_status_mb_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:210:4 + wire [pt[1027-:7] - 1:0] way_status_rep_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:211:4 + wire [pt[1027-:7] - 1:0] way_status_mb_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:212:4 + wire [pt[1027-:7] - 1:0] way_status_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:213:4 + wire [pt[1027-:7] - 1:0] way_status_hit_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:214:4 + wire [pt[1027-:7] - 1:0] way_status_new_w_debug; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:215:4 + wire [pt[1060-:7] - 1:0] tagv_mb_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:216:4 + wire [pt[1060-:7] - 1:0] tagv_mb_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:219:4 + wire ifu_wr_data_comb_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:220:4 + wire ifu_byp_data_err_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:221:4 + wire [1:0] ifu_byp_data_err_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:222:4 + wire ifu_wr_cumulative_err_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:223:4 + wire ifu_wr_cumulative_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:224:4 + wire ifu_wr_data_comb_err_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:225:4 + wire scnd_miss_index_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:228:4 + wire ifc_dma_access_q_ok; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:229:4 + wire ifc_iccm_access_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:230:4 + wire ifc_region_acc_fault_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:231:4 + wire ifc_region_acc_fault_final_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:232:4 + wire [1:0] ifc_bus_acc_fault_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:233:4 + wire ic_act_miss_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:234:4 + wire ic_miss_under_miss_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:235:4 + wire ic_ignore_2nd_miss_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:236:4 + wire ic_act_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:237:4 + wire miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:238:4 + wire [31:1] imb_in; + wire [31:1] imb_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:239:4 + wire [31:pt[1182-:8] + 1] miss_addr_in; + wire [31:pt[1182-:8] + 1] miss_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:240:4 + wire miss_wrap_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:241:4 + wire flush_final_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:242:4 + wire ifc_fetch_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:243:4 + wire ifc_fetch_req_f_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:244:4 + wire fetch_req_f_qual; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:245:4 + wire ifc_fetch_req_qual_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:246:4 + wire [pt[1060-:7] - 1:0] replace_way_mb_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:247:4 + wire last_beat; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:248:4 + wire reset_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:249:4 + wire [pt[1182-:8]:3] ic_req_addr_bits_hi_3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:250:4 + wire [pt[1182-:8]:3] ic_wr_addr_bits_hi_3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:251:4 + wire [31:1] ifu_fetch_addr_int_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:252:4 + wire [31:1] ifu_ic_rw_int_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:253:4 + wire crit_wd_byp_ok_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:254:4 + wire ic_crit_wd_rdy_new_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:255:4 + wire [79:0] ic_byp_data_only_pre_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:256:4 + wire [79:0] ic_byp_data_only_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:257:4 + wire ic_byp_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:258:4 + wire ic_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:259:4 + wire ic_valid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:260:4 + wire reset_all_tags; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:261:4 + wire ic_valid_w_debug; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:263:4 + wire [pt[1060-:7] - 1:0] ifu_tag_wren; + wire [pt[1060-:7] - 1:0] ifu_tag_wren_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:264:4 + wire [pt[1060-:7] - 1:0] ic_debug_tag_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:265:4 + wire [pt[1060-:7] - 1:0] ifu_tag_wren_w_debug; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:266:4 + wire [pt[1060-:7] - 1:0] ic_debug_way_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:267:4 + wire ic_debug_rd_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:268:4 + wire fetch_bf_f_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:269:4 + wire fetch_bf_f_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:270:4 + wire debug_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:271:4 + wire debug_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:273:4 + wire reset_ic_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:274:4 + wire reset_ic_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:275:4 + wire [pt[1182-:8]:1] vaddr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:276:4 + wire [31:1] ifu_status_wr_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:277:4 + wire sel_mb_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:278:4 + wire sel_mb_addr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:279:4 + wire sel_mb_status_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:280:4 + wire [63:0] ic_final_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:282:4 + wire [pt[1104-:9]:pt[998-:7]] ifu_ic_rw_int_addr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:283:4 + wire [pt[1104-:9]:pt[998-:7]] ifu_status_wr_addr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:284:4 + wire [pt[1104-:9]:pt[998-:7]] ifu_ic_rw_int_addr_w_debug; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:285:4 + wire [pt[1104-:9]:pt[998-:7]] ifu_status_wr_addr_w_debug; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:287:4 + wire [pt[1027-:7] - 1:0] way_status_new_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:288:4 + wire way_status_wr_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:289:4 + wire [(pt[1015-:17] * pt[1027-:7]) - 1:0] way_status_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:290:4 + wire [1:0] ic_debug_way_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:292:4 + wire [pt[826-:8] - 1:0] ifu_bus_rid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:294:4 + wire fetch_req_icache_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:295:4 + wire fetch_req_iccm_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:296:4 + wire ic_iccm_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:297:4 + wire fetch_uncacheable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:298:4 + wire way_status_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:299:4 + wire sel_byp_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:300:4 + wire sel_ic_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:301:4 + wire sel_iccm_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:302:4 + wire ic_rd_parity_final_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:303:4 + wire ic_act_miss_f_delayed; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:304:4 + wire bus_ifu_wr_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:305:4 + wire bus_ifu_wr_data_error_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:306:4 + wire way_status_wr_en_w_debug; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:307:4 + wire ic_debug_tag_val_rd_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:308:4 + wire ifu_pmu_ic_miss_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:309:4 + wire ifu_pmu_ic_hit_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:310:4 + wire ifu_pmu_bus_error_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:311:4 + wire ifu_pmu_bus_trxn_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:312:4 + wire ifu_pmu_bus_busy_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:313:4 + wire ic_debug_ict_array_sel_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:314:4 + wire ic_debug_ict_array_sel_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:315:4 + wire debug_data_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:316:4 + wire last_data_recieved_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:317:4 + wire last_data_recieved_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:319:4 + wire ifu_bus_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:320:4 + wire ifu_bus_rvalid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:321:4 + wire ifu_bus_rvalid_unq_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:322:4 + wire ifu_bus_arready_unq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:323:4 + wire ifu_bus_arready_unq_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:324:4 + wire ifu_bus_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:325:4 + wire ifu_bus_arvalid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:326:4 + wire ifu_bus_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:327:4 + wire ifu_bus_arready_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:328:4 + wire [63:0] ifu_bus_rdata_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:329:4 + wire [1:0] ifu_bus_rresp_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:330:4 + wire ifu_bus_rsp_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:331:4 + wire ifu_bus_rsp_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:332:4 + wire [pt[826-:8] - 1:0] ifu_bus_rsp_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:333:4 + wire [63:0] ifu_bus_rsp_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:334:4 + wire [1:0] ifu_bus_rsp_opc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:336:4 + wire [pt[1084-:8] - 1:0] write_fill_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:337:4 + wire [pt[1084-:8] - 1:0] wr_data_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:338:4 + wire [pt[1084-:8] - 1:0] ic_miss_buff_data_valid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:339:4 + wire [pt[1084-:8] - 1:0] ic_miss_buff_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:340:4 + wire [pt[1084-:8] - 1:0] ic_miss_buff_data_error_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:341:4 + wire [pt[1084-:8] - 1:0] ic_miss_buff_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:342:4 + wire [pt[1182-:8]:1] byp_fetch_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:343:4 + wire [pt[1182-:8]:2] byp_fetch_index_0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:344:4 + wire [pt[1182-:8]:2] byp_fetch_index_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:345:4 + wire [pt[1182-:8]:3] byp_fetch_index_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:346:4 + wire [pt[1182-:8]:2] byp_fetch_index_inc_0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:347:4 + wire [pt[1182-:8]:2] byp_fetch_index_inc_1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:348:4 + wire miss_buff_hit_unq_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:349:4 + wire stream_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:350:4 + wire stream_miss_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:351:4 + wire stream_eol_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:352:4 + wire crit_byp_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:353:4 + wire [pt[826-:8] - 1:0] other_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:354:4 + wire [((2 * pt[1084-:8]) * 32) - 1:0] ic_miss_buff_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:355:4 + wire [63:0] ic_miss_buff_half; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:356:4 + wire scnd_miss_req; + wire scnd_miss_req_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:357:4 + wire scnd_miss_req_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:360:4 + wire [pt[936-:9] - 1:2] iccm_ecc_corr_index_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:361:4 + wire [pt[936-:9] - 1:2] iccm_ecc_corr_index_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:362:4 + wire [38:0] iccm_ecc_corr_data_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:363:4 + wire iccm_ecc_write_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:364:4 + wire iccm_rd_ecc_single_err_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:365:4 + wire iccm_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:366:4 + reg perr_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:367:4 + reg miss_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:369:4 + wire busclk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:370:4 + wire busclk_force; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:371:4 + wire busclk_reset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:372:4 + wire bus_ifu_bus_clk_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:373:4 + wire bus_ifu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:375:4 + wire ifc_bus_ic_req_ff_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:376:4 + wire ifu_bus_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:377:4 + wire ifu_bus_cmd_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:379:4 + wire bus_inc_data_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:380:4 + wire bus_reset_data_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:381:4 + wire bus_hold_data_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:383:4 + wire bus_inc_cmd_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:384:4 + wire bus_reset_cmd_beat_cnt_0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:385:4 + wire bus_reset_cmd_beat_cnt_secondlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:386:4 + wire bus_hold_cmd_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:388:4 + wire [pt[1174-:8] - 1:0] bus_new_data_beat_count; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:389:4 + wire [pt[1174-:8] - 1:0] bus_data_beat_count; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:391:4 + wire [pt[1174-:8] - 1:0] bus_new_cmd_beat_count; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:392:4 + wire [pt[1174-:8] - 1:0] bus_cmd_beat_count; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:395:4 + wire [pt[1174-:8] - 1:0] bus_new_rd_addr_count; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:396:4 + wire [pt[1174-:8] - 1:0] bus_rd_addr_count; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:399:4 + wire bus_cmd_sent; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:400:4 + wire bus_last_data_beat; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:403:4 + wire [pt[1060-:7] - 1:0] bus_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:405:4 + wire [pt[1060-:7] - 1:0] bus_wren_last; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:406:4 + wire [pt[1060-:7] - 1:0] wren_reset_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:407:4 + wire ifc_dma_access_ok_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:408:4 + wire ifc_dma_access_ok_prev; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:410:4 + wire bus_cmd_req_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:411:4 + wire bus_cmd_req_hold; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:413:4 + wire second_half_available; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:414:4 + wire write_ic_16_bytes; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:416:4 + wire ifc_region_acc_fault_final_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:417:4 + wire ifc_region_acc_fault_memory_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:418:4 + wire ifc_region_acc_fault_memory_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:419:4 + wire ifc_region_acc_okay; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:421:4 + wire iccm_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:422:4 + wire dma_sb_err_state; + wire dma_sb_err_state_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:423:4 + wire two_byte_instr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:425:4 + // removed localparam type miss_state_t + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:426:4 + wire [2:0] miss_state; + reg [2:0] miss_nxtstate; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:428:4 + // removed localparam type err_stop_state_t + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:429:4 + wire [1:0] err_stop_state; + reg [1:0] err_stop_nxtstate; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:430:4 + reg err_stop_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:431:4 + reg err_stop_fetch; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:433:4 + wire ic_crit_wd_rdy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:435:4 + wire ifu_bp_hit_taken_q_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:436:4 + wire ifu_bus_rvalid_unq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:437:4 + wire bus_cmd_beat_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:444:4 + assign fetch_bf_f_c1_clken = (((ifc_fetch_req_bf_raw | ifc_fetch_req_f) | miss_pending) | exu_flush_final) | scnd_miss_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:445:4 + assign debug_c1_clken = ic_debug_rd_en | ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:448:4 + assign fetch_bf_f_c1_clk = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:449:4 + assign debug_c1_clk = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:458:4 + wire [1:0] iccm_single_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:459:4 + wire dma_iccm_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:460:4 + assign iccm_dma_sb_error = |iccm_single_ecc_error[1:0] & dma_iccm_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:461:4 + assign ifu_async_error_start = iccm_rd_ecc_single_err | ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:464:4 + // removed localparam type perr_state_t + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:465:4 + wire [2:0] perr_state; + reg [2:0] perr_nxtstate; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:468:4 + assign ic_dma_active = (((iccm_correct_ecc | (perr_state == 3'b100)) | (err_stop_state == 2'b11)) | err_stop_fetch) | dec_tlu_flush_err_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:471:4 + assign scnd_miss_req_in = (((((ifu_bus_rsp_valid & bus_ifu_bus_clk_en) & ifu_bus_rsp_ready) & (&bus_new_data_beat_count[pt[1174-:8] - 1:0])) & ~uncacheable_miss_ff) & ((miss_state == 3'b101) | (miss_nxtstate == 3'b101))) & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:475:4 + assign ifu_bp_hit_taken_q_f = ifu_bp_hit_taken_f & ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:483:4 + always @(*) begin : MISS_SM + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:484:7 + miss_nxtstate = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:485:7 + miss_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:486:7 + case (miss_state) + 3'b000: begin : idle + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:488:19 + miss_nxtstate = (ic_act_miss_f & ~exu_flush_final ? 3'b001 : 3'b010); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:489:19 + miss_state_en = ic_act_miss_f & ~dec_tlu_force_halt; + end + 3'b001: begin : crit_byp_ok + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:492:19 + miss_nxtstate = (dec_tlu_force_halt ? 3'b000 : ((ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat))) & uncacheable_miss_ff ? 3'b000 : ((ic_byp_hit_f & ~last_data_recieved_ff) & uncacheable_miss_ff ? 3'b011 : (((~ic_byp_hit_f & ~exu_flush_final) & (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff ? 3'b100 : ((bus_ifu_wr_en_ff & last_beat) & ~uncacheable_miss_ff ? 3'b000 : ((((ic_byp_hit_f & ~exu_flush_final) & ~(bus_ifu_wr_en_ff & last_beat)) & ~ifu_bp_hit_taken_q_f) & ~uncacheable_miss_ff ? 3'b110 : ((((bus_ifu_wr_en_ff & ~exu_flush_final) & ~(bus_ifu_wr_en_ff & last_beat)) & ~ifu_bp_hit_taken_q_f) & ~uncacheable_miss_ff ? 3'b110 : (((~ic_byp_hit_f & ~exu_flush_final) & (bus_ifu_wr_en_ff & last_beat)) & ~uncacheable_miss_ff ? 3'b000 : ((exu_flush_final | ifu_bp_hit_taken_q_f) & ~(bus_ifu_wr_en_ff & last_beat) ? 3'b010 : 3'b000))))))))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:501:19 + miss_state_en = ((((dec_tlu_force_halt | exu_flush_final) | ic_byp_hit_f) | ifu_bp_hit_taken_q_f) | (bus_ifu_wr_en_ff & last_beat)) | (bus_ifu_wr_en_ff & ~uncacheable_miss_ff); + end + 3'b100: begin : crit_wrd_rdy + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:504:19 + miss_nxtstate = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:505:19 + miss_state_en = ((exu_flush_final | flush_final_f) | ic_byp_hit_f) | dec_tlu_force_halt; + end + 3'b110: begin : stream + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:508:19 + miss_nxtstate = ((((exu_flush_final | ifu_bp_hit_taken_q_f) | stream_eol_f) & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? 3'b010 : 3'b000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:509:19 + miss_state_en = (((exu_flush_final | ifu_bp_hit_taken_q_f) | stream_eol_f) | (bus_ifu_wr_en_ff & last_beat)) | dec_tlu_force_halt; + end + 3'b011: begin : miss_wait + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:512:19 + miss_nxtstate = ((exu_flush_final & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? 3'b010 : 3'b000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:513:19 + miss_state_en = (exu_flush_final | (bus_ifu_wr_en_ff & last_beat)) | dec_tlu_force_halt; + end + 3'b010: begin : hit_u_miss + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:516:19 + miss_nxtstate = ((ic_miss_under_miss_f & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? 3'b101 : ((ic_ignore_2nd_miss_f & ~(bus_ifu_wr_en_ff & last_beat)) & ~dec_tlu_force_halt ? 3'b111 : 3'b000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:518:19 + miss_state_en = (((bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f) | ic_ignore_2nd_miss_f) | dec_tlu_force_halt; + end + 3'b101: begin : scnd_miss + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:521:19 + miss_nxtstate = (dec_tlu_force_halt ? 3'b000 : (exu_flush_final ? (bus_ifu_wr_en_ff & last_beat ? 3'b000 : 3'b010) : 3'b001)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:523:19 + miss_state_en = ((bus_ifu_wr_en_ff & last_beat) | exu_flush_final) | dec_tlu_force_halt; + end + 3'b111: begin : stall_scnd_miss + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:526:19 + miss_nxtstate = (dec_tlu_force_halt ? 3'b000 : (exu_flush_final ? (bus_ifu_wr_en_ff & last_beat ? 3'b000 : 3'b010) : 3'b000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:528:19 + miss_state_en = ((bus_ifu_wr_en_ff & last_beat) | exu_flush_final) | dec_tlu_force_halt; + end + default: begin : def_case + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:531:19 + miss_nxtstate = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:532:19 + miss_state_en = 1'b0; + end + endcase + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:536:4 + rvdffs #(.WIDTH(3)) miss_state_ff( + .clk(active_clk), + .din(miss_nxtstate), + .dout({miss_state}), + .en(miss_state_en), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:538:3 + wire sel_hold_imb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:540:4 + assign miss_pending = miss_state != 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:541:4 + assign crit_wd_byp_ok_ff = (miss_state == 3'b001) | ((miss_state == 3'b100) & ~flush_final_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:542:4 + assign sel_hold_imb = ((((miss_pending & ~(bus_ifu_wr_en_ff & last_beat)) & ~((miss_state == 3'b100) & exu_flush_final)) & ~((miss_state == 3'b100) & crit_byp_hit_f)) | ic_act_miss_f) | (miss_pending & (miss_nxtstate == 3'b100)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:547:4 + wire sel_hold_imb_scnd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:548:4 + wire [31:1] imb_scnd_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:549:4 + wire [31:1] imb_scnd_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:550:4 + wire uncacheable_miss_scnd_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:551:4 + wire uncacheable_miss_scnd_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:553:4 + wire [pt[1060-:7] - 1:0] tagv_mb_scnd_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:554:4 + wire [pt[1060-:7] - 1:0] tagv_mb_scnd_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:556:4 + wire [pt[1027-:7] - 1:0] way_status_mb_scnd_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:557:4 + wire [pt[1027-:7] - 1:0] way_status_mb_scnd_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:559:4 + assign sel_hold_imb_scnd = ((miss_state == 3'b101) | ic_miss_under_miss_f) & ~flush_final_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:560:4 + assign way_status_mb_scnd_in[pt[1027-:7] - 1:0] = (miss_state == 3'b101 ? way_status_mb_scnd_ff[pt[1027-:7] - 1:0] : {way_status[pt[1027-:7] - 1:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:561:4 + assign tagv_mb_scnd_in[pt[1060-:7] - 1:0] = (miss_state == 3'b101 ? tagv_mb_scnd_ff[pt[1060-:7] - 1:0] : {ic_tag_valid[pt[1060-:7] - 1:0]} & {pt[1060-:7] {~reset_all_tags & ~exu_flush_final}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:562:4 + assign uncacheable_miss_scnd_in = (sel_hold_imb_scnd ? uncacheable_miss_scnd_ff : ifc_fetch_uncacheable_bf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:565:4 + rvdff_fpga #(.WIDTH(1)) unc_miss_scnd_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din(uncacheable_miss_scnd_in), + .dout(uncacheable_miss_scnd_ff) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:566:4 + rvdffpcie #(.WIDTH(31)) imb_f_scnd_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(fetch_bf_f_c1_clken), + .din({imb_scnd_in[31:1]}), + .dout({imb_scnd_ff[31:1]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:567:4 + rvdff_fpga #(.WIDTH(pt[1027-:7])) mb_rep_wayf2_scnd_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din({way_status_mb_scnd_in[pt[1027-:7] - 1:0]}), + .dout({way_status_mb_scnd_ff[pt[1027-:7] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:568:4 + rvdff_fpga #(.WIDTH(pt[1060-:7])) mb_tagv_scnd_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din({tagv_mb_scnd_in[pt[1060-:7] - 1:0]}), + .dout({tagv_mb_scnd_ff[pt[1060-:7] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:573:4 + assign ic_req_addr_bits_hi_3[pt[1182-:8]:3] = bus_rd_addr_count[pt[1174-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:574:4 + assign ic_wr_addr_bits_hi_3[pt[1182-:8]:3] = ifu_bus_rid_ff[pt[1174-:8] - 1:0] & {pt[1174-:8] {bus_ifu_wr_en_ff}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:580:4 + assign fetch_req_icache_f = (ifc_fetch_req_f & ~ifc_iccm_access_f) & ~ifc_region_acc_fault_final_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:581:4 + assign fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:583:4 + assign ic_iccm_hit_f = fetch_req_iccm_f & ((~miss_pending | (miss_state == 3'b010)) | (miss_state == 3'b110)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:584:4 + assign ic_byp_hit_f = ((crit_byp_hit_f | stream_hit_f) & fetch_req_icache_f) & miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:585:4 + assign ic_act_hit_f = (((|ic_rd_hit[pt[1060-:7] - 1:0] & fetch_req_icache_f) & ~reset_all_tags) & (~miss_pending | (miss_state == 3'b010))) & ~sel_mb_addr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:586:4 + assign ic_act_miss_f = ((((~(|ic_rd_hit[pt[1060-:7] - 1:0]) | reset_all_tags) & fetch_req_icache_f) & ~miss_pending) | scnd_miss_req) & ~ifc_region_acc_fault_final_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:587:4 + assign ic_miss_under_miss_f = ((((((~(|ic_rd_hit[pt[1060-:7] - 1:0]) | reset_all_tags) & fetch_req_icache_f) & (miss_state == 3'b010)) & (imb_ff[31:pt[998-:7]] != ifu_fetch_addr_int_f[31:pt[998-:7]])) & ~uncacheable_miss_ff) & ~sel_mb_addr_ff) & ~ifc_region_acc_fault_final_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:589:4 + assign ic_ignore_2nd_miss_f = (((~(|ic_rd_hit[pt[1060-:7] - 1:0]) | reset_all_tags) & fetch_req_icache_f) & (miss_state == 3'b010)) & ((imb_ff[31:pt[998-:7]] == ifu_fetch_addr_int_f[31:pt[998-:7]]) | uncacheable_miss_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:591:4 + assign ic_hit_f = ((ic_act_hit_f | ic_byp_hit_f) | ic_iccm_hit_f) | (ifc_region_acc_fault_final_f & ifc_fetch_req_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:593:4 + assign uncacheable_miss_in = (scnd_miss_req ? uncacheable_miss_scnd_ff : (sel_hold_imb ? uncacheable_miss_ff : ifc_fetch_uncacheable_bf)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:594:4 + assign imb_in[31:1] = (scnd_miss_req ? imb_scnd_ff[31:1] : (sel_hold_imb ? imb_ff[31:1] : {ifc_fetch_addr_bf[31:1]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:596:4 + assign imb_scnd_in[31:1] = (sel_hold_imb_scnd ? imb_scnd_ff[31:1] : {ifc_fetch_addr_bf[31:1]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:598:4 + assign scnd_miss_index_match = ((imb_ff[pt[1104-:9]:pt[998-:7]] == imb_scnd_ff[pt[1104-:9]:pt[998-:7]]) & scnd_miss_req) & ~ifu_wr_cumulative_err_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:599:4 + assign way_status_mb_in[pt[1027-:7] - 1:0] = (scnd_miss_req & ~scnd_miss_index_match ? way_status_mb_scnd_ff[pt[1027-:7] - 1:0] : (scnd_miss_req & scnd_miss_index_match ? way_status_rep_new[pt[1027-:7] - 1:0] : (miss_pending ? way_status_mb_ff[pt[1027-:7] - 1:0] : {way_status[pt[1027-:7] - 1:0]}))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:603:4 + assign tagv_mb_in[pt[1060-:7] - 1:0] = (scnd_miss_req ? tagv_mb_scnd_ff[pt[1060-:7] - 1:0] | ({pt[1060-:7] {scnd_miss_index_match}} & replace_way_mb_any[pt[1060-:7] - 1:0]) : (miss_pending ? tagv_mb_ff[pt[1060-:7] - 1:0] : {ic_tag_valid[pt[1060-:7] - 1:0]} & {pt[1060-:7] {~reset_all_tags & ~exu_flush_final}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:606:4 + assign reset_ic_in = (miss_pending & ~scnd_miss_req_q) & (reset_all_tags | reset_ic_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:610:4 + rvdffpcie #(.WIDTH(31)) ifu_fetch_addr_f_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(fetch_bf_f_c1_clken), + .din({ifc_fetch_addr_bf[31:1]}), + .dout({ifu_fetch_addr_int_f[31:1]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:612:4 + assign vaddr_f[pt[1182-:8]:1] = ifu_fetch_addr_int_f[pt[1182-:8]:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:614:4 + rvdffpcie #(.WIDTH(31)) imb_f_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(fetch_bf_f_c1_clken), + .din(imb_in[31:1]), + .dout(imb_ff[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:615:4 + rvdff_fpga #(.WIDTH(1)) unc_miss_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din(uncacheable_miss_in), + .dout(uncacheable_miss_ff) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:618:4 + assign miss_addr_in[31:pt[1182-:8] + 1] = (~miss_pending ? imb_ff[31:pt[1182-:8] + 1] : (scnd_miss_req_q ? imb_scnd_ff[31:pt[1182-:8] + 1] : miss_addr[31:pt[1182-:8] + 1])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:622:4 + rvdfflie #( + .WIDTH(31 - pt[1182-:8]), + .LEFT((31 - pt[1182-:8]) - 8) + ) miss_f_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((bus_ifu_bus_clk_en | ic_act_miss_f) | dec_tlu_force_halt), + .din({miss_addr_in[31:pt[1182-:8] + 1]}), + .dout({miss_addr[31:pt[1182-:8] + 1]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:628:4 + rvdff_fpga #(.WIDTH(pt[1027-:7])) mb_rep_wayf2_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din({way_status_mb_in[pt[1027-:7] - 1:0]}), + .dout({way_status_mb_ff[pt[1027-:7] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:629:4 + rvdff_fpga #(.WIDTH(pt[1060-:7])) mb_tagv_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din({tagv_mb_in[pt[1060-:7] - 1:0]}), + .dout({tagv_mb_ff[pt[1060-:7] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:631:4 + assign ifc_fetch_req_qual_bf = (ifc_fetch_req_bf & ~((miss_state == 3'b100) & flush_final_f)) & ~stream_miss_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:633:4 + assign ifc_fetch_req_f = ifc_fetch_req_f_raw & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:635:4 + rvdff_fpga #(.WIDTH(1)) ifu_iccm_acc_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din(ifc_iccm_access_bf), + .dout(ifc_iccm_access_f) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:636:4 + rvdff_fpga #(.WIDTH(1)) ifu_iccm_reg_acc_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din(ifc_region_acc_fault_final_bf), + .dout(ifc_region_acc_fault_final_f) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:637:4 + rvdff_fpga #(.WIDTH(1)) rgn_acc_ff( + .rst_l(rst_l), + .clk(fetch_bf_f_c1_clk), + .clken(fetch_bf_f_c1_clken), + .rawclk(clk), + .din(ifc_region_acc_fault_bf), + .dout(ifc_region_acc_fault_f) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:640:4 + assign ifu_ic_req_addr_f[31:3] = {miss_addr[31:pt[1182-:8] + 1], ic_req_addr_bits_hi_3[pt[1182-:8]:3]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:641:4 + assign ifu_ic_mb_empty = (((miss_state == 3'b010) | (miss_state == 3'b110)) & ~(bus_ifu_wr_en_ff & last_beat)) | ~miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:642:4 + assign ifu_miss_state_idle = miss_state == 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:645:4 + assign sel_mb_addr = ((miss_pending & write_ic_16_bytes) & ~uncacheable_miss_ff) | reset_tag_valid_for_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:646:4 + assign ifu_ic_rw_int_addr[31:1] = ({31 {sel_mb_addr}} & {imb_ff[31:pt[1182-:8] + 1], ic_wr_addr_bits_hi_3[pt[1182-:8]:3], imb_ff[2:1]}) | ({31 {~sel_mb_addr}} & ifc_fetch_addr_bf[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:649:4 + assign sel_mb_status_addr = ((((miss_pending & write_ic_16_bytes) & ~uncacheable_miss_ff) & last_beat) & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:650:4 + assign ifu_status_wr_addr[31:1] = ({31 {sel_mb_status_addr}} & {imb_ff[31:pt[1182-:8] + 1], ic_wr_addr_bits_hi_3[pt[1182-:8]:3], imb_ff[2:1]}) | ({31 {~sel_mb_status_addr}} & ifu_fetch_addr_int_f[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:654:3 + assign ic_rw_addr[31:1] = ifu_ic_rw_int_addr[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:657:1 + generate + if (pt[1125-:5] == 1) begin : icache_ecc_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:658:4 + wire [6:0] ic_wr_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:659:4 + wire [6:0] ic_miss_buff_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:660:4 + wire [141:0] ic_wr_16bytes_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:661:4 + wire [70:0] ifu_ic_debug_rd_data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:663:17 + rvecc_encode_64 ic_ecc_encode_64_bus( + .din(ifu_bus_rdata_ff[63:0]), + .ecc_out(ic_wr_ecc[6:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:666:17 + rvecc_encode_64 ic_ecc_encode_64_buff( + .din(ic_miss_buff_half[63:0]), + .ecc_out(ic_miss_buff_ecc[6:0]) + ); + genvar _gv_i_23; + for (_gv_i_23 = 0; _gv_i_23 < pt[1189-:7]; _gv_i_23 = _gv_i_23 + 1) begin : ic_wr_data_loop + localparam i = _gv_i_23; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:671:7 + assign ic_wr_data[(i * 71) + 70-:71] = ic_wr_16bytes_data[(71 * i) + 70:71 * i]; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:675:4 + assign ic_debug_wr_data[70:0] = {dec_tlu_ic_diag_pkt[89:19]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:676:4 + assign ic_error_start = (|ic_eccerr[pt[1189-:7] - 1:0] & ic_act_hit_f) | ic_rd_parity_final_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:680:3 + assign ifu_ic_debug_rd_data_in[70:0] = (ic_debug_ict_array_sel_ff ? {2'b00, ictag_debug_rd_data[25:21], 32'b00000000000000000000000000000000, ictag_debug_rd_data[20:0], {7 - pt[1027-:7] {1'b0}}, way_status[pt[1027-:7] - 1:0], 3'b000, ic_debug_tag_val_rd_out} : ic_debug_rd_data[70:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:683:3 + rvdffe #(.WIDTH(71)) ifu_debug_data_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(debug_data_clken), + .din({ifu_ic_debug_rd_data_in[70:0]}), + .dout({ifu_ic_debug_rd_data[70:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:693:3 + assign ic_wr_16bytes_data[141:0] = (ifu_bus_rid_ff[0] ? {ic_wr_ecc[6:0], ifu_bus_rdata_ff[63:0], ic_miss_buff_ecc[6:0], ic_miss_buff_half[63:0]} : {ic_miss_buff_ecc[6:0], ic_miss_buff_half[63:0], ic_wr_ecc[6:0], ifu_bus_rdata_ff[63:0]}); + end + else begin : icache_parity_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:699:4 + wire [3:0] ic_wr_parity; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:700:4 + wire [3:0] ic_miss_buff_parity; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:701:4 + wire [135:0] ic_wr_16bytes_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:702:4 + wire [70:0] ifu_ic_debug_rd_data_in; + genvar _gv_i_24; + for (_gv_i_24 = 0; _gv_i_24 < 4; _gv_i_24 = _gv_i_24 + 1) begin : DATA_PGEN + localparam i = _gv_i_24; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:704:8 + rveven_paritygen #(.WIDTH(16)) par_bus( + .data_in(ifu_bus_rdata_ff[(16 * i) + 15:16 * i]), + .parity_out(ic_wr_parity[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:706:8 + rveven_paritygen #(.WIDTH(16)) par_buff( + .data_in(ic_miss_buff_half[(16 * i) + 15:16 * i]), + .parity_out(ic_miss_buff_parity[i]) + ); + end + genvar _gv_i_25; + for (_gv_i_25 = 0; _gv_i_25 < pt[1189-:7]; _gv_i_25 = _gv_i_25 + 1) begin : ic_wr_data_loop + localparam i = _gv_i_25; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:712:7 + assign ic_wr_data[(i * 71) + 70-:71] = {3'b000, ic_wr_16bytes_data[(68 * i) + 67:68 * i]}; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:719:4 + assign ic_debug_wr_data[70:0] = {dec_tlu_ic_diag_pkt[89:19]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:720:4 + assign ic_error_start = (|ic_parerr[pt[1189-:7] - 1:0] & ic_act_hit_f) | ic_rd_parity_final_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:722:4 + assign ifu_ic_debug_rd_data_in[70:0] = (ic_debug_ict_array_sel_ff ? {6'b000000, ictag_debug_rd_data[21], 32'b00000000000000000000000000000000, ictag_debug_rd_data[20:0], {7 - pt[1027-:7] {1'b0}}, way_status[pt[1027-:7] - 1:0], 3'b000, ic_debug_tag_val_rd_out} : ic_debug_rd_data[70:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:725:4 + rvdffe #(.WIDTH(71)) ifu_debug_data_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(debug_data_clken), + .din({ifu_ic_debug_rd_data_in[70:0]}), + .dout({ifu_ic_debug_rd_data[70:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:735:4 + assign ic_wr_16bytes_data[135:0] = (ifu_bus_rid_ff[0] ? {ic_wr_parity[3:0], ifu_bus_rdata_ff[63:0], ic_miss_buff_parity[3:0], ic_miss_buff_half[63:0]} : {ic_miss_buff_parity[3:0], ic_miss_buff_half[63:0], ic_wr_parity[3:0], ifu_bus_rdata_ff[63:0]}); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:741:3 + assign ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:742:3 + assign ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & ~reset_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:743:3 + assign ifu_wr_cumulative_err_data = ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:746:3 + assign sel_byp_data = (ic_crit_wd_rdy | (miss_state == 3'b110)) | (miss_state == 3'b001); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:747:3 + assign sel_ic_data = (~(((ic_crit_wd_rdy | (miss_state == 3'b110)) | (miss_state == 3'b001)) | (miss_state == 3'b011)) & ~fetch_req_iccm_f) & ~ifc_region_acc_fault_final_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:749:2 + generate + if (pt[922-:5] == 1) begin : iccm_icache + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:750:3 + assign sel_iccm_data = fetch_req_iccm_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:752:3 + assign ic_final_data[63:0] = {64 {(sel_byp_data | sel_iccm_data) | sel_ic_data}} & {ic_rd_data[63:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:754:3 + assign ic_premux_data[63:0] = ({64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]}) | ({64 {sel_iccm_data}} & {iccm_rd_data[63:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:757:3 + assign ic_sel_premux_data = sel_iccm_data | sel_byp_data; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:760:1 + generate + if (pt[900-:5] == 1) begin : iccm_only + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:761:3 + assign sel_iccm_data = fetch_req_iccm_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:762:3 + assign ic_final_data[63:0] = ({64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]}) | ({64 {sel_iccm_data}} & {iccm_rd_data[63:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:764:3 + assign ic_premux_data = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:765:3 + assign ic_sel_premux_data = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:768:1 + generate + if (pt[1053-:5] == 1) begin : icache_only + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:769:3 + assign ic_final_data[63:0] = {64 {sel_byp_data | sel_ic_data}} & {ic_rd_data[63:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:770:3 + assign ic_premux_data[63:0] = {64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:771:3 + assign ic_sel_premux_data = sel_byp_data; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:775:1 + generate + if (pt[140-:5] == 1) begin : no_iccm_no_icache + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:776:3 + assign ic_final_data[63:0] = {64 {sel_byp_data}} & {ic_byp_data_only_new[63:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:777:3 + assign ic_premux_data = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:778:3 + assign ic_sel_premux_data = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:782:3 + assign ifc_bus_acc_fault_f[1:0] = {2 {ic_byp_hit_f}} & ifu_byp_data_err_f[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:783:3 + assign ic_data_f[31:0] = ic_final_data[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:787:1 + assign fetch_req_f_qual = ic_hit_f & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:788:1 + assign ic_access_fault_f[1:0] = ({2 {ifc_region_acc_fault_final_f}} | ifc_bus_acc_fault_f[1:0]) & {2 {~exu_flush_final}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:789:1 + assign ic_access_fault_type_f[1:0] = (|iccm_rd_ecc_double_err ? 2'b01 : (ifc_region_acc_fault_f ? 2'b10 : (ifc_region_acc_fault_memory_f ? 2'b11 : 2'b00))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:795:1 + assign ic_fetch_val_f[1] = ((fetch_req_f_qual & ifu_bp_inst_mask_f) & ~(vaddr_f[pt[1182-:8]:1] == {pt[1182-:8] {1'b1}})) & (err_stop_state != 2'b10); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:796:1 + assign ic_fetch_val_f[0] = fetch_req_f_qual; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:797:1 + assign two_byte_instr = ic_data_f[1:0] != 2'b11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:802:6 + wire [63:0] ic_miss_buff_data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:803:6 + assign ic_miss_buff_data_in[63:0] = ifu_bus_rsp_rdata[63:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:805:6 + genvar _gv_i_26; + function automatic signed [pt[826-:8] - 1:0] sv2v_cast_B455E_signed; + input reg signed [pt[826-:8] - 1:0] inp; + sv2v_cast_B455E_signed = inp; + endfunction + generate + for (_gv_i_26 = 0; _gv_i_26 < pt[1084-:8]; _gv_i_26 = _gv_i_26 + 1) begin : wr_flop + localparam i = _gv_i_26; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:807:9 + assign write_fill_data[i] = bus_ifu_wr_en & (sv2v_cast_B455E_signed(i) == ifu_bus_rsp_tag[pt[826-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:809:9 + rvdffe #(.WIDTH(32)) byp_data_0_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_fill_data[i]), + .din(ic_miss_buff_data_in[31:0]), + .dout(ic_miss_buff_data[((i * 2) * 32) + 31-:32]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:815:9 + rvdffe #(.WIDTH(32)) byp_data_1_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(write_fill_data[i]), + .din(ic_miss_buff_data_in[63:32]), + .dout(ic_miss_buff_data[(((i * 2) + 1) * 32) + 31-:32]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:821:9 + assign ic_miss_buff_data_valid_in[i] = (write_fill_data[i] ? 1'b1 : ic_miss_buff_data_valid[i] & ~ic_act_miss_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:823:9 + rvdff #(.WIDTH(1)) byp_data_valid_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(ic_miss_buff_data_valid_in[i]), + .dout(ic_miss_buff_data_valid[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:828:9 + assign ic_miss_buff_data_error_in[i] = (write_fill_data[i] ? bus_ifu_wr_data_error : ic_miss_buff_data_error[i] & ~ic_act_miss_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:830:9 + rvdff #(.WIDTH(1)) byp_data_error_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(ic_miss_buff_data_error_in[i]), + .dout(ic_miss_buff_data_error[i]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:839:4 + wire [pt[1182-:8]:1] bypass_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:840:4 + wire [pt[1182-:8]:3] bypass_index_5_3_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:841:4 + wire bypass_data_ready_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:842:4 + wire ic_crit_wd_rdy_new_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:844:4 + assign bypass_index[pt[1182-:8]:1] = imb_ff[pt[1182-:8]:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:845:4 + assign bypass_index_5_3_inc[pt[1182-:8]:3] = bypass_index[pt[1182-:8]:3] + 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:848:4 + assign bypass_data_ready_in = (((((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & ~bypass_index[2]) & ~bypass_index[1]) | ((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & ~bypass_index[2]) & bypass_index[1])) | ((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & bypass_index[2]) & ~bypass_index[1])) | (((ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & ic_miss_buff_data_valid_in[bypass_index_5_3_inc[pt[1182-:8]:3]]) & bypass_index[2]) & bypass_index[1])) | (ic_miss_buff_data_valid_in[bypass_index[pt[1182-:8]:3]] & (bypass_index[pt[1182-:8]:3] == {pt[1182-:8] {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:856:4 + assign ic_crit_wd_rdy_new_in = (((((bypass_data_ready_in & crit_wd_byp_ok_ff) & uncacheable_miss_ff) & ~exu_flush_final) & ~ifu_bp_hit_taken_q_f) | (((crit_wd_byp_ok_ff & ~uncacheable_miss_ff) & ~exu_flush_final) & ~ifu_bp_hit_taken_q_f)) | (((ic_crit_wd_rdy_new_ff & ~fetch_req_icache_f) & crit_wd_byp_ok_ff) & ~exu_flush_final); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:861:3 + assign byp_fetch_index[pt[1182-:8]:1] = ifu_fetch_addr_int_f[pt[1182-:8]:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:862:3 + assign byp_fetch_index_0[pt[1182-:8]:2] = {ifu_fetch_addr_int_f[pt[1182-:8]:3], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:863:3 + assign byp_fetch_index_1[pt[1182-:8]:2] = {ifu_fetch_addr_int_f[pt[1182-:8]:3], 1'b1}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:864:3 + assign byp_fetch_index_inc[pt[1182-:8]:3] = ifu_fetch_addr_int_f[pt[1182-:8]:3] + 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:865:3 + assign byp_fetch_index_inc_0[pt[1182-:8]:2] = {byp_fetch_index_inc[pt[1182-:8]:3], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:866:3 + assign byp_fetch_index_inc_1[pt[1182-:8]:2] = {byp_fetch_index_inc[pt[1182-:8]:3], 1'b1}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:868:3 + assign ifu_byp_data_err_new = ((((~ifu_fetch_addr_int_f[2] & ~ifu_fetch_addr_int_f[1]) & ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]]) | ((~ifu_fetch_addr_int_f[2] & ifu_fetch_addr_int_f[1]) & ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]])) | ((ifu_fetch_addr_int_f[2] & ~ifu_fetch_addr_int_f[1]) & ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]])) | ((ifu_fetch_addr_int_f[2] & ifu_fetch_addr_int_f[1]) & (ic_miss_buff_data_error[byp_fetch_index_inc[pt[1182-:8]:3]] | ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:873:3 + assign ifu_byp_data_err_f[1:0] = (ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]] ? 2'b11 : (((ifu_fetch_addr_int_f[2] & ifu_fetch_addr_int_f[1]) & ~ic_miss_buff_data_error[byp_fetch_index[pt[1182-:8]:3]]) & (~miss_wrap_f & ic_miss_buff_data_error[byp_fetch_index_inc[pt[1182-:8]:3]]) ? 2'b10 : 2'b00)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:880:3 + assign ic_byp_data_only_pre_new[79:0] = ({80 {~ifu_fetch_addr_int_f[2]}} & {ic_miss_buff_data[(byp_fetch_index_inc_0 * 32) + 15-:16], ic_miss_buff_data[(byp_fetch_index_1 * 32) + 31-:32], ic_miss_buff_data[(byp_fetch_index_0 * 32) + 31-:32]}) | ({80 {ifu_fetch_addr_int_f[2]}} & {ic_miss_buff_data[(byp_fetch_index_inc_1 * 32) + 15-:16], ic_miss_buff_data[(byp_fetch_index_inc_0 * 32) + 31-:32], ic_miss_buff_data[(byp_fetch_index_1 * 32) + 31-:32]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:883:3 + assign ic_byp_data_only_new[79:0] = (~ifu_fetch_addr_int_f[1] ? {ic_byp_data_only_pre_new[79:0]} : {16'b0000000000000000, ic_byp_data_only_pre_new[79:16]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:886:3 + assign miss_wrap_f = imb_ff[pt[998-:7]] != ifu_fetch_addr_int_f[pt[998-:7]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:888:3 + assign miss_buff_hit_unq_f = (((((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & ~byp_fetch_index[2]) & ~byp_fetch_index[1]) | ((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & ~byp_fetch_index[2]) & byp_fetch_index[1])) | ((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & byp_fetch_index[2]) & ~byp_fetch_index[1])) | (((ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & ic_miss_buff_data_valid[byp_fetch_index_inc[pt[1182-:8]:3]]) & byp_fetch_index[2]) & byp_fetch_index[1])) | (ic_miss_buff_data_valid[byp_fetch_index[pt[1182-:8]:3]] & (byp_fetch_index[pt[1182-:8]:3] == {pt[1174-:8] {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:894:3 + assign stream_hit_f = (miss_buff_hit_unq_f & ~miss_wrap_f) & (miss_state == 3'b110); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:895:3 + assign stream_miss_f = (~(miss_buff_hit_unq_f & ~miss_wrap_f) & (miss_state == 3'b110)) & ifc_fetch_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:896:3 + assign stream_eol_f = ((byp_fetch_index[pt[1182-:8]:2] == {pt[1174-:8] + 1 {1'b1}}) & ifc_fetch_req_f) & stream_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:898:3 + assign crit_byp_hit_f = miss_buff_hit_unq_f & ((miss_state == 3'b100) | (miss_state == 3'b001)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:904:1 + assign other_tag[pt[826-:8] - 1:0] = {ifu_bus_rid_ff[pt[826-:8] - 1:1], ~ifu_bus_rid_ff[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:905:1 + assign second_half_available = ic_miss_buff_data_valid[other_tag]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:906:1 + assign write_ic_16_bytes = second_half_available & bus_ifu_wr_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:907:1 + assign ic_miss_buff_half[63:0] = {ic_miss_buff_data[{other_tag, 1'b1} * 32+:32], ic_miss_buff_data[{other_tag, 1'b0} * 32+:32]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:915:1 + assign ic_rd_parity_final_err = (((ic_tag_perr & ~exu_flush_final) & sel_ic_data) & ~(ifc_region_acc_fault_final_f | (|ifc_bus_acc_fault_f))) & (((fetch_req_icache_f & ~reset_all_tags) & (~miss_pending | (miss_state == 3'b010))) & ~sel_mb_addr_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:918:1 + wire [pt[1060-:7] - 1:0] perr_err_inv_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:919:1 + wire [pt[1104-:9]:pt[998-:7]] perr_ic_index_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:920:1 + reg perr_sel_invalidate; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:921:1 + reg perr_sb_write_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:925:4 + rvdffe #( + .WIDTH((pt[1104-:9] - pt[998-:7]) + 1), + .OVERRIDE(1) + ) perr_dat_ff( + .din(ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]]), + .dout(perr_ic_index_ff[pt[1104-:9]:pt[998-:7]]), + .en(perr_sb_write_status), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:927:4 + assign perr_err_inv_way[pt[1060-:7] - 1:0] = {pt[1060-:7] {perr_sel_invalidate}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:928:4 + assign iccm_correct_ecc = perr_state == 3'b011; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:929:4 + assign dma_sb_err_state = perr_state == 3'b100; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:930:4 + assign iccm_buf_correct_ecc = iccm_correct_ecc & ~dma_sb_err_state_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:942:4 + always @(*) begin : ERROR_SM + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:943:7 + perr_nxtstate = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:944:7 + perr_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:945:7 + perr_sb_write_status = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:946:7 + perr_sel_invalidate = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:948:7 + case (perr_state) + 3'b000: begin : err_idle + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:950:19 + perr_nxtstate = (iccm_dma_sb_error ? 3'b100 : (ic_error_start & ~exu_flush_final ? 3'b001 : 3'b010)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:951:19 + perr_state_en = (((iccm_error_start | ic_error_start) & ~dec_tlu_flush_lower_wb) | iccm_dma_sb_error) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:952:19 + perr_sb_write_status = perr_state_en; + end + 3'b001: begin : icache_wff + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:955:19 + perr_nxtstate = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:956:19 + perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:957:19 + perr_sel_invalidate = dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb; + end + 3'b010: begin : ecc_wff + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:960:19 + perr_nxtstate = ((~dec_tlu_flush_err_wb & dec_tlu_flush_lower_wb) | dec_tlu_force_halt ? 3'b000 : 3'b011); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:961:19 + perr_state_en = dec_tlu_flush_lower_wb | dec_tlu_force_halt; + end + 3'b100: begin : dma_sb_ecc + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:964:18 + perr_nxtstate = (dec_tlu_force_halt ? 3'b000 : 3'b011); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:965:18 + perr_state_en = 1'b1; + end + 3'b011: begin : ecc_corr + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:968:19 + perr_nxtstate = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:969:19 + perr_state_en = 1'b1; + end + default: begin : def_case + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:972:19 + perr_nxtstate = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:973:19 + perr_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:974:19 + perr_sb_write_status = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:975:19 + perr_sel_invalidate = 1'b0; + end + endcase + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:980:4 + rvdffs #(.WIDTH(3)) perr_state_ff( + .clk(active_clk), + .din(perr_nxtstate), + .dout({perr_state}), + .en(perr_state_en), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:987:4 + always @(*) begin : ERROR_STOP_FETCH + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:988:7 + err_stop_nxtstate = 2'b00; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:989:7 + err_stop_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:990:7 + err_stop_fetch = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:991:7 + iccm_correction_state = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:993:7 + case (err_stop_state) + 2'b00: begin : err_stop_idle + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:995:19 + err_stop_nxtstate = 2'b01; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:996:19 + err_stop_state_en = (dec_tlu_flush_err_wb & (perr_state == 3'b010)) & ~dec_tlu_force_halt; + end + 2'b01: begin : err_fetch1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:999:19 + err_stop_nxtstate = ((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt ? 2'b00 : ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr) ? 2'b11 : (ifu_fetch_val[0] ? 2'b10 : 2'b01))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1000:19 + err_stop_state_en = (((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | ifu_fetch_val[0]) | ifu_bp_hit_taken_q_f) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1001:19 + err_stop_fetch = ((ifu_fetch_val[1:0] == 2'b11) | (ifu_fetch_val[0] & two_byte_instr)) & ~(exu_flush_final | dec_tlu_i0_commit_cmt); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1002:19 + iccm_correction_state = 1'b1; + end + 2'b10: begin : err_fetch2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1006:19 + err_stop_nxtstate = ((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt ? 2'b00 : (ifu_fetch_val[0] ? 2'b11 : 2'b10)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1007:19 + err_stop_state_en = ((dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | ifu_fetch_val[0]) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1008:19 + err_stop_fetch = (ifu_fetch_val[0] & ~exu_flush_final) & ~dec_tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1009:19 + iccm_correction_state = 1'b1; + end + 2'b11: begin : ecc_wff + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1013:19 + err_stop_nxtstate = (((dec_tlu_flush_lower_wb & ~dec_tlu_flush_err_wb) | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt ? 2'b00 : (dec_tlu_flush_err_wb ? 2'b01 : 2'b11)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1014:19 + err_stop_state_en = (dec_tlu_flush_lower_wb | dec_tlu_i0_commit_cmt) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1015:19 + err_stop_fetch = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1016:19 + iccm_correction_state = 1'b1; + end + default: begin : def_case + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1020:19 + err_stop_nxtstate = 2'b00; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1021:19 + err_stop_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1022:19 + err_stop_fetch = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1023:19 + iccm_correction_state = 1'b1; + end + endcase + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1028:4 + rvdffs #(.WIDTH(2)) err_stop_state_ff( + .clk(active_clk), + .din(err_stop_nxtstate), + .dout({err_stop_state}), + .en(err_stop_state_en), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1032:4 + assign bus_ifu_bus_clk_en = ifu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1035:4 + assign busclk = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1036:4 + assign busclk_force = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1044:4 + assign scnd_miss_req = scnd_miss_req_q & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1046:4 + assign ifc_bus_ic_req_ff_in = (((ic_act_miss_f | bus_cmd_req_hold) | ifu_bus_cmd_valid) & ~dec_tlu_force_halt) & ~((((bus_cmd_beat_count == {pt[1174-:8] {1'b1}}) & ifu_bus_cmd_valid) & ifu_bus_cmd_ready) & miss_pending); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1048:4 + rvdff_fpga #(.WIDTH(1)) bus_ic_req_ff2( + .rst_l(rst_l), + .clk(busclk_force), + .clken(bus_ifu_bus_clk_en | dec_tlu_force_halt), + .rawclk(clk), + .din(ifc_bus_ic_req_ff_in), + .dout(ifu_bus_cmd_valid) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1050:4 + assign bus_cmd_req_in = ((ic_act_miss_f | bus_cmd_req_hold) & ~bus_cmd_sent) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1056:5 + assign ifu_axi_arvalid = ifu_bus_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1057:5 + function automatic [pt[826-:8] - 1:0] sv2v_cast_B455E; + input reg [pt[826-:8] - 1:0] inp; + sv2v_cast_B455E = inp; + endfunction + assign ifu_axi_arid[pt[826-:8] - 1:0] = sv2v_cast_B455E(bus_rd_addr_count[pt[1174-:8] - 1:0]) & {pt[826-:8] {ifu_bus_cmd_valid}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1058:5 + assign ifu_axi_araddr[31:0] = {ifu_ic_req_addr_f[31:3], 3'b000} & {32 {ifu_bus_cmd_valid}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1059:5 + assign ifu_axi_arsize[2:0] = 3'b011; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1060:5 + assign ifu_axi_arprot[2:0] = 3'b101; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1061:5 + assign ifu_axi_arcache[3:0] = 4'b1111; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1062:5 + assign ifu_axi_arregion[3:0] = ifu_ic_req_addr_f[31:28]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1063:5 + assign ifu_axi_arlen[7:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1064:5 + assign ifu_axi_arburst[1:0] = 2'b01; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1065:5 + assign ifu_axi_arqos[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1066:5 + assign ifu_axi_arlock = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1067:5 + assign ifu_axi_rready = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1070:5 + assign ifu_axi_awvalid = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1071:5 + assign ifu_axi_awid[pt[826-:8] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1072:5 + assign ifu_axi_awaddr[31:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1073:5 + assign ifu_axi_awsize[2:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1074:5 + assign ifu_axi_awprot[2:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1075:5 + assign ifu_axi_awcache[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1076:5 + assign ifu_axi_awregion[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1077:5 + assign ifu_axi_awlen[7:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1078:5 + assign ifu_axi_awburst[1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1079:5 + assign ifu_axi_awqos[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1080:5 + assign ifu_axi_awlock = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1082:5 + assign ifu_axi_wvalid = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1083:5 + assign ifu_axi_wstrb[7:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1084:5 + assign ifu_axi_wdata[63:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1085:5 + assign ifu_axi_wlast = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1086:5 + assign ifu_axi_bready = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1089:4 + assign ifu_bus_arready_unq = ifu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1090:4 + assign ifu_bus_rvalid_unq = ifu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1091:4 + assign ifu_bus_arvalid = ifu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1093:4 + rvdff_fpga #(.WIDTH(1)) bus_rdy_ff( + .rst_l(rst_l), + .clk(busclk), + .clken(bus_ifu_bus_clk_en), + .rawclk(clk), + .din(ifu_bus_arready_unq), + .dout(ifu_bus_arready_unq_ff) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1094:4 + rvdff_fpga #(.WIDTH(1)) bus_rsp_vld_ff( + .rst_l(rst_l), + .clk(busclk), + .clken(bus_ifu_bus_clk_en), + .rawclk(clk), + .din(ifu_bus_rvalid_unq), + .dout(ifu_bus_rvalid_unq_ff) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1095:4 + rvdff_fpga #(.WIDTH(1)) bus_cmd_ff( + .rst_l(rst_l), + .clk(busclk), + .clken(bus_ifu_bus_clk_en), + .rawclk(clk), + .din(ifu_bus_arvalid), + .dout(ifu_bus_arvalid_ff) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1096:4 + rvdff_fpga #(.WIDTH(2)) bus_rsp_cmd_ff( + .rst_l(rst_l), + .clk(busclk), + .clken(bus_ifu_bus_clk_en), + .rawclk(clk), + .din(ifu_axi_rresp[1:0]), + .dout(ifu_bus_rresp_ff[1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1097:4 + rvdff_fpga #(.WIDTH(pt[826-:8])) bus_rsp_tag_ff( + .rst_l(rst_l), + .clk(busclk), + .clken(bus_ifu_bus_clk_en), + .rawclk(clk), + .din(ifu_axi_rid[pt[826-:8] - 1:0]), + .dout(ifu_bus_rid_ff[pt[826-:8] - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1098:4 + rvdffe #(.WIDTH(64)) bus_data_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .din(ifu_axi_rdata[63:0]), + .dout(ifu_bus_rdata_ff[63:0]), + .en(ifu_bus_clk_en & ifu_axi_rvalid) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1100:4 + assign ifu_bus_cmd_ready = ifu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1101:4 + assign ifu_bus_rsp_valid = ifu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1102:4 + assign ifu_bus_rsp_ready = ifu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1103:4 + assign ifu_bus_rsp_tag[pt[826-:8] - 1:0] = ifu_axi_rid[pt[826-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1104:4 + assign ifu_bus_rsp_rdata[63:0] = ifu_axi_rdata[63:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1105:4 + assign ifu_bus_rsp_opc[1:0] = {ifu_axi_rresp[1:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1117:4 + assign ifu_bus_rvalid = ifu_bus_rsp_valid & bus_ifu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1121:4 + assign ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1122:4 + assign ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1124:4 + assign ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1125:4 + assign bus_cmd_sent = ((ifu_bus_arvalid & ifu_bus_arready) & miss_pending) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1126:4 + assign bus_inc_data_beat_cnt = (bus_ifu_wr_en_ff & ~bus_last_data_beat) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1127:4 + assign bus_reset_data_beat_cnt = (ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat)) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1128:4 + assign bus_hold_data_beat_cnt = ~bus_inc_data_beat_cnt & ~bus_reset_data_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1130:4 + function automatic signed [pt[1174-:8] - 1:0] sv2v_cast_9E430_signed; + input reg signed [pt[1174-:8] - 1:0] inp; + sv2v_cast_9E430_signed = inp; + endfunction + assign bus_new_data_beat_count[pt[1174-:8] - 1:0] = (({pt[1174-:8] {bus_reset_data_beat_cnt}} & sv2v_cast_9E430_signed(0)) | ({pt[1174-:8] {bus_inc_data_beat_cnt}} & (bus_data_beat_count[pt[1174-:8] - 1:0] + {{pt[1174-:8] - 1 {1'b0}}, 1'b1}))) | ({pt[1174-:8] {bus_hold_data_beat_cnt}} & bus_data_beat_count[pt[1174-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1135:4 + assign last_data_recieved_in = ((bus_ifu_wr_en_ff & bus_last_data_beat) & ~scnd_miss_req) | (last_data_recieved_ff & ~ic_act_miss_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1140:4 + assign bus_new_rd_addr_count[pt[1174-:8] - 1:0] = (~miss_pending ? imb_ff[pt[1182-:8]:3] : (scnd_miss_req_q ? imb_scnd_ff[pt[1182-:8]:3] : (bus_cmd_sent ? bus_rd_addr_count[pt[1174-:8] - 1:0] + 3'b001 : bus_rd_addr_count[pt[1174-:8] - 1:0]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1145:4 + rvdff_fpga #(.WIDTH(pt[1174-:8])) bus_rd_addr_ff( + .rst_l(rst_l), + .clk(busclk_reset), + .clken((bus_ifu_bus_clk_en | ic_act_miss_f) | dec_tlu_force_halt), + .rawclk(clk), + .din({bus_new_rd_addr_count[pt[1174-:8] - 1:0]}), + .dout({bus_rd_addr_count[pt[1174-:8] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1150:4 + assign bus_inc_cmd_beat_cnt = ((ifu_bus_cmd_valid & ifu_bus_cmd_ready) & miss_pending) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1151:4 + assign bus_reset_cmd_beat_cnt_0 = (ic_act_miss_f & ~uncacheable_miss_in) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1152:4 + assign bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1153:4 + assign bus_hold_cmd_beat_cnt = ~bus_inc_cmd_beat_cnt & ~((ic_act_miss_f | scnd_miss_req) | dec_tlu_force_halt); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1154:4 + assign bus_cmd_beat_en = (bus_inc_cmd_beat_cnt | ic_act_miss_f) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1156:4 + function automatic [pt[1174-:8] - 1:0] sv2v_cast_9E430; + input reg [pt[1174-:8] - 1:0] inp; + sv2v_cast_9E430 = inp; + endfunction + assign bus_new_cmd_beat_count[pt[1174-:8] - 1:0] = ((({pt[1174-:8] {bus_reset_cmd_beat_cnt_0}} & sv2v_cast_9E430_signed(0)) | ({pt[1174-:8] {bus_reset_cmd_beat_cnt_secondlast}} & sv2v_cast_9E430(pt[1048-:8]))) | ({pt[1174-:8] {bus_inc_cmd_beat_cnt}} & (bus_cmd_beat_count[pt[1174-:8] - 1:0] + {{pt[1174-:8] - 1 {1'b0}}, 1'b1}))) | ({pt[1174-:8] {bus_hold_cmd_beat_cnt}} & bus_cmd_beat_count[pt[1174-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1162:4 + assign busclk_reset = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1169:4 + rvdffs_fpga #(.WIDTH(pt[1174-:8])) bus_cmd_beat_ff( + .rst_l(rst_l), + .clk(busclk_reset), + .clken((bus_ifu_bus_clk_en | ic_act_miss_f) | dec_tlu_force_halt), + .rawclk(clk), + .en(bus_cmd_beat_en), + .din({bus_new_cmd_beat_count[pt[1174-:8] - 1:0]}), + .dout({bus_cmd_beat_count[pt[1174-:8] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1173:5 + assign bus_last_data_beat = (uncacheable_miss_ff ? bus_data_beat_count[pt[1174-:8] - 1:0] == {{pt[1174-:8] - 1 {1'b0}}, 1'b1} : &bus_data_beat_count[pt[1174-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1175:4 + assign bus_ifu_wr_en = ifu_bus_rvalid & miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1176:4 + assign bus_ifu_wr_en_ff = ifu_bus_rvalid_ff & miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1177:4 + assign bus_ifu_wr_en_ff_q = (((ifu_bus_rvalid_ff & miss_pending) & ~uncacheable_miss_ff) & ~(|ifu_bus_rresp_ff[1:0])) & write_ic_16_bytes; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1178:4 + assign bus_ifu_wr_en_ff_wo_err = (ifu_bus_rvalid_ff & miss_pending) & ~uncacheable_miss_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1181:4 + rvdffie #(.WIDTH(10)) misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({ic_act_miss_f, ifu_wr_cumulative_err, exu_flush_final, ic_crit_wd_rdy_new_in, bus_ifu_bus_clk_en, scnd_miss_req_in, bus_cmd_req_in, last_data_recieved_in, ifc_dma_access_ok_d, dma_iccm_req}), + .dout({ic_act_miss_f_delayed, ifu_wr_data_comb_err_ff, flush_final_f, ic_crit_wd_rdy_new_ff, bus_ifu_bus_clk_en_ff, scnd_miss_req_q, bus_cmd_req_hold, last_data_recieved_ff, ifc_dma_access_ok_prev, dma_iccm_req_f}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1190:4 + rvdffie #( + .WIDTH(pt[1174-:8] + 5), + .OVERRIDE(1) + ) misc1_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({reset_ic_in, sel_mb_addr, bus_new_data_beat_count[pt[1174-:8] - 1:0], ifc_region_acc_fault_memory_bf, ic_debug_rd_en, ic_debug_rd_en_ff}), + .dout({reset_ic_ff, sel_mb_addr_ff, bus_data_beat_count[pt[1174-:8] - 1:0], ifc_region_acc_fault_memory_f, ic_debug_rd_en_ff, ifu_ic_debug_rd_data_valid}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1197:4 + assign reset_tag_valid_for_miss = (ic_act_miss_f_delayed & (miss_state == 3'b001)) & ~uncacheable_miss_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1198:4 + assign bus_ifu_wr_data_error = (|ifu_bus_rsp_opc[1:0] & ifu_bus_rvalid) & miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1199:4 + assign bus_ifu_wr_data_error_ff = (|ifu_bus_rresp_ff[1:0] & ifu_bus_rvalid_ff) & miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1202:4 + assign ic_crit_wd_rdy = ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1203:4 + assign last_beat = bus_last_data_beat & bus_ifu_wr_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1204:4 + assign reset_beat_cnt = bus_reset_data_beat_cnt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1208:4 + assign ifc_dma_access_ok_d = (ifc_dma_access_ok & ~iccm_correct_ecc) & ~iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1209:4 + assign ifc_dma_access_q_ok = (((ifc_dma_access_ok & ~iccm_correct_ecc) & ifc_dma_access_ok_prev) & (perr_state == 3'b000)) & ~iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1210:4 + assign iccm_ready = ifc_dma_access_q_ok; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1212:4 + wire [1:0] iccm_ecc_word_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1214:5 + generate + if (pt[927-:5] == 1) begin : iccm_enabled + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1215:10 + wire [3:2] dma_mem_addr_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1216:10 + wire iccm_dma_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1218:10 + wire iccm_dma_ecc_error_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1219:10 + wire [13:0] dma_mem_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1220:10 + wire [63:0] iccm_dma_rdata_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1221:10 + wire [31:0] iccm_dma_rdata_1_muxed; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1222:10 + wire [63:0] iccm_corrected_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1223:10 + wire [13:0] iccm_corrected_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1226:10 + wire [1:0] iccm_double_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1229:10 + wire [pt[936-:9] - 1:2] iccm_rw_addr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1231:10 + wire [31:0] iccm_corrected_data_f_mux; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1232:10 + wire [6:0] iccm_corrected_ecc_f_mux; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1233:10 + wire iccm_dma_rvalid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1234:10 + wire [77:0] iccm_rdmux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1235:10 + wire iccm_rd_ecc_single_err_hold_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1236:10 + wire [2:0] dma_mem_tag_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1241:10 + assign iccm_wren = ((ifc_dma_access_q_ok & dma_iccm_req) & dma_mem_write) | iccm_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1242:10 + assign iccm_rden = ((ifc_dma_access_q_ok & dma_iccm_req) & ~dma_mem_write) | (ifc_iccm_access_bf & ifc_fetch_req_bf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1243:10 + assign iccm_dma_rden = (ifc_dma_access_q_ok & dma_iccm_req) & ~dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1244:10 + assign iccm_wr_size[2:0] = {3 {dma_iccm_req}} & dma_mem_sz[2:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1246:10 + rvecc_encode iccm_ecc_encode0( + .din(dma_mem_wdata[31:0]), + .ecc_out(dma_mem_ecc[6:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1250:10 + rvecc_encode iccm_ecc_encode1( + .din(dma_mem_wdata[63:32]), + .ecc_out(dma_mem_ecc[13:7]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1254:9 + assign iccm_wr_data[77:0] = (iccm_correct_ecc & ~(ifc_dma_access_q_ok & dma_iccm_req) ? {iccm_ecc_corr_data_ff[38:0], iccm_ecc_corr_data_ff[38:0]} : {dma_mem_ecc[13:7], dma_mem_wdata[63:32], dma_mem_ecc[6:0], dma_mem_wdata[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1257:10 + assign iccm_dma_rdata_1_muxed[31:0] = (dma_mem_addr_ff[2] ? iccm_corrected_data[31-:32] : iccm_corrected_data[63-:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1258:10 + assign iccm_dma_rdata_in[63:0] = (iccm_dma_ecc_error_in ? {2 {dma_mem_addr[31:0]}} : {iccm_dma_rdata_1_muxed[31:0], iccm_corrected_data[0+:32]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1259:10 + assign iccm_dma_ecc_error_in = |iccm_double_ecc_error[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1261:10 + rvdffe #(.WIDTH(64)) dma_data_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(iccm_dma_rvalid_in), + .din(iccm_dma_rdata_in[63:0]), + .dout(iccm_dma_rdata[63:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1262:10 + rvdffie #(.WIDTH(11)) dma_misc_bits( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({dma_mem_tag[2:0], dma_mem_tag_ff[2:0], dma_mem_addr[3:2], iccm_dma_rden, iccm_dma_rvalid_in, iccm_dma_ecc_error_in}), + .dout({dma_mem_tag_ff[2:0], iccm_dma_rtag[2:0], dma_mem_addr_ff[3:2], iccm_dma_rvalid_in, iccm_dma_rvalid, iccm_dma_ecc_error}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1275:10 + assign iccm_rw_addr[pt[936-:9] - 1:1] = ((ifc_dma_access_q_ok & dma_iccm_req) & ~iccm_correct_ecc ? dma_mem_addr[pt[936-:9] - 1:1] : (~(ifc_dma_access_q_ok & dma_iccm_req) & iccm_correct_ecc ? {iccm_ecc_corr_index_ff[pt[936-:9] - 1:2], 1'b0} : ifc_fetch_addr_bf[pt[936-:9] - 1:1])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1285:3 + wire [3:0] ic_fetch_val_int_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1286:3 + wire [3:0] ic_fetch_val_shift_right; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1287:3 + assign ic_fetch_val_int_f[3:0] = {2'b00, ic_fetch_val_f[1:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1288:3 + assign ic_fetch_val_shift_right[3:0] = {ic_fetch_val_int_f << ifu_fetch_addr_int_f[1]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1290:4 + assign iccm_rdmux_data[77:0] = iccm_rd_data_ecc[77:0]; + genvar _gv_i_27; + for (_gv_i_27 = 0; _gv_i_27 < 2; _gv_i_27 = _gv_i_27 + 1) begin : ICCM_ECC_CHECK + localparam i = _gv_i_27; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1292:7 + assign iccm_ecc_word_enable[i] = (((|ic_fetch_val_shift_right[(2 * i) + 1:2 * i] & ~exu_flush_final) & sel_iccm_data) | iccm_dma_rvalid_in) & ~dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1293:4 + rvecc_decode ecc_decode( + .en(iccm_ecc_word_enable[i]), + .sed_ded(1'b0), + .din(iccm_rdmux_data[(39 * i) + 31:39 * i]), + .ecc_in(iccm_rdmux_data[(39 * i) + 38:(39 * i) + 32]), + .dout(iccm_corrected_data[(i * 32) + 31-:32]), + .ecc_out(iccm_corrected_ecc[(i * 7) + 6-:7]), + .single_ecc_error(iccm_single_ecc_error[i]), + .double_ecc_error(iccm_double_ecc_error[i]) + ); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1304:3 + assign iccm_rd_ecc_single_err = (|iccm_single_ecc_error[1:0] & ifc_iccm_access_f) & ifc_fetch_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1305:3 + assign iccm_rd_ecc_double_err[1:0] = (~ifu_fetch_addr_int_f[1] ? {iccm_double_ecc_error[0], iccm_double_ecc_error[0]} & {2 {ifc_iccm_access_f}} : {iccm_double_ecc_error[1], iccm_double_ecc_error[0]} & {2 {ifc_iccm_access_f}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1308:3 + assign iccm_corrected_data_f_mux[31:0] = (iccm_single_ecc_error[0] ? iccm_corrected_data[0+:32] : iccm_corrected_data[32+:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1309:3 + assign iccm_corrected_ecc_f_mux[6:0] = (iccm_single_ecc_error[0] ? iccm_corrected_ecc[0+:7] : iccm_corrected_ecc[7+:7]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1311:3 + assign iccm_ecc_write_status = ((iccm_rd_ecc_single_err & ~iccm_rd_ecc_single_err_ff) & ~exu_flush_final) | iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1312:3 + assign iccm_rd_ecc_single_err_hold_in = (iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & ~exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1313:3 + assign iccm_error_start = iccm_rd_ecc_single_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1314:3 + assign iccm_ecc_corr_index_in[pt[936-:9] - 1:2] = (iccm_single_ecc_error[0] ? iccm_rw_addr_f[pt[936-:9] - 1:2] : iccm_rw_addr_f[pt[936-:9] - 1:2] + 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1316:4 + rvdffie #(.WIDTH(pt[936-:9] - 1)) iccm_index_f( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({iccm_rw_addr[pt[936-:9] - 1:2], iccm_rd_ecc_single_err_hold_in}), + .dout({iccm_rw_addr_f[pt[936-:9] - 1:2], iccm_rd_ecc_single_err_ff}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1322:4 + rvdffe #(.WIDTH(pt[936-:9] + 37)) ecc_dat0_ff( + .clk(clk), + .din({iccm_corrected_ecc_f_mux[6:0], iccm_corrected_data_f_mux[31:0], iccm_ecc_corr_index_in[pt[936-:9] - 1:2]}), + .dout({iccm_ecc_corr_data_ff[38:0], iccm_ecc_corr_index_ff[pt[936-:9] - 1:2]}), + .en(iccm_ecc_write_status), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + end + else begin : iccm_disabled + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1331:10 + assign iccm_dma_rvalid = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1332:10 + assign iccm_dma_ecc_error = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1333:10 + assign iccm_dma_rdata[63:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1334:10 + assign iccm_single_ecc_error = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1335:10 + assign iccm_dma_rtag = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1342:10 + assign iccm_rd_ecc_single_err = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1343:10 + assign iccm_rd_ecc_double_err = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1344:10 + assign iccm_rd_ecc_single_err_ff = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1345:10 + assign iccm_error_start = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1346:10 + assign iccm_ecc_corr_index_ff[pt[936-:9] - 1:2] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1347:10 + assign iccm_ecc_corr_data_ff[38:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1348:10 + assign iccm_ecc_write_status = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1361:2 + assign ic_rd_en = (((ifc_fetch_req_bf & ~ifc_fetch_uncacheable_bf) & ~ifc_iccm_access_bf) & ~(((((((miss_state == 3'b110) & ~miss_state_en) | ((miss_state == 3'b001) & ~miss_state_en)) | ((miss_state == 3'b111) & ~miss_state_en)) | ((miss_state == 3'b011) & ~miss_state_en)) | ((miss_state == 3'b100) & ~miss_state_en)) | (((miss_state == 3'b001) & miss_state_en) & (miss_nxtstate == 3'b011)))) | (((ifc_fetch_req_bf & exu_flush_final) & ~ifc_fetch_uncacheable_bf) & ~ifc_iccm_access_bf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1370:1 + wire ic_real_rd_wp_unused; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1371:1 + assign ic_real_rd_wp_unused = ((((((ifc_fetch_req_bf & ~ifc_iccm_access_bf) & ~ifc_region_acc_fault_final_bf) & ~dec_tlu_fence_i_wb) & ~stream_miss_f) & ~ic_act_miss_f) & ~(((((((((miss_state == 3'b110) & ~miss_state_en) | (((miss_state == 3'b001) & ~miss_state_en) & ~(miss_nxtstate == 3'b011))) | (((miss_state == 3'b001) & miss_state_en) & (miss_nxtstate == 3'b011))) | ((miss_state == 3'b011) & ~miss_state_en)) | ((miss_state == 3'b111) & ~miss_state_en)) | ((miss_state == 3'b100) & ~miss_state_en)) | ((miss_nxtstate == 3'b110) & miss_state_en)) | ((miss_state == 3'b101) & ~miss_state_en))) | (((((ifc_fetch_req_bf & ~ifc_iccm_access_bf) & ~ifc_region_acc_fault_final_bf) & ~dec_tlu_fence_i_wb) & ~stream_miss_f) & exu_flush_final); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1383:1 + assign ic_wr_en[pt[1060-:7] - 1:0] = bus_ic_wr_en[pt[1060-:7] - 1:0] & {pt[1060-:7] {write_ic_16_bytes}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1384:1 + assign ic_write_stall = write_ic_16_bytes & ~(((miss_state == 3'b001) | ((miss_state == 3'b110) & ~((exu_flush_final | ifu_bp_hit_taken_q_f) | stream_eol_f))) & ~((bus_ifu_wr_en_ff & last_beat) & ~uncacheable_miss_ff)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1392:1 + reg [pt[1060-:7] - 1:0] ic_tag_valid_unq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1393:1 + function automatic signed [(pt[991-:9] - pt[998-:7]) - 1:0] sv2v_cast_5A7F8_signed; + input reg signed [(pt[991-:9] - pt[998-:7]) - 1:0] inp; + sv2v_cast_5A7F8_signed = inp; + endfunction + generate + if (pt[1120-:5] == 1) begin : icache_enabled + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1394:4 + assign ic_valid = (~ifu_wr_cumulative_err_data & ~(reset_ic_in | reset_ic_ff)) & ~reset_tag_valid_for_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1396:4 + assign ifu_status_wr_addr_w_debug[pt[1104-:9]:pt[998-:7]] = ((ic_debug_rd_en | ic_debug_wr_en) & ic_debug_tag_array ? ic_debug_addr[pt[1104-:9]:pt[998-:7]] : ifu_status_wr_addr[pt[1104-:9]:pt[998-:7]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1402:10 + assign way_status_wr_en_w_debug = way_status_wr_en | (ic_debug_wr_en & ic_debug_tag_array); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1404:10 + assign way_status_new_w_debug[pt[1027-:7] - 1:0] = (ic_debug_wr_en & ic_debug_tag_array ? (pt[1027-:7] == 1 ? ic_debug_wr_data[4] : ic_debug_wr_data[6:4]) : way_status_new[pt[1027-:7] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1407:4 + rvdffie #( + .WIDTH(((pt[991-:9] - pt[998-:7]) + 1) + pt[1027-:7]), + .OVERRIDE(1) + ) status_misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({ifu_status_wr_addr_w_debug[pt[1104-:9]:pt[998-:7]], way_status_wr_en_w_debug, way_status_new_w_debug[pt[1027-:7] - 1:0]}), + .dout({ifu_status_wr_addr_ff[pt[1104-:9]:pt[998-:7]], way_status_wr_en_ff, way_status_new_ff[pt[1027-:7] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1414:4 + wire [(pt[1015-:17] / 8) - 1:0] way_status_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1415:4 + wire [(pt[1015-:17] / 8) - 1:0] way_status_clk; + genvar _gv_i_28; + for (_gv_i_28 = 0; _gv_i_28 < (pt[1015-:17] / 8); _gv_i_28 = _gv_i_28 + 1) begin : CLK_GRP_WAY_STATUS + localparam i = _gv_i_28; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1418:7 + assign way_status_clken[i] = ifu_status_wr_addr_ff[pt[1104-:9]:pt[998-:7] + 3] == i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1420:9 + assign way_status_clk[i] = 1'b0; + genvar _gv_j_4; + for (_gv_j_4 = 0; _gv_j_4 < 8; _gv_j_4 = _gv_j_4 + 1) begin : WAY_STATUS + localparam j = _gv_j_4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1427:10 + rvdffs_fpga #(.WIDTH(pt[1027-:7])) ic_way_status( + .rst_l(rst_l), + .clk(way_status_clk[i]), + .clken(way_status_clken[i]), + .rawclk(clk), + .en((ifu_status_wr_addr_ff[pt[998-:7] + 2:pt[998-:7]] == j) & way_status_wr_en_ff), + .din(way_status_new_ff[pt[1027-:7] - 1:0]), + .dout(way_status_out[((8 * i) + j) * pt[1027-:7]+:pt[1027-:7]]) + ); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1437:3 + always @(*) begin : way_status_out_mux + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1438:7 + way_status[pt[1027-:7] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1439:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1439:12 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1439:12 + for (j = 0; j < pt[1015-:17]; j = j + 1) + begin : status_mux_loop + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1440:9 + if (ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]] == sv2v_cast_5A7F8_signed(j)) begin : mux_out + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1441:10 + way_status[pt[1027-:7] - 1:0] = way_status_out[j * pt[1027-:7]+:pt[1027-:7]]; + end + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1446:10 + assign ifu_ic_rw_int_addr_w_debug[pt[1104-:9]:pt[998-:7]] = ((ic_debug_rd_en | ic_debug_wr_en) & ic_debug_tag_array ? ic_debug_addr[pt[1104-:9]:pt[998-:7]] : ifu_ic_rw_int_addr[pt[1104-:9]:pt[998-:7]]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1449:10 + assign ifu_tag_wren_w_debug[pt[1060-:7] - 1:0] = ifu_tag_wren[pt[1060-:7] - 1:0] | ic_debug_tag_wr_en[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1451:10 + assign ic_valid_w_debug = (ic_debug_wr_en & ic_debug_tag_array ? ic_debug_wr_data[0] : ic_valid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1453:10 + rvdffie #(.WIDTH(((pt[991-:9] - pt[998-:7]) + pt[1060-:7]) + 1)) tag_addr_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({ifu_ic_rw_int_addr_w_debug[pt[1104-:9]:pt[998-:7]], ifu_tag_wren_w_debug[pt[1060-:7] - 1:0], ic_valid_w_debug}), + .dout({ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]], ifu_tag_wren_ff[pt[1060-:7] - 1:0], ic_valid_ff}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1464:4 + wire [(pt[1060-:7] * pt[1015-:17]) - 1:0] ic_tag_valid_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1466:4 + wire [((pt[1015-:17] / 32) * pt[1060-:7]) - 1:0] tag_valid_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1467:4 + wire [((pt[1015-:17] / 32) * pt[1060-:7]) - 1:0] tag_valid_clk; + genvar _gv_i_29; + for (_gv_i_29 = 0; _gv_i_29 < (pt[1015-:17] / 32); _gv_i_29 = _gv_i_29 + 1) begin : CLK_GRP_TAG_VALID + localparam i = _gv_i_29; + genvar _gv_j_5; + for (_gv_j_5 = 0; _gv_j_5 < pt[1060-:7]; _gv_j_5 = _gv_j_5 + 1) begin : way_clken + localparam j = _gv_j_5; + if (pt[1015-:17] == 32) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1472:9 + assign tag_valid_clken[(i * pt[1060-:7]) + j] = (ifu_tag_wren_ff[j] | perr_err_inv_way[j]) | reset_all_tags; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1474:10 + assign tag_valid_clken[(i * pt[1060-:7]) + j] = (((ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7] + 5] == i) & ifu_tag_wren_ff[j]) | ((perr_ic_index_ff[pt[1104-:9]:pt[998-:7] + 5] == i) & perr_err_inv_way[j])) | reset_all_tags; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1479:9 + assign tag_valid_clk[(i * pt[1060-:7]) + j] = 1'b0; + genvar _gv_k_5; + for (_gv_k_5 = 0; _gv_k_5 < 32; _gv_k_5 = _gv_k_5 + 1) begin : TAG_VALID + localparam k = _gv_k_5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1487:10 + rvdffs_fpga #(.WIDTH(1)) ic_way_tagvalid_dup( + .rst_l(rst_l), + .clk(tag_valid_clk[(i * pt[1060-:7]) + j]), + .clken(tag_valid_clken[(i * pt[1060-:7]) + j]), + .rawclk(clk), + .en((((ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]] == (k + (32 * i))) & ifu_tag_wren_ff[j]) | ((perr_ic_index_ff[pt[1104-:9]:pt[998-:7]] == (k + (32 * i))) & perr_err_inv_way[j])) | reset_all_tags), + .din((ic_valid_ff & ~reset_all_tags) & ~perr_sel_invalidate), + .dout(ic_tag_valid_out[(j * pt[1015-:17]) + ((32 * i) + k)]) + ); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1500:3 + always @(*) begin : tag_valid_out_mux + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1501:7 + ic_tag_valid_unq[pt[1060-:7] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1502:7 + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1502:12 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1502:12 + for (j = 0; j < pt[1015-:17]; j = j + 1) + begin : tag_valid_loop + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1503:9 + if (ifu_ic_rw_int_addr_ff[pt[1104-:9]:pt[998-:7]] == sv2v_cast_5A7F8_signed(j)) begin : valid_out + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1504:12 + begin : sv2v_autoblock_3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1504:18 + reg signed [31:0] k; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1504:18 + for (k = 0; k < pt[1060-:7]; k = k + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1505:14 + ic_tag_valid_unq[k] = ic_tag_valid_unq[k] | ic_tag_valid_out[(k * pt[1015-:17]) + j]; + end + end + end + end + end + end + if (pt[1060-:7] == 4) begin : four_way_plru + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1531:4 + assign replace_way_mb_any[3] = ((way_status_mb_ff[2] & way_status_mb_ff[0]) & (&tagv_mb_ff[3:0])) | (((~tagv_mb_ff[3] & tagv_mb_ff[2]) & tagv_mb_ff[1]) & tagv_mb_ff[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1533:4 + assign replace_way_mb_any[2] = ((~way_status_mb_ff[2] & way_status_mb_ff[0]) & (&tagv_mb_ff[3:0])) | ((~tagv_mb_ff[2] & tagv_mb_ff[1]) & tagv_mb_ff[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1535:4 + assign replace_way_mb_any[1] = ((way_status_mb_ff[1] & ~way_status_mb_ff[0]) & (&tagv_mb_ff[3:0])) | (~tagv_mb_ff[1] & tagv_mb_ff[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1537:4 + assign replace_way_mb_any[0] = ((~way_status_mb_ff[1] & ~way_status_mb_ff[0]) & (&tagv_mb_ff[3:0])) | ~tagv_mb_ff[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1540:4 + assign way_status_hit_new[pt[1027-:7] - 1:0] = ((({3 {~exu_flush_final & ic_rd_hit[0]}} & {way_status[2], 2'b11}) | ({3 {~exu_flush_final & ic_rd_hit[1]}} & {way_status[2], 2'b01})) | ({3 {~exu_flush_final & ic_rd_hit[2]}} & {1'b1, way_status[1], 1'b0})) | ({3 {~exu_flush_final & ic_rd_hit[3]}} & {1'b0, way_status[1], 1'b0}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1545:3 + assign way_status_rep_new[pt[1027-:7] - 1:0] = ((({3 {replace_way_mb_any[0]}} & {way_status_mb_ff[2], 2'b11}) | ({3 {replace_way_mb_any[1]}} & {way_status_mb_ff[2], 2'b01})) | ({3 {replace_way_mb_any[2]}} & {1'b1, way_status_mb_ff[1], 1'b0})) | ({3 {replace_way_mb_any[3]}} & {1'b0, way_status_mb_ff[1], 1'b0}); + end + else begin : two_ways_plru + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1551:7 + assign replace_way_mb_any[0] = ((~way_status_mb_ff & tagv_mb_ff[0]) & tagv_mb_ff[1]) | ~tagv_mb_ff[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1552:7 + assign replace_way_mb_any[1] = ((way_status_mb_ff & tagv_mb_ff[0]) & tagv_mb_ff[1]) | (~tagv_mb_ff[1] & tagv_mb_ff[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1553:7 + assign way_status_hit_new[pt[1027-:7] - 1:0] = ic_rd_hit[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1554:7 + assign way_status_rep_new[pt[1027-:7] - 1:0] = replace_way_mb_any[0]; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1558:3 + assign way_status_new[pt[1027-:7] - 1:0] = (bus_ifu_wr_en_ff_q & last_beat ? way_status_rep_new[pt[1027-:7] - 1:0] : way_status_hit_new[pt[1027-:7] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1562:3 + assign way_status_wr_en = (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f; + genvar _gv_i_30; + for (_gv_i_30 = 0; _gv_i_30 < pt[1060-:7]; _gv_i_30 = _gv_i_30 + 1) begin : bus_wren_loop + localparam i = _gv_i_30; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1565:7 + assign bus_wren[i] = (bus_ifu_wr_en_ff_q & replace_way_mb_any[i]) & miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1566:7 + assign bus_wren_last[i] = ((bus_ifu_wr_en_ff_wo_err & replace_way_mb_any[i]) & miss_pending) & bus_last_data_beat; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1567:7 + assign ifu_tag_wren[i] = bus_wren_last[i] | wren_reset_miss[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1568:7 + assign wren_reset_miss[i] = replace_way_mb_any[i] & reset_tag_valid_for_miss; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1571:4 + assign bus_ic_wr_en[pt[1060-:7] - 1:0] = bus_wren[pt[1060-:7] - 1:0]; + end + else begin : icache_disabled + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1575:4 + wire [pt[1060-:7] * 1:1] sv2v_tmp_CC25A; + assign sv2v_tmp_CC25A = 1'sb0; + always @(*) ic_tag_valid_unq[pt[1060-:7] - 1:0] = sv2v_tmp_CC25A; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1576:4 + wire [pt[1027-:7] * 1:1] sv2v_tmp_F3208; + assign sv2v_tmp_F3208 = 1'sb0; + always @(*) way_status[pt[1027-:7] - 1:0] = sv2v_tmp_F3208; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1577:4 + assign replace_way_mb_any[pt[1060-:7] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1578:4 + assign way_status_hit_new[pt[1027-:7] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1579:4 + assign way_status_rep_new[pt[1027-:7] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1580:4 + assign way_status_new[pt[1027-:7] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1581:4 + assign way_status_wr_en = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1582:4 + assign bus_wren[pt[1060-:7] - 1:0] = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1586:4 + assign ic_tag_valid[pt[1060-:7] - 1:0] = ic_tag_valid_unq[pt[1060-:7] - 1:0] & {pt[1060-:7] {~fetch_uncacheable_ff & ifc_fetch_req_f_raw}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1587:4 + assign ic_debug_tag_val_rd_out = |((ic_tag_valid_unq[pt[1060-:7] - 1:0] & ic_debug_way_ff[pt[1060-:7] - 1:0]) & {pt[1060-:7] {ic_debug_rd_en_ff}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1592:2 + assign ifu_pmu_ic_miss_in = ic_act_miss_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1593:2 + assign ifu_pmu_ic_hit_in = ic_act_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1594:2 + assign ifu_pmu_bus_error_in = |ifc_bus_acc_fault_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1595:2 + assign ifu_pmu_bus_trxn_in = bus_cmd_sent; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1596:2 + assign ifu_pmu_bus_busy_in = (ifu_bus_arvalid_ff & ~ifu_bus_arready_ff) & miss_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1598:4 + rvdffie #(.WIDTH(9)) ifu_pmu_sigs_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({ifc_fetch_uncacheable_bf, ifc_fetch_req_qual_bf, dma_sb_err_state, dec_tlu_fence_i_wb, ifu_pmu_ic_miss_in, ifu_pmu_ic_hit_in, ifu_pmu_bus_error_in, ifu_pmu_bus_busy_in, ifu_pmu_bus_trxn_in}), + .dout({fetch_uncacheable_ff, ifc_fetch_req_f_raw, dma_sb_err_state_ff, reset_all_tags, ifu_pmu_ic_miss, ifu_pmu_ic_hit, ifu_pmu_bus_error, ifu_pmu_bus_busy, ifu_pmu_bus_trxn}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1619:1 + assign ic_debug_addr[pt[1104-:9]:3] = dec_tlu_ic_diag_pkt[pt[1104-:9] - 1:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1620:1 + assign ic_debug_way_enc[1:0] = dec_tlu_ic_diag_pkt[17:16]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1623:1 + assign ic_debug_tag_array = dec_tlu_ic_diag_pkt[18]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1624:1 + assign ic_debug_rd_en = dec_tlu_ic_diag_pkt[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1625:1 + assign ic_debug_wr_en = dec_tlu_ic_diag_pkt[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1628:1 + assign ic_debug_way[pt[1060-:7] - 1:0] = {ic_debug_way_enc[1:0] == 2'b11, ic_debug_way_enc[1:0] == 2'b10, ic_debug_way_enc[1:0] == 2'b01, ic_debug_way_enc[1:0] == 2'b00}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1633:1 + assign ic_debug_tag_wr_en[pt[1060-:7] - 1:0] = {pt[1060-:7] {ic_debug_wr_en & ic_debug_tag_array}} & ic_debug_way[pt[1060-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1635:1 + assign ic_debug_ict_array_sel_in = ic_debug_rd_en & ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1637:1 + rvdff_fpga #(.WIDTH(1 + pt[1060-:7])) ifu_debug_sel_ff( + .rst_l(rst_l), + .clk(debug_c1_clk), + .clken(debug_c1_clken), + .rawclk(clk), + .din({ic_debug_ict_array_sel_in, ic_debug_way[pt[1060-:7] - 1:0]}), + .dout({ic_debug_ict_array_sel_ff, ic_debug_way_ff[pt[1060-:7] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1649:1 + assign debug_data_clken = ic_debug_rd_en_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1655:4 + assign ifc_region_acc_okay = (((((((~(|{pt[530-:5], pt[525-:5], pt[520-:5], pt[515-:5], pt[510-:5], pt[505-:5], pt[500-:5], pt[495-:5]}) | (pt[530-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[490-:36]) == (pt[818-:36] | pt[490-:36])))) | (pt[525-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[454-:36]) == (pt[782-:36] | pt[454-:36])))) | (pt[520-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[418-:36]) == (pt[746-:36] | pt[418-:36])))) | (pt[515-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[382-:36]) == (pt[710-:36] | pt[382-:36])))) | (pt[510-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[346-:36]) == (pt[674-:36] | pt[346-:36])))) | (pt[505-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[310-:36]) == (pt[638-:36] | pt[310-:36])))) | (pt[500-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[274-:36]) == (pt[602-:36] | pt[274-:36])))) | (pt[495-:5] & (({ifc_fetch_addr_bf[31:1], 1'b0} | pt[238-:36]) == (pt[566-:36] | pt[238-:36]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1665:4 + assign ifc_region_acc_fault_memory_bf = (~ifc_iccm_access_bf & ~ifc_region_acc_okay) & ifc_fetch_req_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_mem_ctl.sv:1667:4 + assign ifc_region_acc_fault_final_bf = ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf; + initial _sv2v_0 = 0; +endmodule +module el2_ifu_iccm_mem ( + clk, + active_clk, + rst_l, + clk_override, + iccm_wren, + iccm_rden, + iccm_rw_addr, + iccm_buf_correct_ecc, + iccm_correction_state, + iccm_wr_size, + iccm_wr_data, + iccm_ext_in_pkt, + iccm_rd_data, + iccm_rd_data_ecc, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:27:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:28:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:29:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:30:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:32:4 + input wire iccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:33:4 + input wire iccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:34:4 + input wire [pt[936-:9] - 1:1] iccm_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:35:4 + input wire iccm_buf_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:36:4 + input wire iccm_correction_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:37:4 + input wire [2:0] iccm_wr_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:38:4 + input wire [77:0] iccm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:40:4 + // removed localparam type el2_pkg_el2_ccm_ext_in_pkt_t + input wire [(pt[909-:9] * 12) - 1:0] iccm_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:42:4 + output wire [63:0] iccm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:43:4 + output wire [77:0] iccm_rd_data_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:44:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:49:4 + wire [pt[909-:9] - 1:0] wren_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:50:4 + wire [pt[909-:9] - 1:0] rden_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:51:4 + wire [pt[909-:9] - 1:0] iccm_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:52:4 + wire [((pt[936-:9] - 1) >= pt[945-:9] ? (pt[909-:9] * (((pt[936-:9] - 1) - pt[945-:9]) + 1)) + (pt[945-:9] - 1) : (pt[909-:9] * ((pt[945-:9] - (pt[936-:9] - 1)) + 1)) + (pt[936-:9] - 2)):((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] + 0 : pt[936-:9] - 1)] addr_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:54:4 + wire [(pt[909-:9] * 39) - 1:0] iccm_bank_dout; + wire [(pt[909-:9] * 39) - 1:0] iccm_bank_dout_fn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:55:4 + wire [(pt[909-:9] * 39) - 1:0] iccm_bank_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:56:4 + wire [pt[936-:9] - 1:1] addr_bank_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:57:4 + wire [pt[954-:9]:2] iccm_rd_addr_hi_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:58:4 + wire [pt[954-:9]:1] iccm_rd_addr_lo_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:59:4 + wire [63:0] iccm_rd_data_pre; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:60:4 + wire [63:0] iccm_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:61:4 + wire [1:0] addr_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:62:4 + wire [(pt[909-:9] * 39) - 1:0] iccm_bank_wr_data_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:65:4 + wire [((pt[936-:9] - 1) >= 2 ? (2 * (pt[936-:9] - 2)) + 1 : (2 * (4 - pt[936-:9])) + (pt[936-:9] - 2)):((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)] redundant_address; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:66:4 + wire [77:0] redundant_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:67:4 + wire [1:0] redundant_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:68:4 + wire [pt[909-:9] - 1:0] sel_red1; + wire [pt[909-:9] - 1:0] sel_red0; + wire [pt[909-:9] - 1:0] sel_red1_q; + wire [pt[909-:9] - 1:0] sel_red0_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:71:4 + wire [38:0] redundant_data0_in; + wire [38:0] redundant_data1_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:72:4 + wire redundant_lru; + wire redundant_lru_in; + wire redundant_lru_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:73:4 + wire redundant_data0_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:74:4 + wire redundant_data1_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:75:4 + wire r0_addr_en; + wire r1_addr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:94:4 + assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11 ? 2'b10 : 2'b01); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:95:4 + assign addr_bank_inc[pt[936-:9] - 1:1] = iccm_rw_addr[pt[936-:9] - 1:1] + addr_incr[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:97:4 + genvar _gv_i_31; + generate + for (_gv_i_31 = 0; _gv_i_31 < (pt[909-:9] / 2); _gv_i_31 = _gv_i_31 + 1) begin : mem_bank_data + localparam i = _gv_i_31; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:98:7 + assign iccm_bank_wr_data_vec[(2 * i) * 39+:39] = iccm_wr_data[38:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:99:7 + assign iccm_bank_wr_data_vec[((2 * i) + 1) * 39+:39] = iccm_wr_data[77:39]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:102:4 + genvar _gv_i_32; + generate + for (_gv_i_32 = 0; _gv_i_32 < pt[909-:9]; _gv_i_32 = _gv_i_32 + 1) begin : mem_bank + localparam i = _gv_i_32; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:103:7 + assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[pt[954-:9]:2] == i) | (addr_bank_inc[pt[954-:9]:2] == i)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:104:7 + assign iccm_bank_wr_data[i * 39+:39] = iccm_bank_wr_data_vec[i * 39+:39]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:105:7 + assign rden_bank[i] = iccm_rden & ((iccm_rw_addr[pt[954-:9]:2] == i) | (addr_bank_inc[pt[954-:9]:2] == i)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:106:7 + assign iccm_clken[i] = (wren_bank[i] | rden_bank[i]) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:107:7 + assign addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) : pt[945-:9] - (((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) - (pt[936-:9] - 1))) : (((i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) : pt[945-:9] - (((pt[936-:9] - 1) >= pt[945-:9] ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)) - 1)-:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)] = (wren_bank[i] ? iccm_rw_addr[pt[936-:9] - 1:pt[945-:9]] : (addr_bank_inc[pt[954-:9]:2] == i ? addr_bank_inc[pt[936-:9] - 1:pt[945-:9]] : iccm_rw_addr[pt[936-:9] - 1:pt[945-:9]])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:113:5 + el2_ram #( + .depth(1 << pt[917-:8]), + .width(39) + ) iccm_bank( + .ME(iccm_clken[i]), + .CLK(clk), + .WE(wren_bank[i]), + .ADR(addr_bank[((pt[936-:9] - 1) >= pt[945-:9] ? pt[945-:9] : pt[936-:9] - 1) + (i * ((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1))+:((pt[936-:9] - 1) >= pt[945-:9] ? ((pt[936-:9] - 1) - pt[945-:9]) + 1 : (pt[945-:9] - (pt[936-:9] - 1)) + 1)]), + .D(iccm_bank_wr_data[(i * 39) + 38-:39]), + .Q(iccm_bank_dout[(i * 39) + 38-:39]), + .ROP(), + .TEST1(iccm_ext_in_pkt[(i * 12) + 11]), + .RME(iccm_ext_in_pkt[(i * 12) + 10]), + .RM(iccm_ext_in_pkt[(i * 12) + 9-:4]), + .LS(iccm_ext_in_pkt[(i * 12) + 5]), + .DS(iccm_ext_in_pkt[(i * 12) + 4]), + .SD(iccm_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(iccm_ext_in_pkt[(i * 12) + 2]), + .BC1(iccm_ext_in_pkt[(i * 12) + 1]), + .BC2(iccm_ext_in_pkt[i * 12]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:371:4 + assign sel_red1[i] = redundant_valid[1] & (((iccm_rw_addr[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (iccm_rw_addr[3:2] == i)) | ((addr_bank_inc[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (addr_bank_inc[3:2] == i))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:374:4 + assign sel_red0[i] = redundant_valid[0] & (((iccm_rw_addr[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? 0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (iccm_rw_addr[3:2] == i)) | ((addr_bank_inc[pt[936-:9] - 1:2] == redundant_address[((pt[936-:9] - 1) >= 2 ? 0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) & (addr_bank_inc[3:2] == i))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:377:4 + rvdff #(.WIDTH(1)) selred0( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_red0[i]), + .dout(sel_red0_q[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:382:4 + rvdff #(.WIDTH(1)) selred1( + .rst_l(rst_l), + .clk(active_clk), + .din(sel_red1[i]), + .dout(sel_red1_q[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:389:4 + assign iccm_bank_dout_fn[(i * 39) + 38-:39] = (({39 {sel_red1_q[i]}} & redundant_data[77-:39]) | ({39 {sel_red0_q[i]}} & redundant_data[38-:39])) | ({39 {~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[(i * 39) + 38-:39]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:397:4 + assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:398:4 + assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:399:4 + assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[pt[909-:9] - 1:0] | (|sel_red1[pt[909-:9] - 1:0])) & iccm_rden) & iccm_correction_state); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:400:4 + assign redundant_lru_in = (iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[pt[909-:9] - 1:0] ? 1'b1 : 1'b0)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:402:4 + rvdffs red_lru( + .rst_l(rst_l), + .clk(active_clk), + .en(redundant_lru_en), + .din(redundant_lru_in), + .dout(redundant_lru) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:408:5 + rvdffs #(.WIDTH(pt[936-:9] - 2)) r0_address( + .rst_l(rst_l), + .clk(active_clk), + .en(r0_addr_en), + .din(iccm_rw_addr[pt[936-:9] - 1:2]), + .dout(redundant_address[((pt[936-:9] - 1) >= 2 ? 0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:414:4 + rvdffs #(.WIDTH(pt[936-:9] - 2)) r1_address( + .rst_l(rst_l), + .clk(active_clk), + .en(r1_addr_en), + .din(iccm_rw_addr[pt[936-:9] - 1:2]), + .dout(redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9])]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:420:5 + rvdffs #(.WIDTH(1)) r0_valid( + .rst_l(rst_l), + .clk(active_clk), + .en(r0_addr_en), + .din(1'b1), + .dout(redundant_valid[0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:426:4 + rvdffs #(.WIDTH(1)) r1_valid( + .rst_l(rst_l), + .clk(active_clk), + .en(r1_addr_en), + .din(1'b1), + .dout(redundant_valid[1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:438:5 + assign redundant_data0_en = ((((iccm_rw_addr[pt[936-:9] - 1:3] == redundant_address[((pt[936-:9] - 1) >= 2 ? 0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((0 + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])]) & ((iccm_rw_addr[2] == redundant_address[0 + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) | (iccm_wr_size[1:0] == 2'b11))) & redundant_valid[0]) & iccm_wren) | (~redundant_lru & iccm_buf_correct_ecc); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:441:5 + assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0 + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) & iccm_rw_addr[2]) | (redundant_address[0 + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)] & (iccm_wr_size[1:0] == 2'b11)) ? iccm_wr_data[77:39] : iccm_wr_data[38:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:443:5 + rvdffs #(.WIDTH(39)) r0_data( + .rst_l(rst_l), + .clk(active_clk), + .en(redundant_data0_en), + .din(redundant_data0_in[38:0]), + .dout(redundant_data[38-:39]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:449:4 + assign redundant_data1_en = ((((iccm_rw_addr[pt[936-:9] - 1:3] == redundant_address[((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1))) : ((((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) : 2 - (((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 1 : ((pt[936-:9] - 1) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1) - (pt[936-:9] - 1)))) + ((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])) - 1)-:((pt[936-:9] - 1) >= 3 ? pt[936-:9] - 3 : 5 - pt[936-:9])]) & ((iccm_rw_addr[2] == redundant_address[((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) | (iccm_wr_size[1:0] == 2'b11))) & redundant_valid[1]) & iccm_wren) | (redundant_lru & iccm_buf_correct_ecc); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:452:4 + assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)]) & iccm_rw_addr[2]) | (redundant_address[((pt[936-:9] - 1) >= 2 ? pt[936-:9] - 2 : 4 - pt[936-:9]) + ((pt[936-:9] - 1) >= 2 ? 2 : pt[936-:9] - 1)] & (iccm_wr_size[1:0] == 2'b11)) ? iccm_wr_data[77:39] : iccm_wr_data[38:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:454:5 + rvdffs #(.WIDTH(39)) r1_data( + .rst_l(rst_l), + .clk(active_clk), + .en(redundant_data1_en), + .din(redundant_data1_in[38:0]), + .dout(redundant_data[77-:39]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:461:4 + rvdffs #(.WIDTH(pt[954-:9])) rd_addr_lo_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(iccm_rw_addr[pt[954-:9]:1]), + .dout(iccm_rd_addr_lo_q[pt[954-:9]:1]), + .en(1'b1) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:462:4 + rvdffs #(.WIDTH(pt[961-:7])) rd_addr_hi_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(addr_bank_inc[pt[954-:9]:2]), + .dout(iccm_rd_addr_hi_q[pt[954-:9]:2]), + .en(1'b1) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:464:4 + assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[(iccm_rd_addr_hi_q * 39) + 31-:32], iccm_bank_dout_fn[(iccm_rd_addr_lo_q[pt[954-:9]:2] * 39) + 31-:32]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:465:4 + function automatic [63:0] sv2v_cast_64; + input reg [63:0] inp; + sv2v_cast_64 = inp; + endfunction + assign iccm_data[63:0] = sv2v_cast_64({16'b0000000000000000, iccm_rd_data_pre[63:0] >> (16 * iccm_rd_addr_lo_q[1])}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:466:4 + assign iccm_rd_data[63:0] = {iccm_data[63:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu_iccm_mem.sv:467:4 + assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[(iccm_rd_addr_hi_q * 39) + 38-:39], iccm_bank_dout_fn[(iccm_rd_addr_lo_q[pt[954-:9]:2] * 39) + 38-:39]}; +endmodule +module el2_ifu ( + free_l2clk, + active_clk, + clk, + rst_l, + dec_i0_decode_d, + exu_flush_final, + dec_tlu_i0_commit_cmt, + dec_tlu_flush_err_wb, + dec_tlu_flush_noredir_wb, + exu_flush_path_final, + dec_tlu_mrac_ff, + dec_tlu_fence_i_wb, + dec_tlu_flush_leak_one_wb, + dec_tlu_bpred_disable, + dec_tlu_core_ecc_disable, + dec_tlu_force_halt, + ifu_axi_awvalid, + ifu_axi_awid, + ifu_axi_awaddr, + ifu_axi_awregion, + ifu_axi_awlen, + ifu_axi_awsize, + ifu_axi_awburst, + ifu_axi_awlock, + ifu_axi_awcache, + ifu_axi_awprot, + ifu_axi_awqos, + ifu_axi_wvalid, + ifu_axi_wdata, + ifu_axi_wstrb, + ifu_axi_wlast, + ifu_axi_bready, + ifu_axi_arvalid, + ifu_axi_arready, + ifu_axi_arid, + ifu_axi_araddr, + ifu_axi_arregion, + ifu_axi_arlen, + ifu_axi_arsize, + ifu_axi_arburst, + ifu_axi_arlock, + ifu_axi_arcache, + ifu_axi_arprot, + ifu_axi_arqos, + ifu_axi_rvalid, + ifu_axi_rready, + ifu_axi_rid, + ifu_axi_rdata, + ifu_axi_rresp, + ifu_bus_clk_en, + dma_iccm_req, + dma_mem_addr, + dma_mem_sz, + dma_mem_write, + dma_mem_wdata, + dma_mem_tag, + dma_iccm_stall_any, + iccm_dma_ecc_error, + iccm_dma_rvalid, + iccm_dma_rdata, + iccm_dma_rtag, + iccm_ready, + ifu_pmu_instr_aligned, + ifu_pmu_fetch_stall, + ifu_ic_error_start, + ic_rw_addr, + ic_wr_en, + ic_rd_en, + ic_wr_data, + ic_rd_data, + ic_debug_rd_data, + ictag_debug_rd_data, + ic_debug_wr_data, + ifu_ic_debug_rd_data, + ic_eccerr, + ic_parerr, + ic_premux_data, + ic_sel_premux_data, + ic_debug_addr, + ic_debug_rd_en, + ic_debug_wr_en, + ic_debug_tag_array, + ic_debug_way, + ic_tag_valid, + ic_rd_hit, + ic_tag_perr, + iccm_rw_addr, + iccm_wren, + iccm_rden, + iccm_wr_data, + iccm_wr_size, + iccm_rd_data, + iccm_rd_data_ecc, + ifu_iccm_rd_ecc_single_err, + ifu_pmu_ic_miss, + ifu_pmu_ic_hit, + ifu_pmu_bus_error, + ifu_pmu_bus_busy, + ifu_pmu_bus_trxn, + ifu_i0_icaf, + ifu_i0_icaf_type, + ifu_i0_valid, + ifu_i0_icaf_second, + ifu_i0_dbecc, + iccm_dma_sb_error, + ifu_i0_instr, + ifu_i0_pc, + ifu_i0_pc4, + ifu_miss_state_idle, + i0_brp, + ifu_i0_bp_index, + ifu_i0_bp_fghr, + ifu_i0_bp_btag, + ifu_i0_fa_index, + exu_mp_pkt, + exu_mp_eghr, + exu_mp_fghr, + exu_mp_index, + exu_mp_btag, + dec_tlu_br0_r_pkt, + exu_i0_br_fghr_r, + exu_i0_br_index_r, + dec_fa_error_index, + dec_tlu_flush_lower_wb, + ifu_i0_cinst, + dec_tlu_ic_diag_pkt, + ifu_ic_debug_rd_data_valid, + iccm_buf_correct_ecc, + iccm_correction_state, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:28:4 + input wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:29:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:30:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:31:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:33:4 + input wire dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:35:4 + input wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:36:4 + input wire dec_tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:37:4 + input wire dec_tlu_flush_err_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:38:4 + input wire dec_tlu_flush_noredir_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:39:4 + input wire [31:1] exu_flush_path_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:41:4 + input wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:42:4 + input wire dec_tlu_fence_i_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:43:4 + input wire dec_tlu_flush_leak_one_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:45:4 + input wire dec_tlu_bpred_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:46:4 + input wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:47:4 + input wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:51:4 + output wire ifu_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:52:4 + output wire [pt[826-:8] - 1:0] ifu_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:53:4 + output wire [31:0] ifu_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:54:4 + output wire [3:0] ifu_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:55:4 + output wire [7:0] ifu_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:56:4 + output wire [2:0] ifu_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:57:4 + output wire [1:0] ifu_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:58:4 + output wire ifu_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:59:4 + output wire [3:0] ifu_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:60:4 + output wire [2:0] ifu_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:61:4 + output wire [3:0] ifu_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:63:4 + output wire ifu_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:64:4 + output wire [63:0] ifu_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:65:4 + output wire [7:0] ifu_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:66:4 + output wire ifu_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:68:4 + output wire ifu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:71:4 + output wire ifu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:72:4 + input wire ifu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:73:4 + output wire [pt[826-:8] - 1:0] ifu_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:74:4 + output wire [31:0] ifu_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:75:4 + output wire [3:0] ifu_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:76:4 + output wire [7:0] ifu_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:77:4 + output wire [2:0] ifu_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:78:4 + output wire [1:0] ifu_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:79:4 + output wire ifu_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:80:4 + output wire [3:0] ifu_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:81:4 + output wire [2:0] ifu_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:82:4 + output wire [3:0] ifu_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:84:4 + input wire ifu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:85:4 + output wire ifu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:86:4 + input wire [pt[826-:8] - 1:0] ifu_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:87:4 + input wire [63:0] ifu_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:88:4 + input wire [1:0] ifu_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:90:4 + input wire ifu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:92:4 + input wire dma_iccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:93:4 + input wire [31:0] dma_mem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:94:4 + input wire [2:0] dma_mem_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:95:4 + input wire dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:96:4 + input wire [63:0] dma_mem_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:97:4 + input wire [2:0] dma_mem_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:100:4 + input wire dma_iccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:101:4 + output wire iccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:102:4 + output wire iccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:103:4 + output wire [63:0] iccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:104:4 + output wire [2:0] iccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:105:4 + output wire iccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:107:4 + output wire ifu_pmu_instr_aligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:108:4 + output wire ifu_pmu_fetch_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:109:4 + output wire ifu_ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:112:4 + output wire [31:1] ic_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:113:4 + output wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:114:4 + output wire ic_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:116:4 + output wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:117:4 + input wire [63:0] ic_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:118:4 + input wire [70:0] ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:119:4 + input wire [25:0] ictag_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:120:4 + output wire [70:0] ic_debug_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:122:4 + output wire [70:0] ifu_ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:124:4 + input wire [pt[1189-:7] - 1:0] ic_eccerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:125:4 + input wire [pt[1189-:7] - 1:0] ic_parerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:126:4 + output wire [63:0] ic_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:127:4 + output wire ic_sel_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:129:4 + output wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:130:4 + output wire ic_debug_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:131:4 + output wire ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:132:4 + output wire ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:133:4 + output wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:136:4 + output wire [pt[1060-:7] - 1:0] ic_tag_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:138:4 + input wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:139:4 + input wire ic_tag_perr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:143:4 + output wire [pt[936-:9] - 1:1] iccm_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:144:4 + output wire iccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:145:4 + output wire iccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:146:4 + output wire [77:0] iccm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:147:4 + output wire [2:0] iccm_wr_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:149:4 + input wire [63:0] iccm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:150:4 + input wire [77:0] iccm_rd_data_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:152:4 + output wire ifu_iccm_rd_ecc_single_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:155:4 + output wire ifu_pmu_ic_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:156:4 + output wire ifu_pmu_ic_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:157:4 + output wire ifu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:158:4 + output wire ifu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:159:4 + output wire ifu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:162:4 + output wire ifu_i0_icaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:163:4 + output wire [1:0] ifu_i0_icaf_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:165:4 + output wire ifu_i0_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:166:4 + output wire ifu_i0_icaf_second; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:167:4 + output wire ifu_i0_dbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:168:4 + output wire iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:169:4 + output wire [31:0] ifu_i0_instr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:170:4 + output wire [31:1] ifu_i0_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:171:4 + output wire ifu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:173:4 + output wire ifu_miss_state_idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:175:4 + // removed localparam type el2_pkg_el2_br_pkt_t + output wire [50:0] i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:176:4 + output wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:177:4 + output wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:178:4 + output wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:179:4 + output wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:181:4 + // removed localparam type el2_pkg_el2_predict_pkt_t + input wire [55:0] exu_mp_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:182:4 + input wire [pt[2236-:8] - 1:0] exu_mp_eghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:183:4 + input wire [pt[2236-:8] - 1:0] exu_mp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:184:4 + input wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:185:4 + input wire [pt[2139-:9] - 1:0] exu_mp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:187:4 + // removed localparam type el2_pkg_el2_br_tlu_pkt_t + input wire [6:0] dec_tlu_br0_r_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:188:4 + input wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:189:4 + input wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:190:4 + input wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:192:4 + input dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:194:4 + output wire [15:0] ifu_i0_cinst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:198:4 + // removed localparam type el2_pkg_el2_cache_debug_pkt_t + input wire [89:0] dec_tlu_ic_diag_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:199:4 + output wire ifu_ic_debug_rd_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:200:4 + output wire iccm_buf_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:201:4 + output wire iccm_correction_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:203:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:206:4 + localparam TAGWIDTH = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:207:4 + localparam IDWIDTH = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:209:4 + wire ifu_fb_consume1; + wire ifu_fb_consume2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:210:4 + wire [31:1] ifc_fetch_addr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:211:4 + wire [31:1] ifc_fetch_addr_bf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:213:4 + wire [1:0] ifu_fetch_val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:214:4 + wire [31:1] ifu_fetch_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:216:4 + wire iccm_rd_ecc_single_err; + wire ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:217:4 + assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:218:4 + assign ifu_ic_error_start = ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:221:4 + wire ic_write_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:222:4 + wire ic_dma_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:223:4 + wire ifc_dma_access_ok; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:224:4 + wire [1:0] ic_access_fault_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:225:4 + wire [1:0] ic_access_fault_type_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:226:4 + wire ifu_ic_mb_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:228:4 + wire ic_hit_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:230:4 + wire [1:0] ifu_bp_way_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:231:4 + wire ifu_bp_hit_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:232:4 + wire [31:1] ifu_bp_btb_target_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:233:4 + wire ifu_bp_inst_mask_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:234:4 + wire [1:0] ifu_bp_hist1_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:235:4 + wire [1:0] ifu_bp_hist0_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:236:4 + wire [11:0] ifu_bp_poffset_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:237:4 + wire [1:0] ifu_bp_ret_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:238:4 + wire [1:0] ifu_bp_pc4_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:239:4 + wire [1:0] ifu_bp_valid_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:240:4 + wire [pt[2236-:8] - 1:0] ifu_bp_fghr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:241:4 + wire [(2 * $clog2(pt[2061-:14])) - 1:0] ifu_bp_fa_index_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:245:4 + wire ifc_fetch_req_bf; + wire ifc_fetch_req_bf_raw; + wire ifc_fetch_req_f; + wire ifc_fetch_uncacheable_bf; + wire ifc_iccm_access_bf; + wire ifc_region_acc_fault_bf; + el2_ifu_ifc_ctl #(.pt(pt)) ifc( + .clk(clk), + .free_l2clk(free_l2clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .ic_hit_f(ic_hit_f), + .ifu_ic_mb_empty(ifu_ic_mb_empty), + .ifu_fb_consume1(ifu_fb_consume1), + .ifu_fb_consume2(ifu_fb_consume2), + .dec_tlu_flush_noredir_wb(dec_tlu_flush_noredir_wb), + .exu_flush_final(exu_flush_final), + .exu_flush_path_final(exu_flush_path_final), + .ifu_bp_hit_taken_f(ifu_bp_hit_taken_f), + .ifu_bp_btb_target_f(ifu_bp_btb_target_f), + .ic_dma_active(ic_dma_active), + .ic_write_stall(ic_write_stall), + .dma_iccm_stall_any(dma_iccm_stall_any), + .dec_tlu_mrac_ff(dec_tlu_mrac_ff), + .ifc_fetch_addr_f(ifc_fetch_addr_f), + .ifc_fetch_addr_bf(ifc_fetch_addr_bf), + .ifc_fetch_req_f(ifc_fetch_req_f), + .ifu_pmu_fetch_stall(ifu_pmu_fetch_stall), + .ifc_fetch_uncacheable_bf(ifc_fetch_uncacheable_bf), + .ifc_fetch_req_bf(ifc_fetch_req_bf), + .ifc_fetch_req_bf_raw(ifc_fetch_req_bf_raw), + .ifc_iccm_access_bf(ifc_iccm_access_bf), + .ifc_region_acc_fault_bf(ifc_region_acc_fault_bf), + .ifc_dma_access_ok(ifc_dma_access_ok) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:249:4 + generate + if (pt[2130-:5] == 1) begin : bpred + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:250:7 + el2_ifu_bp_ctl #(.pt(pt)) bp( + .clk(clk), + .rst_l(rst_l), + .ic_hit_f(ic_hit_f), + .ifc_fetch_addr_f(ifc_fetch_addr_f), + .ifc_fetch_req_f(ifc_fetch_req_f), + .dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt), + .exu_i0_br_fghr_r(exu_i0_br_fghr_r), + .exu_i0_br_index_r(exu_i0_br_index_r), + .dec_fa_error_index(dec_fa_error_index), + .dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb), + .dec_tlu_flush_leak_one_wb(dec_tlu_flush_leak_one_wb), + .dec_tlu_bpred_disable(dec_tlu_bpred_disable), + .exu_mp_pkt(exu_mp_pkt), + .exu_mp_eghr(exu_mp_eghr), + .exu_mp_fghr(exu_mp_fghr), + .exu_mp_index(exu_mp_index), + .exu_mp_btag(exu_mp_btag), + .exu_flush_final(exu_flush_final), + .ifu_bp_hit_taken_f(ifu_bp_hit_taken_f), + .ifu_bp_btb_target_f(ifu_bp_btb_target_f), + .ifu_bp_inst_mask_f(ifu_bp_inst_mask_f), + .ifu_bp_fghr_f(ifu_bp_fghr_f), + .ifu_bp_way_f(ifu_bp_way_f), + .ifu_bp_ret_f(ifu_bp_ret_f), + .ifu_bp_hist1_f(ifu_bp_hist1_f), + .ifu_bp_hist0_f(ifu_bp_hist0_f), + .ifu_bp_pc4_f(ifu_bp_pc4_f), + .ifu_bp_valid_f(ifu_bp_valid_f), + .ifu_bp_poffset_f(ifu_bp_poffset_f), + .ifu_bp_fa_index_f(ifu_bp_fa_index_f), + .scan_mode(scan_mode) + ); + end + else begin : bpred + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:253:7 + assign ifu_bp_hit_taken_f = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:255:7 + wire btb_wr_en_way0; + wire btb_wr_en_way1; + wire dec_tlu_error_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:256:7 + wire [16 + pt[2139-:9]:0] btb_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:257:7 + assign btb_wr_en_way0 = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:258:7 + assign btb_wr_en_way1 = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:259:7 + assign btb_wr_data = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:260:7 + assign dec_tlu_error_wb = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:261:7 + assign ifu_bp_inst_mask_f = 1'b1; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:265:4 + wire [1:0] ic_fetch_val_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:266:4 + wire [31:0] ic_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:267:4 + wire [31:0] ifu_fetch_data_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:268:4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:269:4 + wire ifc_fetch_req_f_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:270:4 + wire [1:0] iccm_rd_ecc_double_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:272:4 + wire ifu_async_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:275:4 + assign ifu_fetch_data_f[31:0] = ic_data_f[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:276:4 + assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:277:4 + assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:279:2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:280:2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:281:2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:282:2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:283:2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:287:4 + el2_ifu_aln_ctl #(.pt(pt)) aln( + .scan_mode(scan_mode), + .rst_l(rst_l), + .clk(clk), + .active_clk(active_clk), + .ifu_async_error_start(ifu_async_error_start), + .iccm_rd_ecc_double_err(iccm_rd_ecc_double_err), + .ic_access_fault_f(ic_access_fault_f), + .ic_access_fault_type_f(ic_access_fault_type_f), + .exu_flush_final(exu_flush_final), + .dec_i0_decode_d(dec_i0_decode_d), + .ifu_fetch_data_f(ifu_fetch_data_f), + .ifu_fetch_val(ifu_fetch_val), + .ifu_fetch_pc(ifu_fetch_pc), + .ifu_i0_valid(ifu_i0_valid), + .ifu_i0_icaf(ifu_i0_icaf), + .ifu_i0_icaf_type(ifu_i0_icaf_type), + .ifu_i0_icaf_second(ifu_i0_icaf_second), + .ifu_i0_dbecc(ifu_i0_dbecc), + .ifu_i0_instr(ifu_i0_instr), + .ifu_i0_pc(ifu_i0_pc), + .ifu_i0_pc4(ifu_i0_pc4), + .ifu_fb_consume1(ifu_fb_consume1), + .ifu_fb_consume2(ifu_fb_consume2), + .ifu_bp_fghr_f(ifu_bp_fghr_f), + .ifu_bp_btb_target_f(ifu_bp_btb_target_f), + .ifu_bp_poffset_f(ifu_bp_poffset_f), + .ifu_bp_fa_index_f(ifu_bp_fa_index_f), + .ifu_bp_hist0_f(ifu_bp_hist0_f), + .ifu_bp_hist1_f(ifu_bp_hist1_f), + .ifu_bp_pc4_f(ifu_bp_pc4_f), + .ifu_bp_way_f(ifu_bp_way_f), + .ifu_bp_valid_f(ifu_bp_valid_f), + .ifu_bp_ret_f(ifu_bp_ret_f), + .i0_brp(i0_brp), + .ifu_i0_bp_index(ifu_i0_bp_index), + .ifu_i0_bp_fghr(ifu_i0_bp_fghr), + .ifu_i0_bp_btag(ifu_i0_bp_btag), + .ifu_i0_fa_index(ifu_i0_fa_index), + .ifu_pmu_instr_aligned(ifu_pmu_instr_aligned), + .ifu_i0_cinst(ifu_i0_cinst) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/ifu/el2_ifu.sv:293:4 + el2_ifu_mem_ctl #(.pt(pt)) mem_ctl( + .clk(clk), + .active_clk(active_clk), + .free_l2clk(free_l2clk), + .rst_l(rst_l), + .exu_flush_final(exu_flush_final), + .dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb), + .dec_tlu_flush_err_wb(dec_tlu_flush_err_wb), + .dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt), + .dec_tlu_force_halt(dec_tlu_force_halt), + .ifc_fetch_addr_bf(ifc_fetch_addr_bf), + .ifc_fetch_uncacheable_bf(ifc_fetch_uncacheable_bf), + .ifc_fetch_req_bf(ifc_fetch_req_bf), + .ifc_fetch_req_bf_raw(ifc_fetch_req_bf_raw), + .ifc_iccm_access_bf(ifc_iccm_access_bf), + .ifc_region_acc_fault_bf(ifc_region_acc_fault_bf), + .ifc_dma_access_ok(ifc_dma_access_ok), + .dec_tlu_fence_i_wb(dec_tlu_fence_i_wb), + .ifu_bp_hit_taken_f(ifu_bp_hit_taken_f), + .ifu_bp_inst_mask_f(ifu_bp_inst_mask_f), + .ifu_miss_state_idle(ifu_miss_state_idle), + .ifu_ic_mb_empty(ifu_ic_mb_empty), + .ic_dma_active(ic_dma_active), + .ic_write_stall(ic_write_stall), + .ifu_pmu_ic_miss(ifu_pmu_ic_miss), + .ifu_pmu_ic_hit(ifu_pmu_ic_hit), + .ifu_pmu_bus_error(ifu_pmu_bus_error), + .ifu_pmu_bus_busy(ifu_pmu_bus_busy), + .ifu_pmu_bus_trxn(ifu_pmu_bus_trxn), + .ifu_axi_awvalid(ifu_axi_awvalid), + .ifu_axi_awid(ifu_axi_awid), + .ifu_axi_awaddr(ifu_axi_awaddr), + .ifu_axi_awregion(ifu_axi_awregion), + .ifu_axi_awlen(ifu_axi_awlen), + .ifu_axi_awsize(ifu_axi_awsize), + .ifu_axi_awburst(ifu_axi_awburst), + .ifu_axi_awlock(ifu_axi_awlock), + .ifu_axi_awcache(ifu_axi_awcache), + .ifu_axi_awprot(ifu_axi_awprot), + .ifu_axi_awqos(ifu_axi_awqos), + .ifu_axi_wvalid(ifu_axi_wvalid), + .ifu_axi_wdata(ifu_axi_wdata), + .ifu_axi_wstrb(ifu_axi_wstrb), + .ifu_axi_wlast(ifu_axi_wlast), + .ifu_axi_bready(ifu_axi_bready), + .ifu_axi_arvalid(ifu_axi_arvalid), + .ifu_axi_arready(ifu_axi_arready), + .ifu_axi_arid(ifu_axi_arid), + .ifu_axi_araddr(ifu_axi_araddr), + .ifu_axi_arregion(ifu_axi_arregion), + .ifu_axi_arlen(ifu_axi_arlen), + .ifu_axi_arsize(ifu_axi_arsize), + .ifu_axi_arburst(ifu_axi_arburst), + .ifu_axi_arlock(ifu_axi_arlock), + .ifu_axi_arcache(ifu_axi_arcache), + .ifu_axi_arprot(ifu_axi_arprot), + .ifu_axi_arqos(ifu_axi_arqos), + .ifu_axi_rvalid(ifu_axi_rvalid), + .ifu_axi_rready(ifu_axi_rready), + .ifu_axi_rid(ifu_axi_rid), + .ifu_axi_rdata(ifu_axi_rdata), + .ifu_axi_rresp(ifu_axi_rresp), + .ifu_bus_clk_en(ifu_bus_clk_en), + .dma_iccm_req(dma_iccm_req), + .dma_mem_addr(dma_mem_addr), + .dma_mem_sz(dma_mem_sz), + .dma_mem_write(dma_mem_write), + .dma_mem_wdata(dma_mem_wdata), + .dma_mem_tag(dma_mem_tag), + .iccm_dma_ecc_error(iccm_dma_ecc_error), + .iccm_dma_rvalid(iccm_dma_rvalid), + .iccm_dma_rdata(iccm_dma_rdata), + .iccm_dma_rtag(iccm_dma_rtag), + .iccm_ready(iccm_ready), + .ic_rw_addr(ic_rw_addr), + .ic_wr_en(ic_wr_en), + .ic_rd_en(ic_rd_en), + .ic_wr_data(ic_wr_data), + .ic_rd_data(ic_rd_data), + .ic_debug_rd_data(ic_debug_rd_data), + .ictag_debug_rd_data(ictag_debug_rd_data), + .ic_debug_wr_data(ic_debug_wr_data), + .ifu_ic_debug_rd_data(ifu_ic_debug_rd_data), + .ic_eccerr(ic_eccerr), + .ic_parerr(ic_parerr), + .ic_debug_addr(ic_debug_addr), + .ic_debug_rd_en(ic_debug_rd_en), + .ic_debug_wr_en(ic_debug_wr_en), + .ic_debug_tag_array(ic_debug_tag_array), + .ic_debug_way(ic_debug_way), + .ic_tag_valid(ic_tag_valid), + .ic_rd_hit(ic_rd_hit), + .ic_tag_perr(ic_tag_perr), + .iccm_rw_addr(iccm_rw_addr), + .iccm_wren(iccm_wren), + .iccm_rden(iccm_rden), + .iccm_wr_data(iccm_wr_data), + .iccm_wr_size(iccm_wr_size), + .iccm_rd_data(iccm_rd_data), + .iccm_rd_data_ecc(iccm_rd_data_ecc), + .ifu_fetch_val(ifu_fetch_val), + .ic_hit_f(ic_hit_f), + .ic_access_fault_f(ic_access_fault_f), + .ic_access_fault_type_f(ic_access_fault_type_f), + .iccm_rd_ecc_single_err(iccm_rd_ecc_single_err), + .iccm_rd_ecc_double_err(iccm_rd_ecc_double_err), + .ic_error_start(ic_error_start), + .ifu_async_error_start(ifu_async_error_start), + .iccm_dma_sb_error(iccm_dma_sb_error), + .ic_fetch_val_f(ic_fetch_val_f), + .ic_premux_data(ic_premux_data), + .ic_sel_premux_data(ic_sel_premux_data), + .dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid), + .iccm_buf_correct_ecc(iccm_buf_correct_ecc), + .iccm_correction_state(iccm_correction_state), + .scan_mode(scan_mode), + .ic_data_f(ic_data_f[31:0]) + ); +endmodule +module el2_dec_decode_ctl ( + dec_tlu_trace_disable, + dec_debug_valid_d, + dec_tlu_flush_extint, + dec_tlu_force_halt, + dec_extint_stall, + ifu_i0_cinst, + dec_i0_inst_wb, + dec_i0_pc_wb, + lsu_nonblock_load_valid_m, + lsu_nonblock_load_tag_m, + lsu_nonblock_load_inv_r, + lsu_nonblock_load_inv_tag_r, + lsu_nonblock_load_data_valid, + lsu_nonblock_load_data_error, + lsu_nonblock_load_data_tag, + dec_i0_trigger_match_d, + dec_tlu_wr_pause_r, + dec_tlu_pipelining_disable, + lsu_trigger_match_m, + lsu_pmu_misaligned_m, + dec_tlu_debug_stall, + dec_tlu_flush_leak_one_r, + dec_debug_fence_d, + dbg_cmd_wrdata, + dec_i0_icaf_d, + dec_i0_icaf_second_d, + dec_i0_icaf_type_d, + dec_i0_dbecc_d, + dec_i0_brp, + dec_i0_bp_index, + dec_i0_bp_fghr, + dec_i0_bp_btag, + dec_i0_bp_fa_index, + lsu_idle_any, + lsu_load_stall_any, + lsu_store_stall_any, + dma_dccm_stall_any, + exu_div_wren, + dec_tlu_i0_kill_writeb_wb, + dec_tlu_flush_lower_wb, + dec_tlu_i0_kill_writeb_r, + dec_tlu_flush_lower_r, + dec_tlu_flush_pause_r, + dec_tlu_presync_d, + dec_tlu_postsync_d, + dec_i0_pc4_d, + dec_csr_rddata_d, + dec_csr_legal_d, + exu_csr_rs1_x, + lsu_result_m, + lsu_result_corr_r, + exu_flush_final, + exu_i0_pc_x, + dec_i0_instr_d, + dec_ib0_valid_d, + exu_i0_result_x, + clk, + active_clk, + free_l2clk, + clk_override, + rst_l, + dec_i0_rs1_en_d, + dec_i0_rs2_en_d, + dec_i0_rs1_d, + dec_i0_rs2_d, + dec_i0_immed_d, + dec_i0_br_immed_d, + i0_ap, + dec_i0_decode_d, + dec_i0_alu_decode_d, + dec_i0_branch_d, + dec_i0_waddr_r, + dec_i0_wen_r, + dec_i0_wdata_r, + dec_i0_select_pc_d, + dec_i0_rs1_bypass_en_d, + dec_i0_rs2_bypass_en_d, + dec_i0_result_r, + lsu_p, + dec_qual_lsu_d, + mul_p, + div_p, + div_waddr_wb, + dec_div_cancel, + dec_lsu_valid_raw_d, + dec_lsu_offset_d, + dec_csr_ren_d, + dec_csr_wen_unq_d, + dec_csr_any_unq_d, + dec_csr_rdaddr_d, + dec_csr_wen_r, + dec_csr_wraddr_r, + dec_csr_wrdata_r, + dec_csr_stall_int_ff, + dec_tlu_i0_valid_r, + dec_tlu_packet_r, + dec_tlu_i0_pc_r, + dec_illegal_inst, + pred_correct_npc_x, + dec_i0_predict_p_d, + i0_predict_fghr_d, + i0_predict_index_d, + i0_predict_btag_d, + dec_fa_error_index, + dec_data_en, + dec_ctl_en, + dec_pmu_instr_decoded, + dec_pmu_decode_stall, + dec_pmu_presync_stall, + dec_pmu_postsync_stall, + dec_nonblock_load_wen, + dec_nonblock_load_waddr, + dec_pause_state, + dec_pause_state_cg, + dec_div_active, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:23:4 + input wire dec_tlu_trace_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:24:4 + input wire dec_debug_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:26:4 + input wire dec_tlu_flush_extint; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:28:4 + input wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:30:4 + output wire dec_extint_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:32:4 + input wire [15:0] ifu_i0_cinst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:33:4 + output wire [31:0] dec_i0_inst_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:34:4 + output wire [31:1] dec_i0_pc_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:37:4 + input wire lsu_nonblock_load_valid_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:38:4 + input wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:39:4 + input wire lsu_nonblock_load_inv_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:40:4 + input wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:41:4 + input wire lsu_nonblock_load_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:42:4 + input wire lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:43:4 + input wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:46:4 + input wire [3:0] dec_i0_trigger_match_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:48:4 + input wire dec_tlu_wr_pause_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:49:4 + input wire dec_tlu_pipelining_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:51:4 + input wire [3:0] lsu_trigger_match_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:53:4 + input wire lsu_pmu_misaligned_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:54:4 + input wire dec_tlu_debug_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:55:4 + input wire dec_tlu_flush_leak_one_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:57:4 + input wire dec_debug_fence_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:59:4 + input wire [1:0] dbg_cmd_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:61:4 + input wire dec_i0_icaf_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:62:4 + input wire dec_i0_icaf_second_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:63:4 + input wire [1:0] dec_i0_icaf_type_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:65:4 + input wire dec_i0_dbecc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:67:4 + // removed localparam type el2_pkg_el2_br_pkt_t + input wire [50:0] dec_i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:68:4 + input wire [pt[2172-:9]:pt[2163-:6]] dec_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:69:4 + input wire [pt[2236-:8] - 1:0] dec_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:70:4 + input wire [pt[2139-:9] - 1:0] dec_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:71:4 + input wire [$clog2(pt[2061-:14]) - 1:0] dec_i0_bp_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:73:4 + input wire lsu_idle_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:75:4 + input wire lsu_load_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:76:4 + input wire lsu_store_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:77:4 + input wire dma_dccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:79:4 + input wire exu_div_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:81:4 + input wire dec_tlu_i0_kill_writeb_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:82:4 + input wire dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:83:4 + input wire dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:84:4 + input wire dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:85:4 + input wire dec_tlu_flush_pause_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:86:4 + input wire dec_tlu_presync_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:87:4 + input wire dec_tlu_postsync_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:89:4 + input wire dec_i0_pc4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:91:4 + input wire [31:0] dec_csr_rddata_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:92:4 + input wire dec_csr_legal_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:94:4 + input wire [31:0] exu_csr_rs1_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:96:4 + input wire [31:0] lsu_result_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:97:4 + input wire [31:0] lsu_result_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:99:4 + input wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:101:4 + input wire [31:1] exu_i0_pc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:103:4 + input wire [31:0] dec_i0_instr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:105:4 + input wire dec_ib0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:107:4 + input wire [31:0] exu_i0_result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:109:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:110:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:111:4 + input wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:113:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:114:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:118:4 + output wire dec_i0_rs1_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:119:4 + output wire dec_i0_rs2_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:121:4 + output wire [4:0] dec_i0_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:122:4 + output wire [4:0] dec_i0_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:124:4 + output wire [31:0] dec_i0_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:127:4 + output wire [12:1] dec_i0_br_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:129:4 + // removed localparam type el2_pkg_el2_alu_pkt_t + output wire [41:0] i0_ap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:131:4 + output wire dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:133:4 + output wire dec_i0_alu_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:134:4 + output wire dec_i0_branch_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:136:4 + output wire [4:0] dec_i0_waddr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:137:4 + output wire dec_i0_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:138:4 + output wire [31:0] dec_i0_wdata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:140:4 + output wire dec_i0_select_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:142:4 + output wire [3:0] dec_i0_rs1_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:143:4 + output wire [3:0] dec_i0_rs2_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:144:4 + output wire [31:0] dec_i0_result_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:146:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + output reg [13:0] lsu_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:147:4 + output wire dec_qual_lsu_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:149:4 + // removed localparam type el2_pkg_el2_mul_pkt_t + output wire [22:0] mul_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:151:4 + // removed localparam type el2_pkg_el2_div_pkt_t + output wire [2:0] div_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:152:4 + output wire [4:0] div_waddr_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:153:4 + output wire dec_div_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:155:4 + output wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:156:4 + output wire [11:0] dec_lsu_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:158:4 + output wire dec_csr_ren_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:159:4 + output wire dec_csr_wen_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:160:4 + output wire dec_csr_any_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:161:4 + output wire [11:0] dec_csr_rdaddr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:162:4 + output wire dec_csr_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:163:4 + output wire [11:0] dec_csr_wraddr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:164:4 + output wire [31:0] dec_csr_wrdata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:165:4 + output wire dec_csr_stall_int_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:167:4 + output wire dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:169:4 + // removed localparam type el2_pkg_el2_inst_pkt_t + // removed localparam type el2_pkg_el2_trap_pkt_t + output reg [16:0] dec_tlu_packet_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:171:4 + output wire [31:1] dec_tlu_i0_pc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:173:4 + output wire [31:0] dec_illegal_inst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:174:4 + output wire [31:1] pred_correct_npc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:176:4 + // removed localparam type el2_pkg_el2_predict_pkt_t + output reg [55:0] dec_i0_predict_p_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:177:4 + output wire [pt[2236-:8] - 1:0] i0_predict_fghr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:178:4 + output wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:179:4 + output wire [pt[2139-:9] - 1:0] i0_predict_btag_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:181:4 + output wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:183:4 + output wire [1:0] dec_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:184:4 + output wire [1:0] dec_ctl_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:186:4 + output wire dec_pmu_instr_decoded; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:187:4 + output wire dec_pmu_decode_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:188:4 + output wire dec_pmu_presync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:189:4 + output wire dec_pmu_postsync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:191:4 + output wire dec_nonblock_load_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:192:4 + output reg [4:0] dec_nonblock_load_waddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:193:4 + output wire dec_pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:194:4 + output wire dec_pause_state_cg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:196:4 + output wire dec_div_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:198:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:204:4 + // removed localparam type el2_pkg_el2_dec_pkt_t + wire [95:0] i0_dp_raw; + reg [95:0] i0_dp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:206:4 + wire [31:0] i0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:207:4 + wire i0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:209:4 + wire [31:0] i0_result_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:211:4 + wire [2:0] i0_rs1bypass; + wire [2:0] i0_rs2bypass; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:213:4 + wire i0_jalimm20; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:214:4 + wire i0_uiimm20; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:216:4 + wire lsu_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:217:4 + wire [31:0] i0_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:218:4 + wire i0_presync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:219:4 + wire i0_postsync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:221:4 + wire postsync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:222:4 + wire ps_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:224:4 + wire prior_inflight; + wire prior_inflight_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:226:4 + wire csr_clr_d; + wire csr_set_d; + wire csr_write_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:228:4 + wire csr_clr_x; + wire csr_set_x; + wire csr_write_x; + wire csr_imm_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:229:4 + wire [31:0] csr_mask_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:230:4 + wire [31:0] write_csr_data_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:231:4 + wire [31:0] write_csr_data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:232:4 + wire [31:0] write_csr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:233:4 + wire csr_data_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:235:4 + wire [4:0] csrimm_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:237:4 + wire [31:0] csr_rddata_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:239:4 + wire mul_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:240:4 + wire div_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:241:4 + wire div_e1_to_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:242:4 + wire div_flush; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:243:4 + wire div_active_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:244:4 + wire div_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:245:4 + wire i0_nonblock_div_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:246:4 + wire i0_div_prior_div_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:247:4 + wire nonblock_div_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:249:4 + wire i0_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:250:4 + wire shift_illegal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:251:4 + wire illegal_inst_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:252:4 + wire illegal_lockout_in; + wire illegal_lockout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:253:4 + wire i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:254:4 + wire i0_exulegal_decode_d; + wire i0_exudecode_d; + wire i0_exublock_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:256:4 + wire [12:1] last_br_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:257:4 + wire i0_rs1_depend_i0_x; + wire i0_rs1_depend_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:258:4 + wire i0_rs2_depend_i0_x; + wire i0_rs2_depend_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:260:4 + wire i0_div_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:261:4 + wire i0_load_block_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:262:4 + wire [1:0] i0_rs1_depth_d; + wire [1:0] i0_rs2_depth_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:264:4 + wire i0_load_stall_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:265:4 + wire i0_store_stall_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:267:4 + wire i0_predict_nt; + wire i0_predict_t; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:269:4 + wire i0_notbr_error; + wire i0_br_toffset_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:270:4 + wire i0_ret_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:271:4 + wire i0_br_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:272:4 + wire i0_br_error_all; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:273:4 + wire [11:0] i0_br_offset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:275:4 + wire [20:1] i0_pcall_imm; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:276:4 + wire i0_pcall_12b_offset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:277:4 + wire i0_pcall_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:278:4 + wire i0_pcall_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:279:4 + wire i0_pcall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:281:4 + wire i0_pja_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:282:4 + wire i0_pja_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:283:4 + wire i0_pja; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:285:4 + wire i0_pret_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:286:4 + wire i0_pret_raw; + wire i0_pret; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:288:4 + wire i0_jal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:291:4 + wire i0_predict_br; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:293:4 + wire store_data_bypass_d; + wire store_data_bypass_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:295:4 + // removed localparam type el2_pkg_el2_class_pkt_t + wire [2:0] i0_rs1_class_d; + wire [2:0] i0_rs2_class_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:297:4 + wire [2:0] i0_d_c; + wire [2:0] i0_x_c; + wire [2:0] i0_r_c; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:300:4 + wire i0_ap_pc2; + wire i0_ap_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:302:4 + wire i0_rd_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:304:4 + wire load_ldst_bypass_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:306:4 + wire leak1_i0_stall_in; + wire leak1_i0_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:307:4 + wire leak1_i1_stall_in; + wire leak1_i1_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:308:4 + wire leak1_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:310:4 + wire i0_csr_write_only_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:312:4 + wire prior_inflight_x; + wire prior_inflight_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:313:4 + wire any_csr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:315:4 + wire prior_csr_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:317:4 + wire [3:0] i0_pipe_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:318:4 + wire i0_r_ctl_en; + wire i0_x_ctl_en; + wire i0_wb_ctl_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:319:4 + wire i0_x_data_en; + wire i0_r_data_en; + wire i0_wb_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:321:4 + wire debug_fence_i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:322:4 + wire debug_fence; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:324:4 + wire i0_csr_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:325:4 + wire presync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:327:4 + wire i0_instr_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:328:4 + wire i0_icaf_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:330:4 + wire clear_pause; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:331:4 + wire pause_state_in; + wire pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:332:4 + wire pause_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:334:4 + wire i0_brp_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:335:4 + wire nonblock_load_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:336:4 + wire lsu_idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:337:4 + wire lsu_pmu_misaligned_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:338:4 + wire csr_ren_qual_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:339:4 + wire csr_read_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:340:4 + wire i0_block_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:341:4 + wire i0_block_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:342:4 + wire ps_stall_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:343:4 + wire [31:0] i0_result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:345:4 + // removed localparam type el2_pkg_el2_dest_pkt_t + wire [23:0] d_d; + wire [23:0] x_d; + wire [23:0] r_d; + wire [23:0] wbd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:346:4 + reg [23:0] x_d_in; + reg [23:0] r_d_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:348:4 + wire [16:0] d_t; + wire [16:0] x_t; + reg [16:0] x_t_in; + reg [16:0] r_t_in; + wire [16:0] r_t; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:350:4 + wire [3:0] lsu_trigger_match_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:352:4 + wire [31:1] dec_i0_pc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:354:4 + wire csr_read; + wire csr_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:355:4 + wire i0_br_unpred; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:357:4 + wire nonblock_load_valid_m_delay; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:358:4 + wire i0_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:360:4 + wire tlu_wr_pause_r1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:361:4 + wire tlu_wr_pause_r2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:363:4 + wire flush_final_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:365:4 + wire bitmanip_zbb_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:366:4 + wire bitmanip_zbs_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:367:4 + wire bitmanip_zbe_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:368:4 + wire bitmanip_zbc_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:369:4 + wire bitmanip_zbp_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:370:4 + wire bitmanip_zbr_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:371:4 + wire bitmanip_zbf_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:372:4 + wire bitmanip_zba_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:373:4 + wire bitmanip_zbb_zbp_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:374:4 + wire bitmanip_zbp_zbe_zbf_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:375:4 + wire bitmanip_zbb_zbp_zbe_zbf_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:376:4 + wire bitmanip_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:378:4 + wire data_gate_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:379:4 + wire data_gate_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:382:4 + localparam NBLOAD_SIZE = pt[173-:9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:383:4 + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + localparam NBLOAD_SIZE_MSB = sv2v_cast_32_signed(pt[173-:9]) - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:384:4 + localparam NBLOAD_TAG_MSB = pt[164-:7] - 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:387:4 + wire cam_write; + wire cam_inv_reset; + wire cam_data_reset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:388:4 + wire [NBLOAD_TAG_MSB:0] cam_write_tag; + wire [NBLOAD_TAG_MSB:0] cam_inv_reset_tag; + wire [NBLOAD_TAG_MSB:0] cam_data_reset_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:389:4 + reg [NBLOAD_SIZE_MSB:0] cam_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:391:4 + wire [NBLOAD_TAG_MSB:0] load_data_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:392:4 + wire [NBLOAD_SIZE_MSB:0] nonblock_load_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:394:4 + // removed localparam type el2_pkg_el2_load_cam_pkt_t + reg [(NBLOAD_SIZE_MSB >= 0 ? ((NBLOAD_SIZE_MSB + 1) * 10) - 1 : ((1 - NBLOAD_SIZE_MSB) * 10) + ((NBLOAD_SIZE_MSB * 10) - 1)):(NBLOAD_SIZE_MSB >= 0 ? 0 : NBLOAD_SIZE_MSB * 10)] cam; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:395:4 + reg [(NBLOAD_SIZE_MSB >= 0 ? ((NBLOAD_SIZE_MSB + 1) * 10) - 1 : ((1 - NBLOAD_SIZE_MSB) * 10) + ((NBLOAD_SIZE_MSB * 10) - 1)):(NBLOAD_SIZE_MSB >= 0 ? 0 : NBLOAD_SIZE_MSB * 10)] cam_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:396:4 + wire [(NBLOAD_SIZE_MSB >= 0 ? ((NBLOAD_SIZE_MSB + 1) * 10) - 1 : ((1 - NBLOAD_SIZE_MSB) * 10) + ((NBLOAD_SIZE_MSB * 10) - 1)):(NBLOAD_SIZE_MSB >= 0 ? 0 : NBLOAD_SIZE_MSB * 10)] cam_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:398:4 + wire [4:0] nonblock_load_rd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:399:4 + reg i0_nonblock_load_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:400:4 + wire i0_nonblock_boundary_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:402:4 + wire i0_rs1_nonblock_load_bypass_en_d; + wire i0_rs2_nonblock_load_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:404:4 + wire i0_load_kill_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:406:4 + reg found; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:408:4 + wire [NBLOAD_SIZE_MSB:0] cam_inv_reset_val; + wire [NBLOAD_SIZE_MSB:0] cam_data_reset_val; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:410:4 + wire debug_fence_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:412:4 + wire [31:0] i0_result_r_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:413:4 + wire [31:0] i0_result_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:415:4 + wire [12:1] last_br_immed_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:417:4 + wire [31:0] i0_inst_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:418:4 + wire [31:0] i0_inst_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:419:4 + wire [31:0] i0_inst_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:420:4 + wire [31:0] i0_inst_wb_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:421:4 + wire [31:0] i0_inst_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:423:4 + wire [31:1] i0_pc_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:425:4 + wire i0_wb_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:427:4 + wire trace_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:429:4 + wire debug_valid_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:431:4 + reg [3:0] i0_itype; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:432:4 + // removed localparam type el2_pkg_el2_reg_pkt_t + wire [14:0] i0r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:435:4 + rvdffie #(.WIDTH(8)) misc1ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({leak1_i1_stall_in, leak1_i0_stall_in, dec_tlu_flush_extint, pause_state_in, dec_tlu_wr_pause_r, tlu_wr_pause_r1, illegal_lockout_in, ps_stall_in}), + .dout({leak1_i1_stall, leak1_i0_stall, dec_extint_stall, pause_state, tlu_wr_pause_r1, tlu_wr_pause_r2, illegal_lockout, ps_stall}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:441:4 + rvdffie #(.WIDTH(8)) misc2ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({lsu_trigger_match_m[3:0], lsu_pmu_misaligned_m, div_active_in, exu_flush_final, dec_debug_valid_d}), + .dout({lsu_trigger_match_r[3:0], lsu_pmu_misaligned_r, div_active, flush_final_r, debug_valid_x}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:447:1 + generate + if (pt[2130-:5] == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:453:4 + assign i0_brp_valid = (dec_i0_brp[50] & ~leak1_mode) & ~i0_icaf_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:455:4 + wire [1:1] sv2v_tmp_700E5; + assign sv2v_tmp_700E5 = 1'sb0; + always @(*) dec_i0_predict_p_d[55] = sv2v_tmp_700E5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:456:4 + wire [1:1] sv2v_tmp_56394; + assign sv2v_tmp_56394 = 1'sb0; + always @(*) dec_i0_predict_p_d[54] = sv2v_tmp_56394; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:457:4 + wire [1:1] sv2v_tmp_3B483; + assign sv2v_tmp_3B483 = 1'sb0; + always @(*) dec_i0_predict_p_d[53] = sv2v_tmp_3B483; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:459:4 + wire [1:1] sv2v_tmp_D4DAE; + assign sv2v_tmp_D4DAE = i0_pcall; + always @(*) dec_i0_predict_p_d[34] = sv2v_tmp_D4DAE; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:460:4 + wire [1:1] sv2v_tmp_1648E; + assign sv2v_tmp_1648E = i0_pja; + always @(*) dec_i0_predict_p_d[33] = sv2v_tmp_1648E; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:461:4 + wire [1:1] sv2v_tmp_D905B; + assign sv2v_tmp_D905B = i0_pret; + always @(*) dec_i0_predict_p_d[31] = sv2v_tmp_D905B; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:462:4 + wire [31:1] sv2v_tmp_079FA; + assign sv2v_tmp_079FA = dec_i0_brp[32:2]; + always @(*) dec_i0_predict_p_d[30:0] = sv2v_tmp_079FA; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:463:4 + wire [1:1] sv2v_tmp_AE159; + assign sv2v_tmp_AE159 = dec_i0_pc4_d; + always @(*) dec_i0_predict_p_d[52] = sv2v_tmp_AE159; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:464:4 + wire [2:1] sv2v_tmp_F689C; + assign sv2v_tmp_F689C = dec_i0_brp[37:36]; + always @(*) dec_i0_predict_p_d[51:50] = sv2v_tmp_F689C; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:465:4 + wire [1:1] sv2v_tmp_9D575; + assign sv2v_tmp_9D575 = i0_brp_valid & i0_legal_decode_d; + always @(*) dec_i0_predict_p_d[37] = sv2v_tmp_9D575; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:466:4 + assign i0_notbr_error = i0_brp_valid & ~(((i0_dp_raw[28] | i0_pcall_raw) | i0_pja_raw) | i0_pret_raw); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:469:4 + assign i0_br_toffset_error = ((i0_brp_valid & dec_i0_brp[37]) & (dec_i0_brp[49:38] != i0_br_offset[11:0])) & ~i0_pret_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:470:4 + assign i0_ret_error = i0_brp_valid & (dec_i0_brp[0] ^ i0_pret_raw); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:471:4 + assign i0_br_error = ((dec_i0_brp[35] | i0_notbr_error) | i0_br_toffset_error) | i0_ret_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:472:4 + wire [1:1] sv2v_tmp_922EC; + assign sv2v_tmp_922EC = (i0_br_error & i0_legal_decode_d) & ~leak1_mode; + always @(*) dec_i0_predict_p_d[36] = sv2v_tmp_922EC; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:473:4 + wire [1:1] sv2v_tmp_DF637; + assign sv2v_tmp_DF637 = (dec_i0_brp[34] & i0_legal_decode_d) & ~leak1_mode; + always @(*) dec_i0_predict_p_d[35] = sv2v_tmp_DF637; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:474:4 + assign i0_predict_index_d[pt[2172-:9]:pt[2163-:6]] = dec_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:476:4 + assign i0_predict_btag_d[pt[2139-:9] - 1:0] = dec_i0_bp_btag[pt[2139-:9] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:477:4 + assign i0_br_error_all = (i0_br_error | dec_i0_brp[34]) & ~leak1_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:478:4 + wire [12:1] sv2v_tmp_CA126; + assign sv2v_tmp_CA126 = i0_br_offset[11:0]; + always @(*) dec_i0_predict_p_d[49:38] = sv2v_tmp_CA126; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:479:4 + assign i0_predict_fghr_d[pt[2236-:8] - 1:0] = dec_i0_bp_fghr[pt[2236-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:480:4 + wire [1:1] sv2v_tmp_008B7; + assign sv2v_tmp_008B7 = dec_i0_brp[1]; + always @(*) dec_i0_predict_p_d[32] = sv2v_tmp_008B7; + if (pt[2120-:5]) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:484:7 + wire btb_error_found; + wire btb_error_found_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:485:7 + wire [$clog2(pt[2061-:14]) - 1:0] fa_error_index_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:487:7 + assign btb_error_found = (i0_br_error_all | btb_error_found_f) & ~dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:488:7 + assign fa_error_index_ns = (i0_br_error_all & ~btb_error_found_f ? dec_i0_bp_fa_index : dec_fa_error_index); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:490:7 + rvdff #(.WIDTH($clog2(pt[2061-:14]) + 1)) btberrorfa_f( + .rst_l(rst_l), + .clk(active_clk), + .din({btb_error_found, fa_error_index_ns}), + .dout({btb_error_found_f, dec_fa_error_index}) + ); + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:497:6 + assign dec_fa_error_index = 'b0; + end + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:504:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:505:7 + dec_i0_predict_p_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:506:7 + dec_i0_predict_p_d[34] = i0_pcall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:507:7 + dec_i0_predict_p_d[33] = i0_pja; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:508:7 + dec_i0_predict_p_d[31] = i0_pret; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:509:7 + dec_i0_predict_p_d[52] = dec_i0_pc4_d; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:512:4 + assign i0_br_error_all = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:513:4 + assign i0_predict_index_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:514:4 + assign i0_predict_btag_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:515:4 + assign i0_predict_fghr_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:516:4 + assign i0_brp_valid = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:523:4 + assign i0_icaf_d = dec_i0_icaf_d | dec_i0_dbecc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:525:4 + assign i0_instr_error = i0_icaf_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:527:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:528:7 + i0_dp = i0_dp_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:529:7 + if (i0_br_error_all | i0_instr_error) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:530:10 + i0_dp = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:531:10 + i0_dp[49] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:532:10 + i0_dp[48] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:533:10 + i0_dp[47] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:534:10 + i0_dp[35] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:535:10 + i0_dp[0] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:536:10 + i0_dp[13] = 1'b1; + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:540:4 + assign i0[31:0] = dec_i0_instr_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:542:4 + assign dec_i0_select_pc_d = i0_dp[42]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:546:4 + assign i0_predict_br = ((i0_dp[28] | i0_pcall) | i0_pja) | i0_pret; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:548:4 + assign i0_predict_nt = ~(dec_i0_brp[37] & i0_brp_valid) & i0_predict_br; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:549:4 + assign i0_predict_t = (dec_i0_brp[37] & i0_brp_valid) & i0_predict_br; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:551:4 + assign i0_ap[8] = i0_dp[38]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:552:4 + assign i0_ap[7] = i0_dp[37]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:553:4 + assign i0_ap[18] = i0_dp[36]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:554:4 + assign i0_ap[17] = i0_dp[35]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:555:4 + assign i0_ap[16] = i0_dp[34]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:556:4 + assign i0_ap[15] = i0_dp[33]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:557:4 + assign i0_ap[14] = i0_dp[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:558:4 + assign i0_ap[13] = i0_dp[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:559:4 + assign i0_ap[6] = i0_dp[30]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:560:4 + assign i0_ap[5] = i0_dp[29]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:561:4 + assign i0_ap[12] = i0_dp[27]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:562:4 + assign i0_ap[11] = i0_dp[26]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:563:4 + assign i0_ap[10] = i0_dp[24]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:564:4 + assign i0_ap[9] = i0_dp[25]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:566:4 + assign i0_ap[41] = i0_dp[95]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:567:4 + assign i0_ap[40] = i0_dp[94]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:568:4 + assign i0_ap[39] = i0_dp[93]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:569:4 + assign i0_ap[38] = i0_dp[92]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:570:4 + assign i0_ap[37] = i0_dp[91]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:571:4 + assign i0_ap[22] = i0_dp[53]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:572:4 + assign i0_ap[21] = i0_dp[52]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:573:4 + assign i0_ap[20] = i0_dp[51]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:574:4 + assign i0_ap[19] = i0_dp[50]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:575:4 + assign i0_ap[36] = i0_dp[90]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:576:4 + assign i0_ap[35] = i0_dp[89]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:577:4 + assign i0_ap[34] = i0_dp[88]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:578:4 + assign i0_ap[33] = i0_dp[87]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:579:4 + assign i0_ap[32] = i0_dp[86]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:580:4 + assign i0_ap[31] = i0_dp[85]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:581:4 + assign i0_ap[30] = i0_dp[84]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:582:4 + assign i0_ap[29] = i0_dp[83]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:583:4 + assign i0_ap[28] = i0_dp[82]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:584:4 + assign i0_ap[27] = i0_dp[81]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:585:4 + assign i0_ap[26] = i0_dp[80]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:586:4 + assign i0_ap[25] = i0_dp[79]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:587:4 + assign i0_ap[24] = i0_dp[78]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:588:4 + assign i0_ap[23] = i0_dp[77]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:590:4 + assign i0_ap[1] = i0_csr_write_only_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:591:4 + assign i0_ap[0] = i0_dp[15]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:592:4 + assign i0_ap[4] = i0_jal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:594:4 + assign i0_ap_pc2 = ~dec_i0_pc4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:595:4 + assign i0_ap_pc4 = dec_i0_pc4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:597:4 + assign i0_ap[2] = i0_predict_nt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:598:4 + assign i0_ap[3] = i0_predict_t; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:603:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:604:7 + found = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:605:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:605:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:605:12 + for (i = 0; i < NBLOAD_SIZE; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:606:10 + if (~found) begin + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:607:13 + if (~cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:608:16 + cam_wen[i] = cam_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:609:16 + found = 1'b1; + end + else + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:612:16 + cam_wen[i] = 0; + end + end + else + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:616:13 + cam_wen[i] = 0; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:620:4 + assign cam_write = lsu_nonblock_load_valid_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:621:4 + assign cam_write_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_tag_m[NBLOAD_TAG_MSB:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:623:4 + assign cam_inv_reset = lsu_nonblock_load_inv_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:624:4 + assign cam_inv_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:626:4 + assign cam_data_reset = lsu_nonblock_load_data_valid | lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:627:4 + assign cam_data_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:629:4 + assign nonblock_load_rd[4:0] = (x_d[3] ? x_d[8:4] : 5'b00000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:644:4 + genvar _gv_i_33; + generate + for (_gv_i_33 = 0; _gv_i_33 < NBLOAD_SIZE; _gv_i_33 = _gv_i_33 + 1) begin : cam_array + localparam i = _gv_i_33; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:646:7 + assign cam_inv_reset_val[i] = (cam_inv_reset & (cam_inv_reset_tag[NBLOAD_TAG_MSB:0] == cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))])) & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:648:7 + assign cam_data_reset_val[i] = (cam_data_reset & (cam_data_reset_tag[NBLOAD_TAG_MSB:0] == cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))])) & cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:650:7 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:652:10 + cam[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10] = cam_raw[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:654:10 + if (cam_data_reset_val[i]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:655:12 + cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:657:10 + cam_in[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10] = 1'sb0; + if (cam_wen[i]) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:660:13 + cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:661:13 + cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 8] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:662:13 + cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))] = cam_write_tag[NBLOAD_TAG_MSB:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:663:13 + cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5] = nonblock_load_rd[4:0]; + end + else if (cam_inv_reset_val[i] | ((i0_wen_r & (r_d_in[8:4] == cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5])) & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 8])) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:667:12 + cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b0; + else + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:669:12 + cam_in[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10] = cam[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10]; + if ((nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0] == cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))])) & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:672:12 + cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 8] = 1'b1; + if (dec_tlu_force_halt) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:676:12 + cam_in[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9] = 1'b0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:680:4 + rvdffie #(.WIDTH(10)) cam_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(cam_in[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10]), + .dout(cam_raw[(NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10+:10]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:683:4 + assign nonblock_load_write[i] = (load_data_tag[NBLOAD_TAG_MSB:0] == cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + ((5 + NBLOAD_TAG_MSB) >= 5 ? 5 + NBLOAD_TAG_MSB : ((5 + NBLOAD_TAG_MSB) + ((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))) - 1)-:((5 + NBLOAD_TAG_MSB) >= 5 ? (5 + NBLOAD_TAG_MSB) - 4 : 6 - (5 + NBLOAD_TAG_MSB))]) & cam_raw[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:690:4 + assign load_data_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:697:4 + assign nonblock_load_cancel = (r_d_in[8:4] == dec_nonblock_load_waddr[4:0]) & i0_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:700:4 + assign dec_nonblock_load_wen = (lsu_nonblock_load_data_valid & |nonblock_load_write[NBLOAD_SIZE_MSB:0]) & ~nonblock_load_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:702:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:704:7 + dec_nonblock_load_waddr[4:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:705:7 + i0_nonblock_load_stall = i0_nonblock_boundary_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:707:7 + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:707:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:707:12 + for (i = 0; i < NBLOAD_SIZE; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:708:10 + dec_nonblock_load_waddr[4:0] = dec_nonblock_load_waddr[4:0] | ({5 {nonblock_load_write[i]}} & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:709:10 + i0_nonblock_load_stall = i0_nonblock_load_stall | ((dec_i0_rs1_en_d & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]) & (cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5] == i0r[14:10])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:710:10 + i0_nonblock_load_stall = i0_nonblock_load_stall | ((dec_i0_rs2_en_d & cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 9]) & (cam[((NBLOAD_SIZE_MSB >= 0 ? i : NBLOAD_SIZE_MSB - i) * 10) + 4-:5] == i0r[9:5])); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:715:4 + assign i0_nonblock_boundary_stall = (((nonblock_load_rd[4:0] == i0r[14:10]) & lsu_nonblock_load_valid_m) & dec_i0_rs1_en_d) | (((nonblock_load_rd[4:0] == i0r[9:5]) & lsu_nonblock_load_valid_m) & dec_i0_rs2_en_d); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:722:4 + rvdffs #(.WIDTH(1)) wbnbloaddelayff( + .rst_l(rst_l), + .clk(active_clk), + .en(i0_r_ctl_en), + .din(lsu_nonblock_load_valid_m), + .dout(nonblock_load_valid_m_delay) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:724:4 + assign i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:735:4 + assign csr_read = csr_ren_qual_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:736:4 + assign csr_write = dec_csr_wen_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:738:4 + assign i0_br_unpred = i0_dp[23] & ~i0_predict_br; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:742:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:743:7 + i0_itype = 4'b0000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:745:7 + if (i0_legal_decode_d) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:746:10 + if (i0_dp[9]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:746:42 + i0_itype = 4'b0001; + if (i0_dp[41]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:747:42 + i0_itype = 4'b0010; + if (i0_dp[40]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:748:42 + i0_itype = 4'b0011; + if (i0_dp[1]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:749:42 + i0_itype = 4'b0100; + if (((((((i0_dp[81] | i0_dp[76]) | i0_dp[73]) | i0_dp[69]) | i0_dp[63]) | i0_dp[56]) | i0_dp[54]) | i0_dp[50]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:754:42 + i0_itype = 4'b1111; + if (csr_read & ~csr_write) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:755:42 + i0_itype = 4'b0101; + if (~csr_read & csr_write) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:756:42 + i0_itype = 4'b0110; + if (csr_read & csr_write) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:757:42 + i0_itype = 4'b0111; + if (i0_dp[12]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:758:42 + i0_itype = 4'b1000; + if (i0_dp[11]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:759:42 + i0_itype = 4'b1001; + if (i0_dp[3]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:760:42 + i0_itype = 4'b1010; + if (i0_dp[2]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:761:42 + i0_itype = 4'b1011; + if (i0_dp[10]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:762:42 + i0_itype = 4'b1100; + if (i0_dp[28]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:763:42 + i0_itype = 4'b1101; + if (i0_dp[23]) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:764:42 + i0_itype = 4'b1110; + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:775:4 + el2_dec_dec_ctl i0_dec( + .inst(i0[31:0]), + .out(i0_dp_raw) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:780:4 + rvdff #(.WIDTH(1)) lsu_idle_ff( + .rst_l(rst_l), + .clk(active_clk), + .din(lsu_idle_any), + .dout(lsu_idle) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:784:4 + assign leak1_i1_stall_in = dec_tlu_flush_leak_one_r | (leak1_i1_stall & ~dec_tlu_flush_lower_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:787:4 + assign leak1_mode = leak1_i1_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:789:4 + assign leak1_i0_stall_in = (dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & ~dec_tlu_flush_lower_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:796:4 + assign i0_pcall_imm[20:1] = {i0[31], i0[19:12], i0[20], i0[30:21]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:798:4 + assign i0_pcall_12b_offset = (i0_pcall_imm[12] ? i0_pcall_imm[20:13] == 8'hff : i0_pcall_imm[20:13] == 8'h00); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:800:4 + assign i0_pcall_case = (i0_pcall_12b_offset & i0_dp_raw[43]) & ((i0r[4:0] == 5'd1) | (i0r[4:0] == 5'd5)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:801:4 + assign i0_pja_case = (i0_pcall_12b_offset & i0_dp_raw[43]) & ~((i0r[4:0] == 5'd1) | (i0r[4:0] == 5'd5)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:803:4 + assign i0_pcall_raw = i0_dp_raw[23] & i0_pcall_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:804:4 + assign i0_pcall = i0_dp[23] & i0_pcall_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:806:4 + assign i0_pja_raw = i0_dp_raw[23] & i0_pja_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:807:4 + assign i0_pja = i0_dp[23] & i0_pja_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:810:4 + assign i0_br_offset[11:0] = (i0_pcall_raw | i0_pja_raw ? i0_pcall_imm[12:1] : {i0[31], i0[7], i0[30:25], i0[11:8]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:812:4 + assign i0_pret_case = ((i0_dp_raw[23] & i0_dp_raw[46]) & (i0r[4:0] == 5'b00000)) & ((i0r[14:10] == 5'd1) | (i0r[14:10] == 5'd5)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:814:4 + assign i0_pret_raw = i0_dp_raw[23] & i0_pret_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:815:4 + assign i0_pret = i0_dp[23] & i0_pret_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:817:4 + assign i0_jal = ((i0_dp[23] & ~i0_pcall_case) & ~i0_pja_case) & ~i0_pret_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:821:4 + assign dec_lsu_offset_d[11:0] = ({12 {(~dec_extint_stall & i0_dp[39]) & i0_dp[41]}} & i0[31:20]) | ({12 {(~dec_extint_stall & i0_dp[39]) & i0_dp[40]}} & {i0[31:25], i0[11:7]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:826:4 + assign div_p[2] = div_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:828:4 + assign div_p[1] = i0_dp[29]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:829:4 + assign div_p[0] = i0_dp[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:832:4 + assign mul_p[22] = mul_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:834:4 + assign mul_p[21] = i0_dp[8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:835:4 + assign mul_p[20] = i0_dp[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:836:4 + assign mul_p[19] = i0_dp[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:837:4 + assign mul_p[18] = i0_dp[75]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:838:4 + assign mul_p[17] = i0_dp[74]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:839:4 + assign mul_p[16] = i0_dp[72]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:840:4 + assign mul_p[15] = i0_dp[71]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:841:4 + assign mul_p[14] = i0_dp[70]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:842:4 + assign mul_p[13] = i0_dp[83]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:843:4 + assign mul_p[12] = i0_dp[82]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:844:4 + assign mul_p[11] = i0_dp[68]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:845:4 + assign mul_p[10] = i0_dp[67]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:846:4 + assign mul_p[2] = i0_dp[66]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:847:4 + assign mul_p[1] = i0_dp[65]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:848:4 + assign mul_p[0] = i0_dp[64]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:849:4 + assign mul_p[9] = i0_dp[62]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:850:4 + assign mul_p[8] = i0_dp[61]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:851:4 + assign mul_p[7] = i0_dp[60]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:852:4 + assign mul_p[6] = i0_dp[59]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:853:4 + assign mul_p[5] = i0_dp[58]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:854:4 + assign mul_p[4] = i0_dp[57]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:855:4 + assign mul_p[3] = i0_dp[55]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:858:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:859:7 + lsu_p = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:861:7 + if (dec_extint_stall) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:862:10 + lsu_p[7] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:863:10 + lsu_p[9] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:864:10 + lsu_p[13] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:865:10 + lsu_p[0] = 1'b1; + end + else begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:868:10 + lsu_p[0] = lsu_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:870:10 + lsu_p[7] = i0_dp[41]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:871:10 + lsu_p[6] = i0_dp[40]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:872:10 + lsu_p[11] = i0_dp[22]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:873:10 + lsu_p[10] = i0_dp[21]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:874:10 + lsu_p[9] = i0_dp[20]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:875:10 + lsu_p[12] = i0r[14:10] == 5'd2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:877:10 + lsu_p[2] = load_ldst_bypass_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:878:10 + lsu_p[3] = store_data_bypass_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:879:10 + lsu_p[1] = store_data_bypass_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:881:10 + lsu_p[5] = i0_dp[29]; + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:886:4 + assign dec_lsu_valid_raw_d = (((i0_valid_d & (i0_dp_raw[41] | i0_dp_raw[40])) & ~dma_dccm_stall_any) & ~i0_block_raw_d) | dec_extint_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:890:4 + assign i0r[14:10] = i0[19:15]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:891:4 + assign i0r[9:5] = i0[24:20]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:892:4 + assign i0r[4:0] = i0[11:7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:895:4 + assign dec_i0_rs1_en_d = i0_dp[48] & (i0r[14:10] != 5'd0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:896:4 + assign dec_i0_rs2_en_d = i0_dp[47] & (i0r[9:5] != 5'd0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:897:4 + assign i0_rd_en_d = i0_dp[45] & (i0r[4:0] != 5'd0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:899:4 + assign dec_i0_rs1_d[4:0] = i0r[14:10]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:900:4 + assign dec_i0_rs2_d[4:0] = i0r[9:5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:903:4 + assign i0_jalimm20 = i0_dp[23] & i0_dp[43]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:904:4 + assign i0_uiimm20 = ~i0_dp[23] & i0_dp[43]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:909:4 + assign dec_csr_ren_d = i0_dp[19] & i0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:910:4 + assign csr_ren_qual_d = i0_dp[19] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:912:4 + assign csr_clr_d = i0_dp[18] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:913:4 + assign csr_set_d = i0_dp[17] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:914:4 + assign csr_write_d = i0_csr_write & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:916:4 + assign i0_csr_write_only_d = i0_csr_write & ~i0_dp[19]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:918:4 + assign dec_csr_wen_unq_d = ((i0_dp[18] | i0_dp[17]) | i0_csr_write) & i0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:920:4 + assign dec_csr_any_unq_d = any_csr_d & i0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:923:4 + assign dec_csr_rdaddr_d[11:0] = {12 {dec_csr_any_unq_d}} & i0[31:20]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:924:4 + assign dec_csr_wraddr_r[11:0] = {12 {r_d[22] & r_d[0]}} & r_d[20:9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:929:4 + assign dec_csr_wen_r = (r_d[22] & r_d[0]) & ~dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:932:4 + assign dec_csr_stall_int_ff = ((((r_d[20:9] == 12'h300) | (r_d[20:9] == 12'h304)) & r_d[22]) & r_d[0]) & ~dec_tlu_i0_kill_writeb_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:935:4 + rvdff #(.WIDTH(5)) csrmiscff( + .rst_l(rst_l), + .clk(active_clk), + .din({csr_ren_qual_d, csr_clr_d, csr_set_d, csr_write_d, i0_dp[15]}), + .dout({csr_read_x, csr_clr_x, csr_set_x, csr_write_x, csr_imm_x}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:946:4 + rvdffe #(.WIDTH(37)) csr_rddata_x_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_x_data_en & any_csr_d), + .din({i0[19:15], dec_csr_rddata_d[31:0]}), + .dout({csrimm_x[4:0], csr_rddata_x[31:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:949:4 + assign csr_mask_x[31:0] = ({32 {csr_imm_x}} & {27'b000000000000000000000000000, csrimm_x[4:0]}) | ({32 {~csr_imm_x}} & exu_csr_rs1_x[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:953:4 + assign write_csr_data_x[31:0] = (({32 {csr_clr_x}} & (csr_rddata_x[31:0] & ~csr_mask_x[31:0])) | ({32 {csr_set_x}} & (csr_rddata_x[31:0] | csr_mask_x[31:0]))) | ({32 {csr_write_x}} & csr_mask_x[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:963:4 + assign clear_pause = (dec_tlu_flush_lower_r & ~dec_tlu_flush_pause_r) | (pause_state & (write_csr_data[31:1] == 31'b0000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:966:4 + assign pause_state_in = (dec_tlu_wr_pause_r | pause_state) & ~clear_pause; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:970:4 + assign dec_pause_state = pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:974:7 + assign dec_pause_state_cg = (pause_state & ~tlu_wr_pause_r1) & ~tlu_wr_pause_r2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:979:4 + assign csr_data_wen = ((((csr_clr_x | csr_set_x) | csr_write_x) & csr_read_x) | dec_tlu_wr_pause_r) | pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:981:4 + assign write_csr_data_in[31:0] = (pause_state ? write_csr_data[31:0] - 32'b00000000000000000000000000000001 : (dec_tlu_wr_pause_r ? dec_csr_wrdata_r[31:0] : write_csr_data_x[31:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:985:4 + rvdffe #(.WIDTH(32)) write_csr_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(csr_data_wen), + .din(write_csr_data_in[31:0]), + .dout(write_csr_data[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:987:4 + assign pause_stall = pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:990:4 + assign dec_csr_wrdata_r[31:0] = (r_d[21] & r_d[0] ? i0_result_corr_r[31:0] : write_csr_data[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:994:4 + assign dec_i0_immed_d[31:0] = i0_immed_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:996:4 + assign i0_immed_d[31:0] = (((({32 {i0_dp[46]}} & {{20 {i0[31]}}, i0[31:20]}) | ({32 {i0_dp[44]}} & {27'b000000000000000000000000000, i0[24:20]})) | ({32 {i0_jalimm20}} & {{12 {i0[31]}}, i0[19:12], i0[20], i0[30:21], 1'b0})) | ({32 {i0_uiimm20}} & {i0[31:12], 12'b000000000000})) | ({32 {i0_csr_write_only_d & i0_dp[15]}} & {27'b000000000000000000000000000, i0[19:15]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1005:4 + assign dec_i0_br_immed_d[12:1] = (i0_ap[2] & ~i0_dp[23] ? i0_br_offset[11:0] : {10'b0000000000, i0_ap_pc4, i0_ap_pc2}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1008:4 + assign last_br_immed_d[12:1] = (i0_ap[2] ? {10'b0000000000, i0_ap_pc4, i0_ap_pc2} : i0_br_offset[11:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1010:4 + assign i0_valid_d = dec_ib0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1014:4 + assign i0_load_stall_d = i0_dp[41] & (lsu_load_stall_any | dma_dccm_stall_any); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1016:4 + assign i0_store_stall_d = i0_dp[40] & (lsu_store_stall_any | dma_dccm_stall_any); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1021:4 + assign i0_presync = (((i0_dp[14] | dec_tlu_presync_d) | debug_fence_i) | debug_fence_raw) | dec_tlu_pipelining_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1024:4 + assign i0_postsync = ((i0_dp[13] | dec_tlu_postsync_d) | debug_fence_i) | (i0_csr_write_only_d & (i0[31:20] == 12'h7c2)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1029:4 + assign debug_fence_i = dec_debug_fence_d & dbg_cmd_wrdata[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1030:4 + assign debug_fence_raw = dec_debug_fence_d & dbg_cmd_wrdata[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1032:4 + assign debug_fence = debug_fence_raw | debug_fence_i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1034:4 + assign i0_csr_write = i0_dp[16] & ~dec_debug_fence_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1040:4 + assign presync_stall = i0_presync & prior_inflight_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1042:4 + assign prior_inflight_eff = (i0_dp[5] ? prior_inflight_x : prior_inflight); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1044:4 + assign i0_div_prior_div_stall = i0_dp[5] & div_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1047:4 + assign i0_block_raw_d = (((((((((((i0_dp[19] & prior_csr_write) | dec_extint_stall) | pause_stall) | leak1_i0_stall) | dec_tlu_debug_stall) | postsync_stall) | presync_stall) | ((i0_dp[3] | debug_fence) & ~lsu_idle)) | i0_nonblock_load_stall) | i0_load_block_d) | i0_nonblock_div_stall) | i0_div_prior_div_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1060:4 + assign i0_block_d = (i0_block_raw_d | i0_store_stall_d) | i0_load_stall_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1061:4 + assign i0_exublock_d = i0_block_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1065:4 + assign prior_csr_write = (x_d[21] | r_d[21]) | wbd[21]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1071:4 + generate + if (pt[2207-:5] == 1) begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1072:6 + assign bitmanip_zbb_legal = 1'b1; + end + else begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1074:6 + assign bitmanip_zbb_legal = ~(i0_dp[81] & ~i0_dp[63]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1076:4 + generate + if (pt[2177-:5] == 1) begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1077:6 + assign bitmanip_zbs_legal = 1'b1; + end + else begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1079:6 + assign bitmanip_zbs_legal = ~i0_dp[76]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1081:4 + generate + if (pt[2197-:5] == 1) begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1082:6 + assign bitmanip_zbe_legal = 1'b1; + end + else begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1084:6 + assign bitmanip_zbe_legal = ~((i0_dp[73] & ~i0_dp[63]) & ~i0_dp[54]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1086:4 + generate + if (pt[2202-:5] == 1) begin : genblk6 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1087:6 + assign bitmanip_zbc_legal = 1'b1; + end + else begin : genblk6 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1089:6 + assign bitmanip_zbc_legal = ~i0_dp[69]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1091:4 + generate + if (pt[2187-:5] == 1) begin : genblk7 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1092:6 + assign bitmanip_zbp_legal = 1'b1; + end + else begin : genblk7 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1094:6 + assign bitmanip_zbp_legal = ~(((i0_dp[63] & ~i0_dp[81]) & ~i0_dp[73]) & ~i0_dp[54]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1096:4 + generate + if (pt[2182-:5] == 1) begin : genblk8 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1097:6 + assign bitmanip_zbr_legal = 1'b1; + end + else begin : genblk8 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1099:6 + assign bitmanip_zbr_legal = ~i0_dp[56]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1101:4 + generate + if (pt[2192-:5] == 1) begin : genblk9 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1102:6 + assign bitmanip_zbf_legal = 1'b1; + end + else begin : genblk9 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1104:6 + assign bitmanip_zbf_legal = ~((i0_dp[54] & ~i0_dp[63]) & ~i0_dp[73]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1106:4 + generate + if (pt[2212-:5] == 1) begin : genblk10 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1107:6 + assign bitmanip_zba_legal = 1'b1; + end + else begin : genblk10 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1109:6 + assign bitmanip_zba_legal = ~i0_dp[50]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1111:4 + generate + if ((pt[2207-:5] == 1) | (pt[2187-:5] == 1)) begin : genblk11 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1112:6 + assign bitmanip_zbb_zbp_legal = 1'b1; + end + else begin : genblk11 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1114:6 + assign bitmanip_zbb_zbp_legal = ~((i0_dp[81] & i0_dp[63]) & ~i0_dp[54]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1116:4 + generate + if (((pt[2187-:5] == 1) | (pt[2197-:5] == 1)) | (pt[2192-:5] == 1)) begin : genblk12 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1117:6 + assign bitmanip_zbp_zbe_zbf_legal = 1'b1; + end + else begin : genblk12 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1119:6 + assign bitmanip_zbp_zbe_zbf_legal = ~(((i0_dp[63] & i0_dp[73]) & i0_dp[54]) & ~i0_dp[81]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1121:4 + generate + if ((((pt[2207-:5] == 1) | (pt[2187-:5] == 1)) | (pt[2197-:5] == 1)) | (pt[2192-:5] == 1)) begin : genblk13 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1122:6 + assign bitmanip_zbb_zbp_zbe_zbf_legal = 1'b1; + end + else begin : genblk13 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1124:6 + assign bitmanip_zbb_zbp_zbe_zbf_legal = ~(((i0_dp[63] & i0_dp[73]) & i0_dp[54]) & i0_dp[81]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1127:4 + assign any_csr_d = i0_dp[19] | i0_csr_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1128:4 + assign bitmanip_legal = (((((((((bitmanip_zbb_legal & bitmanip_zbs_legal) & bitmanip_zbe_legal) & bitmanip_zbc_legal) & bitmanip_zbp_legal) & bitmanip_zbr_legal) & bitmanip_zbf_legal) & bitmanip_zba_legal) & bitmanip_zbb_zbp_legal) & bitmanip_zbp_zbe_zbf_legal) & bitmanip_zbb_zbp_zbe_zbf_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1130:4 + assign i0_legal = (i0_dp[0] & (~any_csr_d | dec_csr_legal_d)) & bitmanip_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1137:4 + assign shift_illegal = dec_i0_decode_d & ~i0_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1139:4 + assign illegal_inst_en = shift_illegal & ~illegal_lockout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1141:4 + rvdffe #(.WIDTH(32)) illegal_any_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(illegal_inst_en), + .din(i0_inst_d[31:0]), + .dout(dec_illegal_inst[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1143:4 + assign illegal_lockout_in = (shift_illegal | illegal_lockout) & ~flush_final_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1148:4 + assign dec_i0_decode_d = ((i0_valid_d & ~i0_block_d) & ~dec_tlu_flush_lower_r) & ~flush_final_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1149:4 + assign i0_exudecode_d = ((i0_valid_d & ~i0_exublock_d) & ~dec_tlu_flush_lower_r) & ~flush_final_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1152:4 + assign i0_legal_decode_d = dec_i0_decode_d & i0_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1153:4 + assign i0_exulegal_decode_d = i0_exudecode_d & i0_legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1157:4 + assign dec_pmu_instr_decoded = dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1159:4 + assign dec_pmu_decode_stall = i0_valid_d & ~dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1161:4 + assign dec_pmu_postsync_stall = postsync_stall & i0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1162:4 + assign dec_pmu_presync_stall = presync_stall & i0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1167:4 + assign ps_stall_in = (dec_i0_decode_d & (i0_postsync | ~i0_legal)) | (ps_stall & prior_inflight_x); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1172:4 + assign postsync_stall = ps_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1175:4 + assign prior_inflight_x = x_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1176:4 + assign prior_inflight_wb = r_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1178:4 + assign prior_inflight = prior_inflight_x | prior_inflight_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1180:4 + assign dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp[49]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1181:4 + assign dec_i0_branch_d = (i0_dp[28] | i0_dp[23]) | i0_br_error_all; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1183:4 + assign lsu_decode_d = i0_legal_decode_d & i0_dp[39]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1184:4 + assign mul_decode_d = i0_exulegal_decode_d & i0_dp[9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1185:4 + assign div_decode_d = i0_exulegal_decode_d & i0_dp[5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1187:4 + assign dec_qual_lsu_d = i0_dp[39]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1195:4 + assign i0_rs1_depend_i0_x = (dec_i0_rs1_en_d & x_d[1]) & (x_d[8:4] == i0r[14:10]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1196:4 + assign i0_rs1_depend_i0_r = (dec_i0_rs1_en_d & r_d[1]) & (r_d[8:4] == i0r[14:10]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1198:4 + assign i0_rs2_depend_i0_x = (dec_i0_rs2_en_d & x_d[1]) & (x_d[8:4] == i0r[9:5]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1199:4 + assign i0_rs2_depend_i0_r = (dec_i0_rs2_en_d & r_d[1]) & (r_d[8:4] == i0r[9:5]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1204:4 + assign {i0_rs1_class_d, i0_rs1_depth_d[1:0]} = (i0_rs1_depend_i0_x ? {i0_x_c, 2'd1} : (i0_rs1_depend_i0_r ? {i0_r_c, 2'd2} : {5 {1'sb0}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1207:4 + assign {i0_rs2_class_d, i0_rs2_depth_d[1:0]} = (i0_rs2_depend_i0_x ? {i0_x_c, 2'd1} : (i0_rs2_depend_i0_r ? {i0_r_c, 2'd2} : {5 {1'sb0}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1213:4 + generate + if (pt[202-:5] == 1) begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1214:7 + assign i0_load_block_d = (i0_rs1_class_d[1] & i0_rs1_depth_d[0]) | ((i0_rs2_class_d[1] & i0_rs2_depth_d[0]) & ~i0_dp[40]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1217:7 + assign load_ldst_bypass_d = ((i0_dp[41] | i0_dp[40]) & i0_rs1_depth_d[1]) & i0_rs1_class_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1219:7 + assign store_data_bypass_d = (i0_dp[40] & i0_rs2_depth_d[1]) & i0_rs2_class_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1221:7 + assign store_data_bypass_m = (i0_dp[40] & i0_rs2_depth_d[0]) & i0_rs2_class_d[1]; + end + else begin : genblock + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1225:7 + assign i0_load_block_d = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1227:7 + assign load_ldst_bypass_d = ((i0_dp[41] | i0_dp[40]) & i0_rs1_depth_d[0]) & i0_rs1_class_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1229:7 + assign store_data_bypass_d = (i0_dp[40] & i0_rs2_depth_d[0]) & i0_rs2_class_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1231:7 + assign store_data_bypass_m = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1239:4 + assign dec_tlu_i0_valid_r = r_d[0] & ~dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1242:4 + assign d_t[5] = i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1243:4 + assign d_t[16] = i0_icaf_d & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1244:4 + assign d_t[15] = dec_i0_icaf_second_d & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1245:4 + assign d_t[14:13] = dec_i0_icaf_type_d[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1247:4 + assign d_t[12] = (i0_dp[2] | debug_fence_i) & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1250:4 + assign d_t[3-:4] = i0_itype; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1251:4 + assign d_t[7] = i0_br_unpred; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1252:4 + assign d_t[6] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1253:4 + assign d_t[4] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1255:4 + assign d_t[11:8] = dec_i0_trigger_match_d[3:0] & {4 {dec_i0_decode_d}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1259:4 + rvdfflie #( + .WIDTH(17), + .LEFT(9) + ) trap_xff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_x_ctl_en), + .din(d_t), + .dout(x_t) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1261:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1262:7 + x_t_in = x_t; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1263:7 + x_t_in[11:8] = x_t[11-:4] & ~{4 {dec_tlu_flush_lower_wb}}; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1267:4 + rvdfflie #( + .WIDTH(17), + .LEFT(9) + ) trap_r_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_x_ctl_en), + .din(x_t_in), + .dout(r_t) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1270:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1272:7 + r_t_in = r_t; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1274:7 + r_t_in[11:8] = ({4 {r_d[3] | r_d[2]}} & lsu_trigger_match_r[3:0]) | r_t[11:8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1275:7 + r_t_in[4] = lsu_pmu_misaligned_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1277:7 + if (dec_tlu_flush_lower_wb) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1277:35 + r_t_in = 1'sb0; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1282:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1284:7 + dec_tlu_packet_r = r_t_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1285:7 + dec_tlu_packet_r[6] = r_d[23] & r_d[0]; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1293:4 + assign i0_d_c[2] = i0_dp[9] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1294:4 + assign i0_d_c[1] = i0_dp[41] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1295:4 + assign i0_d_c[0] = i0_dp[49] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1297:4 + rvdffs #(.WIDTH(3)) i0_x_c_ff( + .rst_l(rst_l), + .en(i0_x_ctl_en), + .clk(active_clk), + .din(i0_d_c), + .dout(i0_x_c) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1298:4 + rvdffs #(.WIDTH(3)) i0_r_c_ff( + .rst_l(rst_l), + .en(i0_r_ctl_en), + .clk(active_clk), + .din(i0_x_c), + .dout(i0_r_c) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1301:4 + assign d_d[8:4] = i0r[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1302:4 + assign d_d[1] = i0_rd_en_d & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1303:4 + assign d_d[0] = dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1305:4 + assign d_d[3] = i0_dp[41] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1306:4 + assign d_d[2] = i0_dp[40] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1307:4 + assign d_d[23] = i0_dp[5] & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1310:4 + assign d_d[22] = dec_csr_wen_unq_d & i0_legal_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1311:4 + assign d_d[21] = i0_csr_write_only_d & dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1312:4 + assign d_d[20:9] = (d_d[22] ? i0[31:20] : {12 {1'sb0}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1315:4 + rvdff #(.WIDTH(3)) i0cgff( + .rst_l(rst_l), + .clk(active_clk), + .din(i0_pipe_en[3:1]), + .dout(i0_pipe_en[2:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1317:4 + assign i0_pipe_en[3] = dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1319:4 + assign i0_x_ctl_en = |i0_pipe_en[3:2] | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1320:4 + assign i0_r_ctl_en = |i0_pipe_en[2:1] | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1321:4 + assign i0_wb_ctl_en = |i0_pipe_en[1:0] | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1322:4 + assign i0_x_data_en = i0_pipe_en[3] | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1323:4 + assign i0_r_data_en = i0_pipe_en[2] | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1324:4 + assign i0_wb_data_en = i0_pipe_en[1] | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1326:4 + assign dec_data_en[1:0] = {i0_x_data_en, i0_r_data_en}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1327:4 + assign dec_ctl_en[1:0] = {i0_x_ctl_en, i0_r_ctl_en}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1331:4 + rvdfflie #( + .WIDTH(24), + .LEFT(15) + ) e1ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_x_ctl_en), + .din(d_d), + .dout(x_d) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1333:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1334:7 + x_d_in = x_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1336:7 + x_d_in[1] = (x_d[1] & ~dec_tlu_flush_lower_wb) & ~dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1337:7 + x_d_in[0] = (x_d[0] & ~dec_tlu_flush_lower_wb) & ~dec_tlu_flush_lower_r; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1340:4 + rvdfflie #( + .WIDTH(24), + .LEFT(15) + ) r_d_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_r_ctl_en), + .din(x_d_in), + .dout(r_d) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1343:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1345:9 + r_d_in = r_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1349:7 + r_d_in[8:4] = r_d[8:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1351:7 + r_d_in[1] = r_d[1] & ~dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1352:7 + r_d_in[0] = r_d[0] & ~dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1354:7 + r_d_in[3] = r_d[3] & ~dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1355:7 + r_d_in[2] = r_d[2] & ~dec_tlu_flush_lower_wb; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1360:4 + rvdfflie #( + .WIDTH(24), + .LEFT(15) + ) wbff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_wb_ctl_en), + .din(r_d_in), + .dout(wbd) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1362:4 + assign dec_i0_waddr_r[4:0] = r_d_in[8:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1364:4 + assign i0_wen_r = r_d_in[1] & ~dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1365:4 + assign dec_i0_wen_r = (i0_wen_r & ~r_d_in[23]) & ~i0_load_kill_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1366:4 + assign dec_i0_wdata_r[31:0] = i0_result_corr_r[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1370:4 + assign div_e1_to_r = (x_d[23] & x_d[0]) | (r_d[23] & r_d[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1373:4 + assign div_active_in = i0_div_decode_d | ((div_active & ~exu_div_wren) & ~nonblock_div_cancel); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1376:4 + assign dec_div_active = div_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1380:4 + assign i0_nonblock_div_stall = ((dec_i0_rs1_en_d & div_active) & (div_waddr_wb[4:0] == i0r[14:10])) | ((dec_i0_rs2_en_d & div_active) & (div_waddr_wb[4:0] == i0r[9:5])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1384:4 + assign div_flush = (((x_d[23] & x_d[0]) & (x_d[8:4] == 5'b00000)) | ((x_d[23] & x_d[0]) & dec_tlu_flush_lower_r)) | (((r_d[23] & r_d[0]) & dec_tlu_flush_lower_r) & dec_tlu_i0_kill_writeb_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1390:4 + assign nonblock_div_cancel = (div_active & div_flush) | (((div_active & ~div_e1_to_r) & (r_d[8:4] == div_waddr_wb[4:0])) & i0_wen_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1393:4 + assign dec_div_cancel = nonblock_div_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1397:4 + assign i0_div_decode_d = i0_legal_decode_d & i0_dp[5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1401:4 + generate + if (pt[202-:5] == 1) begin : genblock1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1402:7 + assign i0_result_x[31:0] = exu_i0_result_x[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1403:7 + assign i0_result_r[31:0] = (r_d[1] & r_d[3] ? lsu_result_m[31:0] : i0_result_r_raw[31:0]); + end + else begin : genblock1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1406:7 + assign i0_result_x[31:0] = (x_d[1] & x_d[3] ? lsu_result_m[31:0] : exu_i0_result_x[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1407:7 + assign i0_result_r[31:0] = i0_result_r_raw[31:0]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1411:4 + rvdffe #(.WIDTH(32)) i0_result_r_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_r_data_en & ((x_d[1] | x_d[22]) | debug_valid_x)), + .din(i0_result_x[31:0]), + .dout(i0_result_r_raw[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1414:4 + assign i0_result_corr_r[31:0] = (r_d[1] & r_d[3] ? lsu_result_corr_r[31:0] : i0_result_r_raw[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1417:4 + rvdffe #(.WIDTH(12)) e1brpcff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_x_data_en), + .din(last_br_immed_d[12:1]), + .dout(last_br_immed_x[12:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1421:4 + assign i0_wb_en = i0_wb_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1423:4 + assign i0_inst_wb_in[31:0] = i0_inst_r[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1424:4 + assign i0_inst_d[31:0] = (dec_i0_pc4_d ? i0[31:0] : {16'b0000000000000000, ifu_i0_cinst[15:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1427:4 + assign trace_enable = ~dec_tlu_trace_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1430:4 + rvdffe #( + .WIDTH(5), + .OVERRIDE(1) + ) i0rdff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_div_decode_d), + .din(i0r[4:0]), + .dout(div_waddr_wb[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1432:4 + rvdffe #(.WIDTH(32)) i0xinstff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_x_data_en & trace_enable), + .din(i0_inst_d[31:0]), + .dout(i0_inst_x[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1433:4 + rvdffe #(.WIDTH(32)) i0cinstff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_r_data_en & trace_enable), + .din(i0_inst_x[31:0]), + .dout(i0_inst_r[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1435:4 + rvdffe #(.WIDTH(32)) i0wbinstff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_wb_en & trace_enable), + .din(i0_inst_wb_in[31:0]), + .dout(i0_inst_wb[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1436:4 + rvdffe #(.WIDTH(31)) i0wbpcff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_wb_en & trace_enable), + .din(dec_tlu_i0_pc_r[31:1]), + .dout(i0_pc_wb[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1438:4 + assign dec_i0_inst_wb[31:0] = i0_inst_wb[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1439:4 + assign dec_i0_pc_wb[31:1] = i0_pc_wb[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1443:4 + rvdffpcie #(.WIDTH(31)) i0_pc_r_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(i0_r_data_en), + .din(exu_i0_pc_x[31:1]), + .dout(dec_i0_pc_r[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1445:4 + assign dec_tlu_i0_pc_r[31:1] = dec_i0_pc_r[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1448:4 + rvbradder ibradder_correct( + .pc(exu_i0_pc_x[31:1]), + .offset(last_br_immed_x[12:1]), + .dout(pred_correct_npc_x[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1457:4 + assign i0_rs1_nonblock_load_bypass_en_d = (dec_i0_rs1_en_d & dec_nonblock_load_wen) & (dec_nonblock_load_waddr[4:0] == i0r[14:10]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1459:4 + assign i0_rs2_nonblock_load_bypass_en_d = (dec_i0_rs2_en_d & dec_nonblock_load_wen) & (dec_nonblock_load_waddr[4:0] == i0r[9:5]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1465:4 + assign i0_rs1bypass[2] = i0_rs1_depth_d[0] & (i0_rs1_class_d[0] | i0_rs1_class_d[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1466:4 + assign i0_rs1bypass[1] = i0_rs1_depth_d[0] & i0_rs1_class_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1467:4 + assign i0_rs1bypass[0] = i0_rs1_depth_d[1] & ((i0_rs1_class_d[0] | i0_rs1_class_d[2]) | i0_rs1_class_d[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1469:4 + assign i0_rs2bypass[2] = i0_rs2_depth_d[0] & (i0_rs2_class_d[0] | i0_rs2_class_d[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1470:4 + assign i0_rs2bypass[1] = i0_rs2_depth_d[0] & i0_rs2_class_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1471:4 + assign i0_rs2bypass[0] = i0_rs2_depth_d[1] & ((i0_rs2_class_d[0] | i0_rs2_class_d[2]) | i0_rs2_class_d[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1474:4 + assign dec_i0_rs1_bypass_en_d[3] = ((i0_rs1_nonblock_load_bypass_en_d & ~i0_rs1bypass[0]) & ~i0_rs1bypass[1]) & ~i0_rs1bypass[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1475:4 + assign dec_i0_rs1_bypass_en_d[2] = i0_rs1bypass[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1476:4 + assign dec_i0_rs1_bypass_en_d[1] = i0_rs1bypass[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1477:4 + assign dec_i0_rs1_bypass_en_d[0] = i0_rs1bypass[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1479:4 + assign dec_i0_rs2_bypass_en_d[3] = ((i0_rs2_nonblock_load_bypass_en_d & ~i0_rs2bypass[0]) & ~i0_rs2bypass[1]) & ~i0_rs2bypass[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1480:4 + assign dec_i0_rs2_bypass_en_d[2] = i0_rs2bypass[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1481:4 + assign dec_i0_rs2_bypass_en_d[1] = i0_rs2bypass[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1482:4 + assign dec_i0_rs2_bypass_en_d[0] = i0_rs2bypass[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1485:4 + assign dec_i0_result_r[31:0] = i0_result_r[31:0]; + initial _sv2v_0 = 0; +endmodule +module el2_dec_dec_ctl ( + inst, + out +); + // removed import el2_pkg::*; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1512:4 + input wire [31:0] inst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1514:4 + // removed localparam type el2_pkg_el2_dec_pkt_t + output wire [95:0] out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1517:4 + wire [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1520:4 + assign i[31:0] = inst[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1522:1 + assign out[49] = (((((((((((((((((((((i[30] & i[24]) & i[23]) & !i[22]) & !i[21]) & !i[20]) & i[14]) & !i[5]) & i[4]) | (((i[30] & !i[27]) & !i[24]) & i[4])) | (((!i[30] & !i[25]) & i[13]) & i[12])) | (((!i[29] & !i[27]) & !i[5]) & i[4])) | (((i[27] & i[25]) & i[14]) & i[4])) | ((((!i[29] & !i[25]) & !i[13]) & !i[12]) & i[4])) | ((((i[29] & i[27]) & !i[14]) & i[12]) & i[4])) | (((!i[27] & i[14]) & !i[5]) & i[4])) | (((i[30] & !i[29]) & !i[13]) & i[4])) | (((!i[27] & !i[25]) & i[5]) & i[4])) | ((i[13] & !i[5]) & i[4])) | i[2]) | i[6]) | ((((((((!i[30] & i[29]) & !i[24]) & !i[23]) & i[22]) & i[21]) & i[20]) & !i[5]) & i[4])) | ((!i[12] & !i[5]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1530:1 + assign out[48] = (((((((((((((!i[13] & i[11]) & !i[2]) | ((!i[13] & i[10]) & !i[2])) | ((i[19] & i[13]) & !i[2])) | ((!i[13] & i[9]) & !i[2])) | ((i[18] & i[13]) & !i[2])) | ((!i[13] & i[8]) & !i[2])) | ((i[17] & i[13]) & !i[2])) | ((!i[13] & i[7]) & !i[2])) | ((i[16] & i[13]) & !i[2])) | ((i[15] & i[13]) & !i[2])) | (!i[4] & !i[2])) | (((!i[14] & !i[13]) & i[6]) & !i[3])) | (!i[6] & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1536:1 + assign out[47] = ((i[5] & !i[4]) & !i[2]) | ((!i[6] & i[5]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1538:1 + assign out[46] = ((((!i[4] & !i[3]) & i[2]) | (((i[13] & !i[5]) & i[4]) & !i[2])) | (((!i[13] & !i[12]) & i[6]) & i[4])) | (((!i[12] & !i[5]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1541:1 + assign out[45] = ((!i[5] & !i[2]) | (i[5] & i[2])) | i[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1543:1 + assign out[44] = ((((((!i[29] & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]) | (((((i[27] & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((i[14] & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1546:1 + assign out[43] = (i[5] & i[3]) | (i[4] & i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1548:1 + assign out[42] = ((!i[5] & !i[3]) & i[2]) | (i[5] & i[3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1550:1 + assign out[41] = (!i[5] & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1552:1 + assign out[40] = (!i[6] & i[5]) & !i[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1554:1 + assign out[39] = (!i[6] & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1556:1 + assign out[38] = (((((!i[14] & !i[13]) & !i[12]) & !i[5]) & i[4]) | ((!i[5] & !i[3]) & i[2])) | (((((((!i[30] & !i[25]) & !i[14]) & !i[13]) & !i[12]) & !i[6]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1559:1 + assign out[37] = (((((((((i[30] & !i[14]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]) | ((((((!i[29] & !i[25]) & !i[14]) & i[13]) & !i[6]) & i[4]) & !i[2])) | (((((i[27] & i[25]) & i[14]) & !i[6]) & i[5]) & !i[2])) | ((((!i[14] & i[13]) & !i[5]) & i[4]) & !i[2])) | ((i[6] & !i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1563:1 + assign out[36] = ((((((!i[27] & !i[25]) & i[14]) & i[13]) & i[12]) & !i[6]) & !i[2]) | ((((i[14] & i[13]) & i[12]) & !i[5]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1566:1 + assign out[35] = ((((!i[6] & i[3]) | (((((((!i[29] & !i[27]) & !i[25]) & i[14]) & i[13]) & !i[12]) & !i[6]) & !i[2])) | ((i[5] & i[4]) & i[2])) | (((!i[13] & !i[12]) & i[6]) & i[4])) | ((((i[14] & i[13]) & !i[12]) & !i[5]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1570:1 + assign out[34] = (((((((!i[29] & !i[27]) & !i[25]) & i[14]) & !i[13]) & !i[12]) & i[4]) & !i[2]) | (((((i[14] & !i[13]) & !i[12]) & !i[5]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1573:1 + assign out[33] = (((((((!i[29] & !i[27]) & !i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1575:1 + assign out[32] = ((((((i[30] & !i[29]) & !i[27]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1577:1 + assign out[31] = (((((((!i[30] & !i[27]) & !i[25]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1579:1 + assign out[30] = ((((((!i[29] & !i[25]) & !i[14]) & i[13]) & !i[6]) & i[4]) & !i[2]) | ((((!i[14] & i[13]) & !i[5]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1582:1 + assign out[29] = (((((((!i[14] & i[13]) & i[12]) & !i[5]) & !i[2]) | (((i[13] & i[6]) & !i[4]) & !i[2])) | ((i[14] & !i[5]) & !i[4])) | (((((!i[25] & !i[14]) & i[13]) & i[12]) & !i[6]) & !i[2])) | (((((i[25] & i[14]) & i[12]) & !i[6]) & i[5]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1586:1 + assign out[28] = (i[6] & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1588:1 + assign out[27] = (((!i[14] & !i[12]) & i[6]) & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1590:1 + assign out[26] = (((!i[14] & i[12]) & i[6]) & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1592:1 + assign out[25] = (((i[14] & i[12]) & i[5]) & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1594:1 + assign out[24] = (((i[14] & !i[12]) & i[5]) & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1596:1 + assign out[23] = i[6] & i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1598:1 + assign out[22] = (((!i[13] & !i[12]) & !i[6]) & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1600:1 + assign out[21] = ((i[12] & !i[6]) & !i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1602:1 + assign out[20] = (i[13] & !i[6]) & !i[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1604:1 + assign out[19] = ((((((i[13] & i[6]) & i[4]) | ((i[7] & i[6]) & i[4])) | ((i[8] & i[6]) & i[4])) | ((i[9] & i[6]) & i[4])) | ((i[10] & i[6]) & i[4])) | ((i[11] & i[6]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1607:1 + assign out[18] = (((((((i[15] & i[13]) & i[12]) & i[6]) & i[4]) | ((((i[16] & i[13]) & i[12]) & i[6]) & i[4])) | ((((i[17] & i[13]) & i[12]) & i[6]) & i[4])) | ((((i[18] & i[13]) & i[12]) & i[6]) & i[4])) | ((((i[19] & i[13]) & i[12]) & i[6]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1611:1 + assign out[17] = ((((((i[15] & !i[12]) & i[6]) & i[4]) | (((i[16] & !i[12]) & i[6]) & i[4])) | (((i[17] & !i[12]) & i[6]) & i[4])) | (((i[18] & !i[12]) & i[6]) & i[4])) | (((i[19] & !i[12]) & i[6]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1615:1 + assign out[16] = ((!i[13] & i[12]) & i[6]) & i[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1617:1 + assign out[15] = (((((((i[14] & !i[13]) & i[6]) & i[4]) | (((i[15] & i[14]) & i[6]) & i[4])) | (((i[16] & i[14]) & i[6]) & i[4])) | (((i[17] & i[14]) & i[6]) & i[4])) | (((i[18] & i[14]) & i[6]) & i[4])) | (((i[19] & i[14]) & i[6]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1621:1 + assign out[14] = ((((((((((!i[5] & i[3]) | (((!i[13] & i[7]) & i[6]) & i[4])) | (((!i[13] & i[8]) & i[6]) & i[4])) | (((!i[13] & i[9]) & i[6]) & i[4])) | (((!i[13] & i[10]) & i[6]) & i[4])) | (((!i[13] & i[11]) & i[6]) & i[4])) | (((i[15] & i[13]) & i[6]) & i[4])) | (((i[16] & i[13]) & i[6]) & i[4])) | (((i[17] & i[13]) & i[6]) & i[4])) | (((i[18] & i[13]) & i[6]) & i[4])) | (((i[19] & i[13]) & i[6]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1627:1 + assign out[13] = ((((((((((((i[12] & !i[5]) & i[3]) | ((((!i[22] & !i[13]) & !i[12]) & i[6]) & i[4])) | (((!i[13] & i[7]) & i[6]) & i[4])) | (((!i[13] & i[8]) & i[6]) & i[4])) | (((!i[13] & i[9]) & i[6]) & i[4])) | (((!i[13] & i[10]) & i[6]) & i[4])) | (((!i[13] & i[11]) & i[6]) & i[4])) | (((i[15] & i[13]) & i[6]) & i[4])) | (((i[16] & i[13]) & i[6]) & i[4])) | (((i[17] & i[13]) & i[6]) & i[4])) | (((i[18] & i[13]) & i[6]) & i[4])) | (((i[19] & i[13]) & i[6]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1633:1 + assign out[12] = ((((!i[22] & i[20]) & !i[13]) & !i[12]) & i[6]) & i[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1635:1 + assign out[11] = ((((!i[21] & !i[20]) & !i[13]) & !i[12]) & i[6]) & i[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1637:1 + assign out[10] = (((i[29] & !i[13]) & !i[12]) & i[6]) & i[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1639:1 + assign out[9] = ((((((((((((((((((i[29] & !i[27]) & i[24]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]) | ((((((i[30] & i[27]) & i[13]) & !i[6]) & i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & !i[23]) & !i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & !i[21]) & i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & i[24]) & i[21]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[29] & i[27]) & !i[24]) & !i[22]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((((!i[30] & i[29]) & i[23]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((((i[30] & i[29]) & i[27]) & i[22]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((i[27] & !i[25]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2])) | (((((i[25] & !i[14]) & !i[6]) & i[5]) & i[4]) & !i[2])) | (((((i[29] & i[27]) & i[14]) & !i[6]) & i[5]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1651:1 + assign out[8] = ((((((((!i[27] & i[25]) & !i[14]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]) | (((((((!i[27] & i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1654:1 + assign out[7] = ((((((!i[27] & i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1656:1 + assign out[6] = (((((i[25] & !i[14]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1658:1 + assign out[5] = ((((!i[27] & i[25]) & i[14]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1660:1 + assign out[4] = (((((!i[27] & i[25]) & i[14]) & i[13]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1662:1 + assign out[3] = !i[5] & i[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1664:1 + assign out[2] = (i[12] & !i[5]) & i[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1666:1 + assign out[95] = ((((((((((i[29] & !i[27]) & !i[24]) & !i[22]) & !i[21]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1669:1 + assign out[94] = (((((((((i[29] & !i[27]) & !i[24]) & !i[22]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1672:1 + assign out[93] = ((((((((i[29] & !i[27]) & !i[24]) & i[21]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1674:1 + assign out[92] = ((((((((i[29] & !i[27]) & i[22]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1676:1 + assign out[91] = ((((((((i[29] & !i[27]) & i[22]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1678:1 + assign out[90] = (((((i[27] & i[25]) & i[14]) & !i[13]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1680:1 + assign out[89] = (((((i[27] & i[25]) & i[14]) & i[13]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1682:1 + assign out[88] = (((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1684:1 + assign out[87] = (((((i[30] & i[27]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1686:1 + assign out[86] = ((((((!i[30] & i[27]) & !i[25]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1688:1 + assign out[85] = ((((((i[29] & !i[27]) & !i[14]) & i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1690:1 + assign out[84] = ((((((i[29] & !i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1692:1 + assign out[81] = (((((((((((((((((((!i[30] & !i[29]) & i[27]) & !i[24]) & !i[23]) & !i[22]) & !i[21]) & !i[20]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2]) | (((((((i[29] & !i[27]) & !i[24]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((((i[29] & !i[27]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((i[30] & !i[27]) & i[14]) & !i[12]) & !i[6]) & i[5]) & !i[2])) | ((((((i[30] & !i[27]) & i[13]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((i[29] & !i[27]) & i[12]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((((((((!i[30] & i[29]) & !i[24]) & !i[23]) & i[22]) & i[21]) & i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | ((((((((((((i[30] & i[29]) & i[24]) & i[23]) & !i[22]) & !i[21]) & !i[20]) & i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2])) | (((((i[27] & i[25]) & i[14]) & !i[6]) & i[5]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1701:1 + assign out[80] = ((((((!i[30] & i[29]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1703:1 + assign out[79] = ((((((i[30] & !i[29]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1705:1 + assign out[78] = (((((((i[30] & i[29]) & i[27]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1707:1 + assign out[77] = (((((((i[30] & !i[29]) & i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1709:1 + assign out[76] = (((((((i[29] & i[27]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]) | (((((((i[30] & !i[29]) & i[27]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1712:1 + assign out[75] = ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1714:1 + assign out[74] = ((((((i[30] & i[27]) & i[13]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1716:1 + assign out[73] = ((((((((i[30] & i[27]) & i[14]) & i[13]) & !i[12]) & !i[6]) & i[5]) & !i[2]) | (((((((!i[30] & i[27]) & !i[25]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2])) | ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1720:1 + assign out[72] = ((((((i[27] & i[25]) & !i[14]) & !i[13]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1722:1 + assign out[71] = (((((i[27] & !i[14]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1724:1 + assign out[70] = ((((((i[27] & i[25]) & !i[14]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1726:1 + assign out[69] = (((((i[27] & i[25]) & !i[14]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1728:1 + assign out[83] = (((((((i[30] & i[29]) & i[27]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1730:1 + assign out[82] = ((((((!i[30] & i[29]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1732:1 + assign out[68] = ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1734:1 + assign out[67] = ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1736:1 + assign out[66] = ((((((i[29] & i[27]) & !i[14]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1738:1 + assign out[65] = (((((i[29] & i[27]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1740:1 + assign out[64] = (((((i[29] & i[27]) & i[14]) & i[13]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1742:1 + assign out[63] = (((((((((((((i[30] & !i[27]) & !i[14]) & i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]) | (((((((!i[30] & i[27]) & !i[25]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2])) | ((((((i[30] & !i[27]) & i[13]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((i[27] & !i[25]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2])) | ((((((i[30] & i[14]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2])) | ((((((i[29] & i[27]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2])) | ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2])) | ((((((i[29] & i[14]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1749:1 + assign out[62] = ((((((((((i[29] & !i[27]) & i[24]) & !i[23]) & !i[21]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1752:1 + assign out[61] = (((((((((i[29] & !i[27]) & i[24]) & !i[23]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1755:1 + assign out[60] = (((((((((i[29] & !i[27]) & i[24]) & !i[23]) & i[21]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1758:1 + assign out[59] = (((((((((i[29] & !i[27]) & i[23]) & !i[21]) & !i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1761:1 + assign out[58] = ((((((((i[29] & !i[27]) & i[23]) & i[20]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1763:1 + assign out[57] = ((((((((i[29] & !i[27]) & i[23]) & i[21]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1765:1 + assign out[56] = (((((((i[29] & !i[27]) & i[24]) & !i[14]) & !i[13]) & i[12]) & !i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1767:1 + assign out[55] = (((((i[30] & i[27]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1769:1 + assign out[54] = ((((((((!i[30] & !i[29]) & i[27]) & !i[25]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2]) | ((((((i[27] & !i[25]) & i[13]) & i[12]) & !i[6]) & i[5]) & !i[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1772:1 + assign out[53] = ((((((i[29] & !i[27]) & !i[14]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1774:1 + assign out[52] = ((((((i[29] & !i[27]) & i[14]) & !i[13]) & !i[12]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1776:1 + assign out[51] = (((((i[29] & !i[27]) & i[14]) & i[13]) & !i[6]) & i[5]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1778:1 + assign out[50] = (((((i[29] & !i[27]) & !i[12]) & !i[6]) & i[5]) & i[4]) & !i[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1780:1 + assign out[1] = (((((((((i[28] & i[20]) & !i[13]) & !i[12]) & i[4]) | (((((!i[30] & !i[29]) & !i[27]) & !i[25]) & !i[6]) & i[4])) | ((((((!i[29] & !i[27]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4])) | (((((!i[29] & !i[27]) & !i[25]) & !i[14]) & !i[6]) & i[4])) | ((i[13] & !i[5]) & i[4])) | (i[4] & i[2])) | ((!i[12] & !i[5]) & i[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv:1786:1 + assign out[0] = (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((!i[31] & !i[30]) & i[29]) & i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[22]) & i[21]) & !i[20]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & i[6]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0]) | (((((((((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & i[22]) & !i[21]) & i[20]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & i[6]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[22]) & !i[21]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((((((((((!i[31] & i[30]) & i[29]) & !i[28]) & !i[26]) & !i[25]) & i[24]) & !i[22]) & !i[20]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((((!i[31] & i[30]) & i[29]) & !i[28]) & !i[26]) & !i[25]) & i[24]) & !i[22]) & !i[21]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((((!i[31] & i[30]) & i[29]) & !i[28]) & !i[26]) & !i[25]) & !i[23]) & !i[22]) & !i[20]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((((!i[31] & i[30]) & i[29]) & !i[28]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[21]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[26]) & i[25]) & i[13]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[28]) & i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & !i[30]) & i[29]) & !i[28]) & !i[26]) & !i[25]) & i[13]) & !i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[13]) & !i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & i[30]) & !i[28]) & !i[26]) & !i[25]) & i[14]) & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[26]) & !i[13]) & i[12]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((((!i[31] & i[30]) & i[29]) & !i[28]) & !i[26]) & !i[25]) & !i[13]) & i[12]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((((((((!i[31] & i[30]) & !i[28]) & i[27]) & !i[26]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[29]) & !i[28]) & !i[26]) & !i[25]) & i[14]) & !i[6]) & i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((((((!i[31] & i[29]) & !i[28]) & i[27]) & !i[26]) & !i[25]) & !i[13]) & i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[6]) & i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[26]) & i[14]) & !i[6]) & i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((((!i[14] & !i[13]) & !i[12]) & i[6]) & i[5]) & !i[4]) & !i[3]) & i[1]) & i[0])) | (((((((i[14] & i[6]) & i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((!i[14] & !i[13]) & i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((!i[12] & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((((!i[13] & i[12]) & i[6]) & i[5]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((((((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[27]) & !i[26]) & !i[25]) & !i[24]) & !i[23]) & !i[22]) & !i[21]) & !i[20]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[13]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[6]) & !i[5]) & !i[4]) & i[3]) & i[2]) & i[1]) & i[0])) | (((((((((((((((((((((((!i[31] & !i[30]) & !i[29]) & !i[28]) & !i[19]) & !i[18]) & !i[17]) & !i[16]) & !i[15]) & !i[14]) & !i[13]) & !i[12]) & !i[11]) & !i[10]) & !i[9]) & !i[8]) & !i[7]) & !i[6]) & !i[5]) & !i[4]) & i[3]) & i[2]) & i[1]) & i[0])) | (((((((i[13] & i[6]) & i[5]) & i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((((((!i[31] & !i[30]) & !i[28]) & !i[26]) & !i[25]) & i[14]) & !i[12]) & !i[6]) & i[4]) & !i[3]) & i[1]) & i[0])) | ((((((i[6] & i[5]) & !i[4]) & i[3]) & i[2]) & i[1]) & i[0])) | (((((((!i[14] & !i[12]) & !i[6]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | (((((((!i[13] & !i[6]) & !i[5]) & !i[4]) & !i[3]) & !i[2]) & i[1]) & i[0])) | ((((((i[13] & !i[6]) & !i[5]) & i[4]) & !i[3]) & i[1]) & i[0])) | (((((!i[6] & i[4]) & !i[3]) & i[2]) & i[1]) & i[0]); +endmodule +module el2_dec_gpr_ctl ( + raddr0, + raddr1, + wen0, + waddr0, + wd0, + wen1, + waddr1, + wd1, + wen2, + waddr2, + wd2, + clk, + rst_l, + rd0, + rd1, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:21:5 + input wire [4:0] raddr0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:22:5 + input wire [4:0] raddr1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:24:5 + input wire wen0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:25:5 + input wire [4:0] waddr0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:26:5 + input wire [31:0] wd0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:28:5 + input wire wen1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:29:5 + input wire [4:0] waddr1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:30:5 + input wire [31:0] wd1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:32:5 + input wire wen2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:33:5 + input wire [4:0] waddr2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:34:5 + input wire [31:0] wd2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:36:5 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:37:5 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:39:5 + output reg [31:0] rd0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:40:5 + output reg [31:0] rd1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:42:5 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:45:4 + wire [1023:32] gpr_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:46:4 + reg [1023:32] gpr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:47:4 + reg [31:1] w0v; + reg [31:1] w1v; + reg [31:1] w2v; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:48:4 + wire [31:1] gpr_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:51:4 + assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1]) | w2v[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:52:4 + genvar _gv_j_6; + generate + for (_gv_j_6 = 1; _gv_j_6 < 32; _gv_j_6 = _gv_j_6 + 1) begin : gpr + localparam j = _gv_j_6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:53:7 + rvdffe #(.WIDTH(32)) gprff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(gpr_wr_en[j]), + .din(gpr_in[(j * 32) + 31-:32]), + .dout(gpr_out[(j * 32) + 31-:32]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:57:4 + function automatic signed [4:0] sv2v_cast_5_signed; + input reg signed [4:0] inp; + sv2v_cast_5_signed = inp; + endfunction + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:58:7 + rd0[31:0] = 32'b00000000000000000000000000000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:59:7 + rd1[31:0] = 32'b00000000000000000000000000000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:60:7 + w0v[31:1] = 31'b0000000000000000000000000000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:61:7 + w1v[31:1] = 31'b0000000000000000000000000000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:62:7 + w2v[31:1] = 31'b0000000000000000000000000000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:63:7 + gpr_in[32+:992] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:66:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:66:12 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:66:12 + for (j = 1; j < 32; j = j + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:67:10 + rd0[31:0] = rd0[31:0] | ({32 {raddr0[4:0] == sv2v_cast_5_signed(j)}} & gpr_out[(j * 32) + 31-:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:68:10 + rd1[31:0] = rd1[31:0] | ({32 {raddr1[4:0] == sv2v_cast_5_signed(j)}} & gpr_out[(j * 32) + 31-:32]); + end + end + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:72:11 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:72:11 + for (j = 1; j < 32; j = j + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:73:10 + w0v[j] = wen0 & (waddr0[4:0] == sv2v_cast_5_signed(j)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:74:10 + w1v[j] = wen1 & (waddr1[4:0] == sv2v_cast_5_signed(j)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:75:10 + w2v[j] = wen2 & (waddr2[4:0] == sv2v_cast_5_signed(j)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv:76:10 + gpr_in[j * 32+:32] = (({32 {w0v[j]}} & wd0[31:0]) | ({32 {w1v[j]}} & wd1[31:0])) | ({32 {w2v[j]}} & wd2[31:0]); + end + end + end + initial _sv2v_0 = 0; +endmodule +module el2_dec_ib_ctl ( + dbg_cmd_valid, + dbg_cmd_write, + dbg_cmd_type, + dbg_cmd_addr, + i0_brp, + ifu_i0_bp_index, + ifu_i0_bp_fghr, + ifu_i0_bp_btag, + ifu_i0_fa_index, + ifu_i0_pc4, + ifu_i0_valid, + ifu_i0_icaf, + ifu_i0_icaf_type, + ifu_i0_icaf_second, + ifu_i0_dbecc, + ifu_i0_instr, + ifu_i0_pc, + dec_ib0_valid_d, + dec_debug_valid_d, + dec_i0_instr_d, + dec_i0_pc_d, + dec_i0_pc4_d, + dec_i0_brp, + dec_i0_bp_index, + dec_i0_bp_fghr, + dec_i0_bp_btag, + dec_i0_bp_fa_index, + dec_i0_icaf_d, + dec_i0_icaf_second_d, + dec_i0_icaf_type_d, + dec_i0_dbecc_d, + dec_debug_wdata_rs1_d, + dec_debug_fence_d +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:22:4 + input wire dbg_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:24:4 + input wire dbg_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:25:4 + input wire [1:0] dbg_cmd_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:26:4 + input wire [31:0] dbg_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:28:4 + // removed localparam type el2_pkg_el2_br_pkt_t + input wire [50:0] i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:29:4 + input wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:30:4 + input wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:31:4 + input wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:32:4 + input wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:34:4 + input wire ifu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:35:4 + input wire ifu_i0_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:36:4 + input wire ifu_i0_icaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:37:4 + input wire [1:0] ifu_i0_icaf_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:39:4 + input wire ifu_i0_icaf_second; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:40:4 + input wire ifu_i0_dbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:41:4 + input wire [31:0] ifu_i0_instr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:42:4 + input wire [31:1] ifu_i0_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:45:4 + output wire dec_ib0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:46:4 + output wire dec_debug_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:49:4 + output wire [31:0] dec_i0_instr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:51:4 + output wire [31:1] dec_i0_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:53:4 + output wire dec_i0_pc4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:55:4 + output wire [50:0] dec_i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:56:4 + output wire [pt[2172-:9]:pt[2163-:6]] dec_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:57:4 + output wire [pt[2236-:8] - 1:0] dec_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:58:4 + output wire [pt[2139-:9] - 1:0] dec_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:59:4 + output wire [$clog2(pt[2061-:14]) - 1:0] dec_i0_bp_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:61:4 + output wire dec_i0_icaf_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:62:4 + output wire dec_i0_icaf_second_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:63:4 + output wire [1:0] dec_i0_icaf_type_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:64:4 + output wire dec_i0_dbecc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:65:4 + output wire dec_debug_wdata_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:67:4 + output wire dec_debug_fence_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:72:4 + wire debug_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:73:4 + wire [4:0] dreg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:74:4 + wire [11:0] dcsr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:75:4 + wire [31:0] ib0; + wire [31:0] ib0_debug_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:77:4 + wire debug_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:78:4 + wire debug_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:79:4 + wire debug_read_gpr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:80:4 + wire debug_write_gpr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:81:4 + wire debug_read_csr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:82:4 + wire debug_write_csr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:84:4 + wire [34:0] ifu_i0_pcdata; + wire [34:0] pc0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:86:4 + assign ifu_i0_pcdata[34:0] = {ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf, ifu_i0_pc[31:1], ifu_i0_pc4}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:89:4 + assign pc0[34:0] = ifu_i0_pcdata[34:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:91:4 + assign dec_i0_icaf_second_d = pc0[34]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:93:4 + assign dec_i0_dbecc_d = pc0[33]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:95:4 + assign dec_i0_icaf_d = pc0[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:96:4 + assign dec_i0_pc_d[31:1] = pc0[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:97:4 + assign dec_i0_pc4_d = pc0[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:99:4 + assign dec_i0_icaf_type_d[1:0] = ifu_i0_icaf_type[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:119:4 + assign debug_valid = dbg_cmd_valid & (dbg_cmd_type[1:0] != 2'h2); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:122:4 + assign debug_read = debug_valid & ~dbg_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:123:4 + assign debug_write = debug_valid & dbg_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:125:4 + assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0] == 2'h0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:126:4 + assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0] == 2'h0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:127:4 + assign debug_read_csr = debug_read & (dbg_cmd_type[1:0] == 2'h1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:128:4 + assign debug_write_csr = debug_write & (dbg_cmd_type[1:0] == 2'h1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:130:4 + assign dreg[4:0] = dbg_cmd_addr[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:131:4 + assign dcsr[11:0] = dbg_cmd_addr[11:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:134:4 + assign ib0_debug_in[31:0] = ((({32 {debug_read_gpr}} & {12'b000000000000, dreg[4:0], 15'b110000000110011}) | ({32 {debug_write_gpr}} & {20'b00000000000000000110, dreg[4:0], 7'b0110011})) | ({32 {debug_read_csr}} & {dcsr[11:0], 20'b00000010000001110011})) | ({32 {debug_write_csr}} & {dcsr[11:0], 20'b00000001000001110011}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:143:4 + assign dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:148:4 + assign dec_debug_fence_d = debug_write_csr & (dcsr[11:0] == 12'h7c4); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:150:4 + assign ib0[31:0] = (debug_valid ? ib0_debug_in[31:0] : ifu_i0_instr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:152:4 + assign dec_ib0_valid_d = ifu_i0_valid | debug_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:154:4 + assign dec_debug_valid_d = debug_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:156:4 + assign dec_i0_instr_d[31:0] = ib0[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:158:4 + assign dec_i0_brp = i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:159:4 + assign dec_i0_bp_index = ifu_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:160:4 + assign dec_i0_bp_fghr = ifu_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:161:4 + assign dec_i0_bp_btag = ifu_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv:162:4 + assign dec_i0_bp_fa_index = ifu_i0_fa_index; +endmodule +module el2_dec_tlu_ctl ( + clk, + free_clk, + free_l2clk, + rst_l, + scan_mode, + rst_vec, + nmi_int, + nmi_vec, + i_cpu_halt_req, + i_cpu_run_req, + lsu_fastint_stall_any, + ifu_pmu_instr_aligned, + ifu_pmu_fetch_stall, + ifu_pmu_ic_miss, + ifu_pmu_ic_hit, + ifu_pmu_bus_error, + ifu_pmu_bus_busy, + ifu_pmu_bus_trxn, + dec_pmu_instr_decoded, + dec_pmu_decode_stall, + dec_pmu_presync_stall, + dec_pmu_postsync_stall, + lsu_store_stall_any, + dma_dccm_stall_any, + dma_iccm_stall_any, + exu_pmu_i0_br_misp, + exu_pmu_i0_br_ataken, + exu_pmu_i0_pc4, + lsu_pmu_bus_trxn, + lsu_pmu_bus_misaligned, + lsu_pmu_bus_error, + lsu_pmu_bus_busy, + lsu_pmu_load_external_m, + lsu_pmu_store_external_m, + dma_pmu_dccm_read, + dma_pmu_dccm_write, + dma_pmu_any_read, + dma_pmu_any_write, + lsu_fir_addr, + lsu_fir_error, + iccm_dma_sb_error, + lsu_error_pkt_r, + lsu_single_ecc_error_incr, + dec_pause_state, + lsu_imprecise_error_store_any, + lsu_imprecise_error_load_any, + lsu_imprecise_error_addr_any, + dec_csr_wen_unq_d, + dec_csr_any_unq_d, + dec_csr_rdaddr_d, + dec_csr_wen_r, + dec_csr_wraddr_r, + dec_csr_wrdata_r, + dec_csr_stall_int_ff, + dec_tlu_i0_valid_r, + exu_npc_r, + dec_tlu_i0_pc_r, + dec_tlu_packet_r, + dec_illegal_inst, + dec_i0_decode_d, + exu_i0_br_hist_r, + exu_i0_br_error_r, + exu_i0_br_start_error_r, + exu_i0_br_valid_r, + exu_i0_br_mp_r, + exu_i0_br_middle_r, + exu_i0_br_way_r, + dec_tlu_core_empty, + dec_dbg_cmd_done, + dec_dbg_cmd_fail, + dec_tlu_dbg_halted, + dec_tlu_debug_mode, + dec_tlu_resume_ack, + dec_tlu_debug_stall, + dec_tlu_flush_noredir_r, + dec_tlu_mpc_halted_only, + dec_tlu_flush_leak_one_r, + dec_tlu_flush_err_r, + dec_tlu_flush_extint, + dec_tlu_meihap, + dbg_halt_req, + dbg_resume_req, + ifu_miss_state_idle, + lsu_idle_any, + dec_div_active, + trigger_pkt_any, + ifu_ic_error_start, + ifu_iccm_rd_ecc_single_err, + ifu_ic_debug_rd_data, + ifu_ic_debug_rd_data_valid, + dec_tlu_ic_diag_pkt, + pic_claimid, + pic_pl, + mhwakeup, + mexintpend, + timer_int, + soft_int, + o_cpu_halt_status, + o_cpu_halt_ack, + o_cpu_run_ack, + o_debug_mode_status, + core_id, + mpc_debug_halt_req, + mpc_debug_run_req, + mpc_reset_run_req, + mpc_debug_halt_ack, + mpc_debug_run_ack, + debug_brkpt_status, + dec_tlu_meicurpl, + dec_tlu_meipt, + dec_csr_rddata_d, + dec_csr_legal_d, + dec_tlu_br0_r_pkt, + dec_tlu_i0_kill_writeb_wb, + dec_tlu_flush_lower_wb, + dec_tlu_i0_commit_cmt, + dec_tlu_i0_kill_writeb_r, + dec_tlu_flush_lower_r, + dec_tlu_flush_path_r, + dec_tlu_fence_i_r, + dec_tlu_wr_pause_r, + dec_tlu_flush_pause_r, + dec_tlu_presync_d, + dec_tlu_postsync_d, + dec_tlu_mrac_ff, + dec_tlu_force_halt, + dec_tlu_perfcnt0, + dec_tlu_perfcnt1, + dec_tlu_perfcnt2, + dec_tlu_perfcnt3, + dec_tlu_i0_exc_valid_wb1, + dec_tlu_i0_valid_wb1, + dec_tlu_int_valid_wb1, + dec_tlu_exc_cause_wb1, + dec_tlu_mtval_wb1, + dec_tlu_external_ldfwd_disable, + dec_tlu_sideeffect_posted_disable, + dec_tlu_core_ecc_disable, + dec_tlu_bpred_disable, + dec_tlu_wb_coalescing_disable, + dec_tlu_pipelining_disable, + dec_tlu_trace_disable, + dec_tlu_dma_qos_prty, + dec_tlu_misc_clk_override, + dec_tlu_dec_clk_override, + dec_tlu_ifu_clk_override, + dec_tlu_lsu_clk_override, + dec_tlu_bus_clk_override, + dec_tlu_pic_clk_override, + dec_tlu_picio_clk_override, + dec_tlu_dccm_clk_override, + dec_tlu_icm_clk_override +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:32:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:33:4 + input wire free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:34:4 + input wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:35:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:36:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:38:4 + input wire [31:1] rst_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:39:4 + input wire nmi_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:40:4 + input wire [31:1] nmi_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:41:4 + input wire i_cpu_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:42:4 + input wire i_cpu_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:44:4 + input wire lsu_fastint_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:48:4 + input wire ifu_pmu_instr_aligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:49:4 + input wire ifu_pmu_fetch_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:50:4 + input wire ifu_pmu_ic_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:51:4 + input wire ifu_pmu_ic_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:52:4 + input wire ifu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:53:4 + input wire ifu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:54:4 + input wire ifu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:55:4 + input wire dec_pmu_instr_decoded; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:56:4 + input wire dec_pmu_decode_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:57:4 + input wire dec_pmu_presync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:58:4 + input wire dec_pmu_postsync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:59:4 + input wire lsu_store_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:60:4 + input wire dma_dccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:61:4 + input wire dma_iccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:62:4 + input wire exu_pmu_i0_br_misp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:63:4 + input wire exu_pmu_i0_br_ataken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:64:4 + input wire exu_pmu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:65:4 + input wire lsu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:66:4 + input wire lsu_pmu_bus_misaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:67:4 + input wire lsu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:68:4 + input wire lsu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:69:4 + input wire lsu_pmu_load_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:70:4 + input wire lsu_pmu_store_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:71:4 + input wire dma_pmu_dccm_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:72:4 + input wire dma_pmu_dccm_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:73:4 + input wire dma_pmu_any_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:74:4 + input wire dma_pmu_any_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:76:4 + input wire [31:1] lsu_fir_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:77:4 + input wire [1:0] lsu_fir_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:79:4 + input wire iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:81:4 + // removed localparam type el2_pkg_el2_lsu_error_pkt_t + input wire [39:0] lsu_error_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:82:4 + input wire lsu_single_ecc_error_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:84:4 + input wire dec_pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:85:4 + input wire lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:86:4 + input wire lsu_imprecise_error_load_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:87:4 + input wire [31:0] lsu_imprecise_error_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:89:4 + input wire dec_csr_wen_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:90:4 + input wire dec_csr_any_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:91:4 + input wire [11:0] dec_csr_rdaddr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:93:4 + input wire dec_csr_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:94:4 + input wire [11:0] dec_csr_wraddr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:95:4 + input wire [31:0] dec_csr_wrdata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:97:4 + input wire dec_csr_stall_int_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:99:4 + input wire dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:101:4 + input wire [31:1] exu_npc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:103:4 + input wire [31:1] dec_tlu_i0_pc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:105:4 + // removed localparam type el2_pkg_el2_inst_pkt_t + // removed localparam type el2_pkg_el2_trap_pkt_t + input wire [16:0] dec_tlu_packet_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:107:4 + input wire [31:0] dec_illegal_inst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:108:4 + input wire dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:111:4 + input wire [1:0] exu_i0_br_hist_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:112:4 + input wire exu_i0_br_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:113:4 + input wire exu_i0_br_start_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:114:4 + input wire exu_i0_br_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:115:4 + input wire exu_i0_br_mp_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:116:4 + input wire exu_i0_br_middle_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:120:4 + input wire exu_i0_br_way_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:122:4 + output wire dec_tlu_core_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:124:4 + output wire dec_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:125:4 + output wire dec_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:126:4 + output wire dec_tlu_dbg_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:127:4 + output wire dec_tlu_debug_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:128:4 + output wire dec_tlu_resume_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:129:4 + output wire dec_tlu_debug_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:131:4 + output wire dec_tlu_flush_noredir_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:132:4 + output wire dec_tlu_mpc_halted_only; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:133:4 + output wire dec_tlu_flush_leak_one_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:134:4 + output wire dec_tlu_flush_err_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:136:4 + output wire dec_tlu_flush_extint; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:137:4 + output wire [31:2] dec_tlu_meihap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:139:4 + input wire dbg_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:140:4 + input wire dbg_resume_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:141:4 + input wire ifu_miss_state_idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:142:4 + input wire lsu_idle_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:143:4 + input wire dec_div_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:144:4 + // removed localparam type el2_pkg_el2_trigger_pkt_t + output wire [151:0] trigger_pkt_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:146:4 + input wire ifu_ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:147:4 + input wire ifu_iccm_rd_ecc_single_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:150:4 + input wire [70:0] ifu_ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:151:4 + input wire ifu_ic_debug_rd_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:152:4 + // removed localparam type el2_pkg_el2_cache_debug_pkt_t + output wire [89:0] dec_tlu_ic_diag_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:155:4 + input wire [7:0] pic_claimid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:156:4 + input wire [3:0] pic_pl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:157:4 + input wire mhwakeup; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:159:4 + input wire mexintpend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:160:4 + input wire timer_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:161:4 + input wire soft_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:163:4 + output wire o_cpu_halt_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:164:4 + output wire o_cpu_halt_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:165:4 + output wire o_cpu_run_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:166:4 + output wire o_debug_mode_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:168:4 + input wire [31:4] core_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:171:4 + input wire mpc_debug_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:172:4 + input wire mpc_debug_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:173:4 + input wire mpc_reset_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:174:4 + output wire mpc_debug_halt_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:175:4 + output wire mpc_debug_run_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:176:4 + output wire debug_brkpt_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:178:4 + output wire [3:0] dec_tlu_meicurpl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:179:4 + output wire [3:0] dec_tlu_meipt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:182:4 + output wire [31:0] dec_csr_rddata_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:183:4 + output wire dec_csr_legal_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:185:4 + // removed localparam type el2_pkg_el2_br_tlu_pkt_t + output wire [6:0] dec_tlu_br0_r_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:187:4 + output wire dec_tlu_i0_kill_writeb_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:188:4 + output wire dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:189:4 + output wire dec_tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:191:4 + output wire dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:192:4 + output wire dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:193:4 + output wire [31:1] dec_tlu_flush_path_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:194:4 + output wire dec_tlu_fence_i_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:195:4 + output wire dec_tlu_wr_pause_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:196:4 + output wire dec_tlu_flush_pause_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:198:4 + output wire dec_tlu_presync_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:199:4 + output wire dec_tlu_postsync_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:202:4 + output wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:204:4 + output wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:206:4 + output wire dec_tlu_perfcnt0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:207:4 + output wire dec_tlu_perfcnt1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:208:4 + output wire dec_tlu_perfcnt2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:209:4 + output wire dec_tlu_perfcnt3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:211:4 + output wire dec_tlu_i0_exc_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:212:4 + output wire dec_tlu_i0_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:213:4 + output wire dec_tlu_int_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:214:4 + output wire [4:0] dec_tlu_exc_cause_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:215:4 + output wire [31:0] dec_tlu_mtval_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:218:4 + output wire dec_tlu_external_ldfwd_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:219:4 + output wire dec_tlu_sideeffect_posted_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:220:4 + output wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:221:4 + output wire dec_tlu_bpred_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:222:4 + output wire dec_tlu_wb_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:223:4 + output wire dec_tlu_pipelining_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:224:4 + output wire dec_tlu_trace_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:225:4 + output wire [2:0] dec_tlu_dma_qos_prty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:228:4 + output wire dec_tlu_misc_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:229:4 + output wire dec_tlu_dec_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:230:4 + output wire dec_tlu_ifu_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:231:4 + output wire dec_tlu_lsu_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:232:4 + output wire dec_tlu_bus_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:233:4 + output wire dec_tlu_pic_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:234:4 + output wire dec_tlu_picio_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:235:4 + output wire dec_tlu_dccm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:236:4 + output wire dec_tlu_icm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:240:4 + wire clk_override; + wire e4e5_int_clk; + wire nmi_fir_type; + wire nmi_lsu_load_type; + wire nmi_lsu_store_type; + wire nmi_int_detected_f; + wire nmi_lsu_load_type_f; + wire nmi_lsu_store_type_f; + wire allow_dbg_halt_csr_write; + wire dbg_cmd_done_ns; + wire i_cpu_run_req_d1_raw; + wire debug_mode_status; + wire lsu_single_ecc_error_r_d1; + wire sel_npc_r; + wire sel_npc_resume; + wire ce_int; + wire nmi_in_debug_mode; + wire dpc_capture_npc; + wire dpc_capture_pc; + wire tdata_load; + wire tdata_opcode; + wire tdata_action; + wire perfcnt_halted; + wire tdata_chain; + wire tdata_kill_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:247:4 + wire reset_delayed; + wire reset_detect; + wire reset_detected; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:248:4 + wire wr_mstatus_r; + wire wr_mtvec_r; + wire wr_mcyclel_r; + wire wr_mcycleh_r; + wire wr_minstretl_r; + wire wr_minstreth_r; + wire wr_mscratch_r; + wire wr_mepc_r; + wire wr_mcause_r; + wire wr_mscause_r; + wire wr_mtval_r; + wire wr_mrac_r; + wire wr_meihap_r; + wire wr_meicurpl_r; + wire wr_meipt_r; + wire wr_dcsr_r; + wire wr_dpc_r; + wire wr_meicidpl_r; + wire wr_meivt_r; + wire wr_meicpct_r; + wire wr_micect_r; + wire wr_miccmect_r; + wire wr_mfdht_r; + wire wr_mfdhs_r; + wire wr_mdccmect_r; + wire wr_mhpme3_r; + wire wr_mhpme4_r; + wire wr_mhpme5_r; + wire wr_mhpme6_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:253:4 + wire wr_mpmc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:254:4 + wire [1:1] mpmc_b_ns; + wire [1:1] mpmc; + wire [1:1] mpmc_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:255:4 + wire set_mie_pmu_fw_halt; + wire fw_halted_ns; + wire fw_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:256:4 + wire wr_mcountinhibit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:257:4 + wire [6:0] mcountinhibit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:258:4 + wire wr_mtsel_r; + wire wr_mtdata1_t0_r; + wire wr_mtdata1_t1_r; + wire wr_mtdata1_t2_r; + wire wr_mtdata1_t3_r; + wire wr_mtdata2_t0_r; + wire wr_mtdata2_t1_r; + wire wr_mtdata2_t2_r; + wire wr_mtdata2_t3_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:259:4 + wire [31:0] mtdata2_t0; + wire [31:0] mtdata2_t1; + wire [31:0] mtdata2_t2; + wire [31:0] mtdata2_t3; + wire [31:0] mtdata2_tsel_out; + wire [31:0] mtdata1_tsel_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:260:4 + wire [9:0] mtdata1_t0_ns; + wire [9:0] mtdata1_t0; + wire [9:0] mtdata1_t1_ns; + wire [9:0] mtdata1_t1; + wire [9:0] mtdata1_t2_ns; + wire [9:0] mtdata1_t2; + wire [9:0] mtdata1_t3_ns; + wire [9:0] mtdata1_t3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:261:4 + wire [9:0] tdata_wrdata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:262:4 + wire [1:0] mtsel_ns; + wire [1:0] mtsel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:263:4 + wire tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:264:4 + wire [1:0] mstatus_ns; + wire [1:0] mstatus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:265:4 + wire [1:0] mfdhs_ns; + wire [1:0] mfdhs; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:266:4 + wire [31:0] force_halt_ctr; + wire [31:0] force_halt_ctr_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:267:4 + wire force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:268:4 + wire [5:0] mfdht; + wire [5:0] mfdht_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:269:4 + wire mstatus_mie_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:270:4 + wire [30:0] mtvec_ns; + wire [30:0] mtvec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:271:4 + wire [15:2] dcsr_ns; + wire [15:2] dcsr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:272:4 + wire [5:0] mip_ns; + wire [5:0] mip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:273:4 + wire [5:0] mie_ns; + wire [5:0] mie; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:274:4 + wire [31:0] mcyclel_ns; + wire [31:0] mcyclel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:275:4 + wire [31:0] mcycleh_ns; + wire [31:0] mcycleh; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:276:4 + wire [31:0] minstretl_ns; + wire [31:0] minstretl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:277:4 + wire [31:0] minstreth_ns; + wire [31:0] minstreth; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:278:4 + wire [31:0] micect_ns; + wire [31:0] micect; + wire [31:0] miccmect_ns; + wire [31:0] miccmect; + wire [31:0] mdccmect_ns; + wire [31:0] mdccmect; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:279:4 + wire [26:0] micect_inc; + wire [26:0] miccmect_inc; + wire [26:0] mdccmect_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:280:4 + wire [31:0] mscratch; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:281:4 + wire [31:0] mhpmc3; + wire [31:0] mhpmc3_ns; + wire [31:0] mhpmc4; + wire [31:0] mhpmc4_ns; + wire [31:0] mhpmc5; + wire [31:0] mhpmc5_ns; + wire [31:0] mhpmc6; + wire [31:0] mhpmc6_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:282:4 + wire [31:0] mhpmc3h; + wire [31:0] mhpmc3h_ns; + wire [31:0] mhpmc4h; + wire [31:0] mhpmc4h_ns; + wire [31:0] mhpmc5h; + wire [31:0] mhpmc5h_ns; + wire [31:0] mhpmc6h; + wire [31:0] mhpmc6h_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:283:4 + wire [9:0] mhpme3; + wire [9:0] mhpme4; + wire [9:0] mhpme5; + wire [9:0] mhpme6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:284:4 + wire [31:0] mrac; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:285:4 + wire [9:2] meihap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:286:4 + wire [31:10] meivt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:287:4 + wire [3:0] meicurpl_ns; + wire [3:0] meicurpl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:288:4 + wire [3:0] meicidpl_ns; + wire [3:0] meicidpl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:289:4 + wire [3:0] meipt_ns; + wire [3:0] meipt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:290:4 + wire [31:0] mdseac; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:291:4 + wire mdseac_locked_ns; + wire mdseac_locked_f; + wire mdseac_en; + wire nmi_lsu_detected; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:292:4 + wire [31:1] mepc_ns; + wire [31:1] mepc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:293:4 + wire [31:1] dpc_ns; + wire [31:1] dpc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:294:4 + wire [31:0] mcause_ns; + wire [31:0] mcause; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:295:4 + wire [3:0] mscause_ns; + wire [3:0] mscause; + wire [3:0] mscause_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:296:4 + wire [31:0] mtval_ns; + wire [31:0] mtval; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:297:4 + wire dec_pause_state_f; + wire dec_tlu_wr_pause_r_d1; + wire pause_expired_r; + wire pause_expired_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:298:4 + wire tlu_flush_lower_r; + wire tlu_flush_lower_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:299:4 + wire [31:1] tlu_flush_path_r; + wire [31:1] tlu_flush_path_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:300:4 + wire i0_valid_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:301:4 + wire tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:302:4 + wire [31:1] vectored_path; + wire [31:1] interrupt_path; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:303:4 + wire [16:0] dicawics_ns; + wire [16:0] dicawics; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:304:4 + wire wr_dicawics_r; + wire wr_dicad0_r; + wire wr_dicad1_r; + wire wr_dicad0h_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:305:4 + wire [31:0] dicad0_ns; + wire [31:0] dicad0; + wire [31:0] dicad0h_ns; + wire [31:0] dicad0h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:307:4 + wire [6:0] dicad1_ns; + wire [6:0] dicad1_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:308:4 + wire [31:0] dicad1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:309:4 + wire ebreak_r; + wire ebreak_to_debug_mode_r; + wire ecall_r; + wire illegal_r; + wire mret_r; + wire inst_acc_r; + wire fence_i_r; + wire ic_perr_r; + wire iccm_sbecc_r; + wire ebreak_to_debug_mode_r_d1; + wire kill_ebreak_count_r; + wire inst_acc_second_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:311:4 + wire ce_int_ready; + wire ext_int_ready; + wire timer_int_ready; + wire soft_int_ready; + wire int_timer0_int_ready; + wire int_timer1_int_ready; + wire mhwakeup_ready; + wire take_ext_int; + wire take_ce_int; + wire take_timer_int; + wire take_soft_int; + wire take_int_timer0_int; + wire take_int_timer1_int; + wire take_nmi; + wire take_nmi_r_d1; + wire int_timer0_int_possible; + wire int_timer1_int_possible; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:313:4 + wire i0_exception_valid_r; + wire interrupt_valid_r; + wire i0_exception_valid_r_d1; + wire interrupt_valid_r_d1; + wire exc_or_int_valid_r; + wire exc_or_int_valid_r_d1; + wire mdccme_ce_req; + wire miccme_ce_req; + wire mice_ce_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:314:4 + wire synchronous_flush_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:315:4 + wire [4:0] exc_cause_r; + wire [4:0] exc_cause_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:316:4 + wire mcyclel_cout; + wire mcyclel_cout_f; + wire mcyclela_cout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:317:4 + wire [31:0] mcyclel_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:318:4 + wire [31:0] mcycleh_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:320:4 + wire minstretl_cout; + wire minstretl_cout_f; + wire minstret_enable; + wire minstretl_cout_ns; + wire minstretl_couta; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:322:4 + wire [31:0] minstretl_inc; + wire [31:0] minstretl_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:323:4 + wire [31:0] minstreth_inc; + wire [31:0] minstreth_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:324:4 + wire [31:1] pc_r; + wire [31:1] pc_r_d1; + wire [31:1] npc_r; + wire [31:1] npc_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:325:4 + wire valid_csr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:326:4 + wire rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:327:4 + wire lsu_i0_rfnpc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:328:4 + wire dec_tlu_br0_error_r; + wire dec_tlu_br0_start_error_r; + wire dec_tlu_br0_v_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:329:4 + wire lsu_i0_exc_r; + wire lsu_i0_exc_r_raw; + wire lsu_exc_ma_r; + wire lsu_exc_acc_r; + wire lsu_exc_st_r; + wire lsu_exc_valid_r; + wire lsu_exc_valid_r_raw; + wire lsu_exc_valid_r_d1; + wire lsu_i0_exc_r_d1; + wire block_interrupts; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:331:4 + wire i0_trigger_eval_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:333:4 + wire request_debug_mode_r; + wire request_debug_mode_r_d1; + wire request_debug_mode_done; + wire request_debug_mode_done_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:334:4 + wire take_halt; + wire halt_taken; + wire halt_taken_f; + wire internal_dbg_halt_mode; + wire dbg_tlu_halted_f; + wire take_reset; + wire dbg_tlu_halted; + wire core_empty; + wire lsu_idle_any_f; + wire ifu_miss_state_idle_f; + wire resume_ack_ns; + wire debug_halt_req_f; + wire debug_resume_req_f_raw; + wire debug_resume_req_f; + wire enter_debug_halt_req; + wire dcsr_single_step_done; + wire dcsr_single_step_done_f; + wire debug_halt_req_d1; + wire debug_halt_req_ns; + wire dcsr_single_step_running; + wire dcsr_single_step_running_f; + wire internal_dbg_halt_timers; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:339:4 + wire [3:0] i0_trigger_r; + wire [3:0] trigger_action; + wire [3:0] trigger_enabled; + wire [3:0] i0_trigger_chain_masked_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:341:4 + wire i0_trigger_hit_r; + wire i0_trigger_hit_raw_r; + wire i0_trigger_action_r; + wire trigger_hit_r_d1; + wire mepc_trigger_hit_sel_pc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:344:4 + wire [3:0] update_hit_bit_r; + wire [3:0] i0_iside_trigger_has_pri_r; + wire [3:0] i0trigger_qual_r; + wire [3:0] i0_lsu_trigger_has_pri_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:345:4 + wire cpu_halt_status; + wire cpu_halt_ack; + wire cpu_run_ack; + wire ext_halt_pulse; + wire i_cpu_halt_req_d1; + wire i_cpu_run_req_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:347:4 + wire inst_acc_r_raw; + wire trigger_hit_dmode_r; + wire trigger_hit_dmode_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:348:4 + wire [9:0] mcgc; + wire [9:0] mcgc_ns; + wire [9:0] mcgc_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:349:4 + wire [18:0] mfdc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:350:4 + wire i_cpu_halt_req_sync_qual; + wire i_cpu_run_req_sync_qual; + wire pmu_fw_halt_req_ns; + wire pmu_fw_halt_req_f; + wire int_timer_stalled; + wire fw_halt_req; + wire enter_pmu_fw_halt_req; + wire pmu_fw_tlu_halted; + wire pmu_fw_tlu_halted_f; + wire internal_pmu_fw_halt_mode; + wire internal_pmu_fw_halt_mode_f; + wire int_timer0_int_hold; + wire int_timer1_int_hold; + wire int_timer0_int_hold_f; + wire int_timer1_int_hold_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:353:4 + wire nmi_int_delayed; + wire nmi_int_detected; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:354:4 + wire [3:0] trigger_execute; + wire [3:0] trigger_data; + wire [3:0] trigger_store; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:355:4 + wire dec_tlu_pmu_fw_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:357:4 + wire mpc_run_state_ns; + wire debug_brkpt_status_ns; + wire mpc_debug_halt_ack_ns; + wire mpc_debug_run_ack_ns; + wire dbg_halt_state_ns; + wire dbg_run_state_ns; + wire dbg_halt_state_f; + wire mpc_debug_halt_req_sync_f; + wire mpc_debug_run_req_sync_f; + wire mpc_halt_state_f; + wire mpc_halt_state_ns; + wire mpc_run_state_f; + wire debug_brkpt_status_f; + wire mpc_debug_halt_ack_f; + wire mpc_debug_run_ack_f; + wire dbg_run_state_f; + wire mpc_debug_halt_req_sync_pulse; + wire mpc_debug_run_req_sync_pulse; + wire debug_brkpt_valid; + wire debug_halt_req; + wire debug_resume_req; + wire dec_tlu_mpc_halted_only_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:361:4 + wire take_ext_int_start; + wire ext_int_freeze; + wire take_ext_int_start_d1; + wire take_ext_int_start_d2; + wire take_ext_int_start_d3; + wire ext_int_freeze_d1; + wire csr_meicpct; + wire ignore_ext_int_due_to_lsu_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:363:4 + wire mcause_sel_nmi_store; + wire mcause_sel_nmi_load; + wire mcause_sel_nmi_ext; + wire fast_int_meicpct; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:364:4 + wire [1:0] mcause_fir_error_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:365:4 + wire dbg_halt_req_held_ns; + wire dbg_halt_req_held; + wire dbg_halt_req_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:366:4 + wire iccm_repair_state_ns; + wire iccm_repair_state_d1; + wire iccm_repair_state_rfnpc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:370:4 + wire [31:0] dec_timer_rddata_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:371:4 + wire dec_timer_read_d; + wire dec_timer_t0_pulse; + wire dec_timer_t1_pulse; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:372:4 + wire csr_mitctl0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:373:4 + wire csr_mitctl1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:374:4 + wire csr_mitb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:375:4 + wire csr_mitb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:376:4 + wire csr_mitcnt0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:377:4 + wire csr_mitcnt1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:379:4 + wire nmi_int_sync; + wire timer_int_sync; + wire soft_int_sync; + wire i_cpu_halt_req_sync; + wire i_cpu_run_req_sync; + wire mpc_debug_halt_req_sync; + wire mpc_debug_run_req_sync; + wire mpc_debug_halt_req_sync_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:380:4 + wire csr_wr_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:381:4 + wire e4e5_clk; + wire e4_valid; + wire e5_valid; + wire e4e5_valid; + wire internal_dbg_halt_mode_f; + wire internal_dbg_halt_mode_f2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:382:4 + wire lsu_pmu_load_external_r; + wire lsu_pmu_store_external_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:383:4 + wire dec_tlu_flush_noredir_r_d1; + wire dec_tlu_flush_pause_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:384:4 + wire lsu_single_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:385:4 + wire [31:0] lsu_error_pkt_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:386:4 + wire mcyclel_cout_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:387:4 + wire i0_valid_no_ebreak_ecall_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:388:4 + wire minstret_enable_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:389:4 + wire sel_exu_npc_r; + wire sel_flush_npc_r; + wire sel_hold_npc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:390:4 + wire pc0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:391:4 + wire [15:0] mfdc_int; + wire [15:0] mfdc_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:392:4 + wire [31:0] mrac_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:393:4 + wire [31:27] csr_sat; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:394:4 + wire [8:6] dcsr_cause; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:395:4 + wire enter_debug_halt_req_le; + wire dcsr_cause_upgradeable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:396:4 + wire icache_rd_valid; + wire icache_wr_valid; + wire icache_rd_valid_f; + wire icache_wr_valid_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:397:4 + wire [3:0] mhpmc_inc_r; + wire [3:0] mhpmc_inc_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:399:4 + wire [39:0] mhpme_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:400:4 + wire mhpmc3_wr_en0; + wire mhpmc3_wr_en1; + wire mhpmc3_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:401:4 + wire mhpmc4_wr_en0; + wire mhpmc4_wr_en1; + wire mhpmc4_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:402:4 + wire mhpmc5_wr_en0; + wire mhpmc5_wr_en1; + wire mhpmc5_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:403:4 + wire mhpmc6_wr_en0; + wire mhpmc6_wr_en1; + wire mhpmc6_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:404:4 + wire mhpmc3h_wr_en0; + wire mhpmc3h_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:405:4 + wire mhpmc4h_wr_en0; + wire mhpmc4h_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:406:4 + wire mhpmc5h_wr_en0; + wire mhpmc5h_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:407:4 + wire mhpmc6h_wr_en0; + wire mhpmc6h_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:408:4 + wire [63:0] mhpmc3_incr; + wire [63:0] mhpmc4_incr; + wire [63:0] mhpmc5_incr; + wire [63:0] mhpmc6_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:409:4 + wire perfcnt_halted_d1; + wire zero_event_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:410:4 + wire [3:0] perfcnt_during_sleep; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:411:4 + wire [9:0] event_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:413:4 + wire [3:0] pmu_i0_itype_qual; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:415:4 + wire csr_mfdht; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:416:4 + wire csr_mfdhs; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:417:4 + wire csr_misa; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:418:4 + wire csr_mvendorid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:419:4 + wire csr_marchid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:420:4 + wire csr_mimpid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:421:4 + wire csr_mhartid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:422:4 + wire csr_mstatus; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:423:4 + wire csr_mtvec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:424:4 + wire csr_mip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:425:4 + wire csr_mie; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:426:4 + wire csr_mcyclel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:427:4 + wire csr_mcycleh; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:428:4 + wire csr_minstretl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:429:4 + wire csr_minstreth; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:430:4 + wire csr_mscratch; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:431:4 + wire csr_mepc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:432:4 + wire csr_mcause; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:433:4 + wire csr_mscause; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:434:4 + wire csr_mtval; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:435:4 + wire csr_mrac; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:436:4 + wire csr_dmst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:437:4 + wire csr_mdseac; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:438:4 + wire csr_meihap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:439:4 + wire csr_meivt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:440:4 + wire csr_meipt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:441:4 + wire csr_meicurpl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:442:4 + wire csr_meicidpl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:443:4 + wire csr_dcsr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:444:4 + wire csr_mcgc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:445:4 + wire csr_mfdc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:446:4 + wire csr_dpc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:447:4 + wire csr_mtsel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:448:4 + wire csr_mtdata1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:449:4 + wire csr_mtdata2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:450:4 + wire csr_mhpmc3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:451:4 + wire csr_mhpmc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:452:4 + wire csr_mhpmc5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:453:4 + wire csr_mhpmc6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:454:4 + wire csr_mhpmc3h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:455:4 + wire csr_mhpmc4h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:456:4 + wire csr_mhpmc5h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:457:4 + wire csr_mhpmc6h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:458:4 + wire csr_mhpme3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:459:4 + wire csr_mhpme4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:460:4 + wire csr_mhpme5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:461:4 + wire csr_mhpme6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:462:4 + wire csr_mcountinhibit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:463:4 + wire csr_mpmc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:464:4 + wire csr_micect; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:465:4 + wire csr_miccmect; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:466:4 + wire csr_mdccmect; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:467:4 + wire csr_dicawics; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:468:4 + wire csr_dicad0h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:469:4 + wire csr_dicad0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:470:4 + wire csr_dicad1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:471:4 + wire csr_dicago; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:472:4 + wire presync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:473:4 + wire postsync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:474:4 + wire legal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:475:4 + wire dec_csr_wen_r_mod; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:477:4 + wire flush_clkvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:478:4 + wire sel_fir_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:479:4 + wire wr_mie_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:480:4 + wire mtval_capture_pc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:481:4 + wire mtval_capture_pc_plus2_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:482:4 + wire mtval_capture_inst_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:483:4 + wire mtval_capture_lsu_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:484:4 + wire mtval_clear_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:485:4 + wire wr_mcgc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:486:4 + wire wr_mfdc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:487:4 + wire wr_mdeau_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:488:4 + wire trigger_hit_for_dscr_cause_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:489:4 + wire conditionally_illegal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:491:4 + wire [3:0] ifu_mscause; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:492:4 + wire ifu_ic_error_start_f; + wire ifu_iccm_rd_ecc_single_err_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:494:4 + el2_dec_timer_ctl #(.pt(pt)) int_timers( + .clk(clk), + .free_l2clk(free_l2clk), + .csr_wr_clk(csr_wr_clk), + .rst_l(rst_l), + .dec_csr_wen_r_mod(dec_csr_wen_r_mod), + .dec_csr_wraddr_r(dec_csr_wraddr_r), + .dec_csr_wrdata_r(dec_csr_wrdata_r), + .csr_mitctl0(csr_mitctl0), + .csr_mitctl1(csr_mitctl1), + .csr_mitb0(csr_mitb0), + .csr_mitb1(csr_mitb1), + .csr_mitcnt0(csr_mitcnt0), + .csr_mitcnt1(csr_mitcnt1), + .dec_pause_state(dec_pause_state), + .dec_tlu_pmu_fw_halted(dec_tlu_pmu_fw_halted), + .internal_dbg_halt_timers(internal_dbg_halt_timers), + .dec_timer_rddata_d(dec_timer_rddata_d), + .dec_timer_read_d(dec_timer_read_d), + .dec_timer_t0_pulse(dec_timer_t0_pulse), + .dec_timer_t1_pulse(dec_timer_t1_pulse), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:497:4 + assign clk_override = dec_tlu_dec_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:500:4 + rvsyncss #(.WIDTH(7)) syncro_ff( + .rst_l(rst_l), + .clk(free_clk), + .din({nmi_int, timer_int, soft_int, i_cpu_halt_req, i_cpu_run_req, mpc_debug_halt_req, mpc_debug_run_req}), + .dout({nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync_raw, mpc_debug_run_req_sync}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:507:4 + rvoclkhdr csrwr_r_cgc( + .en(dec_csr_wen_r_mod | clk_override), + .l1clk(csr_wr_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:509:4 + assign e4_valid = dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:510:4 + assign e4e5_valid = e4_valid | e5_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:511:4 + assign flush_clkvalid = ((((((((internal_dbg_halt_mode_f | i_cpu_run_req_d1) | interrupt_valid_r) | interrupt_valid_r_d1) | reset_delayed) | pause_expired_r) | pause_expired_wb) | ic_perr_r) | iccm_sbecc_r) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:514:4 + rvoclkhdr e4e5_cgc( + .en(e4e5_valid | clk_override), + .l1clk(e4e5_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:515:4 + rvoclkhdr e4e5_int_cgc( + .en(e4e5_valid | flush_clkvalid), + .l1clk(e4e5_int_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:517:4 + rvdffie #(.WIDTH(11)) freeff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({ifu_ic_error_start, ifu_iccm_rd_ecc_single_err, iccm_repair_state_ns, e4_valid, internal_dbg_halt_mode, lsu_pmu_load_external_m, lsu_pmu_store_external_m, tlu_flush_lower_r, tlu_i0_kill_writeb_r, internal_dbg_halt_mode_f, force_halt}), + .dout({ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f, iccm_repair_state_d1, e5_valid, internal_dbg_halt_mode_f, lsu_pmu_load_external_r, lsu_pmu_store_external_r, tlu_flush_lower_r_d1, dec_tlu_i0_kill_writeb_wb, internal_dbg_halt_mode_f2, dec_tlu_force_halt}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:525:4 + assign dec_tlu_i0_kill_writeb_r = tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:527:4 + assign nmi_int_detected = (((nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected) | (nmi_int_detected_f & ~take_nmi_r_d1)) | nmi_fir_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:529:4 + assign nmi_lsu_load_type = ((nmi_lsu_detected & lsu_imprecise_error_load_any) & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_load_type_f & ~take_nmi_r_d1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:531:4 + assign nmi_lsu_store_type = ((nmi_lsu_detected & lsu_imprecise_error_store_any) & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_store_type_f & ~take_nmi_r_d1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:534:4 + assign nmi_fir_type = (~nmi_int_detected_f & take_ext_int_start_d3) & |lsu_fir_error[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:537:4 + assign nmi_lsu_detected = (~mdseac_locked_f & (lsu_imprecise_error_load_any | lsu_imprecise_error_store_any)) & ~nmi_fir_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:540:1 + localparam MSTATUS_MIE = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:541:1 + localparam MIP_MCEIP = 5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:542:1 + localparam MIP_MITIP0 = 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:543:1 + localparam MIP_MITIP1 = 3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:544:1 + localparam MIP_MEIP = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:545:1 + localparam MIP_MTIP = 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:546:1 + localparam MIP_MSIP = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:548:1 + localparam MIE_MCEIE = 5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:549:1 + localparam MIE_MITIE0 = 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:550:1 + localparam MIE_MITIE1 = 3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:551:1 + localparam MIE_MEIE = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:552:1 + localparam MIE_MTIE = 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:553:1 + localparam MIE_MSIE = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:555:1 + localparam DCSR_EBREAKM = 15; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:556:1 + localparam DCSR_STEPIE = 11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:557:1 + localparam DCSR_STOPC = 10; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:558:1 + localparam DCSR_STEP = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:561:4 + assign reset_delayed = reset_detect ^ reset_detected; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:568:4 + assign mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:570:5 + rvdffie #(.WIDTH(16)) mpvhalt_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({1'b1, reset_detect, nmi_int_sync, nmi_int_detected, nmi_lsu_load_type, nmi_lsu_store_type, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_halt_state_ns, mpc_run_state_ns, debug_brkpt_status_ns, mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns, dbg_halt_state_ns, dbg_run_state_ns, dec_tlu_mpc_halted_only_ns}), + .dout({reset_detect, reset_detected, nmi_int_delayed, nmi_int_detected_f, nmi_lsu_load_type_f, nmi_lsu_store_type_f, mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f, mpc_halt_state_f, mpc_run_state_f, debug_brkpt_status_f, mpc_debug_halt_ack_f, mpc_debug_run_ack_f, dbg_halt_state_f, dbg_run_state_f, dec_tlu_mpc_halted_only}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:587:4 + assign mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:588:4 + assign mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:591:4 + assign mpc_halt_state_ns = ((mpc_halt_state_f | mpc_debug_halt_req_sync_pulse) | (reset_delayed & ~mpc_reset_run_req)) & ~mpc_debug_run_req_sync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:592:4 + assign mpc_run_state_ns = (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:596:4 + assign dbg_halt_state_ns = (dbg_halt_state_f | (((dbg_halt_req_final | dcsr_single_step_done_f) | trigger_hit_dmode_r_d1) | ebreak_to_debug_mode_r_d1)) & ~dbg_resume_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:597:4 + assign dbg_run_state_ns = (dbg_run_state_f | dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:600:4 + assign dec_tlu_mpc_halted_only_ns = ~dbg_halt_state_f & mpc_halt_state_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:603:4 + assign debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:604:4 + assign debug_brkpt_status_ns = (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:607:4 + assign mpc_debug_halt_ack_ns = (((mpc_halt_state_f & internal_dbg_halt_mode_f) & mpc_debug_halt_req_sync) & core_empty) | (mpc_debug_halt_ack_f & mpc_debug_halt_req_sync); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:608:4 + assign mpc_debug_run_ack_ns = ((mpc_debug_run_req_sync & ~internal_dbg_halt_mode) & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:611:4 + assign mpc_debug_halt_ack = mpc_debug_halt_ack_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:612:4 + assign mpc_debug_run_ack = mpc_debug_run_ack_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:613:4 + assign debug_brkpt_status = debug_brkpt_status_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:616:4 + assign dbg_halt_req_held_ns = (dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:617:4 + assign dbg_halt_req_final = (dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:620:4 + assign debug_halt_req = (((dbg_halt_req_final | mpc_debug_halt_req_sync) | (reset_delayed & ~mpc_reset_run_req)) & ~internal_dbg_halt_mode_f) & ~ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:622:4 + assign debug_resume_req = ~debug_resume_req_f & ((mpc_run_state_ns & ~dbg_halt_state_ns) | (dbg_run_state_ns & ~mpc_halt_state_ns)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:629:4 + assign take_halt = (((((debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r) & ~mret_r) & ~halt_taken_f) & ~dec_tlu_flush_noredir_r_d1) & ~take_reset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:632:4 + assign halt_taken = ((dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1) & ~take_ext_int_start_d1) | (((halt_taken_f & ~dbg_tlu_halted_f) & ~pmu_fw_tlu_halted_f) & ~interrupt_valid_r_d1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:636:4 + assign core_empty = force_halt | ((((((lsu_idle_any & lsu_idle_any_f) & ifu_miss_state_idle) & ifu_miss_state_idle_f) & ~debug_halt_req) & ~debug_halt_req_d1) & ~dec_div_active); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:639:4 + assign dec_tlu_core_empty = core_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:645:4 + assign enter_debug_halt_req = (((~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f) | trigger_hit_dmode_r_d1) | ebreak_to_debug_mode_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:648:4 + assign internal_dbg_halt_mode = debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr[DCSR_STEP])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:650:4 + assign allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:654:4 + assign debug_halt_req_ns = enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:656:4 + assign dbg_tlu_halted = ((debug_halt_req_f & core_empty) & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:658:4 + assign resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f) & dbg_run_state_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:660:4 + assign dcsr_single_step_done = ((dec_tlu_i0_valid_r & ~dec_tlu_dbg_halted) & dcsr[DCSR_STEP]) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:662:4 + assign dcsr_single_step_running = (debug_resume_req_f & dcsr[DCSR_STEP]) | (dcsr_single_step_running_f & ~dcsr_single_step_done_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:664:4 + assign dbg_cmd_done_ns = dec_tlu_i0_valid_r & dec_tlu_dbg_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:667:4 + assign request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~dec_tlu_flush_lower_wb); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:669:4 + assign request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:671:5 + rvdffie #(.WIDTH(18)) halt_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({dec_tlu_flush_noredir_r, halt_taken, lsu_idle_any, ifu_miss_state_idle, dbg_tlu_halted, resume_ack_ns, debug_halt_req_ns, debug_resume_req, trigger_hit_dmode_r, dcsr_single_step_done, debug_halt_req, dec_tlu_wr_pause_r, dec_pause_state, request_debug_mode_r, request_debug_mode_done, dcsr_single_step_running, dec_tlu_flush_pause_r, dbg_halt_req_held_ns}), + .dout({dec_tlu_flush_noredir_r_d1, halt_taken_f, lsu_idle_any_f, ifu_miss_state_idle_f, dbg_tlu_halted_f, dec_tlu_resume_ack, debug_halt_req_f, debug_resume_req_f_raw, trigger_hit_dmode_r_d1, dcsr_single_step_done_f, debug_halt_req_d1, dec_tlu_wr_pause_r_d1, dec_pause_state_f, request_debug_mode_r_d1, request_debug_mode_done_f, dcsr_single_step_running_f, dec_tlu_flush_pause_r_d1, dbg_halt_req_held}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:684:4 + assign debug_resume_req_f = debug_resume_req_f_raw & ~dbg_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:686:4 + assign dec_tlu_debug_stall = debug_halt_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:687:4 + assign dec_tlu_dbg_halted = dbg_tlu_halted_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:688:4 + assign dec_tlu_debug_mode = internal_dbg_halt_mode_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:689:4 + assign dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:692:4 + assign dec_tlu_flush_noredir_r = (((take_halt | (fence_i_r & internal_dbg_halt_mode)) | dec_tlu_flush_pause_r) | (i0_trigger_hit_r & trigger_hit_dmode_r)) | take_ext_int_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:694:4 + assign dec_tlu_flush_extint = take_ext_int_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:697:4 + assign dec_tlu_flush_pause_r = (dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r) & ~take_ext_int_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:700:4 + assign pause_expired_r = (((((~dec_pause_state & dec_pause_state_f) & ~(((((((ext_int_ready | ce_int_ready) | timer_int_ready) | soft_int_ready) | int_timer0_int_hold_f) | int_timer1_int_hold_f) | nmi_int_detected) | ext_int_freeze_d1)) & ~interrupt_valid_r_d1) & ~debug_halt_req_f) & ~pmu_fw_halt_req_f) & ~halt_taken_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:702:4 + assign dec_tlu_flush_leak_one_r = ((dec_tlu_flush_lower_r & dcsr[DCSR_STEP]) & (dec_tlu_resume_ack | dcsr_single_step_running)) & ~dec_tlu_flush_noredir_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:703:4 + assign dec_tlu_flush_err_r = dec_tlu_flush_lower_r & (ic_perr_r | iccm_sbecc_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:706:4 + assign dec_dbg_cmd_done = dbg_cmd_done_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:707:4 + assign dec_dbg_cmd_fail = illegal_r & dec_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:714:1 + localparam MTDATA1_DMODE = 9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:715:1 + localparam MTDATA1_SEL = 7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:716:1 + localparam MTDATA1_ACTION = 6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:717:1 + localparam MTDATA1_CHAIN = 5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:718:1 + localparam MTDATA1_MATCH = 4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:719:1 + localparam MTDATA1_M_ENABLED = 3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:720:1 + localparam MTDATA1_EXE = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:721:1 + localparam MTDATA1_ST = 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:722:1 + localparam MTDATA1_LD = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:729:4 + assign trigger_execute[3:0] = {mtdata1_t3[MTDATA1_EXE], mtdata1_t2[MTDATA1_EXE], mtdata1_t1[MTDATA1_EXE], mtdata1_t0[MTDATA1_EXE]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:730:4 + assign trigger_data[3:0] = {mtdata1_t3[MTDATA1_SEL], mtdata1_t2[MTDATA1_SEL], mtdata1_t1[MTDATA1_SEL], mtdata1_t0[MTDATA1_SEL]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:731:4 + assign trigger_store[3:0] = {mtdata1_t3[MTDATA1_ST], mtdata1_t2[MTDATA1_ST], mtdata1_t1[MTDATA1_ST], mtdata1_t0[MTDATA1_ST]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:734:4 + assign trigger_enabled[3:0] = {(mtdata1_t3[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t3[MTDATA1_M_ENABLED], (mtdata1_t2[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t2[MTDATA1_M_ENABLED], (mtdata1_t1[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t1[MTDATA1_M_ENABLED], (mtdata1_t0[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t0[MTDATA1_M_ENABLED]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:740:4 + assign i0_iside_trigger_has_pri_r[3:0] = ~(((trigger_execute[3:0] & trigger_data[3:0]) & {4 {inst_acc_r_raw}}) | {4 {exu_i0_br_error_r | exu_i0_br_start_error_r}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:744:4 + assign i0_lsu_trigger_has_pri_r[3:0] = ~((trigger_store[3:0] & trigger_data[3:0]) & {4 {lsu_i0_exc_r_raw}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:747:4 + assign i0_trigger_eval_r = dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:749:4 + assign i0trigger_qual_r[3:0] = ((({4 {i0_trigger_eval_r}} & dec_tlu_packet_r[11:8]) & i0_iside_trigger_has_pri_r[3:0]) & i0_lsu_trigger_has_pri_r[3:0]) & trigger_enabled[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:752:4 + assign i0_trigger_r[3:0] = ~{4 {dec_tlu_flush_lower_wb | dec_tlu_dbg_halted}} & i0trigger_qual_r[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:755:4 + assign i0_trigger_chain_masked_r[3:0] = {i0_trigger_r[3] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[2]), i0_trigger_r[2] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[3]), i0_trigger_r[1] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[0]), i0_trigger_r[0] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[1])}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:761:4 + assign i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:763:4 + assign i0_trigger_hit_r = i0_trigger_hit_raw_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:767:4 + assign trigger_action[3:0] = {mtdata1_t3[MTDATA1_ACTION] & mtdata1_t3[MTDATA1_DMODE], (mtdata1_t2[MTDATA1_ACTION] & mtdata1_t2[MTDATA1_DMODE]) & ~mtdata1_t2[MTDATA1_CHAIN], mtdata1_t1[MTDATA1_ACTION] & mtdata1_t1[MTDATA1_DMODE], (mtdata1_t0[MTDATA1_ACTION] & mtdata1_t0[MTDATA1_DMODE]) & ~mtdata1_t0[MTDATA1_CHAIN]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:773:4 + assign update_hit_bit_r[3:0] = {4 {|i0_trigger_r[3:0] & ~rfpc_i0_r}} & {i0_trigger_chain_masked_r[3], i0_trigger_r[2], i0_trigger_chain_masked_r[1], i0_trigger_r[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:776:4 + assign i0_trigger_action_r = |(i0_trigger_chain_masked_r[3:0] & trigger_action[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:778:4 + assign trigger_hit_dmode_r = i0_trigger_hit_r & i0_trigger_action_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:780:4 + assign mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:808:4 + assign i_cpu_halt_req_sync_qual = (i_cpu_halt_req_sync & ~dec_tlu_debug_mode) & ~ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:809:4 + assign i_cpu_run_req_sync_qual = ((i_cpu_run_req_sync & ~dec_tlu_debug_mode) & pmu_fw_tlu_halted_f) & ~ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:811:4 + rvdffie #(.WIDTH(10)) exthaltff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, cpu_halt_status, cpu_halt_ack, cpu_run_ack, internal_pmu_fw_halt_mode, pmu_fw_halt_req_ns, pmu_fw_tlu_halted, int_timer0_int_hold, int_timer1_int_hold}), + .dout({i_cpu_halt_req_d1, i_cpu_run_req_d1_raw, o_cpu_halt_status, o_cpu_halt_ack, o_cpu_run_ack, internal_pmu_fw_halt_mode_f, pmu_fw_halt_req_f, pmu_fw_tlu_halted_f, int_timer0_int_hold_f, int_timer1_int_hold_f}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:821:4 + assign ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:823:4 + assign enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:825:4 + assign pmu_fw_halt_req_ns = (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:827:4 + assign internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | ((internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1) & ~debug_halt_req_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:830:4 + assign pmu_fw_tlu_halted = ((((pmu_fw_halt_req_f & core_empty) & halt_taken) & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:832:4 + assign cpu_halt_ack = (i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f) | (o_cpu_halt_ack & i_cpu_halt_req_sync); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:833:4 + assign cpu_halt_status = (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | ((o_cpu_halt_status & ~i_cpu_run_req_d1) & ~internal_dbg_halt_mode_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:834:4 + assign cpu_run_ack = ((~pmu_fw_tlu_halted_f & i_cpu_run_req_sync) | (o_cpu_halt_status & i_cpu_run_req_d1_raw)) | (o_cpu_run_ack & i_cpu_run_req_sync); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:835:4 + assign debug_mode_status = internal_dbg_halt_mode_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:836:4 + assign o_debug_mode_status = debug_mode_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:844:4 + assign i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | (((((((nmi_int_detected | timer_int_ready) | soft_int_ready) | int_timer0_int_hold_f) | int_timer1_int_hold_f) | (mhwakeup & mhwakeup_ready)) & o_cpu_halt_status) & ~i_cpu_halt_req_d1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:849:4 + assign lsu_single_ecc_error_r = lsu_single_ecc_error_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:851:4 + assign lsu_error_pkt_addr_r[31:0] = lsu_error_pkt_r[33:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:854:4 + assign lsu_exc_valid_r_raw = lsu_error_pkt_r[0] & ~dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:856:4 + assign lsu_i0_exc_r_raw = lsu_error_pkt_r[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:858:4 + assign lsu_i0_exc_r = ((lsu_i0_exc_r_raw & lsu_exc_valid_r_raw) & ~i0_trigger_hit_r) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:860:4 + assign lsu_exc_valid_r = lsu_i0_exc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:862:4 + assign lsu_exc_ma_r = lsu_i0_exc_r & ~lsu_error_pkt_r[38]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:863:4 + assign lsu_exc_acc_r = lsu_i0_exc_r & lsu_error_pkt_r[38]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:864:4 + assign lsu_exc_st_r = lsu_i0_exc_r & lsu_error_pkt_r[39]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:868:4 + assign lsu_i0_rfnpc_r = (dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & (~lsu_error_pkt_r[39] & lsu_error_pkt_r[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:872:4 + assign tlu_i0_commit_cmt = (((((dec_tlu_i0_valid_r & ~rfpc_i0_r) & ~lsu_i0_exc_r) & ~inst_acc_r) & ~dec_tlu_dbg_halted) & ~request_debug_mode_r_d1) & ~i0_trigger_hit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:881:4 + assign tlu_i0_kill_writeb_r = (((rfpc_i0_r | lsu_i0_exc_r) | inst_acc_r) | (illegal_r & dec_tlu_dbg_halted)) | i0_trigger_hit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:882:4 + assign dec_tlu_i0_commit_cmt = tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:887:4 + assign rfpc_i0_r = ((((dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1) & (exu_i0_br_error_r | exu_i0_br_start_error_r)) | ((ic_perr_r | iccm_sbecc_r) & ~ext_int_freeze_d1)) & ~i0_trigger_hit_r) & ~lsu_i0_rfnpc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:893:4 + assign iccm_repair_state_ns = iccm_sbecc_r | (iccm_repair_state_d1 & ~dec_tlu_flush_lower_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:896:4 + localparam MCPC = 12'h7c2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:899:4 + assign iccm_repair_state_rfnpc = (tlu_i0_commit_cmt & iccm_repair_state_d1) & ~(((((ebreak_r | ecall_r) | mret_r) | take_reset) | illegal_r) | (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:902:1 + generate + if (pt[2130-:5] == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:904:4 + assign dec_tlu_br0_error_r = (exu_i0_br_error_r & dec_tlu_i0_valid_r) & ~tlu_flush_lower_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:905:4 + assign dec_tlu_br0_start_error_r = (exu_i0_br_start_error_r & dec_tlu_i0_valid_r) & ~tlu_flush_lower_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:906:4 + assign dec_tlu_br0_v_r = ((exu_i0_br_valid_r & dec_tlu_i0_valid_r) & ~tlu_flush_lower_r_d1) & (~exu_i0_br_mp_r | ~exu_pmu_i0_br_ataken); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:909:4 + assign dec_tlu_br0_r_pkt[5:4] = exu_i0_br_hist_r[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:910:4 + assign dec_tlu_br0_r_pkt[3] = dec_tlu_br0_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:911:4 + assign dec_tlu_br0_r_pkt[2] = dec_tlu_br0_start_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:912:4 + assign dec_tlu_br0_r_pkt[6] = dec_tlu_br0_v_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:913:4 + assign dec_tlu_br0_r_pkt[1] = exu_i0_br_way_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:914:4 + assign dec_tlu_br0_r_pkt[0] = exu_i0_br_middle_r; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:917:4 + assign dec_tlu_br0_error_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:918:4 + assign dec_tlu_br0_start_error_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:919:4 + assign dec_tlu_br0_v_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:920:4 + assign dec_tlu_br0_r_pkt = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:925:4 + assign ebreak_r = ((((dec_tlu_packet_r[3-:4] == 4'b1000) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~dcsr[DCSR_EBREAKM]) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:926:4 + assign ecall_r = (((dec_tlu_packet_r[3-:4] == 4'b1001) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:927:4 + assign illegal_r = ((~dec_tlu_packet_r[5] & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:928:4 + assign mret_r = (((dec_tlu_packet_r[3-:4] == 4'b1100) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:930:4 + assign fence_i_r = ((dec_tlu_packet_r[12] & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:931:4 + assign ic_perr_r = ((ifu_ic_error_start_f & ~ext_int_freeze_d1) & (~internal_dbg_halt_mode_f | dcsr_single_step_running)) & ~internal_pmu_fw_halt_mode_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:932:4 + assign iccm_sbecc_r = ((ifu_iccm_rd_ecc_single_err_f & ~ext_int_freeze_d1) & (~internal_dbg_halt_mode_f | dcsr_single_step_running)) & ~internal_pmu_fw_halt_mode_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:933:4 + assign inst_acc_r_raw = dec_tlu_packet_r[16] & dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:934:4 + assign inst_acc_r = (inst_acc_r_raw & ~rfpc_i0_r) & ~i0_trigger_hit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:935:4 + assign inst_acc_second_r = dec_tlu_packet_r[15]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:937:4 + assign ebreak_to_debug_mode_r = ((((dec_tlu_packet_r[3-:4] == 4'b1000) & dec_tlu_i0_valid_r) & ~i0_trigger_hit_r) & dcsr[DCSR_EBREAKM]) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:939:4 + rvdff #(.WIDTH(1)) exctype_wb_ff( + .rst_l(rst_l), + .clk(e4e5_clk), + .din(ebreak_to_debug_mode_r), + .dout(ebreak_to_debug_mode_r_d1) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:943:4 + assign dec_tlu_fence_i_r = fence_i_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:955:4 + assign i0_exception_valid_r = ((((ebreak_r | ecall_r) | illegal_r) | inst_acc_r) & ~rfpc_i0_r) & ~dec_tlu_dbg_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:964:4 + assign exc_cause_r[4:0] = (((((((((((((({5 {take_ext_int}} & 5'h0b) | ({5 {take_timer_int}} & 5'h07)) | ({5 {take_soft_int}} & 5'h03)) | ({5 {take_int_timer0_int}} & 5'h1d)) | ({5 {take_int_timer1_int}} & 5'h1c)) | ({5 {take_ce_int}} & 5'h1e)) | ({5 {illegal_r}} & 5'h02)) | ({5 {ecall_r}} & 5'h0b)) | ({5 {inst_acc_r}} & 5'h01)) | ({5 {ebreak_r | i0_trigger_hit_r}} & 5'h03)) | ({5 {lsu_exc_ma_r & ~lsu_exc_st_r}} & 5'h04)) | ({5 {lsu_exc_acc_r & ~lsu_exc_st_r}} & 5'h05)) | ({5 {lsu_exc_ma_r & lsu_exc_st_r}} & 5'h06)) | ({5 {lsu_exc_acc_r & lsu_exc_st_r}} & 5'h07)) & ~{5 {take_nmi}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:989:4 + assign mhwakeup_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MEIP]) & mie_ns[MIE_MEIE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:990:4 + assign ext_int_ready = (((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MEIP]) & mie_ns[MIE_MEIE]) & ~ignore_ext_int_due_to_lsu_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:991:4 + assign ce_int_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MCEIP]) & mie_ns[MIE_MCEIE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:992:4 + assign soft_int_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MSIP]) & mie_ns[MIE_MSIE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:993:4 + assign timer_int_ready = ((~dec_csr_stall_int_ff & mstatus_mie_ns) & mip[MIP_MTIP]) & mie_ns[MIE_MTIE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:996:4 + assign int_timer0_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:997:4 + assign int_timer0_int_ready = mip[MIP_MITIP0] & int_timer0_int_possible; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:998:4 + assign int_timer1_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:999:4 + assign int_timer1_int_ready = mip[MIP_MITIP1] & int_timer1_int_possible; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1003:4 + assign int_timer_stalled = ((dec_csr_stall_int_ff | synchronous_flush_r) | exc_or_int_valid_r_d1) | mret_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1005:4 + assign int_timer0_int_hold = (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | ((((int_timer0_int_possible & int_timer0_int_hold_f) & ~interrupt_valid_r) & ~take_ext_int_start) & ~internal_dbg_halt_mode_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1006:4 + assign int_timer1_int_hold = (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | ((((int_timer1_int_possible & int_timer1_int_hold_f) & ~interrupt_valid_r) & ~take_ext_int_start) & ~internal_dbg_halt_mode_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1009:4 + assign internal_dbg_halt_timers = internal_dbg_halt_mode_f & ~dcsr_single_step_running; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1012:4 + assign block_interrupts = ((((((((internal_dbg_halt_mode & (~dcsr_single_step_running | dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode) | i_cpu_halt_req_d1) | take_nmi) | ebreak_to_debug_mode_r) | synchronous_flush_r) | exc_or_int_valid_r_d1) | mret_r) | ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1023:1 + generate + if (pt[1227-:5]) begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1026:4 + assign take_ext_int_start = ext_int_ready & ~block_interrupts; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1028:4 + assign ext_int_freeze = ((take_ext_int_start | take_ext_int_start_d1) | take_ext_int_start_d2) | take_ext_int_start_d3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1029:4 + assign take_ext_int = take_ext_int_start_d3 & ~|lsu_fir_error[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1030:4 + assign fast_int_meicpct = csr_meicpct & dec_csr_any_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1032:4 + assign ignore_ext_int_due_to_lsu_stall = lsu_fastint_stall_any; + end + else begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1035:4 + assign take_ext_int_start = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1036:4 + assign ext_int_freeze = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1037:4 + assign ext_int_freeze_d1 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1038:4 + assign take_ext_int_start_d1 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1039:4 + assign take_ext_int_start_d2 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1040:4 + assign take_ext_int_start_d3 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1041:4 + assign fast_int_meicpct = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1042:4 + assign ignore_ext_int_due_to_lsu_stall = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1044:4 + assign take_ext_int = ext_int_ready & ~block_interrupts; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1047:4 + assign take_ce_int = (ce_int_ready & ~ext_int_ready) & ~block_interrupts; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1048:4 + assign take_soft_int = ((soft_int_ready & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1049:4 + assign take_timer_int = (((timer_int_ready & ~soft_int_ready) & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1050:4 + assign take_int_timer0_int = (((((((int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible) & ~dec_csr_stall_int_ff) & ~timer_int_ready) & ~soft_int_ready) & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1052:4 + assign take_int_timer1_int = ((((((((int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible) & ~dec_csr_stall_int_ff) & ~(int_timer0_int_ready | int_timer0_int_hold_f)) & ~timer_int_ready) & ~soft_int_ready) & ~ext_int_ready) & ~ce_int_ready) & ~block_interrupts; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1055:4 + assign take_reset = reset_delayed & mpc_reset_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1056:4 + assign take_nmi = ((((((nmi_int_detected & ~internal_pmu_fw_halt_mode) & (~internal_dbg_halt_mode | (((dcsr_single_step_running_f & dcsr[DCSR_STEPIE]) & ~dec_tlu_i0_valid_r) & ~dcsr_single_step_done_f))) & ~synchronous_flush_r) & ~mret_r) & ~take_reset) & ~ebreak_to_debug_mode_r) & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & |lsu_fir_error[1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1059:4 + assign interrupt_valid_r = (((((take_ext_int | take_timer_int) | take_soft_int) | take_nmi) | take_ce_int) | take_int_timer0_int) | take_int_timer1_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1064:4 + assign vectored_path[31:1] = {mtvec[30:1], 1'b0} + {25'b0000000000000000000000000, exc_cause_r[4:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1065:4 + assign interrupt_path[31:1] = (take_nmi ? nmi_vec[31:1] : (mtvec[0] == 1'b1 ? vectored_path[31:1] : {mtvec[30:1], 1'b0})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1067:4 + assign sel_npc_r = (((lsu_i0_rfnpc_r | fence_i_r) | iccm_repair_state_rfnpc) | (i_cpu_run_req_d1 & ~interrupt_valid_r)) | (rfpc_i0_r & ~dec_tlu_i0_valid_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1068:4 + assign sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1070:4 + assign sel_fir_addr = take_ext_int_start_d3 & ~|lsu_fir_error[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1072:4 + assign synchronous_flush_r = ((((((((i0_exception_valid_r | rfpc_i0_r) | lsu_exc_valid_r) | fence_i_r) | lsu_i0_rfnpc_r) | iccm_repair_state_rfnpc) | debug_resume_req_f) | sel_npc_resume) | dec_tlu_wr_pause_r_d1) | i0_trigger_hit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1083:4 + assign tlu_flush_lower_r = ((((interrupt_valid_r | mret_r) | synchronous_flush_r) | take_halt) | take_reset) | take_ext_int_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1085:4 + assign tlu_flush_path_r[31:1] = (take_reset ? rst_vec[31:1] : ((((((({31 {sel_fir_addr}} & lsu_fir_addr[31:1]) | ({31 {~take_nmi & sel_npc_r}} & npc_r[31:1])) | ({31 {((~take_nmi & rfpc_i0_r) & dec_tlu_i0_valid_r) & ~sel_npc_r}} & dec_tlu_i0_pc_r[31:1])) | ({31 {interrupt_valid_r & ~sel_fir_addr}} & interrupt_path[31:1])) | ({31 {(((i0_exception_valid_r | lsu_exc_valid_r) | (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r) & ~sel_fir_addr}} & {mtvec[30:1], 1'b0})) | ({31 {~take_nmi & mret_r}} & mepc[31:1])) | ({31 {~take_nmi & debug_resume_req_f}} & dpc[31:1])) | ({31 {~take_nmi & sel_npc_resume}} & npc_r_d1[31:1])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1097:4 + rvdffpcie #(.WIDTH(31)) flush_lower_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(tlu_flush_lower_r), + .din({tlu_flush_path_r[31:1]}), + .dout({tlu_flush_path_r_d1[31:1]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1101:4 + assign dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1102:4 + assign dec_tlu_flush_lower_r = tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1103:4 + assign dec_tlu_flush_path_r[31:1] = tlu_flush_path_r[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1107:4 + assign exc_or_int_valid_r = ((lsu_exc_valid_r | i0_exception_valid_r) | interrupt_valid_r) | (i0_trigger_hit_r & ~trigger_hit_dmode_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1110:4 + rvdffie #(.WIDTH(12)) excinfo_wb_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({interrupt_valid_r, i0_exception_valid_r, exc_or_int_valid_r, exc_cause_r[4:0], tlu_i0_commit_cmt & ~illegal_r, i0_trigger_hit_r, take_nmi, pause_expired_r}), + .dout({interrupt_valid_r_d1, i0_exception_valid_r_d1, exc_or_int_valid_r_d1, exc_cause_wb[4:0], i0_valid_wb, trigger_hit_r_d1, take_nmi_r_d1, pause_expired_wb}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1131:4 + localparam MISA = 12'h301; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1134:4 + localparam MVENDORID = 12'hf11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1135:4 + localparam MARCHID = 12'hf12; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1136:4 + localparam MIMPID = 12'hf13; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1137:4 + localparam MHARTID = 12'hf14; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1145:4 + localparam MSTATUS = 12'h300; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1151:4 + assign dec_csr_wen_r_mod = (dec_csr_wen_r & ~i0_trigger_hit_r) & ~rfpc_i0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1152:4 + assign wr_mstatus_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSTATUS); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1155:4 + assign set_mie_pmu_fw_halt = ~mpmc_b_ns[1] & fw_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1157:4 + assign mstatus_ns[1:0] = ((((({2 {~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MIE], 1'b0}) | ({2 {wr_mstatus_r & exc_or_int_valid_r}} & {dec_csr_wrdata_r[3], 1'b0})) | ({2 {mret_r & ~exc_or_int_valid_r}} & {1'b1, mstatus[1]})) | ({2 {set_mie_pmu_fw_halt}} & {mstatus[1], 1'b1})) | ({2 {wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]})) | ({2 {((~wr_mstatus_r & ~exc_or_int_valid_r) & ~mret_r) & ~set_mie_pmu_fw_halt}} & mstatus[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1165:4 + assign mstatus_mie_ns = mstatus[MSTATUS_MIE] & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1172:4 + localparam MTVEC = 12'h305; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1174:4 + assign wr_mtvec_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVEC); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1175:4 + assign mtvec_ns[30:0] = {dec_csr_wrdata_r[31:2], dec_csr_wrdata_r[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1176:4 + rvdffe #(.WIDTH(31)) mtvec_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mtvec_r), + .din(mtvec_ns[30:0]), + .dout(mtvec[30:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1187:4 + localparam MIP = 12'h344; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1189:4 + assign ce_int = (mdccme_ce_req | miccme_ce_req) | mice_ce_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1191:4 + assign mip_ns[5:0] = {ce_int, dec_timer_t0_pulse, dec_timer_t1_pulse, mexintpend, timer_int_sync, soft_int_sync}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1201:4 + localparam MIE = 12'h304; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1203:4 + assign wr_mie_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MIE); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1204:4 + assign mie_ns[5:0] = (wr_mie_r ? {dec_csr_wrdata_r[30:28], dec_csr_wrdata_r[11], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]} : mie[5:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1205:4 + rvdff #(.WIDTH(6)) mie_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .din(mie_ns[5:0]), + .dout(mie[5:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1212:4 + localparam MCYCLEL = 12'hb00; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1214:4 + assign kill_ebreak_count_r = ebreak_to_debug_mode_r & dcsr[DCSR_STOPC]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1216:4 + assign wr_mcyclel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEL); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1218:4 + assign mcyclel_cout_in = ~(((kill_ebreak_count_r | (dec_tlu_dbg_halted & dcsr[DCSR_STOPC])) | dec_tlu_pmu_fw_halted) | mcountinhibit[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1221:4 + assign {mcyclela_cout, mcyclel_inc[7:0]} = mcyclel[7:0] + 8'b00000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1222:4 + assign {mcyclel_cout, mcyclel_inc[31:8]} = mcyclel[31:8] + {23'b00000000000000000000000, mcyclela_cout}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1224:4 + assign mcyclel_ns[31:0] = (wr_mcyclel_r ? dec_csr_wrdata_r[31:0] : mcyclel_inc[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1226:4 + rvdffe #(.WIDTH(24)) mcyclel_bff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(wr_mcyclel_r | (mcyclela_cout & mcyclel_cout_in)), + .din(mcyclel_ns[31:8]), + .dout(mcyclel[31:8]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1227:4 + rvdffe #(.WIDTH(8)) mcyclel_aff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(wr_mcyclel_r | mcyclel_cout_in), + .din(mcyclel_ns[7:0]), + .dout(mcyclel[7:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1234:4 + localparam MCYCLEH = 12'hb80; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1236:4 + assign wr_mcycleh_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEH); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1238:4 + assign mcycleh_inc[31:0] = mcycleh[31:0] + {31'b0000000000000000000000000000000, mcyclel_cout_f}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1239:4 + assign mcycleh_ns[31:0] = (wr_mcycleh_r ? dec_csr_wrdata_r[31:0] : mcycleh_inc[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1241:4 + rvdffe #(.WIDTH(32)) mcycleh_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(wr_mcycleh_r | mcyclel_cout_f), + .din(mcycleh_ns[31:0]), + .dout(mcycleh[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1252:4 + localparam MINSTRETL = 12'hb02; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1254:4 + assign i0_valid_no_ebreak_ecall_r = dec_tlu_i0_valid_r & ~((((ebreak_r | ecall_r) | ebreak_to_debug_mode_r) | illegal_r) | mcountinhibit[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1256:4 + assign wr_minstretl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETL); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1258:4 + assign {minstretl_couta, minstretl_inc[7:0]} = minstretl[7:0] + 8'b00000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1259:4 + assign {minstretl_cout, minstretl_inc[31:8]} = minstretl[31:8] + {23'b00000000000000000000000, minstretl_couta}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1261:4 + assign minstret_enable = (i0_valid_no_ebreak_ecall_r & tlu_i0_commit_cmt) | wr_minstretl_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1263:4 + assign minstretl_cout_ns = ((minstretl_cout & ~wr_minstreth_r) & i0_valid_no_ebreak_ecall_r) & ~dec_tlu_dbg_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1265:4 + assign minstretl_ns[31:0] = (wr_minstretl_r ? dec_csr_wrdata_r[31:0] : minstretl_inc[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1266:4 + rvdffe #(.WIDTH(24)) minstretl_bff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_minstretl_r | (minstretl_couta & minstret_enable)), + .din(minstretl_ns[31:8]), + .dout(minstretl[31:8]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1268:4 + rvdffe #(.WIDTH(8)) minstretl_aff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(minstret_enable), + .din(minstretl_ns[7:0]), + .dout(minstretl[7:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1272:4 + assign minstretl_read[31:0] = minstretl[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1278:4 + localparam MINSTRETH = 12'hb82; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1280:4 + assign wr_minstreth_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETH); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1282:4 + assign minstreth_inc[31:0] = minstreth[31:0] + {31'b0000000000000000000000000000000, minstretl_cout_f}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1283:4 + assign minstreth_ns[31:0] = (wr_minstreth_r ? dec_csr_wrdata_r[31:0] : minstreth_inc[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1284:4 + rvdffe #(.WIDTH(32)) minstreth_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((minstret_enable_f & minstretl_cout_f) | wr_minstreth_r), + .din(minstreth_ns[31:0]), + .dout(minstreth[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1286:4 + assign minstreth_read[31:0] = minstreth_inc[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1291:4 + localparam MSCRATCH = 12'h340; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1293:4 + assign wr_mscratch_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCRATCH); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1295:4 + rvdffe #(.WIDTH(32)) mscratch_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mscratch_r), + .din(dec_csr_wrdata_r[31:0]), + .dout(mscratch[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1300:4 + localparam MEPC = 12'h341; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1304:4 + assign sel_exu_npc_r = (~dec_tlu_dbg_halted & ~tlu_flush_lower_r_d1) & dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1305:4 + assign sel_flush_npc_r = (~dec_tlu_dbg_halted & tlu_flush_lower_r_d1) & ~dec_tlu_flush_noredir_r_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1306:4 + assign sel_hold_npc_r = ~sel_exu_npc_r & ~sel_flush_npc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1308:4 + assign npc_r[31:1] = ((({31 {sel_exu_npc_r}} & exu_npc_r[31:1]) | ({31 {~mpc_reset_run_req & reset_delayed}} & rst_vec[31:1])) | ({31 {sel_flush_npc_r}} & tlu_flush_path_r_d1[31:1])) | ({31 {sel_hold_npc_r}} & npc_r_d1[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1313:4 + rvdffpcie #(.WIDTH(31)) npwbc_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((sel_exu_npc_r | sel_flush_npc_r) | reset_delayed), + .din(npc_r[31:1]), + .dout(npc_r_d1[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1317:4 + assign pc0_valid_r = ~dec_tlu_dbg_halted & dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1319:4 + assign pc_r[31:1] = ({31 {pc0_valid_r}} & dec_tlu_i0_pc_r[31:1]) | ({31 {~pc0_valid_r}} & pc_r_d1[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1322:4 + rvdffpcie #(.WIDTH(31)) pwbc_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(pc0_valid_r), + .din(pc_r[31:1]), + .dout(pc_r_d1[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1324:4 + assign wr_mepc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEPC); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1326:4 + assign mepc_ns[31:1] = ((({31 {(i0_exception_valid_r | lsu_exc_valid_r) | mepc_trigger_hit_sel_pc_r}} & pc_r[31:1]) | ({31 {interrupt_valid_r}} & npc_r[31:1])) | ({31 {wr_mepc_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:1])) | ({31 {~wr_mepc_r & ~exc_or_int_valid_r}} & mepc[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1332:4 + rvdffe #(.WIDTH(31)) mepc_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((((i0_exception_valid_r | lsu_exc_valid_r) | mepc_trigger_hit_sel_pc_r) | interrupt_valid_r) | wr_mepc_r), + .din(mepc_ns[31:1]), + .dout(mepc[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1337:4 + localparam MCAUSE = 12'h342; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1339:4 + assign wr_mcause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCAUSE); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1340:4 + assign mcause_sel_nmi_store = (exc_or_int_valid_r & take_nmi) & nmi_lsu_store_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1341:4 + assign mcause_sel_nmi_load = (exc_or_int_valid_r & take_nmi) & nmi_lsu_load_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1342:4 + assign mcause_sel_nmi_ext = (((exc_or_int_valid_r & take_nmi) & take_ext_int_start_d3) & |lsu_fir_error[1:0]) & ~nmi_int_detected_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1348:4 + assign mcause_fir_error_type[1:0] = {&lsu_fir_error[1:0], lsu_fir_error[1] & ~lsu_fir_error[0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1350:4 + assign mcause_ns[31:0] = ((((({32 {mcause_sel_nmi_store}} & 32'hf0000000) | ({32 {mcause_sel_nmi_load}} & 32'hf0000001)) | ({32 {mcause_sel_nmi_ext}} & {30'h3c000400, mcause_fir_error_type[1:0]})) | ({32 {exc_or_int_valid_r & ~take_nmi}} & {interrupt_valid_r, 26'b00000000000000000000000000, exc_cause_r[4:0]})) | ({32 {wr_mcause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:0])) | ({32 {~wr_mcause_r & ~exc_or_int_valid_r}} & mcause[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1357:4 + rvdffe #(.WIDTH(32)) mcause_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(exc_or_int_valid_r | wr_mcause_r), + .din(mcause_ns[31:0]), + .dout(mcause[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1361:4 + localparam MSCAUSE = 12'h7ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1363:4 + assign wr_mscause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCAUSE); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1365:4 + assign ifu_mscause[3:0] = (dec_tlu_packet_r[14:13] == 2'b00 ? 4'b1001 : {2'b00, dec_tlu_packet_r[14:13]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1368:4 + assign mscause_type[3:0] = ((({4 {lsu_i0_exc_r}} & lsu_error_pkt_r[37:34]) | ({4 {i0_trigger_hit_r}} & 4'b0001)) | ({4 {ebreak_r}} & 4'b0010)) | ({4 {inst_acc_r}} & ifu_mscause[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1374:4 + assign mscause_ns[3:0] = (({4 {exc_or_int_valid_r}} & mscause_type[3:0]) | ({4 {wr_mscause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[3:0])) | ({4 {~wr_mscause_r & ~exc_or_int_valid_r}} & mscause[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1379:4 + rvdff #(.WIDTH(4)) mscause_ff( + .rst_l(rst_l), + .clk(e4e5_int_clk), + .din(mscause_ns[3:0]), + .dout(mscause[3:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1383:4 + localparam MTVAL = 12'h343; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1385:4 + assign wr_mtval_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVAL); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1386:4 + assign mtval_capture_pc_r = (exc_or_int_valid_r & ((ebreak_r | (inst_acc_r & ~inst_acc_second_r)) | mepc_trigger_hit_sel_pc_r)) & ~take_nmi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1387:4 + assign mtval_capture_pc_plus2_r = (exc_or_int_valid_r & (inst_acc_r & inst_acc_second_r)) & ~take_nmi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1388:4 + assign mtval_capture_inst_r = (exc_or_int_valid_r & illegal_r) & ~take_nmi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1389:4 + assign mtval_capture_lsu_r = (exc_or_int_valid_r & lsu_exc_valid_r) & ~take_nmi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1390:4 + assign mtval_clear_r = (((exc_or_int_valid_r & ~mtval_capture_pc_r) & ~mtval_capture_inst_r) & ~mtval_capture_lsu_r) & ~mepc_trigger_hit_sel_pc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1393:4 + assign mtval_ns[31:0] = ((((({32 {mtval_capture_pc_r}} & {pc_r[31:1], 1'b0}) | ({32 {mtval_capture_pc_plus2_r}} & {pc_r[31:1] + 31'b0000000000000000000000000000001, 1'b0})) | ({32 {mtval_capture_inst_r}} & dec_illegal_inst[31:0])) | ({32 {mtval_capture_lsu_r}} & lsu_error_pkt_addr_r[31:0])) | ({32 {wr_mtval_r & ~interrupt_valid_r}} & dec_csr_wrdata_r[31:0])) | ({32 {((((~take_nmi & ~wr_mtval_r) & ~mtval_capture_pc_r) & ~mtval_capture_inst_r) & ~mtval_clear_r) & ~mtval_capture_lsu_r}} & mtval[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1401:4 + rvdffe #(.WIDTH(32)) mtval_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(tlu_flush_lower_r | wr_mtval_r), + .din(mtval_ns[31:0]), + .dout(mtval[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1416:4 + localparam MCGC = 12'h7f8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1417:4 + assign wr_mcgc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCGC); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1419:4 + assign mcgc_ns[9:0] = (wr_mcgc_r ? {~dec_csr_wrdata_r[9], dec_csr_wrdata_r[8:0]} : mcgc_int[9:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1420:4 + rvdffe #(.WIDTH(10)) mcgc_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mcgc_r), + .din(mcgc_ns[9:0]), + .dout(mcgc_int[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1422:4 + assign mcgc[9:0] = {~mcgc_int[9], mcgc_int[8:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1424:4 + assign dec_tlu_picio_clk_override = mcgc[9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1425:4 + assign dec_tlu_misc_clk_override = mcgc[8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1426:4 + assign dec_tlu_dec_clk_override = mcgc[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1428:4 + assign dec_tlu_ifu_clk_override = mcgc[5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1429:4 + assign dec_tlu_lsu_clk_override = mcgc[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1430:4 + assign dec_tlu_bus_clk_override = mcgc[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1431:4 + assign dec_tlu_pic_clk_override = mcgc[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1432:4 + assign dec_tlu_dccm_clk_override = mcgc[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1433:4 + assign dec_tlu_icm_clk_override = mcgc[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1454:4 + localparam MFDC = 12'h7f9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1456:4 + assign wr_mfdc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDC); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1458:4 + rvdffe #(.WIDTH(16)) mfdc_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mfdc_r), + .din({mfdc_ns[15:0]}), + .dout(mfdc_int[15:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1461:4 + generate + if (pt[2037-:5] == 1) begin : axi4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1463:10 + assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12], dec_csr_wrdata_r[11:7], ~dec_csr_wrdata_r[6], dec_csr_wrdata_r[5:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1464:10 + assign mfdc[18:0] = {~mfdc_int[15:13], 3'b000, mfdc_int[12], mfdc_int[11:7], ~mfdc_int[6], mfdc_int[5:0]}; + end + else begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1468:10 + assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1469:10 + assign mfdc[18:0] = {~mfdc_int[15:13], 3'b000, mfdc_int[12:0]}; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1473:4 + assign dec_tlu_dma_qos_prty[2:0] = mfdc[18:16]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1474:4 + assign dec_tlu_trace_disable = mfdc[12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1475:4 + assign dec_tlu_external_ldfwd_disable = mfdc[11]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1476:4 + assign dec_tlu_core_ecc_disable = mfdc[8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1477:4 + assign dec_tlu_sideeffect_posted_disable = mfdc[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1478:4 + assign dec_tlu_bpred_disable = mfdc[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1479:4 + assign dec_tlu_wb_coalescing_disable = mfdc[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1480:4 + assign dec_tlu_pipelining_disable = mfdc[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1486:4 + assign dec_tlu_wr_pause_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC)) & ~interrupt_valid_r) & ~take_ext_int_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1491:4 + localparam MRAC = 12'h7c0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1493:4 + assign wr_mrac_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MRAC); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1496:4 + assign mrac_in[31:0] = {dec_csr_wrdata_r[31], dec_csr_wrdata_r[30] & ~dec_csr_wrdata_r[31], dec_csr_wrdata_r[29], dec_csr_wrdata_r[28] & ~dec_csr_wrdata_r[29], dec_csr_wrdata_r[27], dec_csr_wrdata_r[26] & ~dec_csr_wrdata_r[27], dec_csr_wrdata_r[25], dec_csr_wrdata_r[24] & ~dec_csr_wrdata_r[25], dec_csr_wrdata_r[23], dec_csr_wrdata_r[22] & ~dec_csr_wrdata_r[23], dec_csr_wrdata_r[21], dec_csr_wrdata_r[20] & ~dec_csr_wrdata_r[21], dec_csr_wrdata_r[19], dec_csr_wrdata_r[18] & ~dec_csr_wrdata_r[19], dec_csr_wrdata_r[17], dec_csr_wrdata_r[16] & ~dec_csr_wrdata_r[17], dec_csr_wrdata_r[15], dec_csr_wrdata_r[14] & ~dec_csr_wrdata_r[15], dec_csr_wrdata_r[13], dec_csr_wrdata_r[12] & ~dec_csr_wrdata_r[13], dec_csr_wrdata_r[11], dec_csr_wrdata_r[10] & ~dec_csr_wrdata_r[11], dec_csr_wrdata_r[9], dec_csr_wrdata_r[8] & ~dec_csr_wrdata_r[9], dec_csr_wrdata_r[7], dec_csr_wrdata_r[6] & ~dec_csr_wrdata_r[7], dec_csr_wrdata_r[5], dec_csr_wrdata_r[4] & ~dec_csr_wrdata_r[5], dec_csr_wrdata_r[3], dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[3], dec_csr_wrdata_r[1], dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[1]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1513:4 + rvdffe #(.WIDTH(32)) mrac_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mrac_r), + .din(mrac_in[31:0]), + .dout(mrac[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1516:4 + assign dec_tlu_mrac_ff[31:0] = mrac[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1522:4 + localparam MDEAU = 12'hbc0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1524:4 + assign wr_mdeau_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDEAU); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1531:4 + localparam MDSEAC = 12'hfc0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1534:4 + assign mdseac_locked_ns = mdseac_en | (mdseac_locked_f & ~wr_mdeau_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1536:4 + assign mdseac_en = ((lsu_imprecise_error_store_any | lsu_imprecise_error_load_any) & ~nmi_int_detected_f) & ~mdseac_locked_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1538:4 + rvdffe #(.WIDTH(32)) mdseac_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(mdseac_en), + .din(lsu_imprecise_error_addr_any[31:0]), + .dout(mdseac[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1545:4 + localparam MPMC = 12'h7c6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1547:4 + assign wr_mpmc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MPMC); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1551:4 + assign fw_halt_req = ((wr_mpmc_r & dec_csr_wrdata_r[0]) & ~internal_dbg_halt_mode_f2) & ~ext_int_freeze_d1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1553:4 + assign fw_halted_ns = (fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1554:4 + assign mpmc_b_ns[1] = (wr_mpmc_r ? ~dec_csr_wrdata_r[1] : ~mpmc[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1555:4 + rvdff #(.WIDTH(1)) mpmc_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .din(mpmc_b_ns[1]), + .dout(mpmc_b[1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1556:4 + assign mpmc[1] = ~mpmc_b[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1562:4 + localparam MICECT = 12'h7f0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1564:4 + assign csr_sat[31:27] = (dec_csr_wrdata_r[31:27] > 5'd26 ? 5'd26 : dec_csr_wrdata_r[31:27]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1566:4 + assign wr_micect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICECT); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1567:4 + assign micect_inc[26:0] = micect[26:0] + {26'b00000000000000000000000000, ic_perr_r}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1568:4 + assign micect_ns = (wr_micect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {micect[31:27], micect_inc[26:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1570:4 + rvdffe #(.WIDTH(32)) micect_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_micect_r | ic_perr_r), + .din(micect_ns[31:0]), + .dout(micect[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1572:4 + assign mice_ce_req = |({32'hffffffff << micect[31:27]} & {5'b00000, micect[26:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1578:4 + localparam MICCMECT = 12'h7f1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1580:4 + assign wr_miccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICCMECT); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1581:4 + assign miccmect_inc[26:0] = miccmect[26:0] + {26'b00000000000000000000000000, iccm_sbecc_r | iccm_dma_sb_error}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1582:4 + assign miccmect_ns = (wr_miccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {miccmect[31:27], miccmect_inc[26:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1584:4 + rvdffe #(.WIDTH(32)) miccmect_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en((wr_miccmect_r | iccm_sbecc_r) | iccm_dma_sb_error), + .din(miccmect_ns[31:0]), + .dout(miccmect[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1586:4 + assign miccme_ce_req = |({32'hffffffff << miccmect[31:27]} & {5'b00000, miccmect[26:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1592:4 + localparam MDCCMECT = 12'h7f2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1594:4 + assign wr_mdccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDCCMECT); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1595:4 + assign mdccmect_inc[26:0] = mdccmect[26:0] + {26'b00000000000000000000000000, lsu_single_ecc_error_r_d1}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1596:4 + assign mdccmect_ns = (wr_mdccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {mdccmect[31:27], mdccmect_inc[26:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1598:4 + rvdffe #(.WIDTH(32)) mdccmect_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(wr_mdccmect_r | lsu_single_ecc_error_r_d1), + .din(mdccmect_ns[31:0]), + .dout(mdccmect[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1600:4 + assign mdccme_ce_req = |({32'hffffffff << mdccmect[31:27]} & {5'b00000, mdccmect[26:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1607:4 + localparam MFDHT = 12'h7ce; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1609:4 + assign wr_mfdht_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHT); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1611:4 + assign mfdht_ns[5:0] = (wr_mfdht_r ? dec_csr_wrdata_r[5:0] : mfdht[5:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1613:4 + rvdffs #(.WIDTH(6)) mfdht_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .en(wr_mfdht_r), + .din(mfdht_ns[5:0]), + .dout(mfdht[5:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1620:4 + localparam MFDHS = 12'h7cf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1622:4 + assign wr_mfdhs_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHS); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1624:4 + assign mfdhs_ns[1:0] = (wr_mfdhs_r ? dec_csr_wrdata_r[1:0] : (dbg_tlu_halted & ~dbg_tlu_halted_f ? {~lsu_idle_any_f, ~ifu_miss_state_idle_f} : mfdhs[1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1626:4 + rvdffs #(.WIDTH(2)) mfdhs_ff( + .rst_l(rst_l), + .clk(free_clk), + .en(wr_mfdhs_r | dbg_tlu_halted), + .din(mfdhs_ns[1:0]), + .dout(mfdhs[1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1628:4 + assign force_halt_ctr[31:0] = (debug_halt_req_f ? force_halt_ctr_f[31:0] + 32'b00000000000000000000000000000001 : (dbg_tlu_halted_f ? 32'b00000000000000000000000000000000 : force_halt_ctr_f[31:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1630:4 + rvdffe #(.WIDTH(32)) forcehaltctr_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(mfdht[0]), + .din(force_halt_ctr[31:0]), + .dout(force_halt_ctr_f[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1632:4 + assign force_halt = mfdht[0] & |(force_halt_ctr_f[31:0] & (32'hffffffff << mfdht[5:1])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1639:4 + localparam MEIVT = 12'hbc8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1641:4 + assign wr_meivt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIVT); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1643:4 + rvdffe #(.WIDTH(22)) meivt_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_meivt_r), + .din(dec_csr_wrdata_r[31:10]), + .dout(meivt[31:10]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1651:4 + localparam MEIHAP = 12'hfc8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1653:4 + assign wr_meihap_r = wr_meicpct_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1655:4 + rvdffe #(.WIDTH(8)) meihap_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_meihap_r), + .din(pic_claimid[7:0]), + .dout(meihap[9:2]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1657:4 + assign dec_tlu_meihap[31:2] = {meivt[31:10], meihap[9:2]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1662:4 + localparam MEICURPL = 12'hbcc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1664:4 + assign wr_meicurpl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICURPL); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1665:4 + assign meicurpl_ns[3:0] = (wr_meicurpl_r ? dec_csr_wrdata_r[3:0] : meicurpl[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1667:4 + rvdff #(.WIDTH(4)) meicurpl_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .din(meicurpl_ns[3:0]), + .dout(meicurpl[3:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1670:4 + assign dec_tlu_meicurpl[3:0] = meicurpl[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1677:4 + localparam MEICIDPL = 12'hbcb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1679:4 + assign wr_meicidpl_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICIDPL)) | take_ext_int_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1681:4 + assign meicidpl_ns[3:0] = (wr_meicpct_r ? pic_pl[3:0] : (wr_meicidpl_r ? dec_csr_wrdata_r[3:0] : meicidpl[3:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1688:4 + localparam MEICPCT = 12'hbca; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1690:4 + assign wr_meicpct_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICPCT)) | take_ext_int_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1696:4 + localparam MEIPT = 12'hbc9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1698:4 + assign wr_meipt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIPT); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1699:4 + assign meipt_ns[3:0] = (wr_meipt_r ? dec_csr_wrdata_r[3:0] : meipt[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1701:4 + rvdff #(.WIDTH(4)) meipt_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .din(meipt_ns[3:0]), + .dout(meipt[3:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1704:4 + assign dec_tlu_meipt[3:0] = meipt[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1722:4 + localparam DCSR = 12'h7b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1728:4 + assign trigger_hit_for_dscr_cause_r_d1 = trigger_hit_dmode_r_d1 | (trigger_hit_r_d1 & dcsr_single_step_done_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1730:4 + assign dcsr_cause[8:6] = ((({3 {((dcsr_single_step_done_f & ~ebreak_to_debug_mode_r_d1) & ~trigger_hit_for_dscr_cause_r_d1) & ~debug_halt_req}} & 3'b100) | ({3 {(debug_halt_req & ~ebreak_to_debug_mode_r_d1) & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b011)) | ({3 {ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b001)) | ({3 {trigger_hit_for_dscr_cause_r_d1}} & 3'b010); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1735:4 + assign wr_dcsr_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DCSR); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1741:4 + assign dcsr_cause_upgradeable = internal_dbg_halt_mode_f & (dcsr[8:6] == 3'b011); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1742:4 + assign enter_debug_halt_req_le = enter_debug_halt_req & (~dbg_tlu_halted | dcsr_cause_upgradeable); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1744:4 + assign nmi_in_debug_mode = nmi_int_detected_f & internal_dbg_halt_mode_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1745:4 + assign dcsr_ns[15:2] = (enter_debug_halt_req_le ? {dcsr[15:9], dcsr_cause[8:6], dcsr[5:2]} : (wr_dcsr_r ? {dec_csr_wrdata_r[15], 3'b000, dec_csr_wrdata_r[11:10], 1'b0, dcsr[8:6], 2'b00, nmi_in_debug_mode | dcsr[3], dec_csr_wrdata_r[2]} : {dcsr[15:4], nmi_in_debug_mode, dcsr[2]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1749:4 + rvdffe #(.WIDTH(14)) dcsr_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(((enter_debug_halt_req_le | wr_dcsr_r) | internal_dbg_halt_mode) | take_nmi), + .din(dcsr_ns[15:2]), + .dout(dcsr[15:2]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1754:4 + localparam DPC = 12'h7b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1756:4 + assign wr_dpc_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DPC); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1757:4 + assign dpc_capture_npc = (dbg_tlu_halted & ~dbg_tlu_halted_f) & ~request_debug_mode_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1758:4 + assign dpc_capture_pc = request_debug_mode_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1760:4 + assign dpc_ns[31:1] = (({31 {(~dpc_capture_pc & ~dpc_capture_npc) & wr_dpc_r}} & dec_csr_wrdata_r[31:1]) | ({31 {dpc_capture_pc}} & pc_r[31:1])) | ({31 {~dpc_capture_pc & dpc_capture_npc}} & npc_r[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1764:4 + rvdffe #(.WIDTH(31)) dpc_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en((wr_dpc_r | dpc_capture_pc) | dpc_capture_npc), + .din(dpc_ns[31:1]), + .dout(dpc[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1775:4 + localparam DICAWICS = 12'h7c8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1777:4 + assign dicawics_ns[16:0] = {dec_csr_wrdata_r[24], dec_csr_wrdata_r[21:20], dec_csr_wrdata_r[16:3]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1778:4 + assign wr_dicawics_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAWICS); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1780:4 + rvdffe #(.WIDTH(17)) dicawics_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_dicawics_r), + .din(dicawics_ns[16:0]), + .dout(dicawics[16:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1794:4 + localparam DICAD0 = 12'h7c9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1796:4 + assign dicad0_ns[31:0] = (wr_dicad0_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1798:4 + assign wr_dicad0_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1800:4 + rvdffe #(.WIDTH(32)) dicad0_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_dicad0_r | ifu_ic_debug_rd_data_valid), + .din(dicad0_ns[31:0]), + .dout(dicad0[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1808:4 + localparam DICAD0H = 12'h7cc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1810:4 + assign dicad0h_ns[31:0] = (wr_dicad0h_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[63:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1812:4 + assign wr_dicad0h_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD0H); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1814:4 + rvdffe #(.WIDTH(32)) dicad0h_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_dicad0h_r | ifu_ic_debug_rd_data_valid), + .din(dicad0h_ns[31:0]), + .dout(dicad0h[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1817:1 + generate + if (pt[1125-:5] == 1) begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1821:4 + localparam DICAD1 = 12'h7ca; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1823:4 + assign dicad1_ns[6:0] = (wr_dicad1_r ? dec_csr_wrdata_r[6:0] : ifu_ic_debug_rd_data[70:64]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1825:4 + assign wr_dicad1_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1827:4 + rvdffe #( + .WIDTH(7), + .OVERRIDE(1) + ) dicad1_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), + .din(dicad1_ns[6:0]), + .dout(dicad1_raw[6:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1829:4 + assign dicad1[31:0] = {25'b0000000000000000000000000, dicad1_raw[6:0]}; + end + else begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1836:4 + localparam DICAD1 = 12'h7ca; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1838:4 + assign dicad1_ns[3:0] = (wr_dicad1_r ? dec_csr_wrdata_r[3:0] : ifu_ic_debug_rd_data[67:64]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1840:4 + assign wr_dicad1_r = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAD1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1842:4 + rvdffs #(.WIDTH(4)) dicad1_ff( + .rst_l(rst_l), + .clk(free_clk), + .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), + .din(dicad1_ns[3:0]), + .dout(dicad1_raw[3:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1844:4 + assign dicad1[31:0] = {28'b0000000000000000000000000000, dicad1_raw[3:0]}; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1849:4 + localparam DICAGO = 12'h7cb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1851:1 + generate + if (pt[1125-:5] == 1) begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1852:4 + assign dec_tlu_ic_diag_pkt[89:19] = {dicad1[6:0], dicad0h[31:0], dicad0[31:0]}; + end + else begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1854:4 + assign dec_tlu_ic_diag_pkt[89:19] = {3'b000, dicad1[3:0], dicad0h[31:0], dicad0[31:0]}; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1857:4 + assign dec_tlu_ic_diag_pkt[18:2] = dicawics[16:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1859:4 + assign icache_rd_valid = (((allow_dbg_halt_csr_write & dec_csr_any_unq_d) & dec_i0_decode_d) & ~dec_csr_wen_unq_d) & (dec_csr_rdaddr_d[11:0] == DICAGO); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1860:4 + assign icache_wr_valid = (allow_dbg_halt_csr_write & dec_csr_wen_r_mod) & (dec_csr_wraddr_r[11:0] == DICAGO); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1863:4 + assign dec_tlu_ic_diag_pkt[1] = icache_rd_valid_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1864:4 + assign dec_tlu_ic_diag_pkt[0] = icache_wr_valid_f; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1869:4 + localparam MTSEL = 12'h7a0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1871:4 + assign wr_mtsel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTSEL); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1872:4 + assign mtsel_ns[1:0] = (wr_mtsel_r ? {dec_csr_wrdata_r[1:0]} : mtsel[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1874:4 + rvdff #(.WIDTH(2)) mtsel_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .din(mtsel_ns[1:0]), + .dout(mtsel[1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1879:4 + localparam MTDATA1 = 12'h7a1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1911:4 + assign tdata_load = dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[19]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1913:4 + assign tdata_opcode = dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[19]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1915:4 + assign tdata_action = (dec_csr_wrdata_r[27] & dbg_tlu_halted_f) & dec_csr_wrdata_r[12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1918:4 + assign tdata_chain = (mtsel[0] ? 1'b0 : (mtsel[1] ? dec_csr_wrdata_r[11] & ~(mtdata1_t3[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]) : dec_csr_wrdata_r[11] & ~(mtdata1_t1[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1923:4 + assign tdata_kill_write = (mtsel[1] ? dec_csr_wrdata_r[27] & (~mtdata1_t2[MTDATA1_DMODE] & mtdata1_t2[MTDATA1_CHAIN]) : dec_csr_wrdata_r[27] & (~mtdata1_t0[MTDATA1_DMODE] & mtdata1_t0[MTDATA1_CHAIN])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1927:4 + assign tdata_wrdata_r[9:0] = {dec_csr_wrdata_r[27] & dbg_tlu_halted_f, dec_csr_wrdata_r[20:19], tdata_action, tdata_chain, dec_csr_wrdata_r[7:6], tdata_opcode, dec_csr_wrdata_r[1], tdata_load}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1937:4 + assign wr_mtdata1_t0_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b00)) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1938:4 + assign mtdata1_t0_ns[9:0] = (wr_mtdata1_t0_r ? tdata_wrdata_r[9:0] : {mtdata1_t0[9], update_hit_bit_r[0] | mtdata1_t0[8], mtdata1_t0[7:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1941:4 + assign wr_mtdata1_t1_r = (((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b01)) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f)) & ~tdata_kill_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1942:4 + assign mtdata1_t1_ns[9:0] = (wr_mtdata1_t1_r ? tdata_wrdata_r[9:0] : {mtdata1_t1[9], update_hit_bit_r[1] | mtdata1_t1[8], mtdata1_t1[7:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1945:4 + assign wr_mtdata1_t2_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b10)) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1946:4 + assign mtdata1_t2_ns[9:0] = (wr_mtdata1_t2_r ? tdata_wrdata_r[9:0] : {mtdata1_t2[9], update_hit_bit_r[2] | mtdata1_t2[8], mtdata1_t2[7:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1949:4 + assign wr_mtdata1_t3_r = (((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1)) & (mtsel[1:0] == 2'b11)) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f)) & ~tdata_kill_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1950:4 + assign mtdata1_t3_ns[9:0] = (wr_mtdata1_t3_r ? tdata_wrdata_r[9:0] : {mtdata1_t3[9], update_hit_bit_r[3] | mtdata1_t3[8], mtdata1_t3[7:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1954:4 + rvdffe #(.WIDTH(10)) mtdata1_t0_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(trigger_enabled[0] | wr_mtdata1_t0_r), + .din(mtdata1_t0_ns[9:0]), + .dout(mtdata1_t0[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1955:4 + rvdffe #(.WIDTH(10)) mtdata1_t1_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(trigger_enabled[1] | wr_mtdata1_t1_r), + .din(mtdata1_t1_ns[9:0]), + .dout(mtdata1_t1[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1956:4 + rvdffe #(.WIDTH(10)) mtdata1_t2_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(trigger_enabled[2] | wr_mtdata1_t2_r), + .din(mtdata1_t2_ns[9:0]), + .dout(mtdata1_t2[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1957:4 + rvdffe #(.WIDTH(10)) mtdata1_t3_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(trigger_enabled[3] | wr_mtdata1_t3_r), + .din(mtdata1_t3_ns[9:0]), + .dout(mtdata1_t3[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1959:4 + assign mtdata1_tsel_out[31:0] = ((({32 {mtsel[1:0] == 2'b00}} & {4'h2, mtdata1_t0[9], 6'b011111, mtdata1_t0[8:7], 6'b000000, mtdata1_t0[6:5], 3'b000, mtdata1_t0[4:3], 3'b000, mtdata1_t0[2:0]}) | ({32 {mtsel[1:0] == 2'b01}} & {4'h2, mtdata1_t1[9], 6'b011111, mtdata1_t1[8:7], 6'b000000, mtdata1_t1[6:5], 3'b000, mtdata1_t1[4:3], 3'b000, mtdata1_t1[2:0]})) | ({32 {mtsel[1:0] == 2'b10}} & {4'h2, mtdata1_t2[9], 6'b011111, mtdata1_t2[8:7], 6'b000000, mtdata1_t2[6:5], 3'b000, mtdata1_t2[4:3], 3'b000, mtdata1_t2[2:0]})) | ({32 {mtsel[1:0] == 2'b11}} & {4'h2, mtdata1_t3[9], 6'b011111, mtdata1_t3[8:7], 6'b000000, mtdata1_t3[6:5], 3'b000, mtdata1_t3[4:3], 3'b000, mtdata1_t3[2:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1964:4 + assign trigger_pkt_any[37] = mtdata1_t0[MTDATA1_SEL]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1965:4 + assign trigger_pkt_any[36] = mtdata1_t0[MTDATA1_MATCH]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1966:4 + assign trigger_pkt_any[35] = mtdata1_t0[MTDATA1_ST]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1967:4 + assign trigger_pkt_any[34] = mtdata1_t0[MTDATA1_LD]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1968:4 + assign trigger_pkt_any[33] = mtdata1_t0[MTDATA1_EXE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1969:4 + assign trigger_pkt_any[32] = mtdata1_t0[MTDATA1_M_ENABLED]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1971:4 + assign trigger_pkt_any[75] = mtdata1_t1[MTDATA1_SEL]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1972:4 + assign trigger_pkt_any[74] = mtdata1_t1[MTDATA1_MATCH]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1973:4 + assign trigger_pkt_any[73] = mtdata1_t1[MTDATA1_ST]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1974:4 + assign trigger_pkt_any[72] = mtdata1_t1[MTDATA1_LD]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1975:4 + assign trigger_pkt_any[71] = mtdata1_t1[MTDATA1_EXE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1976:4 + assign trigger_pkt_any[70] = mtdata1_t1[MTDATA1_M_ENABLED]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1978:4 + assign trigger_pkt_any[113] = mtdata1_t2[MTDATA1_SEL]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1979:4 + assign trigger_pkt_any[112] = mtdata1_t2[MTDATA1_MATCH]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1980:4 + assign trigger_pkt_any[111] = mtdata1_t2[MTDATA1_ST]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1981:4 + assign trigger_pkt_any[110] = mtdata1_t2[MTDATA1_LD]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1982:4 + assign trigger_pkt_any[109] = mtdata1_t2[MTDATA1_EXE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1983:4 + assign trigger_pkt_any[108] = mtdata1_t2[MTDATA1_M_ENABLED]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1985:4 + assign trigger_pkt_any[151] = mtdata1_t3[MTDATA1_SEL]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1986:4 + assign trigger_pkt_any[150] = mtdata1_t3[MTDATA1_MATCH]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1987:4 + assign trigger_pkt_any[149] = mtdata1_t3[MTDATA1_ST]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1988:4 + assign trigger_pkt_any[148] = mtdata1_t3[MTDATA1_LD]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1989:4 + assign trigger_pkt_any[147] = mtdata1_t3[MTDATA1_EXE]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1990:4 + assign trigger_pkt_any[146] = mtdata1_t3[MTDATA1_M_ENABLED]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:1999:4 + localparam MTDATA2 = 12'h7a2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2002:4 + assign wr_mtdata2_t0_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b00)) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2003:4 + assign wr_mtdata2_t1_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b01)) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2004:4 + assign wr_mtdata2_t2_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b10)) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2005:4 + assign wr_mtdata2_t3_r = ((dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2)) & (mtsel[1:0] == 2'b11)) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2007:4 + rvdffe #(.WIDTH(32)) mtdata2_t0_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mtdata2_t0_r), + .din(dec_csr_wrdata_r[31:0]), + .dout(mtdata2_t0[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2008:4 + rvdffe #(.WIDTH(32)) mtdata2_t1_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mtdata2_t1_r), + .din(dec_csr_wrdata_r[31:0]), + .dout(mtdata2_t1[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2009:4 + rvdffe #(.WIDTH(32)) mtdata2_t2_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mtdata2_t2_r), + .din(dec_csr_wrdata_r[31:0]), + .dout(mtdata2_t2[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2010:4 + rvdffe #(.WIDTH(32)) mtdata2_t3_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mtdata2_t3_r), + .din(dec_csr_wrdata_r[31:0]), + .dout(mtdata2_t3[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2012:4 + assign mtdata2_tsel_out[31:0] = ((({32 {mtsel[1:0] == 2'b00}} & mtdata2_t0[31:0]) | ({32 {mtsel[1:0] == 2'b01}} & mtdata2_t1[31:0])) | ({32 {mtsel[1:0] == 2'b10}} & mtdata2_t2[31:0])) | ({32 {mtsel[1:0] == 2'b11}} & mtdata2_t3[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2017:4 + assign trigger_pkt_any[31-:32] = mtdata2_t0[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2018:4 + assign trigger_pkt_any[69-:32] = mtdata2_t1[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2019:4 + assign trigger_pkt_any[107-:32] = mtdata2_t2[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2020:4 + assign trigger_pkt_any[145-:32] = mtdata2_t3[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2026:4 + localparam MHPME_NOEVENT = 10'd0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2027:4 + localparam MHPME_CLK_ACTIVE = 10'd1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2028:4 + localparam MHPME_ICACHE_HIT = 10'd2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2029:4 + localparam MHPME_ICACHE_MISS = 10'd3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2030:4 + localparam MHPME_INST_COMMIT = 10'd4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2031:4 + localparam MHPME_INST_COMMIT_16B = 10'd5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2032:4 + localparam MHPME_INST_COMMIT_32B = 10'd6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2033:4 + localparam MHPME_INST_ALIGNED = 10'd7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2034:4 + localparam MHPME_INST_DECODED = 10'd8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2035:4 + localparam MHPME_INST_MUL = 10'd9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2036:4 + localparam MHPME_INST_DIV = 10'd10; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2037:4 + localparam MHPME_INST_LOAD = 10'd11; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2038:4 + localparam MHPME_INST_STORE = 10'd12; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2039:4 + localparam MHPME_INST_MALOAD = 10'd13; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2040:4 + localparam MHPME_INST_MASTORE = 10'd14; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2041:4 + localparam MHPME_INST_ALU = 10'd15; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2042:4 + localparam MHPME_INST_CSRREAD = 10'd16; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2043:4 + localparam MHPME_INST_CSRRW = 10'd17; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2044:4 + localparam MHPME_INST_CSRWRITE = 10'd18; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2045:4 + localparam MHPME_INST_EBREAK = 10'd19; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2046:4 + localparam MHPME_INST_ECALL = 10'd20; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2047:4 + localparam MHPME_INST_FENCE = 10'd21; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2048:4 + localparam MHPME_INST_FENCEI = 10'd22; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2049:4 + localparam MHPME_INST_MRET = 10'd23; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2050:4 + localparam MHPME_INST_BRANCH = 10'd24; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2051:4 + localparam MHPME_BRANCH_MP = 10'd25; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2052:4 + localparam MHPME_BRANCH_TAKEN = 10'd26; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2053:4 + localparam MHPME_BRANCH_NOTP = 10'd27; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2054:4 + localparam MHPME_FETCH_STALL = 10'd28; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2055:4 + localparam MHPME_DECODE_STALL = 10'd30; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2056:4 + localparam MHPME_POSTSYNC_STALL = 10'd31; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2057:4 + localparam MHPME_PRESYNC_STALL = 10'd32; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2058:4 + localparam MHPME_LSU_SB_WB_STALL = 10'd34; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2059:4 + localparam MHPME_DMA_DCCM_STALL = 10'd35; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2060:4 + localparam MHPME_DMA_ICCM_STALL = 10'd36; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2061:4 + localparam MHPME_EXC_TAKEN = 10'd37; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2062:4 + localparam MHPME_TIMER_INT_TAKEN = 10'd38; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2063:4 + localparam MHPME_EXT_INT_TAKEN = 10'd39; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2064:4 + localparam MHPME_FLUSH_LOWER = 10'd40; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2065:4 + localparam MHPME_BR_ERROR = 10'd41; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2066:4 + localparam MHPME_IBUS_TRANS = 10'd42; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2067:4 + localparam MHPME_DBUS_TRANS = 10'd43; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2068:4 + localparam MHPME_DBUS_MA_TRANS = 10'd44; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2069:4 + localparam MHPME_IBUS_ERROR = 10'd45; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2070:4 + localparam MHPME_DBUS_ERROR = 10'd46; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2071:4 + localparam MHPME_IBUS_STALL = 10'd47; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2072:4 + localparam MHPME_DBUS_STALL = 10'd48; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2073:4 + localparam MHPME_INT_DISABLED = 10'd49; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2074:4 + localparam MHPME_INT_STALLED = 10'd50; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2075:4 + localparam MHPME_INST_BITMANIP = 10'd54; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2076:4 + localparam MHPME_DBUS_LOAD = 10'd55; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2077:4 + localparam MHPME_DBUS_STORE = 10'd56; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2079:4 + localparam MHPME_SLEEP_CYC = 10'd512; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2080:4 + localparam MHPME_DMA_READ_ALL = 10'd513; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2081:4 + localparam MHPME_DMA_WRITE_ALL = 10'd514; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2082:4 + localparam MHPME_DMA_READ_DCCM = 10'd515; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2083:4 + localparam MHPME_DMA_WRITE_DCCM = 10'd516; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2086:4 + assign mhpme_vec[9-:10] = mhpme3[9:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2087:4 + assign mhpme_vec[19-:10] = mhpme4[9:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2088:4 + assign mhpme_vec[29-:10] = mhpme5[9:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2089:4 + assign mhpme_vec[39-:10] = mhpme6[9:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2093:4 + assign pmu_i0_itype_qual[3:0] = dec_tlu_packet_r[3:0] & {4 {tlu_i0_commit_cmt}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2096:4 + genvar _gv_i_34; + generate + for (_gv_i_34 = 0; _gv_i_34 < 4; _gv_i_34 = _gv_i_34 + 1) begin : genblk6 + localparam i = _gv_i_34; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2097:7 + assign mhpmc_inc_r[i] = {~mcountinhibit[i + 3]} & ((((((((((((((((((((((((((((((((((((((((((((((((((((((((({mhpme_vec[(i * 10) + 9-:10] == MHPME_CLK_ACTIVE} & 1'b1) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_ICACHE_HIT} & {ifu_pmu_ic_hit})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_ICACHE_MISS} & {ifu_pmu_ic_miss})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_COMMIT} & {tlu_i0_commit_cmt & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_COMMIT_16B} & {(tlu_i0_commit_cmt & ~exu_pmu_i0_pc4) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_COMMIT_32B} & {(tlu_i0_commit_cmt & exu_pmu_i0_pc4) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_ALIGNED} & ifu_pmu_instr_aligned)) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_DECODED} & dec_pmu_instr_decoded)) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DECODE_STALL} & {dec_pmu_decode_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MUL} & {pmu_i0_itype_qual == 4'b0001})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_DIV} & {(dec_tlu_packet_r[6] & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_LOAD} & {pmu_i0_itype_qual == 4'b0010})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_STORE} & {pmu_i0_itype_qual == 4'b0011})) | (({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MALOAD} & {pmu_i0_itype_qual == 4'b0010}) & {dec_tlu_packet_r[4]})) | (({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MASTORE} & {pmu_i0_itype_qual == 4'b0011}) & {dec_tlu_packet_r[4]})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_ALU} & {pmu_i0_itype_qual == 4'b0100})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_CSRREAD} & {pmu_i0_itype_qual == 4'b0101})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_CSRWRITE} & {pmu_i0_itype_qual == 4'b0110})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_CSRRW} & {pmu_i0_itype_qual == 4'b0111})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_EBREAK} & {pmu_i0_itype_qual == 4'b1000})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_ECALL} & {pmu_i0_itype_qual == 4'b1001})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_FENCE} & {pmu_i0_itype_qual == 4'b1010})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_FENCEI} & {pmu_i0_itype_qual == 4'b1011})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_MRET} & {pmu_i0_itype_qual == 4'b1100})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_BRANCH} & {(pmu_i0_itype_qual == 4'b1101) | (pmu_i0_itype_qual == 4'b1110)})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BRANCH_MP} & {(exu_pmu_i0_br_misp & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BRANCH_TAKEN} & {(exu_pmu_i0_br_ataken & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BRANCH_NOTP} & {(dec_tlu_packet_r[7] & tlu_i0_commit_cmt) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_FETCH_STALL} & {ifu_pmu_fetch_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DECODE_STALL} & {dec_pmu_decode_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_POSTSYNC_STALL} & {dec_pmu_postsync_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_PRESYNC_STALL} & {dec_pmu_presync_stall})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_LSU_SB_WB_STALL} & {lsu_store_stall_any})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_DCCM_STALL} & {dma_dccm_stall_any})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_ICCM_STALL} & {dma_iccm_stall_any})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_EXC_TAKEN} & {(i0_exception_valid_r | i0_trigger_hit_r) | lsu_exc_valid_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_TIMER_INT_TAKEN} & {(take_timer_int | take_int_timer0_int) | take_int_timer1_int})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_EXT_INT_TAKEN} & {take_ext_int})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_FLUSH_LOWER} & {tlu_flush_lower_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_BR_ERROR} & {(dec_tlu_br0_error_r | dec_tlu_br0_start_error_r) & rfpc_i0_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_IBUS_TRANS} & {ifu_pmu_bus_trxn})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_TRANS} & {lsu_pmu_bus_trxn})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_MA_TRANS} & {lsu_pmu_bus_misaligned})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_IBUS_ERROR} & {ifu_pmu_bus_error})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_ERROR} & {lsu_pmu_bus_error})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_IBUS_STALL} & {ifu_pmu_bus_busy})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_STALL} & {lsu_pmu_bus_busy})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INT_DISABLED} & {~mstatus[MSTATUS_MIE]})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INT_STALLED} & {~mstatus[MSTATUS_MIE] & |(mip[5:0] & mie[5:0])})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_INST_BITMANIP} & {pmu_i0_itype_qual == 4'b1111})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_LOAD} & {(tlu_i0_commit_cmt & lsu_pmu_load_external_r) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DBUS_STORE} & {(tlu_i0_commit_cmt & lsu_pmu_store_external_r) & ~illegal_r})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_SLEEP_CYC} & {dec_tlu_pmu_fw_halted})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_READ_ALL} & {dma_pmu_any_read})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_WRITE_ALL} & {dma_pmu_any_write})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_READ_DCCM} & {dma_pmu_dccm_read})) | ({mhpme_vec[(i * 10) + 9-:10] == MHPME_DMA_WRITE_DCCM} & {dma_pmu_dccm_write})); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2164:4 + generate + if (pt[1227-:5]) begin : genblk7 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2165:4 + rvdffie #(.WIDTH(31)) mstatus_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze, mip_ns[5:0], (mcyclel_cout & ~wr_mcycleh_r) & mcyclel_cout_in, minstret_enable, minstretl_cout_ns, fw_halted_ns, meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, mstatus_ns[1:0]}), + .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1, mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, mstatus[1:0]}) + ); + end + else begin : genblk7 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2180:4 + rvdffie #(.WIDTH(27)) mstatus_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, mip_ns[5:0], (mcyclel_cout & ~wr_mcycleh_r) & mcyclel_cout_in, minstret_enable, minstretl_cout_ns, fw_halted_ns, meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, mstatus_ns[1:0]}), + .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, mstatus[1:0]}) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2192:4 + assign perfcnt_halted = (dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2193:4 + assign perfcnt_during_sleep[3:0] = {4 {~(dec_tlu_dbg_halted & dcsr[DCSR_STOPC])}} & {mhpme_vec[39], mhpme_vec[29], mhpme_vec[19], mhpme_vec[9]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2195:4 + assign dec_tlu_perfcnt0 = mhpmc_inc_r_d1[0] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2196:4 + assign dec_tlu_perfcnt1 = mhpmc_inc_r_d1[1] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2197:4 + assign dec_tlu_perfcnt2 = mhpmc_inc_r_d1[2] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2198:4 + assign dec_tlu_perfcnt3 = mhpmc_inc_r_d1[3] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2203:4 + localparam MHPMC3 = 12'hb03; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2204:4 + localparam MHPMC3H = 12'hb83; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2206:4 + assign mhpmc3_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2207:4 + assign mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[0]) & |mhpmc_inc_r[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2208:4 + assign mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2209:4 + assign mhpmc3_incr[63:0] = {mhpmc3h[31:0], mhpmc3[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2210:4 + assign mhpmc3_ns[31:0] = (mhpmc3_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2211:4 + rvdffe #(.WIDTH(32)) mhpmc3_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc3_wr_en), + .din(mhpmc3_ns[31:0]), + .dout(mhpmc3[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2213:4 + assign mhpmc3h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3H); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2214:4 + assign mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2215:4 + assign mhpmc3h_ns[31:0] = (mhpmc3h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[63:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2216:4 + rvdffe #(.WIDTH(32)) mhpmc3h_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc3h_wr_en), + .din(mhpmc3h_ns[31:0]), + .dout(mhpmc3h[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2221:4 + localparam MHPMC4 = 12'hb04; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2222:4 + localparam MHPMC4H = 12'hb84; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2224:4 + assign mhpmc4_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2225:4 + assign mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[1]) & |mhpmc_inc_r[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2226:4 + assign mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2227:4 + assign mhpmc4_incr[63:0] = {mhpmc4h[31:0], mhpmc4[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2228:4 + assign mhpmc4_ns[31:0] = (mhpmc4_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2229:4 + rvdffe #(.WIDTH(32)) mhpmc4_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc4_wr_en), + .din(mhpmc4_ns[31:0]), + .dout(mhpmc4[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2231:4 + assign mhpmc4h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4H); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2232:4 + assign mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2233:4 + assign mhpmc4h_ns[31:0] = (mhpmc4h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[63:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2234:4 + rvdffe #(.WIDTH(32)) mhpmc4h_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc4h_wr_en), + .din(mhpmc4h_ns[31:0]), + .dout(mhpmc4h[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2239:4 + localparam MHPMC5 = 12'hb05; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2240:4 + localparam MHPMC5H = 12'hb85; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2242:4 + assign mhpmc5_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2243:4 + assign mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[2]) & |mhpmc_inc_r[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2244:4 + assign mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2245:4 + assign mhpmc5_incr[63:0] = {mhpmc5h[31:0], mhpmc5[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2246:4 + assign mhpmc5_ns[31:0] = (mhpmc5_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2247:4 + rvdffe #(.WIDTH(32)) mhpmc5_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc5_wr_en), + .din(mhpmc5_ns[31:0]), + .dout(mhpmc5[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2249:4 + assign mhpmc5h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5H); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2250:4 + assign mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2251:4 + assign mhpmc5h_ns[31:0] = (mhpmc5h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[63:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2252:4 + rvdffe #(.WIDTH(32)) mhpmc5h_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc5h_wr_en), + .din(mhpmc5h_ns[31:0]), + .dout(mhpmc5h[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2257:4 + localparam MHPMC6 = 12'hb06; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2258:4 + localparam MHPMC6H = 12'hb86; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2260:4 + assign mhpmc6_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2261:4 + assign mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[3]) & |mhpmc_inc_r[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2262:4 + assign mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2263:4 + assign mhpmc6_incr[63:0] = {mhpmc6h[31:0], mhpmc6[31:0]} + 64'b0000000000000000000000000000000000000000000000000000000000000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2264:4 + assign mhpmc6_ns[31:0] = (mhpmc6_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2265:4 + rvdffe #(.WIDTH(32)) mhpmc6_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc6_wr_en), + .din(mhpmc6_ns[31:0]), + .dout(mhpmc6[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2267:4 + assign mhpmc6h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6H); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2268:4 + assign mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2269:4 + assign mhpmc6h_ns[31:0] = (mhpmc6h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[63:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2270:4 + rvdffe #(.WIDTH(32)) mhpmc6h_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en(mhpmc6h_wr_en), + .din(mhpmc6h_ns[31:0]), + .dout(mhpmc6h[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2275:4 + localparam MHPME3 = 12'h323; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2278:4 + assign zero_event_r = (((((dec_csr_wrdata_r[9:0] > 10'd516) | (|dec_csr_wrdata_r[31:10])) | ((dec_csr_wrdata_r[9:0] < 10'd512) & (dec_csr_wrdata_r[9:0] > 10'd56))) | ((dec_csr_wrdata_r[9:0] < 10'd54) & (dec_csr_wrdata_r[9:0] > 10'd50))) | (dec_csr_wrdata_r[9:0] == 10'd29)) | (dec_csr_wrdata_r[9:0] == 10'd33); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2286:4 + assign event_r[9:0] = (zero_event_r ? {10 {1'sb0}} : dec_csr_wrdata_r[9:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2288:4 + assign wr_mhpme3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME3); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2289:4 + rvdffe #(.WIDTH(10)) mhpme3_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mhpme3_r), + .din(event_r[9:0]), + .dout(mhpme3[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2293:4 + localparam MHPME4 = 12'h324; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2295:4 + assign wr_mhpme4_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME4); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2296:4 + rvdffe #(.WIDTH(10)) mhpme4_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mhpme4_r), + .din(event_r[9:0]), + .dout(mhpme4[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2300:4 + localparam MHPME5 = 12'h325; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2302:4 + assign wr_mhpme5_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME5); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2303:4 + rvdffe #(.WIDTH(10)) mhpme5_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mhpme5_r), + .din(event_r[9:0]), + .dout(mhpme5[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2307:4 + localparam MHPME6 = 12'h326; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2309:4 + assign wr_mhpme6_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME6); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2310:4 + rvdffe #(.WIDTH(10)) mhpme6_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mhpme6_r), + .din(event_r[9:0]), + .dout(mhpme6[9:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2327:4 + localparam MCOUNTINHIBIT = 12'h320; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2329:4 + assign wr_mcountinhibit_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTINHIBIT); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2330:4 + rvdffs #(.WIDTH(6)) mcountinhibit_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .en(wr_mcountinhibit_r), + .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), + .dout({mcountinhibit[6:2], mcountinhibit[0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2331:4 + assign mcountinhibit[1] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2336:4 + wire [4:0] dec_tlu_exc_cause_wb1_raw; + wire [4:0] dec_tlu_exc_cause_wb2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2337:4 + wire dec_tlu_int_valid_wb1_raw; + wire dec_tlu_int_valid_wb2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2339:4 + assign {dec_tlu_i0_valid_wb1, dec_tlu_i0_exc_valid_wb1, dec_tlu_exc_cause_wb1_raw[4:0], dec_tlu_int_valid_wb1_raw} = {8 {~dec_tlu_trace_disable}} & {i0_valid_wb, (i0_exception_valid_r_d1 | lsu_i0_exc_r_d1) | (trigger_hit_r_d1 & ~trigger_hit_dmode_r_d1), exc_cause_wb[4:0], interrupt_valid_r_d1}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2350:4 + rvdffie #( + .WIDTH(6), + .OVERRIDE(1) + ) traceskidff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .din({dec_tlu_exc_cause_wb1_raw[4:0], dec_tlu_int_valid_wb1_raw}), + .dout({dec_tlu_exc_cause_wb2[4:0], dec_tlu_int_valid_wb2}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2356:4 + assign dec_tlu_exc_cause_wb1[4:0] = (dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2[4:0] : dec_tlu_exc_cause_wb1_raw[4:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2357:4 + assign dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2359:4 + assign dec_tlu_mtval_wb1 = mtval[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2385:1 + assign csr_misa = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2388:1 + assign csr_mvendorid = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2391:1 + assign csr_marchid = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2394:1 + assign csr_mimpid = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2397:1 + assign csr_mhartid = (dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2400:1 + assign csr_mstatus = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2403:1 + assign csr_mtvec = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2406:1 + assign csr_mip = (!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2408:1 + assign csr_mie = (((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2411:1 + assign csr_mcyclel = ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2415:1 + assign csr_mcycleh = (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2419:1 + assign csr_minstretl = (((((!dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2423:1 + assign csr_minstreth = (((((!dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2427:1 + assign csr_mscratch = (((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2430:1 + assign csr_mepc = ((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2433:1 + assign csr_mcause = ((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2436:1 + assign csr_mscause = (dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2439:1 + assign csr_mtval = ((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2442:1 + assign csr_mrac = ((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2445:1 + assign csr_dmst = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2448:1 + assign csr_mdseac = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2451:1 + assign csr_meihap = (dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2454:1 + assign csr_meivt = ((((!dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2458:1 + assign csr_meipt = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2461:1 + assign csr_meicurpl = (dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2464:1 + assign csr_meicidpl = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2467:1 + assign csr_dcsr = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2470:1 + assign csr_mcgc = ((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2473:1 + assign csr_mfdc = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2476:1 + assign csr_dpc = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2479:1 + assign csr_mtsel = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2482:1 + assign csr_mtdata1 = ((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2485:1 + assign csr_mtdata2 = ((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2488:1 + assign csr_mhpmc3 = ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2492:1 + assign csr_mhpmc4 = (((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2496:1 + assign csr_mhpmc5 = ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2500:1 + assign csr_mhpmc6 = (((((!dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2504:1 + assign csr_mhpmc3h = ((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2508:1 + assign csr_mhpmc4h = (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2512:1 + assign csr_mhpmc5h = ((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2516:1 + assign csr_mhpmc6h = (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2520:1 + assign csr_mhpme3 = ((((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2524:1 + assign csr_mhpme4 = ((((dec_csr_rdaddr_d[5] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2528:1 + assign csr_mhpme5 = ((((dec_csr_rdaddr_d[5] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2532:1 + assign csr_mhpme6 = ((((dec_csr_rdaddr_d[5] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2536:1 + assign csr_mcountinhibit = ((((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2540:1 + assign csr_mitctl0 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2543:1 + assign csr_mitctl1 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2546:1 + assign csr_mitb0 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2549:1 + assign csr_mitb1 = (((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2552:1 + assign csr_mitcnt0 = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2555:1 + assign csr_mitcnt1 = ((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2558:1 + assign csr_mpmc = (((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2561:1 + assign csr_meicpct = ((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2564:1 + assign csr_micect = (((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2567:1 + assign csr_miccmect = ((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2570:1 + assign csr_mdccmect = ((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2573:1 + assign csr_mfdht = (((dec_csr_rdaddr_d[6] & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2576:1 + assign csr_mfdhs = ((dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2579:1 + assign csr_dicawics = ((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2583:1 + assign csr_dicad0h = ((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2586:1 + assign csr_dicad0 = (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2589:1 + assign csr_dicad1 = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2592:1 + assign csr_dicago = (((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2595:1 + assign presync = (((((((((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]) | (((((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0])) | (((((dec_csr_rdaddr_d[5] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0])) | (((((!dec_csr_rdaddr_d[6] & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1])) | ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | ((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1])) | (((((dec_csr_rdaddr_d[7] & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2609:1 + assign postsync = (((((((((dec_csr_rdaddr_d[10] & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0]) | ((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0])) | (((!dec_csr_rdaddr_d[7] & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0])) | (((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[0])) | ((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0])) | (((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1])) | ((((dec_csr_rdaddr_d[10] & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2622:1 + assign legal = (((((((((((((((((((((((((((((((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0]) | (((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1])) | ((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | (((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[0])) | (((((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1])) | (((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1])) | (((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2])) | ((((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[1])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[2])) | (((((((((dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & dec_csr_rdaddr_d[1])) | ((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[1]) & dec_csr_rdaddr_d[0])) | ((((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2])) | (((((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[2])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & dec_csr_rdaddr_d[1])) | ((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[0])) | (((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2])) | ((((((((((!dec_csr_rdaddr_d[11] & dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2]) & !dec_csr_rdaddr_d[0])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[1])) | (((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[2])) | (((((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[5]) & !dec_csr_rdaddr_d[4]) & !dec_csr_rdaddr_d[3]) & !dec_csr_rdaddr_d[1]) & !dec_csr_rdaddr_d[0])) | (((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[3])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[3])) | (((((((!dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[7]) & !dec_csr_rdaddr_d[6]) & dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4])) | ((((((dec_csr_rdaddr_d[11] & !dec_csr_rdaddr_d[10]) & dec_csr_rdaddr_d[9]) & dec_csr_rdaddr_d[8]) & !dec_csr_rdaddr_d[6]) & !dec_csr_rdaddr_d[5]) & dec_csr_rdaddr_d[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2715:1 + assign dec_tlu_presync_d = (presync & dec_csr_any_unq_d) & ~dec_csr_wen_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2716:1 + assign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2719:1 + assign conditionally_illegal = (((((csr_mitcnt0 | csr_mitcnt1) | csr_mitb0) | csr_mitb1) | csr_mitctl0) | csr_mitctl1) & !pt[4-:5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2721:1 + assign valid_csr = ((legal & (~(((((((csr_dcsr | csr_dpc) | csr_dmst) | csr_dicawics) | csr_dicad0) | csr_dicad0h) | csr_dicad1) | csr_dicago) | dbg_tlu_halted_f)) & ~fast_int_meicpct) & ~conditionally_illegal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2724:1 + assign dec_csr_legal_d = (dec_csr_any_unq_d & valid_csr) & ~(dec_csr_wen_unq_d & (((((csr_mvendorid | csr_marchid) | csr_mimpid) | csr_mhartid) | csr_mdseac) | csr_meihap)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2729:1 + assign dec_csr_rddata_d[31:0] = ((((((((((((((((((((((((((((((((((((((((((((((((((((((({32 {csr_misa}} & 32'h40001104) | ({32 {csr_mvendorid}} & 32'h00000045)) | ({32 {csr_marchid}} & 32'h00000010)) | ({32 {csr_mimpid}} & 32'h00000004)) | ({32 {csr_mhartid}} & {core_id[31:4], 4'b0000})) | ({32 {csr_mstatus}} & {24'b000000000000000000011000, mstatus[1], 3'b000, mstatus[0], 3'b000})) | ({32 {csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]})) | ({32 {csr_mip}} & {1'b0, mip[5:3], 16'b0000000000000000, mip[2], 3'b000, mip[1], 3'b000, mip[0], 3'b000})) | ({32 {csr_mie}} & {1'b0, mie[5:3], 16'b0000000000000000, mie[2], 3'b000, mie[1], 3'b000, mie[0], 3'b000})) | ({32 {csr_mcyclel}} & mcyclel[31:0])) | ({32 {csr_mcycleh}} & mcycleh_inc[31:0])) | ({32 {csr_minstretl}} & minstretl_read[31:0])) | ({32 {csr_minstreth}} & minstreth_read[31:0])) | ({32 {csr_mscratch}} & mscratch[31:0])) | ({32 {csr_mepc}} & {mepc[31:1], 1'b0})) | ({32 {csr_mcause}} & mcause[31:0])) | ({32 {csr_mscause}} & {28'b0000000000000000000000000000, mscause[3:0]})) | ({32 {csr_mtval}} & mtval[31:0])) | ({32 {csr_mrac}} & mrac[31:0])) | ({32 {csr_mdseac}} & mdseac[31:0])) | ({32 {csr_meivt}} & {meivt[31:10], 10'b0000000000})) | ({32 {csr_meihap}} & {meivt[31:10], meihap[9:2], 2'b00})) | ({32 {csr_meicurpl}} & {28'b0000000000000000000000000000, meicurpl[3:0]})) | ({32 {csr_meicidpl}} & {28'b0000000000000000000000000000, meicidpl[3:0]})) | ({32 {csr_meipt}} & {28'b0000000000000000000000000000, meipt[3:0]})) | ({32 {csr_mcgc}} & {22'b0000000000000000000000, mcgc[9:0]})) | ({32 {csr_mfdc}} & {13'b0000000000000, mfdc[18:0]})) | ({32 {csr_dcsr}} & {16'h4000, dcsr[15:2], 2'b11})) | ({32 {csr_dpc}} & {dpc[31:1], 1'b0})) | ({32 {csr_dicad0}} & dicad0[31:0])) | ({32 {csr_dicad0h}} & dicad0h[31:0])) | ({32 {csr_dicad1}} & dicad1[31:0])) | ({32 {csr_dicawics}} & {7'b0000000, dicawics[16], 2'b00, dicawics[15:14], 3'b000, dicawics[13:0], 3'b000})) | ({32 {csr_mtsel}} & {30'b000000000000000000000000000000, mtsel[1:0]})) | ({32 {csr_mtdata1}} & {mtdata1_tsel_out[31:0]})) | ({32 {csr_mtdata2}} & {mtdata2_tsel_out[31:0]})) | ({32 {csr_micect}} & {micect[31:0]})) | ({32 {csr_miccmect}} & {miccmect[31:0]})) | ({32 {csr_mdccmect}} & {mdccmect[31:0]})) | ({32 {csr_mhpmc3}} & mhpmc3[31:0])) | ({32 {csr_mhpmc4}} & mhpmc4[31:0])) | ({32 {csr_mhpmc5}} & mhpmc5[31:0])) | ({32 {csr_mhpmc6}} & mhpmc6[31:0])) | ({32 {csr_mhpmc3h}} & mhpmc3h[31:0])) | ({32 {csr_mhpmc4h}} & mhpmc4h[31:0])) | ({32 {csr_mhpmc5h}} & mhpmc5h[31:0])) | ({32 {csr_mhpmc6h}} & mhpmc6h[31:0])) | ({32 {csr_mfdht}} & {26'b00000000000000000000000000, mfdht[5:0]})) | ({32 {csr_mfdhs}} & {30'b000000000000000000000000000000, mfdhs[1:0]})) | ({32 {csr_mhpme3}} & {22'b0000000000000000000000, mhpme3[9:0]})) | ({32 {csr_mhpme4}} & {22'b0000000000000000000000, mhpme4[9:0]})) | ({32 {csr_mhpme5}} & {22'b0000000000000000000000, mhpme5[9:0]})) | ({32 {csr_mhpme6}} & {22'b0000000000000000000000, mhpme6[9:0]})) | ({32 {csr_mcountinhibit}} & {25'b0000000000000000000000000, mcountinhibit[6:0]})) | ({32 {csr_mpmc}} & {30'b000000000000000000000000000000, mpmc[1], 1'b0})) | ({32 {dec_timer_read_d}} & dec_timer_rddata_d[31:0]); +endmodule +module el2_dec_timer_ctl ( + clk, + free_l2clk, + csr_wr_clk, + rst_l, + dec_csr_wen_r_mod, + dec_csr_wraddr_r, + dec_csr_wrdata_r, + csr_mitctl0, + csr_mitctl1, + csr_mitb0, + csr_mitb1, + csr_mitcnt0, + csr_mitcnt1, + dec_pause_state, + dec_tlu_pmu_fw_halted, + internal_dbg_halt_timers, + dec_timer_rddata_d, + dec_timer_read_d, + dec_timer_t0_pulse, + dec_timer_t1_pulse, + scan_mode +); + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2795:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2796:4 + input wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2797:4 + input wire csr_wr_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2798:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2799:4 + input wire dec_csr_wen_r_mod; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2800:4 + input wire [11:0] dec_csr_wraddr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2801:4 + input wire [31:0] dec_csr_wrdata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2803:4 + input wire csr_mitctl0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2804:4 + input wire csr_mitctl1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2805:4 + input wire csr_mitb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2806:4 + input wire csr_mitb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2807:4 + input wire csr_mitcnt0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2808:4 + input wire csr_mitcnt1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2811:4 + input wire dec_pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2812:4 + input wire dec_tlu_pmu_fw_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2813:4 + input wire internal_dbg_halt_timers; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2815:4 + output wire [31:0] dec_timer_rddata_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2816:4 + output wire dec_timer_read_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2817:4 + output wire dec_timer_t0_pulse; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2818:4 + output wire dec_timer_t1_pulse; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2820:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2822:4 + localparam MITCTL_ENABLE = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2823:4 + localparam MITCTL_ENABLE_HALTED = 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2824:4 + localparam MITCTL_ENABLE_PAUSED = 2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2826:4 + wire [31:0] mitcnt0_ns; + wire [31:0] mitcnt0; + wire [31:0] mitcnt1_ns; + wire [31:0] mitcnt1; + wire [31:0] mitb0; + wire [31:0] mitb1; + wire [31:0] mitb0_b; + wire [31:0] mitb1_b; + wire [31:0] mitcnt0_inc; + wire [31:0] mitcnt1_inc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2827:4 + wire [2:0] mitctl0_ns; + wire [2:0] mitctl0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2828:4 + wire [3:0] mitctl1_ns; + wire [3:0] mitctl1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2829:4 + wire wr_mitcnt0_r; + wire wr_mitcnt1_r; + wire wr_mitb0_r; + wire wr_mitb1_r; + wire wr_mitctl0_r; + wire wr_mitctl1_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2830:4 + wire mitcnt0_inc_ok; + wire mitcnt1_inc_ok; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2831:4 + wire mitcnt0_inc_cout; + wire mitcnt1_inc_cout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2832:2 + wire mit0_match_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2833:2 + wire mit1_match_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2834:2 + wire mitctl0_0_b_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2835:2 + wire mitctl0_0_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2836:2 + wire mitctl1_0_b_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2837:2 + wire mitctl1_0_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2839:4 + assign mit0_match_ns = mitcnt0[31:0] >= mitb0[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2840:4 + assign mit1_match_ns = mitcnt1[31:0] >= mitb1[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2842:4 + assign dec_timer_t0_pulse = mit0_match_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2843:4 + assign dec_timer_t1_pulse = mit1_match_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2848:4 + localparam MITCNT0 = 12'h7d2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2850:4 + assign wr_mitcnt0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2852:4 + assign mitcnt0_inc_ok = ((mitctl0[MITCTL_ENABLE] & (~dec_pause_state | mitctl0[MITCTL_ENABLE_PAUSED])) & (~dec_tlu_pmu_fw_halted | mitctl0[MITCTL_ENABLE_HALTED])) & ~internal_dbg_halt_timers; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2854:4 + assign {mitcnt0_inc_cout, mitcnt0_inc[7:0]} = mitcnt0[7:0] + 8'b00000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2855:4 + assign mitcnt0_inc[31:8] = mitcnt0[31:8] + {23'b00000000000000000000000, mitcnt0_inc_cout}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2857:4 + assign mitcnt0_ns[31:0] = (wr_mitcnt0_r ? dec_csr_wrdata_r[31:0] : (mit0_match_ns ? 'b0 : mitcnt0_inc[31:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2859:4 + rvdffe #(.WIDTH(24)) mitcnt0_ffb( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en((wr_mitcnt0_r | (mitcnt0_inc_ok & mitcnt0_inc_cout)) | mit0_match_ns), + .din(mitcnt0_ns[31:8]), + .dout(mitcnt0[31:8]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2860:4 + rvdffe #(.WIDTH(8)) mitcnt0_ffa( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en((wr_mitcnt0_r | mitcnt0_inc_ok) | mit0_match_ns), + .din(mitcnt0_ns[7:0]), + .dout(mitcnt0[7:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2866:4 + localparam MITCNT1 = 12'h7d5; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2868:4 + assign wr_mitcnt1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2870:4 + assign mitcnt1_inc_ok = (((mitctl1[MITCTL_ENABLE] & (~dec_pause_state | mitctl1[MITCTL_ENABLE_PAUSED])) & (~dec_tlu_pmu_fw_halted | mitctl1[MITCTL_ENABLE_HALTED])) & ~internal_dbg_halt_timers) & (~mitctl1[3] | mit0_match_ns); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2877:4 + assign {mitcnt1_inc_cout, mitcnt1_inc[7:0]} = mitcnt1[7:0] + 8'b00000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2878:4 + assign mitcnt1_inc[31:8] = mitcnt1[31:8] + {23'b00000000000000000000000, mitcnt1_inc_cout}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2880:4 + assign mitcnt1_ns[31:0] = (wr_mitcnt1_r ? dec_csr_wrdata_r[31:0] : (mit1_match_ns ? 'b0 : mitcnt1_inc[31:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2882:4 + rvdffe #(.WIDTH(24)) mitcnt1_ffb( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en((wr_mitcnt1_r | (mitcnt1_inc_ok & mitcnt1_inc_cout)) | mit1_match_ns), + .din(mitcnt1_ns[31:8]), + .dout(mitcnt1[31:8]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2883:4 + rvdffe #(.WIDTH(8)) mitcnt1_ffa( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(free_l2clk), + .en((wr_mitcnt1_r | mitcnt1_inc_ok) | mit1_match_ns), + .din(mitcnt1_ns[7:0]), + .dout(mitcnt1[7:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2890:4 + localparam MITB0 = 12'h7d3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2892:4 + assign wr_mitb0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2894:4 + rvdffe #(.WIDTH(32)) mitb0_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mitb0_r), + .din(~dec_csr_wrdata_r[31:0]), + .dout(mitb0_b[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2895:4 + assign mitb0[31:0] = ~mitb0_b[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2901:4 + localparam MITB1 = 12'h7d6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2903:4 + assign wr_mitb1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2905:4 + rvdffe #(.WIDTH(32)) mitb1_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .en(wr_mitb1_r), + .din(~dec_csr_wrdata_r[31:0]), + .dout(mitb1_b[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2906:4 + assign mitb1[31:0] = ~mitb1_b[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2915:4 + localparam MITCTL0 = 12'h7d4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2917:4 + assign wr_mitctl0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2918:4 + assign mitctl0_ns[2:0] = (wr_mitctl0_r ? {dec_csr_wrdata_r[2:0]} : {mitctl0[2:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2920:4 + assign mitctl0_0_b_ns = ~mitctl0_ns[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2921:4 + rvdffs #(.WIDTH(3)) mitctl0_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .en(wr_mitctl0_r), + .din({mitctl0_ns[2:1], mitctl0_0_b_ns}), + .dout({mitctl0[2:1], mitctl0_0_b}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2922:4 + assign mitctl0[0] = ~mitctl0_0_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2932:4 + localparam MITCTL1 = 12'h7d7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2934:4 + assign wr_mitctl1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2935:4 + assign mitctl1_ns[3:0] = (wr_mitctl1_r ? {dec_csr_wrdata_r[3:0]} : {mitctl1[3:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2937:4 + assign mitctl1_0_b_ns = ~mitctl1_ns[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2938:4 + rvdffs #(.WIDTH(4)) mitctl1_ff( + .rst_l(rst_l), + .clk(csr_wr_clk), + .en(wr_mitctl1_r), + .din({mitctl1_ns[3:1], mitctl1_0_b_ns}), + .dout({mitctl1[3:1], mitctl1_0_b}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2939:4 + assign mitctl1[0] = ~mitctl1_0_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2940:4 + assign dec_timer_read_d = ((((csr_mitcnt1 | csr_mitcnt0) | csr_mitb1) | csr_mitb0) | csr_mitctl0) | csr_mitctl1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv:2941:4 + assign dec_timer_rddata_d[31:0] = ((((({32 {csr_mitcnt0}} & mitcnt0[31:0]) | ({32 {csr_mitcnt1}} & mitcnt1[31:0])) | ({32 {csr_mitb0}} & mitb0[31:0])) | ({32 {csr_mitb1}} & mitb1[31:0])) | ({32 {csr_mitctl0}} & {29'b00000000000000000000000000000, mitctl0[2:0]})) | ({32 {csr_mitctl1}} & {28'b0000000000000000000000000000, mitctl1[3:0]}); +endmodule +module el2_dec_trigger ( + trigger_pkt_any, + dec_i0_pc_d, + dec_i0_trigger_match_d +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:31:4 + // removed localparam type el2_pkg_el2_trigger_pkt_t + input wire [151:0] trigger_pkt_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:32:4 + input wire [31:1] dec_i0_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:34:4 + output wire [3:0] dec_i0_trigger_match_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:37:4 + wire [127:0] dec_i0_match_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:38:4 + wire [3:0] dec_i0_trigger_data_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:40:4 + genvar _gv_i_35; + generate + for (_gv_i_35 = 0; _gv_i_35 < 4; _gv_i_35 = _gv_i_35 + 1) begin : genblk1 + localparam i = _gv_i_35; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:41:7 + assign dec_i0_match_data[(i * 32) + 31-:32] = {32 {~trigger_pkt_any[(i * 38) + 37] & trigger_pkt_any[(i * 38) + 33]}} & {dec_i0_pc_d[31:1], trigger_pkt_any[i * 38]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:43:7 + rvmaskandmatch trigger_i0_match( + .mask(trigger_pkt_any[(i * 38) + 31-:32]), + .data(dec_i0_match_data[(i * 32) + 31-:32]), + .masken(trigger_pkt_any[(i * 38) + 36]), + .match(dec_i0_trigger_data_match[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv:45:7 + assign dec_i0_trigger_match_d[i] = (trigger_pkt_any[(i * 38) + 33] & trigger_pkt_any[(i * 38) + 32]) & dec_i0_trigger_data_match[i]; + end + endgenerate +endmodule +module el2_dec ( + clk, + active_clk, + free_clk, + free_l2clk, + lsu_fastint_stall_any, + dec_extint_stall, + dec_i0_decode_d, + dec_pause_state_cg, + dec_tlu_core_empty, + rst_l, + rst_vec, + nmi_int, + nmi_vec, + i_cpu_halt_req, + i_cpu_run_req, + o_cpu_halt_status, + o_cpu_halt_ack, + o_cpu_run_ack, + o_debug_mode_status, + core_id, + mpc_debug_halt_req, + mpc_debug_run_req, + mpc_reset_run_req, + mpc_debug_halt_ack, + mpc_debug_run_ack, + debug_brkpt_status, + exu_pmu_i0_br_misp, + exu_pmu_i0_br_ataken, + exu_pmu_i0_pc4, + lsu_nonblock_load_valid_m, + lsu_nonblock_load_tag_m, + lsu_nonblock_load_inv_r, + lsu_nonblock_load_inv_tag_r, + lsu_nonblock_load_data_valid, + lsu_nonblock_load_data_error, + lsu_nonblock_load_data_tag, + lsu_nonblock_load_data, + lsu_pmu_bus_trxn, + lsu_pmu_bus_misaligned, + lsu_pmu_bus_error, + lsu_pmu_bus_busy, + lsu_pmu_misaligned_m, + lsu_pmu_load_external_m, + lsu_pmu_store_external_m, + dma_pmu_dccm_read, + dma_pmu_dccm_write, + dma_pmu_any_read, + dma_pmu_any_write, + lsu_fir_addr, + lsu_fir_error, + ifu_pmu_instr_aligned, + ifu_pmu_fetch_stall, + ifu_pmu_ic_miss, + ifu_pmu_ic_hit, + ifu_pmu_bus_error, + ifu_pmu_bus_busy, + ifu_pmu_bus_trxn, + ifu_ic_error_start, + ifu_iccm_rd_ecc_single_err, + lsu_trigger_match_m, + dbg_cmd_valid, + dbg_cmd_write, + dbg_cmd_type, + dbg_cmd_addr, + dbg_cmd_wrdata, + ifu_i0_icaf, + ifu_i0_icaf_type, + ifu_i0_icaf_second, + ifu_i0_dbecc, + lsu_idle_any, + i0_brp, + ifu_i0_bp_index, + ifu_i0_bp_fghr, + ifu_i0_bp_btag, + ifu_i0_fa_index, + lsu_error_pkt_r, + lsu_single_ecc_error_incr, + lsu_imprecise_error_load_any, + lsu_imprecise_error_store_any, + lsu_imprecise_error_addr_any, + exu_div_result, + exu_div_wren, + exu_csr_rs1_x, + lsu_result_m, + lsu_result_corr_r, + lsu_load_stall_any, + lsu_store_stall_any, + dma_dccm_stall_any, + dma_iccm_stall_any, + iccm_dma_sb_error, + exu_flush_final, + exu_npc_r, + exu_i0_result_x, + ifu_i0_valid, + ifu_i0_instr, + ifu_i0_pc, + ifu_i0_pc4, + exu_i0_pc_x, + mexintpend, + timer_int, + soft_int, + pic_claimid, + pic_pl, + mhwakeup, + dec_tlu_meicurpl, + dec_tlu_meipt, + ifu_ic_debug_rd_data, + ifu_ic_debug_rd_data_valid, + dec_tlu_ic_diag_pkt, + dbg_halt_req, + dbg_resume_req, + ifu_miss_state_idle, + dec_tlu_dbg_halted, + dec_tlu_debug_mode, + dec_tlu_resume_ack, + dec_tlu_flush_noredir_r, + dec_tlu_mpc_halted_only, + dec_tlu_flush_leak_one_r, + dec_tlu_flush_err_r, + dec_tlu_meihap, + dec_debug_wdata_rs1_d, + dec_dbg_rddata, + dec_dbg_cmd_done, + dec_dbg_cmd_fail, + trigger_pkt_any, + dec_tlu_force_halt, + exu_i0_br_hist_r, + exu_i0_br_error_r, + exu_i0_br_start_error_r, + exu_i0_br_valid_r, + exu_i0_br_mp_r, + exu_i0_br_middle_r, + exu_i0_br_way_r, + dec_i0_rs1_en_d, + dec_i0_rs2_en_d, + gpr_i0_rs1_d, + gpr_i0_rs2_d, + dec_i0_immed_d, + dec_i0_br_immed_d, + i0_ap, + dec_i0_alu_decode_d, + dec_i0_branch_d, + dec_i0_select_pc_d, + dec_i0_pc_d, + dec_i0_rs1_bypass_en_d, + dec_i0_rs2_bypass_en_d, + dec_i0_result_r, + lsu_p, + dec_qual_lsu_d, + mul_p, + div_p, + dec_div_cancel, + dec_lsu_offset_d, + dec_csr_ren_d, + dec_csr_rddata_d, + dec_tlu_flush_lower_r, + dec_tlu_flush_lower_wb, + dec_tlu_flush_path_r, + dec_tlu_i0_kill_writeb_r, + dec_tlu_fence_i_r, + pred_correct_npc_x, + dec_tlu_br0_r_pkt, + dec_tlu_perfcnt0, + dec_tlu_perfcnt1, + dec_tlu_perfcnt2, + dec_tlu_perfcnt3, + dec_i0_predict_p_d, + i0_predict_fghr_d, + i0_predict_index_d, + i0_predict_btag_d, + dec_fa_error_index, + dec_lsu_valid_raw_d, + dec_tlu_mrac_ff, + dec_data_en, + dec_ctl_en, + ifu_i0_cinst, + trace_rv_trace_pkt, + dec_tlu_external_ldfwd_disable, + dec_tlu_sideeffect_posted_disable, + dec_tlu_core_ecc_disable, + dec_tlu_bpred_disable, + dec_tlu_wb_coalescing_disable, + dec_tlu_dma_qos_prty, + dec_tlu_misc_clk_override, + dec_tlu_ifu_clk_override, + dec_tlu_lsu_clk_override, + dec_tlu_bus_clk_override, + dec_tlu_pic_clk_override, + dec_tlu_picio_clk_override, + dec_tlu_dccm_clk_override, + dec_tlu_icm_clk_override, + dec_tlu_i0_commit_cmt, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:36:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:37:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:38:4 + input wire free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:39:4 + input wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:41:4 + input wire lsu_fastint_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:43:4 + output wire dec_extint_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:45:4 + output wire dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:46:4 + output wire dec_pause_state_cg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:48:4 + output wire dec_tlu_core_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:50:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:51:4 + input wire [31:1] rst_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:53:4 + input wire nmi_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:54:4 + input wire [31:1] nmi_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:56:4 + input wire i_cpu_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:57:4 + input wire i_cpu_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:59:4 + output wire o_cpu_halt_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:60:4 + output wire o_cpu_halt_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:61:4 + output wire o_cpu_run_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:62:4 + output wire o_debug_mode_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:64:4 + input wire [31:4] core_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:67:4 + input wire mpc_debug_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:68:4 + input wire mpc_debug_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:69:4 + input wire mpc_reset_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:70:4 + output wire mpc_debug_halt_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:71:4 + output wire mpc_debug_run_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:72:4 + output wire debug_brkpt_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:74:5 + input wire exu_pmu_i0_br_misp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:75:4 + input wire exu_pmu_i0_br_ataken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:76:4 + input wire exu_pmu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:79:4 + input wire lsu_nonblock_load_valid_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:80:4 + input wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:81:4 + input wire lsu_nonblock_load_inv_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:82:4 + input wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:83:4 + input wire lsu_nonblock_load_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:84:4 + input wire lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:85:4 + input wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:86:4 + input wire [31:0] lsu_nonblock_load_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:88:4 + input wire lsu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:89:4 + input wire lsu_pmu_bus_misaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:90:4 + input wire lsu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:91:4 + input wire lsu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:92:4 + input wire lsu_pmu_misaligned_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:93:4 + input wire lsu_pmu_load_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:94:4 + input wire lsu_pmu_store_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:95:4 + input wire dma_pmu_dccm_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:96:4 + input wire dma_pmu_dccm_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:97:4 + input wire dma_pmu_any_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:98:4 + input wire dma_pmu_any_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:100:4 + input wire [31:1] lsu_fir_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:101:4 + input wire [1:0] lsu_fir_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:103:4 + input wire ifu_pmu_instr_aligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:104:4 + input wire ifu_pmu_fetch_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:105:4 + input wire ifu_pmu_ic_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:106:4 + input wire ifu_pmu_ic_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:107:4 + input wire ifu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:108:4 + input wire ifu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:109:4 + input wire ifu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:111:4 + input wire ifu_ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:112:4 + input wire ifu_iccm_rd_ecc_single_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:114:4 + input wire [3:0] lsu_trigger_match_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:115:4 + input wire dbg_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:116:4 + input wire dbg_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:117:4 + input wire [1:0] dbg_cmd_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:118:4 + input wire [31:0] dbg_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:119:4 + input wire [1:0] dbg_cmd_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:122:4 + input wire ifu_i0_icaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:123:4 + input wire [1:0] ifu_i0_icaf_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:125:4 + input wire ifu_i0_icaf_second; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:126:4 + input wire ifu_i0_dbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:128:4 + input wire lsu_idle_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:130:4 + // removed localparam type el2_pkg_el2_br_pkt_t + input wire [50:0] i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:131:4 + input wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:132:4 + input wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:133:4 + input wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:134:4 + input wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:136:4 + // removed localparam type el2_pkg_el2_lsu_error_pkt_t + input wire [39:0] lsu_error_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:137:4 + input wire lsu_single_ecc_error_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:139:4 + input wire lsu_imprecise_error_load_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:140:4 + input wire lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:141:4 + input wire [31:0] lsu_imprecise_error_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:143:4 + input wire [31:0] exu_div_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:144:4 + input wire exu_div_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:146:4 + input wire [31:0] exu_csr_rs1_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:148:4 + input wire [31:0] lsu_result_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:149:4 + input wire [31:0] lsu_result_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:151:4 + input wire lsu_load_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:152:4 + input wire lsu_store_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:153:4 + input wire dma_dccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:154:4 + input wire dma_iccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:156:4 + input wire iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:158:4 + input wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:160:4 + input wire [31:1] exu_npc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:162:4 + input wire [31:0] exu_i0_result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:165:4 + input wire ifu_i0_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:166:4 + input wire [31:0] ifu_i0_instr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:167:4 + input wire [31:1] ifu_i0_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:168:4 + input wire ifu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:169:4 + input wire [31:1] exu_i0_pc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:171:4 + input wire mexintpend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:172:4 + input wire timer_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:173:4 + input wire soft_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:175:4 + input wire [7:0] pic_claimid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:176:4 + input wire [3:0] pic_pl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:177:4 + input wire mhwakeup; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:179:4 + output wire [3:0] dec_tlu_meicurpl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:180:4 + output wire [3:0] dec_tlu_meipt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:182:4 + input wire [70:0] ifu_ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:183:4 + input wire ifu_ic_debug_rd_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:184:4 + // removed localparam type el2_pkg_el2_cache_debug_pkt_t + output wire [89:0] dec_tlu_ic_diag_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:188:4 + input wire dbg_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:189:4 + input wire dbg_resume_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:190:4 + input wire ifu_miss_state_idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:192:4 + output wire dec_tlu_dbg_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:193:4 + output wire dec_tlu_debug_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:194:4 + output wire dec_tlu_resume_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:195:4 + output wire dec_tlu_flush_noredir_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:196:4 + output wire dec_tlu_mpc_halted_only; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:197:4 + output wire dec_tlu_flush_leak_one_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:198:4 + output wire dec_tlu_flush_err_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:199:4 + output wire [31:2] dec_tlu_meihap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:201:4 + output wire dec_debug_wdata_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:203:4 + output wire [31:0] dec_dbg_rddata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:205:4 + output wire dec_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:206:4 + output wire dec_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:208:4 + // removed localparam type el2_pkg_el2_trigger_pkt_t + output wire [151:0] trigger_pkt_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:210:4 + output wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:213:4 + input wire [1:0] exu_i0_br_hist_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:214:4 + input wire exu_i0_br_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:215:4 + input wire exu_i0_br_start_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:216:4 + input wire exu_i0_br_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:217:4 + input wire exu_i0_br_mp_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:218:4 + input wire exu_i0_br_middle_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:222:4 + input wire exu_i0_br_way_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:224:4 + output wire dec_i0_rs1_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:225:4 + output wire dec_i0_rs2_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:226:4 + output wire [31:0] gpr_i0_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:227:4 + output wire [31:0] gpr_i0_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:229:4 + output wire [31:0] dec_i0_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:230:4 + output wire [12:1] dec_i0_br_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:232:4 + // removed localparam type el2_pkg_el2_alu_pkt_t + output wire [41:0] i0_ap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:234:4 + output wire dec_i0_alu_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:235:4 + output wire dec_i0_branch_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:237:4 + output wire dec_i0_select_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:239:4 + output wire [31:1] dec_i0_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:240:4 + output wire [3:0] dec_i0_rs1_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:241:4 + output wire [3:0] dec_i0_rs2_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:243:4 + output wire [31:0] dec_i0_result_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:245:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + output wire [13:0] lsu_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:246:4 + output wire dec_qual_lsu_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:247:4 + // removed localparam type el2_pkg_el2_mul_pkt_t + output wire [22:0] mul_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:248:4 + // removed localparam type el2_pkg_el2_div_pkt_t + output wire [2:0] div_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:249:4 + output wire dec_div_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:251:4 + output wire [11:0] dec_lsu_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:253:4 + output wire dec_csr_ren_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:254:4 + output wire [31:0] dec_csr_rddata_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:256:4 + output wire dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:257:4 + output wire dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:258:4 + output wire [31:1] dec_tlu_flush_path_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:259:4 + output wire dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:260:4 + output wire dec_tlu_fence_i_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:262:4 + output wire [31:1] pred_correct_npc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:264:4 + // removed localparam type el2_pkg_el2_br_tlu_pkt_t + output wire [6:0] dec_tlu_br0_r_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:266:4 + output wire dec_tlu_perfcnt0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:267:4 + output wire dec_tlu_perfcnt1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:268:4 + output wire dec_tlu_perfcnt2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:269:4 + output wire dec_tlu_perfcnt3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:271:4 + // removed localparam type el2_pkg_el2_predict_pkt_t + output wire [55:0] dec_i0_predict_p_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:272:4 + output wire [pt[2236-:8] - 1:0] i0_predict_fghr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:273:4 + output wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:274:4 + output wire [pt[2139-:9] - 1:0] i0_predict_btag_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:276:4 + output wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:278:4 + output wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:280:4 + output wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:282:4 + output wire [1:0] dec_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:283:4 + output wire [1:0] dec_ctl_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:285:4 + input wire [15:0] ifu_i0_cinst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:287:4 + // removed localparam type el2_pkg_el2_trace_pkt_t + output wire [103:0] trace_rv_trace_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:290:4 + output wire dec_tlu_external_ldfwd_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:291:4 + output wire dec_tlu_sideeffect_posted_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:292:4 + output wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:293:4 + output wire dec_tlu_bpred_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:294:4 + output wire dec_tlu_wb_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:295:4 + output wire [2:0] dec_tlu_dma_qos_prty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:298:4 + output wire dec_tlu_misc_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:299:4 + output wire dec_tlu_ifu_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:300:4 + output wire dec_tlu_lsu_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:301:4 + output wire dec_tlu_bus_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:302:4 + output wire dec_tlu_pic_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:303:4 + output wire dec_tlu_picio_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:304:4 + output wire dec_tlu_dccm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:305:4 + output wire dec_tlu_icm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:307:4 + output wire dec_tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:308:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:313:4 + wire dec_tlu_dec_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:314:4 + wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:316:4 + wire dec_ib0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:318:4 + wire dec_pmu_instr_decoded; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:319:4 + wire dec_pmu_decode_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:320:4 + wire dec_pmu_presync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:321:4 + wire dec_pmu_postsync_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:323:4 + wire dec_tlu_wr_pause_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:325:4 + wire [4:0] dec_i0_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:326:4 + wire [4:0] dec_i0_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:328:4 + wire [31:0] dec_i0_instr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:330:4 + wire dec_tlu_trace_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:331:4 + wire dec_tlu_pipelining_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:334:4 + wire [4:0] dec_i0_waddr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:335:4 + wire dec_i0_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:336:4 + wire [31:0] dec_i0_wdata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:337:4 + wire dec_csr_wen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:338:4 + wire [11:0] dec_csr_wraddr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:339:4 + wire [31:0] dec_csr_wrdata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:341:4 + wire [11:0] dec_csr_rdaddr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:342:4 + wire dec_csr_legal_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:344:4 + wire dec_csr_wen_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:345:4 + wire dec_csr_any_unq_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:346:4 + wire dec_csr_stall_int_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:348:4 + // removed localparam type el2_pkg_el2_inst_pkt_t + // removed localparam type el2_pkg_el2_trap_pkt_t + wire [16:0] dec_tlu_packet_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:350:4 + wire dec_i0_pc4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:351:4 + wire dec_tlu_presync_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:352:4 + wire dec_tlu_postsync_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:353:4 + wire dec_tlu_debug_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:355:4 + wire [31:0] dec_illegal_inst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:357:4 + wire dec_i0_icaf_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:359:4 + wire dec_i0_dbecc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:360:4 + wire dec_i0_icaf_second_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:361:4 + wire [3:0] dec_i0_trigger_match_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:362:4 + wire dec_debug_fence_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:363:4 + wire dec_nonblock_load_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:364:4 + wire [4:0] dec_nonblock_load_waddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:365:4 + wire dec_tlu_flush_pause_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:366:4 + wire [50:0] dec_i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:367:4 + wire [pt[2172-:9]:pt[2163-:6]] dec_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:368:4 + wire [pt[2236-:8] - 1:0] dec_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:369:4 + wire [pt[2139-:9] - 1:0] dec_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:370:4 + wire [$clog2(pt[2061-:14]) - 1:0] dec_i0_bp_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:372:4 + wire [31:1] dec_tlu_i0_pc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:373:4 + wire dec_tlu_i0_kill_writeb_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:374:4 + wire dec_tlu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:376:4 + wire dec_pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:378:4 + wire [1:0] dec_i0_icaf_type_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:380:4 + wire dec_tlu_flush_extint; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:382:4 + wire [31:0] dec_i0_inst_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:383:4 + wire [31:1] dec_i0_pc_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:384:4 + wire dec_tlu_i0_valid_wb1; + wire dec_tlu_int_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:385:4 + wire [4:0] dec_tlu_exc_cause_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:386:4 + wire [31:0] dec_tlu_mtval_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:387:4 + wire dec_tlu_i0_exc_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:389:4 + wire [4:0] div_waddr_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:390:4 + wire dec_div_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:392:4 + wire dec_debug_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:394:4 + assign clk_override = dec_tlu_dec_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:397:4 + assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:400:4 + el2_dec_ib_ctl #(.pt(pt)) instbuff( + .dbg_cmd_valid(dbg_cmd_valid), + .dbg_cmd_write(dbg_cmd_write), + .dbg_cmd_type(dbg_cmd_type), + .dbg_cmd_addr(dbg_cmd_addr), + .i0_brp(i0_brp), + .ifu_i0_bp_index(ifu_i0_bp_index), + .ifu_i0_bp_fghr(ifu_i0_bp_fghr), + .ifu_i0_bp_btag(ifu_i0_bp_btag), + .ifu_i0_fa_index(ifu_i0_fa_index), + .ifu_i0_pc4(ifu_i0_pc4), + .ifu_i0_valid(ifu_i0_valid), + .ifu_i0_icaf(ifu_i0_icaf), + .ifu_i0_icaf_type(ifu_i0_icaf_type), + .ifu_i0_icaf_second(ifu_i0_icaf_second), + .ifu_i0_dbecc(ifu_i0_dbecc), + .ifu_i0_instr(ifu_i0_instr), + .ifu_i0_pc(ifu_i0_pc), + .dec_ib0_valid_d(dec_ib0_valid_d), + .dec_debug_valid_d(dec_debug_valid_d), + .dec_i0_instr_d(dec_i0_instr_d), + .dec_i0_pc_d(dec_i0_pc_d), + .dec_i0_pc4_d(dec_i0_pc4_d), + .dec_i0_brp(dec_i0_brp), + .dec_i0_bp_index(dec_i0_bp_index), + .dec_i0_bp_fghr(dec_i0_bp_fghr), + .dec_i0_bp_btag(dec_i0_bp_btag), + .dec_i0_bp_fa_index(dec_i0_bp_fa_index), + .dec_i0_icaf_d(dec_i0_icaf_d), + .dec_i0_icaf_second_d(dec_i0_icaf_second_d), + .dec_i0_icaf_type_d(dec_i0_icaf_type_d), + .dec_i0_dbecc_d(dec_i0_dbecc_d), + .dec_debug_wdata_rs1_d(dec_debug_wdata_rs1_d), + .dec_debug_fence_d(dec_debug_fence_d) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:403:4 + el2_dec_decode_ctl #(.pt(pt)) decode( + .dec_tlu_trace_disable(dec_tlu_trace_disable), + .dec_debug_valid_d(dec_debug_valid_d), + .dec_tlu_flush_extint(dec_tlu_flush_extint), + .dec_tlu_force_halt(dec_tlu_force_halt), + .dec_extint_stall(dec_extint_stall), + .ifu_i0_cinst(ifu_i0_cinst), + .dec_i0_inst_wb(dec_i0_inst_wb), + .dec_i0_pc_wb(dec_i0_pc_wb), + .lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m), + .lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m), + .lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r), + .lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r), + .lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid), + .lsu_nonblock_load_data_error(lsu_nonblock_load_data_error), + .lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag), + .dec_i0_trigger_match_d(dec_i0_trigger_match_d), + .dec_tlu_wr_pause_r(dec_tlu_wr_pause_r), + .dec_tlu_pipelining_disable(dec_tlu_pipelining_disable), + .lsu_trigger_match_m(lsu_trigger_match_m), + .lsu_pmu_misaligned_m(lsu_pmu_misaligned_m), + .dec_tlu_debug_stall(dec_tlu_debug_stall), + .dec_tlu_flush_leak_one_r(dec_tlu_flush_leak_one_r), + .dec_debug_fence_d(dec_debug_fence_d), + .dbg_cmd_wrdata(dbg_cmd_wrdata), + .dec_i0_icaf_d(dec_i0_icaf_d), + .dec_i0_icaf_second_d(dec_i0_icaf_second_d), + .dec_i0_icaf_type_d(dec_i0_icaf_type_d), + .dec_i0_dbecc_d(dec_i0_dbecc_d), + .dec_i0_brp(dec_i0_brp), + .dec_i0_bp_index(dec_i0_bp_index), + .dec_i0_bp_fghr(dec_i0_bp_fghr), + .dec_i0_bp_btag(dec_i0_bp_btag), + .dec_i0_bp_fa_index(dec_i0_bp_fa_index), + .lsu_idle_any(lsu_idle_any), + .lsu_load_stall_any(lsu_load_stall_any), + .lsu_store_stall_any(lsu_store_stall_any), + .dma_dccm_stall_any(dma_dccm_stall_any), + .exu_div_wren(exu_div_wren), + .dec_tlu_i0_kill_writeb_wb(dec_tlu_i0_kill_writeb_wb), + .dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb), + .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r), + .dec_tlu_flush_lower_r(dec_tlu_flush_lower_r), + .dec_tlu_flush_pause_r(dec_tlu_flush_pause_r), + .dec_tlu_presync_d(dec_tlu_presync_d), + .dec_tlu_postsync_d(dec_tlu_postsync_d), + .dec_i0_pc4_d(dec_i0_pc4_d), + .dec_csr_rddata_d(dec_csr_rddata_d), + .dec_csr_legal_d(dec_csr_legal_d), + .exu_csr_rs1_x(exu_csr_rs1_x), + .lsu_result_m(lsu_result_m), + .lsu_result_corr_r(lsu_result_corr_r), + .exu_flush_final(exu_flush_final), + .exu_i0_pc_x(exu_i0_pc_x), + .dec_i0_instr_d(dec_i0_instr_d), + .dec_ib0_valid_d(dec_ib0_valid_d), + .exu_i0_result_x(exu_i0_result_x), + .clk(clk), + .active_clk(active_clk), + .free_l2clk(free_l2clk), + .clk_override(clk_override), + .rst_l(rst_l), + .dec_i0_rs1_en_d(dec_i0_rs1_en_d), + .dec_i0_rs2_en_d(dec_i0_rs2_en_d), + .dec_i0_rs1_d(dec_i0_rs1_d), + .dec_i0_rs2_d(dec_i0_rs2_d), + .dec_i0_immed_d(dec_i0_immed_d), + .dec_i0_br_immed_d(dec_i0_br_immed_d), + .i0_ap(i0_ap), + .dec_i0_decode_d(dec_i0_decode_d), + .dec_i0_alu_decode_d(dec_i0_alu_decode_d), + .dec_i0_branch_d(dec_i0_branch_d), + .dec_i0_waddr_r(dec_i0_waddr_r), + .dec_i0_wen_r(dec_i0_wen_r), + .dec_i0_wdata_r(dec_i0_wdata_r), + .dec_i0_select_pc_d(dec_i0_select_pc_d), + .dec_i0_rs1_bypass_en_d(dec_i0_rs1_bypass_en_d), + .dec_i0_rs2_bypass_en_d(dec_i0_rs2_bypass_en_d), + .dec_i0_result_r(dec_i0_result_r), + .lsu_p(lsu_p), + .dec_qual_lsu_d(dec_qual_lsu_d), + .mul_p(mul_p), + .div_p(div_p), + .div_waddr_wb(div_waddr_wb), + .dec_div_cancel(dec_div_cancel), + .dec_lsu_valid_raw_d(dec_lsu_valid_raw_d), + .dec_lsu_offset_d(dec_lsu_offset_d), + .dec_csr_ren_d(dec_csr_ren_d), + .dec_csr_wen_unq_d(dec_csr_wen_unq_d), + .dec_csr_any_unq_d(dec_csr_any_unq_d), + .dec_csr_rdaddr_d(dec_csr_rdaddr_d), + .dec_csr_wen_r(dec_csr_wen_r), + .dec_csr_wraddr_r(dec_csr_wraddr_r), + .dec_csr_wrdata_r(dec_csr_wrdata_r), + .dec_csr_stall_int_ff(dec_csr_stall_int_ff), + .dec_tlu_i0_valid_r(dec_tlu_i0_valid_r), + .dec_tlu_packet_r(dec_tlu_packet_r), + .dec_tlu_i0_pc_r(dec_tlu_i0_pc_r), + .dec_illegal_inst(dec_illegal_inst), + .pred_correct_npc_x(pred_correct_npc_x), + .dec_i0_predict_p_d(dec_i0_predict_p_d), + .i0_predict_fghr_d(i0_predict_fghr_d), + .i0_predict_index_d(i0_predict_index_d), + .i0_predict_btag_d(i0_predict_btag_d), + .dec_fa_error_index(dec_fa_error_index), + .dec_data_en(dec_data_en), + .dec_ctl_en(dec_ctl_en), + .dec_pmu_instr_decoded(dec_pmu_instr_decoded), + .dec_pmu_decode_stall(dec_pmu_decode_stall), + .dec_pmu_presync_stall(dec_pmu_presync_stall), + .dec_pmu_postsync_stall(dec_pmu_postsync_stall), + .dec_nonblock_load_wen(dec_nonblock_load_wen), + .dec_nonblock_load_waddr(dec_nonblock_load_waddr), + .dec_pause_state(dec_pause_state), + .dec_pause_state_cg(dec_pause_state_cg), + .dec_div_active(dec_div_active), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:406:4 + el2_dec_tlu_ctl #(.pt(pt)) tlu( + .clk(clk), + .free_clk(free_clk), + .free_l2clk(free_l2clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .rst_vec(rst_vec), + .nmi_int(nmi_int), + .nmi_vec(nmi_vec), + .i_cpu_halt_req(i_cpu_halt_req), + .i_cpu_run_req(i_cpu_run_req), + .lsu_fastint_stall_any(lsu_fastint_stall_any), + .ifu_pmu_instr_aligned(ifu_pmu_instr_aligned), + .ifu_pmu_fetch_stall(ifu_pmu_fetch_stall), + .ifu_pmu_ic_miss(ifu_pmu_ic_miss), + .ifu_pmu_ic_hit(ifu_pmu_ic_hit), + .ifu_pmu_bus_error(ifu_pmu_bus_error), + .ifu_pmu_bus_busy(ifu_pmu_bus_busy), + .ifu_pmu_bus_trxn(ifu_pmu_bus_trxn), + .dec_pmu_instr_decoded(dec_pmu_instr_decoded), + .dec_pmu_decode_stall(dec_pmu_decode_stall), + .dec_pmu_presync_stall(dec_pmu_presync_stall), + .dec_pmu_postsync_stall(dec_pmu_postsync_stall), + .lsu_store_stall_any(lsu_store_stall_any), + .dma_dccm_stall_any(dma_dccm_stall_any), + .dma_iccm_stall_any(dma_iccm_stall_any), + .exu_pmu_i0_br_misp(exu_pmu_i0_br_misp), + .exu_pmu_i0_br_ataken(exu_pmu_i0_br_ataken), + .exu_pmu_i0_pc4(exu_pmu_i0_pc4), + .lsu_pmu_bus_trxn(lsu_pmu_bus_trxn), + .lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned), + .lsu_pmu_bus_error(lsu_pmu_bus_error), + .lsu_pmu_bus_busy(lsu_pmu_bus_busy), + .lsu_pmu_load_external_m(lsu_pmu_load_external_m), + .lsu_pmu_store_external_m(lsu_pmu_store_external_m), + .dma_pmu_dccm_read(dma_pmu_dccm_read), + .dma_pmu_dccm_write(dma_pmu_dccm_write), + .dma_pmu_any_read(dma_pmu_any_read), + .dma_pmu_any_write(dma_pmu_any_write), + .lsu_fir_addr(lsu_fir_addr), + .lsu_fir_error(lsu_fir_error), + .iccm_dma_sb_error(iccm_dma_sb_error), + .lsu_error_pkt_r(lsu_error_pkt_r), + .lsu_single_ecc_error_incr(lsu_single_ecc_error_incr), + .dec_pause_state(dec_pause_state), + .lsu_imprecise_error_store_any(lsu_imprecise_error_store_any), + .lsu_imprecise_error_load_any(lsu_imprecise_error_load_any), + .lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any), + .dec_csr_wen_unq_d(dec_csr_wen_unq_d), + .dec_csr_any_unq_d(dec_csr_any_unq_d), + .dec_csr_rdaddr_d(dec_csr_rdaddr_d), + .dec_csr_wen_r(dec_csr_wen_r), + .dec_csr_wraddr_r(dec_csr_wraddr_r), + .dec_csr_wrdata_r(dec_csr_wrdata_r), + .dec_csr_stall_int_ff(dec_csr_stall_int_ff), + .dec_tlu_i0_valid_r(dec_tlu_i0_valid_r), + .exu_npc_r(exu_npc_r), + .dec_tlu_i0_pc_r(dec_tlu_i0_pc_r), + .dec_tlu_packet_r(dec_tlu_packet_r), + .dec_illegal_inst(dec_illegal_inst), + .dec_i0_decode_d(dec_i0_decode_d), + .exu_i0_br_hist_r(exu_i0_br_hist_r), + .exu_i0_br_error_r(exu_i0_br_error_r), + .exu_i0_br_start_error_r(exu_i0_br_start_error_r), + .exu_i0_br_valid_r(exu_i0_br_valid_r), + .exu_i0_br_mp_r(exu_i0_br_mp_r), + .exu_i0_br_middle_r(exu_i0_br_middle_r), + .exu_i0_br_way_r(exu_i0_br_way_r), + .dec_tlu_core_empty(dec_tlu_core_empty), + .dec_dbg_cmd_done(dec_dbg_cmd_done), + .dec_dbg_cmd_fail(dec_dbg_cmd_fail), + .dec_tlu_dbg_halted(dec_tlu_dbg_halted), + .dec_tlu_debug_mode(dec_tlu_debug_mode), + .dec_tlu_resume_ack(dec_tlu_resume_ack), + .dec_tlu_debug_stall(dec_tlu_debug_stall), + .dec_tlu_flush_noredir_r(dec_tlu_flush_noredir_r), + .dec_tlu_mpc_halted_only(dec_tlu_mpc_halted_only), + .dec_tlu_flush_leak_one_r(dec_tlu_flush_leak_one_r), + .dec_tlu_flush_err_r(dec_tlu_flush_err_r), + .dec_tlu_flush_extint(dec_tlu_flush_extint), + .dec_tlu_meihap(dec_tlu_meihap), + .dbg_halt_req(dbg_halt_req), + .dbg_resume_req(dbg_resume_req), + .ifu_miss_state_idle(ifu_miss_state_idle), + .lsu_idle_any(lsu_idle_any), + .dec_div_active(dec_div_active), + .trigger_pkt_any(trigger_pkt_any), + .ifu_ic_error_start(ifu_ic_error_start), + .ifu_iccm_rd_ecc_single_err(ifu_iccm_rd_ecc_single_err), + .ifu_ic_debug_rd_data(ifu_ic_debug_rd_data), + .ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid), + .dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt), + .pic_claimid(pic_claimid), + .pic_pl(pic_pl), + .mhwakeup(mhwakeup), + .mexintpend(mexintpend), + .timer_int(timer_int), + .soft_int(soft_int), + .o_cpu_halt_status(o_cpu_halt_status), + .o_cpu_halt_ack(o_cpu_halt_ack), + .o_cpu_run_ack(o_cpu_run_ack), + .o_debug_mode_status(o_debug_mode_status), + .core_id(core_id), + .mpc_debug_halt_req(mpc_debug_halt_req), + .mpc_debug_run_req(mpc_debug_run_req), + .mpc_reset_run_req(mpc_reset_run_req), + .mpc_debug_halt_ack(mpc_debug_halt_ack), + .mpc_debug_run_ack(mpc_debug_run_ack), + .debug_brkpt_status(debug_brkpt_status), + .dec_tlu_meicurpl(dec_tlu_meicurpl), + .dec_tlu_meipt(dec_tlu_meipt), + .dec_csr_rddata_d(dec_csr_rddata_d), + .dec_csr_legal_d(dec_csr_legal_d), + .dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt), + .dec_tlu_i0_kill_writeb_wb(dec_tlu_i0_kill_writeb_wb), + .dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb), + .dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt), + .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r), + .dec_tlu_flush_lower_r(dec_tlu_flush_lower_r), + .dec_tlu_flush_path_r(dec_tlu_flush_path_r), + .dec_tlu_fence_i_r(dec_tlu_fence_i_r), + .dec_tlu_wr_pause_r(dec_tlu_wr_pause_r), + .dec_tlu_flush_pause_r(dec_tlu_flush_pause_r), + .dec_tlu_presync_d(dec_tlu_presync_d), + .dec_tlu_postsync_d(dec_tlu_postsync_d), + .dec_tlu_mrac_ff(dec_tlu_mrac_ff), + .dec_tlu_force_halt(dec_tlu_force_halt), + .dec_tlu_perfcnt0(dec_tlu_perfcnt0), + .dec_tlu_perfcnt1(dec_tlu_perfcnt1), + .dec_tlu_perfcnt2(dec_tlu_perfcnt2), + .dec_tlu_perfcnt3(dec_tlu_perfcnt3), + .dec_tlu_i0_exc_valid_wb1(dec_tlu_i0_exc_valid_wb1), + .dec_tlu_i0_valid_wb1(dec_tlu_i0_valid_wb1), + .dec_tlu_int_valid_wb1(dec_tlu_int_valid_wb1), + .dec_tlu_exc_cause_wb1(dec_tlu_exc_cause_wb1), + .dec_tlu_mtval_wb1(dec_tlu_mtval_wb1), + .dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable), + .dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .dec_tlu_bpred_disable(dec_tlu_bpred_disable), + .dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable), + .dec_tlu_pipelining_disable(dec_tlu_pipelining_disable), + .dec_tlu_trace_disable(dec_tlu_trace_disable), + .dec_tlu_dma_qos_prty(dec_tlu_dma_qos_prty), + .dec_tlu_misc_clk_override(dec_tlu_misc_clk_override), + .dec_tlu_dec_clk_override(dec_tlu_dec_clk_override), + .dec_tlu_ifu_clk_override(dec_tlu_ifu_clk_override), + .dec_tlu_lsu_clk_override(dec_tlu_lsu_clk_override), + .dec_tlu_bus_clk_override(dec_tlu_bus_clk_override), + .dec_tlu_pic_clk_override(dec_tlu_pic_clk_override), + .dec_tlu_picio_clk_override(dec_tlu_picio_clk_override), + .dec_tlu_dccm_clk_override(dec_tlu_dccm_clk_override), + .dec_tlu_icm_clk_override(dec_tlu_icm_clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:409:4 + el2_dec_gpr_ctl #(.pt(pt)) arf( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .raddr0(dec_i0_rs1_d[4:0]), + .raddr1(dec_i0_rs2_d[4:0]), + .wen0(dec_i0_wen_r), + .waddr0(dec_i0_waddr_r[4:0]), + .wd0(dec_i0_wdata_r[31:0]), + .wen1(dec_nonblock_load_wen), + .waddr1(dec_nonblock_load_waddr[4:0]), + .wd1(lsu_nonblock_load_data[31:0]), + .wen2(exu_div_wren), + .waddr2(div_waddr_wb), + .wd2(exu_div_result[31:0]), + .rd0(gpr_i0_rs1_d[31:0]), + .rd1(gpr_i0_rs2_d[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:425:4 + el2_dec_trigger #(.pt(pt)) dec_trigger( + .trigger_pkt_any(trigger_pkt_any), + .dec_i0_pc_d(dec_i0_pc_d), + .dec_i0_trigger_match_d(dec_i0_trigger_match_d) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:431:4 + assign trace_rv_trace_pkt[102-:32] = dec_i0_inst_wb[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:432:4 + assign trace_rv_trace_pkt[70-:32] = {dec_i0_pc_wb[31:1], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:434:4 + assign trace_rv_trace_pkt[103] = (dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1) | dec_tlu_i0_exc_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:435:4 + assign trace_rv_trace_pkt[38] = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:436:4 + assign trace_rv_trace_pkt[37-:5] = dec_tlu_exc_cause_wb1[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:437:4 + assign trace_rv_trace_pkt[32] = dec_tlu_int_valid_wb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv:438:4 + assign trace_rv_trace_pkt[31-:32] = dec_tlu_mtval_wb1[31:0]; +endmodule +module el2_exu_alu_ctl ( + clk, + rst_l, + scan_mode, + flush_upper_x, + flush_lower_r, + enable, + valid_in, + ap, + csr_ren_in, + csr_rddata_in, + a_in, + b_in, + pc_in, + pp_in, + brimm_in, + result_ff, + flush_upper_out, + flush_final_out, + flush_path_out, + pc_ff, + pred_correct_out, + predict_p_out +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:23:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:24:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:25:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:27:4 + input wire flush_upper_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:28:4 + input wire flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:29:4 + input wire enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:30:4 + input wire valid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:31:4 + // removed localparam type el2_pkg_el2_alu_pkt_t + input wire [41:0] ap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:32:4 + input wire csr_ren_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:33:4 + input wire [31:0] csr_rddata_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:34:4 + input wire signed [31:0] a_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:35:4 + input wire [31:0] b_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:36:4 + input wire [31:1] pc_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:37:4 + // removed localparam type el2_pkg_el2_predict_pkt_t + input wire [55:0] pp_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:38:4 + input wire [12:1] brimm_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:41:4 + output wire [31:0] result_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:42:4 + output wire flush_upper_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:43:4 + output wire flush_final_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:44:4 + output wire [31:1] flush_path_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:45:4 + output wire [31:1] pc_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:46:4 + output wire pred_correct_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:47:4 + output reg [55:0] predict_p_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:51:4 + wire [31:0] zba_a_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:52:4 + wire [31:0] aout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:53:4 + wire cout; + wire ov; + wire neg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:54:4 + wire [31:0] lout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:55:4 + wire [31:0] sout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:56:4 + wire sel_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:57:4 + wire sel_adder; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:58:4 + wire slt_one; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:59:4 + wire actual_taken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:60:4 + wire [31:1] pcout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:61:4 + wire cond_mispredict; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:62:4 + wire target_mispredict; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:63:4 + wire eq; + wire ne; + wire lt; + wire ge; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:64:4 + wire any_jal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:65:4 + wire [1:0] newhist; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:66:4 + wire sel_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:67:4 + wire [31:0] csr_write_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:68:4 + wire [31:0] result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:76:4 + wire ap_clz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:77:4 + wire ap_ctz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:78:4 + wire ap_cpop; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:79:4 + wire ap_sext_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:80:4 + wire ap_sext_h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:81:4 + wire ap_min; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:82:4 + wire ap_max; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:83:4 + wire ap_rol; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:84:4 + wire ap_ror; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:85:4 + wire ap_rev8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:86:4 + wire ap_orc_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:87:4 + wire ap_zbb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:90:4 + wire ap_bset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:91:4 + wire ap_bclr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:92:4 + wire ap_binv; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:93:4 + wire ap_bext; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:96:4 + wire ap_pack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:97:4 + wire ap_packu; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:98:4 + wire ap_packh; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:101:4 + wire ap_sh1add; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:102:4 + wire ap_sh2add; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:103:4 + wire ap_sh3add; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:104:4 + wire ap_zba; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:108:4 + generate + if (pt[2207-:5] == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:110:8 + assign ap_clz = ap[41]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:111:8 + assign ap_ctz = ap[40]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:112:8 + assign ap_cpop = ap[39]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:113:8 + assign ap_sext_b = ap[38]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:114:8 + assign ap_sext_h = ap[37]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:115:8 + assign ap_min = ap[36]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:116:8 + assign ap_max = ap[35]; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:120:8 + assign ap_clz = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:121:8 + assign ap_ctz = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:122:8 + assign ap_cpop = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:123:8 + assign ap_sext_b = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:124:8 + assign ap_sext_h = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:125:8 + assign ap_min = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:126:8 + assign ap_max = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:130:4 + generate + if ((pt[2207-:5] == 1) | (pt[2187-:5] == 1)) begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:132:8 + assign ap_rol = ap[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:133:8 + assign ap_ror = ap[30]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:134:8 + assign ap_rev8 = ap[29] & (b_in[4:0] == 5'b11000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:135:8 + assign ap_orc_b = ap[28] & (b_in[4:0] == 5'b00111); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:136:8 + assign ap_zbb = ap[27]; + end + else begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:140:8 + assign ap_rol = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:141:8 + assign ap_ror = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:142:8 + assign ap_rev8 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:143:8 + assign ap_orc_b = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:144:8 + assign ap_zbb = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:148:4 + generate + if (pt[2177-:5] == 1) begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:150:8 + assign ap_bset = ap[26]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:151:8 + assign ap_bclr = ap[25]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:152:8 + assign ap_binv = ap[24]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:153:8 + assign ap_bext = ap[23]; + end + else begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:157:8 + assign ap_bset = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:158:8 + assign ap_bclr = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:159:8 + assign ap_binv = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:160:8 + assign ap_bext = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:164:4 + generate + if (pt[2187-:5] == 1) begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:166:8 + assign ap_packu = ap[33]; + end + else begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:170:8 + assign ap_packu = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:174:4 + generate + if ((((pt[2207-:5] == 1) | (pt[2187-:5] == 1)) | (pt[2197-:5] == 1)) | (pt[2192-:5] == 1)) begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:176:8 + assign ap_pack = ap[34]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:177:8 + assign ap_packh = ap[32]; + end + else begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:181:8 + assign ap_pack = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:182:8 + assign ap_packh = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:186:4 + generate + if (pt[2212-:5] == 1) begin : genblk6 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:188:8 + assign ap_sh1add = ap[22]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:189:8 + assign ap_sh2add = ap[21]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:190:8 + assign ap_sh3add = ap[20]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:191:8 + assign ap_zba = ap[19]; + end + else begin : genblk6 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:195:8 + assign ap_sh1add = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:196:8 + assign ap_sh2add = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:197:8 + assign ap_sh3add = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:198:8 + assign ap_zba = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:209:4 + rvdffpcie #(.WIDTH(31)) i_pc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(enable), + .din(pc_in[31:1]), + .dout(pc_ff[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:210:4 + rvdffe #(.WIDTH(32)) i_result_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(enable & valid_in), + .din(result[31:0]), + .dout(result_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:242:4 + assign zba_a_in[31:0] = ((({32 {ap_sh1add}} & {a_in[30:0], 1'b0}) | ({32 {ap_sh2add}} & {a_in[29:0], 2'b00})) | ({32 {ap_sh3add}} & {a_in[28:0], 3'b000})) | ({32 {~ap_zba}} & a_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:247:4 + wire [31:0] bm; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:249:4 + assign bm[31:0] = (ap[7] ? ~b_in[31:0] : b_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:251:4 + assign {cout, aout[31:0]} = ({1'b0, zba_a_in[31:0]} + {1'b0, bm[31:0]}) + {32'b00000000000000000000000000000000, ap[7]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:253:4 + assign ov = ((~a_in[31] & ~bm[31]) & aout[31]) | ((a_in[31] & bm[31]) & ~aout[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:256:4 + assign lt = (~ap[5] & (neg ^ ov)) | (ap[5] & ~cout); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:259:4 + assign eq = a_in[31:0] == b_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:260:4 + assign ne = ~eq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:261:4 + assign neg = aout[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:262:4 + assign ge = ~lt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:266:4 + assign lout[31:0] = (((((({32 {csr_ren_in}} & csr_rddata_in[31:0]) | (({32 {ap[18] & ~ap_zbb}} & a_in[31:0]) & b_in[31:0])) | ({32 {ap[17] & ~ap_zbb}} & (a_in[31:0] | b_in[31:0]))) | ({32 {ap[16] & ~ap_zbb}} & (a_in[31:0] ^ b_in[31:0]))) | (({32 {ap[18] & ap_zbb}} & a_in[31:0]) & ~b_in[31:0])) | ({32 {ap[17] & ap_zbb}} & (a_in[31:0] | ~b_in[31:0]))) | ({32 {ap[16] & ap_zbb}} & (a_in[31:0] ^ ~b_in[31:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:280:4 + wire [5:0] shift_amount; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:281:4 + wire [31:0] shift_mask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:282:4 + wire [62:0] shift_extend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:283:4 + wire [62:0] shift_long; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:286:4 + assign shift_amount[5:0] = ((((({6 {ap[15]}} & (6'd32 - {1'b0, b_in[4:0]})) | ({6 {ap[14]}} & {1'b0, b_in[4:0]})) | ({6 {ap[13]}} & {1'b0, b_in[4:0]})) | ({6 {ap_rol}} & (6'd32 - {1'b0, b_in[4:0]}))) | ({6 {ap_ror}} & {1'b0, b_in[4:0]})) | ({6 {ap_bext}} & {1'b0, b_in[4:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:294:4 + assign shift_mask[31:0] = 32'hffffffff << ({5 {ap[15]}} & b_in[4:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:297:4 + assign shift_extend[31:0] = a_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:299:4 + assign shift_extend[62:32] = ((({31 {ap[13]}} & {31 {a_in[31]}}) | ({31 {ap[15]}} & a_in[30:0])) | ({31 {ap_rol}} & a_in[30:0])) | ({31 {ap_ror}} & a_in[30:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:305:4 + assign shift_long[62:0] = shift_extend[62:0] >> shift_amount[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:307:4 + assign sout[31:0] = shift_long[31:0] & shift_mask[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:314:4 + wire bitmanip_clz_ctz_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:315:4 + wire [31:0] bitmanip_a_reverse_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:316:4 + wire [31:0] bitmanip_lzd_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:317:4 + reg [5:0] bitmanip_dw_lzd_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:318:4 + wire [5:0] bitmanip_clz_ctz_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:320:4 + assign bitmanip_clz_ctz_sel = ap_clz | ap_ctz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:322:4 + assign bitmanip_a_reverse_ff[31:0] = {a_in[0], a_in[1], a_in[2], a_in[3], a_in[4], a_in[5], a_in[6], a_in[7], a_in[8], a_in[9], a_in[10], a_in[11], a_in[12], a_in[13], a_in[14], a_in[15], a_in[16], a_in[17], a_in[18], a_in[19], a_in[20], a_in[21], a_in[22], a_in[23], a_in[24], a_in[25], a_in[26], a_in[27], a_in[28], a_in[29], a_in[30], a_in[31]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:327:4 + assign bitmanip_lzd_in[31:0] = ({32 {ap_clz}} & a_in[31:0]) | ({32 {ap_ctz}} & bitmanip_a_reverse_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:330:4 + reg [31:0] bitmanip_lzd_os; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:331:4 + integer i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:332:4 + reg found; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:334:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:336:9 + bitmanip_lzd_os[31:0] = bitmanip_lzd_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:337:9 + bitmanip_dw_lzd_enc[5:0] = 6'b000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:338:9 + found = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:340:9 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:340:14 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:340:14 + for (i = 0; i < 32; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:341:12 + if ((bitmanip_lzd_os[31] == 1'b0) && (found == 0)) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:342:15 + bitmanip_dw_lzd_enc[5:0] = bitmanip_dw_lzd_enc[5:0] + 6'b000001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:343:15 + bitmanip_lzd_os[31:0] = bitmanip_lzd_os[31:0] << 1; + end + else + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:346:15 + found = 1'b1; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:352:4 + assign bitmanip_clz_ctz_result[5:0] = {6 {bitmanip_clz_ctz_sel}} & {bitmanip_dw_lzd_enc[5], {5 {~bitmanip_dw_lzd_enc[5]}} & bitmanip_dw_lzd_enc[4:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:359:4 + reg [5:0] bitmanip_cpop; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:360:4 + wire [5:0] bitmanip_cpop_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:363:4 + integer bitmanip_cpop_i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:365:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:367:8 + bitmanip_cpop[5:0] = 6'b000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:369:8 + for (bitmanip_cpop_i = 0; bitmanip_cpop_i < 32; bitmanip_cpop_i = bitmanip_cpop_i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:371:13 + bitmanip_cpop[5:0] = bitmanip_cpop[5:0] + {5'b00000, a_in[bitmanip_cpop_i]}; + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:376:4 + assign bitmanip_cpop_result[5:0] = {6 {ap_cpop}} & bitmanip_cpop[5:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:383:4 + wire [31:0] bitmanip_sext_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:385:4 + assign bitmanip_sext_result[31:0] = ({32 {ap_sext_b}} & {{24 {a_in[7]}}, a_in[7:0]}) | ({32 {ap_sext_h}} & {{16 {a_in[15]}}, a_in[15:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:393:4 + wire bitmanip_minmax_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:394:4 + wire [31:0] bitmanip_minmax_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:396:4 + assign bitmanip_minmax_sel = ap_min | ap_max; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:398:4 + wire bitmanip_minmax_sel_a; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:400:4 + assign bitmanip_minmax_sel_a = ge ^ ap_min; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:402:4 + assign bitmanip_minmax_result[31:0] = ({32 {bitmanip_minmax_sel & bitmanip_minmax_sel_a}} & a_in[31:0]) | ({32 {bitmanip_minmax_sel & ~bitmanip_minmax_sel_a}} & b_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:410:4 + wire [31:0] bitmanip_pack_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:411:4 + wire [31:0] bitmanip_packu_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:412:4 + wire [31:0] bitmanip_packh_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:414:4 + assign bitmanip_pack_result[31:0] = {32 {ap_pack}} & {b_in[15:0], a_in[15:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:415:4 + assign bitmanip_packu_result[31:0] = {32 {ap_packu}} & {b_in[31:16], a_in[31:16]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:416:4 + assign bitmanip_packh_result[31:0] = {32 {ap_packh}} & {16'b0000000000000000, b_in[7:0], a_in[7:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:422:4 + wire [31:0] bitmanip_rev8_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:423:4 + wire [31:0] bitmanip_orc_b_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:425:4 + assign bitmanip_rev8_result[31:0] = {32 {ap_rev8}} & {a_in[7:0], a_in[15:8], a_in[23:16], a_in[31:24]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:450:4 + assign bitmanip_orc_b_result[31:0] = {32 {ap_orc_b}} & {{8 {|a_in[31:24]}}, {8 {|a_in[23:16]}}, {8 {|a_in[15:8]}}, {8 {|a_in[7:0]}}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:456:4 + wire [31:0] bitmanip_sb_1hot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:457:4 + wire [31:0] bitmanip_sb_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:459:4 + assign bitmanip_sb_1hot[31:0] = 32'h00000001 << b_in[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:461:4 + assign bitmanip_sb_data[31:0] = (({32 {ap_bset}} & (a_in[31:0] | bitmanip_sb_1hot[31:0])) | ({32 {ap_bclr}} & (a_in[31:0] & ~bitmanip_sb_1hot[31:0]))) | ({32 {ap_binv}} & (a_in[31:0] ^ bitmanip_sb_1hot[31:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:470:4 + assign sel_shift = (((ap[15] | ap[14]) | ap[13]) | ap_rol) | ap_ror; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:471:4 + assign sel_adder = ((((ap[8] | ap[7]) | ap_zba) & ~ap[6]) & ~ap_min) & ~ap_max; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:472:4 + assign sel_pc = ((ap[4] | pp_in[34]) | pp_in[33]) | pp_in[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:473:4 + assign csr_write_data[31:0] = (ap[0] ? b_in[31:0] : a_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:475:4 + assign slt_one = ap[6] & lt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:479:4 + assign result[31:0] = (((((((((((((((lout[31:0] | ({32 {sel_shift}} & sout[31:0])) | ({32 {sel_adder}} & aout[31:0])) | ({32 {sel_pc}} & {pcout[31:1], 1'b0})) | ({32 {ap[1]}} & csr_write_data[31:0])) | {31'b0000000000000000000000000000000, slt_one}) | ({32 {ap_bext}} & {31'b0000000000000000000000000000000, sout[0]})) | {26'b00000000000000000000000000, bitmanip_clz_ctz_result[5:0]}) | {26'b00000000000000000000000000, bitmanip_cpop_result[5:0]}) | bitmanip_sext_result[31:0]) | bitmanip_minmax_result[31:0]) | bitmanip_pack_result[31:0]) | bitmanip_packu_result[31:0]) | bitmanip_packh_result[31:0]) | bitmanip_rev8_result[31:0]) | bitmanip_orc_b_result[31:0]) | bitmanip_sb_data[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:501:4 + assign any_jal = ((ap[4] | pp_in[34]) | pp_in[33]) | pp_in[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:506:4 + assign actual_taken = ((((ap[12] & eq) | (ap[11] & ne)) | (ap[10] & lt)) | (ap[9] & ge)) | any_jal; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:515:4 + rvbradder ibradder( + .pc(pc_in[31:1]), + .offset(brimm_in[12:1]), + .dout(pcout[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:525:4 + assign pred_correct_out = (((valid_in & ap[2]) & ~actual_taken) & ~any_jal) | (((valid_in & ap[3]) & actual_taken) & ~any_jal); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:530:4 + assign flush_path_out[31:1] = (any_jal ? aout[31:1] : pcout[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:534:4 + assign cond_mispredict = (ap[3] & ~actual_taken) | (ap[2] & actual_taken); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:540:4 + assign target_mispredict = pp_in[31] & (pp_in[30:0] != aout[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:542:4 + assign flush_upper_out = ((((ap[4] | cond_mispredict) | target_mispredict) & valid_in) & ~flush_upper_x) & ~flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:543:4 + assign flush_final_out = ((((ap[4] | cond_mispredict) | target_mispredict) & valid_in) & ~flush_upper_x) | flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:561:4 + assign newhist[1] = (pp_in[51] & pp_in[50]) | (~pp_in[50] & actual_taken); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:562:4 + assign newhist[0] = (~pp_in[51] & ~actual_taken) | (pp_in[51] & actual_taken); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:564:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:565:7 + predict_p_out = pp_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:567:7 + predict_p_out[55] = (~flush_upper_x & ~flush_lower_r) & (cond_mispredict | target_mispredict); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:568:7 + predict_p_out[54] = actual_taken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:569:7 + predict_p_out[51] = newhist[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_alu_ctl.sv:570:7 + predict_p_out[50] = newhist[0]; + end + initial _sv2v_0 = 0; +endmodule +module el2_exu_mul_ctl ( + clk, + rst_l, + scan_mode, + mul_p, + rs1_in, + rs2_in, + result_x +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:23:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:24:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:25:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:27:4 + // removed localparam type el2_pkg_el2_mul_pkt_t + input wire [22:0] mul_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:29:4 + input wire [31:0] rs1_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:30:4 + input wire [31:0] rs2_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:33:4 + output wire [31:0] result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:37:4 + wire mul_x_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:38:4 + wire bit_x_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:39:4 + wire signed [32:0] rs1_ext_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:40:4 + wire signed [32:0] rs2_ext_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:41:4 + wire [65:0] prod_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:42:4 + wire low_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:48:4 + wire bitmanip_sel_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:49:4 + wire bitmanip_sel_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:50:4 + wire [31:0] bitmanip_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:51:4 + wire [31:0] bitmanip_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:56:4 + wire ap_bcompress; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:57:4 + wire ap_bdecompress; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:60:4 + wire ap_clmul; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:61:4 + wire ap_clmulh; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:62:4 + wire ap_clmulr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:65:4 + wire ap_grev; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:66:4 + wire ap_gorc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:67:4 + wire ap_shfl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:68:4 + wire ap_unshfl; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:69:4 + wire ap_xperm_n; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:70:4 + wire ap_xperm_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:71:4 + wire ap_xperm_h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:74:4 + wire ap_crc32_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:75:4 + wire ap_crc32_h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:76:4 + wire ap_crc32_w; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:77:4 + wire ap_crc32c_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:78:4 + wire ap_crc32c_h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:79:4 + wire ap_crc32c_w; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:82:4 + wire ap_bfp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:85:4 + generate + if (pt[2197-:5] == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:87:8 + assign ap_bcompress = mul_p[18]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:88:8 + assign ap_bdecompress = mul_p[17]; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:92:8 + assign ap_bcompress = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:93:8 + assign ap_bdecompress = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:96:4 + generate + if (pt[2202-:5] == 1) begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:98:8 + assign ap_clmul = mul_p[16]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:99:8 + assign ap_clmulh = mul_p[15]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:100:8 + assign ap_clmulr = mul_p[14]; + end + else begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:104:8 + assign ap_clmul = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:105:8 + assign ap_clmulh = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:106:8 + assign ap_clmulr = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:109:4 + generate + if (pt[2187-:5] == 1) begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:111:8 + assign ap_grev = mul_p[13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:112:8 + assign ap_gorc = mul_p[12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:113:8 + assign ap_shfl = mul_p[11]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:114:8 + assign ap_unshfl = mul_p[10]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:115:8 + assign ap_xperm_n = mul_p[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:116:8 + assign ap_xperm_b = mul_p[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:117:8 + assign ap_xperm_h = mul_p[0]; + end + else begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:121:8 + assign ap_grev = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:122:8 + assign ap_gorc = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:123:8 + assign ap_shfl = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:124:8 + assign ap_unshfl = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:125:8 + assign ap_xperm_n = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:126:8 + assign ap_xperm_b = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:127:8 + assign ap_xperm_h = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:130:4 + generate + if (pt[2182-:5] == 1) begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:132:8 + assign ap_crc32_b = mul_p[9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:133:8 + assign ap_crc32_h = mul_p[8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:134:8 + assign ap_crc32_w = mul_p[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:135:8 + assign ap_crc32c_b = mul_p[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:136:8 + assign ap_crc32c_h = mul_p[5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:137:8 + assign ap_crc32c_w = mul_p[4]; + end + else begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:141:8 + assign ap_crc32_b = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:142:8 + assign ap_crc32_h = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:143:8 + assign ap_crc32_w = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:144:8 + assign ap_crc32c_b = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:145:8 + assign ap_crc32c_h = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:146:8 + assign ap_crc32c_w = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:149:4 + generate + if (pt[2192-:5] == 1) begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:151:8 + assign ap_bfp = mul_p[3]; + end + else begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:155:8 + assign ap_bfp = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:163:4 + assign mul_x_enable = mul_p[22]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:164:4 + assign bit_x_enable = mul_p[22]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:166:4 + assign rs1_ext_in[32] = mul_p[21] & rs1_in[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:167:4 + assign rs2_ext_in[32] = mul_p[20] & rs2_in[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:169:4 + assign rs1_ext_in[31:0] = rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:170:4 + assign rs2_ext_in[31:0] = rs2_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:177:4 + wire signed [32:0] rs1_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:178:4 + wire signed [32:0] rs2_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:180:4 + rvdffe #(.WIDTH(34)) i_a_x_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .din({mul_p[19], rs1_ext_in[32:0]}), + .dout({low_x, rs1_x[32:0]}), + .en(mul_x_enable) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:181:4 + rvdffe #(.WIDTH(33)) i_b_x_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .din(rs2_ext_in[32:0]), + .dout(rs2_x[32:0]), + .en(mul_x_enable) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:184:4 + assign prod_x[65:0] = rs1_x * rs2_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:194:4 + reg [31:0] bcompress_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:195:4 + reg bcompress_test_bit_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:196:4 + integer bcompress_i; + integer bcompress_j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:199:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:202:8 + bcompress_j = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:203:8 + bcompress_test_bit_d = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:204:8 + bcompress_d[31:0] = 32'b00000000000000000000000000000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:206:8 + for (bcompress_i = 0; bcompress_i < 32; bcompress_i = bcompress_i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:208:14 + bcompress_test_bit_d = rs2_in[bcompress_i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:209:14 + if (bcompress_test_bit_d) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:211:19 + bcompress_d[bcompress_j] = rs1_in[bcompress_i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:212:19 + bcompress_j = bcompress_j + 1; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:221:4 + reg [31:0] bdecompress_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:222:4 + reg bdecompress_test_bit_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:223:4 + integer bdecompress_i; + integer bdecompress_j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:226:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:229:8 + bdecompress_j = 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:230:8 + bdecompress_test_bit_d = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:231:8 + bdecompress_d[31:0] = 32'b00000000000000000000000000000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:233:8 + for (bdecompress_i = 0; bdecompress_i < 32; bdecompress_i = bdecompress_i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:235:14 + bdecompress_test_bit_d = rs2_in[bdecompress_i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:236:14 + if (bdecompress_test_bit_d) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:238:19 + bdecompress_d[bdecompress_i] = rs1_in[bdecompress_j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:239:19 + bdecompress_j = bdecompress_j + 1; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:249:4 + wire [62:0] clmul_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:252:4 + assign clmul_raw_d[62:0] = ((((((((((((((((((((((((((((((({63 {rs2_in[0]}} & {31'b0000000000000000000000000000000, rs1_in[31:0]}) ^ ({63 {rs2_in[1]}} & {30'b000000000000000000000000000000, rs1_in[31:0], 1'b0})) ^ ({63 {rs2_in[2]}} & {29'b00000000000000000000000000000, rs1_in[31:0], 2'b00})) ^ ({63 {rs2_in[3]}} & {28'b0000000000000000000000000000, rs1_in[31:0], 3'b000})) ^ ({63 {rs2_in[4]}} & {27'b000000000000000000000000000, rs1_in[31:0], 4'b0000})) ^ ({63 {rs2_in[5]}} & {26'b00000000000000000000000000, rs1_in[31:0], 5'b00000})) ^ ({63 {rs2_in[6]}} & {25'b0000000000000000000000000, rs1_in[31:0], 6'b000000})) ^ ({63 {rs2_in[7]}} & {24'b000000000000000000000000, rs1_in[31:0], 7'b0000000})) ^ ({63 {rs2_in[8]}} & {23'b00000000000000000000000, rs1_in[31:0], 8'b00000000})) ^ ({63 {rs2_in[9]}} & {22'b0000000000000000000000, rs1_in[31:0], 9'b000000000})) ^ ({63 {rs2_in[10]}} & {21'b000000000000000000000, rs1_in[31:0], 10'b0000000000})) ^ ({63 {rs2_in[11]}} & {20'b00000000000000000000, rs1_in[31:0], 11'b00000000000})) ^ ({63 {rs2_in[12]}} & {19'b0000000000000000000, rs1_in[31:0], 12'b000000000000})) ^ ({63 {rs2_in[13]}} & {18'b000000000000000000, rs1_in[31:0], 13'b0000000000000})) ^ ({63 {rs2_in[14]}} & {17'b00000000000000000, rs1_in[31:0], 14'b00000000000000})) ^ ({63 {rs2_in[15]}} & {16'b0000000000000000, rs1_in[31:0], 15'b000000000000000})) ^ ({63 {rs2_in[16]}} & {15'b000000000000000, rs1_in[31:0], 16'b0000000000000000})) ^ ({63 {rs2_in[17]}} & {14'b00000000000000, rs1_in[31:0], 17'b00000000000000000})) ^ ({63 {rs2_in[18]}} & {13'b0000000000000, rs1_in[31:0], 18'b000000000000000000})) ^ ({63 {rs2_in[19]}} & {12'b000000000000, rs1_in[31:0], 19'b0000000000000000000})) ^ ({63 {rs2_in[20]}} & {11'b00000000000, rs1_in[31:0], 20'b00000000000000000000})) ^ ({63 {rs2_in[21]}} & {10'b0000000000, rs1_in[31:0], 21'b000000000000000000000})) ^ ({63 {rs2_in[22]}} & {9'b000000000, rs1_in[31:0], 22'b0000000000000000000000})) ^ ({63 {rs2_in[23]}} & {8'b00000000, rs1_in[31:0], 23'b00000000000000000000000})) ^ ({63 {rs2_in[24]}} & {7'b0000000, rs1_in[31:0], 24'b000000000000000000000000})) ^ ({63 {rs2_in[25]}} & {6'b000000, rs1_in[31:0], 25'b0000000000000000000000000})) ^ ({63 {rs2_in[26]}} & {5'b00000, rs1_in[31:0], 26'b00000000000000000000000000})) ^ ({63 {rs2_in[27]}} & {4'b0000, rs1_in[31:0], 27'b000000000000000000000000000})) ^ ({63 {rs2_in[28]}} & {3'b000, rs1_in[31:0], 28'b0000000000000000000000000000})) ^ ({63 {rs2_in[29]}} & {2'b00, rs1_in[31:0], 29'b00000000000000000000000000000})) ^ ({63 {rs2_in[30]}} & {1'b0, rs1_in[31:0], 30'b000000000000000000000000000000})) ^ ({63 {rs2_in[31]}} & {rs1_in[31:0], 31'b0000000000000000000000000000000}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:305:4 + wire [31:0] grev1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:306:4 + wire [31:0] grev2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:307:4 + wire [31:0] grev4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:308:4 + wire [31:0] grev8_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:309:4 + wire [31:0] grev_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:312:4 + assign grev1_d[31:0] = (rs2_in[0] ? {rs1_in[30], rs1_in[31], rs1_in[28], rs1_in[29], rs1_in[26], rs1_in[27], rs1_in[24], rs1_in[25], rs1_in[22], rs1_in[23], rs1_in[20], rs1_in[21], rs1_in[18], rs1_in[19], rs1_in[16], rs1_in[17], rs1_in[14], rs1_in[15], rs1_in[12], rs1_in[13], rs1_in[10], rs1_in[11], rs1_in[8], rs1_in[9], rs1_in[6], rs1_in[7], rs1_in[4], rs1_in[5], rs1_in[2], rs1_in[3], rs1_in[0], rs1_in[1]} : rs1_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:317:4 + assign grev2_d[31:0] = (rs2_in[1] ? {grev1_d[29:28], grev1_d[31:30], grev1_d[25:24], grev1_d[27:26], grev1_d[21:20], grev1_d[23:22], grev1_d[17:16], grev1_d[19:18], grev1_d[13:12], grev1_d[15:14], grev1_d[9:8], grev1_d[11:10], grev1_d[5:4], grev1_d[7:6], grev1_d[1:0], grev1_d[3:2]} : grev1_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:322:4 + assign grev4_d[31:0] = (rs2_in[2] ? {grev2_d[27:24], grev2_d[31:28], grev2_d[19:16], grev2_d[23:20], grev2_d[11:8], grev2_d[15:12], grev2_d[3:0], grev2_d[7:4]} : grev2_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:325:4 + assign grev8_d[31:0] = (rs2_in[3] ? {grev4_d[23:16], grev4_d[31:24], grev4_d[7:0], grev4_d[15:8]} : grev4_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:327:4 + assign grev_d[31:0] = (rs2_in[4] ? {grev8_d[15:0], grev8_d[31:16]} : grev8_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:349:4 + wire [31:0] gorc1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:350:4 + wire [31:0] gorc2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:351:4 + wire [31:0] gorc4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:352:4 + wire [31:0] gorc8_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:353:4 + wire [31:0] gorc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:356:4 + assign gorc1_d[31:0] = ({32 {rs2_in[0]}} & {rs1_in[30], rs1_in[31], rs1_in[28], rs1_in[29], rs1_in[26], rs1_in[27], rs1_in[24], rs1_in[25], rs1_in[22], rs1_in[23], rs1_in[20], rs1_in[21], rs1_in[18], rs1_in[19], rs1_in[16], rs1_in[17], rs1_in[14], rs1_in[15], rs1_in[12], rs1_in[13], rs1_in[10], rs1_in[11], rs1_in[8], rs1_in[9], rs1_in[6], rs1_in[7], rs1_in[4], rs1_in[5], rs1_in[2], rs1_in[3], rs1_in[0], rs1_in[1]}) | rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:361:4 + assign gorc2_d[31:0] = ({32 {rs2_in[1]}} & {gorc1_d[29:28], gorc1_d[31:30], gorc1_d[25:24], gorc1_d[27:26], gorc1_d[21:20], gorc1_d[23:22], gorc1_d[17:16], gorc1_d[19:18], gorc1_d[13:12], gorc1_d[15:14], gorc1_d[9:8], gorc1_d[11:10], gorc1_d[5:4], gorc1_d[7:6], gorc1_d[1:0], gorc1_d[3:2]}) | gorc1_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:366:4 + assign gorc4_d[31:0] = ({32 {rs2_in[2]}} & {gorc2_d[27:24], gorc2_d[31:28], gorc2_d[19:16], gorc2_d[23:20], gorc2_d[11:8], gorc2_d[15:12], gorc2_d[3:0], gorc2_d[7:4]}) | gorc2_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:369:4 + assign gorc8_d[31:0] = ({32 {rs2_in[3]}} & {gorc4_d[23:16], gorc4_d[31:24], gorc4_d[7:0], gorc4_d[15:8]}) | gorc4_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:371:4 + assign gorc_d[31:0] = ({32 {rs2_in[4]}} & {gorc8_d[15:0], gorc8_d[31:16]}) | gorc8_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:401:4 + wire [31:0] shfl8_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:402:4 + wire [31:0] shfl4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:403:4 + wire [31:0] shfl2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:404:4 + wire [31:0] shfl_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:408:4 + assign shfl8_d[31:0] = (rs2_in[3] ? {rs1_in[31:24], rs1_in[15:8], rs1_in[23:16], rs1_in[7:0]} : rs1_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:410:4 + assign shfl4_d[31:0] = (rs2_in[2] ? {shfl8_d[31:28], shfl8_d[23:20], shfl8_d[27:24], shfl8_d[19:16], shfl8_d[15:12], shfl8_d[7:4], shfl8_d[11:8], shfl8_d[3:0]} : shfl8_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:413:4 + assign shfl2_d[31:0] = (rs2_in[1] ? {shfl4_d[31:30], shfl4_d[27:26], shfl4_d[29:28], shfl4_d[25:24], shfl4_d[23:22], shfl4_d[19:18], shfl4_d[21:20], shfl4_d[17:16], shfl4_d[15:14], shfl4_d[11:10], shfl4_d[13:12], shfl4_d[9:8], shfl4_d[7:6], shfl4_d[3:2], shfl4_d[5:4], shfl4_d[1:0]} : shfl4_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:418:4 + assign shfl_d[31:0] = (rs2_in[0] ? {shfl2_d[31], shfl2_d[29], shfl2_d[30], shfl2_d[28], shfl2_d[27], shfl2_d[25], shfl2_d[26], shfl2_d[24], shfl2_d[23], shfl2_d[21], shfl2_d[22], shfl2_d[20], shfl2_d[19], shfl2_d[17], shfl2_d[18], shfl2_d[16], shfl2_d[15], shfl2_d[13], shfl2_d[14], shfl2_d[12], shfl2_d[11], shfl2_d[9], shfl2_d[10], shfl2_d[8], shfl2_d[7], shfl2_d[5], shfl2_d[6], shfl2_d[4], shfl2_d[3], shfl2_d[1], shfl2_d[2], shfl2_d[0]} : shfl2_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:440:4 + wire [31:0] unshfl1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:441:4 + wire [31:0] unshfl2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:442:4 + wire [31:0] unshfl4_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:443:4 + wire [31:0] unshfl_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:446:4 + assign unshfl1_d[31:0] = (rs2_in[0] ? {rs1_in[31], rs1_in[29], rs1_in[30], rs1_in[28], rs1_in[27], rs1_in[25], rs1_in[26], rs1_in[24], rs1_in[23], rs1_in[21], rs1_in[22], rs1_in[20], rs1_in[19], rs1_in[17], rs1_in[18], rs1_in[16], rs1_in[15], rs1_in[13], rs1_in[14], rs1_in[12], rs1_in[11], rs1_in[9], rs1_in[10], rs1_in[8], rs1_in[7], rs1_in[5], rs1_in[6], rs1_in[4], rs1_in[3], rs1_in[1], rs1_in[2], rs1_in[0]} : rs1_in[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:451:4 + assign unshfl2_d[31:0] = (rs2_in[1] ? {unshfl1_d[31:30], unshfl1_d[27:26], unshfl1_d[29:28], unshfl1_d[25:24], unshfl1_d[23:22], unshfl1_d[19:18], unshfl1_d[21:20], unshfl1_d[17:16], unshfl1_d[15:14], unshfl1_d[11:10], unshfl1_d[13:12], unshfl1_d[9:8], unshfl1_d[7:6], unshfl1_d[3:2], unshfl1_d[5:4], unshfl1_d[1:0]} : unshfl1_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:456:4 + assign unshfl4_d[31:0] = (rs2_in[2] ? {unshfl2_d[31:28], unshfl2_d[23:20], unshfl2_d[27:24], unshfl2_d[19:16], unshfl2_d[15:12], unshfl2_d[7:4], unshfl2_d[11:8], unshfl2_d[3:0]} : unshfl2_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:459:4 + assign unshfl_d[31:0] = (rs2_in[3] ? {unshfl4_d[31:24], unshfl4_d[15:8], unshfl4_d[23:16], unshfl4_d[7:0]} : unshfl4_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:522:4 + wire [31:0] xperm_n; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:523:4 + wire [31:0] xperm_b; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:524:4 + wire [31:0] xperm_h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:526:4 + assign xperm_n[3:0] = {4 {~rs2_in[3]}} & ((rs1_in[31:0] >> {rs2_in[2:0], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:527:4 + assign xperm_n[7:4] = {4 {~rs2_in[7]}} & ((rs1_in[31:0] >> {rs2_in[6:4], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:528:4 + assign xperm_n[11:8] = {4 {~rs2_in[11]}} & ((rs1_in[31:0] >> {rs2_in[10:8], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:529:4 + assign xperm_n[15:12] = {4 {~rs2_in[15]}} & ((rs1_in[31:0] >> {rs2_in[14:12], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:530:4 + assign xperm_n[19:16] = {4 {~rs2_in[19]}} & ((rs1_in[31:0] >> {rs2_in[18:16], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:531:4 + assign xperm_n[23:20] = {4 {~rs2_in[23]}} & ((rs1_in[31:0] >> {rs2_in[22:20], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:532:4 + assign xperm_n[27:24] = {4 {~rs2_in[27]}} & ((rs1_in[31:0] >> {rs2_in[26:24], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:533:4 + assign xperm_n[31:28] = {4 {~rs2_in[31]}} & ((rs1_in[31:0] >> {rs2_in[30:28], 2'b00}) & 4'hf); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:535:4 + assign xperm_b[7:0] = {8 {~(|rs2_in[7:2])}} & ((rs1_in[31:0] >> {rs2_in[1:0], 3'b000}) & 8'hff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:536:4 + assign xperm_b[15:8] = {8 {~(|rs2_in[15:10])}} & ((rs1_in[31:0] >> {rs2_in[9:8], 3'b000}) & 8'hff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:537:4 + assign xperm_b[23:16] = {8 {~(|rs2_in[23:18])}} & ((rs1_in[31:0] >> {rs2_in[17:16], 3'b000}) & 8'hff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:538:4 + assign xperm_b[31:24] = {8 {~(|rs2_in[31:26])}} & ((rs1_in[31:0] >> {rs2_in[25:24], 3'b000}) & 8'hff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:540:4 + assign xperm_h[15:0] = {16 {~(|rs2_in[15:1])}} & ((rs1_in[31:0] >> {rs2_in[0], 4'b0000}) & 16'hffff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:541:4 + assign xperm_h[31:16] = {16 {~(|rs2_in[31:17])}} & ((rs1_in[31:0] >> {rs2_in[16], 4'b0000}) & 16'hffff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:574:4 + wire crc32_all; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:575:4 + wire [31:0] crc32_poly_rev; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:576:4 + wire [31:0] crc32c_poly_rev; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:577:4 + integer crc32_bi; + integer crc32_hi; + integer crc32_wi; + integer crc32c_bi; + integer crc32c_hi; + integer crc32c_wi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:578:4 + reg [31:0] crc32_bd; + reg [31:0] crc32_hd; + reg [31:0] crc32_wd; + reg [31:0] crc32c_bd; + reg [31:0] crc32c_hd; + reg [31:0] crc32c_wd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:581:4 + assign crc32_all = ((((ap_crc32_b | ap_crc32_h) | ap_crc32_w) | ap_crc32c_b) | ap_crc32c_h) | ap_crc32c_w; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:583:4 + assign crc32_poly_rev[31:0] = 32'hedb88320; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:584:4 + assign crc32c_poly_rev[31:0] = 32'h82f63b78; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:587:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:589:8 + crc32_bd[31:0] = rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:591:8 + for (crc32_bi = 0; crc32_bi < 8; crc32_bi = crc32_bi + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:593:13 + crc32_bd[31:0] = (crc32_bd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32 {crc32_bd[0]}}); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:598:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:600:8 + crc32_hd[31:0] = rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:602:8 + for (crc32_hi = 0; crc32_hi < 16; crc32_hi = crc32_hi + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:604:13 + crc32_hd[31:0] = (crc32_hd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32 {crc32_hd[0]}}); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:609:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:611:8 + crc32_wd[31:0] = rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:613:8 + for (crc32_wi = 0; crc32_wi < 32; crc32_wi = crc32_wi + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:615:13 + crc32_wd[31:0] = (crc32_wd[31:0] >> 1) ^ (crc32_poly_rev[31:0] & {32 {crc32_wd[0]}}); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:622:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:624:8 + crc32c_bd[31:0] = rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:626:8 + for (crc32c_bi = 0; crc32c_bi < 8; crc32c_bi = crc32c_bi + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:628:13 + crc32c_bd[31:0] = (crc32c_bd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32 {crc32c_bd[0]}}); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:633:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:635:8 + crc32c_hd[31:0] = rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:637:8 + for (crc32c_hi = 0; crc32c_hi < 16; crc32c_hi = crc32c_hi + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:639:13 + crc32c_hd[31:0] = (crc32c_hd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32 {crc32c_hd[0]}}); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:644:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:646:8 + crc32c_wd[31:0] = rs1_in[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:648:8 + for (crc32c_wi = 0; crc32c_wi < 32; crc32c_wi = crc32c_wi + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:650:13 + crc32c_wd[31:0] = (crc32c_wd[31:0] >> 1) ^ (crc32c_poly_rev[31:0] & {32 {crc32c_wd[0]}}); + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:673:4 + wire [4:0] bfp_len; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:674:4 + wire [4:0] bfp_off; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:675:4 + wire [31:0] bfp_len_mask_; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:676:4 + wire [31:0] bfp_off_mask_; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:677:4 + wire [15:0] bfp_preshift_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:678:4 + wire [31:0] bfp_shift_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:679:4 + wire [31:0] bfp_shift_mask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:680:4 + wire [31:0] bfp_result_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:683:4 + assign bfp_len[3:0] = rs2_in[27:24]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:684:4 + assign bfp_len[4] = bfp_len[3:0] == 4'b0000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:685:4 + assign bfp_off[4:0] = rs2_in[20:16]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:687:4 + assign bfp_len_mask_[31:0] = 32'hffffffff << bfp_len[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:688:4 + assign bfp_off_mask_[31:0] = 32'hffffffff << bfp_off[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:689:4 + assign bfp_preshift_data[15:0] = rs2_in[15:0] & ~bfp_len_mask_[15:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:691:4 + assign bfp_shift_data[31:0] = {16'b0000000000000000, bfp_preshift_data[15:0]} << bfp_off[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:692:4 + assign bfp_shift_mask[31:0] = (bfp_len_mask_[31:0] << bfp_off[4:0]) | ~bfp_off_mask_[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:694:4 + assign bfp_result_d[31:0] = bfp_shift_data[31:0] | (rs1_in[31:0] & bfp_shift_mask[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:702:4 + assign bitmanip_sel_d = ((((((((((((ap_bcompress | ap_bdecompress) | ap_clmul) | ap_clmulh) | ap_clmulr) | ap_grev) | ap_gorc) | ap_shfl) | ap_unshfl) | crc32_all) | ap_bfp) | ap_xperm_n) | ap_xperm_b) | ap_xperm_h; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:704:4 + assign bitmanip_d[31:0] = (((((((((((((((((({32 {ap_bcompress}} & bcompress_d[31:0]) | ({32 {ap_bdecompress}} & bdecompress_d[31:0])) | ({32 {ap_clmul}} & clmul_raw_d[31:0])) | ({32 {ap_clmulh}} & {1'b0, clmul_raw_d[62:32]})) | ({32 {ap_clmulr}} & clmul_raw_d[62:31])) | ({32 {ap_grev}} & grev_d[31:0])) | ({32 {ap_gorc}} & gorc_d[31:0])) | ({32 {ap_shfl}} & shfl_d[31:0])) | ({32 {ap_unshfl}} & unshfl_d[31:0])) | ({32 {ap_crc32_b}} & crc32_bd[31:0])) | ({32 {ap_crc32_h}} & crc32_hd[31:0])) | ({32 {ap_crc32_w}} & crc32_wd[31:0])) | ({32 {ap_crc32c_b}} & crc32c_bd[31:0])) | ({32 {ap_crc32c_h}} & crc32c_hd[31:0])) | ({32 {ap_crc32c_w}} & crc32c_wd[31:0])) | ({32 {ap_bfp}} & bfp_result_d[31:0])) | ({32 {ap_xperm_n}} & xperm_n[31:0])) | ({32 {ap_xperm_b}} & xperm_b[31:0])) | ({32 {ap_xperm_h}} & xperm_h[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:726:4 + rvdffe #(.WIDTH(33)) i_bitmanip_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .din({bitmanip_sel_d, bitmanip_d[31:0]}), + .dout({bitmanip_sel_x, bitmanip_x[31:0]}), + .en(bit_x_enable) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_mul_ctl.sv:731:4 + assign result_x[31:0] = (({32 {~bitmanip_sel_x & ~low_x}} & prod_x[63:32]) | ({32 {~bitmanip_sel_x & low_x}} & prod_x[31:0])) | bitmanip_x[31:0]; + initial _sv2v_0 = 0; +endmodule +module el2_exu_div_ctl ( + clk, + rst_l, + scan_mode, + dp, + dividend, + divisor, + cancel, + finish_dly, + out +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:23:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:24:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:25:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:27:4 + // removed localparam type el2_pkg_el2_div_pkt_t + input wire [2:0] dp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:28:4 + input wire [31:0] dividend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:29:4 + input wire [31:0] divisor; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:31:4 + input wire cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:34:4 + output wire finish_dly; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:35:4 + output wire [31:0] out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:39:4 + wire [31:0] out_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:41:4 + assign out[31:0] = {32 {finish_dly}} & out_raw[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:45:4 + generate + if (pt[1262-:5] == 0) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:47:9 + el2_exu_div_existing_1bit_cheapshortq i_existing_1bit_div_cheapshortq( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .cancel(cancel), + .valid_in(dp[2]), + .signed_in(~dp[1]), + .rem_in(dp[0]), + .dividend_in(dividend[31:0]), + .divisor_in(divisor[31:0]), + .valid_out(finish_dly), + .data_out(out_raw[31:0]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:62:4 + generate + if ((pt[1262-:5] == 1) & (pt[1269-:7] == 1)) begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:64:9 + el2_exu_div_new_1bit_fullshortq i_new_1bit_div_fullshortq( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .cancel(cancel), + .valid_in(dp[2]), + .signed_in(~dp[1]), + .rem_in(dp[0]), + .dividend_in(dividend[31:0]), + .divisor_in(divisor[31:0]), + .valid_out(finish_dly), + .data_out(out_raw[31:0]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:79:4 + generate + if ((pt[1262-:5] == 1) & (pt[1269-:7] == 2)) begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:81:9 + el2_exu_div_new_2bit_fullshortq i_new_2bit_div_fullshortq( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .cancel(cancel), + .valid_in(dp[2]), + .signed_in(~dp[1]), + .rem_in(dp[0]), + .dividend_in(dividend[31:0]), + .divisor_in(divisor[31:0]), + .valid_out(finish_dly), + .data_out(out_raw[31:0]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:96:4 + generate + if ((pt[1262-:5] == 1) & (pt[1269-:7] == 3)) begin : genblk4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:98:9 + el2_exu_div_new_3bit_fullshortq i_new_3bit_div_fullshortq( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .cancel(cancel), + .valid_in(dp[2]), + .signed_in(~dp[1]), + .rem_in(dp[0]), + .dividend_in(dividend[31:0]), + .divisor_in(divisor[31:0]), + .valid_out(finish_dly), + .data_out(out_raw[31:0]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:113:4 + generate + if ((pt[1262-:5] == 1) & (pt[1269-:7] == 4)) begin : genblk5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:115:9 + el2_exu_div_new_4bit_fullshortq i_new_4bit_div_fullshortq( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .cancel(cancel), + .valid_in(dp[2]), + .signed_in(~dp[1]), + .rem_in(dp[0]), + .dividend_in(dividend[31:0]), + .divisor_in(divisor[31:0]), + .valid_out(finish_dly), + .data_out(out_raw[31:0]) + ); + end + endgenerate +endmodule +module el2_exu_div_existing_1bit_cheapshortq ( + clk, + rst_l, + scan_mode, + cancel, + valid_in, + signed_in, + rem_in, + dividend_in, + divisor_in, + valid_out, + data_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:141:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:142:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:143:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:145:4 + input wire cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:146:4 + input wire valid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:147:4 + input wire signed_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:148:4 + input wire rem_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:149:4 + input wire [31:0] dividend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:150:4 + input wire [31:0] divisor_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:152:4 + output wire valid_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:153:4 + output wire [31:0] data_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:157:4 + wire div_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:158:4 + wire run_in; + wire run_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:159:4 + wire [5:0] count_in; + wire [5:0] count; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:160:4 + wire [32:0] m_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:161:4 + wire qff_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:162:4 + wire aff_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:163:4 + wire [32:0] q_in; + wire [32:0] q_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:164:4 + wire [32:0] a_in; + wire [32:0] a_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:165:4 + wire [32:0] m_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:166:4 + wire [32:0] a_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:167:4 + wire dividend_neg_ff; + wire divisor_neg_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:168:4 + wire [31:0] dividend_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:169:4 + wire [31:0] dividend_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:170:4 + wire [31:0] q_ff_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:171:4 + wire [31:0] q_ff_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:172:4 + wire [31:0] a_ff_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:173:4 + wire [31:0] a_ff_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:174:4 + wire sign_ff; + wire sign_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:175:4 + wire rem_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:176:4 + wire add; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:177:4 + wire [32:0] a_eff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:178:4 + wire [64:0] a_eff_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:179:4 + wire rem_correct; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:180:4 + wire valid_ff_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:181:4 + wire valid_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:182:4 + wire finish; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:183:4 + wire finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:185:4 + wire smallnum_case; + wire smallnum_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:186:4 + wire [3:0] smallnum; + wire [3:0] smallnum_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:187:4 + wire m_already_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:189:4 + wire [4:0] a_cls; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:190:4 + wire [4:0] b_cls; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:191:4 + wire [5:0] shortq_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:192:4 + wire [5:0] shortq_shift_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:193:4 + wire [5:0] shortq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:194:4 + wire shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:195:4 + wire shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:196:4 + wire [32:0] short_dividend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:197:4 + wire [3:0] shortq_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:198:4 + wire [3:0] shortq_shift_xx; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:202:4 + rvdffe #(.WIDTH(23)) i_misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(div_clken), + .din({valid_in & ~cancel, finish & ~cancel, run_in, count_in[5:0], (valid_in & dividend_in[31]) | (~valid_in & dividend_neg_ff), (valid_in & divisor_in[31]) | (~valid_in & divisor_neg_ff), (valid_in & sign_eff) | (~valid_in & sign_ff), (valid_in & rem_in) | (~valid_in & rem_ff), smallnum_case, smallnum[3:0], shortq_enable, shortq_shift[3:0]}), + .dout({valid_ff_x, finish_ff, run_state, count[5:0], dividend_neg_ff, divisor_neg_ff, sign_ff, rem_ff, smallnum_case_ff, smallnum_ff[3:0], shortq_enable_ff, shortq_shift_xx[3:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:229:4 + rvdffe #(.WIDTH(33)) mff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(valid_in), + .din({signed_in & divisor_in[31], divisor_in[31:0]}), + .dout(m_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:230:4 + rvdffe #(.WIDTH(33)) qff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(qff_enable), + .din(q_in[32:0]), + .dout(q_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:231:4 + rvdffe #(.WIDTH(33)) aff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(aff_enable), + .din(a_in[32:0]), + .dout(a_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:233:4 + rvtwoscomp #(.WIDTH(32)) i_dividend_comp( + .din(q_ff[31:0]), + .dout(dividend_comp[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:234:4 + rvtwoscomp #(.WIDTH(32)) i_q_ff_comp( + .din(q_ff[31:0]), + .dout(q_ff_comp[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:235:4 + rvtwoscomp #(.WIDTH(32)) i_a_ff_comp( + .din(a_ff[31:0]), + .dout(a_ff_comp[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:238:4 + assign valid_x = valid_ff_x & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:249:4 + assign smallnum_case = (((((q_ff[31:4] == 28'b0000000000000000000000000000) & (m_ff[31:4] == 28'b0000000000000000000000000000)) & (m_ff[31:0] != 32'b00000000000000000000000000000000)) & ~rem_ff) & valid_x) | ((((q_ff[31:0] == 32'b00000000000000000000000000000000) & (m_ff[31:0] != 32'b00000000000000000000000000000000)) & ~rem_ff) & valid_x); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:253:4 + assign smallnum[3] = ((q_ff[3] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:256:4 + assign smallnum[2] = ((((q_ff[3] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[0]) | (((q_ff[2] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & q_ff[2]) & ~m_ff[3]) & ~m_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:261:4 + assign smallnum[1] = ((((((((((q_ff[2] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[0]) | (((q_ff[1] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & ~m_ff[3]) & ~m_ff[1]) & ~m_ff[0])) | (((((q_ff[3] & ~q_ff[2]) & ~m_ff[3]) & ~m_ff[2]) & m_ff[1]) & m_ff[0])) | ((((~q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & ~m_ff[2])) | (((q_ff[3] & q_ff[2]) & ~m_ff[3]) & ~m_ff[0])) | ((((q_ff[3] & q_ff[2]) & ~m_ff[3]) & m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & q_ff[1]) & ~m_ff[3]) & ~m_ff[1])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & m_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:272:4 + assign smallnum[0] = ((((((((((((((((((((((((((((q_ff[2] & q_ff[1]) & q_ff[0]) & ~m_ff[3]) & ~m_ff[1]) | (((((q_ff[3] & ~q_ff[2]) & q_ff[0]) & ~m_ff[3]) & m_ff[1]) & m_ff[0])) | (((q_ff[2] & ~m_ff[3]) & ~m_ff[1]) & ~m_ff[0])) | (((q_ff[1] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[0])) | (((q_ff[0] & ~m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | ((((((~q_ff[3] & q_ff[2]) & ~q_ff[1]) & ~m_ff[3]) & ~m_ff[2]) & m_ff[1]) & m_ff[0])) | ((((~q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & ~m_ff[0])) | (((q_ff[3] & ~m_ff[2]) & ~m_ff[1]) & ~m_ff[0])) | ((((q_ff[3] & ~q_ff[2]) & ~m_ff[3]) & m_ff[2]) & m_ff[1])) | (((((~q_ff[3] & q_ff[2]) & q_ff[1]) & ~m_ff[3]) & m_ff[2]) & ~m_ff[1])) | ((((~q_ff[3] & q_ff[2]) & q_ff[0]) & ~m_ff[3]) & ~m_ff[1])) | (((((q_ff[3] & ~q_ff[2]) & ~q_ff[1]) & ~m_ff[3]) & m_ff[2]) & m_ff[0])) | ((((~q_ff[2] & q_ff[1]) & q_ff[0]) & ~m_ff[3]) & ~m_ff[2])) | (((q_ff[3] & q_ff[2]) & ~m_ff[1]) & ~m_ff[0])) | (((q_ff[3] & q_ff[1]) & ~m_ff[2]) & ~m_ff[0])) | (((((~q_ff[3] & q_ff[2]) & q_ff[1]) & q_ff[0]) & ~m_ff[3]) & m_ff[2])) | (((q_ff[3] & q_ff[2]) & m_ff[3]) & ~m_ff[2])) | ((((q_ff[3] & q_ff[1]) & m_ff[3]) & ~m_ff[2]) & ~m_ff[1])) | (((q_ff[3] & q_ff[0]) & ~m_ff[2]) & ~m_ff[1])) | (((((q_ff[3] & ~q_ff[1]) & ~m_ff[3]) & m_ff[2]) & m_ff[1]) & m_ff[0])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & m_ff[3]) & ~m_ff[0])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & m_ff[3]) & ~m_ff[1])) | ((((q_ff[3] & q_ff[2]) & q_ff[0]) & m_ff[3]) & ~m_ff[1])) | ((((q_ff[3] & ~q_ff[2]) & q_ff[1]) & ~m_ff[3]) & m_ff[1])) | (((q_ff[3] & q_ff[1]) & q_ff[0]) & ~m_ff[2])) | ((((q_ff[3] & q_ff[2]) & q_ff[1]) & q_ff[0]) & m_ff[3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:305:4 + assign short_dividend[31:0] = q_ff[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:306:4 + assign short_dividend[32] = sign_ff & q_ff[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:329:4 + assign a_cls[4:3] = 2'b00; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:330:4 + assign a_cls[2] = (~short_dividend[32] & (short_dividend[31:24] != {8 {1'b0}})) | (short_dividend[32] & (short_dividend[31:23] != {9 {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:331:4 + assign a_cls[1] = (~short_dividend[32] & (short_dividend[23:16] != {8 {1'b0}})) | (short_dividend[32] & (short_dividend[22:15] != {8 {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:332:4 + assign a_cls[0] = (~short_dividend[32] & (short_dividend[15:8] != {8 {1'b0}})) | (short_dividend[32] & (short_dividend[14:7] != {8 {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:334:4 + assign b_cls[4:3] = 2'b00; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:335:4 + assign b_cls[2] = (~m_ff[32] & (m_ff[31:24] != {8 {1'b0}})) | (m_ff[32] & (m_ff[31:24] != {8 {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:336:4 + assign b_cls[1] = (~m_ff[32] & (m_ff[23:16] != {8 {1'b0}})) | (m_ff[32] & (m_ff[23:16] != {8 {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:337:4 + assign b_cls[0] = (~m_ff[32] & (m_ff[15:8] != {8 {1'b0}})) | (m_ff[32] & (m_ff[15:8] != {8 {1'b1}})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:339:4 + assign shortq_raw[3] = ((((((a_cls[2:1] == 2'b01) & (b_cls[2] == 1'b1)) | ((a_cls[2:0] == 3'b001) & (b_cls[2] == 1'b1))) | ((a_cls[2:0] == 3'b000) & (b_cls[2] == 1'b1))) | ((a_cls[2:0] == 3'b001) & (b_cls[2:1] == 2'b01))) | ((a_cls[2:0] == 3'b000) & (b_cls[2:1] == 2'b01))) | ((a_cls[2:0] == 3'b000) & (b_cls[2:0] == 3'b001)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:346:4 + assign shortq_raw[2] = ((((a_cls[2] == 1'b1) & (b_cls[2] == 1'b1)) | ((a_cls[2:1] == 2'b01) & (b_cls[2:1] == 2'b01))) | ((a_cls[2:0] == 3'b001) & (b_cls[2:0] == 3'b001))) | ((a_cls[2:0] == 3'b000) & (b_cls[2:0] == 3'b000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:351:4 + assign shortq_raw[1] = (((a_cls[2] == 1'b1) & (b_cls[2:1] == 2'b01)) | ((a_cls[2:1] == 2'b01) & (b_cls[2:0] == 3'b001))) | ((a_cls[2:0] == 3'b001) & (b_cls[2:0] == 3'b000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:355:4 + assign shortq_raw[0] = ((a_cls[2] == 1'b1) & (b_cls[2:0] == 3'b001)) | ((a_cls[2:1] == 2'b01) & (b_cls[2:0] == 3'b000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:359:4 + assign shortq_enable = (valid_ff_x & (m_ff[31:0] != 32'b00000000000000000000000000000000)) & (shortq_raw[3:0] != 4'b0000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:361:4 + assign shortq_shift[3:0] = {4 {shortq_enable}} & shortq_raw[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:363:4 + assign shortq[5:0] = 6'b000000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:364:4 + assign shortq_shift[5:4] = 2'b00; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:365:4 + assign shortq_shift_ff[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:367:4 + assign shortq_shift_ff[4:0] = ((({5 {shortq_shift_xx[3]}} & 5'b11111) | ({5 {shortq_shift_xx[2]}} & 5'b11000)) | ({5 {shortq_shift_xx[1]}} & 5'b10000)) | ({5 {shortq_shift_xx[0]}} & 5'b01000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:378:4 + assign div_clken = ((valid_in | run_state) | finish) | finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:380:4 + assign run_in = ((valid_in | run_state) & ~finish) & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:382:4 + assign count_in[5:0] = {6 {((run_state & ~finish) & ~cancel) & ~shortq_enable}} & ((count[5:0] + {1'b0, shortq_shift_ff[4:0]}) + 6'd1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:385:4 + assign finish = smallnum_case | (~rem_ff ? count[5:0] == 6'd32 : count[5:0] == 6'd33); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:387:4 + assign valid_out = finish_ff & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:389:4 + assign sign_eff = signed_in & (divisor_in[31:0] != 32'b00000000000000000000000000000000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:392:4 + assign q_in[32:0] = (({33 {~run_state}} & {1'b0, dividend_in[31:0]}) | ({33 {run_state & (valid_ff_x | shortq_enable_ff)}} & ({dividend_eff[31:0], ~a_in[32]} << shortq_shift_ff[4:0]))) | ({33 {run_state & ~(valid_ff_x | shortq_enable_ff)}} & {q_ff[31:0], ~a_in[32]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:396:4 + assign qff_enable = valid_in | (run_state & ~shortq_enable); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:401:4 + assign dividend_eff[31:0] = (sign_ff & dividend_neg_ff ? dividend_comp[31:0] : q_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:404:4 + assign m_eff[32:0] = (add ? m_ff[32:0] : ~m_ff[32:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:406:4 + assign a_eff_shift[64:0] = {33'b000000000000000000000000000000000, dividend_eff[31:0]} << shortq_shift_ff[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:408:4 + assign a_eff[32:0] = (({33 {rem_correct}} & a_ff[32:0]) | ({33 {~rem_correct & ~shortq_enable_ff}} & {a_ff[31:0], q_ff[32]})) | ({33 {~rem_correct & shortq_enable_ff}} & a_eff_shift[64:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:412:4 + assign a_shift[32:0] = {33 {run_state}} & a_eff[32:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:414:4 + assign a_in[32:0] = {33 {run_state}} & ((a_shift[32:0] + m_eff[32:0]) + {32'b00000000000000000000000000000000, ~add}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:416:4 + assign aff_enable = (valid_in | ((run_state & ~shortq_enable) & (count[5:0] != 6'd33))) | rem_correct; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:419:4 + assign m_already_comp = divisor_neg_ff & sign_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:422:4 + assign add = (a_ff[32] | rem_correct) ^ m_already_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:424:4 + assign rem_correct = ((count[5:0] == 6'd33) & rem_ff) & a_ff[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:428:4 + assign q_ff_eff[31:0] = (sign_ff & (dividend_neg_ff ^ divisor_neg_ff) ? q_ff_comp[31:0] : q_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:430:4 + assign a_ff_eff[31:0] = (sign_ff & dividend_neg_ff ? a_ff_comp[31:0] : a_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:432:4 + assign data_out[31:0] = (({32 {smallnum_case_ff}} & {28'b0000000000000000000000000000, smallnum_ff[3:0]}) | ({32 {rem_ff}} & a_ff_eff[31:0])) | ({32 {~smallnum_case_ff & ~rem_ff}} & q_ff_eff[31:0]); +endmodule +module el2_exu_div_new_1bit_fullshortq ( + clk, + rst_l, + scan_mode, + cancel, + valid_in, + signed_in, + rem_in, + dividend_in, + divisor_in, + valid_out, + data_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:449:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:450:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:451:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:453:4 + input wire cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:454:4 + input wire valid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:455:4 + input wire signed_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:456:4 + input wire rem_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:457:4 + input wire [31:0] dividend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:458:4 + input wire [31:0] divisor_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:460:4 + output wire valid_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:461:4 + output wire [31:0] data_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:465:4 + wire valid_ff_in; + wire valid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:466:4 + wire finish_raw; + wire finish; + wire finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:467:4 + wire running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:468:4 + wire misc_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:469:4 + wire [2:0] control_in; + wire [2:0] control_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:470:4 + wire dividend_sign_ff; + wire divisor_sign_ff; + wire rem_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:471:4 + wire count_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:472:4 + wire [6:0] count_in; + wire [6:0] count_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:474:4 + wire smallnum_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:475:4 + wire [3:0] smallnum; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:477:4 + wire a_enable; + wire a_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:478:4 + wire [31:0] a_in; + wire [31:0] a_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:480:4 + wire b_enable; + wire b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:481:4 + wire [32:0] b_in; + wire [32:0] b_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:483:4 + wire [31:0] q_in; + wire [31:0] q_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:485:4 + wire rq_enable; + wire r_sign_sel; + wire r_restore_sel; + wire r_adder_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:486:4 + wire [31:0] r_in; + wire [31:0] r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:488:4 + wire twos_comp_q_sel; + wire twos_comp_b_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:489:4 + wire [31:0] twos_comp_in; + wire [31:0] twos_comp_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:491:4 + wire quotient_set; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:492:4 + wire [32:0] adder_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:494:4 + wire [63:0] ar_shifted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:495:4 + wire [5:0] shortq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:496:4 + wire [4:0] shortq_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:497:4 + wire [4:0] shortq_shift_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:498:4 + wire shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:499:4 + wire shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:500:4 + wire [32:0] shortq_dividend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:502:4 + wire by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:503:4 + wire by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:507:4 + rvdffe #(.WIDTH(19)) i_misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(misc_enable), + .din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}), + .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:510:4 + rvdffe #(.WIDTH(32)) i_a_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(a_enable), + .din(a_in[31:0]), + .dout(a_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:511:4 + rvdffe #(.WIDTH(33)) i_b_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(b_enable), + .din(b_in[32:0]), + .dout(b_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:512:4 + rvdffe #(.WIDTH(32)) i_r_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(r_in[31:0]), + .dout(r_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:513:4 + rvdffe #(.WIDTH(32)) i_q_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(q_in[31:0]), + .dout(q_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:518:4 + assign valid_ff_in = valid_in & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:520:4 + assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:521:4 + assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:522:4 + assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:524:4 + assign dividend_sign_ff = control_ff[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:525:4 + assign divisor_sign_ff = control_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:526:4 + assign rem_ff = control_ff[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:529:4 + assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:531:4 + assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:532:4 + assign running_state = |count_ff[6:0] | shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:533:4 + assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd32); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:538:4 + assign finish = finish_raw & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:539:4 + assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:540:4 + assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'b0000001) + {2'b00, shortq_shift_ff[4:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:543:4 + assign a_enable = valid_in | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:544:4 + assign a_shift = running_state & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:546:4 + assign ar_shifted[63:0] = {{32 {dividend_sign_ff}}, a_ff[31:0]} << shortq_shift_ff[4:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:548:4 + assign a_in[31:0] = (({32 {~a_shift & ~shortq_enable_ff}} & dividend_in[31:0]) | ({32 {a_shift}} & {a_ff[30:0], 1'b0})) | ({32 {shortq_enable_ff}} & ar_shifted[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:554:4 + assign b_enable = valid_in | b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:555:4 + assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:557:4 + assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:561:4 + assign rq_enable = (valid_in | valid_ff) | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:562:4 + assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:563:4 + assign r_restore_sel = (running_state & ~quotient_set) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:564:4 + assign r_adder_sel = (running_state & quotient_set) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:567:4 + assign r_in[31:0] = (((({32 {r_sign_sel}} & 32'hffffffff) | ({32 {r_restore_sel}} & {r_ff[30:0], a_ff[31]})) | ({32 {r_adder_sel}} & adder_out[31:0])) | ({32 {shortq_enable_ff}} & ar_shifted[63:32])) | ({32 {by_zero_case}} & a_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:574:4 + assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[30:0], quotient_set}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:580:4 + assign adder_out[32:0] = {r_ff[31:0], a_ff[31]} + {b_ff[32:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:583:4 + assign quotient_set = (~adder_out[32] ^ dividend_sign_ff) | ((a_ff[30:0] == 31'b0000000000000000000000000000000) & (adder_out[32:0] == 33'b000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:587:4 + assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:588:4 + assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:590:4 + assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:593:4 + rvtwoscomp #(.WIDTH(32)) i_twos_comp( + .din(twos_comp_in[31:0]), + .dout(twos_comp_out[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:597:4 + assign valid_out = finish_ff & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:599:4 + assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:608:4 + assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:611:4 + assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:613:4 + assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:617:4 + assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:627:4 + assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:661:4 + assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:664:4 + wire [5:0] dw_a_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:665:4 + wire [5:0] dw_b_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:666:4 + wire [6:0] dw_shortq_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:670:4 + el2_exu_div_cls i_a_cls( + .operand(shortq_dividend[32:0]), + .cls(dw_a_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:674:4 + el2_exu_div_cls i_b_cls( + .operand(b_ff[32:0]), + .cls(dw_b_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:678:4 + assign dw_a_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:679:4 + assign dw_b_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:683:4 + assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:684:4 + assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:686:4 + assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:1] == 4'b1111)) & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:688:4 + assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : 5'b11111 - shortq[4:0]); +endmodule +module el2_exu_div_new_2bit_fullshortq ( + clk, + rst_l, + scan_mode, + cancel, + valid_in, + signed_in, + rem_in, + dividend_in, + divisor_in, + valid_out, + data_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:707:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:708:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:709:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:711:4 + input wire cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:712:4 + input wire valid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:713:4 + input wire signed_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:714:4 + input wire rem_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:715:4 + input wire [31:0] dividend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:716:4 + input wire [31:0] divisor_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:718:4 + output wire valid_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:719:4 + output wire [31:0] data_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:723:4 + wire valid_ff_in; + wire valid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:724:4 + wire finish_raw; + wire finish; + wire finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:725:4 + wire running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:726:4 + wire misc_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:727:4 + wire [2:0] control_in; + wire [2:0] control_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:728:4 + wire dividend_sign_ff; + wire divisor_sign_ff; + wire rem_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:729:4 + wire count_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:730:4 + wire [6:0] count_in; + wire [6:0] count_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:732:4 + wire smallnum_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:733:4 + wire [3:0] smallnum; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:735:4 + wire a_enable; + wire a_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:736:4 + wire [31:0] a_in; + wire [31:0] a_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:738:4 + wire b_enable; + wire b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:739:4 + wire [32:0] b_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:740:4 + wire [34:0] b_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:742:4 + wire [31:0] q_in; + wire [31:0] q_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:744:4 + wire rq_enable; + wire r_sign_sel; + wire r_restore_sel; + wire r_adder1_sel; + wire r_adder2_sel; + wire r_adder3_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:745:4 + wire [31:0] r_in; + wire [31:0] r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:747:4 + wire twos_comp_q_sel; + wire twos_comp_b_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:748:4 + wire [31:0] twos_comp_in; + wire [31:0] twos_comp_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:750:4 + wire [3:1] quotient_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:751:4 + wire [1:0] quotient_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:752:4 + wire [32:0] adder1_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:753:4 + wire [33:0] adder2_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:754:4 + wire [34:0] adder3_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:756:4 + wire [63:0] ar_shifted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:757:4 + wire [5:0] shortq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:758:4 + wire [4:0] shortq_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:759:4 + wire [4:1] shortq_shift_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:760:4 + wire shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:761:4 + wire shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:762:4 + wire [32:0] shortq_dividend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:764:4 + wire by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:765:4 + wire by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:769:4 + rvdffe #(.WIDTH(18)) i_misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(misc_enable), + .din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:1], finish, count_in[6:0]}), + .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:1], finish_ff, count_ff[6:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:772:4 + rvdffe #(.WIDTH(32)) i_a_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(a_enable), + .din(a_in[31:0]), + .dout(a_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:773:4 + rvdffe #(.WIDTH(33)) i_b_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(b_enable), + .din(b_in[32:0]), + .dout(b_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:774:4 + rvdffe #(.WIDTH(32)) i_r_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(r_in[31:0]), + .dout(r_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:775:4 + rvdffe #(.WIDTH(32)) i_q_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(q_in[31:0]), + .dout(q_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:780:4 + assign valid_ff_in = valid_in & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:782:4 + assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:783:4 + assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:784:4 + assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:786:4 + assign dividend_sign_ff = control_ff[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:787:4 + assign divisor_sign_ff = control_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:788:4 + assign rem_ff = control_ff[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:791:4 + assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:793:4 + assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:794:4 + assign running_state = |count_ff[6:0] | shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:795:4 + assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd32); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:800:4 + assign finish = finish_raw & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:801:4 + assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:802:4 + assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'b0000010) + {2'b00, shortq_shift_ff[4:1], 1'b0}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:805:4 + assign a_enable = valid_in | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:806:4 + assign a_shift = running_state & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:808:4 + assign ar_shifted[63:0] = {{32 {dividend_sign_ff}}, a_ff[31:0]} << {shortq_shift_ff[4:1], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:810:4 + assign a_in[31:0] = (({32 {~a_shift & ~shortq_enable_ff}} & dividend_in[31:0]) | ({32 {a_shift}} & {a_ff[29:0], 2'b00})) | ({32 {shortq_enable_ff}} & ar_shifted[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:816:4 + assign b_enable = valid_in | b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:817:4 + assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:819:4 + assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:823:4 + assign rq_enable = (valid_in | valid_ff) | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:824:4 + assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:825:4 + assign r_restore_sel = (running_state & (quotient_new[1:0] == 2'b00)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:826:4 + assign r_adder1_sel = (running_state & (quotient_new[1:0] == 2'b01)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:827:4 + assign r_adder2_sel = (running_state & (quotient_new[1:0] == 2'b10)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:828:4 + assign r_adder3_sel = (running_state & (quotient_new[1:0] == 2'b11)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:831:4 + assign r_in[31:0] = (((((({32 {r_sign_sel}} & 32'hffffffff) | ({32 {r_restore_sel}} & {r_ff[29:0], a_ff[31:30]})) | ({32 {r_adder1_sel}} & adder1_out[31:0])) | ({32 {r_adder2_sel}} & adder2_out[31:0])) | ({32 {r_adder3_sel}} & adder3_out[31:0])) | ({32 {shortq_enable_ff}} & ar_shifted[63:32])) | ({32 {by_zero_case}} & a_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:840:4 + assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[29:0], quotient_new[1:0]}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:845:4 + assign b_ff[34:33] = {b_ff[32], b_ff[32]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:848:4 + assign adder1_out[32:0] = {r_ff[30:0], a_ff[31:30]} + b_ff[32:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:849:4 + assign adder2_out[33:0] = {r_ff[31:0], a_ff[31:30]} + {b_ff[32:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:850:4 + assign adder3_out[34:0] = ({r_ff[31], r_ff[31:0], a_ff[31:30]} + {b_ff[33:0], 1'b0}) + b_ff[34:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:853:4 + assign quotient_raw[1] = (~adder1_out[32] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder1_out[32:0] == 33'b000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:854:4 + assign quotient_raw[2] = (~adder2_out[33] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder2_out[33:0] == 34'b0000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:855:4 + assign quotient_raw[3] = (~adder3_out[34] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder3_out[34:0] == 35'b00000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:857:4 + assign quotient_new[1] = quotient_raw[3] | quotient_raw[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:858:4 + assign quotient_new[0] = quotient_raw[3] | (~quotient_raw[2] & quotient_raw[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:861:4 + assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:862:4 + assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:864:4 + assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:867:4 + rvtwoscomp #(.WIDTH(32)) i_twos_comp( + .din(twos_comp_in[31:0]), + .dout(twos_comp_out[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:871:4 + assign valid_out = finish_ff & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:873:4 + assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:882:4 + assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:885:4 + assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:887:4 + assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:891:4 + assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:901:4 + assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:935:4 + assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:938:4 + wire [5:0] dw_a_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:939:4 + wire [5:0] dw_b_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:940:4 + wire [6:0] dw_shortq_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:944:4 + el2_exu_div_cls i_a_cls( + .operand(shortq_dividend[32:0]), + .cls(dw_a_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:948:4 + el2_exu_div_cls i_b_cls( + .operand(b_ff[32:0]), + .cls(dw_b_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:952:4 + assign dw_a_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:953:4 + assign dw_b_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:957:4 + assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:958:4 + assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:960:4 + assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:1] == 4'b1111)) & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:962:4 + assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : 5'b11111 - shortq[4:0]); +endmodule +module el2_exu_div_new_3bit_fullshortq ( + clk, + rst_l, + scan_mode, + cancel, + valid_in, + signed_in, + rem_in, + dividend_in, + divisor_in, + valid_out, + data_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:981:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:982:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:983:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:985:4 + input wire cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:986:4 + input wire valid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:987:4 + input wire signed_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:988:4 + input wire rem_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:989:4 + input wire [31:0] dividend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:990:4 + input wire [31:0] divisor_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:992:4 + output wire valid_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:993:4 + output wire [31:0] data_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:997:4 + wire valid_ff_in; + wire valid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:998:4 + wire finish_raw; + wire finish; + wire finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:999:4 + wire running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1000:4 + wire misc_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1001:4 + wire [2:0] control_in; + wire [2:0] control_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1002:4 + wire dividend_sign_ff; + wire divisor_sign_ff; + wire rem_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1003:4 + wire count_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1004:4 + wire [6:0] count_in; + wire [6:0] count_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1006:4 + wire smallnum_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1007:4 + wire [3:0] smallnum; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1009:4 + wire a_enable; + wire a_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1010:4 + wire [32:0] a_in; + wire [32:0] a_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1012:4 + wire b_enable; + wire b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1013:4 + wire [32:0] b_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1014:4 + wire [36:0] b_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1016:4 + wire [31:0] q_in; + wire [31:0] q_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1018:4 + wire rq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1019:4 + wire r_sign_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1020:4 + wire r_restore_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1021:4 + wire r_adder1_sel; + wire r_adder2_sel; + wire r_adder3_sel; + wire r_adder4_sel; + wire r_adder5_sel; + wire r_adder6_sel; + wire r_adder7_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1022:4 + wire [32:0] r_in; + wire [32:0] r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1024:4 + wire twos_comp_q_sel; + wire twos_comp_b_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1025:4 + wire [31:0] twos_comp_in; + wire [31:0] twos_comp_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1027:4 + wire [7:1] quotient_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1028:4 + wire [2:0] quotient_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1029:4 + wire [33:0] adder1_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1030:4 + wire [34:0] adder2_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1031:4 + wire [35:0] adder3_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1032:4 + wire [36:0] adder4_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1033:4 + wire [36:0] adder5_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1034:4 + wire [36:0] adder6_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1035:4 + wire [36:0] adder7_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1037:4 + wire [65:0] ar_shifted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1038:4 + wire [5:0] shortq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1039:4 + wire [4:0] shortq_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1040:4 + wire [4:0] shortq_decode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1041:4 + wire [4:0] shortq_shift_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1042:4 + wire shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1043:4 + wire shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1044:4 + wire [32:0] shortq_dividend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1046:4 + wire by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1047:4 + wire by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1051:4 + rvdffe #(.WIDTH(19)) i_misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(misc_enable), + .din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}), + .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1054:4 + rvdffe #(.WIDTH(33)) i_a_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(a_enable), + .din(a_in[32:0]), + .dout(a_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1055:4 + rvdffe #(.WIDTH(33)) i_b_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(b_enable), + .din(b_in[32:0]), + .dout(b_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1056:4 + rvdffe #(.WIDTH(33)) i_r_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(r_in[32:0]), + .dout(r_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1057:4 + rvdffe #(.WIDTH(32)) i_q_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(q_in[31:0]), + .dout(q_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1062:4 + assign valid_ff_in = valid_in & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1064:4 + assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1065:4 + assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1066:4 + assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1068:4 + assign dividend_sign_ff = control_ff[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1069:4 + assign divisor_sign_ff = control_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1070:4 + assign rem_ff = control_ff[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1073:4 + assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1075:4 + assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1076:4 + assign running_state = |count_ff[6:0] | shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1077:4 + assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd33); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1082:4 + assign finish = finish_raw & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1083:4 + assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1084:4 + assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'b0000011) + {2'b00, shortq_shift_ff[4:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1087:4 + assign a_enable = valid_in | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1088:4 + assign a_shift = running_state & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1090:4 + assign ar_shifted[65:0] = {{33 {dividend_sign_ff}}, a_ff[32:0]} << {shortq_shift_ff[4:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1092:4 + assign a_in[32:0] = (({33 {~a_shift & ~shortq_enable_ff}} & {signed_in & dividend_in[31], dividend_in[31:0]}) | ({33 {a_shift}} & {a_ff[29:0], 3'b000})) | ({33 {shortq_enable_ff}} & ar_shifted[32:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1098:4 + assign b_enable = valid_in | b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1099:4 + assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1101:4 + assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1105:4 + assign rq_enable = (valid_in | valid_ff) | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1106:4 + assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1107:4 + assign r_restore_sel = (running_state & (quotient_new[2:0] == 3'b000)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1108:4 + assign r_adder1_sel = (running_state & (quotient_new[2:0] == 3'b001)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1109:4 + assign r_adder2_sel = (running_state & (quotient_new[2:0] == 3'b010)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1110:4 + assign r_adder3_sel = (running_state & (quotient_new[2:0] == 3'b011)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1111:4 + assign r_adder4_sel = (running_state & (quotient_new[2:0] == 3'b100)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1112:4 + assign r_adder5_sel = (running_state & (quotient_new[2:0] == 3'b101)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1113:4 + assign r_adder6_sel = (running_state & (quotient_new[2:0] == 3'b110)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1114:4 + assign r_adder7_sel = (running_state & (quotient_new[2:0] == 3'b111)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1117:4 + assign r_in[32:0] = (((((((((({33 {r_sign_sel}} & {33 {1'b1}}) | ({33 {r_restore_sel}} & {r_ff[29:0], a_ff[32:30]})) | ({33 {r_adder1_sel}} & adder1_out[32:0])) | ({33 {r_adder2_sel}} & adder2_out[32:0])) | ({33 {r_adder3_sel}} & adder3_out[32:0])) | ({33 {r_adder4_sel}} & adder4_out[32:0])) | ({33 {r_adder5_sel}} & adder5_out[32:0])) | ({33 {r_adder6_sel}} & adder6_out[32:0])) | ({33 {r_adder7_sel}} & adder7_out[32:0])) | ({33 {shortq_enable_ff}} & ar_shifted[65:33])) | ({33 {by_zero_case}} & {1'b0, a_ff[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1130:4 + assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[28:0], quotient_new[2:0]}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1135:4 + assign b_ff[36:33] = {b_ff[32], b_ff[32], b_ff[32], b_ff[32]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1138:4 + assign adder1_out[33:0] = {r_ff[30:0], a_ff[32:30]} + b_ff[33:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1139:4 + assign adder2_out[34:0] = {r_ff[31:0], a_ff[32:30]} + {b_ff[33:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1140:4 + assign adder3_out[35:0] = ({r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 1'b0}) + b_ff[35:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1141:4 + assign adder4_out[36:0] = {r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1142:4 + assign adder5_out[36:0] = ({r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00}) + b_ff[36:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1143:4 + assign adder6_out[36:0] = ({r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00}) + {b_ff[35:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1144:4 + assign adder7_out[36:0] = (({r_ff[32], r_ff[32:0], a_ff[32:30]} + {b_ff[34:0], 2'b00}) + {b_ff[35:0], 1'b0}) + b_ff[36:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1146:4 + assign quotient_raw[1] = (~adder1_out[33] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder1_out[33:0] == 34'b0000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1147:4 + assign quotient_raw[2] = (~adder2_out[34] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder2_out[34:0] == 35'b00000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1148:4 + assign quotient_raw[3] = (~adder3_out[35] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder3_out[35:0] == 36'b000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1149:4 + assign quotient_raw[4] = (~adder4_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder4_out[36:0] == 37'b0000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1150:4 + assign quotient_raw[5] = (~adder5_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder5_out[36:0] == 37'b0000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1151:4 + assign quotient_raw[6] = (~adder6_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder6_out[36:0] == 37'b0000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1152:4 + assign quotient_raw[7] = (~adder7_out[36] ^ dividend_sign_ff) | ((a_ff[29:0] == 30'b000000000000000000000000000000) & (adder7_out[36:0] == 37'b0000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1154:4 + assign quotient_new[2] = ((quotient_raw[7] | quotient_raw[6]) | quotient_raw[5]) | quotient_raw[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1155:4 + assign quotient_new[1] = ((quotient_raw[7] | quotient_raw[6]) | (~quotient_raw[4] & quotient_raw[3])) | (~quotient_raw[3] & quotient_raw[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1156:4 + assign quotient_new[0] = ((quotient_raw[7] | (~quotient_raw[6] & quotient_raw[5])) | (~quotient_raw[4] & quotient_raw[3])) | (~quotient_raw[2] & quotient_raw[1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1159:4 + assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1160:4 + assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1162:4 + assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1165:4 + rvtwoscomp #(.WIDTH(32)) i_twos_comp( + .din(twos_comp_in[31:0]), + .dout(twos_comp_out[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1169:4 + assign valid_out = finish_ff & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1171:4 + assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1180:4 + assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1183:4 + assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1185:4 + assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1189:4 + assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1199:4 + assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1233:4 + assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1236:4 + wire [5:0] dw_a_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1237:4 + wire [5:0] dw_b_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1238:4 + wire [6:0] dw_shortq_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1242:4 + el2_exu_div_cls i_a_cls( + .operand(shortq_dividend[32:0]), + .cls(dw_a_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1246:4 + el2_exu_div_cls i_b_cls( + .operand(b_ff[32:0]), + .cls(dw_b_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1250:4 + assign dw_a_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1251:4 + assign dw_b_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1255:4 + assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1256:4 + assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1258:4 + assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:2] == 3'b111)) & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1260:4 + assign shortq_decode[4:0] = ((((((((((((((((((((((((((((((({5 {shortq[4:0] == 5'd31}} & 5'd0) | ({5 {shortq[4:0] == 5'd30}} & 5'd0)) | ({5 {shortq[4:0] == 5'd29}} & 5'd0)) | ({5 {shortq[4:0] == 5'd28}} & 5'd0)) | ({5 {shortq[4:0] == 5'd27}} & 5'd3)) | ({5 {shortq[4:0] == 5'd26}} & 5'd6)) | ({5 {shortq[4:0] == 5'd25}} & 5'd6)) | ({5 {shortq[4:0] == 5'd24}} & 5'd6)) | ({5 {shortq[4:0] == 5'd23}} & 5'd9)) | ({5 {shortq[4:0] == 5'd22}} & 5'd9)) | ({5 {shortq[4:0] == 5'd21}} & 5'd9)) | ({5 {shortq[4:0] == 5'd20}} & 5'd12)) | ({5 {shortq[4:0] == 5'd19}} & 5'd12)) | ({5 {shortq[4:0] == 5'd18}} & 5'd12)) | ({5 {shortq[4:0] == 5'd17}} & 5'd15)) | ({5 {shortq[4:0] == 5'd16}} & 5'd15)) | ({5 {shortq[4:0] == 5'd15}} & 5'd15)) | ({5 {shortq[4:0] == 5'd14}} & 5'd18)) | ({5 {shortq[4:0] == 5'd13}} & 5'd18)) | ({5 {shortq[4:0] == 5'd12}} & 5'd18)) | ({5 {shortq[4:0] == 5'd11}} & 5'd21)) | ({5 {shortq[4:0] == 5'd10}} & 5'd21)) | ({5 {shortq[4:0] == 5'd9}} & 5'd21)) | ({5 {shortq[4:0] == 5'd8}} & 5'd24)) | ({5 {shortq[4:0] == 5'd7}} & 5'd24)) | ({5 {shortq[4:0] == 5'd6}} & 5'd24)) | ({5 {shortq[4:0] == 5'd5}} & 5'd27)) | ({5 {shortq[4:0] == 5'd4}} & 5'd27)) | ({5 {shortq[4:0] == 5'd3}} & 5'd27)) | ({5 {shortq[4:0] == 5'd2}} & 5'd27)) | ({5 {shortq[4:0] == 5'd1}} & 5'd27)) | ({5 {shortq[4:0] == 5'd0}} & 5'd27); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1294:4 + assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : shortq_decode[4:0]); +endmodule +module el2_exu_div_new_4bit_fullshortq ( + clk, + rst_l, + scan_mode, + cancel, + valid_in, + signed_in, + rem_in, + dividend_in, + divisor_in, + valid_out, + data_out +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1313:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1314:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1315:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1317:4 + input wire cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1318:4 + input wire valid_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1319:4 + input wire signed_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1320:4 + input wire rem_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1321:4 + input wire [31:0] dividend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1322:4 + input wire [31:0] divisor_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1324:4 + output wire valid_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1325:4 + output wire [31:0] data_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1329:4 + wire valid_ff_in; + wire valid_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1330:4 + wire finish_raw; + wire finish; + wire finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1331:4 + wire running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1332:4 + wire misc_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1333:4 + wire [2:0] control_in; + wire [2:0] control_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1334:4 + wire dividend_sign_ff; + wire divisor_sign_ff; + wire rem_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1335:4 + wire count_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1336:4 + wire [6:0] count_in; + wire [6:0] count_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1338:4 + wire smallnum_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1339:4 + wire [3:0] smallnum; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1341:4 + wire a_enable; + wire a_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1342:4 + wire [31:0] a_in; + wire [31:0] a_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1344:4 + wire b_enable; + wire b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1345:4 + wire [32:0] b_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1346:4 + wire [37:0] b_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1348:4 + wire [31:0] q_in; + wire [31:0] q_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1350:4 + wire rq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1351:4 + wire r_sign_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1352:4 + wire r_restore_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1353:4 + wire r_adder01_sel; + wire r_adder02_sel; + wire r_adder03_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1354:4 + wire r_adder04_sel; + wire r_adder05_sel; + wire r_adder06_sel; + wire r_adder07_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1355:4 + wire r_adder08_sel; + wire r_adder09_sel; + wire r_adder10_sel; + wire r_adder11_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1356:4 + wire r_adder12_sel; + wire r_adder13_sel; + wire r_adder14_sel; + wire r_adder15_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1357:4 + wire [32:0] r_in; + wire [32:0] r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1359:4 + wire twos_comp_q_sel; + wire twos_comp_b_sel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1360:4 + wire [31:0] twos_comp_in; + wire [31:0] twos_comp_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1362:4 + wire [15:1] quotient_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1363:4 + wire [3:0] quotient_new; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1364:4 + wire [34:0] adder01_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1365:4 + wire [35:0] adder02_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1366:4 + wire [36:0] adder03_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1367:4 + wire [37:0] adder04_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1368:4 + wire [37:0] adder05_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1369:4 + wire [37:0] adder06_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1370:4 + wire [37:0] adder07_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1371:4 + wire [37:0] adder08_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1372:4 + wire [37:0] adder09_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1373:4 + wire [37:0] adder10_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1374:4 + wire [37:0] adder11_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1375:4 + wire [37:0] adder12_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1376:4 + wire [37:0] adder13_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1377:4 + wire [37:0] adder14_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1378:4 + wire [37:0] adder15_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1380:4 + wire [64:0] ar_shifted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1381:4 + wire [5:0] shortq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1382:4 + wire [4:0] shortq_shift; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1383:4 + wire [4:0] shortq_decode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1384:4 + wire [4:0] shortq_shift_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1385:4 + wire shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1386:4 + wire shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1387:4 + wire [32:0] shortq_dividend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1389:4 + wire by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1390:4 + wire by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1394:4 + rvdffe #(.WIDTH(19)) i_misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(misc_enable), + .din({valid_ff_in, control_in[2:0], by_zero_case, shortq_enable, shortq_shift[4:0], finish, count_in[6:0]}), + .dout({valid_ff, control_ff[2:0], by_zero_case_ff, shortq_enable_ff, shortq_shift_ff[4:0], finish_ff, count_ff[6:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1397:4 + rvdffe #(.WIDTH(32)) i_a_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(a_enable), + .din(a_in[31:0]), + .dout(a_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1398:4 + rvdffe #(.WIDTH(33)) i_b_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(b_enable), + .din(b_in[32:0]), + .dout(b_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1399:4 + rvdffe #(.WIDTH(33)) i_r_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(r_in[32:0]), + .dout(r_ff[32:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1400:4 + rvdffe #(.WIDTH(32)) i_q_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(rq_enable), + .din(q_in[31:0]), + .dout(q_ff[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1405:4 + assign valid_ff_in = valid_in & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1407:4 + assign control_in[2] = (~valid_in & control_ff[2]) | ((valid_in & signed_in) & dividend_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1408:4 + assign control_in[1] = (~valid_in & control_ff[1]) | ((valid_in & signed_in) & divisor_in[31]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1409:4 + assign control_in[0] = (~valid_in & control_ff[0]) | (valid_in & rem_in); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1411:4 + assign dividend_sign_ff = control_ff[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1412:4 + assign divisor_sign_ff = control_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1413:4 + assign rem_ff = control_ff[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1416:4 + assign by_zero_case = valid_ff & (b_ff[31:0] == 32'b00000000000000000000000000000000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1418:4 + assign misc_enable = (((valid_in | valid_ff) | cancel) | running_state) | finish_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1419:4 + assign running_state = |count_ff[6:0] | shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1420:4 + assign finish_raw = (smallnum_case | by_zero_case) | (count_ff[6:0] == 7'd32); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1425:4 + assign finish = finish_raw & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1426:4 + assign count_enable = ((((valid_ff | running_state) & ~finish) & ~finish_ff) & ~cancel) & ~shortq_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1427:4 + assign count_in[6:0] = {7 {count_enable}} & ((count_ff[6:0] + 7'd4) + {2'b00, shortq_shift_ff[4:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1430:4 + assign a_enable = valid_in | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1431:4 + assign a_shift = running_state & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1433:4 + assign ar_shifted[64:0] = {{33 {dividend_sign_ff}}, a_ff[31:0]} << {shortq_shift_ff[4:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1435:4 + assign a_in[31:0] = (({32 {~a_shift & ~shortq_enable_ff}} & dividend_in[31:0]) | ({32 {a_shift}} & {a_ff[27:0], 4'b0000})) | ({32 {shortq_enable_ff}} & ar_shifted[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1441:4 + assign b_enable = valid_in | b_twos_comp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1442:4 + assign b_twos_comp = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1444:4 + assign b_in[32:0] = ({33 {~b_twos_comp}} & {signed_in & divisor_in[31], divisor_in[31:0]}) | ({33 {b_twos_comp}} & {~divisor_sign_ff, twos_comp_out[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1448:4 + assign rq_enable = (valid_in | valid_ff) | running_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1449:4 + assign r_sign_sel = (valid_ff & dividend_sign_ff) & ~by_zero_case; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1450:4 + assign r_restore_sel = (running_state & (quotient_new[3:0] == 4'd0)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1451:4 + assign r_adder01_sel = (running_state & (quotient_new[3:0] == 4'd1)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1452:4 + assign r_adder02_sel = (running_state & (quotient_new[3:0] == 4'd2)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1453:4 + assign r_adder03_sel = (running_state & (quotient_new[3:0] == 4'd3)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1454:4 + assign r_adder04_sel = (running_state & (quotient_new[3:0] == 4'd4)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1455:4 + assign r_adder05_sel = (running_state & (quotient_new[3:0] == 4'd5)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1456:4 + assign r_adder06_sel = (running_state & (quotient_new[3:0] == 4'd6)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1457:4 + assign r_adder07_sel = (running_state & (quotient_new[3:0] == 4'd7)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1458:4 + assign r_adder08_sel = (running_state & (quotient_new[3:0] == 4'd8)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1459:4 + assign r_adder09_sel = (running_state & (quotient_new[3:0] == 4'd9)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1460:4 + assign r_adder10_sel = (running_state & (quotient_new[3:0] == 4'd10)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1461:4 + assign r_adder11_sel = (running_state & (quotient_new[3:0] == 4'd11)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1462:4 + assign r_adder12_sel = (running_state & (quotient_new[3:0] == 4'd12)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1463:4 + assign r_adder13_sel = (running_state & (quotient_new[3:0] == 4'd13)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1464:4 + assign r_adder14_sel = (running_state & (quotient_new[3:0] == 4'd14)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1465:4 + assign r_adder15_sel = (running_state & (quotient_new[3:0] == 4'd15)) & ~shortq_enable_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1467:4 + assign r_in[32:0] = (((((((((((((((((({33 {r_sign_sel}} & {33 {1'b1}}) | ({33 {r_restore_sel}} & {r_ff[28:0], a_ff[31:28]})) | ({33 {r_adder01_sel}} & adder01_out[32:0])) | ({33 {r_adder02_sel}} & adder02_out[32:0])) | ({33 {r_adder03_sel}} & adder03_out[32:0])) | ({33 {r_adder04_sel}} & adder04_out[32:0])) | ({33 {r_adder05_sel}} & adder05_out[32:0])) | ({33 {r_adder06_sel}} & adder06_out[32:0])) | ({33 {r_adder07_sel}} & adder07_out[32:0])) | ({33 {r_adder08_sel}} & adder08_out[32:0])) | ({33 {r_adder09_sel}} & adder09_out[32:0])) | ({33 {r_adder10_sel}} & adder10_out[32:0])) | ({33 {r_adder11_sel}} & adder11_out[32:0])) | ({33 {r_adder12_sel}} & adder12_out[32:0])) | ({33 {r_adder13_sel}} & adder13_out[32:0])) | ({33 {r_adder14_sel}} & adder14_out[32:0])) | ({33 {r_adder15_sel}} & adder15_out[32:0])) | ({33 {shortq_enable_ff}} & ar_shifted[64:32])) | ({33 {by_zero_case}} & {1'b0, a_ff[31:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1488:4 + assign q_in[31:0] = (({32 {~valid_ff}} & {q_ff[27:0], quotient_new[3:0]}) | ({32 {smallnum_case}} & {28'b0000000000000000000000000000, smallnum[3:0]})) | ({32 {by_zero_case}} & {32 {1'b1}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1493:4 + assign b_ff[37:33] = {b_ff[32], b_ff[32], b_ff[32], b_ff[32], b_ff[32]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1496:4 + assign adder01_out[34:0] = {r_ff[30:0], a_ff[31:28]} + b_ff[34:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1497:4 + assign adder02_out[35:0] = {r_ff[31:0], a_ff[31:28]} + {b_ff[34:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1498:4 + assign adder03_out[36:0] = ({r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 1'b0}) + b_ff[36:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1499:4 + assign adder04_out[37:0] = {r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1500:4 + assign adder05_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00}) + b_ff[37:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1501:4 + assign adder06_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1502:4 + assign adder07_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0}) + b_ff[37:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1503:4 + assign adder08_out[37:0] = {r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1504:4 + assign adder09_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + b_ff[37:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1505:4 + assign adder10_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[36:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1506:4 + assign adder11_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[36:0], 1'b0}) + b_ff[37:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1507:4 + assign adder12_out[37:0] = ({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1508:4 + assign adder13_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00}) + b_ff[37:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1509:4 + assign adder14_out[37:0] = (({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1510:4 + assign adder15_out[37:0] = ((({r_ff[32], r_ff[32:0], a_ff[31:28]} + {b_ff[34:0], 3'b000}) + {b_ff[35:0], 2'b00}) + {b_ff[36:0], 1'b0}) + b_ff[37:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1512:4 + assign quotient_raw[1] = (~adder01_out[34] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder01_out[34:0] == 35'b00000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1513:4 + assign quotient_raw[2] = (~adder02_out[35] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder02_out[35:0] == 36'b000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1514:4 + assign quotient_raw[3] = (~adder03_out[36] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder03_out[36:0] == 37'b0000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1515:4 + assign quotient_raw[4] = (~adder04_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder04_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1516:4 + assign quotient_raw[5] = (~adder05_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder05_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1517:4 + assign quotient_raw[6] = (~adder06_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder06_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1518:4 + assign quotient_raw[7] = (~adder07_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder07_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1519:4 + assign quotient_raw[8] = (~adder08_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder08_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1520:4 + assign quotient_raw[9] = (~adder09_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder09_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1521:4 + assign quotient_raw[10] = (~adder10_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder10_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1522:4 + assign quotient_raw[11] = (~adder11_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder11_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1523:4 + assign quotient_raw[12] = (~adder12_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder12_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1524:4 + assign quotient_raw[13] = (~adder13_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder13_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1525:4 + assign quotient_raw[14] = (~adder14_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder14_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1526:4 + assign quotient_raw[15] = (~adder15_out[37] ^ dividend_sign_ff) | ((a_ff[27:0] == 28'b0000000000000000000000000000) & (adder15_out[37:0] == 38'b00000000000000000000000000000000000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1529:4 + assign quotient_new[0] = (((((((quotient_raw[15:1] == 15'b000000000000001) | (quotient_raw[15:3] == 13'b0000000000001)) | (quotient_raw[15:5] == 11'b00000000001)) | (quotient_raw[15:7] == 9'b000000001)) | (quotient_raw[15:9] == 7'b0000001)) | (quotient_raw[15:11] == 5'b00001)) | (quotient_raw[15:13] == 3'b001)) | (quotient_raw[15] == 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1538:4 + assign quotient_new[1] = (((((((quotient_raw[15:2] == 14'b00000000000001) | (quotient_raw[15:3] == 13'b0000000000001)) | (quotient_raw[15:6] == 10'b0000000001)) | (quotient_raw[15:7] == 9'b000000001)) | (quotient_raw[15:10] == 6'b000001)) | (quotient_raw[15:11] == 5'b00001)) | (quotient_raw[15:14] == 2'b01)) | (quotient_raw[15] == 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1547:4 + assign quotient_new[2] = (((((((quotient_raw[15:4] == 12'b000000000001) | (quotient_raw[15:5] == 11'b00000000001)) | (quotient_raw[15:6] == 10'b0000000001)) | (quotient_raw[15:7] == 9'b000000001)) | (quotient_raw[15:12] == 4'b0001)) | (quotient_raw[15:13] == 3'b001)) | (quotient_raw[15:14] == 2'b01)) | (quotient_raw[15] == 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1556:4 + assign quotient_new[3] = (((((((quotient_raw[15:8] == 8'b00000001) | (quotient_raw[15:9] == 7'b0000001)) | (quotient_raw[15:10] == 6'b000001)) | (quotient_raw[15:11] == 5'b00001)) | (quotient_raw[15:12] == 4'b0001)) | (quotient_raw[15:13] == 3'b001)) | (quotient_raw[15:14] == 2'b01)) | (quotient_raw[15] == 1'b1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1566:4 + assign twos_comp_b_sel = valid_ff & ~(dividend_sign_ff ^ divisor_sign_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1567:4 + assign twos_comp_q_sel = ((~valid_ff & ~rem_ff) & (dividend_sign_ff ^ divisor_sign_ff)) & ~by_zero_case_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1569:4 + assign twos_comp_in[31:0] = ({32 {twos_comp_q_sel}} & q_ff[31:0]) | ({32 {twos_comp_b_sel}} & b_ff[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1572:4 + rvtwoscomp #(.WIDTH(32)) i_twos_comp( + .din(twos_comp_in[31:0]), + .dout(twos_comp_out[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1576:4 + assign valid_out = finish_ff & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1578:4 + assign data_out[31:0] = (({32 {~rem_ff & ~twos_comp_q_sel}} & q_ff[31:0]) | ({32 {rem_ff}} & r_ff[31:0])) | ({32 {twos_comp_q_sel}} & twos_comp_out[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1587:4 + assign smallnum_case = ((((((a_ff[31:4] == 28'b0000000000000000000000000000) & (b_ff[31:4] == 28'b0000000000000000000000000000)) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel) | (((((a_ff[31:0] == 32'b00000000000000000000000000000000) & ~by_zero_case) & ~rem_ff) & valid_ff) & ~cancel); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1590:4 + assign smallnum[3] = ((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1592:4 + assign smallnum[2] = ((((a_ff[3] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1596:4 + assign smallnum[1] = ((((((((((a_ff[2] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0]) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[1]) & ~b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1606:4 + assign smallnum[0] = ((((((((((((((((((((((((((((a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1]) | (((((a_ff[3] & ~a_ff[2]) & a_ff[0]) & ~b_ff[3]) & b_ff[1]) & b_ff[0])) | (((a_ff[2] & ~b_ff[3]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[1] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[0])) | (((a_ff[0] & ~b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | ((((((~a_ff[3] & a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & ~b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & ~b_ff[0])) | (((a_ff[3] & ~b_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | ((((a_ff[3] & ~a_ff[2]) & ~b_ff[3]) & b_ff[2]) & b_ff[1])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[2]) & ~b_ff[1])) | ((((~a_ff[3] & a_ff[2]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[2]) & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[0])) | ((((~a_ff[2] & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & ~b_ff[2])) | (((a_ff[3] & a_ff[2]) & ~b_ff[1]) & ~b_ff[0])) | (((a_ff[3] & a_ff[1]) & ~b_ff[2]) & ~b_ff[0])) | (((((~a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & ~b_ff[3]) & b_ff[2])) | (((a_ff[3] & a_ff[2]) & b_ff[3]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[1]) & b_ff[3]) & ~b_ff[2]) & ~b_ff[1])) | (((a_ff[3] & a_ff[0]) & ~b_ff[2]) & ~b_ff[1])) | (((((a_ff[3] & ~a_ff[1]) & ~b_ff[3]) & b_ff[2]) & b_ff[1]) & b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[0])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & a_ff[2]) & a_ff[0]) & b_ff[3]) & ~b_ff[1])) | ((((a_ff[3] & ~a_ff[2]) & a_ff[1]) & ~b_ff[3]) & b_ff[1])) | (((a_ff[3] & a_ff[1]) & a_ff[0]) & ~b_ff[2])) | ((((a_ff[3] & a_ff[2]) & a_ff[1]) & a_ff[0]) & b_ff[3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1640:4 + assign shortq_dividend[32:0] = {dividend_sign_ff, a_ff[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1643:4 + wire [5:0] dw_a_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1644:4 + wire [5:0] dw_b_enc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1645:4 + wire [6:0] dw_shortq_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1649:4 + el2_exu_div_cls i_a_cls( + .operand(shortq_dividend[32:0]), + .cls(dw_a_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1653:4 + el2_exu_div_cls i_b_cls( + .operand(b_ff[32:0]), + .cls(dw_b_enc[4:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1657:4 + assign dw_a_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1658:4 + assign dw_b_enc[5] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1661:4 + assign dw_shortq_raw[6:0] = ({1'b0, dw_b_enc[5:0]} - {1'b0, dw_a_enc[5:0]}) + 7'd1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1662:4 + assign shortq[5:0] = (dw_shortq_raw[6] ? 6'd0 : dw_shortq_raw[5:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1664:4 + assign shortq_enable = ((valid_ff & ~shortq[5]) & ~(shortq[4:2] == 3'b111)) & ~cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1666:4 + assign shortq_decode[4:0] = ((((((((((((((((((((((((((((((({5 {shortq[4:0] == 5'd31}} & 5'd0) | ({5 {shortq[4:0] == 5'd30}} & 5'd0)) | ({5 {shortq[4:0] == 5'd29}} & 5'd0)) | ({5 {shortq[4:0] == 5'd28}} & 5'd0)) | ({5 {shortq[4:0] == 5'd27}} & 5'd4)) | ({5 {shortq[4:0] == 5'd26}} & 5'd4)) | ({5 {shortq[4:0] == 5'd25}} & 5'd4)) | ({5 {shortq[4:0] == 5'd24}} & 5'd4)) | ({5 {shortq[4:0] == 5'd23}} & 5'd8)) | ({5 {shortq[4:0] == 5'd22}} & 5'd8)) | ({5 {shortq[4:0] == 5'd21}} & 5'd8)) | ({5 {shortq[4:0] == 5'd20}} & 5'd8)) | ({5 {shortq[4:0] == 5'd19}} & 5'd12)) | ({5 {shortq[4:0] == 5'd18}} & 5'd12)) | ({5 {shortq[4:0] == 5'd17}} & 5'd12)) | ({5 {shortq[4:0] == 5'd16}} & 5'd12)) | ({5 {shortq[4:0] == 5'd15}} & 5'd16)) | ({5 {shortq[4:0] == 5'd14}} & 5'd16)) | ({5 {shortq[4:0] == 5'd13}} & 5'd16)) | ({5 {shortq[4:0] == 5'd12}} & 5'd16)) | ({5 {shortq[4:0] == 5'd11}} & 5'd20)) | ({5 {shortq[4:0] == 5'd10}} & 5'd20)) | ({5 {shortq[4:0] == 5'd9}} & 5'd20)) | ({5 {shortq[4:0] == 5'd8}} & 5'd20)) | ({5 {shortq[4:0] == 5'd7}} & 5'd24)) | ({5 {shortq[4:0] == 5'd6}} & 5'd24)) | ({5 {shortq[4:0] == 5'd5}} & 5'd24)) | ({5 {shortq[4:0] == 5'd4}} & 5'd24)) | ({5 {shortq[4:0] == 5'd3}} & 5'd28)) | ({5 {shortq[4:0] == 5'd2}} & 5'd28)) | ({5 {shortq[4:0] == 5'd1}} & 5'd28)) | ({5 {shortq[4:0] == 5'd0}} & 5'd28); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1700:4 + assign shortq_shift[4:0] = (~shortq_enable ? 5'd0 : shortq_decode[4:0]); +endmodule +module el2_exu_div_cls ( + operand, + cls +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1720:4 + input wire [32:0] operand; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1722:4 + output wire [4:0] cls; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1726:4 + wire [4:0] cls_zeros; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1727:4 + wire [4:0] cls_ones; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1730:1 + assign cls_zeros[4:0] = (((((((((((((((((((((((((((((((({5 {operand[31] == 1'b1}} & 5'd0) | ({5 {operand[31:30] == 2'b01}} & 5'd1)) | ({5 {operand[31:29] == {{2 {1'b0}}, 1'b1}}} & 5'd2)) | ({5 {operand[31:28] == {{3 {1'b0}}, 1'b1}}} & 5'd3)) | ({5 {operand[31:27] == {{4 {1'b0}}, 1'b1}}} & 5'd4)) | ({5 {operand[31:26] == {{5 {1'b0}}, 1'b1}}} & 5'd5)) | ({5 {operand[31:25] == {{6 {1'b0}}, 1'b1}}} & 5'd6)) | ({5 {operand[31:24] == {{7 {1'b0}}, 1'b1}}} & 5'd7)) | ({5 {operand[31:23] == {{8 {1'b0}}, 1'b1}}} & 5'd8)) | ({5 {operand[31:22] == {{9 {1'b0}}, 1'b1}}} & 5'd9)) | ({5 {operand[31:21] == {{10 {1'b0}}, 1'b1}}} & 5'd10)) | ({5 {operand[31:20] == {{11 {1'b0}}, 1'b1}}} & 5'd11)) | ({5 {operand[31:19] == {{12 {1'b0}}, 1'b1}}} & 5'd12)) | ({5 {operand[31:18] == {{13 {1'b0}}, 1'b1}}} & 5'd13)) | ({5 {operand[31:17] == {{14 {1'b0}}, 1'b1}}} & 5'd14)) | ({5 {operand[31:16] == {{15 {1'b0}}, 1'b1}}} & 5'd15)) | ({5 {operand[31:15] == {{16 {1'b0}}, 1'b1}}} & 5'd16)) | ({5 {operand[31:14] == {{17 {1'b0}}, 1'b1}}} & 5'd17)) | ({5 {operand[31:13] == {{18 {1'b0}}, 1'b1}}} & 5'd18)) | ({5 {operand[31:12] == {{19 {1'b0}}, 1'b1}}} & 5'd19)) | ({5 {operand[31:11] == {{20 {1'b0}}, 1'b1}}} & 5'd20)) | ({5 {operand[31:10] == {{21 {1'b0}}, 1'b1}}} & 5'd21)) | ({5 {operand[31:9] == {{22 {1'b0}}, 1'b1}}} & 5'd22)) | ({5 {operand[31:8] == {{23 {1'b0}}, 1'b1}}} & 5'd23)) | ({5 {operand[31:7] == {{24 {1'b0}}, 1'b1}}} & 5'd24)) | ({5 {operand[31:6] == {{25 {1'b0}}, 1'b1}}} & 5'd25)) | ({5 {operand[31:5] == {{26 {1'b0}}, 1'b1}}} & 5'd26)) | ({5 {operand[31:4] == {{27 {1'b0}}, 1'b1}}} & 5'd27)) | ({5 {operand[31:3] == {{28 {1'b0}}, 1'b1}}} & 5'd28)) | ({5 {operand[31:2] == {{29 {1'b0}}, 1'b1}}} & 5'd29)) | ({5 {operand[31:1] == {{30 {1'b0}}, 1'b1}}} & 5'd30)) | ({5 {operand[31:0] == {{31 {1'b0}}, 1'b1}}} & 5'd31)) | ({5 {operand[31:0] == {32 {1'b0}}}} & 5'd0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1765:1 + assign cls_ones[4:0] = ((((((((((((((((((((((((((((((({5 {operand[31:30] == 2'b10}} & 5'd0) | ({5 {operand[31:29] == {{2 {1'b1}}, 1'b0}}} & 5'd1)) | ({5 {operand[31:28] == {{3 {1'b1}}, 1'b0}}} & 5'd2)) | ({5 {operand[31:27] == {{4 {1'b1}}, 1'b0}}} & 5'd3)) | ({5 {operand[31:26] == {{5 {1'b1}}, 1'b0}}} & 5'd4)) | ({5 {operand[31:25] == {{6 {1'b1}}, 1'b0}}} & 5'd5)) | ({5 {operand[31:24] == {{7 {1'b1}}, 1'b0}}} & 5'd6)) | ({5 {operand[31:23] == {{8 {1'b1}}, 1'b0}}} & 5'd7)) | ({5 {operand[31:22] == {{9 {1'b1}}, 1'b0}}} & 5'd8)) | ({5 {operand[31:21] == {{10 {1'b1}}, 1'b0}}} & 5'd9)) | ({5 {operand[31:20] == {{11 {1'b1}}, 1'b0}}} & 5'd10)) | ({5 {operand[31:19] == {{12 {1'b1}}, 1'b0}}} & 5'd11)) | ({5 {operand[31:18] == {{13 {1'b1}}, 1'b0}}} & 5'd12)) | ({5 {operand[31:17] == {{14 {1'b1}}, 1'b0}}} & 5'd13)) | ({5 {operand[31:16] == {{15 {1'b1}}, 1'b0}}} & 5'd14)) | ({5 {operand[31:15] == {{16 {1'b1}}, 1'b0}}} & 5'd15)) | ({5 {operand[31:14] == {{17 {1'b1}}, 1'b0}}} & 5'd16)) | ({5 {operand[31:13] == {{18 {1'b1}}, 1'b0}}} & 5'd17)) | ({5 {operand[31:12] == {{19 {1'b1}}, 1'b0}}} & 5'd18)) | ({5 {operand[31:11] == {{20 {1'b1}}, 1'b0}}} & 5'd19)) | ({5 {operand[31:10] == {{21 {1'b1}}, 1'b0}}} & 5'd20)) | ({5 {operand[31:9] == {{22 {1'b1}}, 1'b0}}} & 5'd21)) | ({5 {operand[31:8] == {{23 {1'b1}}, 1'b0}}} & 5'd22)) | ({5 {operand[31:7] == {{24 {1'b1}}, 1'b0}}} & 5'd23)) | ({5 {operand[31:6] == {{25 {1'b1}}, 1'b0}}} & 5'd24)) | ({5 {operand[31:5] == {{26 {1'b1}}, 1'b0}}} & 5'd25)) | ({5 {operand[31:4] == {{27 {1'b1}}, 1'b0}}} & 5'd26)) | ({5 {operand[31:3] == {{28 {1'b1}}, 1'b0}}} & 5'd27)) | ({5 {operand[31:2] == {{29 {1'b1}}, 1'b0}}} & 5'd28)) | ({5 {operand[31:1] == {{30 {1'b1}}, 1'b0}}} & 5'd29)) | ({5 {operand[31:0] == {{31 {1'b1}}, 1'b0}}} & 5'd30)) | ({5 {operand[31:0] == {32 {1'b1}}}} & 5'd31); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu_div_ctl.sv:1799:1 + assign cls[4:0] = (operand[32] ? cls_ones[4:0] : cls_zeros[4:0]); +endmodule +module el2_exu ( + clk, + rst_l, + scan_mode, + dec_data_en, + dec_ctl_en, + dbg_cmd_wrdata, + i0_ap, + dec_debug_wdata_rs1_d, + dec_i0_predict_p_d, + i0_predict_fghr_d, + i0_predict_index_d, + i0_predict_btag_d, + lsu_result_m, + lsu_nonblock_load_data, + dec_i0_rs1_en_d, + dec_i0_rs2_en_d, + gpr_i0_rs1_d, + gpr_i0_rs2_d, + dec_i0_immed_d, + dec_i0_result_r, + dec_i0_br_immed_d, + dec_i0_alu_decode_d, + dec_i0_branch_d, + dec_i0_select_pc_d, + dec_i0_pc_d, + dec_i0_rs1_bypass_en_d, + dec_i0_rs2_bypass_en_d, + dec_csr_ren_d, + dec_csr_rddata_d, + dec_qual_lsu_d, + mul_p, + div_p, + dec_div_cancel, + pred_correct_npc_x, + dec_tlu_flush_lower_r, + dec_tlu_flush_path_r, + dec_extint_stall, + dec_tlu_meihap, + exu_lsu_rs1_d, + exu_lsu_rs2_d, + exu_flush_final, + exu_flush_path_final, + exu_i0_result_x, + exu_i0_pc_x, + exu_csr_rs1_x, + exu_npc_r, + exu_i0_br_hist_r, + exu_i0_br_error_r, + exu_i0_br_start_error_r, + exu_i0_br_index_r, + exu_i0_br_valid_r, + exu_i0_br_mp_r, + exu_i0_br_middle_r, + exu_i0_br_fghr_r, + exu_i0_br_way_r, + exu_mp_pkt, + exu_mp_eghr, + exu_mp_fghr, + exu_mp_index, + exu_mp_btag, + exu_pmu_i0_br_misp, + exu_pmu_i0_br_ataken, + exu_pmu_i0_pc4, + exu_div_result, + exu_div_wren +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:23:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:24:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:25:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:27:4 + input wire [1:0] dec_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:28:4 + input wire [1:0] dec_ctl_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:29:4 + input wire [31:0] dbg_cmd_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:30:4 + // removed localparam type el2_pkg_el2_alu_pkt_t + input wire [41:0] i0_ap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:32:4 + input wire dec_debug_wdata_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:34:4 + // removed localparam type el2_pkg_el2_predict_pkt_t + input wire [55:0] dec_i0_predict_p_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:35:4 + input wire [pt[2236-:8] - 1:0] i0_predict_fghr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:36:4 + input wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:37:4 + input wire [pt[2139-:9] - 1:0] i0_predict_btag_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:39:4 + input wire [31:0] lsu_result_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:40:4 + input wire [31:0] lsu_nonblock_load_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:41:4 + input wire dec_i0_rs1_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:42:4 + input wire dec_i0_rs2_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:43:4 + input wire [31:0] gpr_i0_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:44:4 + input wire [31:0] gpr_i0_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:45:4 + input wire [31:0] dec_i0_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:46:4 + input wire [31:0] dec_i0_result_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:47:4 + input wire [12:1] dec_i0_br_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:48:4 + input wire dec_i0_alu_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:49:4 + input wire dec_i0_branch_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:50:4 + input wire dec_i0_select_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:51:4 + input wire [31:1] dec_i0_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:52:4 + input wire [3:0] dec_i0_rs1_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:53:4 + input wire [3:0] dec_i0_rs2_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:54:4 + input wire dec_csr_ren_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:55:4 + input wire [31:0] dec_csr_rddata_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:57:4 + input wire dec_qual_lsu_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:58:4 + // removed localparam type el2_pkg_el2_mul_pkt_t + input wire [22:0] mul_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:59:4 + // removed localparam type el2_pkg_el2_div_pkt_t + input wire [2:0] div_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:60:4 + input wire dec_div_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:62:4 + input wire [31:1] pred_correct_npc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:64:4 + input wire dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:65:4 + input wire [31:1] dec_tlu_flush_path_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:68:4 + input wire dec_extint_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:69:4 + input wire [31:2] dec_tlu_meihap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:72:4 + output wire [31:0] exu_lsu_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:73:4 + output wire [31:0] exu_lsu_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:75:4 + output wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:76:4 + output wire [31:1] exu_flush_path_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:78:4 + output wire [31:0] exu_i0_result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:79:4 + output wire [31:1] exu_i0_pc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:80:4 + output wire [31:0] exu_csr_rs1_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:82:4 + output wire [31:1] exu_npc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:83:4 + output wire [1:0] exu_i0_br_hist_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:84:4 + output wire exu_i0_br_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:85:4 + output wire exu_i0_br_start_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:86:4 + output wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:87:4 + output wire exu_i0_br_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:88:4 + output wire exu_i0_br_mp_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:89:4 + output wire exu_i0_br_middle_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:90:4 + output wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:91:4 + output wire exu_i0_br_way_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:93:4 + output wire [55:0] exu_mp_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:94:4 + output wire [pt[2236-:8] - 1:0] exu_mp_eghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:95:4 + output wire [pt[2236-:8] - 1:0] exu_mp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:96:4 + output wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:97:4 + output wire [pt[2139-:9] - 1:0] exu_mp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:100:4 + output wire exu_pmu_i0_br_misp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:101:4 + output wire exu_pmu_i0_br_ataken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:102:4 + output wire exu_pmu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:105:4 + output wire [31:0] exu_div_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:106:4 + output wire exu_div_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:112:4 + wire [31:0] i0_rs1_bypass_data_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:113:4 + wire [31:0] i0_rs2_bypass_data_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:114:4 + wire i0_rs1_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:115:4 + wire i0_rs2_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:116:4 + wire [31:0] i0_rs1_d; + wire [31:0] i0_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:117:4 + wire [31:0] muldiv_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:118:4 + wire [31:1] pred_correct_npc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:119:4 + wire i0_pred_correct_upper_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:120:4 + wire [31:1] i0_flush_path_upper_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:121:4 + wire x_data_en; + wire x_data_en_q1; + wire x_data_en_q2; + wire r_data_en; + wire r_data_en_q2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:122:4 + wire x_ctl_en; + wire r_ctl_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:124:4 + wire [pt[2236-:8] - 1:0] ghr_d_ns; + wire [pt[2236-:8] - 1:0] ghr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:125:4 + wire [pt[2236-:8] - 1:0] ghr_x_ns; + wire [pt[2236-:8] - 1:0] ghr_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:126:4 + wire i0_taken_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:127:4 + wire i0_taken_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:128:4 + wire i0_valid_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:129:4 + wire i0_valid_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:130:4 + wire [pt[2236-:8] - 1:0] after_flush_eghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:132:4 + wire [55:0] final_predict_mp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:133:4 + reg [55:0] i0_predict_newp_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:135:4 + wire flush_in_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:136:4 + wire [31:0] alu_result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:138:4 + wire mul_valid_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:139:4 + wire [31:0] mul_result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:141:4 + wire [55:0] i0_pp_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:143:4 + wire i0_flush_upper_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:144:4 + wire [31:1] i0_flush_path_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:145:4 + wire [55:0] i0_predict_p_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:146:4 + wire i0_pred_correct_upper_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:148:4 + wire i0_flush_upper_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:149:4 + wire [31:1] i0_flush_path_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:150:4 + wire [55:0] i0_predict_p_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:151:4 + wire i0_pred_correct_upper_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:152:4 + wire i0_branch_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:154:4 + localparam PREDPIPESIZE = (((pt[2172-:9] - pt[2163-:6]) + 1) + pt[2236-:8]) + pt[2139-:9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:155:4 + wire [PREDPIPESIZE - 1:0] predpipe_d; + wire [PREDPIPESIZE - 1:0] predpipe_x; + wire [PREDPIPESIZE - 1:0] predpipe_r; + wire [PREDPIPESIZE - 1:0] final_predpipe_mp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:160:4 + rvdffpcie #(.WIDTH(31)) i_flush_path_x_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(x_data_en), + .din(i0_flush_path_d[31:1]), + .dout(i0_flush_path_x[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:161:4 + rvdffe #(.WIDTH(32)) i_csr_rs1_x_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(x_data_en_q1), + .din(i0_rs1_d[31:0]), + .dout(exu_csr_rs1_x[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:162:4 + rvdffppe #(.WIDTH(56)) i_predictpacket_x_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(x_data_en), + .din(i0_predict_p_d), + .dout(i0_predict_p_x) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:163:4 + rvdffe #(.WIDTH(PREDPIPESIZE)) i_predpipe_x_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(x_data_en_q2), + .din(predpipe_d), + .dout(predpipe_x) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:164:4 + rvdffe #(.WIDTH(PREDPIPESIZE)) i_predpipe_r_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(r_data_en_q2), + .din(predpipe_x), + .dout(predpipe_r) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:166:4 + rvdffe #(.WIDTH(4 + pt[2236-:8])) i_x_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(x_ctl_en), + .din({i0_valid_d, i0_taken_d, i0_flush_upper_d, i0_pred_correct_upper_d, ghr_x_ns[pt[2236-:8] - 1:0]}), + .dout({i0_valid_x, i0_taken_x, i0_flush_upper_x, i0_pred_correct_upper_x, ghr_x[pt[2236-:8] - 1:0]}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:169:4 + rvdffppe #(.WIDTH(57)) i_r_ff0( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(r_ctl_en), + .din({i0_pred_correct_upper_x, i0_predict_p_x}), + .dout({i0_pred_correct_upper_r, i0_pp_r}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:172:4 + rvdffpcie #(.WIDTH(31)) i_flush_r_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(r_data_en), + .din(i0_flush_path_x[31:1]), + .dout(i0_flush_path_upper_r[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:173:4 + rvdffpcie #(.WIDTH(31)) i_npc_r_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .en(r_data_en), + .din(pred_correct_npc_x[31:1]), + .dout(pred_correct_npc_r[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:175:4 + rvdffie #( + .WIDTH(pt[2236-:8] + 2), + .OVERRIDE(1) + ) i_misc_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .clk(clk), + .din({ghr_d_ns[pt[2236-:8] - 1:0], mul_p[22], dec_i0_branch_d}), + .dout({ghr_d[pt[2236-:8] - 1:0], mul_valid_x, i0_branch_x}) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:182:4 + assign predpipe_d[PREDPIPESIZE - 1:0] = {i0_predict_fghr_d, i0_predict_index_d, i0_predict_btag_d}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:186:4 + assign i0_rs1_bypass_en_d = ((dec_i0_rs1_bypass_en_d[0] | dec_i0_rs1_bypass_en_d[1]) | dec_i0_rs1_bypass_en_d[2]) | dec_i0_rs1_bypass_en_d[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:187:4 + assign i0_rs2_bypass_en_d = ((dec_i0_rs2_bypass_en_d[0] | dec_i0_rs2_bypass_en_d[1]) | dec_i0_rs2_bypass_en_d[2]) | dec_i0_rs2_bypass_en_d[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:189:4 + assign i0_rs1_bypass_data_d[31:0] = ((({32 {dec_i0_rs1_bypass_en_d[0]}} & dec_i0_result_r[31:0]) | ({32 {dec_i0_rs1_bypass_en_d[1]}} & lsu_result_m[31:0])) | ({32 {dec_i0_rs1_bypass_en_d[2]}} & exu_i0_result_x[31:0])) | ({32 {dec_i0_rs1_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:194:4 + assign i0_rs2_bypass_data_d[31:0] = ((({32 {dec_i0_rs2_bypass_en_d[0]}} & dec_i0_result_r[31:0]) | ({32 {dec_i0_rs2_bypass_en_d[1]}} & lsu_result_m[31:0])) | ({32 {dec_i0_rs2_bypass_en_d[2]}} & exu_i0_result_x[31:0])) | ({32 {dec_i0_rs2_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:200:4 + assign i0_rs1_d[31:0] = ((({32 {i0_rs1_bypass_en_d}} & i0_rs1_bypass_data_d[31:0]) | ({32 {~i0_rs1_bypass_en_d & dec_i0_select_pc_d}} & {dec_i0_pc_d[31:1], 1'b0})) | ({32 {~i0_rs1_bypass_en_d & dec_debug_wdata_rs1_d}} & dbg_cmd_wrdata[31:0])) | ({32 {(~i0_rs1_bypass_en_d & ~dec_debug_wdata_rs1_d) & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:205:4 + assign i0_rs2_d[31:0] = (({32 {~i0_rs2_bypass_en_d & dec_i0_rs2_en_d}} & gpr_i0_rs2_d[31:0]) | ({32 {~i0_rs2_bypass_en_d}} & dec_i0_immed_d[31:0])) | ({32 {i0_rs2_bypass_en_d}} & i0_rs2_bypass_data_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:210:4 + assign exu_lsu_rs1_d[31:0] = (({32 {((~i0_rs1_bypass_en_d & ~dec_extint_stall) & dec_i0_rs1_en_d) & dec_qual_lsu_d}} & gpr_i0_rs1_d[31:0]) | ({32 {(i0_rs1_bypass_en_d & ~dec_extint_stall) & dec_qual_lsu_d}} & i0_rs1_bypass_data_d[31:0])) | ({32 {dec_extint_stall & dec_qual_lsu_d}} & {dec_tlu_meihap[31:2], 2'b00}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:214:4 + assign exu_lsu_rs2_d[31:0] = ({32 {((~i0_rs2_bypass_en_d & ~dec_extint_stall) & dec_i0_rs2_en_d) & dec_qual_lsu_d}} & gpr_i0_rs2_d[31:0]) | ({32 {(i0_rs2_bypass_en_d & ~dec_extint_stall) & dec_qual_lsu_d}} & i0_rs2_bypass_data_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:218:4 + assign muldiv_rs1_d[31:0] = ({32 {~i0_rs1_bypass_en_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0]) | ({32 {i0_rs1_bypass_en_d}} & i0_rs1_bypass_data_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:222:4 + assign x_data_en = dec_data_en[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:223:4 + assign x_data_en_q1 = dec_data_en[1] & dec_csr_ren_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:224:4 + assign x_data_en_q2 = dec_data_en[1] & dec_i0_branch_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:225:4 + assign r_data_en = dec_data_en[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:226:4 + assign r_data_en_q2 = dec_data_en[0] & i0_branch_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:227:4 + assign x_ctl_en = dec_ctl_en[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:228:4 + assign r_ctl_en = dec_ctl_en[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:233:4 + el2_exu_alu_ctl #(.pt(pt)) i_alu( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .enable(x_data_en), + .pp_in(i0_predict_newp_d), + .valid_in(dec_i0_alu_decode_d), + .flush_upper_x(i0_flush_upper_x), + .flush_lower_r(dec_tlu_flush_lower_r), + .a_in(i0_rs1_d[31:0]), + .b_in(i0_rs2_d[31:0]), + .pc_in(dec_i0_pc_d[31:1]), + .brimm_in(dec_i0_br_immed_d[12:1]), + .ap(i0_ap), + .csr_ren_in(dec_csr_ren_d), + .csr_rddata_in(dec_csr_rddata_d[31:0]), + .result_ff(alu_result_x[31:0]), + .flush_upper_out(i0_flush_upper_d), + .flush_final_out(exu_flush_final), + .flush_path_out(i0_flush_path_d[31:1]), + .predict_p_out(i0_predict_p_d), + .pred_correct_out(i0_pred_correct_upper_d), + .pc_ff(exu_i0_pc_x[31:1]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:256:4 + el2_exu_mul_ctl #(.pt(pt)) i_mul( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .mul_p(mul_p & {23 {mul_p[22]}}), + .rs1_in(muldiv_rs1_d[31:0] & {32 {mul_p[22]}}), + .rs2_in(i0_rs2_d[31:0] & {32 {mul_p[22]}}), + .result_x(mul_result_x[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:264:4 + el2_exu_div_ctl #(.pt(pt)) i_div( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .cancel(dec_div_cancel), + .dp(div_p), + .dividend(muldiv_rs1_d[31:0]), + .divisor(i0_rs2_d[31:0]), + .finish_dly(exu_div_wren), + .out(exu_div_result[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:274:4 + assign exu_i0_result_x[31:0] = (mul_valid_x ? mul_result_x[31:0] : alu_result_x[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:279:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:280:7 + i0_predict_newp_d = dec_i0_predict_p_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:281:7 + i0_predict_newp_d[53] = dec_i0_pc_d[1]; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:285:4 + assign exu_pmu_i0_br_misp = i0_pp_r[55]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:286:4 + assign exu_pmu_i0_br_ataken = i0_pp_r[54]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:287:4 + assign exu_pmu_i0_pc4 = i0_pp_r[52]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:290:4 + assign i0_valid_d = (i0_predict_p_d[37] & dec_i0_alu_decode_d) & ~dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:291:4 + assign i0_taken_d = i0_predict_p_d[54] & dec_i0_alu_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:293:1 + generate + if (pt[2130-:5] == 1) begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:295:4 + assign ghr_d_ns[pt[2236-:8] - 1:0] = (({pt[2236-:8] {~dec_tlu_flush_lower_r & i0_valid_d}} & {ghr_d[pt[2236-:8] - 2:0], i0_taken_d}) | ({pt[2236-:8] {~dec_tlu_flush_lower_r & ~i0_valid_d}} & ghr_d[pt[2236-:8] - 1:0])) | ({pt[2236-:8] {dec_tlu_flush_lower_r}} & ghr_x[pt[2236-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:301:4 + assign ghr_x_ns[pt[2236-:8] - 1:0] = ({pt[2236-:8] {i0_valid_x}} & {ghr_x[pt[2236-:8] - 2:0], i0_taken_x}) | ({pt[2236-:8] {~i0_valid_x}} & ghr_x[pt[2236-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:306:4 + assign exu_i0_br_valid_r = i0_pp_r[37]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:307:4 + assign exu_i0_br_mp_r = i0_pp_r[55]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:308:4 + assign exu_i0_br_way_r = i0_pp_r[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:309:4 + assign exu_i0_br_hist_r[1:0] = {2 {i0_pp_r[37]}} & i0_pp_r[51:50]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:310:4 + assign exu_i0_br_error_r = i0_pp_r[36]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:311:4 + assign exu_i0_br_middle_r = i0_pp_r[52] ^ i0_pp_r[53]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:312:4 + assign exu_i0_br_start_error_r = i0_pp_r[35]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:314:4 + assign {exu_i0_br_fghr_r[pt[2236-:8] - 1:0], exu_i0_br_index_r[pt[2172-:9]:pt[2163-:6]]} = predpipe_r[PREDPIPESIZE - 1:pt[2139-:9]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:318:4 + assign final_predict_mp = (i0_flush_upper_x ? i0_predict_p_x : {56 {1'sb0}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:320:4 + assign final_predpipe_mp[PREDPIPESIZE - 1:0] = (i0_flush_upper_x ? predpipe_x : {PREDPIPESIZE * 1 {1'sb0}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:322:4 + assign after_flush_eghr[pt[2236-:8] - 1:0] = (i0_flush_upper_x & ~dec_tlu_flush_lower_r ? ghr_d[pt[2236-:8] - 1:0] : ghr_x[pt[2236-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:325:4 + assign exu_mp_pkt[37] = final_predict_mp[37]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:326:4 + assign exu_mp_pkt[32] = final_predict_mp[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:327:4 + assign exu_mp_pkt[55] = final_predict_mp[55]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:328:4 + assign exu_mp_pkt[34] = final_predict_mp[34]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:329:4 + assign exu_mp_pkt[33] = final_predict_mp[33]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:330:4 + assign exu_mp_pkt[31] = final_predict_mp[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:331:4 + assign exu_mp_pkt[54] = final_predict_mp[54]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:332:4 + assign exu_mp_pkt[53] = final_predict_mp[53]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:333:4 + assign exu_mp_pkt[52] = final_predict_mp[52]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:334:4 + assign exu_mp_pkt[51:50] = final_predict_mp[51:50]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:335:4 + assign exu_mp_pkt[49:38] = final_predict_mp[49:38]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:337:4 + assign exu_mp_fghr[pt[2236-:8] - 1:0] = after_flush_eghr[pt[2236-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:339:4 + assign {exu_mp_index[pt[2172-:9]:pt[2163-:6]], exu_mp_btag[pt[2139-:9] - 1:0]} = final_predpipe_mp[(PREDPIPESIZE - pt[2236-:8]) - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:342:4 + assign exu_mp_eghr[pt[2236-:8] - 1:0] = final_predpipe_mp[PREDPIPESIZE - 1:((pt[2172-:9] - pt[2163-:6]) + pt[2139-:9]) + 1]; + end + else begin : genblk1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:345:4 + assign ghr_d_ns = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:346:4 + assign ghr_x_ns = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:347:4 + assign exu_mp_pkt = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:348:4 + assign exu_mp_eghr = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:349:4 + assign exu_mp_fghr = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:350:4 + assign exu_mp_index = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:351:4 + assign exu_mp_btag = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:352:4 + assign exu_i0_br_hist_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:353:4 + assign exu_i0_br_error_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:354:4 + assign exu_i0_br_start_error_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:355:4 + assign exu_i0_br_index_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:356:4 + assign exu_i0_br_valid_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:357:4 + assign exu_i0_br_mp_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:358:4 + assign exu_i0_br_middle_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:359:4 + assign exu_i0_br_fghr_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:360:4 + assign exu_i0_br_way_r = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:363:4 + assign exu_flush_path_final[31:1] = ({31 {dec_tlu_flush_lower_r}} & dec_tlu_flush_path_r[31:1]) | ({31 {~dec_tlu_flush_lower_r & i0_flush_upper_d}} & i0_flush_path_d[31:1]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/exu/el2_exu.sv:366:4 + assign exu_npc_r[31:1] = (i0_pred_correct_upper_r ? pred_correct_npc_r[31:1] : i0_flush_path_upper_r[31:1]); + initial _sv2v_0 = 0; +endmodule +module el2_lsu ( + clk_override, + dec_tlu_flush_lower_r, + dec_tlu_i0_kill_writeb_r, + dec_tlu_force_halt, + dec_tlu_external_ldfwd_disable, + dec_tlu_wb_coalescing_disable, + dec_tlu_sideeffect_posted_disable, + dec_tlu_core_ecc_disable, + exu_lsu_rs1_d, + exu_lsu_rs2_d, + dec_lsu_offset_d, + lsu_p, + dec_lsu_valid_raw_d, + dec_tlu_mrac_ff, + lsu_result_m, + lsu_result_corr_r, + lsu_load_stall_any, + lsu_store_stall_any, + lsu_fastint_stall_any, + lsu_idle_any, + lsu_active, + lsu_fir_addr, + lsu_fir_error, + lsu_single_ecc_error_incr, + lsu_error_pkt_r, + lsu_imprecise_error_load_any, + lsu_imprecise_error_store_any, + lsu_imprecise_error_addr_any, + lsu_nonblock_load_valid_m, + lsu_nonblock_load_tag_m, + lsu_nonblock_load_inv_r, + lsu_nonblock_load_inv_tag_r, + lsu_nonblock_load_data_valid, + lsu_nonblock_load_data_error, + lsu_nonblock_load_data_tag, + lsu_nonblock_load_data, + lsu_pmu_load_external_m, + lsu_pmu_store_external_m, + lsu_pmu_misaligned_m, + lsu_pmu_bus_trxn, + lsu_pmu_bus_misaligned, + lsu_pmu_bus_error, + lsu_pmu_bus_busy, + trigger_pkt_any, + lsu_trigger_match_m, + dccm_wren, + dccm_rden, + dccm_wr_addr_lo, + dccm_wr_addr_hi, + dccm_rd_addr_lo, + dccm_rd_addr_hi, + dccm_wr_data_lo, + dccm_wr_data_hi, + dccm_rd_data_lo, + dccm_rd_data_hi, + picm_wren, + picm_rden, + picm_mken, + picm_rdaddr, + picm_wraddr, + picm_wr_data, + picm_rd_data, + lsu_axi_awvalid, + lsu_axi_awready, + lsu_axi_awid, + lsu_axi_awaddr, + lsu_axi_awregion, + lsu_axi_awlen, + lsu_axi_awsize, + lsu_axi_awburst, + lsu_axi_awlock, + lsu_axi_awcache, + lsu_axi_awprot, + lsu_axi_awqos, + lsu_axi_wvalid, + lsu_axi_wready, + lsu_axi_wdata, + lsu_axi_wstrb, + lsu_axi_wlast, + lsu_axi_bvalid, + lsu_axi_bready, + lsu_axi_bresp, + lsu_axi_bid, + lsu_axi_arvalid, + lsu_axi_arready, + lsu_axi_arid, + lsu_axi_araddr, + lsu_axi_arregion, + lsu_axi_arlen, + lsu_axi_arsize, + lsu_axi_arburst, + lsu_axi_arlock, + lsu_axi_arcache, + lsu_axi_arprot, + lsu_axi_arqos, + lsu_axi_rvalid, + lsu_axi_rready, + lsu_axi_rid, + lsu_axi_rdata, + lsu_axi_rresp, + lsu_axi_rlast, + lsu_bus_clk_en, + dma_dccm_req, + dma_mem_tag, + dma_mem_addr, + dma_mem_sz, + dma_mem_write, + dma_mem_wdata, + dccm_dma_rvalid, + dccm_dma_ecc_error, + dccm_dma_rtag, + dccm_dma_rdata, + dccm_ready, + scan_mode, + clk, + active_clk, + rst_l +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:35:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:36:4 + input wire dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:37:4 + input wire dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:38:4 + input wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:41:4 + input wire dec_tlu_external_ldfwd_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:42:4 + input wire dec_tlu_wb_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:43:4 + input wire dec_tlu_sideeffect_posted_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:44:4 + input wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:46:4 + input wire [31:0] exu_lsu_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:47:4 + input wire [31:0] exu_lsu_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:48:4 + input wire [11:0] dec_lsu_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:50:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:51:4 + input wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:52:4 + input wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:54:4 + output wire [31:0] lsu_result_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:55:4 + output wire [31:0] lsu_result_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:56:4 + output wire lsu_load_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:57:4 + output wire lsu_store_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:58:4 + output wire lsu_fastint_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:59:4 + output wire lsu_idle_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:60:4 + output wire lsu_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:62:4 + output wire [31:1] lsu_fir_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:63:4 + output wire [1:0] lsu_fir_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:65:4 + output wire lsu_single_ecc_error_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:66:4 + // removed localparam type el2_pkg_el2_lsu_error_pkt_t + output wire [39:0] lsu_error_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:67:4 + output wire lsu_imprecise_error_load_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:68:4 + output wire lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:69:4 + output wire [31:0] lsu_imprecise_error_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:72:4 + output wire lsu_nonblock_load_valid_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:73:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:74:4 + output wire lsu_nonblock_load_inv_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:75:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:76:4 + output wire lsu_nonblock_load_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:77:4 + output wire lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:78:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:79:4 + output wire [31:0] lsu_nonblock_load_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:81:4 + output wire lsu_pmu_load_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:82:4 + output wire lsu_pmu_store_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:83:4 + output wire lsu_pmu_misaligned_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:84:4 + output wire lsu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:85:4 + output wire lsu_pmu_bus_misaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:86:4 + output wire lsu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:87:4 + output wire lsu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:90:4 + // removed localparam type el2_pkg_el2_trigger_pkt_t + input wire [151:0] trigger_pkt_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:91:4 + output wire [3:0] lsu_trigger_match_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:94:4 + output wire dccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:95:4 + output wire dccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:96:4 + output wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:97:4 + output wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:98:4 + output wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:99:4 + output wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:100:4 + output wire [pt[1360-:10] - 1:0] dccm_wr_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:101:4 + output wire [pt[1360-:10] - 1:0] dccm_wr_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:103:4 + input wire [pt[1360-:10] - 1:0] dccm_rd_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:104:4 + input wire [pt[1360-:10] - 1:0] dccm_rd_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:107:4 + output wire picm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:108:4 + output wire picm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:109:4 + output wire picm_mken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:110:4 + output wire [31:0] picm_rdaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:111:4 + output wire [31:0] picm_wraddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:112:4 + output wire [31:0] picm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:113:4 + input wire [31:0] picm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:116:4 + output wire lsu_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:117:4 + input wire lsu_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:118:4 + output wire [pt[181-:8] - 1:0] lsu_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:119:4 + output wire [31:0] lsu_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:120:4 + output wire [3:0] lsu_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:121:4 + output wire [7:0] lsu_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:122:4 + output wire [2:0] lsu_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:123:4 + output wire [1:0] lsu_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:124:4 + output wire lsu_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:125:4 + output wire [3:0] lsu_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:126:4 + output wire [2:0] lsu_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:127:4 + output wire [3:0] lsu_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:129:4 + output wire lsu_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:130:4 + input wire lsu_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:131:4 + output wire [63:0] lsu_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:132:4 + output wire [7:0] lsu_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:133:4 + output wire lsu_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:135:4 + input wire lsu_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:136:4 + output wire lsu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:137:4 + input wire [1:0] lsu_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:138:4 + input wire [pt[181-:8] - 1:0] lsu_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:141:4 + output wire lsu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:142:4 + input wire lsu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:143:4 + output wire [pt[181-:8] - 1:0] lsu_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:144:4 + output wire [31:0] lsu_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:145:4 + output wire [3:0] lsu_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:146:4 + output wire [7:0] lsu_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:147:4 + output wire [2:0] lsu_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:148:4 + output wire [1:0] lsu_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:149:4 + output wire lsu_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:150:4 + output wire [3:0] lsu_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:151:4 + output wire [2:0] lsu_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:152:4 + output wire [3:0] lsu_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:154:4 + input wire lsu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:155:4 + output wire lsu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:156:4 + input wire [pt[181-:8] - 1:0] lsu_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:157:4 + input wire [63:0] lsu_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:158:4 + input wire [1:0] lsu_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:159:4 + input wire lsu_axi_rlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:161:4 + input wire lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:164:4 + input wire dma_dccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:165:4 + input wire [2:0] dma_mem_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:166:4 + input wire [31:0] dma_mem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:167:4 + input wire [2:0] dma_mem_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:168:4 + input wire dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:169:4 + input wire [63:0] dma_mem_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:171:4 + output wire dccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:172:4 + output wire dccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:173:4 + output wire [2:0] dccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:174:4 + output wire [63:0] dccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:175:4 + output wire dccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:177:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:178:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:179:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:180:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:184:4 + wire lsu_dccm_rden_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:185:4 + wire lsu_dccm_rden_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:186:4 + wire [31:0] store_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:187:4 + wire [31:0] store_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:188:4 + wire [31:0] store_data_hi_r; + wire [31:0] store_data_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:189:4 + wire [31:0] store_datafn_hi_r; + wire [31:0] store_datafn_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:190:4 + wire [31:0] sec_data_lo_m; + wire [31:0] sec_data_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:191:4 + wire [31:0] sec_data_lo_r; + wire [31:0] sec_data_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:193:4 + wire [31:0] lsu_ld_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:194:4 + wire [31:0] dccm_rdata_hi_m; + wire [31:0] dccm_rdata_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:195:4 + wire [6:0] dccm_data_ecc_hi_m; + wire [6:0] dccm_data_ecc_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:196:4 + wire lsu_single_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:197:4 + wire lsu_double_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:199:4 + wire [31:0] lsu_ld_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:200:4 + wire [31:0] lsu_ld_data_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:201:4 + wire [31:0] dccm_rdata_hi_r; + wire [31:0] dccm_rdata_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:202:4 + wire [6:0] dccm_data_ecc_hi_r; + wire [6:0] dccm_data_ecc_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:203:4 + wire single_ecc_error_hi_r; + wire single_ecc_error_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:204:4 + wire lsu_single_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:205:4 + wire lsu_double_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:206:4 + wire ld_single_ecc_error_r; + wire ld_single_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:208:4 + wire [31:0] picm_mask_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:210:4 + wire [31:0] lsu_addr_d; + wire [31:0] lsu_addr_m; + wire [31:0] lsu_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:211:4 + wire [31:0] end_addr_d; + wire [31:0] end_addr_m; + wire [31:0] end_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:213:4 + wire [13:0] lsu_pkt_d; + wire [13:0] lsu_pkt_m; + wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:214:4 + wire lsu_i0_valid_d; + wire lsu_i0_valid_m; + wire lsu_i0_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:217:4 + wire store_stbuf_reqvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:218:4 + wire ldst_stbuf_reqvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:220:4 + wire lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:221:4 + wire lsu_exc_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:223:4 + wire addr_in_dccm_d; + wire addr_in_dccm_m; + wire addr_in_dccm_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:224:4 + wire addr_in_pic_d; + wire addr_in_pic_m; + wire addr_in_pic_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:225:4 + wire ldst_dual_d; + wire ldst_dual_m; + wire ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:226:4 + wire addr_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:228:4 + wire stbuf_reqvld_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:229:4 + wire stbuf_reqvld_flushed_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:230:4 + wire [pt[157-:9] - 1:0] stbuf_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:231:4 + wire [pt[1382-:10] - 1:0] stbuf_data_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:232:4 + wire [pt[1372-:7] - 1:0] stbuf_ecc_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:233:4 + wire [pt[1382-:10] - 1:0] sec_data_lo_r_ff; + wire [pt[1382-:10] - 1:0] sec_data_hi_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:234:4 + wire [pt[1372-:7] - 1:0] sec_data_ecc_hi_r_ff; + wire [pt[1372-:7] - 1:0] sec_data_ecc_lo_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:236:4 + wire lsu_cmpen_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:237:4 + wire [pt[1382-:10] - 1:0] stbuf_fwddata_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:238:4 + wire [pt[1382-:10] - 1:0] stbuf_fwddata_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:239:4 + wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:240:4 + wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:242:4 + wire lsu_stbuf_commit_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:243:4 + wire lsu_stbuf_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:244:4 + wire lsu_stbuf_full_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:247:4 + wire lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:248:4 + wire lsu_bus_buffer_pend_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:249:4 + wire lsu_bus_buffer_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:250:4 + wire lsu_bus_buffer_full_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:251:4 + wire lsu_busreq_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:252:4 + wire [31:0] bus_read_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:254:4 + wire flush_m_up; + wire flush_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:255:4 + wire is_sideeffects_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:256:4 + wire [2:0] dma_mem_tag_d; + wire [2:0] dma_mem_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:257:4 + wire ldst_nodma_mtor; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:258:4 + wire dma_dccm_wen; + wire dma_pic_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:259:4 + wire [31:0] dma_dccm_wdata_lo; + wire [31:0] dma_dccm_wdata_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:260:4 + wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_lo; + wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:263:4 + wire lsu_busm_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:264:4 + wire lsu_bus_obuf_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:265:4 + wire lsu_c1_m_clk; + wire lsu_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:266:4 + wire lsu_c2_m_clk; + wire lsu_c2_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:267:4 + wire lsu_store_c1_m_clk; + wire lsu_store_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:269:4 + wire lsu_stbuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:270:4 + wire lsu_bus_ibuf_c1_clk; + wire lsu_bus_obuf_c1_clk; + wire lsu_bus_buf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:271:4 + wire lsu_busm_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:272:4 + wire lsu_free_c2_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:274:4 + wire lsu_raw_fwd_lo_m; + wire lsu_raw_fwd_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:275:4 + wire lsu_raw_fwd_lo_r; + wire lsu_raw_fwd_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:277:4 + assign lsu_raw_fwd_lo_m = |stbuf_fwdbyteen_lo_m[pt[1389-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:278:4 + assign lsu_raw_fwd_hi_m = |stbuf_fwdbyteen_hi_m[pt[1389-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:280:4 + el2_lsu_lsc_ctl #(.pt(pt)) lsu_lsc_ctl( + .rst_l(rst_l), + .clk_override(clk_override), + .clk(clk), + .lsu_c1_m_clk(lsu_c1_m_clk), + .lsu_c1_r_clk(lsu_c1_r_clk), + .lsu_c2_m_clk(lsu_c2_m_clk), + .lsu_c2_r_clk(lsu_c2_r_clk), + .lsu_store_c1_m_clk(lsu_store_c1_m_clk), + .lsu_ld_data_r(lsu_ld_data_r), + .lsu_ld_data_corr_r(lsu_ld_data_corr_r), + .lsu_single_ecc_error_r(lsu_single_ecc_error_r), + .lsu_double_ecc_error_r(lsu_double_ecc_error_r), + .lsu_ld_data_m(lsu_ld_data_m), + .lsu_single_ecc_error_m(lsu_single_ecc_error_m), + .lsu_double_ecc_error_m(lsu_double_ecc_error_m), + .flush_m_up(flush_m_up), + .flush_r(flush_r), + .ldst_dual_d(ldst_dual_d), + .ldst_dual_m(ldst_dual_m), + .ldst_dual_r(ldst_dual_r), + .exu_lsu_rs1_d(exu_lsu_rs1_d), + .exu_lsu_rs2_d(exu_lsu_rs2_d), + .lsu_p(lsu_p), + .dec_lsu_valid_raw_d(dec_lsu_valid_raw_d), + .dec_lsu_offset_d(dec_lsu_offset_d), + .picm_mask_data_m(picm_mask_data_m), + .bus_read_data_m(bus_read_data_m), + .lsu_result_m(lsu_result_m), + .lsu_result_corr_r(lsu_result_corr_r), + .lsu_addr_d(lsu_addr_d), + .lsu_addr_m(lsu_addr_m), + .lsu_addr_r(lsu_addr_r), + .end_addr_d(end_addr_d), + .end_addr_m(end_addr_m), + .end_addr_r(end_addr_r), + .store_data_m(store_data_m), + .dec_tlu_mrac_ff(dec_tlu_mrac_ff), + .lsu_exc_m(lsu_exc_m), + .is_sideeffects_m(is_sideeffects_m), + .lsu_commit_r(lsu_commit_r), + .lsu_single_ecc_error_incr(lsu_single_ecc_error_incr), + .lsu_error_pkt_r(lsu_error_pkt_r), + .lsu_fir_addr(lsu_fir_addr), + .lsu_fir_error(lsu_fir_error), + .addr_in_dccm_d(addr_in_dccm_d), + .addr_in_dccm_m(addr_in_dccm_m), + .addr_in_dccm_r(addr_in_dccm_r), + .addr_in_pic_d(addr_in_pic_d), + .addr_in_pic_m(addr_in_pic_m), + .addr_in_pic_r(addr_in_pic_r), + .addr_external_m(addr_external_m), + .dma_dccm_req(dma_dccm_req), + .dma_mem_addr(dma_mem_addr), + .dma_mem_sz(dma_mem_sz), + .dma_mem_write(dma_mem_write), + .dma_mem_wdata(dma_mem_wdata), + .lsu_pkt_d(lsu_pkt_d), + .lsu_pkt_m(lsu_pkt_m), + .lsu_pkt_r(lsu_pkt_r), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:283:4 + assign lsu_store_stall_any = (lsu_stbuf_full_any | lsu_bus_buffer_full_any) | ld_single_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:284:4 + assign lsu_load_stall_any = lsu_bus_buffer_full_any | ld_single_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:285:4 + assign lsu_fastint_stall_any = ld_single_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:289:4 + assign dma_mem_tag_d[2:0] = dma_mem_tag[2:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:290:4 + assign ldst_nodma_mtor = ((lsu_pkt_m[0] & ~lsu_pkt_m[4]) & (addr_in_dccm_m | addr_in_pic_m)) & lsu_pkt_m[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:292:4 + assign dccm_ready = ~((dec_lsu_valid_raw_d | ldst_nodma_mtor) | ld_single_ecc_error_r_ff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:294:4 + assign dma_dccm_wen = ((dma_dccm_req & dma_mem_write) & addr_in_dccm_d) & dma_mem_sz[1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:295:4 + assign dma_pic_wen = (dma_dccm_req & dma_mem_write) & addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:296:4 + assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:300:4 + assign flush_m_up = dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:301:4 + assign flush_r = dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:308:4 + assign lsu_idle_any = ~((lsu_pkt_m[0] & ~lsu_pkt_m[4]) | (lsu_pkt_r[0] & ~lsu_pkt_r[4])) & lsu_bus_buffer_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:312:4 + assign lsu_active = ((lsu_pkt_m[0] | lsu_pkt_r[0]) | ld_single_ecc_error_r_ff) | ~lsu_bus_buffer_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:315:4 + assign store_stbuf_reqvld_r = (((lsu_pkt_r[0] & lsu_pkt_r[6]) & addr_in_dccm_r) & ~flush_r) & (~lsu_pkt_r[4] | ((lsu_pkt_r[11] | lsu_pkt_r[10]) & ~lsu_double_ecc_error_r)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:318:4 + assign lsu_cmpen_m = (lsu_pkt_m[0] & (lsu_pkt_m[7] | lsu_pkt_m[6])) & (addr_in_dccm_m | addr_in_pic_m); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:321:4 + assign lsu_busreq_m = (((lsu_pkt_m[0] & ((lsu_pkt_m[7] | lsu_pkt_m[6]) & addr_external_m)) & ~flush_m_up) & ~lsu_exc_m) & ~lsu_pkt_m[13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:324:4 + assign ldst_dual_d = lsu_addr_d[2] != end_addr_d[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:325:4 + assign ldst_dual_m = lsu_addr_m[2] != end_addr_m[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:326:4 + assign ldst_dual_r = lsu_addr_r[2] != end_addr_r[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:329:4 + assign lsu_pmu_misaligned_m = lsu_pkt_m[0] & ((lsu_pkt_m[10] & lsu_addr_m[0]) | (lsu_pkt_m[9] & |lsu_addr_m[1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:330:4 + assign lsu_pmu_load_external_m = (lsu_pkt_m[0] & lsu_pkt_m[7]) & addr_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:331:4 + assign lsu_pmu_store_external_m = (lsu_pkt_m[0] & lsu_pkt_m[6]) & addr_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:333:4 + el2_lsu_dccm_ctl #(.pt(pt)) dccm_ctl( + .lsu_addr_d(lsu_addr_d[31:0]), + .end_addr_d(end_addr_d[pt[1398-:9] - 1:0]), + .lsu_addr_m(lsu_addr_m[pt[1398-:9] - 1:0]), + .lsu_addr_r(lsu_addr_r[31:0]), + .end_addr_m(end_addr_m[pt[1398-:9] - 1:0]), + .end_addr_r(end_addr_r[pt[1398-:9] - 1:0]), + .lsu_c2_m_clk(lsu_c2_m_clk), + .lsu_c2_r_clk(lsu_c2_r_clk), + .lsu_c1_r_clk(lsu_c1_r_clk), + .lsu_store_c1_r_clk(lsu_store_c1_r_clk), + .lsu_free_c2_clk(lsu_free_c2_clk), + .clk_override(clk_override), + .clk(clk), + .rst_l(rst_l), + .lsu_pkt_r(lsu_pkt_r), + .lsu_pkt_m(lsu_pkt_m), + .lsu_pkt_d(lsu_pkt_d), + .addr_in_dccm_d(addr_in_dccm_d), + .addr_in_pic_d(addr_in_pic_d), + .addr_in_pic_m(addr_in_pic_m), + .addr_in_dccm_m(addr_in_dccm_m), + .addr_in_dccm_r(addr_in_dccm_r), + .addr_in_pic_r(addr_in_pic_r), + .lsu_raw_fwd_lo_r(lsu_raw_fwd_lo_r), + .lsu_raw_fwd_hi_r(lsu_raw_fwd_hi_r), + .lsu_commit_r(lsu_commit_r), + .ldst_dual_m(ldst_dual_m), + .ldst_dual_r(ldst_dual_r), + .stbuf_reqvld_any(stbuf_reqvld_any), + .stbuf_addr_any(stbuf_addr_any), + .stbuf_data_any(stbuf_data_any), + .stbuf_ecc_any(stbuf_ecc_any), + .stbuf_fwddata_hi_m(stbuf_fwddata_hi_m), + .stbuf_fwddata_lo_m(stbuf_fwddata_lo_m), + .stbuf_fwdbyteen_hi_m(stbuf_fwdbyteen_hi_m), + .stbuf_fwdbyteen_lo_m(stbuf_fwdbyteen_lo_m), + .dccm_rdata_hi_r(dccm_rdata_hi_r), + .dccm_rdata_lo_r(dccm_rdata_lo_r), + .dccm_data_ecc_hi_r(dccm_data_ecc_hi_r), + .dccm_data_ecc_lo_r(dccm_data_ecc_lo_r), + .lsu_ld_data_r(lsu_ld_data_r), + .lsu_ld_data_corr_r(lsu_ld_data_corr_r), + .lsu_double_ecc_error_r(lsu_double_ecc_error_r), + .single_ecc_error_hi_r(single_ecc_error_hi_r), + .single_ecc_error_lo_r(single_ecc_error_lo_r), + .sec_data_hi_r(sec_data_hi_r), + .sec_data_lo_r(sec_data_lo_r), + .sec_data_hi_r_ff(sec_data_hi_r_ff), + .sec_data_lo_r_ff(sec_data_lo_r_ff), + .sec_data_ecc_hi_r_ff(sec_data_ecc_hi_r_ff), + .sec_data_ecc_lo_r_ff(sec_data_ecc_lo_r_ff), + .dccm_rdata_hi_m(dccm_rdata_hi_m), + .dccm_rdata_lo_m(dccm_rdata_lo_m), + .dccm_data_ecc_hi_m(dccm_data_ecc_hi_m), + .dccm_data_ecc_lo_m(dccm_data_ecc_lo_m), + .lsu_ld_data_m(lsu_ld_data_m), + .lsu_double_ecc_error_m(lsu_double_ecc_error_m), + .sec_data_hi_m(sec_data_hi_m), + .sec_data_lo_m(sec_data_lo_m), + .store_data_m(store_data_m), + .dma_dccm_wen(dma_dccm_wen), + .dma_pic_wen(dma_pic_wen), + .dma_mem_tag_m(dma_mem_tag_m), + .dma_mem_addr(dma_mem_addr), + .dma_mem_wdata(dma_mem_wdata), + .dma_dccm_wdata_lo(dma_dccm_wdata_lo), + .dma_dccm_wdata_hi(dma_dccm_wdata_hi), + .dma_dccm_wdata_ecc_hi(dma_dccm_wdata_ecc_hi), + .dma_dccm_wdata_ecc_lo(dma_dccm_wdata_ecc_lo), + .store_data_hi_r(store_data_hi_r), + .store_data_lo_r(store_data_lo_r), + .store_datafn_hi_r(store_datafn_hi_r), + .store_datafn_lo_r(store_datafn_lo_r), + .store_data_r(store_data_r), + .ld_single_ecc_error_r(ld_single_ecc_error_r), + .ld_single_ecc_error_r_ff(ld_single_ecc_error_r_ff), + .picm_mask_data_m(picm_mask_data_m), + .lsu_stbuf_commit_any(lsu_stbuf_commit_any), + .lsu_dccm_rden_m(lsu_dccm_rden_m), + .lsu_dccm_rden_r(lsu_dccm_rden_r), + .dccm_dma_rvalid(dccm_dma_rvalid), + .dccm_dma_ecc_error(dccm_dma_ecc_error), + .dccm_dma_rtag(dccm_dma_rtag), + .dccm_dma_rdata(dccm_dma_rdata), + .dccm_wren(dccm_wren), + .dccm_rden(dccm_rden), + .dccm_wr_addr_lo(dccm_wr_addr_lo), + .dccm_wr_addr_hi(dccm_wr_addr_hi), + .dccm_rd_addr_lo(dccm_rd_addr_lo), + .dccm_rd_addr_hi(dccm_rd_addr_hi), + .dccm_wr_data_lo(dccm_wr_data_lo), + .dccm_wr_data_hi(dccm_wr_data_hi), + .dccm_rd_data_lo(dccm_rd_data_lo), + .dccm_rd_data_hi(dccm_rd_data_hi), + .picm_wren(picm_wren), + .picm_rden(picm_rden), + .picm_mken(picm_mken), + .picm_rdaddr(picm_rdaddr), + .picm_wraddr(picm_wraddr), + .picm_wr_data(picm_wr_data), + .picm_rd_data(picm_rd_data), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:344:4 + el2_lsu_stbuf #(.pt(pt)) stbuf( + .lsu_addr_d(lsu_addr_d[pt[157-:9] - 1:0]), + .end_addr_d(end_addr_d[pt[157-:9] - 1:0]), + .clk(clk), + .rst_l(rst_l), + .lsu_stbuf_c1_clk(lsu_stbuf_c1_clk), + .lsu_free_c2_clk(lsu_free_c2_clk), + .store_stbuf_reqvld_r(store_stbuf_reqvld_r), + .lsu_commit_r(lsu_commit_r), + .dec_lsu_valid_raw_d(dec_lsu_valid_raw_d), + .store_data_hi_r(store_data_hi_r), + .store_data_lo_r(store_data_lo_r), + .store_datafn_hi_r(store_datafn_hi_r), + .store_datafn_lo_r(store_datafn_lo_r), + .stbuf_reqvld_any(stbuf_reqvld_any), + .stbuf_reqvld_flushed_any(stbuf_reqvld_flushed_any), + .stbuf_addr_any(stbuf_addr_any), + .stbuf_data_any(stbuf_data_any), + .lsu_stbuf_commit_any(lsu_stbuf_commit_any), + .lsu_stbuf_full_any(lsu_stbuf_full_any), + .lsu_stbuf_empty_any(lsu_stbuf_empty_any), + .ldst_stbuf_reqvld_r(ldst_stbuf_reqvld_r), + .lsu_addr_m(lsu_addr_m), + .lsu_addr_r(lsu_addr_r), + .end_addr_m(end_addr_m), + .end_addr_r(end_addr_r), + .ldst_dual_d(ldst_dual_d), + .ldst_dual_m(ldst_dual_m), + .ldst_dual_r(ldst_dual_r), + .addr_in_dccm_m(addr_in_dccm_m), + .addr_in_dccm_r(addr_in_dccm_r), + .lsu_cmpen_m(lsu_cmpen_m), + .lsu_pkt_m(lsu_pkt_m), + .lsu_pkt_r(lsu_pkt_r), + .stbuf_fwddata_hi_m(stbuf_fwddata_hi_m), + .stbuf_fwddata_lo_m(stbuf_fwddata_lo_m), + .stbuf_fwdbyteen_hi_m(stbuf_fwdbyteen_hi_m), + .stbuf_fwdbyteen_lo_m(stbuf_fwdbyteen_lo_m), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:352:4 + el2_lsu_ecc #(.pt(pt)) ecc( + .lsu_addr_r(lsu_addr_r[pt[1398-:9] - 1:0]), + .end_addr_r(end_addr_r[pt[1398-:9] - 1:0]), + .lsu_addr_m(lsu_addr_m[pt[1398-:9] - 1:0]), + .end_addr_m(end_addr_m[pt[1398-:9] - 1:0]), + .clk(clk), + .lsu_c2_r_clk(lsu_c2_r_clk), + .clk_override(clk_override), + .rst_l(rst_l), + .scan_mode(scan_mode), + .lsu_pkt_m(lsu_pkt_m), + .lsu_pkt_r(lsu_pkt_r), + .stbuf_data_any(stbuf_data_any), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .lsu_dccm_rden_r(lsu_dccm_rden_r), + .addr_in_dccm_r(addr_in_dccm_r), + .dccm_rdata_hi_r(dccm_rdata_hi_r), + .dccm_rdata_lo_r(dccm_rdata_lo_r), + .dccm_data_ecc_hi_r(dccm_data_ecc_hi_r), + .dccm_data_ecc_lo_r(dccm_data_ecc_lo_r), + .sec_data_hi_r(sec_data_hi_r), + .sec_data_lo_r(sec_data_lo_r), + .sec_data_hi_r_ff(sec_data_hi_r_ff), + .sec_data_lo_r_ff(sec_data_lo_r_ff), + .ld_single_ecc_error_r(ld_single_ecc_error_r), + .ld_single_ecc_error_r_ff(ld_single_ecc_error_r_ff), + .lsu_dccm_rden_m(lsu_dccm_rden_m), + .addr_in_dccm_m(addr_in_dccm_m), + .dccm_rdata_hi_m(dccm_rdata_hi_m), + .dccm_rdata_lo_m(dccm_rdata_lo_m), + .dccm_data_ecc_hi_m(dccm_data_ecc_hi_m), + .dccm_data_ecc_lo_m(dccm_data_ecc_lo_m), + .sec_data_hi_m(sec_data_hi_m), + .sec_data_lo_m(sec_data_lo_m), + .dma_dccm_wen(dma_dccm_wen), + .dma_dccm_wdata_lo(dma_dccm_wdata_lo), + .dma_dccm_wdata_hi(dma_dccm_wdata_hi), + .dma_dccm_wdata_ecc_hi(dma_dccm_wdata_ecc_hi), + .dma_dccm_wdata_ecc_lo(dma_dccm_wdata_ecc_lo), + .stbuf_ecc_any(stbuf_ecc_any), + .sec_data_ecc_hi_r_ff(sec_data_ecc_hi_r_ff), + .sec_data_ecc_lo_r_ff(sec_data_ecc_lo_r_ff), + .single_ecc_error_hi_r(single_ecc_error_hi_r), + .single_ecc_error_lo_r(single_ecc_error_lo_r), + .lsu_single_ecc_error_r(lsu_single_ecc_error_r), + .lsu_double_ecc_error_r(lsu_double_ecc_error_r), + .lsu_single_ecc_error_m(lsu_single_ecc_error_m), + .lsu_double_ecc_error_m(lsu_double_ecc_error_m) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:360:4 + el2_lsu_trigger #(.pt(pt)) trigger( + .store_data_m(store_data_m[31:0]), + .trigger_pkt_any(trigger_pkt_any), + .lsu_pkt_m(lsu_pkt_m), + .lsu_addr_m(lsu_addr_m), + .lsu_trigger_match_m(lsu_trigger_match_m) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:366:4 + el2_lsu_clkdomain #(.pt(pt)) clkdomain( + .clk(clk), + .active_clk(active_clk), + .rst_l(rst_l), + .dec_tlu_force_halt(dec_tlu_force_halt), + .clk_override(clk_override), + .dma_dccm_req(dma_dccm_req), + .ldst_stbuf_reqvld_r(ldst_stbuf_reqvld_r), + .stbuf_reqvld_any(stbuf_reqvld_any), + .stbuf_reqvld_flushed_any(stbuf_reqvld_flushed_any), + .lsu_busreq_r(lsu_busreq_r), + .lsu_bus_buffer_pend_any(lsu_bus_buffer_pend_any), + .lsu_bus_buffer_empty_any(lsu_bus_buffer_empty_any), + .lsu_stbuf_empty_any(lsu_stbuf_empty_any), + .lsu_bus_clk_en(lsu_bus_clk_en), + .lsu_p(lsu_p), + .lsu_pkt_d(lsu_pkt_d), + .lsu_pkt_m(lsu_pkt_m), + .lsu_pkt_r(lsu_pkt_r), + .lsu_bus_obuf_c1_clken(lsu_bus_obuf_c1_clken), + .lsu_busm_clken(lsu_busm_clken), + .lsu_c1_m_clk(lsu_c1_m_clk), + .lsu_c1_r_clk(lsu_c1_r_clk), + .lsu_c2_m_clk(lsu_c2_m_clk), + .lsu_c2_r_clk(lsu_c2_r_clk), + .lsu_store_c1_m_clk(lsu_store_c1_m_clk), + .lsu_store_c1_r_clk(lsu_store_c1_r_clk), + .lsu_stbuf_c1_clk(lsu_stbuf_c1_clk), + .lsu_bus_obuf_c1_clk(lsu_bus_obuf_c1_clk), + .lsu_bus_ibuf_c1_clk(lsu_bus_ibuf_c1_clk), + .lsu_bus_buf_c1_clk(lsu_bus_buf_c1_clk), + .lsu_busm_clk(lsu_busm_clk), + .lsu_free_c2_clk(lsu_free_c2_clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:369:4 + el2_lsu_bus_intf #(.pt(pt)) bus_intf( + .lsu_addr_m(lsu_addr_m[31:0] & {32 {addr_external_m & lsu_pkt_m[0]}}), + .lsu_addr_r(lsu_addr_r[31:0] & {32 {lsu_busreq_r}}), + .end_addr_m(end_addr_m[31:0] & {32 {addr_external_m & lsu_pkt_m[0]}}), + .end_addr_r(end_addr_r[31:0] & {32 {lsu_busreq_r}}), + .store_data_r(store_data_r[31:0] & {32 {lsu_busreq_r}}), + .clk(clk), + .clk_override(clk_override), + .rst_l(rst_l), + .scan_mode(scan_mode), + .dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable), + .dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable), + .dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable), + .lsu_bus_obuf_c1_clken(lsu_bus_obuf_c1_clken), + .lsu_busm_clken(lsu_busm_clken), + .lsu_c1_r_clk(lsu_c1_r_clk), + .lsu_c2_r_clk(lsu_c2_r_clk), + .lsu_bus_ibuf_c1_clk(lsu_bus_ibuf_c1_clk), + .lsu_bus_obuf_c1_clk(lsu_bus_obuf_c1_clk), + .lsu_bus_buf_c1_clk(lsu_bus_buf_c1_clk), + .lsu_free_c2_clk(lsu_free_c2_clk), + .active_clk(active_clk), + .lsu_busm_clk(lsu_busm_clk), + .dec_lsu_valid_raw_d(dec_lsu_valid_raw_d), + .lsu_busreq_m(lsu_busreq_m), + .lsu_pkt_m(lsu_pkt_m), + .lsu_pkt_r(lsu_pkt_r), + .dec_tlu_force_halt(dec_tlu_force_halt), + .lsu_commit_r(lsu_commit_r), + .is_sideeffects_m(is_sideeffects_m), + .flush_m_up(flush_m_up), + .flush_r(flush_r), + .ldst_dual_d(ldst_dual_d), + .ldst_dual_m(ldst_dual_m), + .ldst_dual_r(ldst_dual_r), + .lsu_busreq_r(lsu_busreq_r), + .lsu_bus_buffer_pend_any(lsu_bus_buffer_pend_any), + .lsu_bus_buffer_full_any(lsu_bus_buffer_full_any), + .lsu_bus_buffer_empty_any(lsu_bus_buffer_empty_any), + .bus_read_data_m(bus_read_data_m), + .lsu_imprecise_error_load_any(lsu_imprecise_error_load_any), + .lsu_imprecise_error_store_any(lsu_imprecise_error_store_any), + .lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any), + .lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m), + .lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m), + .lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r), + .lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r), + .lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid), + .lsu_nonblock_load_data_error(lsu_nonblock_load_data_error), + .lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag), + .lsu_nonblock_load_data(lsu_nonblock_load_data), + .lsu_pmu_bus_trxn(lsu_pmu_bus_trxn), + .lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned), + .lsu_pmu_bus_error(lsu_pmu_bus_error), + .lsu_pmu_bus_busy(lsu_pmu_bus_busy), + .lsu_axi_awvalid(lsu_axi_awvalid), + .lsu_axi_awready(lsu_axi_awready), + .lsu_axi_awid(lsu_axi_awid), + .lsu_axi_awaddr(lsu_axi_awaddr), + .lsu_axi_awregion(lsu_axi_awregion), + .lsu_axi_awlen(lsu_axi_awlen), + .lsu_axi_awsize(lsu_axi_awsize), + .lsu_axi_awburst(lsu_axi_awburst), + .lsu_axi_awlock(lsu_axi_awlock), + .lsu_axi_awcache(lsu_axi_awcache), + .lsu_axi_awprot(lsu_axi_awprot), + .lsu_axi_awqos(lsu_axi_awqos), + .lsu_axi_wvalid(lsu_axi_wvalid), + .lsu_axi_wready(lsu_axi_wready), + .lsu_axi_wdata(lsu_axi_wdata), + .lsu_axi_wstrb(lsu_axi_wstrb), + .lsu_axi_wlast(lsu_axi_wlast), + .lsu_axi_bvalid(lsu_axi_bvalid), + .lsu_axi_bready(lsu_axi_bready), + .lsu_axi_bresp(lsu_axi_bresp), + .lsu_axi_bid(lsu_axi_bid), + .lsu_axi_arvalid(lsu_axi_arvalid), + .lsu_axi_arready(lsu_axi_arready), + .lsu_axi_arid(lsu_axi_arid), + .lsu_axi_araddr(lsu_axi_araddr), + .lsu_axi_arregion(lsu_axi_arregion), + .lsu_axi_arlen(lsu_axi_arlen), + .lsu_axi_arsize(lsu_axi_arsize), + .lsu_axi_arburst(lsu_axi_arburst), + .lsu_axi_arlock(lsu_axi_arlock), + .lsu_axi_arcache(lsu_axi_arcache), + .lsu_axi_arprot(lsu_axi_arprot), + .lsu_axi_arqos(lsu_axi_arqos), + .lsu_axi_rvalid(lsu_axi_rvalid), + .lsu_axi_rready(lsu_axi_rready), + .lsu_axi_rid(lsu_axi_rid), + .lsu_axi_rdata(lsu_axi_rdata), + .lsu_axi_rresp(lsu_axi_rresp), + .lsu_bus_clk_en(lsu_bus_clk_en) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:381:4 + rvdff #(.WIDTH(3)) dma_mem_tag_mff( + .rst_l(rst_l), + .din(dma_mem_tag_d[2:0]), + .dout(dma_mem_tag_m[2:0]), + .clk(lsu_c1_m_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu.sv:382:4 + rvdff #(.WIDTH(2)) lsu_raw_fwd_r_ff( + .rst_l(rst_l), + .din({lsu_raw_fwd_hi_m, lsu_raw_fwd_lo_m}), + .dout({lsu_raw_fwd_hi_r, lsu_raw_fwd_lo_r}), + .clk(lsu_c2_r_clk) + ); +endmodule +module el2_lsu_bus_buffer ( + clk, + clk_override, + rst_l, + scan_mode, + dec_tlu_external_ldfwd_disable, + dec_tlu_wb_coalescing_disable, + dec_tlu_sideeffect_posted_disable, + dec_tlu_force_halt, + lsu_bus_obuf_c1_clken, + lsu_busm_clken, + lsu_c2_r_clk, + lsu_bus_ibuf_c1_clk, + lsu_bus_obuf_c1_clk, + lsu_bus_buf_c1_clk, + lsu_free_c2_clk, + lsu_busm_clk, + dec_lsu_valid_raw_d, + lsu_pkt_m, + lsu_pkt_r, + lsu_addr_m, + end_addr_m, + lsu_addr_r, + end_addr_r, + store_data_r, + no_word_merge_r, + no_dword_merge_r, + lsu_busreq_m, + lsu_busreq_r, + ld_full_hit_m, + flush_m_up, + flush_r, + lsu_commit_r, + is_sideeffects_r, + ldst_dual_d, + ldst_dual_m, + ldst_dual_r, + ldst_byteen_ext_m, + lsu_bus_buffer_pend_any, + lsu_bus_buffer_full_any, + lsu_bus_buffer_empty_any, + ld_byte_hit_buf_lo, + ld_byte_hit_buf_hi, + ld_fwddata_buf_lo, + ld_fwddata_buf_hi, + lsu_imprecise_error_load_any, + lsu_imprecise_error_store_any, + lsu_imprecise_error_addr_any, + lsu_nonblock_load_valid_m, + lsu_nonblock_load_tag_m, + lsu_nonblock_load_inv_r, + lsu_nonblock_load_inv_tag_r, + lsu_nonblock_load_data_valid, + lsu_nonblock_load_data_error, + lsu_nonblock_load_data_tag, + lsu_nonblock_load_data, + lsu_pmu_bus_trxn, + lsu_pmu_bus_misaligned, + lsu_pmu_bus_error, + lsu_pmu_bus_busy, + lsu_axi_awvalid, + lsu_axi_awready, + lsu_axi_awid, + lsu_axi_awaddr, + lsu_axi_awregion, + lsu_axi_awlen, + lsu_axi_awsize, + lsu_axi_awburst, + lsu_axi_awlock, + lsu_axi_awcache, + lsu_axi_awprot, + lsu_axi_awqos, + lsu_axi_wvalid, + lsu_axi_wready, + lsu_axi_wdata, + lsu_axi_wstrb, + lsu_axi_wlast, + lsu_axi_bvalid, + lsu_axi_bready, + lsu_axi_bresp, + lsu_axi_bid, + lsu_axi_arvalid, + lsu_axi_arready, + lsu_axi_arid, + lsu_axi_araddr, + lsu_axi_arregion, + lsu_axi_arlen, + lsu_axi_arsize, + lsu_axi_arburst, + lsu_axi_arlock, + lsu_axi_arcache, + lsu_axi_arprot, + lsu_axi_arqos, + lsu_axi_rvalid, + lsu_axi_rready, + lsu_axi_rid, + lsu_axi_rdata, + lsu_axi_rresp, + lsu_bus_clk_en, + lsu_bus_clk_en_q +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:31:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:32:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:33:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:34:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:35:4 + input wire dec_tlu_external_ldfwd_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:36:4 + input wire dec_tlu_wb_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:37:4 + input wire dec_tlu_sideeffect_posted_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:38:4 + input wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:41:4 + input wire lsu_bus_obuf_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:42:4 + input wire lsu_busm_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:43:4 + input wire lsu_c2_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:44:4 + input wire lsu_bus_ibuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:45:4 + input wire lsu_bus_obuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:46:4 + input wire lsu_bus_buf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:47:4 + input wire lsu_free_c2_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:48:4 + input wire lsu_busm_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:51:4 + input wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:52:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:53:4 + input wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:55:4 + input wire [31:0] lsu_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:56:4 + input wire [31:0] end_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:57:4 + input wire [31:0] lsu_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:58:4 + input wire [31:0] end_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:59:4 + input wire [31:0] store_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:61:4 + input wire no_word_merge_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:62:4 + input wire no_dword_merge_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:63:4 + input wire lsu_busreq_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:64:4 + output wire lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:65:4 + input wire ld_full_hit_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:66:4 + input wire flush_m_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:67:4 + input wire flush_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:68:4 + input wire lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:69:4 + input wire is_sideeffects_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:70:4 + input wire ldst_dual_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:71:4 + input wire ldst_dual_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:72:4 + input wire ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:74:4 + input wire [7:0] ldst_byteen_ext_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:76:4 + output wire lsu_bus_buffer_pend_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:77:4 + output wire lsu_bus_buffer_full_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:78:4 + output wire lsu_bus_buffer_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:80:4 + output wire [3:0] ld_byte_hit_buf_lo; + output wire [3:0] ld_byte_hit_buf_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:81:4 + output reg [31:0] ld_fwddata_buf_lo; + output reg [31:0] ld_fwddata_buf_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:83:4 + output wire lsu_imprecise_error_load_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:84:4 + output reg lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:85:4 + output wire [31:0] lsu_imprecise_error_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:88:4 + output wire lsu_nonblock_load_valid_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:89:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:90:4 + output wire lsu_nonblock_load_inv_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:91:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:92:4 + output wire lsu_nonblock_load_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:93:4 + output reg lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:94:4 + output reg [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:95:4 + output wire [31:0] lsu_nonblock_load_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:98:4 + output wire lsu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:99:4 + output wire lsu_pmu_bus_misaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:100:4 + output wire lsu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:101:4 + output wire lsu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:104:4 + output wire lsu_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:105:4 + input wire lsu_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:106:4 + output wire [pt[181-:8] - 1:0] lsu_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:107:4 + output wire [31:0] lsu_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:108:4 + output wire [3:0] lsu_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:109:4 + output wire [7:0] lsu_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:110:4 + output wire [2:0] lsu_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:111:4 + output wire [1:0] lsu_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:112:4 + output wire lsu_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:113:4 + output wire [3:0] lsu_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:114:4 + output wire [2:0] lsu_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:115:4 + output wire [3:0] lsu_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:117:4 + output wire lsu_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:118:4 + input wire lsu_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:119:4 + output wire [63:0] lsu_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:120:4 + output wire [7:0] lsu_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:121:4 + output wire lsu_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:123:4 + input wire lsu_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:124:4 + output wire lsu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:125:4 + input wire [1:0] lsu_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:126:4 + input wire [pt[181-:8] - 1:0] lsu_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:129:4 + output wire lsu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:130:4 + input wire lsu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:131:4 + output wire [pt[181-:8] - 1:0] lsu_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:132:4 + output wire [31:0] lsu_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:133:4 + output wire [3:0] lsu_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:134:4 + output wire [7:0] lsu_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:135:4 + output wire [2:0] lsu_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:136:4 + output wire [1:0] lsu_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:137:4 + output wire lsu_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:138:4 + output wire [3:0] lsu_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:139:4 + output wire [2:0] lsu_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:140:4 + output wire [3:0] lsu_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:142:4 + input wire lsu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:143:4 + output wire lsu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:144:4 + input wire [pt[181-:8] - 1:0] lsu_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:145:4 + input wire [63:0] lsu_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:146:4 + input wire [1:0] lsu_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:148:4 + input wire lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:149:4 + input wire lsu_bus_clk_en_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:155:4 + // removed localparam type state_t + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:157:4 + localparam DEPTH = pt[173-:9]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:158:4 + localparam DEPTH_LOG2 = pt[164-:7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:159:4 + localparam TIMER = 8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:160:4 + localparam TIMER_MAX = 7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:161:4 + localparam TIMER_LOG2 = 3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:163:4 + wire [3:0] ldst_byteen_hi_m; + wire [3:0] ldst_byteen_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:164:4 + wire [DEPTH - 1:0] ld_addr_hitvec_lo; + wire [DEPTH - 1:0] ld_addr_hitvec_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:165:4 + wire [(4 * DEPTH) - 1:0] ld_byte_hitvec_lo; + wire [(4 * DEPTH) - 1:0] ld_byte_hitvec_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:166:4 + wire [(4 * DEPTH) - 1:0] ld_byte_hitvecfn_lo; + wire [(4 * DEPTH) - 1:0] ld_byte_hitvecfn_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:168:4 + wire ld_addr_ibuf_hit_lo; + wire ld_addr_ibuf_hit_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:169:4 + wire [3:0] ld_byte_ibuf_hit_lo; + wire [3:0] ld_byte_ibuf_hit_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:171:4 + wire [3:0] ldst_byteen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:172:4 + wire [3:0] ldst_byteen_hi_r; + wire [3:0] ldst_byteen_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:173:4 + wire [31:0] store_data_hi_r; + wire [31:0] store_data_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:174:4 + wire is_aligned_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:175:4 + wire ldst_samedw_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:177:4 + wire lsu_nonblock_load_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:178:4 + reg [31:0] lsu_nonblock_load_data_hi; + reg [31:0] lsu_nonblock_load_data_lo; + wire [31:0] lsu_nonblock_data_unalgn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:179:4 + wire [1:0] lsu_nonblock_addr_offset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:180:4 + wire [1:0] lsu_nonblock_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:181:4 + wire lsu_nonblock_unsign; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:182:4 + reg lsu_nonblock_load_data_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:184:4 + wire [DEPTH - 1:0] CmdPtr0Dec; + wire [DEPTH - 1:0] CmdPtr1Dec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:185:4 + wire [DEPTH - 1:0] RspPtrDec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:186:4 + wire [DEPTH_LOG2 - 1:0] CmdPtr0; + wire [DEPTH_LOG2 - 1:0] CmdPtr1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:187:4 + wire [DEPTH_LOG2 - 1:0] RspPtr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:188:4 + reg [DEPTH_LOG2 - 1:0] WrPtr0_m; + wire [DEPTH_LOG2 - 1:0] WrPtr0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:189:4 + reg [DEPTH_LOG2 - 1:0] WrPtr1_m; + wire [DEPTH_LOG2 - 1:0] WrPtr1_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:190:4 + reg found_wrptr0; + reg found_wrptr1; + wire found_cmdptr0; + wire found_cmdptr1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:191:4 + reg [3:0] buf_numvld_any; + reg [3:0] buf_numvld_wrcmd_any; + reg [3:0] buf_numvld_cmd_any; + reg [3:0] buf_numvld_pend_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:192:4 + reg any_done_wait_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:193:4 + reg bus_sideeffect_pend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:194:4 + wire bus_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:196:4 + reg bus_addr_match_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:197:4 + wire bus_cmd_sent; + wire bus_cmd_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:198:4 + wire bus_wcmd_sent; + wire bus_wdata_sent; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:199:4 + wire bus_rsp_read; + wire bus_rsp_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:200:4 + wire [pt[181-:8] - 1:0] bus_rsp_read_tag; + wire [pt[181-:8] - 1:0] bus_rsp_write_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:201:4 + wire bus_rsp_read_error; + wire bus_rsp_write_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:202:4 + wire [63:0] bus_rsp_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:205:4 + wire [(DEPTH * 3) - 1:0] buf_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:206:4 + wire [(DEPTH * 2) - 1:0] buf_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:207:4 + wire [(DEPTH * 32) - 1:0] buf_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:208:4 + wire [(DEPTH * 4) - 1:0] buf_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:209:4 + wire [DEPTH - 1:0] buf_sideeffect; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:210:4 + wire [DEPTH - 1:0] buf_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:211:4 + wire [DEPTH - 1:0] buf_unsign; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:212:4 + wire [DEPTH - 1:0] buf_dual; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:213:4 + wire [DEPTH - 1:0] buf_samedw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:214:4 + wire [DEPTH - 1:0] buf_nomerge; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:215:4 + wire [DEPTH - 1:0] buf_dualhi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:216:4 + wire [(DEPTH * DEPTH_LOG2) - 1:0] buf_dualtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:217:4 + wire [DEPTH - 1:0] buf_ldfwd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:218:4 + wire [(DEPTH * DEPTH_LOG2) - 1:0] buf_ldfwdtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:219:4 + wire [DEPTH - 1:0] buf_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:220:4 + wire [(DEPTH * 32) - 1:0] buf_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:221:4 + wire [(DEPTH * DEPTH) - 1:0] buf_age; + wire [(DEPTH * DEPTH) - 1:0] buf_age_younger; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:222:4 + wire [(DEPTH * DEPTH) - 1:0] buf_rspage; + wire [(DEPTH * DEPTH) - 1:0] buf_rsp_pickage; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:224:4 + reg [(DEPTH * 3) - 1:0] buf_nxtstate; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:225:4 + reg [DEPTH - 1:0] buf_rst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:226:4 + reg [DEPTH - 1:0] buf_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:227:4 + reg [DEPTH - 1:0] buf_cmd_state_bus_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:228:4 + reg [DEPTH - 1:0] buf_resp_state_bus_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:229:4 + reg [DEPTH - 1:0] buf_state_bus_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:230:4 + wire [DEPTH - 1:0] buf_dual_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:231:4 + wire [DEPTH - 1:0] buf_samedw_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:232:4 + wire [DEPTH - 1:0] buf_nomerge_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:233:4 + wire [DEPTH - 1:0] buf_sideeffect_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:234:4 + wire [DEPTH - 1:0] buf_unsign_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:235:4 + wire [(DEPTH * 2) - 1:0] buf_sz_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:236:4 + wire [DEPTH - 1:0] buf_write_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:237:4 + reg [DEPTH - 1:0] buf_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:238:4 + wire [DEPTH - 1:0] buf_dualhi_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:239:4 + wire [(DEPTH * DEPTH_LOG2) - 1:0] buf_dualtag_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:240:4 + reg [DEPTH - 1:0] buf_ldfwd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:241:4 + reg [DEPTH - 1:0] buf_ldfwd_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:242:4 + reg [(DEPTH * DEPTH_LOG2) - 1:0] buf_ldfwdtag_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:243:4 + wire [(DEPTH * 4) - 1:0] buf_byteen_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:244:4 + wire [(DEPTH * 32) - 1:0] buf_addr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:245:4 + reg [(DEPTH * 32) - 1:0] buf_data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:246:4 + reg [DEPTH - 1:0] buf_error_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:247:4 + reg [DEPTH - 1:0] buf_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:248:4 + wire [(DEPTH * DEPTH) - 1:0] buf_age_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:249:4 + wire [(DEPTH * DEPTH) - 1:0] buf_ageQ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:250:4 + wire [(DEPTH * DEPTH) - 1:0] buf_rspage_set; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:251:4 + wire [(DEPTH * DEPTH) - 1:0] buf_rspage_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:252:4 + wire [(DEPTH * DEPTH) - 1:0] buf_rspageQ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:255:4 + wire ibuf_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:256:4 + wire ibuf_dual; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:257:4 + wire ibuf_samedw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:258:4 + wire ibuf_nomerge; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:259:4 + wire [DEPTH_LOG2 - 1:0] ibuf_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:260:4 + wire [DEPTH_LOG2 - 1:0] ibuf_dualtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:261:4 + wire ibuf_sideeffect; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:262:4 + wire ibuf_unsign; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:263:4 + wire ibuf_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:264:4 + wire [1:0] ibuf_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:265:4 + wire [3:0] ibuf_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:266:4 + wire [31:0] ibuf_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:267:4 + wire [31:0] ibuf_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:268:4 + wire [2:0] ibuf_timer; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:270:4 + wire ibuf_byp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:271:4 + wire ibuf_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:272:4 + wire ibuf_rst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:273:4 + wire ibuf_force_drain; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:274:4 + wire ibuf_drain_vld; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:275:4 + wire [DEPTH - 1:0] ibuf_drainvec_vld; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:276:4 + wire [DEPTH_LOG2 - 1:0] ibuf_tag_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:277:4 + wire [DEPTH_LOG2 - 1:0] ibuf_dualtag_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:278:4 + wire [1:0] ibuf_sz_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:279:4 + wire [31:0] ibuf_addr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:280:4 + wire [3:0] ibuf_byteen_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:281:4 + wire [31:0] ibuf_data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:282:4 + wire [2:0] ibuf_timer_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:283:4 + wire [3:0] ibuf_byteen_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:284:4 + wire [31:0] ibuf_data_out; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:285:4 + wire ibuf_merge_en; + wire ibuf_merge_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:288:4 + wire obuf_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:289:4 + wire obuf_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:290:4 + wire obuf_nosend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:291:4 + wire obuf_rdrsp_pend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:292:4 + wire obuf_sideeffect; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:293:4 + wire [31:0] obuf_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:294:4 + wire [63:0] obuf_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:295:4 + wire [1:0] obuf_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:296:4 + wire [7:0] obuf_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:297:4 + wire obuf_merge; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:298:4 + wire obuf_cmd_done; + wire obuf_data_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:299:4 + wire [pt[181-:8] - 1:0] obuf_tag0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:300:4 + wire [pt[181-:8] - 1:0] obuf_tag1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:301:4 + wire [pt[181-:8] - 1:0] obuf_rdrsp_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:303:4 + wire ibuf_buf_byp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:304:4 + wire obuf_force_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:305:4 + wire obuf_wr_wait; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:306:4 + wire obuf_wr_en; + wire obuf_wr_enQ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:307:4 + wire obuf_rst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:308:4 + wire obuf_write_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:309:4 + wire obuf_nosend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:310:4 + wire obuf_rdrsp_pend_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:311:4 + wire obuf_rdrsp_pend_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:312:4 + wire obuf_sideeffect_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:313:4 + wire obuf_aligned_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:314:4 + wire [31:0] obuf_addr_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:315:4 + wire [63:0] obuf_data_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:316:4 + wire [1:0] obuf_sz_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:317:4 + wire [7:0] obuf_byteen_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:318:4 + wire obuf_merge_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:319:4 + wire obuf_cmd_done_in; + wire obuf_data_done_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:320:4 + wire [pt[181-:8] - 1:0] obuf_tag0_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:321:4 + wire [pt[181-:8] - 1:0] obuf_tag1_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:322:4 + wire [pt[181-:8] - 1:0] obuf_rdrsp_tag_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:324:4 + wire obuf_merge_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:325:4 + wire [2:0] obuf_wr_timer; + wire [2:0] obuf_wr_timer_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:326:4 + wire [7:0] obuf_byteen0_in; + wire [7:0] obuf_byteen1_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:327:4 + wire [63:0] obuf_data0_in; + wire [63:0] obuf_data1_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:329:4 + wire lsu_axi_awvalid_q; + wire lsu_axi_awready_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:330:4 + wire lsu_axi_wvalid_q; + wire lsu_axi_wready_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:331:4 + wire lsu_axi_arvalid_q; + wire lsu_axi_arready_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:332:4 + wire lsu_axi_bvalid_q; + wire lsu_axi_bready_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:333:4 + wire lsu_axi_rvalid_q; + wire lsu_axi_rready_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:334:4 + wire [pt[181-:8] - 1:0] lsu_axi_bid_q; + wire [pt[181-:8] - 1:0] lsu_axi_rid_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:335:4 + wire [1:0] lsu_axi_bresp_q; + wire [1:0] lsu_axi_rresp_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:336:4 + reg [pt[181-:8] - 1:0] lsu_imprecise_error_store_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:337:4 + wire [63:0] lsu_axi_rdata_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:344:4 + function automatic [2:0] f_Enc8to3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:345:7 + input reg [7:0] Dec_value; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:347:7 + reg [2:0] Enc_value; + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:348:7 + Enc_value[0] = ((Dec_value[1] | Dec_value[3]) | Dec_value[5]) | Dec_value[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:349:7 + Enc_value[1] = ((Dec_value[2] | Dec_value[3]) | Dec_value[6]) | Dec_value[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:350:7 + Enc_value[2] = ((Dec_value[4] | Dec_value[5]) | Dec_value[6]) | Dec_value[7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:352:7 + f_Enc8to3 = Enc_value[2:0]; + end + endfunction + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:356:4 + assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:357:4 + assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:358:4 + genvar _gv_i_36; + generate + for (_gv_i_36 = 0; _gv_i_36 < DEPTH; _gv_i_36 = _gv_i_36 + 1) begin : genblk1 + localparam i = _gv_i_36; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:359:7 + assign ld_addr_hitvec_lo[i] = (((lsu_addr_m[31:2] == buf_addr[(i * 32) + 31-:30]) & buf_write[i]) & (buf_state[i * 3+:3] != 3'b000)) & lsu_busreq_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:360:7 + assign ld_addr_hitvec_hi[i] = (((end_addr_m[31:2] == buf_addr[(i * 32) + 31-:30]) & buf_write[i]) & (buf_state[i * 3+:3] != 3'b000)) & lsu_busreq_m; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:363:4 + genvar _gv_j_7; + generate + for (_gv_j_7 = 0; _gv_j_7 < 4; _gv_j_7 = _gv_j_7 + 1) begin : genblk2 + localparam j = _gv_j_7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:364:6 + assign ld_byte_hit_buf_lo[j] = |ld_byte_hitvecfn_lo[j * DEPTH+:DEPTH] | ld_byte_ibuf_hit_lo[j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:365:6 + assign ld_byte_hit_buf_hi[j] = |ld_byte_hitvecfn_hi[j * DEPTH+:DEPTH] | ld_byte_ibuf_hit_hi[j]; + genvar _gv_i_37; + for (_gv_i_37 = 0; _gv_i_37 < DEPTH; _gv_i_37 = _gv_i_37 + 1) begin : genblk1 + localparam i = _gv_i_37; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:367:10 + assign ld_byte_hitvec_lo[(j * DEPTH) + i] = (ld_addr_hitvec_lo[i] & buf_byteen[(i * 4) + j]) & ldst_byteen_lo_m[j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:368:10 + assign ld_byte_hitvec_hi[(j * DEPTH) + i] = (ld_addr_hitvec_hi[i] & buf_byteen[(i * 4) + j]) & ldst_byteen_hi_m[j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:370:10 + assign ld_byte_hitvecfn_lo[(j * DEPTH) + i] = (ld_byte_hitvec_lo[(j * DEPTH) + i] & ~(|(ld_byte_hitvec_lo[j * DEPTH+:DEPTH] & buf_age_younger[i * DEPTH+:DEPTH]))) & ~ld_byte_ibuf_hit_lo[j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:371:10 + assign ld_byte_hitvecfn_hi[(j * DEPTH) + i] = (ld_byte_hitvec_hi[(j * DEPTH) + i] & ~(|(ld_byte_hitvec_hi[j * DEPTH+:DEPTH] & buf_age_younger[i * DEPTH+:DEPTH]))) & ~ld_byte_ibuf_hit_hi[j]; + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:376:4 + assign ld_addr_ibuf_hit_lo = (((lsu_addr_m[31:2] == ibuf_addr[31:2]) & ibuf_write) & ibuf_valid) & lsu_busreq_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:377:4 + assign ld_addr_ibuf_hit_hi = (((end_addr_m[31:2] == ibuf_addr[31:2]) & ibuf_write) & ibuf_valid) & lsu_busreq_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:379:4 + genvar _gv_i_38; + generate + for (_gv_i_38 = 0; _gv_i_38 < 4; _gv_i_38 = _gv_i_38 + 1) begin : genblk3 + localparam i = _gv_i_38; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:380:7 + assign ld_byte_ibuf_hit_lo[i] = (ld_addr_ibuf_hit_lo & ibuf_byteen[i]) & ldst_byteen_lo_m[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:381:7 + assign ld_byte_ibuf_hit_hi[i] = (ld_addr_ibuf_hit_hi & ibuf_byteen[i]) & ldst_byteen_hi_m[i]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:384:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:385:7 + ld_fwddata_buf_lo[31:0] = {{8 {ld_byte_ibuf_hit_lo[3]}}, {8 {ld_byte_ibuf_hit_lo[2]}}, {8 {ld_byte_ibuf_hit_lo[1]}}, {8 {ld_byte_ibuf_hit_lo[0]}}} & ibuf_data[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:386:7 + ld_fwddata_buf_hi[31:0] = {{8 {ld_byte_ibuf_hit_hi[3]}}, {8 {ld_byte_ibuf_hit_hi[2]}}, {8 {ld_byte_ibuf_hit_hi[1]}}, {8 {ld_byte_ibuf_hit_hi[0]}}} & ibuf_data[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:387:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:387:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:387:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:388:10 + ld_fwddata_buf_lo[7:0] = ld_fwddata_buf_lo[7:0] | ({8 {ld_byte_hitvecfn_lo[0 + i]}} & buf_data[(i * 32) + 7-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:389:10 + ld_fwddata_buf_lo[15:8] = ld_fwddata_buf_lo[15:8] | ({8 {ld_byte_hitvecfn_lo[DEPTH + i]}} & buf_data[(i * 32) + 15-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:390:10 + ld_fwddata_buf_lo[23:16] = ld_fwddata_buf_lo[23:16] | ({8 {ld_byte_hitvecfn_lo[(2 * DEPTH) + i]}} & buf_data[(i * 32) + 23-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:391:10 + ld_fwddata_buf_lo[31:24] = ld_fwddata_buf_lo[31:24] | ({8 {ld_byte_hitvecfn_lo[(3 * DEPTH) + i]}} & buf_data[(i * 32) + 31-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:393:10 + ld_fwddata_buf_hi[7:0] = ld_fwddata_buf_hi[7:0] | ({8 {ld_byte_hitvecfn_hi[0 + i]}} & buf_data[(i * 32) + 7-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:394:10 + ld_fwddata_buf_hi[15:8] = ld_fwddata_buf_hi[15:8] | ({8 {ld_byte_hitvecfn_hi[DEPTH + i]}} & buf_data[(i * 32) + 15-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:395:10 + ld_fwddata_buf_hi[23:16] = ld_fwddata_buf_hi[23:16] | ({8 {ld_byte_hitvecfn_hi[(2 * DEPTH) + i]}} & buf_data[(i * 32) + 23-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:396:10 + ld_fwddata_buf_hi[31:24] = ld_fwddata_buf_hi[31:24] | ({8 {ld_byte_hitvecfn_hi[(3 * DEPTH) + i]}} & buf_data[(i * 32) + 31-:8]); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:404:4 + assign bus_coalescing_disable = dec_tlu_wb_coalescing_disable | pt[2038]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:407:4 + assign ldst_byteen_r[3:0] = (({4 {lsu_pkt_r[11]}} & 4'b0001) | ({4 {lsu_pkt_r[10]}} & 4'b0011)) | ({4 {lsu_pkt_r[9]}} & 4'b1111); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:411:4 + assign {ldst_byteen_hi_r[3:0], ldst_byteen_lo_r[3:0]} = {4'b0000, ldst_byteen_r[3:0]} << lsu_addr_r[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:412:4 + assign {store_data_hi_r[31:0], store_data_lo_r[31:0]} = {32'b00000000000000000000000000000000, store_data_r[31:0]} << (8 * lsu_addr_r[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:413:4 + assign ldst_samedw_r = lsu_addr_r[3] == end_addr_r[3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:414:4 + assign is_aligned_r = ((lsu_pkt_r[9] & (lsu_addr_r[1:0] == 2'b00)) | (lsu_pkt_r[10] & (lsu_addr_r[0] == 1'b0))) | lsu_pkt_r[11]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:422:4 + assign ibuf_byp = (lsu_busreq_r & (lsu_pkt_r[7] | no_word_merge_r)) & ~ibuf_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:423:4 + assign ibuf_wr_en = (lsu_busreq_r & lsu_commit_r) & ~ibuf_byp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:424:4 + assign ibuf_rst = (ibuf_drain_vld & ~ibuf_wr_en) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:425:4 + assign ibuf_force_drain = ((lsu_busreq_m & ~lsu_busreq_r) & ibuf_valid) & (lsu_pkt_m[7] | (ibuf_addr[31:2] != lsu_addr_m[31:2])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:426:4 + assign ibuf_drain_vld = ibuf_valid & (((((((ibuf_wr_en | (ibuf_timer == TIMER_MAX)) & ~(ibuf_merge_en & ibuf_merge_in)) | ibuf_byp) | ibuf_force_drain) | ibuf_sideeffect) | ~ibuf_write) | bus_coalescing_disable); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:427:4 + assign ibuf_tag_in[DEPTH_LOG2 - 1:0] = (ibuf_merge_en & ibuf_merge_in ? ibuf_tag[DEPTH_LOG2 - 1:0] : (ldst_dual_r ? WrPtr1_r : WrPtr0_r)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:428:4 + assign ibuf_dualtag_in[DEPTH_LOG2 - 1:0] = WrPtr0_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:429:4 + assign ibuf_sz_in[1:0] = {lsu_pkt_r[9], lsu_pkt_r[10]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:430:4 + assign ibuf_addr_in[31:0] = (ldst_dual_r ? end_addr_r[31:0] : lsu_addr_r[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:431:4 + assign ibuf_byteen_in[3:0] = (ibuf_merge_en & ibuf_merge_in ? ibuf_byteen[3:0] | ldst_byteen_lo_r[3:0] : (ldst_dual_r ? ldst_byteen_hi_r[3:0] : ldst_byteen_lo_r[3:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:432:4 + genvar _gv_i_39; + generate + for (_gv_i_39 = 0; _gv_i_39 < 4; _gv_i_39 = _gv_i_39 + 1) begin : genblk4 + localparam i = _gv_i_39; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:433:7 + assign ibuf_data_in[(8 * i) + 7:8 * i] = (ibuf_merge_en & ibuf_merge_in ? (ldst_byteen_lo_r[i] ? store_data_lo_r[(8 * i) + 7:8 * i] : ibuf_data[(8 * i) + 7:8 * i]) : (ldst_dual_r ? store_data_hi_r[(8 * i) + 7:8 * i] : store_data_lo_r[(8 * i) + 7:8 * i])); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:436:4 + assign ibuf_timer_in = (ibuf_wr_en ? {3 {1'sb0}} : (ibuf_timer < TIMER_MAX ? ibuf_timer + 1'b1 : ibuf_timer)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:439:4 + assign ibuf_merge_en = ((((((lsu_busreq_r & lsu_commit_r) & lsu_pkt_r[6]) & ibuf_valid) & ibuf_write) & (lsu_addr_r[31:2] == ibuf_addr[31:2])) & ~is_sideeffects_r) & ~bus_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:440:4 + assign ibuf_merge_in = ~ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:443:4 + genvar _gv_i_40; + generate + for (_gv_i_40 = 0; _gv_i_40 < 4; _gv_i_40 = _gv_i_40 + 1) begin : genblk5 + localparam i = _gv_i_40; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:444:7 + assign ibuf_byteen_out[i] = (ibuf_merge_en & ~ibuf_merge_in ? ibuf_byteen[i] | ldst_byteen_lo_r[i] : ibuf_byteen[i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:445:7 + assign ibuf_data_out[(8 * i) + 7:8 * i] = (ibuf_merge_en & ~ibuf_merge_in ? (ldst_byteen_lo_r[i] ? store_data_lo_r[(8 * i) + 7:8 * i] : ibuf_data[(8 * i) + 7:8 * i]) : ibuf_data[(8 * i) + 7:8 * i]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:449:4 + rvdffsc #(.WIDTH(1)) ibuf_valid_ff( + .din(1'b1), + .dout(ibuf_valid), + .en(ibuf_wr_en), + .clear(ibuf_rst), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:450:4 + rvdffs #(.WIDTH(DEPTH_LOG2)) ibuf_tagff( + .din(ibuf_tag_in), + .dout(ibuf_tag), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:451:4 + rvdffs #(.WIDTH(DEPTH_LOG2)) ibuf_dualtagff( + .din(ibuf_dualtag_in), + .dout(ibuf_dualtag), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:452:4 + rvdffs #(.WIDTH(1)) ibuf_dualff( + .din(ldst_dual_r), + .dout(ibuf_dual), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:453:4 + rvdffs #(.WIDTH(1)) ibuf_samedwff( + .din(ldst_samedw_r), + .dout(ibuf_samedw), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:454:4 + rvdffs #(.WIDTH(1)) ibuf_nomergeff( + .din(no_dword_merge_r), + .dout(ibuf_nomerge), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:455:4 + rvdffs #(.WIDTH(1)) ibuf_sideeffectff( + .din(is_sideeffects_r), + .dout(ibuf_sideeffect), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:456:4 + rvdffs #(.WIDTH(1)) ibuf_unsignff( + .din(lsu_pkt_r[5]), + .dout(ibuf_unsign), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:457:4 + rvdffs #(.WIDTH(1)) ibuf_writeff( + .din(lsu_pkt_r[6]), + .dout(ibuf_write), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:458:4 + rvdffs #(.WIDTH(2)) ibuf_szff( + .din(ibuf_sz_in[1:0]), + .dout(ibuf_sz), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:459:4 + rvdffe #(.WIDTH(32)) ibuf_addrff( + .din(ibuf_addr_in[31:0]), + .dout(ibuf_addr), + .en(ibuf_wr_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:460:4 + rvdffs #(.WIDTH(4)) ibuf_byteenff( + .din(ibuf_byteen_in[3:0]), + .dout(ibuf_byteen), + .en(ibuf_wr_en), + .clk(lsu_bus_ibuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:461:4 + rvdffe #(.WIDTH(32)) ibuf_dataff( + .din(ibuf_data_in[31:0]), + .dout(ibuf_data), + .en(ibuf_wr_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:462:4 + rvdff #(.WIDTH(TIMER_LOG2)) ibuf_timerff( + .din(ibuf_timer_in), + .dout(ibuf_timer), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:474:4 + assign obuf_wr_wait = ((((((buf_numvld_wrcmd_any[3:0] == 4'b0001) & (buf_numvld_cmd_any[3:0] == 4'b0001)) & (obuf_wr_timer != TIMER_MAX)) & ~bus_coalescing_disable) & ~buf_nomerge[CmdPtr0]) & ~buf_sideeffect[CmdPtr0]) & ~obuf_force_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:476:4 + assign obuf_wr_timer_in = (obuf_wr_en ? 3'b000 : ((buf_numvld_cmd_any > 4'b0000) & (obuf_wr_timer < TIMER_MAX) ? obuf_wr_timer + 1'b1 : obuf_wr_timer)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:477:4 + assign obuf_force_wr_en = (((lsu_busreq_m & ~lsu_busreq_r) & ~ibuf_valid) & (buf_numvld_cmd_any[3:0] == 4'b0001)) & (lsu_addr_m[31:2] != buf_addr[(CmdPtr0 * 32) + 31-:30]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:478:4 + assign ibuf_buf_byp = (ibuf_byp & (buf_numvld_pend_any[3:0] == 4'b0000)) & (~lsu_pkt_r[6] | no_dword_merge_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:480:4 + assign obuf_wr_en = ((((((ibuf_buf_byp & lsu_commit_r) & ~(is_sideeffects_r & bus_sideeffect_pend)) | (((((buf_state[CmdPtr0 * 3+:3] == 3'b010) & found_cmdptr0) & ~buf_cmd_state_bus_en[CmdPtr0]) & ~(buf_sideeffect[CmdPtr0] & bus_sideeffect_pend)) & (((~((buf_dual[CmdPtr0] & buf_samedw[CmdPtr0]) & ~buf_write[CmdPtr0]) | found_cmdptr1) | buf_nomerge[CmdPtr0]) | obuf_force_wr_en))) & ((bus_cmd_ready | ~obuf_valid) | obuf_nosend)) & ~obuf_wr_wait) & ~bus_addr_match_pending) & lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:485:4 + assign obuf_rst = (((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en) & lsu_bus_clk_en) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:487:4 + assign obuf_write_in = (ibuf_buf_byp ? lsu_pkt_r[6] : buf_write[CmdPtr0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:488:4 + assign obuf_sideeffect_in = (ibuf_buf_byp ? is_sideeffects_r : buf_sideeffect[CmdPtr0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:489:4 + assign obuf_addr_in[31:0] = (ibuf_buf_byp ? lsu_addr_r[31:0] : buf_addr[CmdPtr0 * 32+:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:490:4 + assign obuf_sz_in[1:0] = (ibuf_buf_byp ? {lsu_pkt_r[9], lsu_pkt_r[10]} : buf_sz[CmdPtr0 * 2+:2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:491:4 + assign obuf_merge_in = obuf_merge_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:492:4 + function automatic [pt[181-:8] - 1:0] sv2v_cast_E7F3A; + input reg [pt[181-:8] - 1:0] inp; + sv2v_cast_E7F3A = inp; + endfunction + assign obuf_tag0_in[pt[181-:8] - 1:0] = (ibuf_buf_byp ? sv2v_cast_E7F3A(WrPtr0_r) : sv2v_cast_E7F3A(CmdPtr0)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:493:4 + assign obuf_tag1_in[pt[181-:8] - 1:0] = (ibuf_buf_byp ? sv2v_cast_E7F3A(WrPtr1_r) : sv2v_cast_E7F3A(CmdPtr1)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:495:4 + assign obuf_cmd_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:496:4 + assign obuf_data_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:498:4 + assign obuf_aligned_in = (ibuf_buf_byp ? is_aligned_r : ((obuf_sz_in[1:0] == 2'b00) | (obuf_sz_in[0] & ~obuf_addr_in[0])) | (obuf_sz_in[1] & ~(|obuf_addr_in[1:0]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:502:4 + assign obuf_rdrsp_pend_in = (((~(obuf_wr_en & ~obuf_nosend_in) & obuf_rdrsp_pend) & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag))) | (bus_cmd_sent & ~obuf_write)) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:503:4 + assign obuf_rdrsp_pend_en = lsu_bus_clk_en | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:504:4 + assign obuf_rdrsp_tag_in[pt[181-:8] - 1:0] = (bus_cmd_sent & ~obuf_write ? obuf_tag0[pt[181-:8] - 1:0] : obuf_rdrsp_tag[pt[181-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:506:4 + assign obuf_nosend_in = ((((((obuf_addr_in[31:3] == obuf_addr[31:3]) & obuf_aligned_in) & ~obuf_sideeffect) & ~obuf_write) & ~obuf_write_in) & ~dec_tlu_external_ldfwd_disable) & ((obuf_valid & ~obuf_nosend) | (obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:509:4 + assign obuf_byteen0_in[7:0] = (ibuf_buf_byp ? (lsu_addr_r[2] ? {ldst_byteen_lo_r[3:0], 4'b0000} : {4'b0000, ldst_byteen_lo_r[3:0]}) : (buf_addr[(CmdPtr0 * 32) + 2] ? {buf_byteen[CmdPtr0 * 4+:4], 4'b0000} : {4'b0000, buf_byteen[CmdPtr0 * 4+:4]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:511:4 + assign obuf_byteen1_in[7:0] = (ibuf_buf_byp ? (end_addr_r[2] ? {ldst_byteen_hi_r[3:0], 4'b0000} : {4'b0000, ldst_byteen_hi_r[3:0]}) : (buf_addr[(CmdPtr1 * 32) + 2] ? {buf_byteen[CmdPtr1 * 4+:4], 4'b0000} : {4'b0000, buf_byteen[CmdPtr1 * 4+:4]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:513:4 + assign obuf_data0_in[63:0] = (ibuf_buf_byp ? (lsu_addr_r[2] ? {store_data_lo_r[31:0], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, store_data_lo_r[31:0]}) : (buf_addr[(CmdPtr0 * 32) + 2] ? {buf_data[CmdPtr0 * 32+:32], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, buf_data[CmdPtr0 * 32+:32]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:515:4 + assign obuf_data1_in[63:0] = (ibuf_buf_byp ? (end_addr_r[2] ? {store_data_hi_r[31:0], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, store_data_hi_r[31:0]}) : (buf_addr[(CmdPtr1 * 32) + 2] ? {buf_data[CmdPtr1 * 32+:32], 32'b00000000000000000000000000000000} : {32'b00000000000000000000000000000000, buf_data[CmdPtr1 * 32+:32]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:518:4 + genvar _gv_i_41; + generate + for (_gv_i_41 = 0; _gv_i_41 < 8; _gv_i_41 = _gv_i_41 + 1) begin : genblk6 + localparam i = _gv_i_41; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:519:7 + assign obuf_byteen_in[i] = obuf_byteen0_in[i] | (obuf_merge_en & obuf_byteen1_in[i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:520:7 + assign obuf_data_in[(8 * i) + 7:8 * i] = (obuf_merge_en & obuf_byteen1_in[i] ? obuf_data1_in[(8 * i) + 7:8 * i] : obuf_data0_in[(8 * i) + 7:8 * i]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:524:4 + assign obuf_merge_en = ((((((((CmdPtr0 != CmdPtr1) & found_cmdptr0) & found_cmdptr1) & (buf_state[CmdPtr0 * 3+:3] == 3'b010)) & (buf_state[CmdPtr1 * 3+:3] == 3'b010)) & ~buf_cmd_state_bus_en[CmdPtr0]) & ~buf_sideeffect[CmdPtr0]) & (((~buf_write[CmdPtr0] & buf_dual[CmdPtr0]) & ~buf_dualhi[CmdPtr0]) & buf_samedw[CmdPtr0])) | ((ibuf_buf_byp & ldst_samedw_r) & ldst_dual_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:530:4 + rvdff_fpga #(.WIDTH(1)) obuf_wren_ff( + .din(obuf_wr_en), + .dout(obuf_wr_enQ), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:531:4 + rvdffsc #(.WIDTH(1)) obuf_valid_ff( + .din(1'b1), + .dout(obuf_valid), + .en(obuf_wr_en), + .clear(obuf_rst), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:532:4 + rvdffs #(.WIDTH(1)) obuf_nosend_ff( + .din(obuf_nosend_in), + .dout(obuf_nosend), + .en(obuf_wr_en), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:533:4 + rvdffs #(.WIDTH(1)) obuf_rdrsp_pend_ff( + .din(obuf_rdrsp_pend_in), + .dout(obuf_rdrsp_pend), + .en(obuf_rdrsp_pend_en), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:534:4 + rvdff_fpga #(.WIDTH(1)) obuf_cmd_done_ff( + .din(obuf_cmd_done_in), + .dout(obuf_cmd_done), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:535:4 + rvdff_fpga #(.WIDTH(1)) obuf_data_done_ff( + .din(obuf_data_done_in), + .dout(obuf_data_done), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:536:4 + rvdff_fpga #(.WIDTH(pt[181-:8])) obuf_rdrsp_tagff( + .din(obuf_rdrsp_tag_in), + .dout(obuf_rdrsp_tag), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:537:4 + rvdffs_fpga #(.WIDTH(pt[181-:8])) obuf_tag0ff( + .din(obuf_tag0_in), + .dout(obuf_tag0), + .en(obuf_wr_en), + .clk(lsu_bus_obuf_c1_clk), + .clken(lsu_bus_obuf_c1_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:538:4 + rvdffs_fpga #(.WIDTH(pt[181-:8])) obuf_tag1ff( + .din(obuf_tag1_in), + .dout(obuf_tag1), + .en(obuf_wr_en), + .clk(lsu_bus_obuf_c1_clk), + .clken(lsu_bus_obuf_c1_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:539:4 + rvdffs_fpga #(.WIDTH(1)) obuf_mergeff( + .din(obuf_merge_in), + .dout(obuf_merge), + .en(obuf_wr_en), + .clk(lsu_bus_obuf_c1_clk), + .clken(lsu_bus_obuf_c1_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:540:4 + rvdffs_fpga #(.WIDTH(1)) obuf_writeff( + .din(obuf_write_in), + .dout(obuf_write), + .en(obuf_wr_en), + .clk(lsu_bus_obuf_c1_clk), + .clken(lsu_bus_obuf_c1_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:541:4 + rvdffs_fpga #(.WIDTH(1)) obuf_sideeffectff( + .din(obuf_sideeffect_in), + .dout(obuf_sideeffect), + .en(obuf_wr_en), + .clk(lsu_bus_obuf_c1_clk), + .clken(lsu_bus_obuf_c1_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:542:4 + rvdffs_fpga #(.WIDTH(2)) obuf_szff( + .din(obuf_sz_in[1:0]), + .dout(obuf_sz), + .en(obuf_wr_en), + .clk(lsu_bus_obuf_c1_clk), + .clken(lsu_bus_obuf_c1_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:543:4 + rvdffs_fpga #(.WIDTH(8)) obuf_byteenff( + .din(obuf_byteen_in[7:0]), + .dout(obuf_byteen), + .en(obuf_wr_en), + .clk(lsu_bus_obuf_c1_clk), + .clken(lsu_bus_obuf_c1_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:544:4 + rvdffe #(.WIDTH(32)) obuf_addrff( + .din(obuf_addr_in[31:0]), + .dout(obuf_addr), + .en(obuf_wr_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:545:4 + rvdffe #(.WIDTH(64)) obuf_dataff( + .din(obuf_data_in[63:0]), + .dout(obuf_data), + .en(obuf_wr_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:546:4 + rvdff_fpga #(.WIDTH(TIMER_LOG2)) obuf_timerff( + .din(obuf_wr_timer_in), + .dout(obuf_wr_timer), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:554:4 + function automatic signed [DEPTH_LOG2 - 1:0] sv2v_cast_6BEEB_signed; + input reg signed [DEPTH_LOG2 - 1:0] inp; + sv2v_cast_6BEEB_signed = inp; + endfunction + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:555:7 + WrPtr0_m[DEPTH_LOG2 - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:556:7 + WrPtr1_m[DEPTH_LOG2 - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:557:7 + found_wrptr0 = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:558:7 + found_wrptr1 = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:561:7 + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:561:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:561:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:562:10 + if (~found_wrptr0) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:563:13 + WrPtr0_m[DEPTH_LOG2 - 1:0] = sv2v_cast_6BEEB_signed(i); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:564:13 + found_wrptr0 = (buf_state[i * 3+:3] == 3'b000) & ~((ibuf_valid & (ibuf_tag == i)) | (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i))))); + end + end + end + begin : sv2v_autoblock_3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:570:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:570:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:571:10 + if (~found_wrptr1) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:572:13 + WrPtr1_m[DEPTH_LOG2 - 1:0] = sv2v_cast_6BEEB_signed(i); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:573:13 + found_wrptr1 = (buf_state[i * 3+:3] == 3'b000) & ~(((ibuf_valid & (ibuf_tag == i)) | (lsu_busreq_m & (WrPtr0_m == i))) | (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i))))); + end + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:581:4 + genvar _gv_i_42; + generate + for (_gv_i_42 = 0; _gv_i_42 < DEPTH; _gv_i_42 = _gv_i_42 + 1) begin : genblk7 + localparam i = _gv_i_42; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:583:7 + assign CmdPtr0Dec[i] = (~(|buf_age[i * DEPTH+:DEPTH]) & (buf_state[i * 3+:3] == 3'b010)) & ~buf_cmd_state_bus_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:584:7 + assign CmdPtr1Dec[i] = ((~(|(buf_age[i * DEPTH+:DEPTH] & ~CmdPtr0Dec)) & ~CmdPtr0Dec[i]) & (buf_state[i * 3+:3] == 3'b010)) & ~buf_cmd_state_bus_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:585:7 + assign RspPtrDec[i] = ~(|buf_rsp_pickage[i * DEPTH+:DEPTH]) & (buf_state[i * 3+:3] == 3'b101); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:588:4 + assign found_cmdptr0 = |CmdPtr0Dec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:589:4 + assign found_cmdptr1 = |CmdPtr1Dec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:590:4 + function automatic [7:0] sv2v_cast_8; + input reg [7:0] inp; + sv2v_cast_8 = inp; + endfunction + assign CmdPtr0 = f_Enc8to3(sv2v_cast_8(CmdPtr0Dec[DEPTH - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:591:4 + assign CmdPtr1 = f_Enc8to3(sv2v_cast_8(CmdPtr1Dec[DEPTH - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:592:4 + assign RspPtr = f_Enc8to3(sv2v_cast_8(RspPtrDec[DEPTH - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:595:4 + genvar _gv_i_43; + generate + for (_gv_i_43 = 0; _gv_i_43 < DEPTH; _gv_i_43 = _gv_i_43 + 1) begin : GenAgeVec + localparam i = _gv_i_43; + genvar _gv_j_8; + for (_gv_j_8 = 0; _gv_j_8 < DEPTH; _gv_j_8 = _gv_j_8 + 1) begin : genblk1 + localparam j = _gv_j_8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:597:10 + assign buf_age_in[(i * DEPTH) + j] = (((buf_state[i * 3+:3] == 3'b000) & buf_state_en[i]) & ((((buf_state[j * 3+:3] == 3'b001) | ((buf_state[j * 3+:3] == 3'b010) & ~buf_cmd_state_bus_en[j])) | ((((ibuf_drain_vld & lsu_busreq_r) & (ibuf_byp | ldst_dual_r)) & (i == WrPtr0_r)) & (j == ibuf_tag))) | ((((ibuf_byp & lsu_busreq_r) & ldst_dual_r) & (i == WrPtr1_r)) & (j == WrPtr0_r)))) | buf_age[(i * DEPTH) + j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:604:10 + assign buf_age[(i * DEPTH) + j] = (buf_ageQ[(i * DEPTH) + j] & ~((buf_state[j * 3+:3] == 3'b010) & buf_cmd_state_bus_en[j])) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:606:10 + assign buf_age_younger[(i * DEPTH) + j] = (i == j ? 1'b0 : ~buf_age[(i * DEPTH) + j] & (buf_state[j * 3+:3] != 3'b000)); + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:611:4 + genvar _gv_i_44; + generate + for (_gv_i_44 = 0; _gv_i_44 < DEPTH; _gv_i_44 = _gv_i_44 + 1) begin : GenRspAgeVec + localparam i = _gv_i_44; + genvar _gv_j_9; + for (_gv_j_9 = 0; _gv_j_9 < DEPTH; _gv_j_9 = _gv_j_9 + 1) begin : genblk1 + localparam j = _gv_j_9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:613:10 + assign buf_rspage_set[(i * DEPTH) + j] = ((buf_state[i * 3+:3] == 3'b000) & buf_state_en[i]) & ((~((buf_state[j * 3+:3] == 3'b000) | (buf_state[j * 3+:3] == 3'b110)) | ((((ibuf_drain_vld & lsu_busreq_r) & (ibuf_byp | ldst_dual_r)) & (sv2v_cast_6BEEB_signed(i) == WrPtr0_r)) & (sv2v_cast_6BEEB_signed(j) == ibuf_tag))) | ((((ibuf_byp & lsu_busreq_r) & ldst_dual_r) & (sv2v_cast_6BEEB_signed(i) == WrPtr1_r)) & (sv2v_cast_6BEEB_signed(j) == WrPtr0_r))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:617:10 + assign buf_rspage_in[(i * DEPTH) + j] = buf_rspage_set[(i * DEPTH) + j] | buf_rspage[(i * DEPTH) + j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:618:10 + assign buf_rspage[(i * DEPTH) + j] = (buf_rspageQ[(i * DEPTH) + j] & ~((buf_state[j * 3+:3] == 3'b110) | (buf_state[j * 3+:3] == 3'b000))) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:619:10 + assign buf_rsp_pickage[(i * DEPTH) + j] = buf_rspageQ[(i * DEPTH) + j] & (buf_state[j * 3+:3] == 3'b101); + end + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:626:4 + genvar _gv_i_45; + function automatic [DEPTH_LOG2 - 1:0] sv2v_cast_6BEEB; + input reg [DEPTH_LOG2 - 1:0] inp; + sv2v_cast_6BEEB = inp; + endfunction + function automatic signed [pt[181-:8] - 1:0] sv2v_cast_E7F3A_signed; + input reg signed [pt[181-:8] - 1:0] inp; + sv2v_cast_E7F3A_signed = inp; + endfunction + generate + for (_gv_i_45 = 0; _gv_i_45 < DEPTH; _gv_i_45 = _gv_i_45 + 1) begin : genblk10 + localparam i = _gv_i_45; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:628:7 + assign ibuf_drainvec_vld[i] = ibuf_drain_vld & (i == ibuf_tag); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:629:7 + assign buf_byteen_in[i * 4+:4] = (ibuf_drainvec_vld[i] ? ibuf_byteen_out[3:0] : ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r) ? ldst_byteen_hi_r[3:0] : ldst_byteen_lo_r[3:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:630:7 + assign buf_addr_in[i * 32+:32] = (ibuf_drainvec_vld[i] ? ibuf_addr[31:0] : ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r) ? end_addr_r[31:0] : lsu_addr_r[31:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:631:7 + assign buf_dual_in[i] = (ibuf_drainvec_vld[i] ? ibuf_dual : ldst_dual_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:632:7 + assign buf_samedw_in[i] = (ibuf_drainvec_vld[i] ? ibuf_samedw : ldst_samedw_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:633:7 + assign buf_nomerge_in[i] = (ibuf_drainvec_vld[i] ? ibuf_nomerge | ibuf_force_drain : no_dword_merge_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:634:7 + assign buf_dualhi_in[i] = (ibuf_drainvec_vld[i] ? ibuf_dual : (ibuf_byp & ldst_dual_r) & (i == WrPtr1_r)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:635:7 + assign buf_dualtag_in[i * DEPTH_LOG2+:DEPTH_LOG2] = (ibuf_drainvec_vld[i] ? ibuf_dualtag : ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r) ? WrPtr0_r : WrPtr1_r)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:636:7 + assign buf_sideeffect_in[i] = (ibuf_drainvec_vld[i] ? ibuf_sideeffect : is_sideeffects_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:637:7 + assign buf_unsign_in[i] = (ibuf_drainvec_vld[i] ? ibuf_unsign : lsu_pkt_r[5]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:638:7 + assign buf_sz_in[i * 2+:2] = (ibuf_drainvec_vld[i] ? ibuf_sz : {lsu_pkt_r[9], lsu_pkt_r[10]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:639:7 + assign buf_write_in[i] = (ibuf_drainvec_vld[i] ? ibuf_write : lsu_pkt_r[6]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:642:7 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:643:10 + buf_nxtstate[i * 3+:3] = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:644:10 + buf_state_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:645:10 + buf_resp_state_bus_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:646:10 + buf_state_bus_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:647:10 + buf_wr_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:648:10 + buf_data_in[i * 32+:32] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:649:10 + buf_data_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:650:10 + buf_error_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:651:10 + buf_rst[i] = dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:652:10 + buf_ldfwd_en[i] = dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:653:10 + buf_ldfwd_in[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:654:10 + buf_ldfwdtag_in[i * DEPTH_LOG2+:DEPTH_LOG2] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:656:10 + case (buf_state[i * 3+:3]) + 3'b000: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:658:22 + buf_nxtstate[i * 3+:3] = (lsu_bus_clk_en ? 3'b010 : 3'b001); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:659:22 + buf_state_en[i] = ((lsu_busreq_r & lsu_commit_r) & ((((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en) & (i == WrPtr0_r)) | ((ibuf_byp & ldst_dual_r) & (i == WrPtr1_r)))) | (ibuf_drain_vld & (i == ibuf_tag)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:661:22 + buf_wr_en[i] = buf_state_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:662:22 + buf_data_en[i] = buf_state_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:663:22 + buf_data_in[i * 32+:32] = (ibuf_drain_vld & (i == ibuf_tag) ? ibuf_data_out[31:0] : store_data_lo_r[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:664:22 + buf_cmd_state_bus_en[i] = 1'sb0; + end + 3'b001: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:667:22 + buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? 3'b000 : 3'b010); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:668:22 + buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:669:22 + buf_cmd_state_bus_en[i] = 1'sb0; + end + 3'b010: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:672:22 + buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? 3'b000 : ((obuf_nosend & bus_rsp_read) & (bus_rsp_read_tag == obuf_rdrsp_tag) ? 3'b101 : 3'b011)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:673:22 + buf_cmd_state_bus_en[i] = (((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid) & obuf_wr_enQ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:674:22 + buf_state_bus_en[i] = buf_cmd_state_bus_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:675:22 + buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:676:22 + buf_ldfwd_in[i] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:677:22 + buf_ldfwd_en[i] = ((buf_state_en[i] & ~buf_write[i]) & obuf_nosend) & ~dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:678:22 + buf_ldfwdtag_in[i * DEPTH_LOG2+:DEPTH_LOG2] = sv2v_cast_6BEEB(obuf_rdrsp_tag[pt[181-:8] - 2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:679:22 + buf_data_en[i] = ((buf_state_bus_en[i] & lsu_bus_clk_en) & obuf_nosend) & bus_rsp_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:680:22 + buf_error_en[i] = ((buf_state_bus_en[i] & lsu_bus_clk_en) & obuf_nosend) & bus_rsp_read_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:681:22 + buf_data_in[i * 32+:32] = (buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[(i * 32) + 2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0])); + end + 3'b011: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:684:22 + buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error) ? 3'b000 : (((buf_dual[i] & ~buf_samedw[i]) & ~buf_write[i]) & (buf_state[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] * 3+:3] != 3'b100) ? 3'b100 : ((buf_ldfwd[i] | any_done_wait_state) | (((((buf_dual[i] & ~buf_samedw[i]) & ~buf_write[i]) & buf_ldfwd[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]]) & (buf_state[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] * 3+:3] == 3'b100)) & any_done_wait_state) ? 3'b101 : 3'b110))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:689:22 + buf_resp_state_bus_en[i] = (bus_rsp_write & (bus_rsp_write_tag == sv2v_cast_E7F3A_signed(i))) | (bus_rsp_read & (((bus_rsp_read_tag == sv2v_cast_E7F3A_signed(i)) | (buf_ldfwd[i] & (bus_rsp_read_tag == sv2v_cast_E7F3A(buf_ldfwdtag[i * DEPTH_LOG2+:DEPTH_LOG2])))) | ((((buf_dual[i] & buf_dualhi[i]) & ~buf_write[i]) & buf_samedw[i]) & (bus_rsp_read_tag == sv2v_cast_E7F3A(buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]))))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:693:22 + buf_state_bus_en[i] = buf_resp_state_bus_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:694:22 + buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:695:22 + buf_data_en[i] = (buf_state_bus_en[i] & bus_rsp_read) & lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:697:22 + buf_error_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) & (((bus_rsp_read_error & (bus_rsp_read_tag == sv2v_cast_E7F3A_signed(i))) | ((bus_rsp_read_error & buf_ldfwd[i]) & (bus_rsp_read_tag == sv2v_cast_E7F3A(buf_ldfwdtag[i * DEPTH_LOG2+:DEPTH_LOG2])))) | (bus_rsp_write_error & (bus_rsp_write_tag == sv2v_cast_E7F3A_signed(i)))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:700:22 + buf_data_in[(i * 32) + 31-:32] = (buf_state_en[i] & ~buf_error_en[i] ? (buf_addr[(i * 32) + 2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:701:22 + buf_cmd_state_bus_en[i] = 1'sb0; + end + 3'b100: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:704:22 + buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? 3'b000 : ((buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]]) | any_done_wait_state ? 3'b101 : 3'b110)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:705:22 + buf_state_bus_en[i] = bus_rsp_read & ((bus_rsp_read_tag == sv2v_cast_E7F3A(buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2])) | (buf_ldfwd[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]] & (bus_rsp_read_tag == sv2v_cast_E7F3A(buf_ldfwdtag[buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] * DEPTH_LOG2+:DEPTH_LOG2])))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:707:22 + buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:708:22 + buf_cmd_state_bus_en[i] = 1'sb0; + end + 3'b101: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:711:23 + buf_nxtstate[i * 3+:3] = (dec_tlu_force_halt ? 3'b000 : 3'b110); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:712:23 + buf_state_en[i] = ((RspPtr == sv2v_cast_6BEEB_signed(i)) | (buf_dual[i] & (buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2] == RspPtr))) | dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:713:23 + buf_cmd_state_bus_en[i] = 1'sb0; + end + 3'b110: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:716:22 + buf_nxtstate[i * 3+:3] = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:717:22 + buf_rst[i] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:718:22 + buf_state_en[i] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:719:22 + buf_ldfwd_in[i] = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:720:22 + buf_ldfwd_en[i] = buf_state_en[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:721:22 + buf_cmd_state_bus_en[i] = 1'sb0; + end + default: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:724:22 + buf_nxtstate[i * 3+:3] = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:725:22 + buf_state_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:726:22 + buf_resp_state_bus_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:727:22 + buf_state_bus_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:728:22 + buf_wr_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:729:22 + buf_data_in[i * 32+:32] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:730:22 + buf_data_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:731:22 + buf_error_en[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:732:22 + buf_rst[i] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:733:22 + buf_cmd_state_bus_en[i] = 1'sb0; + end + endcase + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:738:7 + rvdffs #(.WIDTH(3)) buf_state_ff( + .din(buf_nxtstate[i * 3+:3]), + .dout({buf_state[i * 3+:3]}), + .en(buf_state_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:739:7 + rvdff #(.WIDTH(DEPTH)) buf_ageff( + .din(buf_age_in[i * DEPTH+:DEPTH]), + .dout(buf_ageQ[i * DEPTH+:DEPTH]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:740:7 + rvdff #(.WIDTH(DEPTH)) buf_rspageff( + .din(buf_rspage_in[i * DEPTH+:DEPTH]), + .dout(buf_rspageQ[i * DEPTH+:DEPTH]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:741:7 + rvdffs #(.WIDTH(DEPTH_LOG2)) buf_dualtagff( + .din(buf_dualtag_in[i * DEPTH_LOG2+:DEPTH_LOG2]), + .dout(buf_dualtag[i * DEPTH_LOG2+:DEPTH_LOG2]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:742:7 + rvdffs #(.WIDTH(1)) buf_dualff( + .din(buf_dual_in[i]), + .dout(buf_dual[i]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:743:7 + rvdffs #(.WIDTH(1)) buf_samedwff( + .din(buf_samedw_in[i]), + .dout(buf_samedw[i]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:744:7 + rvdffs #(.WIDTH(1)) buf_nomergeff( + .din(buf_nomerge_in[i]), + .dout(buf_nomerge[i]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:745:7 + rvdffs #(.WIDTH(1)) buf_dualhiff( + .din(buf_dualhi_in[i]), + .dout(buf_dualhi[i]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:746:7 + rvdffs #(.WIDTH(1)) buf_ldfwdff( + .din(buf_ldfwd_in[i]), + .dout(buf_ldfwd[i]), + .en(buf_ldfwd_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:747:7 + rvdffs #(.WIDTH(DEPTH_LOG2)) buf_ldfwdtagff( + .din(buf_ldfwdtag_in[i * DEPTH_LOG2+:DEPTH_LOG2]), + .dout(buf_ldfwdtag[i * DEPTH_LOG2+:DEPTH_LOG2]), + .en(buf_ldfwd_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:748:7 + rvdffs #(.WIDTH(1)) buf_sideeffectff( + .din(buf_sideeffect_in[i]), + .dout(buf_sideeffect[i]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:749:7 + rvdffs #(.WIDTH(1)) buf_unsignff( + .din(buf_unsign_in[i]), + .dout(buf_unsign[i]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:750:7 + rvdffs #(.WIDTH(1)) buf_writeff( + .din(buf_write_in[i]), + .dout(buf_write[i]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:751:7 + rvdffs #(.WIDTH(2)) buf_szff( + .din(buf_sz_in[i * 2+:2]), + .dout(buf_sz[i * 2+:2]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:752:7 + rvdffe #(.WIDTH(32)) buf_addrff( + .din(buf_addr_in[(i * 32) + 31-:32]), + .dout(buf_addr[i * 32+:32]), + .en(buf_wr_en[i]), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:753:7 + rvdffs #(.WIDTH(4)) buf_byteenff( + .din(buf_byteen_in[(i * 4) + 3-:4]), + .dout(buf_byteen[i * 4+:4]), + .en(buf_wr_en[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:754:7 + rvdffe #(.WIDTH(32)) buf_dataff( + .din(buf_data_in[(i * 32) + 31-:32]), + .dout(buf_data[i * 32+:32]), + .en(buf_data_en[i]), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:755:7 + rvdffsc #(.WIDTH(1)) buf_errorff( + .din(1'b1), + .dout(buf_error[i]), + .en(buf_error_en[i]), + .clear(buf_rst[i]), + .clk(lsu_bus_buf_c1_clk), + .rst_l(rst_l) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:760:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:761:7 + buf_numvld_any[3:0] = (({1'b0, lsu_busreq_m} << ldst_dual_m) + ({1'b0, lsu_busreq_r} << ldst_dual_r)) + ibuf_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:764:7 + buf_numvld_wrcmd_any[3:0] = 4'b0000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:765:7 + buf_numvld_cmd_any[3:0] = 4'b0000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:766:7 + buf_numvld_pend_any[3:0] = 4'b0000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:767:7 + any_done_wait_state = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:768:7 + begin : sv2v_autoblock_4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:768:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:768:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:769:10 + buf_numvld_any[3:0] = buf_numvld_any[3:0] + {3'b000, buf_state[i * 3+:3] != 3'b000}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:770:10 + buf_numvld_wrcmd_any[3:0] = buf_numvld_wrcmd_any[3:0] + {3'b000, (buf_write[i] & (buf_state[i * 3+:3] == 3'b010)) & ~buf_cmd_state_bus_en[i]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:771:10 + buf_numvld_cmd_any[3:0] = buf_numvld_cmd_any[3:0] + {3'b000, (buf_state[i * 3+:3] == 3'b010) & ~buf_cmd_state_bus_en[i]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:772:10 + buf_numvld_pend_any[3:0] = buf_numvld_pend_any[3:0] + {3'b000, (buf_state[i * 3+:3] == 3'b001) | ((buf_state[i * 3+:3] == 3'b010) & ~buf_cmd_state_bus_en[i])}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:773:10 + any_done_wait_state = any_done_wait_state | (buf_state[i * 3+:3] == 3'b101); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:777:4 + assign lsu_bus_buffer_pend_any = buf_numvld_pend_any != 0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:778:4 + assign lsu_bus_buffer_full_any = (ldst_dual_d & dec_lsu_valid_raw_d ? buf_numvld_any[3:0] >= (DEPTH - 1) : buf_numvld_any[3:0] == DEPTH); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:779:4 + assign lsu_bus_buffer_empty_any = (~(|buf_state[3 * ((DEPTH - 1) - (DEPTH - 1))+:3 * DEPTH]) & ~ibuf_valid) & ~obuf_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:783:4 + assign lsu_nonblock_load_valid_m = (((lsu_busreq_m & lsu_pkt_m[0]) & lsu_pkt_m[7]) & ~flush_m_up) & ~ld_full_hit_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:784:4 + assign lsu_nonblock_load_tag_m[DEPTH_LOG2 - 1:0] = WrPtr0_m[DEPTH_LOG2 - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:785:4 + assign lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & ~lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:786:4 + assign lsu_nonblock_load_inv_tag_r[DEPTH_LOG2 - 1:0] = WrPtr0_r[DEPTH_LOG2 - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:788:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:789:7 + lsu_nonblock_load_data_ready = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:790:7 + lsu_nonblock_load_data_error = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:791:7 + lsu_nonblock_load_data_tag[DEPTH_LOG2 - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:792:7 + lsu_nonblock_load_data_lo[31:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:793:7 + lsu_nonblock_load_data_hi[31:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:794:7 + begin : sv2v_autoblock_5 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:794:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:794:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:796:11 + lsu_nonblock_load_data_ready = lsu_nonblock_load_data_ready | ((buf_state[i * 3+:3] == 3'b110) & ~buf_write[i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:797:11 + lsu_nonblock_load_data_error = lsu_nonblock_load_data_error | (((buf_state[i * 3+:3] == 3'b110) & buf_error[i]) & ~buf_write[i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:798:11 + lsu_nonblock_load_data_tag[DEPTH_LOG2 - 1:0] = lsu_nonblock_load_data_tag[DEPTH_LOG2 - 1:0] | (sv2v_cast_6BEEB_signed(i) & {DEPTH_LOG2 {((buf_state[i * 3+:3] == 3'b110) & ~buf_write[i]) & (~buf_dual[i] | ~buf_dualhi[i])}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:799:11 + lsu_nonblock_load_data_lo[31:0] = lsu_nonblock_load_data_lo[31:0] | (buf_data[(i * 32) + 31-:32] & {32 {((buf_state[i * 3+:3] == 3'b110) & ~buf_write[i]) & (~buf_dual[i] | ~buf_dualhi[i])}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:800:11 + lsu_nonblock_load_data_hi[31:0] = lsu_nonblock_load_data_hi[31:0] | (buf_data[(i * 32) + 31-:32] & {32 {((buf_state[i * 3+:3] == 3'b110) & ~buf_write[i]) & (buf_dual[i] & buf_dualhi[i])}}); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:804:4 + assign lsu_nonblock_addr_offset[1:0] = buf_addr[(lsu_nonblock_load_data_tag * 32) + 1-:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:805:4 + assign lsu_nonblock_sz[1:0] = buf_sz[(lsu_nonblock_load_data_tag * 2) + 1-:2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:806:4 + assign lsu_nonblock_unsign = buf_unsign[lsu_nonblock_load_data_tag]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:807:4 + function automatic [31:0] sv2v_cast_32; + input reg [31:0] inp; + sv2v_cast_32 = inp; + endfunction + assign lsu_nonblock_data_unalgn[31:0] = sv2v_cast_32({lsu_nonblock_load_data_hi[31:0], lsu_nonblock_load_data_lo[31:0]} >> (8 * lsu_nonblock_addr_offset[1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:809:4 + assign lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & ~lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:810:4 + assign lsu_nonblock_load_data[31:0] = (((({32 {lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {24'b000000000000000000000000, lsu_nonblock_data_unalgn[7:0]}) | ({32 {lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {16'b0000000000000000, lsu_nonblock_data_unalgn[15:0]})) | ({32 {~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {{24 {lsu_nonblock_data_unalgn[7]}}, lsu_nonblock_data_unalgn[7:0]})) | ({32 {~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {{16 {lsu_nonblock_data_unalgn[15]}}, lsu_nonblock_data_unalgn[15:0]})) | ({32 {lsu_nonblock_sz[1:0] == 2'b10}} & lsu_nonblock_data_unalgn[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:817:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:818:7 + bus_sideeffect_pend = (obuf_valid & obuf_sideeffect) & dec_tlu_sideeffect_posted_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:819:7 + begin : sv2v_autoblock_6 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:819:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:819:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:820:10 + bus_sideeffect_pend = bus_sideeffect_pend | (((buf_state[i * 3+:3] == 3'b011) & buf_sideeffect[i]) & dec_tlu_sideeffect_posted_disable); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:825:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:826:7 + bus_addr_match_pending = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:827:7 + begin : sv2v_autoblock_7 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:827:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:827:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:828:10 + bus_addr_match_pending = bus_addr_match_pending | (((obuf_valid & (obuf_addr[31:3] == buf_addr[(i * 32) + 31-:29])) & (buf_state[i * 3+:3] == 3'b011)) & ~((obuf_tag0 == sv2v_cast_E7F3A_signed(i)) | (obuf_merge & (obuf_tag1 == sv2v_cast_E7F3A_signed(i))))); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:833:4 + assign bus_cmd_ready = (obuf_write ? (obuf_cmd_done | obuf_data_done ? (obuf_cmd_done ? lsu_axi_wready : lsu_axi_awready) : lsu_axi_awready & lsu_axi_wready) : lsu_axi_arready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:834:4 + assign bus_wcmd_sent = lsu_axi_awvalid & lsu_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:835:4 + assign bus_wdata_sent = lsu_axi_wvalid & lsu_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:836:4 + assign bus_cmd_sent = ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (lsu_axi_arvalid & lsu_axi_arready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:838:4 + assign bus_rsp_read = lsu_axi_rvalid & lsu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:839:4 + assign bus_rsp_write = lsu_axi_bvalid & lsu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:840:4 + assign bus_rsp_read_tag[pt[181-:8] - 1:0] = lsu_axi_rid[pt[181-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:841:4 + assign bus_rsp_write_tag[pt[181-:8] - 1:0] = lsu_axi_bid[pt[181-:8] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:842:4 + assign bus_rsp_write_error = bus_rsp_write & (lsu_axi_bresp[1:0] != 2'b00); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:843:4 + assign bus_rsp_read_error = bus_rsp_read & (lsu_axi_rresp[1:0] != 2'b00); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:844:4 + assign bus_rsp_rdata[63:0] = lsu_axi_rdata[63:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:847:4 + assign lsu_axi_awvalid = ((obuf_valid & obuf_write) & ~obuf_cmd_done) & ~bus_addr_match_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:848:4 + assign lsu_axi_awid[pt[181-:8] - 1:0] = sv2v_cast_E7F3A(obuf_tag0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:849:4 + assign lsu_axi_awaddr[31:0] = (obuf_sideeffect ? obuf_addr[31:0] : {obuf_addr[31:3], 3'b000}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:850:4 + assign lsu_axi_awsize[2:0] = (obuf_sideeffect ? {1'b0, obuf_sz[1:0]} : 3'b011); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:851:4 + assign lsu_axi_awprot[2:0] = 3'b001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:852:4 + assign lsu_axi_awcache[3:0] = (obuf_sideeffect ? 4'b0000 : 4'b1111); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:853:4 + assign lsu_axi_awregion[3:0] = obuf_addr[31:28]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:854:4 + assign lsu_axi_awlen[7:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:855:4 + assign lsu_axi_awburst[1:0] = 2'b01; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:856:4 + assign lsu_axi_awqos[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:857:4 + assign lsu_axi_awlock = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:859:4 + assign lsu_axi_wvalid = ((obuf_valid & obuf_write) & ~obuf_data_done) & ~bus_addr_match_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:860:4 + assign lsu_axi_wstrb[7:0] = obuf_byteen[7:0] & {8 {obuf_write}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:861:4 + assign lsu_axi_wdata[63:0] = obuf_data[63:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:862:4 + assign lsu_axi_wlast = 1'sb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:864:4 + assign lsu_axi_arvalid = ((obuf_valid & ~obuf_write) & ~obuf_nosend) & ~bus_addr_match_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:865:4 + assign lsu_axi_arid[pt[181-:8] - 1:0] = sv2v_cast_E7F3A(obuf_tag0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:866:4 + assign lsu_axi_araddr[31:0] = (obuf_sideeffect ? obuf_addr[31:0] : {obuf_addr[31:3], 3'b000}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:867:4 + assign lsu_axi_arsize[2:0] = (obuf_sideeffect ? {1'b0, obuf_sz[1:0]} : 3'b011); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:868:4 + assign lsu_axi_arprot[2:0] = 3'b001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:869:4 + assign lsu_axi_arcache[3:0] = (obuf_sideeffect ? 4'b0000 : 4'b1111); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:870:4 + assign lsu_axi_arregion[3:0] = obuf_addr[31:28]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:871:4 + assign lsu_axi_arlen[7:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:872:4 + assign lsu_axi_arburst[1:0] = 2'b01; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:873:4 + assign lsu_axi_arqos[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:874:4 + assign lsu_axi_arlock = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:876:4 + assign lsu_axi_bready = 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:877:4 + assign lsu_axi_rready = 1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:879:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:880:7 + lsu_imprecise_error_store_any = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:881:7 + lsu_imprecise_error_store_tag = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:882:7 + begin : sv2v_autoblock_8 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:882:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:882:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:883:10 + lsu_imprecise_error_store_any = lsu_imprecise_error_store_any | (((lsu_bus_clk_en_q & (buf_state[i * 3+:3] == 3'b110)) & buf_error[i]) & buf_write[i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:884:10 + lsu_imprecise_error_store_tag = lsu_imprecise_error_store_tag | (sv2v_cast_6BEEB_signed(i) & {DEPTH_LOG2 {((buf_state[i * 3+:3] == 3'b110) & buf_error[i]) & buf_write[i]}}); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:887:4 + assign lsu_imprecise_error_load_any = lsu_nonblock_load_data_error & ~lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:888:4 + assign lsu_imprecise_error_addr_any[31:0] = (lsu_imprecise_error_store_any ? buf_addr[lsu_imprecise_error_store_tag * 32+:32] : buf_addr[lsu_nonblock_load_data_tag * 32+:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:891:4 + assign lsu_pmu_bus_trxn = ((lsu_axi_awvalid & lsu_axi_awready) | (lsu_axi_wvalid & lsu_axi_wready)) | (lsu_axi_arvalid & lsu_axi_arready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:892:4 + assign lsu_pmu_bus_misaligned = (lsu_busreq_r & ldst_dual_r) & lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:893:4 + assign lsu_pmu_bus_error = lsu_imprecise_error_load_any | lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:894:4 + assign lsu_pmu_bus_busy = ((lsu_axi_awvalid & ~lsu_axi_awready) | (lsu_axi_wvalid & ~lsu_axi_wready)) | (lsu_axi_arvalid & ~lsu_axi_arready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:896:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_awvalid_ff( + .din(lsu_axi_awvalid), + .dout(lsu_axi_awvalid_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:897:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_awready_ff( + .din(lsu_axi_awready), + .dout(lsu_axi_awready_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:898:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_wvalid_ff( + .din(lsu_axi_wvalid), + .dout(lsu_axi_wvalid_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:899:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_wready_ff( + .din(lsu_axi_wready), + .dout(lsu_axi_wready_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:900:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_arvalid_ff( + .din(lsu_axi_arvalid), + .dout(lsu_axi_arvalid_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:901:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_arready_ff( + .din(lsu_axi_arready), + .dout(lsu_axi_arready_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:903:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_bvalid_ff( + .din(lsu_axi_bvalid), + .dout(lsu_axi_bvalid_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:904:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_bready_ff( + .din(lsu_axi_bready), + .dout(lsu_axi_bready_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:905:4 + rvdff_fpga #(.WIDTH(2)) lsu_axi_bresp_ff( + .din(lsu_axi_bresp[1:0]), + .dout(lsu_axi_bresp_q[1:0]), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:906:4 + rvdff_fpga #(.WIDTH(pt[181-:8])) lsu_axi_bid_ff( + .din(lsu_axi_bid[pt[181-:8] - 1:0]), + .dout(lsu_axi_bid_q[pt[181-:8] - 1:0]), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:907:4 + rvdffe #(.WIDTH(64)) lsu_axi_rdata_ff( + .din(lsu_axi_rdata[63:0]), + .dout(lsu_axi_rdata_q[63:0]), + .en((lsu_axi_rvalid | clk_override) & lsu_bus_clk_en), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:909:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_rvalid_ff( + .din(lsu_axi_rvalid), + .dout(lsu_axi_rvalid_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:910:4 + rvdff_fpga #(.WIDTH(1)) lsu_axi_rready_ff( + .din(lsu_axi_rready), + .dout(lsu_axi_rready_q), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:911:4 + rvdff_fpga #(.WIDTH(2)) lsu_axi_rresp_ff( + .din(lsu_axi_rresp[1:0]), + .dout(lsu_axi_rresp_q[1:0]), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:912:4 + rvdff_fpga #(.WIDTH(pt[181-:8])) lsu_axi_rid_ff( + .din(lsu_axi_rid[pt[181-:8] - 1:0]), + .dout(lsu_axi_rid_q[pt[181-:8] - 1:0]), + .clk(lsu_busm_clk), + .clken(lsu_busm_clken), + .rawclk(clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:914:4 + rvdff #(.WIDTH(DEPTH_LOG2)) lsu_WrPtr0_rff( + .din(WrPtr0_m), + .dout(WrPtr0_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:915:4 + rvdff #(.WIDTH(DEPTH_LOG2)) lsu_WrPtr1_rff( + .din(WrPtr1_m), + .dout(WrPtr1_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:917:4 + rvdff #(.WIDTH(1)) lsu_busreq_rff( + .din((lsu_busreq_m & ~flush_r) & ~ld_full_hit_m), + .dout(lsu_busreq_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_buffer.sv:918:4 + rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_rff( + .din(lsu_nonblock_load_valid_m), + .dout(lsu_nonblock_load_valid_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + initial _sv2v_0 = 0; +endmodule +module el2_lsu_clkdomain ( + clk, + active_clk, + rst_l, + dec_tlu_force_halt, + clk_override, + dma_dccm_req, + ldst_stbuf_reqvld_r, + stbuf_reqvld_any, + stbuf_reqvld_flushed_any, + lsu_busreq_r, + lsu_bus_buffer_pend_any, + lsu_bus_buffer_empty_any, + lsu_stbuf_empty_any, + lsu_bus_clk_en, + lsu_p, + lsu_pkt_d, + lsu_pkt_m, + lsu_pkt_r, + lsu_bus_obuf_c1_clken, + lsu_busm_clken, + lsu_c1_m_clk, + lsu_c1_r_clk, + lsu_c2_m_clk, + lsu_c2_r_clk, + lsu_store_c1_m_clk, + lsu_store_c1_r_clk, + lsu_stbuf_c1_clk, + lsu_bus_obuf_c1_clk, + lsu_bus_ibuf_c1_clk, + lsu_bus_buf_c1_clk, + lsu_busm_clk, + lsu_free_c2_clk, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:31:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:32:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:33:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:34:4 + input wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:37:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:38:4 + input wire dma_dccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:39:4 + input wire ldst_stbuf_reqvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:41:4 + input wire stbuf_reqvld_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:42:4 + input wire stbuf_reqvld_flushed_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:43:4 + input wire lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:44:4 + input wire lsu_bus_buffer_pend_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:45:4 + input wire lsu_bus_buffer_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:46:4 + input wire lsu_stbuf_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:48:4 + input wire lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:50:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:51:4 + input wire [13:0] lsu_pkt_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:52:4 + input wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:53:4 + input wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:56:4 + output wire lsu_bus_obuf_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:57:4 + output wire lsu_busm_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:59:4 + output wire lsu_c1_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:60:4 + output wire lsu_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:62:4 + output wire lsu_c2_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:63:4 + output wire lsu_c2_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:65:4 + output wire lsu_store_c1_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:66:4 + output wire lsu_store_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:68:4 + output wire lsu_stbuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:69:4 + output wire lsu_bus_obuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:70:4 + output wire lsu_bus_ibuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:71:4 + output wire lsu_bus_buf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:72:4 + output wire lsu_busm_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:74:4 + output wire lsu_free_c2_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:76:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:79:4 + wire lsu_c1_m_clken; + wire lsu_c1_r_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:80:4 + wire lsu_c2_m_clken; + wire lsu_c2_r_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:81:4 + wire lsu_c1_m_clken_q; + wire lsu_c1_r_clken_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:82:4 + wire lsu_store_c1_m_clken; + wire lsu_store_c1_r_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:85:4 + wire lsu_stbuf_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:86:4 + wire lsu_bus_ibuf_c1_clken; + wire lsu_bus_buf_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:88:4 + wire lsu_free_c1_clken; + wire lsu_free_c1_clken_q; + wire lsu_free_c2_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:94:4 + assign lsu_c1_m_clken = (lsu_p[0] | dma_dccm_req) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:95:4 + assign lsu_c1_r_clken = (lsu_pkt_m[0] | lsu_c1_m_clken_q) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:97:4 + assign lsu_c2_m_clken = (lsu_c1_m_clken | lsu_c1_m_clken_q) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:98:4 + assign lsu_c2_r_clken = (lsu_c1_r_clken | lsu_c1_r_clken_q) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:100:4 + assign lsu_store_c1_m_clken = (lsu_c1_m_clken & lsu_pkt_d[6]) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:101:4 + assign lsu_store_c1_r_clken = (lsu_c1_r_clken & lsu_pkt_m[6]) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:103:4 + assign lsu_stbuf_c1_clken = ((ldst_stbuf_reqvld_r | stbuf_reqvld_any) | stbuf_reqvld_flushed_any) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:104:4 + assign lsu_bus_ibuf_c1_clken = lsu_busreq_r | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:105:4 + assign lsu_bus_obuf_c1_clken = ((lsu_bus_buffer_pend_any | lsu_busreq_r) | clk_override) & lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:106:4 + assign lsu_bus_buf_c1_clken = ((~lsu_bus_buffer_empty_any | lsu_busreq_r) | dec_tlu_force_halt) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:108:4 + assign lsu_free_c1_clken = (((((lsu_p[0] | lsu_pkt_d[0]) | lsu_pkt_m[0]) | lsu_pkt_r[0]) | ~lsu_bus_buffer_empty_any) | ~lsu_stbuf_empty_any) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:110:4 + assign lsu_free_c2_clken = (lsu_free_c1_clken | lsu_free_c1_clken_q) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:113:4 + rvdff #(.WIDTH(1)) lsu_free_c1_clkenff( + .din(lsu_free_c1_clken), + .dout(lsu_free_c1_clken_q), + .clk(active_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:115:4 + rvdff #(.WIDTH(1)) lsu_c1_m_clkenff( + .din(lsu_c1_m_clken), + .dout(lsu_c1_m_clken_q), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:116:4 + rvdff #(.WIDTH(1)) lsu_c1_r_clkenff( + .din(lsu_c1_r_clken), + .dout(lsu_c1_r_clken_q), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:119:4 + rvoclkhdr lsu_c1m_cgc( + .en(lsu_c1_m_clken), + .l1clk(lsu_c1_m_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:120:4 + rvoclkhdr lsu_c1r_cgc( + .en(lsu_c1_r_clken), + .l1clk(lsu_c1_r_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:122:4 + rvoclkhdr lsu_c2m_cgc( + .en(lsu_c2_m_clken), + .l1clk(lsu_c2_m_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:123:4 + rvoclkhdr lsu_c2r_cgc( + .en(lsu_c2_r_clken), + .l1clk(lsu_c2_r_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:125:4 + rvoclkhdr lsu_store_c1m_cgc( + .en(lsu_store_c1_m_clken), + .l1clk(lsu_store_c1_m_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:126:4 + rvoclkhdr lsu_store_c1r_cgc( + .en(lsu_store_c1_r_clken), + .l1clk(lsu_store_c1_r_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:128:4 + rvoclkhdr lsu_stbuf_c1_cgc( + .en(lsu_stbuf_c1_clken), + .l1clk(lsu_stbuf_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:129:4 + rvoclkhdr lsu_bus_ibuf_c1_cgc( + .en(lsu_bus_ibuf_c1_clken), + .l1clk(lsu_bus_ibuf_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:130:4 + rvoclkhdr lsu_bus_buf_c1_cgc( + .en(lsu_bus_buf_c1_clken), + .l1clk(lsu_bus_buf_c1_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:132:4 + assign lsu_busm_clken = ((~lsu_bus_buffer_empty_any | lsu_busreq_r) | clk_override) & lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:135:4 + assign lsu_busm_clk = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:136:4 + assign lsu_bus_obuf_c1_clk = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_clkdomain.sv:142:4 + rvoclkhdr lsu_free_cgc( + .en(lsu_free_c2_clken), + .l1clk(lsu_free_c2_clk), + .clk(clk), + .scan_mode(scan_mode) + ); +endmodule +module el2_lsu_addrcheck ( + lsu_c2_m_clk, + rst_l, + start_addr_d, + end_addr_d, + lsu_pkt_d, + dec_tlu_mrac_ff, + rs1_region_d, + rs1_d, + is_sideeffects_m, + addr_in_dccm_d, + addr_in_pic_d, + addr_external_d, + access_fault_d, + misaligned_fault_d, + exc_mscause_d, + fir_dccm_access_error_d, + fir_nondccm_access_error_d, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:30:4 + input wire lsu_c2_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:31:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:33:4 + input wire [31:0] start_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:34:4 + input wire [31:0] end_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:35:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_pkt_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:36:4 + input wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:37:4 + input wire [3:0] rs1_region_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:39:4 + input wire [31:0] rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:41:4 + output wire is_sideeffects_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:42:4 + output wire addr_in_dccm_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:43:4 + output wire addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:44:4 + output wire addr_external_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:46:4 + output wire access_fault_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:47:4 + output wire misaligned_fault_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:48:4 + output wire [3:0] exc_mscause_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:50:4 + output wire fir_dccm_access_error_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:51:4 + output wire fir_nondccm_access_error_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:53:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:57:4 + wire non_dccm_access_ok; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:58:4 + wire is_sideeffects_d; + wire is_aligned_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:59:4 + wire start_addr_in_dccm_d; + wire end_addr_in_dccm_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:60:4 + wire start_addr_in_dccm_region_d; + wire end_addr_in_dccm_region_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:61:4 + wire start_addr_in_pic_d; + wire end_addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:62:4 + wire start_addr_in_pic_region_d; + wire end_addr_in_pic_region_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:63:4 + wire [4:0] csr_idx; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:64:4 + wire addr_in_iccm; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:65:4 + wire start_addr_dccm_or_pic; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:66:4 + wire base_reg_dccm_or_pic; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:67:4 + wire unmapped_access_fault_d; + wire mpu_access_fault_d; + wire picm_access_fault_d; + wire regpred_access_fault_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:68:4 + wire regcross_misaligned_fault_d; + wire sideeffect_misaligned_fault_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:69:4 + wire [3:0] access_fault_mscause_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:70:4 + wire [3:0] misaligned_fault_mscause_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:72:4 + generate + if (pt[1365-:5] == 1) begin : Gen_dccm_enable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:74:7 + rvrangecheck #( + .CCM_SADR(pt[1325-:36]), + .CCM_SIZE(pt[1289-:14]) + ) start_addr_dccm_rangecheck( + .addr(start_addr_d[31:0]), + .in_range(start_addr_in_dccm_d), + .in_region(start_addr_in_dccm_region_d) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:82:7 + rvrangecheck #( + .CCM_SADR(pt[1325-:36]), + .CCM_SIZE(pt[1289-:14]) + ) end_addr_dccm_rangecheck( + .addr(end_addr_d[31:0]), + .in_range(end_addr_in_dccm_d), + .in_region(end_addr_in_dccm_region_d) + ); + end + else begin : Gen_dccm_disable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:89:7 + assign start_addr_in_dccm_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:90:7 + assign start_addr_in_dccm_region_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:91:7 + assign end_addr_in_dccm_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:92:7 + assign end_addr_in_dccm_region_d = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:95:4 + generate + if (pt[927-:5] == 1) begin : check_iccm + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:96:7 + assign addr_in_iccm = start_addr_d[31:28] == pt[895-:8]; + end + else begin : genblk2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:98:6 + assign addr_in_iccm = 1'b0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:103:4 + rvrangecheck #( + .CCM_SADR(pt[130-:36]), + .CCM_SIZE(pt[69-:13]) + ) start_addr_pic_rangecheck( + .addr(start_addr_d[31:0]), + .in_range(start_addr_in_pic_d), + .in_region(start_addr_in_pic_region_d) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:111:4 + rvrangecheck #( + .CCM_SADR(pt[130-:36]), + .CCM_SIZE(pt[69-:13]) + ) end_addr_pic_rangecheck( + .addr(end_addr_d[31:0]), + .in_range(end_addr_in_pic_d), + .in_region(end_addr_in_pic_region_d) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:118:4 + assign start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:119:4 + assign base_reg_dccm_or_pic = ((rs1_region_d[3:0] == pt[1333-:8]) & pt[1365-:5]) | (rs1_region_d[3:0] == pt[77-:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:120:4 + assign addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:121:4 + assign addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:123:4 + assign addr_external_d = ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:124:4 + assign csr_idx[4:0] = {start_addr_d[31:28], 1'b1}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:125:4 + assign is_sideeffects_d = ((dec_tlu_mrac_ff[csr_idx] & ~((start_addr_in_dccm_region_d | start_addr_in_pic_region_d) | addr_in_iccm)) & lsu_pkt_d[0]) & (lsu_pkt_d[6] | lsu_pkt_d[7]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:126:4 + assign is_aligned_d = ((lsu_pkt_d[9] & (start_addr_d[1:0] == 2'b00)) | (lsu_pkt_d[10] & (start_addr_d[0] == 1'b0))) | lsu_pkt_d[11]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:130:4 + assign non_dccm_access_ok = ~(|{pt[1733-:5], pt[1728-:5], pt[1723-:5], pt[1718-:5], pt[1713-:5], pt[1708-:5], pt[1703-:5], pt[1698-:5]}) | (((((((((pt[1733-:5] & ((start_addr_d[31:0] | pt[1693-:36]) == (pt[2021-:36] | pt[1693-:36]))) | (pt[1728-:5] & ((start_addr_d[31:0] | pt[1657-:36]) == (pt[1985-:36] | pt[1657-:36])))) | (pt[1723-:5] & ((start_addr_d[31:0] | pt[1621-:36]) == (pt[1949-:36] | pt[1621-:36])))) | (pt[1718-:5] & ((start_addr_d[31:0] | pt[1585-:36]) == (pt[1913-:36] | pt[1585-:36])))) | (pt[1713-:5] & ((start_addr_d[31:0] | pt[1549-:36]) == (pt[1877-:36] | pt[1549-:36])))) | (pt[1708-:5] & ((start_addr_d[31:0] | pt[1513-:36]) == (pt[1841-:36] | pt[1513-:36])))) | (pt[1703-:5] & ((start_addr_d[31:0] | pt[1477-:36]) == (pt[1805-:36] | pt[1477-:36])))) | (pt[1698-:5] & ((start_addr_d[31:0] | pt[1441-:36]) == (pt[1769-:36] | pt[1441-:36])))) & ((((((((pt[1733-:5] & ((end_addr_d[31:0] | pt[1693-:36]) == (pt[2021-:36] | pt[1693-:36]))) | (pt[1728-:5] & ((end_addr_d[31:0] | pt[1657-:36]) == (pt[1985-:36] | pt[1657-:36])))) | (pt[1723-:5] & ((end_addr_d[31:0] | pt[1621-:36]) == (pt[1949-:36] | pt[1621-:36])))) | (pt[1718-:5] & ((end_addr_d[31:0] | pt[1585-:36]) == (pt[1913-:36] | pt[1585-:36])))) | (pt[1713-:5] & ((end_addr_d[31:0] | pt[1549-:36]) == (pt[1877-:36] | pt[1549-:36])))) | (pt[1708-:5] & ((end_addr_d[31:0] | pt[1513-:36]) == (pt[1841-:36] | pt[1513-:36])))) | (pt[1703-:5] & ((end_addr_d[31:0] | pt[1477-:36]) == (pt[1805-:36] | pt[1477-:36])))) | (pt[1698-:5] & ((end_addr_d[31:0] | pt[1441-:36]) == (pt[1769-:36] | pt[1441-:36]))))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:154:4 + assign regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:155:4 + assign picm_access_fault_d = addr_in_pic_d & ((start_addr_d[1:0] != 2'b00) | ~lsu_pkt_d[9]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:157:4 + generate + if (pt[1365-:5] & (pt[1333-:8] == pt[77-:8])) begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:158:7 + assign unmapped_access_fault_d = (((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) | (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d))) | (start_addr_in_dccm_d & end_addr_in_pic_d)) | (start_addr_in_pic_d & end_addr_in_dccm_d); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:162:7 + assign mpu_access_fault_d = ~start_addr_in_dccm_region_d & ~non_dccm_access_ok; + end + else begin : genblk3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:164:7 + assign unmapped_access_fault_d = (((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) | (start_addr_in_pic_region_d & ~start_addr_in_pic_d)) | (end_addr_in_pic_region_d & ~end_addr_in_pic_d); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:168:7 + assign mpu_access_fault_d = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d) & ~non_dccm_access_ok; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:171:4 + assign access_fault_d = ((((unmapped_access_fault_d | mpu_access_fault_d) | picm_access_fault_d) | regpred_access_fault_d) & lsu_pkt_d[0]) & ~lsu_pkt_d[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:172:4 + assign access_fault_mscause_d[3:0] = (unmapped_access_fault_d ? 4'h2 : (mpu_access_fault_d ? 4'h3 : (regpred_access_fault_d ? 4'h5 : (picm_access_fault_d ? 4'h6 : 4'h0)))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:177:4 + assign regcross_misaligned_fault_d = start_addr_d[31:28] != end_addr_d[31:28]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:178:4 + assign sideeffect_misaligned_fault_d = is_sideeffects_d & ~is_aligned_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:179:4 + assign misaligned_fault_d = ((regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & addr_external_d)) & lsu_pkt_d[0]) & ~lsu_pkt_d[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:180:4 + assign misaligned_fault_mscause_d[3:0] = (regcross_misaligned_fault_d ? 4'h2 : (sideeffect_misaligned_fault_d ? 4'h1 : 4'h0)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:182:4 + assign exc_mscause_d[3:0] = (misaligned_fault_d ? misaligned_fault_mscause_d[3:0] : access_fault_mscause_d[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:185:4 + assign fir_dccm_access_error_d = (((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)) & lsu_pkt_d[0]) & lsu_pkt_d[13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:187:4 + assign fir_nondccm_access_error_d = (~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & lsu_pkt_d[0]) & lsu_pkt_d[13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_addrcheck.sv:189:4 + rvdff #(.WIDTH(1)) is_sideeffects_mff( + .din(is_sideeffects_d), + .dout(is_sideeffects_m), + .clk(lsu_c2_m_clk), + .rst_l(rst_l) + ); +endmodule +module el2_lsu_lsc_ctl ( + rst_l, + clk_override, + clk, + lsu_c1_m_clk, + lsu_c1_r_clk, + lsu_c2_m_clk, + lsu_c2_r_clk, + lsu_store_c1_m_clk, + lsu_ld_data_r, + lsu_ld_data_corr_r, + lsu_single_ecc_error_r, + lsu_double_ecc_error_r, + lsu_ld_data_m, + lsu_single_ecc_error_m, + lsu_double_ecc_error_m, + flush_m_up, + flush_r, + ldst_dual_d, + ldst_dual_m, + ldst_dual_r, + exu_lsu_rs1_d, + exu_lsu_rs2_d, + lsu_p, + dec_lsu_valid_raw_d, + dec_lsu_offset_d, + picm_mask_data_m, + bus_read_data_m, + lsu_result_m, + lsu_result_corr_r, + lsu_addr_d, + lsu_addr_m, + lsu_addr_r, + end_addr_d, + end_addr_m, + end_addr_r, + store_data_m, + dec_tlu_mrac_ff, + lsu_exc_m, + is_sideeffects_m, + lsu_commit_r, + lsu_single_ecc_error_incr, + lsu_error_pkt_r, + lsu_fir_addr, + lsu_fir_error, + addr_in_dccm_d, + addr_in_dccm_m, + addr_in_dccm_r, + addr_in_pic_d, + addr_in_pic_m, + addr_in_pic_r, + addr_external_m, + dma_dccm_req, + dma_mem_addr, + dma_mem_sz, + dma_mem_write, + dma_mem_wdata, + lsu_pkt_d, + lsu_pkt_m, + lsu_pkt_r, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:33:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:34:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:35:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:38:4 + input wire lsu_c1_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:39:4 + input wire lsu_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:40:4 + input wire lsu_c2_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:41:4 + input wire lsu_c2_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:42:4 + input wire lsu_store_c1_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:44:4 + input wire [31:0] lsu_ld_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:45:4 + input wire [31:0] lsu_ld_data_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:46:4 + input wire lsu_single_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:47:4 + input wire lsu_double_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:49:4 + input wire [31:0] lsu_ld_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:50:4 + input wire lsu_single_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:51:4 + input wire lsu_double_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:53:4 + input wire flush_m_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:54:4 + input wire flush_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:55:4 + input wire ldst_dual_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:56:4 + input wire ldst_dual_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:57:4 + input wire ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:59:4 + input wire [31:0] exu_lsu_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:60:4 + input wire [31:0] exu_lsu_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:62:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:63:4 + input wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:64:4 + input wire [11:0] dec_lsu_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:66:4 + input wire [31:0] picm_mask_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:67:4 + input wire [31:0] bus_read_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:68:4 + output wire [31:0] lsu_result_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:69:4 + output wire [31:0] lsu_result_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:71:4 + output wire [31:0] lsu_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:72:4 + output wire [31:0] lsu_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:73:4 + output wire [31:0] lsu_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:75:4 + output wire [31:0] end_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:76:4 + output wire [31:0] end_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:77:4 + output wire [31:0] end_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:79:4 + output wire [31:0] store_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:81:4 + input wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:82:4 + output wire lsu_exc_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:83:4 + output wire is_sideeffects_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:84:4 + output wire lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:85:4 + output wire lsu_single_ecc_error_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:86:4 + // removed localparam type el2_pkg_el2_lsu_error_pkt_t + output wire [39:0] lsu_error_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:88:4 + output wire [31:1] lsu_fir_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:89:4 + output wire [1:0] lsu_fir_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:92:4 + output wire addr_in_dccm_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:93:4 + output wire addr_in_dccm_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:94:4 + output wire addr_in_dccm_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:96:4 + output wire addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:97:4 + output wire addr_in_pic_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:98:4 + output wire addr_in_pic_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:100:4 + output wire addr_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:103:4 + input wire dma_dccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:104:4 + input wire [31:0] dma_mem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:105:4 + input wire [2:0] dma_mem_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:106:4 + input wire dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:107:4 + input wire [63:0] dma_mem_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:110:4 + output reg [13:0] lsu_pkt_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:111:4 + output wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:112:4 + output wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:114:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:118:4 + wire [31:3] end_addr_pre_m; + wire [31:3] end_addr_pre_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:119:4 + wire [31:0] full_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:120:4 + wire [31:0] full_end_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:121:4 + wire [31:0] lsu_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:122:4 + wire [11:0] lsu_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:123:4 + wire [31:0] rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:124:4 + wire [11:0] offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:125:4 + wire [12:0] end_addr_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:126:4 + wire [2:0] addr_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:128:4 + wire [63:0] dma_mem_wdata_shifted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:129:4 + wire addr_external_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:130:4 + wire addr_external_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:131:4 + wire access_fault_d; + wire misaligned_fault_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:132:4 + wire access_fault_m; + wire misaligned_fault_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:134:4 + wire fir_dccm_access_error_d; + wire fir_nondccm_access_error_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:135:4 + wire fir_dccm_access_error_m; + wire fir_nondccm_access_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:137:4 + wire [3:0] exc_mscause_d; + wire [3:0] exc_mscause_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:138:4 + wire [31:0] rs1_d_raw; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:139:4 + wire [31:0] store_data_d; + wire [31:0] store_data_pre_m; + wire [31:0] store_data_m_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:140:4 + wire [31:0] bus_read_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:142:4 + reg [13:0] dma_pkt_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:143:4 + reg [13:0] lsu_pkt_m_in; + reg [13:0] lsu_pkt_r_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:144:4 + wire [39:0] lsu_error_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:148:4 + assign lsu_rs1_d[31:0] = (dec_lsu_valid_raw_d ? exu_lsu_rs1_d[31:0] : dma_mem_addr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:149:4 + assign lsu_offset_d[11:0] = dec_lsu_offset_d[11:0] & {12 {dec_lsu_valid_raw_d}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:150:4 + assign rs1_d_raw[31:0] = lsu_rs1_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:151:4 + assign offset_d[11:0] = lsu_offset_d[11:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:153:4 + assign rs1_d[31:0] = (lsu_pkt_d[2] ? lsu_result_m[31:0] : rs1_d_raw[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:156:4 + rvlsadder lsadder( + .rs1(rs1_d[31:0]), + .offset(offset_d[11:0]), + .dout(full_addr_d[31:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:162:4 + el2_lsu_addrcheck addrcheck( + .start_addr_d(full_addr_d[31:0]), + .end_addr_d(full_end_addr_d[31:0]), + .rs1_region_d(rs1_d[31:28]), + .lsu_c2_m_clk(lsu_c2_m_clk), + .rst_l(rst_l), + .lsu_pkt_d(lsu_pkt_d), + .dec_tlu_mrac_ff(dec_tlu_mrac_ff), + .rs1_d(rs1_d), + .is_sideeffects_m(is_sideeffects_m), + .addr_in_dccm_d(addr_in_dccm_d), + .addr_in_pic_d(addr_in_pic_d), + .addr_external_d(addr_external_d), + .access_fault_d(access_fault_d), + .misaligned_fault_d(misaligned_fault_d), + .exc_mscause_d(exc_mscause_d), + .fir_dccm_access_error_d(fir_dccm_access_error_d), + .fir_nondccm_access_error_d(fir_nondccm_access_error_d), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:170:4 + assign addr_offset_d[2:0] = (({3 {lsu_pkt_d[10]}} & 3'b001) | ({3 {lsu_pkt_d[9]}} & 3'b011)) | ({3 {lsu_pkt_d[8]}} & 3'b111); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:171:4 + assign end_addr_offset_d[12:0] = {offset_d[11], offset_d[11:0]} + {9'b000000000, addr_offset_d[2:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:172:4 + assign full_end_addr_d[31:0] = rs1_d[31:0] + {{19 {end_addr_offset_d[12]}}, end_addr_offset_d[12:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:173:4 + assign end_addr_d[31:0] = full_end_addr_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:174:4 + assign lsu_exc_m = access_fault_m | misaligned_fault_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:177:4 + assign lsu_single_ecc_error_incr = ((lsu_single_ecc_error_r & ~lsu_double_ecc_error_r) & (lsu_commit_r | lsu_pkt_r[4])) & lsu_pkt_r[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:179:4 + generate + if (pt[202-:5] == 1) begin : L2U_Plus1_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:180:7 + wire access_fault_r; + wire misaligned_fault_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:181:7 + wire [3:0] exc_mscause_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:182:7 + wire fir_dccm_access_error_r; + wire fir_nondccm_access_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:185:7 + assign lsu_error_pkt_r[0] = ((((access_fault_r | misaligned_fault_r) | lsu_double_ecc_error_r) & lsu_pkt_r[0]) & ~lsu_pkt_r[4]) & ~lsu_pkt_r[13]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:186:7 + assign lsu_error_pkt_r[1] = (lsu_single_ecc_error_r & ~lsu_error_pkt_r[0]) & ~lsu_pkt_r[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:187:7 + assign lsu_error_pkt_r[39] = lsu_pkt_r[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:188:7 + assign lsu_error_pkt_r[38] = ~misaligned_fault_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:189:7 + assign lsu_error_pkt_r[37:34] = ((lsu_double_ecc_error_r & ~misaligned_fault_r) & ~access_fault_r ? 4'h1 : exc_mscause_r[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:190:7 + assign lsu_error_pkt_r[33:2] = lsu_addr_r[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:192:7 + assign lsu_fir_error[1:0] = (fir_nondccm_access_error_r ? 2'b11 : (fir_dccm_access_error_r ? 2'b10 : (lsu_pkt_r[13] & lsu_double_ecc_error_r ? 2'b01 : 2'b00))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:194:7 + rvdff #(.WIDTH(1)) access_fault_rff( + .din(access_fault_m), + .dout(access_fault_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:195:7 + rvdff #(.WIDTH(1)) misaligned_fault_rff( + .din(misaligned_fault_m), + .dout(misaligned_fault_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:196:7 + rvdff #(.WIDTH(4)) exc_mscause_rff( + .din(exc_mscause_m[3:0]), + .dout(exc_mscause_r[3:0]), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:197:7 + rvdff #(.WIDTH(1)) fir_dccm_access_error_mff( + .din(fir_dccm_access_error_m), + .dout(fir_dccm_access_error_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:198:7 + rvdff #(.WIDTH(1)) fir_nondccm_access_error_mff( + .din(fir_nondccm_access_error_m), + .dout(fir_nondccm_access_error_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + end + else begin : L2U_Plus1_0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:201:7 + wire [1:0] lsu_fir_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:204:7 + assign lsu_error_pkt_m[0] = (((((access_fault_m | misaligned_fault_m) | lsu_double_ecc_error_m) & lsu_pkt_m[0]) & ~lsu_pkt_m[4]) & ~lsu_pkt_m[13]) & ~flush_m_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:205:7 + assign lsu_error_pkt_m[1] = (lsu_single_ecc_error_m & ~lsu_error_pkt_m[0]) & ~lsu_pkt_m[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:206:7 + assign lsu_error_pkt_m[39] = lsu_pkt_m[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:207:7 + assign lsu_error_pkt_m[38] = ~misaligned_fault_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:208:7 + assign lsu_error_pkt_m[37:34] = ((lsu_double_ecc_error_m & ~misaligned_fault_m) & ~access_fault_m ? 4'h1 : exc_mscause_m[3:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:209:7 + assign lsu_error_pkt_m[33:2] = lsu_addr_m[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:211:7 + assign lsu_fir_error_m[1:0] = (fir_nondccm_access_error_m ? 2'b11 : (fir_dccm_access_error_m ? 2'b10 : (lsu_pkt_m[13] & lsu_double_ecc_error_m ? 2'b01 : 2'b00))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:213:7 + rvdff #(.WIDTH(1)) lsu_exc_valid_rff( + .rst_l(rst_l), + .din(lsu_error_pkt_m[0]), + .dout(lsu_error_pkt_r[0]), + .clk(lsu_c2_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:214:7 + rvdff #(.WIDTH(1)) lsu_single_ecc_error_rff( + .rst_l(rst_l), + .din(lsu_error_pkt_m[1]), + .dout(lsu_error_pkt_r[1]), + .clk(lsu_c2_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:215:7 + rvdffe #(.WIDTH(38)) lsu_error_pkt_rff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(lsu_error_pkt_m[39:2]), + .dout(lsu_error_pkt_r[39:2]), + .en((lsu_error_pkt_m[0] | lsu_error_pkt_m[1]) | clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:216:7 + rvdff #(.WIDTH(2)) lsu_fir_error_rff( + .rst_l(rst_l), + .din(lsu_fir_error_m[1:0]), + .dout(lsu_fir_error[1:0]), + .clk(lsu_c2_r_clk) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:220:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:221:7 + dma_pkt_d = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:222:7 + dma_pkt_d[0] = dma_dccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:223:7 + dma_pkt_d[4] = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:224:7 + dma_pkt_d[6] = dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:225:7 + dma_pkt_d[7] = ~dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:226:7 + dma_pkt_d[11] = dma_mem_sz[2:0] == 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:227:7 + dma_pkt_d[10] = dma_mem_sz[2:0] == 3'b001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:228:7 + dma_pkt_d[9] = dma_mem_sz[2:0] == 3'b010; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:229:7 + dma_pkt_d[8] = dma_mem_sz[2:0] == 3'b011; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:232:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:233:7 + lsu_pkt_d = (dec_lsu_valid_raw_d ? lsu_p : dma_pkt_d); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:234:7 + lsu_pkt_m_in = lsu_pkt_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:235:7 + lsu_pkt_r_in = lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:237:7 + lsu_pkt_d[0] = (lsu_p[0] & ~(flush_m_up & ~lsu_p[13])) | dma_dccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:238:7 + lsu_pkt_m_in[0] = lsu_pkt_d[0] & ~(flush_m_up & ~lsu_pkt_d[4]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:239:7 + lsu_pkt_r_in[0] = lsu_pkt_m[0] & ~(flush_m_up & ~lsu_pkt_m[4]); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:243:4 + rvdff #(.WIDTH(1)) lsu_pkt_vldmff( + .rst_l(rst_l), + .din(lsu_pkt_m_in[0]), + .dout(lsu_pkt_m[0]), + .clk(lsu_c2_m_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:244:4 + rvdff #(.WIDTH(1)) lsu_pkt_vldrff( + .rst_l(rst_l), + .din(lsu_pkt_r_in[0]), + .dout(lsu_pkt_r[0]), + .clk(lsu_c2_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:246:4 + rvdff #(.WIDTH(13)) lsu_pkt_mff( + .rst_l(rst_l), + .din(lsu_pkt_m_in[13:1]), + .dout(lsu_pkt_m[13:1]), + .clk(lsu_c1_m_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:247:4 + rvdff #(.WIDTH(13)) lsu_pkt_rff( + .rst_l(rst_l), + .din(lsu_pkt_r_in[13:1]), + .dout(lsu_pkt_r[13:1]), + .clk(lsu_c1_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:251:4 + generate + if (pt[202-:5] == 1) begin : L2U1_Plus1_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:252:7 + wire [31:0] lsu_ld_datafn_r; + wire [31:0] lsu_ld_datafn_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:254:7 + assign lsu_ld_datafn_r[31:0] = (addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_r[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:255:7 + assign lsu_ld_datafn_corr_r[31:0] = (addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:258:7 + assign lsu_result_m[31:0] = (((({32 {lsu_pkt_r[5] & lsu_pkt_r[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_r[7:0]}) | ({32 {lsu_pkt_r[5] & lsu_pkt_r[10]}} & {16'b0000000000000000, lsu_ld_datafn_r[15:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[11]}} & {{24 {lsu_ld_datafn_r[7]}}, lsu_ld_datafn_r[7:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[10]}} & {{16 {lsu_ld_datafn_r[15]}}, lsu_ld_datafn_r[15:0]})) | ({32 {lsu_pkt_r[9]}} & lsu_ld_datafn_r[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:265:7 + assign lsu_result_corr_r[31:0] = (((({32 {lsu_pkt_r[5] & lsu_pkt_r[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_corr_r[7:0]}) | ({32 {lsu_pkt_r[5] & lsu_pkt_r[10]}} & {16'b0000000000000000, lsu_ld_datafn_corr_r[15:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[11]}} & {{24 {lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[10]}} & {{16 {lsu_ld_datafn_corr_r[15]}}, lsu_ld_datafn_corr_r[15:0]})) | ({32 {lsu_pkt_r[9]}} & lsu_ld_datafn_corr_r[31:0]); + end + else begin : L2U1_Plus1_0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:272:7 + wire [31:0] lsu_ld_datafn_m; + wire [31:0] lsu_ld_datafn_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:274:7 + assign lsu_ld_datafn_m[31:0] = (addr_external_m ? bus_read_data_m[31:0] : lsu_ld_data_m[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:275:7 + assign lsu_ld_datafn_corr_r[31:0] = (addr_external_r ? bus_read_data_r[31:0] : lsu_ld_data_corr_r[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:278:7 + assign lsu_result_m[31:0] = (((({32 {lsu_pkt_m[5] & lsu_pkt_m[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_m[7:0]}) | ({32 {lsu_pkt_m[5] & lsu_pkt_m[10]}} & {16'b0000000000000000, lsu_ld_datafn_m[15:0]})) | ({32 {~lsu_pkt_m[5] & lsu_pkt_m[11]}} & {{24 {lsu_ld_datafn_m[7]}}, lsu_ld_datafn_m[7:0]})) | ({32 {~lsu_pkt_m[5] & lsu_pkt_m[10]}} & {{16 {lsu_ld_datafn_m[15]}}, lsu_ld_datafn_m[15:0]})) | ({32 {lsu_pkt_m[9]}} & lsu_ld_datafn_m[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:285:7 + assign lsu_result_corr_r[31:0] = (((({32 {lsu_pkt_r[5] & lsu_pkt_r[11]}} & {24'b000000000000000000000000, lsu_ld_datafn_corr_r[7:0]}) | ({32 {lsu_pkt_r[5] & lsu_pkt_r[10]}} & {16'b0000000000000000, lsu_ld_datafn_corr_r[15:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[11]}} & {{24 {lsu_ld_datafn_corr_r[7]}}, lsu_ld_datafn_corr_r[7:0]})) | ({32 {~lsu_pkt_r[5] & lsu_pkt_r[10]}} & {{16 {lsu_ld_datafn_corr_r[15]}}, lsu_ld_datafn_corr_r[15:0]})) | ({32 {lsu_pkt_r[9]}} & lsu_ld_datafn_corr_r[31:0]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:293:4 + assign lsu_fir_addr[31:1] = lsu_ld_data_corr_r[31:1]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:296:4 + assign lsu_addr_d[31:0] = full_addr_d[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:299:4 + assign lsu_commit_r = ((lsu_pkt_r[0] & (lsu_pkt_r[6] | lsu_pkt_r[7])) & ~flush_r) & ~lsu_pkt_r[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:301:4 + assign dma_mem_wdata_shifted[63:0] = dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:302:4 + assign store_data_d[31:0] = (dma_dccm_req ? dma_mem_wdata_shifted[31:0] : exu_lsu_rs2_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:304:4 + assign store_data_m_in[31:0] = (lsu_pkt_d[3] ? lsu_result_m[31:0] : store_data_d[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:306:4 + assign store_data_m[31:0] = (picm_mask_data_m[31:0] | {32 {~addr_in_pic_m}}) & (lsu_pkt_m[1] ? lsu_result_m[31:0] : store_data_pre_m[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:309:4 + rvdff #(.WIDTH(32)) sdmff( + .rst_l(rst_l), + .din(store_data_m_in[31:0]), + .dout(store_data_pre_m[31:0]), + .clk(lsu_store_c1_m_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:311:4 + rvdff #(.WIDTH(32)) samff( + .rst_l(rst_l), + .din(lsu_addr_d[31:0]), + .dout(lsu_addr_m[31:0]), + .clk(lsu_c1_m_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:312:4 + rvdff #(.WIDTH(32)) sarff( + .rst_l(rst_l), + .din(lsu_addr_m[31:0]), + .dout(lsu_addr_r[31:0]), + .clk(lsu_c1_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:314:4 + assign end_addr_m[31:3] = (ldst_dual_m ? end_addr_pre_m[31:3] : lsu_addr_m[31:3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:315:4 + assign end_addr_r[31:3] = (ldst_dual_r ? end_addr_pre_r[31:3] : lsu_addr_r[31:3]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:317:4 + rvdffe #(.WIDTH(29)) end_addr_hi_mff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(end_addr_d[31:3]), + .dout(end_addr_pre_m[31:3]), + .en((lsu_pkt_d[0] & ldst_dual_d) | clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:318:4 + rvdffe #(.WIDTH(29)) end_addr_hi_rff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(end_addr_m[31:3]), + .dout(end_addr_pre_r[31:3]), + .en((lsu_pkt_m[0] & ldst_dual_m) | clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:320:4 + rvdff #(.WIDTH(3)) end_addr_lo_mff( + .rst_l(rst_l), + .din(end_addr_d[2:0]), + .dout(end_addr_m[2:0]), + .clk(lsu_c1_m_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:321:4 + rvdff #(.WIDTH(3)) end_addr_lo_rff( + .rst_l(rst_l), + .din(end_addr_m[2:0]), + .dout(end_addr_r[2:0]), + .clk(lsu_c1_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:323:4 + rvdff #(.WIDTH(1)) addr_in_dccm_mff( + .din(addr_in_dccm_d), + .dout(addr_in_dccm_m), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:324:4 + rvdff #(.WIDTH(1)) addr_in_dccm_rff( + .din(addr_in_dccm_m), + .dout(addr_in_dccm_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:326:4 + rvdff #(.WIDTH(1)) addr_in_pic_mff( + .din(addr_in_pic_d), + .dout(addr_in_pic_m), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:327:4 + rvdff #(.WIDTH(1)) addr_in_pic_rff( + .din(addr_in_pic_m), + .dout(addr_in_pic_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:329:4 + rvdff #(.WIDTH(1)) addr_external_mff( + .din(addr_external_d), + .dout(addr_external_m), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:330:4 + rvdff #(.WIDTH(1)) addr_external_rff( + .din(addr_external_m), + .dout(addr_external_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:332:4 + rvdff #(.WIDTH(1)) access_fault_mff( + .din(access_fault_d), + .dout(access_fault_m), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:333:4 + rvdff #(.WIDTH(1)) misaligned_fault_mff( + .din(misaligned_fault_d), + .dout(misaligned_fault_m), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:334:4 + rvdff #(.WIDTH(4)) exc_mscause_mff( + .din(exc_mscause_d[3:0]), + .dout(exc_mscause_m[3:0]), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:336:4 + rvdff #(.WIDTH(1)) fir_dccm_access_error_mff( + .din(fir_dccm_access_error_d), + .dout(fir_dccm_access_error_m), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:337:4 + rvdff #(.WIDTH(1)) fir_nondccm_access_error_mff( + .din(fir_nondccm_access_error_d), + .dout(fir_nondccm_access_error_m), + .clk(lsu_c1_m_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_lsc_ctl.sv:339:4 + rvdffe #(.WIDTH(32)) bus_read_data_r_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(bus_read_data_m[31:0]), + .dout(bus_read_data_r[31:0]), + .en(addr_external_m | clk_override) + ); + initial _sv2v_0 = 0; +endmodule +module el2_lsu_stbuf ( + clk, + rst_l, + lsu_stbuf_c1_clk, + lsu_free_c2_clk, + store_stbuf_reqvld_r, + lsu_commit_r, + dec_lsu_valid_raw_d, + store_data_hi_r, + store_data_lo_r, + store_datafn_hi_r, + store_datafn_lo_r, + stbuf_reqvld_any, + stbuf_reqvld_flushed_any, + stbuf_addr_any, + stbuf_data_any, + lsu_stbuf_commit_any, + lsu_stbuf_full_any, + lsu_stbuf_empty_any, + ldst_stbuf_reqvld_r, + lsu_addr_d, + lsu_addr_m, + lsu_addr_r, + end_addr_d, + end_addr_m, + end_addr_r, + ldst_dual_d, + ldst_dual_m, + ldst_dual_r, + addr_in_dccm_m, + addr_in_dccm_r, + lsu_cmpen_m, + lsu_pkt_m, + lsu_pkt_r, + stbuf_fwddata_hi_m, + stbuf_fwddata_lo_m, + stbuf_fwdbyteen_hi_m, + stbuf_fwdbyteen_lo_m, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:36:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:37:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:39:4 + input wire lsu_stbuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:40:4 + input wire lsu_free_c2_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:43:4 + input wire store_stbuf_reqvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:44:4 + input wire lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:45:4 + input wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:46:4 + input wire [pt[1382-:10] - 1:0] store_data_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:47:4 + input wire [pt[1382-:10] - 1:0] store_data_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:48:4 + input wire [pt[1382-:10] - 1:0] store_datafn_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:49:4 + input wire [pt[1382-:10] - 1:0] store_datafn_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:52:4 + output wire stbuf_reqvld_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:53:4 + output wire stbuf_reqvld_flushed_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:54:4 + output wire [pt[157-:9] - 1:0] stbuf_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:55:4 + output wire [pt[1382-:10] - 1:0] stbuf_data_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:57:4 + input wire lsu_stbuf_commit_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:58:4 + output wire lsu_stbuf_full_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:59:4 + output wire lsu_stbuf_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:60:4 + output wire ldst_stbuf_reqvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:62:4 + input wire [pt[157-:9] - 1:0] lsu_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:63:4 + input wire [31:0] lsu_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:64:4 + input wire [31:0] lsu_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:66:4 + input wire [pt[157-:9] - 1:0] end_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:67:4 + input wire [31:0] end_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:68:4 + input wire [31:0] end_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:70:4 + input wire ldst_dual_d; + input wire ldst_dual_m; + input wire ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:71:4 + input wire addr_in_dccm_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:72:4 + input wire addr_in_dccm_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:75:4 + input wire lsu_cmpen_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:76:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:77:4 + input wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:79:4 + output wire [pt[1382-:10] - 1:0] stbuf_fwddata_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:80:4 + output wire [pt[1382-:10] - 1:0] stbuf_fwddata_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:81:4 + output wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:82:4 + output wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:84:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:89:4 + localparam DEPTH = pt[148-:8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:90:4 + localparam DATA_WIDTH = pt[1382-:10]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:91:4 + localparam BYTE_WIDTH = pt[1389-:7]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:92:4 + localparam DEPTH_LOG2 = $clog2(DEPTH); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:95:4 + wire [DEPTH - 1:0] stbuf_vld; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:96:4 + wire [DEPTH - 1:0] stbuf_dma_kill; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:97:4 + wire [(DEPTH * pt[157-:9]) - 1:0] stbuf_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:98:4 + wire [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_byteen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:99:4 + wire [(DEPTH * DATA_WIDTH) - 1:0] stbuf_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:101:4 + wire [DEPTH - 1:0] sel_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:102:4 + wire [DEPTH - 1:0] stbuf_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:103:4 + reg [DEPTH - 1:0] stbuf_dma_kill_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:104:4 + wire [DEPTH - 1:0] stbuf_reset; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:105:4 + wire [(DEPTH * pt[157-:9]) - 1:0] stbuf_addrin; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:106:4 + wire [(DEPTH * DATA_WIDTH) - 1:0] stbuf_datain; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:107:4 + wire [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_byteenin; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:109:4 + wire [7:0] store_byteen_ext_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:110:4 + wire [BYTE_WIDTH - 1:0] store_byteen_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:111:4 + wire [BYTE_WIDTH - 1:0] store_byteen_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:113:4 + wire WrPtrEn; + wire RdPtrEn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:114:4 + wire [DEPTH_LOG2 - 1:0] WrPtr; + wire [DEPTH_LOG2 - 1:0] RdPtr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:115:4 + wire [DEPTH_LOG2 - 1:0] NxtWrPtr; + wire [DEPTH_LOG2 - 1:0] NxtRdPtr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:116:4 + wire [DEPTH_LOG2 - 1:0] WrPtrPlus1; + wire [DEPTH_LOG2 - 1:0] WrPtrPlus2; + wire [DEPTH_LOG2 - 1:0] RdPtrPlus1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:118:4 + wire dual_stbuf_write_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:120:4 + wire isdccmst_m; + wire isdccmst_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:121:4 + reg [3:0] stbuf_numvld_any; + wire [3:0] stbuf_specvld_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:122:4 + wire [1:0] stbuf_specvld_m; + wire [1:0] stbuf_specvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:124:4 + wire [pt[157-:9] - 1:$clog2(BYTE_WIDTH)] cmpaddr_hi_m; + wire [pt[157-:9] - 1:$clog2(BYTE_WIDTH)] cmpaddr_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:127:4 + reg [DEPTH - 1:0] stbuf_match_hi; + reg [DEPTH - 1:0] stbuf_match_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:128:4 + reg [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_fwdbyteenvec_hi; + reg [(DEPTH * BYTE_WIDTH) - 1:0] stbuf_fwdbyteenvec_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:129:4 + reg [DATA_WIDTH - 1:0] stbuf_fwddata_hi_pre_m; + reg [DATA_WIDTH - 1:0] stbuf_fwddata_lo_pre_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:130:4 + reg [BYTE_WIDTH - 1:0] stbuf_fwdbyteen_hi_pre_m; + reg [BYTE_WIDTH - 1:0] stbuf_fwdbyteen_lo_pre_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:133:4 + wire [BYTE_WIDTH - 1:0] ld_byte_rhit_lo_lo; + wire [BYTE_WIDTH - 1:0] ld_byte_rhit_hi_lo; + wire [BYTE_WIDTH - 1:0] ld_byte_rhit_lo_hi; + wire [BYTE_WIDTH - 1:0] ld_byte_rhit_hi_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:134:4 + wire ld_addr_rhit_lo_lo; + wire ld_addr_rhit_hi_lo; + wire ld_addr_rhit_lo_hi; + wire ld_addr_rhit_hi_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:136:4 + wire [BYTE_WIDTH - 1:0] ld_byte_hit_lo; + wire [BYTE_WIDTH - 1:0] ld_byte_rhit_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:137:4 + wire [BYTE_WIDTH - 1:0] ld_byte_hit_hi; + wire [BYTE_WIDTH - 1:0] ld_byte_rhit_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:139:4 + wire [BYTE_WIDTH - 1:0] ldst_byteen_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:140:4 + wire [BYTE_WIDTH - 1:0] ldst_byteen_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:142:4 + wire [7:0] ldst_byteen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:143:4 + wire [7:0] ldst_byteen_ext_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:145:4 + wire [31:0] ld_fwddata_rpipe_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:146:4 + wire [31:0] ld_fwddata_rpipe_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:149:4 + wire [DEPTH - 1:0] store_matchvec_lo_r; + wire [DEPTH - 1:0] store_matchvec_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:150:4 + wire store_coalesce_lo_r; + wire store_coalesce_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:156:4 + assign store_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:157:4 + assign store_byteen_hi_r[BYTE_WIDTH - 1:0] = store_byteen_ext_r[7:4] & {4 {lsu_pkt_r[6]}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:158:4 + assign store_byteen_lo_r[BYTE_WIDTH - 1:0] = store_byteen_ext_r[3:0] & {4 {lsu_pkt_r[6]}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:160:4 + assign RdPtrPlus1[DEPTH_LOG2 - 1:0] = RdPtr[DEPTH_LOG2 - 1:0] + 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:161:4 + assign WrPtrPlus1[DEPTH_LOG2 - 1:0] = WrPtr[DEPTH_LOG2 - 1:0] + 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:162:4 + assign WrPtrPlus2[DEPTH_LOG2 - 1:0] = WrPtr[DEPTH_LOG2 - 1:0] + 2'b10; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:165:4 + assign dual_stbuf_write_r = ldst_dual_r & store_stbuf_reqvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:166:4 + assign ldst_stbuf_reqvld_r = (lsu_commit_r | lsu_pkt_r[4]) & store_stbuf_reqvld_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:169:4 + genvar _gv_i_46; + generate + for (_gv_i_46 = 0; _gv_i_46 < DEPTH; _gv_i_46 = _gv_i_46 + 1) begin : FindMatchEntry + localparam i = _gv_i_46; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:170:8 + assign store_matchvec_lo_r[i] = (((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == lsu_addr_r[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & ~stbuf_reset[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:171:8 + assign store_matchvec_hi_r[i] = ((((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == end_addr_r[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & dual_stbuf_write_r) & ~stbuf_reset[i]; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:174:4 + assign store_coalesce_lo_r = |store_matchvec_lo_r[DEPTH - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:175:4 + assign store_coalesce_hi_r = |store_matchvec_hi_r[DEPTH - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:178:4 + generate + if (pt[1365-:5] == 1) begin : Gen_dccm_enable + genvar _gv_i_47; + for (_gv_i_47 = 0; _gv_i_47 < DEPTH; _gv_i_47 = _gv_i_47 + 1) begin : GenStBuf + localparam i = _gv_i_47; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:186:10 + assign stbuf_wr_en[i] = ldst_stbuf_reqvld_r & ((((((i == WrPtr[DEPTH_LOG2 - 1:0]) & ~store_coalesce_lo_r) | (((i == WrPtr[DEPTH_LOG2 - 1:0]) & dual_stbuf_write_r) & ~store_coalesce_hi_r)) | (((i == WrPtrPlus1[DEPTH_LOG2 - 1:0]) & dual_stbuf_write_r) & ~(store_coalesce_lo_r | store_coalesce_hi_r))) | store_matchvec_lo_r[i]) | store_matchvec_hi_r[i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:191:10 + assign stbuf_reset[i] = (lsu_stbuf_commit_any | stbuf_reqvld_flushed_any) & (i == RdPtr[DEPTH_LOG2 - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:194:10 + assign sel_lo[i] = (((~ldst_dual_r | store_stbuf_reqvld_r) & (i == WrPtr[DEPTH_LOG2 - 1:0])) & ~store_coalesce_lo_r) | store_matchvec_lo_r[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:196:10 + assign stbuf_addrin[(i * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]] = (sel_lo[i] ? lsu_addr_r[pt[157-:9] - 1:0] : end_addr_r[pt[157-:9] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:197:10 + assign stbuf_byteenin[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH] = (sel_lo[i] ? stbuf_byteen[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH] | store_byteen_lo_r[BYTE_WIDTH - 1:0] : stbuf_byteen[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH] | store_byteen_hi_r[BYTE_WIDTH - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:198:10 + assign stbuf_datain[(i * DATA_WIDTH) + 7-:8] = (sel_lo[i] ? (~stbuf_byteen[i * BYTE_WIDTH] | store_byteen_lo_r[0] ? store_datafn_lo_r[7:0] : stbuf_data[(i * DATA_WIDTH) + 7-:8]) : (~stbuf_byteen[i * BYTE_WIDTH] | store_byteen_hi_r[0] ? store_datafn_hi_r[7:0] : stbuf_data[(i * DATA_WIDTH) + 7-:8])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:200:10 + assign stbuf_datain[(i * DATA_WIDTH) + 15-:8] = (sel_lo[i] ? (~stbuf_byteen[(i * BYTE_WIDTH) + 1] | store_byteen_lo_r[1] ? store_datafn_lo_r[15:8] : stbuf_data[(i * DATA_WIDTH) + 15-:8]) : (~stbuf_byteen[(i * BYTE_WIDTH) + 1] | store_byteen_hi_r[1] ? store_datafn_hi_r[15:8] : stbuf_data[(i * DATA_WIDTH) + 15-:8])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:202:10 + assign stbuf_datain[(i * DATA_WIDTH) + 23-:8] = (sel_lo[i] ? (~stbuf_byteen[(i * BYTE_WIDTH) + 2] | store_byteen_lo_r[2] ? store_datafn_lo_r[23:16] : stbuf_data[(i * DATA_WIDTH) + 23-:8]) : (~stbuf_byteen[(i * BYTE_WIDTH) + 2] | store_byteen_hi_r[2] ? store_datafn_hi_r[23:16] : stbuf_data[(i * DATA_WIDTH) + 23-:8])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:204:10 + assign stbuf_datain[(i * DATA_WIDTH) + 31-:8] = (sel_lo[i] ? (~stbuf_byteen[(i * BYTE_WIDTH) + 3] | store_byteen_lo_r[3] ? store_datafn_lo_r[31:24] : stbuf_data[(i * DATA_WIDTH) + 31-:8]) : (~stbuf_byteen[(i * BYTE_WIDTH) + 3] | store_byteen_hi_r[3] ? store_datafn_hi_r[31:24] : stbuf_data[(i * DATA_WIDTH) + 31-:8])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:207:10 + rvdffsc #(.WIDTH(1)) stbuf_vldff( + .din(1'b1), + .dout(stbuf_vld[i]), + .en(stbuf_wr_en[i]), + .clear(stbuf_reset[i]), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:208:10 + rvdffsc #(.WIDTH(1)) stbuf_killff( + .din(1'b1), + .dout(stbuf_dma_kill[i]), + .en(stbuf_dma_kill_en[i]), + .clear(stbuf_reset[i]), + .clk(lsu_free_c2_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:209:10 + rvdffe #(.WIDTH(pt[157-:9])) stbuf_addrff( + .din(stbuf_addrin[(i * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]]), + .dout(stbuf_addr[(i * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]]), + .en(stbuf_wr_en[i]), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:210:10 + rvdffsc #(.WIDTH(BYTE_WIDTH)) stbuf_byteenff( + .din(stbuf_byteenin[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH]), + .dout(stbuf_byteen[(i * BYTE_WIDTH) + (BYTE_WIDTH - 1)-:BYTE_WIDTH]), + .en(stbuf_wr_en[i]), + .clear(stbuf_reset[i]), + .clk(lsu_stbuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:211:10 + rvdffe #(.WIDTH(DATA_WIDTH)) stbuf_dataff( + .din(stbuf_datain[(i * DATA_WIDTH) + (DATA_WIDTH - 1)-:DATA_WIDTH]), + .dout(stbuf_data[(i * DATA_WIDTH) + (DATA_WIDTH - 1)-:DATA_WIDTH]), + .en(stbuf_wr_en[i]), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + end + end + else begin : Gen_dccm_disable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:214:7 + assign stbuf_wr_en[DEPTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:215:7 + assign stbuf_reset[DEPTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:216:7 + assign stbuf_vld[DEPTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:217:7 + assign stbuf_dma_kill[DEPTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:218:7 + assign stbuf_addr[pt[157-:9] * ((DEPTH - 1) - (DEPTH - 1))+:pt[157-:9] * DEPTH] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:219:7 + assign stbuf_byteen[BYTE_WIDTH * ((DEPTH - 1) - (DEPTH - 1))+:BYTE_WIDTH * DEPTH] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:220:7 + assign stbuf_data[DATA_WIDTH * ((DEPTH - 1) - (DEPTH - 1))+:DATA_WIDTH * DEPTH] = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:224:4 + assign stbuf_reqvld_flushed_any = stbuf_vld[RdPtr] & stbuf_dma_kill[RdPtr]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:225:4 + assign stbuf_reqvld_any = (stbuf_vld[RdPtr] & ~stbuf_dma_kill[RdPtr]) & ~(|stbuf_dma_kill_en[DEPTH - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:226:4 + assign stbuf_addr_any[pt[157-:9] - 1:0] = stbuf_addr[(RdPtr * pt[157-:9]) + (pt[157-:9] - 1)-:pt[157-:9]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:227:4 + assign stbuf_data_any[DATA_WIDTH - 1:0] = stbuf_data[(RdPtr * DATA_WIDTH) + (DATA_WIDTH - 1)-:DATA_WIDTH]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:231:4 + assign WrPtrEn = ((ldst_stbuf_reqvld_r & ~dual_stbuf_write_r) & ~(store_coalesce_hi_r | store_coalesce_lo_r)) | ((ldst_stbuf_reqvld_r & dual_stbuf_write_r) & ~(store_coalesce_hi_r & store_coalesce_lo_r)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:233:4 + assign NxtWrPtr[DEPTH_LOG2 - 1:0] = ((ldst_stbuf_reqvld_r & dual_stbuf_write_r) & ~(store_coalesce_hi_r | store_coalesce_lo_r) ? WrPtrPlus2[DEPTH_LOG2 - 1:0] : WrPtrPlus1[DEPTH_LOG2 - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:234:4 + assign RdPtrEn = lsu_stbuf_commit_any | stbuf_reqvld_flushed_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:235:4 + assign NxtRdPtr[DEPTH_LOG2 - 1:0] = RdPtrPlus1[DEPTH_LOG2 - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:237:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:238:7 + stbuf_numvld_any[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:239:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:239:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:239:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:240:10 + stbuf_numvld_any[3:0] = stbuf_numvld_any[3:0] + {3'b000, stbuf_vld[i]}; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:245:4 + assign isdccmst_m = ((lsu_pkt_m[0] & lsu_pkt_m[6]) & addr_in_dccm_m) & ~lsu_pkt_m[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:246:4 + assign isdccmst_r = ((lsu_pkt_r[0] & lsu_pkt_r[6]) & addr_in_dccm_r) & ~lsu_pkt_r[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:248:4 + assign stbuf_specvld_m[1:0] = {1'b0, isdccmst_m} << (isdccmst_m & ldst_dual_m); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:249:4 + assign stbuf_specvld_r[1:0] = {1'b0, isdccmst_r} << (isdccmst_r & ldst_dual_r); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:250:4 + assign stbuf_specvld_any[3:0] = (stbuf_numvld_any[3:0] + {2'b00, stbuf_specvld_m[1:0]}) + {2'b00, stbuf_specvld_r[1:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:252:4 + assign lsu_stbuf_full_any = (~ldst_dual_d & dec_lsu_valid_raw_d ? stbuf_specvld_any[3:0] >= DEPTH : stbuf_specvld_any[3:0] >= (DEPTH - 1)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:253:4 + assign lsu_stbuf_empty_any = stbuf_numvld_any[3:0] == 4'b0000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:256:4 + assign cmpaddr_hi_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)] = end_addr_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:258:4 + assign cmpaddr_lo_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)] = lsu_addr_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:260:4 + always @(*) begin : GenLdFwd + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:261:7 + stbuf_fwdbyteen_hi_pre_m[BYTE_WIDTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:262:7 + stbuf_fwdbyteen_lo_pre_m[BYTE_WIDTH - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:264:7 + begin : sv2v_autoblock_2 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:264:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:264:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:265:10 + stbuf_match_hi[i] = (((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == cmpaddr_hi_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & addr_in_dccm_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:266:10 + stbuf_match_lo[i] = (((stbuf_addr[(i * pt[157-:9]) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? pt[157-:9] - 1 : ((pt[157-:9] - 1) + ((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)) - 1)-:((pt[157-:9] - 1) >= $clog2(BYTE_WIDTH) ? ((pt[157-:9] - 1) - $clog2(BYTE_WIDTH)) + 1 : ($clog2(BYTE_WIDTH) - (pt[157-:9] - 1)) + 1)] == cmpaddr_lo_m[pt[157-:9] - 1:$clog2(BYTE_WIDTH)]) & stbuf_vld[i]) & ~stbuf_dma_kill[i]) & addr_in_dccm_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:269:10 + stbuf_dma_kill_en[i] = (((stbuf_match_hi[i] | stbuf_match_lo[i]) & lsu_pkt_m[0]) & lsu_pkt_m[4]) & lsu_pkt_m[6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:271:10 + begin : sv2v_autoblock_3 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:271:15 + reg signed [31:0] j; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:271:15 + for (j = 0; j < BYTE_WIDTH; j = j + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:272:13 + stbuf_fwdbyteenvec_hi[(i * BYTE_WIDTH) + j] = (stbuf_match_hi[i] & stbuf_byteen[(i * BYTE_WIDTH) + j]) & stbuf_vld[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:273:13 + stbuf_fwdbyteen_hi_pre_m[j] = stbuf_fwdbyteen_hi_pre_m[j] | stbuf_fwdbyteenvec_hi[(i * BYTE_WIDTH) + j]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:275:13 + stbuf_fwdbyteenvec_lo[(i * BYTE_WIDTH) + j] = (stbuf_match_lo[i] & stbuf_byteen[(i * BYTE_WIDTH) + j]) & stbuf_vld[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:276:13 + stbuf_fwdbyteen_lo_pre_m[j] = stbuf_fwdbyteen_lo_pre_m[j] | stbuf_fwdbyteenvec_lo[(i * BYTE_WIDTH) + j]; + end + end + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:281:4 + always @(*) begin : GenLdData + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:282:7 + stbuf_fwddata_hi_pre_m[31:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:283:7 + stbuf_fwddata_lo_pre_m[31:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:285:7 + begin : sv2v_autoblock_4 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:285:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:285:12 + for (i = 0; i < DEPTH; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:286:10 + stbuf_fwddata_hi_pre_m[31:0] = stbuf_fwddata_hi_pre_m[31:0] | ({32 {stbuf_match_hi[i]}} & stbuf_data[(i * DATA_WIDTH) + 31-:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:287:10 + stbuf_fwddata_lo_pre_m[31:0] = stbuf_fwddata_lo_pre_m[31:0] | ({32 {stbuf_match_lo[i]}} & stbuf_data[(i * DATA_WIDTH) + 31-:32]); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:294:4 + assign ldst_byteen_r[7:0] = ((({8 {lsu_pkt_r[11]}} & 8'b00000001) | ({8 {lsu_pkt_r[10]}} & 8'b00000011)) | ({8 {lsu_pkt_r[9]}} & 8'b00001111)) | ({8 {lsu_pkt_r[8]}} & 8'b11111111); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:299:4 + assign ldst_byteen_ext_r[7:0] = ldst_byteen_r[7:0] << lsu_addr_r[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:301:4 + assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:302:4 + assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:304:4 + assign ld_addr_rhit_lo_lo = (((lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:305:4 + assign ld_addr_rhit_lo_hi = (((end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:306:4 + assign ld_addr_rhit_hi_lo = ((((lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4]) & dual_stbuf_write_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:307:4 + assign ld_addr_rhit_hi_hi = ((((end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & ~lsu_pkt_r[4]) & dual_stbuf_write_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:309:4 + genvar _gv_i_48; + generate + for (_gv_i_48 = 0; _gv_i_48 < BYTE_WIDTH; _gv_i_48 = _gv_i_48 + 1) begin : genblk3 + localparam i = _gv_i_48; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:310:7 + assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:311:7 + assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:312:7 + assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:313:7 + assign ld_byte_rhit_hi_hi[i] = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:315:7 + assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:316:7 + assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:318:8 + assign ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:321:8 + assign ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:324:7 + assign ld_byte_hit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:325:7 + assign ld_byte_hit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:327:7 + assign stbuf_fwdbyteen_hi_m[i] = ld_byte_hit_hi[i] | stbuf_fwdbyteen_hi_pre_m[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:328:7 + assign stbuf_fwdbyteen_lo_m[i] = ld_byte_hit_lo[i] | stbuf_fwdbyteen_lo_pre_m[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:330:7 + assign stbuf_fwddata_lo_m[(8 * i) + 7:8 * i] = (ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] : stbuf_fwddata_lo_pre_m[(8 * i) + 7:8 * i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:332:7 + assign stbuf_fwddata_hi_m[(8 * i) + 7:8 * i] = (ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] : stbuf_fwddata_hi_pre_m[(8 * i) + 7:8 * i]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:336:4 + rvdffs #(.WIDTH(DEPTH_LOG2)) WrPtrff( + .din(NxtWrPtr[DEPTH_LOG2 - 1:0]), + .dout(WrPtr[DEPTH_LOG2 - 1:0]), + .en(WrPtrEn), + .clk(lsu_stbuf_c1_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_stbuf.sv:337:4 + rvdffs #(.WIDTH(DEPTH_LOG2)) RdPtrff( + .din(NxtRdPtr[DEPTH_LOG2 - 1:0]), + .dout(RdPtr[DEPTH_LOG2 - 1:0]), + .en(RdPtrEn), + .clk(lsu_stbuf_c1_clk), + .rst_l(rst_l) + ); + initial _sv2v_0 = 0; +endmodule +module el2_lsu_bus_intf ( + clk, + clk_override, + rst_l, + scan_mode, + dec_tlu_external_ldfwd_disable, + dec_tlu_wb_coalescing_disable, + dec_tlu_sideeffect_posted_disable, + lsu_bus_obuf_c1_clken, + lsu_busm_clken, + lsu_c1_r_clk, + lsu_c2_r_clk, + lsu_bus_ibuf_c1_clk, + lsu_bus_obuf_c1_clk, + lsu_bus_buf_c1_clk, + lsu_free_c2_clk, + active_clk, + lsu_busm_clk, + dec_lsu_valid_raw_d, + lsu_busreq_m, + lsu_pkt_m, + lsu_pkt_r, + lsu_addr_m, + lsu_addr_r, + end_addr_m, + end_addr_r, + store_data_r, + dec_tlu_force_halt, + lsu_commit_r, + is_sideeffects_m, + flush_m_up, + flush_r, + ldst_dual_d, + ldst_dual_m, + ldst_dual_r, + lsu_busreq_r, + lsu_bus_buffer_pend_any, + lsu_bus_buffer_full_any, + lsu_bus_buffer_empty_any, + bus_read_data_m, + lsu_imprecise_error_load_any, + lsu_imprecise_error_store_any, + lsu_imprecise_error_addr_any, + lsu_nonblock_load_valid_m, + lsu_nonblock_load_tag_m, + lsu_nonblock_load_inv_r, + lsu_nonblock_load_inv_tag_r, + lsu_nonblock_load_data_valid, + lsu_nonblock_load_data_error, + lsu_nonblock_load_data_tag, + lsu_nonblock_load_data, + lsu_pmu_bus_trxn, + lsu_pmu_bus_misaligned, + lsu_pmu_bus_error, + lsu_pmu_bus_busy, + lsu_axi_awvalid, + lsu_axi_awready, + lsu_axi_awid, + lsu_axi_awaddr, + lsu_axi_awregion, + lsu_axi_awlen, + lsu_axi_awsize, + lsu_axi_awburst, + lsu_axi_awlock, + lsu_axi_awcache, + lsu_axi_awprot, + lsu_axi_awqos, + lsu_axi_wvalid, + lsu_axi_wready, + lsu_axi_wdata, + lsu_axi_wstrb, + lsu_axi_wlast, + lsu_axi_bvalid, + lsu_axi_bready, + lsu_axi_bresp, + lsu_axi_bid, + lsu_axi_arvalid, + lsu_axi_arready, + lsu_axi_arid, + lsu_axi_araddr, + lsu_axi_arregion, + lsu_axi_arlen, + lsu_axi_arsize, + lsu_axi_arburst, + lsu_axi_arlock, + lsu_axi_arcache, + lsu_axi_arprot, + lsu_axi_arqos, + lsu_axi_rvalid, + lsu_axi_rready, + lsu_axi_rid, + lsu_axi_rdata, + lsu_axi_rresp, + lsu_bus_clk_en +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:30:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:31:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:32:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:33:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:34:4 + input wire dec_tlu_external_ldfwd_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:35:4 + input wire dec_tlu_wb_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:36:4 + input wire dec_tlu_sideeffect_posted_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:39:4 + input wire lsu_bus_obuf_c1_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:40:4 + input wire lsu_busm_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:42:4 + input wire lsu_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:43:4 + input wire lsu_c2_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:44:4 + input wire lsu_bus_ibuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:45:4 + input wire lsu_bus_obuf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:46:4 + input wire lsu_bus_buf_c1_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:47:4 + input wire lsu_free_c2_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:48:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:49:4 + input wire lsu_busm_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:51:4 + input wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:52:4 + input wire lsu_busreq_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:54:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:55:4 + input wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:57:4 + input wire [31:0] lsu_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:58:4 + input wire [31:0] lsu_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:60:4 + input wire [31:0] end_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:61:4 + input wire [31:0] end_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:63:4 + input wire [31:0] store_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:64:4 + input wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:66:4 + input wire lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:67:4 + input wire is_sideeffects_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:68:4 + input wire flush_m_up; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:69:4 + input wire flush_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:70:4 + input wire ldst_dual_d; + input wire ldst_dual_m; + input wire ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:72:4 + output wire lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:73:4 + output wire lsu_bus_buffer_pend_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:74:4 + output wire lsu_bus_buffer_full_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:75:4 + output wire lsu_bus_buffer_empty_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:76:4 + output wire [31:0] bus_read_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:79:4 + output wire lsu_imprecise_error_load_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:80:4 + output wire lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:81:4 + output wire [31:0] lsu_imprecise_error_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:84:4 + output wire lsu_nonblock_load_valid_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:85:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:86:4 + output wire lsu_nonblock_load_inv_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:87:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:88:4 + output wire lsu_nonblock_load_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:89:4 + output wire lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:90:4 + output wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:91:4 + output wire [31:0] lsu_nonblock_load_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:94:4 + output wire lsu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:95:4 + output wire lsu_pmu_bus_misaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:96:4 + output wire lsu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:97:4 + output wire lsu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:100:4 + output wire lsu_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:101:4 + input wire lsu_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:102:4 + output wire [pt[181-:8] - 1:0] lsu_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:103:4 + output wire [31:0] lsu_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:104:4 + output wire [3:0] lsu_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:105:4 + output wire [7:0] lsu_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:106:4 + output wire [2:0] lsu_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:107:4 + output wire [1:0] lsu_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:108:4 + output wire lsu_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:109:4 + output wire [3:0] lsu_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:110:4 + output wire [2:0] lsu_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:111:4 + output wire [3:0] lsu_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:113:4 + output wire lsu_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:114:4 + input wire lsu_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:115:4 + output wire [63:0] lsu_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:116:4 + output wire [7:0] lsu_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:117:4 + output wire lsu_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:119:4 + input wire lsu_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:120:4 + output wire lsu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:121:4 + input wire [1:0] lsu_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:122:4 + input wire [pt[181-:8] - 1:0] lsu_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:125:4 + output wire lsu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:126:4 + input wire lsu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:127:4 + output wire [pt[181-:8] - 1:0] lsu_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:128:4 + output wire [31:0] lsu_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:129:4 + output wire [3:0] lsu_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:130:4 + output wire [7:0] lsu_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:131:4 + output wire [2:0] lsu_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:132:4 + output wire [1:0] lsu_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:133:4 + output wire lsu_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:134:4 + output wire [3:0] lsu_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:135:4 + output wire [2:0] lsu_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:136:4 + output wire [3:0] lsu_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:138:4 + input wire lsu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:139:4 + output wire lsu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:140:4 + input wire [pt[181-:8] - 1:0] lsu_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:141:4 + input wire [63:0] lsu_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:142:4 + input wire [1:0] lsu_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:144:4 + input wire lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:150:4 + wire lsu_bus_clk_en_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:152:4 + wire [3:0] ldst_byteen_m; + wire [3:0] ldst_byteen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:153:4 + wire [7:0] ldst_byteen_ext_m; + wire [7:0] ldst_byteen_ext_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:154:4 + wire [3:0] ldst_byteen_hi_m; + wire [3:0] ldst_byteen_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:155:4 + wire [3:0] ldst_byteen_lo_m; + wire [3:0] ldst_byteen_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:156:4 + wire is_sideeffects_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:158:4 + wire [63:0] store_data_ext_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:159:4 + wire [31:0] store_data_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:160:4 + wire [31:0] store_data_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:162:4 + wire addr_match_dw_lo_r_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:163:4 + wire addr_match_word_lo_r_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:164:4 + wire no_word_merge_r; + wire no_dword_merge_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:166:4 + wire ld_addr_rhit_lo_lo; + wire ld_addr_rhit_hi_lo; + wire ld_addr_rhit_lo_hi; + wire ld_addr_rhit_hi_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:167:4 + wire [3:0] ld_byte_rhit_lo_lo; + wire [3:0] ld_byte_rhit_hi_lo; + wire [3:0] ld_byte_rhit_lo_hi; + wire [3:0] ld_byte_rhit_hi_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:169:4 + wire [3:0] ld_byte_hit_lo; + wire [3:0] ld_byte_rhit_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:170:4 + wire [3:0] ld_byte_hit_hi; + wire [3:0] ld_byte_rhit_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:172:4 + wire [31:0] ld_fwddata_rpipe_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:173:4 + wire [31:0] ld_fwddata_rpipe_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:175:4 + wire [3:0] ld_byte_hit_buf_lo; + wire [3:0] ld_byte_hit_buf_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:176:4 + wire [31:0] ld_fwddata_buf_lo; + wire [31:0] ld_fwddata_buf_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:178:4 + wire [63:0] ld_fwddata_lo; + wire [63:0] ld_fwddata_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:179:4 + wire [63:0] ld_fwddata_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:181:4 + reg ld_full_hit_hi_m; + reg ld_full_hit_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:182:4 + wire ld_full_hit_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:184:4 + assign ldst_byteen_m[3:0] = (({4 {lsu_pkt_m[11]}} & 4'b0001) | ({4 {lsu_pkt_m[10]}} & 4'b0011)) | ({4 {lsu_pkt_m[9]}} & 4'b1111); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:189:4 + el2_lsu_bus_buffer #(.pt(pt)) bus_buffer( + .clk(clk), + .clk_override(clk_override), + .rst_l(rst_l), + .scan_mode(scan_mode), + .dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable), + .dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable), + .dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable), + .dec_tlu_force_halt(dec_tlu_force_halt), + .lsu_bus_obuf_c1_clken(lsu_bus_obuf_c1_clken), + .lsu_busm_clken(lsu_busm_clken), + .lsu_c2_r_clk(lsu_c2_r_clk), + .lsu_bus_ibuf_c1_clk(lsu_bus_ibuf_c1_clk), + .lsu_bus_obuf_c1_clk(lsu_bus_obuf_c1_clk), + .lsu_bus_buf_c1_clk(lsu_bus_buf_c1_clk), + .lsu_free_c2_clk(lsu_free_c2_clk), + .lsu_busm_clk(lsu_busm_clk), + .dec_lsu_valid_raw_d(dec_lsu_valid_raw_d), + .lsu_pkt_m(lsu_pkt_m), + .lsu_pkt_r(lsu_pkt_r), + .lsu_addr_m(lsu_addr_m), + .end_addr_m(end_addr_m), + .lsu_addr_r(lsu_addr_r), + .end_addr_r(end_addr_r), + .store_data_r(store_data_r), + .no_word_merge_r(no_word_merge_r), + .no_dword_merge_r(no_dword_merge_r), + .lsu_busreq_m(lsu_busreq_m), + .lsu_busreq_r(lsu_busreq_r), + .ld_full_hit_m(ld_full_hit_m), + .flush_m_up(flush_m_up), + .flush_r(flush_r), + .lsu_commit_r(lsu_commit_r), + .is_sideeffects_r(is_sideeffects_r), + .ldst_dual_d(ldst_dual_d), + .ldst_dual_m(ldst_dual_m), + .ldst_dual_r(ldst_dual_r), + .ldst_byteen_ext_m(ldst_byteen_ext_m), + .lsu_bus_buffer_pend_any(lsu_bus_buffer_pend_any), + .lsu_bus_buffer_full_any(lsu_bus_buffer_full_any), + .lsu_bus_buffer_empty_any(lsu_bus_buffer_empty_any), + .ld_byte_hit_buf_lo(ld_byte_hit_buf_lo), + .ld_byte_hit_buf_hi(ld_byte_hit_buf_hi), + .ld_fwddata_buf_lo(ld_fwddata_buf_lo), + .ld_fwddata_buf_hi(ld_fwddata_buf_hi), + .lsu_imprecise_error_load_any(lsu_imprecise_error_load_any), + .lsu_imprecise_error_store_any(lsu_imprecise_error_store_any), + .lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any), + .lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m), + .lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m), + .lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r), + .lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r), + .lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid), + .lsu_nonblock_load_data_error(lsu_nonblock_load_data_error), + .lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag), + .lsu_nonblock_load_data(lsu_nonblock_load_data), + .lsu_pmu_bus_trxn(lsu_pmu_bus_trxn), + .lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned), + .lsu_pmu_bus_error(lsu_pmu_bus_error), + .lsu_pmu_bus_busy(lsu_pmu_bus_busy), + .lsu_axi_awvalid(lsu_axi_awvalid), + .lsu_axi_awready(lsu_axi_awready), + .lsu_axi_awid(lsu_axi_awid), + .lsu_axi_awaddr(lsu_axi_awaddr), + .lsu_axi_awregion(lsu_axi_awregion), + .lsu_axi_awlen(lsu_axi_awlen), + .lsu_axi_awsize(lsu_axi_awsize), + .lsu_axi_awburst(lsu_axi_awburst), + .lsu_axi_awlock(lsu_axi_awlock), + .lsu_axi_awcache(lsu_axi_awcache), + .lsu_axi_awprot(lsu_axi_awprot), + .lsu_axi_awqos(lsu_axi_awqos), + .lsu_axi_wvalid(lsu_axi_wvalid), + .lsu_axi_wready(lsu_axi_wready), + .lsu_axi_wdata(lsu_axi_wdata), + .lsu_axi_wstrb(lsu_axi_wstrb), + .lsu_axi_wlast(lsu_axi_wlast), + .lsu_axi_bvalid(lsu_axi_bvalid), + .lsu_axi_bready(lsu_axi_bready), + .lsu_axi_bresp(lsu_axi_bresp), + .lsu_axi_bid(lsu_axi_bid), + .lsu_axi_arvalid(lsu_axi_arvalid), + .lsu_axi_arready(lsu_axi_arready), + .lsu_axi_arid(lsu_axi_arid), + .lsu_axi_araddr(lsu_axi_araddr), + .lsu_axi_arregion(lsu_axi_arregion), + .lsu_axi_arlen(lsu_axi_arlen), + .lsu_axi_arsize(lsu_axi_arsize), + .lsu_axi_arburst(lsu_axi_arburst), + .lsu_axi_arlock(lsu_axi_arlock), + .lsu_axi_arcache(lsu_axi_arcache), + .lsu_axi_arprot(lsu_axi_arprot), + .lsu_axi_arqos(lsu_axi_arqos), + .lsu_axi_rvalid(lsu_axi_rvalid), + .lsu_axi_rready(lsu_axi_rready), + .lsu_axi_rid(lsu_axi_rid), + .lsu_axi_rdata(lsu_axi_rdata), + .lsu_axi_rresp(lsu_axi_rresp), + .lsu_bus_clk_en(lsu_bus_clk_en), + .lsu_bus_clk_en_q(lsu_bus_clk_en_q) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:194:4 + assign addr_match_dw_lo_r_m = lsu_addr_r[31:3] == lsu_addr_m[31:3]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:195:4 + assign addr_match_word_lo_r_m = addr_match_dw_lo_r_m & ~(lsu_addr_r[2] ^ lsu_addr_m[2]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:197:4 + assign no_word_merge_r = ((lsu_busreq_r & ~ldst_dual_r) & lsu_busreq_m) & (lsu_pkt_m[7] | ~addr_match_word_lo_r_m); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:198:4 + assign no_dword_merge_r = ((lsu_busreq_r & ~ldst_dual_r) & lsu_busreq_m) & (lsu_pkt_m[7] | ~addr_match_dw_lo_r_m); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:201:4 + assign ldst_byteen_ext_m[7:0] = {4'b0000, ldst_byteen_m[3:0]} << lsu_addr_m[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:202:4 + assign ldst_byteen_ext_r[7:0] = {4'b0000, ldst_byteen_r[3:0]} << lsu_addr_r[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:204:4 + assign store_data_ext_r[63:0] = {32'b00000000000000000000000000000000, store_data_r[31:0]} << {lsu_addr_r[1:0], 3'b000}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:206:4 + assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:207:4 + assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:208:4 + assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:209:4 + assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:211:4 + assign store_data_hi_r[31:0] = store_data_ext_r[63:32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:212:4 + assign store_data_lo_r[31:0] = store_data_ext_r[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:214:4 + assign ld_addr_rhit_lo_lo = ((((lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m) & lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:215:4 + assign ld_addr_rhit_lo_hi = ((((end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m) & lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:216:4 + assign ld_addr_rhit_hi_lo = ((((lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m) & lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:217:4 + assign ld_addr_rhit_hi_hi = ((((end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r[0]) & lsu_pkt_r[6]) & lsu_busreq_m) & lsu_busreq_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:219:4 + genvar _gv_i_49; + generate + for (_gv_i_49 = 0; _gv_i_49 < 4; _gv_i_49 = _gv_i_49 + 1) begin : GenBusBufFwd + localparam i = _gv_i_49; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:220:7 + assign ld_byte_rhit_lo_lo[i] = (ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i]) & ldst_byteen_lo_m[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:221:7 + assign ld_byte_rhit_lo_hi[i] = (ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i]) & ldst_byteen_hi_m[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:222:7 + assign ld_byte_rhit_hi_lo[i] = (ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i]) & ldst_byteen_lo_m[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:223:7 + assign ld_byte_rhit_hi_hi[i] = (ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i]) & ldst_byteen_hi_m[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:225:7 + assign ld_byte_hit_lo[i] = (ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i]) | ld_byte_hit_buf_lo[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:228:7 + assign ld_byte_hit_hi[i] = (ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i]) | ld_byte_hit_buf_hi[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:231:7 + assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:232:7 + assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:234:7 + assign ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:237:7 + assign ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] = ({8 {ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8 * i) + 7:8 * i]) | ({8 {ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8 * i) + 7:8 * i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:241:7 + assign ld_fwddata_lo[(8 * i) + 7:8 * i] = (ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8 * i) + 7:8 * i] : ld_fwddata_buf_lo[(8 * i) + 7:8 * i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:243:7 + assign ld_fwddata_hi[(8 * i) + 7:8 * i] = (ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8 * i) + 7:8 * i] : ld_fwddata_buf_hi[(8 * i) + 7:8 * i]); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:247:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:248:7 + ld_full_hit_lo_m = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:249:7 + ld_full_hit_hi_m = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:250:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:250:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:250:12 + for (i = 0; i < 4; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:251:10 + ld_full_hit_lo_m = ld_full_hit_lo_m & (ld_byte_hit_lo[i] | ~ldst_byteen_lo_m[i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:252:10 + ld_full_hit_hi_m = ld_full_hit_hi_m & (ld_byte_hit_hi[i] | ~ldst_byteen_hi_m[i]); + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:257:4 + assign ld_full_hit_m = (((ld_full_hit_lo_m & ld_full_hit_hi_m) & lsu_busreq_m) & lsu_pkt_m[7]) & ~is_sideeffects_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:259:4 + assign ld_fwddata_m[63:0] = {ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8 * lsu_addr_m[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:260:4 + assign bus_read_data_m[31:0] = ld_fwddata_m[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:264:4 + rvdff #(.WIDTH(1)) clken_ff( + .din(lsu_bus_clk_en), + .dout(lsu_bus_clk_en_q), + .clk(active_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:266:4 + rvdff #(.WIDTH(1)) is_sideeffects_rff( + .din(is_sideeffects_m), + .dout(is_sideeffects_r), + .clk(lsu_c1_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_bus_intf.sv:268:4 + rvdff #(.WIDTH(4)) lsu_byten_rff( + .rst_l(rst_l), + .din(ldst_byteen_m[3:0]), + .dout(ldst_byteen_r[3:0]), + .clk(lsu_c1_r_clk) + ); + initial _sv2v_0 = 0; +endmodule +module el2_lsu_ecc ( + clk, + lsu_c2_r_clk, + clk_override, + rst_l, + scan_mode, + lsu_pkt_m, + lsu_pkt_r, + stbuf_data_any, + dec_tlu_core_ecc_disable, + lsu_dccm_rden_r, + addr_in_dccm_r, + lsu_addr_r, + end_addr_r, + dccm_rdata_hi_r, + dccm_rdata_lo_r, + dccm_data_ecc_hi_r, + dccm_data_ecc_lo_r, + sec_data_hi_r, + sec_data_lo_r, + sec_data_hi_r_ff, + sec_data_lo_r_ff, + ld_single_ecc_error_r, + ld_single_ecc_error_r_ff, + lsu_dccm_rden_m, + addr_in_dccm_m, + lsu_addr_m, + end_addr_m, + dccm_rdata_hi_m, + dccm_rdata_lo_m, + dccm_data_ecc_hi_m, + dccm_data_ecc_lo_m, + sec_data_hi_m, + sec_data_lo_m, + dma_dccm_wen, + dma_dccm_wdata_lo, + dma_dccm_wdata_hi, + dma_dccm_wdata_ecc_hi, + dma_dccm_wdata_ecc_lo, + stbuf_ecc_any, + sec_data_ecc_hi_r_ff, + sec_data_ecc_lo_r_ff, + single_ecc_error_hi_r, + single_ecc_error_lo_r, + lsu_single_ecc_error_r, + lsu_double_ecc_error_r, + lsu_single_ecc_error_m, + lsu_double_ecc_error_m +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:34:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:35:4 + input wire lsu_c2_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:36:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:37:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:38:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:40:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:41:4 + input wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:42:4 + input wire [pt[1382-:10] - 1:0] stbuf_data_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:44:4 + input wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:46:4 + input wire lsu_dccm_rden_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:47:4 + input wire addr_in_dccm_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:48:4 + input wire [pt[1398-:9] - 1:0] lsu_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:49:4 + input wire [pt[1398-:9] - 1:0] end_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:50:4 + input wire [pt[1382-:10] - 1:0] dccm_rdata_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:51:4 + input wire [pt[1382-:10] - 1:0] dccm_rdata_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:52:4 + input wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:53:4 + input wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:54:4 + output wire [pt[1382-:10] - 1:0] sec_data_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:55:4 + output wire [pt[1382-:10] - 1:0] sec_data_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:56:4 + output wire [pt[1382-:10] - 1:0] sec_data_hi_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:57:4 + output wire [pt[1382-:10] - 1:0] sec_data_lo_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:59:4 + input wire ld_single_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:60:4 + input wire ld_single_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:61:4 + input wire lsu_dccm_rden_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:62:4 + input wire addr_in_dccm_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:63:4 + input wire [pt[1398-:9] - 1:0] lsu_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:64:4 + input wire [pt[1398-:9] - 1:0] end_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:65:4 + input wire [pt[1382-:10] - 1:0] dccm_rdata_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:66:4 + input wire [pt[1382-:10] - 1:0] dccm_rdata_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:67:4 + input wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:68:4 + input wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:69:4 + output wire [pt[1382-:10] - 1:0] sec_data_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:70:4 + output wire [pt[1382-:10] - 1:0] sec_data_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:72:4 + input wire dma_dccm_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:73:4 + input wire [31:0] dma_dccm_wdata_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:74:4 + input wire [31:0] dma_dccm_wdata_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:75:4 + output wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:76:4 + output wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:78:4 + output wire [pt[1372-:7] - 1:0] stbuf_ecc_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:79:4 + output wire [pt[1372-:7] - 1:0] sec_data_ecc_hi_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:80:4 + output wire [pt[1372-:7] - 1:0] sec_data_ecc_lo_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:82:4 + output wire single_ecc_error_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:83:4 + output wire single_ecc_error_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:84:4 + output wire lsu_single_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:85:4 + output wire lsu_double_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:87:4 + output wire lsu_single_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:88:4 + output wire lsu_double_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:92:4 + wire is_ldst_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:93:4 + wire is_ldst_hi_any; + wire is_ldst_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:94:4 + wire [pt[1382-:10] - 1:0] dccm_wdata_hi_any; + wire [pt[1382-:10] - 1:0] dccm_wdata_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:95:4 + wire [pt[1372-:7] - 1:0] dccm_wdata_ecc_hi_any; + wire [pt[1372-:7] - 1:0] dccm_wdata_ecc_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:96:4 + wire [pt[1382-:10] - 1:0] dccm_rdata_hi_any; + wire [pt[1382-:10] - 1:0] dccm_rdata_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:97:4 + wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_any; + wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:98:4 + wire [pt[1382-:10] - 1:0] sec_data_hi_any; + wire [pt[1382-:10] - 1:0] sec_data_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:99:4 + wire single_ecc_error_hi_any; + wire single_ecc_error_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:100:4 + wire double_ecc_error_hi_any; + wire double_ecc_error_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:102:4 + wire double_ecc_error_hi_m; + wire double_ecc_error_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:103:4 + wire double_ecc_error_hi_r; + wire double_ecc_error_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:105:4 + wire [6:0] ecc_out_hi_nc; + wire [6:0] ecc_out_lo_nc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:108:4 + generate + if (pt[202-:5] == 1) begin : L2U_Plus1_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:109:7 + wire ldst_dual_m; + wire ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:110:7 + wire is_ldst_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:111:7 + wire is_ldst_hi_r; + wire is_ldst_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:113:7 + assign ldst_dual_r = lsu_addr_r[2] != end_addr_r[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:114:7 + assign is_ldst_r = ((lsu_pkt_r[0] & (lsu_pkt_r[7] | lsu_pkt_r[6])) & addr_in_dccm_r) & lsu_dccm_rden_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:115:7 + assign is_ldst_lo_r = is_ldst_r & ~dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:116:7 + assign is_ldst_hi_r = (is_ldst_r & ldst_dual_r) & ~dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:118:7 + assign is_ldst_hi_any = is_ldst_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:119:7 + assign dccm_rdata_hi_any[pt[1382-:10] - 1:0] = dccm_rdata_hi_r[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:120:7 + assign dccm_data_ecc_hi_any[pt[1372-:7] - 1:0] = dccm_data_ecc_hi_r[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:121:7 + assign is_ldst_lo_any = is_ldst_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:122:7 + assign dccm_rdata_lo_any[pt[1382-:10] - 1:0] = dccm_rdata_lo_r[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:123:7 + assign dccm_data_ecc_lo_any[pt[1372-:7] - 1:0] = dccm_data_ecc_lo_r[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:125:7 + assign sec_data_hi_r[pt[1382-:10] - 1:0] = sec_data_hi_any[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:126:7 + assign single_ecc_error_hi_r = single_ecc_error_hi_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:127:7 + assign double_ecc_error_hi_r = double_ecc_error_hi_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:128:7 + assign sec_data_lo_r[pt[1382-:10] - 1:0] = sec_data_lo_any[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:129:7 + assign single_ecc_error_lo_r = single_ecc_error_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:130:7 + assign double_ecc_error_lo_r = double_ecc_error_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:132:7 + assign lsu_single_ecc_error_r = single_ecc_error_hi_r | single_ecc_error_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:133:7 + assign lsu_double_ecc_error_r = double_ecc_error_hi_r | double_ecc_error_lo_r; + end + else begin : L2U_Plus1_0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:137:7 + wire ldst_dual_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:138:7 + wire is_ldst_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:139:7 + wire is_ldst_hi_m; + wire is_ldst_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:141:7 + assign ldst_dual_m = lsu_addr_m[2] != end_addr_m[2]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:142:7 + assign is_ldst_m = ((lsu_pkt_m[0] & (lsu_pkt_m[7] | lsu_pkt_m[6])) & addr_in_dccm_m) & lsu_dccm_rden_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:143:7 + assign is_ldst_lo_m = is_ldst_m & ~dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:144:7 + assign is_ldst_hi_m = (is_ldst_m & (ldst_dual_m | lsu_pkt_m[4])) & ~dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:146:7 + assign is_ldst_hi_any = is_ldst_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:147:7 + assign dccm_rdata_hi_any[pt[1382-:10] - 1:0] = dccm_rdata_hi_m[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:148:7 + assign dccm_data_ecc_hi_any[pt[1372-:7] - 1:0] = dccm_data_ecc_hi_m[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:149:7 + assign is_ldst_lo_any = is_ldst_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:150:7 + assign dccm_rdata_lo_any[pt[1382-:10] - 1:0] = dccm_rdata_lo_m[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:151:7 + assign dccm_data_ecc_lo_any[pt[1372-:7] - 1:0] = dccm_data_ecc_lo_m[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:153:7 + assign sec_data_hi_m[pt[1382-:10] - 1:0] = sec_data_hi_any[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:154:7 + assign double_ecc_error_hi_m = double_ecc_error_hi_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:155:7 + assign sec_data_lo_m[pt[1382-:10] - 1:0] = sec_data_lo_any[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:156:7 + assign double_ecc_error_lo_m = double_ecc_error_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:158:7 + assign lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:159:7 + assign lsu_double_ecc_error_m = double_ecc_error_hi_m | double_ecc_error_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:162:7 + rvdff #(.WIDTH(1)) lsu_single_ecc_err_r( + .din(lsu_single_ecc_error_m), + .dout(lsu_single_ecc_error_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:163:7 + rvdff #(.WIDTH(1)) lsu_double_ecc_err_r( + .din(lsu_double_ecc_error_m), + .dout(lsu_double_ecc_error_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:164:7 + rvdff #(.WIDTH(1)) ldst_sec_lo_rff( + .din(single_ecc_error_lo_any), + .dout(single_ecc_error_lo_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:165:7 + rvdff #(.WIDTH(1)) ldst_sec_hi_rff( + .din(single_ecc_error_hi_any), + .dout(single_ecc_error_hi_r), + .clk(lsu_c2_r_clk), + .rst_l(rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:166:7 + rvdffe #(.WIDTH(pt[1382-:10])) sec_data_hi_rff( + .din(sec_data_hi_m[pt[1382-:10] - 1:0]), + .dout(sec_data_hi_r[pt[1382-:10] - 1:0]), + .en(lsu_single_ecc_error_m | clk_override), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:167:7 + rvdffe #(.WIDTH(pt[1382-:10])) sec_data_lo_rff( + .din(sec_data_lo_m[pt[1382-:10] - 1:0]), + .dout(sec_data_lo_r[pt[1382-:10] - 1:0]), + .en(lsu_single_ecc_error_m | clk_override), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:172:4 + assign dccm_wdata_lo_any[pt[1382-:10] - 1:0] = (ld_single_ecc_error_r_ff ? sec_data_lo_r_ff[pt[1382-:10] - 1:0] : (dma_dccm_wen ? dma_dccm_wdata_lo[pt[1382-:10] - 1:0] : stbuf_data_any[pt[1382-:10] - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:173:4 + assign dccm_wdata_hi_any[pt[1382-:10] - 1:0] = (ld_single_ecc_error_r_ff ? sec_data_hi_r_ff[pt[1382-:10] - 1:0] : (dma_dccm_wen ? dma_dccm_wdata_hi[pt[1382-:10] - 1:0] : 32'h00000000)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:175:4 + assign sec_data_ecc_hi_r_ff[pt[1372-:7] - 1:0] = dccm_wdata_ecc_hi_any[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:176:4 + assign sec_data_ecc_lo_r_ff[pt[1372-:7] - 1:0] = dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:177:4 + assign stbuf_ecc_any[pt[1372-:7] - 1:0] = dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:178:4 + assign dma_dccm_wdata_ecc_hi[pt[1372-:7] - 1:0] = dccm_wdata_ecc_hi_any[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:179:4 + assign dma_dccm_wdata_ecc_lo[pt[1372-:7] - 1:0] = dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:182:4 + generate + if (pt[1365-:5] == 1) begin : Gen_dccm_enable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:185:7 + rvecc_decode lsu_ecc_decode_hi( + .en(is_ldst_hi_any), + .sed_ded(1'b0), + .din(dccm_rdata_hi_any[pt[1382-:10] - 1:0]), + .ecc_in(dccm_data_ecc_hi_any[pt[1372-:7] - 1:0]), + .dout(sec_data_hi_any[pt[1382-:10] - 1:0]), + .ecc_out(ecc_out_hi_nc[6:0]), + .single_ecc_error(single_ecc_error_hi_any), + .double_ecc_error(double_ecc_error_hi_any) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:200:7 + rvecc_decode lsu_ecc_decode_lo( + .en(is_ldst_lo_any), + .sed_ded(1'b0), + .din(dccm_rdata_lo_any[pt[1382-:10] - 1:0]), + .ecc_in(dccm_data_ecc_lo_any[pt[1372-:7] - 1:0]), + .dout(sec_data_lo_any[pt[1382-:10] - 1:0]), + .ecc_out(ecc_out_lo_nc[6:0]), + .single_ecc_error(single_ecc_error_lo_any), + .double_ecc_error(double_ecc_error_lo_any) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:214:7 + rvecc_encode lsu_ecc_encode_hi( + .din(dccm_wdata_hi_any[pt[1382-:10] - 1:0]), + .ecc_out(dccm_wdata_ecc_hi_any[pt[1372-:7] - 1:0]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:221:7 + rvecc_encode lsu_ecc_encode_lo( + .din(dccm_wdata_lo_any[pt[1382-:10] - 1:0]), + .ecc_out(dccm_wdata_ecc_lo_any[pt[1372-:7] - 1:0]) + ); + end + else begin : Gen_dccm_disable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:229:7 + assign sec_data_hi_any[pt[1382-:10] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:230:7 + assign sec_data_lo_any[pt[1382-:10] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:231:7 + assign single_ecc_error_hi_any = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:232:7 + assign double_ecc_error_hi_any = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:233:7 + assign single_ecc_error_lo_any = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:234:7 + assign double_ecc_error_lo_any = 1'sb0; + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:237:4 + rvdffe #(.WIDTH(pt[1382-:10])) sec_data_hi_rplus1ff( + .din(sec_data_hi_r[pt[1382-:10] - 1:0]), + .dout(sec_data_hi_r_ff[pt[1382-:10] - 1:0]), + .en(ld_single_ecc_error_r | clk_override), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_ecc.sv:238:4 + rvdffe #(.WIDTH(pt[1382-:10])) sec_data_lo_rplus1ff( + .din(sec_data_lo_r[pt[1382-:10] - 1:0]), + .dout(sec_data_lo_r_ff[pt[1382-:10] - 1:0]), + .en(ld_single_ecc_error_r | clk_override), + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode) + ); +endmodule +module el2_lsu_dccm_mem ( + clk, + active_clk, + rst_l, + clk_override, + dccm_wren, + dccm_rden, + dccm_wr_addr_lo, + dccm_wr_addr_hi, + dccm_rd_addr_lo, + dccm_rd_addr_hi, + dccm_wr_data_lo, + dccm_wr_data_hi, + dccm_ext_in_pkt, + dccm_rd_data_lo, + dccm_rd_data_hi, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:47:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:48:4 + input wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:49:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:50:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:52:4 + input wire dccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:53:4 + input wire dccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:54:4 + input wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:55:4 + input wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:56:4 + input wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:57:4 + input wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:58:4 + input wire [pt[1360-:10] - 1:0] dccm_wr_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:59:4 + input wire [pt[1360-:10] - 1:0] dccm_wr_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:60:4 + // removed localparam type el2_pkg_el2_dccm_ext_in_pkt_t + input wire [(pt[1342-:9] * 12) - 1:0] dccm_ext_in_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:62:4 + output wire [pt[1360-:10] - 1:0] dccm_rd_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:63:4 + output wire [pt[1360-:10] - 1:0] dccm_rd_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:65:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:69:4 + localparam DCCM_WIDTH_BITS = $clog2(pt[1389-:7]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:70:4 + localparam DCCM_INDEX_BITS = (pt[1398-:9] - pt[1405-:7]) - pt[1275-:6]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:71:4 + localparam DCCM_INDEX_DEPTH = (pt[1289-:14] * 1024) / (pt[1389-:7] * pt[1342-:9]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:73:4 + wire [pt[1342-:9] - 1:0] wren_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:74:4 + wire [pt[1342-:9] - 1:0] rden_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:75:4 + wire [((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? (pt[1342-:9] * (((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1)) + (pt[1405-:7] + 1) : (pt[1342-:9] * (((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)) + (pt[1398-:9] - 2)):((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1)] addr_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:76:4 + wire [pt[1398-:9] - 1:pt[1405-:7] + DCCM_WIDTH_BITS] rd_addr_even; + wire [pt[1398-:9] - 1:pt[1405-:7] + DCCM_WIDTH_BITS] rd_addr_odd; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:77:4 + wire rd_unaligned; + wire wr_unaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:78:4 + wire [(pt[1342-:9] * pt[1360-:10]) - 1:0] dccm_bank_dout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:79:4 + wire [pt[1360-:10] - 1:0] wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:81:4 + wire [(pt[1342-:9] * pt[1360-:10]) - 1:0] wr_data_bank; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:83:4 + wire [(DCCM_WIDTH_BITS + pt[1405-:7]) - 1:DCCM_WIDTH_BITS] dccm_rd_addr_lo_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:84:4 + wire [(DCCM_WIDTH_BITS + pt[1405-:7]) - 1:DCCM_WIDTH_BITS] dccm_rd_addr_hi_q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:86:4 + wire [pt[1342-:9] - 1:0] dccm_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:88:4 + assign rd_unaligned = dccm_rd_addr_lo[DCCM_WIDTH_BITS+:pt[1405-:7]] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:pt[1405-:7]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:89:4 + assign wr_unaligned = dccm_wr_addr_lo[DCCM_WIDTH_BITS+:pt[1405-:7]] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:pt[1405-:7]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:92:4 + assign dccm_rd_data_lo[pt[1360-:10] - 1:0] = dccm_bank_dout[(dccm_rd_addr_lo_q[pt[1275-:6]+:pt[1405-:7]] * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:93:4 + assign dccm_rd_data_hi[pt[1360-:10] - 1:0] = dccm_bank_dout[(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:pt[1405-:7]] * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:97:4 + genvar _gv_i_50; + generate + for (_gv_i_50 = 0; _gv_i_50 < pt[1342-:9]; _gv_i_50 = _gv_i_50 + 1) begin : mem_bank + localparam i = _gv_i_50; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:98:7 + assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:pt[1405-:7]] == i) | (dccm_wr_addr_lo[2+:pt[1405-:7]] == i)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:99:7 + assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:pt[1405-:7]] == i) | (dccm_rd_addr_lo[2+:pt[1405-:7]] == i)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:100:7 + assign addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)) + ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + DCCM_WIDTH_BITS : (pt[1405-:7] + 2) - ((pt[1405-:7] + DCCM_WIDTH_BITS) - (pt[1398-:9] - 1))) : (((i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)) + ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + DCCM_WIDTH_BITS : (pt[1405-:7] + 2) - ((pt[1405-:7] + DCCM_WIDTH_BITS) - (pt[1398-:9] - 1)))) - DCCM_INDEX_BITS) + 1)+:DCCM_INDEX_BITS] = (wren_bank[i] ? ((dccm_wr_addr_hi[2+:pt[1405-:7]] == i) & wr_unaligned ? dccm_wr_addr_hi[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS] : dccm_wr_addr_lo[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS]) : ((dccm_rd_addr_hi[2+:pt[1405-:7]] == i) & rd_unaligned ? dccm_rd_addr_hi[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS] : dccm_rd_addr_lo[pt[1405-:7] + DCCM_WIDTH_BITS+:DCCM_INDEX_BITS])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:107:7 + assign wr_data_bank[i * pt[1360-:10]+:pt[1360-:10]] = ((dccm_wr_addr_hi[2+:pt[1405-:7]] == i) & wr_unaligned ? dccm_wr_data_hi[pt[1360-:10] - 1:0] : dccm_wr_data_lo[pt[1360-:10] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:110:7 + assign dccm_clken[i] = (wren_bank[i] | rden_bank[i]) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:115:9 + el2_ram #( + .depth(DCCM_INDEX_DEPTH), + .width(39) + ) ram( + .ME(dccm_clken[i]), + .CLK(clk), + .WE(wren_bank[i]), + .ADR(addr_bank[((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? pt[1405-:7] + 2 : pt[1398-:9] - 1) + (i * ((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1))+:((pt[1398-:9] - 1) >= (pt[1405-:7] + 2) ? ((pt[1398-:9] - 1) - (pt[1405-:7] + 2)) + 1 : ((pt[1405-:7] + 2) - (pt[1398-:9] - 1)) + 1)]), + .D(wr_data_bank[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]), + .Q(dccm_bank_dout[(i * pt[1360-:10]) + (pt[1360-:10] - 1)-:pt[1360-:10]]), + .ROP(), + .TEST1(dccm_ext_in_pkt[(i * 12) + 11]), + .RME(dccm_ext_in_pkt[(i * 12) + 10]), + .RM(dccm_ext_in_pkt[(i * 12) + 9-:4]), + .LS(dccm_ext_in_pkt[(i * 12) + 5]), + .DS(dccm_ext_in_pkt[(i * 12) + 4]), + .SD(dccm_ext_in_pkt[(i * 12) + 3]), + .TEST_RNM(dccm_ext_in_pkt[(i * 12) + 2]), + .BC1(dccm_ext_in_pkt[(i * 12) + 1]), + .BC2(dccm_ext_in_pkt[i * 12]) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:285:4 + rvdff #(.WIDTH(pt[1405-:7])) rd_addr_lo_ff( + .rst_l(rst_l), + .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:pt[1405-:7]]), + .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:pt[1405-:7]]), + .clk(active_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_mem.sv:286:4 + rvdff #(.WIDTH(pt[1405-:7])) rd_addr_hi_ff( + .rst_l(rst_l), + .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:pt[1405-:7]]), + .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:pt[1405-:7]]), + .clk(active_clk) + ); +endmodule +module el2_lsu_dccm_ctl ( + lsu_c2_m_clk, + lsu_c2_r_clk, + lsu_c1_r_clk, + lsu_store_c1_r_clk, + lsu_free_c2_clk, + clk_override, + clk, + rst_l, + lsu_pkt_r, + lsu_pkt_m, + lsu_pkt_d, + addr_in_dccm_d, + addr_in_pic_d, + addr_in_pic_m, + addr_in_dccm_m, + addr_in_dccm_r, + addr_in_pic_r, + lsu_raw_fwd_lo_r, + lsu_raw_fwd_hi_r, + lsu_commit_r, + ldst_dual_m, + ldst_dual_r, + lsu_addr_d, + lsu_addr_m, + lsu_addr_r, + end_addr_d, + end_addr_m, + end_addr_r, + stbuf_reqvld_any, + stbuf_addr_any, + stbuf_data_any, + stbuf_ecc_any, + stbuf_fwddata_hi_m, + stbuf_fwddata_lo_m, + stbuf_fwdbyteen_hi_m, + stbuf_fwdbyteen_lo_m, + dccm_rdata_hi_r, + dccm_rdata_lo_r, + dccm_data_ecc_hi_r, + dccm_data_ecc_lo_r, + lsu_ld_data_r, + lsu_ld_data_corr_r, + lsu_double_ecc_error_r, + single_ecc_error_hi_r, + single_ecc_error_lo_r, + sec_data_hi_r, + sec_data_lo_r, + sec_data_hi_r_ff, + sec_data_lo_r_ff, + sec_data_ecc_hi_r_ff, + sec_data_ecc_lo_r_ff, + dccm_rdata_hi_m, + dccm_rdata_lo_m, + dccm_data_ecc_hi_m, + dccm_data_ecc_lo_m, + lsu_ld_data_m, + lsu_double_ecc_error_m, + sec_data_hi_m, + sec_data_lo_m, + store_data_m, + dma_dccm_wen, + dma_pic_wen, + dma_mem_tag_m, + dma_mem_addr, + dma_mem_wdata, + dma_dccm_wdata_lo, + dma_dccm_wdata_hi, + dma_dccm_wdata_ecc_hi, + dma_dccm_wdata_ecc_lo, + store_data_hi_r, + store_data_lo_r, + store_datafn_hi_r, + store_datafn_lo_r, + store_data_r, + ld_single_ecc_error_r, + ld_single_ecc_error_r_ff, + picm_mask_data_m, + lsu_stbuf_commit_any, + lsu_dccm_rden_m, + lsu_dccm_rden_r, + dccm_dma_rvalid, + dccm_dma_ecc_error, + dccm_dma_rtag, + dccm_dma_rdata, + dccm_wren, + dccm_rden, + dccm_wr_addr_lo, + dccm_wr_addr_hi, + dccm_rd_addr_lo, + dccm_rd_addr_hi, + dccm_wr_data_lo, + dccm_wr_data_hi, + dccm_rd_data_lo, + dccm_rd_data_hi, + picm_wren, + picm_rden, + picm_mken, + picm_rdaddr, + picm_wraddr, + picm_wr_data, + picm_rd_data, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:35:4 + input wire lsu_c2_m_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:36:4 + input wire lsu_c2_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:37:4 + input wire lsu_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:38:4 + input wire lsu_store_c1_r_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:39:4 + input wire lsu_free_c2_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:40:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:41:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:43:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:45:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:46:4 + input wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:47:4 + input wire [13:0] lsu_pkt_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:48:4 + input wire addr_in_dccm_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:49:4 + input wire addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:50:4 + input wire addr_in_pic_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:51:4 + input wire addr_in_dccm_m; + input wire addr_in_dccm_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:52:4 + input wire addr_in_pic_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:53:4 + input wire lsu_raw_fwd_lo_r; + input wire lsu_raw_fwd_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:54:4 + input wire lsu_commit_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:55:4 + input wire ldst_dual_m; + input wire ldst_dual_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:58:4 + input wire [31:0] lsu_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:59:4 + input wire [pt[1398-:9] - 1:0] lsu_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:60:4 + input wire [31:0] lsu_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:63:4 + input wire [pt[1398-:9] - 1:0] end_addr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:64:4 + input wire [pt[1398-:9] - 1:0] end_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:65:4 + input wire [pt[1398-:9] - 1:0] end_addr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:68:4 + input wire stbuf_reqvld_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:69:4 + input wire [pt[157-:9] - 1:0] stbuf_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:71:4 + input wire [pt[1382-:10] - 1:0] stbuf_data_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:72:4 + input wire [pt[1372-:7] - 1:0] stbuf_ecc_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:73:4 + input wire [pt[1382-:10] - 1:0] stbuf_fwddata_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:74:4 + input wire [pt[1382-:10] - 1:0] stbuf_fwddata_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:75:4 + input wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:76:4 + input wire [pt[1389-:7] - 1:0] stbuf_fwdbyteen_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:78:4 + output wire [pt[1382-:10] - 1:0] dccm_rdata_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:79:4 + output wire [pt[1382-:10] - 1:0] dccm_rdata_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:80:4 + output wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:81:4 + output wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:82:4 + output wire [pt[1382-:10] - 1:0] lsu_ld_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:83:4 + output wire [pt[1382-:10] - 1:0] lsu_ld_data_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:85:4 + input wire lsu_double_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:86:4 + input wire single_ecc_error_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:87:4 + input wire single_ecc_error_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:88:4 + input wire [pt[1382-:10] - 1:0] sec_data_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:89:4 + input wire [pt[1382-:10] - 1:0] sec_data_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:90:4 + input wire [pt[1382-:10] - 1:0] sec_data_hi_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:91:4 + input wire [pt[1382-:10] - 1:0] sec_data_lo_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:92:4 + input wire [pt[1372-:7] - 1:0] sec_data_ecc_hi_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:93:4 + input wire [pt[1372-:7] - 1:0] sec_data_ecc_lo_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:95:4 + output wire [pt[1382-:10] - 1:0] dccm_rdata_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:96:4 + output wire [pt[1382-:10] - 1:0] dccm_rdata_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:97:4 + output wire [pt[1372-:7] - 1:0] dccm_data_ecc_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:98:4 + output wire [pt[1372-:7] - 1:0] dccm_data_ecc_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:99:4 + output wire [pt[1382-:10] - 1:0] lsu_ld_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:101:4 + input wire lsu_double_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:102:4 + input wire [pt[1382-:10] - 1:0] sec_data_hi_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:103:4 + input wire [pt[1382-:10] - 1:0] sec_data_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:105:4 + input wire [31:0] store_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:106:4 + input wire dma_dccm_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:107:4 + input wire dma_pic_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:108:4 + input wire [2:0] dma_mem_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:109:4 + input wire [31:0] dma_mem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:110:4 + input wire [63:0] dma_mem_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:111:4 + input wire [31:0] dma_dccm_wdata_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:112:4 + input wire [31:0] dma_dccm_wdata_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:113:4 + input wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:114:4 + input wire [pt[1372-:7] - 1:0] dma_dccm_wdata_ecc_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:116:4 + output wire [pt[1382-:10] - 1:0] store_data_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:117:4 + output wire [pt[1382-:10] - 1:0] store_data_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:118:4 + output wire [pt[1382-:10] - 1:0] store_datafn_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:119:4 + output wire [pt[1382-:10] - 1:0] store_datafn_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:120:4 + output wire [31:0] store_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:121:4 + output wire ld_single_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:122:4 + output wire ld_single_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:124:4 + output wire [31:0] picm_mask_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:125:4 + output wire lsu_stbuf_commit_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:126:4 + output wire lsu_dccm_rden_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:127:4 + output wire lsu_dccm_rden_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:129:4 + output wire dccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:130:4 + output wire dccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:131:4 + output wire [2:0] dccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:132:4 + output wire [63:0] dccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:135:4 + output wire dccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:136:4 + output wire dccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:137:4 + output wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:138:4 + output wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:139:4 + output wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:140:4 + output wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:141:4 + output wire [pt[1360-:10] - 1:0] dccm_wr_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:142:4 + output wire [pt[1360-:10] - 1:0] dccm_wr_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:144:4 + input wire [pt[1360-:10] - 1:0] dccm_rd_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:145:4 + input wire [pt[1360-:10] - 1:0] dccm_rd_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:148:4 + output wire picm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:149:4 + output wire picm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:150:4 + output wire picm_mken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:151:4 + output wire [31:0] picm_rdaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:152:4 + output wire [31:0] picm_wraddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:153:4 + output wire [31:0] picm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:154:4 + input wire [31:0] picm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:156:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:160:4 + localparam DCCM_WIDTH_BITS = $clog2(pt[1389-:7]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:162:4 + wire lsu_dccm_rden_d; + wire lsu_dccm_wren_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:163:4 + wire ld_single_ecc_error_lo_r; + wire ld_single_ecc_error_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:164:4 + wire ld_single_ecc_error_lo_r_ns; + wire ld_single_ecc_error_hi_r_ns; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:165:4 + wire ld_single_ecc_error_lo_r_ff; + wire ld_single_ecc_error_hi_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:166:4 + wire lsu_double_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:167:4 + wire [pt[1398-:9] - 1:0] ld_sec_addr_lo_r_ff; + wire [pt[1398-:9] - 1:0] ld_sec_addr_hi_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:168:4 + wire [pt[1382-:10] - 1:0] store_data_lo_r_in; + wire [pt[1382-:10] - 1:0] store_data_hi_r_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:169:4 + wire [63:0] picm_rd_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:171:4 + wire dccm_wr_bypass_d_m_hi; + wire dccm_wr_bypass_d_r_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:172:4 + wire dccm_wr_bypass_d_m_lo; + wire dccm_wr_bypass_d_r_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:173:4 + wire kill_ecc_corr_lo_r; + wire kill_ecc_corr_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:176:4 + wire [3:0] store_byteen_m; + wire [3:0] store_byteen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:177:4 + wire [7:0] store_byteen_ext_m; + wire [7:0] store_byteen_ext_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:179:4 + generate + if (pt[202-:5] == 1) begin : L2U_Plus1_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:180:7 + wire [63:0] lsu_rdata_r; + wire [63:0] lsu_rdata_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:181:7 + wire [63:0] dccm_rdata_r; + wire [63:0] dccm_rdata_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:182:7 + wire [63:0] stbuf_fwddata_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:183:7 + wire [7:0] stbuf_fwdbyteen_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:184:7 + wire [31:0] stbuf_fwddata_lo_r; + wire [31:0] stbuf_fwddata_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:185:7 + wire [3:0] stbuf_fwdbyteen_lo_r; + wire [3:0] stbuf_fwdbyteen_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:186:7 + wire [31:0] lsu_rdata_lo_r; + wire [31:0] lsu_rdata_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:187:7 + wire [63:0] picm_rd_data_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:188:7 + wire [63:32] lsu_ld_data_r_nc; + wire [63:32] lsu_ld_data_corr_r_nc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:189:7 + wire [2:0] dma_mem_tag_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:190:7 + wire stbuf_fwddata_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:192:7 + assign dccm_dma_rvalid = (lsu_pkt_r[0] & lsu_pkt_r[7]) & lsu_pkt_r[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:193:7 + assign dccm_dma_ecc_error = lsu_double_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:194:7 + assign dccm_dma_rtag[2:0] = dma_mem_tag_r[2:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:195:7 + assign dccm_dma_rdata[63:0] = (ldst_dual_r ? lsu_rdata_corr_r[63:0] : {2 {lsu_rdata_corr_r[31:0]}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:196:7 + assign {lsu_ld_data_r_nc[63:32], lsu_ld_data_r[31:0]} = lsu_rdata_r[63:0] >> (8 * lsu_addr_r[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:197:7 + assign {lsu_ld_data_corr_r_nc[63:32], lsu_ld_data_corr_r[31:0]} = lsu_rdata_corr_r[63:0] >> (8 * lsu_addr_r[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:199:7 + assign picm_rd_data_r[63:32] = picm_rd_data_r[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:200:7 + assign dccm_rdata_r[63:0] = {dccm_rdata_hi_r[31:0], dccm_rdata_lo_r[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:201:7 + assign dccm_rdata_corr_r[63:0] = {sec_data_hi_r[31:0], sec_data_lo_r[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:202:7 + assign stbuf_fwddata_r[63:0] = {stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:203:7 + assign stbuf_fwdbyteen_r[7:0] = {stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:204:7 + assign stbuf_fwddata_en = (|stbuf_fwdbyteen_hi_m[3:0] | (|stbuf_fwdbyteen_lo_m[3:0])) | clk_override; + genvar _gv_i_51; + for (_gv_i_51 = 0; _gv_i_51 < 8; _gv_i_51 = _gv_i_51 + 1) begin : GenDMAData + localparam i = _gv_i_51; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:207:10 + assign lsu_rdata_corr_r[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8 * i) + 7:8 * i] : (addr_in_pic_r ? picm_rd_data_r[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_r}} & dccm_rdata_corr_r[(8 * i) + 7:8 * i])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:210:10 + assign lsu_rdata_r[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_r[i] ? stbuf_fwddata_r[(8 * i) + 7:8 * i] : (addr_in_pic_r ? picm_rd_data_r[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_r}} & dccm_rdata_r[(8 * i) + 7:8 * i])); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:213:7 + rvdffe #(.WIDTH(pt[1382-:10])) dccm_rdata_hi_r_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(dccm_rdata_hi_m[pt[1382-:10] - 1:0]), + .dout(dccm_rdata_hi_r[pt[1382-:10] - 1:0]), + .en((lsu_dccm_rden_m & ldst_dual_m) | clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:214:7 + rvdffe #(.WIDTH(pt[1382-:10])) dccm_rdata_lo_r_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(dccm_rdata_lo_m[pt[1382-:10] - 1:0]), + .dout(dccm_rdata_lo_r[pt[1382-:10] - 1:0]), + .en(lsu_dccm_rden_m | clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:215:7 + rvdffe #(.WIDTH(2 * pt[1372-:7])) dccm_data_ecc_r_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({dccm_data_ecc_hi_m[pt[1372-:7] - 1:0], dccm_data_ecc_lo_m[pt[1372-:7] - 1:0]}), + .dout({dccm_data_ecc_hi_r[pt[1372-:7] - 1:0], dccm_data_ecc_lo_r[pt[1372-:7] - 1:0]}), + .en(lsu_dccm_rden_m | clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:217:7 + rvdff #(.WIDTH(8)) stbuf_fwdbyteen_ff( + .rst_l(rst_l), + .din({stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]}), + .dout({stbuf_fwdbyteen_hi_r[3:0], stbuf_fwdbyteen_lo_r[3:0]}), + .clk(lsu_c2_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:218:7 + rvdffe #(.WIDTH(64)) stbuf_fwddata_ff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din({stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]}), + .dout({stbuf_fwddata_hi_r[31:0], stbuf_fwddata_lo_r[31:0]}), + .en(stbuf_fwddata_en) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:219:7 + rvdffe #(.WIDTH(32)) picm_rddata_rff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(picm_rd_data_m[31:0]), + .dout(picm_rd_data_r[31:0]), + .en(addr_in_pic_m | clk_override) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:220:7 + rvdff #(.WIDTH(3)) dma_mem_tag_rff( + .rst_l(rst_l), + .din(dma_mem_tag_m[2:0]), + .dout(dma_mem_tag_r[2:0]), + .clk(lsu_c1_r_clk) + ); + end + else begin : L2U_Plus1_0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:224:7 + wire [63:0] lsu_rdata_m; + wire [63:0] lsu_rdata_corr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:225:7 + wire [63:0] dccm_rdata_m; + wire [63:0] dccm_rdata_corr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:226:7 + wire [63:0] stbuf_fwddata_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:227:7 + wire [7:0] stbuf_fwdbyteen_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:228:7 + wire [63:32] lsu_ld_data_m_nc; + wire [63:32] lsu_ld_data_corr_m_nc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:229:7 + wire [31:0] lsu_ld_data_corr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:231:7 + assign dccm_dma_rvalid = (lsu_pkt_m[0] & lsu_pkt_m[7]) & lsu_pkt_m[4]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:232:7 + assign dccm_dma_ecc_error = lsu_double_ecc_error_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:233:7 + assign dccm_dma_rtag[2:0] = dma_mem_tag_m[2:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:234:7 + assign dccm_dma_rdata[63:0] = (ldst_dual_m ? lsu_rdata_corr_m[63:0] : {2 {lsu_rdata_corr_m[31:0]}}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:235:7 + assign {lsu_ld_data_m_nc[63:32], lsu_ld_data_m[31:0]} = lsu_rdata_m[63:0] >> (8 * lsu_addr_m[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:236:7 + assign {lsu_ld_data_corr_m_nc[63:32], lsu_ld_data_corr_m[31:0]} = lsu_rdata_corr_m[63:0] >> (8 * lsu_addr_m[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:238:7 + assign dccm_rdata_m[63:0] = {dccm_rdata_hi_m[31:0], dccm_rdata_lo_m[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:239:7 + assign dccm_rdata_corr_m[63:0] = {sec_data_hi_m[31:0], sec_data_lo_m[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:240:7 + assign stbuf_fwddata_m[63:0] = {stbuf_fwddata_hi_m[31:0], stbuf_fwddata_lo_m[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:241:7 + assign stbuf_fwdbyteen_m[7:0] = {stbuf_fwdbyteen_hi_m[3:0], stbuf_fwdbyteen_lo_m[3:0]}; + genvar _gv_i_52; + for (_gv_i_52 = 0; _gv_i_52 < 8; _gv_i_52 = _gv_i_52 + 1) begin : GenLoop + localparam i = _gv_i_52; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:244:10 + assign lsu_rdata_corr_m[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_m[i] ? stbuf_fwddata_m[(8 * i) + 7:8 * i] : (addr_in_pic_m ? picm_rd_data_m[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_m}} & dccm_rdata_corr_m[(8 * i) + 7:8 * i])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:247:10 + assign lsu_rdata_m[(8 * i) + 7:8 * i] = (stbuf_fwdbyteen_m[i] ? stbuf_fwddata_m[(8 * i) + 7:8 * i] : (addr_in_pic_m ? picm_rd_data_m[(8 * i) + 7:8 * i] : {8 {addr_in_dccm_m}} & dccm_rdata_m[(8 * i) + 7:8 * i])); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:251:7 + rvdffe #(.WIDTH(32)) lsu_ld_data_corr_rff( + .clk(clk), + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(lsu_ld_data_corr_m[31:0]), + .dout(lsu_ld_data_corr_r[31:0]), + .en(((lsu_pkt_m[0] & lsu_pkt_m[7]) & (addr_in_pic_m | addr_in_dccm_m)) | clk_override) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:254:4 + assign kill_ecc_corr_lo_r = ((((((lsu_addr_d[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2]) | (end_addr_d[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_d[0]) & lsu_pkt_d[6]) & lsu_pkt_d[4]) & addr_in_dccm_d) | ((((((lsu_addr_m[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2]) | (end_addr_m[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_m[0]) & lsu_pkt_m[6]) & lsu_pkt_m[4]) & addr_in_dccm_m); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:257:4 + assign kill_ecc_corr_hi_r = ((((((lsu_addr_d[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2]) | (end_addr_d[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_d[0]) & lsu_pkt_d[6]) & lsu_pkt_d[4]) & addr_in_dccm_d) | ((((((lsu_addr_m[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2]) | (end_addr_m[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2])) & lsu_pkt_m[0]) & lsu_pkt_m[6]) & lsu_pkt_m[4]) & addr_in_dccm_m); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:260:4 + assign ld_single_ecc_error_lo_r = (lsu_pkt_r[7] & single_ecc_error_lo_r) & ~lsu_raw_fwd_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:261:4 + assign ld_single_ecc_error_hi_r = (lsu_pkt_r[7] & single_ecc_error_hi_r) & ~lsu_raw_fwd_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:262:4 + assign ld_single_ecc_error_r = (ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r) & ~lsu_double_ecc_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:264:4 + assign ld_single_ecc_error_lo_r_ns = (ld_single_ecc_error_lo_r & (lsu_commit_r | lsu_pkt_r[4])) & ~kill_ecc_corr_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:265:4 + assign ld_single_ecc_error_hi_r_ns = (ld_single_ecc_error_hi_r & (lsu_commit_r | lsu_pkt_r[4])) & ~kill_ecc_corr_hi_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:266:4 + assign ld_single_ecc_error_r_ff = (ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff) & ~lsu_double_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:268:4 + assign lsu_stbuf_commit_any = stbuf_reqvld_any & (~((lsu_dccm_rden_d | lsu_dccm_wren_d) | ld_single_ecc_error_r_ff) | (lsu_dccm_rden_d & ~((stbuf_addr_any[pt[1275-:6]+:pt[1405-:7]] == lsu_addr_d[pt[1275-:6]+:pt[1405-:7]]) | (stbuf_addr_any[pt[1275-:6]+:pt[1405-:7]] == end_addr_d[pt[1275-:6]+:pt[1405-:7]])))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:274:4 + assign lsu_dccm_rden_d = (lsu_pkt_d[0] & (lsu_pkt_d[7] | (lsu_pkt_d[6] & (~(lsu_pkt_d[9] | lsu_pkt_d[8]) | (lsu_addr_d[1:0] != 2'b00))))) & addr_in_dccm_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:277:4 + assign lsu_dccm_wren_d = dma_dccm_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:280:4 + assign dccm_wren = (lsu_dccm_wren_d | lsu_stbuf_commit_any) | ld_single_ecc_error_r_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:281:4 + assign dccm_rden = lsu_dccm_rden_d & addr_in_dccm_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:282:4 + assign dccm_wr_addr_lo[pt[1398-:9] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0] : ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0]) : (lsu_dccm_wren_d ? lsu_addr_d[pt[1398-:9] - 1:0] : stbuf_addr_any[pt[1398-:9] - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:284:4 + assign dccm_wr_addr_hi[pt[1398-:9] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0] : ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0]) : (lsu_dccm_wren_d ? end_addr_d[pt[1398-:9] - 1:0] : stbuf_addr_any[pt[1398-:9] - 1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:286:4 + assign dccm_rd_addr_lo[pt[1398-:9] - 1:0] = lsu_addr_d[pt[1398-:9] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:287:4 + assign dccm_rd_addr_hi[pt[1398-:9] - 1:0] = end_addr_d[pt[1398-:9] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:288:4 + assign dccm_wr_data_lo[pt[1360-:10] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_lo_r_ff ? {sec_data_ecc_lo_r_ff[pt[1372-:7] - 1:0], sec_data_lo_r_ff[pt[1382-:10] - 1:0]} : {sec_data_ecc_hi_r_ff[pt[1372-:7] - 1:0], sec_data_hi_r_ff[pt[1382-:10] - 1:0]}) : (dma_dccm_wen ? {dma_dccm_wdata_ecc_lo[pt[1372-:7] - 1:0], dma_dccm_wdata_lo[pt[1382-:10] - 1:0]} : {stbuf_ecc_any[pt[1372-:7] - 1:0], stbuf_data_any[pt[1382-:10] - 1:0]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:292:4 + assign dccm_wr_data_hi[pt[1360-:10] - 1:0] = (ld_single_ecc_error_r_ff ? (ld_single_ecc_error_hi_r_ff ? {sec_data_ecc_hi_r_ff[pt[1372-:7] - 1:0], sec_data_hi_r_ff[pt[1382-:10] - 1:0]} : {sec_data_ecc_lo_r_ff[pt[1372-:7] - 1:0], sec_data_lo_r_ff[pt[1382-:10] - 1:0]}) : (dma_dccm_wen ? {dma_dccm_wdata_ecc_hi[pt[1372-:7] - 1:0], dma_dccm_wdata_hi[pt[1382-:10] - 1:0]} : {stbuf_ecc_any[pt[1372-:7] - 1:0], stbuf_data_any[pt[1382-:10] - 1:0]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:298:4 + assign store_byteen_m[3:0] = {4 {lsu_pkt_m[6]}} & ((({4 {lsu_pkt_m[11]}} & 4'b0001) | ({4 {lsu_pkt_m[10]}} & 4'b0011)) | ({4 {lsu_pkt_m[9]}} & 4'b1111)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:303:4 + assign store_byteen_r[3:0] = {4 {lsu_pkt_r[6]}} & ((({4 {lsu_pkt_r[11]}} & 4'b0001) | ({4 {lsu_pkt_r[10]}} & 4'b0011)) | ({4 {lsu_pkt_r[9]}} & 4'b1111)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:308:4 + assign store_byteen_ext_m[7:0] = {4'b0000, store_byteen_m[3:0]} << lsu_addr_m[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:309:4 + assign store_byteen_ext_r[7:0] = {4'b0000, store_byteen_r[3:0]} << lsu_addr_r[1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:313:4 + assign dccm_wr_bypass_d_m_lo = (stbuf_addr_any[pt[1398-:9] - 1:2] == lsu_addr_m[pt[1398-:9] - 1:2]) & addr_in_dccm_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:314:4 + assign dccm_wr_bypass_d_m_hi = (stbuf_addr_any[pt[1398-:9] - 1:2] == end_addr_m[pt[1398-:9] - 1:2]) & addr_in_dccm_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:316:4 + assign dccm_wr_bypass_d_r_lo = (stbuf_addr_any[pt[1398-:9] - 1:2] == lsu_addr_r[pt[1398-:9] - 1:2]) & addr_in_dccm_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:317:4 + assign dccm_wr_bypass_d_r_hi = (stbuf_addr_any[pt[1398-:9] - 1:2] == end_addr_r[pt[1398-:9] - 1:2]) & addr_in_dccm_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:320:4 + function automatic [31:0] sv2v_cast_32; + input reg [31:0] inp; + sv2v_cast_32 = inp; + endfunction + generate + if (pt[202-:5] == 1) begin : L2U1_Plus1_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:321:7 + wire dccm_wren_Q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:322:7 + wire [31:0] dccm_wr_data_Q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:323:7 + wire dccm_wr_bypass_d_m_lo_Q; + wire dccm_wr_bypass_d_m_hi_Q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:324:7 + wire [31:0] store_data_pre_hi_r; + wire [31:0] store_data_pre_lo_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:326:7 + assign {store_data_pre_hi_r[31:0], store_data_pre_lo_r[31:0]} = {32'b00000000000000000000000000000000, store_data_r[31:0]} << (8 * lsu_addr_r[1:0]); + genvar _gv_i_53; + for (_gv_i_53 = 0; _gv_i_53 < 4; _gv_i_53 = _gv_i_53 + 1) begin : genblk1 + localparam i = _gv_i_53; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:329:11 + assign store_data_lo_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i] ? store_data_pre_lo_r[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_lo_r[(8 * i) + 7:8 * i])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:330:11 + assign store_data_hi_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i + 4] ? store_data_pre_hi_r[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_hi_r[(8 * i) + 7:8 * i])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:332:11 + assign store_datafn_lo_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i] ? store_data_pre_lo_r[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo ? stbuf_data_any[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_lo_r[(8 * i) + 7:8 * i]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:334:11 + assign store_datafn_hi_r[(8 * i) + 7:8 * i] = (store_byteen_ext_r[i + 4] ? store_data_pre_hi_r[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi ? stbuf_data_any[(8 * i) + 7:8 * i] : (dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q ? dccm_wr_data_Q[(8 * i) + 7:8 * i] : sec_data_hi_r[(8 * i) + 7:8 * i]))); + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:338:7 + rvdff #(.WIDTH(1)) dccm_wren_ff( + .rst_l(rst_l), + .din(lsu_stbuf_commit_any), + .dout(dccm_wren_Q), + .clk(lsu_free_c2_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:339:7 + rvdffe #(.WIDTH(32)) dccm_wrdata_ff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(stbuf_data_any[31:0]), + .dout(dccm_wr_data_Q[31:0]), + .en(lsu_stbuf_commit_any | clk_override), + .clk(clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:340:7 + rvdff #(.WIDTH(1)) dccm_wrbyp_dm_loff( + .rst_l(rst_l), + .din(dccm_wr_bypass_d_m_lo), + .dout(dccm_wr_bypass_d_m_lo_Q), + .clk(lsu_free_c2_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:341:7 + rvdff #(.WIDTH(1)) dccm_wrbyp_dm_hiff( + .rst_l(rst_l), + .din(dccm_wr_bypass_d_m_hi), + .dout(dccm_wr_bypass_d_m_hi_Q), + .clk(lsu_free_c2_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:342:7 + rvdff #(.WIDTH(32)) store_data_rff( + .rst_l(rst_l), + .din(store_data_m[31:0]), + .dout(store_data_r[31:0]), + .clk(lsu_store_c1_r_clk) + ); + end + else begin : L2U1_Plus1_0 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:346:7 + wire [31:0] store_data_hi_m; + wire [31:0] store_data_lo_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:347:7 + wire [63:0] store_data_mask; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:348:7 + assign {store_data_hi_m[31:0], store_data_lo_m[31:0]} = {32'b00000000000000000000000000000000, store_data_m[31:0]} << (8 * lsu_addr_m[1:0]); + genvar _gv_i_54; + for (_gv_i_54 = 0; _gv_i_54 < 4; _gv_i_54 = _gv_i_54 + 1) begin : genblk1 + localparam i = _gv_i_54; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:351:10 + assign store_data_hi_r_in[(8 * i) + 7:8 * i] = (store_byteen_ext_m[i + 4] ? store_data_hi_m[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi ? stbuf_data_any[(8 * i) + 7:8 * i] : sec_data_hi_m[(8 * i) + 7:8 * i])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:353:10 + assign store_data_lo_r_in[(8 * i) + 7:8 * i] = (store_byteen_ext_m[i] ? store_data_lo_m[(8 * i) + 7:8 * i] : (lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo ? stbuf_data_any[(8 * i) + 7:8 * i] : sec_data_lo_m[(8 * i) + 7:8 * i])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:356:10 + assign store_datafn_lo_r[(8 * i) + 7:8 * i] = ((lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo) & ~store_byteen_ext_r[i] ? stbuf_data_any[(8 * i) + 7:8 * i] : store_data_lo_r[(8 * i) + 7:8 * i]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:357:10 + assign store_datafn_hi_r[(8 * i) + 7:8 * i] = ((lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi) & ~store_byteen_ext_r[i + 4] ? stbuf_data_any[(8 * i) + 7:8 * i] : store_data_hi_r[(8 * i) + 7:8 * i]); + end + genvar _gv_i_55; + for (_gv_i_55 = 0; _gv_i_55 < 4; _gv_i_55 = _gv_i_55 + 1) begin : genblk2 + localparam i = _gv_i_55; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:361:10 + assign store_data_mask[(8 * i) + 7:8 * i] = {8 {store_byteen_r[i]}}; + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:363:7 + assign store_data_r[31:0] = sv2v_cast_32({store_data_hi_r[31:0], store_data_lo_r[31:0]} >> (8 * lsu_addr_r[1:0])) & store_data_mask[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:365:7 + rvdffe #(.WIDTH(pt[1382-:10])) store_data_hi_rff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(store_data_hi_r_in[pt[1382-:10] - 1:0]), + .dout(store_data_hi_r[pt[1382-:10] - 1:0]), + .en(((ldst_dual_m & lsu_pkt_m[0]) & lsu_pkt_m[6]) | clk_override), + .clk(clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:366:7 + rvdff #(.WIDTH(pt[1382-:10])) store_data_lo_rff( + .rst_l(rst_l), + .din(store_data_lo_r_in[pt[1382-:10] - 1:0]), + .dout(store_data_lo_r[pt[1382-:10] - 1:0]), + .clk(lsu_store_c1_r_clk) + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:370:4 + assign dccm_rdata_lo_m[pt[1382-:10] - 1:0] = dccm_rd_data_lo[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:371:4 + assign dccm_rdata_hi_m[pt[1382-:10] - 1:0] = dccm_rd_data_hi[pt[1382-:10] - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:373:4 + assign dccm_data_ecc_lo_m[pt[1372-:7] - 1:0] = dccm_rd_data_lo[pt[1360-:10] - 1:pt[1382-:10]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:374:4 + assign dccm_data_ecc_hi_m[pt[1372-:7] - 1:0] = dccm_rd_data_hi[pt[1360-:10] - 1:pt[1382-:10]]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:377:4 + assign picm_wren = (((lsu_pkt_r[0] & lsu_pkt_r[6]) & addr_in_pic_r) & lsu_commit_r) | dma_pic_wen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:378:4 + assign picm_rden = (lsu_pkt_d[0] & lsu_pkt_d[7]) & addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:379:4 + assign picm_mken = (lsu_pkt_d[0] & lsu_pkt_d[6]) & addr_in_pic_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:380:4 + assign picm_rdaddr[31:0] = pt[130-:36] | {{32 - pt[94-:9] {1'b0}}, lsu_addr_d[pt[94-:9] - 1:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:382:4 + assign picm_wraddr[31:0] = pt[130-:36] | {{32 - pt[94-:9] {1'b0}}, (dma_pic_wen ? dma_mem_addr[pt[94-:9] - 1:0] : lsu_addr_r[pt[94-:9] - 1:0])}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:384:4 + assign picm_wr_data[31:0] = (dma_pic_wen ? dma_mem_wdata[31:0] : store_datafn_lo_r[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:386:4 + assign picm_mask_data_m[31:0] = picm_rd_data_m[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:387:4 + assign picm_rd_data_m[63:0] = {picm_rd_data[31:0], picm_rd_data[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:389:4 + generate + if (pt[1365-:5] == 1) begin : Gen_dccm_enable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:390:7 + rvdff #(.WIDTH(1)) dccm_rden_mff( + .rst_l(rst_l), + .din(lsu_dccm_rden_d), + .dout(lsu_dccm_rden_m), + .clk(lsu_c2_m_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:391:7 + rvdff #(.WIDTH(1)) dccm_rden_rff( + .rst_l(rst_l), + .din(lsu_dccm_rden_m), + .dout(lsu_dccm_rden_r), + .clk(lsu_c2_r_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:396:7 + rvdff #(.WIDTH(1)) ld_double_ecc_error_rff( + .rst_l(rst_l), + .din(lsu_double_ecc_error_r), + .dout(lsu_double_ecc_error_r_ff), + .clk(lsu_free_c2_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:397:7 + rvdff #(.WIDTH(1)) ld_single_ecc_error_hi_rff( + .rst_l(rst_l), + .din(ld_single_ecc_error_hi_r_ns), + .dout(ld_single_ecc_error_hi_r_ff), + .clk(lsu_free_c2_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:398:7 + rvdff #(.WIDTH(1)) ld_single_ecc_error_lo_rff( + .rst_l(rst_l), + .din(ld_single_ecc_error_lo_r_ns), + .dout(ld_single_ecc_error_lo_r_ff), + .clk(lsu_free_c2_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:399:7 + rvdffe #(.WIDTH(pt[1398-:9])) ld_sec_addr_hi_rff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(end_addr_r[pt[1398-:9] - 1:0]), + .dout(ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0]), + .en(ld_single_ecc_error_r | clk_override), + .clk(clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:400:7 + rvdffe #(.WIDTH(pt[1398-:9])) ld_sec_addr_lo_rff( + .rst_l(rst_l), + .scan_mode(scan_mode), + .din(lsu_addr_r[pt[1398-:9] - 1:0]), + .dout(ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0]), + .en(ld_single_ecc_error_r | clk_override), + .clk(clk) + ); + end + else begin : Gen_dccm_disable + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:403:7 + assign lsu_dccm_rden_m = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:404:7 + assign lsu_dccm_rden_r = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:406:7 + assign lsu_double_ecc_error_r_ff = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:407:7 + assign ld_single_ecc_error_hi_r_ff = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:408:7 + assign ld_single_ecc_error_lo_r_ff = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:409:7 + assign ld_sec_addr_hi_r_ff[pt[1398-:9] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_dccm_ctl.sv:410:7 + assign ld_sec_addr_lo_r_ff[pt[1398-:9] - 1:0] = 1'sb0; + end + endgenerate +endmodule +module el2_lsu_trigger ( + trigger_pkt_any, + lsu_pkt_m, + lsu_addr_m, + store_data_m, + lsu_trigger_match_m +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:30:4 + // removed localparam type el2_pkg_el2_trigger_pkt_t + input wire [151:0] trigger_pkt_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:31:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + input wire [13:0] lsu_pkt_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:32:4 + input wire [31:0] lsu_addr_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:33:4 + input wire [31:0] store_data_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:35:4 + output wire [3:0] lsu_trigger_match_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:38:4 + reg trigger_enable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:39:4 + wire [127:0] lsu_match_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:40:4 + wire [3:0] lsu_trigger_data_match; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:41:4 + wire [31:0] store_data_trigger_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:42:4 + wire [31:0] ldst_addr_trigger_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:45:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:46:7 + trigger_enable = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:47:7 + begin : sv2v_autoblock_1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:47:12 + reg signed [31:0] i; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:47:12 + for (i = 0; i < 4; i = i + 1) + begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:48:10 + trigger_enable = trigger_enable | trigger_pkt_any[(i * 38) + 32]; + end + end + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:52:4 + assign store_data_trigger_m[31:0] = {{16 {lsu_pkt_m[9]}} & store_data_m[31:16], {8 {lsu_pkt_m[10] | lsu_pkt_m[9]}} & store_data_m[15:8], store_data_m[7:0]} & {32 {trigger_enable}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:53:4 + assign ldst_addr_trigger_m[31:0] = lsu_addr_m[31:0] & {32 {trigger_enable}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:56:4 + genvar _gv_i_56; + generate + for (_gv_i_56 = 0; _gv_i_56 < 4; _gv_i_56 = _gv_i_56 + 1) begin : genblk1 + localparam i = _gv_i_56; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:57:7 + assign lsu_match_data[(i * 32) + 31-:32] = ({32 {~trigger_pkt_any[(i * 38) + 37]}} & ldst_addr_trigger_m[31:0]) | ({32 {trigger_pkt_any[(i * 38) + 37] & trigger_pkt_any[(i * 38) + 35]}} & store_data_trigger_m[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:60:7 + rvmaskandmatch trigger_match( + .mask(trigger_pkt_any[(i * 38) + 31-:32]), + .data(lsu_match_data[(i * 32) + 31-:32]), + .masken(trigger_pkt_any[(i * 38) + 36]), + .match(lsu_trigger_data_match[i]) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lsu/el2_lsu_trigger.sv:62:7 + assign lsu_trigger_match_m[i] = (((lsu_pkt_m[0] & ~lsu_pkt_m[4]) & trigger_enable) & ((trigger_pkt_any[(i * 38) + 35] & lsu_pkt_m[6]) | ((trigger_pkt_any[(i * 38) + 34] & lsu_pkt_m[7]) & ~trigger_pkt_any[(i * 38) + 37]))) & lsu_trigger_data_match[i]; + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module el2_dbg ( + dbg_cmd_addr, + dbg_cmd_wrdata, + dbg_cmd_valid, + dbg_cmd_write, + dbg_cmd_type, + dbg_cmd_size, + dbg_core_rst_l, + core_dbg_rddata, + core_dbg_cmd_done, + core_dbg_cmd_fail, + dbg_dma_bubble, + dma_dbg_ready, + dbg_halt_req, + dbg_resume_req, + dec_tlu_debug_mode, + dec_tlu_dbg_halted, + dec_tlu_mpc_halted_only, + dec_tlu_resume_ack, + dmi_reg_en, + dmi_reg_addr, + dmi_reg_wr_en, + dmi_reg_wdata, + dmi_reg_rdata, + sb_axi_awvalid, + sb_axi_awready, + sb_axi_awid, + sb_axi_awaddr, + sb_axi_awregion, + sb_axi_awlen, + sb_axi_awsize, + sb_axi_awburst, + sb_axi_awlock, + sb_axi_awcache, + sb_axi_awprot, + sb_axi_awqos, + sb_axi_wvalid, + sb_axi_wready, + sb_axi_wdata, + sb_axi_wstrb, + sb_axi_wlast, + sb_axi_bvalid, + sb_axi_bready, + sb_axi_bresp, + sb_axi_arvalid, + sb_axi_arready, + sb_axi_arid, + sb_axi_araddr, + sb_axi_arregion, + sb_axi_arlen, + sb_axi_arsize, + sb_axi_arburst, + sb_axi_arlock, + sb_axi_arcache, + sb_axi_arprot, + sb_axi_arqos, + sb_axi_rvalid, + sb_axi_rready, + sb_axi_rdata, + sb_axi_rresp, + dbg_bus_clk_en, + clk, + free_clk, + rst_l, + dbg_rst_l, + clk_override, + scan_mode +); + reg _sv2v_0; + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:30:4 + output wire [31:0] dbg_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:31:4 + output wire [31:0] dbg_cmd_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:32:4 + output wire dbg_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:33:4 + output wire dbg_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:34:4 + output wire [1:0] dbg_cmd_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:35:4 + output wire [1:0] dbg_cmd_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:36:4 + output wire dbg_core_rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:39:4 + input wire [31:0] core_dbg_rddata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:40:4 + input wire core_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:41:4 + input wire core_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:44:4 + output wire dbg_dma_bubble; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:45:4 + input wire dma_dbg_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:48:4 + output reg dbg_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:49:4 + output reg dbg_resume_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:50:4 + input wire dec_tlu_debug_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:51:4 + input wire dec_tlu_dbg_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:52:4 + input wire dec_tlu_mpc_halted_only; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:53:4 + input wire dec_tlu_resume_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:56:4 + input wire dmi_reg_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:57:4 + input wire [6:0] dmi_reg_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:58:4 + input wire dmi_reg_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:59:4 + input wire [31:0] dmi_reg_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:62:4 + output wire [31:0] dmi_reg_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:65:4 + output wire sb_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:66:4 + input wire sb_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:67:4 + output wire [pt[12-:8] - 1:0] sb_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:68:4 + output wire [31:0] sb_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:69:4 + output wire [3:0] sb_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:70:4 + output wire [7:0] sb_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:71:4 + output wire [2:0] sb_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:72:4 + output wire [1:0] sb_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:73:4 + output wire sb_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:74:4 + output wire [3:0] sb_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:75:4 + output wire [2:0] sb_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:76:4 + output wire [3:0] sb_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:78:4 + output wire sb_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:79:4 + input wire sb_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:80:4 + output wire [63:0] sb_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:81:4 + output wire [7:0] sb_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:82:4 + output wire sb_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:84:4 + input wire sb_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:85:4 + output wire sb_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:86:4 + input wire [1:0] sb_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:89:4 + output wire sb_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:90:4 + input wire sb_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:91:4 + output wire [pt[12-:8] - 1:0] sb_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:92:4 + output wire [31:0] sb_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:93:4 + output wire [3:0] sb_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:94:4 + output wire [7:0] sb_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:95:4 + output wire [2:0] sb_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:96:4 + output wire [1:0] sb_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:97:4 + output wire sb_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:98:4 + output wire [3:0] sb_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:99:4 + output wire [2:0] sb_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:100:4 + output wire [3:0] sb_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:102:4 + input wire sb_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:103:4 + output wire sb_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:104:4 + input wire [63:0] sb_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:105:4 + input wire [1:0] sb_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:107:4 + input wire dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:110:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:111:4 + input wire free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:112:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:113:4 + input wire dbg_rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:114:4 + input wire clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:115:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:119:4 + // removed localparam type state_t + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:120:4 + // removed localparam type sb_state_t + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:122:4 + wire [3:0] dbg_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:123:4 + reg [3:0] dbg_nxtstate; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:124:4 + reg dbg_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:126:4 + wire [31:0] dmstatus_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:127:4 + wire [31:0] dmcontrol_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:128:4 + wire [31:0] command_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:129:4 + wire [31:0] abstractcs_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:130:4 + wire [31:0] haltsum0_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:131:4 + wire [31:0] data0_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:132:4 + wire [31:0] data1_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:135:4 + wire [31:0] data0_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:136:4 + wire data0_reg_wren; + wire data0_reg_wren0; + wire data0_reg_wren1; + reg data0_reg_wren2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:138:4 + wire [31:0] data1_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:139:4 + wire data1_reg_wren; + wire data1_reg_wren0; + wire data1_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:141:4 + reg abstractcs_busy_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:142:4 + reg abstractcs_busy_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:143:4 + wire [2:0] abstractcs_error_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:144:4 + wire abstractcs_error_sel0; + wire abstractcs_error_sel1; + wire abstractcs_error_sel2; + wire abstractcs_error_sel3; + wire abstractcs_error_sel4; + wire abstractcs_error_sel5; + wire abstractcs_error_sel6; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:145:4 + reg dbg_sb_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:147:4 + wire abstractauto_reg_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:148:4 + wire [1:0] abstractauto_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:151:4 + wire dmstatus_resumeack_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:152:4 + wire dmstatus_resumeack_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:153:4 + wire dmstatus_haveresetn_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:154:4 + wire dmstatus_resumeack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:155:4 + wire dmstatus_unavail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:156:4 + wire dmstatus_running; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:157:4 + wire dmstatus_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:158:4 + wire dmstatus_havereset; + wire dmstatus_haveresetn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:161:4 + wire resumereq; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:162:4 + wire dmcontrol_wren; + wire dmcontrol_wren_Q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:164:4 + wire execute_command_ns; + wire execute_command; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:165:4 + wire command_wren; + wire command_regno_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:166:4 + wire command_transfer_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:167:4 + wire command_postexec_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:168:4 + wire [31:0] command_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:169:4 + wire [3:0] dbg_cmd_addr_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:170:4 + wire [31:0] dbg_cmd_curr_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:171:4 + wire [31:0] dbg_cmd_next_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:174:4 + wire [31:0] dmi_reg_rdata_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:176:4 + wire [3:0] sb_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:177:4 + reg [3:0] sb_nxtstate; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:178:4 + reg sb_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:181:4 + wire sbcs_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:182:4 + reg sbcs_sbbusy_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:183:4 + reg sbcs_sbbusy_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:184:4 + wire sbcs_sbbusyerror_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:185:4 + wire sbcs_sbbusyerror_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:187:4 + reg sbcs_sberror_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:188:4 + reg [2:0] sbcs_sberror_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:189:4 + wire sbcs_unaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:190:4 + wire sbcs_illegal_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:191:4 + wire [19:15] sbcs_reg_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:194:4 + wire sbdata0_reg_wren0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:195:4 + wire sbdata0_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:196:4 + wire sbdata0_reg_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:197:4 + wire [31:0] sbdata0_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:199:4 + wire sbdata1_reg_wren0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:200:4 + wire sbdata1_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:201:4 + wire sbdata1_reg_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:202:4 + wire [31:0] sbdata1_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:204:4 + wire sbaddress0_reg_wren0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:205:4 + reg sbaddress0_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:206:4 + wire sbaddress0_reg_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:207:4 + wire [31:0] sbaddress0_reg_din; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:208:4 + wire [3:0] sbaddress0_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:209:4 + wire sbreadonaddr_access; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:210:4 + wire sbreadondata_access; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:211:4 + wire sbdata0wr_access; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:213:4 + reg sb_abmem_cmd_done_in; + reg sb_abmem_data_done_in; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:214:4 + reg sb_abmem_cmd_done_en; + reg sb_abmem_data_done_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:215:4 + wire sb_abmem_cmd_done; + wire sb_abmem_data_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:216:4 + wire [31:0] abmem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:217:4 + wire abmem_addr_in_dccm_region; + wire abmem_addr_in_iccm_region; + wire abmem_addr_in_pic_region; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:218:4 + wire abmem_addr_core_local; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:219:4 + wire abmem_addr_external; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:221:4 + wire sb_cmd_pending; + wire sb_abmem_cmd_pending; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:222:4 + wire sb_abmem_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:223:4 + wire [2:0] sb_abmem_cmd_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:224:4 + wire [31:0] sb_abmem_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:225:4 + wire [31:0] sb_abmem_cmd_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:227:4 + wire [2:0] sb_cmd_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:228:4 + wire [31:0] sb_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:229:4 + wire [63:0] sb_cmd_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:231:4 + wire sb_bus_cmd_read; + wire sb_bus_cmd_write_addr; + wire sb_bus_cmd_write_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:232:4 + wire sb_bus_rsp_read; + wire sb_bus_rsp_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:233:4 + wire sb_bus_rsp_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:234:4 + wire [63:0] sb_bus_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:237:4 + wire [31:0] sbcs_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:238:4 + wire [31:0] sbaddress0_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:239:4 + wire [31:0] sbdata0_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:240:4 + wire [31:0] sbdata1_reg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:242:4 + wire sb_abmem_cmd_arvalid; + wire sb_abmem_cmd_awvalid; + wire sb_abmem_cmd_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:243:4 + wire sb_abmem_read_pend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:244:4 + wire sb_cmd_awvalid; + wire sb_cmd_wvalid; + wire sb_cmd_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:245:4 + wire sb_read_pend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:246:4 + wire [31:0] sb_axi_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:247:4 + wire [63:0] sb_axi_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:248:4 + wire [2:0] sb_axi_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:250:4 + wire dbg_dm_rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:251:4 + wire rst_l_sync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:254:4 + wire dbg_free_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:255:4 + wire dbg_free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:257:4 + wire sb_free_clken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:258:4 + wire sb_free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:262:4 + assign dbg_free_clken = (((((((dmi_reg_en | execute_command) | (dbg_state != 4'h0)) | dbg_state_en) | dec_tlu_dbg_halted) | dec_tlu_mpc_halted_only) | dec_tlu_debug_mode) | dbg_halt_req) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:265:4 + assign sb_free_clken = (((dmi_reg_en | execute_command) | sb_state_en) | (sb_state != 4'h0)) | clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:267:4 + rvoclkhdr dbg_free_cgc( + .en(dbg_free_clken), + .l1clk(dbg_free_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:268:4 + rvoclkhdr sb_free_cgc( + .en(sb_free_clken), + .l1clk(sb_free_clk), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:273:4 + assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:274:4 + assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:277:4 + rvsyncss #(.WIDTH(1)) rstl_syncff( + .din(rst_l), + .dout(rst_l_sync), + .clk(free_clk), + .rst_l(dbg_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:281:4 + assign sbcs_reg[31:29] = 3'b001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:282:4 + assign sbcs_reg[28:23] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:283:4 + assign sbcs_reg[19:15] = {sbcs_reg_int[19], ~sbcs_reg_int[18], sbcs_reg_int[17:15]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:284:4 + assign sbcs_reg[11:5] = 7'h20; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:285:4 + assign sbcs_reg[4:0] = 5'b01111; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:286:4 + assign sbcs_wren = (((dmi_reg_addr == 7'h38) & dmi_reg_en) & dmi_reg_wr_en) & (sb_state == 4'h0); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:287:4 + assign sbcs_sbbusyerror_wren = (sbcs_wren & dmi_reg_wdata[22]) | ((sbcs_reg[21] & dmi_reg_en) & (((dmi_reg_wr_en & (dmi_reg_addr == 7'h39)) | (dmi_reg_addr == 7'h3c)) | (dmi_reg_addr == 7'h3d))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:289:4 + assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:291:4 + rvdffs #(.WIDTH(1)) sbcs_sbbusyerror_reg( + .din(sbcs_sbbusyerror_din), + .dout(sbcs_reg[22]), + .en(sbcs_sbbusyerror_wren), + .rst_l(dbg_dm_rst_l), + .clk(sb_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:292:4 + rvdffs #(.WIDTH(1)) sbcs_sbbusy_reg( + .din(sbcs_sbbusy_din), + .dout(sbcs_reg[21]), + .en(sbcs_sbbusy_wren), + .rst_l(dbg_dm_rst_l), + .clk(sb_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:293:4 + rvdffs #(.WIDTH(1)) sbcs_sbreadonaddr_reg( + .din(dmi_reg_wdata[20]), + .dout(sbcs_reg[20]), + .en(sbcs_wren), + .rst_l(dbg_dm_rst_l), + .clk(sb_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:294:4 + rvdffs #(.WIDTH(5)) sbcs_misc_reg( + .din({dmi_reg_wdata[19], ~dmi_reg_wdata[18], dmi_reg_wdata[17:15]}), + .dout(sbcs_reg_int[19:15]), + .en(sbcs_wren), + .rst_l(dbg_dm_rst_l), + .clk(sb_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:296:4 + rvdffs #(.WIDTH(3)) sbcs_error_reg( + .din(sbcs_sberror_din[2:0]), + .dout(sbcs_reg[14:12]), + .en(sbcs_sberror_wren), + .rst_l(dbg_dm_rst_l), + .clk(sb_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:298:4 + assign sbcs_unaligned = (((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) | ((sbcs_reg[19:17] == 3'b010) & |sbaddress0_reg[1:0])) | ((sbcs_reg[19:17] == 3'b011) & |sbaddress0_reg[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:302:4 + assign sbcs_illegal_size = sbcs_reg[19]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:304:4 + assign sbaddress0_incr[3:0] = ((({4 {sbcs_reg[19:17] == 3'h0}} & 4'b0001) | ({4 {sbcs_reg[19:17] == 3'h1}} & 4'b0010)) | ({4 {sbcs_reg[19:17] == 3'h2}} & 4'b0100)) | ({4 {sbcs_reg[19:17] == 3'h3}} & 4'b1000); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:310:4 + assign sbdata0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h3c); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:311:4 + assign sbdata0_reg_wren1 = ((sb_state == 4'h7) & sb_state_en) & ~sbcs_sberror_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:312:4 + assign sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:314:4 + assign sbdata1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h3d); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:315:4 + assign sbdata1_reg_wren1 = ((sb_state == 4'h7) & sb_state_en) & ~sbcs_sberror_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:316:4 + assign sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:318:4 + assign sbdata0_din[31:0] = ({32 {sbdata0_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {sbdata0_reg_wren1}} & sb_bus_rdata[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:320:4 + assign sbdata1_din[31:0] = ({32 {sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {sbdata1_reg_wren1}} & sb_bus_rdata[63:32]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:323:4 + rvdffe #(.WIDTH(32)) dbg_sbdata0_reg( + .clk(clk), + .scan_mode(scan_mode), + .din(sbdata0_din[31:0]), + .dout(sbdata0_reg[31:0]), + .en(sbdata0_reg_wren), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:324:4 + rvdffe #(.WIDTH(32)) dbg_sbdata1_reg( + .clk(clk), + .scan_mode(scan_mode), + .din(sbdata1_din[31:0]), + .dout(sbdata1_reg[31:0]), + .en(sbdata1_reg_wren), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:327:4 + assign sbaddress0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h39); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:328:4 + assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:329:4 + assign sbaddress0_reg_din[31:0] = ({32 {sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {sbaddress0_reg_wren1}} & (sbaddress0_reg[31:0] + {28'b0000000000000000000000000000, sbaddress0_incr[3:0]})); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:331:4 + rvdffe #(.WIDTH(32)) dbg_sbaddress0_reg( + .clk(clk), + .scan_mode(scan_mode), + .din(sbaddress0_reg_din[31:0]), + .dout(sbaddress0_reg[31:0]), + .en(sbaddress0_reg_wren), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:333:4 + assign sbreadonaddr_access = ((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h39)) & sbcs_reg[20]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:334:4 + assign sbreadondata_access = ((dmi_reg_en & ~dmi_reg_wr_en) & (dmi_reg_addr == 7'h3c)) & sbcs_reg[15]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:335:4 + assign sbdata0wr_access = (dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h3c); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:341:4 + assign dmcontrol_wren = ((dmi_reg_addr == 7'h10) & dmi_reg_en) & dmi_reg_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:342:4 + assign dmcontrol_reg[29] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:343:4 + assign dmcontrol_reg[27:2] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:344:4 + assign resumereq = (dmcontrol_reg[30] & ~dmcontrol_reg[31]) & dmcontrol_wren_Q; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:345:4 + rvdffs #(.WIDTH(4)) dmcontrolff( + .din({dmi_reg_wdata[31:30], dmi_reg_wdata[28], dmi_reg_wdata[1]}), + .dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}), + .en(dmcontrol_wren), + .rst_l(dbg_dm_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:346:4 + rvdffs #(.WIDTH(1)) dmcontrol_dmactive_ff( + .din(dmi_reg_wdata[0]), + .dout(dmcontrol_reg[0]), + .en(dmcontrol_wren), + .rst_l(dbg_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:347:4 + rvdff #(.WIDTH(1)) dmcontrol_wrenff( + .din(dmcontrol_wren), + .dout(dmcontrol_wren_Q), + .rst_l(dbg_dm_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:353:4 + assign dmstatus_reg[31:20] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:354:4 + assign dmstatus_reg[19:18] = {2 {dmstatus_havereset}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:355:4 + assign dmstatus_reg[15:14] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:356:4 + assign dmstatus_reg[7] = 1'sb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:357:4 + assign dmstatus_reg[6:4] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:358:4 + assign dmstatus_reg[17:16] = {2 {dmstatus_resumeack}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:359:4 + assign dmstatus_reg[13:12] = {2 {dmstatus_unavail}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:360:4 + assign dmstatus_reg[11:10] = {2 {dmstatus_running}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:361:4 + assign dmstatus_reg[9:8] = {2 {dmstatus_halted}}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:362:4 + assign dmstatus_reg[3:0] = 4'h2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:364:4 + assign dmstatus_resumeack_wren = ((dbg_state == 4'h9) & dec_tlu_resume_ack) | ((dmstatus_resumeack & resumereq) & dmstatus_halted); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:365:4 + assign dmstatus_resumeack_din = (dbg_state == 4'h9) & dec_tlu_resume_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:367:4 + assign dmstatus_haveresetn_wren = ((((dmi_reg_addr == 7'h10) & dmi_reg_wdata[28]) & dmi_reg_en) & dmi_reg_wr_en) & dmcontrol_reg[0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:368:4 + assign dmstatus_havereset = ~dmstatus_haveresetn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:370:4 + assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l_sync; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:371:4 + assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:373:4 + rvdffs #(.WIDTH(1)) dmstatus_resumeack_reg( + .din(dmstatus_resumeack_din), + .dout(dmstatus_resumeack), + .en(dmstatus_resumeack_wren), + .rst_l(dbg_dm_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:374:4 + rvdff #(.WIDTH(1)) dmstatus_halted_reg( + .din(dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only), + .dout(dmstatus_halted), + .rst_l(dbg_dm_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:375:4 + rvdffs #(.WIDTH(1)) dmstatus_haveresetn_reg( + .din(1'b1), + .dout(dmstatus_haveresetn), + .en(dmstatus_haveresetn_wren), + .rst_l(rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:378:4 + assign haltsum0_reg[31:1] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:379:4 + assign haltsum0_reg[0] = dmstatus_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:383:4 + assign abstractcs_reg[31:13] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:384:4 + assign abstractcs_reg[11] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:385:4 + assign abstractcs_reg[7:4] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:386:4 + assign abstractcs_reg[3:0] = 4'h2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:388:4 + assign abstractcs_error_sel0 = ((abstractcs_reg[12] & ~(|abstractcs_reg[10:8])) & dmi_reg_en) & ((((dmi_reg_wr_en & ((dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17))) | (dmi_reg_addr == 7'h18)) | (dmi_reg_addr == 7'h04)) | (dmi_reg_addr == 7'h05)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:390:4 + assign abstractcs_error_sel1 = (execute_command & ~(|abstractcs_reg[10:8])) & (((~((command_reg[31:24] == 8'b00000000) | (command_reg[31:24] == 8'h02)) | (((command_reg[22:20] == 3'b011) | command_reg[22]) & (command_reg[31:24] == 8'h02))) | ((command_reg[22:20] != 3'b010) & ((command_reg[31:24] == 8'h00) & command_reg[17]))) | ((command_reg[31:24] == 8'h00) & command_reg[18])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:395:4 + assign abstractcs_error_sel2 = ((core_dbg_cmd_done & core_dbg_cmd_fail) | ((execute_command & (command_reg[31:24] == 8'h00)) & (((command_reg[15:12] == 4'h1) & (command_reg[11:5] != 0)) | (command_reg[15:13] != 0)))) & ~(|abstractcs_reg[10:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:398:4 + assign abstractcs_error_sel3 = (execute_command & (dbg_state != 4'h2)) & ~(|abstractcs_reg[10:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:399:4 + assign abstractcs_error_sel4 = (dbg_sb_bus_error & dbg_bus_clk_en) & ~(|abstractcs_reg[10:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:400:4 + assign abstractcs_error_sel5 = ((execute_command & (command_reg[31:24] == 8'h02)) & ~(|abstractcs_reg[10:8])) & (((command_reg[22:20] == 3'b001) & data1_reg[0]) | ((command_reg[22:20] == 3'b010) & |data1_reg[1:0])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:402:4 + assign abstractcs_error_sel6 = ((dmi_reg_addr == 7'h16) & dmi_reg_en) & dmi_reg_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:404:4 + assign abstractcs_error_din[2:0] = (abstractcs_error_sel0 ? 3'b001 : (abstractcs_error_sel1 ? 3'b010 : (abstractcs_error_sel2 ? 3'b011 : (abstractcs_error_sel3 ? 3'b100 : (abstractcs_error_sel4 ? 3'b101 : (abstractcs_error_sel5 ? 3'b111 : (abstractcs_error_sel6 ? ~dmi_reg_wdata[10:8] & abstractcs_reg[10:8] : abstractcs_reg[10:8]))))))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:413:4 + rvdffs #(.WIDTH(1)) dmabstractcs_busy_reg( + .din(abstractcs_busy_din), + .dout(abstractcs_reg[12]), + .en(abstractcs_busy_wren), + .rst_l(dbg_dm_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:414:4 + rvdff #(.WIDTH(3)) dmabstractcs_error_reg( + .din(abstractcs_error_din[2:0]), + .dout(abstractcs_reg[10:8]), + .rst_l(dbg_dm_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:417:4 + assign abstractauto_reg_wren = ((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h18)) & ~abstractcs_reg[12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:418:4 + rvdffs #(.WIDTH(2)) dbg_abstractauto_reg( + .din(dmi_reg_wdata[1:0]), + .dout(abstractauto_reg[1:0]), + .en(abstractauto_reg_wren), + .rst_l(dbg_dm_rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:422:4 + assign execute_command_ns = command_wren | ((dmi_reg_en & ~abstractcs_reg[12]) & (((dmi_reg_addr == 7'h04) & abstractauto_reg[0]) | ((dmi_reg_addr == 7'h05) & abstractauto_reg[1]))); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:424:4 + assign command_wren = ((dmi_reg_addr == 7'h17) & dmi_reg_en) & dmi_reg_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:425:4 + assign command_regno_wren = command_wren | ((((command_reg[31:24] == 8'h00) & command_reg[19]) & (dbg_state == 4'h8)) & ~(|abstractcs_reg[10:8])); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:426:4 + assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h00) & dmi_reg_wdata[18]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:427:4 + assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h00) & dmi_reg_wdata[17]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:428:4 + assign command_din[31:16] = {dmi_reg_wdata[31:24], 1'b0, dmi_reg_wdata[22:19], command_postexec_din, command_transfer_din, dmi_reg_wdata[16]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:429:4 + assign command_din[15:0] = (command_wren ? dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:430:4 + rvdff #(.WIDTH(1)) execute_commandff( + .din(execute_command_ns), + .dout(execute_command), + .clk(dbg_free_clk), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:431:4 + rvdffe #(.WIDTH(16)) dmcommand_reg( + .clk(clk), + .scan_mode(scan_mode), + .din(command_din[31:16]), + .dout(command_reg[31:16]), + .en(command_wren), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:432:4 + rvdffe #(.WIDTH(16)) dmcommand_regno_reg( + .clk(clk), + .scan_mode(scan_mode), + .din(command_din[15:0]), + .dout(command_reg[15:0]), + .en(command_regno_wren), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:435:4 + assign data0_reg_wren0 = (((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h04)) & (dbg_state == 4'h2)) & ~abstractcs_reg[12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:436:4 + assign data0_reg_wren1 = (core_dbg_cmd_done & (dbg_state == 4'h4)) & ~command_reg[16]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:437:4 + assign data0_reg_wren = (data0_reg_wren0 | data0_reg_wren1) | data0_reg_wren2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:439:4 + assign data0_din[31:0] = (({32 {data0_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {data0_reg_wren1}} & core_dbg_rddata[31:0])) | ({32 {data0_reg_wren2}} & sb_bus_rdata[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:443:4 + rvdffe #(.WIDTH(32)) dbg_data0_reg( + .clk(clk), + .scan_mode(scan_mode), + .din(data0_din[31:0]), + .dout(data0_reg[31:0]), + .en(data0_reg_wren), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:446:4 + assign data1_reg_wren0 = (((dmi_reg_en & dmi_reg_wr_en) & (dmi_reg_addr == 7'h05)) & (dbg_state == 4'h2)) & ~abstractcs_reg[12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:447:4 + assign data1_reg_wren1 = (((dbg_state == 4'h8) & (command_reg[31:24] == 8'h02)) & command_reg[19]) & ~(|abstractcs_reg[10:8]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:448:4 + assign data1_reg_wren = data1_reg_wren0 | data1_reg_wren1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:450:4 + assign data1_din[31:0] = ({32 {data1_reg_wren0}} & dmi_reg_wdata[31:0]) | ({32 {data1_reg_wren1}} & dbg_cmd_next_addr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:453:4 + rvdffe #(.WIDTH(32)) dbg_data1_reg( + .clk(clk), + .scan_mode(scan_mode), + .din(data1_din[31:0]), + .dout(data1_reg[31:0]), + .en(data1_reg_wren), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:455:4 + rvdffs #(.WIDTH(1)) sb_abmem_cmd_doneff( + .din(sb_abmem_cmd_done_in), + .dout(sb_abmem_cmd_done), + .en(sb_abmem_cmd_done_en), + .clk(dbg_free_clk), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:456:4 + rvdffs #(.WIDTH(1)) sb_abmem_data_doneff( + .din(sb_abmem_data_done_in), + .dout(sb_abmem_data_done), + .en(sb_abmem_data_done_en), + .clk(dbg_free_clk), + .rst_l(dbg_dm_rst_l) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:459:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:460:7 + dbg_nxtstate = 4'h0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:461:7 + dbg_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:462:7 + abstractcs_busy_wren = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:463:7 + abstractcs_busy_din = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:464:7 + dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:465:7 + dbg_resume_req = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:466:7 + dbg_sb_bus_error = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:467:7 + data0_reg_wren2 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:468:7 + sb_abmem_cmd_done_in = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:469:7 + sb_abmem_data_done_in = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:470:7 + sb_abmem_cmd_done_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:471:7 + sb_abmem_data_done_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:473:8 + case (dbg_state) + 4'h0: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:475:22 + dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only ? 4'h2 : 4'h1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:476:22 + dbg_state_en = (dmcontrol_reg[31] | dmstatus_reg[9]) | dec_tlu_mpc_halted_only; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:477:22 + dbg_halt_req = dmcontrol_reg[31]; + end + 4'h1: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:480:22 + dbg_nxtstate = 4'h2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:481:22 + dbg_state_en = dmstatus_reg[9] | dec_tlu_mpc_halted_only; + end + 4'h2: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:485:22 + dbg_nxtstate = (dmstatus_reg[9] ? (resumereq ? 4'h9 : ((command_reg[31:24] == 8'h02) & abmem_addr_external ? 4'h5 : 4'h3)) : (dmcontrol_reg[31] ? 4'h1 : 4'h0)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:487:22 + dbg_state_en = ((dmstatus_reg[9] & resumereq) | execute_command) | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:488:22 + abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == 4'h3) | (dbg_nxtstate == 4'h5)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:489:22 + abstractcs_busy_din = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:490:22 + dbg_resume_req = dbg_state_en & (dbg_nxtstate == 4'h9); + end + 4'h3: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:494:22 + dbg_nxtstate = (|abstractcs_reg[10:8] | ((command_reg[31:24] == 8'h00) & ~command_reg[17]) ? 4'h8 : 4'h4); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:495:22 + dbg_state_en = (dbg_cmd_valid | (|abstractcs_reg[10:8])) | ((command_reg[31:24] == 8'h00) & ~command_reg[17]); + end + 4'h4: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:498:22 + dbg_nxtstate = 4'h8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:499:22 + dbg_state_en = core_dbg_cmd_done; + end + 4'h5: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:502:22 + dbg_nxtstate = (|abstractcs_reg[10:8] ? 4'h8 : 4'h6); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:503:22 + dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | (|abstractcs_reg[10:8]); + end + 4'h6: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:506:22 + sb_abmem_cmd_done_in = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:507:22 + sb_abmem_data_done_in = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:508:22 + sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:509:22 + sb_abmem_data_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:510:22 + dbg_nxtstate = 4'h7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:511:22 + dbg_state_en = ((sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en)) & dbg_bus_clk_en; + end + 4'h7: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:514:22 + dbg_nxtstate = 4'h8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:515:22 + dbg_state_en = (sb_bus_rsp_read | sb_bus_rsp_write) & dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:516:22 + dbg_sb_bus_error = ((sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error) & dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:517:22 + data0_reg_wren2 = (dbg_state_en & ~sb_abmem_cmd_write) & ~dbg_sb_bus_error; + end + 4'h8: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:520:22 + dbg_nxtstate = 4'h2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:521:22 + dbg_state_en = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:522:22 + abstractcs_busy_wren = dbg_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:523:22 + abstractcs_busy_din = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:524:22 + sb_abmem_cmd_done_in = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:525:22 + sb_abmem_data_done_in = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:526:22 + sb_abmem_cmd_done_en = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:527:22 + sb_abmem_data_done_en = 1'b1; + end + 4'h9: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:530:22 + dbg_nxtstate = 4'h0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:531:22 + dbg_state_en = dmstatus_reg[17]; + end + default: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:534:22 + dbg_nxtstate = 4'h0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:535:22 + dbg_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:536:22 + abstractcs_busy_wren = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:537:22 + abstractcs_busy_din = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:538:22 + dbg_halt_req = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:539:22 + dbg_resume_req = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:540:22 + dbg_sb_bus_error = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:541:22 + data0_reg_wren2 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:542:22 + sb_abmem_cmd_done_in = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:543:22 + sb_abmem_data_done_in = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:544:22 + sb_abmem_cmd_done_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:545:22 + sb_abmem_data_done_en = 1'b0; + end + endcase + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:550:4 + assign dmi_reg_rdata_din[31:0] = ((((((((((({32 {dmi_reg_addr == 7'h04}} & data0_reg[31:0]) | ({32 {dmi_reg_addr == 7'h05}} & data1_reg[31:0])) | ({32 {dmi_reg_addr == 7'h10}} & {2'b00, dmcontrol_reg[29], 1'b0, dmcontrol_reg[27:0]})) | ({32 {dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0])) | ({32 {dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0])) | ({32 {dmi_reg_addr == 7'h17}} & command_reg[31:0])) | ({32 {dmi_reg_addr == 7'h18}} & {30'h00000000, abstractauto_reg[1:0]})) | ({32 {dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0])) | ({32 {dmi_reg_addr == 7'h38}} & sbcs_reg[31:0])) | ({32 {dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0])) | ({32 {dmi_reg_addr == 7'h3c}} & sbdata0_reg[31:0])) | ({32 {dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:564:4 + rvdffs #(.WIDTH(4)) dbg_state_reg( + .din(dbg_nxtstate), + .dout({dbg_state}), + .en(dbg_state_en), + .rst_l(dbg_dm_rst_l & rst_l), + .clk(dbg_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:565:4 + rvdffe #(.WIDTH(32)) dmi_rddata_reg( + .din(dmi_reg_rdata_din[31:0]), + .dout(dmi_reg_rdata[31:0]), + .en(dmi_reg_en), + .rst_l(dbg_dm_rst_l), + .clk(clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:567:4 + assign abmem_addr[31:0] = data1_reg[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:568:4 + assign abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region) | abmem_addr_in_pic_region; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:569:4 + assign abmem_addr_external = ~abmem_addr_core_local; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:571:4 + assign abmem_addr_in_dccm_region = (abmem_addr[31:28] == pt[1333-:8]) & pt[1365-:5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:572:4 + assign abmem_addr_in_iccm_region = (abmem_addr[31:28] == pt[895-:8]) & pt[927-:5]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:573:4 + assign abmem_addr_in_pic_region = abmem_addr[31:28] == pt[77-:8]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:576:4 + assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h02 ? data1_reg[31:0] : {20'b00000000000000000000, command_reg[11:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:577:4 + assign dbg_cmd_wrdata[31:0] = data0_reg[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:578:4 + assign dbg_cmd_valid = ((dbg_state == 4'h3) & ~((|abstractcs_reg[10:8] | ((command_reg[31:24] == 8'h00) & ~command_reg[17])) | ((command_reg[31:24] == 8'h02) & abmem_addr_external))) & dma_dbg_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:579:4 + assign dbg_cmd_write = command_reg[16]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:580:4 + assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h02 ? 2'b10 : {1'b0, command_reg[15:12] == 4'b0000}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:581:4 + assign dbg_cmd_size[1:0] = command_reg[21:20]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:583:4 + assign dbg_cmd_addr_incr[3:0] = (command_reg[31:24] == 8'h02 ? 4'h1 << sb_abmem_cmd_size[1:0] : 4'h1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:584:4 + assign dbg_cmd_curr_addr[31:0] = (command_reg[31:24] == 8'h02 ? data1_reg[31:0] : {16'b0000000000000000, command_reg[15:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:585:4 + assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0000000, dbg_cmd_addr_incr[3:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:588:4 + assign dbg_dma_bubble = ((dbg_state == 4'h3) & ~(|abstractcs_reg[10:8])) | (dbg_state == 4'h4); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:590:4 + assign sb_cmd_pending = (((((sb_state == 4'h3) | (sb_state == 4'h4)) | (sb_state == 4'h5)) | (sb_state == 4'h6)) | (sb_state == 4'h7)) | (sb_state == 4'h8); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:591:4 + assign sb_abmem_cmd_pending = ((dbg_state == 4'h5) | (dbg_state == 4'h6)) | (dbg_state == 4'h7); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:595:3 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:596:7 + sb_nxtstate = 4'h0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:597:7 + sb_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:598:7 + sbcs_sbbusy_wren = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:599:7 + sbcs_sbbusy_din = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:600:7 + sbcs_sberror_wren = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:601:7 + sbcs_sberror_din[2:0] = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:602:7 + sbaddress0_reg_wren1 = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:603:7 + case (sb_state) + 4'h0: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:605:22 + sb_nxtstate = (sbdata0wr_access ? 4'h2 : 4'h1); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:606:22 + sb_state_en = (((sbdata0wr_access | sbreadondata_access) | sbreadonaddr_access) & ~(|sbcs_reg[14:12])) & ~sbcs_reg[22]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:607:22 + sbcs_sbbusy_wren = sb_state_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:608:22 + sbcs_sbbusy_din = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:609:22 + sbcs_sberror_wren = sbcs_wren & |dmi_reg_wdata[14:12]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:610:22 + sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; + end + 4'h1: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:613:22 + sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size ? 4'h9 : 4'h3); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:614:22 + sb_state_en = ((dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned) | sbcs_illegal_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:615:22 + sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:616:22 + sbcs_sberror_din[2:0] = (sbcs_unaligned ? 3'b011 : 3'b100); + end + 4'h2: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:619:22 + sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size ? 4'h9 : 4'h4); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:620:22 + sb_state_en = ((dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned) | sbcs_illegal_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:621:22 + sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:622:22 + sbcs_sberror_din[2:0] = (sbcs_unaligned ? 3'b011 : 3'b100); + end + 4'h3: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:625:22 + sb_nxtstate = 4'h7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:626:22 + sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en; + end + 4'h4: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:629:22 + sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data ? 4'h8 : (sb_bus_cmd_write_data ? 4'h5 : 4'h6)); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:630:22 + sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en; + end + 4'h5: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:633:22 + sb_nxtstate = 4'h8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:634:22 + sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en; + end + 4'h6: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:637:22 + sb_nxtstate = 4'h8; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:638:22 + sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en; + end + 4'h7: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:641:22 + sb_nxtstate = 4'h9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:642:22 + sb_state_en = sb_bus_rsp_read & dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:643:22 + sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:644:22 + sbcs_sberror_din[2:0] = 3'b010; + end + 4'h8: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:647:22 + sb_nxtstate = 4'h9; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:648:22 + sb_state_en = sb_bus_rsp_write & dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:649:22 + sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:650:22 + sbcs_sberror_din[2:0] = 3'b010; + end + 4'h9: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:653:22 + sb_nxtstate = 4'h0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:654:22 + sb_state_en = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:655:22 + sbcs_sbbusy_wren = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:656:22 + sbcs_sbbusy_din = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:657:22 + sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b000); + end + default: begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:660:22 + sb_nxtstate = 4'h0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:661:22 + sb_state_en = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:662:22 + sbcs_sbbusy_wren = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:663:22 + sbcs_sbbusy_din = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:664:22 + sbcs_sberror_wren = 1'b0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:665:22 + sbcs_sberror_din[2:0] = 3'b000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:666:22 + sbaddress0_reg_wren1 = 1'b0; + end + endcase + end + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:671:4 + rvdffs #(.WIDTH(4)) sb_state_reg( + .din(sb_nxtstate), + .dout({sb_state}), + .en(sb_state_en), + .rst_l(dbg_dm_rst_l), + .clk(sb_free_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:673:4 + assign sb_abmem_cmd_write = command_reg[16]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:674:4 + assign sb_abmem_cmd_size[2:0] = {1'b0, command_reg[21:20]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:675:4 + assign sb_abmem_cmd_addr[31:0] = abmem_addr[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:676:4 + assign sb_abmem_cmd_wdata[31:0] = data0_reg[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:678:4 + assign sb_cmd_size[2:0] = sbcs_reg[19:17]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:679:4 + assign sb_cmd_wdata[63:0] = {sbdata1_reg[31:0], sbdata0_reg[31:0]}; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:680:4 + assign sb_cmd_addr[31:0] = sbaddress0_reg[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:682:4 + assign sb_abmem_cmd_awvalid = ((dbg_state == 4'h6) & sb_abmem_cmd_write) & ~sb_abmem_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:683:4 + assign sb_abmem_cmd_wvalid = ((dbg_state == 4'h6) & sb_abmem_cmd_write) & ~sb_abmem_data_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:684:4 + assign sb_abmem_cmd_arvalid = (((dbg_state == 4'h6) & ~sb_abmem_cmd_write) & ~sb_abmem_cmd_done) & ~sb_abmem_data_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:685:4 + assign sb_abmem_read_pend = (dbg_state == 4'h7) & ~sb_abmem_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:687:4 + assign sb_cmd_awvalid = (sb_state == 4'h4) | (sb_state == 4'h5); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:688:4 + assign sb_cmd_wvalid = (sb_state == 4'h4) | (sb_state == 4'h6); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:689:4 + assign sb_cmd_arvalid = sb_state == 4'h3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:690:4 + assign sb_read_pend = sb_state == 4'h7; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:692:4 + assign sb_axi_size[2:0] = (((sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) | sb_abmem_cmd_arvalid) | sb_abmem_read_pend ? sb_abmem_cmd_size[2:0] : sb_cmd_size[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:693:4 + assign sb_axi_addr[31:0] = (((sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) | sb_abmem_cmd_arvalid) | sb_abmem_read_pend ? sb_abmem_cmd_addr[31:0] : sb_cmd_addr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:694:4 + assign sb_axi_wrdata[63:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid ? {2 {sb_abmem_cmd_wdata[31:0]}} : sb_cmd_wdata[63:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:697:4 + assign sb_bus_cmd_read = sb_axi_arvalid & sb_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:698:4 + assign sb_bus_cmd_write_addr = sb_axi_awvalid & sb_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:699:4 + assign sb_bus_cmd_write_data = sb_axi_wvalid & sb_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:701:4 + assign sb_bus_rsp_read = sb_axi_rvalid & sb_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:702:4 + assign sb_bus_rsp_write = sb_axi_bvalid & sb_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:703:4 + assign sb_bus_rsp_error = (sb_bus_rsp_read & |sb_axi_rresp[1:0]) | (sb_bus_rsp_write & |sb_axi_bresp[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:706:4 + assign sb_axi_awvalid = sb_abmem_cmd_awvalid | sb_cmd_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:707:4 + assign sb_axi_awaddr[31:0] = sb_axi_addr[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:708:4 + assign sb_axi_awid[pt[12-:8] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:709:4 + assign sb_axi_awsize[2:0] = sb_axi_size[2:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:710:4 + assign sb_axi_awprot[2:0] = 3'b001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:711:4 + assign sb_axi_awcache[3:0] = 4'b1111; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:712:4 + assign sb_axi_awregion[3:0] = sb_axi_addr[31:28]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:713:4 + assign sb_axi_awlen[7:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:714:4 + assign sb_axi_awburst[1:0] = 2'b01; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:715:4 + assign sb_axi_awqos[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:716:4 + assign sb_axi_awlock = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:718:4 + assign sb_axi_wvalid = sb_abmem_cmd_wvalid | sb_cmd_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:719:4 + assign sb_axi_wdata[63:0] = ((({64 {sb_axi_size[2:0] == 3'h0}} & {8 {sb_axi_wrdata[7:0]}}) | ({64 {sb_axi_size[2:0] == 3'h1}} & {4 {sb_axi_wrdata[15:0]}})) | ({64 {sb_axi_size[2:0] == 3'h2}} & {2 {sb_axi_wrdata[31:0]}})) | ({64 {sb_axi_size[2:0] == 3'h3}} & {sb_axi_wrdata[63:0]}); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:723:4 + assign sb_axi_wstrb[7:0] = ((({8 {sb_axi_size[2:0] == 3'h0}} & (8'h01 << sb_axi_addr[2:0])) | ({8 {sb_axi_size[2:0] == 3'h1}} & (8'h03 << {sb_axi_addr[2:1], 1'b0}))) | ({8 {sb_axi_size[2:0] == 3'h2}} & (8'h0f << {sb_axi_addr[2], 2'b00}))) | ({8 {sb_axi_size[2:0] == 3'h3}} & 8'hff); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:727:4 + assign sb_axi_wlast = 1'sb1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:729:4 + assign sb_axi_arvalid = sb_abmem_cmd_arvalid | sb_cmd_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:730:4 + assign sb_axi_araddr[31:0] = sb_axi_addr[31:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:731:4 + assign sb_axi_arid[pt[12-:8] - 1:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:732:4 + assign sb_axi_arsize[2:0] = sb_axi_size[2:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:733:4 + assign sb_axi_arprot[2:0] = 3'b001; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:734:4 + assign sb_axi_arcache[3:0] = 4'b0000; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:735:4 + assign sb_axi_arregion[3:0] = sb_axi_addr[31:28]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:736:4 + assign sb_axi_arlen[7:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:737:4 + assign sb_axi_arburst[1:0] = 2'b01; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:738:4 + assign sb_axi_arqos[3:0] = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:739:4 + assign sb_axi_arlock = 1'sb0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:742:4 + assign sb_axi_bready = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:744:4 + assign sb_axi_rready = 1'b1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv:745:4 + assign sb_bus_rdata[63:0] = ((({64 {sb_axi_size == 3'h0}} & ((sb_axi_rdata[63:0] >> (8 * sb_axi_addr[2:0])) & 64'h00000000000000ff)) | ({64 {sb_axi_size == 3'h1}} & ((sb_axi_rdata[63:0] >> (16 * sb_axi_addr[2:1])) & 64'h000000000000ffff))) | ({64 {sb_axi_size == 3'h2}} & ((sb_axi_rdata[63:0] >> (32 * sb_axi_addr[2])) & 64'h00000000ffffffff))) | ({64 {sb_axi_size == 3'h3}} & sb_axi_rdata[63:0]); + initial _sv2v_0 = 0; +endmodule +module el2_ram ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:86:18 + parameter depth = 4096; + parameter width = 39; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:87:1 + input wire [$clog2(depth) - 1:0] ADR; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:88:1 + input wire [width - 1:0] D; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:89:1 + output reg [width - 1:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:3 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:33 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:63 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:93 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:123 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:153 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:183 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:213 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:243 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:273 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:303 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:333 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:90:363 + output wire ROP; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:92:1 + reg [width - 1:0] ram_core [depth - 1:0]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:94:1 + always @(posedge CLK) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:98:4 + if (ME && WE) begin + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:98:24 + ram_core[ADR] <= D; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:98:44 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:100:19 + Q <= ram_core[ADR]; + end +endmodule +module ram_8192x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:60 + input wire [12:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:105 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:150 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:281 + reg [67:0] ram_core [8191:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:132:1014 + assign ROP = ME; +endmodule +module ram_4096x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:60 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:105 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:150 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:281 + reg [67:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:133:1014 + assign ROP = ME; +endmodule +module ram_2048x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:60 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:105 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:150 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:281 + reg [67:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:134:1014 + assign ROP = ME; +endmodule +module ram_1024x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:60 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:105 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:150 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:281 + reg [67:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:135:1014 + assign ROP = ME; +endmodule +module ram_512x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:59 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:104 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:149 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:280 + reg [67:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:136:1013 + assign ROP = ME; +endmodule +module ram_256x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:59 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:104 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:149 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:280 + reg [67:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:137:1013 + assign ROP = ME; +endmodule +module ram_128x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:59 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:104 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:149 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:280 + reg [67:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:138:1013 + assign ROP = ME; +endmodule +module ram_64x68 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:58 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:103 + input wire [67:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:148 + output reg [67:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:279 + reg [67:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:822 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:842 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:862 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:940 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:139:1012 + assign ROP = ME; +endmodule +module ram_8192x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:60 + input wire [12:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:105 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:150 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:281 + reg [70:0] ram_core [8191:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:140:1014 + assign ROP = ME; +endmodule +module ram_4096x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:60 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:105 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:150 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:281 + reg [70:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:141:1014 + assign ROP = ME; +endmodule +module ram_2048x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:60 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:105 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:150 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:281 + reg [70:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:142:1014 + assign ROP = ME; +endmodule +module ram_1024x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:60 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:105 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:150 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:281 + reg [70:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:143:1014 + assign ROP = ME; +endmodule +module ram_512x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:59 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:104 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:149 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:280 + reg [70:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:144:1013 + assign ROP = ME; +endmodule +module ram_256x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:59 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:104 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:149 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:280 + reg [70:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:145:1013 + assign ROP = ME; +endmodule +module ram_128x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:59 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:104 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:149 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:280 + reg [70:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:146:1013 + assign ROP = ME; +endmodule +module ram_64x71 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:58 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:103 + input wire [70:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:148 + output reg [70:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:279 + reg [70:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:822 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:842 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:862 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:940 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:147:1012 + assign ROP = ME; +endmodule +module ram_4096x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:60 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:105 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:150 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:281 + reg [21:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:155:1014 + assign ROP = ME; +endmodule +module ram_2048x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:60 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:105 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:150 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:281 + reg [21:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:156:1014 + assign ROP = ME; +endmodule +module ram_1024x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:60 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:105 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:150 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:281 + reg [21:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:157:1014 + assign ROP = ME; +endmodule +module ram_512x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:59 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:104 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:149 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:280 + reg [21:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:158:1013 + assign ROP = ME; +endmodule +module ram_256x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:59 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:104 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:149 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:280 + reg [21:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:159:1013 + assign ROP = ME; +endmodule +module ram_128x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:59 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:104 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:149 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:280 + reg [21:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:160:1013 + assign ROP = ME; +endmodule +module ram_64x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:58 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:103 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:148 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:279 + reg [21:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:822 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:842 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:862 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:940 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:161:1012 + assign ROP = ME; +endmodule +module ram_1024x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:60 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:105 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:150 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:281 + reg [25:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:162:1014 + assign ROP = ME; +endmodule +module ram_4096x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:60 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:105 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:150 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:281 + reg [25:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:163:1014 + assign ROP = ME; +endmodule +module ram_2048x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:60 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:105 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:150 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:281 + reg [25:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:824 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:844 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:864 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:942 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:164:1014 + assign ROP = ME; +endmodule +module ram_512x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:59 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:104 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:149 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:280 + reg [25:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:165:1013 + assign ROP = ME; +endmodule +module ram_256x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:59 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:104 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:149 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:280 + reg [25:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:166:1013 + assign ROP = ME; +endmodule +module ram_128x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:59 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:104 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:149 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:280 + reg [25:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:823 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:843 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:863 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:941 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:167:1013 + assign ROP = ME; +endmodule +module ram_64x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:58 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:103 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:148 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:279 + reg [25:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:822 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:842 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:862 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:940 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:168:1012 + assign ROP = ME; +endmodule +module ram_32x26 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:58 + input wire [4:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:103 + input wire [25:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:148 + output reg [25:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:279 + reg [25:0] ram_core [31:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:822 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:842 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:862 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:940 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:169:1012 + assign ROP = ME; +endmodule +module ram_32x22 ( + ADR, + D, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:58 + input wire [4:0] ADR; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:103 + input wire [21:0] D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:148 + output reg [21:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:279 + reg [21:0] ram_core [31:0]; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:822 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:842 + ram_core[ADR] <= D; + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:862 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:940 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:170:1012 + assign ROP = ME; +endmodule +module ram_be_8192x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:61 + input wire [12:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:106 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:151 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:282 + reg [141:0] ram_core [8191:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:171:1080 + assign ROP = ME; +endmodule +module ram_be_4096x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:61 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:106 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:151 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:282 + reg [141:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:172:1080 + assign ROP = ME; +endmodule +module ram_be_2048x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:61 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:106 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:151 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:282 + reg [141:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:173:1080 + assign ROP = ME; +endmodule +module ram_be_1024x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:61 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:106 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:151 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:282 + reg [141:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:174:1080 + assign ROP = ME; +endmodule +module ram_be_512x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:60 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:105 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:150 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:281 + reg [141:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:175:1079 + assign ROP = ME; +endmodule +module ram_be_256x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:60 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:105 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:150 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:281 + reg [141:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:176:1079 + assign ROP = ME; +endmodule +module ram_be_128x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:60 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:105 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:150 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:281 + reg [141:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:177:1079 + assign ROP = ME; +endmodule +module ram_be_64x142 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:59 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:104 + input wire [141:0] D; + input wire [141:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:149 + output reg [141:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:280 + reg [141:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:178:1078 + assign ROP = ME; +endmodule +module ram_be_8192x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:61 + input wire [12:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:106 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:151 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:282 + reg [283:0] ram_core [8191:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:179:1080 + assign ROP = ME; +endmodule +module ram_be_4096x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:61 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:106 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:151 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:282 + reg [283:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:180:1080 + assign ROP = ME; +endmodule +module ram_be_2048x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:61 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:106 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:151 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:282 + reg [283:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:181:1080 + assign ROP = ME; +endmodule +module ram_be_1024x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:61 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:106 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:151 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:282 + reg [283:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:182:1080 + assign ROP = ME; +endmodule +module ram_be_512x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:60 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:105 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:150 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:281 + reg [283:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:183:1079 + assign ROP = ME; +endmodule +module ram_be_256x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:60 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:105 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:150 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:281 + reg [283:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:184:1079 + assign ROP = ME; +endmodule +module ram_be_128x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:60 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:105 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:150 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:281 + reg [283:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:185:1079 + assign ROP = ME; +endmodule +module ram_be_64x284 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:59 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:104 + input wire [283:0] D; + input wire [283:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:149 + output reg [283:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:280 + reg [283:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:186:1078 + assign ROP = ME; +endmodule +module ram_be_8192x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:61 + input wire [12:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:106 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:151 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:282 + reg [135:0] ram_core [8191:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:187:1080 + assign ROP = ME; +endmodule +module ram_be_4096x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:61 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:106 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:151 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:282 + reg [135:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:188:1080 + assign ROP = ME; +endmodule +module ram_be_2048x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:61 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:106 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:151 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:282 + reg [135:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:189:1080 + assign ROP = ME; +endmodule +module ram_be_1024x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:61 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:106 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:151 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:282 + reg [135:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:190:1080 + assign ROP = ME; +endmodule +module ram_be_512x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:60 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:105 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:150 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:281 + reg [135:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:191:1079 + assign ROP = ME; +endmodule +module ram_be_256x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:60 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:105 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:150 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:281 + reg [135:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:192:1079 + assign ROP = ME; +endmodule +module ram_be_128x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:60 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:105 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:150 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:281 + reg [135:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:193:1079 + assign ROP = ME; +endmodule +module ram_be_64x136 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:59 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:104 + input wire [135:0] D; + input wire [135:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:149 + output reg [135:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:280 + reg [135:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:194:1078 + assign ROP = ME; +endmodule +module ram_be_8192x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:61 + input wire [12:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:106 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:151 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:282 + reg [271:0] ram_core [8191:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:195:1080 + assign ROP = ME; +endmodule +module ram_be_4096x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:61 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:106 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:151 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:282 + reg [271:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:196:1080 + assign ROP = ME; +endmodule +module ram_be_2048x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:61 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:106 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:151 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:282 + reg [271:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:197:1080 + assign ROP = ME; +endmodule +module ram_be_1024x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:61 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:106 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:151 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:282 + reg [271:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:198:1080 + assign ROP = ME; +endmodule +module ram_be_512x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:60 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:105 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:150 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:281 + reg [271:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:199:1079 + assign ROP = ME; +endmodule +module ram_be_256x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:60 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:105 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:150 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:281 + reg [271:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:200:1079 + assign ROP = ME; +endmodule +module ram_be_128x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:60 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:105 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:150 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:281 + reg [271:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:201:1079 + assign ROP = ME; +endmodule +module ram_be_64x272 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:59 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:104 + input wire [271:0] D; + input wire [271:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:149 + output reg [271:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:280 + reg [271:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:202:1078 + assign ROP = ME; +endmodule +module ram_be_4096x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:60 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:105 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:150 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:281 + reg [51:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:203:1079 + assign ROP = ME; +endmodule +module ram_be_2048x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:60 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:105 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:150 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:281 + reg [51:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:204:1079 + assign ROP = ME; +endmodule +module ram_be_1024x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:60 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:105 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:150 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:281 + reg [51:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:205:1079 + assign ROP = ME; +endmodule +module ram_be_512x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:59 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:104 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:149 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:280 + reg [51:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:206:1078 + assign ROP = ME; +endmodule +module ram_be_256x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:59 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:104 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:149 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:280 + reg [51:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:207:1078 + assign ROP = ME; +endmodule +module ram_be_128x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:59 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:104 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:149 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:280 + reg [51:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:208:1078 + assign ROP = ME; +endmodule +module ram_be_64x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:58 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:103 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:148 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:279 + reg [51:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:855 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:875 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:924 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:1002 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:209:1077 + assign ROP = ME; +endmodule +module ram_be_32x52 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:58 + input wire [4:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:103 + input wire [51:0] D; + input wire [51:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:148 + output reg [51:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:279 + reg [51:0] ram_core [31:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:855 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:875 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:924 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:1002 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:210:1077 + assign ROP = ME; +endmodule +module ram_be_4096x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:61 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:106 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:151 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:282 + reg [103:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:211:1080 + assign ROP = ME; +endmodule +module ram_be_2048x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:61 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:106 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:151 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:282 + reg [103:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:212:1080 + assign ROP = ME; +endmodule +module ram_be_1024x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:61 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:106 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:151 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:198 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:228 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:258 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:288 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:318 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:348 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:378 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:408 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:438 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:468 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:498 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:528 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:558 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:282 + reg [103:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:642 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:858 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:878 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:927 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:1005 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:213:1080 + assign ROP = ME; +endmodule +module ram_be_512x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:60 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:105 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:150 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:281 + reg [103:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:214:1079 + assign ROP = ME; +endmodule +module ram_be_256x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:60 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:105 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:150 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:281 + reg [103:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:215:1079 + assign ROP = ME; +endmodule +module ram_be_128x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:60 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:105 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:150 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:281 + reg [103:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:216:1079 + assign ROP = ME; +endmodule +module ram_be_64x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:59 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:104 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:149 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:280 + reg [103:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:217:1078 + assign ROP = ME; +endmodule +module ram_be_32x104 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:59 + input wire [4:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:104 + input wire [103:0] D; + input wire [103:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:149 + output reg [103:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:280 + reg [103:0] ram_core [31:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:218:1078 + assign ROP = ME; +endmodule +module ram_be_4096x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:60 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:105 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:150 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:281 + reg [43:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:219:1079 + assign ROP = ME; +endmodule +module ram_be_2048x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:60 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:105 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:150 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:281 + reg [43:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:220:1079 + assign ROP = ME; +endmodule +module ram_be_1024x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:60 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:105 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:150 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:281 + reg [43:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:221:1079 + assign ROP = ME; +endmodule +module ram_be_512x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:59 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:104 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:149 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:280 + reg [43:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:222:1078 + assign ROP = ME; +endmodule +module ram_be_256x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:59 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:104 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:149 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:280 + reg [43:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:223:1078 + assign ROP = ME; +endmodule +module ram_be_128x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:59 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:104 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:149 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:280 + reg [43:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:224:1078 + assign ROP = ME; +endmodule +module ram_be_64x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:58 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:103 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:148 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:279 + reg [43:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:855 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:875 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:924 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:1002 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:225:1077 + assign ROP = ME; +endmodule +module ram_be_32x44 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:58 + input wire [4:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:103 + input wire [43:0] D; + input wire [43:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:148 + output reg [43:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:279 + reg [43:0] ram_core [31:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:855 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:875 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:924 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:1002 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:226:1077 + assign ROP = ME; +endmodule +module ram_be_4096x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:60 + input wire [11:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:105 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:150 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:281 + reg [87:0] ram_core [4095:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:227:1079 + assign ROP = ME; +endmodule +module ram_be_2048x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:60 + input wire [10:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:105 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:150 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:281 + reg [87:0] ram_core [2047:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:228:1079 + assign ROP = ME; +endmodule +module ram_be_1024x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:60 + input wire [9:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:105 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:150 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:197 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:227 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:257 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:287 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:317 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:347 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:377 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:407 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:437 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:467 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:497 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:527 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:557 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:281 + reg [87:0] ram_core [1023:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:641 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:857 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:877 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:926 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:1004 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:229:1079 + assign ROP = ME; +endmodule +module ram_be_512x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:59 + input wire [8:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:104 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:149 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:280 + reg [87:0] ram_core [511:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:230:1078 + assign ROP = ME; +endmodule +module ram_be_256x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:59 + input wire [7:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:104 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:149 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:280 + reg [87:0] ram_core [255:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:231:1078 + assign ROP = ME; +endmodule +module ram_be_128x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:59 + input wire [6:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:104 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:149 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:196 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:226 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:256 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:286 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:316 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:346 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:376 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:406 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:436 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:466 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:496 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:526 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:556 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:280 + reg [87:0] ram_core [127:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:640 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:856 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:876 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:925 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:1003 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:232:1078 + assign ROP = ME; +endmodule +module ram_be_64x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:58 + input wire [5:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:103 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:148 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:279 + reg [87:0] ram_core [63:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:855 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:875 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:924 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:1002 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:233:1077 + assign ROP = ME; +endmodule +module ram_be_32x88 ( + ADR, + D, + WEM, + Q, + WE, + ME, + CLK, + TEST1, + RME, + RM, + LS, + DS, + SD, + TEST_RNM, + BC1, + BC2, + ROP +); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:58 + input wire [4:0] ADR; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:103 + input wire [87:0] D; + input wire [87:0] WEM; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:148 + output reg [87:0] Q; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:195 + input wire WE; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:225 + input wire ME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:255 + input wire CLK; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:285 + input wire TEST1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:315 + input wire RME; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:345 + input wire [3:0] RM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:375 + input wire LS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:405 + input wire DS; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:435 + input wire SD; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:465 + input wire TEST_RNM; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:495 + input wire BC1; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:525 + input wire BC2; + // Trace: macro expansion of EL2_LOCAL_RAM_TEST_IO at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:555 + output wire ROP; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:279 + reg [87:0] ram_core [31:0]; + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:639 + always @(posedge CLK) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:855 + if (ME && WE) begin + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:875 + ram_core[ADR] <= (D & WEM) | (~WEM & ram_core[ADR]); + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:924 + Q <= 1'sbx; + end + if (ME && ~WE) + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:1002 + Q <= ram_core[ADR]; + end + // Trace: macro expansion of EL2_RAM_BE at ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/lib/mem_lib.sv:234:1077 + assign ROP = ME; +endmodule +module el2_veer ( + clk, + rst_l, + dbg_rst_l, + rst_vec, + nmi_int, + nmi_vec, + core_rst_l, + active_l2clk, + free_l2clk, + trace_rv_i_insn_ip, + trace_rv_i_address_ip, + trace_rv_i_valid_ip, + trace_rv_i_exception_ip, + trace_rv_i_ecause_ip, + trace_rv_i_interrupt_ip, + trace_rv_i_tval_ip, + dccm_clk_override, + icm_clk_override, + dec_tlu_core_ecc_disable, + i_cpu_halt_req, + i_cpu_run_req, + o_cpu_halt_ack, + o_cpu_halt_status, + o_cpu_run_ack, + o_debug_mode_status, + core_id, + mpc_debug_halt_req, + mpc_debug_run_req, + mpc_reset_run_req, + mpc_debug_halt_ack, + mpc_debug_run_ack, + debug_brkpt_status, + dec_tlu_perfcnt0, + dec_tlu_perfcnt1, + dec_tlu_perfcnt2, + dec_tlu_perfcnt3, + dccm_wren, + dccm_rden, + dccm_wr_addr_lo, + dccm_wr_addr_hi, + dccm_rd_addr_lo, + dccm_rd_addr_hi, + dccm_wr_data_lo, + dccm_wr_data_hi, + dccm_rd_data_lo, + dccm_rd_data_hi, + iccm_rw_addr, + iccm_wren, + iccm_rden, + iccm_wr_size, + iccm_wr_data, + iccm_buf_correct_ecc, + iccm_correction_state, + iccm_rd_data, + iccm_rd_data_ecc, + ic_rw_addr, + ic_tag_valid, + ic_wr_en, + ic_rd_en, + ic_wr_data, + ic_rd_data, + ic_debug_rd_data, + ictag_debug_rd_data, + ic_debug_wr_data, + ic_eccerr, + ic_parerr, + ic_premux_data, + ic_sel_premux_data, + ic_debug_addr, + ic_debug_rd_en, + ic_debug_wr_en, + ic_debug_tag_array, + ic_debug_way, + ic_rd_hit, + ic_tag_perr, + lsu_axi_awvalid, + lsu_axi_awready, + lsu_axi_awid, + lsu_axi_awaddr, + lsu_axi_awregion, + lsu_axi_awlen, + lsu_axi_awsize, + lsu_axi_awburst, + lsu_axi_awlock, + lsu_axi_awcache, + lsu_axi_awprot, + lsu_axi_awqos, + lsu_axi_wvalid, + lsu_axi_wready, + lsu_axi_wdata, + lsu_axi_wstrb, + lsu_axi_wlast, + lsu_axi_bvalid, + lsu_axi_bready, + lsu_axi_bresp, + lsu_axi_bid, + lsu_axi_arvalid, + lsu_axi_arready, + lsu_axi_arid, + lsu_axi_araddr, + lsu_axi_arregion, + lsu_axi_arlen, + lsu_axi_arsize, + lsu_axi_arburst, + lsu_axi_arlock, + lsu_axi_arcache, + lsu_axi_arprot, + lsu_axi_arqos, + lsu_axi_rvalid, + lsu_axi_rready, + lsu_axi_rid, + lsu_axi_rdata, + lsu_axi_rresp, + lsu_axi_rlast, + ifu_axi_awvalid, + ifu_axi_awready, + ifu_axi_awid, + ifu_axi_awaddr, + ifu_axi_awregion, + ifu_axi_awlen, + ifu_axi_awsize, + ifu_axi_awburst, + ifu_axi_awlock, + ifu_axi_awcache, + ifu_axi_awprot, + ifu_axi_awqos, + ifu_axi_wvalid, + ifu_axi_wready, + ifu_axi_wdata, + ifu_axi_wstrb, + ifu_axi_wlast, + ifu_axi_bvalid, + ifu_axi_bready, + ifu_axi_bresp, + ifu_axi_bid, + ifu_axi_arvalid, + ifu_axi_arready, + ifu_axi_arid, + ifu_axi_araddr, + ifu_axi_arregion, + ifu_axi_arlen, + ifu_axi_arsize, + ifu_axi_arburst, + ifu_axi_arlock, + ifu_axi_arcache, + ifu_axi_arprot, + ifu_axi_arqos, + ifu_axi_rvalid, + ifu_axi_rready, + ifu_axi_rid, + ifu_axi_rdata, + ifu_axi_rresp, + ifu_axi_rlast, + sb_axi_awvalid, + sb_axi_awready, + sb_axi_awid, + sb_axi_awaddr, + sb_axi_awregion, + sb_axi_awlen, + sb_axi_awsize, + sb_axi_awburst, + sb_axi_awlock, + sb_axi_awcache, + sb_axi_awprot, + sb_axi_awqos, + sb_axi_wvalid, + sb_axi_wready, + sb_axi_wdata, + sb_axi_wstrb, + sb_axi_wlast, + sb_axi_bvalid, + sb_axi_bready, + sb_axi_bresp, + sb_axi_bid, + sb_axi_arvalid, + sb_axi_arready, + sb_axi_arid, + sb_axi_araddr, + sb_axi_arregion, + sb_axi_arlen, + sb_axi_arsize, + sb_axi_arburst, + sb_axi_arlock, + sb_axi_arcache, + sb_axi_arprot, + sb_axi_arqos, + sb_axi_rvalid, + sb_axi_rready, + sb_axi_rid, + sb_axi_rdata, + sb_axi_rresp, + sb_axi_rlast, + dma_axi_awvalid, + dma_axi_awready, + dma_axi_awid, + dma_axi_awaddr, + dma_axi_awsize, + dma_axi_awprot, + dma_axi_awlen, + dma_axi_awburst, + dma_axi_wvalid, + dma_axi_wready, + dma_axi_wdata, + dma_axi_wstrb, + dma_axi_wlast, + dma_axi_bvalid, + dma_axi_bready, + dma_axi_bresp, + dma_axi_bid, + dma_axi_arvalid, + dma_axi_arready, + dma_axi_arid, + dma_axi_araddr, + dma_axi_arsize, + dma_axi_arprot, + dma_axi_arlen, + dma_axi_arburst, + dma_axi_rvalid, + dma_axi_rready, + dma_axi_rid, + dma_axi_rdata, + dma_axi_rresp, + dma_axi_rlast, + haddr, + hburst, + hmastlock, + hprot, + hsize, + htrans, + hwrite, + hrdata, + hready, + hresp, + lsu_haddr, + lsu_hburst, + lsu_hmastlock, + lsu_hprot, + lsu_hsize, + lsu_htrans, + lsu_hwrite, + lsu_hwdata, + lsu_hrdata, + lsu_hready, + lsu_hresp, + sb_haddr, + sb_hburst, + sb_hmastlock, + sb_hprot, + sb_hsize, + sb_htrans, + sb_hwrite, + sb_hwdata, + sb_hrdata, + sb_hready, + sb_hresp, + dma_hsel, + dma_haddr, + dma_hburst, + dma_hmastlock, + dma_hprot, + dma_hsize, + dma_htrans, + dma_hwrite, + dma_hwdata, + dma_hreadyin, + dma_hrdata, + dma_hreadyout, + dma_hresp, + lsu_bus_clk_en, + ifu_bus_clk_en, + dbg_bus_clk_en, + dma_bus_clk_en, + dmi_reg_en, + dmi_reg_addr, + dmi_reg_wr_en, + dmi_reg_wdata, + dmi_reg_rdata, + extintsrc_req, + timer_int, + soft_int, + scan_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:29:4 + input wire clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:30:4 + input wire rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:31:4 + input wire dbg_rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:32:4 + input wire [31:1] rst_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:33:4 + input wire nmi_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:34:4 + input wire [31:1] nmi_vec; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:35:4 + output wire core_rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:37:4 + output wire active_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:38:4 + output wire free_l2clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:40:4 + output wire [31:0] trace_rv_i_insn_ip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:41:4 + output wire [31:0] trace_rv_i_address_ip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:42:4 + output wire trace_rv_i_valid_ip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:43:4 + output wire trace_rv_i_exception_ip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:44:4 + output wire [4:0] trace_rv_i_ecause_ip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:45:4 + output wire trace_rv_i_interrupt_ip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:46:4 + output wire [31:0] trace_rv_i_tval_ip; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:49:4 + output wire dccm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:50:4 + output wire icm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:51:4 + output wire dec_tlu_core_ecc_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:54:4 + input wire i_cpu_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:55:4 + input wire i_cpu_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:56:4 + output wire o_cpu_halt_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:57:4 + output wire o_cpu_halt_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:58:4 + output wire o_cpu_run_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:59:4 + output wire o_debug_mode_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:61:4 + input wire [31:4] core_id; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:64:4 + input wire mpc_debug_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:65:4 + input wire mpc_debug_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:66:4 + input wire mpc_reset_run_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:67:4 + output wire mpc_debug_halt_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:68:4 + output wire mpc_debug_run_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:69:4 + output wire debug_brkpt_status; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:71:4 + output wire dec_tlu_perfcnt0; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:72:4 + output wire dec_tlu_perfcnt1; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:73:4 + output wire dec_tlu_perfcnt2; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:74:4 + output wire dec_tlu_perfcnt3; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:77:4 + output wire dccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:78:4 + output wire dccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:79:4 + output wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:80:4 + output wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:81:4 + output wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:82:4 + output wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:83:4 + output wire [pt[1360-:10] - 1:0] dccm_wr_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:84:4 + output wire [pt[1360-:10] - 1:0] dccm_wr_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:86:4 + input wire [pt[1360-:10] - 1:0] dccm_rd_data_lo; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:87:4 + input wire [pt[1360-:10] - 1:0] dccm_rd_data_hi; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:90:4 + output wire [pt[936-:9] - 1:1] iccm_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:91:4 + output wire iccm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:92:4 + output wire iccm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:93:4 + output wire [2:0] iccm_wr_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:94:4 + output wire [77:0] iccm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:95:4 + output wire iccm_buf_correct_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:96:4 + output wire iccm_correction_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:98:4 + input wire [63:0] iccm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:99:4 + input wire [77:0] iccm_rd_data_ecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:102:4 + output wire [31:1] ic_rw_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:103:4 + output wire [pt[1060-:7] - 1:0] ic_tag_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:104:4 + output wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:105:4 + output wire ic_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:107:4 + output wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:108:4 + input wire [63:0] ic_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:109:4 + input wire [70:0] ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:110:4 + input wire [25:0] ictag_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:111:4 + output wire [70:0] ic_debug_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:113:4 + input wire [pt[1189-:7] - 1:0] ic_eccerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:114:4 + input wire [pt[1189-:7] - 1:0] ic_parerr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:115:4 + output wire [63:0] ic_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:116:4 + output wire ic_sel_premux_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:119:4 + output wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:120:4 + output wire ic_debug_rd_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:121:4 + output wire ic_debug_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:122:4 + output wire ic_debug_tag_array; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:123:4 + output wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:127:4 + input wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:128:4 + input wire ic_tag_perr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:132:4 + output wire lsu_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:133:4 + input wire lsu_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:134:4 + output wire [pt[181-:8] - 1:0] lsu_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:135:4 + output wire [31:0] lsu_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:136:4 + output wire [3:0] lsu_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:137:4 + output wire [7:0] lsu_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:138:4 + output wire [2:0] lsu_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:139:4 + output wire [1:0] lsu_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:140:4 + output wire lsu_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:141:4 + output wire [3:0] lsu_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:142:4 + output wire [2:0] lsu_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:143:4 + output wire [3:0] lsu_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:145:4 + output wire lsu_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:146:4 + input wire lsu_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:147:4 + output wire [63:0] lsu_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:148:4 + output wire [7:0] lsu_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:149:4 + output wire lsu_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:151:4 + input wire lsu_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:152:4 + output wire lsu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:153:4 + input wire [1:0] lsu_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:154:4 + input wire [pt[181-:8] - 1:0] lsu_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:157:4 + output wire lsu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:158:4 + input wire lsu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:159:4 + output wire [pt[181-:8] - 1:0] lsu_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:160:4 + output wire [31:0] lsu_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:161:4 + output wire [3:0] lsu_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:162:4 + output wire [7:0] lsu_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:163:4 + output wire [2:0] lsu_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:164:4 + output wire [1:0] lsu_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:165:4 + output wire lsu_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:166:4 + output wire [3:0] lsu_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:167:4 + output wire [2:0] lsu_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:168:4 + output wire [3:0] lsu_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:170:4 + input wire lsu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:171:4 + output wire lsu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:172:4 + input wire [pt[181-:8] - 1:0] lsu_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:173:4 + input wire [63:0] lsu_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:174:4 + input wire [1:0] lsu_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:175:4 + input wire lsu_axi_rlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:179:4 + output wire ifu_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:180:4 + input wire ifu_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:181:4 + output wire [pt[826-:8] - 1:0] ifu_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:182:4 + output wire [31:0] ifu_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:183:4 + output wire [3:0] ifu_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:184:4 + output wire [7:0] ifu_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:185:4 + output wire [2:0] ifu_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:186:4 + output wire [1:0] ifu_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:187:4 + output wire ifu_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:188:4 + output wire [3:0] ifu_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:189:4 + output wire [2:0] ifu_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:190:4 + output wire [3:0] ifu_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:192:4 + output wire ifu_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:193:4 + input wire ifu_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:194:4 + output wire [63:0] ifu_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:195:4 + output wire [7:0] ifu_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:196:4 + output wire ifu_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:198:4 + input wire ifu_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:199:4 + output wire ifu_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:200:4 + input wire [1:0] ifu_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:201:4 + input wire [pt[826-:8] - 1:0] ifu_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:204:4 + output wire ifu_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:205:4 + input wire ifu_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:206:4 + output wire [pt[826-:8] - 1:0] ifu_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:207:4 + output wire [31:0] ifu_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:208:4 + output wire [3:0] ifu_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:209:4 + output wire [7:0] ifu_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:210:4 + output wire [2:0] ifu_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:211:4 + output wire [1:0] ifu_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:212:4 + output wire ifu_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:213:4 + output wire [3:0] ifu_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:214:4 + output wire [2:0] ifu_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:215:4 + output wire [3:0] ifu_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:217:4 + input wire ifu_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:218:4 + output wire ifu_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:219:4 + input wire [pt[826-:8] - 1:0] ifu_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:220:4 + input wire [63:0] ifu_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:221:4 + input wire [1:0] ifu_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:222:4 + input wire ifu_axi_rlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:226:4 + output wire sb_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:227:4 + input wire sb_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:228:4 + output wire [pt[12-:8] - 1:0] sb_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:229:4 + output wire [31:0] sb_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:230:4 + output wire [3:0] sb_axi_awregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:231:4 + output wire [7:0] sb_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:232:4 + output wire [2:0] sb_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:233:4 + output wire [1:0] sb_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:234:4 + output wire sb_axi_awlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:235:4 + output wire [3:0] sb_axi_awcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:236:4 + output wire [2:0] sb_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:237:4 + output wire [3:0] sb_axi_awqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:239:4 + output wire sb_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:240:4 + input wire sb_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:241:4 + output wire [63:0] sb_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:242:4 + output wire [7:0] sb_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:243:4 + output wire sb_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:245:4 + input wire sb_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:246:4 + output wire sb_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:247:4 + input wire [1:0] sb_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:248:4 + input wire [pt[12-:8] - 1:0] sb_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:251:4 + output wire sb_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:252:4 + input wire sb_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:253:4 + output wire [pt[12-:8] - 1:0] sb_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:254:4 + output wire [31:0] sb_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:255:4 + output wire [3:0] sb_axi_arregion; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:256:4 + output wire [7:0] sb_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:257:4 + output wire [2:0] sb_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:258:4 + output wire [1:0] sb_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:259:4 + output wire sb_axi_arlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:260:4 + output wire [3:0] sb_axi_arcache; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:261:4 + output wire [2:0] sb_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:262:4 + output wire [3:0] sb_axi_arqos; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:264:4 + input wire sb_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:265:4 + output wire sb_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:266:4 + input wire [pt[12-:8] - 1:0] sb_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:267:4 + input wire [63:0] sb_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:268:4 + input wire [1:0] sb_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:269:4 + input wire sb_axi_rlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:273:4 + input wire dma_axi_awvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:274:4 + output wire dma_axi_awready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:275:4 + input wire [pt[1235-:8] - 1:0] dma_axi_awid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:276:4 + input wire [31:0] dma_axi_awaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:277:4 + input wire [2:0] dma_axi_awsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:278:4 + input wire [2:0] dma_axi_awprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:279:4 + input wire [7:0] dma_axi_awlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:280:4 + input wire [1:0] dma_axi_awburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:283:4 + input wire dma_axi_wvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:284:4 + output wire dma_axi_wready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:285:4 + input wire [63:0] dma_axi_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:286:4 + input wire [7:0] dma_axi_wstrb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:287:4 + input wire dma_axi_wlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:289:4 + output wire dma_axi_bvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:290:4 + input wire dma_axi_bready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:291:4 + output wire [1:0] dma_axi_bresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:292:4 + output wire [pt[1235-:8] - 1:0] dma_axi_bid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:295:4 + input wire dma_axi_arvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:296:4 + output wire dma_axi_arready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:297:4 + input wire [pt[1235-:8] - 1:0] dma_axi_arid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:298:4 + input wire [31:0] dma_axi_araddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:299:4 + input wire [2:0] dma_axi_arsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:300:4 + input wire [2:0] dma_axi_arprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:301:4 + input wire [7:0] dma_axi_arlen; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:302:4 + input wire [1:0] dma_axi_arburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:304:4 + output wire dma_axi_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:305:4 + input wire dma_axi_rready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:306:4 + output wire [pt[1235-:8] - 1:0] dma_axi_rid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:307:4 + output wire [63:0] dma_axi_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:308:4 + output wire [1:0] dma_axi_rresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:309:4 + output wire dma_axi_rlast; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:313:4 + output wire [31:0] haddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:314:4 + output wire [2:0] hburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:315:4 + output wire hmastlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:316:4 + output wire [3:0] hprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:317:4 + output wire [2:0] hsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:318:4 + output wire [1:0] htrans; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:319:4 + output wire hwrite; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:321:4 + input wire [63:0] hrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:322:4 + input wire hready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:323:4 + input wire hresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:326:4 + output wire [31:0] lsu_haddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:327:4 + output wire [2:0] lsu_hburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:328:4 + output wire lsu_hmastlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:329:4 + output wire [3:0] lsu_hprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:330:4 + output wire [2:0] lsu_hsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:331:4 + output wire [1:0] lsu_htrans; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:332:4 + output wire lsu_hwrite; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:333:4 + output wire [63:0] lsu_hwdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:335:4 + input wire [63:0] lsu_hrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:336:4 + input wire lsu_hready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:337:4 + input wire lsu_hresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:340:4 + output wire [31:0] sb_haddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:341:4 + output wire [2:0] sb_hburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:342:4 + output wire sb_hmastlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:343:4 + output wire [3:0] sb_hprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:344:4 + output wire [2:0] sb_hsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:345:4 + output wire [1:0] sb_htrans; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:346:4 + output wire sb_hwrite; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:347:4 + output wire [63:0] sb_hwdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:349:4 + input wire [63:0] sb_hrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:350:4 + input wire sb_hready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:351:4 + input wire sb_hresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:354:4 + input wire dma_hsel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:355:4 + input wire [31:0] dma_haddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:356:4 + input wire [2:0] dma_hburst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:357:4 + input wire dma_hmastlock; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:358:4 + input wire [3:0] dma_hprot; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:359:4 + input wire [2:0] dma_hsize; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:360:4 + input wire [1:0] dma_htrans; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:361:4 + input wire dma_hwrite; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:362:4 + input wire [63:0] dma_hwdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:363:4 + input wire dma_hreadyin; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:365:4 + output wire [63:0] dma_hrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:366:4 + output wire dma_hreadyout; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:367:4 + output wire dma_hresp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:369:4 + input wire lsu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:370:4 + input wire ifu_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:371:4 + input wire dbg_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:372:4 + input wire dma_bus_clk_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:374:4 + input wire dmi_reg_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:375:4 + input wire [6:0] dmi_reg_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:376:4 + input wire dmi_reg_wr_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:377:4 + input wire [31:0] dmi_reg_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:378:4 + output wire [31:0] dmi_reg_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:380:4 + input wire [pt[56-:12]:1] extintsrc_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:381:4 + input wire timer_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:382:4 + input wire soft_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:383:4 + input wire scan_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:389:4 + wire [63:0] hwdata_nc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:394:4 + wire ifu_pmu_instr_aligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:395:4 + wire ifu_ic_error_start; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:396:4 + wire ifu_iccm_rd_ecc_single_err; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:398:4 + wire lsu_axi_awready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:399:4 + wire lsu_axi_wready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:400:4 + wire lsu_axi_bvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:401:4 + wire lsu_axi_bready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:402:4 + wire [1:0] lsu_axi_bresp_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:403:4 + wire [pt[181-:8] - 1:0] lsu_axi_bid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:404:4 + wire lsu_axi_arready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:405:4 + wire lsu_axi_rvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:406:4 + wire [pt[181-:8] - 1:0] lsu_axi_rid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:407:4 + wire [63:0] lsu_axi_rdata_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:408:4 + wire [1:0] lsu_axi_rresp_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:409:4 + wire lsu_axi_rlast_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:411:4 + wire lsu_axi_awready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:412:4 + wire lsu_axi_wready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:413:4 + wire lsu_axi_bvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:414:4 + wire lsu_axi_bready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:415:4 + wire [1:0] lsu_axi_bresp_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:416:4 + wire [pt[181-:8] - 1:0] lsu_axi_bid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:417:4 + wire lsu_axi_arready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:418:4 + wire lsu_axi_rvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:419:4 + wire [pt[181-:8] - 1:0] lsu_axi_rid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:420:4 + wire [63:0] lsu_axi_rdata_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:421:4 + wire [1:0] lsu_axi_rresp_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:422:4 + wire lsu_axi_rlast_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:424:4 + wire ifu_axi_awready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:425:4 + wire ifu_axi_wready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:426:4 + wire ifu_axi_bvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:427:4 + wire ifu_axi_bready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:428:4 + wire [1:0] ifu_axi_bresp_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:429:4 + wire [pt[826-:8] - 1:0] ifu_axi_bid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:430:4 + wire ifu_axi_arready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:431:4 + wire ifu_axi_rvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:432:4 + wire [pt[826-:8] - 1:0] ifu_axi_rid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:433:4 + wire [63:0] ifu_axi_rdata_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:434:4 + wire [1:0] ifu_axi_rresp_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:435:4 + wire ifu_axi_rlast_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:437:4 + wire ifu_axi_awready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:438:4 + wire ifu_axi_wready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:439:4 + wire ifu_axi_bvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:440:4 + wire ifu_axi_bready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:441:4 + wire [1:0] ifu_axi_bresp_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:442:4 + wire [pt[826-:8] - 1:0] ifu_axi_bid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:443:4 + wire ifu_axi_arready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:444:4 + wire ifu_axi_rvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:445:4 + wire [pt[826-:8] - 1:0] ifu_axi_rid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:446:4 + wire [63:0] ifu_axi_rdata_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:447:4 + wire [1:0] ifu_axi_rresp_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:448:4 + wire ifu_axi_rlast_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:450:4 + wire sb_axi_awready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:451:4 + wire sb_axi_wready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:452:4 + wire sb_axi_bvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:453:4 + wire sb_axi_bready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:454:4 + wire [1:0] sb_axi_bresp_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:455:4 + wire [pt[12-:8] - 1:0] sb_axi_bid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:456:4 + wire sb_axi_arready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:457:4 + wire sb_axi_rvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:458:4 + wire [pt[12-:8] - 1:0] sb_axi_rid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:459:4 + wire [63:0] sb_axi_rdata_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:460:4 + wire [1:0] sb_axi_rresp_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:461:4 + wire sb_axi_rlast_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:463:4 + wire sb_axi_awready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:464:4 + wire sb_axi_wready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:465:4 + wire sb_axi_bvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:466:4 + wire sb_axi_bready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:467:4 + wire [1:0] sb_axi_bresp_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:468:4 + wire [pt[12-:8] - 1:0] sb_axi_bid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:469:4 + wire sb_axi_arready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:470:4 + wire sb_axi_rvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:471:4 + wire [pt[12-:8] - 1:0] sb_axi_rid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:472:4 + wire [63:0] sb_axi_rdata_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:473:4 + wire [1:0] sb_axi_rresp_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:474:4 + wire sb_axi_rlast_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:476:4 + wire dma_axi_awvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:477:4 + wire [pt[1235-:8] - 1:0] dma_axi_awid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:478:4 + wire [31:0] dma_axi_awaddr_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:479:4 + wire [2:0] dma_axi_awsize_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:480:4 + wire [2:0] dma_axi_awprot_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:481:4 + wire [7:0] dma_axi_awlen_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:482:4 + wire [1:0] dma_axi_awburst_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:483:4 + wire dma_axi_wvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:484:4 + wire [63:0] dma_axi_wdata_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:485:4 + wire [7:0] dma_axi_wstrb_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:486:4 + wire dma_axi_wlast_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:487:4 + wire dma_axi_bready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:488:4 + wire dma_axi_arvalid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:489:4 + wire [pt[1235-:8] - 1:0] dma_axi_arid_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:490:4 + wire [31:0] dma_axi_araddr_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:491:4 + wire [2:0] dma_axi_arsize_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:492:4 + wire [2:0] dma_axi_arprot_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:493:4 + wire [7:0] dma_axi_arlen_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:494:4 + wire [1:0] dma_axi_arburst_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:495:4 + wire dma_axi_rready_ahb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:497:4 + wire dma_axi_awvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:498:4 + wire [pt[1235-:8] - 1:0] dma_axi_awid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:499:4 + wire [31:0] dma_axi_awaddr_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:500:4 + wire [2:0] dma_axi_awsize_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:501:4 + wire [2:0] dma_axi_awprot_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:502:4 + wire [7:0] dma_axi_awlen_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:503:4 + wire [1:0] dma_axi_awburst_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:504:4 + wire dma_axi_wvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:505:4 + wire [63:0] dma_axi_wdata_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:506:4 + wire [7:0] dma_axi_wstrb_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:507:4 + wire dma_axi_wlast_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:508:4 + wire dma_axi_bready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:509:4 + wire dma_axi_arvalid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:510:4 + wire [pt[1235-:8] - 1:0] dma_axi_arid_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:511:4 + wire [31:0] dma_axi_araddr_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:512:4 + wire [2:0] dma_axi_arsize_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:513:4 + wire [2:0] dma_axi_arprot_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:514:4 + wire [7:0] dma_axi_arlen_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:515:4 + wire [1:0] dma_axi_arburst_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:516:4 + wire dma_axi_rready_int; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:520:4 + wire [70:0] ifu_ic_debug_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:521:4 + wire ifu_ic_debug_rd_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:522:4 + // removed localparam type el2_pkg_el2_cache_debug_pkt_t + wire [89:0] dec_tlu_ic_diag_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:525:4 + wire dec_i0_rs1_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:526:4 + wire dec_i0_rs2_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:527:4 + wire [31:0] gpr_i0_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:528:4 + wire [31:0] gpr_i0_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:530:4 + wire [31:0] dec_i0_result_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:531:4 + wire [31:0] exu_i0_result_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:532:4 + wire [31:1] exu_i0_pc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:533:4 + wire [31:1] exu_npc_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:535:4 + // removed localparam type el2_pkg_el2_alu_pkt_t + wire [41:0] i0_ap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:538:4 + // removed localparam type el2_pkg_el2_trigger_pkt_t + wire [151:0] trigger_pkt_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:539:4 + wire [3:0] lsu_trigger_match_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:542:4 + wire [31:0] dec_i0_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:543:4 + wire [12:1] dec_i0_br_immed_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:544:4 + wire dec_i0_select_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:546:4 + wire [31:1] dec_i0_pc_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:547:4 + wire [3:0] dec_i0_rs1_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:548:4 + wire [3:0] dec_i0_rs2_bypass_en_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:550:4 + wire dec_i0_alu_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:551:4 + wire dec_i0_branch_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:553:4 + wire ifu_miss_state_idle; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:554:4 + wire dec_tlu_flush_noredir_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:555:4 + wire dec_tlu_flush_leak_one_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:556:4 + wire dec_tlu_flush_err_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:557:4 + wire ifu_i0_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:558:4 + wire [31:0] ifu_i0_instr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:559:4 + wire [31:1] ifu_i0_pc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:561:4 + wire exu_flush_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:563:4 + wire [31:1] exu_flush_path_final; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:565:4 + wire [31:0] exu_lsu_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:566:4 + wire [31:0] exu_lsu_rs2_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:569:4 + // removed localparam type el2_pkg_el2_lsu_pkt_t + wire [13:0] lsu_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:570:4 + wire dec_qual_lsu_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:572:4 + wire dec_lsu_valid_raw_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:573:4 + wire [11:0] dec_lsu_offset_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:575:4 + wire [31:0] lsu_result_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:576:4 + wire [31:0] lsu_result_corr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:577:4 + wire lsu_single_ecc_error_incr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:578:4 + // removed localparam type el2_pkg_el2_lsu_error_pkt_t + wire [39:0] lsu_error_pkt_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:579:4 + wire lsu_imprecise_error_load_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:580:4 + wire lsu_imprecise_error_store_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:581:4 + wire [31:0] lsu_imprecise_error_addr_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:582:4 + wire lsu_load_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:583:4 + wire lsu_store_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:584:4 + wire lsu_idle_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:585:4 + wire lsu_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:588:4 + wire [31:1] lsu_fir_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:589:4 + wire [1:0] lsu_fir_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:592:4 + wire lsu_nonblock_load_valid_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:593:4 + wire [pt[164-:7] - 1:0] lsu_nonblock_load_tag_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:594:4 + wire lsu_nonblock_load_inv_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:595:4 + wire [pt[164-:7] - 1:0] lsu_nonblock_load_inv_tag_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:596:4 + wire lsu_nonblock_load_data_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:597:4 + wire [pt[164-:7] - 1:0] lsu_nonblock_load_data_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:598:4 + wire [31:0] lsu_nonblock_load_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:600:4 + wire dec_csr_ren_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:601:4 + wire [31:0] dec_csr_rddata_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:603:4 + wire [31:0] exu_csr_rs1_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:605:4 + wire dec_tlu_i0_commit_cmt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:606:4 + wire dec_tlu_flush_lower_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:607:4 + wire dec_tlu_flush_lower_wb; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:608:4 + wire dec_tlu_i0_kill_writeb_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:609:4 + wire dec_tlu_fence_i_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:611:4 + wire [31:1] dec_tlu_flush_path_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:612:4 + wire [31:0] dec_tlu_mrac_ff; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:614:4 + wire ifu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:616:4 + // removed localparam type el2_pkg_el2_mul_pkt_t + wire [22:0] mul_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:618:4 + // removed localparam type el2_pkg_el2_div_pkt_t + wire [2:0] div_p; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:619:4 + wire dec_div_cancel; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:621:4 + wire [31:0] exu_div_result; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:622:4 + wire exu_div_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:624:4 + wire dec_i0_decode_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:627:4 + wire [31:1] pred_correct_npc_x; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:629:4 + // removed localparam type el2_pkg_el2_br_tlu_pkt_t + wire [6:0] dec_tlu_br0_r_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:631:4 + // removed localparam type el2_pkg_el2_predict_pkt_t + wire [55:0] exu_mp_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:632:4 + wire [pt[2236-:8] - 1:0] exu_mp_eghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:633:4 + wire [pt[2236-:8] - 1:0] exu_mp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:634:4 + wire [pt[2172-:9]:pt[2163-:6]] exu_mp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:635:4 + wire [pt[2139-:9] - 1:0] exu_mp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:637:4 + wire [pt[2236-:8] - 1:0] exu_i0_br_fghr_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:638:4 + wire [1:0] exu_i0_br_hist_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:639:4 + wire exu_i0_br_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:640:4 + wire exu_i0_br_start_error_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:641:4 + wire exu_i0_br_valid_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:642:4 + wire exu_i0_br_mp_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:643:4 + wire exu_i0_br_middle_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:645:4 + wire exu_i0_br_way_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:647:4 + wire [pt[2172-:9]:pt[2163-:6]] exu_i0_br_index_r; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:649:4 + wire dma_dccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:650:4 + wire dma_iccm_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:651:4 + wire [2:0] dma_mem_tag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:652:4 + wire [31:0] dma_mem_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:653:4 + wire [2:0] dma_mem_sz; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:654:4 + wire dma_mem_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:655:4 + wire [63:0] dma_mem_wdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:657:4 + wire dccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:658:4 + wire dccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:659:4 + wire [2:0] dccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:660:4 + wire [63:0] dccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:661:4 + wire iccm_dma_rvalid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:662:4 + wire iccm_dma_ecc_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:663:4 + wire [2:0] iccm_dma_rtag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:664:4 + wire [63:0] iccm_dma_rdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:666:4 + wire dma_dccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:667:4 + wire dma_iccm_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:668:4 + wire dccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:669:4 + wire iccm_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:671:4 + wire dma_pmu_dccm_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:672:4 + wire dma_pmu_dccm_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:673:4 + wire dma_pmu_any_read; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:674:4 + wire dma_pmu_any_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:676:4 + wire ifu_i0_icaf; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:677:4 + wire [1:0] ifu_i0_icaf_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:680:4 + wire ifu_i0_icaf_second; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:681:4 + wire ifu_i0_dbecc; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:682:4 + wire iccm_dma_sb_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:684:4 + // removed localparam type el2_pkg_el2_br_pkt_t + wire [50:0] i0_brp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:685:4 + wire [pt[2172-:9]:pt[2163-:6]] ifu_i0_bp_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:686:4 + wire [pt[2236-:8] - 1:0] ifu_i0_bp_fghr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:687:4 + wire [pt[2139-:9] - 1:0] ifu_i0_bp_btag; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:689:4 + wire [$clog2(pt[2061-:14]) - 1:0] ifu_i0_fa_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:690:4 + wire [$clog2(pt[2061-:14]) - 1:0] dec_fa_error_index; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:693:4 + wire [55:0] dec_i0_predict_p_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:695:4 + wire [pt[2236-:8] - 1:0] i0_predict_fghr_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:696:4 + wire [pt[2172-:9]:pt[2163-:6]] i0_predict_index_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:697:4 + wire [pt[2139-:9] - 1:0] i0_predict_btag_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:700:4 + wire picm_wren; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:701:4 + wire picm_rden; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:702:4 + wire picm_mken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:703:4 + wire [31:0] picm_rdaddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:704:4 + wire [31:0] picm_wraddr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:705:4 + wire [31:0] picm_wr_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:706:4 + wire [31:0] picm_rd_data; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:709:4 + wire dec_tlu_external_ldfwd_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:710:4 + wire dec_tlu_bpred_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:711:4 + wire dec_tlu_wb_coalescing_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:712:4 + wire dec_tlu_sideeffect_posted_disable; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:713:4 + wire [2:0] dec_tlu_dma_qos_prty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:716:4 + wire dec_tlu_misc_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:717:4 + wire dec_tlu_ifu_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:718:4 + wire dec_tlu_lsu_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:719:4 + wire dec_tlu_bus_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:720:4 + wire dec_tlu_pic_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:721:4 + wire dec_tlu_dccm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:722:4 + wire dec_tlu_icm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:724:4 + wire dec_tlu_picio_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:726:4 + assign dccm_clk_override = dec_tlu_dccm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:727:4 + assign icm_clk_override = dec_tlu_icm_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:731:4 + wire [31:0] dbg_cmd_addr; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:732:4 + wire [31:0] dbg_cmd_wrdata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:733:4 + wire dbg_cmd_valid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:734:4 + wire dbg_cmd_write; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:735:4 + wire [1:0] dbg_cmd_type; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:736:4 + wire [1:0] dbg_cmd_size; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:737:4 + wire dbg_halt_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:738:4 + wire dbg_resume_req; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:739:4 + wire dbg_core_rst_l; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:741:4 + wire core_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:742:4 + wire core_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:743:4 + wire [31:0] core_dbg_rddata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:745:4 + wire dma_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:746:4 + wire dma_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:747:4 + wire [31:0] dma_dbg_rddata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:749:4 + wire dbg_dma_bubble; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:750:4 + wire dma_dbg_ready; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:752:4 + wire [31:0] dec_dbg_rddata; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:753:4 + wire dec_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:754:4 + wire dec_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:755:4 + wire dec_tlu_mpc_halted_only; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:756:4 + wire dec_tlu_dbg_halted; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:757:4 + wire dec_tlu_resume_ack; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:758:4 + wire dec_tlu_debug_mode; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:759:4 + wire dec_debug_wdata_rs1_d; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:760:4 + wire dec_tlu_force_halt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:762:4 + wire [1:0] dec_data_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:763:4 + wire [1:0] dec_ctl_en; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:766:4 + wire exu_pmu_i0_br_misp; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:767:4 + wire exu_pmu_i0_br_ataken; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:768:4 + wire exu_pmu_i0_pc4; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:770:4 + wire lsu_pmu_load_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:771:4 + wire lsu_pmu_store_external_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:772:4 + wire lsu_pmu_misaligned_m; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:773:4 + wire lsu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:774:4 + wire lsu_pmu_bus_misaligned; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:775:4 + wire lsu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:776:4 + wire lsu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:778:4 + wire ifu_pmu_fetch_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:779:4 + wire ifu_pmu_ic_miss; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:780:4 + wire ifu_pmu_ic_hit; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:781:4 + wire ifu_pmu_bus_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:782:4 + wire ifu_pmu_bus_busy; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:783:4 + wire ifu_pmu_bus_trxn; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:785:4 + wire active_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:786:4 + wire free_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:787:4 + wire active_clk; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:788:4 + wire dec_pause_state_cg; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:790:4 + wire lsu_nonblock_load_data_error; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:792:4 + wire [15:0] ifu_i0_cinst; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:795:4 + wire [31:2] dec_tlu_meihap; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:796:4 + wire dec_extint_stall; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:798:4 + // removed localparam type el2_pkg_el2_trace_pkt_t + wire [103:0] trace_rv_trace_pkt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:801:4 + wire lsu_fastint_stall_any; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:803:4 + wire [7:0] pic_claimid; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:804:4 + wire [3:0] pic_pl; + wire [3:0] dec_tlu_meicurpl; + wire [3:0] dec_tlu_meipt; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:805:4 + wire mexintpend; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:806:4 + wire mhwakeup; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:808:4 + wire dma_active; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:811:4 + wire pause_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:812:4 + wire halt_state; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:814:4 + wire dec_tlu_core_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:816:4 + assign pause_state = (dec_pause_state_cg & ~(dma_active | lsu_active)) & dec_tlu_core_empty; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:818:4 + assign halt_state = o_cpu_halt_status & ~(dma_active | lsu_active); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:821:4 + assign active_state = ((~(halt_state | pause_state) | dec_tlu_flush_lower_r) | dec_tlu_flush_lower_wb) | dec_tlu_misc_clk_override; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:823:4 + rvoclkhdr free_cg2( + .clk(clk), + .en(1'b1), + .l1clk(free_l2clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:824:4 + rvoclkhdr active_cg2( + .clk(clk), + .en(active_state), + .l1clk(active_l2clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:827:4 + rvoclkhdr free_cg1( + .clk(free_l2clk), + .en(1'b1), + .l1clk(free_clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:828:4 + rvoclkhdr active_cg1( + .clk(active_l2clk), + .en(1'b1), + .l1clk(active_clk), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:831:4 + assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:832:4 + assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:833:4 + assign core_dbg_rddata[31:0] = (dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:835:4 + el2_dbg #(.pt(pt)) dbg( + .rst_l(core_rst_l), + .clk(free_l2clk), + .clk_override(dec_tlu_misc_clk_override), + .sb_axi_awready(sb_axi_awready_int), + .sb_axi_wready(sb_axi_wready_int), + .sb_axi_bvalid(sb_axi_bvalid_int), + .sb_axi_bresp(sb_axi_bresp_int[1:0]), + .sb_axi_arready(sb_axi_arready_int), + .sb_axi_rvalid(sb_axi_rvalid_int), + .sb_axi_rdata(sb_axi_rdata_int[63:0]), + .sb_axi_rresp(sb_axi_rresp_int[1:0]), + .dbg_cmd_addr(dbg_cmd_addr), + .dbg_cmd_wrdata(dbg_cmd_wrdata), + .dbg_cmd_valid(dbg_cmd_valid), + .dbg_cmd_write(dbg_cmd_write), + .dbg_cmd_type(dbg_cmd_type), + .dbg_cmd_size(dbg_cmd_size), + .dbg_core_rst_l(dbg_core_rst_l), + .core_dbg_rddata(core_dbg_rddata), + .core_dbg_cmd_done(core_dbg_cmd_done), + .core_dbg_cmd_fail(core_dbg_cmd_fail), + .dbg_dma_bubble(dbg_dma_bubble), + .dma_dbg_ready(dma_dbg_ready), + .dbg_halt_req(dbg_halt_req), + .dbg_resume_req(dbg_resume_req), + .dec_tlu_debug_mode(dec_tlu_debug_mode), + .dec_tlu_dbg_halted(dec_tlu_dbg_halted), + .dec_tlu_mpc_halted_only(dec_tlu_mpc_halted_only), + .dec_tlu_resume_ack(dec_tlu_resume_ack), + .dmi_reg_en(dmi_reg_en), + .dmi_reg_addr(dmi_reg_addr), + .dmi_reg_wr_en(dmi_reg_wr_en), + .dmi_reg_wdata(dmi_reg_wdata), + .dmi_reg_rdata(dmi_reg_rdata), + .sb_axi_awvalid(sb_axi_awvalid), + .sb_axi_awid(sb_axi_awid), + .sb_axi_awaddr(sb_axi_awaddr), + .sb_axi_awregion(sb_axi_awregion), + .sb_axi_awlen(sb_axi_awlen), + .sb_axi_awsize(sb_axi_awsize), + .sb_axi_awburst(sb_axi_awburst), + .sb_axi_awlock(sb_axi_awlock), + .sb_axi_awcache(sb_axi_awcache), + .sb_axi_awprot(sb_axi_awprot), + .sb_axi_awqos(sb_axi_awqos), + .sb_axi_wvalid(sb_axi_wvalid), + .sb_axi_wdata(sb_axi_wdata), + .sb_axi_wstrb(sb_axi_wstrb), + .sb_axi_wlast(sb_axi_wlast), + .sb_axi_bready(sb_axi_bready), + .sb_axi_arvalid(sb_axi_arvalid), + .sb_axi_arid(sb_axi_arid), + .sb_axi_araddr(sb_axi_araddr), + .sb_axi_arregion(sb_axi_arregion), + .sb_axi_arlen(sb_axi_arlen), + .sb_axi_arsize(sb_axi_arsize), + .sb_axi_arburst(sb_axi_arburst), + .sb_axi_arlock(sb_axi_arlock), + .sb_axi_arcache(sb_axi_arcache), + .sb_axi_arprot(sb_axi_arprot), + .sb_axi_arqos(sb_axi_arqos), + .sb_axi_rready(sb_axi_rready), + .dbg_bus_clk_en(dbg_bus_clk_en), + .free_clk(free_clk), + .dbg_rst_l(dbg_rst_l), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:859:4 + assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:861:4 + el2_ifu #(.pt(pt)) ifu( + .clk(active_l2clk), + .rst_l(core_rst_l), + .dec_tlu_flush_err_wb(dec_tlu_flush_err_r), + .dec_tlu_flush_noredir_wb(dec_tlu_flush_noredir_r), + .dec_tlu_fence_i_wb(dec_tlu_fence_i_r), + .dec_tlu_flush_leak_one_wb(dec_tlu_flush_leak_one_r), + .dec_tlu_flush_lower_wb(dec_tlu_flush_lower_r), + .ifu_axi_arready(ifu_axi_arready_int), + .ifu_axi_rvalid(ifu_axi_rvalid_int), + .ifu_axi_rid(ifu_axi_rid_int[pt[826-:8] - 1:0]), + .ifu_axi_rdata(ifu_axi_rdata_int[63:0]), + .ifu_axi_rresp(ifu_axi_rresp_int[1:0]), + .free_l2clk(free_l2clk), + .active_clk(active_clk), + .dec_i0_decode_d(dec_i0_decode_d), + .exu_flush_final(exu_flush_final), + .dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt), + .exu_flush_path_final(exu_flush_path_final), + .dec_tlu_mrac_ff(dec_tlu_mrac_ff), + .dec_tlu_bpred_disable(dec_tlu_bpred_disable), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .dec_tlu_force_halt(dec_tlu_force_halt), + .ifu_axi_awvalid(ifu_axi_awvalid), + .ifu_axi_awid(ifu_axi_awid), + .ifu_axi_awaddr(ifu_axi_awaddr), + .ifu_axi_awregion(ifu_axi_awregion), + .ifu_axi_awlen(ifu_axi_awlen), + .ifu_axi_awsize(ifu_axi_awsize), + .ifu_axi_awburst(ifu_axi_awburst), + .ifu_axi_awlock(ifu_axi_awlock), + .ifu_axi_awcache(ifu_axi_awcache), + .ifu_axi_awprot(ifu_axi_awprot), + .ifu_axi_awqos(ifu_axi_awqos), + .ifu_axi_wvalid(ifu_axi_wvalid), + .ifu_axi_wdata(ifu_axi_wdata), + .ifu_axi_wstrb(ifu_axi_wstrb), + .ifu_axi_wlast(ifu_axi_wlast), + .ifu_axi_bready(ifu_axi_bready), + .ifu_axi_arvalid(ifu_axi_arvalid), + .ifu_axi_arid(ifu_axi_arid), + .ifu_axi_araddr(ifu_axi_araddr), + .ifu_axi_arregion(ifu_axi_arregion), + .ifu_axi_arlen(ifu_axi_arlen), + .ifu_axi_arsize(ifu_axi_arsize), + .ifu_axi_arburst(ifu_axi_arburst), + .ifu_axi_arlock(ifu_axi_arlock), + .ifu_axi_arcache(ifu_axi_arcache), + .ifu_axi_arprot(ifu_axi_arprot), + .ifu_axi_arqos(ifu_axi_arqos), + .ifu_axi_rready(ifu_axi_rready), + .ifu_bus_clk_en(ifu_bus_clk_en), + .dma_iccm_req(dma_iccm_req), + .dma_mem_addr(dma_mem_addr), + .dma_mem_sz(dma_mem_sz), + .dma_mem_write(dma_mem_write), + .dma_mem_wdata(dma_mem_wdata), + .dma_mem_tag(dma_mem_tag), + .dma_iccm_stall_any(dma_iccm_stall_any), + .iccm_dma_ecc_error(iccm_dma_ecc_error), + .iccm_dma_rvalid(iccm_dma_rvalid), + .iccm_dma_rdata(iccm_dma_rdata), + .iccm_dma_rtag(iccm_dma_rtag), + .iccm_ready(iccm_ready), + .ifu_pmu_instr_aligned(ifu_pmu_instr_aligned), + .ifu_pmu_fetch_stall(ifu_pmu_fetch_stall), + .ifu_ic_error_start(ifu_ic_error_start), + .ic_rw_addr(ic_rw_addr), + .ic_wr_en(ic_wr_en), + .ic_rd_en(ic_rd_en), + .ic_wr_data(ic_wr_data), + .ic_rd_data(ic_rd_data), + .ic_debug_rd_data(ic_debug_rd_data), + .ictag_debug_rd_data(ictag_debug_rd_data), + .ic_debug_wr_data(ic_debug_wr_data), + .ifu_ic_debug_rd_data(ifu_ic_debug_rd_data), + .ic_eccerr(ic_eccerr), + .ic_parerr(ic_parerr), + .ic_premux_data(ic_premux_data), + .ic_sel_premux_data(ic_sel_premux_data), + .ic_debug_addr(ic_debug_addr), + .ic_debug_rd_en(ic_debug_rd_en), + .ic_debug_wr_en(ic_debug_wr_en), + .ic_debug_tag_array(ic_debug_tag_array), + .ic_debug_way(ic_debug_way), + .ic_tag_valid(ic_tag_valid), + .ic_rd_hit(ic_rd_hit), + .ic_tag_perr(ic_tag_perr), + .iccm_rw_addr(iccm_rw_addr), + .iccm_wren(iccm_wren), + .iccm_rden(iccm_rden), + .iccm_wr_data(iccm_wr_data), + .iccm_wr_size(iccm_wr_size), + .iccm_rd_data(iccm_rd_data), + .iccm_rd_data_ecc(iccm_rd_data_ecc), + .ifu_iccm_rd_ecc_single_err(ifu_iccm_rd_ecc_single_err), + .ifu_pmu_ic_miss(ifu_pmu_ic_miss), + .ifu_pmu_ic_hit(ifu_pmu_ic_hit), + .ifu_pmu_bus_error(ifu_pmu_bus_error), + .ifu_pmu_bus_busy(ifu_pmu_bus_busy), + .ifu_pmu_bus_trxn(ifu_pmu_bus_trxn), + .ifu_i0_icaf(ifu_i0_icaf), + .ifu_i0_icaf_type(ifu_i0_icaf_type), + .ifu_i0_valid(ifu_i0_valid), + .ifu_i0_icaf_second(ifu_i0_icaf_second), + .ifu_i0_dbecc(ifu_i0_dbecc), + .iccm_dma_sb_error(iccm_dma_sb_error), + .ifu_i0_instr(ifu_i0_instr), + .ifu_i0_pc(ifu_i0_pc), + .ifu_i0_pc4(ifu_i0_pc4), + .ifu_miss_state_idle(ifu_miss_state_idle), + .i0_brp(i0_brp), + .ifu_i0_bp_index(ifu_i0_bp_index), + .ifu_i0_bp_fghr(ifu_i0_bp_fghr), + .ifu_i0_bp_btag(ifu_i0_bp_btag), + .ifu_i0_fa_index(ifu_i0_fa_index), + .exu_mp_pkt(exu_mp_pkt), + .exu_mp_eghr(exu_mp_eghr), + .exu_mp_fghr(exu_mp_fghr), + .exu_mp_index(exu_mp_index), + .exu_mp_btag(exu_mp_btag), + .dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt), + .exu_i0_br_fghr_r(exu_i0_br_fghr_r), + .exu_i0_br_index_r(exu_i0_br_index_r), + .dec_fa_error_index(dec_fa_error_index), + .ifu_i0_cinst(ifu_i0_cinst), + .dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt), + .ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid), + .iccm_buf_correct_ecc(iccm_buf_correct_ecc), + .iccm_correction_state(iccm_correction_state), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:881:4 + el2_dec #(.pt(pt)) dec( + .clk(active_l2clk), + .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]), + .rst_l(core_rst_l), + .active_clk(active_clk), + .free_clk(free_clk), + .free_l2clk(free_l2clk), + .lsu_fastint_stall_any(lsu_fastint_stall_any), + .dec_extint_stall(dec_extint_stall), + .dec_i0_decode_d(dec_i0_decode_d), + .dec_pause_state_cg(dec_pause_state_cg), + .dec_tlu_core_empty(dec_tlu_core_empty), + .rst_vec(rst_vec), + .nmi_int(nmi_int), + .nmi_vec(nmi_vec), + .i_cpu_halt_req(i_cpu_halt_req), + .i_cpu_run_req(i_cpu_run_req), + .o_cpu_halt_status(o_cpu_halt_status), + .o_cpu_halt_ack(o_cpu_halt_ack), + .o_cpu_run_ack(o_cpu_run_ack), + .o_debug_mode_status(o_debug_mode_status), + .core_id(core_id), + .mpc_debug_halt_req(mpc_debug_halt_req), + .mpc_debug_run_req(mpc_debug_run_req), + .mpc_reset_run_req(mpc_reset_run_req), + .mpc_debug_halt_ack(mpc_debug_halt_ack), + .mpc_debug_run_ack(mpc_debug_run_ack), + .debug_brkpt_status(debug_brkpt_status), + .exu_pmu_i0_br_misp(exu_pmu_i0_br_misp), + .exu_pmu_i0_br_ataken(exu_pmu_i0_br_ataken), + .exu_pmu_i0_pc4(exu_pmu_i0_pc4), + .lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m), + .lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m), + .lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r), + .lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r), + .lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid), + .lsu_nonblock_load_data_error(lsu_nonblock_load_data_error), + .lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag), + .lsu_nonblock_load_data(lsu_nonblock_load_data), + .lsu_pmu_bus_trxn(lsu_pmu_bus_trxn), + .lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned), + .lsu_pmu_bus_error(lsu_pmu_bus_error), + .lsu_pmu_bus_busy(lsu_pmu_bus_busy), + .lsu_pmu_misaligned_m(lsu_pmu_misaligned_m), + .lsu_pmu_load_external_m(lsu_pmu_load_external_m), + .lsu_pmu_store_external_m(lsu_pmu_store_external_m), + .dma_pmu_dccm_read(dma_pmu_dccm_read), + .dma_pmu_dccm_write(dma_pmu_dccm_write), + .dma_pmu_any_read(dma_pmu_any_read), + .dma_pmu_any_write(dma_pmu_any_write), + .lsu_fir_addr(lsu_fir_addr), + .lsu_fir_error(lsu_fir_error), + .ifu_pmu_instr_aligned(ifu_pmu_instr_aligned), + .ifu_pmu_fetch_stall(ifu_pmu_fetch_stall), + .ifu_pmu_ic_miss(ifu_pmu_ic_miss), + .ifu_pmu_ic_hit(ifu_pmu_ic_hit), + .ifu_pmu_bus_error(ifu_pmu_bus_error), + .ifu_pmu_bus_busy(ifu_pmu_bus_busy), + .ifu_pmu_bus_trxn(ifu_pmu_bus_trxn), + .ifu_ic_error_start(ifu_ic_error_start), + .ifu_iccm_rd_ecc_single_err(ifu_iccm_rd_ecc_single_err), + .lsu_trigger_match_m(lsu_trigger_match_m), + .dbg_cmd_valid(dbg_cmd_valid), + .dbg_cmd_write(dbg_cmd_write), + .dbg_cmd_type(dbg_cmd_type), + .dbg_cmd_addr(dbg_cmd_addr), + .ifu_i0_icaf(ifu_i0_icaf), + .ifu_i0_icaf_type(ifu_i0_icaf_type), + .ifu_i0_icaf_second(ifu_i0_icaf_second), + .ifu_i0_dbecc(ifu_i0_dbecc), + .lsu_idle_any(lsu_idle_any), + .i0_brp(i0_brp), + .ifu_i0_bp_index(ifu_i0_bp_index), + .ifu_i0_bp_fghr(ifu_i0_bp_fghr), + .ifu_i0_bp_btag(ifu_i0_bp_btag), + .ifu_i0_fa_index(ifu_i0_fa_index), + .lsu_error_pkt_r(lsu_error_pkt_r), + .lsu_single_ecc_error_incr(lsu_single_ecc_error_incr), + .lsu_imprecise_error_load_any(lsu_imprecise_error_load_any), + .lsu_imprecise_error_store_any(lsu_imprecise_error_store_any), + .lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any), + .exu_div_result(exu_div_result), + .exu_div_wren(exu_div_wren), + .exu_csr_rs1_x(exu_csr_rs1_x), + .lsu_result_m(lsu_result_m), + .lsu_result_corr_r(lsu_result_corr_r), + .lsu_load_stall_any(lsu_load_stall_any), + .lsu_store_stall_any(lsu_store_stall_any), + .dma_dccm_stall_any(dma_dccm_stall_any), + .dma_iccm_stall_any(dma_iccm_stall_any), + .iccm_dma_sb_error(iccm_dma_sb_error), + .exu_flush_final(exu_flush_final), + .exu_npc_r(exu_npc_r), + .exu_i0_result_x(exu_i0_result_x), + .ifu_i0_valid(ifu_i0_valid), + .ifu_i0_instr(ifu_i0_instr), + .ifu_i0_pc(ifu_i0_pc), + .ifu_i0_pc4(ifu_i0_pc4), + .exu_i0_pc_x(exu_i0_pc_x), + .mexintpend(mexintpend), + .timer_int(timer_int), + .soft_int(soft_int), + .pic_claimid(pic_claimid), + .pic_pl(pic_pl), + .mhwakeup(mhwakeup), + .dec_tlu_meicurpl(dec_tlu_meicurpl), + .dec_tlu_meipt(dec_tlu_meipt), + .ifu_ic_debug_rd_data(ifu_ic_debug_rd_data), + .ifu_ic_debug_rd_data_valid(ifu_ic_debug_rd_data_valid), + .dec_tlu_ic_diag_pkt(dec_tlu_ic_diag_pkt), + .dbg_halt_req(dbg_halt_req), + .dbg_resume_req(dbg_resume_req), + .ifu_miss_state_idle(ifu_miss_state_idle), + .dec_tlu_dbg_halted(dec_tlu_dbg_halted), + .dec_tlu_debug_mode(dec_tlu_debug_mode), + .dec_tlu_resume_ack(dec_tlu_resume_ack), + .dec_tlu_flush_noredir_r(dec_tlu_flush_noredir_r), + .dec_tlu_mpc_halted_only(dec_tlu_mpc_halted_only), + .dec_tlu_flush_leak_one_r(dec_tlu_flush_leak_one_r), + .dec_tlu_flush_err_r(dec_tlu_flush_err_r), + .dec_tlu_meihap(dec_tlu_meihap), + .dec_debug_wdata_rs1_d(dec_debug_wdata_rs1_d), + .dec_dbg_rddata(dec_dbg_rddata), + .dec_dbg_cmd_done(dec_dbg_cmd_done), + .dec_dbg_cmd_fail(dec_dbg_cmd_fail), + .trigger_pkt_any(trigger_pkt_any), + .dec_tlu_force_halt(dec_tlu_force_halt), + .exu_i0_br_hist_r(exu_i0_br_hist_r), + .exu_i0_br_error_r(exu_i0_br_error_r), + .exu_i0_br_start_error_r(exu_i0_br_start_error_r), + .exu_i0_br_valid_r(exu_i0_br_valid_r), + .exu_i0_br_mp_r(exu_i0_br_mp_r), + .exu_i0_br_middle_r(exu_i0_br_middle_r), + .exu_i0_br_way_r(exu_i0_br_way_r), + .dec_i0_rs1_en_d(dec_i0_rs1_en_d), + .dec_i0_rs2_en_d(dec_i0_rs2_en_d), + .gpr_i0_rs1_d(gpr_i0_rs1_d), + .gpr_i0_rs2_d(gpr_i0_rs2_d), + .dec_i0_immed_d(dec_i0_immed_d), + .dec_i0_br_immed_d(dec_i0_br_immed_d), + .i0_ap(i0_ap), + .dec_i0_alu_decode_d(dec_i0_alu_decode_d), + .dec_i0_branch_d(dec_i0_branch_d), + .dec_i0_select_pc_d(dec_i0_select_pc_d), + .dec_i0_pc_d(dec_i0_pc_d), + .dec_i0_rs1_bypass_en_d(dec_i0_rs1_bypass_en_d), + .dec_i0_rs2_bypass_en_d(dec_i0_rs2_bypass_en_d), + .dec_i0_result_r(dec_i0_result_r), + .lsu_p(lsu_p), + .dec_qual_lsu_d(dec_qual_lsu_d), + .mul_p(mul_p), + .div_p(div_p), + .dec_div_cancel(dec_div_cancel), + .dec_lsu_offset_d(dec_lsu_offset_d), + .dec_csr_ren_d(dec_csr_ren_d), + .dec_csr_rddata_d(dec_csr_rddata_d), + .dec_tlu_flush_lower_r(dec_tlu_flush_lower_r), + .dec_tlu_flush_lower_wb(dec_tlu_flush_lower_wb), + .dec_tlu_flush_path_r(dec_tlu_flush_path_r), + .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r), + .dec_tlu_fence_i_r(dec_tlu_fence_i_r), + .pred_correct_npc_x(pred_correct_npc_x), + .dec_tlu_br0_r_pkt(dec_tlu_br0_r_pkt), + .dec_tlu_perfcnt0(dec_tlu_perfcnt0), + .dec_tlu_perfcnt1(dec_tlu_perfcnt1), + .dec_tlu_perfcnt2(dec_tlu_perfcnt2), + .dec_tlu_perfcnt3(dec_tlu_perfcnt3), + .dec_i0_predict_p_d(dec_i0_predict_p_d), + .i0_predict_fghr_d(i0_predict_fghr_d), + .i0_predict_index_d(i0_predict_index_d), + .i0_predict_btag_d(i0_predict_btag_d), + .dec_fa_error_index(dec_fa_error_index), + .dec_lsu_valid_raw_d(dec_lsu_valid_raw_d), + .dec_tlu_mrac_ff(dec_tlu_mrac_ff), + .dec_data_en(dec_data_en), + .dec_ctl_en(dec_ctl_en), + .ifu_i0_cinst(ifu_i0_cinst), + .trace_rv_trace_pkt(trace_rv_trace_pkt), + .dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable), + .dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .dec_tlu_bpred_disable(dec_tlu_bpred_disable), + .dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable), + .dec_tlu_dma_qos_prty(dec_tlu_dma_qos_prty), + .dec_tlu_misc_clk_override(dec_tlu_misc_clk_override), + .dec_tlu_ifu_clk_override(dec_tlu_ifu_clk_override), + .dec_tlu_lsu_clk_override(dec_tlu_lsu_clk_override), + .dec_tlu_bus_clk_override(dec_tlu_bus_clk_override), + .dec_tlu_pic_clk_override(dec_tlu_pic_clk_override), + .dec_tlu_picio_clk_override(dec_tlu_picio_clk_override), + .dec_tlu_dccm_clk_override(dec_tlu_dccm_clk_override), + .dec_tlu_icm_clk_override(dec_tlu_icm_clk_override), + .dec_tlu_i0_commit_cmt(dec_tlu_i0_commit_cmt), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:888:4 + el2_exu #(.pt(pt)) exu( + .clk(active_l2clk), + .rst_l(core_rst_l), + .scan_mode(scan_mode), + .dec_data_en(dec_data_en), + .dec_ctl_en(dec_ctl_en), + .dbg_cmd_wrdata(dbg_cmd_wrdata), + .i0_ap(i0_ap), + .dec_debug_wdata_rs1_d(dec_debug_wdata_rs1_d), + .dec_i0_predict_p_d(dec_i0_predict_p_d), + .i0_predict_fghr_d(i0_predict_fghr_d), + .i0_predict_index_d(i0_predict_index_d), + .i0_predict_btag_d(i0_predict_btag_d), + .lsu_result_m(lsu_result_m), + .lsu_nonblock_load_data(lsu_nonblock_load_data), + .dec_i0_rs1_en_d(dec_i0_rs1_en_d), + .dec_i0_rs2_en_d(dec_i0_rs2_en_d), + .gpr_i0_rs1_d(gpr_i0_rs1_d), + .gpr_i0_rs2_d(gpr_i0_rs2_d), + .dec_i0_immed_d(dec_i0_immed_d), + .dec_i0_result_r(dec_i0_result_r), + .dec_i0_br_immed_d(dec_i0_br_immed_d), + .dec_i0_alu_decode_d(dec_i0_alu_decode_d), + .dec_i0_branch_d(dec_i0_branch_d), + .dec_i0_select_pc_d(dec_i0_select_pc_d), + .dec_i0_pc_d(dec_i0_pc_d), + .dec_i0_rs1_bypass_en_d(dec_i0_rs1_bypass_en_d), + .dec_i0_rs2_bypass_en_d(dec_i0_rs2_bypass_en_d), + .dec_csr_ren_d(dec_csr_ren_d), + .dec_csr_rddata_d(dec_csr_rddata_d), + .dec_qual_lsu_d(dec_qual_lsu_d), + .mul_p(mul_p), + .div_p(div_p), + .dec_div_cancel(dec_div_cancel), + .pred_correct_npc_x(pred_correct_npc_x), + .dec_tlu_flush_lower_r(dec_tlu_flush_lower_r), + .dec_tlu_flush_path_r(dec_tlu_flush_path_r), + .dec_extint_stall(dec_extint_stall), + .dec_tlu_meihap(dec_tlu_meihap), + .exu_lsu_rs1_d(exu_lsu_rs1_d), + .exu_lsu_rs2_d(exu_lsu_rs2_d), + .exu_flush_final(exu_flush_final), + .exu_flush_path_final(exu_flush_path_final), + .exu_i0_result_x(exu_i0_result_x), + .exu_i0_pc_x(exu_i0_pc_x), + .exu_csr_rs1_x(exu_csr_rs1_x), + .exu_npc_r(exu_npc_r), + .exu_i0_br_hist_r(exu_i0_br_hist_r), + .exu_i0_br_error_r(exu_i0_br_error_r), + .exu_i0_br_start_error_r(exu_i0_br_start_error_r), + .exu_i0_br_index_r(exu_i0_br_index_r), + .exu_i0_br_valid_r(exu_i0_br_valid_r), + .exu_i0_br_mp_r(exu_i0_br_mp_r), + .exu_i0_br_middle_r(exu_i0_br_middle_r), + .exu_i0_br_fghr_r(exu_i0_br_fghr_r), + .exu_i0_br_way_r(exu_i0_br_way_r), + .exu_mp_pkt(exu_mp_pkt), + .exu_mp_eghr(exu_mp_eghr), + .exu_mp_fghr(exu_mp_fghr), + .exu_mp_index(exu_mp_index), + .exu_mp_btag(exu_mp_btag), + .exu_pmu_i0_br_misp(exu_pmu_i0_br_misp), + .exu_pmu_i0_br_ataken(exu_pmu_i0_br_ataken), + .exu_pmu_i0_pc4(exu_pmu_i0_pc4), + .exu_div_result(exu_div_result), + .exu_div_wren(exu_div_wren) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:894:4 + el2_lsu #(.pt(pt)) lsu( + .clk(active_l2clk), + .rst_l(core_rst_l), + .clk_override(dec_tlu_lsu_clk_override), + .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r), + .lsu_axi_awready(lsu_axi_awready_int), + .lsu_axi_wready(lsu_axi_wready_int), + .lsu_axi_bvalid(lsu_axi_bvalid_int), + .lsu_axi_bid(lsu_axi_bid_int[pt[181-:8] - 1:0]), + .lsu_axi_bresp(lsu_axi_bresp_int[1:0]), + .lsu_axi_arready(lsu_axi_arready_int), + .lsu_axi_rvalid(lsu_axi_rvalid_int), + .lsu_axi_rid(lsu_axi_rid_int[pt[181-:8] - 1:0]), + .lsu_axi_rdata(lsu_axi_rdata_int[63:0]), + .lsu_axi_rresp(lsu_axi_rresp_int[1:0]), + .lsu_axi_rlast(lsu_axi_rlast_int), + .dec_tlu_flush_lower_r(dec_tlu_flush_lower_r), + .dec_tlu_force_halt(dec_tlu_force_halt), + .dec_tlu_external_ldfwd_disable(dec_tlu_external_ldfwd_disable), + .dec_tlu_wb_coalescing_disable(dec_tlu_wb_coalescing_disable), + .dec_tlu_sideeffect_posted_disable(dec_tlu_sideeffect_posted_disable), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .exu_lsu_rs1_d(exu_lsu_rs1_d), + .exu_lsu_rs2_d(exu_lsu_rs2_d), + .dec_lsu_offset_d(dec_lsu_offset_d), + .lsu_p(lsu_p), + .dec_lsu_valid_raw_d(dec_lsu_valid_raw_d), + .dec_tlu_mrac_ff(dec_tlu_mrac_ff), + .lsu_result_m(lsu_result_m), + .lsu_result_corr_r(lsu_result_corr_r), + .lsu_load_stall_any(lsu_load_stall_any), + .lsu_store_stall_any(lsu_store_stall_any), + .lsu_fastint_stall_any(lsu_fastint_stall_any), + .lsu_idle_any(lsu_idle_any), + .lsu_active(lsu_active), + .lsu_fir_addr(lsu_fir_addr), + .lsu_fir_error(lsu_fir_error), + .lsu_single_ecc_error_incr(lsu_single_ecc_error_incr), + .lsu_error_pkt_r(lsu_error_pkt_r), + .lsu_imprecise_error_load_any(lsu_imprecise_error_load_any), + .lsu_imprecise_error_store_any(lsu_imprecise_error_store_any), + .lsu_imprecise_error_addr_any(lsu_imprecise_error_addr_any), + .lsu_nonblock_load_valid_m(lsu_nonblock_load_valid_m), + .lsu_nonblock_load_tag_m(lsu_nonblock_load_tag_m), + .lsu_nonblock_load_inv_r(lsu_nonblock_load_inv_r), + .lsu_nonblock_load_inv_tag_r(lsu_nonblock_load_inv_tag_r), + .lsu_nonblock_load_data_valid(lsu_nonblock_load_data_valid), + .lsu_nonblock_load_data_error(lsu_nonblock_load_data_error), + .lsu_nonblock_load_data_tag(lsu_nonblock_load_data_tag), + .lsu_nonblock_load_data(lsu_nonblock_load_data), + .lsu_pmu_load_external_m(lsu_pmu_load_external_m), + .lsu_pmu_store_external_m(lsu_pmu_store_external_m), + .lsu_pmu_misaligned_m(lsu_pmu_misaligned_m), + .lsu_pmu_bus_trxn(lsu_pmu_bus_trxn), + .lsu_pmu_bus_misaligned(lsu_pmu_bus_misaligned), + .lsu_pmu_bus_error(lsu_pmu_bus_error), + .lsu_pmu_bus_busy(lsu_pmu_bus_busy), + .trigger_pkt_any(trigger_pkt_any), + .lsu_trigger_match_m(lsu_trigger_match_m), + .dccm_wren(dccm_wren), + .dccm_rden(dccm_rden), + .dccm_wr_addr_lo(dccm_wr_addr_lo), + .dccm_wr_addr_hi(dccm_wr_addr_hi), + .dccm_rd_addr_lo(dccm_rd_addr_lo), + .dccm_rd_addr_hi(dccm_rd_addr_hi), + .dccm_wr_data_lo(dccm_wr_data_lo), + .dccm_wr_data_hi(dccm_wr_data_hi), + .dccm_rd_data_lo(dccm_rd_data_lo), + .dccm_rd_data_hi(dccm_rd_data_hi), + .picm_wren(picm_wren), + .picm_rden(picm_rden), + .picm_mken(picm_mken), + .picm_rdaddr(picm_rdaddr), + .picm_wraddr(picm_wraddr), + .picm_wr_data(picm_wr_data), + .picm_rd_data(picm_rd_data), + .lsu_axi_awvalid(lsu_axi_awvalid), + .lsu_axi_awid(lsu_axi_awid), + .lsu_axi_awaddr(lsu_axi_awaddr), + .lsu_axi_awregion(lsu_axi_awregion), + .lsu_axi_awlen(lsu_axi_awlen), + .lsu_axi_awsize(lsu_axi_awsize), + .lsu_axi_awburst(lsu_axi_awburst), + .lsu_axi_awlock(lsu_axi_awlock), + .lsu_axi_awcache(lsu_axi_awcache), + .lsu_axi_awprot(lsu_axi_awprot), + .lsu_axi_awqos(lsu_axi_awqos), + .lsu_axi_wvalid(lsu_axi_wvalid), + .lsu_axi_wdata(lsu_axi_wdata), + .lsu_axi_wstrb(lsu_axi_wstrb), + .lsu_axi_wlast(lsu_axi_wlast), + .lsu_axi_bready(lsu_axi_bready), + .lsu_axi_arvalid(lsu_axi_arvalid), + .lsu_axi_arid(lsu_axi_arid), + .lsu_axi_araddr(lsu_axi_araddr), + .lsu_axi_arregion(lsu_axi_arregion), + .lsu_axi_arlen(lsu_axi_arlen), + .lsu_axi_arsize(lsu_axi_arsize), + .lsu_axi_arburst(lsu_axi_arburst), + .lsu_axi_arlock(lsu_axi_arlock), + .lsu_axi_arcache(lsu_axi_arcache), + .lsu_axi_arprot(lsu_axi_arprot), + .lsu_axi_arqos(lsu_axi_arqos), + .lsu_axi_rready(lsu_axi_rready), + .lsu_bus_clk_en(lsu_bus_clk_en), + .dma_dccm_req(dma_dccm_req), + .dma_mem_tag(dma_mem_tag), + .dma_mem_addr(dma_mem_addr), + .dma_mem_sz(dma_mem_sz), + .dma_mem_write(dma_mem_write), + .dma_mem_wdata(dma_mem_wdata), + .dccm_dma_rvalid(dccm_dma_rvalid), + .dccm_dma_ecc_error(dccm_dma_ecc_error), + .dccm_dma_rtag(dccm_dma_rtag), + .dccm_dma_rdata(dccm_dma_rdata), + .dccm_ready(dccm_ready), + .scan_mode(scan_mode), + .active_clk(active_clk) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:919:4 + el2_pic_ctrl #(.pt(pt)) pic_ctrl_inst( + .clk(free_l2clk), + .clk_override(dec_tlu_pic_clk_override), + .io_clk_override(dec_tlu_picio_clk_override), + .picm_mken(picm_mken), + .extintsrc_req({extintsrc_req[pt[56-:12]:1], 1'b0}), + .pl(pic_pl[3:0]), + .claimid(pic_claimid[7:0]), + .meicurpl(dec_tlu_meicurpl[3:0]), + .meipt(dec_tlu_meipt[3:0]), + .rst_l(core_rst_l), + .free_clk(free_clk), + .picm_rdaddr(picm_rdaddr), + .picm_wraddr(picm_wraddr), + .picm_wr_data(picm_wr_data), + .picm_wren(picm_wren), + .picm_rden(picm_rden), + .mexintpend(mexintpend), + .picm_rd_data(picm_rd_data), + .mhwakeup(mhwakeup), + .scan_mode(scan_mode) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:932:4 + el2_dma_ctrl #(.pt(pt)) dma_ctrl( + .clk(free_l2clk), + .rst_l(core_rst_l), + .clk_override(dec_tlu_misc_clk_override), + .dma_axi_awvalid(dma_axi_awvalid_int), + .dma_axi_awid(dma_axi_awid_int[pt[1235-:8] - 1:0]), + .dma_axi_awaddr(dma_axi_awaddr_int[31:0]), + .dma_axi_awsize(dma_axi_awsize_int[2:0]), + .dma_axi_wvalid(dma_axi_wvalid_int), + .dma_axi_wdata(dma_axi_wdata_int[63:0]), + .dma_axi_wstrb(dma_axi_wstrb_int[7:0]), + .dma_axi_bready(dma_axi_bready_int), + .dma_axi_arvalid(dma_axi_arvalid_int), + .dma_axi_arid(dma_axi_arid_int[pt[1235-:8] - 1:0]), + .dma_axi_araddr(dma_axi_araddr_int[31:0]), + .dma_axi_arsize(dma_axi_arsize_int[2:0]), + .dma_axi_rready(dma_axi_rready_int), + .free_clk(free_clk), + .dma_bus_clk_en(dma_bus_clk_en), + .scan_mode(scan_mode), + .dbg_cmd_addr(dbg_cmd_addr), + .dbg_cmd_wrdata(dbg_cmd_wrdata), + .dbg_cmd_valid(dbg_cmd_valid), + .dbg_cmd_write(dbg_cmd_write), + .dbg_cmd_type(dbg_cmd_type), + .dbg_cmd_size(dbg_cmd_size), + .dbg_dma_bubble(dbg_dma_bubble), + .dma_dbg_ready(dma_dbg_ready), + .dma_dbg_cmd_done(dma_dbg_cmd_done), + .dma_dbg_cmd_fail(dma_dbg_cmd_fail), + .dma_dbg_rddata(dma_dbg_rddata), + .dma_dccm_req(dma_dccm_req), + .dma_iccm_req(dma_iccm_req), + .dma_mem_tag(dma_mem_tag), + .dma_mem_addr(dma_mem_addr), + .dma_mem_sz(dma_mem_sz), + .dma_mem_write(dma_mem_write), + .dma_mem_wdata(dma_mem_wdata), + .dccm_dma_rvalid(dccm_dma_rvalid), + .dccm_dma_ecc_error(dccm_dma_ecc_error), + .dccm_dma_rtag(dccm_dma_rtag), + .dccm_dma_rdata(dccm_dma_rdata), + .iccm_dma_rvalid(iccm_dma_rvalid), + .iccm_dma_ecc_error(iccm_dma_ecc_error), + .iccm_dma_rtag(iccm_dma_rtag), + .iccm_dma_rdata(iccm_dma_rdata), + .dma_active(dma_active), + .dma_dccm_stall_any(dma_dccm_stall_any), + .dma_iccm_stall_any(dma_iccm_stall_any), + .dccm_ready(dccm_ready), + .iccm_ready(iccm_ready), + .dec_tlu_dma_qos_prty(dec_tlu_dma_qos_prty), + .dma_pmu_dccm_read(dma_pmu_dccm_read), + .dma_pmu_dccm_write(dma_pmu_dccm_write), + .dma_pmu_any_read(dma_pmu_any_read), + .dma_pmu_any_write(dma_pmu_any_write), + .dma_axi_awready(dma_axi_awready), + .dma_axi_wready(dma_axi_wready), + .dma_axi_bvalid(dma_axi_bvalid), + .dma_axi_bresp(dma_axi_bresp), + .dma_axi_bid(dma_axi_bid), + .dma_axi_arready(dma_axi_arready), + .dma_axi_rvalid(dma_axi_rvalid), + .dma_axi_rid(dma_axi_rid), + .dma_axi_rdata(dma_axi_rdata), + .dma_axi_rresp(dma_axi_rresp), + .dma_axi_rlast(dma_axi_rlast) + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:956:4 + generate + if (pt[2038] == 1) begin : Gen_AXI_To_AHB + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:959:7 + axi4_to_ahb #( + .pt(pt), + .TAG(pt[181-:8]) + ) lsu_axi4_to_ahb( + .clk(free_l2clk), + .free_clk(free_clk), + .rst_l(core_rst_l), + .clk_override(dec_tlu_bus_clk_override), + .bus_clk_en(lsu_bus_clk_en), + .dec_tlu_force_halt(dec_tlu_force_halt), + .axi_awvalid(lsu_axi_awvalid), + .axi_awready(lsu_axi_awready_ahb), + .axi_awid(lsu_axi_awid[pt[181-:8] - 1:0]), + .axi_awaddr(lsu_axi_awaddr[31:0]), + .axi_awsize(lsu_axi_awsize[2:0]), + .axi_awprot(lsu_axi_awprot[2:0]), + .axi_wvalid(lsu_axi_wvalid), + .axi_wready(lsu_axi_wready_ahb), + .axi_wdata(lsu_axi_wdata[63:0]), + .axi_wstrb(lsu_axi_wstrb[7:0]), + .axi_wlast(lsu_axi_wlast), + .axi_bvalid(lsu_axi_bvalid_ahb), + .axi_bready(lsu_axi_bready), + .axi_bresp(lsu_axi_bresp_ahb[1:0]), + .axi_bid(lsu_axi_bid_ahb[pt[181-:8] - 1:0]), + .axi_arvalid(lsu_axi_arvalid), + .axi_arready(lsu_axi_arready_ahb), + .axi_arid(lsu_axi_arid[pt[181-:8] - 1:0]), + .axi_araddr(lsu_axi_araddr[31:0]), + .axi_arsize(lsu_axi_arsize[2:0]), + .axi_arprot(lsu_axi_arprot[2:0]), + .axi_rvalid(lsu_axi_rvalid_ahb), + .axi_rready(lsu_axi_rready), + .axi_rid(lsu_axi_rid_ahb[pt[181-:8] - 1:0]), + .axi_rdata(lsu_axi_rdata_ahb[63:0]), + .axi_rresp(lsu_axi_rresp_ahb[1:0]), + .axi_rlast(lsu_axi_rlast_ahb), + .ahb_haddr(lsu_haddr[31:0]), + .ahb_hburst(lsu_hburst), + .ahb_hmastlock(lsu_hmastlock), + .ahb_hprot(lsu_hprot[3:0]), + .ahb_hsize(lsu_hsize[2:0]), + .ahb_htrans(lsu_htrans[1:0]), + .ahb_hwrite(lsu_hwrite), + .ahb_hwdata(lsu_hwdata[63:0]), + .ahb_hrdata(lsu_hrdata[63:0]), + .ahb_hready(lsu_hready), + .ahb_hresp(lsu_hresp), + .* + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1020:7 + axi4_to_ahb #( + .pt(pt), + .TAG(pt[826-:8]) + ) ifu_axi4_to_ahb( + .clk(free_l2clk), + .free_clk(free_clk), + .rst_l(core_rst_l), + .clk_override(dec_tlu_bus_clk_override), + .bus_clk_en(ifu_bus_clk_en), + .dec_tlu_force_halt(dec_tlu_force_halt), + .ahb_haddr(haddr[31:0]), + .ahb_hburst(hburst), + .ahb_hmastlock(hmastlock), + .ahb_hprot(hprot[3:0]), + .ahb_hsize(hsize[2:0]), + .ahb_htrans(htrans[1:0]), + .ahb_hwrite(hwrite), + .ahb_hwdata(hwdata_nc[63:0]), + .ahb_hrdata(hrdata[63:0]), + .ahb_hready(hready), + .ahb_hresp(hresp), + .axi_awvalid(ifu_axi_awvalid), + .axi_awready(ifu_axi_awready_ahb), + .axi_awid(ifu_axi_awid[pt[826-:8] - 1:0]), + .axi_awaddr(ifu_axi_awaddr[31:0]), + .axi_awsize(ifu_axi_awsize[2:0]), + .axi_awprot(ifu_axi_awprot[2:0]), + .axi_wvalid(ifu_axi_wvalid), + .axi_wready(ifu_axi_wready_ahb), + .axi_wdata(ifu_axi_wdata[63:0]), + .axi_wstrb(ifu_axi_wstrb[7:0]), + .axi_wlast(ifu_axi_wlast), + .axi_bvalid(ifu_axi_bvalid_ahb), + .axi_bready(1'b1), + .axi_bresp(ifu_axi_bresp_ahb[1:0]), + .axi_bid(ifu_axi_bid_ahb[pt[826-:8] - 1:0]), + .axi_arvalid(ifu_axi_arvalid), + .axi_arready(ifu_axi_arready_ahb), + .axi_arid(ifu_axi_arid[pt[826-:8] - 1:0]), + .axi_araddr(ifu_axi_araddr[31:0]), + .axi_arsize(ifu_axi_arsize[2:0]), + .axi_arprot(ifu_axi_arprot[2:0]), + .axi_rvalid(ifu_axi_rvalid_ahb), + .axi_rready(ifu_axi_rready), + .axi_rid(ifu_axi_rid_ahb[pt[826-:8] - 1:0]), + .axi_rdata(ifu_axi_rdata_ahb[63:0]), + .axi_rresp(ifu_axi_rresp_ahb[1:0]), + .axi_rlast(ifu_axi_rlast_ahb), + .* + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1080:7 + axi4_to_ahb #( + .pt(pt), + .TAG(pt[12-:8]) + ) sb_axi4_to_ahb( + .clk(free_l2clk), + .free_clk(free_clk), + .rst_l(dbg_rst_l), + .clk_override(dec_tlu_bus_clk_override), + .bus_clk_en(dbg_bus_clk_en), + .dec_tlu_force_halt(1'b0), + .axi_awvalid(sb_axi_awvalid), + .axi_awready(sb_axi_awready_ahb), + .axi_awid(sb_axi_awid[pt[12-:8] - 1:0]), + .axi_awaddr(sb_axi_awaddr[31:0]), + .axi_awsize(sb_axi_awsize[2:0]), + .axi_awprot(sb_axi_awprot[2:0]), + .axi_wvalid(sb_axi_wvalid), + .axi_wready(sb_axi_wready_ahb), + .axi_wdata(sb_axi_wdata[63:0]), + .axi_wstrb(sb_axi_wstrb[7:0]), + .axi_wlast(sb_axi_wlast), + .axi_bvalid(sb_axi_bvalid_ahb), + .axi_bready(sb_axi_bready), + .axi_bresp(sb_axi_bresp_ahb[1:0]), + .axi_bid(sb_axi_bid_ahb[pt[12-:8] - 1:0]), + .axi_arvalid(sb_axi_arvalid), + .axi_arready(sb_axi_arready_ahb), + .axi_arid(sb_axi_arid[pt[12-:8] - 1:0]), + .axi_araddr(sb_axi_araddr[31:0]), + .axi_arsize(sb_axi_arsize[2:0]), + .axi_arprot(sb_axi_arprot[2:0]), + .axi_rvalid(sb_axi_rvalid_ahb), + .axi_rready(sb_axi_rready), + .axi_rid(sb_axi_rid_ahb[pt[12-:8] - 1:0]), + .axi_rdata(sb_axi_rdata_ahb[63:0]), + .axi_rresp(sb_axi_rresp_ahb[1:0]), + .axi_rlast(sb_axi_rlast_ahb), + .ahb_haddr(sb_haddr[31:0]), + .ahb_hburst(sb_hburst), + .ahb_hmastlock(sb_hmastlock), + .ahb_hprot(sb_hprot[3:0]), + .ahb_hsize(sb_hsize[2:0]), + .ahb_htrans(sb_htrans[1:0]), + .ahb_hwrite(sb_hwrite), + .ahb_hwdata(sb_hwdata[63:0]), + .ahb_hrdata(sb_hrdata[63:0]), + .ahb_hready(sb_hready), + .ahb_hresp(sb_hresp), + .* + ); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1140:7 + ahb_to_axi4 #( + .pt(pt), + .TAG(pt[1235-:8]) + ) dma_ahb_to_axi4( + .clk(free_l2clk), + .rst_l(core_rst_l), + .clk_override(dec_tlu_bus_clk_override), + .bus_clk_en(dma_bus_clk_en), + .axi_awvalid(dma_axi_awvalid_ahb), + .axi_awready(dma_axi_awready), + .axi_awid(dma_axi_awid_ahb[pt[1235-:8] - 1:0]), + .axi_awaddr(dma_axi_awaddr_ahb[31:0]), + .axi_awsize(dma_axi_awsize_ahb[2:0]), + .axi_awprot(dma_axi_awprot_ahb[2:0]), + .axi_awlen(dma_axi_awlen_ahb[7:0]), + .axi_awburst(dma_axi_awburst_ahb[1:0]), + .axi_wvalid(dma_axi_wvalid_ahb), + .axi_wready(dma_axi_wready), + .axi_wdata(dma_axi_wdata_ahb[63:0]), + .axi_wstrb(dma_axi_wstrb_ahb[7:0]), + .axi_wlast(dma_axi_wlast_ahb), + .axi_bvalid(dma_axi_bvalid), + .axi_bready(dma_axi_bready_ahb), + .axi_bresp(dma_axi_bresp[1:0]), + .axi_bid(dma_axi_bid[pt[1235-:8] - 1:0]), + .axi_arvalid(dma_axi_arvalid_ahb), + .axi_arready(dma_axi_arready), + .axi_arid(dma_axi_arid_ahb[pt[1235-:8] - 1:0]), + .axi_araddr(dma_axi_araddr_ahb[31:0]), + .axi_arsize(dma_axi_arsize_ahb[2:0]), + .axi_arprot(dma_axi_arprot_ahb[2:0]), + .axi_arlen(dma_axi_arlen_ahb[7:0]), + .axi_arburst(dma_axi_arburst_ahb[1:0]), + .axi_rvalid(dma_axi_rvalid), + .axi_rready(dma_axi_rready_ahb), + .axi_rid(dma_axi_rid[pt[1235-:8] - 1:0]), + .axi_rdata(dma_axi_rdata[63:0]), + .axi_rresp(dma_axi_rresp[1:0]), + .ahb_haddr(dma_haddr[31:0]), + .ahb_hburst(dma_hburst), + .ahb_hmastlock(dma_hmastlock), + .ahb_hprot(dma_hprot[3:0]), + .ahb_hsize(dma_hsize[2:0]), + .ahb_htrans(dma_htrans[1:0]), + .ahb_hwrite(dma_hwrite), + .ahb_hwdata(dma_hwdata[63:0]), + .ahb_hrdata(dma_hrdata[63:0]), + .ahb_hreadyout(dma_hreadyout), + .ahb_hresp(dma_hresp), + .ahb_hreadyin(dma_hreadyin), + .ahb_hsel(dma_hsel), + .* + ); + end + endgenerate + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1205:4 + assign lsu_axi_awready_int = (pt[2038] ? lsu_axi_awready_ahb : lsu_axi_awready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1206:4 + assign lsu_axi_wready_int = (pt[2038] ? lsu_axi_wready_ahb : lsu_axi_wready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1207:4 + assign lsu_axi_bvalid_int = (pt[2038] ? lsu_axi_bvalid_ahb : lsu_axi_bvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1208:4 + assign lsu_axi_bready_int = (pt[2038] ? lsu_axi_bready_ahb : lsu_axi_bready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1209:4 + assign lsu_axi_bresp_int[1:0] = (pt[2038] ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1210:4 + assign lsu_axi_bid_int[pt[181-:8] - 1:0] = (pt[2038] ? lsu_axi_bid_ahb[pt[181-:8] - 1:0] : lsu_axi_bid[pt[181-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1211:4 + assign lsu_axi_arready_int = (pt[2038] ? lsu_axi_arready_ahb : lsu_axi_arready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1212:4 + assign lsu_axi_rvalid_int = (pt[2038] ? lsu_axi_rvalid_ahb : lsu_axi_rvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1213:4 + assign lsu_axi_rid_int[pt[181-:8] - 1:0] = (pt[2038] ? lsu_axi_rid_ahb[pt[181-:8] - 1:0] : lsu_axi_rid[pt[181-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1214:4 + assign lsu_axi_rdata_int[63:0] = (pt[2038] ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1215:4 + assign lsu_axi_rresp_int[1:0] = (pt[2038] ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1216:4 + assign lsu_axi_rlast_int = (pt[2038] ? lsu_axi_rlast_ahb : lsu_axi_rlast); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1218:4 + assign ifu_axi_awready_int = (pt[2038] ? ifu_axi_awready_ahb : ifu_axi_awready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1219:4 + assign ifu_axi_wready_int = (pt[2038] ? ifu_axi_wready_ahb : ifu_axi_wready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1220:4 + assign ifu_axi_bvalid_int = (pt[2038] ? ifu_axi_bvalid_ahb : ifu_axi_bvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1221:4 + assign ifu_axi_bready_int = (pt[2038] ? ifu_axi_bready_ahb : ifu_axi_bready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1222:4 + assign ifu_axi_bresp_int[1:0] = (pt[2038] ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1223:4 + assign ifu_axi_bid_int[pt[826-:8] - 1:0] = (pt[2038] ? ifu_axi_bid_ahb[pt[826-:8] - 1:0] : ifu_axi_bid[pt[826-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1224:4 + assign ifu_axi_arready_int = (pt[2038] ? ifu_axi_arready_ahb : ifu_axi_arready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1225:4 + assign ifu_axi_rvalid_int = (pt[2038] ? ifu_axi_rvalid_ahb : ifu_axi_rvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1226:4 + assign ifu_axi_rid_int[pt[826-:8] - 1:0] = (pt[2038] ? ifu_axi_rid_ahb[pt[826-:8] - 1:0] : ifu_axi_rid[pt[826-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1227:4 + assign ifu_axi_rdata_int[63:0] = (pt[2038] ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1228:4 + assign ifu_axi_rresp_int[1:0] = (pt[2038] ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1229:4 + assign ifu_axi_rlast_int = (pt[2038] ? ifu_axi_rlast_ahb : ifu_axi_rlast); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1231:4 + assign sb_axi_awready_int = (pt[2038] ? sb_axi_awready_ahb : sb_axi_awready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1232:4 + assign sb_axi_wready_int = (pt[2038] ? sb_axi_wready_ahb : sb_axi_wready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1233:4 + assign sb_axi_bvalid_int = (pt[2038] ? sb_axi_bvalid_ahb : sb_axi_bvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1234:4 + assign sb_axi_bready_int = (pt[2038] ? sb_axi_bready_ahb : sb_axi_bready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1235:4 + assign sb_axi_bresp_int[1:0] = (pt[2038] ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1236:4 + assign sb_axi_bid_int[pt[12-:8] - 1:0] = (pt[2038] ? sb_axi_bid_ahb[pt[12-:8] - 1:0] : sb_axi_bid[pt[12-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1237:4 + assign sb_axi_arready_int = (pt[2038] ? sb_axi_arready_ahb : sb_axi_arready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1238:4 + assign sb_axi_rvalid_int = (pt[2038] ? sb_axi_rvalid_ahb : sb_axi_rvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1239:4 + assign sb_axi_rid_int[pt[12-:8] - 1:0] = (pt[2038] ? sb_axi_rid_ahb[pt[12-:8] - 1:0] : sb_axi_rid[pt[12-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1240:4 + assign sb_axi_rdata_int[63:0] = (pt[2038] ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1241:4 + assign sb_axi_rresp_int[1:0] = (pt[2038] ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1242:4 + assign sb_axi_rlast_int = (pt[2038] ? sb_axi_rlast_ahb : sb_axi_rlast); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1244:4 + assign dma_axi_awvalid_int = (pt[2038] ? dma_axi_awvalid_ahb : dma_axi_awvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1245:4 + assign dma_axi_awid_int[pt[1235-:8] - 1:0] = (pt[2038] ? dma_axi_awid_ahb[pt[1235-:8] - 1:0] : dma_axi_awid[pt[1235-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1246:4 + assign dma_axi_awaddr_int[31:0] = (pt[2038] ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1247:4 + assign dma_axi_awsize_int[2:0] = (pt[2038] ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1248:4 + assign dma_axi_awprot_int[2:0] = (pt[2038] ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1249:4 + assign dma_axi_awlen_int[7:0] = (pt[2038] ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1250:4 + assign dma_axi_awburst_int[1:0] = (pt[2038] ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1251:4 + assign dma_axi_wvalid_int = (pt[2038] ? dma_axi_wvalid_ahb : dma_axi_wvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1252:4 + assign dma_axi_wdata_int[63:0] = (pt[2038] ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1253:4 + assign dma_axi_wstrb_int[7:0] = (pt[2038] ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1254:4 + assign dma_axi_wlast_int = (pt[2038] ? dma_axi_wlast_ahb : dma_axi_wlast); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1255:4 + assign dma_axi_bready_int = (pt[2038] ? dma_axi_bready_ahb : dma_axi_bready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1256:4 + assign dma_axi_arvalid_int = (pt[2038] ? dma_axi_arvalid_ahb : dma_axi_arvalid); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1257:4 + assign dma_axi_arid_int[pt[1235-:8] - 1:0] = (pt[2038] ? dma_axi_arid_ahb[pt[1235-:8] - 1:0] : dma_axi_arid[pt[1235-:8] - 1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1258:4 + assign dma_axi_araddr_int[31:0] = (pt[2038] ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1259:4 + assign dma_axi_arsize_int[2:0] = (pt[2038] ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1260:4 + assign dma_axi_arprot_int[2:0] = (pt[2038] ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1261:4 + assign dma_axi_arlen_int[7:0] = (pt[2038] ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1262:4 + assign dma_axi_arburst_int[1:0] = (pt[2038] ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0]); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1263:4 + assign dma_axi_rready_int = (pt[2038] ? dma_axi_rready_ahb : dma_axi_rready); + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1266:1 + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1292:7 + assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt[102:71]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1294:7 + assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt[70:39]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1296:7 + assign trace_rv_i_valid_ip = trace_rv_trace_pkt[103]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1298:7 + assign trace_rv_i_exception_ip = trace_rv_trace_pkt[38]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1300:7 + assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt[37:33]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1302:7 + assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt[32]; + // Trace: ./src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/el2_veer.sv:1304:7 + assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt[31:0]; +endmodule +// removed package "cb_filter_pkg" +// removed package "cf_math_pkg" +module delta_counter ( + clk_i, + rst_ni, + clear_i, + en_i, + load_i, + down_i, + delta_i, + d_i, + q_o, + overflow_o +); + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:14:15 + parameter [31:0] WIDTH = 4; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:15:15 + parameter [0:0] STICKY_OVERFLOW = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:17:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:18:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:19:5 + input wire clear_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:20:5 + input wire en_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:21:5 + input wire load_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:22:5 + input wire down_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:23:5 + input wire [WIDTH - 1:0] delta_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:24:5 + input wire [WIDTH - 1:0] d_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:25:5 + output wire [WIDTH - 1:0] q_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:26:5 + output wire overflow_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:28:5 + reg [WIDTH:0] counter_q; + reg [WIDTH:0] counter_d; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:29:5 + generate + if (STICKY_OVERFLOW) begin : gen_sticky_overflow + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:30:9 + reg overflow_d; + reg overflow_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:31:9 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:31:54 + overflow_q <= (~rst_ni ? 1'b0 : overflow_d); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:32:9 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:33:13 + overflow_d = overflow_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:34:13 + if (clear_i || load_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:35:17 + overflow_d = 1'b0; + else if (!overflow_q && en_i) begin + begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:37:17 + if (down_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:38:21 + overflow_d = delta_i > counter_q[WIDTH - 1:0]; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:40:21 + overflow_d = counter_q[WIDTH - 1:0] > ({WIDTH {1'b1}} - delta_i); + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:44:9 + assign overflow_o = overflow_q; + end + else begin : gen_transient_overflow + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:47:9 + assign overflow_o = counter_q[WIDTH]; + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:49:5 + assign q_o = counter_q[WIDTH - 1:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:51:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:52:9 + counter_d = counter_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:54:9 + if (clear_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:55:13 + counter_d = 1'sb0; + else if (load_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:57:13 + counter_d = {1'b0, d_i}; + else if (en_i) begin + begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:59:13 + if (down_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:60:17 + counter_d = counter_q - delta_i; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:62:17 + counter_d = counter_q + delta_i; + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:67:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:68:9 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:69:12 + counter_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/delta_counter.sv:71:12 + counter_q <= counter_d; + initial _sv2v_0 = 0; +endmodule +// removed package "ecc_pkg" +module fifo_v3_0EFFB_75D82 ( + clk_i, + rst_ni, + flush_i, + testmode_i, + full_o, + empty_o, + usage_o, + data_i, + push_i, + data_o, + pop_i +); + // removed localparam type dtype_AxiIdWidth_type + parameter [31:0] dtype_AxiIdWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:14:15 + parameter [0:0] FALL_THROUGH = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:15:15 + parameter [31:0] DATA_WIDTH = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:16:15 + parameter [31:0] DEPTH = 8; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:17:20 + // removed localparam type dtype + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:19:15 + parameter [31:0] ADDR_DEPTH = (DEPTH > 1 ? $clog2(DEPTH) : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:21:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:22:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:23:5 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:24:5 + input wire testmode_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:26:5 + output wire full_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:27:5 + output wire empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:28:5 + output wire [ADDR_DEPTH - 1:0] usage_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:30:5 + input wire [dtype_AxiIdWidth + 7:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:31:5 + input wire push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:33:5 + output reg [dtype_AxiIdWidth + 7:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:34:5 + input wire pop_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:38:5 + localparam [31:0] FifoDepth = (DEPTH > 0 ? DEPTH : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:40:5 + reg gate_clock; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:42:5 + reg [ADDR_DEPTH - 1:0] read_pointer_n; + reg [ADDR_DEPTH - 1:0] read_pointer_q; + reg [ADDR_DEPTH - 1:0] write_pointer_n; + reg [ADDR_DEPTH - 1:0] write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:45:5 + reg [ADDR_DEPTH:0] status_cnt_n; + reg [ADDR_DEPTH:0] status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:47:5 + reg [((dtype_AxiIdWidth + 7) >= 0 ? (FifoDepth * (dtype_AxiIdWidth + 8)) - 1 : (FifoDepth * (1 - (dtype_AxiIdWidth + 7))) + (dtype_AxiIdWidth + 6)):((dtype_AxiIdWidth + 7) >= 0 ? 0 : dtype_AxiIdWidth + 7)] mem_n; + reg [((dtype_AxiIdWidth + 7) >= 0 ? (FifoDepth * (dtype_AxiIdWidth + 8)) - 1 : (FifoDepth * (1 - (dtype_AxiIdWidth + 7))) + (dtype_AxiIdWidth + 6)):((dtype_AxiIdWidth + 7) >= 0 ? 0 : dtype_AxiIdWidth + 7)] mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:49:5 + assign usage_o = status_cnt_q[ADDR_DEPTH - 1:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:51:5 + generate + if (DEPTH == 0) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:52:9 + assign empty_o = ~push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:53:9 + assign full_o = ~pop_i; + end + else begin : gen_fifo + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:55:9 + assign full_o = status_cnt_q == FifoDepth[ADDR_DEPTH:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:56:9 + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:61:5 + always @(*) begin : read_write_comb + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:63:9 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:64:9 + write_pointer_n = write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:65:9 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:66:9 + data_o = (DEPTH == 0 ? data_i : mem_q[((dtype_AxiIdWidth + 7) >= 0 ? 0 : dtype_AxiIdWidth + 7) + (read_pointer_q * ((dtype_AxiIdWidth + 7) >= 0 ? dtype_AxiIdWidth + 8 : 1 - (dtype_AxiIdWidth + 7)))+:((dtype_AxiIdWidth + 7) >= 0 ? dtype_AxiIdWidth + 8 : 1 - (dtype_AxiIdWidth + 7))]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:67:9 + mem_n = mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:68:9 + gate_clock = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:71:9 + if (push_i && ~full_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:73:13 + mem_n[((dtype_AxiIdWidth + 7) >= 0 ? 0 : dtype_AxiIdWidth + 7) + (write_pointer_q * ((dtype_AxiIdWidth + 7) >= 0 ? dtype_AxiIdWidth + 8 : 1 - (dtype_AxiIdWidth + 7)))+:((dtype_AxiIdWidth + 7) >= 0 ? dtype_AxiIdWidth + 8 : 1 - (dtype_AxiIdWidth + 7))] = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:75:13 + gate_clock = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:77:13 + if (write_pointer_q == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:78:17 + write_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:80:17 + write_pointer_n = write_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:82:13 + status_cnt_n = status_cnt_q + 1; + end + if (pop_i && ~empty_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:88:13 + if (read_pointer_n == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:89:17 + read_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:91:17 + read_pointer_n = read_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:93:13 + status_cnt_n = status_cnt_q - 1; + end + if (((push_i && pop_i) && ~full_o) && ~empty_o) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:98:13 + status_cnt_n = status_cnt_q; + if ((FALL_THROUGH && (status_cnt_q == 0)) && push_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:102:13 + data_o = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:103:13 + if (pop_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:104:17 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:105:17 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:106:17 + write_pointer_n = write_pointer_q; + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:112:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:113:9 + if (~rst_ni) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:114:13 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:115:13 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:116:13 + status_cnt_q <= 1'sb0; + end + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:118:13 + if (flush_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:119:17 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:120:17 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:121:17 + status_cnt_q <= 1'sb0; + end + else begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:123:17 + read_pointer_q <= read_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:124:17 + write_pointer_q <= write_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:125:17 + status_cnt_q <= status_cnt_n; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:130:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:131:9 + if (~rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:132:13 + mem_q <= 1'sb0; + else if (!gate_clock) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:134:13 + mem_q <= mem_n; + initial _sv2v_0 = 0; +endmodule +module fifo_v3_7ABAC_FAAEB ( + clk_i, + rst_ni, + flush_i, + testmode_i, + full_o, + empty_o, + usage_o, + data_i, + push_i, + data_o, + pop_i +); + // removed localparam type dtype_MstIdxBits_type + parameter [31:0] dtype_MstIdxBits = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:14:15 + parameter [0:0] FALL_THROUGH = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:15:15 + parameter [31:0] DATA_WIDTH = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:16:15 + parameter [31:0] DEPTH = 8; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:17:20 + // removed localparam type dtype + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:19:15 + parameter [31:0] ADDR_DEPTH = (DEPTH > 1 ? $clog2(DEPTH) : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:21:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:22:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:23:5 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:24:5 + input wire testmode_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:26:5 + output wire full_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:27:5 + output wire empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:28:5 + output wire [ADDR_DEPTH - 1:0] usage_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:30:5 + input wire [dtype_MstIdxBits - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:31:5 + input wire push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:33:5 + output reg [dtype_MstIdxBits - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:34:5 + input wire pop_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:38:5 + localparam [31:0] FifoDepth = (DEPTH > 0 ? DEPTH : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:40:5 + reg gate_clock; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:42:5 + reg [ADDR_DEPTH - 1:0] read_pointer_n; + reg [ADDR_DEPTH - 1:0] read_pointer_q; + reg [ADDR_DEPTH - 1:0] write_pointer_n; + reg [ADDR_DEPTH - 1:0] write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:45:5 + reg [ADDR_DEPTH:0] status_cnt_n; + reg [ADDR_DEPTH:0] status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:47:5 + reg [(FifoDepth * dtype_MstIdxBits) - 1:0] mem_n; + reg [(FifoDepth * dtype_MstIdxBits) - 1:0] mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:49:5 + assign usage_o = status_cnt_q[ADDR_DEPTH - 1:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:51:5 + generate + if (DEPTH == 0) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:52:9 + assign empty_o = ~push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:53:9 + assign full_o = ~pop_i; + end + else begin : gen_fifo + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:55:9 + assign full_o = status_cnt_q == FifoDepth[ADDR_DEPTH:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:56:9 + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:61:5 + always @(*) begin : read_write_comb + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:63:9 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:64:9 + write_pointer_n = write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:65:9 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:66:9 + data_o = (DEPTH == 0 ? data_i : mem_q[read_pointer_q * dtype_MstIdxBits+:dtype_MstIdxBits]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:67:9 + mem_n = mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:68:9 + gate_clock = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:71:9 + if (push_i && ~full_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:73:13 + mem_n[write_pointer_q * dtype_MstIdxBits+:dtype_MstIdxBits] = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:75:13 + gate_clock = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:77:13 + if (write_pointer_q == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:78:17 + write_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:80:17 + write_pointer_n = write_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:82:13 + status_cnt_n = status_cnt_q + 1; + end + if (pop_i && ~empty_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:88:13 + if (read_pointer_n == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:89:17 + read_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:91:17 + read_pointer_n = read_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:93:13 + status_cnt_n = status_cnt_q - 1; + end + if (((push_i && pop_i) && ~full_o) && ~empty_o) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:98:13 + status_cnt_n = status_cnt_q; + if ((FALL_THROUGH && (status_cnt_q == 0)) && push_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:102:13 + data_o = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:103:13 + if (pop_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:104:17 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:105:17 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:106:17 + write_pointer_n = write_pointer_q; + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:112:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:113:9 + if (~rst_ni) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:114:13 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:115:13 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:116:13 + status_cnt_q <= 1'sb0; + end + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:118:13 + if (flush_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:119:17 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:120:17 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:121:17 + status_cnt_q <= 1'sb0; + end + else begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:123:17 + read_pointer_q <= read_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:124:17 + write_pointer_q <= write_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:125:17 + status_cnt_q <= status_cnt_n; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:130:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:131:9 + if (~rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:132:13 + mem_q <= 1'sb0; + else if (!gate_clock) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:134:13 + mem_q <= mem_n; + initial _sv2v_0 = 0; +endmodule +module fifo_v3_F9D8C_B67E5 ( + clk_i, + rst_ni, + flush_i, + testmode_i, + full_o, + empty_o, + usage_o, + data_i, + push_i, + data_o, + pop_i +); + // removed localparam type dtype_AxiIdWidth_type + parameter [31:0] dtype_AxiIdWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:14:15 + parameter [0:0] FALL_THROUGH = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:15:15 + parameter [31:0] DATA_WIDTH = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:16:15 + parameter [31:0] DEPTH = 8; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:17:20 + // removed localparam type dtype + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:19:15 + parameter [31:0] ADDR_DEPTH = (DEPTH > 1 ? $clog2(DEPTH) : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:21:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:22:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:23:5 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:24:5 + input wire testmode_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:26:5 + output wire full_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:27:5 + output wire empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:28:5 + output wire [ADDR_DEPTH - 1:0] usage_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:30:5 + input wire [dtype_AxiIdWidth - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:31:5 + input wire push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:33:5 + output reg [dtype_AxiIdWidth - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:34:5 + input wire pop_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:38:5 + localparam [31:0] FifoDepth = (DEPTH > 0 ? DEPTH : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:40:5 + reg gate_clock; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:42:5 + reg [ADDR_DEPTH - 1:0] read_pointer_n; + reg [ADDR_DEPTH - 1:0] read_pointer_q; + reg [ADDR_DEPTH - 1:0] write_pointer_n; + reg [ADDR_DEPTH - 1:0] write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:45:5 + reg [ADDR_DEPTH:0] status_cnt_n; + reg [ADDR_DEPTH:0] status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:47:5 + reg [(FifoDepth * dtype_AxiIdWidth) - 1:0] mem_n; + reg [(FifoDepth * dtype_AxiIdWidth) - 1:0] mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:49:5 + assign usage_o = status_cnt_q[ADDR_DEPTH - 1:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:51:5 + generate + if (DEPTH == 0) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:52:9 + assign empty_o = ~push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:53:9 + assign full_o = ~pop_i; + end + else begin : gen_fifo + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:55:9 + assign full_o = status_cnt_q == FifoDepth[ADDR_DEPTH:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:56:9 + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:61:5 + always @(*) begin : read_write_comb + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:63:9 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:64:9 + write_pointer_n = write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:65:9 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:66:9 + data_o = (DEPTH == 0 ? data_i : mem_q[read_pointer_q * dtype_AxiIdWidth+:dtype_AxiIdWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:67:9 + mem_n = mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:68:9 + gate_clock = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:71:9 + if (push_i && ~full_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:73:13 + mem_n[write_pointer_q * dtype_AxiIdWidth+:dtype_AxiIdWidth] = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:75:13 + gate_clock = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:77:13 + if (write_pointer_q == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:78:17 + write_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:80:17 + write_pointer_n = write_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:82:13 + status_cnt_n = status_cnt_q + 1; + end + if (pop_i && ~empty_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:88:13 + if (read_pointer_n == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:89:17 + read_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:91:17 + read_pointer_n = read_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:93:13 + status_cnt_n = status_cnt_q - 1; + end + if (((push_i && pop_i) && ~full_o) && ~empty_o) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:98:13 + status_cnt_n = status_cnt_q; + if ((FALL_THROUGH && (status_cnt_q == 0)) && push_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:102:13 + data_o = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:103:13 + if (pop_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:104:17 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:105:17 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:106:17 + write_pointer_n = write_pointer_q; + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:112:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:113:9 + if (~rst_ni) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:114:13 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:115:13 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:116:13 + status_cnt_q <= 1'sb0; + end + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:118:13 + if (flush_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:119:17 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:120:17 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:121:17 + status_cnt_q <= 1'sb0; + end + else begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:123:17 + read_pointer_q <= read_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:124:17 + write_pointer_q <= write_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:125:17 + status_cnt_q <= status_cnt_n; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:130:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:131:9 + if (~rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:132:13 + mem_q <= 1'sb0; + else if (!gate_clock) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:134:13 + mem_q <= mem_n; + initial _sv2v_0 = 0; +endmodule +module fifo_v3_A7CFE_56795 ( + clk_i, + rst_ni, + flush_i, + testmode_i, + full_o, + empty_o, + usage_o, + data_i, + push_i, + data_o, + pop_i +); + // removed localparam type dtype_SelectWidth_type + parameter [31:0] dtype_SelectWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:14:15 + parameter [0:0] FALL_THROUGH = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:15:15 + parameter [31:0] DATA_WIDTH = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:16:15 + parameter [31:0] DEPTH = 8; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:17:20 + // removed localparam type dtype + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:19:15 + parameter [31:0] ADDR_DEPTH = (DEPTH > 1 ? $clog2(DEPTH) : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:21:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:22:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:23:5 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:24:5 + input wire testmode_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:26:5 + output wire full_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:27:5 + output wire empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:28:5 + output wire [ADDR_DEPTH - 1:0] usage_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:30:5 + input wire [dtype_SelectWidth - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:31:5 + input wire push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:33:5 + output reg [dtype_SelectWidth - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:34:5 + input wire pop_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:38:5 + localparam [31:0] FifoDepth = (DEPTH > 0 ? DEPTH : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:40:5 + reg gate_clock; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:42:5 + reg [ADDR_DEPTH - 1:0] read_pointer_n; + reg [ADDR_DEPTH - 1:0] read_pointer_q; + reg [ADDR_DEPTH - 1:0] write_pointer_n; + reg [ADDR_DEPTH - 1:0] write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:45:5 + reg [ADDR_DEPTH:0] status_cnt_n; + reg [ADDR_DEPTH:0] status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:47:5 + reg [(FifoDepth * dtype_SelectWidth) - 1:0] mem_n; + reg [(FifoDepth * dtype_SelectWidth) - 1:0] mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:49:5 + assign usage_o = status_cnt_q[ADDR_DEPTH - 1:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:51:5 + generate + if (DEPTH == 0) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:52:9 + assign empty_o = ~push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:53:9 + assign full_o = ~pop_i; + end + else begin : gen_fifo + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:55:9 + assign full_o = status_cnt_q == FifoDepth[ADDR_DEPTH:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:56:9 + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:61:5 + always @(*) begin : read_write_comb + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:63:9 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:64:9 + write_pointer_n = write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:65:9 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:66:9 + data_o = (DEPTH == 0 ? data_i : mem_q[read_pointer_q * dtype_SelectWidth+:dtype_SelectWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:67:9 + mem_n = mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:68:9 + gate_clock = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:71:9 + if (push_i && ~full_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:73:13 + mem_n[write_pointer_q * dtype_SelectWidth+:dtype_SelectWidth] = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:75:13 + gate_clock = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:77:13 + if (write_pointer_q == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:78:17 + write_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:80:17 + write_pointer_n = write_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:82:13 + status_cnt_n = status_cnt_q + 1; + end + if (pop_i && ~empty_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:88:13 + if (read_pointer_n == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:89:17 + read_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:91:17 + read_pointer_n = read_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:93:13 + status_cnt_n = status_cnt_q - 1; + end + if (((push_i && pop_i) && ~full_o) && ~empty_o) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:98:13 + status_cnt_n = status_cnt_q; + if ((FALL_THROUGH && (status_cnt_q == 0)) && push_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:102:13 + data_o = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:103:13 + if (pop_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:104:17 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:105:17 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:106:17 + write_pointer_n = write_pointer_q; + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:112:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:113:9 + if (~rst_ni) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:114:13 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:115:13 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:116:13 + status_cnt_q <= 1'sb0; + end + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:118:13 + if (flush_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:119:17 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:120:17 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:121:17 + status_cnt_q <= 1'sb0; + end + else begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:123:17 + read_pointer_q <= read_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:124:17 + write_pointer_q <= write_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:125:17 + status_cnt_q <= status_cnt_n; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:130:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:131:9 + if (~rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:132:13 + mem_q <= 1'sb0; + else if (!gate_clock) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:134:13 + mem_q <= mem_n; + initial _sv2v_0 = 0; +endmodule +module fifo_v3_B0153 ( + clk_i, + rst_ni, + flush_i, + testmode_i, + full_o, + empty_o, + usage_o, + data_i, + push_i, + data_o, + pop_i +); + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:14:15 + parameter [0:0] FALL_THROUGH = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:15:15 + parameter [31:0] DATA_WIDTH = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:16:15 + parameter [31:0] DEPTH = 8; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:17:20 + // removed localparam type dtype + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:19:15 + parameter [31:0] ADDR_DEPTH = (DEPTH > 1 ? $clog2(DEPTH) : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:21:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:22:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:23:5 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:24:5 + input wire testmode_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:26:5 + output wire full_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:27:5 + output wire empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:28:5 + output wire [ADDR_DEPTH - 1:0] usage_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:30:5 + input wire [7:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:31:5 + input wire push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:33:5 + output reg [7:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:34:5 + input wire pop_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:38:5 + localparam [31:0] FifoDepth = (DEPTH > 0 ? DEPTH : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:40:5 + reg gate_clock; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:42:5 + reg [ADDR_DEPTH - 1:0] read_pointer_n; + reg [ADDR_DEPTH - 1:0] read_pointer_q; + reg [ADDR_DEPTH - 1:0] write_pointer_n; + reg [ADDR_DEPTH - 1:0] write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:45:5 + reg [ADDR_DEPTH:0] status_cnt_n; + reg [ADDR_DEPTH:0] status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:47:5 + reg [(FifoDepth * 8) - 1:0] mem_n; + reg [(FifoDepth * 8) - 1:0] mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:49:5 + assign usage_o = status_cnt_q[ADDR_DEPTH - 1:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:51:5 + generate + if (DEPTH == 0) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:52:9 + assign empty_o = ~push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:53:9 + assign full_o = ~pop_i; + end + else begin : gen_fifo + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:55:9 + assign full_o = status_cnt_q == FifoDepth[ADDR_DEPTH:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:56:9 + assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i); + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:61:5 + always @(*) begin : read_write_comb + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:63:9 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:64:9 + write_pointer_n = write_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:65:9 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:66:9 + data_o = (DEPTH == 0 ? data_i : mem_q[read_pointer_q * 8+:8]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:67:9 + mem_n = mem_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:68:9 + gate_clock = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:71:9 + if (push_i && ~full_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:73:13 + mem_n[write_pointer_q * 8+:8] = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:75:13 + gate_clock = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:77:13 + if (write_pointer_q == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:78:17 + write_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:80:17 + write_pointer_n = write_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:82:13 + status_cnt_n = status_cnt_q + 1; + end + if (pop_i && ~empty_o) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:88:13 + if (read_pointer_n == (FifoDepth[ADDR_DEPTH - 1:0] - 1)) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:89:17 + read_pointer_n = 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:91:17 + read_pointer_n = read_pointer_q + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:93:13 + status_cnt_n = status_cnt_q - 1; + end + if (((push_i && pop_i) && ~full_o) && ~empty_o) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:98:13 + status_cnt_n = status_cnt_q; + if ((FALL_THROUGH && (status_cnt_q == 0)) && push_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:102:13 + data_o = data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:103:13 + if (pop_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:104:17 + status_cnt_n = status_cnt_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:105:17 + read_pointer_n = read_pointer_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:106:17 + write_pointer_n = write_pointer_q; + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:112:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:113:9 + if (~rst_ni) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:114:13 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:115:13 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:116:13 + status_cnt_q <= 1'sb0; + end + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:118:13 + if (flush_i) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:119:17 + read_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:120:17 + write_pointer_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:121:17 + status_cnt_q <= 1'sb0; + end + else begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:123:17 + read_pointer_q <= read_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:124:17 + write_pointer_q <= write_pointer_n; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:125:17 + status_cnt_q <= status_cnt_n; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:130:5 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:131:9 + if (~rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:132:13 + mem_q <= 1'sb0; + else if (!gate_clock) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/fifo_v3.sv:134:13 + mem_q <= mem_n; + initial _sv2v_0 = 0; +endmodule +module popcount ( + data_i, + popcount_o +); + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:20:15 + parameter [31:0] INPUT_WIDTH = 256; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:21:16 + localparam [31:0] PopcountWidth = $clog2(INPUT_WIDTH) + 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:23:5 + input wire [INPUT_WIDTH - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:24:5 + output wire [PopcountWidth - 1:0] popcount_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:27:4 + localparam [31:0] PaddedWidth = 1 << $clog2(INPUT_WIDTH); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:29:4 + reg [PaddedWidth - 1:0] padded_input; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:30:4 + wire [PopcountWidth - 2:0] left_child_result; + wire [PopcountWidth - 2:0] right_child_result; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:33:4 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:34:6 + padded_input = 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:35:6 + padded_input[INPUT_WIDTH - 1:0] = data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:39:4 + generate + if (INPUT_WIDTH == 1) begin : single_node + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:40:6 + assign left_child_result = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:41:6 + assign right_child_result = padded_input[0]; + end + else if (INPUT_WIDTH == 2) begin : leaf_node + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:43:6 + assign left_child_result = padded_input[1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:44:6 + assign right_child_result = padded_input[0]; + end + else begin : non_leaf_node + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:46:6 + popcount #(.INPUT_WIDTH(PaddedWidth / 2)) left_child( + .data_i(padded_input[PaddedWidth - 1:PaddedWidth / 2]), + .popcount_o(left_child_result) + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:51:6 + popcount #(.INPUT_WIDTH(PaddedWidth / 2)) right_child( + .data_i(padded_input[(PaddedWidth / 2) - 1:0]), + .popcount_o(right_child_result) + ); + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/popcount.sv:58:4 + assign popcount_o = left_child_result + right_child_result; + initial _sv2v_0 = 0; +endmodule +module rr_arb_tree_1A97E_3F3CA ( + clk_i, + rst_ni, + flush_i, + rr_i, + req_i, + gnt_o, + data_i, + req_o, + gnt_i, + data_o, + idx_o +); + // removed localparam type DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth_type + // removed localparam type DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves_type + // removed localparam type DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth_type + parameter [31:0] DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:49:13 + parameter [31:0] NumIn = 64; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:51:13 + parameter [31:0] DataWidth = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:53:26 + // removed localparam type DataType + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:60:13 + parameter [0:0] ExtPrio = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:67:13 + parameter [0:0] AxiVldRdy = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:74:13 + parameter [0:0] LockIn = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:78:13 + parameter [0:0] FairArb = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:81:13 + parameter [31:0] IdxWidth = (NumIn > 32'd1 ? $unsigned($clog2(NumIn)) : 32'd1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:84:26 + // removed localparam type idx_t + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:87:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:89:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:91:3 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:93:3 + input wire [IdxWidth - 1:0] rr_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:95:3 + input wire [NumIn - 1:0] req_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:98:3 + output wire [NumIn - 1:0] gnt_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:101:3 + input wire [(NumIn * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:103:3 + output wire req_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:105:3 + input wire gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:107:3 + output wire [(((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:109:3 + output wire [IdxWidth - 1:0] idx_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:122:3 + function automatic [IdxWidth - 1:0] sv2v_cast_5FDFE; + input reg [IdxWidth - 1:0] inp; + sv2v_cast_5FDFE = inp; + endfunction + function automatic [(((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] sv2v_cast_9F378; + input reg [(((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] inp; + sv2v_cast_9F378 = inp; + endfunction + generate + if (NumIn == $unsigned(1)) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:123:5 + assign req_o = req_i[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:124:5 + assign gnt_o[0] = gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:125:5 + assign data_o = data_i[0+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:126:5 + assign idx_o = 1'sb0; + end + else begin : gen_arbiter + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:129:5 + localparam [31:0] NumLevels = $unsigned($clog2(NumIn)); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:132:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * IdxWidth) - 1 : ((3 - (2 ** NumLevels)) * IdxWidth) + ((((2 ** NumLevels) - 2) * IdxWidth) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * IdxWidth)] index_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:133:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)) - 1 : ((3 - (2 ** NumLevels)) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)) + ((((2 ** NumLevels) - 2) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth))] data_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:134:5 + wire [(2 ** NumLevels) - 2:0] gnt_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:135:5 + wire [(2 ** NumLevels) - 2:0] req_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:137:5 + reg [IdxWidth - 1:0] rr_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:138:5 + wire [NumIn - 1:0] req_d; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:141:5 + assign req_o = req_nodes[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:142:5 + assign data_o = data_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:143:5 + assign idx_o = index_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * IdxWidth+:IdxWidth]; + if (ExtPrio) begin : gen_ext_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:146:7 + wire [IdxWidth:1] sv2v_tmp_0900B; + assign sv2v_tmp_0900B = rr_i; + always @(*) rr_q = sv2v_tmp_0900B; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:147:7 + assign req_d = req_i; + end + else begin : gen_int_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:149:7 + wire [IdxWidth - 1:0] rr_d; + if (LockIn) begin : gen_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:153:9 + wire lock_d; + reg lock_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:154:9 + reg [NumIn - 1:0] req_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:156:9 + assign lock_d = req_o & ~gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:157:9 + assign req_d = (lock_q ? req_q : req_i); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:159:9 + always @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:160:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:161:13 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:163:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:164:15 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:166:15 + lock_q <= lock_d; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:187:9 + always @(posedge clk_i or negedge rst_ni) begin : p_req_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:188:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:189:13 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:191:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:192:15 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:194:15 + req_q <= req_d; + end + end + else begin : gen_no_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:199:9 + assign req_d = req_i; + end + if (FairArb) begin : gen_fair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:203:9 + wire [NumIn - 1:0] upper_mask; + wire [NumIn - 1:0] lower_mask; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:204:9 + wire [IdxWidth - 1:0] upper_idx; + wire [IdxWidth - 1:0] lower_idx; + wire [IdxWidth - 1:0] next_idx; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:205:9 + wire upper_empty; + wire lower_empty; + genvar _gv_i_59; + for (_gv_i_59 = 0; _gv_i_59 < NumIn; _gv_i_59 = _gv_i_59 + 1) begin : gen_mask + localparam i = _gv_i_59; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:208:11 + assign upper_mask[i] = (i > rr_q ? req_d[i] : 1'b0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:209:11 + assign lower_mask[i] = (i <= rr_q ? req_d[i] : 1'b0); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:212:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_upper( + .in_i(upper_mask), + .cnt_o(upper_idx), + .empty_o(upper_empty) + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:221:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_lower( + .in_i(lower_mask), + .cnt_o(lower_idx), + .empty_o() + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:230:9 + assign next_idx = (upper_empty ? lower_idx : upper_idx); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:231:9 + assign rr_d = (gnt_i && req_o ? next_idx : rr_q); + end + else begin : gen_unfair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:234:9 + assign rr_d = (gnt_i && req_o ? (rr_q == sv2v_cast_5FDFE(NumIn - 1) ? {IdxWidth {1'sb0}} : rr_q + 1'b1) : rr_q); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:238:7 + always @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:239:9 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:240:11 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:242:11 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:243:13 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:245:13 + rr_q <= rr_d; + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:251:5 + assign gnt_nodes[0] = gnt_i; + genvar _gv_level_1; + for (_gv_level_1 = 0; $unsigned(_gv_level_1) < NumLevels; _gv_level_1 = _gv_level_1 + 1) begin : gen_levels + localparam level = _gv_level_1; + genvar _gv_l_98; + for (_gv_l_98 = 0; _gv_l_98 < (2 ** level); _gv_l_98 = _gv_l_98 + 1) begin : gen_level + localparam l = _gv_l_98; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:257:9 + wire sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:259:9 + localparam [31:0] Idx0 = ((2 ** level) - 1) + l; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:260:9 + localparam [31:0] Idx1 = ((2 ** (level + 1)) - 1) + (l * 2); + if ($unsigned(level) == (NumLevels - 1)) begin : gen_first_level + if (($unsigned(l) * 2) < (NumIn - 1)) begin : gen_reduce + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:266:13 + assign req_nodes[Idx0] = req_d[l * 2] | req_d[(l * 2) + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:269:13 + assign sel = ~req_d[l * 2] | (req_d[(l * 2) + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:271:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(sel); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:272:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] = (sel ? data_i[((l * 2) + 1) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] : data_i[(l * 2) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:273:13 + assign gnt_o[l * 2] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2])) & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:274:13 + assign gnt_o[(l * 2) + 1] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[(l * 2) + 1])) & sel; + end + if (($unsigned(l) * 2) == (NumIn - 1)) begin : gen_first + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:278:13 + assign req_nodes[Idx0] = req_d[l * 2]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:279:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:280:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] = data_i[(l * 2) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:281:13 + assign gnt_o[l * 2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2]); + end + if (($unsigned(l) * 2) > (NumIn - 1)) begin : gen_out_of_range + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:285:13 + assign req_nodes[Idx0] = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:286:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(1'sb0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:287:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] = sv2v_cast_9F378(1'sb0); + end + end + else begin : gen_other_levels + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:292:11 + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1 + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:295:11 + assign sel = ~req_nodes[Idx1] | (req_nodes[Idx1 + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:297:11 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = (sel ? sv2v_cast_5FDFE({1'b1, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]}) : sv2v_cast_5FDFE({1'b0, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]})); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:301:11 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] = (sel ? data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] : data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * (((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:302:11 + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:303:11 + assign gnt_nodes[Idx1 + 1] = gnt_nodes[Idx0] & sel; + end + end + end + end + endgenerate +endmodule +module rr_arb_tree_25334_B05A2 ( + clk_i, + rst_ni, + flush_i, + rr_i, + req_i, + gnt_o, + data_i, + req_o, + gnt_i, + data_o, + idx_o +); + // removed localparam type DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth_type + // removed localparam type DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves_type + // removed localparam type DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth_type + parameter [31:0] DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:49:13 + parameter [31:0] NumIn = 64; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:51:13 + parameter [31:0] DataWidth = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:53:26 + // removed localparam type DataType + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:60:13 + parameter [0:0] ExtPrio = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:67:13 + parameter [0:0] AxiVldRdy = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:74:13 + parameter [0:0] LockIn = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:78:13 + parameter [0:0] FairArb = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:81:13 + parameter [31:0] IdxWidth = (NumIn > 32'd1 ? $unsigned($clog2(NumIn)) : 32'd1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:84:26 + // removed localparam type idx_t + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:87:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:89:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:91:3 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:93:3 + input wire [IdxWidth - 1:0] rr_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:95:3 + input wire [NumIn - 1:0] req_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:98:3 + output wire [NumIn - 1:0] gnt_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:101:3 + input wire [(NumIn * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:103:3 + output wire req_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:105:3 + input wire gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:107:3 + output wire [(((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:109:3 + output wire [IdxWidth - 1:0] idx_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:122:3 + function automatic [IdxWidth - 1:0] sv2v_cast_5FDFE; + input reg [IdxWidth - 1:0] inp; + sv2v_cast_5FDFE = inp; + endfunction + function automatic [(((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] sv2v_cast_7F7BA; + input reg [(((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] inp; + sv2v_cast_7F7BA = inp; + endfunction + generate + if (NumIn == $unsigned(1)) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:123:5 + assign req_o = req_i[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:124:5 + assign gnt_o[0] = gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:125:5 + assign data_o = data_i[0+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:126:5 + assign idx_o = 1'sb0; + end + else begin : gen_arbiter + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:129:5 + localparam [31:0] NumLevels = $unsigned($clog2(NumIn)); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:132:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * IdxWidth) - 1 : ((3 - (2 ** NumLevels)) * IdxWidth) + ((((2 ** NumLevels) - 2) * IdxWidth) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * IdxWidth)] index_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:133:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)) - 1 : ((3 - (2 ** NumLevels)) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)) + ((((2 ** NumLevels) - 2) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth))] data_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:134:5 + wire [(2 ** NumLevels) - 2:0] gnt_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:135:5 + wire [(2 ** NumLevels) - 2:0] req_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:137:5 + reg [IdxWidth - 1:0] rr_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:138:5 + wire [NumIn - 1:0] req_d; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:141:5 + assign req_o = req_nodes[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:142:5 + assign data_o = data_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:143:5 + assign idx_o = index_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * IdxWidth+:IdxWidth]; + if (ExtPrio) begin : gen_ext_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:146:7 + wire [IdxWidth:1] sv2v_tmp_0900B; + assign sv2v_tmp_0900B = rr_i; + always @(*) rr_q = sv2v_tmp_0900B; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:147:7 + assign req_d = req_i; + end + else begin : gen_int_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:149:7 + wire [IdxWidth - 1:0] rr_d; + if (LockIn) begin : gen_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:153:9 + wire lock_d; + reg lock_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:154:9 + reg [NumIn - 1:0] req_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:156:9 + assign lock_d = req_o & ~gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:157:9 + assign req_d = (lock_q ? req_q : req_i); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:159:9 + always @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:160:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:161:13 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:163:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:164:15 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:166:15 + lock_q <= lock_d; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:187:9 + always @(posedge clk_i or negedge rst_ni) begin : p_req_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:188:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:189:13 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:191:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:192:15 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:194:15 + req_q <= req_d; + end + end + else begin : gen_no_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:199:9 + assign req_d = req_i; + end + if (FairArb) begin : gen_fair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:203:9 + wire [NumIn - 1:0] upper_mask; + wire [NumIn - 1:0] lower_mask; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:204:9 + wire [IdxWidth - 1:0] upper_idx; + wire [IdxWidth - 1:0] lower_idx; + wire [IdxWidth - 1:0] next_idx; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:205:9 + wire upper_empty; + wire lower_empty; + genvar _gv_i_59; + for (_gv_i_59 = 0; _gv_i_59 < NumIn; _gv_i_59 = _gv_i_59 + 1) begin : gen_mask + localparam i = _gv_i_59; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:208:11 + assign upper_mask[i] = (i > rr_q ? req_d[i] : 1'b0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:209:11 + assign lower_mask[i] = (i <= rr_q ? req_d[i] : 1'b0); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:212:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_upper( + .in_i(upper_mask), + .cnt_o(upper_idx), + .empty_o(upper_empty) + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:221:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_lower( + .in_i(lower_mask), + .cnt_o(lower_idx), + .empty_o() + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:230:9 + assign next_idx = (upper_empty ? lower_idx : upper_idx); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:231:9 + assign rr_d = (gnt_i && req_o ? next_idx : rr_q); + end + else begin : gen_unfair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:234:9 + assign rr_d = (gnt_i && req_o ? (rr_q == sv2v_cast_5FDFE(NumIn - 1) ? {IdxWidth {1'sb0}} : rr_q + 1'b1) : rr_q); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:238:7 + always @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:239:9 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:240:11 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:242:11 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:243:13 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:245:13 + rr_q <= rr_d; + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:251:5 + assign gnt_nodes[0] = gnt_i; + genvar _gv_level_1; + for (_gv_level_1 = 0; $unsigned(_gv_level_1) < NumLevels; _gv_level_1 = _gv_level_1 + 1) begin : gen_levels + localparam level = _gv_level_1; + genvar _gv_l_98; + for (_gv_l_98 = 0; _gv_l_98 < (2 ** level); _gv_l_98 = _gv_l_98 + 1) begin : gen_level + localparam l = _gv_l_98; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:257:9 + wire sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:259:9 + localparam [31:0] Idx0 = ((2 ** level) - 1) + l; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:260:9 + localparam [31:0] Idx1 = ((2 ** (level + 1)) - 1) + (l * 2); + if ($unsigned(level) == (NumLevels - 1)) begin : gen_first_level + if (($unsigned(l) * 2) < (NumIn - 1)) begin : gen_reduce + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:266:13 + assign req_nodes[Idx0] = req_d[l * 2] | req_d[(l * 2) + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:269:13 + assign sel = ~req_d[l * 2] | (req_d[(l * 2) + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:271:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(sel); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:272:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] = (sel ? data_i[((l * 2) + 1) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] : data_i[(l * 2) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:273:13 + assign gnt_o[l * 2] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2])) & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:274:13 + assign gnt_o[(l * 2) + 1] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[(l * 2) + 1])) & sel; + end + if (($unsigned(l) * 2) == (NumIn - 1)) begin : gen_first + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:278:13 + assign req_nodes[Idx0] = req_d[l * 2]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:279:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:280:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] = data_i[(l * 2) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:281:13 + assign gnt_o[l * 2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2]); + end + if (($unsigned(l) * 2) > (NumIn - 1)) begin : gen_out_of_range + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:285:13 + assign req_nodes[Idx0] = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:286:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(1'sb0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:287:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] = sv2v_cast_7F7BA(1'sb0); + end + end + else begin : gen_other_levels + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:292:11 + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1 + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:295:11 + assign sel = ~req_nodes[Idx1] | (req_nodes[Idx1 + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:297:11 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = (sel ? sv2v_cast_5FDFE({1'b1, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]}) : sv2v_cast_5FDFE({1'b0, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]})); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:301:11 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] = (sel ? data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] : data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * (((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:302:11 + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:303:11 + assign gnt_nodes[Idx1 + 1] = gnt_nodes[Idx0] & sel; + end + end + end + end + endgenerate +endmodule +module rr_arb_tree_7C886_BBDFA ( + clk_i, + rst_ni, + flush_i, + rr_i, + req_i, + gnt_o, + data_i, + req_o, + gnt_i, + data_o, + idx_o +); + // removed localparam type DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters_type + // removed localparam type DataType_b_chan_t_slv_b_chan_t_AxiUserWidth_type + parameter [31:0] DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] DataType_b_chan_t_slv_b_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:49:13 + parameter [31:0] NumIn = 64; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:51:13 + parameter [31:0] DataWidth = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:53:26 + // removed localparam type DataType + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:60:13 + parameter [0:0] ExtPrio = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:67:13 + parameter [0:0] AxiVldRdy = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:74:13 + parameter [0:0] LockIn = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:78:13 + parameter [0:0] FairArb = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:81:13 + parameter [31:0] IdxWidth = (NumIn > 32'd1 ? $unsigned($clog2(NumIn)) : 32'd1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:84:26 + // removed localparam type idx_t + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:87:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:89:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:91:3 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:93:3 + input wire [IdxWidth - 1:0] rr_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:95:3 + input wire [NumIn - 1:0] req_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:98:3 + output wire [NumIn - 1:0] gnt_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:101:3 + input wire [(NumIn * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:103:3 + output wire req_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:105:3 + input wire gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:107:3 + output wire [((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:109:3 + output wire [IdxWidth - 1:0] idx_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:122:3 + function automatic [IdxWidth - 1:0] sv2v_cast_5FDFE; + input reg [IdxWidth - 1:0] inp; + sv2v_cast_5FDFE = inp; + endfunction + function automatic [((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] sv2v_cast_559F1; + input reg [((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] inp; + sv2v_cast_559F1 = inp; + endfunction + generate + if (NumIn == $unsigned(1)) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:123:5 + assign req_o = req_i[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:124:5 + assign gnt_o[0] = gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:125:5 + assign data_o = data_i[0+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:126:5 + assign idx_o = 1'sb0; + end + else begin : gen_arbiter + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:129:5 + localparam [31:0] NumLevels = $unsigned($clog2(NumIn)); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:132:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * IdxWidth) - 1 : ((3 - (2 ** NumLevels)) * IdxWidth) + ((((2 ** NumLevels) - 2) * IdxWidth) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * IdxWidth)] index_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:133:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)) - 1 : ((3 - (2 ** NumLevels)) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)) + ((((2 ** NumLevels) - 2) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth))] data_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:134:5 + wire [(2 ** NumLevels) - 2:0] gnt_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:135:5 + wire [(2 ** NumLevels) - 2:0] req_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:137:5 + reg [IdxWidth - 1:0] rr_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:138:5 + wire [NumIn - 1:0] req_d; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:141:5 + assign req_o = req_nodes[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:142:5 + assign data_o = data_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:143:5 + assign idx_o = index_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * IdxWidth+:IdxWidth]; + if (ExtPrio) begin : gen_ext_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:146:7 + wire [IdxWidth:1] sv2v_tmp_0900B; + assign sv2v_tmp_0900B = rr_i; + always @(*) rr_q = sv2v_tmp_0900B; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:147:7 + assign req_d = req_i; + end + else begin : gen_int_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:149:7 + wire [IdxWidth - 1:0] rr_d; + if (LockIn) begin : gen_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:153:9 + wire lock_d; + reg lock_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:154:9 + reg [NumIn - 1:0] req_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:156:9 + assign lock_d = req_o & ~gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:157:9 + assign req_d = (lock_q ? req_q : req_i); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:159:9 + always @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:160:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:161:13 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:163:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:164:15 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:166:15 + lock_q <= lock_d; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:187:9 + always @(posedge clk_i or negedge rst_ni) begin : p_req_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:188:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:189:13 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:191:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:192:15 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:194:15 + req_q <= req_d; + end + end + else begin : gen_no_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:199:9 + assign req_d = req_i; + end + if (FairArb) begin : gen_fair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:203:9 + wire [NumIn - 1:0] upper_mask; + wire [NumIn - 1:0] lower_mask; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:204:9 + wire [IdxWidth - 1:0] upper_idx; + wire [IdxWidth - 1:0] lower_idx; + wire [IdxWidth - 1:0] next_idx; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:205:9 + wire upper_empty; + wire lower_empty; + genvar _gv_i_59; + for (_gv_i_59 = 0; _gv_i_59 < NumIn; _gv_i_59 = _gv_i_59 + 1) begin : gen_mask + localparam i = _gv_i_59; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:208:11 + assign upper_mask[i] = (i > rr_q ? req_d[i] : 1'b0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:209:11 + assign lower_mask[i] = (i <= rr_q ? req_d[i] : 1'b0); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:212:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_upper( + .in_i(upper_mask), + .cnt_o(upper_idx), + .empty_o(upper_empty) + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:221:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_lower( + .in_i(lower_mask), + .cnt_o(lower_idx), + .empty_o() + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:230:9 + assign next_idx = (upper_empty ? lower_idx : upper_idx); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:231:9 + assign rr_d = (gnt_i && req_o ? next_idx : rr_q); + end + else begin : gen_unfair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:234:9 + assign rr_d = (gnt_i && req_o ? (rr_q == sv2v_cast_5FDFE(NumIn - 1) ? {IdxWidth {1'sb0}} : rr_q + 1'b1) : rr_q); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:238:7 + always @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:239:9 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:240:11 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:242:11 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:243:13 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:245:13 + rr_q <= rr_d; + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:251:5 + assign gnt_nodes[0] = gnt_i; + genvar _gv_level_1; + for (_gv_level_1 = 0; $unsigned(_gv_level_1) < NumLevels; _gv_level_1 = _gv_level_1 + 1) begin : gen_levels + localparam level = _gv_level_1; + genvar _gv_l_98; + for (_gv_l_98 = 0; _gv_l_98 < (2 ** level); _gv_l_98 = _gv_l_98 + 1) begin : gen_level + localparam l = _gv_l_98; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:257:9 + wire sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:259:9 + localparam [31:0] Idx0 = ((2 ** level) - 1) + l; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:260:9 + localparam [31:0] Idx1 = ((2 ** (level + 1)) - 1) + (l * 2); + if ($unsigned(level) == (NumLevels - 1)) begin : gen_first_level + if (($unsigned(l) * 2) < (NumIn - 1)) begin : gen_reduce + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:266:13 + assign req_nodes[Idx0] = req_d[l * 2] | req_d[(l * 2) + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:269:13 + assign sel = ~req_d[l * 2] | (req_d[(l * 2) + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:271:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(sel); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:272:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth] = (sel ? data_i[((l * 2) + 1) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth] : data_i[(l * 2) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:273:13 + assign gnt_o[l * 2] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2])) & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:274:13 + assign gnt_o[(l * 2) + 1] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[(l * 2) + 1])) & sel; + end + if (($unsigned(l) * 2) == (NumIn - 1)) begin : gen_first + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:278:13 + assign req_nodes[Idx0] = req_d[l * 2]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:279:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:280:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth] = data_i[(l * 2) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:281:13 + assign gnt_o[l * 2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2]); + end + if (($unsigned(l) * 2) > (NumIn - 1)) begin : gen_out_of_range + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:285:13 + assign req_nodes[Idx0] = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:286:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(1'sb0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:287:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth] = sv2v_cast_559F1(1'sb0); + end + end + else begin : gen_other_levels + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:292:11 + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1 + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:295:11 + assign sel = ~req_nodes[Idx1] | (req_nodes[Idx1 + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:297:11 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = (sel ? sv2v_cast_5FDFE({1'b1, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]}) : sv2v_cast_5FDFE({1'b0, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]})); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:301:11 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth] = (sel ? data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth] : data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * ((DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + DataType_b_chan_t_slv_b_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:302:11 + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:303:11 + assign gnt_nodes[Idx1 + 1] = gnt_nodes[Idx0] & sel; + end + end + end + end + endgenerate +endmodule +module rr_arb_tree_CBFCA_FCD03 ( + clk_i, + rst_ni, + flush_i, + rr_i, + req_i, + gnt_o, + data_i, + req_o, + gnt_i, + data_o, + idx_o +); + // removed localparam type DataType_r_chan_t_slv_r_chan_t_AxiDataWidth_type + // removed localparam type DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters_type + // removed localparam type DataType_r_chan_t_slv_r_chan_t_AxiUserWidth_type + parameter [31:0] DataType_r_chan_t_slv_r_chan_t_AxiDataWidth = 0; + parameter [31:0] DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] DataType_r_chan_t_slv_r_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:49:13 + parameter [31:0] NumIn = 64; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:51:13 + parameter [31:0] DataWidth = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:53:26 + // removed localparam type DataType + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:60:13 + parameter [0:0] ExtPrio = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:67:13 + parameter [0:0] AxiVldRdy = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:74:13 + parameter [0:0] LockIn = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:78:13 + parameter [0:0] FairArb = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:81:13 + parameter [31:0] IdxWidth = (NumIn > 32'd1 ? $unsigned($clog2(NumIn)) : 32'd1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:84:26 + // removed localparam type idx_t + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:87:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:89:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:91:3 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:93:3 + input wire [IdxWidth - 1:0] rr_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:95:3 + input wire [NumIn - 1:0] req_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:98:3 + output wire [NumIn - 1:0] gnt_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:101:3 + input wire [(NumIn * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:103:3 + output wire req_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:105:3 + input wire gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:107:3 + output wire [(((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:109:3 + output wire [IdxWidth - 1:0] idx_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:122:3 + function automatic [IdxWidth - 1:0] sv2v_cast_5FDFE; + input reg [IdxWidth - 1:0] inp; + sv2v_cast_5FDFE = inp; + endfunction + function automatic [(((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] sv2v_cast_D586D; + input reg [(((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] inp; + sv2v_cast_D586D = inp; + endfunction + generate + if (NumIn == $unsigned(1)) begin : gen_pass_through + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:123:5 + assign req_o = req_i[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:124:5 + assign gnt_o[0] = gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:125:5 + assign data_o = data_i[0+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:126:5 + assign idx_o = 1'sb0; + end + else begin : gen_arbiter + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:129:5 + localparam [31:0] NumLevels = $unsigned($clog2(NumIn)); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:132:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * IdxWidth) - 1 : ((3 - (2 ** NumLevels)) * IdxWidth) + ((((2 ** NumLevels) - 2) * IdxWidth) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * IdxWidth)] index_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:133:5 + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)) - 1 : ((3 - (2 ** NumLevels)) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)) + ((((2 ** NumLevels) - 2) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth))] data_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:134:5 + wire [(2 ** NumLevels) - 2:0] gnt_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:135:5 + wire [(2 ** NumLevels) - 2:0] req_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:137:5 + reg [IdxWidth - 1:0] rr_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:138:5 + wire [NumIn - 1:0] req_d; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:141:5 + assign req_o = req_nodes[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:142:5 + assign data_o = data_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:143:5 + assign idx_o = index_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * IdxWidth+:IdxWidth]; + if (ExtPrio) begin : gen_ext_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:146:7 + wire [IdxWidth:1] sv2v_tmp_0900B; + assign sv2v_tmp_0900B = rr_i; + always @(*) rr_q = sv2v_tmp_0900B; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:147:7 + assign req_d = req_i; + end + else begin : gen_int_rr + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:149:7 + wire [IdxWidth - 1:0] rr_d; + if (LockIn) begin : gen_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:153:9 + wire lock_d; + reg lock_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:154:9 + reg [NumIn - 1:0] req_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:156:9 + assign lock_d = req_o & ~gnt_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:157:9 + assign req_d = (lock_q ? req_q : req_i); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:159:9 + always @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:160:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:161:13 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:163:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:164:15 + lock_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:166:15 + lock_q <= lock_d; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:187:9 + always @(posedge clk_i or negedge rst_ni) begin : p_req_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:188:11 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:189:13 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:191:13 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:192:15 + req_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:194:15 + req_q <= req_d; + end + end + else begin : gen_no_lock + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:199:9 + assign req_d = req_i; + end + if (FairArb) begin : gen_fair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:203:9 + wire [NumIn - 1:0] upper_mask; + wire [NumIn - 1:0] lower_mask; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:204:9 + wire [IdxWidth - 1:0] upper_idx; + wire [IdxWidth - 1:0] lower_idx; + wire [IdxWidth - 1:0] next_idx; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:205:9 + wire upper_empty; + wire lower_empty; + genvar _gv_i_59; + for (_gv_i_59 = 0; _gv_i_59 < NumIn; _gv_i_59 = _gv_i_59 + 1) begin : gen_mask + localparam i = _gv_i_59; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:208:11 + assign upper_mask[i] = (i > rr_q ? req_d[i] : 1'b0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:209:11 + assign lower_mask[i] = (i <= rr_q ? req_d[i] : 1'b0); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:212:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_upper( + .in_i(upper_mask), + .cnt_o(upper_idx), + .empty_o(upper_empty) + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:221:9 + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_lower( + .in_i(lower_mask), + .cnt_o(lower_idx), + .empty_o() + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:230:9 + assign next_idx = (upper_empty ? lower_idx : upper_idx); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:231:9 + assign rr_d = (gnt_i && req_o ? next_idx : rr_q); + end + else begin : gen_unfair_arb + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:234:9 + assign rr_d = (gnt_i && req_o ? (rr_q == sv2v_cast_5FDFE(NumIn - 1) ? {IdxWidth {1'sb0}} : rr_q + 1'b1) : rr_q); + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:238:7 + always @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:239:9 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:240:11 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:242:11 + if (flush_i) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:243:13 + rr_q <= 1'sb0; + else + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:245:13 + rr_q <= rr_d; + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:251:5 + assign gnt_nodes[0] = gnt_i; + genvar _gv_level_1; + for (_gv_level_1 = 0; $unsigned(_gv_level_1) < NumLevels; _gv_level_1 = _gv_level_1 + 1) begin : gen_levels + localparam level = _gv_level_1; + genvar _gv_l_98; + for (_gv_l_98 = 0; _gv_l_98 < (2 ** level); _gv_l_98 = _gv_l_98 + 1) begin : gen_level + localparam l = _gv_l_98; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:257:9 + wire sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:259:9 + localparam [31:0] Idx0 = ((2 ** level) - 1) + l; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:260:9 + localparam [31:0] Idx1 = ((2 ** (level + 1)) - 1) + (l * 2); + if ($unsigned(level) == (NumLevels - 1)) begin : gen_first_level + if (($unsigned(l) * 2) < (NumIn - 1)) begin : gen_reduce + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:266:13 + assign req_nodes[Idx0] = req_d[l * 2] | req_d[(l * 2) + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:269:13 + assign sel = ~req_d[l * 2] | (req_d[(l * 2) + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:271:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(sel); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:272:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth] = (sel ? data_i[((l * 2) + 1) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth] : data_i[(l * 2) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:273:13 + assign gnt_o[l * 2] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2])) & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:274:13 + assign gnt_o[(l * 2) + 1] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[(l * 2) + 1])) & sel; + end + if (($unsigned(l) * 2) == (NumIn - 1)) begin : gen_first + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:278:13 + assign req_nodes[Idx0] = req_d[l * 2]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:279:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:280:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth] = data_i[(l * 2) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:281:13 + assign gnt_o[l * 2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2]); + end + if (($unsigned(l) * 2) > (NumIn - 1)) begin : gen_out_of_range + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:285:13 + assign req_nodes[Idx0] = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:286:13 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(1'sb0); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:287:13 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth] = sv2v_cast_D586D(1'sb0); + end + end + else begin : gen_other_levels + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:292:11 + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1 + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:295:11 + assign sel = ~req_nodes[Idx1] | (req_nodes[Idx1 + 1] & rr_q[(NumLevels - 1) - level]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:297:11 + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = (sel ? sv2v_cast_5FDFE({1'b1, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]}) : sv2v_cast_5FDFE({1'b0, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]})); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:301:11 + assign data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth] = (sel ? data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth] : data_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * (((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + DataType_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + DataType_r_chan_t_slv_r_chan_t_AxiUserWidth]); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:302:11 + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/rr_arb_tree.sv:303:11 + assign gnt_nodes[Idx1 + 1] = gnt_nodes[Idx0] & sel; + end + end + end + end + endgenerate +endmodule +module spill_register_03B00_458D1 ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_SelectWidth_type + // removed localparam type T_ar_chan_t_slv_ar_chan_t_AxiAddrWidth_type + // removed localparam type T_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters_type + // removed localparam type T_ar_chan_t_slv_ar_chan_t_AxiUserWidth_type + parameter [31:0] T_SelectWidth = 0; + parameter [31:0] T_ar_chan_t_slv_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] T_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] T_ar_chan_t_slv_ar_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [((((T_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + T_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + T_ar_chan_t_slv_ar_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [((((T_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + T_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + T_ar_chan_t_slv_ar_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [((((T_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + T_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + T_ar_chan_t_slv_ar_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [((((T_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + T_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + T_ar_chan_t_slv_ar_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_21A26_75D51 ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_r_chan_t_slv_r_chan_t_AxiDataWidth_type + // removed localparam type T_r_chan_t_slv_r_chan_t_AxiIdWidthMasters_type + // removed localparam type T_r_chan_t_slv_r_chan_t_AxiUserWidth_type + parameter [31:0] T_r_chan_t_slv_r_chan_t_AxiDataWidth = 0; + parameter [31:0] T_r_chan_t_slv_r_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] T_r_chan_t_slv_r_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [(((T_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + T_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + T_r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [(((T_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + T_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + T_r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [(((T_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + T_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + T_r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [(((T_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + T_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + T_r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_2E020_83570 ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_w_chan_t_w_chan_t_AxiDataWidth_type + // removed localparam type T_w_chan_t_w_chan_t_AxiStrbWidth_type + // removed localparam type T_w_chan_t_w_chan_t_AxiUserWidth_type + parameter [31:0] T_w_chan_t_w_chan_t_AxiDataWidth = 0; + parameter [31:0] T_w_chan_t_w_chan_t_AxiStrbWidth = 0; + parameter [31:0] T_w_chan_t_w_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [(((T_w_chan_t_w_chan_t_AxiDataWidth + T_w_chan_t_w_chan_t_AxiStrbWidth) + 1) + T_w_chan_t_w_chan_t_AxiUserWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [(((T_w_chan_t_w_chan_t_AxiDataWidth + T_w_chan_t_w_chan_t_AxiStrbWidth) + 1) + T_w_chan_t_w_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [(((T_w_chan_t_w_chan_t_AxiDataWidth + T_w_chan_t_w_chan_t_AxiStrbWidth) + 1) + T_w_chan_t_w_chan_t_AxiUserWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [(((T_w_chan_t_w_chan_t_AxiDataWidth + T_w_chan_t_w_chan_t_AxiStrbWidth) + 1) + T_w_chan_t_w_chan_t_AxiUserWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_476C7_0441D ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_b_chan_t_slv_b_chan_t_AxiIdWidthMasters_type + // removed localparam type T_b_chan_t_slv_b_chan_t_AxiUserWidth_type + parameter [31:0] T_b_chan_t_slv_b_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] T_b_chan_t_slv_b_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [((T_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + T_b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [((T_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + T_b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [((T_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + T_b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [((T_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + T_b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_B26F0_61C30 ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_SelectWidth_type + // removed localparam type T_aw_chan_t_slv_aw_chan_t_AxiAddrWidth_type + // removed localparam type T_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters_type + // removed localparam type T_aw_chan_t_slv_aw_chan_t_AxiUserWidth_type + parameter [31:0] T_SelectWidth = 0; + parameter [31:0] T_aw_chan_t_slv_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] T_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] T_aw_chan_t_slv_aw_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [((((T_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + T_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + T_aw_chan_t_slv_aw_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [((((T_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + T_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + T_aw_chan_t_slv_aw_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [((((T_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + T_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + T_aw_chan_t_slv_aw_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [((((T_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + T_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + T_aw_chan_t_slv_aw_chan_t_AxiUserWidth) + T_SelectWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_BBFDC_153AC ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_mst_r_chan_t_mst_r_chan_t_AxiDataWidth_type + // removed localparam type T_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves_type + // removed localparam type T_mst_r_chan_t_mst_r_chan_t_AxiUserWidth_type + parameter [31:0] T_mst_r_chan_t_mst_r_chan_t_AxiDataWidth = 0; + parameter [31:0] T_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] T_mst_r_chan_t_mst_r_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [(((T_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + T_mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + T_mst_r_chan_t_mst_r_chan_t_AxiUserWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [(((T_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + T_mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + T_mst_r_chan_t_mst_r_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [(((T_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + T_mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + T_mst_r_chan_t_mst_r_chan_t_AxiUserWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [(((T_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + T_mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + T_mst_r_chan_t_mst_r_chan_t_AxiUserWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_CA6B6_8B0C4 ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth_type + // removed localparam type T_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves_type + // removed localparam type T_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth_type + parameter [31:0] T_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] T_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] T_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [(((T_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + T_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + T_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [(((T_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + T_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + T_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [(((T_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + T_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + T_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [(((T_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + T_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + T_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_D0F05_A8961 ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves_type + // removed localparam type T_mst_b_chan_t_mst_b_chan_t_AxiUserWidth_type + parameter [31:0] T_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] T_mst_b_chan_t_mst_b_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [((T_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + T_mst_b_chan_t_mst_b_chan_t_AxiUserWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [((T_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + T_mst_b_chan_t_mst_b_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [((T_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + T_mst_b_chan_t_mst_b_chan_t_AxiUserWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [((T_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + T_mst_b_chan_t_mst_b_chan_t_AxiUserWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +module spill_register_D20CE_48F44 ( + clk_i, + rst_ni, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // removed localparam type T_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth_type + // removed localparam type T_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves_type + // removed localparam type T_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth_type + parameter [31:0] T_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] T_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] T_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:18:18 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:19:13 + parameter [0:0] Bypass = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:21:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:22:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:23:3 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:24:3 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:25:3 + input wire [(((T_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + T_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + T_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:26:3 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:27:3 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:28:3 + output wire [(((T_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + T_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + T_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:31:3 + generate + if (Bypass) begin : gen_bypass + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:32:5 + assign valid_o = valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:33:5 + assign ready_o = ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:34:5 + assign data_o = data_i; + end + else begin : gen_spill_reg + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:37:5 + reg [(((T_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + T_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + T_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] a_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:38:5 + reg a_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:39:5 + wire a_fill; + wire a_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:40:5 + wire a_en; + wire a_en_data; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:42:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:43:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:44:9 + a_data_q <= 1'sb0; + else if (a_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:46:9 + a_data_q <= data_i; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:49:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_a_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:50:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:51:9 + a_full_q <= 0; + else if (a_fill || a_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:53:9 + a_full_q <= a_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:57:5 + reg [(((T_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + T_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + T_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] b_data_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:58:5 + reg b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:59:5 + wire b_fill; + wire b_drain; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:61:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_data + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:62:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:63:9 + b_data_q <= 1'sb0; + else if (b_fill) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:65:9 + b_data_q <= a_data_q; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:68:5 + always @(posedge clk_i or negedge rst_ni) begin : ps_b_full + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:69:7 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:70:9 + b_full_q <= 0; + else if (b_fill || b_drain) + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:72:9 + b_full_q <= b_fill; + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:77:5 + assign a_fill = valid_i && ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:78:5 + assign a_drain = a_full_q && !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:83:5 + assign b_fill = a_drain && !ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:84:5 + assign b_drain = b_full_q && ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:87:5 + assign ready_o = !a_full_q || !b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:90:5 + assign valid_o = a_full_q | b_full_q; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/spill_register.sv:93:5 + assign data_o = (b_full_q ? b_data_q : a_data_q); + end + endgenerate +endmodule +// removed interface: STREAM_DV +module addr_decode_727A6_BF551 ( + addr_i, + addr_map_i, + idx_o, + dec_valid_o, + dec_error_o, + en_default_idx_i, + default_idx_i +); + // removed localparam type addr_t_Cfg_type + parameter [298:0] addr_t_Cfg = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:32:13 + parameter [31:0] NoIndices = 32'd0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:34:13 + parameter [31:0] NoRules = 32'd0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:36:26 + // removed localparam type addr_t + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:49:26 + // removed localparam type rule_t + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:53:13 + function automatic [31:0] cf_math_pkg_idx_width; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/cf_math_pkg.sv:57:52 + input reg [31:0] num_idx; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/cf_math_pkg.sv:58:9 + cf_math_pkg_idx_width = (num_idx > 32'd1 ? $unsigned($clog2(num_idx)) : 32'd1); + endfunction + parameter [31:0] IdxWidth = cf_math_pkg_idx_width(NoIndices); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:57:26 + // removed localparam type idx_t + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:60:3 + input wire [addr_t_Cfg[95-:32] - 1:0] addr_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:62:3 + input wire [(NoRules * 96) - 1:0] addr_map_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:64:3 + output reg [IdxWidth - 1:0] idx_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:66:3 + output reg dec_valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:68:3 + output reg dec_error_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:72:3 + input wire en_default_idx_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:78:3 + input wire [IdxWidth - 1:0] default_idx_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:81:3 + reg [NoRules - 1:0] matched_rules; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:83:3 + function automatic [IdxWidth - 1:0] sv2v_cast_5FDFE; + input reg [IdxWidth - 1:0] inp; + sv2v_cast_5FDFE = inp; + endfunction + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:85:5 + matched_rules = 1'sb0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:86:5 + dec_valid_o = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:87:5 + dec_error_o = (en_default_idx_i ? 1'b0 : 1'b1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:88:5 + idx_o = (en_default_idx_i ? default_idx_i : {IdxWidth {1'sb0}}); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:91:5 + begin : sv2v_autoblock_1 + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:91:10 + reg [31:0] i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:91:10 + for (i = 0; i < NoRules; i = i + 1) + begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:92:7 + if ((addr_i >= addr_map_i[(i * 96) + 63-:32]) && (addr_i < addr_map_i[(i * 96) + 31-:32])) begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:93:9 + matched_rules[i] = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:94:9 + dec_valid_o = 1'b1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:95:9 + dec_error_o = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv:96:9 + idx_o = sv2v_cast_5FDFE(addr_map_i[(i * 96) + 95-:32]); + end + end + end + end + initial _sv2v_0 = 0; +endmodule +module counter ( + clk_i, + rst_ni, + clear_i, + en_i, + load_i, + down_i, + d_i, + q_o, + overflow_o +); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:15:15 + parameter [31:0] WIDTH = 4; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:16:15 + parameter [0:0] STICKY_OVERFLOW = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:18:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:19:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:20:5 + input wire clear_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:21:5 + input wire en_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:22:5 + input wire load_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:23:5 + input wire down_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:24:5 + input wire [WIDTH - 1:0] d_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:25:5 + output wire [WIDTH - 1:0] q_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:26:5 + output wire overflow_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/counter.sv:28:5 + delta_counter #( + .WIDTH(WIDTH), + .STICKY_OVERFLOW(STICKY_OVERFLOW) + ) i_counter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clear_i(clear_i), + .en_i(en_i), + .load_i(load_i), + .down_i(down_i), + .delta_i({{WIDTH - 1 {1'b0}}, 1'b1}), + .d_i(d_i), + .q_o(q_o), + .overflow_o(overflow_o) + ); +endmodule +module lzc ( + in_i, + cnt_o, + empty_o +); + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:27:13 + parameter [31:0] WIDTH = 2; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:29:13 + parameter [0:0] MODE = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:33:13 + function automatic [31:0] cf_math_pkg_idx_width; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/cf_math_pkg.sv:57:52 + input reg [31:0] num_idx; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/cf_math_pkg.sv:58:9 + cf_math_pkg_idx_width = (num_idx > 32'd1 ? $unsigned($clog2(num_idx)) : 32'd1); + endfunction + parameter [31:0] CNT_WIDTH = cf_math_pkg_idx_width(WIDTH); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:36:3 + input wire [WIDTH - 1:0] in_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:38:3 + output wire [CNT_WIDTH - 1:0] cnt_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:40:3 + output wire empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:43:3 + generate + if (WIDTH == 1) begin : gen_degenerate_lzc + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:45:5 + assign cnt_o[0] = !in_i[0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:46:5 + assign empty_o = !in_i[0]; + end + else begin : gen_lzc + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:50:5 + localparam [31:0] NumLevels = $clog2(WIDTH); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:53:5 + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:58:5 + wire [(WIDTH * NumLevels) - 1:0] index_lut; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:59:5 + wire [(2 ** NumLevels) - 1:0] sel_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:60:5 + wire [((2 ** NumLevels) * NumLevels) - 1:0] index_nodes; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:62:5 + reg [WIDTH - 1:0] in_tmp; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:65:5 + always @(*) begin : flip_vector + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:66:7 + begin : sv2v_autoblock_1 + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:66:12 + reg [31:0] i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:66:12 + for (i = 0; i < WIDTH; i = i + 1) + begin + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:67:9 + in_tmp[i] = (MODE ? in_i[(WIDTH - 1) - i] : in_i[i]); + end + end + end + genvar _gv_j_11; + for (_gv_j_11 = 0; $unsigned(_gv_j_11) < WIDTH; _gv_j_11 = _gv_j_11 + 1) begin : g_index_lut + localparam j = _gv_j_11; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:72:7 + function automatic [NumLevels - 1:0] sv2v_cast_677FF; + input reg [NumLevels - 1:0] inp; + sv2v_cast_677FF = inp; + endfunction + assign index_lut[j * NumLevels+:NumLevels] = sv2v_cast_677FF($unsigned(j)); + end + genvar _gv_level_2; + for (_gv_level_2 = 0; $unsigned(_gv_level_2) < NumLevels; _gv_level_2 = _gv_level_2 + 1) begin : g_levels + localparam level = _gv_level_2; + if ($unsigned(level) == (NumLevels - 1)) begin : g_last_level + genvar _gv_k_6; + for (_gv_k_6 = 0; _gv_k_6 < (2 ** level); _gv_k_6 = _gv_k_6 + 1) begin : g_level + localparam k = _gv_k_6; + if (($unsigned(k) * 2) < (WIDTH - 1)) begin : g_reduce + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:80:13 + assign sel_nodes[((2 ** level) - 1) + k] = in_tmp[k * 2] | in_tmp[(k * 2) + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:81:13 + assign index_nodes[(((2 ** level) - 1) + k) * NumLevels+:NumLevels] = (in_tmp[k * 2] == 1'b1 ? index_lut[(k * 2) * NumLevels+:NumLevels] : index_lut[((k * 2) + 1) * NumLevels+:NumLevels]); + end + if (($unsigned(k) * 2) == (WIDTH - 1)) begin : g_base + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:87:13 + assign sel_nodes[((2 ** level) - 1) + k] = in_tmp[k * 2]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:88:13 + assign index_nodes[(((2 ** level) - 1) + k) * NumLevels+:NumLevels] = index_lut[(k * 2) * NumLevels+:NumLevels]; + end + if (($unsigned(k) * 2) > (WIDTH - 1)) begin : g_out_of_range + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:92:13 + assign sel_nodes[((2 ** level) - 1) + k] = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:93:13 + assign index_nodes[(((2 ** level) - 1) + k) * NumLevels+:NumLevels] = 1'sb0; + end + end + end + else begin : g_not_last_level + genvar _gv_l_99; + for (_gv_l_99 = 0; _gv_l_99 < (2 ** level); _gv_l_99 = _gv_l_99 + 1) begin : g_level + localparam l = _gv_l_99; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:98:11 + assign sel_nodes[((2 ** level) - 1) + l] = sel_nodes[((2 ** (level + 1)) - 1) + (l * 2)] | sel_nodes[(((2 ** (level + 1)) - 1) + (l * 2)) + 1]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:100:11 + assign index_nodes[(((2 ** level) - 1) + l) * NumLevels+:NumLevels] = (sel_nodes[((2 ** (level + 1)) - 1) + (l * 2)] == 1'b1 ? index_nodes[(((2 ** (level + 1)) - 1) + (l * 2)) * NumLevels+:NumLevels] : index_nodes[((((2 ** (level + 1)) - 1) + (l * 2)) + 1) * NumLevels+:NumLevels]); + end + end + end + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:107:5 + assign cnt_o = (NumLevels > $unsigned(0) ? index_nodes[0+:NumLevels] : {$clog2(WIDTH) {1'b0}}); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/lzc.sv:108:5 + assign empty_o = (NumLevels > $unsigned(0) ? ~sel_nodes[0] : ~(|in_i)); + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module stream_register_11179 ( + clk_i, + rst_ni, + clr_i, + testmode_i, + valid_i, + ready_o, + data_i, + valid_o, + ready_i, + data_o +); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:15:20 + // removed localparam type T + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:17:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:18:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:19:5 + input wire clr_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:20:5 + input wire testmode_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:22:5 + input wire valid_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:23:5 + output wire ready_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:24:5 + input wire [7:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:26:5 + output wire valid_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:27:5 + input wire ready_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:28:5 + output wire [7:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:31:5 + wire fifo_empty; + wire fifo_full; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:34:5 + fifo_v2_BC5B2 #( + .FALL_THROUGH(1'b0), + .DATA_WIDTH(8), + .DEPTH(1) + ) i_fifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(clr_i), + .testmode_i(testmode_i), + .full_o(fifo_full), + .empty_o(fifo_empty), + .alm_full_o(), + .alm_empty_o(), + .data_i(data_i), + .push_i(valid_i & ~fifo_full), + .data_o(data_o), + .pop_i(ready_i & ~fifo_empty) + ); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:54:5 + assign ready_o = ~fifo_full; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/stream_register.sv:55:5 + assign valid_o = ~fifo_empty; +endmodule +module fifo_v2_BC5B2 ( + clk_i, + rst_ni, + flush_i, + testmode_i, + full_o, + empty_o, + alm_full_o, + alm_empty_o, + data_i, + push_i, + data_o, + pop_i +); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:14:15 + parameter [0:0] FALL_THROUGH = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:15:15 + parameter [31:0] DATA_WIDTH = 32; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:16:15 + parameter [31:0] DEPTH = 8; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:17:15 + parameter [31:0] ALM_EMPTY_TH = 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:18:15 + parameter [31:0] ALM_FULL_TH = 1; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:19:20 + // removed localparam type dtype + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:21:15 + parameter [31:0] ADDR_DEPTH = (DEPTH > 1 ? $clog2(DEPTH) : 1); + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:23:5 + input wire clk_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:24:5 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:25:5 + input wire flush_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:26:5 + input wire testmode_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:28:5 + output wire full_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:29:5 + output wire empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:30:5 + output wire alm_full_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:31:5 + output wire alm_empty_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:33:5 + input wire [7:0] data_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:34:5 + input wire push_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:36:5 + output wire [7:0] data_o; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:37:5 + input wire pop_i; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:40:5 + wire [ADDR_DEPTH - 1:0] usage; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:43:5 + generate + if (DEPTH == 0) begin : genblk1 + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:44:9 + assign alm_full_o = 1'b0; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:45:9 + assign alm_empty_o = 1'b0; + end + else begin : genblk1 + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:47:9 + assign alm_full_o = usage >= ALM_FULL_TH[ADDR_DEPTH - 1:0]; + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:48:9 + assign alm_empty_o = usage <= ALM_EMPTY_TH[ADDR_DEPTH - 1:0]; + end + endgenerate + // Trace: ./src/pulp-platform.org__common_cells_1.20.0/src/deprecated/fifo_v2.sv:51:5 + fifo_v3_B0153 #( + .FALL_THROUGH(FALL_THROUGH), + .DATA_WIDTH(DATA_WIDTH), + .DEPTH(DEPTH) + ) i_fifo_v3( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(flush_i), + .testmode_i(testmode_i), + .full_o(full_o), + .empty_o(empty_o), + .usage_o(usage), + .data_i(data_i), + .push_i(push_i), + .data_o(data_o), + .pop_i(pop_i) + ); +endmodule +module raminfr ( + clk, + we, + a, + dpra, + di, + dpo +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:86:1 + parameter addr_width = 4; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:87:1 + parameter data_width = 8; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:88:1 + parameter depth = 16; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:90:1 + input clk; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:91:1 + input we; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:92:1 + input wire [addr_width - 1:0] a; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:93:1 + input wire [addr_width - 1:0] dpra; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:94:1 + input wire [data_width - 1:0] di; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:96:1 + output wire [data_width - 1:0] dpo; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:97:1 + reg [data_width - 1:0] ram [depth - 1:0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:99:1 + // combined with dpo + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:100:1 + // combined with di + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:101:1 + // combined with a + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:102:1 + // combined with dpra + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:104:3 + always @(posedge clk) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:105:5 + if (we) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:106:7 + ram[a] <= di; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/raminfr.v:109:3 + assign dpo = ram[dpra]; +endmodule +module uart_receiver ( + clk, + wb_rst_i, + lcr, + rf_pop, + srx_pad_i, + enable, + counter_t, + rf_count, + rf_data_out, + rf_error_bit, + rf_overrun, + rx_reset, + lsr_mask, + rstate, + rf_push_pulse +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:197:1 + input clk; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:198:1 + input wb_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:199:1 + input [7:0] lcr; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:200:1 + input wire rf_pop; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:201:1 + input srx_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:202:1 + input enable; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:203:1 + input rx_reset; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:204:1 + input lsr_mask; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:206:1 + output reg [9:0] counter_t; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:207:1 + output wire [4:0] rf_count; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:208:1 + output wire [10:0] rf_data_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:209:1 + output wire rf_overrun; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:210:1 + output wire rf_error_bit; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:211:1 + output reg [3:0] rstate; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:212:1 + output wire rf_push_pulse; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:214:1 + // combined with rstate + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:215:1 + reg [3:0] rcounter16; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:216:1 + reg [2:0] rbit_counter; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:217:1 + reg [7:0] rshift; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:218:1 + reg rparity; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:219:1 + reg rparity_error; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:220:1 + reg rframing_error; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:221:1 + reg rparity_xor; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:222:1 + reg [7:0] counter_b; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:223:1 + reg rf_push_q; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:226:1 + reg [10:0] rf_data_in; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:227:1 + // combined with rf_data_out + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:228:1 + // combined with rf_push_pulse + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:229:1 + reg rf_push; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:230:1 + // combined with rf_pop + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:231:1 + // combined with rf_overrun + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:232:1 + // combined with rf_count + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:233:1 + // combined with rf_error_bit + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:234:1 + wire break_error = counter_b == 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:237:1 + uart_rfifo #(.fifo_width(11)) fifo_rx( + .clk(clk), + .wb_rst_i(wb_rst_i), + .data_in(rf_data_in), + .data_out(rf_data_out), + .push(rf_push_pulse), + .pop(rf_pop), + .overrun(rf_overrun), + .count(rf_count), + .error_bit(rf_error_bit), + .fifo_reset(rx_reset), + .reset_status(lsr_mask) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:251:1 + wire rcounter16_eq_7 = rcounter16 == 4'd7; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:252:1 + wire rcounter16_eq_0 = rcounter16 == 4'd0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:254:1 + wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:256:1 + parameter sr_idle = 4'd0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:257:1 + parameter sr_rec_start = 4'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:258:1 + parameter sr_rec_bit = 4'd2; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:259:1 + parameter sr_rec_parity = 4'd3; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:260:1 + parameter sr_rec_stop = 4'd4; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:261:1 + parameter sr_check_parity = 4'd5; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:262:1 + parameter sr_rec_prepare = 4'd6; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:263:1 + parameter sr_end_bit = 4'd7; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:264:1 + parameter sr_ca_lc_parity = 4'd8; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:265:1 + parameter sr_wait1 = 4'd9; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:266:1 + parameter sr_push = 4'd10; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:269:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:271:3 + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:273:6 + rstate <= sr_idle; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:274:4 + rcounter16 <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:275:4 + rbit_counter <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:276:4 + rparity_xor <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:277:4 + rframing_error <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:278:4 + rparity_error <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:279:4 + rparity <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:280:4 + rshift <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:281:4 + rf_push <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:282:4 + rf_data_in <= 0; + end + else if (enable) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:287:2 + case (rstate) + sr_idle: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:289:4 + rf_push <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:290:4 + rf_data_in <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:291:4 + rcounter16 <= 4'b1110; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:292:4 + if ((srx_pad_i == 1'b0) & ~break_error) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:294:5 + rstate <= sr_rec_start; + end + sr_rec_start: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:298:6 + rf_push <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:299:5 + if (rcounter16_eq_7) begin + if (srx_pad_i == 1'b1) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:301:7 + rstate <= sr_idle; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:303:7 + rstate <= sr_rec_prepare; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:304:5 + rcounter16 <= rcounter16_minus_1; + end + sr_rec_prepare: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:307:5 + case (lcr[1:0]) + 2'b00: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:308:13 + rbit_counter <= 3'b100; + 2'b01: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:309:13 + rbit_counter <= 3'b101; + 2'b10: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:310:13 + rbit_counter <= 3'b110; + 2'b11: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:311:13 + rbit_counter <= 3'b111; + endcase + if (rcounter16_eq_0) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:315:6 + rstate <= sr_rec_bit; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:316:6 + rcounter16 <= 4'b1110; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:317:6 + rshift <= 0; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:320:6 + rstate <= sr_rec_prepare; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:321:5 + rcounter16 <= rcounter16_minus_1; + end + sr_rec_bit: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:324:5 + if (rcounter16_eq_0) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:325:6 + rstate <= sr_end_bit; + if (rcounter16_eq_7) + case (lcr[1:0]) + 2'b00: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:328:14 + rshift[4:0] <= {srx_pad_i, rshift[4:1]}; + 2'b01: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:329:14 + rshift[5:0] <= {srx_pad_i, rshift[5:1]}; + 2'b10: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:330:14 + rshift[6:0] <= {srx_pad_i, rshift[6:1]}; + 2'b11: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:331:14 + rshift[7:0] <= {srx_pad_i, rshift[7:1]}; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:333:5 + rcounter16 <= rcounter16_minus_1; + end + sr_end_bit: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:336:5 + if (rbit_counter == 3'b000) begin + if (lcr[3]) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:338:7 + rstate <= sr_rec_parity; + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:341:7 + rstate <= sr_rec_stop; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:342:7 + rparity_error <= 1'b0; + end + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:346:6 + rstate <= sr_rec_bit; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:347:6 + rbit_counter <= rbit_counter - 3'd1; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:349:5 + rcounter16 <= 4'b1110; + end + sr_rec_parity: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:352:5 + if (rcounter16_eq_7) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:354:6 + rparity <= srx_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:355:6 + rstate <= sr_ca_lc_parity; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:357:5 + rcounter16 <= rcounter16_minus_1; + end + sr_ca_lc_parity: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:360:5 + rcounter16 <= rcounter16_minus_1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:361:5 + rparity_xor <= ^{rshift, rparity}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:362:5 + rstate <= sr_check_parity; + end + sr_check_parity: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:365:5 + case ({lcr[4], lcr[5]}) + 2'b00: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:366:13 + rparity_error <= rparity_xor == 0; + 2'b01: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:367:13 + rparity_error <= ~rparity; + 2'b10: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:368:13 + rparity_error <= rparity_xor == 1; + 2'b11: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:369:13 + rparity_error <= rparity; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:371:5 + rcounter16 <= rcounter16_minus_1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:372:5 + rstate <= sr_wait1; + end + sr_wait1: + if (rcounter16_eq_0) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:376:5 + rstate <= sr_rec_stop; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:377:5 + rcounter16 <= 4'b1110; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:380:5 + rcounter16 <= rcounter16_minus_1; + sr_rec_stop: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:382:5 + if (rcounter16_eq_7) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:384:6 + rframing_error <= !srx_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:385:6 + rstate <= sr_push; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:387:5 + rcounter16 <= rcounter16_minus_1; + end + sr_push: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:392:9 + if (srx_pad_i | break_error) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:394:13 + if (break_error) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:395:13 + rf_data_in <= 11'b00000000100; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:397:12 + rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:398:11 + rf_push <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:399:9 + rstate <= sr_idle; + end + else if (~rframing_error) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:403:11 + rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:404:11 + rf_push <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:405:10 + rcounter16 <= 4'b1110; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:406:9 + rstate <= sr_rec_start; + end + default: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:410:12 + rstate <= sr_idle; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:415:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:417:3 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:418:5 + rf_push_q <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:420:5 + rf_push_q <= rf_push; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:423:1 + assign rf_push_pulse = rf_push & ~rf_push_q; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:430:1 + reg [9:0] toc_value; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:432:1 + always @(lcr) + case (lcr[3:0]) + 4'b0000: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:434:22 + toc_value = 447; + 4'b0100: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:435:22 + toc_value = 479; + 4'b0001, 4'b1000: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:436:28 + toc_value = 511; + 4'b1100: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:437:22 + toc_value = 543; + 4'b0010, 4'b0101, 4'b1001: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:438:34 + toc_value = 575; + 4'b0011, 4'b0110, 4'b1010, 4'b1101: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:439:40 + toc_value = 639; + 4'b0111, 4'b1011, 4'b1110: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:440:34 + toc_value = 703; + 4'b1111: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:441:22 + toc_value = 767; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:444:1 + wire [7:0] brc_value; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:445:1 + assign brc_value = toc_value[9:2]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:447:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:449:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:450:3 + counter_b <= 8'd159; + else if (srx_pad_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:453:3 + counter_b <= brc_value; + else if (enable & (counter_b != 8'b00000000)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:456:3 + counter_b <= counter_b - 8'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:461:1 + // combined with counter_t + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:463:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:465:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:466:3 + counter_t <= 10'd639; + else if ((rf_push_pulse || rf_pop) || (rf_count == 0)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:469:4 + counter_t <= toc_value; + else if (enable && (counter_t != 10'b0000000000)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_receiver.v:472:4 + counter_t <= counter_t - 10'd1; +endmodule +module uart_regs ( + clk, + wb_rst_i, + wb_addr_i, + wb_dat_i, + wb_dat_o, + wb_we_i, + wb_re_i, + modem_inputs, + stx_pad_o, + srx_pad_i, + rts_pad_o, + dtr_pad_o, + int_o +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:228:13 + parameter SIM = 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:243:1 + input clk; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:244:1 + input wb_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:245:1 + input wire [2:0] wb_addr_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:246:1 + input wire [7:0] wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:247:1 + output reg [7:0] wb_dat_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:248:1 + input wb_we_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:249:1 + input wb_re_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:251:1 + output wire stx_pad_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:252:1 + input wire srx_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:254:1 + input wire [3:0] modem_inputs; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:255:1 + output wire rts_pad_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:256:1 + output wire dtr_pad_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:257:1 + output reg int_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:262:1 + // combined with modem_inputs + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:263:1 + reg enable; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:269:1 + // combined with stx_pad_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:270:1 + // combined with srx_pad_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:271:1 + wire srx_pad; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:273:1 + // combined with wb_dat_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:275:1 + // combined with wb_addr_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:276:1 + // combined with wb_dat_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:279:1 + reg [3:0] ier; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:280:1 + reg [3:0] iir; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:281:1 + reg [1:0] fcr; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:282:1 + reg [4:0] mcr; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:283:1 + reg [7:0] lcr; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:284:1 + reg [7:0] msr; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:285:1 + reg [15:0] dl; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:286:1 + reg [7:0] scratch; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:287:1 + reg start_dlc; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:288:1 + reg lsr_mask_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:289:1 + reg msi_reset; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:291:1 + reg [15:0] dlc; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:292:1 + // combined with int_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:294:1 + reg [3:0] trigger_level; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:295:1 + reg rx_reset; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:296:1 + reg tx_reset; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:298:1 + wire dlab; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:299:1 + wire cts_pad_i; + wire dsr_pad_i; + wire ri_pad_i; + wire dcd_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:300:1 + wire loopback; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:301:1 + wire cts; + wire dsr; + wire ri; + wire dcd; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:302:1 + wire cts_c; + wire dsr_c; + wire ri_c; + wire dcd_c; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:303:1 + // combined with rts_pad_o + // combined with dtr_pad_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:306:1 + wire [7:0] lsr; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:307:1 + wire lsr0; + wire lsr1; + wire lsr2; + wire lsr3; + wire lsr4; + wire lsr5; + wire lsr6; + wire lsr7; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:308:1 + reg lsr0r; + reg lsr1r; + reg lsr2r; + reg lsr3r; + reg lsr4r; + reg lsr5r; + reg lsr6r; + reg lsr7r; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:309:1 + wire lsr_mask; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:315:1 + assign lsr[7:0] = {lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:317:1 + assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:318:1 + assign {cts, dsr, ri, dcd} = ~{cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:320:1 + assign {cts_c, dsr_c, ri_c, dcd_c} = (loopback ? {mcr[1], mcr[0], mcr[2], mcr[3]} : {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i}); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:323:1 + assign dlab = lcr[7]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:324:1 + assign loopback = mcr[4]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:327:1 + assign rts_pad_o = mcr[1]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:328:1 + assign dtr_pad_o = mcr[0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:331:1 + wire rls_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:332:1 + wire rda_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:333:1 + wire ti_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:334:1 + wire thre_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:335:1 + wire ms_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:338:1 + reg tf_push; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:339:1 + reg rf_pop; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:340:1 + wire [10:0] rf_data_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:341:1 + wire rf_error_bit; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:342:1 + wire rf_overrun; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:343:1 + wire rf_push_pulse; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:344:1 + wire [4:0] rf_count; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:345:1 + wire [4:0] tf_count; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:346:1 + wire [2:0] tstate; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:347:1 + wire [3:0] rstate; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:348:1 + wire [9:0] counter_t; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:350:1 + wire thre_set_en; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:351:1 + reg [7:0] block_cnt; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:352:1 + reg [7:0] block_value; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:355:1 + wire serial_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:357:1 + uart_transmitter #(.SIM(SIM)) transmitter( + .clk(clk), + .wb_rst_i(wb_rst_i), + .lcr(lcr), + .tf_push(tf_push), + .wb_dat_i(wb_dat_i), + .enable(enable), + .stx_pad_o(serial_out), + .tstate(tstate), + .tf_count(tf_count), + .tx_reset(tx_reset), + .lsr_mask(lsr_mask) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:360:3 + uart_sync_flops i_uart_sync_flops( + .rst_i(wb_rst_i), + .clk_i(clk), + .stage1_rst_i(1'b0), + .stage1_clk_en_i(1'b1), + .async_dat_i(srx_pad_i), + .sync_dat_o(srx_pad) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:369:3 + defparam i_uart_sync_flops.width = 1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:370:3 + defparam i_uart_sync_flops.init_value = 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:373:1 + wire serial_in = (loopback ? serial_out : srx_pad); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:374:1 + assign stx_pad_o = (loopback ? 1'b1 : serial_out); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:377:1 + uart_receiver receiver( + .clk(clk), + .wb_rst_i(wb_rst_i), + .lcr(lcr), + .rf_pop(rf_pop), + .srx_pad_i(serial_in), + .enable(enable), + .counter_t(counter_t), + .rf_count(rf_count), + .rf_data_out(rf_data_out), + .rf_error_bit(rf_error_bit), + .rf_overrun(rf_overrun), + .rx_reset(rx_reset), + .lsr_mask(lsr_mask), + .rstate(rstate), + .rf_push_pulse(rf_push_pulse) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:382:1 + always @(dl or dlab or ier or iir or scratch or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:385:2 + case (wb_addr_i) + 3'd0: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:386:20 + wb_dat_o = (dlab ? dl[7:0] : rf_data_out[10:3]); + 3'd1: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:387:18 + wb_dat_o = (dlab ? dl[15:8] : {4'd0, ier}); + 3'd2: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:388:18 + wb_dat_o = {4'b1100, iir}; + 3'd3: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:389:18 + wb_dat_o = lcr; + 3'd5: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:390:18 + wb_dat_o = lsr; + 3'd6: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:391:18 + wb_dat_o = msr; + 3'd7: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:392:18 + wb_dat_o = scratch; + default: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:393:13 + wb_dat_o = 8'b00000000; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:399:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:401:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:402:3 + rf_pop <= 0; + else if (rf_pop) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:405:3 + rf_pop <= 0; + else if ((wb_re_i && (wb_addr_i == 3'd0)) && !dlab) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:408:3 + rf_pop <= 1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:411:1 + wire lsr_mask_condition; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:412:1 + wire iir_read; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:413:1 + wire msr_read; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:414:1 + wire fifo_read; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:415:1 + wire fifo_write; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:417:1 + assign lsr_mask_condition = (wb_re_i && (wb_addr_i == 3'd5)) && !dlab; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:418:1 + assign iir_read = (wb_re_i && (wb_addr_i == 3'd2)) && !dlab; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:419:1 + assign msr_read = (wb_re_i && (wb_addr_i == 3'd6)) && !dlab; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:420:1 + assign fifo_read = (wb_re_i && (wb_addr_i == 3'd0)) && !dlab; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:421:1 + assign fifo_write = (wb_we_i && (wb_addr_i == 3'd0)) && !dlab; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:424:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:426:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:427:3 + lsr_mask_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:429:3 + lsr_mask_d <= lsr_mask_condition; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:433:1 + assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:436:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:438:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:439:3 + msi_reset <= 1; + else if (msi_reset) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:442:3 + msi_reset <= 0; + else if (msr_read) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:445:3 + msi_reset <= 1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:453:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:455:3 + lcr <= 8'b00000011; + else if (wb_we_i && (wb_addr_i == 3'd3)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:458:3 + lcr <= wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:461:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:464:3 + ier <= 4'b0000; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:468:3 + dl[15:8] <= 8'b00000000; + end + else if (wb_we_i && (wb_addr_i == 3'd1)) begin + if (dlab) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:475:4 + dl[15:8] <= wb_dat_i; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:483:4 + ier <= wb_dat_i[3:0]; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:487:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:489:3 + fcr <= 2'b11; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:490:3 + rx_reset <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:491:3 + tx_reset <= 0; + end + else if (wb_we_i && (wb_addr_i == 3'd2)) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:494:3 + fcr <= wb_dat_i[7:6]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:495:3 + rx_reset <= wb_dat_i[1]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:496:3 + tx_reset <= wb_dat_i[2]; + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:498:3 + rx_reset <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:499:3 + tx_reset <= 0; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:503:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:505:3 + mcr <= 5'b00000; + else if (wb_we_i && (wb_addr_i == 3'd4)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:508:4 + mcr <= wb_dat_i[4:0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:512:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:514:3 + scratch <= 0; + else if (wb_we_i && (wb_addr_i == 3'd7)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:517:3 + scratch <= wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:520:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:526:3 + dl[7:0] <= 8'b00000000; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:528:3 + tf_push <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:529:3 + start_dlc <= 1'b0; + end + else if (wb_we_i && (wb_addr_i == 3'd0)) begin + if (dlab) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:538:4 + dl[7:0] <= wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:540:4 + start_dlc <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:541:4 + tf_push <= 1'b0; + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:545:4 + tf_push <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:546:4 + start_dlc <= 1'b0; + end + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:550:3 + start_dlc <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:551:3 + tf_push <= 1'b0; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:555:1 + always @(fcr) + case (fcr[1:0]) + 2'b00: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:557:11 + trigger_level = 1; + 2'b01: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:558:11 + trigger_level = 4; + 2'b10: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:559:11 + trigger_level = 8; + 2'b11: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:560:11 + trigger_level = 14; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:568:1 + reg [3:0] delayed_modem_signals; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:569:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:571:2 + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:573:5 + msr <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:574:5 + delayed_modem_signals[3:0] <= 0; + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:577:3 + msr[3:0] <= (msi_reset ? 4'b0000 : msr[3:0] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0])); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:579:3 + msr[7:4] <= {dcd_c, ri_c, dsr_c, cts_c}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:580:3 + delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts}; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:588:1 + assign lsr0 = (rf_count == 0) && rf_push_pulse; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:589:1 + assign lsr1 = rf_overrun; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:590:1 + assign lsr2 = rf_data_out[1]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:591:1 + assign lsr3 = rf_data_out[0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:592:1 + assign lsr4 = rf_data_out[2]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:593:1 + assign lsr5 = (tf_count == 5'b00000) && thre_set_en; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:594:1 + assign lsr6 = ((tf_count == 5'b00000) && thre_set_en) && (tstate == 0); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:595:1 + assign lsr7 = rf_error_bit | rf_overrun; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:598:1 + reg lsr0_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:600:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:601:16 + lsr0_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:602:7 + lsr0_d <= lsr0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:604:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:605:16 + lsr0r <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:606:7 + lsr0r <= ((((rf_count == 1) && rf_pop) && !rf_push_pulse) || rx_reset ? 1'b0 : lsr0r || (lsr0 && ~lsr0_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:610:1 + reg lsr1_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:612:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:613:16 + lsr1_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:614:7 + lsr1_d <= lsr1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:616:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:617:16 + lsr1r <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:618:7 + lsr1r <= (lsr_mask ? 1'b0 : lsr1r || (lsr1 && ~lsr1_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:621:1 + reg lsr2_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:623:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:624:16 + lsr2_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:625:7 + lsr2_d <= lsr2; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:627:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:628:16 + lsr2r <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:629:7 + lsr2r <= (lsr_mask ? 1'b0 : lsr2r || (lsr2 && ~lsr2_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:632:1 + reg lsr3_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:634:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:635:16 + lsr3_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:636:7 + lsr3_d <= lsr3; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:638:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:639:16 + lsr3r <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:640:7 + lsr3r <= (lsr_mask ? 1'b0 : lsr3r || (lsr3 && ~lsr3_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:643:1 + reg lsr4_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:645:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:646:16 + lsr4_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:647:7 + lsr4_d <= lsr4; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:649:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:650:16 + lsr4r <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:651:7 + lsr4r <= (lsr_mask ? 1'b0 : lsr4r || (lsr4 && ~lsr4_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:654:1 + reg lsr5_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:656:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:657:16 + lsr5_d <= 1; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:658:7 + lsr5_d <= lsr5; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:660:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:661:16 + lsr5r <= 1; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:662:7 + lsr5r <= (fifo_write ? 1'b0 : lsr5r || (lsr5 && ~lsr5_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:665:1 + reg lsr6_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:667:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:668:16 + lsr6_d <= 1; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:669:7 + lsr6_d <= lsr6; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:671:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:672:16 + lsr6r <= 1; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:673:7 + lsr6r <= (fifo_write ? 1'b0 : lsr6r || (lsr6 && ~lsr6_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:676:1 + reg lsr7_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:678:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:679:16 + lsr7_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:680:7 + lsr7_d <= lsr7; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:682:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:683:16 + lsr7r <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:684:7 + lsr7r <= (lsr_mask ? 1'b0 : lsr7r || (lsr7 && ~lsr7_d)); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:687:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:689:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:690:3 + dlc <= 0; + else if (start_dlc | ~(|dlc)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:693:6 + dlc <= dl - 16'd1; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:695:4 + dlc <= dlc - 16'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:699:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:701:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:702:3 + enable <= 1'b0; + else if (|dl & ~(|dlc)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:705:4 + enable <= 1'b1; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:707:4 + enable <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:711:1 + always @(lcr) + case (lcr[3:0]) + 4'b0000: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:713:43 + block_value = 95; + 4'b0100: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:714:43 + block_value = 103; + 4'b0001, 4'b1000: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:715:43 + block_value = 111; + 4'b1100: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:716:43 + block_value = 119; + 4'b0010, 4'b0101, 4'b1001: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:717:43 + block_value = 127; + 4'b0011, 4'b0110, 4'b1010, 4'b1101: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:718:43 + block_value = 143; + 4'b0111, 4'b1011, 4'b1110: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:719:43 + block_value = 159; + 4'b1111: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:720:43 + block_value = 175; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:724:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:726:3 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:727:5 + block_cnt <= 8'd0; + else if (lsr5r & fifo_write) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:730:5 + block_cnt <= (SIM ? 8'd1 : block_value); + else if (enable & (block_cnt != 8'b00000000)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:733:5 + block_cnt <= block_cnt - 8'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:737:1 + assign thre_set_en = ~(|block_cnt); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:744:1 + assign rls_int = ier[2] && (((lsr[1] || lsr[2]) || lsr[3]) || lsr[4]); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:745:1 + assign rda_int = ier[0] && (rf_count >= {1'b0, trigger_level}); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:746:1 + assign thre_int = ier[1] && lsr[5]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:747:1 + assign ms_int = ier[3] && |msr[3:0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:748:1 + assign ti_int = (ier[0] && (counter_t == 10'b0000000000)) && |rf_count; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:750:1 + reg rls_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:751:1 + reg thre_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:752:1 + reg ms_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:753:1 + reg ti_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:754:1 + reg rda_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:757:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:758:16 + rls_int_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:759:7 + rls_int_d <= rls_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:761:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:762:16 + rda_int_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:763:7 + rda_int_d <= rda_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:765:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:766:16 + thre_int_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:767:7 + thre_int_d <= thre_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:769:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:770:16 + ms_int_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:771:7 + ms_int_d <= ms_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:773:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:774:16 + ti_int_d <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:775:7 + ti_int_d <= ti_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:779:1 + wire rls_int_rise; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:780:1 + wire thre_int_rise; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:781:1 + wire ms_int_rise; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:782:1 + wire ti_int_rise; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:783:1 + wire rda_int_rise; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:785:1 + assign rda_int_rise = rda_int & ~rda_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:786:1 + assign rls_int_rise = rls_int & ~rls_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:787:1 + assign thre_int_rise = thre_int & ~thre_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:788:1 + assign ms_int_rise = ms_int & ~ms_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:789:1 + assign ti_int_rise = ti_int & ~ti_int_d; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:792:1 + reg rls_int_pnd; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:793:1 + reg rda_int_pnd; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:794:1 + reg thre_int_pnd; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:795:1 + reg ms_int_pnd; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:796:1 + reg ti_int_pnd; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:799:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:800:16 + rls_int_pnd <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:802:3 + rls_int_pnd <= (lsr_mask ? 1'b0 : (rls_int_rise ? 1'b1 : rls_int_pnd && ier[2])); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:806:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:807:16 + rda_int_pnd <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:809:3 + rda_int_pnd <= ((rf_count == {1'b0, trigger_level}) && fifo_read ? 1'b0 : (rda_int_rise ? 1'b1 : rda_int_pnd && ier[0])); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:813:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:814:16 + thre_int_pnd <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:816:3 + thre_int_pnd <= (fifo_write || ((iir_read & ~iir[0]) & (iir[3:1] == 3'b001)) ? 1'b0 : (thre_int_rise ? 1'b1 : thre_int_pnd && ier[1])); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:820:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:821:16 + ms_int_pnd <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:823:3 + ms_int_pnd <= (msr_read ? 1'b0 : (ms_int_rise ? 1'b1 : ms_int_pnd && ier[3])); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:827:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:828:16 + ti_int_pnd <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:830:3 + ti_int_pnd <= (fifo_read ? 1'b0 : (ti_int_rise ? 1'b1 : ti_int_pnd && ier[0])); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:836:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:838:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:839:3 + int_o <= 1'b0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:841:3 + int_o <= (rls_int_pnd ? ~lsr_mask : (rda_int_pnd ? 1'b1 : (ti_int_pnd ? ~fifo_read : (thre_int_pnd ? !(fifo_write & iir_read) : (ms_int_pnd ? ~msr_read : 1'd0))))); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:852:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:854:2 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:855:3 + iir <= 1; + else if (rls_int_pnd) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:859:3 + iir[3:1] <= 3'b011; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:860:3 + iir[0] <= 1'b0; + end + else if (rda_int) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:864:3 + iir[3:1] <= 3'b010; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:865:3 + iir[0] <= 1'b0; + end + else if (ti_int_pnd) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:869:3 + iir[3:1] <= 3'b110; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:870:3 + iir[0] <= 1'b0; + end + else if (thre_int_pnd) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:874:3 + iir[3:1] <= 3'b001; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:875:3 + iir[0] <= 1'b0; + end + else if (ms_int_pnd) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:879:3 + iir[3:1] <= 3'b000; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:880:3 + iir[0] <= 1'b0; + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:883:3 + iir[3:1] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_regs.v:884:3 + iir[0] <= 1'b1; + end +endmodule +module uart_rfifo ( + clk, + wb_rst_i, + data_in, + data_out, + push, + pop, + overrun, + count, + error_bit, + fifo_reset, + reset_status +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:161:1 + parameter fifo_width = 8; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:162:1 + parameter fifo_depth = 16; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:163:1 + parameter fifo_pointer_w = 4; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:164:1 + parameter fifo_counter_w = 5; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:166:1 + input clk; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:167:1 + input wb_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:168:1 + input push; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:169:1 + input pop; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:170:1 + input [fifo_width - 1:0] data_in; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:171:1 + input fifo_reset; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:172:1 + input reset_status; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:174:1 + output wire [fifo_width - 1:0] data_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:175:1 + output reg overrun; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:176:1 + output reg [fifo_counter_w - 1:0] count; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:177:1 + output wire error_bit; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:179:1 + // combined with data_out + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:180:1 + wire [7:0] data8_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:182:1 + reg [2:0] fifo [fifo_depth - 1:0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:185:1 + reg [fifo_pointer_w - 1:0] top; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:186:1 + reg [fifo_pointer_w - 1:0] bottom; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:188:1 + // combined with count + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:189:1 + // combined with overrun + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:191:1 + wire [fifo_pointer_w - 1:0] top_plus_1 = top + 4'h1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:193:1 + raminfr #( + .addr_width(fifo_pointer_w), + .data_width(8), + .depth(fifo_depth) + ) rfifo( + .clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in[fifo_width - 1:fifo_width - 8]), + .dpo(data8_out) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:202:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:204:2 + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:206:3 + top <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:207:3 + bottom <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:208:3 + count <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:209:3 + fifo[0] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:210:3 + fifo[1] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:211:3 + fifo[2] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:212:3 + fifo[3] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:213:3 + fifo[4] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:214:3 + fifo[5] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:215:3 + fifo[6] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:216:3 + fifo[7] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:217:3 + fifo[8] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:218:3 + fifo[9] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:219:3 + fifo[10] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:220:3 + fifo[11] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:221:3 + fifo[12] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:222:3 + fifo[13] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:223:3 + fifo[14] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:224:3 + fifo[15] <= 0; + end + else if (fifo_reset) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:228:3 + top <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:229:3 + bottom <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:230:3 + count <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:231:3 + fifo[0] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:232:3 + fifo[1] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:233:3 + fifo[2] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:234:3 + fifo[3] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:235:3 + fifo[4] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:236:3 + fifo[5] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:237:3 + fifo[6] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:238:3 + fifo[7] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:239:3 + fifo[8] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:240:3 + fifo[9] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:241:3 + fifo[10] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:242:3 + fifo[11] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:243:3 + fifo[12] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:244:3 + fifo[13] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:245:3 + fifo[14] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:246:3 + fifo[15] <= 0; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:250:3 + case ({push, pop}) + 2'b10: + if (count < fifo_depth) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:253:5 + top <= top_plus_1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:254:5 + fifo[top] <= data_in[2:0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:255:5 + count <= count + 5'd1; + end + 2'b01: + if (count > 0) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:259:9 + fifo[bottom] <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:260:5 + bottom <= bottom + 4'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:261:5 + count <= count - 5'd1; + end + 2'b11: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:264:5 + bottom <= bottom + 4'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:265:5 + top <= top_plus_1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:266:5 + fifo[top] <= data_in[2:0]; + end + default: + ; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:273:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:275:3 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:276:5 + overrun <= 1'b0; + else if (fifo_reset | reset_status) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:279:5 + overrun <= 1'b0; + else if ((push & ~pop) & (count == fifo_depth)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:282:5 + overrun <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:287:1 + assign data_out = {data8_out, fifo[bottom]}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:292:1 + wire [2:0] word0 = fifo[0]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:293:1 + wire [2:0] word1 = fifo[1]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:294:1 + wire [2:0] word2 = fifo[2]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:295:1 + wire [2:0] word3 = fifo[3]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:296:1 + wire [2:0] word4 = fifo[4]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:297:1 + wire [2:0] word5 = fifo[5]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:298:1 + wire [2:0] word6 = fifo[6]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:299:1 + wire [2:0] word7 = fifo[7]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:301:1 + wire [2:0] word8 = fifo[8]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:302:1 + wire [2:0] word9 = fifo[9]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:303:1 + wire [2:0] word10 = fifo[10]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:304:1 + wire [2:0] word11 = fifo[11]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:305:1 + wire [2:0] word12 = fifo[12]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:306:1 + wire [2:0] word13 = fifo[13]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:307:1 + wire [2:0] word14 = fifo[14]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:308:1 + wire [2:0] word15 = fifo[15]; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_rfifo.v:311:1 + assign error_bit = |(((((((((((((((word0[2:0] | word1[2:0]) | word2[2:0]) | word3[2:0]) | word4[2:0]) | word5[2:0]) | word6[2:0]) | word7[2:0]) | word8[2:0]) | word9[2:0]) | word10[2:0]) | word11[2:0]) | word12[2:0]) | word13[2:0]) | word14[2:0]) | word15[2:0]); +endmodule +module uart_sync_flops ( + rst_i, + clk_i, + stage1_rst_i, + stage1_clk_en_i, + async_dat_i, + sync_dat_o +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:78:1 + parameter width = 1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:79:1 + parameter init_value = 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:81:1 + input rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:82:1 + input clk_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:83:1 + input stage1_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:84:1 + input stage1_clk_en_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:85:1 + input [width - 1:0] async_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:86:1 + output reg [width - 1:0] sync_dat_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:93:1 + // combined with sync_dat_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:94:1 + reg [width - 1:0] flop_0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:98:1 + always @(posedge clk_i or posedge rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:100:5 + if (rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:101:9 + flop_0 <= {width {init_value}}; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:103:9 + flop_0 <= async_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:107:1 + always @(posedge clk_i or posedge rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:109:5 + if (rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:110:9 + sync_dat_o <= {width {init_value}}; + else if (stage1_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:112:9 + sync_dat_o <= {width {init_value}}; + else if (stage1_clk_en_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_sync_flops.v:114:9 + sync_dat_o <= flop_0; +endmodule +module uart_tfifo ( + clk, + wb_rst_i, + data_in, + data_out, + push, + pop, + overrun, + count, + fifo_reset, + reset_status +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:154:1 + parameter fifo_width = 8; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:155:1 + parameter fifo_depth = 16; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:156:1 + parameter fifo_pointer_w = 4; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:157:1 + parameter fifo_counter_w = 5; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:159:1 + input clk; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:160:1 + input wb_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:161:1 + input push; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:162:1 + input pop; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:163:1 + input [fifo_width - 1:0] data_in; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:164:1 + input fifo_reset; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:165:1 + input reset_status; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:167:1 + output wire [fifo_width - 1:0] data_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:168:1 + output reg overrun; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:169:1 + output reg [fifo_counter_w - 1:0] count; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:171:1 + // combined with data_out + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:174:1 + reg [fifo_pointer_w - 1:0] top; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:175:1 + reg [fifo_pointer_w - 1:0] bottom; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:177:1 + // combined with count + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:178:1 + // combined with overrun + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:179:1 + wire [fifo_pointer_w - 1:0] top_plus_1 = top + 4'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:181:1 + raminfr #( + .addr_width(fifo_pointer_w), + .data_width(fifo_width), + .depth(fifo_depth) + ) tfifo( + .clk(clk), + .we(push), + .a(top), + .dpra(bottom), + .di(data_in), + .dpo(data_out) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:191:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:193:2 + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:195:3 + top <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:196:3 + bottom <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:197:3 + count <= 0; + end + else if (fifo_reset) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:201:3 + top <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:202:3 + bottom <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:203:3 + count <= 0; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:207:3 + case ({push, pop}) + 2'b10: + if (count < fifo_depth) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:210:5 + top <= top_plus_1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:211:5 + count <= count + 5'd1; + end + 2'b01: + if (count > 0) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:215:5 + bottom <= bottom + 4'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:216:5 + count <= count - 5'd1; + end + 2'b11: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:219:5 + bottom <= bottom + 4'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:220:5 + top <= top_plus_1; + end + default: + ; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:227:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:229:3 + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:230:5 + overrun <= 1'b0; + else if (fifo_reset | reset_status) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:233:5 + overrun <= 1'b0; + else if (push & (count == fifo_depth)) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_tfifo.v:236:5 + overrun <= 1'b1; +endmodule +module uart_top ( + wb_clk_i, + wb_rst_i, + wb_adr_i, + wb_dat_i, + wb_dat_o, + wb_we_i, + wb_stb_i, + wb_cyc_i, + wb_ack_o, + wb_sel_i, + int_o, + stx_pad_o, + srx_pad_i, + rts_pad_o, + cts_pad_i, + dtr_pad_o, + dsr_pad_i, + ri_pad_i, + dcd_pad_i +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:154:1 + parameter SIM = 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:155:1 + parameter debug = 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:157:1 + input wb_clk_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:160:1 + input wb_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:161:1 + input wire [2:0] wb_adr_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:162:1 + input wire [7:0] wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:163:1 + output wire [7:0] wb_dat_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:164:1 + input wb_we_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:165:1 + input wb_stb_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:166:1 + input wb_cyc_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:167:1 + input wire [3:0] wb_sel_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:168:1 + output wire wb_ack_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:169:1 + output wire int_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:172:1 + input srx_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:173:1 + output wire stx_pad_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:174:1 + output wire rts_pad_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:175:1 + input cts_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:176:1 + output wire dtr_pad_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:177:1 + input dsr_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:178:1 + input ri_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:179:1 + input dcd_pad_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:187:1 + // combined with stx_pad_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:188:1 + // combined with rts_pad_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:189:1 + // combined with dtr_pad_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:191:1 + // combined with wb_adr_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:192:1 + // combined with wb_dat_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:193:1 + // combined with wb_dat_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:195:1 + wire [7:0] wb_dat8_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:196:1 + wire [7:0] wb_dat8_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:197:1 + wire [31:0] wb_dat32_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:198:1 + // combined with wb_sel_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:199:1 + wire [2:0] wb_adr_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:200:1 + wire we_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:201:1 + wire re_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:207:1 + uart_wb wb_interface( + .clk(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wb_dat_i(wb_dat_i), + .wb_dat_o(wb_dat_o), + .wb_dat8_i(wb_dat8_i), + .wb_dat8_o(wb_dat8_o), + .wb_dat32_o(32'b00000000000000000000000000000000), + .wb_sel_i(4'b0000), + .wb_we_i(wb_we_i), + .wb_stb_i(wb_stb_i), + .wb_cyc_i(wb_cyc_i), + .wb_ack_o(wb_ack_o), + .wb_adr_i(wb_adr_i), + .wb_adr_int(wb_adr_int), + .we_o(we_o), + .re_o(re_o) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:227:1 + uart_regs #(.SIM(SIM)) regs( + .clk(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wb_addr_i(wb_adr_int), + .wb_dat_i(wb_dat8_i), + .wb_dat_o(wb_dat8_o), + .wb_we_i(we_o), + .wb_re_i(re_o), + .modem_inputs({cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i}), + .stx_pad_o(stx_pad_o), + .srx_pad_i(srx_pad_i), + .rts_pad_o(rts_pad_o), + .dtr_pad_o(dtr_pad_o), + .int_o(int_o) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:248:1 + initial begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:250:4 + if (debug) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_top.v:254:3 + $display("(%m) UART INFO: Doesn't have baudrate output\n"); + end +endmodule +module uart_transmitter ( + clk, + wb_rst_i, + lcr, + tf_push, + wb_dat_i, + enable, + stx_pad_o, + tstate, + tf_count, + tx_reset, + lsr_mask +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:151:13 + parameter SIM = 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:154:1 + input clk; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:155:1 + input wb_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:156:1 + input [7:0] lcr; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:157:1 + input wire tf_push; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:158:1 + input [7:0] wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:159:1 + input enable; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:160:1 + input tx_reset; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:161:1 + input lsr_mask; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:162:1 + output wire stx_pad_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:163:1 + output reg [2:0] tstate; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:164:1 + output wire [4:0] tf_count; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:166:1 + // combined with tstate + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:167:1 + reg [4:0] counter; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:168:1 + reg [2:0] bit_counter; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:169:1 + reg [6:0] shift_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:170:1 + reg stx_o_tmp; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:171:1 + reg parity_xor; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:172:1 + reg tf_pop; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:173:1 + reg bit_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:178:1 + wire [7:0] tf_data_in; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:179:1 + wire [7:0] tf_data_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:180:1 + // combined with tf_push + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:181:1 + wire tf_overrun; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:182:1 + // combined with tf_count + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:184:1 + assign tf_data_in = wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:186:1 + uart_tfifo fifo_tx( + .clk(clk), + .wb_rst_i(wb_rst_i), + .data_in(tf_data_in), + .data_out(tf_data_out), + .push(tf_push), + .pop(tf_pop), + .overrun(tf_overrun), + .count(tf_count), + .fifo_reset(tx_reset), + .reset_status(lsr_mask) + ); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:201:1 + localparam s_idle = 3'd0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:202:1 + localparam s_send_start = 3'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:203:1 + localparam s_send_byte = 3'd2; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:204:1 + localparam s_send_parity = 3'd3; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:205:1 + localparam s_send_stop = 3'd4; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:206:1 + localparam s_pop_byte = 3'd5; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:208:1 + always @(posedge clk or posedge wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:210:3 + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:212:2 + tstate <= s_idle; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:213:2 + stx_o_tmp <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:214:2 + counter <= 5'b00000; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:215:2 + shift_out <= 7'b0000000; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:216:2 + bit_out <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:217:2 + parity_xor <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:218:2 + tf_pop <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:219:2 + bit_counter <= 3'b000; + end + else if (enable | SIM) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:224:2 + case (tstate) + s_idle: + if (~|tf_count) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:227:5 + tstate <= s_idle; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:228:5 + stx_o_tmp <= 1'b1; + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:232:5 + tf_pop <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:233:5 + stx_o_tmp <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:234:5 + tstate <= s_pop_byte; + end + s_pop_byte: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:237:5 + tf_pop <= 1'b1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:238:5 + case (lcr[1:0]) + 2'b00: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:240:6 + bit_counter <= 3'b100; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:241:6 + parity_xor <= ^tf_data_out[4:0]; + end + 2'b01: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:244:6 + bit_counter <= 3'b101; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:245:6 + parity_xor <= ^tf_data_out[5:0]; + end + 2'b10: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:248:6 + bit_counter <= 3'b110; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:249:6 + parity_xor <= ^tf_data_out[6:0]; + end + 2'b11: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:252:6 + bit_counter <= 3'b111; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:253:6 + parity_xor <= ^tf_data_out[7:0]; + end + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:256:5 + {shift_out[6:0], bit_out} <= tf_data_out; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:257:5 + tstate <= s_send_start; + end + s_send_start: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:260:5 + tf_pop <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:261:5 + if (~|counter) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:262:6 + counter <= 5'b01111; + else if (counter == 5'b00001) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:266:6 + counter <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:267:6 + tstate <= s_send_byte; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:270:6 + counter <= counter - 5'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:271:5 + stx_o_tmp <= 1'b0; + if (SIM) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:273:6 + tstate <= s_idle; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:274:6 + $write("%c", tf_data_out); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:275:6 + $fflush(32'h80000001); + end + end + s_send_byte: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:279:5 + if (~|counter) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:280:6 + counter <= 5'b01111; + else if (counter == 5'b00001) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:284:6 + if (bit_counter > 3'b000) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:286:7 + bit_counter <= bit_counter - 3'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:287:7 + {shift_out[5:0], bit_out} <= {shift_out[6:1], shift_out[0]}; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:288:7 + tstate <= s_send_byte; + end + else if (~lcr[3]) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:293:7 + tstate <= s_send_stop; + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:297:7 + case ({lcr[4], lcr[5]}) + 2'b00: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:298:14 + bit_out <= ~parity_xor; + 2'b01: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:299:14 + bit_out <= 1'b1; + 2'b10: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:300:14 + bit_out <= parity_xor; + 2'b11: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:301:14 + bit_out <= 1'b0; + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:303:7 + tstate <= s_send_parity; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:305:6 + counter <= 0; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:308:6 + counter <= counter - 5'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:309:5 + stx_o_tmp <= bit_out; + end + s_send_parity: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:312:5 + if (~|counter) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:313:6 + counter <= 5'b01111; + else if (counter == 5'b00001) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:317:6 + counter <= 5'd0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:318:6 + tstate <= s_send_stop; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:321:6 + counter <= counter - 5'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:322:5 + stx_o_tmp <= bit_out; + end + s_send_stop: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:325:5 + if (~|counter) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:327:7 + casez ({lcr[2], lcr[1:0]}) + 3'b0zz: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:328:19 + counter <= 5'b01101; + 3'b100: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:329:19 + counter <= 5'b10101; + default: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:330:20 + counter <= 5'b11101; + endcase + else if (counter == 5'b00001) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:336:6 + counter <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:337:6 + tstate <= s_idle; + end + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:340:6 + counter <= counter - 5'd1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:341:5 + stx_o_tmp <= 1'b1; + end + default: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:345:4 + tstate <= s_idle; + endcase + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:349:5 + tf_pop <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_transmitter.v:352:1 + assign stx_pad_o = (lcr[6] ? 1'b0 : stx_o_tmp); +endmodule +module uart_wb ( + clk, + wb_rst_i, + wb_we_i, + wb_stb_i, + wb_cyc_i, + wb_ack_o, + wb_adr_i, + wb_adr_int, + wb_dat_i, + wb_dat_o, + wb_dat8_i, + wb_dat8_o, + wb_dat32_o, + wb_sel_i, + we_o, + re_o +); + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:145:1 + input clk; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:148:1 + input wb_rst_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:149:1 + input wb_we_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:150:1 + input wb_stb_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:151:1 + input wb_cyc_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:152:1 + input wire [3:0] wb_sel_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:153:1 + input [2:0] wb_adr_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:155:1 + input wire [7:0] wb_dat_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:156:1 + output reg [7:0] wb_dat_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:157:1 + // combined with wb_dat_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:158:1 + // combined with wb_dat_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:159:1 + reg [7:0] wb_dat_is; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:161:1 + output wire [2:0] wb_adr_int; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:162:1 + input wire [7:0] wb_dat8_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:163:1 + output reg [7:0] wb_dat8_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:164:1 + input [31:0] wb_dat32_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:165:1 + output reg wb_ack_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:166:1 + output wire we_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:167:1 + output wire re_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:169:1 + // combined with we_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:170:1 + // combined with wb_ack_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:171:1 + // combined with wb_dat8_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:172:1 + // combined with wb_dat8_o + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:173:1 + // combined with wb_adr_int + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:174:1 + reg [2:0] wb_adr_is; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:175:1 + reg wb_we_is; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:176:1 + reg wb_cyc_is; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:177:1 + reg wb_stb_is; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:178:1 + // combined with wb_sel_i + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:179:1 + reg wre; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:182:1 + reg [1:0] wbstate; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:183:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:185:3 + wb_ack_o <= 1'b0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:186:3 + wbstate <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:187:3 + wre <= 1'b1; + end + else + case (wbstate) + 0: + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:191:5 + if (wb_stb_is & wb_cyc_is) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:192:6 + wre <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:193:6 + wbstate <= 1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:194:6 + wb_ack_o <= 1; + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:196:6 + wre <= 1; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:197:6 + wb_ack_o <= 0; + end + 1: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:201:7 + wb_ack_o <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:202:5 + wbstate <= 2; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:203:5 + wre <= 0; + end + 2: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:206:5 + wb_ack_o <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:207:5 + wbstate <= 3; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:208:5 + wre <= 0; + end + 3: begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:211:5 + wb_ack_o <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:212:5 + wbstate <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:213:5 + wre <= 1; + end + endcase + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:217:1 + assign we_o = ((wb_we_is & wb_stb_is) & wb_cyc_is) & wre; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:218:1 + assign re_o = ((~wb_we_is & wb_stb_is) & wb_cyc_is) & wre; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:221:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:223:3 + wb_adr_is <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:224:3 + wb_we_is <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:225:3 + wb_cyc_is <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:226:3 + wb_stb_is <= 0; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:227:3 + wb_dat_is <= 0; + end + else begin + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:229:3 + wb_adr_is <= wb_adr_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:230:3 + wb_we_is <= wb_we_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:231:3 + wb_cyc_is <= wb_cyc_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:232:3 + wb_stb_is <= wb_stb_i; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:233:3 + wb_dat_is <= wb_dat_i; + end + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:236:1 + always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:238:3 + wb_dat_o <= 0; + else + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:240:3 + wb_dat_o <= wb_dat8_o; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:242:1 + always @(wb_dat_is) + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:243:2 + wb_dat8_i = wb_dat_is; + // Trace: ./src/uart16550_1.5.5-r1/rtl/verilog/uart_wb.v:245:1 + assign wb_adr_int = wb_adr_is; +endmodule +// removed package "axi_pkg" +// removed interface: AXI_BUS +// removed interface: AXI_BUS_DV +// removed interface: AXI_BUS_ASYNC +// removed interface: AXI_LITE +// removed interface: AXI_LITE_DV +module axi_atop_filter_99C72_35AFC ( + clk_i, + rst_ni, + slv_req_i, + slv_resp_o, + mst_req_o, + mst_resp_i +); + // removed localparam type req_t_req_t_slv_req_t_AxiAddrWidth_type + // removed localparam type req_t_req_t_slv_req_t_AxiDataWidth_type + // removed localparam type req_t_req_t_slv_req_t_AxiIdWidthMasters_type + // removed localparam type req_t_req_t_slv_req_t_AxiStrbWidth_type + // removed localparam type req_t_req_t_slv_req_t_AxiUserWidth_type + parameter [31:0] req_t_req_t_slv_req_t_AxiAddrWidth = 0; + parameter [31:0] req_t_req_t_slv_req_t_AxiDataWidth = 0; + parameter [31:0] req_t_req_t_slv_req_t_AxiIdWidthMasters = 0; + parameter [31:0] req_t_req_t_slv_req_t_AxiStrbWidth = 0; + parameter [31:0] req_t_req_t_slv_req_t_AxiUserWidth = 0; + // removed localparam type resp_t_resp_t_slv_resp_t_AxiDataWidth_type + // removed localparam type resp_t_resp_t_slv_resp_t_AxiIdWidthMasters_type + // removed localparam type resp_t_resp_t_slv_resp_t_AxiUserWidth_type + parameter [31:0] resp_t_resp_t_slv_resp_t_AxiDataWidth = 0; + parameter [31:0] resp_t_resp_t_slv_resp_t_AxiIdWidthMasters = 0; + parameter [31:0] resp_t_resp_t_slv_resp_t_AxiUserWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:38:13 + parameter [31:0] AxiIdWidth = 0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:40:13 + parameter [31:0] AxiMaxWriteTxns = 0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:42:18 + // removed localparam type req_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:44:18 + // removed localparam type resp_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:47:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:49:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:51:3 + input wire [(((((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth)) + 1:0] slv_req_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:53:3 + output reg [(((4 + ((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth)) - 1:0] slv_resp_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:55:3 + output reg [(((((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth)) + 1:0] mst_req_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:57:3 + input wire [(((4 + ((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth)) - 1:0] mst_resp_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:61:3 + localparam [31:0] COUNTER_WIDTH = (AxiMaxWriteTxns == 1 ? 2 : $clog2(AxiMaxWriteTxns + 1)); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:62:3 + // removed localparam type cnt_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:66:3 + reg [(1 + COUNTER_WIDTH) - 1:0] w_cnt_d; + reg [(1 + COUNTER_WIDTH) - 1:0] w_cnt_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:68:3 + // removed localparam type w_state_e + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:71:3 + reg [2:0] w_state_d; + reg [2:0] w_state_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:73:3 + // removed localparam type r_state_e + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:74:3 + reg [1:0] r_state_d; + reg [1:0] r_state_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:76:3 + // removed localparam type id_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:77:3 + reg [AxiIdWidth - 1:0] id_d; + reg [AxiIdWidth - 1:0] id_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:79:3 + // removed localparam type len_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:80:3 + reg [7:0] r_beats_d; + reg [7:0] r_beats_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:82:3 + // removed localparam type r_resp_cmd_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:85:3 + wire [7:0] r_resp_cmd_push; + wire [7:0] r_resp_cmd_pop; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:87:3 + wire aw_without_complete_w_downstream; + wire complete_w_without_aw_downstream; + reg r_resp_cmd_push_valid; + wire r_resp_cmd_push_ready; + wire r_resp_cmd_pop_valid; + reg r_resp_cmd_pop_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:94:3 + assign aw_without_complete_w_downstream = !w_cnt_q[COUNTER_WIDTH + 0] && (w_cnt_q[COUNTER_WIDTH - 1-:COUNTER_WIDTH] > 0); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:96:3 + assign complete_w_without_aw_downstream = w_cnt_q[COUNTER_WIDTH + 0] && &w_cnt_q[COUNTER_WIDTH - 1-:COUNTER_WIDTH]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:99:3 + localparam axi_pkg_ATOP_ATOMICSTORE = 2'b01; + localparam axi_pkg_ATOP_NONE = 2'b00; + localparam axi_pkg_RESP_SLVERR = 2'b10; + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:102:5 + mst_req_o[1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:103:5 + slv_resp_o[4 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:104:5 + mst_req_o[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:105:5 + slv_resp_o[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:107:5 + mst_req_o[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] = slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:108:5 + slv_resp_o[1 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = mst_resp_i[1 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:109:5 + slv_resp_o[((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)-:((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) >= (1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) ? ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1)] = mst_resp_i[((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)-:((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) >= (1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) ? ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:111:5 + id_d = id_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:113:5 + r_resp_cmd_push_valid = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:115:5 + w_state_d = w_state_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:117:5 + (* full_case, parallel_case *) + case (w_state_q) + 3'd0: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:120:9 + if (complete_w_without_aw_downstream || (w_cnt_q[COUNTER_WIDTH - 1-:COUNTER_WIDTH] < AxiMaxWriteTxns)) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:121:11 + mst_req_o[1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))] = slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:122:11 + slv_resp_o[4 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = mst_resp_i[4 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))]; + end + if (aw_without_complete_w_downstream || ((slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))] && (slv_req_i[((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 5)):((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 4))] == axi_pkg_ATOP_NONE)) && !complete_w_without_aw_downstream)) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:131:11 + mst_req_o[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] = slv_req_i[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:132:11 + slv_resp_o[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = mst_resp_i[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))]; + end + if (slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))] && (slv_req_i[((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 5)):((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 4))] != axi_pkg_ATOP_NONE)) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:136:11 + mst_req_o[1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:137:11 + slv_resp_o[4 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:138:11 + id_d = slv_req_i[((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiIdWidthMasters + (req_t_req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5)))))-:((req_t_req_t_slv_req_t_AxiIdWidthMasters + (req_t_req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5)))) >= (req_t_req_t_slv_req_t_AxiAddrWidth + (35 + (req_t_req_t_slv_req_t_AxiUserWidth + 0))) ? ((req_t_req_t_slv_req_t_AxiIdWidthMasters + (req_t_req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5)))) - (req_t_req_t_slv_req_t_AxiAddrWidth + (35 + (req_t_req_t_slv_req_t_AxiUserWidth + 0)))) + 1 : ((req_t_req_t_slv_req_t_AxiAddrWidth + (35 + (req_t_req_t_slv_req_t_AxiUserWidth + 0))) - (req_t_req_t_slv_req_t_AxiIdWidthMasters + (req_t_req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5))))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:140:11 + if (slv_req_i[((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 5)):((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 4))] != axi_pkg_ATOP_ATOMICSTORE) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:144:13 + r_resp_cmd_push_valid = 1'b1; + if (aw_without_complete_w_downstream) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:148:13 + w_state_d = 3'd1; + else begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:151:13 + mst_req_o[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:152:13 + slv_resp_o[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:153:13 + if (slv_req_i[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] && slv_req_i[((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) - (((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 0))]) begin + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:157:15 + if (slv_resp_o[1 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] && !slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:158:17 + w_state_d = 3'd3; + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:160:17 + w_state_d = 3'd4; + end + end + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:164:15 + w_state_d = 3'd2; + end + end + end + 3'd1: + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:172:9 + if (aw_without_complete_w_downstream) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:173:11 + mst_req_o[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] = slv_req_i[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:174:11 + slv_resp_o[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = mst_resp_i[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))]; + end + else begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:177:11 + slv_resp_o[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:178:11 + if (slv_req_i[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] && slv_req_i[((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) - (((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 0))]) begin + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:180:13 + if (slv_resp_o[1 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] && !slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:181:15 + w_state_d = 3'd3; + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:183:15 + w_state_d = 3'd4; + end + end + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:187:13 + w_state_d = 3'd2; + end + 3'd2: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:194:9 + slv_resp_o[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:195:9 + if (slv_req_i[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] && slv_req_i[((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) - (((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 0))]) begin + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:196:11 + if (slv_resp_o[1 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] && !slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:197:13 + w_state_d = 3'd3; + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:199:13 + w_state_d = 3'd4; + end + end + end + 3'd3: + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:206:9 + if (slv_resp_o[1 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] && slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:207:11 + w_state_d = 3'd4; + 3'd4: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:213:9 + mst_req_o[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:217:9 + slv_resp_o[((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)-:((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) >= (1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) ? ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1)] = 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:218:9 + slv_resp_o[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 1)))-:((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 1)) >= (2 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0)) ? ((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 1)) - (2 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0))) + 1 : ((2 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0)) - (resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 1))) + 1)] = id_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:219:9 + slv_resp_o[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0)) - ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_resp_t_slv_resp_t_AxiUserWidth + 1))-:((resp_t_resp_t_slv_resp_t_AxiUserWidth + 1) >= (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0) ? ((resp_t_resp_t_slv_resp_t_AxiUserWidth + 1) - (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0)) + 1 : ((resp_t_resp_t_slv_resp_t_AxiUserWidth + 0) - (resp_t_resp_t_slv_resp_t_AxiUserWidth + 1)) + 1)] = axi_pkg_RESP_SLVERR; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:220:9 + slv_resp_o[1 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:221:9 + if (slv_req_i[1 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)]) begin + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:224:11 + if (r_resp_cmd_pop_valid && !r_resp_cmd_pop_ready) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:225:13 + w_state_d = 3'd5; + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:227:13 + w_state_d = 3'd0; + end + end + end + 3'd5: + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:235:9 + if (!r_resp_cmd_pop_valid) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:236:11 + w_state_d = 3'd0; + default: + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:240:16 + w_state_d = 3'd0; + endcase + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:246:3 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:248:5 + mst_req_o[(((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))-:(((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) >= (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)))) ? (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)))) - ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))))) + 1)] = slv_req_i[(((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))-:(((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) >= (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)))) ? (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)))) - ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:249:5 + mst_req_o[((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 5))-:((req_t_req_t_slv_req_t_AxiUserWidth + 5) >= (req_t_req_t_slv_req_t_AxiUserWidth + 0) ? ((req_t_req_t_slv_req_t_AxiUserWidth + 5) - (req_t_req_t_slv_req_t_AxiUserWidth + 0)) + 1 : ((req_t_req_t_slv_req_t_AxiUserWidth + 0) - (req_t_req_t_slv_req_t_AxiUserWidth + 5)) + 1)] = 1'sb0; + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:251:3 + wire [(((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)) - ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))) + 1) * 1:1] sv2v_tmp_385D0; + assign sv2v_tmp_385D0 = slv_req_i[(((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))-:(((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)) - ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))) + 1)]; + always @(*) mst_req_o[(((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))-:(((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 2)) - ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))) + 1)] = sv2v_tmp_385D0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:254:3 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:257:5 + slv_resp_o[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1-:((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth] = mst_resp_i[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1-:((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:258:5 + slv_resp_o[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0] = mst_resp_i[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:259:5 + mst_req_o[0] = slv_req_i[0]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:261:5 + r_resp_cmd_pop_ready = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:263:5 + r_beats_d = r_beats_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:265:5 + r_state_d = r_state_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:267:5 + (* full_case, parallel_case *) + case (r_state_q) + 2'd0: + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:269:9 + if (mst_resp_i[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0] && !slv_req_i[0]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:270:11 + r_state_d = 2'd2; + else if (r_resp_cmd_pop_valid) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:275:11 + r_beats_d = r_resp_cmd_pop[7-:8]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:276:11 + r_state_d = 2'd1; + end + 2'd1: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:281:9 + mst_req_o[0] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:282:9 + slv_resp_o[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1-:((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth] = 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:283:9 + slv_resp_o[((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiDataWidth + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 2))))-:((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiDataWidth + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 2))) >= (resp_t_resp_t_slv_resp_t_AxiDataWidth + (3 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0))) ? ((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiDataWidth + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 2))) - (resp_t_resp_t_slv_resp_t_AxiDataWidth + (3 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0)))) + 1 : ((resp_t_resp_t_slv_resp_t_AxiDataWidth + (3 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0))) - (resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_resp_t_slv_resp_t_AxiDataWidth + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 2)))) + 1)] = id_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:284:9 + slv_resp_o[((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_resp_t_slv_resp_t_AxiUserWidth + 2))-:((resp_t_resp_t_slv_resp_t_AxiUserWidth + 2) >= (1 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0)) ? ((resp_t_resp_t_slv_resp_t_AxiUserWidth + 2) - (1 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0))) + 1 : ((1 + (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0)) - (resp_t_resp_t_slv_resp_t_AxiUserWidth + 2)) + 1)] = axi_pkg_RESP_SLVERR; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:285:9 + slv_resp_o[((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0))] = r_beats_q == {8 {1'sb0}}; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:286:9 + slv_resp_o[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:287:9 + if (slv_req_i[0]) begin + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:288:11 + if (slv_resp_o[((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_resp_t_slv_resp_t_AxiUserWidth + 0))]) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:289:13 + r_resp_cmd_pop_ready = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:290:13 + r_state_d = 2'd0; + end + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:292:13 + r_beats_d = r_beats_d - 1; + end + end + end + 2'd2: + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:298:9 + if (mst_resp_i[(((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0] && slv_req_i[0]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:299:11 + r_state_d = 2'd0; + default: + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:303:16 + r_state_d = 2'd0; + endcase + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:307:3 + wire [(((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)) * 1:1] sv2v_tmp_3E8BA; + assign sv2v_tmp_3E8BA = slv_req_i[(((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1-:(((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))]; + always @(*) mst_req_o[(((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1-:(((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))] = sv2v_tmp_3E8BA; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:308:3 + wire [1:1] sv2v_tmp_37B66; + assign sv2v_tmp_37B66 = slv_req_i[1]; + always @(*) mst_req_o[1] = sv2v_tmp_37B66; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:309:3 + wire [1:1] sv2v_tmp_ABE98; + assign sv2v_tmp_ABE98 = mst_resp_i[3 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))]; + always @(*) slv_resp_o[3 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))] = sv2v_tmp_ABE98; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:312:3 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:313:5 + w_cnt_d = w_cnt_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:314:5 + if (mst_req_o[1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)))] && mst_resp_i[4 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:315:7 + w_cnt_d[COUNTER_WIDTH - 1-:COUNTER_WIDTH] = w_cnt_d[COUNTER_WIDTH - 1-:COUNTER_WIDTH] + 1; + if ((mst_req_o[2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1)] && mst_resp_i[2 + (((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_resp_t_slv_resp_t_AxiUserWidth) + 0))]) && mst_req_o[((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))) - (((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_req_t_slv_req_t_AxiUserWidth + 0))]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:318:7 + w_cnt_d[COUNTER_WIDTH - 1-:COUNTER_WIDTH] = w_cnt_d[COUNTER_WIDTH - 1-:COUNTER_WIDTH] - 1; + if (w_cnt_q[COUNTER_WIDTH + 0] && (w_cnt_d[COUNTER_WIDTH - 1-:COUNTER_WIDTH] == {COUNTER_WIDTH * 1 {1'sb0}})) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:321:7 + w_cnt_d[COUNTER_WIDTH + 0] = 1'b0; + else if ((w_cnt_q[COUNTER_WIDTH - 1-:COUNTER_WIDTH] == {COUNTER_WIDTH * 1 {1'sb0}}) && &w_cnt_d[COUNTER_WIDTH - 1-:COUNTER_WIDTH]) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:323:7 + w_cnt_d[COUNTER_WIDTH + 0] = 1'b1; + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:327:3 + function automatic [COUNTER_WIDTH - 1:0] sv2v_cast_B90DC; + input reg [COUNTER_WIDTH - 1:0] inp; + sv2v_cast_B90DC = inp; + endfunction + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:328:5 + if (!rst_ni) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:329:7 + id_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:330:7 + r_beats_q <= 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:331:7 + r_state_q <= 2'd0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:332:7 + w_cnt_q <= {1'b0, sv2v_cast_B90DC(1'sb0)}; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:333:7 + w_state_q <= 3'd0; + end + else begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:335:7 + id_q <= id_d; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:336:7 + r_beats_q <= r_beats_d; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:337:7 + r_state_q <= r_state_d; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:338:7 + w_cnt_q <= w_cnt_d; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:339:7 + w_state_q <= w_state_d; + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:343:3 + stream_register_11179 r_resp_cmd( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(1'b0), + .testmode_i(1'b0), + .valid_i(r_resp_cmd_push_valid), + .ready_o(r_resp_cmd_push_ready), + .data_i(r_resp_cmd_push), + .valid_o(r_resp_cmd_pop_valid), + .ready_i(r_resp_cmd_pop_ready), + .data_o(r_resp_cmd_pop) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_atop_filter.sv:357:3 + assign r_resp_cmd_push[7-:8] = slv_req_i[((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_req_t_slv_req_t_AxiDataWidth + req_t_req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_req_t_slv_req_t_AxiIdWidthMasters + req_t_req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_req_t_slv_req_t_AxiUserWidth) - 1) - (29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5)))-:((29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5)) >= (27 + (req_t_req_t_slv_req_t_AxiUserWidth + 0)) ? ((29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5)) - (27 + (req_t_req_t_slv_req_t_AxiUserWidth + 0))) + 1 : ((27 + (req_t_req_t_slv_req_t_AxiUserWidth + 0)) - (29 + (req_t_req_t_slv_req_t_AxiUserWidth + 5))) + 1)]; + initial _sv2v_0 = 0; +endmodule +// removed module with interface ports: axi_atop_filter_intf +// removed module with interface ports: axi_cdc_intf +// removed module with interface ports: axi_lite_cdc_intf +// removed module with interface ports: axi_cut_intf +// removed module with interface ports: axi_lite_cut_intf +// removed module with interface ports: axi_delayer_intf +module axi_demux_3FE59_D0B23 ( + clk_i, + rst_ni, + test_i, + slv_req_i, + slv_aw_select_i, + slv_ar_select_i, + slv_resp_o, + mst_reqs_o, + mst_resps_i +); + // removed localparam type ar_chan_t_slv_ar_chan_t_AxiAddrWidth_type + // removed localparam type ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters_type + // removed localparam type ar_chan_t_slv_ar_chan_t_AxiUserWidth_type + parameter [31:0] ar_chan_t_slv_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] ar_chan_t_slv_ar_chan_t_AxiUserWidth = 0; + // removed localparam type aw_chan_t_slv_aw_chan_t_AxiAddrWidth_type + // removed localparam type aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters_type + // removed localparam type aw_chan_t_slv_aw_chan_t_AxiUserWidth_type + parameter [31:0] aw_chan_t_slv_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] aw_chan_t_slv_aw_chan_t_AxiUserWidth = 0; + // removed localparam type b_chan_t_slv_b_chan_t_AxiIdWidthMasters_type + // removed localparam type b_chan_t_slv_b_chan_t_AxiUserWidth_type + parameter [31:0] b_chan_t_slv_b_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] b_chan_t_slv_b_chan_t_AxiUserWidth = 0; + // removed localparam type r_chan_t_slv_r_chan_t_AxiDataWidth_type + // removed localparam type r_chan_t_slv_r_chan_t_AxiIdWidthMasters_type + // removed localparam type r_chan_t_slv_r_chan_t_AxiUserWidth_type + parameter [31:0] r_chan_t_slv_r_chan_t_AxiDataWidth = 0; + parameter [31:0] r_chan_t_slv_r_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] r_chan_t_slv_r_chan_t_AxiUserWidth = 0; + // removed localparam type req_t_slv_req_t_AxiAddrWidth_type + // removed localparam type req_t_slv_req_t_AxiDataWidth_type + // removed localparam type req_t_slv_req_t_AxiIdWidthMasters_type + // removed localparam type req_t_slv_req_t_AxiStrbWidth_type + // removed localparam type req_t_slv_req_t_AxiUserWidth_type + parameter [31:0] req_t_slv_req_t_AxiAddrWidth = 0; + parameter [31:0] req_t_slv_req_t_AxiDataWidth = 0; + parameter [31:0] req_t_slv_req_t_AxiIdWidthMasters = 0; + parameter [31:0] req_t_slv_req_t_AxiStrbWidth = 0; + parameter [31:0] req_t_slv_req_t_AxiUserWidth = 0; + // removed localparam type resp_t_slv_resp_t_AxiDataWidth_type + // removed localparam type resp_t_slv_resp_t_AxiIdWidthMasters_type + // removed localparam type resp_t_slv_resp_t_AxiUserWidth_type + parameter [31:0] resp_t_slv_resp_t_AxiDataWidth = 0; + parameter [31:0] resp_t_slv_resp_t_AxiIdWidthMasters = 0; + parameter [31:0] resp_t_slv_resp_t_AxiUserWidth = 0; + // removed localparam type w_chan_t_w_chan_t_AxiDataWidth_type + // removed localparam type w_chan_t_w_chan_t_AxiStrbWidth_type + // removed localparam type w_chan_t_w_chan_t_AxiUserWidth_type + parameter [31:0] w_chan_t_w_chan_t_AxiDataWidth = 0; + parameter [31:0] w_chan_t_w_chan_t_AxiStrbWidth = 0; + parameter [31:0] w_chan_t_w_chan_t_AxiUserWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:18:13 + parameter [31:0] AxiIdWidth = 32'd0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:19:26 + // removed localparam type aw_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:20:26 + // removed localparam type w_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:21:26 + // removed localparam type b_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:22:26 + // removed localparam type ar_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:23:26 + // removed localparam type r_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:24:26 + // removed localparam type req_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:25:26 + // removed localparam type resp_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:26:13 + parameter [31:0] NoMstPorts = 32'd0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:27:13 + parameter [31:0] MaxTrans = 32'd8; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:28:13 + parameter [31:0] AxiLookBits = 32'd3; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:29:13 + parameter [0:0] FallThrough = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:30:13 + parameter [0:0] SpillAw = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:31:13 + parameter [0:0] SpillW = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:32:13 + parameter [0:0] SpillB = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:33:13 + parameter [0:0] SpillAr = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:34:13 + parameter [0:0] SpillR = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:36:13 + parameter [31:0] SelectWidth = (NoMstPorts > 32'd1 ? $clog2(NoMstPorts) : 32'd1); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:37:26 + // removed localparam type select_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:39:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:40:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:41:3 + input wire test_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:43:3 + input wire [(((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1:0] slv_req_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:44:3 + input wire [SelectWidth - 1:0] slv_aw_select_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:45:3 + input wire [SelectWidth - 1:0] slv_ar_select_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:46:3 + output wire [(((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth)) - 1:0] slv_resp_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:48:3 + output reg [(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (NoMstPorts * ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2)) - 1 : (NoMstPorts * (1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 0)):(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1)] mst_reqs_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:49:3 + input wire [(NoMstPorts * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) - 1:0] mst_resps_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:52:3 + localparam [31:0] IdCounterWidth = (MaxTrans > 1 ? $clog2(MaxTrans) : 1); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:57:3 + // removed localparam type axi_id_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:58:3 + // removed localparam type aw_chan_select_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:62:3 + // removed localparam type ar_chan_select_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:68:3 + generate + if (NoMstPorts == 32'h00000001) begin : gen_no_demux + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:69:5 + wire [(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1)) * 1:1] sv2v_tmp_343E5; + assign sv2v_tmp_343E5 = slv_req_i; + always @(*) mst_reqs_o[(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) + 0+:(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))] = sv2v_tmp_343E5; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:70:5 + assign slv_resp_o = mst_resps_i; + end + else begin : gen_demux + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:84:5 + wire [((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + SelectWidth) - 1:0] slv_aw_chan_select; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:85:5 + wire slv_aw_valid; + reg slv_aw_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:88:5 + wire [SelectWidth - 1:0] lookup_aw_select; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:89:5 + wire aw_select_occupied; + wire aw_id_cnt_full; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:90:5 + reg aw_push; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:92:5 + reg atop_inject; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:95:5 + reg w_fifo_pop; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:96:5 + wire w_fifo_full; + wire w_fifo_empty; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:97:5 + wire [SelectWidth - 1:0] w_select; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:100:5 + reg lock_aw_valid_d; + reg lock_aw_valid_q; + reg load_aw_lock; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:101:5 + reg aw_valid; + wire aw_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:104:5 + wire [(((w_chan_t_w_chan_t_AxiDataWidth + w_chan_t_w_chan_t_AxiStrbWidth) + 1) + w_chan_t_w_chan_t_AxiUserWidth) - 1:0] slv_w_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:105:5 + wire slv_w_valid; + reg slv_w_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:108:5 + wire [(NoMstPorts * ((b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + b_chan_t_slv_b_chan_t_AxiUserWidth)) - 1:0] mst_b_chans; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:109:5 + wire [NoMstPorts - 1:0] mst_b_valids; + wire [NoMstPorts - 1:0] mst_b_readies; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:112:5 + wire [((b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + b_chan_t_slv_b_chan_t_AxiUserWidth) - 1:0] slv_b_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:113:5 + wire slv_b_valid; + wire slv_b_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:119:5 + wire [((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + SelectWidth) - 1:0] slv_ar_chan_select; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:120:5 + wire slv_ar_valid; + reg slv_ar_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:123:5 + wire [SelectWidth - 1:0] lookup_ar_select; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:124:5 + wire ar_select_occupied; + wire ar_id_cnt_full; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:125:5 + reg ar_push; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:128:5 + reg lock_ar_valid_d; + reg lock_ar_valid_q; + reg load_ar_lock; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:129:5 + reg ar_valid; + wire ar_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:132:5 + wire [(NoMstPorts * (((r_chan_t_slv_r_chan_t_AxiIdWidthMasters + r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + r_chan_t_slv_r_chan_t_AxiUserWidth)) - 1:0] mst_r_chans; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:133:5 + wire [NoMstPorts - 1:0] mst_r_valids; + wire [NoMstPorts - 1:0] mst_r_readies; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:136:5 + wire [(((r_chan_t_slv_r_chan_t_AxiIdWidthMasters + r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + r_chan_t_slv_r_chan_t_AxiUserWidth) - 1:0] slv_r_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:137:5 + wire slv_r_valid; + wire slv_r_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:149:5 + wire [((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + SelectWidth) - 1:0] slv_aw_chan_select_in; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:150:5 + assign slv_aw_chan_select_in[(((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)-:(((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) >= (SelectWidth + 0) ? (((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (SelectWidth + 0)) + 1 : ((SelectWidth + 0) - ((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1))) + 1)] = slv_req_i[(((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))-:(((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) >= (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)))) ? (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) - (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)))) - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:151:5 + assign slv_aw_chan_select_in[SelectWidth - 1-:SelectWidth] = slv_aw_select_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:153:5 + spill_register_B26F0_61C30 #( + .T_SelectWidth(SelectWidth), + .T_aw_chan_t_slv_aw_chan_t_AxiAddrWidth(aw_chan_t_slv_aw_chan_t_AxiAddrWidth), + .T_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters(aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters), + .T_aw_chan_t_slv_aw_chan_t_AxiUserWidth(aw_chan_t_slv_aw_chan_t_AxiUserWidth), + .Bypass(~SpillAw) + ) i_aw_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(slv_req_i[1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))]), + .ready_o(slv_resp_o[4 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))]), + .data_i(slv_aw_chan_select_in), + .valid_o(slv_aw_valid), + .ready_i(slv_aw_ready), + .data_o(slv_aw_chan_select) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:168:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:170:7 + slv_aw_ready = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:171:7 + aw_valid = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:177:7 + lock_aw_valid_d = lock_aw_valid_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:178:7 + load_aw_lock = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:180:7 + aw_push = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:182:7 + atop_inject = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:184:7 + if (lock_aw_valid_q) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:185:9 + aw_valid = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:187:9 + if (aw_ready) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:188:11 + slv_aw_ready = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:189:11 + lock_aw_valid_d = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:190:11 + load_aw_lock = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:191:11 + atop_inject = slv_aw_chan_select[((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) - 1) - (aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5))]; + end + end + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:196:9 + if ((!aw_id_cnt_full && !w_fifo_full) && !ar_id_cnt_full) begin + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:198:11 + if (slv_aw_valid && (!aw_select_occupied || (slv_aw_chan_select[SelectWidth - 1-:SelectWidth] == lookup_aw_select))) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:201:13 + aw_valid = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:203:13 + aw_push = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:205:13 + if (aw_ready) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:206:15 + slv_aw_ready = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:207:15 + atop_inject = slv_aw_chan_select[((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) - 1) - (aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5))]; + end + else begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:210:15 + lock_aw_valid_d = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:211:15 + load_aw_lock = 1'b1; + end + end + end + end + end + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:220:75 + always @(posedge clk_i or negedge rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:220:143 + if (!rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:220:211 + lock_aw_valid_q <= 1'sb0; + else + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:220:343 + lock_aw_valid_q <= (load_aw_lock ? lock_aw_valid_d : lock_aw_valid_q); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:222:5 + localparam [31:0] sv2v_uu_i_aw_id_counter_AxiIdBits = AxiLookBits; + // removed localparam type sv2v_uu_i_aw_id_counter_inject_axi_id_i + localparam [sv2v_uu_i_aw_id_counter_AxiIdBits - 1:0] sv2v_uu_i_aw_id_counter_ext_inject_axi_id_i_0 = 1'sb0; + axi_demux_id_counters_2349C_D3F56 #( + .mst_port_select_t_SelectWidth(SelectWidth), + .AxiIdBits(AxiLookBits), + .CounterWidth(IdCounterWidth) + ) i_aw_id_counter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .lookup_axi_id_i(slv_aw_chan_select[((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) - 1) - ((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)))+:AxiLookBits]), + .lookup_mst_select_o(lookup_aw_select), + .lookup_mst_select_occupied_o(aw_select_occupied), + .full_o(aw_id_cnt_full), + .inject_axi_id_i(sv2v_uu_i_aw_id_counter_ext_inject_axi_id_i_0), + .inject_i(1'b0), + .push_axi_id_i(slv_aw_chan_select[((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) - 1) - ((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)))+:AxiLookBits]), + .push_mst_select_i(slv_aw_chan_select[SelectWidth - 1-:SelectWidth]), + .push_i(aw_push), + .pop_axi_id_i(slv_b_chan[(b_chan_t_slv_b_chan_t_AxiIdWidthMasters + (b_chan_t_slv_b_chan_t_AxiUserWidth + 1)) - (b_chan_t_slv_b_chan_t_AxiIdWidthMasters - 1)+:AxiLookBits]), + .pop_i(slv_b_valid & slv_b_ready) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:244:5 + fifo_v3_A7CFE_56795 #( + .dtype_SelectWidth(SelectWidth), + .FALL_THROUGH(FallThrough), + .DEPTH(MaxTrans) + ) i_w_fifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .testmode_i(test_i), + .full_o(w_fifo_full), + .empty_o(w_fifo_empty), + .usage_o(), + .data_i(slv_aw_chan_select[SelectWidth - 1-:SelectWidth]), + .push_i(aw_push), + .data_o(w_select), + .pop_i(w_fifo_pop) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:265:5 + spill_register_2E020_83570 #( + .T_w_chan_t_w_chan_t_AxiDataWidth(w_chan_t_w_chan_t_AxiDataWidth), + .T_w_chan_t_w_chan_t_AxiStrbWidth(w_chan_t_w_chan_t_AxiStrbWidth), + .T_w_chan_t_w_chan_t_AxiUserWidth(w_chan_t_w_chan_t_AxiUserWidth), + .Bypass(~SpillW) + ) i_w_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(slv_req_i[2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)]), + .ready_o(slv_resp_o[2 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))]), + .data_i(slv_req_i[(((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))-:(((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)) - ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))) + 1)]), + .valid_o(slv_w_valid), + .ready_i(slv_w_ready), + .data_o(slv_w_chan) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:283:5 + spill_register_476C7_0441D #( + .T_b_chan_t_slv_b_chan_t_AxiIdWidthMasters(b_chan_t_slv_b_chan_t_AxiIdWidthMasters), + .T_b_chan_t_slv_b_chan_t_AxiUserWidth(b_chan_t_slv_b_chan_t_AxiUserWidth), + .Bypass(~SpillB) + ) i_b_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(slv_b_valid), + .ready_o(slv_b_ready), + .data_i(slv_b_chan), + .valid_o(slv_resp_o[1 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))]), + .ready_i(slv_req_i[1 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)]), + .data_o(slv_resp_o[((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)-:((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) >= (1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) ? ((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - (1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1)]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:298:5 + localparam [31:0] sv2v_uu_i_b_mux_NumIn = NoMstPorts; + localparam [31:0] sv2v_uu_i_b_mux_IdxWidth = (sv2v_uu_i_b_mux_NumIn > 32'd1 ? $unsigned($clog2(sv2v_uu_i_b_mux_NumIn)) : 32'd1); + // removed localparam type sv2v_uu_i_b_mux_rr_i + localparam [sv2v_uu_i_b_mux_IdxWidth - 1:0] sv2v_uu_i_b_mux_ext_rr_i_0 = 1'sb0; + rr_arb_tree_7C886_BBDFA #( + .DataType_b_chan_t_slv_b_chan_t_AxiIdWidthMasters(b_chan_t_slv_b_chan_t_AxiIdWidthMasters), + .DataType_b_chan_t_slv_b_chan_t_AxiUserWidth(b_chan_t_slv_b_chan_t_AxiUserWidth), + .NumIn(NoMstPorts), + .AxiVldRdy(1'b1), + .LockIn(1'b1) + ) i_b_mux( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .rr_i(sv2v_uu_i_b_mux_ext_rr_i_0), + .req_i(mst_b_valids), + .gnt_o(mst_b_readies), + .data_i(mst_b_chans), + .gnt_i(slv_b_ready), + .req_o(slv_b_valid), + .data_o(slv_b_chan), + .idx_o() + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:320:5 + wire [((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + SelectWidth) - 1:0] slv_ar_chan_select_in; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:321:5 + assign slv_ar_chan_select_in[(((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)-:(((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)) >= (SelectWidth + 0) ? (((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (SelectWidth + 0)) + 1 : ((SelectWidth + 0) - ((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1))) + 1)] = slv_req_i[(((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1-:(((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:323:5 + assign slv_ar_chan_select_in[SelectWidth - 1-:SelectWidth] = slv_ar_select_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:324:5 + spill_register_03B00_458D1 #( + .T_SelectWidth(SelectWidth), + .T_ar_chan_t_slv_ar_chan_t_AxiAddrWidth(ar_chan_t_slv_ar_chan_t_AxiAddrWidth), + .T_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters(ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters), + .T_ar_chan_t_slv_ar_chan_t_AxiUserWidth(ar_chan_t_slv_ar_chan_t_AxiUserWidth), + .Bypass(~SpillAr) + ) i_ar_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(slv_req_i[1]), + .ready_o(slv_resp_o[3 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))]), + .data_i(slv_ar_chan_select_in), + .valid_o(slv_ar_valid), + .ready_i(slv_ar_ready), + .data_o(slv_ar_chan_select) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:339:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:341:7 + slv_ar_ready = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:342:7 + ar_valid = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:347:7 + lock_ar_valid_d = lock_ar_valid_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:348:7 + load_ar_lock = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:350:7 + ar_push = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:353:7 + if (lock_ar_valid_q) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:354:9 + ar_valid = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:356:9 + if (ar_ready) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:357:11 + slv_ar_ready = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:358:11 + ar_push = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:359:11 + lock_ar_valid_d = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:360:11 + load_ar_lock = 1'b1; + end + end + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:364:9 + if (!ar_id_cnt_full) begin + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:366:11 + if (slv_ar_valid && (!ar_select_occupied || (slv_ar_chan_select[SelectWidth - 1-:SelectWidth] == lookup_ar_select))) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:369:13 + ar_valid = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:371:13 + if (ar_ready) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:372:15 + slv_ar_ready = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:373:15 + ar_push = 1'b1; + end + else begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:376:15 + lock_ar_valid_d = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:377:15 + load_ar_lock = 1'b1; + end + end + end + end + end + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:385:75 + always @(posedge clk_i or negedge rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:385:143 + if (!rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:385:211 + lock_ar_valid_q <= 1'sb0; + else + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:385:343 + lock_ar_valid_q <= (load_ar_lock ? lock_ar_valid_d : lock_ar_valid_q); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:387:5 + axi_demux_id_counters_2349C_D3F56 #( + .mst_port_select_t_SelectWidth(SelectWidth), + .AxiIdBits(AxiLookBits), + .CounterWidth(IdCounterWidth) + ) i_ar_id_counter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .lookup_axi_id_i(slv_ar_chan_select[((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) - 1) - ((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1)))+:AxiLookBits]), + .lookup_mst_select_o(lookup_ar_select), + .lookup_mst_select_occupied_o(ar_select_occupied), + .full_o(ar_id_cnt_full), + .inject_axi_id_i(slv_aw_chan_select[((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) - 1) - ((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)))+:AxiLookBits]), + .inject_i(atop_inject), + .push_axi_id_i(slv_ar_chan_select[((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) - 1) - ((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1)))+:AxiLookBits]), + .push_mst_select_i(slv_ar_chan_select[SelectWidth - 1-:SelectWidth]), + .push_i(ar_push), + .pop_axi_id_i(slv_r_chan[(r_chan_t_slv_r_chan_t_AxiIdWidthMasters + (r_chan_t_slv_r_chan_t_AxiDataWidth + (r_chan_t_slv_r_chan_t_AxiUserWidth + 2))) - (r_chan_t_slv_r_chan_t_AxiIdWidthMasters - 1)+:AxiLookBits]), + .pop_i((slv_r_valid & slv_r_ready) & slv_r_chan[r_chan_t_slv_r_chan_t_AxiUserWidth + 0]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:411:5 + spill_register_21A26_75D51 #( + .T_r_chan_t_slv_r_chan_t_AxiDataWidth(r_chan_t_slv_r_chan_t_AxiDataWidth), + .T_r_chan_t_slv_r_chan_t_AxiIdWidthMasters(r_chan_t_slv_r_chan_t_AxiIdWidthMasters), + .T_r_chan_t_slv_r_chan_t_AxiUserWidth(r_chan_t_slv_r_chan_t_AxiUserWidth), + .Bypass(~SpillR) + ) i_r_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(slv_r_valid), + .ready_o(slv_r_ready), + .data_i(slv_r_chan), + .valid_o(slv_resp_o[(((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0]), + .ready_i(slv_req_i[0]), + .data_o(slv_resp_o[(((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1-:((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:426:5 + localparam [31:0] sv2v_uu_i_r_mux_NumIn = NoMstPorts; + localparam [31:0] sv2v_uu_i_r_mux_IdxWidth = (sv2v_uu_i_r_mux_NumIn > 32'd1 ? $unsigned($clog2(sv2v_uu_i_r_mux_NumIn)) : 32'd1); + // removed localparam type sv2v_uu_i_r_mux_rr_i + localparam [sv2v_uu_i_r_mux_IdxWidth - 1:0] sv2v_uu_i_r_mux_ext_rr_i_0 = 1'sb0; + rr_arb_tree_CBFCA_FCD03 #( + .DataType_r_chan_t_slv_r_chan_t_AxiDataWidth(r_chan_t_slv_r_chan_t_AxiDataWidth), + .DataType_r_chan_t_slv_r_chan_t_AxiIdWidthMasters(r_chan_t_slv_r_chan_t_AxiIdWidthMasters), + .DataType_r_chan_t_slv_r_chan_t_AxiUserWidth(r_chan_t_slv_r_chan_t_AxiUserWidth), + .NumIn(NoMstPorts), + .AxiVldRdy(1'b1), + .LockIn(1'b1) + ) i_r_mux( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .rr_i(sv2v_uu_i_r_mux_ext_rr_i_0), + .req_i(mst_r_valids), + .gnt_o(mst_r_readies), + .data_i(mst_r_chans), + .gnt_i(slv_r_ready), + .req_o(slv_r_valid), + .data_o(slv_r_chan), + .idx_o() + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:445:4 + assign ar_ready = ar_valid & mst_resps_i[(slv_ar_chan_select[SelectWidth - 1-:SelectWidth] * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + (3 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:446:4 + assign aw_ready = aw_valid & mst_resps_i[(slv_aw_chan_select[SelectWidth - 1-:SelectWidth] * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + (4 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:450:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:452:7 + mst_reqs_o = 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:453:7 + slv_w_ready = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:454:7 + w_fifo_pop = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:456:7 + begin : sv2v_autoblock_1 + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:456:12 + reg [31:0] i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:456:12 + for (i = 0; i < NoMstPorts; i = i + 1) + begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:458:9 + mst_reqs_o[(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))))) : (((i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))))) + (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) >= (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)))) ? (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) - (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)))) - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))))) + 1)) - 1)-:(((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) >= (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)))) ? (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) - (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)))) - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))))) + 1)] = slv_aw_chan_select[(((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)-:(((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) >= (SelectWidth + 0) ? (((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (SelectWidth + 0)) + 1 : ((SelectWidth + 0) - ((((aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + aw_chan_t_slv_aw_chan_t_AxiUserWidth) + (SelectWidth - 1))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:459:9 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))))] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:460:9 + if (aw_valid && (slv_aw_chan_select[SelectWidth - 1-:SelectWidth] == i)) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:461:11 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:465:9 + mst_reqs_o[(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))) : (((i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) + (((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)) - ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))) + 1)) - 1)-:(((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 2)) - ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))) + 1)] = slv_w_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:466:9 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))] = 1'b0; + if (!w_fifo_empty && (w_select == i)) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:468:11 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))] = slv_w_valid; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:469:11 + slv_w_ready = mst_resps_i[(i * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + (2 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:470:11 + w_fifo_pop = (slv_w_valid & mst_resps_i[(i * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + (2 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)))]) & slv_w_chan[w_chan_t_w_chan_t_AxiUserWidth + 0]; + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:474:9 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - (1 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))] = mst_b_readies[i]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:477:9 + mst_reqs_o[(((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1 : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)) : (((i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1 : ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) + (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) - 1)-:(((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))] = slv_ar_chan_select[(((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)-:(((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)) >= (SelectWidth + 0) ? (((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1)) - (SelectWidth + 0)) + 1 : ((SelectWidth + 0) - ((((ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + ar_chan_t_slv_ar_chan_t_AxiUserWidth) + (SelectWidth - 1))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:478:9 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 : (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 0)] = 1'b0; + if (ar_valid && (slv_ar_chan_select[SelectWidth - 1-:SelectWidth] == i)) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:480:11 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 : (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 0)] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:484:9 + mst_reqs_o[(i * (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1)] = mst_r_readies[i]; + end + end + end + genvar _gv_i_83; + for (_gv_i_83 = 0; _gv_i_83 < NoMstPorts; _gv_i_83 = _gv_i_83 + 1) begin : gen_b_channels + localparam i = _gv_i_83; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:489:7 + assign mst_b_chans[i * ((b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + b_chan_t_slv_b_chan_t_AxiUserWidth)+:(b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + b_chan_t_slv_b_chan_t_AxiUserWidth] = mst_resps_i[(i * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))-:((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) >= (1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) ? ((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - (1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:490:7 + assign mst_b_valids[i] = mst_resps_i[(i * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + (1 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:491:7 + assign mst_r_chans[i * (((r_chan_t_slv_r_chan_t_AxiIdWidthMasters + r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + r_chan_t_slv_r_chan_t_AxiUserWidth)+:((r_chan_t_slv_r_chan_t_AxiIdWidthMasters + r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + r_chan_t_slv_r_chan_t_AxiUserWidth] = mst_resps_i[(i * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1)-:((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:492:7 + assign mst_r_valids[i] = mst_resps_i[(i * (((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth))) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)]; + end + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module axi_demux_id_counters_2349C_D3F56 ( + clk_i, + rst_ni, + lookup_axi_id_i, + lookup_mst_select_o, + lookup_mst_select_occupied_o, + full_o, + push_axi_id_i, + push_mst_select_i, + push_i, + inject_axi_id_i, + inject_i, + pop_axi_id_i, + pop_i +); + // removed localparam type mst_port_select_t_SelectWidth_type + parameter [31:0] mst_port_select_t_SelectWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:540:13 + parameter [31:0] AxiIdBits = 2; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:541:13 + parameter [31:0] CounterWidth = 4; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:542:26 + // removed localparam type mst_port_select_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:544:3 + input clk_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:545:3 + input rst_ni; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:547:3 + input wire [AxiIdBits - 1:0] lookup_axi_id_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:548:3 + output wire [mst_port_select_t_SelectWidth - 1:0] lookup_mst_select_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:549:3 + output wire lookup_mst_select_occupied_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:551:3 + output wire full_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:552:3 + input wire [AxiIdBits - 1:0] push_axi_id_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:553:3 + input wire [mst_port_select_t_SelectWidth - 1:0] push_mst_select_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:554:3 + input wire push_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:556:3 + input wire [AxiIdBits - 1:0] inject_axi_id_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:557:3 + input wire inject_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:559:3 + input wire [AxiIdBits - 1:0] pop_axi_id_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:560:3 + input wire pop_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:562:3 + localparam [31:0] NoCounters = 2 ** AxiIdBits; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:563:3 + // removed localparam type cnt_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:566:3 + reg [(NoCounters * mst_port_select_t_SelectWidth) - 1:0] mst_select_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:569:3 + wire [NoCounters - 1:0] push_en; + wire [NoCounters - 1:0] inject_en; + wire [NoCounters - 1:0] pop_en; + wire [NoCounters - 1:0] occupied; + wire [NoCounters - 1:0] cnt_full; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:574:3 + assign lookup_mst_select_o = mst_select_q[lookup_axi_id_i * mst_port_select_t_SelectWidth+:mst_port_select_t_SelectWidth]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:575:3 + assign lookup_mst_select_occupied_o = occupied[lookup_axi_id_i]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:579:3 + assign push_en = (push_i ? 1 << push_axi_id_i : {NoCounters {1'sb0}}); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:580:3 + assign inject_en = (inject_i ? 1 << inject_axi_id_i : {NoCounters {1'sb0}}); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:581:3 + assign pop_en = (pop_i ? 1 << pop_axi_id_i : {NoCounters {1'sb0}}); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:582:3 + assign full_o = |cnt_full; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:584:3 + genvar _gv_i_84; + function automatic [CounterWidth - 1:0] sv2v_cast_9AD3B; + input reg [CounterWidth - 1:0] inp; + sv2v_cast_9AD3B = inp; + endfunction + generate + for (_gv_i_84 = 0; _gv_i_84 < NoCounters; _gv_i_84 = _gv_i_84 + 1) begin : gen_counters + localparam i = _gv_i_84; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:585:5 + reg cnt_en; + reg cnt_down; + wire overflow; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:586:5 + reg [CounterWidth - 1:0] cnt_delta; + wire [CounterWidth - 1:0] in_flight; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:587:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:588:7 + (* full_case, parallel_case *) + case ({push_en[i], inject_en[i], pop_en[i]}) + 3'b001: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:590:11 + cnt_en = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:591:11 + cnt_down = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:592:11 + cnt_delta = sv2v_cast_9AD3B(1); + end + 3'b010: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:595:11 + cnt_en = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:596:11 + cnt_down = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:597:11 + cnt_delta = sv2v_cast_9AD3B(1); + end + 3'b100: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:601:11 + cnt_en = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:602:11 + cnt_down = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:603:11 + cnt_delta = sv2v_cast_9AD3B(1); + end + 3'b110: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:607:11 + cnt_en = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:608:11 + cnt_down = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:609:11 + cnt_delta = sv2v_cast_9AD3B(2); + end + 3'b111: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:612:11 + cnt_en = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:613:11 + cnt_down = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:614:11 + cnt_delta = sv2v_cast_9AD3B(1); + end + default: begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:617:11 + cnt_en = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:618:11 + cnt_down = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:619:11 + cnt_delta = sv2v_cast_9AD3B(0); + end + endcase + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:624:5 + localparam [31:0] sv2v_uu_i_in_flight_cnt_WIDTH = CounterWidth; + // removed localparam type sv2v_uu_i_in_flight_cnt_d_i + localparam [CounterWidth - 1:0] sv2v_uu_i_in_flight_cnt_ext_d_i_0 = 1'sb0; + delta_counter #( + .WIDTH(CounterWidth), + .STICKY_OVERFLOW(1'b0) + ) i_in_flight_cnt( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clear_i(1'b0), + .en_i(cnt_en), + .load_i(1'b0), + .down_i(cnt_down), + .delta_i(cnt_delta), + .d_i(sv2v_uu_i_in_flight_cnt_ext_d_i_0), + .q_o(in_flight), + .overflow_o(overflow) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:639:5 + assign occupied[i] = |in_flight; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:640:5 + assign cnt_full[i] = overflow | &in_flight; + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:643:75 + always @(posedge clk_i or negedge rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:643:143 + if (!rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:643:211 + mst_select_q[i * mst_port_select_t_SelectWidth+:mst_port_select_t_SelectWidth] <= 1'sb0; + else + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_demux.sv:643:343 + mst_select_q[i * mst_port_select_t_SelectWidth+:mst_port_select_t_SelectWidth] <= (push_en[i] ? push_mst_select_i : mst_select_q[i * mst_port_select_t_SelectWidth+:mst_port_select_t_SelectWidth]); + end + endgenerate + initial _sv2v_0 = 0; +endmodule +// removed module with interface ports: axi_demux_intf +module axi_id_prepend_7D093_4DC7E ( + pre_id_i, + slv_aw_chans_i, + slv_aw_valids_i, + slv_aw_readies_o, + slv_w_chans_i, + slv_w_valids_i, + slv_w_readies_o, + slv_b_chans_o, + slv_b_valids_o, + slv_b_readies_i, + slv_ar_chans_i, + slv_ar_valids_i, + slv_ar_readies_o, + slv_r_chans_o, + slv_r_valids_o, + slv_r_readies_i, + mst_aw_chans_o, + mst_aw_valids_o, + mst_aw_readies_i, + mst_w_chans_o, + mst_w_valids_o, + mst_w_readies_i, + mst_b_chans_i, + mst_b_valids_i, + mst_b_readies_o, + mst_ar_chans_o, + mst_ar_valids_o, + mst_ar_readies_i, + mst_r_chans_i, + mst_r_valids_i, + mst_r_readies_o +); + // removed localparam type mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth_type + // removed localparam type mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth_type + parameter [31:0] mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth = 0; + // removed localparam type mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth_type + // removed localparam type mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth_type + parameter [31:0] mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth = 0; + // removed localparam type mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiUserWidth_type + parameter [31:0] mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiUserWidth = 0; + // removed localparam type mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiDataWidth_type + // removed localparam type mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiUserWidth_type + parameter [31:0] mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiDataWidth = 0; + parameter [31:0] mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiUserWidth = 0; + // removed localparam type mst_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth_type + // removed localparam type mst_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth_type + // removed localparam type mst_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth_type + parameter [31:0] mst_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth = 0; + parameter [31:0] mst_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth = 0; + parameter [31:0] mst_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth = 0; + // removed localparam type slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth_type + // removed localparam type slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth_type + parameter [31:0] slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth = 0; + // removed localparam type slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth_type + // removed localparam type slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth_type + parameter [31:0] slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth = 0; + // removed localparam type slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiUserWidth_type + parameter [31:0] slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiUserWidth = 0; + // removed localparam type slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiDataWidth_type + // removed localparam type slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiUserWidth_type + parameter [31:0] slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiDataWidth = 0; + parameter [31:0] slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiUserWidth = 0; + // removed localparam type slv_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth_type + // removed localparam type slv_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth_type + // removed localparam type slv_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth_type + parameter [31:0] slv_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth = 0; + parameter [31:0] slv_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth = 0; + parameter [31:0] slv_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:17:13 + parameter [31:0] NoBus = 1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:18:13 + parameter [31:0] AxiIdWidthSlvPort = 4; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:19:13 + parameter [31:0] AxiIdWidthMstPort = 6; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:20:26 + // removed localparam type slv_aw_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:21:26 + // removed localparam type slv_w_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:22:26 + // removed localparam type slv_b_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:23:26 + // removed localparam type slv_ar_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:24:26 + // removed localparam type slv_r_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:25:26 + // removed localparam type mst_aw_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:26:26 + // removed localparam type mst_w_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:27:26 + // removed localparam type mst_b_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:28:26 + // removed localparam type mst_ar_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:29:26 + // removed localparam type mst_r_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:31:13 + parameter [31:0] PreIdWidth = AxiIdWidthMstPort - AxiIdWidthSlvPort; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:33:3 + input wire [PreIdWidth - 1:0] pre_id_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:36:3 + input wire [(NoBus * (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth)) - 1:0] slv_aw_chans_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:37:3 + input wire [NoBus - 1:0] slv_aw_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:38:3 + output wire [NoBus - 1:0] slv_aw_readies_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:40:3 + input wire [(NoBus * (((slv_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth + slv_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth) + 1) + slv_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth)) - 1:0] slv_w_chans_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:41:3 + input wire [NoBus - 1:0] slv_w_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:42:3 + output wire [NoBus - 1:0] slv_w_readies_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:44:3 + output wire [(NoBus * ((slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiUserWidth)) - 1:0] slv_b_chans_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:45:3 + output wire [NoBus - 1:0] slv_b_valids_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:46:3 + input wire [NoBus - 1:0] slv_b_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:48:3 + input wire [(NoBus * (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth)) - 1:0] slv_ar_chans_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:49:3 + input wire [NoBus - 1:0] slv_ar_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:50:3 + output wire [NoBus - 1:0] slv_ar_readies_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:52:3 + output wire [(NoBus * (((slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiUserWidth)) - 1:0] slv_r_chans_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:53:3 + output wire [NoBus - 1:0] slv_r_valids_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:54:3 + input wire [NoBus - 1:0] slv_r_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:57:3 + output reg [(NoBus * (((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)) - 1:0] mst_aw_chans_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:58:3 + output wire [NoBus - 1:0] mst_aw_valids_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:59:3 + input wire [NoBus - 1:0] mst_aw_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:61:3 + output wire [(NoBus * (((mst_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth + mst_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth) + 1) + mst_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth)) - 1:0] mst_w_chans_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:62:3 + output wire [NoBus - 1:0] mst_w_valids_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:63:3 + input wire [NoBus - 1:0] mst_w_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:65:3 + input wire [(NoBus * ((mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiUserWidth)) - 1:0] mst_b_chans_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:66:3 + input wire [NoBus - 1:0] mst_b_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:67:3 + output wire [NoBus - 1:0] mst_b_readies_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:69:3 + output reg [(NoBus * (((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)) - 1:0] mst_ar_chans_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:70:3 + output wire [NoBus - 1:0] mst_ar_valids_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:71:3 + input wire [NoBus - 1:0] mst_ar_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:73:3 + input wire [(NoBus * (((mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiUserWidth)) - 1:0] mst_r_chans_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:74:3 + input wire [NoBus - 1:0] mst_r_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:75:3 + output wire [NoBus - 1:0] mst_r_readies_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:79:3 + genvar _gv_i_86; + generate + for (_gv_i_86 = 0; _gv_i_86 < NoBus; _gv_i_86 = _gv_i_86 + 1) begin : gen_id_prepend + localparam i = _gv_i_86; + if (PreIdWidth == 0) begin : gen_no_prepend + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:81:7 + wire [(((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) * 1:1] sv2v_tmp_3A044; + assign sv2v_tmp_3A044 = slv_aw_chans_i[i * (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth)+:((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth]; + always @(*) mst_aw_chans_o[i * (((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] = sv2v_tmp_3A044; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:82:7 + wire [(((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) * 1:1] sv2v_tmp_54010; + assign sv2v_tmp_54010 = slv_ar_chans_i[i * (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth)+:((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth]; + always @(*) mst_ar_chans_o[i * (((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] = sv2v_tmp_54010; + end + else begin : gen_prepend + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:84:7 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:85:9 + mst_aw_chans_o[i * (((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth] = slv_aw_chans_i[i * (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth)+:((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:86:9 + mst_ar_chans_o[i * (((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth] = slv_ar_chans_i[i * (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth)+:((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:87:9 + mst_aw_chans_o[(i * (((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)) + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (29 + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 5))))-:((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (29 + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 5)))) >= (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (35 + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 0))) ? ((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (29 + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 5)))) - (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (35 + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 0)))) + 1 : ((mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (35 + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 0))) - (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (29 + (mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 5))))) + 1)] = {pre_id_i, slv_aw_chans_i[(i * (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth) + 35) + slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth)) + (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) >= ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)) ? (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1)) : (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) + (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) >= ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)) ? (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1))) + 1 : (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1)))) + 1)) - 1)-:(((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) >= ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)) ? (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1))) + 1 : (((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1)) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth + (29 + (slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth + 5)))) - ((slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1)))) + 1)]}; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:88:9 + mst_ar_chans_o[(i * (((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)) + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth + (21 + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth + 7))))-:((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth + (21 + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth + 7)))) >= (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth + (29 + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth + 0))) ? ((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth + (21 + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth + 7)))) - (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth + (29 + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth + 0)))) + 1 : ((mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth + (29 + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth + 0))) - (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth + (21 + (mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth + 7))))) + 1)] = {pre_id_i, slv_ar_chans_i[(i * (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth) + 29) + slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth)) + (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) >= ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1)) ? (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1)) : (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) + (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) >= ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1)) ? (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1))) + 1 : (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1)) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1)))) + 1)) - 1)-:(((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) >= ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1)) ? (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1))) + 1 : (((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1)) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth + (21 + (slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth + 7)))) - ((slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters - 1) - (AxiIdWidthSlvPort - 1)))) + 1)]}; + end + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:93:5 + assign slv_b_chans_o[i * ((slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiUserWidth)+:(slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters + 2) + slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiUserWidth] = mst_b_chans_i[i * ((mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiUserWidth)+:(mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:94:5 + assign slv_r_chans_o[i * (((slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiUserWidth)+:((slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters + slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiDataWidth) + 3) + slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiUserWidth] = mst_r_chans_i[i * (((mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiUserWidth)+:((mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiUserWidth]; + end + endgenerate + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:98:3 + assign mst_w_chans_o = slv_w_chans_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:99:3 + assign mst_aw_valids_o = slv_aw_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:100:3 + assign slv_aw_readies_o = mst_aw_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:101:3 + assign mst_w_valids_o = slv_w_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:102:3 + assign slv_w_readies_o = mst_w_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:103:3 + assign slv_b_valids_o = mst_b_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:104:3 + assign mst_b_readies_o = slv_b_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:105:3 + assign mst_ar_valids_o = slv_ar_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:106:3 + assign slv_ar_readies_o = mst_ar_readies_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:107:3 + assign slv_r_valids_o = mst_r_valids_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_id_prepend.sv:108:3 + assign mst_r_readies_o = slv_r_readies_i; + initial _sv2v_0 = 0; +endmodule +// removed module with interface ports: axi_isolate_intf +// removed module with interface ports: axi_join_intf +// removed module with interface ports: axi_lite_demux_intf +// removed module with interface ports: axi_lite_join_intf +// removed module with interface ports: axi_lite_mailbox_intf +// removed module with interface ports: axi_lite_mux_intf +// removed module with interface ports: axi_lite_regs_intf +// removed module with interface ports: axi_lite_to_apb_intf +// removed module with interface ports: axi_lite_to_axi_intf +// removed module with interface ports: axi_modify_address_intf +module axi_mux_5C4FF_DA91C ( + clk_i, + rst_ni, + test_i, + slv_reqs_i, + slv_resps_o, + mst_req_o, + mst_resp_i +); + // removed localparam type mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth_type + // removed localparam type mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth_type + parameter [31:0] mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth = 0; + // removed localparam type mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth_type + // removed localparam type mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth_type + parameter [31:0] mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth = 0; + // removed localparam type mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_b_chan_t_mst_b_chan_t_AxiUserWidth_type + parameter [31:0] mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_b_chan_t_mst_b_chan_t_AxiUserWidth = 0; + // removed localparam type mst_r_chan_t_mst_r_chan_t_AxiDataWidth_type + // removed localparam type mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_r_chan_t_mst_r_chan_t_AxiUserWidth_type + parameter [31:0] mst_r_chan_t_mst_r_chan_t_AxiDataWidth = 0; + parameter [31:0] mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_r_chan_t_mst_r_chan_t_AxiUserWidth = 0; + // removed localparam type mst_req_t_mst_req_t_AxiAddrWidth_type + // removed localparam type mst_req_t_mst_req_t_AxiDataWidth_type + // removed localparam type mst_req_t_mst_req_t_AxiIdWidthSlaves_type + // removed localparam type mst_req_t_mst_req_t_AxiStrbWidth_type + // removed localparam type mst_req_t_mst_req_t_AxiUserWidth_type + parameter [31:0] mst_req_t_mst_req_t_AxiAddrWidth = 0; + parameter [31:0] mst_req_t_mst_req_t_AxiDataWidth = 0; + parameter [31:0] mst_req_t_mst_req_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_req_t_mst_req_t_AxiStrbWidth = 0; + parameter [31:0] mst_req_t_mst_req_t_AxiUserWidth = 0; + // removed localparam type mst_resp_t_mst_resp_t_AxiDataWidth_type + // removed localparam type mst_resp_t_mst_resp_t_AxiIdWidthSlaves_type + // removed localparam type mst_resp_t_mst_resp_t_AxiUserWidth_type + parameter [31:0] mst_resp_t_mst_resp_t_AxiDataWidth = 0; + parameter [31:0] mst_resp_t_mst_resp_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_resp_t_mst_resp_t_AxiUserWidth = 0; + // removed localparam type slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth_type + // removed localparam type slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth_type + parameter [31:0] slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth = 0; + // removed localparam type slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth_type + // removed localparam type slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth_type + parameter [31:0] slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth = 0; + // removed localparam type slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_b_chan_t_slv_b_chan_t_AxiUserWidth_type + parameter [31:0] slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_b_chan_t_slv_b_chan_t_AxiUserWidth = 0; + // removed localparam type slv_r_chan_t_slv_r_chan_t_AxiDataWidth_type + // removed localparam type slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_r_chan_t_slv_r_chan_t_AxiUserWidth_type + parameter [31:0] slv_r_chan_t_slv_r_chan_t_AxiDataWidth = 0; + parameter [31:0] slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_r_chan_t_slv_r_chan_t_AxiUserWidth = 0; + // removed localparam type slv_req_t_slv_req_t_AxiAddrWidth_type + // removed localparam type slv_req_t_slv_req_t_AxiDataWidth_type + // removed localparam type slv_req_t_slv_req_t_AxiIdWidthMasters_type + // removed localparam type slv_req_t_slv_req_t_AxiStrbWidth_type + // removed localparam type slv_req_t_slv_req_t_AxiUserWidth_type + parameter [31:0] slv_req_t_slv_req_t_AxiAddrWidth = 0; + parameter [31:0] slv_req_t_slv_req_t_AxiDataWidth = 0; + parameter [31:0] slv_req_t_slv_req_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_req_t_slv_req_t_AxiStrbWidth = 0; + parameter [31:0] slv_req_t_slv_req_t_AxiUserWidth = 0; + // removed localparam type slv_resp_t_slv_resp_t_AxiDataWidth_type + // removed localparam type slv_resp_t_slv_resp_t_AxiIdWidthMasters_type + // removed localparam type slv_resp_t_slv_resp_t_AxiUserWidth_type + parameter [31:0] slv_resp_t_slv_resp_t_AxiDataWidth = 0; + parameter [31:0] slv_resp_t_slv_resp_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_resp_t_slv_resp_t_AxiUserWidth = 0; + // removed localparam type w_chan_t_w_chan_t_AxiDataWidth_type + // removed localparam type w_chan_t_w_chan_t_AxiStrbWidth_type + // removed localparam type w_chan_t_w_chan_t_AxiUserWidth_type + parameter [31:0] w_chan_t_w_chan_t_AxiDataWidth = 0; + parameter [31:0] w_chan_t_w_chan_t_AxiStrbWidth = 0; + parameter [31:0] w_chan_t_w_chan_t_AxiUserWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:27:13 + parameter [31:0] SlvAxiIDWidth = 32'd0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:28:26 + // removed localparam type slv_aw_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:29:26 + // removed localparam type mst_aw_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:30:26 + // removed localparam type w_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:31:26 + // removed localparam type slv_b_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:32:26 + // removed localparam type mst_b_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:33:26 + // removed localparam type slv_ar_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:34:26 + // removed localparam type mst_ar_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:35:26 + // removed localparam type slv_r_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:36:26 + // removed localparam type mst_r_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:37:26 + // removed localparam type slv_req_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:38:26 + // removed localparam type slv_resp_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:39:26 + // removed localparam type mst_req_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:40:26 + // removed localparam type mst_resp_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:41:13 + parameter [31:0] NoSlvPorts = 32'd0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:43:13 + parameter [31:0] MaxWTrans = 32'd8; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:45:13 + parameter [0:0] FallThrough = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:47:13 + parameter [0:0] SpillAw = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:48:13 + parameter [0:0] SpillW = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:49:13 + parameter [0:0] SpillB = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:51:13 + parameter [0:0] SpillAr = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:52:13 + parameter [0:0] SpillR = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:54:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:55:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:56:3 + input wire test_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:58:3 + input wire [(((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (NoSlvPorts * ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2)) - 1 : (NoSlvPorts * (1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 0)):(((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1)] slv_reqs_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:59:3 + output wire [(NoSlvPorts * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) - 1:0] slv_resps_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:61:3 + output wire [(((((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 35) + mst_req_t_mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth)) + 1:0] mst_req_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:62:3 + input wire [(((4 + ((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth)) + 1) + (((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth)) - 1:0] mst_resp_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:65:3 + localparam [31:0] MstIdxBits = $clog2(NoSlvPorts); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:66:3 + localparam [31:0] MstAxiIDWidth = SlvAxiIDWidth + MstIdxBits; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:69:3 + function automatic [MstIdxBits - 1:0] sv2v_cast_753CC; + input reg [MstIdxBits - 1:0] inp; + sv2v_cast_753CC = inp; + endfunction + generate + if (NoSlvPorts == 32'h00000001) begin : gen_no_mux + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:70:5 + assign mst_req_o = slv_reqs_i[(((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) + 0+:(((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:71:5 + assign slv_resps_o[0+:((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth)] = mst_resp_i; + end + else begin : gen_mux + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:75:5 + // removed localparam type switch_id_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:78:5 + wire [(NoSlvPorts * (((mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)) - 1:0] slv_aw_chans; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:79:5 + wire [NoSlvPorts - 1:0] slv_aw_valids; + wire [NoSlvPorts - 1:0] slv_aw_readies; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:80:5 + wire [(NoSlvPorts * (((w_chan_t_w_chan_t_AxiDataWidth + w_chan_t_w_chan_t_AxiStrbWidth) + 1) + w_chan_t_w_chan_t_AxiUserWidth)) - 1:0] slv_w_chans; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:81:5 + wire [NoSlvPorts - 1:0] slv_w_valids; + reg [NoSlvPorts - 1:0] slv_w_readies; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:82:5 + wire [(NoSlvPorts * ((mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + mst_b_chan_t_mst_b_chan_t_AxiUserWidth)) - 1:0] slv_b_chans; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:83:5 + wire [NoSlvPorts - 1:0] slv_b_valids; + wire [NoSlvPorts - 1:0] slv_b_readies; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:84:5 + wire [(NoSlvPorts * (((mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)) - 1:0] slv_ar_chans; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:85:5 + wire [NoSlvPorts - 1:0] slv_ar_valids; + wire [NoSlvPorts - 1:0] slv_ar_readies; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:86:5 + wire [(NoSlvPorts * (((mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + mst_r_chan_t_mst_r_chan_t_AxiUserWidth)) - 1:0] slv_r_chans; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:87:5 + wire [NoSlvPorts - 1:0] slv_r_valids; + wire [NoSlvPorts - 1:0] slv_r_readies; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:91:5 + wire [(((mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth) - 1:0] mst_aw_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:92:5 + reg mst_aw_valid; + wire mst_aw_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:95:5 + wire aw_valid; + reg aw_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:100:5 + reg lock_aw_valid_d; + reg lock_aw_valid_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:101:5 + reg load_aw_lock; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:104:5 + wire w_fifo_full; + wire w_fifo_empty; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:105:5 + reg w_fifo_push; + reg w_fifo_pop; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:106:5 + wire [MstIdxBits - 1:0] w_fifo_data; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:109:5 + wire [(((w_chan_t_w_chan_t_AxiDataWidth + w_chan_t_w_chan_t_AxiStrbWidth) + 1) + w_chan_t_w_chan_t_AxiUserWidth) - 1:0] mst_w_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:110:5 + reg mst_w_valid; + wire mst_w_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:113:5 + wire [MstIdxBits - 1:0] switch_b_id; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:116:5 + wire [((mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + mst_b_chan_t_mst_b_chan_t_AxiUserWidth) - 1:0] mst_b_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:117:5 + wire mst_b_valid; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:120:5 + wire [(((mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth) - 1:0] mst_ar_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:121:5 + wire ar_valid; + wire ar_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:124:5 + wire [MstIdxBits - 1:0] switch_r_id; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:127:5 + wire [(((mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + mst_r_chan_t_mst_r_chan_t_AxiUserWidth) - 1:0] mst_r_chan; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:128:5 + wire mst_r_valid; + genvar _gv_i_107; + for (_gv_i_107 = 0; _gv_i_107 < NoSlvPorts; _gv_i_107 = _gv_i_107 + 1) begin : gen_id_prepend + localparam i = _gv_i_107; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:134:7 + axi_id_prepend_7D093_4DC7E #( + .mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth(mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth), + .mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves(mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves), + .mst_ar_chan_t_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth(mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth), + .mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth(mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth), + .mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves(mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves), + .mst_aw_chan_t_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth(mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth), + .mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves(mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves), + .mst_b_chan_t_mst_b_chan_t_mst_b_chan_t_AxiUserWidth(mst_b_chan_t_mst_b_chan_t_AxiUserWidth), + .mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiDataWidth(mst_r_chan_t_mst_r_chan_t_AxiDataWidth), + .mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves(mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves), + .mst_r_chan_t_mst_r_chan_t_mst_r_chan_t_AxiUserWidth(mst_r_chan_t_mst_r_chan_t_AxiUserWidth), + .mst_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth(w_chan_t_w_chan_t_AxiDataWidth), + .mst_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth(w_chan_t_w_chan_t_AxiStrbWidth), + .mst_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth(w_chan_t_w_chan_t_AxiUserWidth), + .slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth(slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth), + .slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters(slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters), + .slv_ar_chan_t_slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth(slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth), + .slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth(slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth), + .slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters(slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters), + .slv_aw_chan_t_slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth(slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth), + .slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters(slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters), + .slv_b_chan_t_slv_b_chan_t_slv_b_chan_t_AxiUserWidth(slv_b_chan_t_slv_b_chan_t_AxiUserWidth), + .slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiDataWidth(slv_r_chan_t_slv_r_chan_t_AxiDataWidth), + .slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters(slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters), + .slv_r_chan_t_slv_r_chan_t_slv_r_chan_t_AxiUserWidth(slv_r_chan_t_slv_r_chan_t_AxiUserWidth), + .slv_w_chan_t_w_chan_t_w_chan_t_AxiDataWidth(w_chan_t_w_chan_t_AxiDataWidth), + .slv_w_chan_t_w_chan_t_w_chan_t_AxiStrbWidth(w_chan_t_w_chan_t_AxiStrbWidth), + .slv_w_chan_t_w_chan_t_w_chan_t_AxiUserWidth(w_chan_t_w_chan_t_AxiUserWidth), + .NoBus(32'd1), + .AxiIdWidthSlvPort(SlvAxiIDWidth), + .AxiIdWidthMstPort(MstAxiIDWidth) + ) i_id_prepend( + .pre_id_i(sv2v_cast_753CC(i)), + .slv_aw_chans_i(slv_reqs_i[(((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))) : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))))) : (((i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))) : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))))))) + (((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))))) >= (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)))) ? (((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))))) - (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)))) - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))))) + 1)) - 1)-:(((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))))) >= (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)))) ? (((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))))) - (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)))) - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))))) + 1)]), + .slv_aw_valids_i(slv_reqs_i[(i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))) : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - (1 + ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))))]), + .slv_aw_readies_o(slv_resps_o[(i * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) + (4 + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)))]), + .slv_w_chans_i(slv_reqs_i[(((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)) : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))) : (((i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)) : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))))) + (((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)) - ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))) + 1)) - 1)-:(((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))) >= (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)) ? (((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))) - (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 2)) - ((((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))) + 1)]), + .slv_w_valids_i(slv_reqs_i[(i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1) : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - (2 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))]), + .slv_w_readies_o(slv_resps_o[(i * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) + (2 + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)))]), + .slv_b_chans_o(slv_resps_o[(i * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0))-:((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)) >= (1 + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)) ? ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (1 + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)) - (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1)]), + .slv_b_valids_o(slv_resps_o[(i * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) + (1 + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)))]), + .slv_b_readies_i(slv_reqs_i[(i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1) : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - (1 + ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)))]), + .slv_ar_chans_i(slv_reqs_i[(((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1 : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1)) : (((i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1 : ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))) + (((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))) - 1)-:(((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1) >= 2 ? (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 0 : 3 - ((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth) + 1))]), + .slv_ar_valids_i(slv_reqs_i[(i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 1 : (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 0)]), + .slv_ar_readies_o(slv_resps_o[(i * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) + (3 + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)))]), + .slv_r_chans_o(slv_resps_o[(i * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) - 1)-:((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth]), + .slv_r_valids_o(slv_resps_o[(i * (((4 + ((slv_resp_t_slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth))) + ((((slv_resp_t_slv_resp_t_AxiIdWidthMasters + slv_resp_t_slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_slv_resp_t_AxiUserWidth) + 0)]), + .slv_r_readies_i(slv_reqs_i[(i * (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 35) + slv_req_t_slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_slv_req_t_AxiDataWidth + slv_req_t_slv_req_t_AxiStrbWidth) + 1) + slv_req_t_slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_slv_req_t_AxiIdWidthMasters + slv_req_t_slv_req_t_AxiAddrWidth) + 29) + slv_req_t_slv_req_t_AxiUserWidth)) + 1)]), + .mst_aw_chans_o(slv_aw_chans[i * (((mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth)+:((mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth) + 35) + mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth]), + .mst_aw_valids_o(slv_aw_valids[i]), + .mst_aw_readies_i(slv_aw_readies[i]), + .mst_w_chans_o(slv_w_chans[i * (((w_chan_t_w_chan_t_AxiDataWidth + w_chan_t_w_chan_t_AxiStrbWidth) + 1) + w_chan_t_w_chan_t_AxiUserWidth)+:((w_chan_t_w_chan_t_AxiDataWidth + w_chan_t_w_chan_t_AxiStrbWidth) + 1) + w_chan_t_w_chan_t_AxiUserWidth]), + .mst_w_valids_o(slv_w_valids[i]), + .mst_w_readies_i(slv_w_readies[i]), + .mst_b_chans_i(slv_b_chans[i * ((mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + mst_b_chan_t_mst_b_chan_t_AxiUserWidth)+:(mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + 2) + mst_b_chan_t_mst_b_chan_t_AxiUserWidth]), + .mst_b_valids_i(slv_b_valids[i]), + .mst_b_readies_o(slv_b_readies[i]), + .mst_ar_chans_o(slv_ar_chans[i * (((mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth)+:((mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves + mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth) + 29) + mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth]), + .mst_ar_valids_o(slv_ar_valids[i]), + .mst_ar_readies_i(slv_ar_readies[i]), + .mst_r_chans_i(slv_r_chans[i * (((mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + mst_r_chan_t_mst_r_chan_t_AxiUserWidth)+:((mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + mst_r_chan_t_mst_r_chan_t_AxiDataWidth) + 3) + mst_r_chan_t_mst_r_chan_t_AxiUserWidth]), + .mst_r_valids_i(slv_r_valids[i]), + .mst_r_readies_o(slv_r_readies[i]) + ); + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:186:5 + localparam [31:0] sv2v_uu_i_aw_arbiter_NumIn = NoSlvPorts; + localparam [31:0] sv2v_uu_i_aw_arbiter_IdxWidth = (sv2v_uu_i_aw_arbiter_NumIn > 32'd1 ? $unsigned($clog2(sv2v_uu_i_aw_arbiter_NumIn)) : 32'd1); + // removed localparam type sv2v_uu_i_aw_arbiter_rr_i + localparam [sv2v_uu_i_aw_arbiter_IdxWidth - 1:0] sv2v_uu_i_aw_arbiter_ext_rr_i_0 = 1'sb0; + rr_arb_tree_25334_B05A2 #( + .DataType_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth(mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth), + .DataType_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves(mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves), + .DataType_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth(mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth), + .NumIn(NoSlvPorts), + .AxiVldRdy(1'b1), + .LockIn(1'b1) + ) i_aw_arbiter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .rr_i(sv2v_uu_i_aw_arbiter_ext_rr_i_0), + .req_i(slv_aw_valids), + .gnt_o(slv_aw_readies), + .data_i(slv_aw_chans), + .gnt_i(aw_ready), + .req_o(aw_valid), + .data_o(mst_aw_chan), + .idx_o() + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:206:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:208:7 + lock_aw_valid_d = lock_aw_valid_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:209:7 + load_aw_lock = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:210:7 + w_fifo_push = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:211:7 + mst_aw_valid = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:212:7 + aw_ready = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:214:7 + if (lock_aw_valid_q) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:215:9 + mst_aw_valid = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:217:9 + if (mst_aw_ready) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:218:11 + aw_ready = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:219:11 + lock_aw_valid_d = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:220:11 + load_aw_lock = 1'b1; + end + end + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:223:9 + if (!w_fifo_full && aw_valid) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:224:11 + mst_aw_valid = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:225:11 + w_fifo_push = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:226:11 + if (mst_aw_ready) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:227:13 + aw_ready = 1'b1; + else begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:230:13 + lock_aw_valid_d = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:231:13 + load_aw_lock = 1'b1; + end + end + end + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:237:75 + always @(posedge clk_i or negedge rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:237:143 + if (!rst_ni) + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:237:211 + lock_aw_valid_q <= 1'sb0; + else + // Trace: macro expansion of FFLARN at ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:237:343 + lock_aw_valid_q <= (load_aw_lock ? lock_aw_valid_d : lock_aw_valid_q); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:239:5 + fifo_v3_7ABAC_FAAEB #( + .dtype_MstIdxBits(MstIdxBits), + .FALL_THROUGH(FallThrough), + .DEPTH(MaxWTrans) + ) i_w_fifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .testmode_i(test_i), + .full_o(w_fifo_full), + .empty_o(w_fifo_empty), + .usage_o(), + .data_i(mst_aw_chan[(mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves + (mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth + (29 + (mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth + 5)))) - ((mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves - 1) - SlvAxiIDWidth)+:MstIdxBits]), + .push_i(w_fifo_push), + .data_o(w_fifo_data), + .pop_i(w_fifo_pop) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:257:5 + spill_register_CA6B6_8B0C4 #( + .T_mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth(mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth), + .T_mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves(mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves), + .T_mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth(mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth), + .Bypass(~SpillAw) + ) i_aw_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(mst_aw_valid), + .ready_o(mst_aw_ready), + .data_i(mst_aw_chan), + .valid_o(mst_req_o[1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1)))]), + .ready_i(mst_resp_i[4 + (((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0))]), + .data_o(mst_req_o[(((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 35) + mst_req_t_mst_req_t_AxiUserWidth) + (1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1))))-:(((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 35) + mst_req_t_mst_req_t_AxiUserWidth) + (1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1))))) >= (1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 2)))) ? (((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 35) + mst_req_t_mst_req_t_AxiUserWidth) + (1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1))))) - (1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 2))))) + 1 : ((1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 2)))) - ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 35) + mst_req_t_mst_req_t_AxiUserWidth) + (1 + ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1)))))) + 1)]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:275:5 + assign mst_w_chan = slv_w_chans[w_fifo_data * (((w_chan_t_w_chan_t_AxiDataWidth + w_chan_t_w_chan_t_AxiStrbWidth) + 1) + w_chan_t_w_chan_t_AxiUserWidth)+:((w_chan_t_w_chan_t_AxiDataWidth + w_chan_t_w_chan_t_AxiStrbWidth) + 1) + w_chan_t_w_chan_t_AxiUserWidth]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:276:5 + always @(*) begin + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:278:7 + mst_w_valid = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:279:7 + slv_w_readies = 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:280:7 + w_fifo_pop = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:282:7 + if (!w_fifo_empty) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:284:9 + mst_w_valid = slv_w_valids[w_fifo_data]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:285:9 + slv_w_readies[w_fifo_data] = mst_w_ready; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:287:9 + w_fifo_pop = (slv_w_valids[w_fifo_data] & mst_w_ready) & mst_w_chan[w_chan_t_w_chan_t_AxiUserWidth + 0]; + end + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:291:5 + spill_register_2E020_83570 #( + .T_w_chan_t_w_chan_t_AxiDataWidth(w_chan_t_w_chan_t_AxiDataWidth), + .T_w_chan_t_w_chan_t_AxiStrbWidth(w_chan_t_w_chan_t_AxiStrbWidth), + .T_w_chan_t_w_chan_t_AxiUserWidth(w_chan_t_w_chan_t_AxiUserWidth), + .Bypass(~SpillW) + ) i_w_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(mst_w_valid), + .ready_o(mst_w_ready), + .data_i(mst_w_chan), + .valid_o(mst_req_o[2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1)]), + .ready_i(mst_resp_i[2 + (((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0))]), + .data_o(mst_req_o[(((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1))-:(((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1))) >= (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 2)) ? (((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1))) - (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 2))) + 1 : ((2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 2)) - ((((mst_req_t_mst_req_t_AxiDataWidth + mst_req_t_mst_req_t_AxiStrbWidth) + 1) + mst_req_t_mst_req_t_AxiUserWidth) + (2 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1)))) + 1)]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:309:5 + assign slv_b_chans = {NoSlvPorts {mst_b_chan}}; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:311:5 + assign switch_b_id = mst_b_chan[(mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves + (mst_b_chan_t_mst_b_chan_t_AxiUserWidth + 1)) - ((mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves - 1) - SlvAxiIDWidth)+:MstIdxBits]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:312:5 + assign slv_b_valids = (mst_b_valid ? 1 << switch_b_id : {NoSlvPorts {1'sb0}}); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:314:5 + spill_register_D0F05_A8961 #( + .T_mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves(mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves), + .T_mst_b_chan_t_mst_b_chan_t_AxiUserWidth(mst_b_chan_t_mst_b_chan_t_AxiUserWidth), + .Bypass(~SpillB) + ) i_b_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(mst_resp_i[1 + (((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0))]), + .ready_o(mst_req_o[1 + ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1)]), + .data_i(mst_resp_i[((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0)-:((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0)) >= (1 + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0)) ? ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0)) - (1 + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0)) - (((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0))) + 1)]), + .valid_o(mst_b_valid), + .ready_i(slv_b_readies[switch_b_id]), + .data_o(mst_b_chan) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:331:5 + localparam [31:0] sv2v_uu_i_ar_arbiter_NumIn = NoSlvPorts; + localparam [31:0] sv2v_uu_i_ar_arbiter_IdxWidth = (sv2v_uu_i_ar_arbiter_NumIn > 32'd1 ? $unsigned($clog2(sv2v_uu_i_ar_arbiter_NumIn)) : 32'd1); + // removed localparam type sv2v_uu_i_ar_arbiter_rr_i + localparam [sv2v_uu_i_ar_arbiter_IdxWidth - 1:0] sv2v_uu_i_ar_arbiter_ext_rr_i_0 = 1'sb0; + rr_arb_tree_1A97E_3F3CA #( + .DataType_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth(mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth), + .DataType_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves(mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves), + .DataType_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth(mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth), + .NumIn(NoSlvPorts), + .AxiVldRdy(1'b1), + .LockIn(1'b1) + ) i_ar_arbiter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .rr_i(sv2v_uu_i_ar_arbiter_ext_rr_i_0), + .req_i(slv_ar_valids), + .gnt_o(slv_ar_readies), + .data_i(slv_ar_chans), + .gnt_i(ar_ready), + .req_o(ar_valid), + .data_o(mst_ar_chan), + .idx_o() + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:350:5 + spill_register_D20CE_48F44 #( + .T_mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth(mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth), + .T_mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves(mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves), + .T_mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth(mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth), + .Bypass(~SpillAr) + ) i_ar_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(ar_valid), + .ready_o(ar_ready), + .data_i(mst_ar_chan), + .valid_o(mst_req_o[1]), + .ready_i(mst_resp_i[3 + (((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_mst_resp_t_AxiUserWidth) + ((((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0))]), + .data_o(mst_req_o[(((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1-:(((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1) >= 2 ? (((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 0 : 3 - ((((mst_req_t_mst_req_t_AxiIdWidthSlaves + mst_req_t_mst_req_t_AxiAddrWidth) + 29) + mst_req_t_mst_req_t_AxiUserWidth) + 1))]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:368:5 + assign slv_r_chans = {NoSlvPorts {mst_r_chan}}; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:370:5 + assign switch_r_id = mst_r_chan[(mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves + (mst_r_chan_t_mst_r_chan_t_AxiDataWidth + (mst_r_chan_t_mst_r_chan_t_AxiUserWidth + 2))) - ((mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves - 1) - SlvAxiIDWidth)+:MstIdxBits]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:371:5 + assign slv_r_valids = (mst_r_valid ? 1 << switch_r_id : {NoSlvPorts {1'sb0}}); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_mux.sv:373:5 + spill_register_BBFDC_153AC #( + .T_mst_r_chan_t_mst_r_chan_t_AxiDataWidth(mst_r_chan_t_mst_r_chan_t_AxiDataWidth), + .T_mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves(mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves), + .T_mst_r_chan_t_mst_r_chan_t_AxiUserWidth(mst_r_chan_t_mst_r_chan_t_AxiUserWidth), + .Bypass(~SpillR) + ) i_r_spill_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(mst_resp_i[(((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) + 0]), + .ready_o(mst_req_o[0]), + .data_i(mst_resp_i[(((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth) - 1-:((mst_resp_t_mst_resp_t_AxiIdWidthSlaves + mst_resp_t_mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_mst_resp_t_AxiUserWidth]), + .valid_o(mst_r_valid), + .ready_i(slv_r_readies[switch_r_id]), + .data_o(mst_r_chan) + ); + end + endgenerate + initial _sv2v_0 = 0; +endmodule +// removed module with interface ports: axi_mux_intf +// removed module with interface ports: axi_serializer_intf +module axi_err_slv_77614_E078A ( + clk_i, + rst_ni, + test_i, + slv_req_i, + slv_resp_o +); + // removed localparam type req_t_slv_req_t_AxiAddrWidth_type + // removed localparam type req_t_slv_req_t_AxiDataWidth_type + // removed localparam type req_t_slv_req_t_AxiIdWidthMasters_type + // removed localparam type req_t_slv_req_t_AxiStrbWidth_type + // removed localparam type req_t_slv_req_t_AxiUserWidth_type + parameter [31:0] req_t_slv_req_t_AxiAddrWidth = 0; + parameter [31:0] req_t_slv_req_t_AxiDataWidth = 0; + parameter [31:0] req_t_slv_req_t_AxiIdWidthMasters = 0; + parameter [31:0] req_t_slv_req_t_AxiStrbWidth = 0; + parameter [31:0] req_t_slv_req_t_AxiUserWidth = 0; + // removed localparam type resp_t_slv_resp_t_AxiDataWidth_type + // removed localparam type resp_t_slv_resp_t_AxiIdWidthMasters_type + // removed localparam type resp_t_slv_resp_t_AxiUserWidth_type + parameter [31:0] resp_t_slv_resp_t_AxiDataWidth = 0; + parameter [31:0] resp_t_slv_resp_t_AxiIdWidthMasters = 0; + parameter [31:0] resp_t_slv_resp_t_AxiUserWidth = 0; + reg _sv2v_0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:17:13 + parameter [31:0] AxiIdWidth = 0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:18:35 + // removed localparam type req_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:19:35 + // removed localparam type resp_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:20:13 + localparam axi_pkg_RESP_DECERR = 2'b11; + // removed localparam type axi_pkg_resp_t + parameter [1:0] Resp = axi_pkg_RESP_DECERR; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:21:13 + parameter [31:0] RespWidth = 32'd64; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:22:13 + parameter [RespWidth - 1:0] RespData = 64'hca11ab1ebadcab1e; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:23:13 + parameter [0:0] ATOPs = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:24:13 + parameter [31:0] MaxTrans = 1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:26:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:27:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:28:3 + input wire test_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:30:3 + input wire [(((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1:0] slv_req_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:31:3 + output wire [(((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth)) - 1:0] slv_resp_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:33:3 + // removed localparam type id_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:34:3 + // removed localparam type axi_pkg_len_t + // removed localparam type r_data_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:39:3 + wire [(((((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + 1) + (((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth)) + 2) + (((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth)) + 1:0] err_req; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:40:3 + reg [(((4 + ((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth)) + 1) + (((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth)) - 1:0] err_resp; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:42:3 + generate + if (ATOPs) begin : genblk1 + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:43:5 + axi_atop_filter_99C72_35AFC #( + .req_t_req_t_slv_req_t_AxiAddrWidth(req_t_slv_req_t_AxiAddrWidth), + .req_t_req_t_slv_req_t_AxiDataWidth(req_t_slv_req_t_AxiDataWidth), + .req_t_req_t_slv_req_t_AxiIdWidthMasters(req_t_slv_req_t_AxiIdWidthMasters), + .req_t_req_t_slv_req_t_AxiStrbWidth(req_t_slv_req_t_AxiStrbWidth), + .req_t_req_t_slv_req_t_AxiUserWidth(req_t_slv_req_t_AxiUserWidth), + .resp_t_resp_t_slv_resp_t_AxiDataWidth(resp_t_slv_resp_t_AxiDataWidth), + .resp_t_resp_t_slv_resp_t_AxiIdWidthMasters(resp_t_slv_resp_t_AxiIdWidthMasters), + .resp_t_resp_t_slv_resp_t_AxiUserWidth(resp_t_slv_resp_t_AxiUserWidth), + .AxiIdWidth(AxiIdWidth), + .AxiMaxWriteTxns(MaxTrans) + ) i_atop_filter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .slv_req_i(slv_req_i), + .slv_resp_o(slv_resp_o), + .mst_req_o(err_req), + .mst_resp_i(err_resp) + ); + end + else begin : genblk1 + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:57:5 + assign err_req = slv_req_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:58:5 + assign slv_resp_o = err_resp; + end + endgenerate + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:62:3 + wire w_fifo_full; + wire w_fifo_empty; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:63:3 + wire w_fifo_push; + reg w_fifo_pop; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:64:3 + wire [AxiIdWidth - 1:0] w_fifo_data; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:66:3 + wire b_fifo_full; + wire b_fifo_empty; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:67:3 + reg b_fifo_push; + reg b_fifo_pop; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:68:3 + wire [AxiIdWidth - 1:0] b_fifo_data; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:70:3 + wire [AxiIdWidth + 7:0] r_fifo_inp; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:71:3 + wire r_fifo_full; + wire r_fifo_empty; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:72:3 + wire r_fifo_push; + reg r_fifo_pop; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:73:3 + wire [AxiIdWidth + 7:0] r_fifo_data; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:75:3 + reg r_cnt_clear; + reg r_cnt_en; + reg r_cnt_load; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:76:3 + wire [7:0] r_current_beat; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:78:3 + reg r_busy_d; + reg r_busy_q; + reg r_busy_load; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:84:3 + assign w_fifo_push = err_req[1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)))] & ~w_fifo_full; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:85:3 + wire [1:1] sv2v_tmp_9AECB; + assign sv2v_tmp_9AECB = ~w_fifo_full; + always @(*) err_resp[4 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))] = sv2v_tmp_9AECB; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:87:3 + fifo_v3_F9D8C_B67E5 #( + .dtype_AxiIdWidth(AxiIdWidth), + .FALL_THROUGH(1'b1), + .DEPTH(MaxTrans) + ) i_w_fifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .testmode_i(test_i), + .full_o(w_fifo_full), + .empty_o(w_fifo_empty), + .usage_o(), + .data_i(err_req[((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) + (1 + ((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))))) - (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 35) + req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_slv_req_t_AxiUserWidth + 5)))))-:((req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_slv_req_t_AxiUserWidth + 5)))) >= (req_t_slv_req_t_AxiAddrWidth + (35 + (req_t_slv_req_t_AxiUserWidth + 0))) ? ((req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_slv_req_t_AxiUserWidth + 5)))) - (req_t_slv_req_t_AxiAddrWidth + (35 + (req_t_slv_req_t_AxiUserWidth + 0)))) + 1 : ((req_t_slv_req_t_AxiAddrWidth + (35 + (req_t_slv_req_t_AxiUserWidth + 0))) - (req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_slv_req_t_AxiUserWidth + 5))))) + 1)]), + .push_i(w_fifo_push), + .data_o(w_fifo_data), + .pop_i(w_fifo_pop) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:105:3 + always @(*) begin : proc_w_channel + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:106:5 + err_resp[2 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:107:5 + w_fifo_pop = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:108:5 + b_fifo_push = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:109:5 + if (!w_fifo_empty && !b_fifo_full) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:111:7 + err_resp[2 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:113:7 + if (err_req[2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)] && err_req[((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) + (2 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1))) - (((((req_t_slv_req_t_AxiDataWidth + req_t_slv_req_t_AxiStrbWidth) + 1) + req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_slv_req_t_AxiUserWidth + 0))]) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:114:9 + w_fifo_pop = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:115:9 + b_fifo_push = 1'b1; + end + end + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:120:3 + fifo_v3_F9D8C_B67E5 #( + .dtype_AxiIdWidth(AxiIdWidth), + .FALL_THROUGH(1'b0), + .DEPTH($unsigned(2)) + ) i_b_fifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .testmode_i(test_i), + .full_o(b_fifo_full), + .empty_o(b_fifo_empty), + .usage_o(), + .data_i(w_fifo_data), + .push_i(b_fifo_push), + .data_o(b_fifo_data), + .pop_i(b_fifo_pop) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:138:3 + always @(*) begin : proc_b_channel + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:139:5 + b_fifo_pop = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:140:5 + err_resp[((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)-:((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) >= (1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) ? ((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - (1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1 : ((1 + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))) + 1)] = 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:141:5 + err_resp[(((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - ((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiUserWidth + 1)))-:((resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiUserWidth + 1)) >= (2 + (resp_t_slv_resp_t_AxiUserWidth + 0)) ? ((resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiUserWidth + 1)) - (2 + (resp_t_slv_resp_t_AxiUserWidth + 0))) + 1 : ((2 + (resp_t_slv_resp_t_AxiUserWidth + 0)) - (resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiUserWidth + 1))) + 1)] = b_fifo_data; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:142:5 + err_resp[(((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0)) - ((((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_slv_resp_t_AxiUserWidth + 1))-:((resp_t_slv_resp_t_AxiUserWidth + 1) >= (resp_t_slv_resp_t_AxiUserWidth + 0) ? ((resp_t_slv_resp_t_AxiUserWidth + 1) - (resp_t_slv_resp_t_AxiUserWidth + 0)) + 1 : ((resp_t_slv_resp_t_AxiUserWidth + 0) - (resp_t_slv_resp_t_AxiUserWidth + 1)) + 1)] = Resp; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:143:5 + err_resp[1 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:144:5 + if (!b_fifo_empty) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:145:7 + err_resp[1 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:147:7 + b_fifo_pop = err_req[1 + ((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1)]; + end + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:155:3 + assign r_fifo_push = err_req[1] & ~r_fifo_full; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:156:3 + wire [1:1] sv2v_tmp_A40F9; + assign sv2v_tmp_A40F9 = ~r_fifo_full; + always @(*) err_resp[3 + (((resp_t_slv_resp_t_AxiIdWidthMasters + 2) + resp_t_slv_resp_t_AxiUserWidth) + ((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0))] = sv2v_tmp_A40F9; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:159:3 + assign r_fifo_inp[AxiIdWidth + 7-:((AxiIdWidth + 7) >= 8 ? AxiIdWidth + 0 : 9 - (AxiIdWidth + 7))] = err_req[((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) - (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) - 1) - (req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (21 + (req_t_slv_req_t_AxiUserWidth + 7)))))-:((req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (21 + (req_t_slv_req_t_AxiUserWidth + 7)))) >= (req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_slv_req_t_AxiUserWidth + 0))) ? ((req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (21 + (req_t_slv_req_t_AxiUserWidth + 7)))) - (req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_slv_req_t_AxiUserWidth + 0)))) + 1 : ((req_t_slv_req_t_AxiAddrWidth + (29 + (req_t_slv_req_t_AxiUserWidth + 0))) - (req_t_slv_req_t_AxiIdWidthMasters + (req_t_slv_req_t_AxiAddrWidth + (21 + (req_t_slv_req_t_AxiUserWidth + 7))))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:160:3 + assign r_fifo_inp[7-:8] = err_req[((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) + 1) - (((((req_t_slv_req_t_AxiIdWidthMasters + req_t_slv_req_t_AxiAddrWidth) + 29) + req_t_slv_req_t_AxiUserWidth) - 1) - (21 + (req_t_slv_req_t_AxiUserWidth + 7)))-:((21 + (req_t_slv_req_t_AxiUserWidth + 7)) >= (21 + (req_t_slv_req_t_AxiUserWidth + 0)) ? ((21 + (req_t_slv_req_t_AxiUserWidth + 7)) - (21 + (req_t_slv_req_t_AxiUserWidth + 0))) + 1 : ((21 + (req_t_slv_req_t_AxiUserWidth + 0)) - (21 + (req_t_slv_req_t_AxiUserWidth + 7))) + 1)]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:162:3 + fifo_v3_0EFFB_75D82 #( + .dtype_AxiIdWidth(AxiIdWidth), + .FALL_THROUGH(1'b0), + .DEPTH(MaxTrans) + ) i_r_fifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(1'b0), + .testmode_i(test_i), + .full_o(r_fifo_full), + .empty_o(r_fifo_empty), + .usage_o(), + .data_i(r_fifo_inp), + .push_i(r_fifo_push), + .data_o(r_fifo_data), + .pop_i(r_fifo_pop) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:180:3 + always @(*) begin : proc_r_channel + if (_sv2v_0) + ; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:182:5 + r_busy_d = r_busy_q; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:183:5 + r_busy_load = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:185:5 + r_fifo_pop = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:187:5 + r_cnt_clear = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:188:5 + r_cnt_en = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:189:5 + r_cnt_load = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:191:5 + err_resp[(((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1-:((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth] = 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:192:5 + err_resp[((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2))))-:((resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2))) >= (resp_t_slv_resp_t_AxiDataWidth + (3 + (resp_t_slv_resp_t_AxiUserWidth + 0))) ? ((resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2))) - (resp_t_slv_resp_t_AxiDataWidth + (3 + (resp_t_slv_resp_t_AxiUserWidth + 0)))) + 1 : ((resp_t_slv_resp_t_AxiDataWidth + (3 + (resp_t_slv_resp_t_AxiUserWidth + 0))) - (resp_t_slv_resp_t_AxiIdWidthMasters + (resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2)))) + 1)] = r_fifo_data[AxiIdWidth + 7-:((AxiIdWidth + 7) >= 8 ? AxiIdWidth + 0 : 9 - (AxiIdWidth + 7))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:193:5 + err_resp[((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2)))-:((resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2)) >= (3 + (resp_t_slv_resp_t_AxiUserWidth + 0)) ? ((resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2)) - (3 + (resp_t_slv_resp_t_AxiUserWidth + 0))) + 1 : ((3 + (resp_t_slv_resp_t_AxiUserWidth + 0)) - (resp_t_slv_resp_t_AxiDataWidth + (resp_t_slv_resp_t_AxiUserWidth + 2))) + 1)] = RespData; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:194:5 + err_resp[((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_slv_resp_t_AxiUserWidth + 2))-:((resp_t_slv_resp_t_AxiUserWidth + 2) >= (1 + (resp_t_slv_resp_t_AxiUserWidth + 0)) ? ((resp_t_slv_resp_t_AxiUserWidth + 2) - (1 + (resp_t_slv_resp_t_AxiUserWidth + 0))) + 1 : ((1 + (resp_t_slv_resp_t_AxiUserWidth + 0)) - (resp_t_slv_resp_t_AxiUserWidth + 2)) + 1)] = Resp; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:195:5 + err_resp[(((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0] = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:197:5 + if (r_busy_q) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:198:7 + err_resp[(((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) + 0] = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:199:7 + err_resp[((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (((((resp_t_slv_resp_t_AxiIdWidthMasters + resp_t_slv_resp_t_AxiDataWidth) + 3) + resp_t_slv_resp_t_AxiUserWidth) - 1) - (resp_t_slv_resp_t_AxiUserWidth + 0))] = r_current_beat == {8 {1'sb0}}; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:201:7 + if (err_req[0]) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:202:9 + r_cnt_en = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:203:9 + if (r_current_beat == {8 {1'sb0}}) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:204:11 + r_busy_d = 1'b0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:205:11 + r_busy_load = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:206:11 + r_cnt_clear = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:207:11 + r_fifo_pop = 1'b1; + end + end + end + else + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:212:7 + if (!r_fifo_empty) begin + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:213:9 + r_busy_d = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:214:9 + r_busy_load = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:215:9 + r_cnt_load = 1'b1; + end + end + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:220:3 + always @(posedge clk_i or negedge rst_ni) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:221:5 + if (!rst_ni) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:222:7 + r_busy_q <= 1'sb0; + else if (r_busy_load) + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:224:7 + r_busy_q <= r_busy_d; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_err_slv.sv:228:3 + counter #(.WIDTH(8)) i_r_counter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clear_i(r_cnt_clear), + .en_i(r_cnt_en), + .load_i(r_cnt_load), + .down_i(1'b1), + .d_i(r_fifo_data[7-:8]), + .q_o(r_current_beat), + .overflow_o() + ); + initial _sv2v_0 = 0; +endmodule +// removed module with interface ports: axi_dw_converter_intf +// removed module with interface ports: axi_multicut_intf +// removed module with interface ports: axi_lite_multicut_intf +// removed module with interface ports: axi_to_axi_lite_intf +module axi_xbar_69337_92F22 ( + clk_i, + rst_ni, + test_i, + slv_ports_req_i, + slv_ports_resp_o, + mst_ports_req_o, + mst_ports_resp_i, + addr_map_i, + en_default_mst_port_i, + default_mst_port_i +); + // removed localparam type mst_ar_chan_t_AxiAddrWidth_type + // removed localparam type mst_ar_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_ar_chan_t_AxiUserWidth_type + parameter [31:0] mst_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] mst_ar_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_ar_chan_t_AxiUserWidth = 0; + // removed localparam type mst_aw_chan_t_AxiAddrWidth_type + // removed localparam type mst_aw_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_aw_chan_t_AxiUserWidth_type + parameter [31:0] mst_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] mst_aw_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_aw_chan_t_AxiUserWidth = 0; + // removed localparam type mst_b_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_b_chan_t_AxiUserWidth_type + parameter [31:0] mst_b_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_b_chan_t_AxiUserWidth = 0; + // removed localparam type mst_r_chan_t_AxiDataWidth_type + // removed localparam type mst_r_chan_t_AxiIdWidthSlaves_type + // removed localparam type mst_r_chan_t_AxiUserWidth_type + parameter [31:0] mst_r_chan_t_AxiDataWidth = 0; + parameter [31:0] mst_r_chan_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_r_chan_t_AxiUserWidth = 0; + // removed localparam type mst_req_t_AxiAddrWidth_type + // removed localparam type mst_req_t_AxiDataWidth_type + // removed localparam type mst_req_t_AxiIdWidthSlaves_type + // removed localparam type mst_req_t_AxiStrbWidth_type + // removed localparam type mst_req_t_AxiUserWidth_type + parameter [31:0] mst_req_t_AxiAddrWidth = 0; + parameter [31:0] mst_req_t_AxiDataWidth = 0; + parameter [31:0] mst_req_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_req_t_AxiStrbWidth = 0; + parameter [31:0] mst_req_t_AxiUserWidth = 0; + // removed localparam type mst_resp_t_AxiDataWidth_type + // removed localparam type mst_resp_t_AxiIdWidthSlaves_type + // removed localparam type mst_resp_t_AxiUserWidth_type + parameter [31:0] mst_resp_t_AxiDataWidth = 0; + parameter [31:0] mst_resp_t_AxiIdWidthSlaves = 0; + parameter [31:0] mst_resp_t_AxiUserWidth = 0; + // removed localparam type slv_ar_chan_t_AxiAddrWidth_type + // removed localparam type slv_ar_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_ar_chan_t_AxiUserWidth_type + parameter [31:0] slv_ar_chan_t_AxiAddrWidth = 0; + parameter [31:0] slv_ar_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_ar_chan_t_AxiUserWidth = 0; + // removed localparam type slv_aw_chan_t_AxiAddrWidth_type + // removed localparam type slv_aw_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_aw_chan_t_AxiUserWidth_type + parameter [31:0] slv_aw_chan_t_AxiAddrWidth = 0; + parameter [31:0] slv_aw_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_aw_chan_t_AxiUserWidth = 0; + // removed localparam type slv_b_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_b_chan_t_AxiUserWidth_type + parameter [31:0] slv_b_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_b_chan_t_AxiUserWidth = 0; + // removed localparam type slv_r_chan_t_AxiDataWidth_type + // removed localparam type slv_r_chan_t_AxiIdWidthMasters_type + // removed localparam type slv_r_chan_t_AxiUserWidth_type + parameter [31:0] slv_r_chan_t_AxiDataWidth = 0; + parameter [31:0] slv_r_chan_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_r_chan_t_AxiUserWidth = 0; + // removed localparam type slv_req_t_AxiAddrWidth_type + // removed localparam type slv_req_t_AxiDataWidth_type + // removed localparam type slv_req_t_AxiIdWidthMasters_type + // removed localparam type slv_req_t_AxiStrbWidth_type + // removed localparam type slv_req_t_AxiUserWidth_type + parameter [31:0] slv_req_t_AxiAddrWidth = 0; + parameter [31:0] slv_req_t_AxiDataWidth = 0; + parameter [31:0] slv_req_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_req_t_AxiStrbWidth = 0; + parameter [31:0] slv_req_t_AxiUserWidth = 0; + // removed localparam type slv_resp_t_AxiDataWidth_type + // removed localparam type slv_resp_t_AxiIdWidthMasters_type + // removed localparam type slv_resp_t_AxiUserWidth_type + parameter [31:0] slv_resp_t_AxiDataWidth = 0; + parameter [31:0] slv_resp_t_AxiIdWidthMasters = 0; + parameter [31:0] slv_resp_t_AxiUserWidth = 0; + // removed localparam type w_chan_t_AxiDataWidth_type + // removed localparam type w_chan_t_AxiStrbWidth_type + // removed localparam type w_chan_t_AxiUserWidth_type + parameter [31:0] w_chan_t_AxiDataWidth = 0; + parameter [31:0] w_chan_t_AxiStrbWidth = 0; + parameter [31:0] w_chan_t_AxiUserWidth = 0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:16:13 + localparam [9:0] axi_pkg_DemuxAr = 64; + localparam [9:0] axi_pkg_DemuxAw = 512; + localparam [9:0] axi_pkg_DemuxB = 128; + localparam [9:0] axi_pkg_DemuxR = 32; + localparam [9:0] axi_pkg_DemuxW = 256; + localparam [9:0] axi_pkg_MuxAr = 2; + localparam [9:0] axi_pkg_MuxAw = 16; + localparam [9:0] axi_pkg_MuxB = 4; + localparam [9:0] axi_pkg_MuxR = 1; + localparam [9:0] axi_pkg_MuxW = 8; + // removed localparam type axi_pkg_xbar_latency_e + // removed localparam type axi_pkg_xbar_cfg_t + parameter [298:0] Cfg = 1'sb0; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:17:13 + parameter [0:0] ATOPs = 1'b1; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:18:18 + // removed localparam type slv_aw_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:19:18 + // removed localparam type mst_aw_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:20:18 + // removed localparam type w_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:21:18 + // removed localparam type slv_b_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:22:18 + // removed localparam type mst_b_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:23:18 + // removed localparam type slv_ar_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:24:18 + // removed localparam type mst_ar_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:25:18 + // removed localparam type slv_r_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:26:18 + // removed localparam type mst_r_chan_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:27:18 + // removed localparam type slv_req_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:28:18 + // removed localparam type slv_resp_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:29:18 + // removed localparam type mst_req_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:30:18 + // removed localparam type mst_resp_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:31:18 + // removed localparam type axi_pkg_xbar_rule_64_t + // removed localparam type rule_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:33:3 + input wire clk_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:34:3 + input wire rst_ni; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:35:3 + input wire test_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:36:3 + input wire [(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (Cfg[298-:32] * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2)) - 1 : (Cfg[298-:32] * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 0)):(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)] slv_ports_req_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:37:3 + output wire [(Cfg[298-:32] * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))) - 1:0] slv_ports_resp_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:38:3 + output wire [(((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1) >= 0 ? (Cfg[266-:32] * ((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 2)) - 1 : (Cfg[266-:32] * (1 - ((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1))) + ((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 0)):(((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1)] mst_ports_req_o; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:39:3 + input wire [(Cfg[266-:32] * (((4 + ((mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_AxiUserWidth)) + 1) + (((mst_resp_t_AxiIdWidthSlaves + mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_AxiUserWidth))) - 1:0] mst_ports_resp_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:40:3 + input wire [(Cfg[31-:32] * 96) - 1:0] addr_map_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:41:3 + input wire [Cfg[298-:32] - 1:0] en_default_mst_port_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:42:3 + input wire [(Cfg[298-:32] * $clog2(Cfg[266-:32])) - 1:0] default_mst_port_i; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:45:3 + // removed localparam type addr_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:47:3 + // removed localparam type mst_port_idx_t + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:50:3 + wire [((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? ((((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) - (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0)) + 1) * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2)) + (((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2)) - 1) : ((((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) - (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0)) + 1) * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + ((((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + ((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))) - 1)) : (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? ((((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1))) + 1) * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2)) + (((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2)) - 1) : ((((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1))) + 1) * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + ((((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + ((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))) - 1))):((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2) : ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + ((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))) : (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2) : ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + ((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))))] slv_reqs; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:51:3 + wire [((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? ((((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) - (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0)) + 1) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))) + (((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))) - 1) : ((((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1))) + 1) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))) + (((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))) - 1)):((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)) : (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)))] slv_resps; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:54:3 + localparam [31:0] cfg_NoMstPorts = Cfg[266-:32]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:57:3 + wire [(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? ((Cfg[266-:32] * Cfg[298-:32]) * ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2)) - 1 : ((Cfg[266-:32] * Cfg[298-:32]) * (1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 0)):(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)] mst_reqs; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:58:3 + wire [((Cfg[266-:32] * Cfg[298-:32]) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))) - 1:0] mst_resps; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:60:3 + genvar _gv_i_113; + localparam axi_pkg_RESP_DECERR = 2'b11; + function automatic [$clog2(Cfg[266-:32] + 1) - 1:0] sv2v_cast_B9918; + input reg [$clog2(Cfg[266-:32] + 1) - 1:0] inp; + sv2v_cast_B9918 = inp; + endfunction + generate + for (_gv_i_113 = 0; _gv_i_113 < Cfg[298-:32]; _gv_i_113 = _gv_i_113 + 1) begin : gen_slv_port_demux + localparam i = _gv_i_113; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:61:5 + wire [$clog2(Cfg[266-:32]) - 1:0] dec_aw; + wire [$clog2(Cfg[266-:32]) - 1:0] dec_ar; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:62:5 + wire [$clog2(Cfg[266-:32] + 1) - 1:0] slv_aw_select; + wire [$clog2(Cfg[266-:32] + 1) - 1:0] slv_ar_select; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:63:5 + wire dec_aw_valid; + wire dec_aw_error; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:64:5 + wire dec_ar_valid; + wire dec_ar_error; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:66:5 + addr_decode_727A6_BF551 #( + .addr_t_Cfg(Cfg), + .NoIndices(Cfg[266-:32]), + .NoRules(Cfg[31-:32]) + ) i_axi_aw_decode( + .addr_i(slv_ports_req_i[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1))))) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5)))) : ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1))))) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5)))))) : (((i * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1))))) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5)))) : ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + (1 + ((((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth) + (2 + ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1))))) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5))))))) + ((slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5))) >= (35 + (slv_req_t_AxiUserWidth + 0)) ? ((slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5))) - (35 + (slv_req_t_AxiUserWidth + 0))) + 1 : ((35 + (slv_req_t_AxiUserWidth + 0)) - (slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5)))) + 1)) - 1)-:((slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5))) >= (35 + (slv_req_t_AxiUserWidth + 0)) ? ((slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5))) - (35 + (slv_req_t_AxiUserWidth + 0))) + 1 : ((35 + (slv_req_t_AxiUserWidth + 0)) - (slv_req_t_AxiAddrWidth + (29 + (slv_req_t_AxiUserWidth + 5)))) + 1)]), + .addr_map_i(addr_map_i), + .idx_o(dec_aw), + .dec_valid_o(dec_aw_valid), + .dec_error_o(dec_aw_error), + .en_default_idx_i(en_default_mst_port_i[i]), + .default_idx_i(default_mst_port_i[i * $clog2(Cfg[266-:32])+:$clog2(Cfg[266-:32])]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:81:5 + addr_decode_727A6_BF551 #( + .addr_t_Cfg(Cfg), + .NoIndices(Cfg[266-:32]), + .NoRules(Cfg[31-:32]) + ) i_axi_ar_decode( + .addr_i(slv_ports_req_i[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (i * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7)))) : ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7)))))) : (((i * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))) + (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? ((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7)))) : ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) + 1) - (((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth) - 1) - (slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7))))))) + ((slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7))) >= (29 + (slv_req_t_AxiUserWidth + 0)) ? ((slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7))) - (29 + (slv_req_t_AxiUserWidth + 0))) + 1 : ((29 + (slv_req_t_AxiUserWidth + 0)) - (slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7)))) + 1)) - 1)-:((slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7))) >= (29 + (slv_req_t_AxiUserWidth + 0)) ? ((slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7))) - (29 + (slv_req_t_AxiUserWidth + 0))) + 1 : ((29 + (slv_req_t_AxiUserWidth + 0)) - (slv_req_t_AxiAddrWidth + (21 + (slv_req_t_AxiUserWidth + 7)))) + 1)]), + .addr_map_i(addr_map_i), + .idx_o(dec_ar), + .dec_valid_o(dec_ar_valid), + .dec_error_o(dec_ar_error), + .en_default_idx_i(en_default_mst_port_i[i]), + .default_idx_i(default_mst_port_i[i * $clog2(Cfg[266-:32])+:$clog2(Cfg[266-:32])]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:96:5 + assign slv_aw_select = (dec_aw_error ? sv2v_cast_B9918(Cfg[266-:32]) : sv2v_cast_B9918(dec_aw)); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:98:5 + assign slv_ar_select = (dec_ar_error ? sv2v_cast_B9918(Cfg[266-:32]) : sv2v_cast_B9918(dec_ar)); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:129:5 + axi_demux_3FE59_D0B23 #( + .ar_chan_t_slv_ar_chan_t_AxiAddrWidth(slv_ar_chan_t_AxiAddrWidth), + .ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters(slv_ar_chan_t_AxiIdWidthMasters), + .ar_chan_t_slv_ar_chan_t_AxiUserWidth(slv_ar_chan_t_AxiUserWidth), + .aw_chan_t_slv_aw_chan_t_AxiAddrWidth(slv_aw_chan_t_AxiAddrWidth), + .aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters(slv_aw_chan_t_AxiIdWidthMasters), + .aw_chan_t_slv_aw_chan_t_AxiUserWidth(slv_aw_chan_t_AxiUserWidth), + .b_chan_t_slv_b_chan_t_AxiIdWidthMasters(slv_b_chan_t_AxiIdWidthMasters), + .b_chan_t_slv_b_chan_t_AxiUserWidth(slv_b_chan_t_AxiUserWidth), + .r_chan_t_slv_r_chan_t_AxiDataWidth(slv_r_chan_t_AxiDataWidth), + .r_chan_t_slv_r_chan_t_AxiIdWidthMasters(slv_r_chan_t_AxiIdWidthMasters), + .r_chan_t_slv_r_chan_t_AxiUserWidth(slv_r_chan_t_AxiUserWidth), + .req_t_slv_req_t_AxiAddrWidth(slv_req_t_AxiAddrWidth), + .req_t_slv_req_t_AxiDataWidth(slv_req_t_AxiDataWidth), + .req_t_slv_req_t_AxiIdWidthMasters(slv_req_t_AxiIdWidthMasters), + .req_t_slv_req_t_AxiStrbWidth(slv_req_t_AxiStrbWidth), + .req_t_slv_req_t_AxiUserWidth(slv_req_t_AxiUserWidth), + .resp_t_slv_resp_t_AxiDataWidth(slv_resp_t_AxiDataWidth), + .resp_t_slv_resp_t_AxiIdWidthMasters(slv_resp_t_AxiIdWidthMasters), + .resp_t_slv_resp_t_AxiUserWidth(slv_resp_t_AxiUserWidth), + .w_chan_t_w_chan_t_AxiDataWidth(w_chan_t_AxiDataWidth), + .w_chan_t_w_chan_t_AxiStrbWidth(w_chan_t_AxiStrbWidth), + .w_chan_t_w_chan_t_AxiUserWidth(w_chan_t_AxiUserWidth), + .AxiIdWidth(Cfg[159-:32]), + .NoMstPorts(Cfg[266-:32] + 1), + .MaxTrans(Cfg[234-:32]), + .AxiLookBits(Cfg[127-:32]), + .FallThrough(Cfg[170]), + .SpillAw(Cfg[169]), + .SpillW(Cfg[168]), + .SpillB(Cfg[167]), + .SpillAr(Cfg[166]), + .SpillR(Cfg[165]) + ) i_axi_demux( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_i(test_i), + .slv_req_i(slv_ports_req_i[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + (i * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))+:(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))]), + .slv_aw_select_i(slv_aw_select), + .slv_ar_select_i(slv_ar_select), + .slv_resp_o(slv_ports_resp_o[i * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))+:((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)]), + .mst_reqs_o(slv_reqs[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + ((((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)) * ((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? ((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) : ((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]))) + ((Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]) - 1)) : (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) : ((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]))) + ((Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]) - 1)) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)))))+:(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)) * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])]), + .mst_resps_i(slv_resps[(((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)) * ((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? ((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) : ((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]))) + ((Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]) - 1)) : (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) : ((Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32]) + (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]))) + ((Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32]) - 1)) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1))))+:(((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)) * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])]) + ); + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:159:5 + axi_err_slv_77614_E078A #( + .req_t_slv_req_t_AxiAddrWidth(slv_req_t_AxiAddrWidth), + .req_t_slv_req_t_AxiDataWidth(slv_req_t_AxiDataWidth), + .req_t_slv_req_t_AxiIdWidthMasters(slv_req_t_AxiIdWidthMasters), + .req_t_slv_req_t_AxiStrbWidth(slv_req_t_AxiStrbWidth), + .req_t_slv_req_t_AxiUserWidth(slv_req_t_AxiUserWidth), + .resp_t_slv_resp_t_AxiDataWidth(slv_resp_t_AxiDataWidth), + .resp_t_slv_resp_t_AxiIdWidthMasters(slv_resp_t_AxiIdWidthMasters), + .resp_t_slv_resp_t_AxiUserWidth(slv_resp_t_AxiUserWidth), + .AxiIdWidth(Cfg[159-:32]), + .Resp(axi_pkg_RESP_DECERR), + .ATOPs(ATOPs), + .MaxTrans(4) + ) i_axi_err_slv( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_i(test_i), + .slv_req_i(slv_reqs[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + (((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? Cfg[266-:32] : Cfg[266-:32] - Cfg[266-:32]) : (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (((i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? Cfg[266-:32] : Cfg[266-:32] - Cfg[266-:32])) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)))) * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))+:(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))]), + .slv_resp_o(slv_resps[((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? cfg_NoMstPorts : Cfg[266-:32] - cfg_NoMstPorts) : (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (((i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? cfg_NoMstPorts : Cfg[266-:32] - cfg_NoMstPorts)) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)))) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))+:((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)]) + ); + end + endgenerate + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:179:3 + genvar _gv_i_114; + generate + for (_gv_i_114 = 0; _gv_i_114 < Cfg[298-:32]; _gv_i_114 = _gv_i_114 + 1) begin : gen_xbar_slv_cross + localparam i = _gv_i_114; + genvar _gv_j_19; + for (_gv_j_19 = 0; _gv_j_19 < Cfg[266-:32]; _gv_j_19 = _gv_j_19 + 1) begin : gen_xbar_mst_cross + localparam j = _gv_j_19; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:181:7 + assign mst_reqs[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + (((j * Cfg[298-:32]) + i) * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))+:(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))] = slv_reqs[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + (((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? j : Cfg[266-:32] - j) : (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (((i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? j : Cfg[266-:32] - j)) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)))) * (((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)))+:(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1))]; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:182:7 + assign slv_resps[((Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)) >= (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) ? (i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? j : Cfg[266-:32] - j) : (Cfg[266-:32] >= 0 ? 0 : Cfg[266-:32] + 0) - (((i * (Cfg[266-:32] >= 0 ? Cfg[266-:32] + 1 : 1 - Cfg[266-:32])) + (Cfg[266-:32] >= 0 ? j : Cfg[266-:32] - j)) - (Cfg[266-:32] >= 0 ? (Cfg[298-:32] * (Cfg[266-:32] + 1)) - 1 : (Cfg[298-:32] * (1 - Cfg[266-:32])) + (Cfg[266-:32] - 1)))) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))+:((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)] = mst_resps[((j * Cfg[298-:32]) + i) * (((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth))+:((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)]; + end + end + endgenerate + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:186:3 + genvar _gv_i_115; + generate + for (_gv_i_115 = 0; _gv_i_115 < Cfg[266-:32]; _gv_i_115 = _gv_i_115 + 1) begin : gen_mst_port_mux + localparam i = _gv_i_115; + // Trace: ./src/pulp-platform.org__axi_0.25.0/src/axi_xbar.sv:187:5 + axi_mux_5C4FF_DA91C #( + .mst_ar_chan_t_mst_ar_chan_t_AxiAddrWidth(mst_ar_chan_t_AxiAddrWidth), + .mst_ar_chan_t_mst_ar_chan_t_AxiIdWidthSlaves(mst_ar_chan_t_AxiIdWidthSlaves), + .mst_ar_chan_t_mst_ar_chan_t_AxiUserWidth(mst_ar_chan_t_AxiUserWidth), + .mst_aw_chan_t_mst_aw_chan_t_AxiAddrWidth(mst_aw_chan_t_AxiAddrWidth), + .mst_aw_chan_t_mst_aw_chan_t_AxiIdWidthSlaves(mst_aw_chan_t_AxiIdWidthSlaves), + .mst_aw_chan_t_mst_aw_chan_t_AxiUserWidth(mst_aw_chan_t_AxiUserWidth), + .mst_b_chan_t_mst_b_chan_t_AxiIdWidthSlaves(mst_b_chan_t_AxiIdWidthSlaves), + .mst_b_chan_t_mst_b_chan_t_AxiUserWidth(mst_b_chan_t_AxiUserWidth), + .mst_r_chan_t_mst_r_chan_t_AxiDataWidth(mst_r_chan_t_AxiDataWidth), + .mst_r_chan_t_mst_r_chan_t_AxiIdWidthSlaves(mst_r_chan_t_AxiIdWidthSlaves), + .mst_r_chan_t_mst_r_chan_t_AxiUserWidth(mst_r_chan_t_AxiUserWidth), + .mst_req_t_mst_req_t_AxiAddrWidth(mst_req_t_AxiAddrWidth), + .mst_req_t_mst_req_t_AxiDataWidth(mst_req_t_AxiDataWidth), + .mst_req_t_mst_req_t_AxiIdWidthSlaves(mst_req_t_AxiIdWidthSlaves), + .mst_req_t_mst_req_t_AxiStrbWidth(mst_req_t_AxiStrbWidth), + .mst_req_t_mst_req_t_AxiUserWidth(mst_req_t_AxiUserWidth), + .mst_resp_t_mst_resp_t_AxiDataWidth(mst_resp_t_AxiDataWidth), + .mst_resp_t_mst_resp_t_AxiIdWidthSlaves(mst_resp_t_AxiIdWidthSlaves), + .mst_resp_t_mst_resp_t_AxiUserWidth(mst_resp_t_AxiUserWidth), + .slv_ar_chan_t_slv_ar_chan_t_AxiAddrWidth(slv_ar_chan_t_AxiAddrWidth), + .slv_ar_chan_t_slv_ar_chan_t_AxiIdWidthMasters(slv_ar_chan_t_AxiIdWidthMasters), + .slv_ar_chan_t_slv_ar_chan_t_AxiUserWidth(slv_ar_chan_t_AxiUserWidth), + .slv_aw_chan_t_slv_aw_chan_t_AxiAddrWidth(slv_aw_chan_t_AxiAddrWidth), + .slv_aw_chan_t_slv_aw_chan_t_AxiIdWidthMasters(slv_aw_chan_t_AxiIdWidthMasters), + .slv_aw_chan_t_slv_aw_chan_t_AxiUserWidth(slv_aw_chan_t_AxiUserWidth), + .slv_b_chan_t_slv_b_chan_t_AxiIdWidthMasters(slv_b_chan_t_AxiIdWidthMasters), + .slv_b_chan_t_slv_b_chan_t_AxiUserWidth(slv_b_chan_t_AxiUserWidth), + .slv_r_chan_t_slv_r_chan_t_AxiDataWidth(slv_r_chan_t_AxiDataWidth), + .slv_r_chan_t_slv_r_chan_t_AxiIdWidthMasters(slv_r_chan_t_AxiIdWidthMasters), + .slv_r_chan_t_slv_r_chan_t_AxiUserWidth(slv_r_chan_t_AxiUserWidth), + .slv_req_t_slv_req_t_AxiAddrWidth(slv_req_t_AxiAddrWidth), + .slv_req_t_slv_req_t_AxiDataWidth(slv_req_t_AxiDataWidth), + .slv_req_t_slv_req_t_AxiIdWidthMasters(slv_req_t_AxiIdWidthMasters), + .slv_req_t_slv_req_t_AxiStrbWidth(slv_req_t_AxiStrbWidth), + .slv_req_t_slv_req_t_AxiUserWidth(slv_req_t_AxiUserWidth), + .slv_resp_t_slv_resp_t_AxiDataWidth(slv_resp_t_AxiDataWidth), + .slv_resp_t_slv_resp_t_AxiIdWidthMasters(slv_resp_t_AxiIdWidthMasters), + .slv_resp_t_slv_resp_t_AxiUserWidth(slv_resp_t_AxiUserWidth), + .w_chan_t_w_chan_t_AxiDataWidth(w_chan_t_AxiDataWidth), + .w_chan_t_w_chan_t_AxiStrbWidth(w_chan_t_AxiStrbWidth), + .w_chan_t_w_chan_t_AxiUserWidth(w_chan_t_AxiUserWidth), + .SlvAxiIDWidth(Cfg[159-:32]), + .NoSlvPorts(Cfg[298-:32]), + .MaxWTrans(Cfg[202-:32]), + .FallThrough(Cfg[170]), + .SpillAw(Cfg[164]), + .SpillW(Cfg[163]), + .SpillB(Cfg[162]), + .SpillAr(Cfg[161]), + .SpillR(Cfg[160]) + ) i_axi_mux( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_i(test_i), + .slv_reqs_i(mst_reqs[(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) + ((((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)) * (i * Cfg[298-:32]))+:(((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 2 : 1 - ((((((((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 35) + slv_req_t_AxiUserWidth) + 1) + (((slv_req_t_AxiDataWidth + slv_req_t_AxiStrbWidth) + 1) + slv_req_t_AxiUserWidth)) + 2) + (((slv_req_t_AxiIdWidthMasters + slv_req_t_AxiAddrWidth) + 29) + slv_req_t_AxiUserWidth)) + 1)) * Cfg[298-:32]]), + .slv_resps_o(mst_resps[(((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)) * (i * Cfg[298-:32])+:(((4 + ((slv_resp_t_AxiIdWidthMasters + 2) + slv_resp_t_AxiUserWidth)) + 1) + (((slv_resp_t_AxiIdWidthMasters + slv_resp_t_AxiDataWidth) + 3) + slv_resp_t_AxiUserWidth)) * Cfg[298-:32]]), + .mst_req_o(mst_ports_req_o[(((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1) >= 0 ? 0 : (((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1) + (i * (((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 2 : 1 - ((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1)))+:(((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1) >= 0 ? (((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 2 : 1 - ((((((((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 35) + mst_req_t_AxiUserWidth) + 1) + (((mst_req_t_AxiDataWidth + mst_req_t_AxiStrbWidth) + 1) + mst_req_t_AxiUserWidth)) + 2) + (((mst_req_t_AxiIdWidthSlaves + mst_req_t_AxiAddrWidth) + 29) + mst_req_t_AxiUserWidth)) + 1))]), + .mst_resp_i(mst_ports_resp_i[i * (((4 + ((mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_AxiUserWidth)) + 1) + (((mst_resp_t_AxiIdWidthSlaves + mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_AxiUserWidth))+:((4 + ((mst_resp_t_AxiIdWidthSlaves + 2) + mst_resp_t_AxiUserWidth)) + 1) + (((mst_resp_t_AxiIdWidthSlaves + mst_resp_t_AxiDataWidth) + 3) + mst_resp_t_AxiUserWidth)]) + ); + end + endgenerate +endmodule +// removed module with interface ports: axi_xbar_intf +module wb_mux ( + wb_clk_i, + wb_rst_i, + wbm_adr_i, + wbm_dat_i, + wbm_sel_i, + wbm_we_i, + wbm_cyc_i, + wbm_stb_i, + wbm_cti_i, + wbm_bte_i, + wbm_dat_o, + wbm_ack_o, + wbm_err_o, + wbm_rty_o, + wbs_adr_o, + wbs_dat_o, + wbs_sel_o, + wbs_we_o, + wbs_cyc_o, + wbs_stb_o, + wbs_cti_o, + wbs_bte_o, + wbs_dat_i, + wbs_ack_i, + wbs_err_i, + wbs_rty_i +); + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:43:15 + parameter dw = 32; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:44:15 + parameter aw = 32; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:45:15 + parameter num_devices = 2; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:46:15 + parameter num_slaves = num_devices; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:47:15 + parameter [(num_slaves * aw) - 1:0] MATCH_ADDR = 0; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:48:15 + parameter [(num_slaves * aw) - 1:0] MATCH_MASK = 0; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:51:5 + input wire wb_clk_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:52:5 + input wire wb_rst_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:55:5 + input wire [aw - 1:0] wbm_adr_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:56:5 + input wire [dw - 1:0] wbm_dat_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:57:5 + input wire [3:0] wbm_sel_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:58:5 + input wire wbm_we_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:59:5 + input wire wbm_cyc_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:60:5 + input wire wbm_stb_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:61:5 + input wire [2:0] wbm_cti_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:62:5 + input wire [1:0] wbm_bte_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:63:5 + output wire [dw - 1:0] wbm_dat_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:64:5 + output wire wbm_ack_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:65:5 + output wire wbm_err_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:66:5 + output wire wbm_rty_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:68:5 + output wire [(num_slaves * aw) - 1:0] wbs_adr_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:69:5 + output wire [(num_slaves * dw) - 1:0] wbs_dat_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:70:5 + output wire [(num_slaves * 4) - 1:0] wbs_sel_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:71:5 + output wire [num_slaves - 1:0] wbs_we_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:72:5 + output wire [num_slaves - 1:0] wbs_cyc_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:73:5 + output wire [num_slaves - 1:0] wbs_stb_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:74:5 + output wire [(num_slaves * 3) - 1:0] wbs_cti_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:75:5 + output wire [(num_slaves * 2) - 1:0] wbs_bte_o; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:76:5 + input wire [(num_slaves * dw) - 1:0] wbs_dat_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:77:5 + input wire [num_slaves - 1:0] wbs_ack_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:78:5 + input wire [num_slaves - 1:0] wbs_err_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:79:5 + input wire [num_slaves - 1:0] wbs_rty_i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:86:4 + parameter slave_sel_bits = (num_slaves > 1 ? $clog2(num_slaves) : 1); + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:88:4 + reg wbm_err; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:89:4 + wire [slave_sel_bits - 1:0] slave_sel; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:90:4 + wire [num_slaves - 1:0] match; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:92:4 + genvar _gv_idx_1; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:94:4 + generate + for (_gv_idx_1 = 0; _gv_idx_1 < num_slaves; _gv_idx_1 = _gv_idx_1 + 1) begin : addr_match + localparam idx = _gv_idx_1; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:96:3 + assign match[idx] = (wbm_adr_i & MATCH_MASK[idx * aw+:aw]) == MATCH_ADDR[idx * aw+:aw]; + end + endgenerate + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:103:4 + function [slave_sel_bits - 1:0] ff1; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:104:7 + input [num_slaves - 1:0] in; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:105:7 + integer i; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:107:7 + begin + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:108:3 + ff1 = 0; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:109:3 + for (i = num_slaves - 1; i >= 0; i = i - 1) + begin + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:110:6 + if (in[i]) + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:112:8 + ff1 = i; + end + end + endfunction + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:118:4 + assign slave_sel = ff1(match); + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:120:4 + always @(posedge wb_clk_i) + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:121:6 + wbm_err <= wbm_cyc_i & !(|match); + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:123:4 + assign wbs_adr_o = {num_slaves {wbm_adr_i}}; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:124:4 + assign wbs_dat_o = {num_slaves {wbm_dat_i}}; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:125:4 + assign wbs_sel_o = {num_slaves {wbm_sel_i}}; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:126:4 + assign wbs_we_o = {num_slaves {wbm_we_i}}; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:129:4 + assign wbs_cyc_o = match & (wbm_cyc_i << slave_sel); + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:131:4 + assign wbs_stb_o = {num_slaves {wbm_stb_i}}; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:133:4 + assign wbs_cti_o = {num_slaves {wbm_cti_i}}; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:134:4 + assign wbs_bte_o = {num_slaves {wbm_bte_i}}; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:136:4 + assign wbm_dat_o = wbs_dat_i[slave_sel * dw+:dw]; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:137:4 + assign wbm_ack_o = wbs_ack_i[slave_sel]; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:138:4 + assign wbm_err_o = wbs_err_i[slave_sel] | wbm_err; + // Trace: ./src/wb_intercon_1.4.1/rtl/verilog/wb_mux.v:139:4 + assign wbm_rty_o = wbs_rty_i[slave_sel]; +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:23:1 +`default_nettype wire +module veer_wrapper_dmi ( + clk, + rst_l, + dbg_rst_l, + rst_vec, + nmi_int, + nmi_vec, + trace_rv_i_insn_ip, + trace_rv_i_address_ip, + trace_rv_i_valid_ip, + trace_rv_i_exception_ip, + trace_rv_i_ecause_ip, + trace_rv_i_interrupt_ip, + trace_rv_i_tval_ip, + lsu_axi_awvalid, + lsu_axi_awready, + lsu_axi_awid, + lsu_axi_awaddr, + lsu_axi_awregion, + lsu_axi_awlen, + lsu_axi_awsize, + lsu_axi_awburst, + lsu_axi_awlock, + lsu_axi_awcache, + lsu_axi_awprot, + lsu_axi_awqos, + lsu_axi_wvalid, + lsu_axi_wready, + lsu_axi_wdata, + lsu_axi_wstrb, + lsu_axi_wlast, + lsu_axi_bvalid, + lsu_axi_bready, + lsu_axi_bresp, + lsu_axi_bid, + lsu_axi_arvalid, + lsu_axi_arready, + lsu_axi_arid, + lsu_axi_araddr, + lsu_axi_arregion, + lsu_axi_arlen, + lsu_axi_arsize, + lsu_axi_arburst, + lsu_axi_arlock, + lsu_axi_arcache, + lsu_axi_arprot, + lsu_axi_arqos, + lsu_axi_rvalid, + lsu_axi_rready, + lsu_axi_rid, + lsu_axi_rdata, + lsu_axi_rresp, + lsu_axi_rlast, + ifu_axi_awvalid, + ifu_axi_awready, + ifu_axi_awid, + ifu_axi_awaddr, + ifu_axi_awregion, + ifu_axi_awlen, + ifu_axi_awsize, + ifu_axi_awburst, + ifu_axi_awlock, + ifu_axi_awcache, + ifu_axi_awprot, + ifu_axi_awqos, + ifu_axi_wvalid, + ifu_axi_wready, + ifu_axi_wdata, + ifu_axi_wstrb, + ifu_axi_wlast, + ifu_axi_bvalid, + ifu_axi_bready, + ifu_axi_bresp, + ifu_axi_bid, + ifu_axi_arvalid, + ifu_axi_arready, + ifu_axi_arid, + ifu_axi_araddr, + ifu_axi_arregion, + ifu_axi_arlen, + ifu_axi_arsize, + ifu_axi_arburst, + ifu_axi_arlock, + ifu_axi_arcache, + ifu_axi_arprot, + ifu_axi_arqos, + ifu_axi_rvalid, + ifu_axi_rready, + ifu_axi_rid, + ifu_axi_rdata, + ifu_axi_rresp, + ifu_axi_rlast, + sb_axi_awvalid, + sb_axi_awready, + sb_axi_awid, + sb_axi_awaddr, + sb_axi_awregion, + sb_axi_awlen, + sb_axi_awsize, + sb_axi_awburst, + sb_axi_awlock, + sb_axi_awcache, + sb_axi_awprot, + sb_axi_awqos, + sb_axi_wvalid, + sb_axi_wready, + sb_axi_wdata, + sb_axi_wstrb, + sb_axi_wlast, + sb_axi_bvalid, + sb_axi_bready, + sb_axi_bresp, + sb_axi_bid, + sb_axi_arvalid, + sb_axi_arready, + sb_axi_arid, + sb_axi_araddr, + sb_axi_arregion, + sb_axi_arlen, + sb_axi_arsize, + sb_axi_arburst, + sb_axi_arlock, + sb_axi_arcache, + sb_axi_arprot, + sb_axi_arqos, + sb_axi_rvalid, + sb_axi_rready, + sb_axi_rid, + sb_axi_rdata, + sb_axi_rresp, + sb_axi_rlast, + dma_axi_awvalid, + dma_axi_awready, + dma_axi_awid, + dma_axi_awaddr, + dma_axi_awsize, + dma_axi_awprot, + dma_axi_awlen, + dma_axi_awburst, + dma_axi_wvalid, + dma_axi_wready, + dma_axi_wdata, + dma_axi_wstrb, + dma_axi_wlast, + dma_axi_bvalid, + dma_axi_bready, + dma_axi_bresp, + dma_axi_bid, + dma_axi_arvalid, + dma_axi_arready, + dma_axi_arid, + dma_axi_araddr, + dma_axi_arsize, + dma_axi_arprot, + dma_axi_arlen, + dma_axi_arburst, + dma_axi_rvalid, + dma_axi_rready, + dma_axi_rid, + dma_axi_rdata, + dma_axi_rresp, + dma_axi_rlast, + lsu_bus_clk_en, + ifu_bus_clk_en, + dbg_bus_clk_en, + dma_bus_clk_en, + timer_int, + extintsrc_req, + dec_tlu_perfcnt0, + dec_tlu_perfcnt1, + dec_tlu_perfcnt2, + dec_tlu_perfcnt3, + dmi_reg_en, + dmi_reg_addr, + dmi_reg_wr_en, + dmi_reg_wdata, + dmi_reg_rdata, + dmi_hard_reset, + mpc_debug_halt_req, + mpc_debug_run_req, + mpc_reset_run_req, + mpc_debug_halt_ack, + mpc_debug_run_ack, + debug_brkpt_status, + i_cpu_halt_req, + o_cpu_halt_ack, + o_cpu_halt_status, + o_debug_mode_status, + i_cpu_run_req, + o_cpu_run_ack, + scan_mode, + mbist_mode +); + // removed import el2_pkg::*; + // Trace: src/veerwolf-veer_el2_pack_config_0.7.5/el2_param.vh:1:11 + // removed localparam type el2_param_t + parameter [2270:0] pt = 2271'h384010020c010010840000020508020104840002808120606828020060210c00000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc3fffffffc083820401c013858083c3c01000000100820428042010040830c2010281840200081002008e0c0801004040800c01002100400606810104100c0810000300800e0ee00000001002101800000000000000000000000000000000000000000000000000000000000000000000000000000000007fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff87fffffff8001080c08081c081007806000003c043c04001000902084021; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:30:4 + input wire clk; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:31:4 + input wire rst_l; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:32:4 + input wire dbg_rst_l; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:33:4 + input wire [31:1] rst_vec; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:34:4 + input wire nmi_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:35:4 + input wire [31:1] nmi_vec; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:38:4 + output wire [31:0] trace_rv_i_insn_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:39:4 + output wire [63:0] trace_rv_i_address_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:40:4 + output wire [2:0] trace_rv_i_valid_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:41:4 + output wire [1:0] trace_rv_i_exception_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:42:4 + output wire [4:0] trace_rv_i_ecause_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:43:4 + output wire [1:0] trace_rv_i_interrupt_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:44:4 + output wire [31:0] trace_rv_i_tval_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:50:4 + output wire lsu_axi_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:51:4 + input wire lsu_axi_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:52:4 + output wire [pt[181-:8] - 1:0] lsu_axi_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:53:4 + output wire [31:0] lsu_axi_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:54:4 + output wire [3:0] lsu_axi_awregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:55:4 + output wire [7:0] lsu_axi_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:56:4 + output wire [2:0] lsu_axi_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:57:4 + output wire [1:0] lsu_axi_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:58:4 + output wire lsu_axi_awlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:59:4 + output wire [3:0] lsu_axi_awcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:60:4 + output wire [2:0] lsu_axi_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:61:4 + output wire [3:0] lsu_axi_awqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:63:4 + output wire lsu_axi_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:64:4 + input wire lsu_axi_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:65:4 + output wire [63:0] lsu_axi_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:66:4 + output wire [7:0] lsu_axi_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:67:4 + output wire lsu_axi_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:69:4 + input wire lsu_axi_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:70:4 + output wire lsu_axi_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:71:4 + input wire [1:0] lsu_axi_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:72:4 + input wire [pt[181-:8] - 1:0] lsu_axi_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:75:4 + output wire lsu_axi_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:76:4 + input wire lsu_axi_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:77:4 + output wire [pt[181-:8] - 1:0] lsu_axi_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:78:4 + output wire [31:0] lsu_axi_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:79:4 + output wire [3:0] lsu_axi_arregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:80:4 + output wire [7:0] lsu_axi_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:81:4 + output wire [2:0] lsu_axi_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:82:4 + output wire [1:0] lsu_axi_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:83:4 + output wire lsu_axi_arlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:84:4 + output wire [3:0] lsu_axi_arcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:85:4 + output wire [2:0] lsu_axi_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:86:4 + output wire [3:0] lsu_axi_arqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:88:4 + input wire lsu_axi_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:89:4 + output wire lsu_axi_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:90:4 + input wire [pt[181-:8] - 1:0] lsu_axi_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:91:4 + input wire [63:0] lsu_axi_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:92:4 + input wire [1:0] lsu_axi_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:93:4 + input wire lsu_axi_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:97:4 + output wire ifu_axi_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:98:4 + input wire ifu_axi_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:99:4 + output wire [pt[826-:8] - 1:0] ifu_axi_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:100:4 + output wire [31:0] ifu_axi_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:101:4 + output wire [3:0] ifu_axi_awregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:102:4 + output wire [7:0] ifu_axi_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:103:4 + output wire [2:0] ifu_axi_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:104:4 + output wire [1:0] ifu_axi_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:105:4 + output wire ifu_axi_awlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:106:4 + output wire [3:0] ifu_axi_awcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:107:4 + output wire [2:0] ifu_axi_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:108:4 + output wire [3:0] ifu_axi_awqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:110:4 + output wire ifu_axi_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:111:4 + input wire ifu_axi_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:112:4 + output wire [63:0] ifu_axi_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:113:4 + output wire [7:0] ifu_axi_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:114:4 + output wire ifu_axi_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:116:4 + input wire ifu_axi_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:117:4 + output wire ifu_axi_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:118:4 + input wire [1:0] ifu_axi_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:119:4 + input wire [pt[826-:8] - 1:0] ifu_axi_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:122:4 + output wire ifu_axi_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:123:4 + input wire ifu_axi_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:124:4 + output wire [pt[826-:8] - 1:0] ifu_axi_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:125:4 + output wire [31:0] ifu_axi_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:126:4 + output wire [3:0] ifu_axi_arregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:127:4 + output wire [7:0] ifu_axi_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:128:4 + output wire [2:0] ifu_axi_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:129:4 + output wire [1:0] ifu_axi_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:130:4 + output wire ifu_axi_arlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:131:4 + output wire [3:0] ifu_axi_arcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:132:4 + output wire [2:0] ifu_axi_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:133:4 + output wire [3:0] ifu_axi_arqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:135:4 + input wire ifu_axi_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:136:4 + output wire ifu_axi_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:137:4 + input wire [pt[826-:8] - 1:0] ifu_axi_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:138:4 + input wire [63:0] ifu_axi_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:139:4 + input wire [1:0] ifu_axi_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:140:4 + input wire ifu_axi_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:144:4 + output wire sb_axi_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:145:4 + input wire sb_axi_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:146:4 + output wire [pt[12-:8] - 1:0] sb_axi_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:147:4 + output wire [31:0] sb_axi_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:148:4 + output wire [3:0] sb_axi_awregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:149:4 + output wire [7:0] sb_axi_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:150:4 + output wire [2:0] sb_axi_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:151:4 + output wire [1:0] sb_axi_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:152:4 + output wire sb_axi_awlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:153:4 + output wire [3:0] sb_axi_awcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:154:4 + output wire [2:0] sb_axi_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:155:4 + output wire [3:0] sb_axi_awqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:157:4 + output wire sb_axi_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:158:4 + input wire sb_axi_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:159:4 + output wire [63:0] sb_axi_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:160:4 + output wire [7:0] sb_axi_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:161:4 + output wire sb_axi_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:163:4 + input wire sb_axi_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:164:4 + output wire sb_axi_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:165:4 + input wire [1:0] sb_axi_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:166:4 + input wire [pt[12-:8] - 1:0] sb_axi_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:169:4 + output wire sb_axi_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:170:4 + input wire sb_axi_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:171:4 + output wire [pt[12-:8] - 1:0] sb_axi_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:172:4 + output wire [31:0] sb_axi_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:173:4 + output wire [3:0] sb_axi_arregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:174:4 + output wire [7:0] sb_axi_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:175:4 + output wire [2:0] sb_axi_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:176:4 + output wire [1:0] sb_axi_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:177:4 + output wire sb_axi_arlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:178:4 + output wire [3:0] sb_axi_arcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:179:4 + output wire [2:0] sb_axi_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:180:4 + output wire [3:0] sb_axi_arqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:182:4 + input wire sb_axi_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:183:4 + output wire sb_axi_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:184:4 + input wire [pt[12-:8] - 1:0] sb_axi_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:185:4 + input wire [63:0] sb_axi_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:186:4 + input wire [1:0] sb_axi_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:187:4 + input wire sb_axi_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:191:4 + input wire dma_axi_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:192:4 + output wire dma_axi_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:193:4 + input wire [pt[1235-:8] - 1:0] dma_axi_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:194:4 + input wire [31:0] dma_axi_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:195:4 + input wire [2:0] dma_axi_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:196:4 + input wire [2:0] dma_axi_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:197:4 + input wire [7:0] dma_axi_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:198:4 + input wire [1:0] dma_axi_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:201:4 + input wire dma_axi_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:202:4 + output wire dma_axi_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:203:4 + input wire [63:0] dma_axi_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:204:4 + input wire [7:0] dma_axi_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:205:4 + input wire dma_axi_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:207:4 + output wire dma_axi_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:208:4 + input wire dma_axi_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:209:4 + output wire [1:0] dma_axi_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:210:4 + output wire [pt[1235-:8] - 1:0] dma_axi_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:213:4 + input wire dma_axi_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:214:4 + output wire dma_axi_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:215:4 + input wire [pt[1235-:8] - 1:0] dma_axi_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:216:4 + input wire [31:0] dma_axi_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:217:4 + input wire [2:0] dma_axi_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:218:4 + input wire [2:0] dma_axi_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:219:4 + input wire [7:0] dma_axi_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:220:4 + input wire [1:0] dma_axi_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:222:4 + output wire dma_axi_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:223:4 + input wire dma_axi_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:224:4 + output wire [pt[1235-:8] - 1:0] dma_axi_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:225:4 + output wire [63:0] dma_axi_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:226:4 + output wire [1:0] dma_axi_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:227:4 + output wire dma_axi_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:230:4 + input wire lsu_bus_clk_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:231:4 + input wire ifu_bus_clk_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:232:4 + input wire dbg_bus_clk_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:233:4 + input wire dma_bus_clk_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:235:4 + input wire timer_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:236:4 + input wire [pt[56-:12]:1] extintsrc_req; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:238:4 + output wire dec_tlu_perfcnt0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:239:4 + output wire dec_tlu_perfcnt1; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:240:4 + output wire dec_tlu_perfcnt2; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:241:4 + output wire dec_tlu_perfcnt3; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:244:4 + input wire dmi_reg_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:245:4 + input wire [6:0] dmi_reg_addr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:246:4 + input wire dmi_reg_wr_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:247:4 + input wire [31:0] dmi_reg_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:248:4 + output wire [31:0] dmi_reg_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:249:4 + input wire dmi_hard_reset; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:252:4 + input wire mpc_debug_halt_req; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:253:4 + input wire mpc_debug_run_req; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:254:4 + input wire mpc_reset_run_req; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:255:4 + output wire mpc_debug_halt_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:256:4 + output wire mpc_debug_run_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:257:4 + output wire debug_brkpt_status; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:259:4 + input wire i_cpu_halt_req; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:260:4 + output wire o_cpu_halt_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:261:4 + output wire o_cpu_halt_status; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:262:4 + output wire o_debug_mode_status; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:263:4 + input wire i_cpu_run_req; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:264:4 + output wire o_cpu_run_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:265:4 + input wire scan_mode; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:266:4 + input wire mbist_mode; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:269:4 + // removed localparam type el2_pkg_el2_dccm_ext_in_pkt_t + wire [(pt[1342-:9] * 12) - 1:0] dccm_ext_in_pkt; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:270:4 + // removed localparam type el2_pkg_el2_ccm_ext_in_pkt_t + wire [(pt[909-:9] * 12) - 1:0] iccm_ext_in_pkt; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:271:4 + // removed localparam type el2_pkg_el2_ic_data_ext_in_pkt_t + wire [((pt[1060-:7] * pt[1189-:7]) * 12) - 1:0] ic_data_ext_in_pkt; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:272:4 + // removed localparam type el2_pkg_el2_ic_tag_ext_in_pkt_t + wire [(pt[1060-:7] * 12) - 1:0] ic_tag_ext_in_pkt; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:274:4 + wire active_l2clk; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:275:4 + wire free_l2clk; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:278:4 + wire dccm_wren; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:279:4 + wire dccm_rden; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:280:4 + wire [pt[1398-:9] - 1:0] dccm_wr_addr_lo; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:281:4 + wire [pt[1398-:9] - 1:0] dccm_wr_addr_hi; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:282:4 + wire [pt[1398-:9] - 1:0] dccm_rd_addr_lo; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:283:4 + wire [pt[1398-:9] - 1:0] dccm_rd_addr_hi; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:284:4 + wire [pt[1360-:10] - 1:0] dccm_wr_data_lo; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:285:4 + wire [pt[1360-:10] - 1:0] dccm_wr_data_hi; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:287:4 + wire [pt[1360-:10] - 1:0] dccm_rd_data_lo; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:288:4 + wire [pt[1360-:10] - 1:0] dccm_rd_data_hi; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:293:4 + wire [31:1] ic_rw_addr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:294:4 + wire [pt[1060-:7] - 1:0] ic_wr_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:295:4 + wire ic_rd_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:298:4 + wire [pt[1060-:7] - 1:0] ic_tag_valid; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:300:4 + wire [pt[1060-:7] - 1:0] ic_rd_hit; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:301:4 + wire ic_tag_perr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:303:4 + wire [pt[1104-:9]:3] ic_debug_addr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:304:4 + wire ic_debug_rd_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:305:4 + wire ic_debug_wr_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:306:4 + wire ic_debug_tag_array; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:307:4 + wire [pt[1060-:7] - 1:0] ic_debug_way; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:309:4 + wire [25:0] ictag_debug_rd_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:310:4 + wire [(pt[1189-:7] * 71) - 1:0] ic_wr_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:311:4 + wire [63:0] ic_rd_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:312:4 + wire [70:0] ic_debug_rd_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:313:4 + wire [70:0] ic_debug_wr_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:315:4 + wire [pt[1189-:7] - 1:0] ic_eccerr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:316:4 + wire [pt[1189-:7] - 1:0] ic_parerr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:318:4 + wire [63:0] ic_premux_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:319:4 + wire ic_sel_premux_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:322:4 + wire [pt[936-:9] - 1:1] iccm_rw_addr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:323:4 + wire iccm_wren; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:324:4 + wire iccm_rden; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:325:4 + wire [2:0] iccm_wr_size; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:326:4 + wire [77:0] iccm_wr_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:327:4 + wire iccm_buf_correct_ecc; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:328:4 + wire iccm_correction_state; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:330:4 + wire [63:0] iccm_rd_data; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:331:4 + wire [77:0] iccm_rd_data_ecc; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:333:4 + wire core_rst_l; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:334:4 + wire jtag_tdoEn; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:336:4 + wire dccm_clk_override; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:337:4 + wire icm_clk_override; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:338:4 + wire dec_tlu_core_ecc_disable; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:341:4 + wire [31:0] haddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:342:4 + wire [2:0] hburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:343:4 + wire hmastlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:344:4 + wire [3:0] hprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:345:4 + wire [2:0] hsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:346:4 + wire [1:0] htrans; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:347:4 + wire hwrite; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:349:4 + wire [63:0] hrdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:350:4 + wire hready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:351:4 + wire hresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:354:4 + wire [31:0] lsu_haddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:355:4 + wire [2:0] lsu_hburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:356:4 + wire lsu_hmastlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:357:4 + wire [3:0] lsu_hprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:358:4 + wire [2:0] lsu_hsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:359:4 + wire [1:0] lsu_htrans; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:360:4 + wire lsu_hwrite; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:361:4 + wire [63:0] lsu_hwdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:363:4 + wire [63:0] lsu_hrdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:364:4 + wire lsu_hready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:365:4 + wire lsu_hresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:367:4 + wire [31:0] sb_haddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:368:4 + wire [2:0] sb_hburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:369:4 + wire sb_hmastlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:370:4 + wire [3:0] sb_hprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:371:4 + wire [2:0] sb_hsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:372:4 + wire [1:0] sb_htrans; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:373:4 + wire sb_hwrite; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:374:4 + wire [63:0] sb_hwdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:376:5 + wire [63:0] sb_hrdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:377:5 + wire sb_hready; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:378:5 + wire sb_hresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:381:4 + wire dma_hsel; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:382:4 + wire [31:0] dma_haddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:383:4 + wire [2:0] dma_hburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:384:4 + wire dma_hmastlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:385:4 + wire [3:0] dma_hprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:386:4 + wire [2:0] dma_hsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:387:4 + wire [1:0] dma_htrans; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:388:4 + wire dma_hwrite; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:389:4 + wire [63:0] dma_hwdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:390:4 + wire dma_hreadyin; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:392:4 + wire [63:0] dma_hrdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:393:4 + wire dma_hreadyout; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:394:4 + wire dma_hresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:399:4 + assign hrdata[63:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:400:4 + assign hready = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:401:4 + assign hresp = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:403:4 + assign lsu_hrdata[63:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:404:4 + assign lsu_hready = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:405:4 + assign lsu_hresp = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:407:4 + assign sb_hrdata[63:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:408:4 + assign sb_hready = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:409:4 + assign sb_hresp = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:412:4 + assign dma_hsel = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:413:4 + assign dma_haddr[31:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:414:4 + assign dma_hburst[2:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:415:4 + assign dma_hmastlock = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:416:4 + assign dma_hprot[3:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:417:4 + assign dma_hsize[2:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:418:4 + assign dma_htrans[1:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:419:4 + assign dma_hwrite = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:420:4 + assign dma_hwdata[63:0] = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:421:4 + assign dma_hreadyin = 1'sb0; + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:424:4 + el2_veer veer( + .soft_int(1'b0), + .core_id(28'd0), + .trace_rv_i_address_ip(trace_rv_i_address_ip[31:0]), + .trace_rv_i_valid_ip(trace_rv_i_valid_ip[0]), + .trace_rv_i_exception_ip(trace_rv_i_exception_ip[0]), + .trace_rv_i_interrupt_ip(trace_rv_i_interrupt_ip[0]), + .clk(clk), + .rst_l(rst_l), + .dbg_rst_l(dbg_rst_l), + .rst_vec(rst_vec), + .nmi_int(nmi_int), + .nmi_vec(nmi_vec), + .core_rst_l(core_rst_l), + .active_l2clk(active_l2clk), + .free_l2clk(free_l2clk), + .trace_rv_i_insn_ip(trace_rv_i_insn_ip), + .trace_rv_i_ecause_ip(trace_rv_i_ecause_ip), + .trace_rv_i_tval_ip(trace_rv_i_tval_ip), + .dccm_clk_override(dccm_clk_override), + .icm_clk_override(icm_clk_override), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .i_cpu_halt_req(i_cpu_halt_req), + .i_cpu_run_req(i_cpu_run_req), + .o_cpu_halt_ack(o_cpu_halt_ack), + .o_cpu_halt_status(o_cpu_halt_status), + .o_cpu_run_ack(o_cpu_run_ack), + .o_debug_mode_status(o_debug_mode_status), + .mpc_debug_halt_req(mpc_debug_halt_req), + .mpc_debug_run_req(mpc_debug_run_req), + .mpc_reset_run_req(mpc_reset_run_req), + .mpc_debug_halt_ack(mpc_debug_halt_ack), + .mpc_debug_run_ack(mpc_debug_run_ack), + .debug_brkpt_status(debug_brkpt_status), + .dec_tlu_perfcnt0(dec_tlu_perfcnt0), + .dec_tlu_perfcnt1(dec_tlu_perfcnt1), + .dec_tlu_perfcnt2(dec_tlu_perfcnt2), + .dec_tlu_perfcnt3(dec_tlu_perfcnt3), + .dccm_wren(dccm_wren), + .dccm_rden(dccm_rden), + .dccm_wr_addr_lo(dccm_wr_addr_lo), + .dccm_wr_addr_hi(dccm_wr_addr_hi), + .dccm_rd_addr_lo(dccm_rd_addr_lo), + .dccm_rd_addr_hi(dccm_rd_addr_hi), + .dccm_wr_data_lo(dccm_wr_data_lo), + .dccm_wr_data_hi(dccm_wr_data_hi), + .dccm_rd_data_lo(dccm_rd_data_lo), + .dccm_rd_data_hi(dccm_rd_data_hi), + .iccm_rw_addr(iccm_rw_addr), + .iccm_wren(iccm_wren), + .iccm_rden(iccm_rden), + .iccm_wr_size(iccm_wr_size), + .iccm_wr_data(iccm_wr_data), + .iccm_buf_correct_ecc(iccm_buf_correct_ecc), + .iccm_correction_state(iccm_correction_state), + .iccm_rd_data(iccm_rd_data), + .iccm_rd_data_ecc(iccm_rd_data_ecc), + .ic_rw_addr(ic_rw_addr), + .ic_tag_valid(ic_tag_valid), + .ic_wr_en(ic_wr_en), + .ic_rd_en(ic_rd_en), + .ic_wr_data(ic_wr_data), + .ic_rd_data(ic_rd_data), + .ic_debug_rd_data(ic_debug_rd_data), + .ictag_debug_rd_data(ictag_debug_rd_data), + .ic_debug_wr_data(ic_debug_wr_data), + .ic_eccerr(ic_eccerr), + .ic_parerr(ic_parerr), + .ic_premux_data(ic_premux_data), + .ic_sel_premux_data(ic_sel_premux_data), + .ic_debug_addr(ic_debug_addr), + .ic_debug_rd_en(ic_debug_rd_en), + .ic_debug_wr_en(ic_debug_wr_en), + .ic_debug_tag_array(ic_debug_tag_array), + .ic_debug_way(ic_debug_way), + .ic_rd_hit(ic_rd_hit), + .ic_tag_perr(ic_tag_perr), + .lsu_axi_awvalid(lsu_axi_awvalid), + .lsu_axi_awready(lsu_axi_awready), + .lsu_axi_awid(lsu_axi_awid), + .lsu_axi_awaddr(lsu_axi_awaddr), + .lsu_axi_awregion(lsu_axi_awregion), + .lsu_axi_awlen(lsu_axi_awlen), + .lsu_axi_awsize(lsu_axi_awsize), + .lsu_axi_awburst(lsu_axi_awburst), + .lsu_axi_awlock(lsu_axi_awlock), + .lsu_axi_awcache(lsu_axi_awcache), + .lsu_axi_awprot(lsu_axi_awprot), + .lsu_axi_awqos(lsu_axi_awqos), + .lsu_axi_wvalid(lsu_axi_wvalid), + .lsu_axi_wready(lsu_axi_wready), + .lsu_axi_wdata(lsu_axi_wdata), + .lsu_axi_wstrb(lsu_axi_wstrb), + .lsu_axi_wlast(lsu_axi_wlast), + .lsu_axi_bvalid(lsu_axi_bvalid), + .lsu_axi_bready(lsu_axi_bready), + .lsu_axi_bresp(lsu_axi_bresp), + .lsu_axi_bid(lsu_axi_bid), + .lsu_axi_arvalid(lsu_axi_arvalid), + .lsu_axi_arready(lsu_axi_arready), + .lsu_axi_arid(lsu_axi_arid), + .lsu_axi_araddr(lsu_axi_araddr), + .lsu_axi_arregion(lsu_axi_arregion), + .lsu_axi_arlen(lsu_axi_arlen), + .lsu_axi_arsize(lsu_axi_arsize), + .lsu_axi_arburst(lsu_axi_arburst), + .lsu_axi_arlock(lsu_axi_arlock), + .lsu_axi_arcache(lsu_axi_arcache), + .lsu_axi_arprot(lsu_axi_arprot), + .lsu_axi_arqos(lsu_axi_arqos), + .lsu_axi_rvalid(lsu_axi_rvalid), + .lsu_axi_rready(lsu_axi_rready), + .lsu_axi_rid(lsu_axi_rid), + .lsu_axi_rdata(lsu_axi_rdata), + .lsu_axi_rresp(lsu_axi_rresp), + .lsu_axi_rlast(lsu_axi_rlast), + .ifu_axi_awvalid(ifu_axi_awvalid), + .ifu_axi_awready(ifu_axi_awready), + .ifu_axi_awid(ifu_axi_awid), + .ifu_axi_awaddr(ifu_axi_awaddr), + .ifu_axi_awregion(ifu_axi_awregion), + .ifu_axi_awlen(ifu_axi_awlen), + .ifu_axi_awsize(ifu_axi_awsize), + .ifu_axi_awburst(ifu_axi_awburst), + .ifu_axi_awlock(ifu_axi_awlock), + .ifu_axi_awcache(ifu_axi_awcache), + .ifu_axi_awprot(ifu_axi_awprot), + .ifu_axi_awqos(ifu_axi_awqos), + .ifu_axi_wvalid(ifu_axi_wvalid), + .ifu_axi_wready(ifu_axi_wready), + .ifu_axi_wdata(ifu_axi_wdata), + .ifu_axi_wstrb(ifu_axi_wstrb), + .ifu_axi_wlast(ifu_axi_wlast), + .ifu_axi_bvalid(ifu_axi_bvalid), + .ifu_axi_bready(ifu_axi_bready), + .ifu_axi_bresp(ifu_axi_bresp), + .ifu_axi_bid(ifu_axi_bid), + .ifu_axi_arvalid(ifu_axi_arvalid), + .ifu_axi_arready(ifu_axi_arready), + .ifu_axi_arid(ifu_axi_arid), + .ifu_axi_araddr(ifu_axi_araddr), + .ifu_axi_arregion(ifu_axi_arregion), + .ifu_axi_arlen(ifu_axi_arlen), + .ifu_axi_arsize(ifu_axi_arsize), + .ifu_axi_arburst(ifu_axi_arburst), + .ifu_axi_arlock(ifu_axi_arlock), + .ifu_axi_arcache(ifu_axi_arcache), + .ifu_axi_arprot(ifu_axi_arprot), + .ifu_axi_arqos(ifu_axi_arqos), + .ifu_axi_rvalid(ifu_axi_rvalid), + .ifu_axi_rready(ifu_axi_rready), + .ifu_axi_rid(ifu_axi_rid), + .ifu_axi_rdata(ifu_axi_rdata), + .ifu_axi_rresp(ifu_axi_rresp), + .ifu_axi_rlast(ifu_axi_rlast), + .sb_axi_awvalid(sb_axi_awvalid), + .sb_axi_awready(sb_axi_awready), + .sb_axi_awid(sb_axi_awid), + .sb_axi_awaddr(sb_axi_awaddr), + .sb_axi_awregion(sb_axi_awregion), + .sb_axi_awlen(sb_axi_awlen), + .sb_axi_awsize(sb_axi_awsize), + .sb_axi_awburst(sb_axi_awburst), + .sb_axi_awlock(sb_axi_awlock), + .sb_axi_awcache(sb_axi_awcache), + .sb_axi_awprot(sb_axi_awprot), + .sb_axi_awqos(sb_axi_awqos), + .sb_axi_wvalid(sb_axi_wvalid), + .sb_axi_wready(sb_axi_wready), + .sb_axi_wdata(sb_axi_wdata), + .sb_axi_wstrb(sb_axi_wstrb), + .sb_axi_wlast(sb_axi_wlast), + .sb_axi_bvalid(sb_axi_bvalid), + .sb_axi_bready(sb_axi_bready), + .sb_axi_bresp(sb_axi_bresp), + .sb_axi_bid(sb_axi_bid), + .sb_axi_arvalid(sb_axi_arvalid), + .sb_axi_arready(sb_axi_arready), + .sb_axi_arid(sb_axi_arid), + .sb_axi_araddr(sb_axi_araddr), + .sb_axi_arregion(sb_axi_arregion), + .sb_axi_arlen(sb_axi_arlen), + .sb_axi_arsize(sb_axi_arsize), + .sb_axi_arburst(sb_axi_arburst), + .sb_axi_arlock(sb_axi_arlock), + .sb_axi_arcache(sb_axi_arcache), + .sb_axi_arprot(sb_axi_arprot), + .sb_axi_arqos(sb_axi_arqos), + .sb_axi_rvalid(sb_axi_rvalid), + .sb_axi_rready(sb_axi_rready), + .sb_axi_rid(sb_axi_rid), + .sb_axi_rdata(sb_axi_rdata), + .sb_axi_rresp(sb_axi_rresp), + .sb_axi_rlast(sb_axi_rlast), + .dma_axi_awvalid(dma_axi_awvalid), + .dma_axi_awready(dma_axi_awready), + .dma_axi_awid(dma_axi_awid), + .dma_axi_awaddr(dma_axi_awaddr), + .dma_axi_awsize(dma_axi_awsize), + .dma_axi_awprot(dma_axi_awprot), + .dma_axi_awlen(dma_axi_awlen), + .dma_axi_awburst(dma_axi_awburst), + .dma_axi_wvalid(dma_axi_wvalid), + .dma_axi_wready(dma_axi_wready), + .dma_axi_wdata(dma_axi_wdata), + .dma_axi_wstrb(dma_axi_wstrb), + .dma_axi_wlast(dma_axi_wlast), + .dma_axi_bvalid(dma_axi_bvalid), + .dma_axi_bready(dma_axi_bready), + .dma_axi_bresp(dma_axi_bresp), + .dma_axi_bid(dma_axi_bid), + .dma_axi_arvalid(dma_axi_arvalid), + .dma_axi_arready(dma_axi_arready), + .dma_axi_arid(dma_axi_arid), + .dma_axi_araddr(dma_axi_araddr), + .dma_axi_arsize(dma_axi_arsize), + .dma_axi_arprot(dma_axi_arprot), + .dma_axi_arlen(dma_axi_arlen), + .dma_axi_arburst(dma_axi_arburst), + .dma_axi_rvalid(dma_axi_rvalid), + .dma_axi_rready(dma_axi_rready), + .dma_axi_rid(dma_axi_rid), + .dma_axi_rdata(dma_axi_rdata), + .dma_axi_rresp(dma_axi_rresp), + .dma_axi_rlast(dma_axi_rlast), + .haddr(haddr), + .hburst(hburst), + .hmastlock(hmastlock), + .hprot(hprot), + .hsize(hsize), + .htrans(htrans), + .hwrite(hwrite), + .hrdata(hrdata), + .hready(hready), + .hresp(hresp), + .lsu_haddr(lsu_haddr), + .lsu_hburst(lsu_hburst), + .lsu_hmastlock(lsu_hmastlock), + .lsu_hprot(lsu_hprot), + .lsu_hsize(lsu_hsize), + .lsu_htrans(lsu_htrans), + .lsu_hwrite(lsu_hwrite), + .lsu_hwdata(lsu_hwdata), + .lsu_hrdata(lsu_hrdata), + .lsu_hready(lsu_hready), + .lsu_hresp(lsu_hresp), + .sb_haddr(sb_haddr), + .sb_hburst(sb_hburst), + .sb_hmastlock(sb_hmastlock), + .sb_hprot(sb_hprot), + .sb_hsize(sb_hsize), + .sb_htrans(sb_htrans), + .sb_hwrite(sb_hwrite), + .sb_hwdata(sb_hwdata), + .sb_hrdata(sb_hrdata), + .sb_hready(sb_hready), + .sb_hresp(sb_hresp), + .dma_hsel(dma_hsel), + .dma_haddr(dma_haddr), + .dma_hburst(dma_hburst), + .dma_hmastlock(dma_hmastlock), + .dma_hprot(dma_hprot), + .dma_hsize(dma_hsize), + .dma_htrans(dma_htrans), + .dma_hwrite(dma_hwrite), + .dma_hwdata(dma_hwdata), + .dma_hreadyin(dma_hreadyin), + .dma_hrdata(dma_hrdata), + .dma_hreadyout(dma_hreadyout), + .dma_hresp(dma_hresp), + .lsu_bus_clk_en(lsu_bus_clk_en), + .ifu_bus_clk_en(ifu_bus_clk_en), + .dbg_bus_clk_en(dbg_bus_clk_en), + .dma_bus_clk_en(dma_bus_clk_en), + .dmi_reg_en(dmi_reg_en), + .dmi_reg_addr(dmi_reg_addr), + .dmi_reg_wr_en(dmi_reg_wr_en), + .dmi_reg_wdata(dmi_reg_wdata), + .dmi_reg_rdata(dmi_reg_rdata), + .extintsrc_req(extintsrc_req), + .timer_int(timer_int), + .scan_mode(scan_mode) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veer_el2_wrapper.sv:435:4 + el2_mem mem( + .clk(active_l2clk), + .rst_l(core_rst_l), + .dccm_clk_override(dccm_clk_override), + .icm_clk_override(icm_clk_override), + .dec_tlu_core_ecc_disable(dec_tlu_core_ecc_disable), + .dccm_wren(dccm_wren), + .dccm_rden(dccm_rden), + .dccm_wr_addr_lo(dccm_wr_addr_lo), + .dccm_wr_addr_hi(dccm_wr_addr_hi), + .dccm_rd_addr_lo(dccm_rd_addr_lo), + .dccm_rd_addr_hi(dccm_rd_addr_hi), + .dccm_wr_data_lo(dccm_wr_data_lo), + .dccm_wr_data_hi(dccm_wr_data_hi), + .dccm_rd_data_lo(dccm_rd_data_lo), + .dccm_rd_data_hi(dccm_rd_data_hi), + .dccm_ext_in_pkt(dccm_ext_in_pkt), + .iccm_ext_in_pkt(iccm_ext_in_pkt), + .iccm_rw_addr(iccm_rw_addr), + .iccm_buf_correct_ecc(iccm_buf_correct_ecc), + .iccm_correction_state(iccm_correction_state), + .iccm_wren(iccm_wren), + .iccm_rden(iccm_rden), + .iccm_wr_size(iccm_wr_size), + .iccm_wr_data(iccm_wr_data), + .iccm_rd_data(iccm_rd_data), + .iccm_rd_data_ecc(iccm_rd_data_ecc), + .ic_rw_addr(ic_rw_addr), + .ic_tag_valid(ic_tag_valid), + .ic_wr_en(ic_wr_en), + .ic_rd_en(ic_rd_en), + .ic_premux_data(ic_premux_data), + .ic_sel_premux_data(ic_sel_premux_data), + .ic_data_ext_in_pkt(ic_data_ext_in_pkt), + .ic_tag_ext_in_pkt(ic_tag_ext_in_pkt), + .ic_wr_data(ic_wr_data), + .ic_debug_wr_data(ic_debug_wr_data), + .ic_debug_rd_data(ic_debug_rd_data), + .ic_debug_addr(ic_debug_addr), + .ic_debug_rd_en(ic_debug_rd_en), + .ic_debug_wr_en(ic_debug_wr_en), + .ic_debug_tag_array(ic_debug_tag_array), + .ic_debug_way(ic_debug_way), + .ic_rd_data(ic_rd_data), + .ictag_debug_rd_data(ictag_debug_rd_data), + .ic_eccerr(ic_eccerr), + .ic_parerr(ic_parerr), + .ic_rd_hit(ic_rd_hit), + .ic_tag_perr(ic_tag_perr), + .scan_mode(scan_mode) + ); +endmodule +module dpram64 ( + clk, + we, + din, + waddr, + raddr, + dout +); + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:25:15 + parameter SIZE = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:26:15 + parameter mem_clear = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:27:15 + parameter memfile = ""; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:28:4 + input wire clk; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:29:4 + input wire [7:0] we; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:30:4 + input wire [63:0] din; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:31:4 + input wire [$clog2(SIZE) - 1:0] waddr; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:32:4 + input wire [$clog2(SIZE) - 1:0] raddr; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:33:4 + output reg [63:0] dout; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:35:4 + localparam AW = $clog2(SIZE); + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:37:4 + reg [63:0] mem [0:(SIZE / 8) - 1]; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:39:4 + integer i; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:40:4 + wire [AW - 4:0] wadd = waddr[AW - 1:3]; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:42:4 + always @(posedge clk) begin + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:43:7 + if (we[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:43:18 + mem[wadd][7:0] <= din[7:0]; + if (we[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:44:18 + mem[wadd][15:8] <= din[15:8]; + if (we[2]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:45:18 + mem[wadd][23:16] <= din[23:16]; + if (we[3]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:46:18 + mem[wadd][31:24] <= din[31:24]; + if (we[4]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:47:18 + mem[wadd][39:32] <= din[39:32]; + if (we[5]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:48:18 + mem[wadd][47:40] <= din[47:40]; + if (we[6]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:49:18 + mem[wadd][55:48] <= din[55:48]; + if (we[7]) + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:50:18 + mem[wadd][63:56] <= din[63:56]; + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:51:7 + dout <= mem[raddr[AW - 1:3]]; + end + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:54:4 + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:55:7 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:56:3 + if (mem_clear) + for (i = 0; i < SIZE; i = i + 1) + begin + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:58:7 + mem[i] = 64'd0; + end + if (|memfile) begin + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:60:6 + $display("Preloading %m from %s", memfile); + // Trace: ./src/veerwolf_0.7.5/rtl/dpram64.v:61:6 + $readmemh(memfile, mem); + end + end +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:24:1 +`default_nettype none +module axi2wb ( + i_clk, + i_rst, + o_wb_adr, + o_wb_dat, + o_wb_sel, + o_wb_we, + o_wb_cyc, + o_wb_stb, + i_wb_rdt, + i_wb_ack, + i_wb_err, + i_awaddr, + i_awid, + i_awvalid, + o_awready, + i_araddr, + i_arid, + i_arvalid, + o_arready, + i_wdata, + i_wstrb, + i_wvalid, + o_wready, + o_bid, + o_bresp, + o_bvalid, + i_bready, + o_rdata, + o_rid, + o_rresp, + o_rlast, + o_rvalid, + i_rready +); + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:26:15 + parameter AW = 12; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:27:15 + parameter IW = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:29:4 + input wire i_clk; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:30:4 + input wire i_rst; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:33:4 + output reg [AW - 1:2] o_wb_adr; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:34:4 + output reg [31:0] o_wb_dat; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:35:4 + output reg [3:0] o_wb_sel; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:36:4 + output reg o_wb_we; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:37:4 + output reg o_wb_cyc; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:38:4 + output reg o_wb_stb; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:40:4 + input wire [31:0] i_wb_rdt; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:41:4 + input wire i_wb_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:42:4 + input wire i_wb_err; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:46:4 + input wire [AW - 1:0] i_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:47:4 + input wire [IW - 1:0] i_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:48:4 + input wire i_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:49:4 + output reg o_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:51:4 + input wire [AW - 1:0] i_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:52:4 + input wire [IW - 1:0] i_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:53:4 + input wire i_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:54:4 + output reg o_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:56:4 + input wire [63:0] i_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:57:4 + input wire [7:0] i_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:58:4 + input wire i_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:59:4 + output reg o_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:61:4 + output reg [IW - 1:0] o_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:62:4 + output wire [1:0] o_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:63:4 + output reg o_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:64:4 + input wire i_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:66:4 + output reg [63:0] o_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:67:4 + output reg [IW - 1:0] o_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:68:4 + output wire [1:0] o_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:69:4 + output wire o_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:70:4 + output reg o_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:71:4 + input wire i_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:74:4 + assign o_bresp = 2'b00; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:75:4 + assign o_rresp = 2'b00; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:76:4 + assign o_rlast = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:78:4 + reg hi_32b_w; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:79:4 + reg arbiter; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:80:4 + reg [31:0] wb_rdt_low; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:83:4 + parameter STATESIZE = 4; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:85:4 + parameter [STATESIZE - 1:0] IDLE = 4'd0; + parameter [STATESIZE - 1:0] AWACK = 4'd1; + parameter [STATESIZE - 1:0] WBWACK = 4'd2; + parameter [STATESIZE - 1:0] WBRACK1 = 4'd3; + parameter [STATESIZE - 1:0] WBR2 = 4'd4; + parameter [STATESIZE - 1:0] WBRACK2 = 4'd5; + parameter [STATESIZE - 1:0] BAXI = 4'd6; + parameter [STATESIZE - 1:0] RRAXI = 4'd7; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:95:4 + reg [STATESIZE - 1:0] cs; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:98:4 + reg aw_req; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:99:4 + reg w_req; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:100:4 + reg ar_req; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:103:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:103:12 + o_rvalid = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:104:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:104:12 + o_bvalid = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:105:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:105:12 + o_wb_stb = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:106:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:106:12 + o_wb_cyc = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:107:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:107:12 + o_wb_we = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:108:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:108:12 + cs = 4'd0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:109:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:109:12 + aw_req = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:110:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:110:12 + w_req = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:111:4 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:111:12 + ar_req = 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:114:4 + always @(posedge i_clk) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:115:7 + if (i_rst) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:116:3 + o_awready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:117:3 + o_wready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:118:3 + o_arready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:119:3 + o_rvalid <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:120:3 + o_bvalid <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:121:3 + o_wb_adr <= {AW - 2 {1'b0}}; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:122:3 + o_wb_cyc <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:123:3 + o_wb_stb <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:124:3 + o_wb_sel <= 4'd0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:125:3 + o_wb_we <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:126:3 + arbiter <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:127:3 + wb_rdt_low <= 32'hdeadbeef; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:128:3 + cs <= IDLE; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:130:3 + aw_req <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:131:3 + w_req <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:132:3 + ar_req <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:133:3 + o_bid <= {IW {1'b0}}; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:134:3 + o_rid <= {IW {1'b0}}; + end + else begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:138:3 + if (i_awvalid & o_awready) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:139:5 + o_bid <= i_awid; + if (i_arvalid & o_arready) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:142:5 + o_rid <= i_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:144:3 + o_awready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:145:3 + o_wready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:146:3 + o_arready <= 1'b0; + if (i_awvalid && o_awready) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:149:5 + aw_req <= 1'b1; + else if (i_bready && o_bvalid) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:151:5 + aw_req <= 1'b0; + if (i_wvalid && o_wready) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:154:5 + w_req <= 1'b1; + else if (i_bready && o_bvalid) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:156:5 + w_req <= 1'b0; + if (i_arvalid && o_arready) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:159:5 + ar_req <= 1'b1; + else if (i_rready && o_rvalid) + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:161:5 + ar_req <= 1'b0; + case (cs) + IDLE: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:165:8 + arbiter <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:166:8 + if (i_awvalid && arbiter) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:167:4 + o_wb_adr[AW - 1:3] <= i_awaddr[AW - 1:3]; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:168:4 + o_awready <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:169:4 + arbiter <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:170:4 + if (i_wvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:171:7 + hi_32b_w = (i_wstrb[3:0] == 4'h0 ? 1'b1 : 1'b0); + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:172:7 + o_wb_adr[2] <= hi_32b_w; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:173:7 + o_wb_cyc <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:174:7 + o_wb_stb <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:175:7 + o_wb_sel <= (hi_32b_w ? i_wstrb[7:4] : i_wstrb[3:0]); + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:176:7 + o_wb_dat <= (hi_32b_w ? i_wdata[63:32] : i_wdata[31:0]); + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:177:7 + o_wb_we <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:178:7 + o_wready <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:179:7 + cs <= WBWACK; + end + else + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:182:7 + cs <= AWACK; + end + else if (i_arvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:186:4 + o_wb_adr[AW - 1:2] <= i_araddr[AW - 1:2]; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:187:4 + o_wb_sel <= 4'hf; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:188:4 + o_wb_cyc <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:189:4 + o_wb_stb <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:190:4 + o_arready <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:191:4 + cs <= WBRACK1; + end + end + AWACK: + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:196:8 + if (i_wvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:197:4 + hi_32b_w = (i_wstrb[3:0] == 4'h0 ? 1'b1 : 1'b0); + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:198:4 + o_wb_adr[2] <= hi_32b_w; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:199:4 + o_wb_cyc <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:200:4 + o_wb_stb <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:201:4 + o_wb_sel <= (hi_32b_w ? i_wstrb[7:4] : i_wstrb[3:0]); + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:202:4 + o_wb_dat <= (hi_32b_w ? i_wdata[63:32] : i_wdata[31:0]); + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:203:4 + o_wb_we <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:204:4 + o_wready <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:205:4 + cs <= WBWACK; + end + WBWACK: + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:210:8 + if (i_wb_err || i_wb_ack) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:211:4 + o_wb_cyc <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:212:4 + o_wb_stb <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:213:4 + o_wb_sel <= 4'h0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:214:4 + o_wb_we <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:215:4 + o_bvalid <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:216:4 + cs <= BAXI; + end + WBRACK1: + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:221:8 + if (i_wb_err || i_wb_ack) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:222:4 + o_wb_cyc <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:223:4 + o_wb_stb <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:224:4 + o_wb_sel <= 4'h0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:225:4 + wb_rdt_low <= i_wb_rdt; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:226:4 + cs <= WBR2; + end + WBR2: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:231:8 + o_wb_adr[2] <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:232:8 + o_wb_sel <= 4'hf; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:233:8 + o_wb_cyc <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:234:8 + o_wb_stb <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:235:8 + cs <= WBRACK2; + end + WBRACK2: + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:240:8 + if (i_wb_err || i_wb_ack) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:241:4 + o_wb_cyc <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:242:4 + o_wb_stb <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:243:4 + o_wb_sel <= 4'h0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:244:4 + o_rvalid <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:245:4 + o_rdata <= {i_wb_rdt, wb_rdt_low}; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:246:4 + cs <= RRAXI; + end + BAXI: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:251:8 + o_bvalid <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:252:8 + if (i_bready) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:253:4 + o_bvalid <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:254:4 + cs <= IDLE; + end + end + RRAXI: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:259:8 + o_rvalid <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:260:8 + if (i_rready) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:261:4 + o_rvalid <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:262:4 + cs <= IDLE; + end + end + default: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:267:8 + o_awready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:268:8 + o_wready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:269:8 + o_arready <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:270:8 + o_rvalid <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:271:8 + o_bvalid <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:272:8 + o_wb_adr <= {AW - 2 {1'b0}}; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:273:8 + o_wb_cyc <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:274:8 + o_wb_stb <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:275:8 + o_wb_sel <= 4'd0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:276:8 + o_wb_we <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:277:8 + arbiter <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:278:8 + cs <= IDLE; + end + endcase + end +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/axi2wb.v:410:1 +`default_nettype wire +// Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:24:1 +`default_nettype none +module wb_mem_wrapper ( + i_clk, + i_rst, + i_wb_adr, + i_wb_dat, + i_wb_sel, + i_wb_we, + i_wb_cyc, + i_wb_stb, + o_wb_ack, + o_wb_rdt +); + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:26:15 + parameter MEM_SIZE = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:27:15 + parameter mem_clear = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:28:15 + parameter INIT_FILE = ""; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:30:4 + input wire i_clk; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:31:4 + input wire i_rst; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:32:4 + input wire [$clog2(MEM_SIZE) - 1:2] i_wb_adr; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:33:4 + input wire [31:0] i_wb_dat; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:34:4 + input wire [3:0] i_wb_sel; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:35:4 + input wire i_wb_we; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:36:4 + input wire i_wb_cyc; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:37:4 + input wire i_wb_stb; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:38:4 + output reg o_wb_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:39:4 + output wire [31:0] o_wb_rdt; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:41:4 + wire [31:0] mem_addr; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:42:4 + wire [63:0] mem_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:43:4 + wire [63:0] mem_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:45:4 + wire [7:0] mem_we; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:47:4 + assign mem_we[3:0] = (((i_wb_cyc & i_wb_stb) & i_wb_we) & !i_wb_adr[2] ? i_wb_sel : 4'd0); + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:48:4 + assign mem_we[7:4] = (((i_wb_cyc & i_wb_stb) & i_wb_we) & i_wb_adr[2] ? i_wb_sel : 4'd0); + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:50:4 + assign mem_wdata = {i_wb_dat, i_wb_dat}; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:52:4 + assign o_wb_rdt = (i_wb_adr[2] ? mem_rdata[63:32] : mem_rdata[31:0]); + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:54:4 + always @(posedge i_clk) begin + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:55:7 + o_wb_ack <= (i_wb_cyc & i_wb_stb) & !o_wb_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:56:7 + if (i_rst) + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:57:2 + o_wb_ack <= 1'b0; + end + // Trace: ./src/veerwolf_0.7.5/rtl/wb_mem_wrapper.v:60:4 + dpram64 #( + .SIZE(MEM_SIZE), + .mem_clear(mem_clear), + .memfile(INIT_FILE) + ) ram( + .clk(i_clk), + .we(mem_we), + .din(mem_wdata), + .waddr({i_wb_adr[$clog2(MEM_SIZE) - 1:3], 3'b000}), + .raddr({i_wb_adr[$clog2(MEM_SIZE) - 1:3], 3'b000}), + .dout(mem_rdata) + ); +endmodule +module veerwolf_syscon ( + i_clk, + i_rst, + i_gpio, + o_gpio, + o_timer_irq, + o_sw_irq3, + o_sw_irq4, + i_ram_init_done, + i_ram_init_error, + o_nmi_vec, + o_nmi_int, + i_wb_adr, + i_wb_dat, + i_wb_sel, + i_wb_we, + i_wb_cyc, + i_wb_stb, + o_wb_rdt, + o_wb_ack +); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:25:15 + parameter [31:0] clk_freq_hz = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:26:4 + input wire i_clk; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:27:4 + input wire i_rst; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:29:4 + input wire [63:0] i_gpio; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:30:4 + output reg [63:0] o_gpio; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:31:4 + output reg o_timer_irq; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:32:4 + output wire o_sw_irq3; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:33:4 + output wire o_sw_irq4; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:34:4 + input wire i_ram_init_done; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:35:4 + input wire i_ram_init_error; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:36:4 + output reg [31:0] o_nmi_vec; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:37:4 + output wire o_nmi_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:39:4 + input wire [5:0] i_wb_adr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:40:4 + input wire [31:0] i_wb_dat; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:41:4 + input wire [3:0] i_wb_sel; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:42:4 + input wire i_wb_we; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:43:4 + input wire i_wb_cyc; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:44:4 + input wire i_wb_stb; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:45:4 + output reg [31:0] o_wb_rdt; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:46:4 + output reg o_wb_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:48:4 + reg [63:0] mtime; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:49:4 + reg [63:0] mtimecmp; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:51:4 + reg sw_irq3; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:52:4 + reg sw_irq3_edge; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:53:4 + reg sw_irq3_pol; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:54:4 + reg sw_irq3_timer; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:55:4 + reg sw_irq4; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:56:4 + reg sw_irq4_edge; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:57:4 + reg sw_irq4_pol; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:58:4 + reg sw_irq4_timer; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:60:4 + reg irq_timer_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:61:4 + reg [31:0] irq_timer_cnt; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:63:4 + reg nmi_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:64:4 + reg nmi_int_r; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:96:4 + wire [31:0] version; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:98:4 + assign version[31] = 1; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:99:4 + assign version[30:24] = 127; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:100:4 + assign version[23:16] = 255; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:101:4 + assign version[15:8] = 255; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:102:4 + assign version[7:0] = 255; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:104:4 + assign o_sw_irq4 = sw_irq4 ^ sw_irq4_pol; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:105:4 + assign o_sw_irq3 = sw_irq3 ^ sw_irq3_pol; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:107:4 + assign o_nmi_int = nmi_int | nmi_int_r; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:109:4 + wire reg_we = ((i_wb_cyc & i_wb_stb) & i_wb_we) & !o_wb_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:120:4 + always @(posedge i_clk) begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:121:7 + o_wb_ack <= i_wb_cyc & !o_wb_ack; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:123:7 + if (sw_irq3_edge) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:124:2 + sw_irq3 <= 1'b0; + if (sw_irq4_edge) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:126:2 + sw_irq4 <= 1'b0; + if (irq_timer_en) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:129:2 + irq_timer_cnt <= irq_timer_cnt - 1; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:131:7 + nmi_int <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:132:7 + nmi_int_r <= nmi_int; + if (irq_timer_cnt == 32'd1) begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:135:3 + irq_timer_en <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:136:3 + if (sw_irq3_timer) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:137:5 + sw_irq3 <= 1'b1; + if (sw_irq4_timer) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:139:5 + sw_irq4 <= 1'b1; + if (!(sw_irq3_timer | sw_irq4_timer)) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:141:5 + nmi_int <= 1'b1; + end + if (reg_we) + case (i_wb_adr[5:2]) + 2: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:157:7 + if (i_wb_sel[3]) begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:158:3 + sw_irq4 <= i_wb_dat[31]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:159:3 + sw_irq4_edge <= i_wb_dat[30]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:160:3 + sw_irq4_pol <= i_wb_dat[29]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:161:3 + sw_irq4_timer <= i_wb_dat[28]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:162:3 + sw_irq3 <= i_wb_dat[27]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:163:3 + sw_irq3_edge <= i_wb_dat[26]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:164:3 + sw_irq3_pol <= i_wb_dat[25]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:165:3 + sw_irq3_timer <= i_wb_dat[24]; + end + 3: begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:169:7 + if (i_wb_sel[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:169:24 + o_nmi_vec[7:0] <= i_wb_dat[7:0]; + if (i_wb_sel[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:170:24 + o_nmi_vec[15:8] <= i_wb_dat[15:8]; + if (i_wb_sel[2]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:171:24 + o_nmi_vec[23:16] <= i_wb_dat[23:16]; + if (i_wb_sel[3]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:172:24 + o_nmi_vec[31:24] <= i_wb_dat[31:24]; + end + 4: begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:175:7 + if (i_wb_sel[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:175:24 + o_gpio[7:0] <= i_wb_dat[7:0]; + if (i_wb_sel[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:176:24 + o_gpio[15:8] <= i_wb_dat[15:8]; + if (i_wb_sel[2]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:177:24 + o_gpio[23:16] <= i_wb_dat[23:16]; + if (i_wb_sel[3]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:178:24 + o_gpio[31:24] <= i_wb_dat[31:24]; + end + 6: begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:181:7 + if (i_wb_sel[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:181:24 + o_gpio[39:32] <= i_wb_dat[7:0]; + if (i_wb_sel[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:182:24 + o_gpio[47:40] <= i_wb_dat[15:8]; + if (i_wb_sel[2]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:183:24 + o_gpio[55:48] <= i_wb_dat[23:16]; + if (i_wb_sel[3]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:184:24 + o_gpio[63:56] <= i_wb_dat[31:24]; + end + 10: begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:187:7 + if (i_wb_sel[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:187:24 + mtimecmp[7:0] <= i_wb_dat[7:0]; + if (i_wb_sel[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:188:24 + mtimecmp[15:8] <= i_wb_dat[15:8]; + if (i_wb_sel[2]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:189:24 + mtimecmp[23:16] <= i_wb_dat[23:16]; + if (i_wb_sel[3]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:190:24 + mtimecmp[31:24] <= i_wb_dat[31:24]; + end + 11: begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:193:7 + if (i_wb_sel[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:193:24 + mtimecmp[39:32] <= i_wb_dat[7:0]; + if (i_wb_sel[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:194:24 + mtimecmp[47:40] <= i_wb_dat[15:8]; + if (i_wb_sel[2]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:195:24 + mtimecmp[55:48] <= i_wb_dat[23:16]; + if (i_wb_sel[3]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:196:24 + mtimecmp[63:56] <= i_wb_dat[31:24]; + end + 12: begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:199:7 + if (i_wb_sel[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:199:24 + irq_timer_cnt[7:0] <= i_wb_dat[7:0]; + if (i_wb_sel[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:200:24 + irq_timer_cnt[15:8] <= i_wb_dat[15:8]; + if (i_wb_sel[2]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:201:24 + irq_timer_cnt[23:16] <= i_wb_dat[23:16]; + if (i_wb_sel[3]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:202:24 + irq_timer_cnt[31:24] <= i_wb_dat[31:24]; + end + 13: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:205:7 + if (i_wb_sel[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:206:9 + irq_timer_en <= i_wb_dat[0]; + endcase + case (i_wb_adr[5:2]) + 0: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:212:6 + o_wb_rdt <= version; + 1: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:214:6 + o_wb_rdt <= 32'hdeadbeef; + 2: begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:218:5 + o_wb_rdt[31:28] <= {sw_irq4, sw_irq4_edge, sw_irq4_pol, sw_irq4_timer}; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:219:5 + o_wb_rdt[27:24] <= {sw_irq3, sw_irq3_edge, sw_irq3_pol, sw_irq3_timer}; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:221:5 + o_wb_rdt[23:18] <= 6'd0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:222:5 + o_wb_rdt[17:16] <= {i_ram_init_error, i_ram_init_done}; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:224:5 + o_wb_rdt[15:0] <= 16'd0; + end + 3: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:227:6 + o_wb_rdt <= o_nmi_vec; + 4: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:229:6 + o_wb_rdt <= i_gpio[31:0]; + 6: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:231:6 + o_wb_rdt <= i_gpio[63:32]; + 8: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:233:6 + o_wb_rdt <= mtime[31:0]; + 9: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:235:6 + o_wb_rdt <= mtime[63:32]; + 10: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:237:7 + o_wb_rdt <= mtimecmp[31:0]; + 11: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:239:7 + o_wb_rdt <= mtimecmp[63:32]; + 12: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:241:7 + o_wb_rdt <= irq_timer_cnt; + 13: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:243:7 + o_wb_rdt <= {31'd0, irq_timer_en}; + 15: + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:245:7 + o_wb_rdt <= clk_freq_hz; + endcase + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:248:7 + mtime <= mtime + 64'd1; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:249:7 + o_timer_irq <= mtime >= mtimecmp; + if (i_rst) begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:252:3 + mtime <= 64'd0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:253:3 + mtimecmp <= 64'd0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_syscon.v:254:3 + o_wb_ack <= 1'b0; + end + end +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:24:1 +`default_nettype none +module veerwolf_nospi ( + clk, + rstn, + dmi_reg_en, + dmi_reg_addr, + dmi_reg_wr_en, + dmi_reg_wdata, + dmi_reg_rdata, + dmi_hard_reset, + i_uart_rx, + o_uart_tx, + o_ram_awid, + o_ram_awaddr, + o_ram_awlen, + o_ram_awsize, + o_ram_awburst, + o_ram_awlock, + o_ram_awcache, + o_ram_awprot, + o_ram_awregion, + o_ram_awqos, + o_ram_awvalid, + i_ram_awready, + o_ram_arid, + o_ram_araddr, + o_ram_arlen, + o_ram_arsize, + o_ram_arburst, + o_ram_arlock, + o_ram_arcache, + o_ram_arprot, + o_ram_arregion, + o_ram_arqos, + o_ram_arvalid, + i_ram_arready, + o_ram_wdata, + o_ram_wstrb, + o_ram_wlast, + o_ram_wvalid, + i_ram_wready, + i_ram_bid, + i_ram_bresp, + i_ram_bvalid, + o_ram_bready, + i_ram_rid, + i_ram_rdata, + i_ram_rresp, + i_ram_rlast, + i_ram_rvalid, + o_ram_rready, + i_ram_init_done, + i_ram_init_error, + i_gpio, + o_gpio +); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:26:15 + parameter bootrom_file = ""; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:27:15 + parameter [0:0] insn_trace = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:28:15 + parameter clk_freq_hz = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:29:5 + input wire clk; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:30:5 + input wire rstn; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:31:5 + input wire dmi_reg_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:32:5 + input wire [6:0] dmi_reg_addr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:33:5 + input wire dmi_reg_wr_en; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:34:5 + input wire [31:0] dmi_reg_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:35:5 + output wire [31:0] dmi_reg_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:36:5 + input wire dmi_hard_reset; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:37:5 + input wire i_uart_rx; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:38:5 + output wire o_uart_tx; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:39:5 + output wire [5:0] o_ram_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:40:5 + output wire [31:0] o_ram_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:41:5 + output wire [7:0] o_ram_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:42:5 + output wire [2:0] o_ram_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:43:5 + output wire [1:0] o_ram_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:44:5 + output wire o_ram_awlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:45:5 + output wire [3:0] o_ram_awcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:46:5 + output wire [2:0] o_ram_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:47:5 + output wire [3:0] o_ram_awregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:48:5 + output wire [3:0] o_ram_awqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:49:5 + output wire o_ram_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:50:5 + input wire i_ram_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:51:5 + output wire [5:0] o_ram_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:52:5 + output wire [31:0] o_ram_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:53:5 + output wire [7:0] o_ram_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:54:5 + output wire [2:0] o_ram_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:55:5 + output wire [1:0] o_ram_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:56:5 + output wire o_ram_arlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:57:5 + output wire [3:0] o_ram_arcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:58:5 + output wire [2:0] o_ram_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:59:5 + output wire [3:0] o_ram_arregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:60:5 + output wire [3:0] o_ram_arqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:61:5 + output wire o_ram_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:62:5 + input wire i_ram_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:63:5 + output wire [63:0] o_ram_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:64:5 + output wire [7:0] o_ram_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:65:5 + output wire o_ram_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:66:5 + output wire o_ram_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:67:5 + input wire i_ram_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:68:5 + input wire [5:0] i_ram_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:69:5 + input wire [1:0] i_ram_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:70:5 + input wire i_ram_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:71:5 + output wire o_ram_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:72:5 + input wire [5:0] i_ram_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:73:5 + input wire [63:0] i_ram_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:74:5 + input wire [1:0] i_ram_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:75:5 + input wire i_ram_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:76:5 + input wire i_ram_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:77:5 + output wire o_ram_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:78:5 + input wire i_ram_init_done; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:79:5 + input wire i_ram_init_error; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:80:5 + input wire [63:0] i_gpio; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:81:5 + output wire [63:0] o_gpio; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:83:4 + localparam BOOTROM_SIZE = 32'h00001000; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:85:4 + wire rst_n = rstn; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:86:4 + wire timer_irq; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:87:4 + wire uart_irq; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:88:4 + wire sw_irq4; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:89:4 + wire sw_irq3; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:90:4 + wire nmi_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:92:4 + wire [31:0] nmi_vec; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:3:1 + wire [2:0] ifu_arid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:4:1 + wire [31:0] ifu_araddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:5:1 + wire [7:0] ifu_arlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:6:1 + wire [2:0] ifu_arsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:7:1 + wire [1:0] ifu_arburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:8:1 + wire ifu_arlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:9:1 + wire [3:0] ifu_arcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:10:1 + wire [2:0] ifu_arprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:11:1 + wire [3:0] ifu_arregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:12:1 + wire [3:0] ifu_arqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:13:1 + wire ifu_arvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:14:1 + wire ifu_arready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:15:1 + wire [2:0] ifu_rid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:16:1 + wire [63:0] ifu_rdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:17:1 + wire [1:0] ifu_rresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:18:1 + wire ifu_rlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:19:1 + wire ifu_rvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:20:1 + wire ifu_rready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:21:1 + wire [3:0] lsu_awid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:22:1 + wire [31:0] lsu_awaddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:23:1 + wire [7:0] lsu_awlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:24:1 + wire [2:0] lsu_awsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:25:1 + wire [1:0] lsu_awburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:26:1 + wire lsu_awlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:27:1 + wire [3:0] lsu_awcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:28:1 + wire [2:0] lsu_awprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:29:1 + wire [3:0] lsu_awregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:30:1 + wire [3:0] lsu_awqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:31:1 + wire lsu_awvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:32:1 + wire lsu_awready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:33:1 + wire [3:0] lsu_arid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:34:1 + wire [31:0] lsu_araddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:35:1 + wire [7:0] lsu_arlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:36:1 + wire [2:0] lsu_arsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:37:1 + wire [1:0] lsu_arburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:38:1 + wire lsu_arlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:39:1 + wire [3:0] lsu_arcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:40:1 + wire [2:0] lsu_arprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:41:1 + wire [3:0] lsu_arregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:42:1 + wire [3:0] lsu_arqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:43:1 + wire lsu_arvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:44:1 + wire lsu_arready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:45:1 + wire [63:0] lsu_wdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:46:1 + wire [7:0] lsu_wstrb; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:47:1 + wire lsu_wlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:48:1 + wire lsu_wvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:49:1 + wire lsu_wready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:50:1 + wire [3:0] lsu_bid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:51:1 + wire [1:0] lsu_bresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:52:1 + wire lsu_bvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:53:1 + wire lsu_bready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:54:1 + wire [3:0] lsu_rid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:55:1 + wire [63:0] lsu_rdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:56:1 + wire [1:0] lsu_rresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:57:1 + wire lsu_rlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:58:1 + wire lsu_rvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:59:1 + wire lsu_rready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:60:1 + wire [0:0] sb_awid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:61:1 + wire [31:0] sb_awaddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:62:1 + wire [7:0] sb_awlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:63:1 + wire [2:0] sb_awsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:64:1 + wire [1:0] sb_awburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:65:1 + wire sb_awlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:66:1 + wire [3:0] sb_awcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:67:1 + wire [2:0] sb_awprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:68:1 + wire [3:0] sb_awregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:69:1 + wire [3:0] sb_awqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:70:1 + wire sb_awvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:71:1 + wire sb_awready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:72:1 + wire [0:0] sb_arid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:73:1 + wire [31:0] sb_araddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:74:1 + wire [7:0] sb_arlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:75:1 + wire [2:0] sb_arsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:76:1 + wire [1:0] sb_arburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:77:1 + wire sb_arlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:78:1 + wire [3:0] sb_arcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:79:1 + wire [2:0] sb_arprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:80:1 + wire [3:0] sb_arregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:81:1 + wire [3:0] sb_arqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:82:1 + wire sb_arvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:83:1 + wire sb_arready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:84:1 + wire [63:0] sb_wdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:85:1 + wire [7:0] sb_wstrb; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:86:1 + wire sb_wlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:87:1 + wire sb_wvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:88:1 + wire sb_wready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:89:1 + wire [0:0] sb_bid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:90:1 + wire [1:0] sb_bresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:91:1 + wire sb_bvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:92:1 + wire sb_bready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:93:1 + wire [0:0] sb_rid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:94:1 + wire [63:0] sb_rdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:95:1 + wire [1:0] sb_rresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:96:1 + wire sb_rlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:97:1 + wire sb_rvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:98:1 + wire sb_rready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:99:1 + wire [5:0] io_awid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:100:1 + wire [31:0] io_awaddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:101:1 + wire [7:0] io_awlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:102:1 + wire [2:0] io_awsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:103:1 + wire [1:0] io_awburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:104:1 + wire io_awlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:105:1 + wire [3:0] io_awcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:106:1 + wire [2:0] io_awprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:107:1 + wire [3:0] io_awregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:108:1 + wire [3:0] io_awqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:109:1 + wire io_awvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:110:1 + wire io_awready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:111:1 + wire [5:0] io_arid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:112:1 + wire [31:0] io_araddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:113:1 + wire [7:0] io_arlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:114:1 + wire [2:0] io_arsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:115:1 + wire [1:0] io_arburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:116:1 + wire io_arlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:117:1 + wire [3:0] io_arcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:118:1 + wire [2:0] io_arprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:119:1 + wire [3:0] io_arregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:120:1 + wire [3:0] io_arqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:121:1 + wire io_arvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:122:1 + wire io_arready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:123:1 + wire [63:0] io_wdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:124:1 + wire [7:0] io_wstrb; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:125:1 + wire io_wlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:126:1 + wire io_wvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:127:1 + wire io_wready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:128:1 + wire [5:0] io_bid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:129:1 + wire [1:0] io_bresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:130:1 + wire io_bvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:131:1 + wire io_bready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:132:1 + wire [5:0] io_rid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:133:1 + wire [63:0] io_rdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:134:1 + wire [1:0] io_rresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:135:1 + wire io_rlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:136:1 + wire io_rvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:137:1 + wire io_rready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:138:1 + wire [5:0] ram_awid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:139:1 + wire [31:0] ram_awaddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:140:1 + wire [7:0] ram_awlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:141:1 + wire [2:0] ram_awsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:142:1 + wire [1:0] ram_awburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:143:1 + wire ram_awlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:144:1 + wire [3:0] ram_awcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:145:1 + wire [2:0] ram_awprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:146:1 + wire [3:0] ram_awregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:147:1 + wire [3:0] ram_awqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:148:1 + wire ram_awvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:149:1 + wire ram_awready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:150:1 + wire [5:0] ram_arid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:151:1 + wire [31:0] ram_araddr; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:152:1 + wire [7:0] ram_arlen; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:153:1 + wire [2:0] ram_arsize; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:154:1 + wire [1:0] ram_arburst; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:155:1 + wire ram_arlock; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:156:1 + wire [3:0] ram_arcache; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:157:1 + wire [2:0] ram_arprot; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:158:1 + wire [3:0] ram_arregion; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:159:1 + wire [3:0] ram_arqos; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:160:1 + wire ram_arvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:161:1 + wire ram_arready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:162:1 + wire [63:0] ram_wdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:163:1 + wire [7:0] ram_wstrb; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:164:1 + wire ram_wlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:165:1 + wire ram_wvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:166:1 + wire ram_wready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:167:1 + wire [5:0] ram_bid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:168:1 + wire [1:0] ram_bresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:169:1 + wire ram_bvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:170:1 + wire ram_bready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:171:1 + wire [5:0] ram_rid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:172:1 + wire [63:0] ram_rdata; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:173:1 + wire [1:0] ram_rresp; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:174:1 + wire ram_rlast; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:175:1 + wire ram_rvalid; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:176:1 + wire ram_rready; + // Trace: src/veerwolf-intercon_0.7.5/axi_intercon.vh:178:1 + axi_intercon axi_intercon( + .clk_i(clk), + .rst_ni(rst_n), + .i_ifu_arid(ifu_arid), + .i_ifu_araddr(ifu_araddr), + .i_ifu_arlen(ifu_arlen), + .i_ifu_arsize(ifu_arsize), + .i_ifu_arburst(ifu_arburst), + .i_ifu_arlock(ifu_arlock), + .i_ifu_arcache(ifu_arcache), + .i_ifu_arprot(ifu_arprot), + .i_ifu_arregion(ifu_arregion), + .i_ifu_arqos(ifu_arqos), + .i_ifu_arvalid(ifu_arvalid), + .o_ifu_arready(ifu_arready), + .o_ifu_rid(ifu_rid), + .o_ifu_rdata(ifu_rdata), + .o_ifu_rresp(ifu_rresp), + .o_ifu_rlast(ifu_rlast), + .o_ifu_rvalid(ifu_rvalid), + .i_ifu_rready(ifu_rready), + .i_lsu_awid(lsu_awid), + .i_lsu_awaddr(lsu_awaddr), + .i_lsu_awlen(lsu_awlen), + .i_lsu_awsize(lsu_awsize), + .i_lsu_awburst(lsu_awburst), + .i_lsu_awlock(lsu_awlock), + .i_lsu_awcache(lsu_awcache), + .i_lsu_awprot(lsu_awprot), + .i_lsu_awregion(lsu_awregion), + .i_lsu_awqos(lsu_awqos), + .i_lsu_awvalid(lsu_awvalid), + .o_lsu_awready(lsu_awready), + .i_lsu_arid(lsu_arid), + .i_lsu_araddr(lsu_araddr), + .i_lsu_arlen(lsu_arlen), + .i_lsu_arsize(lsu_arsize), + .i_lsu_arburst(lsu_arburst), + .i_lsu_arlock(lsu_arlock), + .i_lsu_arcache(lsu_arcache), + .i_lsu_arprot(lsu_arprot), + .i_lsu_arregion(lsu_arregion), + .i_lsu_arqos(lsu_arqos), + .i_lsu_arvalid(lsu_arvalid), + .o_lsu_arready(lsu_arready), + .i_lsu_wdata(lsu_wdata), + .i_lsu_wstrb(lsu_wstrb), + .i_lsu_wlast(lsu_wlast), + .i_lsu_wvalid(lsu_wvalid), + .o_lsu_wready(lsu_wready), + .o_lsu_bid(lsu_bid), + .o_lsu_bresp(lsu_bresp), + .o_lsu_bvalid(lsu_bvalid), + .i_lsu_bready(lsu_bready), + .o_lsu_rid(lsu_rid), + .o_lsu_rdata(lsu_rdata), + .o_lsu_rresp(lsu_rresp), + .o_lsu_rlast(lsu_rlast), + .o_lsu_rvalid(lsu_rvalid), + .i_lsu_rready(lsu_rready), + .i_sb_awid(sb_awid), + .i_sb_awaddr(sb_awaddr), + .i_sb_awlen(sb_awlen), + .i_sb_awsize(sb_awsize), + .i_sb_awburst(sb_awburst), + .i_sb_awlock(sb_awlock), + .i_sb_awcache(sb_awcache), + .i_sb_awprot(sb_awprot), + .i_sb_awregion(sb_awregion), + .i_sb_awqos(sb_awqos), + .i_sb_awvalid(sb_awvalid), + .o_sb_awready(sb_awready), + .i_sb_arid(sb_arid), + .i_sb_araddr(sb_araddr), + .i_sb_arlen(sb_arlen), + .i_sb_arsize(sb_arsize), + .i_sb_arburst(sb_arburst), + .i_sb_arlock(sb_arlock), + .i_sb_arcache(sb_arcache), + .i_sb_arprot(sb_arprot), + .i_sb_arregion(sb_arregion), + .i_sb_arqos(sb_arqos), + .i_sb_arvalid(sb_arvalid), + .o_sb_arready(sb_arready), + .i_sb_wdata(sb_wdata), + .i_sb_wstrb(sb_wstrb), + .i_sb_wlast(sb_wlast), + .i_sb_wvalid(sb_wvalid), + .o_sb_wready(sb_wready), + .o_sb_bid(sb_bid), + .o_sb_bresp(sb_bresp), + .o_sb_bvalid(sb_bvalid), + .i_sb_bready(sb_bready), + .o_sb_rid(sb_rid), + .o_sb_rdata(sb_rdata), + .o_sb_rresp(sb_rresp), + .o_sb_rlast(sb_rlast), + .o_sb_rvalid(sb_rvalid), + .i_sb_rready(sb_rready), + .o_io_awid(io_awid), + .o_io_awaddr(io_awaddr), + .o_io_awlen(io_awlen), + .o_io_awsize(io_awsize), + .o_io_awburst(io_awburst), + .o_io_awlock(io_awlock), + .o_io_awcache(io_awcache), + .o_io_awprot(io_awprot), + .o_io_awregion(io_awregion), + .o_io_awqos(io_awqos), + .o_io_awvalid(io_awvalid), + .i_io_awready(io_awready), + .o_io_arid(io_arid), + .o_io_araddr(io_araddr), + .o_io_arlen(io_arlen), + .o_io_arsize(io_arsize), + .o_io_arburst(io_arburst), + .o_io_arlock(io_arlock), + .o_io_arcache(io_arcache), + .o_io_arprot(io_arprot), + .o_io_arregion(io_arregion), + .o_io_arqos(io_arqos), + .o_io_arvalid(io_arvalid), + .i_io_arready(io_arready), + .o_io_wdata(io_wdata), + .o_io_wstrb(io_wstrb), + .o_io_wlast(io_wlast), + .o_io_wvalid(io_wvalid), + .i_io_wready(io_wready), + .i_io_bid(io_bid), + .i_io_bresp(io_bresp), + .i_io_bvalid(io_bvalid), + .o_io_bready(io_bready), + .i_io_rid(io_rid), + .i_io_rdata(io_rdata), + .i_io_rresp(io_rresp), + .i_io_rlast(io_rlast), + .i_io_rvalid(io_rvalid), + .o_io_rready(io_rready), + .o_ram_awid(ram_awid), + .o_ram_awaddr(ram_awaddr), + .o_ram_awlen(ram_awlen), + .o_ram_awsize(ram_awsize), + .o_ram_awburst(ram_awburst), + .o_ram_awlock(ram_awlock), + .o_ram_awcache(ram_awcache), + .o_ram_awprot(ram_awprot), + .o_ram_awregion(ram_awregion), + .o_ram_awqos(ram_awqos), + .o_ram_awvalid(ram_awvalid), + .i_ram_awready(ram_awready), + .o_ram_arid(ram_arid), + .o_ram_araddr(ram_araddr), + .o_ram_arlen(ram_arlen), + .o_ram_arsize(ram_arsize), + .o_ram_arburst(ram_arburst), + .o_ram_arlock(ram_arlock), + .o_ram_arcache(ram_arcache), + .o_ram_arprot(ram_arprot), + .o_ram_arregion(ram_arregion), + .o_ram_arqos(ram_arqos), + .o_ram_arvalid(ram_arvalid), + .i_ram_arready(ram_arready), + .o_ram_wdata(ram_wdata), + .o_ram_wstrb(ram_wstrb), + .o_ram_wlast(ram_wlast), + .o_ram_wvalid(ram_wvalid), + .i_ram_wready(ram_wready), + .i_ram_bid(ram_bid), + .i_ram_bresp(ram_bresp), + .i_ram_bvalid(ram_bvalid), + .o_ram_bready(ram_bready), + .i_ram_rid(ram_rid), + .i_ram_rdata(ram_rdata), + .i_ram_rresp(ram_rresp), + .i_ram_rlast(ram_rlast), + .i_ram_rvalid(ram_rvalid), + .o_ram_rready(ram_rready) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:96:4 + assign o_ram_awid = ram_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:97:4 + assign o_ram_awaddr = ram_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:98:4 + assign o_ram_awlen = ram_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:99:4 + assign o_ram_awsize = ram_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:100:4 + assign o_ram_awburst = ram_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:101:4 + assign o_ram_awlock = ram_awlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:102:4 + assign o_ram_awcache = ram_awcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:103:4 + assign o_ram_awprot = ram_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:104:4 + assign o_ram_awregion = ram_awregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:105:4 + assign o_ram_awqos = ram_awqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:106:4 + assign o_ram_awvalid = ram_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:107:4 + assign ram_awready = i_ram_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:108:4 + assign o_ram_arid = ram_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:109:4 + assign o_ram_araddr = ram_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:110:4 + assign o_ram_arlen = ram_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:111:4 + assign o_ram_arsize = ram_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:112:4 + assign o_ram_arburst = ram_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:113:4 + assign o_ram_arlock = ram_arlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:114:4 + assign o_ram_arcache = ram_arcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:115:4 + assign o_ram_arprot = ram_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:116:4 + assign o_ram_arregion = ram_arregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:117:4 + assign o_ram_arqos = ram_arqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:118:4 + assign o_ram_arvalid = ram_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:119:4 + assign ram_arready = i_ram_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:120:4 + assign o_ram_wdata = ram_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:121:4 + assign o_ram_wstrb = ram_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:122:4 + assign o_ram_wlast = ram_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:123:4 + assign o_ram_wvalid = ram_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:124:4 + assign ram_wready = i_ram_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:125:4 + assign ram_bid = i_ram_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:126:4 + assign ram_bresp = i_ram_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:127:4 + assign ram_bvalid = i_ram_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:128:4 + assign o_ram_bready = ram_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:129:4 + assign ram_rid = i_ram_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:130:4 + assign ram_rdata = i_ram_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:131:4 + assign ram_rresp = i_ram_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:132:4 + assign ram_rlast = i_ram_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:133:4 + assign ram_rvalid = i_ram_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:134:4 + assign o_ram_rready = ram_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:136:4 + wire wb_clk = clk; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:137:4 + wire wb_rst = ~rst_n; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:1:1 + wire [31:0] wb_io_adr; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:2:1 + wire [31:0] wb_io_dat; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:3:1 + wire [3:0] wb_io_sel; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:4:1 + wire wb_io_we; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:5:1 + wire wb_io_cyc; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:6:1 + wire wb_io_stb; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:7:1 + wire [2:0] wb_io_cti; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:8:1 + wire [1:0] wb_io_bte; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:9:1 + wire [31:0] wb_io_rdt; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:10:1 + wire wb_io_ack; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:11:1 + wire wb_io_err; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:12:1 + wire wb_io_rty; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:13:1 + wire [31:0] wb_rom_adr; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:14:1 + wire [31:0] wb_rom_dat; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:15:1 + wire [3:0] wb_rom_sel; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:16:1 + wire wb_rom_we; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:17:1 + wire wb_rom_cyc; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:18:1 + wire wb_rom_stb; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:19:1 + wire [2:0] wb_rom_cti; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:20:1 + wire [1:0] wb_rom_bte; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:21:1 + wire [31:0] wb_rom_rdt; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:22:1 + wire wb_rom_ack; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:23:1 + wire wb_rom_err; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:24:1 + wire wb_rom_rty; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:25:1 + wire [31:0] wb_sys_adr; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:26:1 + wire [31:0] wb_sys_dat; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:27:1 + wire [3:0] wb_sys_sel; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:28:1 + wire wb_sys_we; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:29:1 + wire wb_sys_cyc; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:30:1 + wire wb_sys_stb; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:31:1 + wire [2:0] wb_sys_cti; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:32:1 + wire [1:0] wb_sys_bte; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:33:1 + wire [31:0] wb_sys_rdt; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:34:1 + wire wb_sys_ack; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:35:1 + wire wb_sys_err; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:36:1 + wire wb_sys_rty; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:37:1 + wire [31:0] wb_uart_adr; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:38:1 + wire [31:0] wb_uart_dat; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:39:1 + wire [3:0] wb_uart_sel; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:40:1 + wire wb_uart_we; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:41:1 + wire wb_uart_cyc; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:42:1 + wire wb_uart_stb; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:43:1 + wire [2:0] wb_uart_cti; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:44:1 + wire [1:0] wb_uart_bte; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:45:1 + wire [31:0] wb_uart_rdt; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:46:1 + wire wb_uart_ack; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:47:1 + wire wb_uart_err; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:48:1 + wire wb_uart_rty; + // Trace: src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.vh:50:1 + wb_intercon wb_intercon0( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_io_adr_i(wb_io_adr), + .wb_io_dat_i(wb_io_dat), + .wb_io_sel_i(wb_io_sel), + .wb_io_we_i(wb_io_we), + .wb_io_cyc_i(wb_io_cyc), + .wb_io_stb_i(wb_io_stb), + .wb_io_cti_i(wb_io_cti), + .wb_io_bte_i(wb_io_bte), + .wb_io_rdt_o(wb_io_rdt), + .wb_io_ack_o(wb_io_ack), + .wb_io_err_o(wb_io_err), + .wb_io_rty_o(wb_io_rty), + .wb_rom_adr_o(wb_rom_adr), + .wb_rom_dat_o(wb_rom_dat), + .wb_rom_sel_o(wb_rom_sel), + .wb_rom_we_o(wb_rom_we), + .wb_rom_cyc_o(wb_rom_cyc), + .wb_rom_stb_o(wb_rom_stb), + .wb_rom_cti_o(wb_rom_cti), + .wb_rom_bte_o(wb_rom_bte), + .wb_rom_rdt_i(wb_rom_rdt), + .wb_rom_ack_i(wb_rom_ack), + .wb_rom_err_i(wb_rom_err), + .wb_rom_rty_i(wb_rom_rty), + .wb_sys_adr_o(wb_sys_adr), + .wb_sys_dat_o(wb_sys_dat), + .wb_sys_sel_o(wb_sys_sel), + .wb_sys_we_o(wb_sys_we), + .wb_sys_cyc_o(wb_sys_cyc), + .wb_sys_stb_o(wb_sys_stb), + .wb_sys_cti_o(wb_sys_cti), + .wb_sys_bte_o(wb_sys_bte), + .wb_sys_rdt_i(wb_sys_rdt), + .wb_sys_ack_i(wb_sys_ack), + .wb_sys_err_i(wb_sys_err), + .wb_sys_rty_i(wb_sys_rty), + .wb_uart_adr_o(wb_uart_adr), + .wb_uart_dat_o(wb_uart_dat), + .wb_uart_sel_o(wb_uart_sel), + .wb_uart_we_o(wb_uart_we), + .wb_uart_cyc_o(wb_uart_cyc), + .wb_uart_stb_o(wb_uart_stb), + .wb_uart_cti_o(wb_uart_cti), + .wb_uart_bte_o(wb_uart_bte), + .wb_uart_rdt_i(wb_uart_rdt), + .wb_uart_ack_i(wb_uart_ack), + .wb_uart_err_i(wb_uart_err), + .wb_uart_rty_i(wb_uart_rty) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:141:4 + wire [15:2] wb_adr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:143:4 + assign wb_io_adr = {16'd0, wb_adr, 2'b00}; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:144:4 + assign wb_io_cti = 3'b000; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:145:4 + assign wb_io_bte = 2'b00; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:147:4 + axi2wb #( + .AW(16), + .IW(6) + ) axi2wb( + .i_clk(clk), + .i_rst(~rst_n), + .o_wb_adr(wb_adr), + .o_wb_dat(wb_io_dat), + .o_wb_sel(wb_io_sel), + .o_wb_we(wb_io_we), + .o_wb_cyc(wb_io_cyc), + .o_wb_stb(wb_io_stb), + .i_wb_rdt(wb_io_rdt), + .i_wb_ack(wb_io_ack), + .i_wb_err(wb_io_err), + .i_awaddr(io_awaddr[15:0]), + .i_awid(io_awid), + .i_awvalid(io_awvalid), + .o_awready(io_awready), + .i_araddr(io_araddr[15:0]), + .i_arid(io_arid), + .i_arvalid(io_arvalid), + .o_arready(io_arready), + .i_wdata(io_wdata), + .i_wstrb(io_wstrb), + .i_wvalid(io_wvalid), + .o_wready(io_wready), + .o_bid(io_bid), + .o_bresp(io_bresp), + .o_bvalid(io_bvalid), + .i_bready(io_bready), + .o_rdata(io_rdata), + .o_rid(io_rid), + .o_rresp(io_rresp), + .o_rlast(io_rlast), + .o_rvalid(io_rvalid), + .i_rready(io_rready) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:191:4 + wb_mem_wrapper #( + .MEM_SIZE(BOOTROM_SIZE), + .INIT_FILE(bootrom_file) + ) bootrom( + .i_clk(wb_clk), + .i_rst(wb_rst), + .i_wb_adr(wb_rom_adr[$clog2(32'h00001000) - 1:2]), + .i_wb_dat(wb_rom_dat), + .i_wb_sel(wb_rom_sel), + .i_wb_we(wb_rom_we), + .i_wb_cyc(wb_rom_cyc), + .i_wb_stb(wb_rom_stb), + .o_wb_rdt(wb_rom_rdt), + .o_wb_ack(wb_rom_ack) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:206:4 + assign wb_rom_err = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:207:4 + assign wb_rom_rty = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:209:4 + veerwolf_syscon #(.clk_freq_hz(clk_freq_hz)) syscon( + .i_clk(clk), + .i_rst(wb_rst), + .i_gpio(i_gpio), + .o_gpio(o_gpio), + .o_timer_irq(timer_irq), + .o_sw_irq3(sw_irq3), + .o_sw_irq4(sw_irq4), + .i_ram_init_done(i_ram_init_done), + .i_ram_init_error(i_ram_init_error), + .o_nmi_vec(nmi_vec), + .o_nmi_int(nmi_int), + .i_wb_adr(wb_sys_adr[5:0]), + .i_wb_dat(wb_sys_dat), + .i_wb_sel(wb_sys_sel), + .i_wb_we(wb_sys_we), + .i_wb_cyc(wb_sys_cyc), + .i_wb_stb(wb_sys_stb), + .o_wb_rdt(wb_sys_rdt), + .o_wb_ack(wb_sys_ack) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:234:4 + assign wb_sys_err = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:235:4 + assign wb_sys_rty = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:237:4 + wire [7:0] uart_rdt; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:238:4 + assign wb_uart_rdt = {24'd0, uart_rdt}; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:239:4 + assign wb_uart_err = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:240:4 + assign wb_uart_rty = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:242:4 + uart_top uart16550_0( + .wb_clk_i(clk), + .wb_rst_i(~rst_n), + .wb_adr_i(wb_uart_adr[4:2]), + .wb_dat_i(wb_uart_dat[7:0]), + .wb_we_i(wb_uart_we), + .wb_cyc_i(wb_uart_cyc), + .wb_stb_i(wb_uart_stb), + .wb_sel_i(4'b0000), + .wb_dat_o(uart_rdt), + .wb_ack_o(wb_uart_ack), + .int_o(uart_irq), + .stx_pad_o(o_uart_tx), + .rts_pad_o(), + .dtr_pad_o(), + .srx_pad_i(i_uart_rx), + .cts_pad_i(1'b0), + .dsr_pad_i(1'b0), + .ri_pad_i(1'b0), + .dcd_pad_i(1'b0) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:268:4 + wire [2:0] valid_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:269:4 + wire [63:0] address_ip; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:270:4 + generate + if (insn_trace) begin : genblk1 + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:273:3 + integer tf; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:275:3 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:275:11 + tf = $fopen("trace.bin", "wb"); + end + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:277:3 + always @(posedge clk) begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:278:6 + if (valid_ip[0]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:278:23 + $fwrite(tf, "%u", address_ip[31:0]); + if (valid_ip[1]) + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:279:23 + $fwrite(tf, "%u", address_ip[63:32]); + end + end + endgenerate + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:291:4 + wire [2:0] lsu_awid_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:292:4 + wire [2:0] lsu_arid_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:293:4 + wire [2:0] lsu_bid_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:294:4 + wire [2:0] lsu_rid_int; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:296:4 + function automatic [3:0] sv2v_cast_4; + input reg [3:0] inp; + sv2v_cast_4 = inp; + endfunction + assign lsu_awid = sv2v_cast_4(lsu_awid_int); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:297:4 + assign lsu_arid = sv2v_cast_4(lsu_arid_int); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:298:4 + assign lsu_bid_int = lsu_bid[2:0]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:299:4 + assign lsu_rid_int = lsu_rid[2:0]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_nospi.v:301:4 + veer_wrapper_dmi rvtop( + .clk(clk), + .rst_l(rstn), + .dbg_rst_l(rstn), + .rst_vec(31'h40000000), + .nmi_int(nmi_int), + .nmi_vec(nmi_vec[31:1]), + .trace_rv_i_insn_ip(), + .trace_rv_i_address_ip(address_ip), + .trace_rv_i_valid_ip(valid_ip), + .trace_rv_i_exception_ip(), + .trace_rv_i_ecause_ip(), + .trace_rv_i_interrupt_ip(), + .trace_rv_i_tval_ip(), + .lsu_axi_awvalid(lsu_awvalid), + .lsu_axi_awready(lsu_awready), + .lsu_axi_awid(lsu_awid_int), + .lsu_axi_awaddr(lsu_awaddr), + .lsu_axi_awregion(lsu_awregion), + .lsu_axi_awlen(lsu_awlen), + .lsu_axi_awsize(lsu_awsize), + .lsu_axi_awburst(lsu_awburst), + .lsu_axi_awlock(lsu_awlock), + .lsu_axi_awcache(lsu_awcache), + .lsu_axi_awprot(lsu_awprot), + .lsu_axi_awqos(lsu_awqos), + .lsu_axi_wvalid(lsu_wvalid), + .lsu_axi_wready(lsu_wready), + .lsu_axi_wdata(lsu_wdata), + .lsu_axi_wstrb(lsu_wstrb), + .lsu_axi_wlast(lsu_wlast), + .lsu_axi_bvalid(lsu_bvalid), + .lsu_axi_bready(lsu_bready), + .lsu_axi_bresp(lsu_bresp), + .lsu_axi_bid(lsu_bid_int), + .lsu_axi_arvalid(lsu_arvalid), + .lsu_axi_arready(lsu_arready), + .lsu_axi_arid(lsu_arid_int), + .lsu_axi_araddr(lsu_araddr), + .lsu_axi_arregion(lsu_arregion), + .lsu_axi_arlen(lsu_arlen), + .lsu_axi_arsize(lsu_arsize), + .lsu_axi_arburst(lsu_arburst), + .lsu_axi_arlock(lsu_arlock), + .lsu_axi_arcache(lsu_arcache), + .lsu_axi_arprot(lsu_arprot), + .lsu_axi_arqos(lsu_arqos), + .lsu_axi_rvalid(lsu_rvalid), + .lsu_axi_rready(lsu_rready), + .lsu_axi_rid(lsu_rid_int), + .lsu_axi_rdata(lsu_rdata), + .lsu_axi_rresp(lsu_rresp), + .lsu_axi_rlast(lsu_rlast), + .ifu_axi_awvalid(), + .ifu_axi_awready(1'b0), + .ifu_axi_awid(), + .ifu_axi_awaddr(), + .ifu_axi_awregion(), + .ifu_axi_awlen(), + .ifu_axi_awsize(), + .ifu_axi_awburst(), + .ifu_axi_awlock(), + .ifu_axi_awcache(), + .ifu_axi_awprot(), + .ifu_axi_awqos(), + .ifu_axi_wvalid(), + .ifu_axi_wready(1'b0), + .ifu_axi_wdata(), + .ifu_axi_wstrb(), + .ifu_axi_wlast(), + .ifu_axi_bvalid(1'b0), + .ifu_axi_bready(), + .ifu_axi_bresp(2'b00), + .ifu_axi_bid(3'd0), + .ifu_axi_arvalid(ifu_arvalid), + .ifu_axi_arready(ifu_arready), + .ifu_axi_arid(ifu_arid), + .ifu_axi_araddr(ifu_araddr), + .ifu_axi_arregion(ifu_arregion), + .ifu_axi_arlen(ifu_arlen), + .ifu_axi_arsize(ifu_arsize), + .ifu_axi_arburst(ifu_arburst), + .ifu_axi_arlock(ifu_arlock), + .ifu_axi_arcache(ifu_arcache), + .ifu_axi_arprot(ifu_arprot), + .ifu_axi_arqos(ifu_arqos), + .ifu_axi_rvalid(ifu_rvalid), + .ifu_axi_rready(ifu_rready), + .ifu_axi_rid(ifu_rid), + .ifu_axi_rdata(ifu_rdata), + .ifu_axi_rresp(ifu_rresp), + .ifu_axi_rlast(ifu_rlast), + .sb_axi_awvalid(sb_awvalid), + .sb_axi_awready(sb_awready), + .sb_axi_awid(sb_awid), + .sb_axi_awaddr(sb_awaddr), + .sb_axi_awregion(sb_awregion), + .sb_axi_awlen(sb_awlen), + .sb_axi_awsize(sb_awsize), + .sb_axi_awburst(sb_awburst), + .sb_axi_awlock(sb_awlock), + .sb_axi_awcache(sb_awcache), + .sb_axi_awprot(sb_awprot), + .sb_axi_awqos(sb_awqos), + .sb_axi_wvalid(sb_wvalid), + .sb_axi_wready(sb_wready), + .sb_axi_wdata(sb_wdata), + .sb_axi_wstrb(sb_wstrb), + .sb_axi_wlast(sb_wlast), + .sb_axi_bvalid(sb_bvalid), + .sb_axi_bready(sb_bready), + .sb_axi_bresp(sb_bresp), + .sb_axi_bid(sb_bid), + .sb_axi_arvalid(sb_arvalid), + .sb_axi_arready(sb_arready), + .sb_axi_arid(sb_arid), + .sb_axi_araddr(sb_araddr), + .sb_axi_arregion(sb_arregion), + .sb_axi_arlen(sb_arlen), + .sb_axi_arsize(sb_arsize), + .sb_axi_arburst(sb_arburst), + .sb_axi_arlock(sb_arlock), + .sb_axi_arcache(sb_arcache), + .sb_axi_arprot(sb_arprot), + .sb_axi_arqos(sb_arqos), + .sb_axi_rvalid(sb_rvalid), + .sb_axi_rready(sb_rready), + .sb_axi_rid(sb_rid), + .sb_axi_rdata(sb_rdata), + .sb_axi_rresp(sb_rresp), + .sb_axi_rlast(sb_rlast), + .dma_axi_awvalid(1'b0), + .dma_axi_awready(), + .dma_axi_awid(1'd0), + .dma_axi_awaddr(32'd0), + .dma_axi_awsize(3'd0), + .dma_axi_awprot(3'd0), + .dma_axi_awlen(8'd0), + .dma_axi_awburst(2'd0), + .dma_axi_wvalid(1'b0), + .dma_axi_wready(), + .dma_axi_wdata(64'd0), + .dma_axi_wstrb(8'd0), + .dma_axi_wlast(1'b0), + .dma_axi_bvalid(), + .dma_axi_bready(1'b0), + .dma_axi_bresp(), + .dma_axi_bid(), + .dma_axi_arvalid(1'b0), + .dma_axi_arready(), + .dma_axi_arid(1'd0), + .dma_axi_araddr(32'd0), + .dma_axi_arsize(3'd0), + .dma_axi_arprot(3'd0), + .dma_axi_arlen(8'd0), + .dma_axi_arburst(2'd0), + .dma_axi_rvalid(), + .dma_axi_rready(1'b0), + .dma_axi_rid(), + .dma_axi_rdata(), + .dma_axi_rresp(), + .dma_axi_rlast(), + .lsu_bus_clk_en(1'b1), + .ifu_bus_clk_en(1'b1), + .dbg_bus_clk_en(1'b1), + .dma_bus_clk_en(1'b1), + .timer_int(timer_irq), + .extintsrc_req({4'd0, sw_irq4, sw_irq3, 1'b0, uart_irq}), + .dec_tlu_perfcnt0(), + .dec_tlu_perfcnt1(), + .dec_tlu_perfcnt2(), + .dec_tlu_perfcnt3(), + .dmi_reg_rdata(dmi_reg_rdata), + .dmi_reg_wdata(dmi_reg_wdata), + .dmi_reg_addr(dmi_reg_addr), + .dmi_reg_en(dmi_reg_en), + .dmi_reg_wr_en(dmi_reg_wr_en), + .dmi_hard_reset(dmi_hard_reset), + .mpc_debug_halt_req(1'b0), + .mpc_debug_run_req(1'b0), + .mpc_reset_run_req(1'b1), + .mpc_debug_halt_ack(), + .mpc_debug_run_ack(), + .debug_brkpt_status(), + .i_cpu_halt_req(1'b0), + .o_cpu_halt_ack(), + .o_cpu_halt_status(), + .o_debug_mode_status(), + .i_cpu_run_req(1'b0), + .o_cpu_run_ack(), + .scan_mode(1'b0), + .mbist_mode(1'b0) + ); +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:1:1 +`default_nettype none +module veerwolf_pack_cc ( + clk, + rstn, + i_uart_rx, + o_uart_tx, + i_sw, + o_led +); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:3:15 + parameter bootrom_file = "pack_rom.vh"; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:4:15 + parameter cpu_type = "EL2"; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:5:5 + input wire clk; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:6:5 + input wire rstn; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:7:5 + input wire i_uart_rx; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:8:5 + output wire o_uart_tx; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:9:5 + input wire [15:0] i_sw; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:10:5 + output reg [15:0] o_led; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:12:4 + wire [63:0] gpio_out; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:13:4 + reg [15:0] led_int_r; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:15:4 + wire clk_core; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:16:4 + wire rst_core; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:18:4 + clkgen clk_gen( + .i_clk(clk), + .i_rst(~rstn), + .o_clk_core(clk_core), + .o_rst_core(rst_core) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_pack_cc.v:26:4 + // rewrote reg-to-output bindings + wire [16:1] sv2v_tmp_veerwolfs_o_led; + always @(*) o_led = sv2v_tmp_veerwolfs_o_led; + veerwolf_pack #(.pack_code(bootrom_file)) veerwolfs( + .clk_core(clk_core), + .rst_core(rst_core), + .i_uart_rx(i_uart_rx), + .o_uart_tx(o_uart_tx), + .i_sw(i_sw), + .o_led(sv2v_tmp_veerwolfs_o_led) + ); +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:24:1 +`default_nettype none +module veerwolf_tile ( + clk_core, + rst_core, + i_uart_rx, + o_uart_tx, + i_sw, + o_led +); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:26:15 + parameter bootrom_file = "bootloader.vh"; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:27:15 + parameter cpu_type = "EH1"; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:28:5 + input wire clk_core; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:29:5 + input wire rst_core; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:30:5 + input wire i_uart_rx; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:31:5 + output wire o_uart_tx; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:32:5 + input wire [15:0] i_sw; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:33:5 + output reg [15:0] o_led; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:35:4 + wire [63:0] gpio_out; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:36:4 + reg [15:0] led_int_r; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:38:4 + reg [15:0] sw_r; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:39:4 + reg [15:0] sw_2r; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:41:4 + localparam RAM_SIZE = 32'h00010000; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:43:4 + wire [5:0] ram_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:44:4 + wire [31:0] ram_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:45:4 + wire [7:0] ram_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:46:4 + wire [2:0] ram_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:47:4 + wire [1:0] ram_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:48:4 + wire ram_awlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:49:4 + wire [3:0] ram_awcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:50:4 + wire [2:0] ram_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:51:4 + wire [3:0] ram_awregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:52:4 + wire [3:0] ram_awqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:53:4 + wire ram_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:54:4 + wire ram_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:55:4 + wire [5:0] ram_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:56:4 + wire [31:0] ram_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:57:4 + wire [7:0] ram_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:58:4 + wire [2:0] ram_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:59:4 + wire [1:0] ram_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:60:4 + wire ram_arlock; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:61:4 + wire [3:0] ram_arcache; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:62:4 + wire [2:0] ram_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:63:4 + wire [3:0] ram_arregion; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:64:4 + wire [3:0] ram_arqos; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:65:4 + wire ram_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:66:4 + wire ram_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:67:4 + wire [63:0] ram_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:68:4 + wire [7:0] ram_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:69:4 + wire ram_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:70:4 + wire ram_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:71:4 + wire ram_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:72:4 + wire [5:0] ram_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:73:4 + wire [1:0] ram_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:74:4 + wire ram_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:75:4 + wire ram_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:76:4 + wire [5:0] ram_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:77:4 + wire [63:0] ram_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:78:4 + wire [1:0] ram_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:79:4 + wire ram_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:80:4 + wire ram_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:81:4 + wire ram_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:83:4 + axi_ram #( + .DATA_WIDTH(64), + .ADDR_WIDTH($clog2(32'h00010000)), + .ID_WIDTH(6) + ) ram( + .clk(clk_core), + .rst(rst_core), + .s_axi_awid(ram_awid), + .s_axi_awaddr(ram_awaddr[$clog2(32'h00010000) - 1:0]), + .s_axi_awlen(ram_awlen), + .s_axi_awsize(ram_awsize), + .s_axi_awburst(ram_awburst), + .s_axi_awlock(1'd0), + .s_axi_awcache(4'd0), + .s_axi_awprot(3'd0), + .s_axi_awvalid(ram_awvalid), + .s_axi_awready(ram_awready), + .s_axi_arid(ram_arid), + .s_axi_araddr(ram_araddr[$clog2(32'h00010000) - 1:0]), + .s_axi_arlen(ram_arlen), + .s_axi_arsize(ram_arsize), + .s_axi_arburst(ram_arburst), + .s_axi_arlock(1'd0), + .s_axi_arcache(4'd0), + .s_axi_arprot(3'd0), + .s_axi_arvalid(ram_arvalid), + .s_axi_arready(ram_arready), + .s_axi_wdata(ram_wdata), + .s_axi_wstrb(ram_wstrb), + .s_axi_wlast(ram_wlast), + .s_axi_wvalid(ram_wvalid), + .s_axi_wready(ram_wready), + .s_axi_bid(ram_bid), + .s_axi_bresp(ram_bresp), + .s_axi_bvalid(ram_bvalid), + .s_axi_bready(ram_bready), + .s_axi_rid(ram_rid), + .s_axi_rdata(ram_rdata), + .s_axi_rresp(ram_rresp), + .s_axi_rlast(ram_rlast), + .s_axi_rvalid(ram_rvalid), + .s_axi_rready(ram_rready) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:130:4 + veerwolf_nospi #( + .bootrom_file(bootrom_file), + .clk_freq_hz((cpu_type == "EL2" ? 32'd25000000 : 32'd50000000)) + ) veerwolf( + .clk(clk_core), + .rstn(~rst_core), + .dmi_reg_rdata(), + .dmi_reg_wdata(32'd0), + .dmi_reg_addr(7'd0), + .dmi_reg_en(1'b0), + .dmi_reg_wr_en(1'b0), + .dmi_hard_reset(1'b0), + .i_uart_rx(i_uart_rx), + .o_uart_tx(o_uart_tx), + .o_ram_awid(ram_awid), + .o_ram_awaddr(ram_awaddr), + .o_ram_awlen(ram_awlen), + .o_ram_awsize(ram_awsize), + .o_ram_awburst(ram_awburst), + .o_ram_awlock(ram_awlock), + .o_ram_awcache(ram_awcache), + .o_ram_awprot(ram_awprot), + .o_ram_awregion(ram_awregion), + .o_ram_awqos(ram_awqos), + .o_ram_awvalid(ram_awvalid), + .i_ram_awready(ram_awready), + .o_ram_arid(ram_arid), + .o_ram_araddr(ram_araddr), + .o_ram_arlen(ram_arlen), + .o_ram_arsize(ram_arsize), + .o_ram_arburst(ram_arburst), + .o_ram_arlock(ram_arlock), + .o_ram_arcache(ram_arcache), + .o_ram_arprot(ram_arprot), + .o_ram_arregion(ram_arregion), + .o_ram_arqos(ram_arqos), + .o_ram_arvalid(ram_arvalid), + .i_ram_arready(ram_arready), + .o_ram_wdata(ram_wdata), + .o_ram_wstrb(ram_wstrb), + .o_ram_wlast(ram_wlast), + .o_ram_wvalid(ram_wvalid), + .i_ram_wready(ram_wready), + .i_ram_bid(ram_bid), + .i_ram_bresp(ram_bresp), + .i_ram_bvalid(ram_bvalid), + .o_ram_bready(ram_bready), + .i_ram_rid(ram_rid), + .i_ram_rdata(ram_rdata), + .i_ram_rresp(ram_rresp), + .i_ram_rlast(ram_rlast), + .i_ram_rvalid(ram_rvalid), + .o_ram_rready(ram_rready), + .i_ram_init_done(1'b1), + .i_ram_init_error(1'b0), + .i_gpio({48'h000000000000, sw_2r}), + .o_gpio(gpio_out) + ); + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:188:4 + always @(posedge clk_core) begin + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:189:7 + o_led <= led_int_r; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:190:7 + led_int_r <= gpio_out[31:16]; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:191:7 + sw_r <= i_sw; + // Trace: ./src/veerwolf_0.7.5/rtl/veerwolf_tile.v:192:7 + sw_2r <= sw_r; + end +endmodule +module clkgen ( + i_clk, + i_rst, + o_clk_core, + o_rst_core +); + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:2:4 + input wire i_clk; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:3:4 + input wire i_rst; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:4:4 + output wire o_clk_core; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:5:4 + output wire o_rst_core; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:8:1 + reg rst_reg1; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:9:1 + reg rst_reg2; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:11:1 + wire o_clk_pll; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:12:1 + wire usr_pll_lock_1; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:14:1 + CC_PLL #( + .REF_CLK("10.0"), + .OUT_CLK("25.0"), + .PERF_MD("ECONOMY"), + .LOW_JITTER(1) + ) pll_inst_ila( + .CLK_REF(i_clk), + .CLK_FEEDBACK(1'b0), + .USR_CLK_REF(1'b0), + .USR_LOCKED_STDY_RST(1'b0), + .USR_PLL_LOCKED_STDY(), + .USR_PLL_LOCKED(usr_pll_lock_1), + .CLK270(), + .CLK180(), + .CLK90(), + .CLK0(o_clk_pll), + .CLK_REF_OUT() + ); + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:30:1 + always @(posedge o_clk_pll) + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:31:4 + if (!usr_pll_lock_1 || i_rst) begin + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:32:7 + rst_reg1 <= 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:33:7 + rst_reg2 <= 1'b1; + end + else begin + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:35:7 + rst_reg1 <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:36:7 + rst_reg2 <= rst_reg1; + end + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:40:1 + assign o_clk_core = o_clk_pll; + // Trace: ./src/veerwolf_0.7.5/rtl/clk_gen_cc.v:41:1 + assign o_rst_core = rst_reg2; +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:27:1 +`resetall +// Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:28:1 +`default_nettype none +module axi_ram ( + clk, + rst, + s_axi_awid, + s_axi_awaddr, + s_axi_awlen, + s_axi_awsize, + s_axi_awburst, + s_axi_awlock, + s_axi_awcache, + s_axi_awprot, + s_axi_awvalid, + s_axi_awready, + s_axi_wdata, + s_axi_wstrb, + s_axi_wlast, + s_axi_wvalid, + s_axi_wready, + s_axi_bid, + s_axi_bresp, + s_axi_bvalid, + s_axi_bready, + s_axi_arid, + s_axi_araddr, + s_axi_arlen, + s_axi_arsize, + s_axi_arburst, + s_axi_arlock, + s_axi_arcache, + s_axi_arprot, + s_axi_arvalid, + s_axi_arready, + s_axi_rid, + s_axi_rdata, + s_axi_rresp, + s_axi_rlast, + s_axi_rvalid, + s_axi_rready +); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:36:15 + parameter DATA_WIDTH = 32; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:38:15 + parameter ADDR_WIDTH = 16; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:40:15 + parameter STRB_WIDTH = DATA_WIDTH / 8; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:42:15 + parameter ID_WIDTH = 8; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:44:15 + parameter PIPELINE_OUTPUT = 0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:47:5 + input wire clk; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:48:5 + input wire rst; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:50:5 + input wire [ID_WIDTH - 1:0] s_axi_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:51:5 + input wire [ADDR_WIDTH - 1:0] s_axi_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:52:5 + input wire [7:0] s_axi_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:53:5 + input wire [2:0] s_axi_awsize; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:54:5 + input wire [1:0] s_axi_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:55:5 + input wire s_axi_awlock; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:56:5 + input wire [3:0] s_axi_awcache; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:57:5 + input wire [2:0] s_axi_awprot; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:58:5 + input wire s_axi_awvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:59:5 + output wire s_axi_awready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:60:5 + input wire [DATA_WIDTH - 1:0] s_axi_wdata; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:61:5 + input wire [STRB_WIDTH - 1:0] s_axi_wstrb; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:62:5 + input wire s_axi_wlast; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:63:5 + input wire s_axi_wvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:64:5 + output wire s_axi_wready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:65:5 + output wire [ID_WIDTH - 1:0] s_axi_bid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:66:5 + output wire [1:0] s_axi_bresp; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:67:5 + output wire s_axi_bvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:68:5 + input wire s_axi_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:69:5 + input wire [ID_WIDTH - 1:0] s_axi_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:70:5 + input wire [ADDR_WIDTH - 1:0] s_axi_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:71:5 + input wire [7:0] s_axi_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:72:5 + input wire [2:0] s_axi_arsize; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:73:5 + input wire [1:0] s_axi_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:74:5 + input wire s_axi_arlock; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:75:5 + input wire [3:0] s_axi_arcache; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:76:5 + input wire [2:0] s_axi_arprot; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:77:5 + input wire s_axi_arvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:78:5 + output wire s_axi_arready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:79:5 + output wire [ID_WIDTH - 1:0] s_axi_rid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:80:5 + output wire [DATA_WIDTH - 1:0] s_axi_rdata; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:81:5 + output wire [1:0] s_axi_rresp; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:82:5 + output wire s_axi_rlast; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:83:5 + output wire s_axi_rvalid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:84:5 + input wire s_axi_rready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:87:1 + parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:88:1 + parameter WORD_WIDTH = STRB_WIDTH; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:89:1 + parameter WORD_SIZE = DATA_WIDTH / WORD_WIDTH; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:92:1 + initial begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:93:5 + if ((WORD_SIZE * STRB_WIDTH) != DATA_WIDTH) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:94:9 + $error("Error: AXI data width not evenly divisble (instance %m)"); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:95:9 + $finish; + end + if ((2 ** $clog2(WORD_WIDTH)) != WORD_WIDTH) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:99:9 + $error("Error: AXI word width must be even power of two (instance %m)"); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:100:9 + $finish; + end + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:104:1 + localparam [0:0] READ_STATE_IDLE = 1'd0; + localparam [0:0] READ_STATE_BURST = 1'd1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:108:1 + reg [0:0] read_state_reg = READ_STATE_IDLE; + reg [0:0] read_state_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:110:1 + localparam [1:0] WRITE_STATE_IDLE = 2'd0; + localparam [1:0] WRITE_STATE_BURST = 2'd1; + localparam [1:0] WRITE_STATE_RESP = 2'd2; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:115:1 + reg [1:0] write_state_reg = WRITE_STATE_IDLE; + reg [1:0] write_state_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:117:1 + reg mem_wr_en; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:118:1 + reg mem_rd_en; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:120:1 + reg [ID_WIDTH - 1:0] read_id_reg = {ID_WIDTH {1'b0}}; + reg [ID_WIDTH - 1:0] read_id_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:121:1 + reg [ADDR_WIDTH - 1:0] read_addr_reg = {ADDR_WIDTH {1'b0}}; + reg [ADDR_WIDTH - 1:0] read_addr_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:122:1 + reg [7:0] read_count_reg = 8'd0; + reg [7:0] read_count_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:123:1 + reg [2:0] read_size_reg = 3'd0; + reg [2:0] read_size_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:124:1 + reg [1:0] read_burst_reg = 2'd0; + reg [1:0] read_burst_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:125:1 + reg [ID_WIDTH - 1:0] write_id_reg = {ID_WIDTH {1'b0}}; + reg [ID_WIDTH - 1:0] write_id_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:126:1 + reg [ADDR_WIDTH - 1:0] write_addr_reg = {ADDR_WIDTH {1'b0}}; + reg [ADDR_WIDTH - 1:0] write_addr_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:127:1 + reg [7:0] write_count_reg = 8'd0; + reg [7:0] write_count_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:128:1 + reg [2:0] write_size_reg = 3'd0; + reg [2:0] write_size_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:129:1 + reg [1:0] write_burst_reg = 2'd0; + reg [1:0] write_burst_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:131:1 + reg s_axi_awready_reg = 1'b0; + reg s_axi_awready_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:132:1 + reg s_axi_wready_reg = 1'b0; + reg s_axi_wready_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:133:1 + reg [ID_WIDTH - 1:0] s_axi_bid_reg = {ID_WIDTH {1'b0}}; + reg [ID_WIDTH - 1:0] s_axi_bid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:134:1 + reg s_axi_bvalid_reg = 1'b0; + reg s_axi_bvalid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:135:1 + reg s_axi_arready_reg = 1'b0; + reg s_axi_arready_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:136:1 + reg [ID_WIDTH - 1:0] s_axi_rid_reg = {ID_WIDTH {1'b0}}; + reg [ID_WIDTH - 1:0] s_axi_rid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:137:1 + reg [DATA_WIDTH - 1:0] s_axi_rdata_reg = {DATA_WIDTH {1'b0}}; + reg [DATA_WIDTH - 1:0] s_axi_rdata_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:138:1 + reg s_axi_rlast_reg = 1'b0; + reg s_axi_rlast_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:139:1 + reg s_axi_rvalid_reg = 1'b0; + reg s_axi_rvalid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:140:1 + reg [ID_WIDTH - 1:0] s_axi_rid_pipe_reg = {ID_WIDTH {1'b0}}; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:141:1 + reg [DATA_WIDTH - 1:0] s_axi_rdata_pipe_reg = {DATA_WIDTH {1'b0}}; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:142:1 + reg s_axi_rlast_pipe_reg = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:143:1 + reg s_axi_rvalid_pipe_reg = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:146:1 + reg [DATA_WIDTH - 1:0] mem [(2 ** VALID_ADDR_WIDTH) - 1:0]; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:148:1 + wire [VALID_ADDR_WIDTH - 1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:149:1 + wire [VALID_ADDR_WIDTH - 1:0] s_axi_araddr_valid = s_axi_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:150:1 + wire [VALID_ADDR_WIDTH - 1:0] read_addr_valid = read_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:151:1 + wire [VALID_ADDR_WIDTH - 1:0] write_addr_valid = write_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:153:1 + assign s_axi_awready = s_axi_awready_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:154:1 + assign s_axi_wready = s_axi_wready_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:155:1 + assign s_axi_bid = s_axi_bid_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:156:1 + assign s_axi_bresp = 2'b00; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:157:1 + assign s_axi_bvalid = s_axi_bvalid_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:158:1 + assign s_axi_arready = s_axi_arready_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:159:1 + assign s_axi_rid = (PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:160:1 + assign s_axi_rdata = (PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:161:1 + assign s_axi_rresp = 2'b00; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:162:1 + assign s_axi_rlast = (PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:163:1 + assign s_axi_rvalid = (PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:165:1 + integer i; + integer j; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:177:1 + always @(*) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:178:5 + write_state_next = WRITE_STATE_IDLE; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:180:5 + mem_wr_en = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:182:5 + write_id_next = write_id_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:183:5 + write_addr_next = write_addr_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:184:5 + write_count_next = write_count_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:185:5 + write_size_next = write_size_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:186:5 + write_burst_next = write_burst_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:188:5 + s_axi_awready_next = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:189:5 + s_axi_wready_next = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:190:5 + s_axi_bid_next = s_axi_bid_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:191:5 + s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:193:5 + case (write_state_reg) + WRITE_STATE_IDLE: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:195:13 + s_axi_awready_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:197:13 + if (s_axi_awready && s_axi_awvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:198:17 + write_id_next = s_axi_awid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:199:17 + write_addr_next = s_axi_awaddr; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:200:17 + write_count_next = s_axi_awlen; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:201:17 + write_size_next = (s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH)); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:202:17 + write_burst_next = s_axi_awburst; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:204:17 + s_axi_awready_next = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:205:17 + s_axi_wready_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:206:17 + write_state_next = WRITE_STATE_BURST; + end + else + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:208:17 + write_state_next = WRITE_STATE_IDLE; + end + WRITE_STATE_BURST: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:212:13 + s_axi_wready_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:214:13 + if (s_axi_wready && s_axi_wvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:215:17 + mem_wr_en = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:216:17 + if (write_burst_reg != 2'b00) + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:217:21 + write_addr_next = write_addr_reg + (1 << write_size_reg); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:219:17 + write_count_next = write_count_reg - 1; + if (write_count_reg > 0) + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:221:21 + write_state_next = WRITE_STATE_BURST; + else begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:223:21 + s_axi_wready_next = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:224:21 + if (s_axi_bready || !s_axi_bvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:225:25 + s_axi_bid_next = write_id_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:226:25 + s_axi_bvalid_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:227:25 + s_axi_awready_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:228:25 + write_state_next = WRITE_STATE_IDLE; + end + else + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:230:25 + write_state_next = WRITE_STATE_RESP; + end + end + else + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:234:17 + write_state_next = WRITE_STATE_BURST; + end + WRITE_STATE_RESP: + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:238:13 + if (s_axi_bready || !s_axi_bvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:239:17 + s_axi_bid_next = write_id_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:240:17 + s_axi_bvalid_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:241:17 + s_axi_awready_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:242:17 + write_state_next = WRITE_STATE_IDLE; + end + else + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:244:17 + write_state_next = WRITE_STATE_RESP; + endcase + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:250:1 + always @(posedge clk) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:251:5 + write_state_reg <= write_state_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:253:5 + write_id_reg <= write_id_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:254:5 + write_addr_reg <= write_addr_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:255:5 + write_count_reg <= write_count_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:256:5 + write_size_reg <= write_size_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:257:5 + write_burst_reg <= write_burst_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:259:5 + s_axi_awready_reg <= s_axi_awready_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:260:5 + s_axi_wready_reg <= s_axi_wready_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:261:5 + s_axi_bid_reg <= s_axi_bid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:262:5 + s_axi_bvalid_reg <= s_axi_bvalid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:264:5 + for (i = 0; i < WORD_WIDTH; i = i + 1) + begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:265:9 + if (mem_wr_en & s_axi_wstrb[i]) + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:266:13 + mem[write_addr_valid][WORD_SIZE * i+:WORD_SIZE] <= s_axi_wdata[WORD_SIZE * i+:WORD_SIZE]; + end + if (rst) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:271:9 + write_state_reg <= WRITE_STATE_IDLE; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:273:9 + s_axi_awready_reg <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:274:9 + s_axi_wready_reg <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:275:9 + s_axi_bvalid_reg <= 1'b0; + end + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:279:1 + always @(*) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:280:5 + read_state_next = READ_STATE_IDLE; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:282:5 + mem_rd_en = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:284:5 + s_axi_rid_next = s_axi_rid_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:285:5 + s_axi_rlast_next = s_axi_rlast_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:286:5 + s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg)); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:288:5 + read_id_next = read_id_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:289:5 + read_addr_next = read_addr_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:290:5 + read_count_next = read_count_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:291:5 + read_size_next = read_size_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:292:5 + read_burst_next = read_burst_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:294:5 + s_axi_arready_next = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:296:5 + case (read_state_reg) + READ_STATE_IDLE: begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:298:13 + s_axi_arready_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:300:13 + if (s_axi_arready && s_axi_arvalid) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:301:17 + read_id_next = s_axi_arid; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:302:17 + read_addr_next = s_axi_araddr; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:303:17 + read_count_next = s_axi_arlen; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:304:17 + read_size_next = (s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH)); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:305:17 + read_burst_next = s_axi_arburst; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:307:17 + s_axi_arready_next = 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:308:17 + read_state_next = READ_STATE_BURST; + end + else + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:310:17 + read_state_next = READ_STATE_IDLE; + end + READ_STATE_BURST: + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:314:13 + if ((s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg)) || !s_axi_rvalid_reg) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:315:17 + mem_rd_en = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:316:17 + s_axi_rvalid_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:317:17 + s_axi_rid_next = read_id_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:318:17 + s_axi_rlast_next = read_count_reg == 0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:319:17 + if (read_burst_reg != 2'b00) + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:320:21 + read_addr_next = read_addr_reg + (1 << read_size_reg); + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:322:17 + read_count_next = read_count_reg - 1; + if (read_count_reg > 0) + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:324:21 + read_state_next = READ_STATE_BURST; + else begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:326:21 + s_axi_arready_next = 1'b1; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:327:21 + read_state_next = READ_STATE_IDLE; + end + end + else + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:330:17 + read_state_next = READ_STATE_BURST; + endcase + end + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:336:1 + always @(posedge clk) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:337:5 + read_state_reg <= read_state_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:339:5 + read_id_reg <= read_id_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:340:5 + read_addr_reg <= read_addr_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:341:5 + read_count_reg <= read_count_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:342:5 + read_size_reg <= read_size_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:343:5 + read_burst_reg <= read_burst_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:345:5 + s_axi_arready_reg <= s_axi_arready_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:346:5 + s_axi_rid_reg <= s_axi_rid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:347:5 + s_axi_rlast_reg <= s_axi_rlast_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:348:5 + s_axi_rvalid_reg <= s_axi_rvalid_next; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:350:5 + if (mem_rd_en) + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:351:9 + s_axi_rdata_reg <= mem[read_addr_valid]; + if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:355:9 + s_axi_rid_pipe_reg <= s_axi_rid_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:356:9 + s_axi_rdata_pipe_reg <= s_axi_rdata_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:357:9 + s_axi_rlast_pipe_reg <= s_axi_rlast_reg; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:358:9 + s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg; + end + if (rst) begin + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:362:9 + read_state_reg <= READ_STATE_IDLE; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:364:9 + s_axi_arready_reg <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:365:9 + s_axi_rvalid_reg <= 1'b0; + // Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:366:9 + s_axi_rvalid_pipe_reg <= 1'b0; + end + end +endmodule +// Trace: ./src/veerwolf_0.7.5/rtl/axi_ram.v:372:1 +`resetall +// Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:3:1 +`default_nettype none +module veerwolf_pack ( + clk_core, + rst_core, + i_uart_rx, + o_uart_tx, + i_sw, + o_led +); + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:5:15 + parameter pack_code = "bootloader.vh"; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:6:5 + input wire clk_core; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:7:5 + input wire rst_core; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:8:5 + input wire i_uart_rx; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:9:5 + output wire o_uart_tx; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:10:5 + input wire [15:0] i_sw; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:11:5 + output wire [15:0] o_led; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:13:1 + wire [15:0] gpio0; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:14:1 + wire uart0; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:15:1 + wire [15:0] gpio1; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:16:1 + wire uart1; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:18:1 + assign gpio0 = i_sw; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:19:1 + assign o_led = gpio1; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:20:1 + assign uart0 = i_uart_rx; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:21:1 + assign o_uart_tx = uart1; + // Trace: ./src/veerwolf-wolfpack_0.7.5/veerwolf_pack.v:23:1 + veerwolf_tile #(.bootrom_file(pack_code)) tile0( + .clk_core(clk_core), + .rst_core(rst_core), + .i_uart_rx(uart0), + .o_uart_tx(uart1), + .i_sw(gpio0), + .o_led(gpio1) + ); +endmodule +// Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:3:1 +`default_nettype none +module axi_intercon ( + clk_i, + rst_ni, + i_ifu_arid, + i_ifu_araddr, + i_ifu_arlen, + i_ifu_arsize, + i_ifu_arburst, + i_ifu_arlock, + i_ifu_arcache, + i_ifu_arprot, + i_ifu_arregion, + i_ifu_arqos, + i_ifu_arvalid, + o_ifu_arready, + o_ifu_rid, + o_ifu_rdata, + o_ifu_rresp, + o_ifu_rlast, + o_ifu_rvalid, + i_ifu_rready, + i_lsu_awid, + i_lsu_awaddr, + i_lsu_awlen, + i_lsu_awsize, + i_lsu_awburst, + i_lsu_awlock, + i_lsu_awcache, + i_lsu_awprot, + i_lsu_awregion, + i_lsu_awqos, + i_lsu_awvalid, + o_lsu_awready, + i_lsu_arid, + i_lsu_araddr, + i_lsu_arlen, + i_lsu_arsize, + i_lsu_arburst, + i_lsu_arlock, + i_lsu_arcache, + i_lsu_arprot, + i_lsu_arregion, + i_lsu_arqos, + i_lsu_arvalid, + o_lsu_arready, + i_lsu_wdata, + i_lsu_wstrb, + i_lsu_wlast, + i_lsu_wvalid, + o_lsu_wready, + o_lsu_bid, + o_lsu_bresp, + o_lsu_bvalid, + i_lsu_bready, + o_lsu_rid, + o_lsu_rdata, + o_lsu_rresp, + o_lsu_rlast, + o_lsu_rvalid, + i_lsu_rready, + i_sb_awid, + i_sb_awaddr, + i_sb_awlen, + i_sb_awsize, + i_sb_awburst, + i_sb_awlock, + i_sb_awcache, + i_sb_awprot, + i_sb_awregion, + i_sb_awqos, + i_sb_awvalid, + o_sb_awready, + i_sb_arid, + i_sb_araddr, + i_sb_arlen, + i_sb_arsize, + i_sb_arburst, + i_sb_arlock, + i_sb_arcache, + i_sb_arprot, + i_sb_arregion, + i_sb_arqos, + i_sb_arvalid, + o_sb_arready, + i_sb_wdata, + i_sb_wstrb, + i_sb_wlast, + i_sb_wvalid, + o_sb_wready, + o_sb_bid, + o_sb_bresp, + o_sb_bvalid, + i_sb_bready, + o_sb_rid, + o_sb_rdata, + o_sb_rresp, + o_sb_rlast, + o_sb_rvalid, + i_sb_rready, + o_io_awid, + o_io_awaddr, + o_io_awlen, + o_io_awsize, + o_io_awburst, + o_io_awlock, + o_io_awcache, + o_io_awprot, + o_io_awregion, + o_io_awqos, + o_io_awvalid, + i_io_awready, + o_io_arid, + o_io_araddr, + o_io_arlen, + o_io_arsize, + o_io_arburst, + o_io_arlock, + o_io_arcache, + o_io_arprot, + o_io_arregion, + o_io_arqos, + o_io_arvalid, + i_io_arready, + o_io_wdata, + o_io_wstrb, + o_io_wlast, + o_io_wvalid, + i_io_wready, + i_io_bid, + i_io_bresp, + i_io_bvalid, + o_io_bready, + i_io_rid, + i_io_rdata, + i_io_rresp, + i_io_rlast, + i_io_rvalid, + o_io_rready, + o_ram_awid, + o_ram_awaddr, + o_ram_awlen, + o_ram_awsize, + o_ram_awburst, + o_ram_awlock, + o_ram_awcache, + o_ram_awprot, + o_ram_awregion, + o_ram_awqos, + o_ram_awvalid, + i_ram_awready, + o_ram_arid, + o_ram_araddr, + o_ram_arlen, + o_ram_arsize, + o_ram_arburst, + o_ram_arlock, + o_ram_arcache, + o_ram_arprot, + o_ram_arregion, + o_ram_arqos, + o_ram_arvalid, + i_ram_arready, + o_ram_wdata, + o_ram_wstrb, + o_ram_wlast, + o_ram_wvalid, + i_ram_wready, + i_ram_bid, + i_ram_bresp, + i_ram_bvalid, + o_ram_bready, + i_ram_rid, + i_ram_rdata, + i_ram_rresp, + i_ram_rlast, + i_ram_rvalid, + o_ram_rready +); + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:5:5 + input wire clk_i; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:6:5 + input wire rst_ni; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:7:5 + input wire [2:0] i_ifu_arid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:8:5 + input wire [31:0] i_ifu_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:9:5 + input wire [7:0] i_ifu_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:10:5 + input wire [2:0] i_ifu_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:11:5 + input wire [1:0] i_ifu_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:12:5 + input wire i_ifu_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:13:5 + input wire [3:0] i_ifu_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:14:5 + input wire [2:0] i_ifu_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:15:5 + input wire [3:0] i_ifu_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:16:5 + input wire [3:0] i_ifu_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:17:5 + input wire i_ifu_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:18:5 + output wire o_ifu_arready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:19:5 + output wire [2:0] o_ifu_rid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:20:5 + output wire [63:0] o_ifu_rdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:21:5 + output wire [1:0] o_ifu_rresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:22:5 + output wire o_ifu_rlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:23:5 + output wire o_ifu_rvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:24:5 + input wire i_ifu_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:25:5 + input wire [3:0] i_lsu_awid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:26:5 + input wire [31:0] i_lsu_awaddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:27:5 + input wire [7:0] i_lsu_awlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:28:5 + input wire [2:0] i_lsu_awsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:29:5 + input wire [1:0] i_lsu_awburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:30:5 + input wire i_lsu_awlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:31:5 + input wire [3:0] i_lsu_awcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:32:5 + input wire [2:0] i_lsu_awprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:33:5 + input wire [3:0] i_lsu_awregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:34:5 + input wire [3:0] i_lsu_awqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:35:5 + input wire i_lsu_awvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:36:5 + output wire o_lsu_awready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:37:5 + input wire [3:0] i_lsu_arid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:38:5 + input wire [31:0] i_lsu_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:39:5 + input wire [7:0] i_lsu_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:40:5 + input wire [2:0] i_lsu_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:41:5 + input wire [1:0] i_lsu_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:42:5 + input wire i_lsu_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:43:5 + input wire [3:0] i_lsu_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:44:5 + input wire [2:0] i_lsu_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:45:5 + input wire [3:0] i_lsu_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:46:5 + input wire [3:0] i_lsu_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:47:5 + input wire i_lsu_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:48:5 + output wire o_lsu_arready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:49:5 + input wire [63:0] i_lsu_wdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:50:5 + input wire [7:0] i_lsu_wstrb; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:51:5 + input wire i_lsu_wlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:52:5 + input wire i_lsu_wvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:53:5 + output wire o_lsu_wready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:54:5 + output wire [3:0] o_lsu_bid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:55:5 + output wire [1:0] o_lsu_bresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:56:5 + output wire o_lsu_bvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:57:5 + input wire i_lsu_bready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:58:5 + output wire [3:0] o_lsu_rid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:59:5 + output wire [63:0] o_lsu_rdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:60:5 + output wire [1:0] o_lsu_rresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:61:5 + output wire o_lsu_rlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:62:5 + output wire o_lsu_rvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:63:5 + input wire i_lsu_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:64:5 + input wire [0:0] i_sb_awid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:65:5 + input wire [31:0] i_sb_awaddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:66:5 + input wire [7:0] i_sb_awlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:67:5 + input wire [2:0] i_sb_awsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:68:5 + input wire [1:0] i_sb_awburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:69:5 + input wire i_sb_awlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:70:5 + input wire [3:0] i_sb_awcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:71:5 + input wire [2:0] i_sb_awprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:72:5 + input wire [3:0] i_sb_awregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:73:5 + input wire [3:0] i_sb_awqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:74:5 + input wire i_sb_awvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:75:5 + output wire o_sb_awready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:76:5 + input wire [0:0] i_sb_arid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:77:5 + input wire [31:0] i_sb_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:78:5 + input wire [7:0] i_sb_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:79:5 + input wire [2:0] i_sb_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:80:5 + input wire [1:0] i_sb_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:81:5 + input wire i_sb_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:82:5 + input wire [3:0] i_sb_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:83:5 + input wire [2:0] i_sb_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:84:5 + input wire [3:0] i_sb_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:85:5 + input wire [3:0] i_sb_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:86:5 + input wire i_sb_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:87:5 + output wire o_sb_arready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:88:5 + input wire [63:0] i_sb_wdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:89:5 + input wire [7:0] i_sb_wstrb; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:90:5 + input wire i_sb_wlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:91:5 + input wire i_sb_wvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:92:5 + output wire o_sb_wready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:93:5 + output wire [0:0] o_sb_bid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:94:5 + output wire [1:0] o_sb_bresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:95:5 + output wire o_sb_bvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:96:5 + input wire i_sb_bready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:97:5 + output wire [0:0] o_sb_rid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:98:5 + output wire [63:0] o_sb_rdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:99:5 + output wire [1:0] o_sb_rresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:100:5 + output wire o_sb_rlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:101:5 + output wire o_sb_rvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:102:5 + input wire i_sb_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:103:5 + output wire [5:0] o_io_awid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:104:5 + output wire [31:0] o_io_awaddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:105:5 + output wire [7:0] o_io_awlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:106:5 + output wire [2:0] o_io_awsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:107:5 + output wire [1:0] o_io_awburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:108:5 + output wire o_io_awlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:109:5 + output wire [3:0] o_io_awcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:110:5 + output wire [2:0] o_io_awprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:111:5 + output wire [3:0] o_io_awregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:112:5 + output wire [3:0] o_io_awqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:113:5 + output wire o_io_awvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:114:5 + input wire i_io_awready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:115:5 + output wire [5:0] o_io_arid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:116:5 + output wire [31:0] o_io_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:117:5 + output wire [7:0] o_io_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:118:5 + output wire [2:0] o_io_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:119:5 + output wire [1:0] o_io_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:120:5 + output wire o_io_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:121:5 + output wire [3:0] o_io_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:122:5 + output wire [2:0] o_io_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:123:5 + output wire [3:0] o_io_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:124:5 + output wire [3:0] o_io_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:125:5 + output wire o_io_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:126:5 + input wire i_io_arready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:127:5 + output wire [63:0] o_io_wdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:128:5 + output wire [7:0] o_io_wstrb; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:129:5 + output wire o_io_wlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:130:5 + output wire o_io_wvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:131:5 + input wire i_io_wready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:132:5 + input wire [5:0] i_io_bid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:133:5 + input wire [1:0] i_io_bresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:134:5 + input wire i_io_bvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:135:5 + output wire o_io_bready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:136:5 + input wire [5:0] i_io_rid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:137:5 + input wire [63:0] i_io_rdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:138:5 + input wire [1:0] i_io_rresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:139:5 + input wire i_io_rlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:140:5 + input wire i_io_rvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:141:5 + output wire o_io_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:142:5 + output wire [5:0] o_ram_awid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:143:5 + output wire [31:0] o_ram_awaddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:144:5 + output wire [7:0] o_ram_awlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:145:5 + output wire [2:0] o_ram_awsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:146:5 + output wire [1:0] o_ram_awburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:147:5 + output wire o_ram_awlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:148:5 + output wire [3:0] o_ram_awcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:149:5 + output wire [2:0] o_ram_awprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:150:5 + output wire [3:0] o_ram_awregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:151:5 + output wire [3:0] o_ram_awqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:152:5 + output wire o_ram_awvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:153:5 + input wire i_ram_awready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:154:5 + output wire [5:0] o_ram_arid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:155:5 + output wire [31:0] o_ram_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:156:5 + output wire [7:0] o_ram_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:157:5 + output wire [2:0] o_ram_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:158:5 + output wire [1:0] o_ram_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:159:5 + output wire o_ram_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:160:5 + output wire [3:0] o_ram_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:161:5 + output wire [2:0] o_ram_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:162:5 + output wire [3:0] o_ram_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:163:5 + output wire [3:0] o_ram_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:164:5 + output wire o_ram_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:165:5 + input wire i_ram_arready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:166:5 + output wire [63:0] o_ram_wdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:167:5 + output wire [7:0] o_ram_wstrb; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:168:5 + output wire o_ram_wlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:169:5 + output wire o_ram_wvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:170:5 + input wire i_ram_wready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:171:5 + input wire [5:0] i_ram_bid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:172:5 + input wire [1:0] i_ram_bresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:173:5 + input wire i_ram_bvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:174:5 + output wire o_ram_bready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:175:5 + input wire [5:0] i_ram_rid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:176:5 + input wire [63:0] i_ram_rdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:177:5 + input wire [1:0] i_ram_rresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:178:5 + input wire i_ram_rlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:179:5 + input wire i_ram_rvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:180:5 + output wire o_ram_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:183:3 + localparam [31:0] NoMasters = 32'd3; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:184:3 + localparam [31:0] NoSlaves = 32'd2; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:187:3 + localparam [31:0] AxiIdWidthMasters = 32'd4; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:188:3 + localparam [31:0] AxiIdUsed = 32'd4; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:189:3 + localparam [31:0] AxiIdWidthSlaves = 6; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:190:3 + localparam [31:0] AxiAddrWidth = 32'd32; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:191:3 + localparam [31:0] AxiDataWidth = 32'd64; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:192:3 + localparam [31:0] AxiStrbWidth = 8; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:193:3 + localparam [31:0] AxiUserWidth = 1; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:194:3 + localparam [9:0] axi_pkg_DemuxAr = 64; + localparam [9:0] axi_pkg_DemuxAw = 512; + localparam [9:0] axi_pkg_DemuxB = 128; + localparam [9:0] axi_pkg_DemuxR = 32; + localparam [9:0] axi_pkg_DemuxW = 256; + localparam [9:0] axi_pkg_MuxAr = 2; + localparam [9:0] axi_pkg_MuxAw = 16; + localparam [9:0] axi_pkg_MuxB = 4; + localparam [9:0] axi_pkg_MuxR = 1; + localparam [9:0] axi_pkg_MuxW = 8; + // removed localparam type axi_pkg_xbar_latency_e + // removed localparam type axi_pkg_xbar_cfg_t + localparam [298:0] xbar_cfg = {NoMasters, NoSlaves, 65'h0000000140000000c, ((axi_pkg_DemuxAw | axi_pkg_DemuxAr) | axi_pkg_MuxAw) | axi_pkg_MuxAr, AxiIdWidthMasters, AxiIdUsed, AxiAddrWidth, AxiDataWidth, NoSlaves}; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:209:3 + // removed localparam type id_mst_t + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:210:3 + // removed localparam type id_slv_t + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:211:3 + // removed localparam type addr_t + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:212:3 + // removed localparam type axi_pkg_xbar_rule_32_t + // removed localparam type rule_t + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:213:3 + // removed localparam type data_t + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:214:3 + // removed localparam type strb_t + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:215:3 + // removed localparam type user_t + // Trace: macro expansion of AXI_TYPEDEF_AW_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:217:47 + // removed localparam type axi_pkg_atop_t + // removed localparam type axi_pkg_burst_t + // removed localparam type axi_pkg_cache_t + // removed localparam type axi_pkg_len_t + // removed localparam type axi_pkg_prot_t + // removed localparam type axi_pkg_qos_t + // removed localparam type axi_pkg_region_t + // removed localparam type axi_pkg_size_t + // removed localparam type aw_chan_mst_t + // Trace: macro expansion of AXI_TYPEDEF_AW_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:218:47 + // removed localparam type aw_chan_slv_t + // Trace: macro expansion of AXI_TYPEDEF_W_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:219:40 + // removed localparam type w_chan_t + // Trace: macro expansion of AXI_TYPEDEF_B_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:220:38 + // removed localparam type axi_pkg_resp_t + // removed localparam type b_chan_mst_t + // Trace: macro expansion of AXI_TYPEDEF_B_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:221:38 + // removed localparam type b_chan_slv_t + // Trace: macro expansion of AXI_TYPEDEF_AR_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:223:47 + // removed localparam type ar_chan_mst_t + // Trace: macro expansion of AXI_TYPEDEF_AR_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:224:47 + // removed localparam type ar_chan_slv_t + // Trace: macro expansion of AXI_TYPEDEF_R_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:225:46 + // removed localparam type r_chan_mst_t + // Trace: macro expansion of AXI_TYPEDEF_R_CHAN_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:226:46 + // removed localparam type r_chan_slv_t + // Trace: macro expansion of AXI_TYPEDEF_REQ_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:228:57 + // removed localparam type slv_req_t + // Trace: macro expansion of AXI_TYPEDEF_RESP_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:229:46 + // removed localparam type slv_resp_t + // Trace: macro expansion of AXI_TYPEDEF_REQ_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:230:57 + // removed localparam type mst_req_t + // Trace: macro expansion of AXI_TYPEDEF_RESP_T at ./src/veerwolf-intercon_0.7.5/axi_intercon.v:231:46 + // removed localparam type mst_resp_t + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:233:3 + localparam [191:0] AddrMap = 192'h000000008000000080004000000000010000000008000000; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:236:4 + wire [(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (3 * ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2)) - 1 : (3 * (1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 0)):(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 : (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)] masters_req; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:237:4 + wire [(3 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) - 1:0] masters_resp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:238:4 + wire [(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (2 * ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2)) - 1 : (2 * (1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 0)):(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 : (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)] slaves_req; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:239:4 + wire [(2 * (14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth))) - 1:0] slaves_resp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:242:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72)))) + 3)-:4] = 4'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:243:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68)))) + 31)-:32] = 32'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:244:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36)))) + 7)-:8] = 8'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:245:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28)))) + 2)-:3] = 3'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:246:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25)))) + 1)-:2] = 2'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:247:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 23) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 23)))] = 1'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:248:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22)))) + 3)-:4] = 4'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:249:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18)))) + 2)-:3] = 3'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:250:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11)))) + 3)-:4] = 4'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:251:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15)))) + 3)-:4] = 4'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:252:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7)))) + 5)-:6] = 6'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:253:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))))] = 1'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:254:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66)))) + 3)-:4] = {1'd0, i_ifu_arid}; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:255:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62)))) + 31)-:32] = i_ifu_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:256:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30)))) + 7)-:8] = i_ifu_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:257:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22)))) + 2)-:3] = i_ifu_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:258:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19)))) + 1)-:2] = i_ifu_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:259:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 17) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 17)))] = i_ifu_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:260:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16)))) + 3)-:4] = i_ifu_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:261:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12)))) + 2)-:3] = i_ifu_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:262:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5)))) + 3)-:4] = i_ifu_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:263:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9)))) + 3)-:4] = i_ifu_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:264:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 : (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 0)] = i_ifu_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:265:4 + assign o_ifu_arready = masters_resp[10 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:266:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74)))) + 63)-:64] = 64'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:267:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10))) : (0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10)))) + 7)-:8] = 8'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:268:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2)))] = 1'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:269:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))] = 1'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:270:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))] = 1'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:271:4 + assign o_ifu_rid = masters_resp[0 + ((((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 67)) >= (((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) ? ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 71) : ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 71)) + ((((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 67)) >= (((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) ? ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 71)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69))) + 1 : ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 71))) + 1)) - 1)-:((((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 67)) >= (((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) ? ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 71)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69))) + 1 : ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 71))) + 1)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:272:4 + assign o_ifu_rdata = masters_resp[0 + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 68))-:64]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:273:4 + assign o_ifu_rresp = masters_resp[0 + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 4))-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:274:4 + assign o_ifu_rlast = masters_resp[0 + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 2))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:275:4 + assign o_ifu_rvalid = masters_resp[0 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:276:4 + assign masters_req[0 + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 : (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)] = i_ifu_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:279:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72)))) + 3)-:4] = i_lsu_awid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:280:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68)))) + 31)-:32] = i_lsu_awaddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:281:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36)))) + 7)-:8] = i_lsu_awlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:282:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28)))) + 2)-:3] = i_lsu_awsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:283:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25)))) + 1)-:2] = i_lsu_awburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:284:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 23) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 23)))] = i_lsu_awlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:285:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22)))) + 3)-:4] = i_lsu_awcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:286:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18)))) + 2)-:3] = i_lsu_awprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:287:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11)))) + 3)-:4] = i_lsu_awregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:288:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15)))) + 3)-:4] = i_lsu_awqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:289:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7)))) + 5)-:6] = 6'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:290:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))))] = i_lsu_awvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:291:4 + assign o_lsu_awready = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (11 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:292:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66)))) + 3)-:4] = i_lsu_arid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:293:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62)))) + 31)-:32] = i_lsu_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:294:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30)))) + 7)-:8] = i_lsu_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:295:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22)))) + 2)-:3] = i_lsu_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:296:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19)))) + 1)-:2] = i_lsu_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:297:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 17) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 17)))] = i_lsu_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:298:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16)))) + 3)-:4] = i_lsu_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:299:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12)))) + 2)-:3] = i_lsu_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:300:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5)))) + 3)-:4] = i_lsu_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:301:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9)))) + 3)-:4] = i_lsu_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:302:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 : (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 0)] = i_lsu_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:303:4 + assign o_lsu_arready = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (10 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:304:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74)))) + 63)-:64] = i_lsu_wdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:305:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10))) : ((((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10)))) + 7)-:8] = i_lsu_wstrb; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:306:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2)))] = i_lsu_wlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:307:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))] = i_lsu_wvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:308:4 + assign o_lsu_wready = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (9 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:309:4 + assign o_lsu_bid = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:310:4 + assign o_lsu_bresp = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + ((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 4)-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:311:4 + assign o_lsu_bvalid = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (8 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:312:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))] = i_lsu_bready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:313:4 + assign o_lsu_rid = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 72))-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:314:4 + assign o_lsu_rdata = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 68))-:64]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:315:4 + assign o_lsu_rresp = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 4))-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:316:4 + assign o_lsu_rlast = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 2))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:317:4 + assign o_lsu_rvalid = masters_resp[(12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth)) + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:318:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 : (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)] = i_lsu_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:321:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 72)))) + 3)-:4] = {3'd0, i_sb_awid}; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:322:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 68)))) + 31)-:32] = i_sb_awaddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:323:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 36)))) + 7)-:8] = i_sb_awlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:324:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 28)))) + 2)-:3] = i_sb_awsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:325:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 25)))) + 1)-:2] = i_sb_awburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:326:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 23) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 23)))] = i_sb_awlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:327:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 22)))) + 3)-:4] = i_sb_awcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:328:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 18)))) + 2)-:3] = i_sb_awprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:329:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 11)))) + 3)-:4] = i_sb_awregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:330:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 15)))) + 3)-:4] = i_sb_awqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:331:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) - 7)))) + 5)-:6] = 6'd0; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:332:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))))] = i_sb_awvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:333:4 + assign o_sb_awready = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (11 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:334:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 66)))) + 3)-:4] = {3'd0, i_sb_arid}; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:335:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 62)))) + 31)-:32] = i_sb_araddr; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:336:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 30)))) + 7)-:8] = i_sb_arlen; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:337:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 22)))) + 2)-:3] = i_sb_arsize; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:338:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 19)))) + 1)-:2] = i_sb_arburst; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:339:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 17) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 17)))] = i_sb_arlock; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:340:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 16)))) + 3)-:4] = i_sb_arcache; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:341:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 12)))) + 2)-:3] = i_sb_arprot; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:342:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 5)))) + 3)-:4] = i_sb_arregion; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:343:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) - 9)))) + 3)-:4] = i_sb_arqos; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:344:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 : (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 0)] = i_sb_arvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:345:4 + assign o_sb_arready = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (10 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:346:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74)))) + 63)-:64] = i_sb_wdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:347:4 + assign masters_req[(((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10))) : ((2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10)))) + 7)-:8] = i_sb_wstrb; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:348:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2)))] = i_sb_wlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:349:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (2 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))] = i_sb_wvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:350:4 + assign o_sb_wready = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (9 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:351:4 + assign o_sb_bid = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (((7 + ((32'd4 + 32'd64) + 4)) - 3) >= ((7 + ((32'd4 + 32'd64) + 4)) - 3) ? (7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3 : (((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3) + (((7 + ((32'd4 + 32'd64) + 4)) - 3) >= ((7 + ((32'd4 + 32'd64) + 4)) - 3) ? (((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3) - ((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3)) + 1 : (((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3) - ((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3)) + 1)) - 1)-:(((7 + ((32'd4 + 32'd64) + 4)) - 3) >= ((7 + ((32'd4 + 32'd64) + 4)) - 3) ? (((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3) - ((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3)) + 1 : (((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3) - ((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 3)) + 1)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:352:4 + assign o_sb_bresp = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + ((7 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 4)-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:353:4 + assign o_sb_bvalid = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (8 + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:354:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))] = i_sb_bready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:355:4 + assign o_sb_rid = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + ((((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) >= (((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) ? ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69) : ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69)) + ((((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) >= (((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) ? ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69))) + 1 : ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69))) + 1)) - 1)-:((((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) >= (((32'd4 + 32'd64) + 3) - ((32'd4 + 32'd64) - 65)) ? ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69))) + 1 : ((((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69)) - (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 69))) + 1)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:356:4 + assign o_sb_rdata = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 68))-:64]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:357:4 + assign o_sb_rresp = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 4))-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:358:4 + assign o_sb_rlast = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + (((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) - 2))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:359:4 + assign o_sb_rvalid = masters_resp[(2 * (12 + (((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth))) + ((((AxiIdWidthMasters + AxiDataWidth) + 3) + AxiUserWidth) + 0)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:360:4 + assign masters_req[(2 * (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1))) + (((((((32'd4 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd4 + 32'd32) + 30)) + 1) >= 0 ? 0 : (((((((AxiIdWidthMasters + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthMasters + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)] = i_sb_rready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:363:4 + assign o_io_awid = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74)))) + 5)-:6]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:364:4 + assign o_io_awaddr = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68)))) + 31)-:32]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:365:4 + assign o_io_awlen = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36)))) + 7)-:8]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:366:4 + assign o_io_awsize = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:367:4 + assign o_io_awburst = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25)))) + 1)-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:368:4 + assign o_io_awlock = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 23) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 23)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:369:4 + assign o_io_awcache = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:370:4 + assign o_io_awprot = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:371:4 + assign o_io_awregion = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:372:4 + assign o_io_awqos = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:373:4 + assign o_io_awvalid = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:374:4 + assign slaves_resp[13 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)] = i_io_awready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:375:4 + assign o_io_arid = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68)))) + 5)-:6]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:376:4 + assign o_io_araddr = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62)))) + 31)-:32]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:377:4 + assign o_io_arlen = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30)))) + 7)-:8]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:378:4 + assign o_io_arsize = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:379:4 + assign o_io_arburst = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19)))) + 1)-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:380:4 + assign o_io_arlock = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 17) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 17)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:381:4 + assign o_io_arcache = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:382:4 + assign o_io_arprot = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:383:4 + assign o_io_arregion = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:384:4 + assign o_io_arqos = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:385:4 + assign o_io_arvalid = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 1 : (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 0)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:386:4 + assign slaves_resp[12 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)] = i_io_arready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:387:4 + assign o_io_wdata = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74)))) + 63)-:64]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:388:4 + assign o_io_wstrb = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10))) : (0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10)))) + 7)-:8]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:389:4 + assign o_io_wlast = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:390:4 + assign o_io_wvalid = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:391:4 + assign slaves_resp[11 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)] = i_io_wready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:392:4 + assign slaves_resp[9 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)-:6] = i_io_bid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:393:4 + assign slaves_resp[(9 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 6-:2] = i_io_bresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:394:4 + assign slaves_resp[10 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)] = i_io_bvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:395:4 + assign o_io_bready = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:396:4 + assign slaves_resp[0 + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 74))-:6] = i_io_rid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:397:4 + assign slaves_resp[0 + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 68))-:64] = i_io_rdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:398:4 + assign slaves_resp[0 + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 4))-:2] = i_io_rresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:399:4 + assign slaves_resp[0 + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 2))] = i_io_rlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:400:4 + assign slaves_resp[0 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)] = i_io_rvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:401:4 + assign o_io_rready = slaves_req[0 + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 : (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:404:4 + assign o_ram_awid = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 74)))) + 5)-:6]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:405:4 + assign o_ram_awaddr = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 68)))) + 31)-:32]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:406:4 + assign o_ram_awlen = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 36)))) + 7)-:8]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:407:4 + assign o_ram_awsize = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 28)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:408:4 + assign o_ram_awburst = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 25)))) + 1)-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:409:4 + assign o_ram_awlock = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 23) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 23)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:410:4 + assign o_ram_awcache = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 22)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:411:4 + assign o_ram_awprot = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 18)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:412:4 + assign o_ram_awregion = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 11)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:413:4 + assign o_ram_awqos = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))))) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) - 15)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:414:4 + assign o_ram_awvalid = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:415:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (13 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0))] = i_ram_awready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:416:4 + assign o_ram_arid = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 68)))) + 5)-:6]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:417:4 + assign o_ram_araddr = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 62)))) + 31)-:32]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:418:4 + assign o_ram_arlen = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 30)))) + 7)-:8]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:419:4 + assign o_ram_arsize = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 22)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:420:4 + assign o_ram_arburst = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 19)))) + 1)-:2]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:421:4 + assign o_ram_arlock = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 17) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 17)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:422:4 + assign o_ram_arcache = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 16)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:423:4 + assign o_ram_arprot = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 12)))) + 2)-:3]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:424:4 + assign o_ram_arregion = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 5)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:425:4 + assign o_ram_arqos = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) - ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) - 9)))) + 3)-:4]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:426:4 + assign o_ram_arvalid = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 1 : (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 0)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:427:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (12 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0))] = i_ram_arready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:428:4 + assign o_ram_wdata = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 74)))) + 63)-:64]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:429:4 + assign o_ram_wstrb = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10))) : ((((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 10)))) + 7)-:8]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:430:4 + assign o_ram_wlast = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) + (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1))) - ((((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth) - 2)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:431:4 + assign o_ram_wvalid = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (2 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:432:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (11 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0))] = i_ram_wready; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:433:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (9 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0))-:6] = i_ram_bid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:434:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + ((9 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)) - 6)-:2] = i_ram_bresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:435:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (10 + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0))] = i_ram_bvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:436:4 + assign o_ram_bready = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 1 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1) : ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1) - (1 + ((((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth) + 1)))]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:437:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 74))-:6] = i_ram_rid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:438:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 68))-:64] = i_ram_rdata; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:439:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 4))-:2] = i_ram_rresp; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:440:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + (((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 1) - ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) - 2))] = i_ram_rlast; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:441:4 + assign slaves_resp[(14 + (((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth)) + ((((AxiIdWidthSlaves + AxiDataWidth) + 3) + AxiUserWidth) + 0)] = i_ram_rvalid; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:442:4 + assign o_ram_rready = slaves_req[(((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 2 : 1 - ((((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)) + (((((((32'd6 + 32'd32) + 37) + ((32'd64 + 32'd8) + 2)) + 2) + ((32'd6 + 32'd32) + 30)) + 1) >= 0 ? 0 : (((((((AxiIdWidthSlaves + AxiAddrWidth) + 35) + AxiUserWidth) + 1) + (((AxiDataWidth + AxiStrbWidth) + 1) + AxiUserWidth)) + 2) + (((AxiIdWidthSlaves + AxiAddrWidth) + 29) + AxiUserWidth)) + 1)]; + // Trace: ./src/veerwolf-intercon_0.7.5/axi_intercon.v:445:1 + localparam [298:0] sv2v_uu_axi_xbar_Cfg = xbar_cfg; + // removed localparam type sv2v_uu_axi_xbar_default_mst_port_i + localparam [(sv2v_uu_axi_xbar_Cfg[298-:32] * $clog2(sv2v_uu_axi_xbar_Cfg[266-:32])) - 1:0] sv2v_uu_axi_xbar_ext_default_mst_port_i_0 = 1'sb0; + axi_xbar_69337_92F22 #( + .mst_ar_chan_t_AxiAddrWidth(AxiAddrWidth), + .mst_ar_chan_t_AxiIdWidthSlaves(AxiIdWidthSlaves), + .mst_ar_chan_t_AxiUserWidth(AxiUserWidth), + .mst_aw_chan_t_AxiAddrWidth(AxiAddrWidth), + .mst_aw_chan_t_AxiIdWidthSlaves(AxiIdWidthSlaves), + .mst_aw_chan_t_AxiUserWidth(AxiUserWidth), + .mst_b_chan_t_AxiIdWidthSlaves(AxiIdWidthSlaves), + .mst_b_chan_t_AxiUserWidth(AxiUserWidth), + .mst_r_chan_t_AxiDataWidth(AxiDataWidth), + .mst_r_chan_t_AxiIdWidthSlaves(AxiIdWidthSlaves), + .mst_r_chan_t_AxiUserWidth(AxiUserWidth), + .mst_req_t_AxiAddrWidth(AxiAddrWidth), + .mst_req_t_AxiDataWidth(AxiDataWidth), + .mst_req_t_AxiIdWidthSlaves(AxiIdWidthSlaves), + .mst_req_t_AxiStrbWidth(AxiStrbWidth), + .mst_req_t_AxiUserWidth(AxiUserWidth), + .mst_resp_t_AxiDataWidth(AxiDataWidth), + .mst_resp_t_AxiIdWidthSlaves(AxiIdWidthSlaves), + .mst_resp_t_AxiUserWidth(AxiUserWidth), + .slv_ar_chan_t_AxiAddrWidth(AxiAddrWidth), + .slv_ar_chan_t_AxiIdWidthMasters(AxiIdWidthMasters), + .slv_ar_chan_t_AxiUserWidth(AxiUserWidth), + .slv_aw_chan_t_AxiAddrWidth(AxiAddrWidth), + .slv_aw_chan_t_AxiIdWidthMasters(AxiIdWidthMasters), + .slv_aw_chan_t_AxiUserWidth(AxiUserWidth), + .slv_b_chan_t_AxiIdWidthMasters(AxiIdWidthMasters), + .slv_b_chan_t_AxiUserWidth(AxiUserWidth), + .slv_r_chan_t_AxiDataWidth(AxiDataWidth), + .slv_r_chan_t_AxiIdWidthMasters(AxiIdWidthMasters), + .slv_r_chan_t_AxiUserWidth(AxiUserWidth), + .slv_req_t_AxiAddrWidth(AxiAddrWidth), + .slv_req_t_AxiDataWidth(AxiDataWidth), + .slv_req_t_AxiIdWidthMasters(AxiIdWidthMasters), + .slv_req_t_AxiStrbWidth(AxiStrbWidth), + .slv_req_t_AxiUserWidth(AxiUserWidth), + .slv_resp_t_AxiDataWidth(AxiDataWidth), + .slv_resp_t_AxiIdWidthMasters(AxiIdWidthMasters), + .slv_resp_t_AxiUserWidth(AxiUserWidth), + .w_chan_t_AxiDataWidth(AxiDataWidth), + .w_chan_t_AxiStrbWidth(AxiStrbWidth), + .w_chan_t_AxiUserWidth(AxiUserWidth), + .Cfg(xbar_cfg), + .ATOPs(1'b0) + ) axi_xbar( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_i(1'b0), + .slv_ports_req_i(masters_req), + .slv_ports_resp_o(masters_resp), + .mst_ports_req_o(slaves_req), + .mst_ports_resp_i(slaves_resp), + .addr_map_i(AddrMap), + .en_default_mst_port_i(3'd0), + .default_mst_port_i(sv2v_uu_axi_xbar_ext_default_mst_port_i_0) + ); +endmodule +// Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:3:1 +`default_nettype none +module wb_intercon ( + wb_clk_i, + wb_rst_i, + wb_io_adr_i, + wb_io_dat_i, + wb_io_sel_i, + wb_io_we_i, + wb_io_cyc_i, + wb_io_stb_i, + wb_io_cti_i, + wb_io_bte_i, + wb_io_rdt_o, + wb_io_ack_o, + wb_io_err_o, + wb_io_rty_o, + wb_rom_adr_o, + wb_rom_dat_o, + wb_rom_sel_o, + wb_rom_we_o, + wb_rom_cyc_o, + wb_rom_stb_o, + wb_rom_cti_o, + wb_rom_bte_o, + wb_rom_rdt_i, + wb_rom_ack_i, + wb_rom_err_i, + wb_rom_rty_i, + wb_sys_adr_o, + wb_sys_dat_o, + wb_sys_sel_o, + wb_sys_we_o, + wb_sys_cyc_o, + wb_sys_stb_o, + wb_sys_cti_o, + wb_sys_bte_o, + wb_sys_rdt_i, + wb_sys_ack_i, + wb_sys_err_i, + wb_sys_rty_i, + wb_uart_adr_o, + wb_uart_dat_o, + wb_uart_sel_o, + wb_uart_we_o, + wb_uart_cyc_o, + wb_uart_stb_o, + wb_uart_cti_o, + wb_uart_bte_o, + wb_uart_rdt_i, + wb_uart_ack_i, + wb_uart_err_i, + wb_uart_rty_i +); + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:5:5 + input wire wb_clk_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:6:5 + input wire wb_rst_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:7:5 + input wire [31:0] wb_io_adr_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:8:5 + input wire [31:0] wb_io_dat_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:9:5 + input wire [3:0] wb_io_sel_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:10:5 + input wire wb_io_we_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:11:5 + input wire wb_io_cyc_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:12:5 + input wire wb_io_stb_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:13:5 + input wire [2:0] wb_io_cti_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:14:5 + input wire [1:0] wb_io_bte_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:15:5 + output wire [31:0] wb_io_rdt_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:16:5 + output wire wb_io_ack_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:17:5 + output wire wb_io_err_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:18:5 + output wire wb_io_rty_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:19:5 + output wire [31:0] wb_rom_adr_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:20:5 + output wire [31:0] wb_rom_dat_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:21:5 + output wire [3:0] wb_rom_sel_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:22:5 + output wire wb_rom_we_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:23:5 + output wire wb_rom_cyc_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:24:5 + output wire wb_rom_stb_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:25:5 + output wire [2:0] wb_rom_cti_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:26:5 + output wire [1:0] wb_rom_bte_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:27:5 + input wire [31:0] wb_rom_rdt_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:28:5 + input wire wb_rom_ack_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:29:5 + input wire wb_rom_err_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:30:5 + input wire wb_rom_rty_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:31:5 + output wire [31:0] wb_sys_adr_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:32:5 + output wire [31:0] wb_sys_dat_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:33:5 + output wire [3:0] wb_sys_sel_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:34:5 + output wire wb_sys_we_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:35:5 + output wire wb_sys_cyc_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:36:5 + output wire wb_sys_stb_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:37:5 + output wire [2:0] wb_sys_cti_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:38:5 + output wire [1:0] wb_sys_bte_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:39:5 + input wire [31:0] wb_sys_rdt_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:40:5 + input wire wb_sys_ack_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:41:5 + input wire wb_sys_err_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:42:5 + input wire wb_sys_rty_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:43:5 + output wire [31:0] wb_uart_adr_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:44:5 + output wire [31:0] wb_uart_dat_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:45:5 + output wire [3:0] wb_uart_sel_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:46:5 + output wire wb_uart_we_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:47:5 + output wire wb_uart_cyc_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:48:5 + output wire wb_uart_stb_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:49:5 + output wire [2:0] wb_uart_cti_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:50:5 + output wire [1:0] wb_uart_bte_o; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:51:5 + input wire [31:0] wb_uart_rdt_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:52:5 + input wire wb_uart_ack_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:53:5 + input wire wb_uart_err_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:54:5 + input wire wb_uart_rty_i; + // Trace: ./src/veerwolf-wb_nospi_intercon_0.7.5/wb_intercon.v:56:1 + wb_mux #( + .num_devices(3), + .MATCH_ADDR(96'h000000000000100000002000), + .MATCH_MASK(96'hfffff000ffffffc0fffff000) + ) wb_mux_io( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wbm_adr_i(wb_io_adr_i), + .wbm_dat_i(wb_io_dat_i), + .wbm_sel_i(wb_io_sel_i), + .wbm_we_i(wb_io_we_i), + .wbm_cyc_i(wb_io_cyc_i), + .wbm_stb_i(wb_io_stb_i), + .wbm_cti_i(wb_io_cti_i), + .wbm_bte_i(wb_io_bte_i), + .wbm_dat_o(wb_io_rdt_o), + .wbm_ack_o(wb_io_ack_o), + .wbm_err_o(wb_io_err_o), + .wbm_rty_o(wb_io_rty_o), + .wbs_adr_o({wb_rom_adr_o, wb_sys_adr_o, wb_uart_adr_o}), + .wbs_dat_o({wb_rom_dat_o, wb_sys_dat_o, wb_uart_dat_o}), + .wbs_sel_o({wb_rom_sel_o, wb_sys_sel_o, wb_uart_sel_o}), + .wbs_we_o({wb_rom_we_o, wb_sys_we_o, wb_uart_we_o}), + .wbs_cyc_o({wb_rom_cyc_o, wb_sys_cyc_o, wb_uart_cyc_o}), + .wbs_stb_o({wb_rom_stb_o, wb_sys_stb_o, wb_uart_stb_o}), + .wbs_cti_o({wb_rom_cti_o, wb_sys_cti_o, wb_uart_cti_o}), + .wbs_bte_o({wb_rom_bte_o, wb_sys_bte_o, wb_uart_bte_o}), + .wbs_dat_i({wb_rom_rdt_i, wb_sys_rdt_i, wb_uart_rdt_i}), + .wbs_ack_i({wb_rom_ack_i, wb_sys_ack_i, wb_uart_ack_i}), + .wbs_err_i({wb_rom_err_i, wb_sys_err_i, wb_uart_err_i}), + .wbs_rty_i({wb_rom_rty_i, wb_sys_rty_i, wb_uart_rty_i}) + ); +endmodule \ No newline at end of file diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/pack_rom.vh b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/pack_rom.vh new file mode 100644 index 0000000000000000000000000000000000000000..565018fd1996f8d919ada067689784d24a86a0c2 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/pack_rom.vh @@ -0,0 +1,15 @@ +800015B780002537 +08000E1301058593 +01B00E9301C50623 +00300E1301D50023 +08700E1301C50623 +0005022301C50423 +001FFF9301450F83 +00054283000F8E63 +020FFF9301450F83 +00128293FE0F8CE3 +0005D30300550023 +0065912300130313 +800015B7FD1FF06F +0005A02300958593 +0000000000000000 diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/cdc_utils_0.1-r1/rtl/verilog/cc561.v b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/cdc_utils_0.1-r1/rtl/verilog/cc561.v new file mode 100644 index 0000000000000000000000000000000000000000..3f7648ca3ae828ba951293d6f84dc452f0c39f4c --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/cdc_utils_0.1-r1/rtl/verilog/cc561.v @@ -0,0 +1,51 @@ +/* +cdc_utils by Olof Kindgren +To the extent possible under law, the person who associated CC0 with +cdc_utils has waived all copyright and related or neighboring rights +to cdc_utils + +You should have received a copy of the CC0 legalcode along with this +work. If not, see . + +Verilog implementation of "MCP formulation using a synchronized enable pulse" +from chapter 5.6.1 in Clifford Cummings "Clock Domain Crossing (CDC) Design & +Verification Techniques Using SystemVerilog" +http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf +*/ + +module cc561 + #(parameter DW=0) + (input aclk, + input arst, + input [DW-1:0] adata, + input aen, + input bclk, + output reg [DW-1:0] bdata, + output reg ben); + + reg [DW-1:0] adata_r; + reg aen_r = 1'b0; + wire bpulse; + + always @(posedge aclk) begin + if (aen) + adata_r <= adata; + + aen_r <= aen ^ aen_r; + if (arst) + aen_r <= 1'b0; + end + + always @(posedge bclk) begin + if (bpulse) + bdata <= adata_r; //CDC + ben <= bpulse; + end + + sync2_pgen sync2_pgen + (.c (bclk), + .d (aen_r), //CDC + .p (bpulse), + .q ()); + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/cdc_utils_0.1-r1/rtl/verilog/sync2_pgen.v b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/cdc_utils_0.1-r1/rtl/verilog/sync2_pgen.v new file mode 100644 index 0000000000000000000000000000000000000000..71a94c956bee4f18ed3bbbd64e221dbd4a3ffaca --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/cdc_utils_0.1-r1/rtl/verilog/sync2_pgen.v @@ -0,0 +1,32 @@ +/* +cdc_utils by Olof Kindgren +To the extent possible under law, the person who associated CC0 with +cdc_utils has waived all copyright and related or neighboring rights +to cdc_utils + +You should have received a copy of the CC0 legalcode along with this +work. If not, see . + +Verilog implementation of "Synchronized pulse generation logic" +from chapter 5.6.1 in Clifford Cummings "Clock Domain Crossing (CDC) Design & +Verification Techniques Using SystemVerilog" +http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf +*/ +module sync2_pgen + (input c, + input d, + output p, + output q); + + reg q1, q2, q3; + + always @(posedge c) begin + q1 <= d; + q2 <= q1; + q3 <= q2; + end + + assign p = q2 ^ q3; + assign q = q3; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv new file mode 100644 index 0000000000000000000000000000000000000000..ef575392503b8763376bc5dea24a813a56761d74 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dbg/el2_dbg.sv @@ -0,0 +1,758 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//******************************************************************************** +// $Id$ +// +// Function: Top level VeeR core file to control the debug mode +// Comments: Responsible to put the rest of the core in quiesce mode, +// Send the commands/address. sends WrData and Recieve read Data. +// And then Resume the core to do the normal mode +// Author : +//******************************************************************************** +module el2_dbg +import el2_pkg::*; +#( +`include "el2_param.vh" + )( + // outputs to the core for command and data interface + output logic [31:0] dbg_cmd_addr, + output logic [31:0] dbg_cmd_wrdata, + output logic dbg_cmd_valid, + output logic dbg_cmd_write, // 1: write command, 0: read_command + output logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory + output logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command + output logic dbg_core_rst_l, // core reset from dm + + // inputs back from the core/dec + input logic [31:0] core_dbg_rddata, + input logic core_dbg_cmd_done, // This will be treated like a valid signal + input logic core_dbg_cmd_fail, // Exception during command run + + // Signals to dma to get a bubble + output logic dbg_dma_bubble, // Debug needs a bubble to send a valid + input logic dma_dbg_ready, // DMA is ready to accept debug request + + // interface with the rest of the core to halt/resume handshaking + output logic dbg_halt_req, // This is a pulse + output logic dbg_resume_req, // Debug sends a resume requests. Pulse + input logic dec_tlu_debug_mode, // Core is in debug mode + input logic dec_tlu_dbg_halted, // The core has finished the queiscing sequence. Core is halted now + input logic dec_tlu_mpc_halted_only, // Only halted due to MPC + input logic dec_tlu_resume_ack, // core sends back an ack for the resume (pulse) + + // inputs from the JTAG + input logic dmi_reg_en, // read or write + input logic [6:0] dmi_reg_addr, // address of DM register + input logic dmi_reg_wr_en, // write instruction + input logic [31:0] dmi_reg_wdata, // write data + + // output + output logic [31:0] dmi_reg_rdata, // read data + + // AXI Write Channels + output logic sb_axi_awvalid, + input logic sb_axi_awready, + output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid, + output logic [31:0] sb_axi_awaddr, + output logic [3:0] sb_axi_awregion, + output logic [7:0] sb_axi_awlen, + output logic [2:0] sb_axi_awsize, + output logic [1:0] sb_axi_awburst, + output logic sb_axi_awlock, + output logic [3:0] sb_axi_awcache, + output logic [2:0] sb_axi_awprot, + output logic [3:0] sb_axi_awqos, + + output logic sb_axi_wvalid, + input logic sb_axi_wready, + output logic [63:0] sb_axi_wdata, + output logic [7:0] sb_axi_wstrb, + output logic sb_axi_wlast, + + input logic sb_axi_bvalid, + output logic sb_axi_bready, + input logic [1:0] sb_axi_bresp, + + // AXI Read Channels + output logic sb_axi_arvalid, + input logic sb_axi_arready, + output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid, + output logic [31:0] sb_axi_araddr, + output logic [3:0] sb_axi_arregion, + output logic [7:0] sb_axi_arlen, + output logic [2:0] sb_axi_arsize, + output logic [1:0] sb_axi_arburst, + output logic sb_axi_arlock, + output logic [3:0] sb_axi_arcache, + output logic [2:0] sb_axi_arprot, + output logic [3:0] sb_axi_arqos, + + input logic sb_axi_rvalid, + output logic sb_axi_rready, + input logic [63:0] sb_axi_rdata, + input logic [1:0] sb_axi_rresp, + + input logic dbg_bus_clk_en, + + // general inputs + input logic clk, + input logic free_clk, + input logic rst_l, // This includes both top rst and debug rst + input logic dbg_rst_l, + input logic clk_override, + input logic scan_mode +); + + + typedef enum logic [3:0] {IDLE=4'h0, HALTING=4'h1, HALTED=4'h2, CORE_CMD_START=4'h3, CORE_CMD_WAIT=4'h4, SB_CMD_START=4'h5, SB_CMD_SEND=4'h6, SB_CMD_RESP=4'h7, CMD_DONE=4'h8, RESUMING=4'h9} state_t; + typedef enum logic [3:0] {SBIDLE=4'h0, WAIT_RD=4'h1, WAIT_WR=4'h2, CMD_RD=4'h3, CMD_WR=4'h4, CMD_WR_ADDR=4'h5, CMD_WR_DATA=4'h6, RSP_RD=4'h7, RSP_WR=4'h8, DONE=4'h9} sb_state_t; + + state_t dbg_state; + state_t dbg_nxtstate; + logic dbg_state_en; + // these are the registers that the debug module implements + logic [31:0] dmstatus_reg; // [26:24]-dmerr, [17:16]-resume ack, [9:8]-halted, [3:0]-version + logic [31:0] dmcontrol_reg; // dmcontrol register has only 6 bits implemented. 31: haltreq, 30: resumereq, 29: haltreset, 28: ackhavereset, 1: ndmreset, 0: dmactive. + logic [31:0] command_reg; + logic [31:0] abstractcs_reg; // bits implemted are [12] - busy and [10:8]= command error + logic [31:0] haltsum0_reg; + logic [31:0] data0_reg; + logic [31:0] data1_reg; + + // data 0 + logic [31:0] data0_din; + logic data0_reg_wren, data0_reg_wren0, data0_reg_wren1, data0_reg_wren2; + // data 1 + logic [31:0] data1_din; + logic data1_reg_wren, data1_reg_wren0, data1_reg_wren1; + // abstractcs + logic abstractcs_busy_wren; + logic abstractcs_busy_din; + logic [2:0] abstractcs_error_din; + logic abstractcs_error_sel0, abstractcs_error_sel1, abstractcs_error_sel2, abstractcs_error_sel3, abstractcs_error_sel4, abstractcs_error_sel5, abstractcs_error_sel6; + logic dbg_sb_bus_error; + // abstractauto + logic abstractauto_reg_wren; + logic [1:0] abstractauto_reg; + + // dmstatus + logic dmstatus_resumeack_wren; + logic dmstatus_resumeack_din; + logic dmstatus_haveresetn_wren; + logic dmstatus_resumeack; + logic dmstatus_unavail; + logic dmstatus_running; + logic dmstatus_halted; + logic dmstatus_havereset, dmstatus_haveresetn; + + // dmcontrol + logic resumereq; + logic dmcontrol_wren, dmcontrol_wren_Q; + // command + logic execute_command_ns, execute_command; + logic command_wren, command_regno_wren; + logic command_transfer_din; + logic command_postexec_din; + logic [31:0] command_din; + logic [3:0] dbg_cmd_addr_incr; + logic [31:0] dbg_cmd_curr_addr; + logic [31:0] dbg_cmd_next_addr; + + // needed to send the read data back for dmi reads + logic [31:0] dmi_reg_rdata_din; + + sb_state_t sb_state; + sb_state_t sb_nxtstate; + logic sb_state_en; + + //System bus section + logic sbcs_wren; + logic sbcs_sbbusy_wren; + logic sbcs_sbbusy_din; + logic sbcs_sbbusyerror_wren; + logic sbcs_sbbusyerror_din; + + logic sbcs_sberror_wren; + logic [2:0] sbcs_sberror_din; + logic sbcs_unaligned; + logic sbcs_illegal_size; + logic [19:15] sbcs_reg_int; + + // data + logic sbdata0_reg_wren0; + logic sbdata0_reg_wren1; + logic sbdata0_reg_wren; + logic [31:0] sbdata0_din; + + logic sbdata1_reg_wren0; + logic sbdata1_reg_wren1; + logic sbdata1_reg_wren; + logic [31:0] sbdata1_din; + + logic sbaddress0_reg_wren0; + logic sbaddress0_reg_wren1; + logic sbaddress0_reg_wren; + logic [31:0] sbaddress0_reg_din; + logic [3:0] sbaddress0_incr; + logic sbreadonaddr_access; + logic sbreadondata_access; + logic sbdata0wr_access; + + logic sb_abmem_cmd_done_in, sb_abmem_data_done_in; + logic sb_abmem_cmd_done_en, sb_abmem_data_done_en; + logic sb_abmem_cmd_done, sb_abmem_data_done; + logic [31:0] abmem_addr; + logic abmem_addr_in_dccm_region, abmem_addr_in_iccm_region, abmem_addr_in_pic_region; + logic abmem_addr_core_local; + logic abmem_addr_external; + + logic sb_cmd_pending, sb_abmem_cmd_pending; + logic sb_abmem_cmd_write; + logic [2:0] sb_abmem_cmd_size; + logic [31:0] sb_abmem_cmd_addr; + logic [31:0] sb_abmem_cmd_wdata; + + logic [2:0] sb_cmd_size; + logic [31:0] sb_cmd_addr; + logic [63:0] sb_cmd_wdata; + + logic sb_bus_cmd_read, sb_bus_cmd_write_addr, sb_bus_cmd_write_data; + logic sb_bus_rsp_read, sb_bus_rsp_write; + logic sb_bus_rsp_error; + logic [63:0] sb_bus_rdata; + + //registers + logic [31:0] sbcs_reg; + logic [31:0] sbaddress0_reg; + logic [31:0] sbdata0_reg; + logic [31:0] sbdata1_reg; + + logic sb_abmem_cmd_arvalid, sb_abmem_cmd_awvalid, sb_abmem_cmd_wvalid; + logic sb_abmem_read_pend; + logic sb_cmd_awvalid, sb_cmd_wvalid, sb_cmd_arvalid; + logic sb_read_pend; + logic [31:0] sb_axi_addr; + logic [63:0] sb_axi_wrdata; + logic [2:0] sb_axi_size; + + logic dbg_dm_rst_l; + logic rst_l_sync; + + //clken + logic dbg_free_clken; + logic dbg_free_clk; + + logic sb_free_clken; + logic sb_free_clk; + + // clocking + // used for the abstract commands. + assign dbg_free_clken = dmi_reg_en | execute_command | (dbg_state != IDLE) | dbg_state_en | dec_tlu_dbg_halted | dec_tlu_mpc_halted_only | dec_tlu_debug_mode | dbg_halt_req | clk_override; + + // used for the system bus + assign sb_free_clken = dmi_reg_en | execute_command | sb_state_en | (sb_state != SBIDLE) | clk_override; + + rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*); + rvoclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*); + + // end clocking section + + // Reset logic + assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode); + assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode; + + // synchronize the rst + rvsyncss #(1) rstl_syncff (.din(rst_l), .dout(rst_l_sync), .clk(free_clk), .rst_l(dbg_rst_l)); + + // system bus register + // sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal + assign sbcs_reg[31:29] = 3'b1; + assign sbcs_reg[28:23] = '0; + assign sbcs_reg[19:15] = {sbcs_reg_int[19], ~sbcs_reg_int[18], sbcs_reg_int[17:15]}; + assign sbcs_reg[11:5] = 7'h20; + assign sbcs_reg[4:0] = 5'b01111; + assign sbcs_wren = (dmi_reg_addr == 7'h38) & dmi_reg_en & dmi_reg_wr_en & (sb_state == SBIDLE); + assign sbcs_sbbusyerror_wren = (sbcs_wren & dmi_reg_wdata[22]) | + (sbcs_reg[21] & dmi_reg_en & ((dmi_reg_wr_en & (dmi_reg_addr == 7'h39)) | (dmi_reg_addr == 7'h3c) | (dmi_reg_addr == 7'h3d))); + assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]); // Clear when writing one + + rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); + rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); + rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); + rvdffs #(5) sbcs_misc_reg (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}), + .dout(sbcs_reg_int[19:15]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); + rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); + + assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) | + ((sbcs_reg[19:17] == 3'b010) & (|sbaddress0_reg[1:0])) | + ((sbcs_reg[19:17] == 3'b011) & (|sbaddress0_reg[2:0])); + + assign sbcs_illegal_size = sbcs_reg[19]; // Anything bigger than 64 bits is illegal + + assign sbaddress0_incr[3:0] = ({4{(sbcs_reg[19:17] == 3'h0)}} & 4'b0001) | + ({4{(sbcs_reg[19:17] == 3'h1)}} & 4'b0010) | + ({4{(sbcs_reg[19:17] == 3'h2)}} & 4'b0100) | + ({4{(sbcs_reg[19:17] == 3'h3)}} & 4'b1000); + + // sbdata + assign sbdata0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3c); // write data only when single read is 0 + assign sbdata0_reg_wren1 = (sb_state == RSP_RD) & sb_state_en & ~sbcs_sberror_wren; + assign sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1; + + assign sbdata1_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3d); // write data only when single read is 0; + assign sbdata1_reg_wren1 = (sb_state == RSP_RD) & sb_state_en & ~sbcs_sberror_wren; + assign sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1; + + assign sbdata0_din[31:0] = ({32{sbdata0_reg_wren0}} & dmi_reg_wdata[31:0]) | + ({32{sbdata0_reg_wren1}} & sb_bus_rdata[31:0]); + assign sbdata1_din[31:0] = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) | + ({32{sbdata1_reg_wren1}} & sb_bus_rdata[63:32]); + + rvdffe #(32) dbg_sbdata0_reg (.*, .din(sbdata0_din[31:0]), .dout(sbdata0_reg[31:0]), .en(sbdata0_reg_wren), .rst_l(dbg_dm_rst_l)); + rvdffe #(32) dbg_sbdata1_reg (.*, .din(sbdata1_din[31:0]), .dout(sbdata1_reg[31:0]), .en(sbdata1_reg_wren), .rst_l(dbg_dm_rst_l)); + + // sbaddress + assign sbaddress0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39); + assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; + assign sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) | + ({32{sbaddress0_reg_wren1}} & (sbaddress0_reg[31:0] + {28'b0,sbaddress0_incr[3:0]})); + rvdffe #(32) dbg_sbaddress0_reg (.*, .din(sbaddress0_reg_din[31:0]), .dout(sbaddress0_reg[31:0]), .en(sbaddress0_reg_wren), .rst_l(dbg_dm_rst_l)); + + assign sbreadonaddr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39) & sbcs_reg[20]; // if readonaddr is set the next command will start upon writing of addr0 + assign sbreadondata_access = dmi_reg_en & ~dmi_reg_wr_en & (dmi_reg_addr == 7'h3c) & sbcs_reg[15]; // if readondata is set the next command will start upon reading of data0 + assign sbdata0wr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3c); // write to sbdata0 will start write command to system bus + + // memory mapped registers + // dmcontrol register has only 5 bits implemented. 31: haltreq, 30: resumereq, 28: ackhavereset, 1: ndmreset, 0: dmactive. + // rest all the bits are zeroed out + // dmactive flop is reset based on core rst_l, all other flops use dm_rst_l + assign dmcontrol_wren = (dmi_reg_addr == 7'h10) & dmi_reg_en & dmi_reg_wr_en; + assign dmcontrol_reg[29] = '0; + assign dmcontrol_reg[27:2] = '0; + assign resumereq = dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q; + rvdffs #(4) dmcontrolff (.din({dmi_reg_wdata[31:30],dmi_reg_wdata[28],dmi_reg_wdata[1]}), .dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}), .en(dmcontrol_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); + rvdffs #(1) dmcontrol_dmactive_ff (.din(dmi_reg_wdata[0]), .dout(dmcontrol_reg[0]), .en(dmcontrol_wren), .rst_l(dbg_rst_l), .clk(dbg_free_clk)); + rvdff #(1) dmcontrol_wrenff(.din(dmcontrol_wren), .dout(dmcontrol_wren_Q), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); + + // dmstatus register bits that are implemented + // [19:18]-havereset,[17:16]-resume ack, [9:8]-halted, [3:0]-version + // rest all the bits are zeroed out + //assign dmstatus_wren = (dmi_reg_addr[31:0] == 32'h11) & dmi_reg_en; + assign dmstatus_reg[31:20] = '0; + assign dmstatus_reg[19:18] = {2{dmstatus_havereset}}; + assign dmstatus_reg[15:14] = '0; + assign dmstatus_reg[7] = '1; + assign dmstatus_reg[6:4] = '0; + assign dmstatus_reg[17:16] = {2{dmstatus_resumeack}}; + assign dmstatus_reg[13:12] = {2{dmstatus_unavail}}; + assign dmstatus_reg[11:10] = {2{dmstatus_running}}; + assign dmstatus_reg[9:8] = {2{dmstatus_halted}}; + assign dmstatus_reg[3:0] = 4'h2; + + assign dmstatus_resumeack_wren = ((dbg_state == RESUMING) & dec_tlu_resume_ack) | (dmstatus_resumeack & resumereq & dmstatus_halted); + assign dmstatus_resumeack_din = (dbg_state == RESUMING) & dec_tlu_resume_ack; + + assign dmstatus_haveresetn_wren = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[28] & dmi_reg_en & dmi_reg_wr_en & dmcontrol_reg[0]; // clear the havereset + assign dmstatus_havereset = ~dmstatus_haveresetn; + + assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l_sync; + assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted); + + rvdffs #(1) dmstatus_resumeack_reg (.din(dmstatus_resumeack_din), .dout(dmstatus_resumeack), .en(dmstatus_resumeack_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); + rvdff #(1) dmstatus_halted_reg (.din(dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only), .dout(dmstatus_halted), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); + rvdffs #(1) dmstatus_haveresetn_reg (.din(1'b1), .dout(dmstatus_haveresetn), .en(dmstatus_haveresetn_wren), .rst_l(rst_l), .clk(dbg_free_clk)); + + // haltsum0 register + assign haltsum0_reg[31:1] = '0; + assign haltsum0_reg[0] = dmstatus_halted; + + // abstractcs register + // bits implemted are [12] - busy and [10:8]= command error + assign abstractcs_reg[31:13] = '0; + assign abstractcs_reg[11] = '0; + assign abstractcs_reg[7:4] = '0; + assign abstractcs_reg[3:0] = 4'h2; // One data register + + assign abstractcs_error_sel0 = abstractcs_reg[12] & ~(|abstractcs_reg[10:8]) & dmi_reg_en & ((dmi_reg_wr_en & ((dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17)) | (dmi_reg_addr == 7'h18)) | + (dmi_reg_addr == 7'h4) | (dmi_reg_addr == 7'h5)); + assign abstractcs_error_sel1 = execute_command & ~(|abstractcs_reg[10:8]) & + ((~((command_reg[31:24] == 8'b0) | (command_reg[31:24] == 8'h2))) | // Illegal command + (((command_reg[22:20] == 3'b011) | (command_reg[22])) & (command_reg[31:24] == 8'h2)) | // Illegal abstract memory size (can't be DW or higher) + ((command_reg[22:20] != 3'b010) & ((command_reg[31:24] == 8'h0) & command_reg[17])) | // Illegal abstract reg size + ((command_reg[31:24] == 8'h0) & command_reg[18])); //postexec for abstract register access + assign abstractcs_error_sel2 = ((core_dbg_cmd_done & core_dbg_cmd_fail) | // exception from core + (execute_command & (command_reg[31:24] == 8'h0) & // unimplemented regs + (((command_reg[15:12] == 4'h1) & (command_reg[11:5] != 0)) | (command_reg[15:13] != 0)))) & ~(|abstractcs_reg[10:8]); + assign abstractcs_error_sel3 = execute_command & (dbg_state != HALTED) & ~(|abstractcs_reg[10:8]); + assign abstractcs_error_sel4 = dbg_sb_bus_error & dbg_bus_clk_en & ~(|abstractcs_reg[10:8]);// sb bus error for abstract memory command + assign abstractcs_error_sel5 = execute_command & (command_reg[31:24] == 8'h2) & ~(|abstractcs_reg[10:8]) & + (((command_reg[22:20] == 3'b001) & data1_reg[0]) | ((command_reg[22:20] == 3'b010) & (|data1_reg[1:0]))); //Unaligned address for abstract memory + assign abstractcs_error_sel6 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en; + + assign abstractcs_error_din[2:0] = abstractcs_error_sel0 ? 3'b001 : // writing command or abstractcs while a command was executing. Or accessing data0 + abstractcs_error_sel1 ? 3'b010 : // writing a illegal command type to cmd field of command + abstractcs_error_sel2 ? 3'b011 : // exception while running command + abstractcs_error_sel3 ? 3'b100 : // writing a comnand when not in the halted state + abstractcs_error_sel4 ? 3'b101 : // Bus error + abstractcs_error_sel5 ? 3'b111 : // unaligned or illegal size abstract memory command + abstractcs_error_sel6 ? (~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) : //W1C + abstractcs_reg[10:8]; //hold + + rvdffs #(1) dmabstractcs_busy_reg (.din(abstractcs_busy_din), .dout(abstractcs_reg[12]), .en(abstractcs_busy_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); + rvdff #(3) dmabstractcs_error_reg (.din(abstractcs_error_din[2:0]), .dout(abstractcs_reg[10:8]), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); + + // abstract auto reg + assign abstractauto_reg_wren = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h18) & ~abstractcs_reg[12]; + rvdffs #(2) dbg_abstractauto_reg (.*, .din(dmi_reg_wdata[1:0]), .dout(abstractauto_reg[1:0]), .en(abstractauto_reg_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk)); + + // command register - implemented all the bits in this register + // command[16] = 1: write, 0: read + assign execute_command_ns = command_wren | + (dmi_reg_en & ~abstractcs_reg[12] & (((dmi_reg_addr == 7'h4) & abstractauto_reg[0]) | ((dmi_reg_addr == 7'h5) & abstractauto_reg[1]))); + assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en; + assign command_regno_wren = command_wren | ((command_reg[31:24] == 8'h0) & command_reg[19] & (dbg_state == CMD_DONE) & ~(|abstractcs_reg[10:8])); // aarpostincrement + assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[18]; + assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17]; + assign command_din[31:16] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din, dmi_reg_wdata[16]}; + assign command_din[15:0] = command_wren ? dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0]; + rvdff #(1) execute_commandff (.*, .din(execute_command_ns), .dout(execute_command), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l)); + rvdffe #(16) dmcommand_reg (.*, .din(command_din[31:16]), .dout(command_reg[31:16]), .en(command_wren), .rst_l(dbg_dm_rst_l)); + rvdffe #(16) dmcommand_regno_reg (.*, .din(command_din[15:0]), .dout(command_reg[15:0]), .en(command_regno_wren), .rst_l(dbg_dm_rst_l)); + + // data0 reg + assign data0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h4) & (dbg_state == HALTED) & ~abstractcs_reg[12]); + assign data0_reg_wren1 = core_dbg_cmd_done & (dbg_state == CORE_CMD_WAIT) & ~command_reg[16]; + assign data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 | data0_reg_wren2; + + assign data0_din[31:0] = ({32{data0_reg_wren0}} & dmi_reg_wdata[31:0]) | + ({32{data0_reg_wren1}} & core_dbg_rddata[31:0]) | + ({32{data0_reg_wren2}} & sb_bus_rdata[31:0]); + + rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l)); + + // data 1 + assign data1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h5) & (dbg_state == HALTED) & ~abstractcs_reg[12]); + assign data1_reg_wren1 = (dbg_state == CMD_DONE) & (command_reg[31:24] == 8'h2) & command_reg[19] & ~(|abstractcs_reg[10:8]); // aampostincrement + assign data1_reg_wren = data1_reg_wren0 | data1_reg_wren1; + + assign data1_din[31:0] = ({32{data1_reg_wren0}} & dmi_reg_wdata[31:0]) | + ({32{data1_reg_wren1}} & dbg_cmd_next_addr[31:0]); + + rvdffe #(32) dbg_data1_reg (.*, .din(data1_din[31:0]), .dout(data1_reg[31:0]), .en(data1_reg_wren), .rst_l(dbg_dm_rst_l)); + + rvdffs #(1) sb_abmem_cmd_doneff (.din(sb_abmem_cmd_done_in), .dout(sb_abmem_cmd_done), .en(sb_abmem_cmd_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*); + rvdffs #(1) sb_abmem_data_doneff (.din(sb_abmem_data_done_in), .dout(sb_abmem_data_done), .en(sb_abmem_data_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*); + + // FSM to control the debug mode entry, command send/recieve, and Resume flow. + always_comb begin + dbg_nxtstate = IDLE; + dbg_state_en = 1'b0; + abstractcs_busy_wren = 1'b0; + abstractcs_busy_din = 1'b0; + dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31]; // single pulse output to the core. Need to drive every time this register is written since core might be halted due to MPC + dbg_resume_req = 1'b0; // single pulse output to the core + dbg_sb_bus_error = 1'b0; + data0_reg_wren2 = 1'b0; + sb_abmem_cmd_done_in = 1'b0; + sb_abmem_data_done_in = 1'b0; + sb_abmem_cmd_done_en = 1'b0; + sb_abmem_data_done_en = 1'b0; + + case (dbg_state) + IDLE: begin + dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING; // initiate the halt command to the core + dbg_state_en = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only; // when the jtag writes the halt bit in the DM register, OR when the status indicates H + dbg_halt_req = dmcontrol_reg[31]; // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes + end + HALTING : begin + dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK + dbg_state_en = dmstatus_reg[9] | dec_tlu_mpc_halted_only; // core indicates halted + end + HALTED: begin + // wait for halted to go away before send to resume. Else start of new command + dbg_nxtstate = dmstatus_reg[9] ? (resumereq ? RESUMING : (((command_reg[31:24] == 8'h2) & abmem_addr_external) ? SB_CMD_START : CORE_CMD_START)) : + (dmcontrol_reg[31] ? HALTING : IDLE); // This is MPC halted case + dbg_state_en = (dmstatus_reg[9] & resumereq) | execute_command | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only); + abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == CORE_CMD_START) | (dbg_nxtstate == SB_CMD_START)); // write busy when a new command was written by jtag + abstractcs_busy_din = 1'b1; + dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming + end + CORE_CMD_START: begin + // Don't execute the command if cmderror or transfer=0 for abstract register access + dbg_nxtstate = ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CORE_CMD_WAIT; // new command sent to the core + dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]); + end + CORE_CMD_WAIT: begin + dbg_nxtstate = CMD_DONE; + dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command + end + SB_CMD_START: begin + dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : SB_CMD_SEND; + dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | (|abstractcs_reg[10:8]); + end + SB_CMD_SEND: begin + sb_abmem_cmd_done_in = 1'b1; + sb_abmem_data_done_in= 1'b1; + sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en; + sb_abmem_data_done_en= (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en; + dbg_nxtstate = SB_CMD_RESP; + dbg_state_en = (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & dbg_bus_clk_en; + end + SB_CMD_RESP: begin + dbg_nxtstate = CMD_DONE; + dbg_state_en = (sb_bus_rsp_read | sb_bus_rsp_write) & dbg_bus_clk_en; + dbg_sb_bus_error = (sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error & dbg_bus_clk_en; + data0_reg_wren2 = dbg_state_en & ~sb_abmem_cmd_write & ~dbg_sb_bus_error; + end + CMD_DONE: begin + dbg_nxtstate = HALTED; + dbg_state_en = 1'b1; + abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 ) + abstractcs_busy_din = 1'b0; + sb_abmem_cmd_done_in = 1'b0; + sb_abmem_data_done_in= 1'b0; + sb_abmem_cmd_done_en = 1'b1; + sb_abmem_data_done_en= 1'b1; + end + RESUMING : begin + dbg_nxtstate = IDLE; + dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register + end + default : begin + dbg_nxtstate = IDLE; + dbg_state_en = 1'b0; + abstractcs_busy_wren = 1'b0; + abstractcs_busy_din = 1'b0; + dbg_halt_req = 1'b0; // single pulse output to the core + dbg_resume_req = 1'b0; // single pulse output to the core + dbg_sb_bus_error = 1'b0; + data0_reg_wren2 = 1'b0; + sb_abmem_cmd_done_in = 1'b0; + sb_abmem_data_done_in = 1'b0; + sb_abmem_cmd_done_en = 1'b0; + sb_abmem_data_done_en = 1'b0; + end + endcase + end // always_comb begin + + assign dmi_reg_rdata_din[31:0] = ({32{dmi_reg_addr == 7'h4}} & data0_reg[31:0]) | + ({32{dmi_reg_addr == 7'h5}} & data1_reg[31:0]) | + ({32{dmi_reg_addr == 7'h10}} & {2'b0,dmcontrol_reg[29],1'b0,dmcontrol_reg[27:0]}) | // Read0 to Write only bits + ({32{dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0]) | + ({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) | + ({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) | + ({32{dmi_reg_addr == 7'h18}} & {30'h0,abstractauto_reg[1:0]}) | + ({32{dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0]) | + ({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) | + ({32{dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0]) | + ({32{dmi_reg_addr == 7'h3c}} & sbdata0_reg[31:0]) | + ({32{dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]); + + + rvdffs #($bits(state_t)) dbg_state_reg (.din(dbg_nxtstate), .dout({dbg_state}), .en(dbg_state_en), .rst_l(dbg_dm_rst_l & rst_l), .clk(dbg_free_clk)); + rvdffe #(32) dmi_rddata_reg (.din(dmi_reg_rdata_din[31:0]), .dout(dmi_reg_rdata[31:0]), .en(dmi_reg_en), .rst_l(dbg_dm_rst_l), .clk(clk), .*); + + assign abmem_addr[31:0] = data1_reg[31:0]; + assign abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region | abmem_addr_in_pic_region); + assign abmem_addr_external = ~abmem_addr_core_local; + + assign abmem_addr_in_dccm_region = (abmem_addr[31:28] == pt.DCCM_REGION) & pt.DCCM_ENABLE; + assign abmem_addr_in_iccm_region = (abmem_addr[31:28] == pt.ICCM_REGION) & pt.ICCM_ENABLE; + assign abmem_addr_in_pic_region = (abmem_addr[31:28] == pt.PIC_REGION); + + // interface for the core + assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {20'b0, command_reg[11:0]}; + assign dbg_cmd_wrdata[31:0] = data0_reg[31:0]; + assign dbg_cmd_valid = (dbg_state == CORE_CMD_START) & ~((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]) | ((command_reg[31:24] == 8'h2) & abmem_addr_external)) & dma_dbg_ready; + assign dbg_cmd_write = command_reg[16]; + assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h2) ? 2'b10 : {1'b0, (command_reg[15:12] == 4'b0)}; + assign dbg_cmd_size[1:0] = command_reg[21:20]; + + assign dbg_cmd_addr_incr[3:0] = (command_reg[31:24] == 8'h2) ? (4'h1 << sb_abmem_cmd_size[1:0]) : 4'h1; + assign dbg_cmd_curr_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {16'b0, command_reg[15:0]}; + assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0,dbg_cmd_addr_incr[3:0]}; + + // Ask DMA to stop taking bus trxns since debug request is done + assign dbg_dma_bubble = ((dbg_state == CORE_CMD_START) & ~(|abstractcs_reg[10:8])) | (dbg_state == CORE_CMD_WAIT); + + assign sb_cmd_pending = (sb_state == CMD_RD) | (sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR) | (sb_state == CMD_WR_DATA) | (sb_state == RSP_RD) | (sb_state == RSP_WR); + assign sb_abmem_cmd_pending = (dbg_state == SB_CMD_START) | (dbg_state == SB_CMD_SEND) | (dbg_state== SB_CMD_RESP); + + + // system bus FSM + always_comb begin + sb_nxtstate = SBIDLE; + sb_state_en = 1'b0; + sbcs_sbbusy_wren = 1'b0; + sbcs_sbbusy_din = 1'b0; + sbcs_sberror_wren = 1'b0; + sbcs_sberror_din[2:0] = 3'b0; + sbaddress0_reg_wren1 = 1'b0; + case (sb_state) + SBIDLE: begin + sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD; + sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22]; + sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command + sbcs_sbbusy_din = 1'b1; + sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits + sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12]; + end + WAIT_RD: begin + sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD; + sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size; + sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; + sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; + end + WAIT_WR: begin + sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR; + sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size; + sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size; + sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100; + end + CMD_RD : begin + sb_nxtstate = RSP_RD; + sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en; + end + CMD_WR : begin + sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data) ? RSP_WR : (sb_bus_cmd_write_data ? CMD_WR_ADDR : CMD_WR_DATA); + sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en; + end + CMD_WR_ADDR : begin + sb_nxtstate = RSP_WR; + sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en; + end + CMD_WR_DATA : begin + sb_nxtstate = RSP_WR; + sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en; + end + RSP_RD: begin + sb_nxtstate = DONE; + sb_state_en = sb_bus_rsp_read & dbg_bus_clk_en; + sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error; + sbcs_sberror_din[2:0] = 3'b010; + end + RSP_WR: begin + sb_nxtstate = DONE; + sb_state_en = sb_bus_rsp_write & dbg_bus_clk_en; + sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error; + sbcs_sberror_din[2:0] = 3'b010; + end + DONE: begin + sb_nxtstate = SBIDLE; + sb_state_en = 1'b1; + sbcs_sbbusy_wren = 1'b1; // reset the single read + sbcs_sbbusy_din = 1'b0; + sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b0); // auto increment was set and no error. Update to new address after completing the current command + end + default : begin + sb_nxtstate = SBIDLE; + sb_state_en = 1'b0; + sbcs_sbbusy_wren = 1'b0; + sbcs_sbbusy_din = 1'b0; + sbcs_sberror_wren = 1'b0; + sbcs_sberror_din[2:0] = 3'b0; + sbaddress0_reg_wren1 = 1'b0; + end + endcase + end // always_comb begin + + rvdffs #($bits(sb_state_t)) sb_state_reg (.din(sb_nxtstate), .dout({sb_state}), .en(sb_state_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk)); + + assign sb_abmem_cmd_write = command_reg[16]; + assign sb_abmem_cmd_size[2:0] = {1'b0, command_reg[21:20]}; + assign sb_abmem_cmd_addr[31:0] = abmem_addr[31:0]; + assign sb_abmem_cmd_wdata[31:0] = data0_reg[31:0]; + + assign sb_cmd_size[2:0] = sbcs_reg[19:17]; + assign sb_cmd_wdata[63:0] = {sbdata1_reg[31:0], sbdata0_reg[31:0]}; + assign sb_cmd_addr[31:0] = sbaddress0_reg[31:0]; + + assign sb_abmem_cmd_awvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_cmd_done; + assign sb_abmem_cmd_wvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_data_done; + assign sb_abmem_cmd_arvalid = (dbg_state == SB_CMD_SEND) & ~sb_abmem_cmd_write & ~sb_abmem_cmd_done & ~sb_abmem_data_done; + assign sb_abmem_read_pend = (dbg_state == SB_CMD_RESP) & ~sb_abmem_cmd_write; + + assign sb_cmd_awvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR)); + assign sb_cmd_wvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_DATA)); + assign sb_cmd_arvalid = (sb_state == CMD_RD); + assign sb_read_pend = (sb_state == RSP_RD); + + assign sb_axi_size[2:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_size[2:0] : sb_cmd_size[2:0]; + assign sb_axi_addr[31:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_addr[31:0] : sb_cmd_addr[31:0]; + assign sb_axi_wrdata[63:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) ? {2{sb_abmem_cmd_wdata[31:0]}} : sb_cmd_wdata[63:0]; + + // Generic bus response signals + assign sb_bus_cmd_read = sb_axi_arvalid & sb_axi_arready; + assign sb_bus_cmd_write_addr = sb_axi_awvalid & sb_axi_awready; + assign sb_bus_cmd_write_data = sb_axi_wvalid & sb_axi_wready; + + assign sb_bus_rsp_read = sb_axi_rvalid & sb_axi_rready; + assign sb_bus_rsp_write = sb_axi_bvalid & sb_axi_bready; + assign sb_bus_rsp_error = (sb_bus_rsp_read & (|(sb_axi_rresp[1:0]))) | (sb_bus_rsp_write & (|(sb_axi_bresp[1:0]))); + + // AXI Request signals + assign sb_axi_awvalid = sb_abmem_cmd_awvalid | sb_cmd_awvalid; + assign sb_axi_awaddr[31:0] = sb_axi_addr[31:0]; + assign sb_axi_awid[pt.SB_BUS_TAG-1:0] = '0; + assign sb_axi_awsize[2:0] = sb_axi_size[2:0]; + assign sb_axi_awprot[2:0] = 3'b001; + assign sb_axi_awcache[3:0] = 4'b1111; + assign sb_axi_awregion[3:0] = sb_axi_addr[31:28]; + assign sb_axi_awlen[7:0] = '0; + assign sb_axi_awburst[1:0] = 2'b01; + assign sb_axi_awqos[3:0] = '0; + assign sb_axi_awlock = '0; + + assign sb_axi_wvalid = sb_abmem_cmd_wvalid | sb_cmd_wvalid; + assign sb_axi_wdata[63:0] = ({64{(sb_axi_size[2:0] == 3'h0)}} & {8{sb_axi_wrdata[7:0]}}) | + ({64{(sb_axi_size[2:0] == 3'h1)}} & {4{sb_axi_wrdata[15:0]}}) | + ({64{(sb_axi_size[2:0] == 3'h2)}} & {2{sb_axi_wrdata[31:0]}}) | + ({64{(sb_axi_size[2:0] == 3'h3)}} & {sb_axi_wrdata[63:0]}); + assign sb_axi_wstrb[7:0] = ({8{(sb_axi_size[2:0] == 3'h0)}} & (8'h1 << sb_axi_addr[2:0])) | + ({8{(sb_axi_size[2:0] == 3'h1)}} & (8'h3 << {sb_axi_addr[2:1],1'b0})) | + ({8{(sb_axi_size[2:0] == 3'h2)}} & (8'hf << {sb_axi_addr[2],2'b0})) | + ({8{(sb_axi_size[2:0] == 3'h3)}} & 8'hff); + assign sb_axi_wlast = '1; + + assign sb_axi_arvalid = sb_abmem_cmd_arvalid | sb_cmd_arvalid; + assign sb_axi_araddr[31:0] = sb_axi_addr[31:0]; + assign sb_axi_arid[pt.SB_BUS_TAG-1:0] = '0; + assign sb_axi_arsize[2:0] = sb_axi_size[2:0]; + assign sb_axi_arprot[2:0] = 3'b001; + assign sb_axi_arcache[3:0] = 4'b0; + assign sb_axi_arregion[3:0] = sb_axi_addr[31:28]; + assign sb_axi_arlen[7:0] = '0; + assign sb_axi_arburst[1:0] = 2'b01; + assign sb_axi_arqos[3:0] = '0; + assign sb_axi_arlock = '0; + + // AXI Response signals + assign sb_axi_bready = 1'b1; + + assign sb_axi_rready = 1'b1; + assign sb_bus_rdata[63:0] = ({64{sb_axi_size == 3'h0}} & ((sb_axi_rdata[63:0] >> 8*sb_axi_addr[2:0]) & 64'hff)) | + ({64{sb_axi_size == 3'h1}} & ((sb_axi_rdata[63:0] >> 16*sb_axi_addr[2:1]) & 64'hffff)) | + ({64{sb_axi_size == 3'h2}} & ((sb_axi_rdata[63:0] >> 32*sb_axi_addr[2]) & 64'hffff_ffff)) | + ({64{sb_axi_size == 3'h3}} & sb_axi_rdata[63:0]); + +`ifdef RV_ASSERT_ON +// assertion. +// when the resume_ack is asserted then the dec_tlu_dbg_halted should be 0 + dm_check_resume_and_halted: assert property (@(posedge clk) disable iff(~rst_l) (~dec_tlu_resume_ack | ~dec_tlu_dbg_halted)); + + assert_b2b_haltreq: assert property (@(posedge clk) disable iff (~(rst_l)) (##1 dbg_halt_req |=> ~dbg_halt_req)); // One cycle delay to fix weird issue around reset + assert_halt_resume_onehot: assert #0 ($onehot0({dbg_halt_req, dbg_resume_req})); +`endif +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv new file mode 100644 index 0000000000000000000000000000000000000000..d22997a0e07ba9aabdb748a40706e9e1047877fc --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec.sv @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// dec: decode unit - decode, bypassing, ARF, interrupts +// +//******************************************************************************** +// $Id$ +// +// +// Function: Decode +// Comments: Decode, dependency scoreboard, ARF +// +// +// A -> D -> EX1 ... WB +// +//******************************************************************************** + +module el2_dec +import el2_pkg::*; +#( +`include "el2_param.vh" + ) + ( + input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. + input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. + input logic free_clk, // Clock always. Through two clock headers. For flops without second clock header built in. + input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. + + input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle + + output logic dec_extint_stall, // Stall on external interrupt + + output logic dec_i0_decode_d, // Valid instruction at D-stage and not blocked + output logic dec_pause_state_cg, // to top for active state clock gating + + output logic dec_tlu_core_empty, + + input logic rst_l, // reset, active low + input logic [31:1] rst_vec, // reset vector, from core pins + + input logic nmi_int, // NMI pin + input logic [31:1] nmi_vec, // NMI vector, from pins + + input logic i_cpu_halt_req, // Asynchronous Halt request to CPU + input logic i_cpu_run_req, // Asynchronous Restart request to CPU + + output logic o_cpu_halt_status, // Halt status of core (pmu/fw) + output logic o_cpu_halt_ack, // Halt request ack + output logic o_cpu_run_ack, // Run request ack + output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + + input logic [31:4] core_id, // CORE ID + + // external MPC halt/run interface + input logic mpc_debug_halt_req, // Async halt request + input logic mpc_debug_run_req, // Async run request + input logic mpc_reset_run_req, // Run/halt after reset + output logic mpc_debug_halt_ack, // Halt ack + output logic mpc_debug_run_ack, // Run ack + output logic debug_brkpt_status, // debug breakpoint + + input logic exu_pmu_i0_br_misp, // slot 0 branch misp + input logic exu_pmu_i0_br_ataken, // slot 0 branch actual taken + input logic exu_pmu_i0_pc4, // slot 0 4 byte branch + + + input logic lsu_nonblock_load_valid_m, // valid nonblock load at m + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag + input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag + input logic lsu_nonblock_load_data_valid, // valid nonblock load data back + input logic lsu_nonblock_load_data_error, // nonblock load bus error + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag + input logic [31:0] lsu_nonblock_load_data, // nonblock load data + + input logic lsu_pmu_bus_trxn, // D side bus transaction + input logic lsu_pmu_bus_misaligned, // D side bus misaligned + input logic lsu_pmu_bus_error, // D side bus error + input logic lsu_pmu_bus_busy, // D side bus busy + input logic lsu_pmu_misaligned_m, // D side load or store misaligned + input logic lsu_pmu_load_external_m, // D side bus load + input logic lsu_pmu_store_external_m, // D side bus store + input logic dma_pmu_dccm_read, // DMA DCCM read + input logic dma_pmu_dccm_write, // DMA DCCM write + input logic dma_pmu_any_read, // DMA read + input logic dma_pmu_any_write, // DMA write + + input logic [31:1] lsu_fir_addr, // Fast int address + input logic [1:0] lsu_fir_error, // Fast int lookup error + + input logic ifu_pmu_instr_aligned, // aligned instructions + input logic ifu_pmu_fetch_stall, // fetch unit stalled + input logic ifu_pmu_ic_miss, // icache miss + input logic ifu_pmu_ic_hit, // icache hit + input logic ifu_pmu_bus_error, // Instruction side bus error + input logic ifu_pmu_bus_busy, // Instruction side bus busy + input logic ifu_pmu_bus_trxn, // Instruction side bus transaction + + input logic ifu_ic_error_start, // IC single bit error + input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error + + input logic [3:0] lsu_trigger_match_m, + input logic dbg_cmd_valid, // debugger abstract command valid + input logic dbg_cmd_write, // command is a write + input logic [1:0] dbg_cmd_type, // command type + input logic [31:0] dbg_cmd_addr, // command address + input logic [1:0] dbg_cmd_wrdata, // command write data, for fence/fence_i + + + input logic ifu_i0_icaf, // icache access fault + input logic [1:0] ifu_i0_icaf_type, // icache access fault type + + input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst + input logic ifu_i0_dbecc, // icache/iccm double-bit error + + input logic lsu_idle_any, // lsu idle for halting + + input el2_br_pkt_t i0_brp, // branch packet + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index + input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR + input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag + input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index + + input el2_lsu_error_pkt_t lsu_error_pkt_r, // LSU exception/error packet + input logic lsu_single_ecc_error_incr, // LSU inc SB error counter + + input logic lsu_imprecise_error_load_any, // LSU imprecise load bus error + input logic lsu_imprecise_error_store_any, // LSU imprecise store bus error + input logic [31:0] lsu_imprecise_error_addr_any, // LSU imprecise bus error address + + input logic [31:0] exu_div_result, // final div result + input logic exu_div_wren, // Divide write enable to GPR + + input logic [31:0] exu_csr_rs1_x, // rs1 for csr instruction + + input logic [31:0] lsu_result_m, // load result + input logic [31:0] lsu_result_corr_r, // load result - corrected load data + + input logic lsu_load_stall_any, // This is for blocking loads + input logic lsu_store_stall_any, // This is for blocking stores + input logic dma_dccm_stall_any, // stall any load/store at decode, pmu event + input logic dma_iccm_stall_any, // iccm stalled, pmu event + + input logic iccm_dma_sb_error, // ICCM DMA single bit error + + input logic exu_flush_final, // slot0 flush + + input logic [31:1] exu_npc_r, // next PC + + input logic [31:0] exu_i0_result_x, // alu result x + + + input logic ifu_i0_valid, // fetch valids to instruction buffer + input logic [31:0] ifu_i0_instr, // fetch inst's to instruction buffer + input logic [31:1] ifu_i0_pc, // pc's for instruction buffer + input logic ifu_i0_pc4, // indication of 4B or 2B for corresponding inst + input logic [31:1] exu_i0_pc_x, // pc's for e1 from the alu's + + input logic mexintpend, // External interrupt pending + input logic timer_int, // Timer interrupt pending (from pin) + input logic soft_int, // Software interrupt pending (from pin) + + input logic [7:0] pic_claimid, // PIC claimid + input logic [3:0] pic_pl, // PIC priv level + input logic mhwakeup, // High priority wakeup + + output logic [3:0] dec_tlu_meicurpl, // to PIC, Current priv level + output logic [3:0] dec_tlu_meipt, // to PIC + + input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data + input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid + output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics + + +// Debug start + input logic dbg_halt_req, // DM requests a halt + input logic dbg_resume_req, // DM requests a resume + input logic ifu_miss_state_idle, // I-side miss buffer empty + + output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command + output logic dec_tlu_debug_mode, // Core is in debug mode + output logic dec_tlu_resume_ack, // Resume acknowledge + output logic dec_tlu_flush_noredir_r, // Tell fetch to idle on this flush + output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC + output logic dec_tlu_flush_leak_one_r, // single step + output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc + output logic [31:2] dec_tlu_meihap, // Fast ext int base + + output logic dec_debug_wdata_rs1_d, // insert debug write data into rs1 at decode + + output logic [31:0] dec_dbg_rddata, // debug command read data + + output logic dec_dbg_cmd_done, // abstract command is done + output logic dec_dbg_cmd_fail, // abstract command failed (illegal reg address) + + output el2_trigger_pkt_t [3:0] trigger_pkt_any, // info needed by debug trigger blocks + + output logic dec_tlu_force_halt, // halt has been forced +// Debug end + // branch info from pipe0 for errors or counter updates + input logic [1:0] exu_i0_br_hist_r, // history + input logic exu_i0_br_error_r, // error + input logic exu_i0_br_start_error_r, // start error + input logic exu_i0_br_valid_r, // valid + input logic exu_i0_br_mp_r, // mispredict + input logic exu_i0_br_middle_r, // middle of bank + + // branch info from pipe1 for errors or counter updates + + input logic exu_i0_br_way_r, // way hit or repl + + output logic dec_i0_rs1_en_d, // Qualify GPR RS1 data + output logic dec_i0_rs2_en_d, // Qualify GPR RS2 data + output logic [31:0] gpr_i0_rs1_d, // gpr rs1 data + output logic [31:0] gpr_i0_rs2_d, // gpr rs2 data + + output logic [31:0] dec_i0_immed_d, // immediate data + output logic [12:1] dec_i0_br_immed_d, // br immediate data + + output el2_alu_pkt_t i0_ap, // alu packet + + output logic dec_i0_alu_decode_d, // schedule on D-stage alu + output logic dec_i0_branch_d, // Branch in D-stage + + output logic dec_i0_select_pc_d, // select pc onto rs1 for jal's + + output logic [31:1] dec_i0_pc_d, // pc's at decode + output logic [3:0] dec_i0_rs1_bypass_en_d, // rs1 bypass enable + output logic [3:0] dec_i0_rs2_bypass_en_d, // rs2 bypass enable + + output logic [31:0] dec_i0_result_r, // Result R-stage + + output el2_lsu_pkt_t lsu_p, // lsu packet + output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands + output el2_mul_pkt_t mul_p, // mul packet + output el2_div_pkt_t div_p, // div packet + output logic dec_div_cancel, // cancel divide operation + + output logic [11:0] dec_lsu_offset_d, // 12b offset for load/store addresses + + output logic dec_csr_ren_d, // CSR read enable + output logic [31:0] dec_csr_rddata_d, // CSR read data + + output logic dec_tlu_flush_lower_r, // tlu flush due to late mp, exception, rfpc, or int + output logic dec_tlu_flush_lower_wb, + output logic [31:1] dec_tlu_flush_path_r, // tlu flush target + output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state + output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache + + output logic [31:1] pred_correct_npc_x, // npc if prediction is correct at e2 stage + + output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot 0 branch predictor update packet + + output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc + output logic dec_tlu_perfcnt1, // toggles when slot0 perf counter 1 has an event inc + output logic dec_tlu_perfcnt2, // toggles when slot0 perf counter 2 has an event inc + output logic dec_tlu_perfcnt3, // toggles when slot0 perf counter 3 has an event inc + + output el2_predict_pkt_t dec_i0_predict_p_d, // prediction packet to alus + output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index + output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag + + output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index + + output logic dec_lsu_valid_raw_d, + + output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control + + output logic [1:0] dec_data_en, // clock-gate control logic + output logic [1:0] dec_ctl_en, + + input logic [15:0] ifu_i0_cinst, // 16b compressed instruction + + output el2_trace_pkt_t trace_rv_trace_pkt, // trace packet + + // feature disable from mfdc + output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding + output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address + output logic dec_tlu_core_ecc_disable, // disable core ECC + output logic dec_tlu_bpred_disable, // disable branch prediction + output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing + output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16] + + // clock gating overrides from mcgc + output logic dec_tlu_misc_clk_override, // override misc clock domain gating + output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating + output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating + output logic dec_tlu_bus_clk_override, // override bus clock domain gating + output logic dec_tlu_pic_clk_override, // override PIC clock domain gating + output logic dec_tlu_picio_clk_override, // override PICIO clock domain gating + output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating + output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating + + output logic dec_tlu_i0_commit_cmt, // committed i0 instruction + input logic scan_mode // Flop scan mode control + + ); + + + logic dec_tlu_dec_clk_override; // to and from dec blocks + logic clk_override; + + logic dec_ib0_valid_d; + + logic dec_pmu_instr_decoded; + logic dec_pmu_decode_stall; + logic dec_pmu_presync_stall; + logic dec_pmu_postsync_stall; + + logic dec_tlu_wr_pause_r; // CSR write to pause reg is at R. + + logic [4:0] dec_i0_rs1_d; + logic [4:0] dec_i0_rs2_d; + + logic [31:0] dec_i0_instr_d; + + logic dec_tlu_trace_disable; + logic dec_tlu_pipelining_disable; + + + logic [4:0] dec_i0_waddr_r; + logic dec_i0_wen_r; + logic [31:0] dec_i0_wdata_r; + logic dec_csr_wen_r; // csr write enable at wb + logic [11:0] dec_csr_wraddr_r; // write address for csryes + logic [31:0] dec_csr_wrdata_r; // csr write data at wb + + logic [11:0] dec_csr_rdaddr_d; // read address for csr + logic dec_csr_legal_d; // csr indicates legal operation + + logic dec_csr_wen_unq_d; // valid csr with write - for csr legal + logic dec_csr_any_unq_d; // valid csr - for csr legal + logic dec_csr_stall_int_ff; // csr is mie/mstatus + + el2_trap_pkt_t dec_tlu_packet_r; + + logic dec_i0_pc4_d; + logic dec_tlu_presync_d; + logic dec_tlu_postsync_d; + logic dec_tlu_debug_stall; + + logic [31:0] dec_illegal_inst; + + logic dec_i0_icaf_d; + + logic dec_i0_dbecc_d; + logic dec_i0_icaf_second_d; + logic [3:0] dec_i0_trigger_match_d; + logic dec_debug_fence_d; + logic dec_nonblock_load_wen; + logic [4:0] dec_nonblock_load_waddr; + logic dec_tlu_flush_pause_r; + el2_br_pkt_t dec_i0_brp; + logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index; + logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr; + logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag; + logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index; // Fully associt btb index + + logic [31:1] dec_tlu_i0_pc_r; + logic dec_tlu_i0_kill_writeb_wb; + logic dec_tlu_i0_valid_r; + + logic dec_pause_state; + + logic [1:0] dec_i0_icaf_type_d; // i0 instruction access fault type + + logic dec_tlu_flush_extint; // Fast ext int started + + logic [31:0] dec_i0_inst_wb; + logic [31:1] dec_i0_pc_wb; + logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1; + logic [4:0] dec_tlu_exc_cause_wb1; + logic [31:0] dec_tlu_mtval_wb1; + logic dec_tlu_i0_exc_valid_wb1; + + logic [4:0] div_waddr_wb; + logic dec_div_active; + + logic dec_debug_valid_d; + + assign clk_override = dec_tlu_dec_clk_override; + + + assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0]; + + + el2_dec_ib_ctl #(.pt(pt)) instbuff (.*); + + + el2_dec_decode_ctl #(.pt(pt)) decode (.*); + + + el2_dec_tlu_ctl #(.pt(pt)) tlu (.*); + + + el2_dec_gpr_ctl #(.pt(pt)) arf (.*, + // inputs + .raddr0(dec_i0_rs1_d[4:0]), + .raddr1(dec_i0_rs2_d[4:0]), + + .wen0(dec_i0_wen_r), .waddr0(dec_i0_waddr_r[4:0]), .wd0(dec_i0_wdata_r[31:0]), + .wen1(dec_nonblock_load_wen), .waddr1(dec_nonblock_load_waddr[4:0]), .wd1(lsu_nonblock_load_data[31:0]), + .wen2(exu_div_wren), .waddr2(div_waddr_wb), .wd2(exu_div_result[31:0]), + + // outputs + .rd0(gpr_i0_rs1_d[31:0]), .rd1(gpr_i0_rs2_d[31:0]) + ); + + +// Trigger + + el2_dec_trigger #(.pt(pt)) dec_trigger (.*); + + + + +// trace + assign trace_rv_trace_pkt.trace_rv_i_insn_ip = dec_i0_inst_wb[31:0]; + assign trace_rv_trace_pkt.trace_rv_i_address_ip = { dec_i0_pc_wb[31:1], 1'b0}; + + assign trace_rv_trace_pkt.trace_rv_i_valid_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1; + assign trace_rv_trace_pkt.trace_rv_i_exception_ip = dec_tlu_int_valid_wb1 | dec_tlu_i0_exc_valid_wb1; + assign trace_rv_trace_pkt.trace_rv_i_ecause_ip = dec_tlu_exc_cause_wb1[4:0]; // replicate across ports + assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = dec_tlu_int_valid_wb1; + assign trace_rv_trace_pkt.trace_rv_i_tval_ip = dec_tlu_mtval_wb1[31:0]; // replicate across ports + + + +// end trace + + +endmodule // el2_dec + diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv new file mode 100644 index 0000000000000000000000000000000000000000..255e320b0aa9e65c1a840d735e66be6c00bd2309 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_decode_ctl.sv @@ -0,0 +1,1835 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +module el2_dec_decode_ctl +import el2_pkg::*; +#( +`include "el2_param.vh" + ) + ( + input logic dec_tlu_trace_disable, + input logic dec_debug_valid_d, + + input logic dec_tlu_flush_extint, // Flush external interrupt + + input logic dec_tlu_force_halt, // invalidate nonblock load cam on a force halt event + + output logic dec_extint_stall, // Stall from external interrupt + + input logic [15:0] ifu_i0_cinst, // 16b compressed instruction + output logic [31:0] dec_i0_inst_wb, // 32b instruction at wb+1 for trace encoder + output logic [31:1] dec_i0_pc_wb, // 31b pc at wb+1 for trace encoder + + + input logic lsu_nonblock_load_valid_m, // valid nonblock load at m + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag + input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag + input logic lsu_nonblock_load_data_valid, // valid nonblock load data back + input logic lsu_nonblock_load_data_error, // nonblock load bus error + input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag + + + input logic [3:0] dec_i0_trigger_match_d, // i0 decode trigger matches + + input logic dec_tlu_wr_pause_r, // pause instruction at r + input logic dec_tlu_pipelining_disable, // pipeline disable - presync, i0 decode only + + input logic [3:0] lsu_trigger_match_m, // lsu trigger matches + + input logic lsu_pmu_misaligned_m, // perf mon: load/store misalign + input logic dec_tlu_debug_stall, // debug stall decode + input logic dec_tlu_flush_leak_one_r, // leak1 instruction + + input logic dec_debug_fence_d, // debug fence instruction + + input logic [1:0] dbg_cmd_wrdata, // disambiguate fence, fence_i + + input logic dec_i0_icaf_d, // icache access fault + input logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst + input logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type + + input logic dec_i0_dbecc_d, // icache/iccm double-bit error + + input el2_br_pkt_t dec_i0_brp, // branch packet + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index + input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR + input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag + input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index + + input logic lsu_idle_any, // lsu idle: if fence instr & ~lsu_idle then stall decode + + input logic lsu_load_stall_any, // stall any load at decode + input logic lsu_store_stall_any, // stall any store at decode + input logic dma_dccm_stall_any, // stall any load/store at decode + + input logic exu_div_wren, // nonblocking divide write enable to GPR. + + input logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state + input logic dec_tlu_flush_lower_wb, // trap lower flush + input logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state + input logic dec_tlu_flush_lower_r, // trap lower flush + input logic dec_tlu_flush_pause_r, // don't clear pause state on initial lower flush + input logic dec_tlu_presync_d, // CSR read needs to be presync'd + input logic dec_tlu_postsync_d, // CSR ops that need to be postsync'd + + input logic dec_i0_pc4_d, // inst is 4B inst else 2B + + input logic [31:0] dec_csr_rddata_d, // csr read data at wb + input logic dec_csr_legal_d, // csr indicates legal operation + + input logic [31:0] exu_csr_rs1_x, // rs1 for csr instr + + input logic [31:0] lsu_result_m, // load result + input logic [31:0] lsu_result_corr_r, // load result - corrected data for writing gpr's, not for bypassing + + input logic exu_flush_final, // lower flush or i0 flush at X or D + + input logic [31:1] exu_i0_pc_x, // pcs at e1 + + input logic [31:0] dec_i0_instr_d, // inst at decode + + input logic dec_ib0_valid_d, // inst valid at decode + + input logic [31:0] exu_i0_result_x, // from primary alu's + + input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. + input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. + input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in. + + input logic clk_override, // Override non-functional clock gating + input logic rst_l, // Flop reset + + + + output logic dec_i0_rs1_en_d, // rs1 enable at decode + output logic dec_i0_rs2_en_d, // rs2 enable at decode + + output logic [4:0] dec_i0_rs1_d, // rs1 logical source + output logic [4:0] dec_i0_rs2_d, // rs2 logical source + + output logic [31:0] dec_i0_immed_d, // 32b immediate data decode + + + output logic [12:1] dec_i0_br_immed_d, // 12b branch immediate + + output el2_alu_pkt_t i0_ap, // alu packets + + output logic dec_i0_decode_d, // i0 decode + + output logic dec_i0_alu_decode_d, // decode to D-stage alu + output logic dec_i0_branch_d, // Branch in D-stage + + output logic [4:0] dec_i0_waddr_r, // i0 logical source to write to gpr's + output logic dec_i0_wen_r, // i0 write enable + output logic [31:0] dec_i0_wdata_r, // i0 write data + + output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches + + output logic [3:0] dec_i0_rs1_bypass_en_d, // i0 rs1 bypass enable + output logic [3:0] dec_i0_rs2_bypass_en_d, // i0 rs2 bypass enable + output logic [31:0] dec_i0_result_r, // Result R-stage + + output el2_lsu_pkt_t lsu_p, // load/store packet + output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands + + output el2_mul_pkt_t mul_p, // multiply packet + + output el2_div_pkt_t div_p, // divide packet + output logic [4:0] div_waddr_wb, // DIV write address to GPR + output logic dec_div_cancel, // cancel the divide operation + + output logic dec_lsu_valid_raw_d, + output logic [11:0] dec_lsu_offset_d, + + output logic dec_csr_ren_d, // valid csr decode + output logic dec_csr_wen_unq_d, // valid csr with write - for csr legal + output logic dec_csr_any_unq_d, // valid csr - for csr legal + output logic [11:0] dec_csr_rdaddr_d, // read address for csr + output logic dec_csr_wen_r, // csr write enable at r + output logic [11:0] dec_csr_wraddr_r, // write address for csr + output logic [31:0] dec_csr_wrdata_r, // csr write data at r + output logic dec_csr_stall_int_ff, // csr is mie/mstatus + + output dec_tlu_i0_valid_r, // i0 valid inst at c + + output el2_trap_pkt_t dec_tlu_packet_r, // trap packet + + output logic [31:1] dec_tlu_i0_pc_r, // i0 trap pc + + output logic [31:0] dec_illegal_inst, // illegal inst + output logic [31:1] pred_correct_npc_x, // npc e2 if the prediction is correct + + output el2_predict_pkt_t dec_i0_predict_p_d, // i0 predict packet decode + output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index + output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag + + output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index + + output logic [1:0] dec_data_en, // clock-gating logic + output logic [1:0] dec_ctl_en, + + output logic dec_pmu_instr_decoded, // number of instructions decode this cycle encoded + output logic dec_pmu_decode_stall, // decode is stalled + output logic dec_pmu_presync_stall, // decode has presync stall + output logic dec_pmu_postsync_stall, // decode has postsync stall + + output logic dec_nonblock_load_wen, // write enable for nonblock load + output logic [4:0] dec_nonblock_load_waddr, // logical write addr for nonblock load + output logic dec_pause_state, // core in pause state + output logic dec_pause_state_cg, // pause state for clock-gating + + output logic dec_div_active, // non-block divide is active + + input logic scan_mode + ); + + + + + el2_dec_pkt_t i0_dp_raw, i0_dp; + + logic [31:0] i0; + logic i0_valid_d; + + logic [31:0] i0_result_r; + + logic [2:0] i0_rs1bypass, i0_rs2bypass; + + logic i0_jalimm20; + logic i0_uiimm20; + + logic lsu_decode_d; + logic [31:0] i0_immed_d; + logic i0_presync; + logic i0_postsync; + + logic postsync_stall; + logic ps_stall; + + logic prior_inflight, prior_inflight_wb; + + logic csr_clr_d, csr_set_d, csr_write_d; + + logic csr_clr_x,csr_set_x,csr_write_x,csr_imm_x; + logic [31:0] csr_mask_x; + logic [31:0] write_csr_data_x; + logic [31:0] write_csr_data_in; + logic [31:0] write_csr_data; + logic csr_data_wen; + + logic [4:0] csrimm_x; + + logic [31:0] csr_rddata_x; + + logic mul_decode_d; + logic div_decode_d; + logic div_e1_to_r; + logic div_flush; + logic div_active_in; + logic div_active; + logic i0_nonblock_div_stall; + logic i0_div_prior_div_stall; + logic nonblock_div_cancel; + + logic i0_legal; + logic shift_illegal; + logic illegal_inst_en; + logic illegal_lockout_in, illegal_lockout; + logic i0_legal_decode_d; + logic i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d; + + logic [12:1] last_br_immed_d; + logic i0_rs1_depend_i0_x, i0_rs1_depend_i0_r; + logic i0_rs2_depend_i0_x, i0_rs2_depend_i0_r; + + logic i0_div_decode_d; + logic i0_load_block_d; + logic [1:0] i0_rs1_depth_d, i0_rs2_depth_d; + + logic i0_load_stall_d; + logic i0_store_stall_d; + + logic i0_predict_nt, i0_predict_t; + + logic i0_notbr_error, i0_br_toffset_error; + logic i0_ret_error; + logic i0_br_error; + logic i0_br_error_all; + logic [11:0] i0_br_offset; + + logic [20:1] i0_pcall_imm; // predicted jal's + logic i0_pcall_12b_offset; + logic i0_pcall_raw; + logic i0_pcall_case; + logic i0_pcall; + + logic i0_pja_raw; + logic i0_pja_case; + logic i0_pja; + + logic i0_pret_case; + logic i0_pret_raw, i0_pret; + + logic i0_jal; // jal's that are not predicted + + + logic i0_predict_br; + + logic store_data_bypass_d, store_data_bypass_m; + + el2_class_pkt_t i0_rs1_class_d, i0_rs2_class_d; + + el2_class_pkt_t i0_d_c, i0_x_c, i0_r_c; + + + logic i0_ap_pc2, i0_ap_pc4; + + logic i0_rd_en_d; + + logic load_ldst_bypass_d; + + logic leak1_i0_stall_in, leak1_i0_stall; + logic leak1_i1_stall_in, leak1_i1_stall; + logic leak1_mode; + + logic i0_csr_write_only_d; + + logic prior_inflight_x, prior_inflight_eff; + logic any_csr_d; + + logic prior_csr_write; + + logic [3:0] i0_pipe_en; + logic i0_r_ctl_en, i0_x_ctl_en, i0_wb_ctl_en; + logic i0_x_data_en, i0_r_data_en, i0_wb_data_en; + + logic debug_fence_i; + logic debug_fence; + + logic i0_csr_write; + logic presync_stall; + + logic i0_instr_error; + logic i0_icaf_d; + + logic clear_pause; + logic pause_state_in, pause_state; + logic pause_stall; + + logic i0_brp_valid; + logic nonblock_load_cancel; + logic lsu_idle; + logic lsu_pmu_misaligned_r; + logic csr_ren_qual_d; + logic csr_read_x; + logic i0_block_d; + logic i0_block_raw_d; // This is use to create the raw valid + logic ps_stall_in; + logic [31:0] i0_result_x; + + el2_dest_pkt_t d_d, x_d, r_d, wbd; + el2_dest_pkt_t x_d_in, r_d_in; + + el2_trap_pkt_t d_t, x_t, x_t_in, r_t_in, r_t; + + logic [3:0] lsu_trigger_match_r; + + logic [31:1] dec_i0_pc_r; + + logic csr_read, csr_write; + logic i0_br_unpred; + + logic nonblock_load_valid_m_delay; + logic i0_wen_r; + + logic tlu_wr_pause_r1; + logic tlu_wr_pause_r2; + + logic flush_final_r; + + logic bitmanip_zbb_legal; + logic bitmanip_zbs_legal; + logic bitmanip_zbe_legal; + logic bitmanip_zbc_legal; + logic bitmanip_zbp_legal; + logic bitmanip_zbr_legal; + logic bitmanip_zbf_legal; + logic bitmanip_zba_legal; + logic bitmanip_zbb_zbp_legal; + logic bitmanip_zbp_zbe_zbf_legal; + logic bitmanip_zbb_zbp_zbe_zbf_legal; + logic bitmanip_legal; + + logic data_gate_en; + logic data_gate_clk; + + + localparam NBLOAD_SIZE = pt.LSU_NUM_NBLOAD; + localparam NBLOAD_SIZE_MSB = int'(pt.LSU_NUM_NBLOAD)-1; + localparam NBLOAD_TAG_MSB = pt.LSU_NUM_NBLOAD_WIDTH-1; + + + logic cam_write, cam_inv_reset, cam_data_reset; + logic [NBLOAD_TAG_MSB:0] cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag; + logic [NBLOAD_SIZE_MSB:0] cam_wen; + + logic [NBLOAD_TAG_MSB:0] load_data_tag; + logic [NBLOAD_SIZE_MSB:0] nonblock_load_write; + + el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam; + el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in; + el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw; + + logic [4:0] nonblock_load_rd; + logic i0_nonblock_load_stall; + logic i0_nonblock_boundary_stall; + + logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d; + + logic i0_load_kill_wen_r; + + logic found; + + logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val; + + logic debug_fence_raw; + + logic [31:0] i0_result_r_raw; + logic [31:0] i0_result_corr_r; + + logic [12:1] last_br_immed_x; + + logic [31:0] i0_inst_d; + logic [31:0] i0_inst_x; + logic [31:0] i0_inst_r; + logic [31:0] i0_inst_wb_in; + logic [31:0] i0_inst_wb; + + logic [31:1] i0_pc_wb; + + logic i0_wb_en; + + logic trace_enable; + + logic debug_valid_x; + + el2_inst_pkt_t i0_itype; + el2_reg_pkt_t i0r; + + + rvdffie #(8) misc1ff (.*, + .clk(free_l2clk), + .din( {leak1_i1_stall_in,leak1_i0_stall_in,dec_tlu_flush_extint,pause_state_in ,dec_tlu_wr_pause_r, tlu_wr_pause_r1,illegal_lockout_in,ps_stall_in}), + .dout({leak1_i1_stall, leak1_i0_stall, dec_extint_stall, pause_state, tlu_wr_pause_r1,tlu_wr_pause_r2,illegal_lockout, ps_stall }) + ); + + rvdffie #(8) misc2ff (.*, + .clk(free_l2clk), + .din( {lsu_trigger_match_m[3:0],lsu_pmu_misaligned_m,div_active_in,exu_flush_final, dec_debug_valid_d}), + .dout({lsu_trigger_match_r[3:0],lsu_pmu_misaligned_r,div_active, flush_final_r, debug_valid_x}) + ); + +if(pt.BTB_ENABLE==1) begin +// branch prediction + + + // in leak1_mode, ignore any predictions for i0, treat branch as if we haven't seen it before + // in leak1 mode, also ignore branch errors for i0 + assign i0_brp_valid = dec_i0_brp.valid & ~leak1_mode & ~i0_icaf_d; + + assign dec_i0_predict_p_d.misp = '0; + assign dec_i0_predict_p_d.ataken = '0; + assign dec_i0_predict_p_d.boffset = '0; + + assign dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error + assign dec_i0_predict_p_d.pja = i0_pja; + assign dec_i0_predict_p_d.pret = i0_pret; + assign dec_i0_predict_p_d.prett[31:1] = dec_i0_brp.prett[31:1]; + assign dec_i0_predict_p_d.pc4 = dec_i0_pc4_d; + assign dec_i0_predict_p_d.hist[1:0] = dec_i0_brp.hist[1:0]; + assign dec_i0_predict_p_d.valid = i0_brp_valid & i0_legal_decode_d; + assign i0_notbr_error = i0_brp_valid & ~(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw); + + // no toffset error for a pret + assign i0_br_toffset_error = i0_brp_valid & dec_i0_brp.hist[1] & (dec_i0_brp.toffset[11:0] != i0_br_offset[11:0]) & ~i0_pret_raw; + assign i0_ret_error = i0_brp_valid & (dec_i0_brp.ret ^ i0_pret_raw); + assign i0_br_error = dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error; + assign dec_i0_predict_p_d.br_error = i0_br_error & i0_legal_decode_d & ~leak1_mode; + assign dec_i0_predict_p_d.br_start_error = dec_i0_brp.br_start_error & i0_legal_decode_d & ~leak1_mode; + assign i0_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_i0_bp_index; + + assign i0_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = dec_i0_bp_btag[pt.BTB_BTAG_SIZE-1:0]; + assign i0_br_error_all = (i0_br_error | dec_i0_brp.br_start_error) & ~leak1_mode; + assign dec_i0_predict_p_d.toffset[11:0] = i0_br_offset[11:0]; + assign i0_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = dec_i0_bp_fghr[pt.BHT_GHR_SIZE-1:0]; + assign dec_i0_predict_p_d.way = dec_i0_brp.way; + + + if(pt.BTB_FULLYA) begin + logic btb_error_found, btb_error_found_f; + logic [$clog2(pt.BTB_SIZE)-1:0] fa_error_index_ns; + + assign btb_error_found = (i0_br_error_all | btb_error_found_f) & ~dec_tlu_flush_lower_r; + assign fa_error_index_ns = (i0_br_error_all & ~btb_error_found_f) ? dec_i0_bp_fa_index : dec_fa_error_index; + + rvdff #($clog2(pt.BTB_SIZE)+1) btberrorfa_f (.*, .clk(active_clk), + .din({btb_error_found, fa_error_index_ns}), + .dout({btb_error_found_f, dec_fa_error_index})); + + + end + else + assign dec_fa_error_index = 'b0; + + + // end +end // if (pt.BTB_ENABLE==1) +else begin + + always_comb begin + dec_i0_predict_p_d = '0; + dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error + dec_i0_predict_p_d.pja = i0_pja; + dec_i0_predict_p_d.pret = i0_pret; + dec_i0_predict_p_d.pc4 = dec_i0_pc4_d; + end + + assign i0_br_error_all = '0; + assign i0_predict_index_d = '0; + assign i0_predict_btag_d = '0; + assign i0_predict_fghr_d = '0; + assign i0_brp_valid = '0; +end // else: !if(pt.BTB_ENABLE==1) + + // on br error turn anything into a nop + // on i0 instruction fetch access fault turn anything into a nop + // nop => alu rs1 imm12 rd lor + + assign i0_icaf_d = dec_i0_icaf_d | dec_i0_dbecc_d; + + assign i0_instr_error = i0_icaf_d; + + always_comb begin + i0_dp = i0_dp_raw; + if (i0_br_error_all | i0_instr_error) begin + i0_dp = '0; + i0_dp.alu = 1'b1; + i0_dp.rs1 = 1'b1; + i0_dp.rs2 = 1'b1; + i0_dp.lor = 1'b1; + i0_dp.legal = 1'b1; + i0_dp.postsync = 1'b1; + end + end + + assign i0[31:0] = dec_i0_instr_d[31:0]; + + assign dec_i0_select_pc_d = i0_dp.pc; + + // branches that can be predicted + + assign i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; + + assign i0_predict_nt = ~(dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br; + assign i0_predict_t = (dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br; + + assign i0_ap.add = i0_dp.add; + assign i0_ap.sub = i0_dp.sub; + assign i0_ap.land = i0_dp.land; + assign i0_ap.lor = i0_dp.lor; + assign i0_ap.lxor = i0_dp.lxor; + assign i0_ap.sll = i0_dp.sll; + assign i0_ap.srl = i0_dp.srl; + assign i0_ap.sra = i0_dp.sra; + assign i0_ap.slt = i0_dp.slt; + assign i0_ap.unsign = i0_dp.unsign; + assign i0_ap.beq = i0_dp.beq; + assign i0_ap.bne = i0_dp.bne; + assign i0_ap.blt = i0_dp.blt; + assign i0_ap.bge = i0_dp.bge; + + assign i0_ap.clz = i0_dp.clz; + assign i0_ap.ctz = i0_dp.ctz; + assign i0_ap.cpop = i0_dp.cpop; + assign i0_ap.sext_b = i0_dp.sext_b; + assign i0_ap.sext_h = i0_dp.sext_h; + assign i0_ap.sh1add = i0_dp.sh1add; + assign i0_ap.sh2add = i0_dp.sh2add; + assign i0_ap.sh3add = i0_dp.sh3add; + assign i0_ap.zba = i0_dp.zba; + assign i0_ap.min = i0_dp.min; + assign i0_ap.max = i0_dp.max; + assign i0_ap.pack = i0_dp.pack; + assign i0_ap.packu = i0_dp.packu; + assign i0_ap.packh = i0_dp.packh; + assign i0_ap.rol = i0_dp.rol; + assign i0_ap.ror = i0_dp.ror; + assign i0_ap.grev = i0_dp.grev; + assign i0_ap.gorc = i0_dp.gorc; + assign i0_ap.zbb = i0_dp.zbb; + assign i0_ap.bset = i0_dp.bset; + assign i0_ap.bclr = i0_dp.bclr; + assign i0_ap.binv = i0_dp.binv; + assign i0_ap.bext = i0_dp.bext; + + assign i0_ap.csr_write = i0_csr_write_only_d; + assign i0_ap.csr_imm = i0_dp.csr_imm; + assign i0_ap.jal = i0_jal; + + assign i0_ap_pc2 = ~dec_i0_pc4_d; + assign i0_ap_pc4 = dec_i0_pc4_d; + + assign i0_ap.predict_nt = i0_predict_nt; + assign i0_ap.predict_t = i0_predict_t; + + +// non block load cam logic + + always_comb begin + found = 0; + for (int i=0; i coredecode.e + +// 2) espresso -Dso -oeqntott coredecode.e | addassign -pre out. > equations + +// to generate the legal (32b instruction is legal) equation below: + +// 1) coredecode -in decode -legal > legal.e + +// 2) espresso -Dso -oeqntott legal.e | addassign -pre out. > legal_equation + +module el2_dec_dec_ctl +import el2_pkg::*; + ( + input logic [31:0] inst, + + output el2_dec_pkt_t out + ); + + logic [31:0] i; + + + assign i[31:0] = inst[31:0]; + +assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[30] + &!i[27]&!i[24]&i[4]) | (!i[30]&!i[25]&i[13]&i[12]) | (!i[29]&!i[27] + &!i[5]&i[4]) | (i[27]&i[25]&i[14]&i[4]) | (!i[29]&!i[25]&!i[13]&!i[12] + &i[4]) | (i[29]&i[27]&!i[14]&i[12]&i[4]) | (!i[27]&i[14]&!i[5]&i[4]) | ( + i[30]&!i[29]&!i[13]&i[4]) | (!i[27]&!i[25]&i[5]&i[4]) | (i[13]&!i[5] + &i[4]) | (i[2]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21] + &i[20]&!i[5]&i[4]) | (!i[12]&!i[5]&i[4]); + +assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | ( + !i[13]&i[9]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | ( + i[17]&i[13]&!i[2]) | (!i[13]&i[7]&!i[2]) | (i[16]&i[13]&!i[2]) | ( + i[15]&i[13]&!i[2]) | (!i[4]&!i[2]) | (!i[14]&!i[13]&i[6]&!i[3]) | ( + !i[6]&!i[2]); + +assign out.rs2 = (i[5]&!i[4]&!i[2]) | (!i[6]&i[5]&!i[2]); + +assign out.imm12 = (!i[4]&!i[3]&i[2]) | (i[13]&!i[5]&i[4]&!i[2]) | (!i[13]&!i[12] + &i[6]&i[4]) | (!i[12]&!i[5]&i[4]&!i[2]); + +assign out.rd = (!i[5]&!i[2]) | (i[5]&i[2]) | (i[4]); + +assign out.shimm5 = (!i[29]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&i[12] + &!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + +assign out.imm20 = (i[5]&i[3]) | (i[4]&i[2]); + +assign out.pc = (!i[5]&!i[3]&i[2]) | (i[5]&i[3]); + +assign out.load = (!i[5]&!i[4]&!i[2]); + +assign out.store = (!i[6]&i[5]&!i[4]); + +assign out.lsu = (!i[6]&!i[4]&!i[2]); + +assign out.add = (!i[14]&!i[13]&!i[12]&!i[5]&i[4]) | (!i[5]&!i[3]&i[2]) | (!i[30] + &!i[25]&!i[14]&!i[13]&!i[12]&!i[6]&i[4]&!i[2]); + +assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i[14] + &i[13]&!i[6]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]) | ( + !i[14]&i[13]&!i[5]&i[4]&!i[2]) | (i[6]&!i[4]&!i[2]); + +assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12] + &!i[5]&!i[2]); + +assign out.lor = (!i[6]&i[3]) | (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | ( + i[5]&i[4]&i[2]) | (!i[13]&!i[12]&i[6]&i[4]) | (i[14]&i[13]&!i[12] + &!i[5]&!i[2]); + +assign out.lxor = (!i[29]&!i[27]&!i[25]&i[14]&!i[13]&!i[12]&i[4]&!i[2]) | (i[14] + &!i[13]&!i[12]&!i[5]&i[4]&!i[2]); + +assign out.sll = (!i[29]&!i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.sra = (i[30]&!i[29]&!i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.srl = (!i[30]&!i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5] + &i[4]&!i[2]); + +assign out.unsign = (!i[14]&i[13]&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | ( + i[14]&!i[5]&!i[4]) | (!i[25]&!i[14]&i[13]&i[12]&!i[6]&!i[2]) | ( + i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]); + +assign out.condbr = (i[6]&!i[4]&!i[2]); + +assign out.beq = (!i[14]&!i[12]&i[6]&!i[4]&!i[2]); + +assign out.bne = (!i[14]&i[12]&i[6]&!i[4]&!i[2]); + +assign out.bge = (i[14]&i[12]&i[5]&!i[4]&!i[2]); + +assign out.blt = (i[14]&!i[12]&i[5]&!i[4]&!i[2]); + +assign out.jal = (i[6]&i[2]); + +assign out.by = (!i[13]&!i[12]&!i[6]&!i[4]&!i[2]); + +assign out.half = (i[12]&!i[6]&!i[4]&!i[2]); + +assign out.word = (i[13]&!i[6]&!i[4]); + +assign out.csr_read = (i[13]&i[6]&i[4]) | (i[7]&i[6]&i[4]) | (i[8]&i[6]&i[4]) | ( + i[9]&i[6]&i[4]) | (i[10]&i[6]&i[4]) | (i[11]&i[6]&i[4]); + +assign out.csr_clr = (i[15]&i[13]&i[12]&i[6]&i[4]) | (i[16]&i[13]&i[12]&i[6]&i[4]) | ( + i[17]&i[13]&i[12]&i[6]&i[4]) | (i[18]&i[13]&i[12]&i[6]&i[4]) | ( + i[19]&i[13]&i[12]&i[6]&i[4]); + +assign out.csr_set = (i[15]&!i[12]&i[6]&i[4]) | (i[16]&!i[12]&i[6]&i[4]) | (i[17] + &!i[12]&i[6]&i[4]) | (i[18]&!i[12]&i[6]&i[4]) | (i[19]&!i[12]&i[6] + &i[4]); + +assign out.csr_write = (!i[13]&i[12]&i[6]&i[4]); + +assign out.csr_imm = (i[14]&!i[13]&i[6]&i[4]) | (i[15]&i[14]&i[6]&i[4]) | (i[16] + &i[14]&i[6]&i[4]) | (i[17]&i[14]&i[6]&i[4]) | (i[18]&i[14]&i[6]&i[4]) | ( + i[19]&i[14]&i[6]&i[4]); + +assign out.presync = (!i[5]&i[3]) | (!i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | ( + !i[13]&i[9]&i[6]&i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11] + &i[6]&i[4]) | (i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | ( + i[17]&i[13]&i[6]&i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6] + &i[4]); + +assign out.postsync = (i[12]&!i[5]&i[3]) | (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | ( + !i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (!i[13]&i[9]&i[6] + &i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]&i[6]&i[4]) | ( + i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (i[17]&i[13]&i[6] + &i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]&i[4]); + +assign out.ebreak = (!i[22]&i[20]&!i[13]&!i[12]&i[6]&i[4]); + +assign out.ecall = (!i[21]&!i[20]&!i[13]&!i[12]&i[6]&i[4]); + +assign out.mret = (i[29]&!i[13]&!i[12]&i[6]&i[4]); + +assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30] + &i[27]&i[13]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[23]&!i[20] + &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[21]&i[20] + &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[24]&i[21] + &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[24]&!i[22] + &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[29]&i[23]&i[14] + &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]&i[29]&i[27]&i[22]&i[14] + &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[25]&i[13]&!i[12]&!i[6] + &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6] + &i[4]&!i[2]) | (i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27] + &i[14]&!i[6]&i[5]&!i[2]); + +assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | ( + !i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.rs2_sign = (!i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.low = (i[25]&!i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + +assign out.div = (!i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]); + +assign out.rem = (!i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + +assign out.fence = (!i[5]&i[3]); + +assign out.fence_i = (i[12]&!i[5]&i[3]); + +assign out.clz = (i[29]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] + &i[4]&!i[2]); + +assign out.ctz = (i[29]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] + &!i[2]); + +assign out.cpop = (i[29]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + +assign out.sext_b = (i[29]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + +assign out.sext_h = (i[29]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + +assign out.min = (i[27]&i[25]&i[14]&!i[13]&!i[6]&i[5]&!i[2]); + +assign out.max = (i[27]&i[25]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + +assign out.pack = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + +assign out.packu = (i[30]&i[27]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + +assign out.packh = (!i[30]&i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]); + +assign out.rol = (i[29]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.ror = (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13] + &!i[12]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&!i[24]&!i[13]&i[12]&!i[5] + &i[4]&!i[2]) | (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | ( + i[30]&!i[27]&i[14]&!i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13] + &!i[6]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | ( + !i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&i[14]&!i[13]&i[12]&!i[5] + &i[4]&!i[2]) | (i[30]&i[29]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14] + &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]); + +assign out.bset = (!i[30]&i[29]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.bclr = (i[30]&!i[29]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.binv = (i[30]&i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.bext = (i[30]&!i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29] + &i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.bcompress = (!i[30]&!i[29]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.bdecompress = (i[30]&i[27]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.zbe = (i[30]&i[27]&i[14]&i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&i[27] + &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25] + &!i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.clmul = (i[27]&i[25]&!i[14]&!i[13]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.clmulh = (i[27]&!i[14]&i[13]&i[12]&!i[6]&i[5]&!i[2]); + +assign out.clmulr = (i[27]&i[25]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.zbc = (i[27]&i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.grev = (i[30]&i[29]&i[27]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.gorc = (!i[30]&i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.xperm_n = (i[29]&i[27]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.xperm_b = (i[29]&i[27]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + +assign out.xperm_h = (i[29]&i[27]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + +assign out.zbp = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[30]&i[27] + &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]&!i[6] + &i[5]&i[4]&!i[2]) | (i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | ( + i[30]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[12]&!i[6] + &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6] + &i[4]&!i[2]) | (i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]); + +assign out.crc32_b = (i[29]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12] + &!i[5]&i[4]&!i[2]); + +assign out.crc32_h = (i[29]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4] + &!i[2]); + +assign out.crc32_w = (i[29]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4] + &!i[2]); + +assign out.crc32c_b = (i[29]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5] + &i[4]&!i[2]); + +assign out.crc32c_h = (i[29]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + +assign out.crc32c_w = (i[29]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + +assign out.zbr = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]); + +assign out.bfp = (i[30]&i[27]&i[13]&i[12]&!i[6]&i[5]&!i[2]); + +assign out.zbf = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | ( + i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]); + +assign out.sh1add = (i[29]&!i[27]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.sh2add = (i[29]&!i[27]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]); + +assign out.sh3add = (i[29]&!i[27]&i[14]&i[13]&!i[6]&i[5]&!i[2]); + +assign out.zba = (i[29]&!i[27]&!i[12]&!i[6]&i[5]&i[4]&!i[2]); + +assign out.pm_alu = (i[28]&i[20]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25] + &!i[6]&i[4]) | (!i[29]&!i[27]&!i[25]&!i[13]&i[12]&!i[6]&i[4]) | ( + !i[29]&!i[27]&!i[25]&!i[14]&!i[6]&i[4]) | (i[13]&!i[5]&i[4]) | (i[4] + &i[2]) | (!i[12]&!i[5]&i[4]); + + +assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23] + &!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11] + &!i[10]&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | ( + !i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&i[22] + &!i[21]&i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10] + &!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31] + &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21] + &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]&!i[9]&!i[8] + &!i[7]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28] + &!i[26]&!i[25]&i[24]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | ( + !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&i[24]&!i[22]&!i[21]&!i[6] + &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]&!i[26] + &!i[25]&!i[23]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | ( + !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[24]&!i[23]&!i[21]&!i[6] + &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26] + &i[25]&i[13]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[28]&i[27]&!i[26] + &!i[25]&!i[24]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30] + &i[29]&!i[28]&!i[26]&!i[25]&i[13]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | ( + !i[31]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[13]&!i[12]&!i[6]&i[4] + &!i[3]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[6] + &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26] + &!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29] + &!i[28]&!i[27]&!i[26]&!i[25]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31] + &i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2] + &i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&!i[26]&!i[25]&!i[13]&i[12] + &!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&!i[26]&!i[25] + &i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27] + &!i[26]&!i[25]&!i[13]&i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31] + &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | ( + !i[31]&!i[30]&!i[29]&!i[28]&!i[26]&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1] + &i[0]) | (!i[14]&!i[13]&!i[12]&i[6]&i[5]&!i[4]&!i[3]&i[1]&i[0]) | ( + i[14]&i[6]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&!i[13]&i[5] + &!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[12]&!i[6]&!i[5]&i[4]&!i[3]&i[1] + &i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31] + &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21] + &!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[11]&!i[10] + &!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[31] + &!i[30]&!i[29]&!i[28]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13] + &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&i[3]&i[2] + &i[1]&i[0]) | (i[13]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31] + &!i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | ( + i[6]&i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4] + &!i[3]&!i[2]&i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1] + &i[0]) | (i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3] + &i[2]&i[1]&i[0]); + + + + +endmodule // el2_dec_dec_ctl diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv new file mode 100644 index 0000000000000000000000000000000000000000..b551d9d652814fecdef0ea3d6e871981d63b5d7b --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_gpr_ctl.sv @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module el2_dec_gpr_ctl +import el2_pkg::*; +#( + `include "el2_param.vh" + ) ( + input logic [4:0] raddr0, // logical read addresses + input logic [4:0] raddr1, + + input logic wen0, // write enable + input logic [4:0] waddr0, // write address + input logic [31:0] wd0, // write data + + input logic wen1, // write enable + input logic [4:0] waddr1, // write address + input logic [31:0] wd1, // write data + + input logic wen2, // write enable + input logic [4:0] waddr2, // write address + input logic [31:0] wd2, // write data + + input logic clk, + input logic rst_l, + + output logic [31:0] rd0, // read data + output logic [31:0] rd1, + + input logic scan_mode +); + + logic [31:1] [31:0] gpr_out; // 31 x 32 bit GPRs + logic [31:1] [31:0] gpr_in; + logic [31:1] w0v,w1v,w2v; + logic [31:1] gpr_wr_en; + + // GPR Write Enables + assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]); + for ( genvar j=1; j<32; j++ ) begin : gpr + rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][31:0]), .dout(gpr_out[j][31:0])); + end : gpr + + // the read out + always_comb begin + rd0[31:0] = 32'b0; + rd1[31:0] = 32'b0; + w0v[31:1] = 31'b0; + w1v[31:1] = 31'b0; + w2v[31:1] = 31'b0; + gpr_in[31:1] = '0; + + // GPR Read logic + for (int j=1; j<32; j++ ) begin + rd0[31:0] |= ({32{(raddr0[4:0]== 5'(j))}} & gpr_out[j][31:0]); + rd1[31:0] |= ({32{(raddr1[4:0]== 5'(j))}} & gpr_out[j][31:0]); + end + + // GPR Write logic + for (int j=1; j<32; j++ ) begin + w0v[j] = wen0 & (waddr0[4:0]== 5'(j) ); + w1v[j] = wen1 & (waddr1[4:0]== 5'(j) ); + w2v[j] = wen2 & (waddr2[4:0]== 5'(j) ); + gpr_in[j] = ({32{w0v[j]}} & wd0[31:0]) | + ({32{w1v[j]}} & wd1[31:0]) | + ({32{w2v[j]}} & wd2[31:0]); + end + end // always_comb begin + +`ifdef RV_ASSERT_ON + + logic write_collision_unused; + assign write_collision_unused = ( (w0v[31:1] == w1v[31:1]) & wen0 & wen1 ) | + ( (w0v[31:1] == w2v[31:1]) & wen0 & wen2 ) | + ( (w1v[31:1] == w2v[31:1]) & wen1 & wen2 ); + + + // asserting that no 2 ports will write to the same gpr simultaneously + assert_multiple_wen_to_same_gpr: assert #0 (~( write_collision_unused ) ); + +`endif + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv new file mode 100644 index 0000000000000000000000000000000000000000..8dbaffda8374a3640efa9782a07e8f16d58d14e1 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_ib_ctl.sv @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module el2_dec_ib_ctl +import el2_pkg::*; +#( +`include "el2_param.vh" + ) + ( + input logic dbg_cmd_valid, // valid dbg cmd + + input logic dbg_cmd_write, // dbg cmd is write + input logic [1:0] dbg_cmd_type, // dbg type + input logic [31:0] dbg_cmd_addr, // expand to 31:0 + + input el2_br_pkt_t i0_brp, // i0 branch packet from aligner + input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index + input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR + input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag + input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index + + input logic ifu_i0_pc4, // i0 is 4B inst else 2B + input logic ifu_i0_valid, // i0 valid from ifu + input logic ifu_i0_icaf, // i0 instruction access fault + input logic [1:0] ifu_i0_icaf_type, // i0 instruction access fault type + + input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst + input logic ifu_i0_dbecc, // i0 double-bit error + input logic [31:0] ifu_i0_instr, // i0 instruction from the aligner + input logic [31:1] ifu_i0_pc, // i0 pc from the aligner + + + output logic dec_ib0_valid_d, // ib0 valid + output logic dec_debug_valid_d, // Debug read or write at D-stage + + + output logic [31:0] dec_i0_instr_d, // i0 inst at decode + + output logic [31:1] dec_i0_pc_d, // i0 pc at decode + + output logic dec_i0_pc4_d, // i0 is 4B inst else 2B + + output el2_br_pkt_t dec_i0_brp, // i0 branch packet at decode + output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index + output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR + output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag + output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index + + output logic dec_i0_icaf_d, // i0 instruction access fault at decode + output logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst + output logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type + output logic dec_i0_dbecc_d, // i0 double-bit error at decode + output logic dec_debug_wdata_rs1_d, // put debug write data onto rs1 source: machine is halted + + output logic dec_debug_fence_d // debug fence inst + + ); + + + logic debug_valid; + logic [4:0] dreg; + logic [11:0] dcsr; + logic [31:0] ib0, ib0_debug_in; + + logic debug_read; + logic debug_write; + logic debug_read_gpr; + logic debug_write_gpr; + logic debug_read_csr; + logic debug_write_csr; + + logic [34:0] ifu_i0_pcdata, pc0; + + assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf, + ifu_i0_pc[31:1], ifu_i0_pc4 }; + + assign pc0[34:0] = ifu_i0_pcdata[34:0]; + + assign dec_i0_icaf_second_d = pc0[34]; // icaf's can only decode as i0 + + assign dec_i0_dbecc_d = pc0[33]; + + assign dec_i0_icaf_d = pc0[32]; + assign dec_i0_pc_d[31:1] = pc0[31:1]; + assign dec_i0_pc4_d = pc0[0]; + + assign dec_i0_icaf_type_d[1:0] = ifu_i0_icaf_type[1:0]; + +// GPR accesses + +// put reg to read on rs1 +// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011} + +// put write date on rs1 +// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011} + + +// CSR accesses +// csr is of form rd, csr, rs1 + +// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011} + +// put write data on rs1 +// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011} + +// abstract memory command not done here + assign debug_valid = dbg_cmd_valid & (dbg_cmd_type[1:0] != 2'h2); + + + assign debug_read = debug_valid & ~dbg_cmd_write; + assign debug_write = debug_valid & dbg_cmd_write; + + assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0]==2'h0); + assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0]==2'h0); + assign debug_read_csr = debug_read & (dbg_cmd_type[1:0]==2'h1); + assign debug_write_csr = debug_write & (dbg_cmd_type[1:0]==2'h1); + + assign dreg[4:0] = dbg_cmd_addr[4:0]; + assign dcsr[11:0] = dbg_cmd_addr[11:0]; + + + assign ib0_debug_in[31:0] = ({32{debug_read_gpr}} & {12'b000000000000,dreg[4:0],15'b110000000110011}) | + ({32{debug_write_gpr}} & {20'b00000000000000000110,dreg[4:0],7'b0110011}) | + ({32{debug_read_csr}} & {dcsr[11:0],20'b00000010000001110011}) | + ({32{debug_write_csr}} & {dcsr[11:0],20'b00000001000001110011}); + + + + // machine is in halted state, pipe empty, write will always happen next cycle + + assign dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; + + + // special fence csr for use only in debug mode + + assign dec_debug_fence_d = debug_write_csr & (dcsr[11:0] == 12'h7c4); + + assign ib0[31:0] = (debug_valid) ? ib0_debug_in[31:0] : ifu_i0_instr[31:0]; + + assign dec_ib0_valid_d = ifu_i0_valid | debug_valid; + + assign dec_debug_valid_d = debug_valid; + + assign dec_i0_instr_d[31:0] = ib0[31:0]; + + assign dec_i0_brp = i0_brp; + assign dec_i0_bp_index = ifu_i0_bp_index; + assign dec_i0_bp_fghr = ifu_i0_bp_fghr; + assign dec_i0_bp_btag = ifu_i0_bp_btag; + assign dec_i0_bp_fa_index = ifu_i0_fa_index; + +endmodule diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv new file mode 100644 index 0000000000000000000000000000000000000000..511c0adaa56281b8b0c0d8dad0c87cc9972b6a49 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_tlu_ctl.sv @@ -0,0 +1,2950 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +//******************************************************************************** +// el2_dec_tlu_ctl.sv +// +// +// Function: CSRs, Commit/WB, flushing, exceptions, interrupts +// Comments: +// +//******************************************************************************** + +module el2_dec_tlu_ctl +import el2_pkg::*; +#( +`include "el2_param.vh" + ) + ( + input logic clk, + input logic free_clk, + input logic free_l2clk, + input logic rst_l, + input logic scan_mode, + + input logic [31:1] rst_vec, // reset vector, from core pins + input logic nmi_int, // nmi pin + input logic [31:1] nmi_vec, // nmi vector + input logic i_cpu_halt_req, // Asynchronous Halt request to CPU + input logic i_cpu_run_req, // Asynchronous Restart request to CPU + + input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle + + + // perf counter inputs + input logic ifu_pmu_instr_aligned, // aligned instructions + input logic ifu_pmu_fetch_stall, // fetch unit stalled + input logic ifu_pmu_ic_miss, // icache miss + input logic ifu_pmu_ic_hit, // icache hit + input logic ifu_pmu_bus_error, // Instruction side bus error + input logic ifu_pmu_bus_busy, // Instruction side bus busy + input logic ifu_pmu_bus_trxn, // Instruction side bus transaction + input logic dec_pmu_instr_decoded, // decoded instructions + input logic dec_pmu_decode_stall, // decode stall + input logic dec_pmu_presync_stall, // decode stall due to presync'd inst + input logic dec_pmu_postsync_stall,// decode stall due to postsync'd inst + input logic lsu_store_stall_any, // SB or WB is full, stall decode + input logic dma_dccm_stall_any, // DMA stall of lsu + input logic dma_iccm_stall_any, // DMA stall of ifu + input logic exu_pmu_i0_br_misp, // pipe 0 branch misp + input logic exu_pmu_i0_br_ataken, // pipe 0 branch actual taken + input logic exu_pmu_i0_pc4, // pipe 0 4 byte branch + input logic lsu_pmu_bus_trxn, // D side bus transaction + input logic lsu_pmu_bus_misaligned, // D side bus misaligned + input logic lsu_pmu_bus_error, // D side bus error + input logic lsu_pmu_bus_busy, // D side bus busy + input logic lsu_pmu_load_external_m, // D side bus load + input logic lsu_pmu_store_external_m, // D side bus store + input logic dma_pmu_dccm_read, // DMA DCCM read + input logic dma_pmu_dccm_write, // DMA DCCM write + input logic dma_pmu_any_read, // DMA read + input logic dma_pmu_any_write, // DMA write + + input logic [31:1] lsu_fir_addr, // Fast int address + input logic [1:0] lsu_fir_error, // Fast int lookup error + + input logic iccm_dma_sb_error, // I side dma single bit error + + input el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu precise exception/error packet + input logic lsu_single_ecc_error_incr, // LSU inc SB error counter + + input logic dec_pause_state, // Pause counter not zero + input logic lsu_imprecise_error_store_any, // store bus error + input logic lsu_imprecise_error_load_any, // store bus error + input logic [31:0] lsu_imprecise_error_addr_any, // store bus error address + + input logic dec_csr_wen_unq_d, // valid csr with write - for csr legal + input logic dec_csr_any_unq_d, // valid csr - for csr legal + input logic [11:0] dec_csr_rdaddr_d, // read address for csr + + input logic dec_csr_wen_r, // csr write enable at wb + input logic [11:0] dec_csr_wraddr_r, // write address for csr + input logic [31:0] dec_csr_wrdata_r, // csr write data at wb + + input logic dec_csr_stall_int_ff, // csr is mie/mstatus + + input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid + + input logic [31:1] exu_npc_r, // for NPC tracking + + input logic [31:1] dec_tlu_i0_pc_r, // for PC/NPC tracking + + input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode + + input logic [31:0] dec_illegal_inst, // For mtval + input logic dec_i0_decode_d, // decode valid, used for clean icache diagnostics + + // branch info from pipe0 for errors or counter updates + input logic [1:0] exu_i0_br_hist_r, // history + input logic exu_i0_br_error_r, // error + input logic exu_i0_br_start_error_r, // start error + input logic exu_i0_br_valid_r, // valid + input logic exu_i0_br_mp_r, // mispredict + input logic exu_i0_br_middle_r, // middle of bank + + // branch info from pipe1 for errors or counter updates + + input logic exu_i0_br_way_r, // way hit or repl + + output logic dec_tlu_core_empty, // core is empty + // Debug start + output logic dec_dbg_cmd_done, // abstract command done + output logic dec_dbg_cmd_fail, // abstract command failed + output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command + output logic dec_tlu_debug_mode, // Core is in debug mode + output logic dec_tlu_resume_ack, // Resume acknowledge + output logic dec_tlu_debug_stall, // stall decode while waiting on core to empty + + output logic dec_tlu_flush_noredir_r , // Tell fetch to idle on this flush + output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC + output logic dec_tlu_flush_leak_one_r, // single step + output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc. This is the D stage of the error + + output logic dec_tlu_flush_extint, // fast ext int started + output logic [31:2] dec_tlu_meihap, // meihap for fast int + + input logic dbg_halt_req, // DM requests a halt + input logic dbg_resume_req, // DM requests a resume + input logic ifu_miss_state_idle, // I-side miss buffer empty + input logic lsu_idle_any, // lsu is idle + input logic dec_div_active, // oop div is active + output el2_trigger_pkt_t [3:0] trigger_pkt_any, // trigger info for trigger blocks + + input logic ifu_ic_error_start, // IC single bit error + input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error + + + input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data + input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid + output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics + // Debug end + + input logic [7:0] pic_claimid, // pic claimid for csr + input logic [3:0] pic_pl, // pic priv level for csr + input logic mhwakeup, // high priority external int, wakeup if halted + + input logic mexintpend, // external interrupt pending + input logic timer_int, // timer interrupt pending + input logic soft_int, // software interrupt pending + + output logic o_cpu_halt_status, // PMU interface, halted + output logic o_cpu_halt_ack, // halt req ack + output logic o_cpu_run_ack, // run req ack + output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + + input logic [31:4] core_id, // Core ID + + // external MPC halt/run interface + input logic mpc_debug_halt_req, // Async halt request + input logic mpc_debug_run_req, // Async run request + input logic mpc_reset_run_req, // Run/halt after reset + output logic mpc_debug_halt_ack, // Halt ack + output logic mpc_debug_run_ack, // Run ack + output logic debug_brkpt_status, // debug breakpoint + + output logic [3:0] dec_tlu_meicurpl, // to PIC + output logic [3:0] dec_tlu_meipt, // to PIC + + + output logic [31:0] dec_csr_rddata_d, // csr read data at wb + output logic dec_csr_legal_d, // csr indicates legal operation + + output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp + + output logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state + output logic dec_tlu_flush_lower_wb, // commit has a flush (exception, int, mispredict at e4) + output logic dec_tlu_i0_commit_cmt, // committed an instruction + + output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state + output logic dec_tlu_flush_lower_r, // commit has a flush (exception, int) + output logic [31:1] dec_tlu_flush_path_r, // flush pc + output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache + output logic dec_tlu_wr_pause_r, // CSR write to pause reg is at R. + output logic dec_tlu_flush_pause_r, // Flush is due to pause + + output logic dec_tlu_presync_d, // CSR read needs to be presync'd + output logic dec_tlu_postsync_d, // CSR needs to be presync'd + + + output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control + + output logic dec_tlu_force_halt, // halt has been forced + + output logic dec_tlu_perfcnt0, // toggles when pipe0 perf counter 0 has an event inc + output logic dec_tlu_perfcnt1, // toggles when pipe0 perf counter 1 has an event inc + output logic dec_tlu_perfcnt2, // toggles when pipe0 perf counter 2 has an event inc + output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc + + output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid + output logic dec_tlu_i0_valid_wb1, // pipe 0 valid + output logic dec_tlu_int_valid_wb1, // pipe 2 int valid + output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause + output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value + + // feature disable from mfdc + output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding + output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address + output logic dec_tlu_core_ecc_disable, // disable core ECC + output logic dec_tlu_bpred_disable, // disable branch prediction + output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing + output logic dec_tlu_pipelining_disable, // disable pipelining + output logic dec_tlu_trace_disable, // disable trace + output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16] + + // clock gating overrides from mcgc + output logic dec_tlu_misc_clk_override, // override misc clock domain gating + output logic dec_tlu_dec_clk_override, // override decode clock domain gating + output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating + output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating + output logic dec_tlu_bus_clk_override, // override bus clock domain gating + output logic dec_tlu_pic_clk_override, // override PIC clock domain gating + output logic dec_tlu_picio_clk_override,// override PICIO clock domain gating + output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating + output logic dec_tlu_icm_clk_override // override ICCM clock domain gating + + ); + + logic clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f, + nmi_lsu_store_type_f, allow_dbg_halt_csr_write, dbg_cmd_done_ns, i_cpu_run_req_d1_raw, debug_mode_status, lsu_single_ecc_error_r_d1, + sel_npc_r, sel_npc_resume, ce_int, + nmi_in_debug_mode, dpc_capture_npc, dpc_capture_pc, tdata_load, tdata_opcode, tdata_action, perfcnt_halted, tdata_chain, + tdata_kill_write; + + + logic reset_delayed, reset_detect, reset_detected; + logic wr_mstatus_r, wr_mtvec_r, wr_mcyclel_r, wr_mcycleh_r, + wr_minstretl_r, wr_minstreth_r, wr_mscratch_r, wr_mepc_r, wr_mcause_r, wr_mscause_r, wr_mtval_r, + wr_mrac_r, wr_meihap_r, wr_meicurpl_r, wr_meipt_r, wr_dcsr_r, + wr_dpc_r, wr_meicidpl_r, wr_meivt_r, wr_meicpct_r, wr_micect_r, wr_miccmect_r, wr_mfdht_r, wr_mfdhs_r, + wr_mdccmect_r,wr_mhpme3_r, wr_mhpme4_r, wr_mhpme5_r, wr_mhpme6_r; + logic wr_mpmc_r; + logic [1:1] mpmc_b_ns, mpmc, mpmc_b; + logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted; + logic wr_mcountinhibit_r; + logic [6:0] mcountinhibit; + logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r; + logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out; + logic [9:0] mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3; + logic [9:0] tdata_wrdata_r; + logic [1:0] mtsel_ns, mtsel; + logic tlu_i0_kill_writeb_r; + logic [1:0] mstatus_ns, mstatus; + logic [1:0] mfdhs_ns, mfdhs; + logic [31:0] force_halt_ctr, force_halt_ctr_f; + logic force_halt; + logic [5:0] mfdht, mfdht_ns; + logic mstatus_mie_ns; + logic [30:0] mtvec_ns, mtvec; + logic [15:2] dcsr_ns, dcsr; + logic [5:0] mip_ns, mip; + logic [5:0] mie_ns, mie; + logic [31:0] mcyclel_ns, mcyclel; + logic [31:0] mcycleh_ns, mcycleh; + logic [31:0] minstretl_ns, minstretl; + logic [31:0] minstreth_ns, minstreth; + logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect; + logic [26:0] micect_inc, miccmect_inc, mdccmect_inc; + logic [31:0] mscratch; + logic [31:0] mhpmc3, mhpmc3_ns, mhpmc4, mhpmc4_ns, mhpmc5, mhpmc5_ns, mhpmc6, mhpmc6_ns; + logic [31:0] mhpmc3h, mhpmc3h_ns, mhpmc4h, mhpmc4h_ns, mhpmc5h, mhpmc5h_ns, mhpmc6h, mhpmc6h_ns; + logic [9:0] mhpme3, mhpme4, mhpme5, mhpme6; + logic [31:0] mrac; + logic [9:2] meihap; + logic [31:10] meivt; + logic [3:0] meicurpl_ns, meicurpl; + logic [3:0] meicidpl_ns, meicidpl; + logic [3:0] meipt_ns, meipt; + logic [31:0] mdseac; + logic mdseac_locked_ns, mdseac_locked_f, mdseac_en, nmi_lsu_detected; + logic [31:1] mepc_ns, mepc; + logic [31:1] dpc_ns, dpc; + logic [31:0] mcause_ns, mcause; + logic [3:0] mscause_ns, mscause, mscause_type; + logic [31:0] mtval_ns, mtval; + logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb; + logic tlu_flush_lower_r, tlu_flush_lower_r_d1; + logic [31:1] tlu_flush_path_r, tlu_flush_path_r_d1; + logic i0_valid_wb; + logic tlu_i0_commit_cmt; + logic [31:1] vectored_path, interrupt_path; + logic [16:0] dicawics_ns, dicawics; + logic wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r; + logic [31:0] dicad0_ns, dicad0, dicad0h_ns, dicad0h; + + logic [6:0] dicad1_ns, dicad1_raw; + logic [31:0] dicad1; + logic ebreak_r, ebreak_to_debug_mode_r, ecall_r, illegal_r, mret_r, inst_acc_r, fence_i_r, + ic_perr_r, iccm_sbecc_r, ebreak_to_debug_mode_r_d1, kill_ebreak_count_r, inst_acc_second_r; + logic ce_int_ready, ext_int_ready, timer_int_ready, soft_int_ready, int_timer0_int_ready, int_timer1_int_ready, mhwakeup_ready, + take_ext_int, take_ce_int, take_timer_int, take_soft_int, take_int_timer0_int, take_int_timer1_int, take_nmi, take_nmi_r_d1, int_timer0_int_possible, int_timer1_int_possible; + logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req; + logic synchronous_flush_r; + logic [4:0] exc_cause_r, exc_cause_wb; + logic mcyclel_cout, mcyclel_cout_f, mcyclela_cout; + logic [31:0] mcyclel_inc; + logic [31:0] mcycleh_inc; + + logic minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta; + + logic [31:0] minstretl_inc, minstretl_read; + logic [31:0] minstreth_inc, minstreth_read; + logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1; + logic valid_csr; + logic rfpc_i0_r; + logic lsu_i0_rfnpc_r; + logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r; + logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r, + lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts; + logic i0_trigger_eval_r; + + logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f; + logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset, + dbg_tlu_halted, core_empty, lsu_idle_any_f, ifu_miss_state_idle_f, resume_ack_ns, + debug_halt_req_f, debug_resume_req_f_raw, debug_resume_req_f, enter_debug_halt_req, dcsr_single_step_done, dcsr_single_step_done_f, + debug_halt_req_d1, debug_halt_req_ns, dcsr_single_step_running, dcsr_single_step_running_f, internal_dbg_halt_timers; + + logic [3:0] i0_trigger_r, trigger_action, trigger_enabled, + i0_trigger_chain_masked_r; + logic i0_trigger_hit_r, i0_trigger_hit_raw_r, i0_trigger_action_r, + trigger_hit_r_d1, + mepc_trigger_hit_sel_pc_r; + logic [3:0] update_hit_bit_r, i0_iside_trigger_has_pri_r,i0trigger_qual_r, i0_lsu_trigger_has_pri_r; + logic cpu_halt_status, cpu_halt_ack, cpu_run_ack, ext_halt_pulse, i_cpu_halt_req_d1, i_cpu_run_req_d1; + + logic inst_acc_r_raw, trigger_hit_dmode_r, trigger_hit_dmode_r_d1; + logic [9:0] mcgc, mcgc_ns, mcgc_int; + logic [18:0] mfdc; + logic i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, pmu_fw_halt_req_ns, pmu_fw_halt_req_f, int_timer_stalled, + fw_halt_req, enter_pmu_fw_halt_req, pmu_fw_tlu_halted, pmu_fw_tlu_halted_f, internal_pmu_fw_halt_mode, + internal_pmu_fw_halt_mode_f, int_timer0_int_hold, int_timer1_int_hold, int_timer0_int_hold_f, int_timer1_int_hold_f; + logic nmi_int_delayed, nmi_int_detected; + logic [3:0] trigger_execute, trigger_data, trigger_store; + logic dec_tlu_pmu_fw_halted; + + logic mpc_run_state_ns, debug_brkpt_status_ns, mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns, dbg_halt_state_ns, dbg_run_state_ns, + dbg_halt_state_f, mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f, mpc_halt_state_f, mpc_halt_state_ns, mpc_run_state_f, debug_brkpt_status_f, + mpc_debug_halt_ack_f, mpc_debug_run_ack_f, dbg_run_state_f, mpc_debug_halt_req_sync_pulse, + mpc_debug_run_req_sync_pulse, debug_brkpt_valid, debug_halt_req, debug_resume_req, dec_tlu_mpc_halted_only_ns; + logic take_ext_int_start, ext_int_freeze, take_ext_int_start_d1, take_ext_int_start_d2, + take_ext_int_start_d3, ext_int_freeze_d1, csr_meicpct, ignore_ext_int_due_to_lsu_stall; + logic mcause_sel_nmi_store, mcause_sel_nmi_load, mcause_sel_nmi_ext, fast_int_meicpct; + logic [1:0] mcause_fir_error_type; + logic dbg_halt_req_held_ns, dbg_halt_req_held, dbg_halt_req_final; + logic iccm_repair_state_ns, iccm_repair_state_d1, iccm_repair_state_rfnpc; + + + // internal timer, isolated for size reasons + logic [31:0] dec_timer_rddata_d; + logic dec_timer_read_d, dec_timer_t0_pulse, dec_timer_t1_pulse; + logic csr_mitctl0; + logic csr_mitctl1; + logic csr_mitb0; + logic csr_mitb1; + logic csr_mitcnt0; + logic csr_mitcnt1; + + logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw; + logic csr_wr_clk; + logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2; + logic lsu_pmu_load_external_r, lsu_pmu_store_external_r; + logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1; + logic lsu_single_ecc_error_r; + logic [31:0] lsu_error_pkt_addr_r; + logic mcyclel_cout_in; + logic i0_valid_no_ebreak_ecall_r; + logic minstret_enable_f; + logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r; + logic pc0_valid_r; + logic [15:0] mfdc_int, mfdc_ns; + logic [31:0] mrac_in; + logic [31:27] csr_sat; + logic [8:6] dcsr_cause; + logic enter_debug_halt_req_le, dcsr_cause_upgradeable; + logic icache_rd_valid, icache_wr_valid, icache_rd_valid_f, icache_wr_valid_f; + logic [3:0] mhpmc_inc_r, mhpmc_inc_r_d1; + + logic [3:0][9:0] mhpme_vec; + logic mhpmc3_wr_en0, mhpmc3_wr_en1, mhpmc3_wr_en; + logic mhpmc4_wr_en0, mhpmc4_wr_en1, mhpmc4_wr_en; + logic mhpmc5_wr_en0, mhpmc5_wr_en1, mhpmc5_wr_en; + logic mhpmc6_wr_en0, mhpmc6_wr_en1, mhpmc6_wr_en; + logic mhpmc3h_wr_en0, mhpmc3h_wr_en; + logic mhpmc4h_wr_en0, mhpmc4h_wr_en; + logic mhpmc5h_wr_en0, mhpmc5h_wr_en; + logic mhpmc6h_wr_en0, mhpmc6h_wr_en; + logic [63:0] mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr; + logic perfcnt_halted_d1, zero_event_r; + logic [3:0] perfcnt_during_sleep; + logic [9:0] event_r; + + el2_inst_pkt_t pmu_i0_itype_qual; + + logic csr_mfdht; + logic csr_mfdhs; + logic csr_misa; + logic csr_mvendorid; + logic csr_marchid; + logic csr_mimpid; + logic csr_mhartid; + logic csr_mstatus; + logic csr_mtvec; + logic csr_mip; + logic csr_mie; + logic csr_mcyclel; + logic csr_mcycleh; + logic csr_minstretl; + logic csr_minstreth; + logic csr_mscratch; + logic csr_mepc; + logic csr_mcause; + logic csr_mscause; + logic csr_mtval; + logic csr_mrac; + logic csr_dmst; + logic csr_mdseac; + logic csr_meihap; + logic csr_meivt; + logic csr_meipt; + logic csr_meicurpl; + logic csr_meicidpl; + logic csr_dcsr; + logic csr_mcgc; + logic csr_mfdc; + logic csr_dpc; + logic csr_mtsel; + logic csr_mtdata1; + logic csr_mtdata2; + logic csr_mhpmc3; + logic csr_mhpmc4; + logic csr_mhpmc5; + logic csr_mhpmc6; + logic csr_mhpmc3h; + logic csr_mhpmc4h; + logic csr_mhpmc5h; + logic csr_mhpmc6h; + logic csr_mhpme3; + logic csr_mhpme4; + logic csr_mhpme5; + logic csr_mhpme6; + logic csr_mcountinhibit; + logic csr_mpmc; + logic csr_micect; + logic csr_miccmect; + logic csr_mdccmect; + logic csr_dicawics; + logic csr_dicad0h; + logic csr_dicad0; + logic csr_dicad1; + logic csr_dicago; + logic presync; + logic postsync; + logic legal; + logic dec_csr_wen_r_mod; + + logic flush_clkvalid; + logic sel_fir_addr; + logic wr_mie_r; + logic mtval_capture_pc_r; + logic mtval_capture_pc_plus2_r; + logic mtval_capture_inst_r; + logic mtval_capture_lsu_r; + logic mtval_clear_r; + logic wr_mcgc_r; + logic wr_mfdc_r; + logic wr_mdeau_r; + logic trigger_hit_for_dscr_cause_r_d1; + logic conditionally_illegal; + + logic [3:0] ifu_mscause ; + logic ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f; + + el2_dec_timer_ctl #(.pt(pt)) int_timers(.*); + // end of internal timers + + assign clk_override = dec_tlu_dec_clk_override; + + // Async inputs to the core have to be sync'd to the core clock. + rvsyncss #(7) syncro_ff(.*, + .clk(free_clk), + .din ({nmi_int, timer_int, soft_int, i_cpu_halt_req, i_cpu_run_req, mpc_debug_halt_req, mpc_debug_run_req}), + .dout({nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync_raw, mpc_debug_run_req_sync})); + + // for CSRs that have inpipe writes only + + rvoclkhdr csrwr_r_cgc ( .en(dec_csr_wen_r_mod | clk_override), .l1clk(csr_wr_clk), .* ); + + assign e4_valid = dec_tlu_i0_valid_r; + assign e4e5_valid = e4_valid | e5_valid; + assign flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | + reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | iccm_sbecc_r | + clk_override; + rvoclkhdr e4e5_cgc ( .en(e4e5_valid | clk_override), .l1clk(e4e5_clk), .* ); + rvoclkhdr e4e5_int_cgc ( .en(e4e5_valid | flush_clkvalid), .l1clk(e4e5_int_clk), .* ); + + rvdffie #(11) freeff (.*, .clk(free_l2clk), + .din ({ifu_ic_error_start, ifu_iccm_rd_ecc_single_err, iccm_repair_state_ns, e4_valid, internal_dbg_halt_mode, + lsu_pmu_load_external_m, lsu_pmu_store_external_m, tlu_flush_lower_r, tlu_i0_kill_writeb_r, + internal_dbg_halt_mode_f, force_halt}), + .dout({ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f, iccm_repair_state_d1, e5_valid, internal_dbg_halt_mode_f, + lsu_pmu_load_external_r, lsu_pmu_store_external_r, tlu_flush_lower_r_d1, dec_tlu_i0_kill_writeb_wb, + internal_dbg_halt_mode_f2, dec_tlu_force_halt})); + + assign dec_tlu_i0_kill_writeb_r = tlu_i0_kill_writeb_r; + + assign nmi_int_detected = (nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected | (nmi_int_detected_f & ~take_nmi_r_d1) | nmi_fir_type; + // if the first nmi is a lsu type, note it. If there's already an nmi pending, ignore. Simultaneous with FIR, drop. + assign nmi_lsu_load_type = (nmi_lsu_detected & lsu_imprecise_error_load_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | + (nmi_lsu_load_type_f & ~take_nmi_r_d1); + assign nmi_lsu_store_type = (nmi_lsu_detected & lsu_imprecise_error_store_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | + (nmi_lsu_store_type_f & ~take_nmi_r_d1); + + assign nmi_fir_type = ~nmi_int_detected_f & take_ext_int_start_d3 & |lsu_fir_error[1:0]; + + // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared + assign nmi_lsu_detected = ~mdseac_locked_f & (lsu_imprecise_error_load_any | lsu_imprecise_error_store_any) & ~nmi_fir_type; + + +localparam MSTATUS_MIE = 0; +localparam MIP_MCEIP = 5; +localparam MIP_MITIP0 = 4; +localparam MIP_MITIP1 = 3; +localparam MIP_MEIP = 2; +localparam MIP_MTIP = 1; +localparam MIP_MSIP = 0; + +localparam MIE_MCEIE = 5; +localparam MIE_MITIE0 = 4; +localparam MIE_MITIE1 = 3; +localparam MIE_MEIE = 2; +localparam MIE_MTIE = 1; +localparam MIE_MSIE = 0; + +localparam DCSR_EBREAKM = 15; +localparam DCSR_STEPIE = 11; +localparam DCSR_STOPC = 10; +localparam DCSR_STEP = 2; + + + assign reset_delayed = reset_detect ^ reset_detected; + + // ---------------------------------------------------------------------- + // MPC halt + // - can interact with debugger halt and v-v + + // fast ints in progress have priority + assign mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1; + + rvdffie #(16) mpvhalt_ff (.*, .clk(free_l2clk), + .din({1'b1, reset_detect, + nmi_int_sync, nmi_int_detected, nmi_lsu_load_type, nmi_lsu_store_type, + mpc_debug_halt_req_sync, mpc_debug_run_req_sync, + mpc_halt_state_ns, mpc_run_state_ns, debug_brkpt_status_ns, + mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns, + dbg_halt_state_ns, dbg_run_state_ns, + dec_tlu_mpc_halted_only_ns}), + .dout({reset_detect, reset_detected, + nmi_int_delayed, nmi_int_detected_f, nmi_lsu_load_type_f, nmi_lsu_store_type_f, + mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f, + mpc_halt_state_f, mpc_run_state_f, debug_brkpt_status_f, + mpc_debug_halt_ack_f, mpc_debug_run_ack_f, + dbg_halt_state_f, dbg_run_state_f, + dec_tlu_mpc_halted_only})); + + // turn level sensitive requests into pulses + assign mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f; + assign mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f; + + // states + assign mpc_halt_state_ns = (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse | (reset_delayed & ~mpc_reset_run_req)) & ~mpc_debug_run_req_sync; + assign mpc_run_state_ns = (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f); + + // note, MPC halt can allow the jtag debugger to just start sending commands. When that happens, set the interal debugger halt state to prevent + // MPC run from starting the core. + assign dbg_halt_state_ns = (dbg_halt_state_f | (dbg_halt_req_final | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1)) & ~dbg_resume_req; + assign dbg_run_state_ns = (dbg_run_state_f | dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f); + + // tell dbg we are only MPC halted + assign dec_tlu_mpc_halted_only_ns = ~dbg_halt_state_f & mpc_halt_state_f; + + // this asserts from detection of bkpt until after we leave debug mode + assign debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; + assign debug_brkpt_status_ns = (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f); + + // acks back to interface + assign mpc_debug_halt_ack_ns = (mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty) | (mpc_debug_halt_ack_f & mpc_debug_halt_req_sync); + assign mpc_debug_run_ack_ns = (mpc_debug_run_req_sync & ~internal_dbg_halt_mode & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) ; + + // Pins + assign mpc_debug_halt_ack = mpc_debug_halt_ack_f; + assign mpc_debug_run_ack = mpc_debug_run_ack_f; + assign debug_brkpt_status = debug_brkpt_status_f; + + // DBG halt req is a pulse, fast ext int in progress has priority + assign dbg_halt_req_held_ns = (dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1; + assign dbg_halt_req_final = (dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1; + + // combine MPC and DBG halt requests + assign debug_halt_req = (dbg_halt_req_final | mpc_debug_halt_req_sync | (reset_delayed & ~mpc_reset_run_req)) & ~internal_dbg_halt_mode_f & ~ext_int_freeze_d1; + + assign debug_resume_req = ~debug_resume_req_f & // squash back to back resumes + ((mpc_run_state_ns & ~dbg_halt_state_ns) | // MPC run req + (dbg_run_state_ns & ~mpc_halt_state_ns)); // dbg request is a pulse + + + // HALT + // dbg/pmu/fw requests halt, service as soon as lsu is not blocking interrupts + assign take_halt = (debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r & ~mret_r & ~halt_taken_f & ~dec_tlu_flush_noredir_r_d1 & ~take_reset; + + // hold after we take a halt, so we don't keep taking halts + assign halt_taken = (dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1 & ~take_ext_int_start_d1) | (halt_taken_f & ~dbg_tlu_halted_f & ~pmu_fw_tlu_halted_f & ~interrupt_valid_r_d1); + + // After doing halt flush (RFNPC) wait until core is idle before asserting a particular halt mode + // It takes a cycle for mb_empty to assert after a fetch, take_halt covers that cycle + assign core_empty = force_halt | + (lsu_idle_any & lsu_idle_any_f & ifu_miss_state_idle & ifu_miss_state_idle_f & ~debug_halt_req & ~debug_halt_req_d1 & ~dec_div_active); + + assign dec_tlu_core_empty = core_empty; + +//-------------------------------------------------------------------------------- +// Debug start +// + + assign enter_debug_halt_req = (~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1; + + // dbg halt state active from request until non-step resume + assign internal_dbg_halt_mode = debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr[DCSR_STEP])); + // dbg halt can access csrs as long as we are not stepping + assign allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f; + + + // hold debug_halt_req_ns high until we enter debug halt + assign debug_halt_req_ns = enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted); + + assign dbg_tlu_halted = (debug_halt_req_f & core_empty & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f); + + assign resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f & dbg_run_state_ns); + + assign dcsr_single_step_done = dec_tlu_i0_valid_r & ~dec_tlu_dbg_halted & dcsr[DCSR_STEP] & ~rfpc_i0_r; + + assign dcsr_single_step_running = (debug_resume_req_f & dcsr[DCSR_STEP]) | (dcsr_single_step_running_f & ~dcsr_single_step_done_f); + + assign dbg_cmd_done_ns = dec_tlu_i0_valid_r & dec_tlu_dbg_halted; + + // used to hold off commits after an in-pipe debug mode request (triggers, DCSR) + assign request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~dec_tlu_flush_lower_wb); + + assign request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f; + + rvdffie #(18) halt_ff (.*, .clk(free_l2clk), + .din({dec_tlu_flush_noredir_r, halt_taken, lsu_idle_any, ifu_miss_state_idle, dbg_tlu_halted, + resume_ack_ns, debug_halt_req_ns, debug_resume_req, trigger_hit_dmode_r, + dcsr_single_step_done, debug_halt_req, dec_tlu_wr_pause_r, dec_pause_state, + request_debug_mode_r, request_debug_mode_done, dcsr_single_step_running, dec_tlu_flush_pause_r, + dbg_halt_req_held_ns}), + .dout({dec_tlu_flush_noredir_r_d1, halt_taken_f, lsu_idle_any_f, ifu_miss_state_idle_f, dbg_tlu_halted_f, + dec_tlu_resume_ack , debug_halt_req_f, debug_resume_req_f_raw, trigger_hit_dmode_r_d1, + dcsr_single_step_done_f, debug_halt_req_d1, dec_tlu_wr_pause_r_d1, dec_pause_state_f, + request_debug_mode_r_d1, request_debug_mode_done_f, dcsr_single_step_running_f, dec_tlu_flush_pause_r_d1, + dbg_halt_req_held})); + + // MPC run collides with DBG halt, fix it here + assign debug_resume_req_f = debug_resume_req_f_raw & ~dbg_halt_req; + + assign dec_tlu_debug_stall = debug_halt_req_f; + assign dec_tlu_dbg_halted = dbg_tlu_halted_f; + assign dec_tlu_debug_mode = internal_dbg_halt_mode_f; + assign dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; + + // kill fetch redirection on flush if going to halt, or if there's a fence during db-halt + assign dec_tlu_flush_noredir_r = take_halt | (fence_i_r & internal_dbg_halt_mode) | dec_tlu_flush_pause_r | (i0_trigger_hit_r & trigger_hit_dmode_r) | take_ext_int_start; + + assign dec_tlu_flush_extint = take_ext_int_start; + + // 1 cycle after writing the PAUSE counter, flush with noredir to idle F1-D. + assign dec_tlu_flush_pause_r = dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r & ~take_ext_int_start; + + // detect end of pause counter and rfpc + assign pause_expired_r = ~dec_pause_state & dec_pause_state_f & ~(ext_int_ready | ce_int_ready | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | nmi_int_detected | ext_int_freeze_d1) & ~interrupt_valid_r_d1 & ~debug_halt_req_f & ~pmu_fw_halt_req_f & ~halt_taken_f; + + assign dec_tlu_flush_leak_one_r = dec_tlu_flush_lower_r & dcsr[DCSR_STEP] & (dec_tlu_resume_ack | dcsr_single_step_running) & ~dec_tlu_flush_noredir_r; + assign dec_tlu_flush_err_r = dec_tlu_flush_lower_r & (ic_perr_r | iccm_sbecc_r); + + // If DM attempts to access an illegal CSR, send cmd_fail back + assign dec_dbg_cmd_done = dbg_cmd_done_ns; + assign dec_dbg_cmd_fail = illegal_r & dec_dbg_cmd_done; + + + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + // Triggers + // +localparam MTDATA1_DMODE = 9; +localparam MTDATA1_SEL = 7; +localparam MTDATA1_ACTION = 6; +localparam MTDATA1_CHAIN = 5; +localparam MTDATA1_MATCH = 4; +localparam MTDATA1_M_ENABLED = 3; +localparam MTDATA1_EXE = 2; +localparam MTDATA1_ST = 1; +localparam MTDATA1_LD = 0; + + // Prioritize trigger hits with other exceptions. + // + // Trigger should have highest priority except: + // - trigger is an execute-data and there is an inst_access exception (lsu triggers won't fire, inst. is nop'd by decode) + // - trigger is a store-data and there is a lsu_acc_exc or lsu_ma_exc. + assign trigger_execute[3:0] = {mtdata1_t3[MTDATA1_EXE], mtdata1_t2[MTDATA1_EXE], mtdata1_t1[MTDATA1_EXE], mtdata1_t0[MTDATA1_EXE]}; + assign trigger_data[3:0] = {mtdata1_t3[MTDATA1_SEL], mtdata1_t2[MTDATA1_SEL], mtdata1_t1[MTDATA1_SEL], mtdata1_t0[MTDATA1_SEL]}; + assign trigger_store[3:0] = {mtdata1_t3[MTDATA1_ST], mtdata1_t2[MTDATA1_ST], mtdata1_t1[MTDATA1_ST], mtdata1_t0[MTDATA1_ST]}; + + // MSTATUS[MIE] needs to be on to take triggers unless the action is trigger to debug mode. + assign trigger_enabled[3:0] = {(mtdata1_t3[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t3[MTDATA1_M_ENABLED], + (mtdata1_t2[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t2[MTDATA1_M_ENABLED], + (mtdata1_t1[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t1[MTDATA1_M_ENABLED], + (mtdata1_t0[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t0[MTDATA1_M_ENABLED]}; + + // iside exceptions are always in i0 + assign i0_iside_trigger_has_pri_r[3:0] = ~( (trigger_execute[3:0] & trigger_data[3:0] & {4{inst_acc_r_raw}}) | // exe-data with inst_acc + ({4{exu_i0_br_error_r | exu_i0_br_start_error_r}})); // branch error in i0 + + // lsu excs have to line up with their respective triggers since the lsu op can be i0 + assign i0_lsu_trigger_has_pri_r[3:0] = ~(trigger_store[3:0] & trigger_data[3:0] & {4{lsu_i0_exc_r_raw}}); + + // trigger hits have to be eval'd to cancel side effect lsu ops even though the pipe is already frozen + assign i0_trigger_eval_r = dec_tlu_i0_valid_r; + + assign i0trigger_qual_r[3:0] = {4{i0_trigger_eval_r}} & dec_tlu_packet_r.i0trigger[3:0] & i0_iside_trigger_has_pri_r[3:0] & i0_lsu_trigger_has_pri_r[3:0] & trigger_enabled[3:0]; + + // Qual trigger hits + assign i0_trigger_r[3:0] = ~{4{dec_tlu_flush_lower_wb | dec_tlu_dbg_halted}} & i0trigger_qual_r[3:0]; + + // chaining can mask raw trigger info + assign i0_trigger_chain_masked_r[3:0] = {i0_trigger_r[3] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[2]), + i0_trigger_r[2] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[3]), + i0_trigger_r[1] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[0]), + i0_trigger_r[0] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[1])}; + + // This is the highest priority by this point. + assign i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r[3:0]; + + assign i0_trigger_hit_r = i0_trigger_hit_raw_r; + + // Actions include breakpoint, or dmode. Dmode is only possible if the DMODE bit is set. + // Otherwise, take a breakpoint. + assign trigger_action[3:0] = {mtdata1_t3[MTDATA1_ACTION] & mtdata1_t3[MTDATA1_DMODE], + mtdata1_t2[MTDATA1_ACTION] & mtdata1_t2[MTDATA1_DMODE] & ~mtdata1_t2[MTDATA1_CHAIN], + mtdata1_t1[MTDATA1_ACTION] & mtdata1_t1[MTDATA1_DMODE], + mtdata1_t0[MTDATA1_ACTION] & mtdata1_t0[MTDATA1_DMODE] & ~mtdata1_t0[MTDATA1_CHAIN]}; + + // this is needed to set the HIT bit in the triggers + assign update_hit_bit_r[3:0] = ({4{|i0_trigger_r[3:0] & ~rfpc_i0_r}} & {i0_trigger_chain_masked_r[3], i0_trigger_r[2], i0_trigger_chain_masked_r[1], i0_trigger_r[0]}); + + // action, 1 means dmode. Simultaneous triggers with at least 1 set for dmode force entire action to dmode. + assign i0_trigger_action_r = |(i0_trigger_chain_masked_r[3:0] & trigger_action[3:0]); + + assign trigger_hit_dmode_r = (i0_trigger_hit_r & i0_trigger_action_r); + + assign mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r; + + +// +// Debug end +//-------------------------------------------------------------------------------- + + //---------------------------------------------------------------------- + // + // Commit + // + //---------------------------------------------------------------------- + + + + //-------------------------------------------------------------------------------- + // External halt (not debug halt) + // - Fully interlocked handshake + // i_cpu_halt_req ____|--------------|_______________ + // core_empty ---------------|___________ + // o_cpu_halt_ack _________________|----|__________ + // o_cpu_halt_status _______________|---------------------|_________ + // i_cpu_run_req ______|----------|____ + // o_cpu_run_ack ____________|------|________ + // + + + // debug mode has priority, ignore PMU/FW halt/run while in debug mode + assign i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~dec_tlu_debug_mode & ~ext_int_freeze_d1; + assign i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1; + + rvdffie #(10) exthaltff (.*, .clk(free_l2clk), .din({i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, cpu_halt_status, + cpu_halt_ack, cpu_run_ack, internal_pmu_fw_halt_mode, + pmu_fw_halt_req_ns, pmu_fw_tlu_halted, + int_timer0_int_hold, int_timer1_int_hold}), + .dout({i_cpu_halt_req_d1, i_cpu_run_req_d1_raw, o_cpu_halt_status, + o_cpu_halt_ack, o_cpu_run_ack, internal_pmu_fw_halt_mode_f, + pmu_fw_halt_req_f, pmu_fw_tlu_halted_f, + int_timer0_int_hold_f, int_timer1_int_hold_f})); + + // only happens if we aren't in dgb_halt + assign ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1; + + assign enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; + + assign pmu_fw_halt_req_ns = (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f; + + assign internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | (internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1 & ~debug_halt_req_f); + + // debug halt has priority + assign pmu_fw_tlu_halted = ((pmu_fw_halt_req_f & core_empty & halt_taken & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f; + + assign cpu_halt_ack = (i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f) | (o_cpu_halt_ack & i_cpu_halt_req_sync); + assign cpu_halt_status = (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | (o_cpu_halt_status & ~i_cpu_run_req_d1 & ~internal_dbg_halt_mode_f); + assign cpu_run_ack = (~pmu_fw_tlu_halted_f & i_cpu_run_req_sync) | (o_cpu_halt_status & i_cpu_run_req_d1_raw) | (o_cpu_run_ack & i_cpu_run_req_sync); + assign debug_mode_status = internal_dbg_halt_mode_f; + assign o_debug_mode_status = debug_mode_status; + +`ifdef RV_ASSERT_ON + assert_commit_while_halted: assert #0 (~(tlu_i0_commit_cmt & o_cpu_halt_status)) else $display("ERROR: Commiting while cpu_halt_status asserted!"); + assert_flush_while_fastint: assert #0 (~((take_ext_int_start_d1 | take_ext_int_start_d2) & dec_tlu_flush_lower_r)) else $display("ERROR: TLU Flushing inside fast interrupt procedure!"); +`endif + + // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts + assign i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (mhwakeup & mhwakeup_ready)) & o_cpu_halt_status & ~i_cpu_halt_req_d1); + + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + + assign lsu_single_ecc_error_r = lsu_single_ecc_error_incr; + + assign lsu_error_pkt_addr_r[31:0] = lsu_error_pkt_r.addr[31:0]; + + + assign lsu_exc_valid_r_raw = lsu_error_pkt_r.exc_valid & ~dec_tlu_flush_lower_wb; + + assign lsu_i0_exc_r_raw = lsu_error_pkt_r.exc_valid; + + assign lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r; + + assign lsu_exc_valid_r = lsu_i0_exc_r; + + assign lsu_exc_ma_r = lsu_i0_exc_r & ~lsu_error_pkt_r.exc_type; + assign lsu_exc_acc_r = lsu_i0_exc_r & lsu_error_pkt_r.exc_type; + assign lsu_exc_st_r = lsu_i0_exc_r & lsu_error_pkt_r.inst_type; + + // Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR. + // LSU turns the load into a store and patches the data in the DCCM + assign lsu_i0_rfnpc_r = dec_tlu_i0_valid_r & ~i0_trigger_hit_r & + (~lsu_error_pkt_r.inst_type & lsu_error_pkt_r.single_ecc_error); + + // Final commit valids + assign tlu_i0_commit_cmt = dec_tlu_i0_valid_r & + ~rfpc_i0_r & + ~lsu_i0_exc_r & + ~inst_acc_r & + ~dec_tlu_dbg_halted & + ~request_debug_mode_r_d1 & + ~i0_trigger_hit_r; + + // unified place to manage the killing of arch state writebacks + assign tlu_i0_kill_writeb_r = rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & dec_tlu_dbg_halted) | i0_trigger_hit_r; + assign dec_tlu_i0_commit_cmt = tlu_i0_commit_cmt; + + + // refetch PC, microarch flush + // ic errors only in pipe0 + assign rfpc_i0_r = ((dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (exu_i0_br_error_r | exu_i0_br_start_error_r)) | // inst commit with rfpc + ((ic_perr_r | iccm_sbecc_r) & ~ext_int_freeze_d1)) & // ic/iccm without inst commit + ~i0_trigger_hit_r & // unless there's a trigger. Err signal to ic/iccm will assert anyway to clear the error. + ~lsu_i0_rfnpc_r; + + // From the indication of a iccm single bit error until the first commit or flush, maintain a repair state. In the repair state, rfnpc i0 commits. + assign iccm_repair_state_ns = iccm_sbecc_r | (iccm_repair_state_d1 & ~dec_tlu_flush_lower_r); + + + localparam MCPC = 12'h7c2; + + // this is a flush of last resort, meaning only assert it if there is no other flush happening. + assign iccm_repair_state_rfnpc = tlu_i0_commit_cmt & iccm_repair_state_d1 & + ~(ebreak_r | ecall_r | mret_r | take_reset | illegal_r | (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC))); + +if(pt.BTB_ENABLE==1) begin + // go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush + assign dec_tlu_br0_error_r = exu_i0_br_error_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1; + assign dec_tlu_br0_start_error_r = exu_i0_br_start_error_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1; + assign dec_tlu_br0_v_r = exu_i0_br_valid_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~exu_i0_br_mp_r | ~exu_pmu_i0_br_ataken); + + + assign dec_tlu_br0_r_pkt.hist[1:0] = exu_i0_br_hist_r[1:0]; + assign dec_tlu_br0_r_pkt.br_error = dec_tlu_br0_error_r; + assign dec_tlu_br0_r_pkt.br_start_error = dec_tlu_br0_start_error_r; + assign dec_tlu_br0_r_pkt.valid = dec_tlu_br0_v_r; + assign dec_tlu_br0_r_pkt.way = exu_i0_br_way_r; + assign dec_tlu_br0_r_pkt.middle = exu_i0_br_middle_r; +end // if (pt.BTB_ENABLE==1) +else begin + assign dec_tlu_br0_error_r = '0; + assign dec_tlu_br0_start_error_r = '0; + assign dec_tlu_br0_v_r = '0; + assign dec_tlu_br0_r_pkt = '0; +end // else: !if(pt.BTB_ENABLE==1) + + + // only expect these in pipe 0 + assign ebreak_r = (dec_tlu_packet_r.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr[DCSR_EBREAKM] & ~rfpc_i0_r; + assign ecall_r = (dec_tlu_packet_r.pmu_i0_itype == ECALL) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; + assign illegal_r = ~dec_tlu_packet_r.legal & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; + assign mret_r = (dec_tlu_packet_r.pmu_i0_itype == MRET) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r; + // fence_i includes debug only fence_i's + assign fence_i_r = (dec_tlu_packet_r.fence_i & dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r; + assign ic_perr_r = ifu_ic_error_start_f & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f; + assign iccm_sbecc_r = ifu_iccm_rd_ecc_single_err_f & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f; + assign inst_acc_r_raw = dec_tlu_packet_r.icaf & dec_tlu_i0_valid_r; + assign inst_acc_r = inst_acc_r_raw & ~rfpc_i0_r & ~i0_trigger_hit_r; + assign inst_acc_second_r = dec_tlu_packet_r.icaf_second; + + assign ebreak_to_debug_mode_r = (dec_tlu_packet_r.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & dcsr[DCSR_EBREAKM] & ~rfpc_i0_r; + + rvdff #(1) exctype_wb_ff (.*, .clk(e4e5_clk), + .din (ebreak_to_debug_mode_r ), + .dout(ebreak_to_debug_mode_r_d1)); + + assign dec_tlu_fence_i_r = fence_i_r; + // + // Exceptions + // + // - MEPC <- PC + // - PC <- MTVEC, assert flush_lower + // - MCAUSE <- cause + // - MSCAUSE <- secondary cause + // - MTVAL <- + // - MPIE <- MIE + // - MIE <- 0 + // + assign i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r) & ~rfpc_i0_r & ~dec_tlu_dbg_halted; + + // Cause: + // + // 0x2 : illegal + // 0x3 : breakpoint + // 0xb : Environment call M-mode + + + assign exc_cause_r[4:0] = ( ({5{take_ext_int}} & 5'h0b) | + ({5{take_timer_int}} & 5'h07) | + ({5{take_soft_int}} & 5'h03) | + ({5{take_int_timer0_int}} & 5'h1d) | + ({5{take_int_timer1_int}} & 5'h1c) | + ({5{take_ce_int}} & 5'h1e) | + ({5{illegal_r}} & 5'h02) | + ({5{ecall_r}} & 5'h0b) | + ({5{inst_acc_r}} & 5'h01) | + ({5{ebreak_r | i0_trigger_hit_r}} & 5'h03) | + ({5{lsu_exc_ma_r & ~lsu_exc_st_r}} & 5'h04) | + ({5{lsu_exc_acc_r & ~lsu_exc_st_r}} & 5'h05) | + ({5{lsu_exc_ma_r & lsu_exc_st_r}} & 5'h06) | + ({5{lsu_exc_acc_r & lsu_exc_st_r}} & 5'h07) + ) & ~{5{take_nmi}}; + + // + // Interrupts + // + // exceptions that are committed have already happened and will cause an int at E4 to wait a cycle + // or more if MSTATUS[MIE] is cleared. + // + // -in priority order, highest to lowest + // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met. + // Hold off externals for a cycle to make sure we are consistent with what was just written + assign mhwakeup_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MEIP] & mie_ns[MIE_MEIE]; + assign ext_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MEIP] & mie_ns[MIE_MEIE] & ~ignore_ext_int_due_to_lsu_stall; + assign ce_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MCEIP] & mie_ns[MIE_MCEIE]; + assign soft_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MSIP] & mie_ns[MIE_MSIE]; + assign timer_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MTIP] & mie_ns[MIE_MTIE]; + + // MIP for internal timers pulses for 1 clock, resets the timer counter. Mip won't hold past the various stall conditions. + assign int_timer0_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE0]; + assign int_timer0_int_ready = mip[MIP_MITIP0] & int_timer0_int_possible; + assign int_timer1_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE1]; + assign int_timer1_int_ready = mip[MIP_MITIP1] & int_timer1_int_possible; + + // Internal timers pulse and reset. If core is PMU/FW halted, the pulse will cause an exit from halt, but won't stick around + // Make it sticky, also for 1 cycle stall conditions. + assign int_timer_stalled = dec_csr_stall_int_ff | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r; + + assign int_timer0_int_hold = (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer0_int_possible & int_timer0_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f); + assign int_timer1_int_hold = (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer1_int_possible & int_timer1_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f); + + + assign internal_dbg_halt_timers = internal_dbg_halt_mode_f & ~dcsr_single_step_running; + + + assign block_interrupts = ( (internal_dbg_halt_mode & (~dcsr_single_step_running | dec_tlu_i0_valid_r)) | // No ints in db-halt unless we are single stepping + internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 |// No ints in PMU/FW halt. First we exit halt + take_nmi | // NMI is top priority + ebreak_to_debug_mode_r | // Heading to debug mode, hold off ints + synchronous_flush_r | // exception flush this cycle + exc_or_int_valid_r_d1 | // ext/int past cycle (need time for MIE to update) + mret_r | // mret in progress, for cases were ISR enables ints before mret + ext_int_freeze_d1 // Fast interrupt in progress (optional) + ); + + +if (pt.FAST_INTERRUPT_REDIRECT) begin + + + assign take_ext_int_start = ext_int_ready & ~block_interrupts; + + assign ext_int_freeze = take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3; + assign take_ext_int = take_ext_int_start_d3 & ~|lsu_fir_error[1:0]; + assign fast_int_meicpct = csr_meicpct & dec_csr_any_unq_d; // MEICPCT becomes illegal if fast ints are enabled + + assign ignore_ext_int_due_to_lsu_stall = lsu_fastint_stall_any; +end +else begin + assign take_ext_int_start = 1'b0; + assign ext_int_freeze = 1'b0; + assign ext_int_freeze_d1 = 1'b0; + assign take_ext_int_start_d1 = 1'b0; + assign take_ext_int_start_d2 = 1'b0; + assign take_ext_int_start_d3 = 1'b0; + assign fast_int_meicpct = 1'b0; + assign ignore_ext_int_due_to_lsu_stall = 1'b0; + + assign take_ext_int = ext_int_ready & ~block_interrupts; +end + + assign take_ce_int = ce_int_ready & ~ext_int_ready & ~block_interrupts; + assign take_soft_int = soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts; + assign take_timer_int = timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts; + assign take_int_timer0_int = (int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible & ~dec_csr_stall_int_ff & + ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts; + assign take_int_timer1_int = (int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible & ~dec_csr_stall_int_ff & + ~(int_timer0_int_ready | int_timer0_int_hold_f) & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts; + + assign take_reset = reset_delayed & mpc_reset_run_req; + assign take_nmi = nmi_int_detected & ~internal_pmu_fw_halt_mode & (~internal_dbg_halt_mode | (dcsr_single_step_running_f & dcsr[DCSR_STEPIE] & ~dec_tlu_i0_valid_r & ~dcsr_single_step_done_f)) & + ~synchronous_flush_r & ~mret_r & ~take_reset & ~ebreak_to_debug_mode_r & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & |lsu_fir_error[1:0])); + + assign interrupt_valid_r = take_ext_int | take_timer_int | take_soft_int | take_nmi | take_ce_int | take_int_timer0_int | take_int_timer1_int; + + + // Compute interrupt path: + // If vectored async is set in mtvec, flush path for interrupts is MTVEC + (4 * CAUSE); + assign vectored_path[31:1] = {mtvec[30:1], 1'b0} + {25'b0, exc_cause_r[4:0], 1'b0}; + assign interrupt_path[31:1] = take_nmi ? nmi_vec[31:1] : ((mtvec[0] == 1'b1) ? vectored_path[31:1] : {mtvec[30:1], 1'b0}); + + assign sel_npc_r = lsu_i0_rfnpc_r | fence_i_r | iccm_repair_state_rfnpc | (i_cpu_run_req_d1 & ~interrupt_valid_r) | (rfpc_i0_r & ~dec_tlu_i0_valid_r); + assign sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r; + + assign sel_fir_addr = take_ext_int_start_d3 & ~|lsu_fir_error[1:0]; + + assign synchronous_flush_r = i0_exception_valid_r | // exception + rfpc_i0_r | // rfpc + lsu_exc_valid_r | // lsu exception in either pipe 0 or pipe 1 + fence_i_r | // fence, a rfnpc + lsu_i0_rfnpc_r | // lsu dccm sb ecc + iccm_repair_state_rfnpc | // Iccm sb ecc + debug_resume_req_f | // resume from debug halt, fetch the dpc + sel_npc_resume | // resume from pmu/fw halt, or from pause and fetch the NPC + dec_tlu_wr_pause_r_d1 | // flush at start of pause + i0_trigger_hit_r; // trigger hit, ebreak or goto debug mode + + assign tlu_flush_lower_r = interrupt_valid_r | mret_r | synchronous_flush_r | take_halt | take_reset | take_ext_int_start; + + assign tlu_flush_path_r[31:1] = take_reset ? rst_vec[31:1] : + + ( ({31{sel_fir_addr}} & lsu_fir_addr[31:1]) | + ({31{~take_nmi & sel_npc_r}} & npc_r[31:1]) | + ({31{~take_nmi & rfpc_i0_r & dec_tlu_i0_valid_r & ~sel_npc_r}} & dec_tlu_i0_pc_r[31:1]) | + ({31{interrupt_valid_r & ~sel_fir_addr}} & interrupt_path[31:1]) | + ({31{(i0_exception_valid_r | lsu_exc_valid_r | + (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r & ~sel_fir_addr}} & {mtvec[30:1],1'b0}) | + ({31{~take_nmi & mret_r}} & mepc[31:1]) | + ({31{~take_nmi & debug_resume_req_f}} & dpc[31:1]) | + ({31{~take_nmi & sel_npc_resume}} & npc_r_d1[31:1]) ); + + rvdffpcie #(31) flush_lower_ff (.*, .en(tlu_flush_lower_r), + .din({tlu_flush_path_r[31:1]}), + .dout({tlu_flush_path_r_d1[31:1]})); + + assign dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; + assign dec_tlu_flush_lower_r = tlu_flush_lower_r; + assign dec_tlu_flush_path_r[31:1] = tlu_flush_path_r[31:1]; + + + // this is used to capture mepc, etc. + assign exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r); + + + rvdffie #(12) excinfo_wb_ff (.*, + .din({interrupt_valid_r, i0_exception_valid_r, exc_or_int_valid_r, + exc_cause_r[4:0], tlu_i0_commit_cmt & ~illegal_r, i0_trigger_hit_r, + take_nmi, pause_expired_r }), + .dout({interrupt_valid_r_d1, i0_exception_valid_r_d1, exc_or_int_valid_r_d1, + exc_cause_wb[4:0], i0_valid_wb, trigger_hit_r_d1, + take_nmi_r_d1, pause_expired_wb})); + + //---------------------------------------------------------------------- + // + // CSRs + // + //---------------------------------------------------------------------- + + + // ---------------------------------------------------------------------- + // MISA (RO) + // [31:30] XLEN - implementation width, 2'b01 - 32 bits + // [12] M - integer mul/div + // [8] I - RV32I + // [2] C - Compressed extension + localparam MISA = 12'h301; + + // MVENDORID, MARCHID, MIMPID, MHARTID + localparam MVENDORID = 12'hf11; + localparam MARCHID = 12'hf12; + localparam MIMPID = 12'hf13; + localparam MHARTID = 12'hf14; + + + // ---------------------------------------------------------------------- + // MSTATUS (RW) + // [12:11] MPP : Prior priv level, always 2'b11, not flopped + // [7] MPIE : Int enable previous [1] + // [3] MIE : Int enable [0] + localparam MSTATUS = 12'h300; + + + //When executing a MRET instruction, supposing MPP holds the value 3, MIE + //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3 + + assign dec_csr_wen_r_mod = dec_csr_wen_r & ~i0_trigger_hit_r & ~rfpc_i0_r; + assign wr_mstatus_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSTATUS); + + // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ... + assign set_mie_pmu_fw_halt = ~mpmc_b_ns[1] & fw_halt_req; + + assign mstatus_ns[1:0] = ( ({2{~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MIE], 1'b0}) | + ({2{ wr_mstatus_r & exc_or_int_valid_r}} & {dec_csr_wrdata_r[3], 1'b0}) | + ({2{mret_r & ~exc_or_int_valid_r}} & {1'b1, mstatus[1]}) | + ({2{set_mie_pmu_fw_halt}} & {mstatus[1], 1'b1}) | + ({2{wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]}) | + ({2{~wr_mstatus_r & ~exc_or_int_valid_r & ~mret_r & ~set_mie_pmu_fw_halt}} & mstatus[1:0]) ); + + // gate MIE if we are single stepping and DCSR[STEPIE] is off + assign mstatus_mie_ns = mstatus[MSTATUS_MIE] & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]); + + // ---------------------------------------------------------------------- + // MTVEC (RW) + // [31:2] BASE : Trap vector base address + // [1] - Reserved, not implemented, reads zero + // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE) + localparam MTVEC = 12'h305; + + assign wr_mtvec_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVEC); + assign mtvec_ns[30:0] = {dec_csr_wrdata_r[31:2], dec_csr_wrdata_r[0]} ; + rvdffe #(31) mtvec_ff (.*, .en(wr_mtvec_r), .din(mtvec_ns[30:0]), .dout(mtvec[30:0])); + + // ---------------------------------------------------------------------- + // MIP (RW) + // + // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending + // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending + // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending + // [11] MEIP : (RO) M-Mode external interrupt pending + // [7] MTIP : (RO) M-Mode timer interrupt pending + // [3] MSIP : (RO) M-Mode software interrupt pending + localparam MIP = 12'h344; + + assign ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req); + + assign mip_ns[5:0] = {ce_int, dec_timer_t0_pulse, dec_timer_t1_pulse, mexintpend, timer_int_sync, soft_int_sync}; + + // ---------------------------------------------------------------------- + // MIE (RW) + // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable + // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable + // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable + // [11] MEIE : (RW) M-Mode external interrupt enable + // [7] MTIE : (RW) M-Mode timer interrupt enable + // [3] MSIE : (RW) M-Mode software interrupt enable + localparam MIE = 12'h304; + + assign wr_mie_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MIE); + assign mie_ns[5:0] = wr_mie_r ? {dec_csr_wrdata_r[30:28], dec_csr_wrdata_r[11], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]} : mie[5:0]; + rvdff #(6) mie_ff (.*, .clk(csr_wr_clk), .din(mie_ns[5:0]), .dout(mie[5:0])); + + + // ---------------------------------------------------------------------- + // MCYCLEL (RW) + // [31:0] : Lower Cycle count + + localparam MCYCLEL = 12'hb00; + + assign kill_ebreak_count_r = ebreak_to_debug_mode_r & dcsr[DCSR_STOPC]; + + assign wr_mcyclel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEL); + + assign mcyclel_cout_in = ~(kill_ebreak_count_r | (dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted | mcountinhibit[0]); + + // split for power + assign {mcyclela_cout, mcyclel_inc[7:0]} = mcyclel[7:0] + {7'b0, 1'b1}; + assign {mcyclel_cout, mcyclel_inc[31:8]} = mcyclel[31:8] + {23'b0, mcyclela_cout}; + + assign mcyclel_ns[31:0] = wr_mcyclel_r ? dec_csr_wrdata_r[31:0] : mcyclel_inc[31:0]; + + rvdffe #(24) mcyclel_bff (.*, .clk(free_l2clk), .en(wr_mcyclel_r | (mcyclela_cout & mcyclel_cout_in)), .din(mcyclel_ns[31:8]), .dout(mcyclel[31:8])); + rvdffe #(8) mcyclel_aff (.*, .clk(free_l2clk), .en(wr_mcyclel_r | mcyclel_cout_in), .din(mcyclel_ns[7:0]), .dout(mcyclel[7:0])); + + // ---------------------------------------------------------------------- + // MCYCLEH (RW) + // [63:32] : Higher Cycle count + // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored. + + localparam MCYCLEH = 12'hb80; + + assign wr_mcycleh_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEH); + + assign mcycleh_inc[31:0] = mcycleh[31:0] + {31'b0, mcyclel_cout_f}; + assign mcycleh_ns[31:0] = wr_mcycleh_r ? dec_csr_wrdata_r[31:0] : mcycleh_inc[31:0]; + + rvdffe #(32) mcycleh_ff (.*, .clk(free_l2clk), .en(wr_mcycleh_r | mcyclel_cout_f), .din(mcycleh_ns[31:0]), .dout(mcycleh[31:0])); + + // ---------------------------------------------------------------------- + // MINSTRETL (RW) + // [31:0] : Lower Instruction retired count + // From the spec "Some CSRs, such as the instructions retired counter, instret, may be modified as side effects + // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the + // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the + // update occurs after the execution of the instruction. In particular, a value written to instret by + // one instruction will be the value read by the following instruction (i.e., the increment of instret + // caused by the first instruction retiring happens before the write of the new value)." + localparam MINSTRETL = 12'hb02; + + assign i0_valid_no_ebreak_ecall_r = dec_tlu_i0_valid_r & ~(ebreak_r | ecall_r | ebreak_to_debug_mode_r | illegal_r | mcountinhibit[2]); + + assign wr_minstretl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETL); + + assign {minstretl_couta, minstretl_inc[7:0]} = minstretl[7:0] + {7'b0,1'b1}; + assign {minstretl_cout, minstretl_inc[31:8]} = minstretl[31:8] + {23'b0, minstretl_couta}; + + assign minstret_enable = (i0_valid_no_ebreak_ecall_r & tlu_i0_commit_cmt) | wr_minstretl_r; + + assign minstretl_cout_ns = minstretl_cout & ~wr_minstreth_r & i0_valid_no_ebreak_ecall_r & ~dec_tlu_dbg_halted; + + assign minstretl_ns[31:0] = wr_minstretl_r ? dec_csr_wrdata_r[31:0] : minstretl_inc[31:0]; + rvdffe #(24) minstretl_bff (.*, .en(wr_minstretl_r | (minstretl_couta & minstret_enable)), + .din(minstretl_ns[31:8]), .dout(minstretl[31:8])); + rvdffe #(8) minstretl_aff (.*, .en(minstret_enable), + .din(minstretl_ns[7:0]), .dout(minstretl[7:0])); + + + assign minstretl_read[31:0] = minstretl[31:0]; + // ---------------------------------------------------------------------- + // MINSTRETH (RW) + // [63:32] : Higher Instret count + // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored. + + localparam MINSTRETH = 12'hb82; + + assign wr_minstreth_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETH); + + assign minstreth_inc[31:0] = minstreth[31:0] + {31'b0, minstretl_cout_f}; + assign minstreth_ns[31:0] = wr_minstreth_r ? dec_csr_wrdata_r[31:0] : minstreth_inc[31:0]; + rvdffe #(32) minstreth_ff (.*, .en((minstret_enable_f & minstretl_cout_f) | wr_minstreth_r), .din(minstreth_ns[31:0]), .dout(minstreth[31:0])); + + assign minstreth_read[31:0] = minstreth_inc[31:0]; + + // ---------------------------------------------------------------------- + // MSCRATCH (RW) + // [31:0] : Scratch register + localparam MSCRATCH = 12'h340; + + assign wr_mscratch_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCRATCH); + + rvdffe #(32) mscratch_ff (.*, .en(wr_mscratch_r), .din(dec_csr_wrdata_r[31:0]), .dout(mscratch[31:0])); + + // ---------------------------------------------------------------------- + // MEPC (RW) + // [31:1] : Exception PC + localparam MEPC = 12'h341; + + // NPC + + assign sel_exu_npc_r = ~dec_tlu_dbg_halted & ~tlu_flush_lower_r_d1 & dec_tlu_i0_valid_r; + assign sel_flush_npc_r = ~dec_tlu_dbg_halted & tlu_flush_lower_r_d1 & ~dec_tlu_flush_noredir_r_d1; + assign sel_hold_npc_r = ~sel_exu_npc_r & ~sel_flush_npc_r; + + assign npc_r[31:1] = ( ({31{sel_exu_npc_r}} & exu_npc_r[31:1]) | + ({31{~mpc_reset_run_req & reset_delayed}} & rst_vec[31:1]) | // init to reset vector for mpc halt on reset case + ({31{(sel_flush_npc_r)}} & tlu_flush_path_r_d1[31:1]) | + ({31{(sel_hold_npc_r)}} & npc_r_d1[31:1]) ); + + rvdffpcie #(31) npwbc_ff (.*, .en(sel_exu_npc_r | sel_flush_npc_r | reset_delayed), .din(npc_r[31:1]), .dout(npc_r_d1[31:1])); + + // PC has to be captured for exceptions and interrupts. For MRET, we could execute it and then take an + // interrupt before the next instruction. + assign pc0_valid_r = ~dec_tlu_dbg_halted & dec_tlu_i0_valid_r; + + assign pc_r[31:1] = ( ({31{ pc0_valid_r}} & dec_tlu_i0_pc_r[31:1]) | + ({31{~pc0_valid_r}} & pc_r_d1[31:1])); + + rvdffpcie #(31) pwbc_ff (.*, .en(pc0_valid_r), .din(pc_r[31:1]), .dout(pc_r_d1[31:1])); + + assign wr_mepc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEPC); + + assign mepc_ns[31:1] = ( ({31{i0_exception_valid_r | lsu_exc_valid_r | mepc_trigger_hit_sel_pc_r}} & pc_r[31:1]) | + ({31{interrupt_valid_r}} & npc_r[31:1]) | + ({31{wr_mepc_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:1]) | + ({31{~wr_mepc_r & ~exc_or_int_valid_r}} & mepc[31:1]) ); + + + rvdffe #(31) mepc_ff (.*, .en(i0_exception_valid_r | lsu_exc_valid_r | mepc_trigger_hit_sel_pc_r | interrupt_valid_r | wr_mepc_r), .din(mepc_ns[31:1]), .dout(mepc[31:1])); + + // ---------------------------------------------------------------------- + // MCAUSE (RW) + // [31:0] : Exception Cause + localparam MCAUSE = 12'h342; + + assign wr_mcause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCAUSE); + assign mcause_sel_nmi_store = exc_or_int_valid_r & take_nmi & nmi_lsu_store_type; + assign mcause_sel_nmi_load = exc_or_int_valid_r & take_nmi & nmi_lsu_load_type; + assign mcause_sel_nmi_ext = exc_or_int_valid_r & take_nmi & take_ext_int_start_d3 & |lsu_fir_error[1:0] & ~nmi_int_detected_f; + // FIR value decoder + // 0 –no error + // 1 –uncorrectable ecc => f000_1000 + // 2 –dccm region access error => f000_1001 + // 3 –non dccm region access error => f000_1002 + assign mcause_fir_error_type[1:0] = {&lsu_fir_error[1:0], lsu_fir_error[1] & ~lsu_fir_error[0]}; + + assign mcause_ns[31:0] = ( ({32{mcause_sel_nmi_store}} & {32'hf000_0000}) | + ({32{mcause_sel_nmi_load}} & {32'hf000_0001}) | + ({32{mcause_sel_nmi_ext}} & {28'hf000_100, 2'b0, mcause_fir_error_type[1:0]}) | + ({32{exc_or_int_valid_r & ~take_nmi}} & {interrupt_valid_r, 26'b0, exc_cause_r[4:0]}) | + ({32{wr_mcause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:0]) | + ({32{~wr_mcause_r & ~exc_or_int_valid_r}} & mcause[31:0]) ); + + rvdffe #(32) mcause_ff (.*, .en(exc_or_int_valid_r | wr_mcause_r), .din(mcause_ns[31:0]), .dout(mcause[31:0])); + // ---------------------------------------------------------------------- + // MSCAUSE (RW) + // [2:0] : Secondary exception Cause + localparam MSCAUSE = 12'h7ff; + + assign wr_mscause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCAUSE); + + assign ifu_mscause[3:0] = (dec_tlu_packet_r.icaf_type[1:0] == 2'b00) ? 4'b1001 : + {2'b00 , dec_tlu_packet_r.icaf_type[1:0]} ; + + assign mscause_type[3:0] = ( ({4{lsu_i0_exc_r}} & lsu_error_pkt_r.mscause[3:0]) | + ({4{i0_trigger_hit_r}} & 4'b0001) | + ({4{ebreak_r}} & 4'b0010) | + ({4{inst_acc_r}} & ifu_mscause[3:0]) + ); + + assign mscause_ns[3:0] = ( ({4{exc_or_int_valid_r}} & mscause_type[3:0]) | + ({4{ wr_mscause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[3:0]) | + ({4{~wr_mscause_r & ~exc_or_int_valid_r}} & mscause[3:0]) + ); + + rvdff #(4) mscause_ff (.*, .clk(e4e5_int_clk), .din(mscause_ns[3:0]), .dout(mscause[3:0])); + // ---------------------------------------------------------------------- + // MTVAL (RW) + // [31:0] : Exception address if relevant + localparam MTVAL = 12'h343; + + assign wr_mtval_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVAL); + assign mtval_capture_pc_r = exc_or_int_valid_r & (ebreak_r | (inst_acc_r & ~inst_acc_second_r) | mepc_trigger_hit_sel_pc_r) & ~take_nmi; + assign mtval_capture_pc_plus2_r = exc_or_int_valid_r & (inst_acc_r & inst_acc_second_r) & ~take_nmi; + assign mtval_capture_inst_r = exc_or_int_valid_r & illegal_r & ~take_nmi; + assign mtval_capture_lsu_r = exc_or_int_valid_r & lsu_exc_valid_r & ~take_nmi; + assign mtval_clear_r = exc_or_int_valid_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_capture_lsu_r & ~mepc_trigger_hit_sel_pc_r; + + + assign mtval_ns[31:0] = (({32{mtval_capture_pc_r}} & {pc_r[31:1], 1'b0}) | + ({32{mtval_capture_pc_plus2_r}} & {pc_r[31:1] + 31'b1, 1'b0}) | + ({32{mtval_capture_inst_r}} & dec_illegal_inst[31:0]) | + ({32{mtval_capture_lsu_r}} & lsu_error_pkt_addr_r[31:0]) | + ({32{wr_mtval_r & ~interrupt_valid_r}} & dec_csr_wrdata_r[31:0]) | + ({32{~take_nmi & ~wr_mtval_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_clear_r & ~mtval_capture_lsu_r}} & mtval[31:0]) ); + + + rvdffe #(32) mtval_ff (.*, .en(tlu_flush_lower_r | wr_mtval_r), .din(mtval_ns[31:0]), .dout(mtval[31:0])); + + // ---------------------------------------------------------------------- + // MCGC (RW) Clock gating control + // [31:10]: Reserved, reads 0x0 + // [9] : picio_clk_override + // [7] : dec_clk_override + // [6] : Unused + // [5] : ifu_clk_override + // [4] : lsu_clk_override + // [3] : bus_clk_override + // [2] : pic_clk_override + // [1] : dccm_clk_override + // [0] : icm_clk_override + // + localparam MCGC = 12'h7f8; + assign wr_mcgc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCGC); + + assign mcgc_ns[9:0] = wr_mcgc_r ? {~dec_csr_wrdata_r[9], dec_csr_wrdata_r[8:0]} : mcgc_int[9:0]; + rvdffe #(10) mcgc_ff (.*, .en(wr_mcgc_r), .din(mcgc_ns[9:0]), .dout(mcgc_int[9:0])); + + assign mcgc[9:0] = {~mcgc_int[9], mcgc_int[8:0]}; + + assign dec_tlu_picio_clk_override= mcgc[9]; + assign dec_tlu_misc_clk_override = mcgc[8]; + assign dec_tlu_dec_clk_override = mcgc[7]; + //sign dec_tlu_exu_clk_override = mcgc[6]; + assign dec_tlu_ifu_clk_override = mcgc[5]; + assign dec_tlu_lsu_clk_override = mcgc[4]; + assign dec_tlu_bus_clk_override = mcgc[3]; + assign dec_tlu_pic_clk_override = mcgc[2]; + assign dec_tlu_dccm_clk_override = mcgc[1]; + assign dec_tlu_icm_clk_override = mcgc[0]; + + // ---------------------------------------------------------------------- + // MFDC (RW) Feature Disable Control + // [31:19] : Reserved, reads 0x0 + // [18:16] : DMA QoS Prty + // [15:13] : Reserved, reads 0x0 + // [12] : Disable trace + // [11] : Disable external load forwarding + // [10] : Disable dual issue + // [9] : Disable pic multiple ints + // [8] : Disable core ecc + // [7] : Disable secondary alu?s + // [6] : Unused, 0x0 + // [5] : Disable non-blocking loads/divides + // [4] : Disable fast divide + // [3] : Disable branch prediction and return stack + // [2] : Disable write buffer coalescing + // [1] : Disable load misses that bypass the write buffer + // [0] : Disable pipelining - Enable single instruction execution + // + localparam MFDC = 12'h7f9; + + assign wr_mfdc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDC); + + rvdffe #(16) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[15:0]}), .dout(mfdc_int[15:0])); + + // flip poweron value of bit 6 for AXI build + if(pt.BUILD_AXI4==1) begin : axi4 + // flip poweron valid of bit 12 + assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12], dec_csr_wrdata_r[11:7], ~dec_csr_wrdata_r[6], dec_csr_wrdata_r[5:0]}; + assign mfdc[18:0] = {~mfdc_int[15:13], 3'b0, mfdc_int[12], mfdc_int[11:7], ~mfdc_int[6], mfdc_int[5:0]}; + end + else begin + // flip poweron valid of bit 12 + assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16],dec_csr_wrdata_r[12:0]}; + assign mfdc[18:0] = {~mfdc_int[15:13], 3'b0, mfdc_int[12:0]}; + end + + + assign dec_tlu_dma_qos_prty[2:0] = mfdc[18:16]; + assign dec_tlu_trace_disable = mfdc[12]; + assign dec_tlu_external_ldfwd_disable = mfdc[11]; + assign dec_tlu_core_ecc_disable = mfdc[8]; + assign dec_tlu_sideeffect_posted_disable = mfdc[6]; + assign dec_tlu_bpred_disable = mfdc[3]; + assign dec_tlu_wb_coalescing_disable = mfdc[2]; + assign dec_tlu_pipelining_disable = mfdc[0]; + + // ---------------------------------------------------------------------- + // MCPC (RW) Pause counter + // [31:0] : Reads 0x0, decs in the wb register in decode_ctl + + assign dec_tlu_wr_pause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC) & ~interrupt_valid_r & ~take_ext_int_start; + + // ---------------------------------------------------------------------- + // MRAC (RW) + // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs + localparam MRAC = 12'h7c0; + + assign wr_mrac_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MRAC); + + // prevent pairs of 0x11, side_effect and cacheable + assign mrac_in[31:0] = {dec_csr_wrdata_r[31], dec_csr_wrdata_r[30] & ~dec_csr_wrdata_r[31], + dec_csr_wrdata_r[29], dec_csr_wrdata_r[28] & ~dec_csr_wrdata_r[29], + dec_csr_wrdata_r[27], dec_csr_wrdata_r[26] & ~dec_csr_wrdata_r[27], + dec_csr_wrdata_r[25], dec_csr_wrdata_r[24] & ~dec_csr_wrdata_r[25], + dec_csr_wrdata_r[23], dec_csr_wrdata_r[22] & ~dec_csr_wrdata_r[23], + dec_csr_wrdata_r[21], dec_csr_wrdata_r[20] & ~dec_csr_wrdata_r[21], + dec_csr_wrdata_r[19], dec_csr_wrdata_r[18] & ~dec_csr_wrdata_r[19], + dec_csr_wrdata_r[17], dec_csr_wrdata_r[16] & ~dec_csr_wrdata_r[17], + dec_csr_wrdata_r[15], dec_csr_wrdata_r[14] & ~dec_csr_wrdata_r[15], + dec_csr_wrdata_r[13], dec_csr_wrdata_r[12] & ~dec_csr_wrdata_r[13], + dec_csr_wrdata_r[11], dec_csr_wrdata_r[10] & ~dec_csr_wrdata_r[11], + dec_csr_wrdata_r[9], dec_csr_wrdata_r[8] & ~dec_csr_wrdata_r[9], + dec_csr_wrdata_r[7], dec_csr_wrdata_r[6] & ~dec_csr_wrdata_r[7], + dec_csr_wrdata_r[5], dec_csr_wrdata_r[4] & ~dec_csr_wrdata_r[5], + dec_csr_wrdata_r[3], dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[3], + dec_csr_wrdata_r[1], dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[1]}; + + rvdffe #(32) mrac_ff (.*, .en(wr_mrac_r), .din(mrac_in[31:0]), .dout(mrac[31:0])); + + // drive to LSU/IFU + assign dec_tlu_mrac_ff[31:0] = mrac[31:0]; + + // ---------------------------------------------------------------------- + // MDEAU (WAR0) + // [31:0] : Dbus Error Address Unlock register + // + localparam MDEAU = 12'hbc0; + + assign wr_mdeau_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDEAU); + + + // ---------------------------------------------------------------------- + // MDSEAC (R) + // [31:0] : Dbus Store Error Address Capture register + // + localparam MDSEAC = 12'hfc0; + + // only capture error bus if the MDSEAC reg is not locked + assign mdseac_locked_ns = mdseac_en | (mdseac_locked_f & ~wr_mdeau_r); + + assign mdseac_en = (lsu_imprecise_error_store_any | lsu_imprecise_error_load_any) & ~nmi_int_detected_f & ~mdseac_locked_f; + + rvdffe #(32) mdseac_ff (.*, .en(mdseac_en), .din(lsu_imprecise_error_addr_any[31:0]), .dout(mdseac[31:0])); + + // ---------------------------------------------------------------------- + // MPMC (R0W1) + // [0] : FW halt + // [1] : Set MSTATUS[MIE] on halt + + localparam MPMC = 12'h7c6; + + assign wr_mpmc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MPMC); + + // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to + // set the mstatus bit potentially, use delayed version of internal dbg halt. + assign fw_halt_req = wr_mpmc_r & dec_csr_wrdata_r[0] & ~internal_dbg_halt_mode_f2 & ~ext_int_freeze_d1; + + assign fw_halted_ns = (fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt; + assign mpmc_b_ns[1] = wr_mpmc_r ? ~dec_csr_wrdata_r[1] : ~mpmc[1]; + rvdff #(1) mpmc_ff (.*, .clk(csr_wr_clk), .din(mpmc_b_ns[1]), .dout(mpmc_b[1])); + assign mpmc[1] = ~mpmc_b[1]; + + // ---------------------------------------------------------------------- + // MICECT (I-Cache error counter/threshold) + // [31:27] : Icache parity error threshold + // [26:0] : Icache parity error count + localparam MICECT = 12'h7f0; + + assign csr_sat[31:27] = (dec_csr_wrdata_r[31:27] > 5'd26) ? 5'd26 : dec_csr_wrdata_r[31:27]; + + assign wr_micect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICECT); + assign micect_inc[26:0] = micect[26:0] + {26'b0, ic_perr_r}; + assign micect_ns = wr_micect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {micect[31:27], micect_inc[26:0]}; + + rvdffe #(32) micect_ff (.*, .en(wr_micect_r | ic_perr_r), .din(micect_ns[31:0]), .dout(micect[31:0])); + + assign mice_ce_req = |({32'hffffffff << micect[31:27]} & {5'b0, micect[26:0]}); + + // ---------------------------------------------------------------------- + // MICCMECT (ICCM error counter/threshold) + // [31:27] : ICCM parity error threshold + // [26:0] : ICCM parity error count + localparam MICCMECT = 12'h7f1; + + assign wr_miccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICCMECT); + assign miccmect_inc[26:0] = miccmect[26:0] + {26'b0, iccm_sbecc_r | iccm_dma_sb_error}; + assign miccmect_ns = wr_miccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {miccmect[31:27], miccmect_inc[26:0]}; + + rvdffe #(32) miccmect_ff (.*, .clk(free_l2clk), .en(wr_miccmect_r | iccm_sbecc_r | iccm_dma_sb_error), .din(miccmect_ns[31:0]), .dout(miccmect[31:0])); + + assign miccme_ce_req = |({32'hffffffff << miccmect[31:27]} & {5'b0, miccmect[26:0]}); + + // ---------------------------------------------------------------------- + // MDCCMECT (DCCM error counter/threshold) + // [31:27] : DCCM parity error threshold + // [26:0] : DCCM parity error count + localparam MDCCMECT = 12'h7f2; + + assign wr_mdccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDCCMECT); + assign mdccmect_inc[26:0] = mdccmect[26:0] + {26'b0, lsu_single_ecc_error_r_d1}; + assign mdccmect_ns = wr_mdccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {mdccmect[31:27], mdccmect_inc[26:0]}; + + rvdffe #(32) mdccmect_ff (.*, .clk(free_l2clk), .en(wr_mdccmect_r | lsu_single_ecc_error_r_d1), .din(mdccmect_ns[31:0]), .dout(mdccmect[31:0])); + + assign mdccme_ce_req = |({32'hffffffff << mdccmect[31:27]} & {5'b0, mdccmect[26:0]}); + + + // ---------------------------------------------------------------------- + // MFDHT (Force Debug Halt Threshold) + // [5:1] : Halt timeout threshold (power of 2) + // [0] : Halt timeout enabled + localparam MFDHT = 12'h7ce; + + assign wr_mfdht_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHT); + + assign mfdht_ns[5:0] = wr_mfdht_r ? dec_csr_wrdata_r[5:0] : mfdht[5:0]; + + rvdffs #(6) mfdht_ff (.*, .clk(csr_wr_clk), .en(wr_mfdht_r), .din(mfdht_ns[5:0]), .dout(mfdht[5:0])); + + // ---------------------------------------------------------------------- + // MFDHS(RW) + // [1] : LSU operation pending when debug halt threshold reached + // [0] : IFU operation pending when debug halt threshold reached + + localparam MFDHS = 12'h7cf; + + assign wr_mfdhs_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHS); + + assign mfdhs_ns[1:0] = wr_mfdhs_r ? dec_csr_wrdata_r[1:0] : ((dbg_tlu_halted & ~dbg_tlu_halted_f) ? {~lsu_idle_any_f, ~ifu_miss_state_idle_f} : mfdhs[1:0]); + + rvdffs #(2) mfdhs_ff (.*, .clk(free_clk), .en(wr_mfdhs_r | dbg_tlu_halted), .din(mfdhs_ns[1:0]), .dout(mfdhs[1:0])); + + assign force_halt_ctr[31:0] = debug_halt_req_f ? (force_halt_ctr_f[31:0] + 32'b1) : (dbg_tlu_halted_f ? 32'b0 : force_halt_ctr_f[31:0]); + + rvdffe #(32) forcehaltctr_ff (.*, .en(mfdht[0]), .din(force_halt_ctr[31:0]), .dout(force_halt_ctr_f[31:0])); + + assign force_halt = mfdht[0] & |(force_halt_ctr_f[31:0] & (32'hffffffff << mfdht[5:1])); + + + // ---------------------------------------------------------------------- + // MEIVT (External Interrupt Vector Table (R/W)) + // [31:10]: Base address (R/W) + // [9:0] : Reserved, reads 0x0 + localparam MEIVT = 12'hbc8; + + assign wr_meivt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIVT); + + rvdffe #(22) meivt_ff (.*, .en(wr_meivt_r), .din(dec_csr_wrdata_r[31:10]), .dout(meivt[31:10])); + + + // ---------------------------------------------------------------------- + // MEIHAP (External Interrupt Handler Access Pointer (R)) + // [31:10]: Base address (R/W) + // [9:2] : ClaimID (R) + // [1:0] : Reserved, 0x0 + localparam MEIHAP = 12'hfc8; + + assign wr_meihap_r = wr_meicpct_r; + + rvdffe #(8) meihap_ff (.*, .en(wr_meihap_r), .din(pic_claimid[7:0]), .dout(meihap[9:2])); + + assign dec_tlu_meihap[31:2] = {meivt[31:10], meihap[9:2]}; + // ---------------------------------------------------------------------- + // MEICURPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W) + localparam MEICURPL = 12'hbcc; + + assign wr_meicurpl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICURPL); + assign meicurpl_ns[3:0] = wr_meicurpl_r ? dec_csr_wrdata_r[3:0] : meicurpl[3:0]; + + rvdff #(4) meicurpl_ff (.*, .clk(csr_wr_clk), .din(meicurpl_ns[3:0]), .dout(meicurpl[3:0])); + + // PIC needs this reg + assign dec_tlu_meicurpl[3:0] = meicurpl[3:0]; + + + // ---------------------------------------------------------------------- + // MEICIDPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : External Interrupt Claim ID's Priority Level Register + localparam MEICIDPL = 12'hbcb; + + assign wr_meicidpl_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICIDPL)) | take_ext_int_start; + + assign meicidpl_ns[3:0] = wr_meicpct_r ? pic_pl[3:0] : (wr_meicidpl_r ? dec_csr_wrdata_r[3:0] : meicidpl[3:0]); + + + // ---------------------------------------------------------------------- + // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL + // [31:1] : Reserved (read 0x0) + // [0] : Capture (W1, Read 0) + localparam MEICPCT = 12'hbca; + + assign wr_meicpct_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICPCT)) | take_ext_int_start; + + // ---------------------------------------------------------------------- + // MEIPT (External Interrupt Priority Threshold) + // [31:4] : Reserved (read 0x0) + // [3:0] : PRITHRESH + localparam MEIPT = 12'hbc9; + + assign wr_meipt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIPT); + assign meipt_ns[3:0] = wr_meipt_r ? dec_csr_wrdata_r[3:0] : meipt[3:0]; + + rvdff #(4) meipt_ff (.*, .clk(csr_wr_clk), .din(meipt_ns[3:0]), .dout(meipt[3:0])); + + // to PIC + assign dec_tlu_meipt[3:0] = meipt[3:0]; + // ---------------------------------------------------------------------- + // DCSR (R/W) (Only accessible in debug mode) + // [31:28] : xdebugver (hard coded to 0x4) RO + // [27:16] : 0x0, reserved + // [15] : ebreakm + // [14] : 0x0, reserved + // [13] : ebreaks (0x0 for this core) + // [12] : ebreaku (0x0 for this core) + // [11] : stepie + // [10] : stopcount + // [9] : 0x0 //stoptime + // [8:6] : cause (RO) + // [5:4] : 0x0, reserved + // [3] : nmip + // [2] : step + // [1:0] : prv (0x3 for this core) + // + localparam DCSR = 12'h7b0; + + // RV has clarified that 'priority 4' in the spec means top priority. + // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger. + + // RV debug spec indicates a cause priority change for trigger hits during single step. + assign trigger_hit_for_dscr_cause_r_d1 = trigger_hit_dmode_r_d1 | (trigger_hit_r_d1 & dcsr_single_step_done_f); + + assign dcsr_cause[8:6] = ( ({3{dcsr_single_step_done_f & ~ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1 & ~debug_halt_req}} & 3'b100) | + ({3{debug_halt_req & ~ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b011) | + ({3{ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b001) | + ({3{trigger_hit_for_dscr_cause_r_d1}} & 3'b010)); + + assign wr_dcsr_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DCSR); + + + + // Multiple halt enter requests can happen before we are halted. + // We have to continue to upgrade based on dcsr_cause priority but we can't downgrade. + assign dcsr_cause_upgradeable = internal_dbg_halt_mode_f & (dcsr[8:6] == 3'b011); + assign enter_debug_halt_req_le = enter_debug_halt_req & (~dbg_tlu_halted | dcsr_cause_upgradeable); + + assign nmi_in_debug_mode = nmi_int_detected_f & internal_dbg_halt_mode_f; + assign dcsr_ns[15:2] = enter_debug_halt_req_le ? {dcsr[15:9], dcsr_cause[8:6], dcsr[5:2]} : + (wr_dcsr_r ? {dec_csr_wrdata_r[15], 3'b0, dec_csr_wrdata_r[11:10], 1'b0, dcsr[8:6], 2'b00, nmi_in_debug_mode | dcsr[3], dec_csr_wrdata_r[2]} : + {dcsr[15:4], nmi_in_debug_mode, dcsr[2]}); + + rvdffe #(14) dcsr_ff (.*, .clk(free_l2clk), .en(enter_debug_halt_req_le | wr_dcsr_r | internal_dbg_halt_mode | take_nmi), .din(dcsr_ns[15:2]), .dout(dcsr[15:2])); + + // ---------------------------------------------------------------------- + // DPC (R/W) (Only accessible in debug mode) + // [31:0] : Debug PC + localparam DPC = 12'h7b1; + + assign wr_dpc_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DPC); + assign dpc_capture_npc = dbg_tlu_halted & ~dbg_tlu_halted_f & ~request_debug_mode_done; + assign dpc_capture_pc = request_debug_mode_r; + + assign dpc_ns[31:1] = ( ({31{~dpc_capture_pc & ~dpc_capture_npc & wr_dpc_r}} & dec_csr_wrdata_r[31:1]) | + ({31{dpc_capture_pc}} & pc_r[31:1]) | + ({31{~dpc_capture_pc & dpc_capture_npc}} & npc_r[31:1]) ); + + rvdffe #(31) dpc_ff (.*, .en(wr_dpc_r | dpc_capture_pc | dpc_capture_npc), .din(dpc_ns[31:1]), .dout(dpc[31:1])); + + // ---------------------------------------------------------------------- + // DICAWICS (R/W) (Only accessible in debug mode) + // [31:25] : Reserved + // [24] : Array select, 0 is data, 1 is tag + // [23:22] : Reserved + // [21:20] : Way select + // [19:17] : Reserved + // [16:3] : Index + // [2:0] : Reserved + localparam DICAWICS = 12'h7c8; + + assign dicawics_ns[16:0] = {dec_csr_wrdata_r[24], dec_csr_wrdata_r[21:20], dec_csr_wrdata_r[16:3]}; + assign wr_dicawics_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAWICS); + + rvdffe #(17) dicawics_ff (.*, .en(wr_dicawics_r), .din(dicawics_ns[16:0]), .dout(dicawics[16:0])); + + // ---------------------------------------------------------------------- + // DICAD0 (R/W) (Only accessible in debug mode) + // + // If dicawics[array] is 0 + // [31:0] : inst data + // + // If dicawics[array] is 1 + // [31:16] : Tag + // [15:7] : Reserved + // [6:4] : LRU + // [3:1] : Reserved + // [0] : Valid + localparam DICAD0 = 12'h7c9; + + assign dicad0_ns[31:0] = wr_dicad0_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[31:0]; + + assign wr_dicad0_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD0); + + rvdffe #(32) dicad0_ff (.*, .en(wr_dicad0_r | ifu_ic_debug_rd_data_valid), .din(dicad0_ns[31:0]), .dout(dicad0[31:0])); + + // ---------------------------------------------------------------------- + // DICAD0H (R/W) (Only accessible in debug mode) + // + // If dicawics[array] is 0 + // [63:32] : inst data + // + localparam DICAD0H = 12'h7cc; + + assign dicad0h_ns[31:0] = wr_dicad0h_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[63:32]; + + assign wr_dicad0h_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD0H); + + rvdffe #(32) dicad0h_ff (.*, .en(wr_dicad0h_r | ifu_ic_debug_rd_data_valid), .din(dicad0h_ns[31:0]), .dout(dicad0h[31:0])); + + +if (pt.ICACHE_ECC == 1) begin + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [6:0] : ECC + localparam DICAD1 = 12'h7ca; + + assign dicad1_ns[6:0] = wr_dicad1_r ? dec_csr_wrdata_r[6:0] : ifu_ic_debug_rd_data[70:64]; + + assign wr_dicad1_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD1); + + rvdffe #(.WIDTH(7), .OVERRIDE(1)) dicad1_ff (.*, .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), .din(dicad1_ns[6:0]), .dout(dicad1_raw[6:0])); + + assign dicad1[31:0] = {25'b0, dicad1_raw[6:0]}; + +end +else begin + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [3:0] : Parity + localparam DICAD1 = 12'h7ca; + + assign dicad1_ns[3:0] = wr_dicad1_r ? dec_csr_wrdata_r[3:0] : ifu_ic_debug_rd_data[67:64]; + + assign wr_dicad1_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD1); + + rvdffs #(4) dicad1_ff (.*, .clk(free_clk), .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), .din(dicad1_ns[3:0]), .dout(dicad1_raw[3:0])); + + assign dicad1[31:0] = {28'b0, dicad1_raw[3:0]}; +end + // ---------------------------------------------------------------------- + // DICAGO (R/W) (Only accessible in debug mode) + // [0] : Go + localparam DICAGO = 12'h7cb; + +if (pt.ICACHE_ECC == 1) + assign dec_tlu_ic_diag_pkt.icache_wrdata[70:0] = { dicad1[6:0], dicad0h[31:0], dicad0[31:0]}; +else + assign dec_tlu_ic_diag_pkt.icache_wrdata[70:0] = {3'b0, dicad1[3:0], dicad0h[31:0], dicad0[31:0]}; + + + assign dec_tlu_ic_diag_pkt.icache_dicawics[16:0] = dicawics[16:0]; + + assign icache_rd_valid = allow_dbg_halt_csr_write & dec_csr_any_unq_d & dec_i0_decode_d & ~dec_csr_wen_unq_d & (dec_csr_rdaddr_d[11:0] == DICAGO); + assign icache_wr_valid = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAGO); + + + assign dec_tlu_ic_diag_pkt.icache_rd_valid = icache_rd_valid_f; + assign dec_tlu_ic_diag_pkt.icache_wr_valid = icache_wr_valid_f; + + // ---------------------------------------------------------------------- + // MTSEL (R/W) + // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count + localparam MTSEL = 12'h7a0; + + assign wr_mtsel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTSEL); + assign mtsel_ns[1:0] = wr_mtsel_r ? {dec_csr_wrdata_r[1:0]} : mtsel[1:0]; + + rvdff #(2) mtsel_ff (.*, .clk(csr_wr_clk), .din(mtsel_ns[1:0]), .dout(mtsel[1:0])); + + // ---------------------------------------------------------------------- + // MTDATA1 (R/W) + // [31:0] : Trigger Data 1 + localparam MTDATA1 = 12'h7a1; + + // for triggers 0, 1, 2 and 3 aka Match Control + // [31:28] : type, hard coded to 0x2 + // [27] : dmode + // [26:21] : hard coded to 0x1f + // [20] : hit + // [19] : select (0 - address, 1 - data) + // [18] : timing, always 'before', reads 0x0 + // [17:12] : action, bits [17:13] not implemented and reads 0x0 + // [11] : chain + // [10:7] : match, bits [10:8] not implemented and reads 0x0 + // [6] : M + // [5:3] : not implemented, reads 0x0 + // [2] : execute + // [1] : store + // [0] : load + // + // decoder ring + // [27] : => 9 + // [20] : => 8 + // [19] : => 7 + // [12] : => 6 + // [11] : => 5 + // [7] : => 4 + // [6] : => 3 + // [2] : => 2 + // [1] : => 1 + // [0] : => 0 + + + // don't allow setting load-data. + assign tdata_load = dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[19]; + // don't allow setting execute-data. + assign tdata_opcode = dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[19]; + // don't allow clearing DMODE and action=1 + assign tdata_action = (dec_csr_wrdata_r[27] & dbg_tlu_halted_f) & dec_csr_wrdata_r[12]; + + // Chain bit has conditions: WARL for triggers without chains. Force to zero if dmode is 0 but next trigger dmode is 1. + assign tdata_chain = mtsel[0] ? 1'b0 : // triggers 1 and 3 chain bit is always zero + mtsel[1] ? dec_csr_wrdata_r[11] & ~(mtdata1_t3[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]) : // trigger 2 + dec_csr_wrdata_r[11] & ~(mtdata1_t1[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]); // trigger 0 + + // Kill mtdata1 write if dmode=1 but prior trigger has dmode=0/chain=1. Only applies to T1 and T3 + assign tdata_kill_write = mtsel[1] ? dec_csr_wrdata_r[27] & (~mtdata1_t2[MTDATA1_DMODE] & mtdata1_t2[MTDATA1_CHAIN]) : // trigger 3 + dec_csr_wrdata_r[27] & (~mtdata1_t0[MTDATA1_DMODE] & mtdata1_t0[MTDATA1_CHAIN]) ; // trigger 1 + + + assign tdata_wrdata_r[9:0] = {dec_csr_wrdata_r[27] & dbg_tlu_halted_f, + dec_csr_wrdata_r[20:19], + tdata_action, + tdata_chain, + dec_csr_wrdata_r[7:6], + tdata_opcode, + dec_csr_wrdata_r[1], + tdata_load}; + + // If the DMODE bit is set, tdata1 can only be updated in debug_mode + assign wr_mtdata1_t0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b0) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f); + assign mtdata1_t0_ns[9:0] = wr_mtdata1_t0_r ? tdata_wrdata_r[9:0] : + {mtdata1_t0[9], update_hit_bit_r[0] | mtdata1_t0[8], mtdata1_t0[7:0]}; + + assign wr_mtdata1_t1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b01) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f) & ~tdata_kill_write; + assign mtdata1_t1_ns[9:0] = wr_mtdata1_t1_r ? tdata_wrdata_r[9:0] : + {mtdata1_t1[9], update_hit_bit_r[1] | mtdata1_t1[8], mtdata1_t1[7:0]}; + + assign wr_mtdata1_t2_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b10) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f); + assign mtdata1_t2_ns[9:0] = wr_mtdata1_t2_r ? tdata_wrdata_r[9:0] : + {mtdata1_t2[9], update_hit_bit_r[2] | mtdata1_t2[8], mtdata1_t2[7:0]}; + + assign wr_mtdata1_t3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b11) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f) & ~tdata_kill_write; + assign mtdata1_t3_ns[9:0] = wr_mtdata1_t3_r ? tdata_wrdata_r[9:0] : + {mtdata1_t3[9], update_hit_bit_r[3] | mtdata1_t3[8], mtdata1_t3[7:0]}; + + + rvdffe #(10) mtdata1_t0_ff (.*, .en(trigger_enabled[0] | wr_mtdata1_t0_r), .din(mtdata1_t0_ns[9:0]), .dout(mtdata1_t0[9:0])); + rvdffe #(10) mtdata1_t1_ff (.*, .en(trigger_enabled[1] | wr_mtdata1_t1_r), .din(mtdata1_t1_ns[9:0]), .dout(mtdata1_t1[9:0])); + rvdffe #(10) mtdata1_t2_ff (.*, .en(trigger_enabled[2] | wr_mtdata1_t2_r), .din(mtdata1_t2_ns[9:0]), .dout(mtdata1_t2[9:0])); + rvdffe #(10) mtdata1_t3_ff (.*, .en(trigger_enabled[3] | wr_mtdata1_t3_r), .din(mtdata1_t3_ns[9:0]), .dout(mtdata1_t3[9:0])); + + assign mtdata1_tsel_out[31:0] = ( ({32{(mtsel[1:0] == 2'b00)}} & {4'h2, mtdata1_t0[9], 6'b011111, mtdata1_t0[8:7], 6'b0, mtdata1_t0[6:5], 3'b0, mtdata1_t0[4:3], 3'b0, mtdata1_t0[2:0]}) | + ({32{(mtsel[1:0] == 2'b01)}} & {4'h2, mtdata1_t1[9], 6'b011111, mtdata1_t1[8:7], 6'b0, mtdata1_t1[6:5], 3'b0, mtdata1_t1[4:3], 3'b0, mtdata1_t1[2:0]}) | + ({32{(mtsel[1:0] == 2'b10)}} & {4'h2, mtdata1_t2[9], 6'b011111, mtdata1_t2[8:7], 6'b0, mtdata1_t2[6:5], 3'b0, mtdata1_t2[4:3], 3'b0, mtdata1_t2[2:0]}) | + ({32{(mtsel[1:0] == 2'b11)}} & {4'h2, mtdata1_t3[9], 6'b011111, mtdata1_t3[8:7], 6'b0, mtdata1_t3[6:5], 3'b0, mtdata1_t3[4:3], 3'b0, mtdata1_t3[2:0]})); + + assign trigger_pkt_any[0].select = mtdata1_t0[MTDATA1_SEL]; + assign trigger_pkt_any[0].match = mtdata1_t0[MTDATA1_MATCH]; + assign trigger_pkt_any[0].store = mtdata1_t0[MTDATA1_ST]; + assign trigger_pkt_any[0].load = mtdata1_t0[MTDATA1_LD]; + assign trigger_pkt_any[0].execute = mtdata1_t0[MTDATA1_EXE]; + assign trigger_pkt_any[0].m = mtdata1_t0[MTDATA1_M_ENABLED]; + + assign trigger_pkt_any[1].select = mtdata1_t1[MTDATA1_SEL]; + assign trigger_pkt_any[1].match = mtdata1_t1[MTDATA1_MATCH]; + assign trigger_pkt_any[1].store = mtdata1_t1[MTDATA1_ST]; + assign trigger_pkt_any[1].load = mtdata1_t1[MTDATA1_LD]; + assign trigger_pkt_any[1].execute = mtdata1_t1[MTDATA1_EXE]; + assign trigger_pkt_any[1].m = mtdata1_t1[MTDATA1_M_ENABLED]; + + assign trigger_pkt_any[2].select = mtdata1_t2[MTDATA1_SEL]; + assign trigger_pkt_any[2].match = mtdata1_t2[MTDATA1_MATCH]; + assign trigger_pkt_any[2].store = mtdata1_t2[MTDATA1_ST]; + assign trigger_pkt_any[2].load = mtdata1_t2[MTDATA1_LD]; + assign trigger_pkt_any[2].execute = mtdata1_t2[MTDATA1_EXE]; + assign trigger_pkt_any[2].m = mtdata1_t2[MTDATA1_M_ENABLED]; + + assign trigger_pkt_any[3].select = mtdata1_t3[MTDATA1_SEL]; + assign trigger_pkt_any[3].match = mtdata1_t3[MTDATA1_MATCH]; + assign trigger_pkt_any[3].store = mtdata1_t3[MTDATA1_ST]; + assign trigger_pkt_any[3].load = mtdata1_t3[MTDATA1_LD]; + assign trigger_pkt_any[3].execute = mtdata1_t3[MTDATA1_EXE]; + assign trigger_pkt_any[3].m = mtdata1_t3[MTDATA1_M_ENABLED]; + + + + + + // ---------------------------------------------------------------------- + // MTDATA2 (R/W) + // [31:0] : Trigger Data 2 + localparam MTDATA2 = 12'h7a2; + + // If the DMODE bit is set, tdata2 can only be updated in debug_mode + assign wr_mtdata2_t0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b0) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f); + assign wr_mtdata2_t1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b01) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f); + assign wr_mtdata2_t2_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b10) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f); + assign wr_mtdata2_t3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b11) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f); + + rvdffe #(32) mtdata2_t0_ff (.*, .en(wr_mtdata2_t0_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t0[31:0])); + rvdffe #(32) mtdata2_t1_ff (.*, .en(wr_mtdata2_t1_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t1[31:0])); + rvdffe #(32) mtdata2_t2_ff (.*, .en(wr_mtdata2_t2_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t2[31:0])); + rvdffe #(32) mtdata2_t3_ff (.*, .en(wr_mtdata2_t3_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t3[31:0])); + + assign mtdata2_tsel_out[31:0] = ( ({32{(mtsel[1:0] == 2'b00)}} & mtdata2_t0[31:0]) | + ({32{(mtsel[1:0] == 2'b01)}} & mtdata2_t1[31:0]) | + ({32{(mtsel[1:0] == 2'b10)}} & mtdata2_t2[31:0]) | + ({32{(mtsel[1:0] == 2'b11)}} & mtdata2_t3[31:0])); + + assign trigger_pkt_any[0].tdata2[31:0] = mtdata2_t0[31:0]; + assign trigger_pkt_any[1].tdata2[31:0] = mtdata2_t1[31:0]; + assign trigger_pkt_any[2].tdata2[31:0] = mtdata2_t2[31:0]; + assign trigger_pkt_any[3].tdata2[31:0] = mtdata2_t3[31:0]; + + + //---------------------------------------------------------------------- + // Performance Monitor Counters section starts + //---------------------------------------------------------------------- + localparam MHPME_NOEVENT = 10'd0; + localparam MHPME_CLK_ACTIVE = 10'd1; // OOP - out of pipe + localparam MHPME_ICACHE_HIT = 10'd2; // OOP + localparam MHPME_ICACHE_MISS = 10'd3; // OOP + localparam MHPME_INST_COMMIT = 10'd4; + localparam MHPME_INST_COMMIT_16B = 10'd5; + localparam MHPME_INST_COMMIT_32B = 10'd6; + localparam MHPME_INST_ALIGNED = 10'd7; // OOP + localparam MHPME_INST_DECODED = 10'd8; // OOP + localparam MHPME_INST_MUL = 10'd9; + localparam MHPME_INST_DIV = 10'd10; + localparam MHPME_INST_LOAD = 10'd11; + localparam MHPME_INST_STORE = 10'd12; + localparam MHPME_INST_MALOAD = 10'd13; + localparam MHPME_INST_MASTORE = 10'd14; + localparam MHPME_INST_ALU = 10'd15; + localparam MHPME_INST_CSRREAD = 10'd16; + localparam MHPME_INST_CSRRW = 10'd17; + localparam MHPME_INST_CSRWRITE = 10'd18; + localparam MHPME_INST_EBREAK = 10'd19; + localparam MHPME_INST_ECALL = 10'd20; + localparam MHPME_INST_FENCE = 10'd21; + localparam MHPME_INST_FENCEI = 10'd22; + localparam MHPME_INST_MRET = 10'd23; + localparam MHPME_INST_BRANCH = 10'd24; + localparam MHPME_BRANCH_MP = 10'd25; + localparam MHPME_BRANCH_TAKEN = 10'd26; + localparam MHPME_BRANCH_NOTP = 10'd27; + localparam MHPME_FETCH_STALL = 10'd28; // OOP + localparam MHPME_DECODE_STALL = 10'd30; // OOP + localparam MHPME_POSTSYNC_STALL = 10'd31; // OOP + localparam MHPME_PRESYNC_STALL = 10'd32; // OOP + localparam MHPME_LSU_SB_WB_STALL = 10'd34; // OOP + localparam MHPME_DMA_DCCM_STALL = 10'd35; // OOP + localparam MHPME_DMA_ICCM_STALL = 10'd36; // OOP + localparam MHPME_EXC_TAKEN = 10'd37; + localparam MHPME_TIMER_INT_TAKEN = 10'd38; + localparam MHPME_EXT_INT_TAKEN = 10'd39; + localparam MHPME_FLUSH_LOWER = 10'd40; + localparam MHPME_BR_ERROR = 10'd41; + localparam MHPME_IBUS_TRANS = 10'd42; // OOP + localparam MHPME_DBUS_TRANS = 10'd43; // OOP + localparam MHPME_DBUS_MA_TRANS = 10'd44; // OOP + localparam MHPME_IBUS_ERROR = 10'd45; // OOP + localparam MHPME_DBUS_ERROR = 10'd46; // OOP + localparam MHPME_IBUS_STALL = 10'd47; // OOP + localparam MHPME_DBUS_STALL = 10'd48; // OOP + localparam MHPME_INT_DISABLED = 10'd49; // OOP + localparam MHPME_INT_STALLED = 10'd50; // OOP + localparam MHPME_INST_BITMANIP = 10'd54; + localparam MHPME_DBUS_LOAD = 10'd55; + localparam MHPME_DBUS_STORE = 10'd56; + // Counts even during sleep state + localparam MHPME_SLEEP_CYC = 10'd512; // OOP + localparam MHPME_DMA_READ_ALL = 10'd513; // OOP + localparam MHPME_DMA_WRITE_ALL = 10'd514; // OOP + localparam MHPME_DMA_READ_DCCM = 10'd515; // OOP + localparam MHPME_DMA_WRITE_DCCM = 10'd516; // OOP + + // Pack the event selects into a vector for genvar + assign mhpme_vec[0][9:0] = mhpme3[9:0]; + assign mhpme_vec[1][9:0] = mhpme4[9:0]; + assign mhpme_vec[2][9:0] = mhpme5[9:0]; + assign mhpme_vec[3][9:0] = mhpme6[9:0]; + + // only consider committed itypes + //logic [3:0] pmu_i0_itype_qual; + assign pmu_i0_itype_qual[3:0] = dec_tlu_packet_r.pmu_i0_itype[3:0] & {4{tlu_i0_commit_cmt}}; + + // Generate the muxed incs for all counters based on event type + for (genvar i=0 ; i < 4; i++) begin + assign mhpmc_inc_r[i] = {{~mcountinhibit[i+3]}} & + ( + ({1{(mhpme_vec[i][9:0] == MHPME_CLK_ACTIVE )}} & 1'b1) | + ({1{(mhpme_vec[i][9:0] == MHPME_ICACHE_HIT )}} & {ifu_pmu_ic_hit}) | + ({1{(mhpme_vec[i][9:0] == MHPME_ICACHE_MISS )}} & {ifu_pmu_ic_miss}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT )}} & {tlu_i0_commit_cmt & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_16B )}} & {tlu_i0_commit_cmt & ~exu_pmu_i0_pc4 & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_32B )}} & {tlu_i0_commit_cmt & exu_pmu_i0_pc4 & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_ALIGNED )}} & ifu_pmu_instr_aligned) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_DECODED )}} & dec_pmu_instr_decoded) | + ({1{(mhpme_vec[i][9:0] == MHPME_DECODE_STALL )}} & {dec_pmu_decode_stall}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_MUL )}} & {(pmu_i0_itype_qual == MUL)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_DIV )}} & {dec_tlu_packet_r.pmu_divide & tlu_i0_commit_cmt & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_LOAD )}} & {(pmu_i0_itype_qual == LOAD)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_STORE )}} & {(pmu_i0_itype_qual == STORE)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_MALOAD )}} & {(pmu_i0_itype_qual == LOAD)} & + {1{dec_tlu_packet_r.pmu_lsu_misaligned}}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_MASTORE )}} & {(pmu_i0_itype_qual == STORE)} & + {1{dec_tlu_packet_r.pmu_lsu_misaligned}}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_ALU )}} & {(pmu_i0_itype_qual == ALU)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRREAD )}} & {(pmu_i0_itype_qual == CSRREAD)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRWRITE )}} & {(pmu_i0_itype_qual == CSRWRITE)})| + ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRRW )}} & {(pmu_i0_itype_qual == CSRRW)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_EBREAK )}} & {(pmu_i0_itype_qual == EBREAK)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_ECALL )}} & {(pmu_i0_itype_qual == ECALL)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_FENCE )}} & {(pmu_i0_itype_qual == FENCE)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_FENCEI )}} & {(pmu_i0_itype_qual == FENCEI)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_MRET )}} & {(pmu_i0_itype_qual == MRET)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_BRANCH )}} & { + ((pmu_i0_itype_qual == CONDBR) | (pmu_i0_itype_qual == JAL))}) | + ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_MP )}} & {exu_pmu_i0_br_misp & tlu_i0_commit_cmt & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_TAKEN )}} & {exu_pmu_i0_br_ataken & tlu_i0_commit_cmt & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_NOTP )}} & {dec_tlu_packet_r.pmu_i0_br_unpred & tlu_i0_commit_cmt & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_FETCH_STALL )}} & { ifu_pmu_fetch_stall}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DECODE_STALL )}} & { dec_pmu_decode_stall}) | + ({1{(mhpme_vec[i][9:0] == MHPME_POSTSYNC_STALL )}} & {dec_pmu_postsync_stall}) | + ({1{(mhpme_vec[i][9:0] == MHPME_PRESYNC_STALL )}} & {dec_pmu_presync_stall}) | + ({1{(mhpme_vec[i][9:0] == MHPME_LSU_SB_WB_STALL )}} & { lsu_store_stall_any}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DMA_DCCM_STALL )}} & { dma_dccm_stall_any}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DMA_ICCM_STALL )}} & { dma_iccm_stall_any}) | + ({1{(mhpme_vec[i][9:0] == MHPME_EXC_TAKEN )}} & { (i0_exception_valid_r | i0_trigger_hit_r | lsu_exc_valid_r)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_TIMER_INT_TAKEN )}} & { take_timer_int | take_int_timer0_int | take_int_timer1_int}) | + ({1{(mhpme_vec[i][9:0] == MHPME_EXT_INT_TAKEN )}} & { take_ext_int}) | + ({1{(mhpme_vec[i][9:0] == MHPME_FLUSH_LOWER )}} & { tlu_flush_lower_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_BR_ERROR )}} & {(dec_tlu_br0_error_r | dec_tlu_br0_start_error_r) & rfpc_i0_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_TRANS )}} & {ifu_pmu_bus_trxn}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_TRANS )}} & {lsu_pmu_bus_trxn}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_MA_TRANS )}} & {lsu_pmu_bus_misaligned}) | + ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_ERROR )}} & {ifu_pmu_bus_error}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_ERROR )}} & {lsu_pmu_bus_error}) | + ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_STALL )}} & {ifu_pmu_bus_busy}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_STALL )}} & {lsu_pmu_bus_busy}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INT_DISABLED )}} & {~mstatus[MSTATUS_MIE]}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INT_STALLED )}} & {~mstatus[MSTATUS_MIE] & |(mip[5:0] & mie[5:0])}) | + ({1{(mhpme_vec[i][9:0] == MHPME_INST_BITMANIP )}} & {(pmu_i0_itype_qual == BITMANIPU)}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_LOAD )}} & {tlu_i0_commit_cmt & lsu_pmu_load_external_r & ~illegal_r}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_STORE )}} & {tlu_i0_commit_cmt & lsu_pmu_store_external_r & ~illegal_r}) | + // These count even during sleep + ({1{(mhpme_vec[i][9:0] == MHPME_SLEEP_CYC )}} & {dec_tlu_pmu_fw_halted}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DMA_READ_ALL )}} & {dma_pmu_any_read}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DMA_WRITE_ALL )}} & {dma_pmu_any_write}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DMA_READ_DCCM )}} & {dma_pmu_dccm_read}) | + ({1{(mhpme_vec[i][9:0] == MHPME_DMA_WRITE_DCCM )}} & {dma_pmu_dccm_write}) + ); + end + + + if(pt.FAST_INTERRUPT_REDIRECT) + rvdffie #(31) mstatus_ff (.*, .clk(free_l2clk), + .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, + take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze, + mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in, + minstret_enable, minstretl_cout_ns, fw_halted_ns, + meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, + mstatus_ns[1:0]}), + .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, + take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1, + mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, + fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, + mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, + mstatus[1:0]})); + + else + rvdffie #(27) mstatus_ff (.*, .clk(free_l2clk), + .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r, + mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in, + minstret_enable, minstretl_cout_ns, fw_halted_ns, + meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted, + mstatus_ns[1:0]}), + .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, + mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f, + fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f, + mhpmc_inc_r_d1[3:0], perfcnt_halted_d1, + mstatus[1:0]})); + + assign perfcnt_halted = ((dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted); + assign perfcnt_during_sleep[3:0] = {4{~(dec_tlu_dbg_halted & dcsr[DCSR_STOPC])}} & {mhpme_vec[3][9],mhpme_vec[2][9],mhpme_vec[1][9],mhpme_vec[0][9]}; + + assign dec_tlu_perfcnt0 = mhpmc_inc_r_d1[0] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[0]); + assign dec_tlu_perfcnt1 = mhpmc_inc_r_d1[1] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[1]); + assign dec_tlu_perfcnt2 = mhpmc_inc_r_d1[2] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[2]); + assign dec_tlu_perfcnt3 = mhpmc_inc_r_d1[3] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[3]); + + // ---------------------------------------------------------------------- + // MHPMC3H(RW), MHPMC3(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 3 + localparam MHPMC3 = 12'hB03; + localparam MHPMC3H = 12'hB83; + + assign mhpmc3_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3); + assign mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[0]) & (|(mhpmc_inc_r[0])); + assign mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1; + assign mhpmc3_incr[63:0] = {mhpmc3h[31:0],mhpmc3[31:0]} + {63'b0, 1'b1}; + assign mhpmc3_ns[31:0] = mhpmc3_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[31:0]; + rvdffe #(32) mhpmc3_ff (.*, .clk(free_l2clk), .en(mhpmc3_wr_en), .din(mhpmc3_ns[31:0]), .dout(mhpmc3[31:0])); + + assign mhpmc3h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3H); + assign mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1; + assign mhpmc3h_ns[31:0] = mhpmc3h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[63:32]; + rvdffe #(32) mhpmc3h_ff (.*, .clk(free_l2clk), .en(mhpmc3h_wr_en), .din(mhpmc3h_ns[31:0]), .dout(mhpmc3h[31:0])); + + // ---------------------------------------------------------------------- + // MHPMC4H(RW), MHPMC4(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 4 + localparam MHPMC4 = 12'hB04; + localparam MHPMC4H = 12'hB84; + + assign mhpmc4_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4); + assign mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[1]) & (|(mhpmc_inc_r[1])); + assign mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1; + assign mhpmc4_incr[63:0] = {mhpmc4h[31:0],mhpmc4[31:0]} + {63'b0,1'b1}; + assign mhpmc4_ns[31:0] = mhpmc4_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[31:0]; + rvdffe #(32) mhpmc4_ff (.*, .clk(free_l2clk), .en(mhpmc4_wr_en), .din(mhpmc4_ns[31:0]), .dout(mhpmc4[31:0])); + + assign mhpmc4h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4H); + assign mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1; + assign mhpmc4h_ns[31:0] = mhpmc4h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[63:32]; + rvdffe #(32) mhpmc4h_ff (.*, .clk(free_l2clk), .en(mhpmc4h_wr_en), .din(mhpmc4h_ns[31:0]), .dout(mhpmc4h[31:0])); + + // ---------------------------------------------------------------------- + // MHPMC5H(RW), MHPMC5(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 5 + localparam MHPMC5 = 12'hB05; + localparam MHPMC5H = 12'hB85; + + assign mhpmc5_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5); + assign mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[2]) & (|(mhpmc_inc_r[2])); + assign mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1; + assign mhpmc5_incr[63:0] = {mhpmc5h[31:0],mhpmc5[31:0]} + {63'b0,1'b1}; + assign mhpmc5_ns[31:0] = mhpmc5_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[31:0]; + rvdffe #(32) mhpmc5_ff (.*, .clk(free_l2clk), .en(mhpmc5_wr_en), .din(mhpmc5_ns[31:0]), .dout(mhpmc5[31:0])); + + assign mhpmc5h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5H); + assign mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1; + assign mhpmc5h_ns[31:0] = mhpmc5h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[63:32]; + rvdffe #(32) mhpmc5h_ff (.*, .clk(free_l2clk), .en(mhpmc5h_wr_en), .din(mhpmc5h_ns[31:0]), .dout(mhpmc5h[31:0])); + + // ---------------------------------------------------------------------- + // MHPMC6H(RW), MHPMC6(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 6 + localparam MHPMC6 = 12'hB06; + localparam MHPMC6H = 12'hB86; + + assign mhpmc6_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6); + assign mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[3]) & (|(mhpmc_inc_r[3])); + assign mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1; + assign mhpmc6_incr[63:0] = {mhpmc6h[31:0],mhpmc6[31:0]} + {63'b0,1'b1}; + assign mhpmc6_ns[31:0] = mhpmc6_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[31:0]; + rvdffe #(32) mhpmc6_ff (.*, .clk(free_l2clk), .en(mhpmc6_wr_en), .din(mhpmc6_ns[31:0]), .dout(mhpmc6[31:0])); + + assign mhpmc6h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6H); + assign mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1; + assign mhpmc6h_ns[31:0] = mhpmc6h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[63:32]; + rvdffe #(32) mhpmc6h_ff (.*, .clk(free_l2clk), .en(mhpmc6h_wr_en), .din(mhpmc6h_ns[31:0]), .dout(mhpmc6h[31:0])); + + // ---------------------------------------------------------------------- + // MHPME3(RW) + // [9:0] : Hardware Performance Monitor Event 3 + localparam MHPME3 = 12'h323; + + // we only have events 0-56 with holes, 512-516, HPME* are WARL so zero otherwise. + assign zero_event_r = ( (dec_csr_wrdata_r[9:0] > 10'd516) | + (|dec_csr_wrdata_r[31:10]) | + ((dec_csr_wrdata_r[9:0] < 10'd512) & (dec_csr_wrdata_r[9:0] > 10'd56)) | + ((dec_csr_wrdata_r[9:0] < 10'd54) & (dec_csr_wrdata_r[9:0] > 10'd50)) | + (dec_csr_wrdata_r[9:0] == 10'd29) | + (dec_csr_wrdata_r[9:0] == 10'd33) + ); + + assign event_r[9:0] = zero_event_r ? '0 : dec_csr_wrdata_r[9:0]; + + assign wr_mhpme3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME3); + rvdffe #(10) mhpme3_ff (.*, .en(wr_mhpme3_r), .din(event_r[9:0]), .dout(mhpme3[9:0])); + // ---------------------------------------------------------------------- + // MHPME4(RW) + // [9:0] : Hardware Performance Monitor Event 4 + localparam MHPME4 = 12'h324; + + assign wr_mhpme4_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME4); + rvdffe #(10) mhpme4_ff (.*, .en(wr_mhpme4_r), .din(event_r[9:0]), .dout(mhpme4[9:0])); + // ---------------------------------------------------------------------- + // MHPME5(RW) + // [9:0] : Hardware Performance Monitor Event 5 + localparam MHPME5 = 12'h325; + + assign wr_mhpme5_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME5); + rvdffe #(10) mhpme5_ff (.*, .en(wr_mhpme5_r), .din(event_r[9:0]), .dout(mhpme5[9:0])); + // ---------------------------------------------------------------------- + // MHPME6(RW) + // [9:0] : Hardware Performance Monitor Event 6 + localparam MHPME6 = 12'h326; + + assign wr_mhpme6_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME6); + rvdffe #(10) mhpme6_ff (.*, .en(wr_mhpme6_r), .din(event_r[9:0]), .dout(mhpme6[9:0])); + + //---------------------------------------------------------------------- + // Performance Monitor Counters section ends + //---------------------------------------------------------------------- + // ---------------------------------------------------------------------- + + // MCOUNTINHIBIT(RW) + // [31:7] : Reserved, read 0x0 + // [6] : HPM6 disable + // [5] : HPM5 disable + // [4] : HPM4 disable + // [3] : HPM3 disable + // [2] : MINSTRET disable + // [1] : reserved, read 0x0 + // [0] : MCYCLE disable + + localparam MCOUNTINHIBIT = 12'h320; + + assign wr_mcountinhibit_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTINHIBIT); + rvdffs #(6) mcountinhibit_ff (.*, .clk(csr_wr_clk), .en(wr_mcountinhibit_r), .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), .dout({mcountinhibit[6:2], mcountinhibit[0]})); + assign mcountinhibit[1] = 1'b0; + + //-------------------------------------------------------------------------------- + // trace + //-------------------------------------------------------------------------------- + logic [4:0] dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2; + logic dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2; + + assign {dec_tlu_i0_valid_wb1, + dec_tlu_i0_exc_valid_wb1, + dec_tlu_exc_cause_wb1_raw[4:0], + dec_tlu_int_valid_wb1_raw} = {8{~dec_tlu_trace_disable}} & {i0_valid_wb, + i0_exception_valid_r_d1 | lsu_i0_exc_r_d1 | (trigger_hit_r_d1 & ~trigger_hit_dmode_r_d1), + exc_cause_wb[4:0], + interrupt_valid_r_d1}; + + + + // skid buffer for ints, reduces trace port count by 1 + rvdffie #(.WIDTH(6), .OVERRIDE(1)) traceskidff (.*, .clk(clk), + .din ({dec_tlu_exc_cause_wb1_raw[4:0], + dec_tlu_int_valid_wb1_raw}), + .dout({dec_tlu_exc_cause_wb2[4:0], + dec_tlu_int_valid_wb2})); + //skid for ints + assign dec_tlu_exc_cause_wb1[4:0] = dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2[4:0] : dec_tlu_exc_cause_wb1_raw[4:0]; + assign dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2; + + assign dec_tlu_mtval_wb1 = mtval[31:0]; + + // end trace + //-------------------------------------------------------------------------------- + + + // ---------------------------------------------------------------------- + // CSR read mux + // ---------------------------------------------------------------------- + +// file "csrdecode" is human readable file that has all of the CSR decodes defined and is part of git repo +// modify this file as needed + +// to generate all the equations below from "csrdecode" except legal equation: + +// 1) coredecode -in csrdecode > corecsrdecode.e + +// 2) espresso -Dso -oeqntott corecsrdecode.e | addassign > csrequations + +// to generate the legal CSR equation below: + +// 1) coredecode -in csrdecode -legal > csrlegal.e + +// 2) espresso -Dso -oeqntott csrlegal.e | addassign > csrlegal_equation +// coredecode -in csrdecode > corecsrdecode.e; espresso -Dso -oeqntott corecsrdecode.e | addassign > csrequations; coredecode -in csrdecode -legal > csrlegal.e; espresso -Dso -oeqntott csrlegal.e | addassign > csrlegal_equation + +assign csr_misa = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mvendorid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_marchid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mimpid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mhartid = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[2]); + +assign csr_mstatus = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); + +assign csr_mtvec = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mip = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2]); + +assign csr_mie = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); + +assign csr_mcyclel = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]); + +assign csr_mcycleh = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_minstretl = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_minstreth = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mscratch = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mepc = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mcause = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mscause = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]); + +assign csr_mtval = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mrac = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_dmst = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_mdseac = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]); + +assign csr_meihap = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[3]); + +assign csr_meivt = (!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_meipt = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_meicurpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[2]); + +assign csr_meicidpl = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dcsr = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]); + +assign csr_mcgc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[0]); + +assign csr_mfdc = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dpc = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[0]); + +assign csr_mtsel = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mtdata1 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]); + +assign csr_mtdata2 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[1]); + +assign csr_mhpmc3 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc4 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc5 = (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc6 = (!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc3h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc4h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpmc5h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpmc6h = (dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mhpme3 = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpme4 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_mhpme5 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &dec_csr_rdaddr_d[0]); + +assign csr_mhpme6 = (dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_mcountinhibit = (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]); + +assign csr_mitctl0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mitctl1 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mitb0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[0]); + +assign csr_mitb1 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mitcnt0 = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]); + +assign csr_mitcnt1 = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_mpmc = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign csr_meicpct = (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_micect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_miccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]); + +assign csr_mdccmect = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mfdht = (dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_mfdhs = (dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]); + +assign csr_dicawics = (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]); + +assign csr_dicad0h = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]); + +assign csr_dicad0 = (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign csr_dicad1 = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]); + +assign csr_dicago = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]); + +assign presync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | ( + dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign postsync = (dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[10] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[1]) | (dec_csr_rdaddr_d[10]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]); + +assign legal = (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | ( + dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2] + &dec_csr_rdaddr_d[0]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[2]) | (dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&dec_csr_rdaddr_d[1]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[1]&dec_csr_rdaddr_d[0]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5] + &!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1] + &!dec_csr_rdaddr_d[0]) | (dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[3]&dec_csr_rdaddr_d[1]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7]&dec_csr_rdaddr_d[6] + &!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4]&dec_csr_rdaddr_d[3] + &!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11]&dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&dec_csr_rdaddr_d[7] + &!dec_csr_rdaddr_d[6]&dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]&!dec_csr_rdaddr_d[0]) | ( + dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5] + &dec_csr_rdaddr_d[1]) | (!dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10] + &dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7] + &dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[2]) | (!dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[5]&!dec_csr_rdaddr_d[4] + &!dec_csr_rdaddr_d[3]&!dec_csr_rdaddr_d[1]&!dec_csr_rdaddr_d[0]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[3]) | ( + !dec_csr_rdaddr_d[11]&!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9] + &dec_csr_rdaddr_d[8]&!dec_csr_rdaddr_d[7]&!dec_csr_rdaddr_d[6] + &dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]) | (dec_csr_rdaddr_d[11] + &!dec_csr_rdaddr_d[10]&dec_csr_rdaddr_d[9]&dec_csr_rdaddr_d[8] + &!dec_csr_rdaddr_d[6]&!dec_csr_rdaddr_d[5]&dec_csr_rdaddr_d[4]); + + + +assign dec_tlu_presync_d = presync & dec_csr_any_unq_d & ~dec_csr_wen_unq_d; +assign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d; + + // allow individual configuration of these features +assign conditionally_illegal = ((csr_mitcnt0 | csr_mitcnt1 | csr_mitb0 | csr_mitb1 | csr_mitctl0 | csr_mitctl1) & !pt.TIMER_LEGAL_EN); + +assign valid_csr = ( legal & (~(csr_dcsr | csr_dpc | csr_dmst | csr_dicawics | csr_dicad0 | csr_dicad0h | csr_dicad1 | csr_dicago) | dbg_tlu_halted_f) + & ~fast_int_meicpct & ~conditionally_illegal); + +assign dec_csr_legal_d = ( dec_csr_any_unq_d & + valid_csr & // of a valid CSR + ~(dec_csr_wen_unq_d & (csr_mvendorid | csr_marchid | csr_mimpid | csr_mhartid | csr_mdseac | csr_meihap)) // that's not a write to a RO CSR + ); + // CSR read mux +assign dec_csr_rddata_d[31:0] = ( ({32{csr_misa}} & 32'h40001104) | + ({32{csr_mvendorid}} & 32'h00000045) | + ({32{csr_marchid}} & 32'h00000010) | + ({32{csr_mimpid}} & 32'h4) | + ({32{csr_mhartid}} & {core_id[31:4], 4'b0}) | + ({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[1], 3'b0, mstatus[0], 3'b0}) | + ({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) | + ({32{csr_mip}} & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) | + ({32{csr_mie}} & {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0}) | + ({32{csr_mcyclel}} & mcyclel[31:0]) | + ({32{csr_mcycleh}} & mcycleh_inc[31:0]) | + ({32{csr_minstretl}} & minstretl_read[31:0]) | + ({32{csr_minstreth}} & minstreth_read[31:0]) | + ({32{csr_mscratch}} & mscratch[31:0]) | + ({32{csr_mepc}} & {mepc[31:1], 1'b0}) | + ({32{csr_mcause}} & mcause[31:0]) | + ({32{csr_mscause}} & {28'b0, mscause[3:0]}) | + ({32{csr_mtval}} & mtval[31:0]) | + ({32{csr_mrac}} & mrac[31:0]) | + ({32{csr_mdseac}} & mdseac[31:0]) | + ({32{csr_meivt}} & {meivt[31:10], 10'b0}) | + ({32{csr_meihap}} & {meivt[31:10], meihap[9:2], 2'b0}) | + ({32{csr_meicurpl}} & {28'b0, meicurpl[3:0]}) | + ({32{csr_meicidpl}} & {28'b0, meicidpl[3:0]}) | + ({32{csr_meipt}} & {28'b0, meipt[3:0]}) | + ({32{csr_mcgc}} & {22'b0, mcgc[9:0]}) | + ({32{csr_mfdc}} & {13'b0, mfdc[18:0]}) | + ({32{csr_dcsr}} & {16'h4000, dcsr[15:2], 2'b11}) | + ({32{csr_dpc}} & {dpc[31:1], 1'b0}) | + ({32{csr_dicad0}} & dicad0[31:0]) | + ({32{csr_dicad0h}} & dicad0h[31:0]) | + ({32{csr_dicad1}} & dicad1[31:0]) | + ({32{csr_dicawics}} & {7'b0, dicawics[16], 2'b0, dicawics[15:14], 3'b0, dicawics[13:0], 3'b0}) | + ({32{csr_mtsel}} & {30'b0, mtsel[1:0]}) | + ({32{csr_mtdata1}} & {mtdata1_tsel_out[31:0]}) | + ({32{csr_mtdata2}} & {mtdata2_tsel_out[31:0]}) | + ({32{csr_micect}} & {micect[31:0]}) | + ({32{csr_miccmect}} & {miccmect[31:0]}) | + ({32{csr_mdccmect}} & {mdccmect[31:0]}) | + ({32{csr_mhpmc3}} & mhpmc3[31:0]) | + ({32{csr_mhpmc4}} & mhpmc4[31:0]) | + ({32{csr_mhpmc5}} & mhpmc5[31:0]) | + ({32{csr_mhpmc6}} & mhpmc6[31:0]) | + ({32{csr_mhpmc3h}} & mhpmc3h[31:0]) | + ({32{csr_mhpmc4h}} & mhpmc4h[31:0]) | + ({32{csr_mhpmc5h}} & mhpmc5h[31:0]) | + ({32{csr_mhpmc6h}} & mhpmc6h[31:0]) | + ({32{csr_mfdht}} & {26'b0, mfdht[5:0]}) | + ({32{csr_mfdhs}} & {30'b0, mfdhs[1:0]}) | + ({32{csr_mhpme3}} & {22'b0,mhpme3[9:0]}) | + ({32{csr_mhpme4}} & {22'b0,mhpme4[9:0]}) | + ({32{csr_mhpme5}} & {22'b0,mhpme5[9:0]}) | + ({32{csr_mhpme6}} & {22'b0,mhpme6[9:0]}) | + ({32{csr_mcountinhibit}} & {25'b0, mcountinhibit[6:0]}) | + ({32{csr_mpmc}} & {30'b0, mpmc[1], 1'b0}) | + ({32{dec_timer_read_d}} & dec_timer_rddata_d[31:0]) + ); + + + +endmodule // el2_dec_tlu_ctl + +module el2_dec_timer_ctl #( +`include "el2_param.vh" + ) + ( + input logic clk, + input logic free_l2clk, + input logic csr_wr_clk, + input logic rst_l, + input logic dec_csr_wen_r_mod, // csr write enable at wb + input logic [11:0] dec_csr_wraddr_r, // write address for csr + input logic [31:0] dec_csr_wrdata_r, // csr write data at wb + + input logic csr_mitctl0, + input logic csr_mitctl1, + input logic csr_mitb0, + input logic csr_mitb1, + input logic csr_mitcnt0, + input logic csr_mitcnt1, + + + input logic dec_pause_state, // Paused + input logic dec_tlu_pmu_fw_halted, // pmu/fw halted + input logic internal_dbg_halt_timers, // debug halted + + output logic [31:0] dec_timer_rddata_d, // timer CSR read data + output logic dec_timer_read_d, // timer CSR address match + output logic dec_timer_t0_pulse, // timer0 int + output logic dec_timer_t1_pulse, // timer1 int + + input logic scan_mode + ); + localparam MITCTL_ENABLE = 0; + localparam MITCTL_ENABLE_HALTED = 1; + localparam MITCTL_ENABLE_PAUSED = 2; + + logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc; + logic [2:0] mitctl0_ns, mitctl0; + logic [3:0] mitctl1_ns, mitctl1; + logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r; + logic mitcnt0_inc_ok, mitcnt1_inc_ok; + logic mitcnt0_inc_cout, mitcnt1_inc_cout; + logic mit0_match_ns; + logic mit1_match_ns; + logic mitctl0_0_b_ns; + logic mitctl0_0_b; + logic mitctl1_0_b_ns; + logic mitctl1_0_b; + + assign mit0_match_ns = (mitcnt0[31:0] >= mitb0[31:0]); + assign mit1_match_ns = (mitcnt1[31:0] >= mitb1[31:0]); + + assign dec_timer_t0_pulse = mit0_match_ns; + assign dec_timer_t1_pulse = mit1_match_ns; + // ---------------------------------------------------------------------- + // MITCNT0 (RW) + // [31:0] : Internal Timer Counter 0 + + localparam MITCNT0 = 12'h7d2; + + assign wr_mitcnt0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT0); + + assign mitcnt0_inc_ok = mitctl0[MITCTL_ENABLE] & (~dec_pause_state | mitctl0[MITCTL_ENABLE_PAUSED]) & (~dec_tlu_pmu_fw_halted | mitctl0[MITCTL_ENABLE_HALTED]) & ~internal_dbg_halt_timers; + + assign {mitcnt0_inc_cout, mitcnt0_inc[7:0]} = mitcnt0[7:0] + {7'b0, 1'b1}; + assign mitcnt0_inc[31:8] = mitcnt0[31:8] + {23'b0, mitcnt0_inc_cout}; + + assign mitcnt0_ns[31:0] = wr_mitcnt0_r ? dec_csr_wrdata_r[31:0] : mit0_match_ns ? 'b0 : mitcnt0_inc[31:0]; + + rvdffe #(24) mitcnt0_ffb (.*, .clk(free_l2clk), .en(wr_mitcnt0_r | (mitcnt0_inc_ok & mitcnt0_inc_cout) | mit0_match_ns), .din(mitcnt0_ns[31:8]), .dout(mitcnt0[31:8])); + rvdffe #(8) mitcnt0_ffa (.*, .clk(free_l2clk), .en(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns), .din(mitcnt0_ns[7:0]), .dout(mitcnt0[7:0])); + + // ---------------------------------------------------------------------- + // MITCNT1 (RW) + // [31:0] : Internal Timer Counter 0 + + localparam MITCNT1 = 12'h7d5; + + assign wr_mitcnt1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT1); + + assign mitcnt1_inc_ok = mitctl1[MITCTL_ENABLE] & + (~dec_pause_state | mitctl1[MITCTL_ENABLE_PAUSED]) & + (~dec_tlu_pmu_fw_halted | mitctl1[MITCTL_ENABLE_HALTED]) & + ~internal_dbg_halt_timers & + (~mitctl1[3] | mit0_match_ns); + + // only inc MITCNT1 if not cascaded with 0, or if 0 overflows + assign {mitcnt1_inc_cout, mitcnt1_inc[7:0]} = mitcnt1[7:0] + {7'b0, 1'b1}; + assign mitcnt1_inc[31:8] = mitcnt1[31:8] + {23'b0, mitcnt1_inc_cout}; + + assign mitcnt1_ns[31:0] = wr_mitcnt1_r ? dec_csr_wrdata_r[31:0] : mit1_match_ns ? 'b0 : mitcnt1_inc[31:0]; + + rvdffe #(24) mitcnt1_ffb (.*, .clk(free_l2clk), .en(wr_mitcnt1_r | (mitcnt1_inc_ok & mitcnt1_inc_cout) | mit1_match_ns), .din(mitcnt1_ns[31:8]), .dout(mitcnt1[31:8])); + rvdffe #(8) mitcnt1_ffa (.*, .clk(free_l2clk), .en(wr_mitcnt1_r | mitcnt1_inc_ok | mit1_match_ns), .din(mitcnt1_ns[7:0]), .dout(mitcnt1[7:0])); + + + // ---------------------------------------------------------------------- + // MITB0 (RW) + // [31:0] : Internal Timer Bound 0 + + localparam MITB0 = 12'h7d3; + + assign wr_mitb0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB0); + + rvdffe #(32) mitb0_ff (.*, .en(wr_mitb0_r), .din(~dec_csr_wrdata_r[31:0]), .dout(mitb0_b[31:0])); + assign mitb0[31:0] = ~mitb0_b[31:0]; + + // ---------------------------------------------------------------------- + // MITB1 (RW) + // [31:0] : Internal Timer Bound 1 + + localparam MITB1 = 12'h7d6; + + assign wr_mitb1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB1); + + rvdffe #(32) mitb1_ff (.*, .en(wr_mitb1_r), .din(~dec_csr_wrdata_r[31:0]), .dout(mitb1_b[31:0])); + assign mitb1[31:0] = ~mitb1_b[31:0]; + + // ---------------------------------------------------------------------- + // MITCTL0 (RW) Internal Timer Ctl 0 + // [31:3] : Reserved, reads 0x0 + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) + + localparam MITCTL0 = 12'h7d4; + + assign wr_mitctl0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL0); + assign mitctl0_ns[2:0] = wr_mitctl0_r ? {dec_csr_wrdata_r[2:0]} : {mitctl0[2:0]}; + + assign mitctl0_0_b_ns = ~mitctl0_ns[0]; + rvdffs #(3) mitctl0_ff (.*, .clk(csr_wr_clk), .en(wr_mitctl0_r), .din({mitctl0_ns[2:1], mitctl0_0_b_ns}), .dout({mitctl0[2:1], mitctl0_0_b})); + assign mitctl0[0] = ~mitctl0_0_b; + + // ---------------------------------------------------------------------- + // MITCTL1 (RW) Internal Timer Ctl 1 + // [31:4] : Reserved, reads 0x0 + // [3] : Cascade + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) + + localparam MITCTL1 = 12'h7d7; + + assign wr_mitctl1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL1); + assign mitctl1_ns[3:0] = wr_mitctl1_r ? {dec_csr_wrdata_r[3:0]} : {mitctl1[3:0]}; + + assign mitctl1_0_b_ns = ~mitctl1_ns[0]; + rvdffs #(4) mitctl1_ff (.*, .clk(csr_wr_clk), .en(wr_mitctl1_r), .din({mitctl1_ns[3:1], mitctl1_0_b_ns}), .dout({mitctl1[3:1], mitctl1_0_b})); + assign mitctl1[0] = ~mitctl1_0_b; + assign dec_timer_read_d = csr_mitcnt1 | csr_mitcnt0 | csr_mitb1 | csr_mitb0 | csr_mitctl0 | csr_mitctl1; + assign dec_timer_rddata_d[31:0] = ( ({32{csr_mitcnt0}} & mitcnt0[31:0]) | + ({32{csr_mitcnt1}} & mitcnt1[31:0]) | + ({32{csr_mitb0}} & mitb0[31:0]) | + ({32{csr_mitb1}} & mitb1[31:0]) | + ({32{csr_mitctl0}} & {29'b0, mitctl0[2:0]}) | + ({32{csr_mitctl1}} & {28'b0, mitctl1[3:0]}) + ); + + +endmodule // dec_timer_ctl diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv new file mode 100644 index 0000000000000000000000000000000000000000..fce7298c186c4240fe12ebcf0f7f5fd16c082ab1 --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dec/el2_dec_trigger.sv @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//******************************************************************************** +// $Id$ +// +// +// Owner: +// Function: DEC Trigger Logic +// Comments: +// +//******************************************************************************** +module el2_dec_trigger +import el2_pkg::*; +#( +`include "el2_param.vh" + )( + + input el2_trigger_pkt_t [3:0] trigger_pkt_any, // Packet from tlu. 'select':0-pc,1-Opcode 'Execute' needs to be set for dec triggers to fire. 'match'-1 do mask, 0: full match + input logic [31:1] dec_i0_pc_d, // i0 pc + + output logic [3:0] dec_i0_trigger_match_d // Trigger match +); + + logic [3:0][31:0] dec_i0_match_data; + logic [3:0] dec_i0_trigger_data_match; + + for (genvar i=0; i<4; i++) begin + assign dec_i0_match_data[i][31:0] = ({32{~trigger_pkt_any[i].select & trigger_pkt_any[i].execute}} & {dec_i0_pc_d[31:1], trigger_pkt_any[i].tdata2[0]}); // select=0; do a PC match + + rvmaskandmatch trigger_i0_match (.mask(trigger_pkt_any[i].tdata2[31:0]), .data(dec_i0_match_data[i][31:0]), .masken(trigger_pkt_any[i].match), .match(dec_i0_trigger_data_match[i])); + + assign dec_i0_trigger_match_d[i] = trigger_pkt_any[i].execute & trigger_pkt_any[i].m & dec_i0_trigger_data_match[i]; + end + +endmodule // el2_dec_trigger + diff --git a/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dmi/dmi_jtag_to_core_sync.v b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dmi/dmi_jtag_to_core_sync.v new file mode 100644 index 0000000000000000000000000000000000000000..562f815e4487b7548b7d41f4f6579704c85ddd4e --- /dev/null +++ b/chili-chips-ba_openCologne/8.StressTest/4.veerwolves/build/veerwolf_0.7.5/gatemate_pack-gatemate/src/chipsalliance.org_cores_VeeR_EL2_1.4/chipsalliance.org_cores_VeeR_EL2_1.4/design/dmi/dmi_jtag_to_core_sync.v @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2019 +// Owner : Alex Grobman +// Description: +// This module Synchronizes the signals between JTAG (TCK) and +// processor (Core_clk) +// +//------------------------------------------------------------------------------------- + +module dmi_jtag_to_core_sync ( +// JTAG signals +input rd_en, // 1 bit Read Enable from JTAG +input wr_en, // 1 bit Write enable from JTAG + +// Processor Signals +input rst_n, // Core reset +input clk, // Core clock + +output reg_en, // 1 bit Write interface bit to Processor +output reg_wr_en // 1 bit Write enable to Processor +); + +wire c_rd_en; +wire c_wr_en; +reg [2:0] rden, wren; + + +// Outputs +assign reg_en = c_wr_en | c_rd_en; +assign reg_wr_en = c_wr_en; + + +// synchronizers +always @ ( posedge clk or negedge rst_n) begin + if(!rst_n) begin + rden <= '0; + wren <= '0; + end + else begin + rden <= {rden[1:0], rd_en}; + wren <= {wren[1:0], wr_en}; + end +end + +assign c_rd_en = rden[1] & ~rden[2]; +assign c_wr_en = wren[1] & ~wren[2]; + + +endmodule